Pull KVM fixes from Paolo Bonzini: "Bug fixes (ARM, s390, x86)" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: async_pf: avoid async pf injection when in guest mode KVM: cpuid: Fix read/write out-of-bounds vulnerability in cpuid emulation arm: KVM: Allow unaligned accesses at HYP arm64: KVM: Allow unaligned accesses at EL2 arm64: KVM: Preserve RES1 bits in SCTLR_EL2 KVM: arm/arm64: Handle possible NULL stage2 pud when ageing pages KVM: nVMX: Fix exception injection kvm: async_pf: fix rcu_irq_enter() with irqs enabled KVM: arm/arm64: vgic-v3: Fix nr_pre_bits bitfield extraction KVM: s390: fix ais handling vs cpu model KVM: arm/arm64: Fix isues with GICv2 on GICv3 migration
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| @@ -417,6 +417,10 @@ · 416 unmodified lines | |||
| 417 | #define ICH_HCR_EN (1 << 0) | 417 | #define ICH_HCR_EN (1 << 0) |
| 418 | #define ICH_HCR_UIE (1 << 1) | 418 | #define ICH_HCR_UIE (1 << 1) |
| 419 | 419 | ||
| 420 | #define ICH_VMCR_ACK_CTL_SHIFT 2 | ||
| 421 | #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) | ||
| 422 | #define ICH_VMCR_FIQ_EN_SHIFT 3 | ||
| 423 | #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) | ||
| 420 | #define ICH_VMCR_CBPR_SHIFT 4 | 424 | #define ICH_VMCR_CBPR_SHIFT 4 |
| 421 | #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) | 425 | #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) |
| 422 | #define ICH_VMCR_EOIM_SHIFT 9 | 426 | #define ICH_VMCR_EOIM_SHIFT 9 |
| @@ -25,7 +25,18 @@ · 24 unmodified lines | |||
| 25 | #define GICC_ENABLE 0x1 | 25 | #define GICC_ENABLE 0x1 |
| 26 | #define GICC_INT_PRI_THRESHOLD 0xf0 | 26 | #define GICC_INT_PRI_THRESHOLD 0xf0 |
| 27 | 27 | ||
| 28 | #define GIC_CPU_CTRL_EOImodeNS (1 << 9) | 28 | #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 |
| 29 | #define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) | ||
| 30 | #define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 | ||
| 31 | #define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) | ||
| 32 | #define GIC_CPU_CTRL_AckCtl_SHIFT 2 | ||
| 33 | #define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) | ||
| 34 | #define GIC_CPU_CTRL_FIQEn_SHIFT 3 | ||
| 35 | #define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) | ||
| 36 | #define GIC_CPU_CTRL_CBPR_SHIFT 4 | ||
| 37 | #define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) | ||
| 38 | #define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 | ||
| 39 | #define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) | ||
| 29 | 40 | ||
| 30 | #define GICC_IAR_INT_ID_MASK 0x3ff | 41 | #define GICC_IAR_INT_ID_MASK 0x3ff |
| 31 | #define GICC_INT_SPURIOUS 1023 | 42 | #define GICC_INT_SPURIOUS 1023 |
| @@ -84,8 +95,19 @@ · 52 unmodified lines | |||
| 84 | #define GICH_LR_EOI (1 << 19) | 95 | #define GICH_LR_EOI (1 << 19) |
| 85 | #define GICH_LR_HW (1 << 31) | 96 | #define GICH_LR_HW (1 << 31) |
| 86 | 97 | ||
| 87 | #define GICH_VMCR_CTRL_SHIFT 0 | 98 | #define GICH_VMCR_ENABLE_GRP0_SHIFT 0 |
| 88 | #define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) | 99 | #define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) |
| 100 | #define GICH_VMCR_ENABLE_GRP1_SHIFT 1 | ||
| 101 | #define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) | ||
| 102 | #define GICH_VMCR_ACK_CTL_SHIFT 2 | ||
| 103 | #define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) | ||
| 104 | #define GICH_VMCR_FIQ_EN_SHIFT 3 | ||
| 105 | #define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) | ||
| 106 | #define GICH_VMCR_CBPR_SHIFT 4 | ||
| 107 | #define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) | ||
| 108 | #define GICH_VMCR_EOI_MODE_SHIFT 9 | ||
| 109 | #define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) | ||
| 110 | |||
| 89 | #define GICH_VMCR_PRIMASK_SHIFT 27 | 111 | #define GICH_VMCR_PRIMASK_SHIFT 27 |
| 90 | #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) | 112 | #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) |
| 91 | #define GICH_VMCR_BINPOINT_SHIFT 21 | 113 | #define GICH_VMCR_BINPOINT_SHIFT 21 |