- Initialize leds class earlier (with an unfortunate Makefile ordering change) so the PCI NPEM driver can use it (Mariusz Tkaczyk) - Add Native PCIe Enclosure Management (NPEM) support for sysfs control of NVMe RAID storage indicators (ok/fail/locate/rebuild/etc) (Mariusz Tkaczyk) - Add support for the ACPI _DSM PCIe SSD status LED management, which is functionally similar to NPEM but mediated by platform firmware (Mariusz Tkaczyk) * pci/npem: PCI/NPEM: Add _DSM PCIe SSD status LED management PCI/NPEM: Add Native PCIe Enclosure Management support leds: Init leds class earlier
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| @@ -742,6 +742,7 @@ · 741 unmodified lines | ||
| 742 | 742 | #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ |
| 743 | 743 | #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ |
| 744 | 744 | #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ |
| 745 | +#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ | |
| 745 | 746 | #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ |
| 746 | 747 | #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ |
| 747 | 748 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE |
| @@ -1123,6 +1124,40 @@ · 375 unmodified lines | ||
| 1123 | 1124 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 |
| 1124 | 1125 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 |
| 1125 | 1126 | |
| 1127 | +/* Native PCIe Enclosure Management */ | |
| 1128 | +#define PCI_NPEM_CAP 0x04 /* NPEM capability register */ | |
| 1129 | +#define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ | |
| 1130 | + | |
| 1131 | +#define PCI_NPEM_CTRL 0x08 /* NPEM control register */ | |
| 1132 | +#define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */ | |
| 1133 | + | |
| 1134 | +/* | |
| 1135 | + * Native PCIe Enclosure Management indication bits and Reset command bit | |
| 1136 | + * are corresponding for capability and control registers. | |
| 1137 | + */ | |
| 1138 | +#define PCI_NPEM_CMD_RESET 0x00000002 /* Reset Command */ | |
| 1139 | +#define PCI_NPEM_IND_OK 0x00000004 /* OK */ | |
| 1140 | +#define PCI_NPEM_IND_LOCATE 0x00000008 /* Locate */ | |
| 1141 | +#define PCI_NPEM_IND_FAIL 0x00000010 /* Fail */ | |
| 1142 | +#define PCI_NPEM_IND_REBUILD 0x00000020 /* Rebuild */ | |
| 1143 | +#define PCI_NPEM_IND_PFA 0x00000040 /* Predicted Failure Analysis */ | |
| 1144 | +#define PCI_NPEM_IND_HOTSPARE 0x00000080 /* Hot Spare */ | |
| 1145 | +#define PCI_NPEM_IND_ICA 0x00000100 /* In Critical Array */ | |
| 1146 | +#define PCI_NPEM_IND_IFA 0x00000200 /* In Failed Array */ | |
| 1147 | +#define PCI_NPEM_IND_IDT 0x00000400 /* Device Type */ | |
| 1148 | +#define PCI_NPEM_IND_DISABLED 0x00000800 /* Disabled */ | |
| 1149 | +#define PCI_NPEM_IND_SPEC_0 0x01000000 | |
| 1150 | +#define PCI_NPEM_IND_SPEC_1 0x02000000 | |
| 1151 | +#define PCI_NPEM_IND_SPEC_2 0x04000000 | |
| 1152 | +#define PCI_NPEM_IND_SPEC_3 0x08000000 | |
| 1153 | +#define PCI_NPEM_IND_SPEC_4 0x10000000 | |
| 1154 | +#define PCI_NPEM_IND_SPEC_5 0x20000000 | |
| 1155 | +#define PCI_NPEM_IND_SPEC_6 0x40000000 | |
| 1156 | +#define PCI_NPEM_IND_SPEC_7 0x80000000 | |
| 1157 | + | |
| 1158 | +#define PCI_NPEM_STATUS 0x0c /* NPEM status register */ | |
| 1159 | +#define PCI_NPEM_STATUS_CC 0x00000001 /* Command Completed */ | |
| 1160 | + | |
| 1126 | 1161 | /* Data Object Exchange */ |
| 1127 | 1162 | #define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */ |
| 1128 | 1163 | #define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */ |