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Merge tag 'char-misc-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver patches from Greg KH: "Here's the big char/misc driver patches for 3.14-rc1. Lots of little things, and a new "big" driver, genwqe. Full details are in the shortlog" * tag 'char-misc-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (90 commits) mei: limit the number of consecutive resets mei: revamp mei reset state machine drivers/char: don't use module_init in non-modular ttyprintk.c VMCI: fix error handling path when registering guest driver extcon: gpio: Add power resume support Documentation: HOWTO: Updates on subsystem trees, patchwork, -next (vs. -mm) in ko_KR Documentation: HOWTO: update for 2.6.x -> 3.x versioning in ko_KR Documentation: HOWTO: update stable address in ko_KR Documentation: HOWTO: update LXR web link in ko_KR char: nwbutton: open-code interruptible_sleep_on mei: fix syntax in comments and debug output mei: nfc: mei_nfc_free has to be called under lock mei: use hbm idle state to prevent spurious resets mei: do not run reset flow from the interrupt thread misc: genwqe: fix return value check in genwqe_device_create() GenWQE: Fix warnings for sparc GenWQE: Fix compile problems for Alpha Documentation/misc-devices/mei/mei-amt-version.c: remove unneeded call of mei_deinit() GenWQE: Rework return code for flash-update ioctl sgi-xp: open-code interruptible_sleep_on_timeout ...

Linus Torvalds committed 12 years ago

Commit 9f676272 parents 82b5173 6adb8ef82 files · +9170 −675Browse files

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include/uapi/linux/genwqe/genwqe_card.h+500−0
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1+#ifndef __GENWQE_CARD_H__
2+#define __GENWQE_CARD_H__
3+
4+/**
5+ * IBM Accelerator Family 'GenWQE'
6+ *
7+ * (C) Copyright IBM Corp. 2013
8+ *
9+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
10+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
11+ * Author: Michael Jung <mijung@de.ibm.com>
12+ * Author: Michael Ruettger <michael@ibmra.de>
13+ *
14+ * This program is free software; you can redistribute it and/or modify
15+ * it under the terms of the GNU General Public License (version 2 only)
16+ * as published by the Free Software Foundation.
17+ *
18+ * This program is distributed in the hope that it will be useful,
19+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21+ * GNU General Public License for more details.
22+ */
23+
24+/*
25+ * User-space API for the GenWQE card. For debugging and test purposes
26+ * the register addresses are included here too.
27+ */
28+
29+#include <linux/types.h>
30+#include <linux/ioctl.h>
31+
32+/* Basename of sysfs, debugfs and /dev interfaces */
33+#define GENWQE_DEVNAME "genwqe"
34+
35+#define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
36+#define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
37+#define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
38+#define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
39+
40+/* MMIO Unit offsets: Each UnitID occupies a defined address range */
41+#define GENWQE_UID_OFFS(uid) ((uid) << 24)
42+#define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
43+#define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1)
44+#define GENWQE_APP_OFFS GENWQE_UID_OFFS(2)
45+#define GENWQE_MAX_UNITS 3
46+
47+/* Common offsets per UnitID */
48+#define IO_EXTENDED_ERROR_POINTER 0x00000048
49+#define IO_ERROR_INJECT_SELECTOR 0x00000060
50+#define IO_EXTENDED_DIAG_SELECTOR 0x00000070
51+#define IO_EXTENDED_DIAG_READ_MBX 0x00000078
52+#define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
53+
54+#define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) (((ring) << 8) | (trace))
55+
56+/* UnitID 0: Service Layer Unit (SLU) */
57+
58+/* SLU: Unit Configuration Register */
59+#define IO_SLU_UNITCFG 0x00000000
60+#define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 /* 27:20 */
61+
62+/* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */
63+#define IO_SLU_FIR 0x00000008 /* read only, wr direct */
64+#define IO_SLU_FIR_CLR 0x00000010 /* read and clear */
65+
66+/* SLU: First Error Capture Register (FEC/WOF) */
67+#define IO_SLU_FEC 0x00000018
68+
69+#define IO_SLU_ERR_ACT_MASK 0x00000020
70+#define IO_SLU_ERR_ATTN_MASK 0x00000028
71+#define IO_SLU_FIRX1_ACT_MASK 0x00000030
72+#define IO_SLU_FIRX0_ACT_MASK 0x00000038
73+#define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040
74+#define IO_SLU_EXTENDED_ERR_PTR 0x00000048
75+#define IO_SLU_COMMON_CONFIG 0x00000060
76+
77+#define IO_SLU_FLASH_FIR 0x00000108
78+#define IO_SLU_SLC_FIR 0x00000110
79+#define IO_SLU_RIU_TRAP 0x00000280
80+#define IO_SLU_FLASH_FEC 0x00000308
81+#define IO_SLU_SLC_FEC 0x00000310
82+
83+/*
84+ * The Virtual Function's Access is from offset 0x00010000
85+ * The Physical Function's Access is from offset 0x00050000
86+ * Single Shared Registers exists only at offset 0x00060000
87+ *
88+ * SLC: Queue Virtual Window Window for accessing into a specific VF
89+ * queue. When accessing the 0x10000 space using the 0x50000 address
90+ * segment, the value indicated here is used to specify which VF
91+ * register is decoded. This register, and the 0x50000 register space
92+ * can only be accessed by the PF. Example, if this register is set to
93+ * 0x2, then a read from 0x50000 is the same as a read from 0x10000
94+ * from VF=2.
95+ */
96+
97+/* SLC: Queue Segment */
98+#define IO_SLC_QUEUE_SEGMENT 0x00010000
99+#define IO_SLC_VF_QUEUE_SEGMENT 0x00050000
100+
101+/* SLC: Queue Offset */
102+#define IO_SLC_QUEUE_OFFSET 0x00010008
103+#define IO_SLC_VF_QUEUE_OFFSET 0x00050008
104+
105+/* SLC: Queue Configuration */
106+#define IO_SLC_QUEUE_CONFIG 0x00010010
107+#define IO_SLC_VF_QUEUE_CONFIG 0x00050010
108+
109+/* SLC: Job Timout/Only accessible for the PF */
110+#define IO_SLC_APPJOB_TIMEOUT 0x00010018
111+#define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018
112+#define TIMEOUT_250MS 0x0000000f
113+#define HEARTBEAT_DISABLE 0x0000ff00
114+
115+/* SLC: Queue InitSequence Register */
116+#define IO_SLC_QUEUE_INITSQN 0x00010020
117+#define IO_SLC_VF_QUEUE_INITSQN 0x00050020
118+
119+/* SLC: Queue Wrap */
120+#define IO_SLC_QUEUE_WRAP 0x00010028
121+#define IO_SLC_VF_QUEUE_WRAP 0x00050028
122+
123+/* SLC: Queue Status */
124+#define IO_SLC_QUEUE_STATUS 0x00010100
125+#define IO_SLC_VF_QUEUE_STATUS 0x00050100
126+
127+/* SLC: Queue Working Time */
128+#define IO_SLC_QUEUE_WTIME 0x00010030
129+#define IO_SLC_VF_QUEUE_WTIME 0x00050030
130+
131+/* SLC: Queue Error Counts */
132+#define IO_SLC_QUEUE_ERRCNTS 0x00010038
133+#define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038
134+
135+/* SLC: Queue Loast Response Word */
136+#define IO_SLC_QUEUE_LRW 0x00010040
137+#define IO_SLC_VF_QUEUE_LRW 0x00050040
138+
139+/* SLC: Freerunning Timer */
140+#define IO_SLC_FREE_RUNNING_TIMER 0x00010108
141+#define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108
142+
143+/* SLC: Queue Virtual Access Region */
144+#define IO_PF_SLC_VIRTUAL_REGION 0x00050000
145+
146+/* SLC: Queue Virtual Window */
147+#define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000
148+
149+/* SLC: DDCB Application Job Pending [n] (n=0:63) */
150+#define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8*(n))
151+#define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n)
152+
153+/* SLC: Parser Trap RAM [n] (n=0:31) */
154+#define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8*(n))
155+
156+/* SLC: Dispatcher Trap RAM [n] (n=0:31) */
157+#define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n))
158+
159+/* Global Fault Isolation Register (GFIR) */
160+#define IO_SLC_CFGREG_GFIR 0x00020000
161+#define GFIR_ERR_TRIGGER 0x0000ffff
162+
163+/* SLU: Soft Reset Register */
164+#define IO_SLC_CFGREG_SOFTRESET 0x00020018
165+
166+/* SLU: Misc Debug Register */
167+#define IO_SLC_MISC_DEBUG 0x00020060
168+#define IO_SLC_MISC_DEBUG_CLR 0x00020068
169+#define IO_SLC_MISC_DEBUG_SET 0x00020070
170+
171+/* Temperature Sensor Reading */
172+#define IO_SLU_TEMPERATURE_SENSOR 0x00030000
173+#define IO_SLU_TEMPERATURE_CONFIG 0x00030008
174+
175+/* Voltage Margining Control */
176+#define IO_SLU_VOLTAGE_CONTROL 0x00030080
177+#define IO_SLU_VOLTAGE_NOMINAL 0x00000000
178+#define IO_SLU_VOLTAGE_DOWN5 0x00000006
179+#define IO_SLU_VOLTAGE_UP5 0x00000007
180+
181+/* Direct LED Control Register */
182+#define IO_SLU_LEDCONTROL 0x00030100
183+
184+/* SLU: Flashbus Direct Access -A5 */
185+#define IO_SLU_FLASH_DIRECTACCESS 0x00040010
186+
187+/* SLU: Flashbus Direct Access2 -A5 */
188+#define IO_SLU_FLASH_DIRECTACCESS2 0x00040020
189+
190+/* SLU: Flashbus Command Interface -A5 */
191+#define IO_SLU_FLASH_CMDINTF 0x00040030
192+
193+/* SLU: BitStream Loaded */
194+#define IO_SLU_BITSTREAM 0x00040040
195+
196+/* This Register has a switch which will change the CAs to UR */
197+#define IO_HSU_ERR_BEHAVIOR 0x01001010
198+
199+#define IO_SLC2_SQB_TRAP 0x00062000
200+#define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008
201+#define IO_SLC2_FLS_MASTER_TRAP 0x00062010
202+
203+/* UnitID 1: HSU Registers */
204+#define IO_HSU_UNITCFG 0x01000000
205+#define IO_HSU_FIR 0x01000008
206+#define IO_HSU_FIR_CLR 0x01000010
207+#define IO_HSU_FEC 0x01000018
208+#define IO_HSU_ERR_ACT_MASK 0x01000020
209+#define IO_HSU_ERR_ATTN_MASK 0x01000028
210+#define IO_HSU_FIRX1_ACT_MASK 0x01000030
211+#define IO_HSU_FIRX0_ACT_MASK 0x01000038
212+#define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040
213+#define IO_HSU_EXTENDED_ERR_PTR 0x01000048
214+#define IO_HSU_COMMON_CONFIG 0x01000060
215+
216+/* UnitID 2: Application Unit (APP) */
217+#define IO_APP_UNITCFG 0x02000000
218+#define IO_APP_FIR 0x02000008
219+#define IO_APP_FIR_CLR 0x02000010
220+#define IO_APP_FEC 0x02000018
221+#define IO_APP_ERR_ACT_MASK 0x02000020
222+#define IO_APP_ERR_ATTN_MASK 0x02000028
223+#define IO_APP_FIRX1_ACT_MASK 0x02000030
224+#define IO_APP_FIRX0_ACT_MASK 0x02000038
225+#define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040
226+#define IO_APP_EXTENDED_ERR_PTR 0x02000048
227+#define IO_APP_COMMON_CONFIG 0x02000060
228+
229+#define IO_APP_DEBUG_REG_01 0x02010000
230+#define IO_APP_DEBUG_REG_02 0x02010008
231+#define IO_APP_DEBUG_REG_03 0x02010010
232+#define IO_APP_DEBUG_REG_04 0x02010018
233+#define IO_APP_DEBUG_REG_05 0x02010020
234+#define IO_APP_DEBUG_REG_06 0x02010028
235+#define IO_APP_DEBUG_REG_07 0x02010030
236+#define IO_APP_DEBUG_REG_08 0x02010038
237+#define IO_APP_DEBUG_REG_09 0x02010040
238+#define IO_APP_DEBUG_REG_10 0x02010048
239+#define IO_APP_DEBUG_REG_11 0x02010050
240+#define IO_APP_DEBUG_REG_12 0x02010058
241+#define IO_APP_DEBUG_REG_13 0x02010060
242+#define IO_APP_DEBUG_REG_14 0x02010068
243+#define IO_APP_DEBUG_REG_15 0x02010070
244+#define IO_APP_DEBUG_REG_16 0x02010078
245+#define IO_APP_DEBUG_REG_17 0x02010080
246+#define IO_APP_DEBUG_REG_18 0x02010088
247+
248+/* Read/write from/to registers */
249+struct genwqe_reg_io {
250+ __u64 num; /* register offset/address */
251+ __u64 val64;
252+};
253+
254+/*
255+ * All registers of our card will return values not equal this values.
256+ * If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the
257+ * card can be considered as unusable. It will need recovery.
258+ */
259+#define IO_ILLEGAL_VALUE 0xffffffffffffffffull
260+
261+/*
262+ * Generic DDCB execution interface.
263+ *
264+ * This interface is a first prototype resulting from discussions we
265+ * had with other teams which wanted to use the Genwqe card. It allows
266+ * to issue a DDCB request in a generic way. The request will block
267+ * until it finishes or time out with error.
268+ *
269+ * Some DDCBs require DMA addresses to be specified in the ASIV
270+ * block. The interface provies the capability to let the kernel
271+ * driver know where those addresses are by specifying the ATS field,
272+ * such that it can replace the user-space addresses with appropriate
273+ * DMA addresses or DMA addresses of a scatter gather list which is
274+ * dynamically created.
275+ *
276+ * Our hardware will refuse DDCB execution if the ATS field is not as
277+ * expected. That means the DDCB execution engine in the chip knows
278+ * where it expects DMA addresses within the ASIV part of the DDCB and
279+ * will check that against the ATS field definition. Any invalid or
280+ * unknown ATS content will lead to DDCB refusal.
281+ */
282+
283+/* Genwqe chip Units */
284+#define DDCB_ACFUNC_SLU 0x00 /* chip service layer unit */
285+#define DDCB_ACFUNC_APP 0x01 /* chip application */
286+
287+/* DDCB return codes (RETC) */
288+#define DDCB_RETC_IDLE 0x0000 /* Unexecuted/DDCB created */
289+#define DDCB_RETC_PENDING 0x0101 /* Pending Execution */
290+#define DDCB_RETC_COMPLETE 0x0102 /* Cmd complete. No error */
291+#define DDCB_RETC_FAULT 0x0104 /* App Err, recoverable */
292+#define DDCB_RETC_ERROR 0x0108 /* App Err, non-recoverable */
293+#define DDCB_RETC_FORCED_ERROR 0x01ff /* overwritten by driver */
294+
295+#define DDCB_RETC_UNEXEC 0x0110 /* Unexe/Removed from queue */
296+#define DDCB_RETC_TERM 0x0120 /* Terminated */
297+#define DDCB_RETC_RES0 0x0140 /* Reserved */
298+#define DDCB_RETC_RES1 0x0180 /* Reserved */
299+
300+/* DDCB Command Options (CMDOPT) */
301+#define DDCB_OPT_ECHO_FORCE_NO 0x0000 /* ECHO DDCB */
302+#define DDCB_OPT_ECHO_FORCE_102 0x0001 /* force return code */
303+#define DDCB_OPT_ECHO_FORCE_104 0x0002
304+#define DDCB_OPT_ECHO_FORCE_108 0x0003
305+
306+#define DDCB_OPT_ECHO_FORCE_110 0x0004 /* only on PF ! */
307+#define DDCB_OPT_ECHO_FORCE_120 0x0005
308+#define DDCB_OPT_ECHO_FORCE_140 0x0006
309+#define DDCB_OPT_ECHO_FORCE_180 0x0007
310+
311+#define DDCB_OPT_ECHO_COPY_NONE (0 << 5)
312+#define DDCB_OPT_ECHO_COPY_ALL (1 << 5)
313+
314+/* Definitions of Service Layer Commands */
315+#define SLCMD_ECHO_SYNC 0x00 /* PF/VF */
316+#define SLCMD_MOVE_FLASH 0x06 /* PF only */
317+#define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */
318+#define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 /* mode: download */
319+#define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 /* mode: emulation */
320+#define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 /* mode: upload */
321+#define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 /* mode: verify */
322+#define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2)/* just dump DDCB and exit */
323+#define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3)/* wait for RETC >= 0102 */
324+#define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4)
325+#define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5)
326+
327+enum genwqe_card_state {
328+ GENWQE_CARD_UNUSED = 0,
329+ GENWQE_CARD_USED = 1,
330+ GENWQE_CARD_FATAL_ERROR = 2,
331+ GENWQE_CARD_STATE_MAX,
332+};
333+
334+/* common struct for chip image exchange */
335+struct genwqe_bitstream {
336+ __u64 data_addr; /* pointer to image data */
337+ __u32 size; /* size of image file */
338+ __u32 crc; /* crc of this image */
339+ __u64 target_addr; /* starting address in Flash */
340+ __u32 partition; /* '0', '1', or 'v' */
341+ __u32 uid; /* 1=host/x=dram */
342+
343+ __u64 slu_id; /* informational/sim: SluID */
344+ __u64 app_id; /* informational/sim: AppID */
345+
346+ __u16 retc; /* returned from processing */
347+ __u16 attn; /* attention code from processing */
348+ __u32 progress; /* progress code from processing */
349+};
350+
351+/* Issuing a specific DDCB command */
352+#define DDCB_LENGTH 256 /* for debug data */
353+#define DDCB_ASIV_LENGTH 104 /* len of the DDCB ASIV array */
354+#define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
355+#define DDCB_ASV_LENGTH 64 /* len of the DDCB ASV array */
356+#define DDCB_FIXUPS 12 /* maximum number of fixups */
357+
358+struct genwqe_debug_data {
359+ char driver_version[64];
360+ __u64 slu_unitcfg;
361+ __u64 app_unitcfg;
362+
363+ __u8 ddcb_before[DDCB_LENGTH];
364+ __u8 ddcb_prev[DDCB_LENGTH];
365+ __u8 ddcb_finished[DDCB_LENGTH];
366+};
367+
368+/*
369+ * Address Translation Specification (ATS) definitions
370+ *
371+ * Each 4 bit within the ATS 64-bit word specify the required address
372+ * translation at the defined offset.
373+ *
374+ * 63 LSB
375+ * 6666.5555.5555.5544.4444.4443.3333.3333 ... 11
376+ * 3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210
377+ *
378+ * offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78
379+ * res res res res ASIV ...
380+ * The first 4 entries in the ATS word are reserved. The following nibbles
381+ * each describe at an 8 byte offset the format of the required data.
382+ */
383+#define ATS_TYPE_DATA 0x0ull /* data */
384+#define ATS_TYPE_FLAT_RD 0x4ull /* flat buffer read only */
385+#define ATS_TYPE_FLAT_RDWR 0x5ull /* flat buffer read/write */
386+#define ATS_TYPE_SGL_RD 0x6ull /* sgl read only */
387+#define ATS_TYPE_SGL_RDWR 0x7ull /* sgl read/write */
388+
389+#define ATS_SET_FLAGS(_struct, _field, _flags) \
390+ (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8))))
391+
392+#define ATS_GET_FLAGS(_ats, _byte_offs) \
393+ (((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf)
394+
395+/**
396+ * struct genwqe_ddcb_cmd - User parameter for generic DDCB commands
397+ *
398+ * On the way into the kernel the driver will read the whole data
399+ * structure. On the way out the driver will not copy the ASIV data
400+ * back to user-space.
401+ */
402+struct genwqe_ddcb_cmd {
403+ /* START of data copied to/from driver */
404+ __u64 next_addr; /* chaining genwqe_ddcb_cmd */
405+ __u64 flags; /* reserved */
406+
407+ __u8 acfunc; /* accelerators functional unit */
408+ __u8 cmd; /* command to execute */
409+ __u8 asiv_length; /* used parameter length */
410+ __u8 asv_length; /* length of valid return values */
411+ __u16 cmdopts; /* command options */
412+ __u16 retc; /* return code from processing */
413+
414+ __u16 attn; /* attention code from processing */
415+ __u16 vcrc; /* variant crc16 */
416+ __u32 progress; /* progress code from processing */
417+
418+ __u64 deque_ts; /* dequeue time stamp */
419+ __u64 cmplt_ts; /* completion time stamp */
420+ __u64 disp_ts; /* SW processing start */
421+
422+ /* move to end and avoid copy-back */
423+ __u64 ddata_addr; /* collect debug data */
424+
425+ /* command specific values */
426+ __u8 asv[DDCB_ASV_LENGTH];
427+
428+ /* END of data copied from driver */
429+ union {
430+ struct {
431+ __u64 ats;
432+ __u8 asiv[DDCB_ASIV_LENGTH_ATS];
433+ };
434+ /* used for flash update to keep it backward compatible */
435+ __u8 __asiv[DDCB_ASIV_LENGTH];
436+ };
437+ /* END of data copied to driver */
438+};
439+
440+#define GENWQE_IOC_CODE 0xa5
441+
442+/* Access functions */
443+#define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io)
444+#define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io)
445+#define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io)
446+#define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io)
447+#define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io)
448+#define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io)
449+
450+#define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state)
451+
452+/**
453+ * struct genwqe_mem - Memory pinning/unpinning information
454+ * @addr: virtual user space address
455+ * @size: size of the area pin/dma-map/unmap
456+ * direction: 0: read/1: read and write
457+ *
458+ * Avoid pinning and unpinning of memory pages dynamically. Instead
459+ * the idea is to pin the whole buffer space required for DDCB
460+ * opertionas in advance. The driver will reuse this pinning and the
461+ * memory associated with it to setup the sglists for the DDCB
462+ * requests without the need to allocate and free memory or map and
463+ * unmap to get the DMA addresses.
464+ *
465+ * The inverse operation needs to be called after the pinning is not
466+ * needed anymore. The pinnings else the pinnings will get removed
467+ * after the device is closed. Note that pinnings will required
468+ * memory.
469+ */
470+struct genwqe_mem {
471+ __u64 addr;
472+ __u64 size;
473+ __u64 direction;
474+ __u64 flags;
475+};
476+
477+#define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem)
478+#define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem)
479+
480+/*
481+ * Generic synchronous DDCB execution interface.
482+ * Synchronously execute a DDCB.
483+ *
484+ * Return: 0 on success or negative error code.
485+ * -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups
486+ * no mappings found/could not create mappings
487+ * -EFAULT: illegal addresses in fixups, purging failed
488+ * -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE
489+ */
490+#define GENWQE_EXECUTE_DDCB \
491+ _IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd)
492+
493+#define GENWQE_EXECUTE_RAW_DDCB \
494+ _IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd)
495+
496+/* Service Layer functions (PF only) */
497+#define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream)
498+#define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream)
499+
500+#endif /* __GENWQE_CARD_H__ */