The term "HQD" is CP-specific and doesn't accurately describe the queue resources for other IP blocks like SDMA, VCN, or VPE. This change: 1. Renames `num_hqds` to `num_slots` in amdgpu_kms.c to better reflect the generic nature of the resource counting 2. Updates the UAPI struct member from `userq_num_hqds` to `userq_num_slots` 3. Maintains the same functionality while using more appropriate terminology
Unified · Split
| @@ -399,7 +399,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, · 398 unmodified lines | |||
| 399 | uint32_t ib_size_alignment = 0; | 399 | uint32_t ib_size_alignment = 0; |
| 400 | enum amd_ip_block_type type; | 400 | enum amd_ip_block_type type; |
| 401 | unsigned int num_rings = 0; | 401 | unsigned int num_rings = 0; |
| 402 | uint32_t num_hqds = 0; | 402 | uint32_t num_slots = 0; |
| 403 | unsigned int i, j; | 403 | unsigned int i, j; |
| 404 | 404 | ||
| 405 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | 405 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
| @@ -415,7 +415,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, · 9 unmodified lines | |||
| 415 | 415 | ||
| 416 | if (!adev->gfx.disable_uq) { | 416 | if (!adev->gfx.disable_uq) { |
| 417 | for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) | 417 | for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) |
| 418 | num_hqds += hweight32(adev->mes.gfx_hqd_mask[i]); | 418 | num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); |
| 419 | } | 419 | } |
| 420 | 420 | ||
| 421 | ib_start_alignment = 32; | 421 | ib_start_alignment = 32; |
| @@ -430,7 +430,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, · 8 unmodified lines | |||
| 430 | 430 | ||
| 431 | if (!adev->sdma.disable_uq) { | 431 | if (!adev->sdma.disable_uq) { |
| 432 | for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) | 432 | for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) |
| 433 | num_hqds += hweight32(adev->mes.compute_hqd_mask[i]); | 433 | num_slots += hweight32(adev->mes.compute_hqd_mask[i]); |
| 434 | } | 434 | } |
| 435 | 435 | ||
| 436 | ib_start_alignment = 32; | 436 | ib_start_alignment = 32; |
| @@ -445,7 +445,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, · 8 unmodified lines | |||
| 445 | 445 | ||
| 446 | if (!adev->gfx.disable_uq) { | 446 | if (!adev->gfx.disable_uq) { |
| 447 | for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) | 447 | for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) |
| 448 | num_hqds += hweight32(adev->mes.sdma_hqd_mask[i]); | 448 | num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); |
| 449 | } | 449 | } |
| 450 | 450 | ||
| 451 | ib_start_alignment = 256; | 451 | ib_start_alignment = 256; |
| @@ -589,7 +589,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, · 137 unmodified lines | |||
| 589 | } | 589 | } |
| 590 | result->capabilities_flags = 0; | 590 | result->capabilities_flags = 0; |
| 591 | result->available_rings = (1 << num_rings) - 1; | 591 | result->available_rings = (1 << num_rings) - 1; |
| 592 | result->userq_num_hqds = num_hqds; | 592 | result->userq_num_slots = num_slots; |
| 593 | result->ib_start_alignment = ib_start_alignment; | 593 | result->ib_start_alignment = ib_start_alignment; |
| 594 | result->ib_size_alignment = ib_size_alignment; | 594 | result->ib_size_alignment = ib_size_alignment; |
| 595 | return 0; | 595 | return 0; |
| @@ -1493,8 +1493,8 @@ struct drm_amdgpu_info_hw_ip { · 1492 unmodified lines | |||
| 1493 | __u32 available_rings; | 1493 | __u32 available_rings; |
| 1494 | /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ | 1494 | /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ |
| 1495 | __u32 ip_discovery_version; | 1495 | __u32 ip_discovery_version; |
| 1496 | /* Userq available hqds */ | 1496 | /* Userq available slots */ |
| 1497 | __u32 userq_num_hqds; | 1497 | __u32 userq_num_slots; |
| 1498 | }; | 1498 | }; |
| 1499 | 1499 | ||
| 1500 | /* GFX metadata BO sizes and alignment info (in bytes) */ | 1500 | /* GFX metadata BO sizes and alignment info (in bytes) */ |