lael-labs/linux

Documentation/DocBook/gpu.tmpl+20−40

           <function>drm_gem_object_init</function>. Storage for private GEM
           objects must be managed by drivers.
         </para>
-        <para>
-          Drivers that do not need to extend GEM objects with private information
-          can call the <function>drm_gem_object_alloc</function> function to
-          allocate and initialize a struct <structname>drm_gem_object</structname>
-          instance. The GEM core will call the optional driver
-          <methodname>gem_init_object</methodname> operation after initializing
-          the GEM object with <function>drm_gem_object_init</function>.
-          <synopsis>int (*gem_init_object) (struct drm_gem_object *obj);</synopsis>
-        </para>
-        <para>
-          No alloc-and-init function exists for private GEM objects.
-        </para>
       </sect3>
       <sect3>
         <title>GEM Objects Lifetime</title>
           acquired and release by <function>calling drm_gem_object_reference</function>
           and <function>drm_gem_object_unreference</function> respectively. The
           caller must hold the <structname>drm_device</structname>
-          <structfield>struct_mutex</structfield> lock. As a convenience, GEM
+	  <structfield>struct_mutex</structfield> lock when calling
-          provides the <function>drm_gem_object_reference_unlocked</function> and
+	  <function>drm_gem_object_reference</function>. As a convenience, GEM
-          <function>drm_gem_object_unreference_unlocked</function> functions that
+	  provides <function>drm_gem_object_unreference_unlocked</function>
-          can be called without holding the lock.
+	  functions that can be called without holding the lock.
         </para>
         <para>
           When the last reference to a GEM object is released the GEM core calls
         </para>
         <para>
           <synopsis>void (*gem_free_object) (struct drm_gem_object *obj);</synopsis>
-          Drivers are responsible for freeing all GEM object resources, including
+          Drivers are responsible for freeing all GEM object resources. This includes
-          the resources created by the GEM core. If an mmap offset has been
+          the resources created by the GEM core, which need to be released with
-          created for the object (in which case
+          <function>drm_gem_object_release</function>.
-          <structname>drm_gem_object</structname>::<structfield>map_list</structfield>::<structfield>map</structfield>
-          is not NULL) it must be freed by a call to
-          <function>drm_gem_free_mmap_offset</function>. The shmfs backing store
-          must be released by calling <function>drm_gem_object_release</function>
-          (that function can safely be called if no shmfs backing store has been
-          created).
         </para>
       </sect3>
       <sect3>
           DRM identifies the GEM object to be mapped by a fake offset passed
           through the mmap offset argument. Prior to being mapped, a GEM object
           must thus be associated with a fake offset. To do so, drivers must call
-          <function>drm_gem_create_mmap_offset</function> on the object. The
+          <function>drm_gem_create_mmap_offset</function> on the object.
-          function allocates a fake offset range from a pool and stores the
-          offset divided by PAGE_SIZE in
-          <literal>obj-&gt;map_list.hash.key</literal>. Care must be taken not to
-          call <function>drm_gem_create_mmap_offset</function> if a fake offset
-          has already been allocated for the object. This can be tested by
-          <literal>obj-&gt;map_list.map</literal> being non-NULL.
         </para>
         <para>
           Once allocated, the fake offset value
-          (<literal>obj-&gt;map_list.hash.key &lt;&lt; PAGE_SHIFT</literal>)
           must be passed to the application in a driver-specific way and can then
           be used as the mmap offset argument.
         </para>
           abstracted from the client in libdrm.
         </para>
       </sect3>
-      <sect3>
+    </sect2>
-        <title>GEM Function Reference</title>
+    <sect2>
+      <title>GEM Function Reference</title>
 !Edrivers/gpu/drm/drm_gem.c
-      </sect3>
+!Iinclude/drm/drm_gem.h
     </sect2>
     <sect2>
       <title>VMA Offset Manager</title>
       </sect2>
     </sect1>
     <sect1>
-      <title>GuC-based Command Submission</title>
+      <title>GuC</title>
       <sect2>
-        <title>GuC</title>
+        <title>GuC-specific firmware loader</title>
 !Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader
 !Idrivers/gpu/drm/i915/intel_guc_loader.c
       </sect2>
       <sect2>
-        <title>GuC Client</title>
+        <title>GuC-based command submission</title>
-!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command submissison
+!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command submission
 !Idrivers/gpu/drm/i915/i915_guc_submission.c
       </sect2>
+      <sect2>
+        <title>GuC Firmware Layout</title>
+!Pdrivers/gpu/drm/i915/intel_guc_fwif.h GuC Firmware Layout
+      </sect2>
     </sect1>
     <sect1>

Documentation/devicetree/bindings/sound/ak4613.txt+10−0

@@ -7,6 +7,16 @@ Required properties: · 6 unmodified lines
7	- compatible : "asahi-kasei,ak4613"	7	- compatible : "asahi-kasei,ak4613"
8	- reg : The chip select number on the I2C bus	8	- reg : The chip select number on the I2C bus
9		9
		10	Optional properties:
		11	- asahi-kasei,in1-single-end : Boolean. Indicate input / output pins are single-ended.
		12	- asahi-kasei,in2-single-end rather than differential.
		13	- asahi-kasei,out1-single-end
		14	- asahi-kasei,out2-single-end
		15	- asahi-kasei,out3-single-end
		16	- asahi-kasei,out4-single-end
		17	- asahi-kasei,out5-single-end
		18	- asahi-kasei,out6-single-end
		19
10	Example:	20	Example:
11		21
12	&i2c {	22	&i2c {

Documentation/devicetree/bindings/sound/atmel-pdmic.txt+55−0

@@ -0,0 +1,55 @@
	1	* Atmel PDMIC driver under ALSA SoC architecture
	2
	3	Required properties:
	4	- compatible
	5	Should be "atmel,sama5d2-pdmic".
	6	- reg
	7	Should contain PDMIC registers location and length.
	8	- interrupts
	9	Should contain the IRQ line for the PDMIC.
	10	- dmas
	11	One DMA specifiers as described in atmel-dma.txt and dma.txt files.
	12	- dma-names
	13	Must be "rx".
	14	- clock-names
	15	Required elements:
	16	- "pclk" peripheral clock
	17	- "gclk" generated clock
	18	- clocks
	19	Must contain an entry for each required entry in clock-names.
	20	Please refer to clock-bindings.txt.
	21	- atmel,mic-min-freq
	22	The minimal frequency that the micphone supports.
	23	- atmel,mic-max-freq
	24	The maximal frequency that the micphone supports.
	25
	26	Optional properties:
	27	- pinctrl-names, pinctrl-0
	28	Please refer to pinctrl-bindings.txt.
	29	- atmel,model
	30	The user-visible name of this sound card.
	31	The default value is "PDMIC".
	32	- atmel,mic-offset
	33	The offset that should be added.
	34	The range is from -32768 to 32767.
	35	The default value is 0.
	36
	37	Example:
	38	pdmic@f8018000 {
	39	compatible = "atmel,sama5d2-pdmic";
	40	reg = <0xf8018000 0x124>;
	41	interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
	42	dmas = <&dma0
	43	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1)
	44	\| AT91_XDMAC_DT_PERID(50))>;
	45	dma-names = "rx";
	46	clocks = <&pdmic_clk>, <&pdmic_gclk>;
	47	clock-names = "pclk", "gclk";
	48
	49	pinctrl-names = "default";
	50	pinctrl-0 = <&pinctrl_pdmic_default>;
	51	atmel,model = "PDMIC @ sama5d2_xplained";
	52	atmel,mic-min-freq = <1000000>;
	53	atmel,mic-max-freq = <3246000>;
	54	atmel,mic-offset = <0x0>;
	55	};

Documentation/devicetree/bindings/sound/da7218.txt+104−0

@@ -0,0 +1,104 @@
	1	Dialog Semiconductor DA7218 Audio Codec bindings
	2
	3	DA7218 is an audio codec with HP detect feature.
	4
	5	======
	6
	7	Required properties:
	8	- compatible : Should be "dlg,da7217" or "dlg,da7218"
	9	- reg: Specifies the I2C slave address
	10
	11	- VDD-supply: VDD power supply for the device
	12	- VDDMIC-supply: VDDMIC power supply for the device
	13	- VDDIO-supply: VDDIO power supply for the device
	14	(See Documentation/devicetree/bindings/regulator/regulator.txt for further
	15	information relating to regulators)
	16
	17	Optional properties:
	18	- interrupt-parent: Specifies the phandle of the interrupt controller to which
	19	the IRQs from DA7218 are delivered to.
	20	- interrupts: IRQ line info for DA7218 chip.
	21	(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
	22	further information relating to interrupt properties)
	23	- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
	24	interrupt is to be used to wake system, otherwise "irq" should be used.
	25	- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
	26
	27	- clocks : phandle and clock specifier for codec MCLK.
	28	- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
	29
	30	- dlg,micbias1-lvl-millivolt : Voltage (mV) for Mic Bias 1
	31	[<1200>, <1600>, <1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>]
	32	- dlg,micbias2-lvl-millivolt : Voltage (mV) for Mic Bias 2
	33	[<1200>, <1600>, <1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>]
	34	- dlg,mic1-amp-in-sel : Mic1 input source type
	35	["diff", "se_p", "se_n"]
	36	- dlg,mic2-amp-in-sel : Mic2 input source type
	37	["diff", "se_p", "se_n"]
	38	- dlg,dmic1-data-sel : DMIC1 channel select based on clock edge.
	39	["lrise_rfall", "lfall_rrise"]
	40	- dlg,dmic1-samplephase : When to sample audio from DMIC1.
	41	["on_clkedge", "between_clkedge"]
	42	- dlg,dmic1-clkrate-hz : DMic1 clock frequency (Hz).
	43	[<1500000>, <3000000>]
	44	- dlg,dmic2-data-sel : DMic2 channel select based on clock edge.
	45	["lrise_rfall", "lfall_rrise"]
	46	- dlg,dmic2-samplephase : When to sample audio from DMic2.
	47	["on_clkedge", "between_clkedge"]
	48	- dlg,dmic2-clkrate-hz : DMic2 clock frequency (Hz).
	49	[<1500000>, <3000000>]
	50	- dlg,hp-diff-single-supply : Boolean flag, use single supply for HP
	51	(DA7217 only)
	52
	53	======
	54
	55	Optional Child node - 'da7218_hpldet' (DA7218 only):
	56
	57	Optional properties:
	58	- dlg,jack-rate-us : Time between jack detect measurements (us)
	59	[<5>, <10>, <20>, <40>, <80>, <160>, <320>, <640>]
	60	- dlg,jack-debounce : Number of debounce measurements taken for jack detect
	61	[<0>, <2>, <3>, <4>]
	62	- dlg,jack-threshold-pct : Threshold level for jack detection (% of VDD)
	63	[<84>, <88>, <92>, <96>]
	64	- dlg,comp-inv : Boolean flag, invert comparator output
	65	- dlg,hyst : Boolean flag, enable hysteresis
	66	- dlg,discharge : Boolean flag, auto discharge of Mic Bias on jack removal
	67
	68	======
	69
	70	Example:
	71
	72	codec: da7218@1a {
	73	compatible = "dlg,da7218";
	74	reg = <0x1a>;
	75	interrupt-parent = <&gpio6>;
	76	interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
	77	wakeup-source;
	78
	79	VDD-supply = <&reg_audio>;
	80	VDDMIC-supply = <&reg_audio>;
	81	VDDIO-supply = <&reg_audio>;
	82
	83	clocks = <&clks 201>;
	84	clock-names = "mclk";
	85
	86	dlg,micbias1-lvl-millivolt = <2600>;
	87	dlg,micbias2-lvl-millivolt = <2600>;
	88	dlg,mic1-amp-in-sel = "diff";
	89	dlg,mic2-amp-in-sel = "diff";
	90
	91	dlg,dmic1-data-sel = "lrise_rfall";
	92	dlg,dmic1-samplephase = "on_clkedge";
	93	dlg,dmic1-clkrate-hz = <3000000>;
	94	dlg,dmic2-data-sel = "lrise_rfall";
	95	dlg,dmic2-samplephase = "on_clkedge";
	96	dlg,dmic2-clkrate-hz = <3000000>;
	97
	98	da7218_hpldet {
	99	dlg,jack-rate-us = <40>;
	100	dlg,jack-debounce = <2>;
	101	dlg,jack-threshold-pct = <84>;
	102	dlg,hyst;
	103	};
	104	};

Documentation/devicetree/bindings/sound/da7219.txt+5−3

 - clocks : phandle and clock specifier for codec MCLK.
 - clock-names : Clock name string for 'clocks' attribute, should be "mclk".
-- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
-	[<1050>, <1100>, <1200>, <1400>]
 - dlg,micbias-lvl : Voltage (mV) for Mic Bias
-	[<1800>, <2000>, <2200>, <2400>, <2600>]
+	[<1600>, <1800>, <2000>, <2200>, <2400>, <2600>]
 - dlg,mic-amp-in-sel : Mic input source type
 	["diff", "se_p", "se_n"]
+Deprecated properties:
+- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
+  (LDO unavailable in production HW so property no longer required).
 ======
 Child node - 'da7219_aad':

Documentation/devicetree/bindings/sound/fsl,asrc.txt+5−0

 	"mem"		  Peripheral access clock to access registers.
 	"ipg"		  Peripheral clock to driver module.
 	"asrck_<0-f>"	  Clock sources for input and output clock.
+	"spba"		  The spba clock is required when ASRC is placed as a
+			  bus slave of the Shared Peripheral Bus and when two
+			  or more bus masters (CPU, DMA or DSP) try to access
+			  it. This property is optional depending on the SoC
+			  design.
    - big-endian		: If this property is absent, the little endian mode
 			  will be in use as default. Otherwise, the big endian

Documentation/devicetree/bindings/sound/fsl,esai.txt+5−0

 			  derive HCK, SCK and FS.
 	"fsys"		  The system clock derived from ahb clock used to
 			  derive HCK, SCK and FS.
+	"spba"		  The spba clock is required when ESAI is placed as a
+			  bus slave of the Shared Peripheral Bus and when two
+			  or more bus masters (CPU, DMA or DSP) try to access
+			  it. This property is optional depending on the SoC
+			  design.
   - fsl,fifo-depth	: The number of elements in the transmit and receive
 			  FIFOs. This number is the maximum allowed value for

Documentation/devicetree/bindings/sound/fsl,spdif.txt+5−0

 			  Transceiver Clock Diagram" of SoC reference manual.
 			  It can also be referred to TxClk_Source bit of
 			  register SPDIF_STC.
+	"spba"		  The spba clock is required when SPDIF is placed as a
+			  bus slave of the Shared Peripheral Bus and when two
+			  or more bus masters (CPU, DMA or DSP) try to access
+			  it. This property is optional depending on the SoC
+			  design.
    - big-endian		: If this property is absent, the native endian mode
 			  will be in use as default, or the big endian mode

Documentation/devicetree/bindings/sound/img,i2s-in.txt+47−0

@@ -0,0 +1,47 @@
	1	Imagination Technologies I2S Input Controller
	2
	3	Required Properties:
	4
	5	- compatible : Compatible list, must contain "img,i2s-in"
	6
	7	- #sound-dai-cells : Must be equal to 0
	8
	9	- reg : Offset and length of the register set for the device
	10
	11	- clocks : Contains an entry for each entry in clock-names
	12
	13	- clock-names : Must include the following entry:
	14	"sys" The system clock
	15
	16	- dmas: Contains an entry for each entry in dma-names.
	17
	18	- dma-names: Must include the following entry:
	19	"rx" Single DMA channel used by all active I2S channels
	20
	21	- img,i2s-channels : Number of I2S channels instantiated in the I2S in block
	22
	23	Optional Properties:
	24
	25	- interrupts : Contains the I2S in interrupts. Depending on
	26	the configuration, there may be no interrupts, one interrupt,
	27	or an interrupt per I2S channel. For the case where there is
	28	one interrupt per channel, the interrupts should be listed
	29	in ascending channel order
	30
	31	- resets: Contains a phandle to the I2S in reset signal
	32
	33	- reset-names: Contains the reset signal name "rst"
	34
	35	Example:
	36
	37	i2s_in: i2s-in@18100800 {
	38	compatible = "img,i2s-in";
	39	reg = <0x18100800 0x200>;
	40	interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
	41	dmas = <&mdc 30 0xffffffff 0>;
	42	dma-names = "rx";
	43	clocks = <&cr_periph SYS_CLK_I2S_IN>;
	44	clock-names = "sys";
	45	img,i2s-channels = <6>;
	46	#sound-dai-cells = <0>;
	47	};

Documentation/devicetree/bindings/sound/img,i2s-out.txt+51−0

@@ -0,0 +1,51 @@
	1	Imagination Technologies I2S Output Controller
	2
	3	Required Properties:
	4
	5	- compatible : Compatible list, must contain "img,i2s-out"
	6
	7	- #sound-dai-cells : Must be equal to 0
	8
	9	- reg : Offset and length of the register set for the device
	10
	11	- clocks : Contains an entry for each entry in clock-names
	12
	13	- clock-names : Must include the following entries:
	14	"sys" The system clock
	15	"ref" The reference clock
	16
	17	- dmas: Contains an entry for each entry in dma-names.
	18
	19	- dma-names: Must include the following entry:
	20	"tx" Single DMA channel used by all active I2S channels
	21
	22	- img,i2s-channels : Number of I2S channels instantiated in the I2S out block
	23
	24	- resets: Contains a phandle to the I2S out reset signal
	25
	26	- reset-names: Contains the reset signal name "rst"
	27
	28	Optional Properties:
	29
	30	- interrupts : Contains the I2S out interrupts. Depending on
	31	the configuration, there may be no interrupts, one interrupt,
	32	or an interrupt per I2S channel. For the case where there is
	33	one interrupt per channel, the interrupts should be listed
	34	in ascending channel order
	35
	36	Example:
	37
	38	i2s_out: i2s-out@18100A00 {
	39	compatible = "img,i2s-out";
	40	reg = <0x18100A00 0x200>;
	41	interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
	42	dmas = <&mdc 23 0xffffffff 0>;
	43	dma-names = "tx";
	44	clocks = <&cr_periph SYS_CLK_I2S_OUT>,
	45	<&clk_core CLK_I2S>;
	46	clock-names = "sys", "ref";
	47	img,i2s-channels = <6>;
	48	resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
	49	reset-names = "rst";
	50	#sound-dai-cells = <0>;
	51	};

Documentation/devicetree/bindings/sound/img,parallel-out.txt+44−0

@@ -0,0 +1,44 @@
	1	Imagination Technologies Parallel Output Controller
	2
	3	Required Properties:
	4
	5	- compatible : Compatible list, must contain "img,parallel-out".
	6
	7	- #sound-dai-cells : Must be equal to 0
	8
	9	- reg : Offset and length of the register set for the device.
	10
	11	- dmas: Contains an entry for each entry in dma-names.
	12
	13	- dma-names: Must include the following entry:
	14	"tx"
	15
	16	- clocks : Contains an entry for each entry in clock-names.
	17
	18	- clock-names : Includes the following entries:
	19	"sys" The system clock
	20	"ref" The reference clock
	21
	22	- resets: Contains a phandle to the parallel out reset signal
	23
	24	- reset-names: Contains the reset signal name "rst"
	25
	26	Optional Properties:
	27
	28	- interrupts : Contains the parallel out interrupt, if present
	29
	30	Example:
	31
	32	parallel_out: parallel-out@18100C00 {
	33	compatible = "img,parallel-out";
	34	reg = <0x18100C00 0x100>;
	35	interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
	36	dmas = <&mdc 16 0xffffffff 0>;
	37	dma-names = "tx";
	38	clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
	39	<&clk_core CLK_AUDIO_DAC>;
	40	clock-names = "sys", "ref";
	41	resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
	42	reset-names = "rst";
	43	#sound-dai-cells = <0>;
	44	};

Documentation/devicetree/bindings/sound/img,pistachio-internal-dac.txt+18−0

@@ -0,0 +1,18 @@
	1	Pistachio internal DAC DT bindings
	2
	3	Required properties:
	4
	5	- compatible: "img,pistachio-internal-dac"
	6
	7	- img,cr-top : Must contain a phandle to the top level control syscon
	8	node which contains the internal dac control registers
	9
	10	- VDD-supply : Digital power supply regulator (+1.8V or +3.3V)
	11
	12	Examples:
	13
	14	internal_dac: internal-dac {
	15	compatible = "img,pistachio-internal-dac";
	16	img,cr-top = <&cr_top>;
	17	VDD-supply = <&supply3v3>;
	18	};

Documentation/devicetree/bindings/sound/img,spdif-in.txt+41−0

@@ -0,0 +1,41 @@
	1	Imagination Technologies SPDIF Input Controller
	2
	3	Required Properties:
	4
	5	- compatible : Compatible list, must contain "img,spdif-in"
	6
	7	- #sound-dai-cells : Must be equal to 0
	8
	9	- reg : Offset and length of the register set for the device
	10
	11	- dmas: Contains an entry for each entry in dma-names.
	12
	13	- dma-names: Must include the following entry:
	14	"rx"
	15
	16	- clocks : Contains an entry for each entry in clock-names
	17
	18	- clock-names : Includes the following entries:
	19	"sys" The system clock
	20
	21	Optional Properties:
	22
	23	- resets: Should contain a phandle to the spdif in reset signal, if any
	24
	25	- reset-names: Should contain the reset signal name "rst", if a
	26	reset phandle is given
	27
	28	- interrupts : Contains the spdif in interrupt, if present
	29
	30	Example:
	31
	32	spdif_in: spdif-in@18100E00 {
	33	compatible = "img,spdif-in";
	34	reg = <0x18100E00 0x100>;
	35	interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
	36	dmas = <&mdc 15 0xffffffff 0>;
	37	dma-names = "rx";
	38	clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
	39	clock-names = "sys";
	40	#sound-dai-cells = <0>;
	41	};

Documentation/devicetree/bindings/sound/img,spdif-out.txt+44−0

@@ -0,0 +1,44 @@
	1	Imagination Technologies SPDIF Output Controller
	2
	3	Required Properties:
	4
	5	- compatible : Compatible list, must contain "img,spdif-out"
	6
	7	- #sound-dai-cells : Must be equal to 0
	8
	9	- reg : Offset and length of the register set for the device
	10
	11	- dmas: Contains an entry for each entry in dma-names.
	12
	13	- dma-names: Must include the following entry:
	14	"tx"
	15
	16	- clocks : Contains an entry for each entry in clock-names.
	17
	18	- clock-names : Includes the following entries:
	19	"sys" The system clock
	20	"ref" The reference clock
	21
	22	- resets: Contains a phandle to the spdif out reset signal
	23
	24	- reset-names: Contains the reset signal name "rst"
	25
	26	Optional Properties:
	27
	28	- interrupts : Contains the parallel out interrupt, if present
	29
	30	Example:
	31
	32	spdif_out: spdif-out@18100D00 {
	33	compatible = "img,spdif-out";
	34	reg = <0x18100D00 0x100>;
	35	interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
	36	dmas = <&mdc 14 0xffffffff 0>;
	37	dma-names = "tx";
	38	clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
	39	<&clk_core CLK_SPDIF>;
	40	clock-names = "sys", "ref";
	41	resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
	42	reset-names = "rst";
	43	#sound-dai-cells = <0>;
	44	};

Documentation/devicetree/bindings/sound/inno-rk3036.txt+20−0

@@ -0,0 +1,20 @@
	1	Inno audio codec for RK3036
	2
	3	Inno audio codec is integrated inside RK3036 SoC.
	4
	5	Required properties:
	6	- compatible : Should be "rockchip,rk3036-codec".
	7	- reg : The registers of codec.
	8	- clock-names : Should be "acodec_pclk".
	9	- clocks : The clock of codec.
	10	- rockchip,grf : The phandle of grf device node.
	11
	12	Example:
	13
	14	acodec: acodec-ana@20030000 {
	15	compatible = "rk3036-codec";
	16	reg = <0x20030000 0x4000>;
	17	rockchip,grf = <&grf>;
	18	clock-names = "acodec_pclk";
	19	clocks = <&cru ACLK_VCODEC>;
	20	};

Documentation/devicetree/bindings/sound/pcm179x.txtrenamed from Documentation/devicetree/bindings/sound/pcm1792a.txt+1−1

@@ -1,4 +1,4 @@
1	Texas Instruments pcm1792a DT bindings	1	Texas Instruments pcm179x DT bindings
2		2
3	This driver supports the SPI bus.	3	This driver supports the SPI bus.
4		4

Documentation/devicetree/bindings/sound/renesas,rsnd.txt+82−0

@@ -7,8 +7,11 @@ Required properties: · 6 unmodified lines
7	"renesas,rcar_sound-gen3" if generation3	7	"renesas,rcar_sound-gen3" if generation3
8	Examples with soctypes are:	8	Examples with soctypes are:
9	- "renesas,rcar_sound-r8a7778" (R-Car M1A)	9	- "renesas,rcar_sound-r8a7778" (R-Car M1A)
		10	- "renesas,rcar_sound-r8a7779" (R-Car H1)
10	- "renesas,rcar_sound-r8a7790" (R-Car H2)	11	- "renesas,rcar_sound-r8a7790" (R-Car H2)
11	- "renesas,rcar_sound-r8a7791" (R-Car M2-W)	12	- "renesas,rcar_sound-r8a7791" (R-Car M2-W)
		13	- "renesas,rcar_sound-r8a7793" (R-Car M2-N)
		14	- "renesas,rcar_sound-r8a7794" (R-Car E2)
12	- "renesas,rcar_sound-r8a7795" (R-Car H3)	15	- "renesas,rcar_sound-r8a7795" (R-Car H3)
13	- reg : Should contain the register physical address.	16	- reg : Should contain the register physical address.
14	required register is	17	required register is
@@ -34,6 +37,8 @@ Required properties: · 19 unmodified lines
34	see below for detail.	37	see below for detail.
35	- #sound-dai-cells : it must be 0 if your system is using single DAI	38	- #sound-dai-cells : it must be 0 if your system is using single DAI
36	it must be 1 if your system is using multi DAI	39	it must be 1 if your system is using multi DAI
		40
		41	Optional properties:
37	- #clock-cells : it must be 0 if your system has audio_clkout	42	- #clock-cells : it must be 0 if your system has audio_clkout
38	it must be 1 if your system has audio_clkout0/1/2/3	43	it must be 1 if your system has audio_clkout0/1/2/3
39	- clock-frequency : for all audio_clkout0/1/2/3	44	- clock-frequency : for all audio_clkout0/1/2/3
@@ -244,3 +249,80 @@ rcar_sound: sound@ec500000 { · 204 unmodified lines
244	};	249	};
245	};	250	};
246	};	251	};
		252
		253	Example: simple sound card
		254
		255	rsnd_ak4643: sound {
		256	compatible = "simple-audio-card";
		257
		258	simple-audio-card,format = "left_j";
		259	simple-audio-card,bitclock-master = <&sndcodec>;
		260	simple-audio-card,frame-master = <&sndcodec>;
		261
		262	sndcpu: simple-audio-card,cpu {
		263	sound-dai = <&rcar_sound>;
		264	};
		265
		266	sndcodec: simple-audio-card,codec {
		267	sound-dai = <&ak4643>;
		268	clocks = <&audio_clock>;
		269	};
		270	};
		271
		272	&rcar_sound {
		273	pinctrl-0 = <&sound_pins &sound_clk_pins>;
		274	pinctrl-names = "default";
		275
		276	/* Single DAI */
		277	#sound-dai-cells = <0>;
		278
		279	status = "okay";
		280
		281	rcar_sound,dai {
		282	dai0 {
		283	playback = <&ssi0 &src2 &dvc0>;
		284	capture = <&ssi1 &src3 &dvc1>;
		285	};
		286	};
		287	};
		288
		289	&ssi1 {
		290	shared-pin;
		291	};
		292
		293	Example: simple sound card for TDM
		294
		295	rsnd_tdm: sound {
		296	compatible = "simple-audio-card";
		297
		298	simple-audio-card,format = "left_j";
		299	simple-audio-card,bitclock-master = <&sndcodec>;
		300	simple-audio-card,frame-master = <&sndcodec>;
		301
		302	sndcpu: simple-audio-card,cpu {
		303	sound-dai = <&rcar_sound>;
		304	dai-tdm-slot-num = <6>;
		305	};
		306
		307	sndcodec: simple-audio-card,codec {
		308	sound-dai = <&xxx>;
		309	};
		310	};
		311
		312	Example: simple sound card for Multi channel
		313
		314	&rcar_sound {
		315	pinctrl-0 = <&sound_pins &sound_clk_pins>;
		316	pinctrl-names = "default";
		317
		318	/* Single DAI */
		319	#sound-dai-cells = <0>;
		320
		321	status = "okay";
		322
		323	rcar_sound,dai {
		324	dai0 {
		325	playback = <&ssi0 &ssi1 &ssi2 &src0 &dvc0>;
		326	};
		327	};
		328	};

Documentation/devicetree/bindings/sound/renesas,rsrc-card.txt+2−2

@@ -4,8 +4,8 @@ Renesas Sampling Rate Convert Sound Card specifies audio DAI connections of SoC · 3 unmodified lines
4		4
5	Required properties:	5	Required properties:
6		6
7	- compatible : "renesas,rsrc-card,<board>"	7	- compatible : "renesas,rsrc-card{,<board>}"
8	Examples with soctypes are:	8	Examples with boards are:
9	- "renesas,rsrc-card"	9	- "renesas,rsrc-card"
10	- "renesas,rsrc-card,lager"	10	- "renesas,rsrc-card,lager"
11	- "renesas,rsrc-card,koelsch"	11	- "renesas,rsrc-card,koelsch"

Documentation/devicetree/bindings/sound/rockchip-i2s.txt+2−0

 - clock-names: should contain followings:
    - "i2s_hclk": clock for I2S BUS
    - "i2s_clk" : clock for I2S controller
+- rockchip,playback-channels: max playback channels, if not set, 8 channels default.
 - rockchip,capture-channels: max capture channels, if not set, 2 channels default.
 Example for rk3288 I2S controller:
 	dma-names = "tx", "rx";
 	clock-names = "i2s_hclk", "i2s_clk";
 	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+	rockchip,playback-channels = <8>;
 	rockchip,capture-channels = <2>;
 };

Documentation/devicetree/bindings/sound/rt5616.txt+26−0

@@ -0,0 +1,26 @@
	1	RT5616 audio CODEC
	2
	3	This device supports I2C only.
	4
	5	Required properties:
	6
	7	- compatible : "realtek,rt5616".
	8
	9	- reg : The I2C address of the device.
	10
	11	Pins on the device (for linking into audio routes) for RT5616:
	12
	13	* IN1P
	14	* IN2P
	15	* IN2N
	16	* LOUTL
	17	* LOUTR
	18	* HPOL
	19	* HPOR
	20
	21	Example:
	22
	23	codec: rt5616@1b {
	24	compatible = "realtek,rt5616";
	25	reg = <0x1b>;
	26	};

Documentation/devicetree/bindings/sound/rt5651.txt+41−0

@@ -0,0 +1,41 @@
	1	RT5651 audio CODEC
	2
	3	This device supports I2C only.
	4
	5	Required properties:
	6
	7	- compatible : "realtek,rt5651".
	8
	9	- reg : The I2C address of the device.
	10
	11	Optional properties:
	12
	13	- realtek,in2-differential
	14	Boolean. Indicate MIC2 input are differential, rather than single-ended.
	15
	16	- realtek,dmic-en
	17	Boolean. true if dmic is used.
	18
	19	Pins on the device (for linking into audio routes) for RT5651:
	20
	21	* DMIC L1
	22	* DMIC R1
	23	* IN1P
	24	* IN2P
	25	* IN2N
	26	* IN3P
	27	* HPOL
	28	* HPOR
	29	* LOUTL
	30	* LOUTR
	31	* PDML
	32	* PDMR
	33
	34	Example:
	35
	36	codec: rt5651@1a {
	37	compatible = "realtek,rt5651";
	38	reg = <0x1a>;
	39	realtek,dmic-en = "true";
	40	realtek,in2-diff = "false";
	41	};

Documentation/devicetree/bindings/sound/rt5659.txt+75−0

@@ -0,0 +1,75 @@
	1	RT5659/RT5658 audio CODEC
	2
	3	This device supports I2C only.
	4
	5	Required properties:
	6
	7	- compatible : One of "realtek,rt5659" or "realtek,rt5658".
	8
	9	- reg : The I2C address of the device.
	10
	11	- interrupts : The CODEC's interrupt output.
	12
	13	Optional properties:
	14
	15	- realtek,in1-differential
	16	- realtek,in3-differential
	17	- realtek,in4-differential
	18	Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
	19
	20	- realtek,dmic1-data-pin
	21	0: dmic1 is not used
	22	1: using IN2N pin as dmic1 data pin
	23	2: using GPIO5 pin as dmic1 data pin
	24	3: using GPIO9 pin as dmic1 data pin
	25	4: using GPIO11 pin as dmic1 data pin
	26
	27	- realtek,dmic2-data-pin
	28	0: dmic2 is not used
	29	1: using IN2P pin as dmic2 data pin
	30	2: using GPIO6 pin as dmic2 data pin
	31	3: using GPIO10 pin as dmic2 data pin
	32	4: using GPIO12 pin as dmic2 data pin
	33
	34	- realtek,jd-src
	35	0: No JD is used
	36	1: using JD3 as JD source
	37
	38	- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
	39	- realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin.
	40
	41	Pins on the device (for linking into audio routes) for RT5659/RT5658:
	42
	43	* DMIC L1
	44	* DMIC R1
	45	* DMIC L2
	46	* DMIC R2
	47	* IN1P
	48	* IN1N
	49	* IN2P
	50	* IN2N
	51	* IN3P
	52	* IN3N
	53	* IN4P
	54	* IN4N
	55	* HPOL
	56	* HPOR
	57	* SPOL
	58	* SPOR
	59	* LOUTL
	60	* LOUTR
	61	* MONOOUT
	62	* PDML
	63	* PDMR
	64	* SPDIF
	65
	66	Example:
	67
	68	rt5659 {
	69	compatible = "realtek,rt5659";
	70	reg = <0x1b>;
	71	interrupt-parent = <&gpio>;
	72	interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
	73	realtek,ldo1-en-gpios =
	74	<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
	75	};

Documentation/devicetree/bindings/sound/rt5677.txt+1−1

@@ -18,7 +18,7 @@ Required properties: · 17 unmodified lines
18	Optional properties:	18	Optional properties:
19		19
20	- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.	20	- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21	- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin.	21	- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
22		22
23	- realtek,in1-differential	23	- realtek,in1-differential
24	- realtek,in2-differential	24	- realtek,in2-differential

Documentation/devicetree/bindings/sound/sun4i-codec.txt+3−0

@@ -14,6 +14,9 @@ Required properties: · 13 unmodified lines
14	- "apb": the parent APB clock for this controller	14	- "apb": the parent APB clock for this controller
15	- "codec": the parent module clock	15	- "codec": the parent module clock
16		16
		17	Optional properties:
		18	- allwinner,pa-gpios: gpio to enable external amplifier
		19
17	Example:	20	Example:
18	codec: codec@01c22c00 {	21	codec: codec@01c22c00 {
19	#sound-dai-cells = <0>;	22	#sound-dai-cells = <0>;

Documentation/devicetree/bindings/sound/ti,pcm3168a.txt+48−0

@@ -0,0 +1,48 @@
	1	Texas Instruments pcm3168a DT bindings
	2
	3	This driver supports both SPI and I2C bus access for this codec
	4
	5	Required properties:
	6
	7	- compatible: "ti,pcm3168a"
	8
	9	- clocks : Contains an entry for each entry in clock-names
	10
	11	- clock-names : Includes the following entries:
	12	"scki" The system clock
	13
	14	- VDD1-supply : Digital power supply regulator 1 (+3.3V)
	15
	16	- VDD2-supply : Digital power supply regulator 2 (+3.3V)
	17
	18	- VCCAD1-supply : ADC power supply regulator 1 (+5V)
	19
	20	- VCCAD2-supply : ADC power supply regulator 2 (+5V)
	21
	22	- VCCDA1-supply : DAC power supply regulator 1 (+5V)
	23
	24	- VCCDA2-supply : DAC power supply regulator 2 (+5V)
	25
	26	For required properties on SPI/I2C, consult SPI/I2C device tree documentation
	27
	28	Examples:
	29
	30	i2c0: i2c0@0 {
	31
	32	...
	33
	34	pcm3168a: audio-codec@44 {
	35	compatible = "ti,pcm3168a";
	36	reg = <0x44>;
	37	clocks = <&clk_core CLK_AUDIO>;
	38	clock-names = "scki";
	39	VDD1-supply = <&supply3v3>;
	40	VDD2-supply = <&supply3v3>;
	41	VCCAD1-supply = <&supply5v0>;
	42	VCCAD2-supply = <&supply5v0>;
	43	VCCDA1-supply = <&supply5v0>;
	44	VCCDA2-supply = <&supply5v0>;
	45	pinctrl-names = "default";
	46	pinctrl-0 = <&dac_clk_pin>;
	47	};
	48	};

Documentation/devicetree/bindings/sound/wlf,wm8974.txt+15−0

@@ -0,0 +1,15 @@
	1	WM8974 audio CODEC
	2
	3	This device supports both I2C and SPI (configured with pin strapping
	4	on the board).
	5
	6	Required properties:
	7	- compatible: "wlf,wm8974"
	8	- reg: the I2C address or SPI chip select number of the device
	9
	10	Examples:
	11
	12	codec: wm8974@1a {
	13	compatible = "wlf,wm8974";
	14	reg = <0x1a>;
	15	};

Documentation/sound/alsa/img,spdif-in.txt+49−0

@@ -0,0 +1,49 @@
	1	The Imagination Technologies SPDIF Input controller contains the following
	2	controls:
	3
	4	name='IEC958 Capture Mask',index=0
	5
	6	This control returns a mask that shows which of the IEC958 status bits
	7	can be read using the 'IEC958 Capture Default' control.
	8
	9	name='IEC958 Capture Default',index=0
	10
	11	This control returns the status bits contained within the SPDIF stream that
	12	is being received. The 'IEC958 Capture Mask' shows which bits can be read
	13	from this control.
	14
	15	name='SPDIF In Multi Frequency Acquire',index=0
	16	name='SPDIF In Multi Frequency Acquire',index=1
	17	name='SPDIF In Multi Frequency Acquire',index=2
	18	name='SPDIF In Multi Frequency Acquire',index=3
	19
	20	This control is used to attempt acquisition of up to four different sample
	21	rates. The active rate can be obtained by reading the 'SPDIF In Lock Frequency'
	22	control.
	23
	24	When the value of this control is set to {0,0,0,0}, the rate given to hw_params
	25	will determine the single rate the block will capture. Else, the rate given to
	26	hw_params will be ignored, and the block will attempt capture for each of the
	27	four sample rates set here.
	28
	29	If less than four rates are required, the same rate can be specified more than
	30	once
	31
	32	name='SPDIF In Lock Frequency',index=0
	33
	34	This control returns the active capture rate, or 0 if a lock has not been
	35	acquired
	36
	37	name='SPDIF In Lock TRK',index=0
	38
	39	This control is used to modify the locking/jitter rejection characteristics
	40	of the block. Larger values increase the locking range, but reduce jitter
	41	rejection.
	42
	43	name='SPDIF In Lock Acquire Threshold',index=0
	44
	45	This control is used to change the threshold at which a lock is acquired.
	46
	47	name='SPDIF In Lock Release Threshold',index=0
	48
	49	This control is used to change the threshold at which a lock is released.

arch/arm/mach-s3c64xx/dev-audio.c+29−18

@@ -54,12 +54,13 @@ static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev) · 53 unmodified lines
54		54
55	static struct resource s3c64xx_iis0_resource[] = {	55	static struct resource s3c64xx_iis0_resource[] = {
56	[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256),	56	[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256),
57	[1] = DEFINE_RES_DMA(DMACH_I2S0_OUT),
58	[2] = DEFINE_RES_DMA(DMACH_I2S0_IN),
59	};	57	};
60		58
61	static struct s3c_audio_pdata i2sv3_pdata = {	59	static struct s3c_audio_pdata i2s0_pdata = {
62	.cfg_gpio = s3c64xx_i2s_cfg_gpio,	60	.cfg_gpio = s3c64xx_i2s_cfg_gpio,
		61	.dma_filter = pl08x_filter_id,
		62	.dma_playback = DMACH_I2S0_OUT,
		63	.dma_capture = DMACH_I2S0_IN,
63	};	64	};
64		65
65	struct platform_device s3c64xx_device_iis0 = {	66	struct platform_device s3c64xx_device_iis0 = {
@@ -68,15 +69,20 @@ struct platform_device s3c64xx_device_iis0 = { · 2 unmodified lines
68	.num_resources = ARRAY_SIZE(s3c64xx_iis0_resource),	69	.num_resources = ARRAY_SIZE(s3c64xx_iis0_resource),
69	.resource = s3c64xx_iis0_resource,	70	.resource = s3c64xx_iis0_resource,
70	.dev = {	71	.dev = {
71	.platform_data = &i2sv3_pdata,	72	.platform_data = &i2s0_pdata,
72	},	73	},
73	};	74	};
74	EXPORT_SYMBOL(s3c64xx_device_iis0);	75	EXPORT_SYMBOL(s3c64xx_device_iis0);
75		76
76	static struct resource s3c64xx_iis1_resource[] = {	77	static struct resource s3c64xx_iis1_resource[] = {
77	[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256),	78	[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256),
78	[1] = DEFINE_RES_DMA(DMACH_I2S1_OUT),	79	};
79	[2] = DEFINE_RES_DMA(DMACH_I2S1_IN),	80
		81	static struct s3c_audio_pdata i2s1_pdata = {
		82	.cfg_gpio = s3c64xx_i2s_cfg_gpio,
		83	.dma_filter = pl08x_filter_id,
		84	.dma_playback = DMACH_I2S1_OUT,
		85	.dma_capture = DMACH_I2S1_IN,
80	};	86	};
81		87
82	struct platform_device s3c64xx_device_iis1 = {	88	struct platform_device s3c64xx_device_iis1 = {
@@ -85,19 +91,20 @@ struct platform_device s3c64xx_device_iis1 = { · 2 unmodified lines
85	.num_resources = ARRAY_SIZE(s3c64xx_iis1_resource),	91	.num_resources = ARRAY_SIZE(s3c64xx_iis1_resource),
86	.resource = s3c64xx_iis1_resource,	92	.resource = s3c64xx_iis1_resource,
87	.dev = {	93	.dev = {
88	.platform_data = &i2sv3_pdata,	94	.platform_data = &i2s1_pdata,
89	},	95	},
90	};	96	};
91	EXPORT_SYMBOL(s3c64xx_device_iis1);	97	EXPORT_SYMBOL(s3c64xx_device_iis1);
92		98
93	static struct resource s3c64xx_iisv4_resource[] = {	99	static struct resource s3c64xx_iisv4_resource[] = {
94	[0] = DEFINE_RES_MEM(S3C64XX_PA_IISV4, SZ_256),	100	[0] = DEFINE_RES_MEM(S3C64XX_PA_IISV4, SZ_256),
95	[1] = DEFINE_RES_DMA(DMACH_HSI_I2SV40_TX),
96	[2] = DEFINE_RES_DMA(DMACH_HSI_I2SV40_RX),
97	};	101	};
98		102
99	static struct s3c_audio_pdata i2sv4_pdata = {	103	static struct s3c_audio_pdata i2sv4_pdata = {
100	.cfg_gpio = s3c64xx_i2s_cfg_gpio,	104	.cfg_gpio = s3c64xx_i2s_cfg_gpio,
		105	.dma_filter = pl08x_filter_id,
		106	.dma_playback = DMACH_HSI_I2SV40_TX,
		107	.dma_capture = DMACH_HSI_I2SV40_RX,
101	.type = {	108	.type = {
102	.i2s = {	109	.i2s = {
103	.quirks = QUIRK_PRI_6CHAN,	110	.quirks = QUIRK_PRI_6CHAN,
@@ -142,12 +149,13 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) · 38 unmodified lines
142		149
143	static struct resource s3c64xx_pcm0_resource[] = {	150	static struct resource s3c64xx_pcm0_resource[] = {
144	[0] = DEFINE_RES_MEM(S3C64XX_PA_PCM0, SZ_256),	151	[0] = DEFINE_RES_MEM(S3C64XX_PA_PCM0, SZ_256),
145	[1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
146	[2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
147	};	152	};
148		153
149	static struct s3c_audio_pdata s3c_pcm0_pdata = {	154	static struct s3c_audio_pdata s3c_pcm0_pdata = {
150	.cfg_gpio = s3c64xx_pcm_cfg_gpio,	155	.cfg_gpio = s3c64xx_pcm_cfg_gpio,
		156	.dma_filter = pl08x_filter_id,
		157	.dma_capture = DMACH_PCM0_RX,
		158	.dma_playback = DMACH_PCM0_TX,
151	};	159	};
152		160
153	struct platform_device s3c64xx_device_pcm0 = {	161	struct platform_device s3c64xx_device_pcm0 = {
@@ -163,12 +171,13 @@ EXPORT_SYMBOL(s3c64xx_device_pcm0); · 9 unmodified lines
163		171
164	static struct resource s3c64xx_pcm1_resource[] = {	172	static struct resource s3c64xx_pcm1_resource[] = {
165	[0] = DEFINE_RES_MEM(S3C64XX_PA_PCM1, SZ_256),	173	[0] = DEFINE_RES_MEM(S3C64XX_PA_PCM1, SZ_256),
166	[1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
167	[2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
168	};	174	};
169		175
170	static struct s3c_audio_pdata s3c_pcm1_pdata = {	176	static struct s3c_audio_pdata s3c_pcm1_pdata = {
171	.cfg_gpio = s3c64xx_pcm_cfg_gpio,	177	.cfg_gpio = s3c64xx_pcm_cfg_gpio,
		178	.dma_filter = pl08x_filter_id,
		179	.dma_playback = DMACH_PCM1_TX,
		180	.dma_capture = DMACH_PCM1_RX,
172	};	181	};
173		182
174	struct platform_device s3c64xx_device_pcm1 = {	183	struct platform_device s3c64xx_device_pcm1 = {
@@ -196,13 +205,15 @@ static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev) · 21 unmodified lines
196		205
197	static struct resource s3c64xx_ac97_resource[] = {	206	static struct resource s3c64xx_ac97_resource[] = {
198	[0] = DEFINE_RES_MEM(S3C64XX_PA_AC97, SZ_256),	207	[0] = DEFINE_RES_MEM(S3C64XX_PA_AC97, SZ_256),
199	[1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),	208	[1] = DEFINE_RES_IRQ(IRQ_AC97),
200	[2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
201	[3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
202	[4] = DEFINE_RES_IRQ(IRQ_AC97),
203	};	209	};
204		210
205	static struct s3c_audio_pdata s3c_ac97_pdata;	211	static struct s3c_audio_pdata s3c_ac97_pdata = {
		212	.dma_playback = DMACH_AC97_PCMOUT,
		213	.dma_filter = pl08x_filter_id,
		214	.dma_capture = DMACH_AC97_PCMIN,
		215	.dma_capture_mic = DMACH_AC97_MICIN,
		216	};
206		217
207	static u64 s3c64xx_ac97_dmamask = DMA_BIT_MASK(32);	218	static u64 s3c64xx_ac97_dmamask = DMA_BIT_MASK(32);
208		219

arch/arm/mach-s3c64xx/include/mach/dma.h+26−26

@@ -14,38 +14,38 @@ · 13 unmodified lines
14	#define S3C64XX_DMA_CHAN(name) ((unsigned long)(name))	14	#define S3C64XX_DMA_CHAN(name) ((unsigned long)(name))
15		15
16	/* DMA0/SDMA0 */	16	/* DMA0/SDMA0 */
17	#define DMACH_UART0 S3C64XX_DMA_CHAN("uart0_tx")	17	#define DMACH_UART0 "uart0_tx"
18	#define DMACH_UART0_SRC2 S3C64XX_DMA_CHAN("uart0_rx")	18	#define DMACH_UART0_SRC2 "uart0_rx"
19	#define DMACH_UART1 S3C64XX_DMA_CHAN("uart1_tx")	19	#define DMACH_UART1 "uart1_tx"
20	#define DMACH_UART1_SRC2 S3C64XX_DMA_CHAN("uart1_rx")	20	#define DMACH_UART1_SRC2 "uart1_rx"
21	#define DMACH_UART2 S3C64XX_DMA_CHAN("uart2_tx")	21	#define DMACH_UART2 "uart2_tx"
22	#define DMACH_UART2_SRC2 S3C64XX_DMA_CHAN("uart2_rx")	22	#define DMACH_UART2_SRC2 "uart2_rx"
23	#define DMACH_UART3 S3C64XX_DMA_CHAN("uart3_tx")	23	#define DMACH_UART3 "uart3_tx"
24	#define DMACH_UART3_SRC2 S3C64XX_DMA_CHAN("uart3_rx")	24	#define DMACH_UART3_SRC2 "uart3_rx"
25	#define DMACH_PCM0_TX S3C64XX_DMA_CHAN("pcm0_tx")	25	#define DMACH_PCM0_TX "pcm0_tx"
26	#define DMACH_PCM0_RX S3C64XX_DMA_CHAN("pcm0_rx")	26	#define DMACH_PCM0_RX "pcm0_rx"
27	#define DMACH_I2S0_OUT S3C64XX_DMA_CHAN("i2s0_tx")	27	#define DMACH_I2S0_OUT "i2s0_tx"
28	#define DMACH_I2S0_IN S3C64XX_DMA_CHAN("i2s0_rx")	28	#define DMACH_I2S0_IN "i2s0_rx"
29	#define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx")	29	#define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx")
30	#define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx")	30	#define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx")
31	#define DMACH_HSI_I2SV40_TX S3C64XX_DMA_CHAN("i2s2_tx")	31	#define DMACH_HSI_I2SV40_TX "i2s2_tx"
32	#define DMACH_HSI_I2SV40_RX S3C64XX_DMA_CHAN("i2s2_rx")	32	#define DMACH_HSI_I2SV40_RX "i2s2_rx"
33		33
34	/* DMA1/SDMA1 */	34	/* DMA1/SDMA1 */
35	#define DMACH_PCM1_TX S3C64XX_DMA_CHAN("pcm1_tx")	35	#define DMACH_PCM1_TX "pcm1_tx"
36	#define DMACH_PCM1_RX S3C64XX_DMA_CHAN("pcm1_rx")	36	#define DMACH_PCM1_RX "pcm1_rx"
37	#define DMACH_I2S1_OUT S3C64XX_DMA_CHAN("i2s1_tx")	37	#define DMACH_I2S1_OUT "i2s1_tx"
38	#define DMACH_I2S1_IN S3C64XX_DMA_CHAN("i2s1_rx")	38	#define DMACH_I2S1_IN "i2s1_rx"
39	#define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx")	39	#define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx")
40	#define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx")	40	#define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx")
41	#define DMACH_AC97_PCMOUT S3C64XX_DMA_CHAN("ac97_out")	41	#define DMACH_AC97_PCMOUT "ac97_out"
42	#define DMACH_AC97_PCMIN S3C64XX_DMA_CHAN("ac97_in")	42	#define DMACH_AC97_PCMIN "ac97_in"
43	#define DMACH_AC97_MICIN S3C64XX_DMA_CHAN("ac97_mic")	43	#define DMACH_AC97_MICIN "ac97_mic"
44	#define DMACH_PWM S3C64XX_DMA_CHAN("pwm")	44	#define DMACH_PWM "pwm"
45	#define DMACH_IRDA S3C64XX_DMA_CHAN("irda")	45	#define DMACH_IRDA "irda"
46	#define DMACH_EXTERNAL S3C64XX_DMA_CHAN("external")	46	#define DMACH_EXTERNAL "external"
47	#define DMACH_SECURITY_RX S3C64XX_DMA_CHAN("sec_rx")	47	#define DMACH_SECURITY_RX "sec_rx"
48	#define DMACH_SECURITY_TX S3C64XX_DMA_CHAN("sec_tx")	48	#define DMACH_SECURITY_TX "sec_tx"
49		49
50	enum dma_ch {	50	enum dma_ch {
51	DMACH_MAX = 32	51	DMACH_MAX = 32

arch/arm/plat-samsung/devs.c+20−3

@@ -65,6 +65,7 @@ · 64 unmodified lines
65	#include <linux/platform_data/usb-ohci-s3c2410.h>	65	#include <linux/platform_data/usb-ohci-s3c2410.h>
66	#include <plat/usb-phy.h>	66	#include <plat/usb-phy.h>
67	#include <plat/regs-spi.h>	67	#include <plat/regs-spi.h>
		68	#include <linux/platform_data/asoc-s3c.h>
68	#include <linux/platform_data/spi-s3c64xx.h>	69	#include <linux/platform_data/spi-s3c64xx.h>
69		70
70	static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);	71	static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
@@ -74,9 +75,15 @@ static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); · 3 unmodified lines
74	static struct resource s3c_ac97_resource[] = {	75	static struct resource s3c_ac97_resource[] = {
75	[0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),	76	[0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
76	[1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),	77	[1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
77	[2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),	78	};
78	[3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),	79
79	[4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),	80	static struct s3c_audio_pdata s3c_ac97_pdata = {
		81	#ifdef CONFIG_S3C24XX_DMAC
		82	.dma_filter = s3c24xx_dma_filter,
		83	#endif
		84	.dma_playback = (void *)DMACH_PCM_OUT,
		85	.dma_capture = (void *)DMACH_PCM_IN,
		86	.dma_capture_mic = (void *)DMACH_MIC_IN,
80	};	87	};
81		88
82	struct platform_device s3c_device_ac97 = {	89	struct platform_device s3c_device_ac97 = {
@@ -87,6 +94,7 @@ struct platform_device s3c_device_ac97 = { · 4 unmodified lines
87	.dev = {	94	.dev = {
88	.dma_mask = &samsung_device_dma_mask,	95	.dma_mask = &samsung_device_dma_mask,
89	.coherent_dma_mask = DMA_BIT_MASK(32),	96	.coherent_dma_mask = DMA_BIT_MASK(32),
		97	.platform_data = &s3c_ac97_pdata,
90	}	98	}
91	};	99	};
92	#endif /* CONFIG_CPU_S3C2440 */	100	#endif /* CONFIG_CPU_S3C2440 */
@@ -566,6 +574,14 @@ static struct resource s3c_iis_resource[] = { · 473 unmodified lines
566	[0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),	574	[0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
567	};	575	};
568		576
		577	static struct s3c_audio_pdata s3c_iis_platdata = {
		578	#ifdef CONFIG_S3C24XX_DMAC
		579	.dma_filter = s3c24xx_dma_filter,
		580	#endif
		581	.dma_playback = (void *)DMACH_I2S_OUT,
		582	.dma_capture = (void *)DMACH_I2S_IN,
		583	};
		584
569	struct platform_device s3c_device_iis = {	585	struct platform_device s3c_device_iis = {
570	.name = "s3c24xx-iis",	586	.name = "s3c24xx-iis",
571	.id = -1,	587	.id = -1,
@@ -574,6 +590,7 @@ struct platform_device s3c_device_iis = { · 2 unmodified lines
574	.dev = {	590	.dev = {
575	.dma_mask = &samsung_device_dma_mask,	591	.dma_mask = &samsung_device_dma_mask,
576	.coherent_dma_mask = DMA_BIT_MASK(32),	592	.coherent_dma_mask = DMA_BIT_MASK(32),
		593	.platform_data = &s3c_iis_platdata,
577	}	594	}
578	};	595	};
579	#endif /* CONFIG_PLAT_S3C24XX */	596	#endif /* CONFIG_PLAT_S3C24XX */

arch/x86/include/asm/platform_sst_audio.h+1−0

@@ -55,6 +55,7 @@ enum sst_audio_device_id_mrfld { · 54 unmodified lines
55	PIPE_MEDIA0_IN = 0x8F,	55	PIPE_MEDIA0_IN = 0x8F,
56	PIPE_MEDIA1_IN = 0x90,	56	PIPE_MEDIA1_IN = 0x90,
57	PIPE_MEDIA2_IN = 0x91,	57	PIPE_MEDIA2_IN = 0x91,
		58	PIPE_MEDIA3_IN = 0x9C,
58	PIPE_RSVD = 0xFF,	59	PIPE_RSVD = 0xFF,
59	};	60	};
60		61

arch/x86/kernel/early-quirks.c+1−0

@@ -547,6 +547,7 @@ static const struct pci_device_id intel_stolen_ids[] __initconst = { · 546 unmodified lines
547	INTEL_CHV_IDS(&chv_stolen_funcs),	547	INTEL_CHV_IDS(&chv_stolen_funcs),
548	INTEL_SKL_IDS(&gen9_stolen_funcs),	548	INTEL_SKL_IDS(&gen9_stolen_funcs),
549	INTEL_BXT_IDS(&gen9_stolen_funcs),	549	INTEL_BXT_IDS(&gen9_stolen_funcs),
		550	INTEL_KBL_IDS(&gen9_stolen_funcs),
550	};	551	};
551		552
552	static void __init intel_graphics_stolen(int num, int slot, int func)	553	static void __init intel_graphics_stolen(int num, int slot, int func)

drivers/dma/Kconfig+1−1

@@ -444,7 +444,7 @@ config STM32_DMA · 443 unmodified lines
444	here.	444	here.
445		445
446	config S3C24XX_DMAC	446	config S3C24XX_DMAC
447	tristate "Samsung S3C24XX DMA support"	447	bool "Samsung S3C24XX DMA support"
448	depends on ARCH_S3C24XX	448	depends on ARCH_S3C24XX
449	select DMA_ENGINE	449	select DMA_ENGINE
450	select DMA_VIRTUAL_CHANNELS	450	select DMA_VIRTUAL_CHANNELS

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+2−2

@@ -518,7 +518,7 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { · 517 unmodified lines
518	int	518	int
519	amdgpu_framebuffer_init(struct drm_device *dev,	519	amdgpu_framebuffer_init(struct drm_device *dev,
520	struct amdgpu_framebuffer *rfb,	520	struct amdgpu_framebuffer *rfb,
521	struct drm_mode_fb_cmd2 *mode_cmd,	521	const struct drm_mode_fb_cmd2 *mode_cmd,
522	struct drm_gem_object *obj)	522	struct drm_gem_object *obj)
523	{	523	{
524	int ret;	524	int ret;
@@ -535,7 +535,7 @@ amdgpu_framebuffer_init(struct drm_device *dev, · 10 unmodified lines
535	static struct drm_framebuffer *	535	static struct drm_framebuffer *
536	amdgpu_user_framebuffer_create(struct drm_device *dev,	536	amdgpu_user_framebuffer_create(struct drm_device *dev,
537	struct drm_file *file_priv,	537	struct drm_file *file_priv,
538	struct drm_mode_fb_cmd2 *mode_cmd)	538	const struct drm_mode_fb_cmd2 *mode_cmd)
539	{	539	{
540	struct drm_gem_object *obj;	540	struct drm_gem_object *obj;
541	struct amdgpu_framebuffer *amdgpu_fb;	541	struct amdgpu_framebuffer *amdgpu_fb;

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c+0−1

@@ -45,7 +45,6 @@ · 44 unmodified lines
45	struct amdgpu_fbdev {	45	struct amdgpu_fbdev {
46	struct drm_fb_helper helper;	46	struct drm_fb_helper helper;
47	struct amdgpu_framebuffer rfb;	47	struct amdgpu_framebuffer rfb;
48	struct list_head fbdev_list;
49	struct amdgpu_device *adev;	48	struct amdgpu_device *adev;
50	};	49	};
51		50

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+1−1

@@ -556,7 +556,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, · 555 unmodified lines
556		556
557	int amdgpu_framebuffer_init(struct drm_device *dev,	557	int amdgpu_framebuffer_init(struct drm_device *dev,
558	struct amdgpu_framebuffer *rfb,	558	struct amdgpu_framebuffer *rfb,
559	struct drm_mode_fb_cmd2 *mode_cmd,	559	const struct drm_mode_fb_cmd2 *mode_cmd,
560	struct drm_gem_object *obj);	560	struct drm_gem_object *obj);
561		561
562	int amdgpufb_remove(struct drm_device dev, struct drm_framebuffer fb);	562	int amdgpufb_remove(struct drm_device dev, struct drm_framebuffer fb);

drivers/gpu/drm/armada/armada_fb.c+2−2

@@ -35,7 +35,7 @@ static const struct drm_framebuffer_funcs armada_fb_funcs = { · 34 unmodified lines
35	};	35	};
36		36
37	struct armada_framebuffer armada_framebuffer_create(struct drm_device dev,	37	struct armada_framebuffer armada_framebuffer_create(struct drm_device dev,
38	struct drm_mode_fb_cmd2 mode, struct armada_gem_object obj)	38	const struct drm_mode_fb_cmd2 mode, struct armada_gem_object obj)
39	{	39	{
40	struct armada_framebuffer *dfb;	40	struct armada_framebuffer *dfb;
41	uint8_t format, config;	41	uint8_t format, config;
@@ -101,7 +101,7 @@ struct armada_framebuffer armada_framebuffer_create(struct drm_device dev, · 59 unmodified lines
101	}	101	}
102		102
103	static struct drm_framebuffer armada_fb_create(struct drm_device dev,	103	static struct drm_framebuffer armada_fb_create(struct drm_device dev,
104	struct drm_file dfile, struct drm_mode_fb_cmd2 mode)	104	struct drm_file dfile, const struct drm_mode_fb_cmd2 mode)
105	{	105	{
106	struct armada_gem_object *obj;	106	struct armada_gem_object *obj;
107	struct armada_framebuffer *dfb;	107	struct armada_framebuffer *dfb;

drivers/gpu/drm/armada/armada_fb.h+1−1

@@ -19,6 +19,6 @@ struct armada_framebuffer { · 18 unmodified lines
19	#define drm_fb_obj(fb) drm_fb_to_armada_fb(fb)->obj	19	#define drm_fb_obj(fb) drm_fb_to_armada_fb(fb)->obj
20		20
21	struct armada_framebuffer armada_framebuffer_create(struct drm_device ,	21	struct armada_framebuffer armada_framebuffer_create(struct drm_device ,
22	struct drm_mode_fb_cmd2 , struct armada_gem_object );	22	const struct drm_mode_fb_cmd2 , struct armada_gem_object );
23		23
24	#endif	24	#endif

drivers/gpu/drm/ast/ast_drv.h+1−2

 struct ast_fbdev {
 	struct drm_fb_helper helper;
 	struct ast_framebuffer afb;
-	struct list_head fbdev_list;
 	void *sysram;
 	int size;
 	struct ttm_bo_kmap_obj mapping;
 int ast_framebuffer_init(struct drm_device *dev,
 			 struct ast_framebuffer *ast_fb,
-			 struct drm_mode_fb_cmd2 *mode_cmd,
+			 const struct drm_mode_fb_cmd2 *mode_cmd,
 			 struct drm_gem_object *obj);
 int ast_fbdev_init(struct drm_device *dev);

drivers/gpu/drm/ast/ast_fb.c+1−1

@@ -163,7 +163,7 @@ static struct fb_ops astfb_ops = { · 162 unmodified lines
163	};	163	};
164		164
165	static int astfb_create_object(struct ast_fbdev *afbdev,	165	static int astfb_create_object(struct ast_fbdev *afbdev,
166	struct drm_mode_fb_cmd2 *mode_cmd,	166	const struct drm_mode_fb_cmd2 *mode_cmd,
167	struct drm_gem_object **gobj_p)	167	struct drm_gem_object **gobj_p)
168	{	168	{
169	struct drm_device *dev = afbdev->helper.dev;	169	struct drm_device *dev = afbdev->helper.dev;

drivers/gpu/drm/ast/ast_main.c+2−2

@@ -309,7 +309,7 @@ static const struct drm_framebuffer_funcs ast_fb_funcs = { · 308 unmodified lines
309		309
310	int ast_framebuffer_init(struct drm_device *dev,	310	int ast_framebuffer_init(struct drm_device *dev,
311	struct ast_framebuffer *ast_fb,	311	struct ast_framebuffer *ast_fb,
312	struct drm_mode_fb_cmd2 *mode_cmd,	312	const struct drm_mode_fb_cmd2 *mode_cmd,
313	struct drm_gem_object *obj)	313	struct drm_gem_object *obj)
314	{	314	{
315	int ret;	315	int ret;
@@ -327,7 +327,7 @@ int ast_framebuffer_init(struct drm_device *dev, · 11 unmodified lines
327	static struct drm_framebuffer *	327	static struct drm_framebuffer *
328	ast_user_framebuffer_create(struct drm_device *dev,	328	ast_user_framebuffer_create(struct drm_device *dev,
329	struct drm_file *filp,	329	struct drm_file *filp,
330	struct drm_mode_fb_cmd2 *mode_cmd)	330	const struct drm_mode_fb_cmd2 *mode_cmd)
331	{	331	{
332	struct drm_gem_object *obj;	332	struct drm_gem_object *obj;
333	struct ast_framebuffer *ast_fb;	333	struct ast_framebuffer *ast_fb;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c+1−1

@@ -402,7 +402,7 @@ static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data) · 401 unmodified lines
402	}	402	}
403		403
404	static struct drm_framebuffer atmel_hlcdc_fb_create(struct drm_device dev,	404	static struct drm_framebuffer atmel_hlcdc_fb_create(struct drm_device dev,
405	struct drm_file file_priv, struct drm_mode_fb_cmd2 mode_cmd)	405	struct drm_file file_priv, const struct drm_mode_fb_cmd2 mode_cmd)
406	{	406	{
407	return drm_fb_cma_create(dev, file_priv, mode_cmd);	407	return drm_fb_cma_create(dev, file_priv, mode_cmd);
408	}	408	}

drivers/gpu/drm/bochs/bochs.h+1−1

@@ -149,7 +149,7 @@ int bochs_dumb_mmap_offset(struct drm_file file, struct drm_device dev, · 148 unmodified lines
149		149
150	int bochs_framebuffer_init(struct drm_device *dev,	150	int bochs_framebuffer_init(struct drm_device *dev,
151	struct bochs_framebuffer *gfb,	151	struct bochs_framebuffer *gfb,
152	struct drm_mode_fb_cmd2 *mode_cmd,	152	const struct drm_mode_fb_cmd2 *mode_cmd,
153	struct drm_gem_object *obj);	153	struct drm_gem_object *obj);
154	int bochs_bo_pin(struct bochs_bo bo, u32 pl_flag, u64 gpu_addr);	154	int bochs_bo_pin(struct bochs_bo bo, u32 pl_flag, u64 gpu_addr);
155	int bochs_bo_unpin(struct bochs_bo *bo);	155	int bochs_bo_unpin(struct bochs_bo *bo);

drivers/gpu/drm/bochs/bochs_fbdev.c+1−1

@@ -34,7 +34,7 @@ static struct fb_ops bochsfb_ops = { · 33 unmodified lines
34	};	34	};
35		35
36	static int bochsfb_create_object(struct bochs_device *bochs,	36	static int bochsfb_create_object(struct bochs_device *bochs,
37	struct drm_mode_fb_cmd2 *mode_cmd,	37	const struct drm_mode_fb_cmd2 *mode_cmd,
38	struct drm_gem_object **gobj_p)	38	struct drm_gem_object **gobj_p)
39	{	39	{
40	struct drm_device *dev = bochs->dev;	40	struct drm_device *dev = bochs->dev;

drivers/gpu/drm/bochs/bochs_mm.c+2−2

@@ -484,7 +484,7 @@ static const struct drm_framebuffer_funcs bochs_fb_funcs = { · 483 unmodified lines
484		484
485	int bochs_framebuffer_init(struct drm_device *dev,	485	int bochs_framebuffer_init(struct drm_device *dev,
486	struct bochs_framebuffer *gfb,	486	struct bochs_framebuffer *gfb,
487	struct drm_mode_fb_cmd2 *mode_cmd,	487	const struct drm_mode_fb_cmd2 *mode_cmd,
488	struct drm_gem_object *obj)	488	struct drm_gem_object *obj)
489	{	489	{
490	int ret;	490	int ret;
@@ -502,7 +502,7 @@ int bochs_framebuffer_init(struct drm_device *dev, · 11 unmodified lines
502	static struct drm_framebuffer *	502	static struct drm_framebuffer *
503	bochs_user_framebuffer_create(struct drm_device *dev,	503	bochs_user_framebuffer_create(struct drm_device *dev,
504	struct drm_file *filp,	504	struct drm_file *filp,
505	struct drm_mode_fb_cmd2 *mode_cmd)	505	const struct drm_mode_fb_cmd2 *mode_cmd)
506	{	506	{
507	struct drm_gem_object *obj;	507	struct drm_gem_object *obj;
508	struct bochs_framebuffer *bochs_fb;	508	struct bochs_framebuffer *bochs_fb;

drivers/gpu/drm/cirrus/cirrus_drv.h+1−2

 struct cirrus_fbdev {
 	struct drm_fb_helper helper;
 	struct cirrus_framebuffer gfb;
-	struct list_head fbdev_list;
 	void *sysram;
 	int size;
 	int x1, y1, x2, y2; /* dirty rect */
 int cirrus_framebuffer_init(struct drm_device *dev,
 			   struct cirrus_framebuffer *gfb,
-			    struct drm_mode_fb_cmd2 *mode_cmd,
+			    const struct drm_mode_fb_cmd2 *mode_cmd,
 			    struct drm_gem_object *obj);
 bool cirrus_check_framebuffer(struct cirrus_device *cdev, int width, int height,

drivers/gpu/drm/cirrus/cirrus_fbdev.c+1−1

@@ -135,7 +135,7 @@ static struct fb_ops cirrusfb_ops = { · 134 unmodified lines
135	};	135	};
136		136
137	static int cirrusfb_create_object(struct cirrus_fbdev *afbdev,	137	static int cirrusfb_create_object(struct cirrus_fbdev *afbdev,
138	struct drm_mode_fb_cmd2 *mode_cmd,	138	const struct drm_mode_fb_cmd2 *mode_cmd,
139	struct drm_gem_object **gobj_p)	139	struct drm_gem_object **gobj_p)
140	{	140	{
141	struct drm_device *dev = afbdev->helper.dev;	141	struct drm_device *dev = afbdev->helper.dev;

drivers/gpu/drm/cirrus/cirrus_main.c+2−2

@@ -29,7 +29,7 @@ static const struct drm_framebuffer_funcs cirrus_fb_funcs = { · 28 unmodified lines
29		29
30	int cirrus_framebuffer_init(struct drm_device *dev,	30	int cirrus_framebuffer_init(struct drm_device *dev,
31	struct cirrus_framebuffer *gfb,	31	struct cirrus_framebuffer *gfb,
32	struct drm_mode_fb_cmd2 *mode_cmd,	32	const struct drm_mode_fb_cmd2 *mode_cmd,
33	struct drm_gem_object *obj)	33	struct drm_gem_object *obj)
34	{	34	{
35	int ret;	35	int ret;
@@ -47,7 +47,7 @@ int cirrus_framebuffer_init(struct drm_device *dev, · 11 unmodified lines
47	static struct drm_framebuffer *	47	static struct drm_framebuffer *
48	cirrus_user_framebuffer_create(struct drm_device *dev,	48	cirrus_user_framebuffer_create(struct drm_device *dev,
49	struct drm_file *filp,	49	struct drm_file *filp,
50	struct drm_mode_fb_cmd2 *mode_cmd)	50	const struct drm_mode_fb_cmd2 *mode_cmd)
51	{	51	{
52	struct cirrus_device *cdev = dev->dev_private;	52	struct cirrus_device *cdev = dev->dev_private;
53	struct drm_gem_object *obj;	53	struct drm_gem_object *obj;

drivers/gpu/drm/drm_atomic.c+5−13

 	if (mode && memcmp(&state->mode, mode, sizeof(*mode)) == 0)
 		return 0;
-	if (state->mode_blob)
+	drm_property_unreference_blob(state->mode_blob);
-		drm_property_unreference_blob(state->mode_blob);
 	state->mode_blob = NULL;
 	if (mode) {
 	if (blob == state->mode_blob)
 		return 0;
-	if (state->mode_blob)
+	drm_property_unreference_blob(state->mode_blob);
-		drm_property_unreference_blob(state->mode_blob);
 	state->mode_blob = NULL;
 	if (blob) {
 		struct drm_property_blob *mode =
 			drm_property_lookup_blob(dev, val);
 		ret = drm_atomic_set_mode_prop_for_crtc(state, mode);
-		if (mode)
+		drm_property_unreference_blob(mode);
-			drm_property_unreference_blob(mode);
 		return ret;
 	}
 	else if (crtc->funcs->atomic_set_property)
 retry:
 	drm_modeset_backoff(state->acquire_ctx);
-	ret = drm_modeset_lock(&state->dev->mode_config.connection_mutex,
+	ret = drm_modeset_lock_all_ctx(state->dev, state->acquire_ctx);
-			       state->acquire_ctx);
-	if (ret)
-		goto retry;
-	ret = drm_modeset_lock_all_crtcs(state->dev,
-					 state->acquire_ctx);
 	if (ret)
 		goto retry;
 }
 }
 /**
- * drm_atomic_update_old_fb -- Unset old_fb pointers and set plane->fb pointers.
+ * drm_atomic_clean_old_fb -- Unset old_fb pointers and set plane->fb pointers.
  *
  * @dev: drm device to check.
  * @plane_mask: plane mask for planes that were updated.

drivers/gpu/drm/drm_atomic_helper.c+241−11

@@ -80,6 +80,27 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state *state, · 79 unmodified lines
80	}	80	}
81	}	81	}
82		82
		83	static bool
		84	check_pending_encoder_assignment(struct drm_atomic_state *state,
		85	struct drm_encoder *new_encoder,
		86	struct drm_connector *new_connector)
		87	{
		88	struct drm_connector *connector;
		89	struct drm_connector_state *conn_state;
		90	int i;
		91
		92	for_each_connector_in_state(state, connector, conn_state, i) {
		93	if (conn_state->best_encoder != new_encoder)
		94	continue;
		95
		96	/* encoder already assigned and we're trying to re-steal it! */
		97	if (connector->state->best_encoder != conn_state->best_encoder)
		98	return false;
		99	}
		100
		101	return true;
		102	}
		103
83	static struct drm_crtc *	104	static struct drm_crtc *
84	get_current_crtc_for_encoder(struct drm_device *dev,	105	get_current_crtc_for_encoder(struct drm_device *dev,
85	struct drm_encoder *encoder)	106	struct drm_encoder *encoder)
@@ -229,6 +250,13 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx) · 143 unmodified lines
229	return 0;	250	return 0;
230	}	251	}
231		252
		253	if (!check_pending_encoder_assignment(state, new_encoder, connector)) {
		254	DRM_DEBUG_ATOMIC("Encoder for [CONNECTOR:%d:%s] already assigned\n",
		255	connector->base.id,
		256	connector->name);
		257	return -EINVAL;
		258	}
		259
232	encoder_crtc = get_current_crtc_for_encoder(state->dev,	260	encoder_crtc = get_current_crtc_for_encoder(state->dev,
233	new_encoder);	261	new_encoder);
234		262
@@ -1341,6 +1369,49 @@ drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state) · 1106 unmodified lines
1341	}	1369	}
1342	EXPORT_SYMBOL(drm_atomic_helper_commit_planes_on_crtc);	1370	EXPORT_SYMBOL(drm_atomic_helper_commit_planes_on_crtc);
1343		1371
		1372	/**
		1373	* drm_atomic_helper_disable_planes_on_crtc - helper to disable CRTC's planes
		1374	* @crtc: CRTC
		1375	* @atomic: if set, synchronize with CRTC's atomic_begin/flush hooks
		1376	*
		1377	* Disables all planes associated with the given CRTC. This can be
		1378	* used for instance in the CRTC helper disable callback to disable
		1379	* all planes before shutting down the display pipeline.
		1380	*
		1381	* If the atomic-parameter is set the function calls the CRTC's
		1382	* atomic_begin hook before and atomic_flush hook after disabling the
		1383	* planes.
		1384	*
		1385	* It is a bug to call this function without having implemented the
		1386	* ->atomic_disable() plane hook.
		1387	*/
		1388	void drm_atomic_helper_disable_planes_on_crtc(struct drm_crtc *crtc,
		1389	bool atomic)
		1390	{
		1391	const struct drm_crtc_helper_funcs *crtc_funcs =
		1392	crtc->helper_private;
		1393	struct drm_plane *plane;
		1394
		1395	if (atomic && crtc_funcs && crtc_funcs->atomic_begin)
		1396	crtc_funcs->atomic_begin(crtc, NULL);
		1397
		1398	drm_for_each_plane(plane, crtc->dev) {
		1399	const struct drm_plane_helper_funcs *plane_funcs =
		1400	plane->helper_private;
		1401
		1402	if (plane->state->crtc != crtc \|\| !plane_funcs)
		1403	continue;
		1404
		1405	WARN_ON(!plane_funcs->atomic_disable);
		1406	if (plane_funcs->atomic_disable)
		1407	plane_funcs->atomic_disable(plane, NULL);
		1408	}
		1409
		1410	if (atomic && crtc_funcs && crtc_funcs->atomic_flush)
		1411	crtc_funcs->atomic_flush(crtc, NULL);
		1412	}
		1413	EXPORT_SYMBOL(drm_atomic_helper_disable_planes_on_crtc);
		1414
1344	/**	1415	/**
1345	* drm_atomic_helper_cleanup_planes - cleanup plane resources after commit	1416	* drm_atomic_helper_cleanup_planes - cleanup plane resources after commit
1346	* @dev: DRM device	1417	* @dev: DRM device
@@ -1485,12 +1556,12 @@ retry: · 138 unmodified lines
1485	drm_atomic_set_fb_for_plane(plane_state, fb);	1556	drm_atomic_set_fb_for_plane(plane_state, fb);
1486	plane_state->crtc_x = crtc_x;	1557	plane_state->crtc_x = crtc_x;
1487	plane_state->crtc_y = crtc_y;	1558	plane_state->crtc_y = crtc_y;
1488	plane_state->crtc_h = crtc_h;
1489	plane_state->crtc_w = crtc_w;	1559	plane_state->crtc_w = crtc_w;
		1560	plane_state->crtc_h = crtc_h;
1490	plane_state->src_x = src_x;	1561	plane_state->src_x = src_x;
1491	plane_state->src_y = src_y;	1562	plane_state->src_y = src_y;
1492	plane_state->src_h = src_h;
1493	plane_state->src_w = src_w;	1563	plane_state->src_w = src_w;
		1564	plane_state->src_h = src_h;
1494		1565
1495	if (plane == crtc->cursor)	1566	if (plane == crtc->cursor)
1496	state->legacy_cursor_update = true;	1567	state->legacy_cursor_update = true;
@@ -1609,12 +1680,12 @@ int __drm_atomic_helper_disable_plane(struct drm_plane *plane, · 112 unmodified lines
1609	drm_atomic_set_fb_for_plane(plane_state, NULL);	1680	drm_atomic_set_fb_for_plane(plane_state, NULL);
1610	plane_state->crtc_x = 0;	1681	plane_state->crtc_x = 0;
1611	plane_state->crtc_y = 0;	1682	plane_state->crtc_y = 0;
1612	plane_state->crtc_h = 0;
1613	plane_state->crtc_w = 0;	1683	plane_state->crtc_w = 0;
		1684	plane_state->crtc_h = 0;
1614	plane_state->src_x = 0;	1685	plane_state->src_x = 0;
1615	plane_state->src_y = 0;	1686	plane_state->src_y = 0;
1616	plane_state->src_h = 0;
1617	plane_state->src_w = 0;	1687	plane_state->src_w = 0;
		1688	plane_state->src_h = 0;
1618		1689
1619	return 0;	1690	return 0;
1620	}	1691	}
@@ -1797,16 +1868,16 @@ int __drm_atomic_helper_set_config(struct drm_mode_set *set, · 176 unmodified lines
1797	drm_atomic_set_fb_for_plane(primary_state, set->fb);	1868	drm_atomic_set_fb_for_plane(primary_state, set->fb);
1798	primary_state->crtc_x = 0;	1869	primary_state->crtc_x = 0;
1799	primary_state->crtc_y = 0;	1870	primary_state->crtc_y = 0;
1800	primary_state->crtc_h = vdisplay;
1801	primary_state->crtc_w = hdisplay;	1871	primary_state->crtc_w = hdisplay;
		1872	primary_state->crtc_h = vdisplay;
1802	primary_state->src_x = set->x << 16;	1873	primary_state->src_x = set->x << 16;
1803	primary_state->src_y = set->y << 16;	1874	primary_state->src_y = set->y << 16;
1804	if (primary_state->rotation & (BIT(DRM_ROTATE_90) \| BIT(DRM_ROTATE_270))) {	1875	if (primary_state->rotation & (BIT(DRM_ROTATE_90) \| BIT(DRM_ROTATE_270))) {
1805	primary_state->src_h = hdisplay << 16;
1806	primary_state->src_w = vdisplay << 16;	1876	primary_state->src_w = vdisplay << 16;
		1877	primary_state->src_h = hdisplay << 16;
1807	} else {	1878	} else {
1808	primary_state->src_h = vdisplay << 16;
1809	primary_state->src_w = hdisplay << 16;	1879	primary_state->src_w = hdisplay << 16;
		1880	primary_state->src_h = vdisplay << 16;
1810	}	1881	}
1811		1882
1812	commit:	1883	commit:
@@ -1817,6 +1888,161 @@ commit: · 4 unmodified lines
1817	return 0;	1888	return 0;
1818	}	1889	}
1819		1890
		1891	/**
		1892	* drm_atomic_helper_disable_all - disable all currently active outputs
		1893	* @dev: DRM device
		1894	* @ctx: lock acquisition context
		1895	*
		1896	* Loops through all connectors, finding those that aren't turned off and then
		1897	* turns them off by setting their DPMS mode to OFF and deactivating the CRTC
		1898	* that they are connected to.
		1899	*
		1900	* This is used for example in suspend/resume to disable all currently active
		1901	* functions when suspending.
		1902	*
		1903	* Note that if callers haven't already acquired all modeset locks this might
		1904	* return -EDEADLK, which must be handled by calling drm_modeset_backoff().
		1905	*
		1906	* Returns:
		1907	* 0 on success or a negative error code on failure.
		1908	*
		1909	* See also:
		1910	* drm_atomic_helper_suspend(), drm_atomic_helper_resume()
		1911	*/
		1912	int drm_atomic_helper_disable_all(struct drm_device *dev,
		1913	struct drm_modeset_acquire_ctx *ctx)
		1914	{
		1915	struct drm_atomic_state *state;
		1916	struct drm_connector *conn;
		1917	int err;
		1918
		1919	state = drm_atomic_state_alloc(dev);
		1920	if (!state)
		1921	return -ENOMEM;
		1922
		1923	state->acquire_ctx = ctx;
		1924
		1925	drm_for_each_connector(conn, dev) {
		1926	struct drm_crtc *crtc = conn->state->crtc;
		1927	struct drm_crtc_state *crtc_state;
		1928
		1929	if (!crtc \|\| conn->dpms != DRM_MODE_DPMS_ON)
		1930	continue;
		1931
		1932	crtc_state = drm_atomic_get_crtc_state(state, crtc);
		1933	if (IS_ERR(crtc_state)) {
		1934	err = PTR_ERR(crtc_state);
		1935	goto free;
		1936	}
		1937
		1938	crtc_state->active = false;
		1939	}
		1940
		1941	err = drm_atomic_commit(state);
		1942
		1943	free:
		1944	if (err < 0)
		1945	drm_atomic_state_free(state);
		1946
		1947	return err;
		1948	}
		1949	EXPORT_SYMBOL(drm_atomic_helper_disable_all);
		1950
		1951	/**
		1952	* drm_atomic_helper_suspend - subsystem-level suspend helper
		1953	* @dev: DRM device
		1954	*
		1955	* Duplicates the current atomic state, disables all active outputs and then
		1956	* returns a pointer to the original atomic state to the caller. Drivers can
		1957	* pass this pointer to the drm_atomic_helper_resume() helper upon resume to
		1958	* restore the output configuration that was active at the time the system
		1959	* entered suspend.
		1960	*
		1961	* Note that it is potentially unsafe to use this. The atomic state object
		1962	* returned by this function is assumed to be persistent. Drivers must ensure
		1963	* that this holds true. Before calling this function, drivers must make sure
		1964	* to suspend fbdev emulation so that nothing can be using the device.
		1965	*
		1966	* Returns:
		1967	* A pointer to a copy of the state before suspend on success or an ERR_PTR()-
		1968	* encoded error code on failure. Drivers should store the returned atomic
		1969	* state object and pass it to the drm_atomic_helper_resume() helper upon
		1970	* resume.
		1971	*
		1972	* See also:
		1973	* drm_atomic_helper_duplicate_state(), drm_atomic_helper_disable_all(),
		1974	* drm_atomic_helper_resume()
		1975	*/
		1976	struct drm_atomic_state drm_atomic_helper_suspend(struct drm_device dev)
		1977	{
		1978	struct drm_modeset_acquire_ctx ctx;
		1979	struct drm_atomic_state *state;
		1980	int err;
		1981
		1982	drm_modeset_acquire_init(&ctx, 0);
		1983
		1984	retry:
		1985	err = drm_modeset_lock_all_ctx(dev, &ctx);
		1986	if (err < 0) {
		1987	state = ERR_PTR(err);
		1988	goto unlock;
		1989	}
		1990
		1991	state = drm_atomic_helper_duplicate_state(dev, &ctx);
		1992	if (IS_ERR(state))
		1993	goto unlock;
		1994
		1995	err = drm_atomic_helper_disable_all(dev, &ctx);
		1996	if (err < 0) {
		1997	drm_atomic_state_free(state);
		1998	state = ERR_PTR(err);
		1999	goto unlock;
		2000	}
		2001
		2002	unlock:
		2003	if (PTR_ERR(state) == -EDEADLK) {
		2004	drm_modeset_backoff(&ctx);
		2005	goto retry;
		2006	}
		2007
		2008	drm_modeset_drop_locks(&ctx);
		2009	drm_modeset_acquire_fini(&ctx);
		2010	return state;
		2011	}
		2012	EXPORT_SYMBOL(drm_atomic_helper_suspend);
		2013
		2014	/**
		2015	* drm_atomic_helper_resume - subsystem-level resume helper
		2016	* @dev: DRM device
		2017	* @state: atomic state to resume to
		2018	*
		2019	* Calls drm_mode_config_reset() to synchronize hardware and software states,
		2020	* grabs all modeset locks and commits the atomic state object. This can be
		2021	* used in conjunction with the drm_atomic_helper_suspend() helper to
		2022	* implement suspend/resume for drivers that support atomic mode-setting.
		2023	*
		2024	* Returns:
		2025	* 0 on success or a negative error code on failure.
		2026	*
		2027	* See also:
		2028	* drm_atomic_helper_suspend()
		2029	*/
		2030	int drm_atomic_helper_resume(struct drm_device *dev,
		2031	struct drm_atomic_state *state)
		2032	{
		2033	struct drm_mode_config *config = &dev->mode_config;
		2034	int err;
		2035
		2036	drm_mode_config_reset(dev);
		2037	drm_modeset_lock_all(dev);
		2038	state->acquire_ctx = config->acquire_ctx;
		2039	err = drm_atomic_commit(state);
		2040	drm_modeset_unlock_all(dev);
		2041
		2042	return err;
		2043	}
		2044	EXPORT_SYMBOL(drm_atomic_helper_resume);
		2045
1820	/**	2046	/**
1821	* drm_atomic_helper_crtc_set_property - helper for crtc properties	2047	* drm_atomic_helper_crtc_set_property - helper for crtc properties
1822	* @crtc: DRM crtc	2048	* @crtc: DRM crtc
@@ -2184,7 +2410,7 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_dpms); · 361 unmodified lines
2184	*/	2410	*/
2185	void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc)	2411	void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc)
2186	{	2412	{
2187	if (crtc->state && crtc->state->mode_blob)	2413	if (crtc->state)
2188	drm_property_unreference_blob(crtc->state->mode_blob);	2414	drm_property_unreference_blob(crtc->state->mode_blob);
2189	kfree(crtc->state);	2415	kfree(crtc->state);
2190	crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL);	2416	crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL);
@@ -2252,8 +2478,7 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_duplicate_state); · 61 unmodified lines
2252	void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,	2478	void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
2253	struct drm_crtc_state *state)	2479	struct drm_crtc_state *state)
2254	{	2480	{
2255	if (state->mode_blob)	2481	drm_property_unreference_blob(state->mode_blob);
2256	drm_property_unreference_blob(state->mode_blob);
2257	}	2482	}
2258	EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);	2483	EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
2259		2484
@@ -2430,7 +2655,9 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_duplicate_state); · 170 unmodified lines
2430	* @ctx: lock acquisition context	2655	* @ctx: lock acquisition context
2431	*	2656	*
2432	* Makes a copy of the current atomic state by looping over all objects and	2657	* Makes a copy of the current atomic state by looping over all objects and
2433	* duplicating their respective states.	2658	* duplicating their respective states. This is used for example by suspend/
		2659	* resume support code to save the state prior to suspend such that it can
		2660	* be restored upon resume.
2434	*	2661	*
2435	* Note that this treats atomic state as persistent between save and restore.	2662	* Note that this treats atomic state as persistent between save and restore.
2436	* Drivers must make sure that this is possible and won't result in confusion	2663	* Drivers must make sure that this is possible and won't result in confusion
@@ -2442,6 +2669,9 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_duplicate_state); · 5 unmodified lines
2442	* Returns:	2669	* Returns:
2443	* A pointer to the copy of the atomic state object on success or an	2670	* A pointer to the copy of the atomic state object on success or an
2444	* ERR_PTR()-encoded error code on failure.	2671	* ERR_PTR()-encoded error code on failure.
		2672	*
		2673	* See also:
		2674	* drm_atomic_helper_suspend(), drm_atomic_helper_resume()
2445	*/	2675	*/
2446	struct drm_atomic_state *	2676	struct drm_atomic_state *
2447	drm_atomic_helper_duplicate_state(struct drm_device *dev,	2677	drm_atomic_helper_duplicate_state(struct drm_device *dev,

drivers/gpu/drm/drm_crtc.c+2−2

@@ -45,7 +45,7 @@ · 44 unmodified lines
45		45
46	static struct drm_framebuffer *	46	static struct drm_framebuffer *
47	internal_framebuffer_create(struct drm_device *dev,	47	internal_framebuffer_create(struct drm_device *dev,
48	struct drm_mode_fb_cmd2 *r,	48	const struct drm_mode_fb_cmd2 *r,
49	struct drm_file *file_priv);	49	struct drm_file *file_priv);
50		50
51	/* Avoid boilerplate. I'm tired of typing. */	51	/* Avoid boilerplate. I'm tired of typing. */
@@ -3235,7 +3235,7 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) · 3183 unmodified lines
3235		3235
3236	static struct drm_framebuffer *	3236	static struct drm_framebuffer *
3237	internal_framebuffer_create(struct drm_device *dev,	3237	internal_framebuffer_create(struct drm_device *dev,
3238	struct drm_mode_fb_cmd2 *r,	3238	const struct drm_mode_fb_cmd2 *r,
3239	struct drm_file *file_priv)	3239	struct drm_file *file_priv)
3240	{	3240	{
3241	struct drm_mode_config *config = &dev->mode_config;	3241	struct drm_mode_config *config = &dev->mode_config;

drivers/gpu/drm/drm_crtc_helper.c+7−1

  * metadata fields.
  */
 void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
-				    struct drm_mode_fb_cmd2 *mode_cmd)
+				    const struct drm_mode_fb_cmd2 *mode_cmd)
 {
 	int i;
  * due to slight differences in allocating shared resources when the
  * configuration is restored in a different order than when userspace set it up)
  * need to use their own restore logic.
+ *
+ * This function is deprecated. New drivers should implement atomic mode-
+ * setting and use the atomic suspend/resume helpers.
+ *
+ * See also:
+ * drm_atomic_helper_suspend(), drm_atomic_helper_resume()
  */
 void drm_helper_resume_force_mode(struct drm_device *dev)
 {

drivers/gpu/drm/drm_edid.c+60−2

@@ -2545,6 +2545,33 @@ cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) · 2544 unmodified lines
2545	return clock;	2545	return clock;
2546	}	2546	}
2547		2547
		2548	static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
		2549	unsigned int clock_tolerance)
		2550	{
		2551	u8 mode;
		2552
		2553	if (!to_match->clock)
		2554	return 0;
		2555
		2556	for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
		2557	const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
		2558	unsigned int clock1, clock2;
		2559
		2560	/* Check both 60Hz and 59.94Hz */
		2561	clock1 = cea_mode->clock;
		2562	clock2 = cea_mode_alternate_clock(cea_mode);
		2563
		2564	if (abs(to_match->clock - clock1) > clock_tolerance &&
		2565	abs(to_match->clock - clock2) > clock_tolerance)
		2566	continue;
		2567
		2568	if (drm_mode_equal_no_clocks(to_match, cea_mode))
		2569	return mode + 1;
		2570	}
		2571
		2572	return 0;
		2573	}
		2574
2548	/**	2575	/**
2549	* drm_match_cea_mode - look for a CEA mode matching given mode	2576	* drm_match_cea_mode - look for a CEA mode matching given mode
2550	* @to_match: display mode	2577	* @to_match: display mode
@@ -2609,6 +2636,33 @@ hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) · 58 unmodified lines
2609	return cea_mode_alternate_clock(hdmi_mode);	2636	return cea_mode_alternate_clock(hdmi_mode);
2610	}	2637	}
2611		2638
		2639	static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
		2640	unsigned int clock_tolerance)
		2641	{
		2642	u8 mode;
		2643
		2644	if (!to_match->clock)
		2645	return 0;
		2646
		2647	for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
		2648	const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
		2649	unsigned int clock1, clock2;
		2650
		2651	/* Make sure to also match alternate clocks */
		2652	clock1 = hdmi_mode->clock;
		2653	clock2 = hdmi_mode_alternate_clock(hdmi_mode);
		2654
		2655	if (abs(to_match->clock - clock1) > clock_tolerance &&
		2656	abs(to_match->clock - clock2) > clock_tolerance)
		2657	continue;
		2658
		2659	if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
		2660	return mode + 1;
		2661	}
		2662
		2663	return 0;
		2664	}
		2665
2612	/*	2666	/*
2613	* drm_match_hdmi_mode - look for a HDMI mode matching given mode	2667	* drm_match_hdmi_mode - look for a HDMI mode matching given mode
2614	* @to_match: display mode	2668	* @to_match: display mode
@@ -3119,14 +3173,18 @@ static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) · 504 unmodified lines
3119	u8 mode_idx;	3173	u8 mode_idx;
3120	const char *type;	3174	const char *type;
3121		3175
3122	mode_idx = drm_match_cea_mode(mode) - 1;	3176	/*
		3177	* allow 5kHz clock difference either way to account for
		3178	* the 10kHz clock resolution limit of detailed timings.
		3179	*/
		3180	mode_idx = drm_match_cea_mode_clock_tolerance(mode, 5) - 1;
3123	if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {	3181	if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
3124	type = "CEA";	3182	type = "CEA";
3125	cea_mode = &edid_cea_modes[mode_idx];	3183	cea_mode = &edid_cea_modes[mode_idx];
3126	clock1 = cea_mode->clock;	3184	clock1 = cea_mode->clock;
3127	clock2 = cea_mode_alternate_clock(cea_mode);	3185	clock2 = cea_mode_alternate_clock(cea_mode);
3128	} else {	3186	} else {
3129	mode_idx = drm_match_hdmi_mode(mode) - 1;	3187	mode_idx = drm_match_hdmi_mode_clock_tolerance(mode, 5) - 1;
3130	if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {	3188	if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
3131	type = "HDMI";	3189	type = "HDMI";
3132	cea_mode = &edid_4k_modes[mode_idx];	3190	cea_mode = &edid_4k_modes[mode_idx];

drivers/gpu/drm/drm_fb_cma_helper.c+2−2

@@ -74,7 +74,7 @@ static struct drm_framebuffer_funcs drm_fb_cma_funcs = { · 73 unmodified lines
74	};	74	};
75		75
76	static struct drm_fb_cma drm_fb_cma_alloc(struct drm_device dev,	76	static struct drm_fb_cma drm_fb_cma_alloc(struct drm_device dev,
77	struct drm_mode_fb_cmd2 mode_cmd, struct drm_gem_cma_object *obj,	77	const const struct drm_mode_fb_cmd2 mode_cmd, struct drm_gem_cma_object *obj,
78	unsigned int num_planes)	78	unsigned int num_planes)
79	{	79	{
80	struct drm_fb_cma *fb_cma;	80	struct drm_fb_cma *fb_cma;
@@ -107,7 +107,7 @@ static struct drm_fb_cma drm_fb_cma_alloc(struct drm_device dev, · 26 unmodified lines
107	* checked before calling this function.	107	* checked before calling this function.
108	*/	108	*/
109	struct drm_framebuffer drm_fb_cma_create(struct drm_device dev,	109	struct drm_framebuffer drm_fb_cma_create(struct drm_device dev,
110	struct drm_file file_priv, struct drm_mode_fb_cmd2 mode_cmd)	110	struct drm_file file_priv, const struct drm_mode_fb_cmd2 mode_cmd)
111	{	111	{
112	struct drm_fb_cma *fb_cma;	112	struct drm_fb_cma *fb_cma;
113	struct drm_gem_cma_object *objs[4];	113	struct drm_gem_cma_object *objs[4];

drivers/gpu/drm/drm_fops.c+37−21

@@ -226,6 +226,8 @@ static int drm_open_helper(struct file filp, struct drm_minor minor) · 225 unmodified lines
226	init_waitqueue_head(&priv->event_wait);	226	init_waitqueue_head(&priv->event_wait);
227	priv->event_space = 4096; /* set aside 4k for event buffer */	227	priv->event_space = 4096; /* set aside 4k for event buffer */
228		228
		229	mutex_init(&priv->event_read_lock);
		230
229	if (drm_core_check_feature(dev, DRIVER_GEM))	231	if (drm_core_check_feature(dev, DRIVER_GEM))
230	drm_gem_open(dev, priv);	232	drm_gem_open(dev, priv);
231		233
@@ -511,14 +513,28 @@ ssize_t drm_read(struct file filp, char __user buffer, · 279 unmodified lines
511	{	513	{
512	struct drm_file *file_priv = filp->private_data;	514	struct drm_file *file_priv = filp->private_data;
513	struct drm_device *dev = file_priv->minor->dev;	515	struct drm_device *dev = file_priv->minor->dev;
514	ssize_t ret = 0;	516	ssize_t ret;
515		517
516	if (!access_ok(VERIFY_WRITE, buffer, count))	518	if (!access_ok(VERIFY_WRITE, buffer, count))
517	return -EFAULT;	519	return -EFAULT;
518		520
519	spin_lock_irq(&dev->event_lock);	521	ret = mutex_lock_interruptible(&file_priv->event_read_lock);
		522	if (ret)
		523	return ret;
		524
520	for (;;) {	525	for (;;) {
521	if (list_empty(&file_priv->event_list)) {	526	struct drm_pending_event *e = NULL;
		527
		528	spin_lock_irq(&dev->event_lock);
		529	if (!list_empty(&file_priv->event_list)) {
		530	e = list_first_entry(&file_priv->event_list,
		531	struct drm_pending_event, link);
		532	file_priv->event_space += e->event->length;
		533	list_del(&e->link);
		534	}
		535	spin_unlock_irq(&dev->event_lock);
		536
		537	if (e == NULL) {
522	if (ret)	538	if (ret)
523	break;	539	break;
524		540
@@ -527,36 +543,36 @@ ssize_t drm_read(struct file filp, char __user buffer, · 2 unmodified lines
527	break;	543	break;
528	}	544	}
529		545
530	spin_unlock_irq(&dev->event_lock);	546	mutex_unlock(&file_priv->event_read_lock);
531	ret = wait_event_interruptible(file_priv->event_wait,	547	ret = wait_event_interruptible(file_priv->event_wait,
532	!list_empty(&file_priv->event_list));	548	!list_empty(&file_priv->event_list));
533	spin_lock_irq(&dev->event_lock);	549	if (ret >= 0)
534	if (ret < 0)	550	ret = mutex_lock_interruptible(&file_priv->event_read_lock);
535	break;	551	if (ret)
536		552	return ret;
537	ret = 0;
538	} else {	553	} else {
539	struct drm_pending_event *e;	554	unsigned length = e->event->length;
540		555
541	e = list_first_entry(&file_priv->event_list,	556	if (length > count - ret) {
542	struct drm_pending_event, link);	557	put_back_event:
543	if (e->event->length + ret > count)	558	spin_lock_irq(&dev->event_lock);
		559	file_priv->event_space -= length;
		560	list_add(&e->link, &file_priv->event_list);
		561	spin_unlock_irq(&dev->event_lock);
544	break;	562	break;
		563	}
545		564
546	if (__copy_to_user_inatomic(buffer + ret,	565	if (copy_to_user(buffer + ret, e->event, length)) {
547	e->event, e->event->length)) {
548	if (ret == 0)	566	if (ret == 0)
549	ret = -EFAULT;	567	ret = -EFAULT;
550	break;	568	goto put_back_event;
551	}	569	}
552		570
553	file_priv->event_space += e->event->length;	571	ret += length;
554	ret += e->event->length;
555	list_del(&e->link);
556	e->destroy(e);	572	e->destroy(e);
557	}	573	}
558	}	574	}
559	spin_unlock_irq(&dev->event_lock);	575	mutex_unlock(&file_priv->event_read_lock);
560		576
561	return ret;	577	return ret;
562	}	578	}

drivers/gpu/drm/drm_gem.c+32−3

  * @filp: drm file-private structure to use for the handle look up
  * @handle: userspace handle to delete
  *
- * Removes the GEM handle from the @filp lookup table and if this is the last
+ * Removes the GEM handle from the @filp lookup table which has been added with
- * handle also cleans up linked resources like GEM names.
+ * drm_gem_handle_create(). If this is the last handle also cleans up linked
+ * resources like GEM names.
  */
 int
 drm_gem_handle_delete(struct drm_file *filp, u32 handle)
  * This expects the dev->object_name_lock to be held already and will drop it
  * before returning. Used to avoid races in establishing new handles when
  * importing an object from either an flink name or a dma-buf.
+ *
+ * Handles must be release again through drm_gem_handle_delete(). This is done
+ * when userspace closes @file_priv for all attached handles, or through the
+ * GEM_CLOSE ioctl for individual handles.
  */
 int
 drm_gem_handle_create_tail(struct drm_file *file_priv,
 }
 EXPORT_SYMBOL(drm_gem_put_pages);
-/** Returns a reference to the object named by the handle. */
+/**
+ * drm_gem_object_lookup - look up a GEM object from it's handle
+ * @dev: DRM device
+ * @filp: DRM file private date
+ * @handle: userspace handle
+ *
+ * Returns:
+ *
+ * A reference to the object named by the handle if such exists on @filp, NULL
+ * otherwise.
+ */
 struct drm_gem_object *
 drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp,
 		      u32 handle)
 }
 EXPORT_SYMBOL(drm_gem_object_free);
+/**
+ * drm_gem_vm_open - vma->ops->open implementation for GEM
+ * @vma: VM area structure
+ *
+ * This function implements the #vm_operations_struct open() callback for GEM
+ * drivers. This must be used together with drm_gem_vm_close().
+ */
 void drm_gem_vm_open(struct vm_area_struct *vma)
 {
 	struct drm_gem_object *obj = vma->vm_private_data;
 }
 EXPORT_SYMBOL(drm_gem_vm_open);
+/**
+ * drm_gem_vm_close - vma->ops->close implementation for GEM
+ * @vma: VM area structure
+ *
+ * This function implements the #vm_operations_struct close() callback for GEM
+ * drivers. This must be used together with drm_gem_vm_open().
+ */
 void drm_gem_vm_close(struct vm_area_struct *vma)
 {
 	struct drm_gem_object *obj = vma->vm_private_data;

drivers/gpu/drm/drm_modes.c+29−6

 	} else if (mode1->clock != mode2->clock)
 		return false;
+	return drm_mode_equal_no_clocks(mode1, mode2);
+}
+EXPORT_SYMBOL(drm_mode_equal);
+/**
+ * drm_mode_equal_no_clocks - test modes for equality
+ * @mode1: first mode
+ * @mode2: second mode
+ *
+ * Check to see if @mode1 and @mode2 are equivalent, but
+ * don't check the pixel clocks.
+ *
+ * Returns:
+ * True if the modes are equal, false otherwise.
+ */
+bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
+{
 	if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) !=
 	    (mode2->flags & DRM_MODE_FLAG_3D_MASK))
 		return false;
 	return drm_mode_equal_no_clocks_no_stereo(mode1, mode2);
 }
-EXPORT_SYMBOL(drm_mode_equal);
+EXPORT_SYMBOL(drm_mode_equal_no_clocks);
 /**
  * drm_mode_equal_no_clocks_no_stereo - test modes for equality
 	unsigned int xres = 0, yres = 0, bpp = 32, refresh = 0;
 	bool yres_specified = false, cvt = false, rb = false;
 	bool interlace = false, margins = false, was_digit = false;
-	int i;
+	int i, err;
 	enum drm_connector_force force = DRM_FORCE_UNSPECIFIED;
 #ifdef CONFIG_FB
 		case '@':
 			if (!refresh_specified && !bpp_specified &&
 			    !yres_specified && !cvt && !rb && was_digit) {
-				refresh = simple_strtol(&name[i+1], NULL, 10);
+				err = kstrtouint(&name[i + 1], 10, &refresh);
+				if (err)
+					return false;
 				refresh_specified = true;
 				was_digit = false;
 			} else
 		case '-':
 			if (!bpp_specified && !yres_specified && !cvt &&
 			    !rb && was_digit) {
-				bpp = simple_strtol(&name[i+1], NULL, 10);
+				err = kstrtouint(&name[i + 1], 10, &bpp);
+				if (err)
+					return false;
 				bpp_specified = true;
 				was_digit = false;
 			} else
 			break;
 		case 'x':
 			if (!yres_specified && was_digit) {
-				yres = simple_strtol(&name[i+1], NULL, 10);
+				err = kstrtouint(&name[i + 1], 10, &yres);
+				if (err)
+					return false;
 				yres_specified = true;
 				was_digit = false;
 			} else
 out:
 	return ret;
 }

drivers/gpu/drm/drm_modeset_lock.c+60−29

 /**
  * drm_modeset_lock_all - take all modeset locks
- * @dev: drm device
+ * @dev: DRM device
  *
  * This function takes all modeset locks, suitable where a more fine-grained
- * scheme isn't (yet) implemented. Locks must be dropped with
+ * scheme isn't (yet) implemented. Locks must be dropped by calling the
- * drm_modeset_unlock_all.
+ * drm_modeset_unlock_all() function.
+ *
+ * This function is deprecated. It allocates a lock acquisition context and
+ * stores it in the DRM device's ->mode_config. This facilitate conversion of
+ * existing code because it removes the need to manually deal with the
+ * acquisition context, but it is also brittle because the context is global
+ * and care must be taken not to nest calls. New code should use the
+ * drm_modeset_lock_all_ctx() function and pass in the context explicitly.
  */
 void drm_modeset_lock_all(struct drm_device *dev)
 {
 	drm_modeset_acquire_init(ctx, 0);
 retry:
-	ret = drm_modeset_lock(&config->connection_mutex, ctx);
+	ret = drm_modeset_lock_all_ctx(dev, ctx);
-	if (ret)
+	if (ret < 0) {
-		goto fail;
+		if (ret == -EDEADLK) {
-	ret = drm_modeset_lock_all_crtcs(dev, ctx);
+			drm_modeset_backoff(ctx);
-	if (ret)
+			goto retry;
-		goto fail;
+		}
+		drm_modeset_acquire_fini(ctx);
+		kfree(ctx);
+		return;
+	}
 	WARN_ON(config->acquire_ctx);
-	/* now we hold the locks, so now that it is safe, stash the
+	/*
-	 * ctx for drm_modeset_unlock_all():
+	 * We hold the locks now, so it is safe to stash the acquisition
+	 * context for drm_modeset_unlock_all().
 	 */
 	config->acquire_ctx = ctx;
 	drm_warn_on_modeset_not_all_locked(dev);
-	return;
-fail:
-	if (ret == -EDEADLK) {
-		drm_modeset_backoff(ctx);
-		goto retry;
-	}
-	kfree(ctx);
 }
 EXPORT_SYMBOL(drm_modeset_lock_all);
 /**
  * drm_modeset_unlock_all - drop all modeset locks
- * @dev: device
+ * @dev: DRM device
  *
- * This function drop all modeset locks taken by drm_modeset_lock_all.
+ * This function drops all modeset locks taken by a previous call to the
+ * drm_modeset_lock_all() function.
+ *
+ * This function is deprecated. It uses the lock acquisition context stored
+ * in the DRM device's ->mode_config. This facilitates conversion of existing
+ * code because it removes the need to manually deal with the acquisition
+ * context, but it is also brittle because the context is global and care must
+ * be taken not to nest calls. New code should pass the acquisition context
+ * directly to the drm_modeset_drop_locks() function.
  */
 void drm_modeset_unlock_all(struct drm_device *dev)
 {
 }
 EXPORT_SYMBOL(drm_modeset_unlock);
-/* In some legacy codepaths it's convenient to just grab all the crtc and plane
+/**
- * related locks. */
+ * drm_modeset_lock_all_ctx - take all modeset locks
-int drm_modeset_lock_all_crtcs(struct drm_device *dev,
+ * @dev: DRM device
-		struct drm_modeset_acquire_ctx *ctx)
+ * @ctx: lock acquisition context
+ *
+ * This function takes all modeset locks, suitable where a more fine-grained
+ * scheme isn't (yet) implemented.
+ *
+ * Unlike drm_modeset_lock_all(), it doesn't take the dev->mode_config.mutex
+ * since that lock isn't required for modeset state changes. Callers which
+ * need to grab that lock too need to do so outside of the acquire context
+ * @ctx.
+ *
+ * Locks acquired with this function should be released by calling the
+ * drm_modeset_drop_locks() function on @ctx.
+ *
+ * Returns: 0 on success or a negative error-code on failure.
+ */
+int drm_modeset_lock_all_ctx(struct drm_device *dev,
+			     struct drm_modeset_acquire_ctx *ctx)
 {
 	struct drm_crtc *crtc;
 	struct drm_plane *plane;
-	int ret = 0;
+	int ret;
+	ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx);
+	if (ret)
+		return ret;
 	drm_for_each_crtc(crtc, dev) {
 		ret = drm_modeset_lock(&crtc->mutex, ctx);
 	return 0;
 }
-EXPORT_SYMBOL(drm_modeset_lock_all_crtcs);
+EXPORT_SYMBOL(drm_modeset_lock_all_ctx);

drivers/gpu/drm/drm_plane_helper.c+4−0

 	vscale = drm_rect_calc_vscale(src, dest, min_scale, max_scale);
 	if (hscale < 0 || vscale < 0) {
 		DRM_DEBUG_KMS("Invalid scaling of plane\n");
+		drm_rect_debug_print("src: ", src, true);
+		drm_rect_debug_print("dst: ", dest, false);
 		return -ERANGE;
 	}
 	if (!can_position && !drm_rect_equals(dest, clip)) {
 		DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+		drm_rect_debug_print("dst: ", dest, false);
+		drm_rect_debug_print("clip: ", clip, false);
 		return -EINVAL;
 	}

drivers/gpu/drm/drm_probe_helper.c+24−23

 	list_for_each_entry(mode, &connector->modes, head)
 		mode->status = MODE_UNVERIFIED;
+	old_status = connector->status;
 	if (connector->force) {
 		if (connector->force == DRM_FORCE_ON ||
 		    connector->force == DRM_FORCE_ON_DIGITAL)
 		if (connector->funcs->force)
 			connector->funcs->force(connector);
 	} else {
-		old_status = connector->status;
 		connector->status = connector->funcs->detect(connector, true);
+	}
+	/*
+	 * Normally either the driver's hpd code or the poll loop should
+	 * pick up any changes and fire the hotplug event. But if
+	 * userspace sneaks in a probe, we might miss a change. Hence
+	 * check here, and if anything changed start the hotplug code.
+	 */
+	if (old_status != connector->status) {
+		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
+			      connector->base.id,
+			      connector->name,
+			      drm_get_connector_status_name(old_status),
+			      drm_get_connector_status_name(connector->status));
 		/*
-		 * Normally either the driver's hpd code or the poll loop should
+		 * The hotplug event code might call into the fb
-		 * pick up any changes and fire the hotplug event. But if
+		 * helpers, and so expects that we do not hold any
-		 * userspace sneaks in a probe, we might miss a change. Hence
+		 * locks. Fire up the poll struct instead, it will
-		 * check here, and if anything changed start the hotplug code.
+		 * disable itself again.
 		 */
-		if (old_status != connector->status) {
+		dev->mode_config.delayed_event = true;
-			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
+		if (dev->mode_config.poll_enabled)
-				      connector->base.id,
+			schedule_delayed_work(&dev->mode_config.output_poll_work,
-				      connector->name,
+					      0);
-				      old_status, connector->status);
-			/*
-			 * The hotplug event code might call into the fb
-			 * helpers, and so expects that we do not hold any
-			 * locks. Fire up the poll struct instead, it will
-			 * disable itself again.
-			 */
-			dev->mode_config.delayed_event = true;
-			if (dev->mode_config.poll_enabled)
-				schedule_delayed_work(&dev->mode_config.output_poll_work,
-						      0);
-		}
 	}
 	/* Re-enable polling in case the global poll config changed. */

drivers/gpu/drm/drm_rect.c+4−3

 /**
  * drm_rect_debug_print - print the rectangle information
+ * @prefix: prefix string
  * @r: rectangle to print
  * @fixed_point: rectangle is in 16.16 fixed point format
  */
-void drm_rect_debug_print(const struct drm_rect *r, bool fixed_point)
+void drm_rect_debug_print(const char *prefix, const struct drm_rect *r, bool fixed_point)
 {
 	int w = drm_rect_width(r);
 	int h = drm_rect_height(r);
 	if (fixed_point)
-		DRM_DEBUG_KMS("%d.%06ux%d.%06u%+d.%06u%+d.%06u\n",
+		DRM_DEBUG_KMS("%s%d.%06ux%d.%06u%+d.%06u%+d.%06u\n", prefix,
 			      w >> 16, ((w & 0xffff) * 15625) >> 10,
 			      h >> 16, ((h & 0xffff) * 15625) >> 10,
 			      r->x1 >> 16, ((r->x1 & 0xffff) * 15625) >> 10,
 			      r->y1 >> 16, ((r->y1 & 0xffff) * 15625) >> 10);
 	else
-		DRM_DEBUG_KMS("%dx%d%+d%+d\n", w, h, r->x1, r->y1);
+		DRM_DEBUG_KMS("%s%dx%d%+d%+d\n", prefix, w, h, r->x1, r->y1);
 }
 EXPORT_SYMBOL(drm_rect_debug_print);

drivers/gpu/drm/drm_sysfs.c+25−29

 {
 	struct drm_connector *connector = to_drm_connector(device);
 	struct drm_device *dev = connector->dev;
-	enum drm_connector_status old_status;
+	enum drm_connector_force old_force;
 	int ret;
 	ret = mutex_lock_interruptible(&dev->mode_config.mutex);
 	if (ret)
 		return ret;
-	old_status = connector->status;
+	old_force = connector->force;
-	if (sysfs_streq(buf, "detect")) {
+	if (sysfs_streq(buf, "detect"))
 		connector->force = 0;
-		connector->status = connector->funcs->detect(connector, true);
+	else if (sysfs_streq(buf, "on"))
-	} else if (sysfs_streq(buf, "on")) {
 		connector->force = DRM_FORCE_ON;
-	} else if (sysfs_streq(buf, "on-digital")) {
+	else if (sysfs_streq(buf, "on-digital"))
 		connector->force = DRM_FORCE_ON_DIGITAL;
-	} else if (sysfs_streq(buf, "off")) {
+	else if (sysfs_streq(buf, "off"))
 		connector->force = DRM_FORCE_OFF;
-	} else
+	else
 		ret = -EINVAL;
-	if (ret == 0 && connector->force) {
+	if (old_force != connector->force || !connector->force) {
-		if (connector->force == DRM_FORCE_ON ||
+		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force updated from %d to %d or reprobing\n",
-		    connector->force == DRM_FORCE_ON_DIGITAL)
-			connector->status = connector_status_connected;
-		else
-			connector->status = connector_status_disconnected;
-		if (connector->funcs->force)
-			connector->funcs->force(connector);
-	}
-	if (old_status != connector->status) {
-		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
 			      connector->base.id,
 			      connector->name,
-			      old_status, connector->status);
+			      old_force, connector->force);
-		dev->mode_config.delayed_event = true;
+		connector->funcs->fill_modes(connector,
-		if (dev->mode_config.poll_enabled)
+					     dev->mode_config.max_width,
-			schedule_delayed_work(&dev->mode_config.output_poll_work,
+					     dev->mode_config.max_height);
-					      0);
 	}
 	mutex_unlock(&dev->mode_config.mutex);
 	struct drm_connector *connector = to_drm_connector(connector_dev);
 	unsigned char *edid;
 	size_t size;
+	ssize_t ret = 0;
+	mutex_lock(&connector->dev->mode_config.mutex);
 	if (!connector->edid_blob_ptr)
-		return 0;
+		goto unlock;
 	edid = connector->edid_blob_ptr->data;
 	size = connector->edid_blob_ptr->length;
 	if (!edid)
-		return 0;
+		goto unlock;
 	if (off >= size)
-		return 0;
+		goto unlock;
 	if (off + count > size)
 		count = size - off;
 	memcpy(buf, edid + off, count);
-	return count;
+	ret = count;
+unlock:
+	mutex_unlock(&connector->dev->mode_config.mutex);
+	return ret;
 }
 static ssize_t modes_show(struct device *device,
 	struct drm_display_mode *mode;
 	int written = 0;
+	mutex_lock(&connector->dev->mode_config.mutex);
 	list_for_each_entry(mode, &connector->modes, head) {
 		written += snprintf(buf + written, PAGE_SIZE - written, "%s\n",
 				    mode->name);
 	}
+	mutex_unlock(&connector->dev->mode_config.mutex);
 	return written;
 }

drivers/gpu/drm/exynos/exynos_drm_fb.c+2−2

@@ -117,7 +117,7 @@ static struct drm_framebuffer_funcs exynos_drm_fb_funcs = { · 116 unmodified lines
117		117
118	struct drm_framebuffer *	118	struct drm_framebuffer *
119	exynos_drm_framebuffer_init(struct drm_device *dev,	119	exynos_drm_framebuffer_init(struct drm_device *dev,
120	struct drm_mode_fb_cmd2 *mode_cmd,	120	const struct drm_mode_fb_cmd2 *mode_cmd,
121	struct exynos_drm_gem **exynos_gem,	121	struct exynos_drm_gem **exynos_gem,
122	int count)	122	int count)
123	{	123	{
@@ -154,7 +154,7 @@ err: · 30 unmodified lines
154		154
155	static struct drm_framebuffer *	155	static struct drm_framebuffer *
156	exynos_user_fb_create(struct drm_device dev, struct drm_file file_priv,	156	exynos_user_fb_create(struct drm_device dev, struct drm_file file_priv,
157	struct drm_mode_fb_cmd2 *mode_cmd)	157	const struct drm_mode_fb_cmd2 *mode_cmd)
158	{	158	{
159	struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER];	159	struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER];
160	struct drm_gem_object *obj;	160	struct drm_gem_object *obj;

drivers/gpu/drm/exynos/exynos_drm_fb.h+1−1

@@ -18,7 +18,7 @@ · 17 unmodified lines
18		18
19	struct drm_framebuffer *	19	struct drm_framebuffer *
20	exynos_drm_framebuffer_init(struct drm_device *dev,	20	exynos_drm_framebuffer_init(struct drm_device *dev,
21	struct drm_mode_fb_cmd2 *mode_cmd,	21	const struct drm_mode_fb_cmd2 *mode_cmd,
22	struct exynos_drm_gem **exynos_gem,	22	struct exynos_drm_gem **exynos_gem,
23	int count);	23	int count);
24		24

drivers/gpu/drm/gma500/framebuffer.c+5−13

  */
 static int psb_framebuffer_init(struct drm_device *dev,
 					struct psb_framebuffer *fb,
-					struct drm_mode_fb_cmd2 *mode_cmd,
+					const struct drm_mode_fb_cmd2 *mode_cmd,
 					struct gtt_range *gt)
 {
 	u32 bpp, depth;
 static struct drm_framebuffer *psb_framebuffer_create
 			(struct drm_device *dev,
-			 struct drm_mode_fb_cmd2 *mode_cmd,
+			 const struct drm_mode_fb_cmd2 *mode_cmd,
 			 struct gtt_range *gt)
 {
 	struct psb_framebuffer *fb;
 	memset(dev_priv->vram_addr + backing->offset, 0, size);
-	mutex_lock(&dev->struct_mutex);
 	info = drm_fb_helper_alloc_fbi(&fbdev->psb_fb_helper);
 	if (IS_ERR(info)) {
 		ret = PTR_ERR(info);
 	dev_dbg(dev->dev, "allocated %dx%d fb\n",
 					psbfb->base.width, psbfb->base.height);
-	mutex_unlock(&dev->struct_mutex);
 	return 0;
 out_unref:
 	if (backing->stolen)
 		psb_gtt_free_range(dev, backing);
 	else
-		drm_gem_object_unreference(&backing->gem);
+		drm_gem_object_unreference_unlocked(&backing->gem);
 	drm_fb_helper_release_fbi(&fbdev->psb_fb_helper);
 out_err1:
-	mutex_unlock(&dev->struct_mutex);
 	psb_gtt_free_range(dev, backing);
 	return ret;
 }
  */
 static struct drm_framebuffer *psb_user_framebuffer_create
 			(struct drm_device *dev, struct drm_file *filp,
-			 struct drm_mode_fb_cmd2 *cmd)
+			 const struct drm_mode_fb_cmd2 *cmd)
 {
 	struct gtt_range *r;
 	struct drm_gem_object *obj;
 	drm_framebuffer_cleanup(&psbfb->base);
 	if (psbfb->gtt)
-		drm_gem_object_unreference(&psbfb->gtt->gem);
+		drm_gem_object_unreference_unlocked(&psbfb->gtt->gem);
 	return 0;
 }
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
 	if (dev_priv->modeset) {
-		mutex_lock(&dev->struct_mutex);
 		drm_kms_helper_poll_fini(dev);
 		psb_fbdev_fini(dev);
 		drm_mode_config_cleanup(dev);
-		mutex_unlock(&dev->struct_mutex);
 	}
 }

drivers/gpu/drm/gma500/gem.c+6−13

 	int ret = 0;
 	struct drm_gem_object *obj;
-	mutex_lock(&dev->struct_mutex);
 	/* GEM does all our handle to object mapping */
 	obj = drm_gem_object_lookup(dev, file, handle);
-	if (obj == NULL) {
+	if (obj == NULL)
-		ret = -ENOENT;
+		return -ENOENT;
-		goto unlock;
-	}
-	/* What validation is needed here ? */
 	/* Make it mmapable */
 	ret = drm_gem_create_mmap_offset(obj);
 		goto out;
 	*offset = drm_vma_node_offset_addr(&obj->vma_node);
 out:
-	drm_gem_object_unreference(obj);
+	drm_gem_object_unreference_unlocked(obj);
-unlock:
-	mutex_unlock(&dev->struct_mutex);
 	return ret;
 }
 		return ret;
 	}
 	/* We have the initial and handle reference but need only one now */
-	drm_gem_object_unreference(&r->gem);
+	drm_gem_object_unreference_unlocked(&r->gem);
 	*handlep = handle;
 	return 0;
 }
 	/* Make sure we don't parallel update on a fault, nor move or remove
 	   something from beneath our feet */
-	mutex_lock(&dev->struct_mutex);
+	mutex_lock(&dev_priv->mmap_mutex);
 	/* For now the mmap pins the object and it stays pinned. As things
 	   stand that will do us no harm */
 	ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
 fail:
-	mutex_unlock(&dev->struct_mutex);
+	mutex_unlock(&dev_priv->mmap_mutex);
 	switch (ret) {
 	case 0:
 	case -ERESTARTSYS:

drivers/gpu/drm/gma500/gma_display.c+3−10

 	/* If we didn't get a handle then turn the cursor off */
 	if (!handle) {
 		temp = CURSOR_MODE_DISABLE;
-		mutex_lock(&dev->struct_mutex);
 		if (gma_power_begin(dev, false)) {
 			REG_WRITE(control, temp);
 			REG_WRITE(base, 0);
 			gt = container_of(gma_crtc->cursor_obj,
 					  struct gtt_range, gem);
 			psb_gtt_unpin(gt);
-			drm_gem_object_unreference(gma_crtc->cursor_obj);
+			drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj);
 			gma_crtc->cursor_obj = NULL;
 		}
-		mutex_unlock(&dev->struct_mutex);
 		return 0;
 	}
 		return -EINVAL;
 	}
-	mutex_lock(&dev->struct_mutex);
 	obj = drm_gem_object_lookup(dev, file_priv, handle);
 	if (!obj) {
 		ret = -ENOENT;
 	if (gma_crtc->cursor_obj) {
 		gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem);
 		psb_gtt_unpin(gt);
-		drm_gem_object_unreference(gma_crtc->cursor_obj);
+		drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj);
 	}
 	gma_crtc->cursor_obj = obj;
 unlock:
-	mutex_unlock(&dev->struct_mutex);
 	return ret;
 unref_cursor:
-	drm_gem_object_unreference(obj);
+	drm_gem_object_unreference_unlocked(obj);
-	mutex_unlock(&dev->struct_mutex);
 	return ret;
 }

drivers/gpu/drm/gma500/gtt.c+1−0

@@ -425,6 +425,7 @@ int psb_gtt_init(struct drm_device *dev, int resume) · 424 unmodified lines
425		425
426	if (!resume) {	426	if (!resume) {
427	mutex_init(&dev_priv->gtt_mutex);	427	mutex_init(&dev_priv->gtt_mutex);
		428	mutex_init(&dev_priv->mmap_mutex);
428	psb_gtt_alloc(dev);	429	psb_gtt_alloc(dev);
429	}	430	}
430		431

drivers/gpu/drm/gma500/psb_drv.h+2−0

@@ -465,6 +465,8 @@ struct drm_psb_private { · 464 unmodified lines
465	struct mutex gtt_mutex;	465	struct mutex gtt_mutex;
466	struct resource gtt_mem; / Our PCI resource */	466	struct resource gtt_mem; / Our PCI resource */
467		467
		468	struct mutex mmap_mutex;
		469
468	struct psb_mmu_driver *mmu;	470	struct psb_mmu_driver *mmu;
469	struct psb_mmu_pd *pf_pd;	471	struct psb_mmu_pd *pf_pd;
470		472

drivers/gpu/drm/i915/Kconfig+1−0

@@ -10,6 +10,7 @@ config DRM_I915 · 9 unmodified lines
10	# the shmem_readpage() which depends upon tmpfs	10	# the shmem_readpage() which depends upon tmpfs
11	select SHMEM	11	select SHMEM
12	select TMPFS	12	select TMPFS
		13	select STOP_MACHINE
13	select DRM_KMS_HELPER	14	select DRM_KMS_HELPER
14	select DRM_PANEL	15	select DRM_PANEL
15	select DRM_MIPI_DSI	16	select DRM_MIPI_DSI

drivers/gpu/drm/i915/Makefile+1−0

@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \ · 76 unmodified lines
77	dvo_tfp410.o \	77	dvo_tfp410.o \
78	intel_crt.o \	78	intel_crt.o \
79	intel_ddi.o \	79	intel_ddi.o \
		80	intel_dp_link_training.o \
80	intel_dp_mst.o \	81	intel_dp_mst.o \
81	intel_dp.o \	82	intel_dp.o \
82	intel_dsi.o \	83	intel_dsi.o \

drivers/gpu/drm/i915/dvo.h+2−1

 	const char *name;
 	int type;
 	/* DVOA/B/C output register */
-	u32 dvo_reg;
+	i915_reg_t dvo_reg;
+	i915_reg_t dvo_srcdim_reg;
 	/* GPIO register used for i2c bus to control this device */
 	u32 gpio;
 	int slave_addr;

drivers/gpu/drm/i915/i915_cmd_parser.c+21−16

  * LRI.
  */
 struct drm_i915_reg_descriptor {
-	u32 addr;
+	i915_reg_t addr;
 	u32 mask;
 	u32 value;
 };
 /* Convenience macro for adding 32-bit registers. */
-#define REG32(address, ...)                             \
+#define REG32(_reg, ...) \
-	{ .addr = address, __VA_ARGS__ }
+	{ .addr = (_reg), __VA_ARGS__ }
 /*
  * Convenience macro for adding 64-bit registers.
  * access commands only allow 32-bit accesses. Hence, we have to include
  * entries for both halves of the 64-bit registers.
  */
-#define REG64(addr)                                     \
+#define REG64(_reg) \
-	REG32(addr), REG32(addr + sizeof(u32))
+	{ .addr = _reg }, \
+	{ .addr = _reg ## _UDW }
+#define REG64_IDX(_reg, idx) \
+	{ .addr = _reg(idx) }, \
+	{ .addr = _reg ## _UDW(idx) }
 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 	REG64(GPGPU_THREADS_DISPATCHED),
 	REG32(GEN7_GPGPU_DISPATCHDIMX),
 	REG32(GEN7_GPGPU_DISPATCHDIMY),
 	REG32(GEN7_GPGPU_DISPATCHDIMZ),
-	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
+	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
-	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
+	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
-	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
+	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
-	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
+	REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
-	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
+	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
-	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
+	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
-	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
+	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
-	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
+	REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
 	REG32(GEN7_SO_WRITE_OFFSET(0)),
 	REG32(GEN7_SO_WRITE_OFFSET(1)),
 	REG32(GEN7_SO_WRITE_OFFSET(2)),
 	bool ret = true;
 	for (i = 0; i < reg_count; i++) {
-		u32 curr = reg_table[i].addr;
+		u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
 		if (curr < previous) {
 			DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 		int i;
 		for (i = 0; i < count; i++) {
-			if (table[i].addr == addr)
+			if (i915_mmio_reg_offset(table[i].addr) == addr)
 				return &table[i];
 		}
 	}
 			 * to the register. Hence, limit OACONTROL writes to
 			 * only MI_LOAD_REGISTER_IMM commands.
 			 */
-			if (reg_addr == OACONTROL) {
+			if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {
 				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
 					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
 					return false;

drivers/gpu/drm/i915/i915_debugfs.c+201−43

@@ -1252,18 +1252,21 @@ static int i915_frequency_info(struct seq_file m, void unused) · 1251 unmodified lines
1252		1252
1253	max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :	1253	max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1254	rp_state_cap >> 16) & 0xff;	1254	rp_state_cap >> 16) & 0xff;
1255	max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);	1255	max_freq *= (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev) ?
		1256	GEN9_FREQ_SCALER : 1);
1256	seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",	1257	seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1257	intel_gpu_freq(dev_priv, max_freq));	1258	intel_gpu_freq(dev_priv, max_freq));
1258		1259
1259	max_freq = (rp_state_cap & 0xff00) >> 8;	1260	max_freq = (rp_state_cap & 0xff00) >> 8;
1260	max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);	1261	max_freq *= (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev) ?
		1262	GEN9_FREQ_SCALER : 1);
1261	seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",	1263	seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1262	intel_gpu_freq(dev_priv, max_freq));	1264	intel_gpu_freq(dev_priv, max_freq));
1263		1265
1264	max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :	1266	max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1265	rp_state_cap >> 0) & 0xff;	1267	rp_state_cap >> 0) & 0xff;
1266	max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);	1268	max_freq *= (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev) ?
		1269	GEN9_FREQ_SCALER : 1);
1267	seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",	1270	seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1268	intel_gpu_freq(dev_priv, max_freq));	1271	intel_gpu_freq(dev_priv, max_freq));
1269	seq_printf(m, "Max overclocked frequency: %dMHz\n",	1272	seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1523,7 +1526,7 @@ static int gen6_drpc_info(struct seq_file *m) · 253 unmodified lines
1523	seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));	1526	seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1524	}	1527	}
1525		1528
1526	gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);	1529	gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1527	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);	1530	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1528		1531
1529	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);	1532	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
@@ -1640,7 +1643,7 @@ static int i915_fbc_status(struct seq_file m, void unused) · 110 unmodified lines
1640	seq_puts(m, "FBC enabled\n");	1643	seq_puts(m, "FBC enabled\n");
1641	else	1644	else
1642	seq_printf(m, "FBC disabled: %s\n",	1645	seq_printf(m, "FBC disabled: %s\n",
1643	intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));	1646	dev_priv->fbc.no_fbc_reason);
1644		1647
1645	if (INTEL_INFO(dev_priv)->gen >= 7)	1648	if (INTEL_INFO(dev_priv)->gen >= 7)
1646	seq_printf(m, "Compressing: %s\n",	1649	seq_printf(m, "Compressing: %s\n",
@@ -1801,7 +1804,7 @@ static int i915_ring_freq_table(struct seq_file m, void unused) · 154 unmodified lines
1801	if (ret)	1804	if (ret)
1802	goto out;	1805	goto out;
1803		1806
1804	if (IS_SKYLAKE(dev)) {	1807	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
1805	/* Convert GT frequency to 50 HZ units */	1808	/* Convert GT frequency to 50 HZ units */
1806	min_gpu_freq =	1809	min_gpu_freq =
1807	dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;	1810	dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
@@ -1821,7 +1824,8 @@ static int i915_ring_freq_table(struct seq_file m, void unused) · 13 unmodified lines
1821	&ia_freq);	1824	&ia_freq);
1822	seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",	1825	seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1823	intel_gpu_freq(dev_priv, (gpu_freq *	1826	intel_gpu_freq(dev_priv, (gpu_freq *
1824	(IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),	1827	(IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev) ?
		1828	GEN9_FREQ_SCALER : 1))),
1825	((ia_freq >> 0) & 0xff) * 100,	1829	((ia_freq >> 0) & 0xff) * 100,
1826	((ia_freq >> 8) & 0xff) * 100);	1830	((ia_freq >> 8) & 0xff) * 100);
1827	}	1831	}
@@ -1873,17 +1877,19 @@ static int i915_gem_framebuffer_info(struct seq_file m, void data) · 45 unmodified lines
1873	struct drm_i915_private *dev_priv = dev->dev_private;	1877	struct drm_i915_private *dev_priv = dev->dev_private;
1874		1878
1875	ifbdev = dev_priv->fbdev;	1879	ifbdev = dev_priv->fbdev;
1876	fb = to_intel_framebuffer(ifbdev->helper.fb);	1880	if (ifbdev) {
1877		1881	fb = to_intel_framebuffer(ifbdev->helper.fb);
1878	seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",	1882
1879	fb->base.width,	1883	seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880	fb->base.height,	1884	fb->base.width,
1881	fb->base.depth,	1885	fb->base.height,
1882	fb->base.bits_per_pixel,	1886	fb->base.depth,
1883	fb->base.modifier[0],	1887	fb->base.bits_per_pixel,
1884	atomic_read(&fb->base.refcount.refcount));	1888	fb->base.modifier[0],
1885	describe_obj(m, fb->obj);	1889	atomic_read(&fb->base.refcount.refcount));
1886	seq_putc(m, '\n');	1890	describe_obj(m, fb->obj);
		1891	seq_putc(m, '\n');
		1892	}
1887	#endif	1893	#endif
1888		1894
1889	mutex_lock(&dev->mode_config.fb_lock);	1895	mutex_lock(&dev->mode_config.fb_lock);
@@ -2402,6 +2408,12 @@ static int i915_guc_load_status_info(struct seq_file m, void data) · 512 unmodified lines
2402	guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);	2408	guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2403	seq_printf(m, "\tversion found: %d.%d\n",	2409	seq_printf(m, "\tversion found: %d.%d\n",
2404	guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);	2410	guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
		2411	seq_printf(m, "\theader: offset is %d; size = %d\n",
		2412	guc_fw->header_offset, guc_fw->header_size);
		2413	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
		2414	guc_fw->ucode_offset, guc_fw->ucode_size);
		2415	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
		2416	guc_fw->rsa_offset, guc_fw->rsa_size);
2405		2417
2406	tmp = I915_READ(GUC_STATUS);	2418	tmp = I915_READ(GUC_STATUS);
2407		2419
@@ -2550,7 +2562,7 @@ static int i915_edp_psr_status(struct seq_file m, void data) · 142 unmodified lines
2550	yesno(work_busy(&dev_priv->psr.work.work)));	2562	yesno(work_busy(&dev_priv->psr.work.work)));
2551		2563
2552	if (HAS_DDI(dev))	2564	if (HAS_DDI(dev))
2553	enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;	2565	enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2554	else {	2566	else {
2555	for_each_pipe(dev_priv, pipe) {	2567	for_each_pipe(dev_priv, pipe) {
2556	stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &	2568	stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
@@ -2572,7 +2584,7 @@ static int i915_edp_psr_status(struct seq_file m, void data) · 15 unmodified lines
2572		2584
2573	/* CHV PSR has no kind of performance counter */	2585	/* CHV PSR has no kind of performance counter */
2574	if (HAS_DDI(dev)) {	2586	if (HAS_DDI(dev)) {
2575	psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &	2587	psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2576	EDP_PSR_PERF_CNT_MASK;	2588	EDP_PSR_PERF_CNT_MASK;
2577		2589
2578	seq_printf(m, "Performance_Counter: %u\n", psrperf);	2590	seq_printf(m, "Performance_Counter: %u\n", psrperf);
@@ -2696,24 +2708,16 @@ static const char *power_domain_str(enum intel_display_power_domain domain) · 117 unmodified lines
2696	return "TRANSCODER_C";	2708	return "TRANSCODER_C";
2697	case POWER_DOMAIN_TRANSCODER_EDP:	2709	case POWER_DOMAIN_TRANSCODER_EDP:
2698	return "TRANSCODER_EDP";	2710	return "TRANSCODER_EDP";
2699	case POWER_DOMAIN_PORT_DDI_A_2_LANES:	2711	case POWER_DOMAIN_PORT_DDI_A_LANES:
2700	return "PORT_DDI_A_2_LANES";	2712	return "PORT_DDI_A_LANES";
2701	case POWER_DOMAIN_PORT_DDI_A_4_LANES:	2713	case POWER_DOMAIN_PORT_DDI_B_LANES:
2702	return "PORT_DDI_A_4_LANES";	2714	return "PORT_DDI_B_LANES";
2703	case POWER_DOMAIN_PORT_DDI_B_2_LANES:	2715	case POWER_DOMAIN_PORT_DDI_C_LANES:
2704	return "PORT_DDI_B_2_LANES";	2716	return "PORT_DDI_C_LANES";
2705	case POWER_DOMAIN_PORT_DDI_B_4_LANES:	2717	case POWER_DOMAIN_PORT_DDI_D_LANES:
2706	return "PORT_DDI_B_4_LANES";	2718	return "PORT_DDI_D_LANES";
2707	case POWER_DOMAIN_PORT_DDI_C_2_LANES:	2719	case POWER_DOMAIN_PORT_DDI_E_LANES:
2708	return "PORT_DDI_C_2_LANES";	2720	return "PORT_DDI_E_LANES";
2709	case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2710	return "PORT_DDI_C_4_LANES";
2711	case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2712	return "PORT_DDI_D_2_LANES";
2713	case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2714	return "PORT_DDI_D_4_LANES";
2715	case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2716	return "PORT_DDI_E_2_LANES";
2717	case POWER_DOMAIN_PORT_DSI:	2721	case POWER_DOMAIN_PORT_DSI:
2718	return "PORT_DSI";	2722	return "PORT_DSI";
2719	case POWER_DOMAIN_PORT_CRT:	2723	case POWER_DOMAIN_PORT_CRT:
@@ -2736,6 +2740,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain) · 16 unmodified lines
2736	return "AUX_D";	2740	return "AUX_D";
2737	case POWER_DOMAIN_GMBUS:	2741	case POWER_DOMAIN_GMBUS:
2738	return "GMBUS";	2742	return "GMBUS";
		2743	case POWER_DOMAIN_MODESET:
		2744	return "MODESET";
2739	case POWER_DOMAIN_INIT:	2745	case POWER_DOMAIN_INIT:
2740	return "INIT";	2746	return "INIT";
2741	default:	2747	default:
@@ -2779,6 +2785,51 @@ static int i915_power_domain_info(struct seq_file m, void unused) · 37 unmodified lines
2779	return 0;	2785	return 0;
2780	}	2786	}
2781		2787
		2788	static int i915_dmc_info(struct seq_file m, void unused)
		2789	{
		2790	struct drm_info_node *node = m->private;
		2791	struct drm_device *dev = node->minor->dev;
		2792	struct drm_i915_private *dev_priv = dev->dev_private;
		2793	struct intel_csr *csr;
		2794
		2795	if (!HAS_CSR(dev)) {
		2796	seq_puts(m, "not supported\n");
		2797	return 0;
		2798	}
		2799
		2800	csr = &dev_priv->csr;
		2801
		2802	intel_runtime_pm_get(dev_priv);
		2803
		2804	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
		2805	seq_printf(m, "path: %s\n", csr->fw_path);
		2806
		2807	if (!csr->dmc_payload)
		2808	goto out;
		2809
		2810	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
		2811	CSR_VERSION_MINOR(csr->version));
		2812
		2813	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
		2814	seq_printf(m, "DC3 -> DC5 count: %d\n",
		2815	I915_READ(SKL_CSR_DC3_DC5_COUNT));
		2816	seq_printf(m, "DC5 -> DC6 count: %d\n",
		2817	I915_READ(SKL_CSR_DC5_DC6_COUNT));
		2818	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
		2819	seq_printf(m, "DC3 -> DC5 count: %d\n",
		2820	I915_READ(BXT_CSR_DC3_DC5_COUNT));
		2821	}
		2822
		2823	out:
		2824	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
		2825	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
		2826	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
		2827
		2828	intel_runtime_pm_put(dev_priv);
		2829
		2830	return 0;
		2831	}
		2832
2782	static void intel_seq_print_mode(struct seq_file *m, int tabs,	2833	static void intel_seq_print_mode(struct seq_file *m, int tabs,
2783	struct drm_display_mode *mode)	2834	struct drm_display_mode *mode)
2784	{	2835	{
@@ -2946,6 +2997,107 @@ static bool cursor_position(struct drm_device dev, int pipe, int x, int *y) · 161 unmodified lines
2946	return cursor_active(dev, pipe);	2997	return cursor_active(dev, pipe);
2947	}	2998	}
2948		2999
		3000	static const char *plane_type(enum drm_plane_type type)
		3001	{
		3002	switch (type) {
		3003	case DRM_PLANE_TYPE_OVERLAY:
		3004	return "OVL";
		3005	case DRM_PLANE_TYPE_PRIMARY:
		3006	return "PRI";
		3007	case DRM_PLANE_TYPE_CURSOR:
		3008	return "CUR";
		3009	/*
		3010	* Deliberately omitting default: to generate compiler warnings
		3011	* when a new drm_plane_type gets added.
		3012	*/
		3013	}
		3014
		3015	return "unknown";
		3016	}
		3017
		3018	static const char *plane_rotation(unsigned int rotation)
		3019	{
		3020	static char buf[48];
		3021	/*
		3022	* According to doc only one DRM_ROTATE_ is allowed but this
		3023	* will print them all to visualize if the values are misused
		3024	*/
		3025	snprintf(buf, sizeof(buf),
		3026	"%s%s%s%s%s%s(0x%08x)",
		3027	(rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
		3028	(rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
		3029	(rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
		3030	(rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
		3031	(rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
		3032	(rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
		3033	rotation);
		3034
		3035	return buf;
		3036	}
		3037
		3038	static void intel_plane_info(struct seq_file m, struct intel_crtc intel_crtc)
		3039	{
		3040	struct drm_info_node *node = m->private;
		3041	struct drm_device *dev = node->minor->dev;
		3042	struct intel_plane *intel_plane;
		3043
		3044	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
		3045	struct drm_plane_state *state;
		3046	struct drm_plane *plane = &intel_plane->base;
		3047
		3048	if (!plane->state) {
		3049	seq_puts(m, "plane->state is NULL!\n");
		3050	continue;
		3051	}
		3052
		3053	state = plane->state;
		3054
		3055	seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
		3056	plane->base.id,
		3057	plane_type(intel_plane->base.type),
		3058	state->crtc_x, state->crtc_y,
		3059	state->crtc_w, state->crtc_h,
		3060	(state->src_x >> 16),
		3061	((state->src_x & 0xffff) * 15625) >> 10,
		3062	(state->src_y >> 16),
		3063	((state->src_y & 0xffff) * 15625) >> 10,
		3064	(state->src_w >> 16),
		3065	((state->src_w & 0xffff) * 15625) >> 10,
		3066	(state->src_h >> 16),
		3067	((state->src_h & 0xffff) * 15625) >> 10,
		3068	state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
		3069	plane_rotation(state->rotation));
		3070	}
		3071	}
		3072
		3073	static void intel_scaler_info(struct seq_file m, struct intel_crtc intel_crtc)
		3074	{
		3075	struct intel_crtc_state *pipe_config;
		3076	int num_scalers = intel_crtc->num_scalers;
		3077	int i;
		3078
		3079	pipe_config = to_intel_crtc_state(intel_crtc->base.state);
		3080
		3081	/* Not all platformas have a scaler */
		3082	if (num_scalers) {
		3083	seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
		3084	num_scalers,
		3085	pipe_config->scaler_state.scaler_users,
		3086	pipe_config->scaler_state.scaler_id);
		3087
		3088	for (i = 0; i < SKL_NUM_SCALERS; i++) {
		3089	struct intel_scaler *sc =
		3090	&pipe_config->scaler_state.scalers[i];
		3091
		3092	seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
		3093	i, yesno(sc->in_use), sc->mode);
		3094	}
		3095	seq_puts(m, "\n");
		3096	} else {
		3097	seq_puts(m, "\tNo scalers available on this platform\n");
		3098	}
		3099	}
		3100
2949	static int i915_display_info(struct seq_file m, void unused)	3101	static int i915_display_info(struct seq_file m, void unused)
2950	{	3102	{
2951	struct drm_info_node *node = m->private;	3103	struct drm_info_node *node = m->private;
@@ -2965,10 +3117,12 @@ static int i915_display_info(struct seq_file m, void unused) · 13 unmodified lines
2965		3117
2966	pipe_config = to_intel_crtc_state(crtc->base.state);	3118	pipe_config = to_intel_crtc_state(crtc->base.state);
2967		3119
2968	seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",	3120	seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
2969	crtc->base.base.id, pipe_name(crtc->pipe),	3121	crtc->base.base.id, pipe_name(crtc->pipe),
2970	yesno(pipe_config->base.active),	3122	yesno(pipe_config->base.active),
2971	pipe_config->pipe_src_w, pipe_config->pipe_src_h);	3123	pipe_config->pipe_src_w, pipe_config->pipe_src_h,
		3124	yesno(pipe_config->dither), pipe_config->pipe_bpp);
		3125
2972	if (pipe_config->base.active) {	3126	if (pipe_config->base.active) {
2973	intel_crtc_info(m, crtc);	3127	intel_crtc_info(m, crtc);
2974		3128
@@ -2978,6 +3132,8 @@ static int i915_display_info(struct seq_file m, void unused) · 3 unmodified lines
2978	x, y, crtc->base.cursor->state->crtc_w,	3132	x, y, crtc->base.cursor->state->crtc_w,
2979	crtc->base.cursor->state->crtc_h,	3133	crtc->base.cursor->state->crtc_h,
2980	crtc->cursor_addr, yesno(active));	3134	crtc->cursor_addr, yesno(active));
		3135	intel_scaler_info(m, crtc);
		3136	intel_plane_info(m, crtc);
2981	}	3137	}
2982		3138
2983	seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",	3139	seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
@@ -3112,7 +3268,8 @@ static int i915_wa_registers(struct seq_file m, void unused) · 128 unmodified lines
3112		3268
3113	seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);	3269	seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3114	for (i = 0; i < dev_priv->workarounds.count; ++i) {	3270	for (i = 0; i < dev_priv->workarounds.count; ++i) {
3115	u32 addr, mask, value, read;	3271	i915_reg_t addr;
		3272	u32 mask, value, read;
3116	bool ok;	3273	bool ok;
3117		3274
3118	addr = dev_priv->workarounds.reg[i].addr;	3275	addr = dev_priv->workarounds.reg[i].addr;
@@ -3121,7 +3278,7 @@ static int i915_wa_registers(struct seq_file m, void unused) · 2 unmodified lines
3121	read = I915_READ(addr);	3278	read = I915_READ(addr);
3122	ok = (value & mask) == (read & mask);	3279	ok = (value & mask) == (read & mask);
3123	seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",	3280	seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3124	addr, value, mask, read, ok ? "OK" : "FAIL");	3281	i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3125	}	3282	}
3126		3283
3127	intel_runtime_pm_put(dev_priv);	3284	intel_runtime_pm_put(dev_priv);
@@ -5025,7 +5182,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, · 1897 unmodified lines
5025		5182
5026	stat->slice_total++;	5183	stat->slice_total++;
5027		5184
5028	if (IS_SKYLAKE(dev))	5185	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
5029	ss_cnt = INTEL_INFO(dev)->subslice_per_slice;	5186	ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5030		5187
5031	for (ss = 0; ss < ss_max; ss++) {	5188	for (ss = 0; ss < ss_max; ss++) {
@@ -5238,6 +5395,7 @@ static const struct drm_info_list i915_debugfs_list[] = { · 206 unmodified lines
5238	{"i915_energy_uJ", i915_energy_uJ, 0},	5395	{"i915_energy_uJ", i915_energy_uJ, 0},
5239	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},	5396	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5240	{"i915_power_domain_info", i915_power_domain_info, 0},	5397	{"i915_power_domain_info", i915_power_domain_info, 0},
		5398	{"i915_dmc_info", i915_dmc_info, 0},
5241	{"i915_display_info", i915_display_info, 0},	5399	{"i915_display_info", i915_display_info, 0},
5242	{"i915_semaphore_status", i915_semaphore_status, 0},	5400	{"i915_semaphore_status", i915_semaphore_status, 0},
5243	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},	5401	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},

drivers/gpu/drm/i915/i915_dma.c+11−15

 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <linux/async.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_helper.h>
 		i915_resume_switcheroo(dev);
 		dev->switch_power_state = DRM_SWITCH_POWER_ON;
 	} else {
-		pr_err("switched off\n");
+		pr_info("switched off\n");
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 		i915_suspend_switcheroo(dev, pmm);
 		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 	if (ret)
 		goto cleanup_vga_switcheroo;
-	intel_power_domains_init_hw(dev_priv);
+	intel_power_domains_init_hw(dev_priv, false);
+	intel_csr_ucode_init(dev_priv);
 	ret = intel_irq_install(dev_priv);
 	if (ret)
 	 * scanning against hotplug events. Hence do this first and ignore the
 	 * tiny window where we will loose hotplug notifactions.
 	 */
-	async_schedule(intel_fbdev_initial_config, dev_priv);
+	intel_fbdev_initial_config_async(dev);
 	drm_kms_helper_poll_init(dev);
 	 * supports EU power gating on devices with more than one EU
 	 * pair per subslice.
 	*/
-	info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
+	info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
+			       (info->slice_total > 1));
 	info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 	info->has_eu_pg = (info->eu_per_subslice > 2);
 }
 	spin_lock_init(&dev_priv->mmio_flip_lock);
 	mutex_init(&dev_priv->sb_lock);
 	mutex_init(&dev_priv->modeset_restore_lock);
-	mutex_init(&dev_priv->csr_lock);
 	mutex_init(&dev_priv->av_mutex);
 	intel_pm_setup(dev);
 	intel_uncore_init(dev);
-	/* Load CSR Firmware for SKL */
-	intel_csr_ucode_init(dev);
 	ret = i915_gem_gtt_init(dev);
 	if (ret)
 		goto out_freecsr;
 out_gtt:
 	i915_global_gtt_cleanup(dev);
 out_freecsr:
-	intel_csr_ucode_fini(dev);
+	intel_csr_ucode_fini(dev_priv);
 	intel_uncore_fini(dev);
 	pci_iounmap(dev->pdev, dev_priv->regs);
 put_bridge:
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
+	intel_fbdev_fini(dev);
 	i915_audio_component_cleanup(dev_priv);
 	ret = i915_gem_suspend(dev);
 	acpi_video_unregister();
-	intel_fbdev_fini(dev);
 	drm_vblank_cleanup(dev);
 	intel_modeset_cleanup(dev);
 	intel_fbc_cleanup_cfb(dev_priv);
 	i915_gem_cleanup_stolen(dev);
-	intel_csr_ucode_fini(dev);
+	intel_csr_ucode_fini(dev_priv);
 	intel_teardown_gmbus(dev);
 	intel_teardown_mchbar(dev);
 {
 	struct drm_i915_file_private *file_priv = file->driver_priv;
-	if (file_priv && file_priv->bsd_ring)
-		file_priv->bsd_ring = NULL;
 	kfree(file_priv);
 }

drivers/gpu/drm/i915/i915_drv.c+82−88

@@ -383,6 +383,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { · 382 unmodified lines
383		383
384	static const struct intel_device_info intel_broxton_info = {	384	static const struct intel_device_info intel_broxton_info = {
385	.is_preliminary = 1,	385	.is_preliminary = 1,
		386	.is_broxton = 1,
386	.gen = 9,	387	.gen = 9,
387	.need_gfx_hws = 1, .has_hotplug = 1,	388	.need_gfx_hws = 1, .has_hotplug = 1,
388	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,	389	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
@@ -394,50 +395,81 @@ static const struct intel_device_info intel_broxton_info = { · 5 unmodified lines
394	IVB_CURSOR_OFFSETS,	395	IVB_CURSOR_OFFSETS,
395	};	396	};
396		397
		398	static const struct intel_device_info intel_kabylake_info = {
		399	.is_preliminary = 1,
		400	.is_kabylake = 1,
		401	.gen = 9,
		402	.num_pipes = 3,
		403	.need_gfx_hws = 1, .has_hotplug = 1,
		404	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
		405	.has_llc = 1,
		406	.has_ddi = 1,
		407	.has_fpga_dbg = 1,
		408	.has_fbc = 1,
		409	GEN_DEFAULT_PIPEOFFSETS,
		410	IVB_CURSOR_OFFSETS,
		411	};
		412
		413	static const struct intel_device_info intel_kabylake_gt3_info = {
		414	.is_preliminary = 1,
		415	.is_kabylake = 1,
		416	.gen = 9,
		417	.num_pipes = 3,
		418	.need_gfx_hws = 1, .has_hotplug = 1,
		419	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
		420	.has_llc = 1,
		421	.has_ddi = 1,
		422	.has_fpga_dbg = 1,
		423	.has_fbc = 1,
		424	GEN_DEFAULT_PIPEOFFSETS,
		425	IVB_CURSOR_OFFSETS,
		426	};
		427
397	/*	428	/*
398	* Make sure any device matches here are from most specific to most	429	* Make sure any device matches here are from most specific to most
399	* general. For example, since the Quanta match is based on the subsystem	430	* general. For example, since the Quanta match is based on the subsystem
400	* and subvendor IDs, we need it to come before the more general IVB	431	* and subvendor IDs, we need it to come before the more general IVB
401	* PCI ID matches, otherwise we'll use the wrong info struct above.	432	* PCI ID matches, otherwise we'll use the wrong info struct above.
402	*/	433	*/
403	#define INTEL_PCI_IDS \	434	static const struct pci_device_id pciidlist[] = {
404	INTEL_I830_IDS(&intel_i830_info), \	435	INTEL_I830_IDS(&intel_i830_info),
405	INTEL_I845G_IDS(&intel_845g_info), \	436	INTEL_I845G_IDS(&intel_845g_info),
406	INTEL_I85X_IDS(&intel_i85x_info), \	437	INTEL_I85X_IDS(&intel_i85x_info),
407	INTEL_I865G_IDS(&intel_i865g_info), \	438	INTEL_I865G_IDS(&intel_i865g_info),
408	INTEL_I915G_IDS(&intel_i915g_info), \	439	INTEL_I915G_IDS(&intel_i915g_info),
409	INTEL_I915GM_IDS(&intel_i915gm_info), \	440	INTEL_I915GM_IDS(&intel_i915gm_info),
410	INTEL_I945G_IDS(&intel_i945g_info), \	441	INTEL_I945G_IDS(&intel_i945g_info),
411	INTEL_I945GM_IDS(&intel_i945gm_info), \	442	INTEL_I945GM_IDS(&intel_i945gm_info),
412	INTEL_I965G_IDS(&intel_i965g_info), \	443	INTEL_I965G_IDS(&intel_i965g_info),
413	INTEL_G33_IDS(&intel_g33_info), \	444	INTEL_G33_IDS(&intel_g33_info),
414	INTEL_I965GM_IDS(&intel_i965gm_info), \	445	INTEL_I965GM_IDS(&intel_i965gm_info),
415	INTEL_GM45_IDS(&intel_gm45_info), \	446	INTEL_GM45_IDS(&intel_gm45_info),
416	INTEL_G45_IDS(&intel_g45_info), \	447	INTEL_G45_IDS(&intel_g45_info),
417	INTEL_PINEVIEW_IDS(&intel_pineview_info), \	448	INTEL_PINEVIEW_IDS(&intel_pineview_info),
418	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \	449	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
419	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \	450	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
420	INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \	451	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
421	INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \	452	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
422	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \	453	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
423	INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \	454	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
424	INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \	455	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
425	INTEL_HSW_D_IDS(&intel_haswell_d_info), \	456	INTEL_HSW_D_IDS(&intel_haswell_d_info),
426	INTEL_HSW_M_IDS(&intel_haswell_m_info), \	457	INTEL_HSW_M_IDS(&intel_haswell_m_info),
427	INTEL_VLV_M_IDS(&intel_valleyview_m_info), \	458	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
428	INTEL_VLV_D_IDS(&intel_valleyview_d_info), \	459	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
429	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \	460	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
430	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \	461	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
431	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \	462	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
432	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \	463	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
433	INTEL_CHV_IDS(&intel_cherryview_info), \	464	INTEL_CHV_IDS(&intel_cherryview_info),
434	INTEL_SKL_GT1_IDS(&intel_skylake_info), \	465	INTEL_SKL_GT1_IDS(&intel_skylake_info),
435	INTEL_SKL_GT2_IDS(&intel_skylake_info), \	466	INTEL_SKL_GT2_IDS(&intel_skylake_info),
436	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \	467	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
437	INTEL_BXT_IDS(&intel_broxton_info)	468	INTEL_BXT_IDS(&intel_broxton_info),
438		469	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
439	static const struct pci_device_id pciidlist[] = { /* aka */	470	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
440	INTEL_PCI_IDS,	471	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
		472	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
441	{0, 0, 0}	473	{0, 0, 0}
442	};	474	};
443		475
@@ -463,7 +495,7 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) · 19 unmodified lines
463	} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {	495	} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
464	ret = PCH_LPT;	496	ret = PCH_LPT;
465	DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");	497	DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
466	} else if (IS_SKYLAKE(dev)) {	498	} else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
467	ret = PCH_SPT;	499	ret = PCH_SPT;
468	DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");	500	DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
469	}	501	}
@@ -526,11 +558,13 @@ void intel_detect_pch(struct drm_device *dev) · 56 unmodified lines
526	} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {	558	} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
527	dev_priv->pch_type = PCH_SPT;	559	dev_priv->pch_type = PCH_SPT;
528	DRM_DEBUG_KMS("Found SunrisePoint PCH\n");	560	DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
529	WARN_ON(!IS_SKYLAKE(dev));	561	WARN_ON(!IS_SKYLAKE(dev) &&
		562	!IS_KABYLAKE(dev));
530	} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {	563	} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
531	dev_priv->pch_type = PCH_SPT;	564	dev_priv->pch_type = PCH_SPT;
532	DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");	565	DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
533	WARN_ON(!IS_SKYLAKE(dev));	566	WARN_ON(!IS_SKYLAKE(dev) &&
		567	!IS_KABYLAKE(dev));
534	} else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {	568	} else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {
535	dev_priv->pch_type = intel_virt_detect_pch(dev);	569	dev_priv->pch_type = intel_virt_detect_pch(dev);
536	} else	570	} else
@@ -570,26 +604,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) · 33 unmodified lines
570	return true;	604	return true;
571	}	605	}
572		606
573	void i915_firmware_load_error_print(const char *fw_path, int err)
574	{
575	DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
576
577	/*
578	* If the reason is not known assume -ENOENT since that's the most
579	* usual failure mode.
580	*/
581	if (!err)
582	err = -ENOENT;
583
584	if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
585	return;
586
587	DRM_ERROR(
588	"The driver is built-in, so to load the firmware you need to\n"
589	"include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
590	"in your initrd/initramfs image.\n");
591	}
592
593	static void intel_suspend_encoders(struct drm_i915_private *dev_priv)	607	static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
594	{	608	{
595	struct drm_device *dev = dev_priv->dev;	609	struct drm_device *dev = dev_priv->dev;
@@ -608,7 +622,6 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv) · 12 unmodified lines
608	static int intel_suspend_complete(struct drm_i915_private *dev_priv);	622	static int intel_suspend_complete(struct drm_i915_private *dev_priv);
609	static int vlv_resume_prepare(struct drm_i915_private *dev_priv,	623	static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
610	bool rpm_resume);	624	bool rpm_resume);
611	static int skl_resume_prepare(struct drm_i915_private *dev_priv);
612	static int bxt_resume_prepare(struct drm_i915_private *dev_priv);	625	static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
613		626
614		627
@@ -679,6 +692,9 @@ static int i915_drm_suspend(struct drm_device *dev) · 64 unmodified lines
679		692
680	intel_display_set_init_power(dev_priv, false);	693	intel_display_set_init_power(dev_priv, false);
681		694
		695	if (HAS_CSR(dev_priv))
		696	flush_work(&dev_priv->csr.work);
		697
682	return 0;	698	return 0;
683	}	699	}
684		700
@@ -687,10 +703,13 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) · 2 unmodified lines
687	struct drm_i915_private *dev_priv = drm_dev->dev_private;	703	struct drm_i915_private *dev_priv = drm_dev->dev_private;
688	int ret;	704	int ret;
689		705
		706	intel_power_domains_suspend(dev_priv);
		707
690	ret = intel_suspend_complete(dev_priv);	708	ret = intel_suspend_complete(dev_priv);
691		709
692	if (ret) {	710	if (ret) {
693	DRM_ERROR("Suspend complete failed: %d\n", ret);	711	DRM_ERROR("Suspend complete failed: %d\n", ret);
		712	intel_power_domains_init_hw(dev_priv, true);
694		713
695	return ret;	714	return ret;
696	}	715	}
@@ -838,13 +857,11 @@ static int i915_drm_resume_early(struct drm_device *dev) · 141 unmodified lines
838		857
839	if (IS_BROXTON(dev))	858	if (IS_BROXTON(dev))
840	ret = bxt_resume_prepare(dev_priv);	859	ret = bxt_resume_prepare(dev_priv);
841	else if (IS_SKYLAKE(dev_priv))
842	ret = skl_resume_prepare(dev_priv);
843	else if (IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))	860	else if (IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))
844	hsw_disable_pc8(dev_priv);	861	hsw_disable_pc8(dev_priv);
845		862
846	intel_uncore_sanitize(dev);	863	intel_uncore_sanitize(dev);
847	intel_power_domains_init_hw(dev_priv);	864	intel_power_domains_init_hw(dev_priv, true);
848		865
849	return ret;	866	return ret;
850	}	867	}
@@ -1051,15 +1068,6 @@ static int i915_pm_resume(struct device *dev) · 200 unmodified lines
1051	return i915_drm_resume(drm_dev);	1068	return i915_drm_resume(drm_dev);
1052	}	1069	}
1053		1070
1054	static int skl_suspend_complete(struct drm_i915_private *dev_priv)
1055	{
1056	/* Enabling DC6 is not a hard requirement to enter runtime D3 */
1057
1058	skl_uninit_cdclk(dev_priv);
1059
1060	return 0;
1061	}
1062
1063	static int hsw_suspend_complete(struct drm_i915_private *dev_priv)	1071	static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1064	{	1072	{
1065	hsw_enable_pc8(dev_priv);	1073	hsw_enable_pc8(dev_priv);
@@ -1099,16 +1107,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) · 33 unmodified lines
1099	return 0;	1107	return 0;
1100	}	1108	}
1101		1109
1102	static int skl_resume_prepare(struct drm_i915_private *dev_priv)
1103	{
1104	struct drm_device *dev = dev_priv->dev;
1105
1106	skl_init_cdclk(dev_priv);
1107	intel_csr_load_program(dev);
1108
1109	return 0;
1110	}
1111
1112	/*	1110	/*
1113	* Save all Gunit registers that may be lost after a D3 and a subsequent	1111	* Save all Gunit registers that may be lost after a D3 and a subsequent
1114	* S0i[R123] transition. The list of registers needing a save/restore is	1112	* S0i[R123] transition. The list of registers needing a save/restore is
@@ -1572,8 +1570,6 @@ static int intel_runtime_resume(struct device *device) · 457 unmodified lines
1572		1570
1573	if (IS_BROXTON(dev))	1571	if (IS_BROXTON(dev))
1574	ret = bxt_resume_prepare(dev_priv);	1572	ret = bxt_resume_prepare(dev_priv);
1575	else if (IS_SKYLAKE(dev))
1576	ret = skl_resume_prepare(dev_priv);
1577	else if (IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))	1573	else if (IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))
1578	hsw_disable_pc8(dev_priv);	1574	hsw_disable_pc8(dev_priv);
1579	else if (IS_VALLEYVIEW(dev_priv))	1575	else if (IS_VALLEYVIEW(dev_priv))
@@ -1616,8 +1612,6 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) · 36 unmodified lines
1616		1612
1617	if (IS_BROXTON(dev_priv))	1613	if (IS_BROXTON(dev_priv))
1618	ret = bxt_suspend_complete(dev_priv);	1614	ret = bxt_suspend_complete(dev_priv);
1619	else if (IS_SKYLAKE(dev_priv))
1620	ret = skl_suspend_complete(dev_priv);
1621	else if (IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))	1615	else if (IS_HASWELL(dev_priv) \|\| IS_BROADWELL(dev_priv))
1622	ret = hsw_suspend_complete(dev_priv);	1616	ret = hsw_suspend_complete(dev_priv);
1623	else if (IS_VALLEYVIEW(dev_priv))	1617	else if (IS_VALLEYVIEW(dev_priv))

drivers/gpu/drm/i915/i915_drv.h+108−80

 #define DRIVER_NAME		"i915"
 #define DRIVER_DESC		"Intel Graphics"
-#define DRIVER_DATE		"20151010"
+#define DRIVER_DATE		"20151120"
 #undef WARN_ON
 /* Many gcc seem to no see through this and fall over :( */
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
 	POWER_DOMAIN_TRANSCODER_EDP,
-	POWER_DOMAIN_PORT_DDI_A_2_LANES,
+	POWER_DOMAIN_PORT_DDI_A_LANES,
-	POWER_DOMAIN_PORT_DDI_A_4_LANES,
+	POWER_DOMAIN_PORT_DDI_B_LANES,
-	POWER_DOMAIN_PORT_DDI_B_2_LANES,
+	POWER_DOMAIN_PORT_DDI_C_LANES,
-	POWER_DOMAIN_PORT_DDI_B_4_LANES,
+	POWER_DOMAIN_PORT_DDI_D_LANES,
-	POWER_DOMAIN_PORT_DDI_C_2_LANES,
+	POWER_DOMAIN_PORT_DDI_E_LANES,
-	POWER_DOMAIN_PORT_DDI_C_4_LANES,
-	POWER_DOMAIN_PORT_DDI_D_2_LANES,
-	POWER_DOMAIN_PORT_DDI_D_4_LANES,
-	POWER_DOMAIN_PORT_DDI_E_2_LANES,
 	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_PORT_CRT,
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_AUX_D,
 	POWER_DOMAIN_GMBUS,
+	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_INIT,
 	POWER_DOMAIN_NUM,
 	list_for_each_entry(intel_plane,				\
 			    &(dev)->mode_config.plane_list,		\
 			    base.head)					\
-		if ((intel_plane)->pipe == (intel_crtc)->pipe)
+		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
 #define for_each_intel_crtc(dev, intel_crtc) \
 	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
-		if ((intel_encoder)->base.crtc == (__crtc))
+		for_each_if ((intel_encoder)->base.crtc == (__crtc))
 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
-		if ((intel_connector)->base.encoder == (__encoder))
+		for_each_if ((intel_connector)->base.encoder == (__encoder))
 #define for_each_power_domain(domain, mask)				\
 	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
-		if ((1 << (domain)) & (mask))
+		for_each_if ((1 << (domain)) & (mask))
 struct drm_i915_private;
 struct i915_mm_struct;
 			  int target, int refclk,
 			  struct dpll *match_clock,
 			  struct dpll *best_clock);
+	int (*compute_pipe_wm)(struct intel_crtc *crtc,
+			       struct drm_atomic_state *state);
 	void (*update_wm)(struct drm_crtc *crtc);
-	void (*update_sprite_wm)(struct drm_plane *plane,
-				 struct drm_crtc *crtc,
-				 uint32_t sprite_width, uint32_t sprite_height,
-				 int pixel_size, bool enable, bool scaled);
 	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
 	/* Returns the active state of the crtc, and if the crtc is active,
 	void (*force_wake_put)(struct drm_i915_private *dev_priv,
 							enum forcewake_domains domains);
-	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
+	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
-	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
+	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
-	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
+	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
-	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
+	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
-	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
 				uint8_t val, bool trace);
-	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
 				uint16_t val, bool trace);
-	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
 				uint32_t val, bool trace);
-	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
 				uint64_t val, bool trace);
 };
 		enum forcewake_domain_id id;
 		unsigned wake_count;
 		struct timer_list timer;
-		u32 reg_set;
+		i915_reg_t reg_set;
 		u32 val_set;
 		u32 val_clear;
-		u32 reg_ack;
+		i915_reg_t reg_ack;
-		u32 reg_post;
+		i915_reg_t reg_post;
 		u32 val_reset;
 	} fw_domain[FW_DOMAIN_ID_COUNT];
 };
 	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
 	     (i__) < FW_DOMAIN_ID_COUNT; \
 	     (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
-		if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
+		for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
 #define for_each_fw_domain(domain__, dev_priv__, i__) \
 	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
-enum csr_state {
+#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
-	FW_UNINITIALIZED = 0,
+#define CSR_VERSION_MAJOR(version)	((version) >> 16)
-	FW_LOADED,
+#define CSR_VERSION_MINOR(version)	((version) & 0xffff)
-	FW_FAILED
-};
 struct intel_csr {
+	struct work_struct work;
 	const char *fw_path;
 	uint32_t *dmc_payload;
 	uint32_t dmc_fw_size;
+	uint32_t version;
 	uint32_t mmio_count;
-	uint32_t mmioaddr[8];
+	i915_reg_t mmioaddr[8];
 	uint32_t mmiodata[8];
-	enum csr_state state;
 };
 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 	func(is_valleyview) sep \
 	func(is_haswell) sep \
 	func(is_skylake) sep \
+	func(is_broxton) sep \
+	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
 	func(has_pipe_cxsr) sep \
 		struct drm_framebuffer *fb;
 	} *fbc_work;
-	enum no_fbc_reason {
+	const char *no_fbc_reason;
-		FBC_OK, /* FBC is enabled */
-		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
-		FBC_NO_OUTPUT, /* no outputs enabled to compress */
-		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
-		FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
-		FBC_MODE_TOO_LARGE, /* mode too large for compression */
-		FBC_BAD_PLANE, /* fbc not supported on plane */
-		FBC_NOT_TILED, /* buffer not tiled */
-		FBC_MULTIPLE_PIPES, /* more than one pipe active */
-		FBC_MODULE_PARAM,
-		FBC_CHIP_DEFAULT, /* disabled by default on this chip */
-		FBC_ROTATION, /* rotation is not supported */
-		FBC_IN_DBG_MASTER, /* kernel debugger is active */
-		FBC_BAD_STRIDE, /* stride is not supported */
-		FBC_PIXEL_RATE, /* pixel rate is too big */
-		FBC_PIXEL_FORMAT /* pixel format is invalid */
-	} no_fbc_reason;
 	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
 	void (*enable_fbc)(struct intel_crtc *crtc);
 	struct i2c_adapter adapter;
 	u32 force_bit;
 	u32 reg0;
-	u32 gpio_reg;
+	i915_reg_t gpio_reg;
 	struct i2c_algo_bit_data bit_algo;
 	struct drm_i915_private *dev_priv;
 };
 };
 struct i915_wa_reg {
-	u32 addr;
+	i915_reg_t addr;
 	u32 value;
 	/* bitmask representing WA bits */
 	u32 mask;
 	struct drm_i915_gem_request     *request;
 };
+/* used in computing the new watermarks state */
+struct intel_wm_config {
+	unsigned int num_pipes_active;
+	bool sprites_enabled;
+	bool sprites_scaled;
+};
 struct drm_i915_private {
 	struct drm_device *dev;
 	struct kmem_cache *objects;
 	struct intel_csr csr;
-	/* Display CSR-related protection */
-	struct mutex csr_lock;
 	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
 	/* MMIO base address for MIPI regs */
 	uint32_t mipi_mmio_base;
+	uint32_t psr_mmio_base;
 	wait_queue_head_t gmbus_wait_queue;
 	struct pci_dev *bridge_dev;
 		 */
 		uint16_t skl_latency[8];
+		/* Committed wm config */
+		struct intel_wm_config config;
 		/*
 		 * The skl_wm_values structure is a bit too big for stack
 		 * allocation, so we keep the staging struct where we store
 	/* perform PHY state sanity checks? */
 	bool chv_phy_assert[2];
+	struct intel_encoder *dig_port_map[I915_MAX_PORTS];
 	/*
 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 	 * will be rejected. Instead look for a better place.
 /* Iterate over initialised rings */
 #define for_each_ring(ring__, dev_priv__, i__) \
 	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
-		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
+		for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
 enum hdmi_force_audio {
 	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
 #define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
 #define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
+#define REVID_FOREVER		0xff
+/*
+ * Return true if revision is in range [since,until] inclusive.
+ *
+ * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
+ */
+#define IS_REVID(p, since, until) \
+	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 #define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
 #define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
 #define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
 #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
-#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
+#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
+#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
-#define SKL_REVID_A0		(0x0)
+#define SKL_REVID_A0		0x0
-#define SKL_REVID_B0		(0x1)
+#define SKL_REVID_B0		0x1
-#define SKL_REVID_C0		(0x2)
+#define SKL_REVID_C0		0x2
-#define SKL_REVID_D0		(0x3)
+#define SKL_REVID_D0		0x3
-#define SKL_REVID_E0		(0x4)
+#define SKL_REVID_E0		0x4
-#define SKL_REVID_F0		(0x5)
+#define SKL_REVID_F0		0x5
+#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
-#define BXT_REVID_A0		(0x0)
+#define BXT_REVID_A0		0x0
-#define BXT_REVID_B0		(0x3)
+#define BXT_REVID_A1		0x1
-#define BXT_REVID_C0		(0x9)
+#define BXT_REVID_B0		0x3
+#define BXT_REVID_C0		0x9
+#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
 /*
  * The genX designation typically refers to the render engine, so render
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
 				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
-				 IS_SKYLAKE(dev))
+				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
-				 IS_SKYLAKE(dev))
+				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 	int panel_use_ssc;
 	int vbt_sdvo_panel_type;
 	int enable_rc6;
+	int enable_dc;
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
-void i915_firmware_load_error_print(const char *fw_path, int err);
 /* intel_hotplug.c */
 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
 int __must_check
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 				     u32 alignment,
-				     struct intel_engine_cs *pipelined,
-				     struct drm_i915_gem_request **pipelined_request,
 				     const struct i915_ggtt_view *view);
 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
 					      const struct i915_ggtt_view *view);
 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
 				  bool enable);
 extern void intel_detect_pch(struct drm_device *dev);
-extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 extern int intel_enable_rc6(const struct drm_device *dev);
 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
 #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
+#define __raw_read(x, s) \
+static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
+					     i915_reg_t reg) \
+{ \
+	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
+}
+#define __raw_write(x, s) \
+static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
+				       i915_reg_t reg, uint##x##_t val) \
+{ \
+	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
+#undef __raw_read
+#undef __raw_write
 /* These are untraced mmio-accessors that are only valid to be used inside
  * criticial sections inside IRQ handlers where forcewake is explicitly
  * controlled.
  * Note: Should only be used between intel_uncore_forcewake_irqlock() and
  * intel_uncore_forcewake_irqunlock().
  */
-#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
+#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
-#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
+#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
 /* "Broadcast RGB" property */
 #define INTEL_BROADCAST_RGB_FULL 1
 #define INTEL_BROADCAST_RGB_LIMITED 2
-static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
+static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
 {
 	if (IS_VALLEYVIEW(dev))
 		return VLV_VGACNTRL;

drivers/gpu/drm/i915/i915_gem.c+37−36

 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
 					struct intel_engine_cs *ring)
 {
+	struct intel_ringbuffer *buffer;
 	while (!list_empty(&ring->active_list)) {
 		struct drm_i915_gem_object *obj;
 	 * are the ones that keep the context and ringbuffer backing objects
 	 * pinned in place.
 	 */
-	while (!list_empty(&ring->execlist_queue)) {
-		struct drm_i915_gem_request *submit_req;
-		submit_req = list_first_entry(&ring->execlist_queue,
+	if (i915.enable_execlists) {
-				struct drm_i915_gem_request,
+		spin_lock_irq(&ring->execlist_lock);
-				execlist_link);
+		while (!list_empty(&ring->execlist_queue)) {
-		list_del(&submit_req->execlist_link);
+			struct drm_i915_gem_request *submit_req;
+			submit_req = list_first_entry(&ring->execlist_queue,
+					struct drm_i915_gem_request,
+					execlist_link);
+			list_del(&submit_req->execlist_link);
-		if (submit_req->ctx != ring->default_context)
+			if (submit_req->ctx != ring->default_context)
-			intel_lr_context_unpin(submit_req);
+				intel_lr_context_unpin(submit_req);
-		i915_gem_request_unreference(submit_req);
+			i915_gem_request_unreference(submit_req);
+		}
+		spin_unlock_irq(&ring->execlist_lock);
 	}
 	/*
 		i915_gem_request_retire(request);
 	}
+	/* Having flushed all requests from all queues, we know that all
+	 * ringbuffers must now be empty. However, since we do not reclaim
+	 * all space when retiring the request (to prevent HEADs colliding
+	 * with rapid ringbuffer wraparound) the amount of available space
+	 * upon reset is less than when we start. Do one more pass over
+	 * all the ringbuffers to reset last_retired_head.
+	 */
+	list_for_each_entry(buffer, &ring->buffers, link) {
+		buffer->last_retired_head = buffer->tail;
+		intel_ring_update_space(buffer);
+	}
 }
 void i915_gem_reset(struct drm_device *dev)
 		 * cacheline, whereas normally such cachelines would get
 		 * invalidated.
 		 */
-		if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)
+		if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 			return -ENODEV;
 		level = I915_CACHE_LLC;
 int
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 				     u32 alignment,
-				     struct intel_engine_cs *pipelined,
-				     struct drm_i915_gem_request **pipelined_request,
 				     const struct i915_ggtt_view *view)
 {
 	u32 old_read_domains, old_write_domain;
 	int ret;
-	ret = i915_gem_object_sync(obj, pipelined, pipelined_request);
-	if (ret)
-		return ret;
 	/* Mark the pin_display early so that we account for the
 	 * display coherency whilst setting up the cache domains.
 	 */
 {
 	struct i915_vma *vma;
 	list_for_each_entry(vma, &obj->vma_list, vma_link) {
-		if (i915_is_ggtt(vma->vm) &&
+		if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
-		    vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
+		    vma->vm == vm)
-			continue;
-		if (vma->vm == vm)
 			return vma;
 	}
 	return NULL;
 	struct intel_engine_cs *ring = req->ring;
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
 	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
 	int i, ret;
 	 * here because no other code should access these registers other than
 	 * at initialization time.
 	 */
-	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
+	for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-		intel_ring_emit(ring, reg_base + i);
+		intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
-		intel_ring_emit(ring, remap_info[i/4]);
+		intel_ring_emit(ring, remap_info[i]);
 	}
 	intel_ring_advance(ring);
 	if (HAS_GUC_UCODE(dev)) {
 		ret = intel_guc_ucode_load(dev);
 		if (ret) {
-			/*
+			DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
-			 * If we got an error and GuC submission is enabled, map
+			ret = -EIO;
-			 * the error to -EIO so the GPU will be declared wedged.
+			goto out;
-			 * OTOH, if we didn't intend to use the GuC anyway, just
-			 * discard the error and carry on.
-			 */
-			DRM_ERROR("Failed to initialize GuC, error %d%s\n", ret,
-				  i915.enable_guc_submission ? "" :
-				  " (ignored)");
-			ret = i915.enable_guc_submission ? -EIO : 0;
-			if (ret)
-				goto out;
 		}
 	}

drivers/gpu/drm/i915/i915_gem_context.c+10−2

 				if (signaller == ring)
 					continue;
-				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
+				intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base));
 				intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
 			}
 		}
 				if (signaller == ring)
 					continue;
-				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
+				intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base));
 				intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
 			}
 		}
 	case I915_CONTEXT_PARAM_NO_ZEROMAP:
 		args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
 		break;
+	case I915_CONTEXT_PARAM_GTT_SIZE:
+		if (ctx->ppgtt)
+			args->value = ctx->ppgtt->base.total;
+		else if (to_i915(dev)->mm.aliasing_ppgtt)
+			args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
+		else
+			args->value = to_i915(dev)->gtt.base.total;
+		break;
 	default:
 		ret = -EINVAL;
 		break;

drivers/gpu/drm/i915/i915_gem_execbuffer.c+2−2

@@ -1114,7 +1114,7 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev, · 1113 unmodified lines
1114		1114
1115	for (i = 0; i < 4; i++) {	1115	for (i = 0; i < 4; i++) {
1116	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));	1116	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1117	intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));	1117	intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1118	intel_ring_emit(ring, 0);	1118	intel_ring_emit(ring, 0);
1119	}	1119	}
1120		1120
@@ -1241,7 +1241,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, · 120 unmodified lines
1241		1241
1242	intel_ring_emit(ring, MI_NOOP);	1242	intel_ring_emit(ring, MI_NOOP);
1243	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));	1243	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1244	intel_ring_emit(ring, INSTPM);	1244	intel_ring_emit_reg(ring, INSTPM);
1245	intel_ring_emit(ring, instp_mask << 16 \| instp_mode);	1245	intel_ring_emit(ring, instp_mask << 16 \| instp_mode);
1246	intel_ring_advance(ring);	1246	intel_ring_advance(ring);
1247		1247

drivers/gpu/drm/i915/i915_gem_fence.c+1−1

@@ -59,7 +59,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg, · 58 unmodified lines
59	struct drm_i915_gem_object *obj)	59	struct drm_i915_gem_object *obj)
60	{	60	{
61	struct drm_i915_private *dev_priv = dev->dev_private;	61	struct drm_i915_private *dev_priv = dev->dev_private;
62	int fence_reg_lo, fence_reg_hi;	62	i915_reg_t fence_reg_lo, fence_reg_hi;
63	int fence_pitch_shift;	63	int fence_pitch_shift;
64		64
65	if (INTEL_INFO(dev)->gen >= 6) {	65	if (INTEL_INFO(dev)->gen >= 6) {

drivers/gpu/drm/i915/i915_gem_gtt.c+42−16

  */
 #include <linux/seq_file.h>
+#include <linux/stop_machine.h>
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 {
 	bool has_aliasing_ppgtt;
 	bool has_full_ppgtt;
+	bool has_full_48bit_ppgtt;
 	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
+	has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
 	if (intel_vgpu_active(dev))
 		has_full_ppgtt = false; /* emulation is too hard */
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
+	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+		return 3;
 #ifdef CONFIG_INTEL_IOMMU
 	/* Disable ppgtt on SNB if VT-d is on. */
 	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 	}
 	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
-		return 2;
+		return has_full_48bit_ppgtt ? 3 : 2;
 	else
 		return has_aliasing_ppgtt ? 1 : 0;
 }
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
+	intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(ring, entry));
 	intel_ring_emit(ring, upper_32_bits(addr));
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
+	intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(ring, entry));
 	intel_ring_emit(ring, lower_32_bits(addr));
 	intel_ring_advance(ring);
 	enum vgt_g2v_type msg;
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned int offset = vgtif_reg(pdp0_lo);
 	int i;
 	if (USES_FULL_48BIT_PPGTT(dev)) {
 		u64 daddr = px_dma(&ppgtt->pml4);
-		I915_WRITE(offset, lower_32_bits(daddr));
+		I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
-		I915_WRITE(offset + 4, upper_32_bits(daddr));
+		I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
 		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 			u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
-			I915_WRITE(offset, lower_32_bits(daddr));
+			I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
-			I915_WRITE(offset + 4, upper_32_bits(daddr));
+			I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
-			offset += 8;
 		}
 		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
-	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
+	intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(ring));
 	intel_ring_emit(ring, PP_DIR_DCLV_2G);
-	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
+	intel_ring_emit_reg(ring, RING_PP_DIR_BASE(ring));
 	intel_ring_emit(ring, get_pd_offset(ppgtt));
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
-	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
+	intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(ring));
 	intel_ring_emit(ring, PP_DIR_DCLV_2G);
-	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
+	intel_ring_emit_reg(ring, RING_PP_DIR_BASE(ring));
 	intel_ring_emit(ring, get_pd_offset(ppgtt));
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	return 0;
 }
+struct ggtt_bind_vma__cb {
+	struct i915_vma *vma;
+	enum i915_cache_level cache_level;
+	u32 flags;
+};
+static int ggtt_bind_vma__cb(void *_arg)
+{
+	struct ggtt_bind_vma__cb *arg = _arg;
+	return ggtt_bind_vma(arg->vma, arg->cache_level, arg->flags);
+}
+static int ggtt_bind_vma__BKL(struct i915_vma *vma,
+			      enum i915_cache_level cache_level,
+			      u32 flags)
+{
+	struct ggtt_bind_vma__cb arg = { vma, cache_level, flags };
+	return stop_machine(ggtt_bind_vma__cb, &arg, NULL);
+}
 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
 				 enum i915_cache_level cache_level,
 				 u32 flags)
 	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
 	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
+	if (IS_CHERRYVIEW(dev))
+		dev_priv->gtt.base.bind_vma = ggtt_bind_vma__BKL;
 	return ret;
 }
 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
 			  struct drm_i915_gem_object *obj)
 {
-	struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
+	struct intel_rotation_info *rot_info = &ggtt_view->params.rotation_info;
 	unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
 	unsigned int size_pages_uv;
 	struct sg_page_iter sg_iter;
 	if (view->type == I915_GGTT_VIEW_NORMAL) {
 		return obj->base.size;
 	} else if (view->type == I915_GGTT_VIEW_ROTATED) {
-		return view->rotation_info.size;
+		return view->params.rotation_info.size;
 	} else if (view->type == I915_GGTT_VIEW_PARTIAL) {
 		return view->params.partial.size << PAGE_SHIFT;
 	} else {

drivers/gpu/drm/i915/i915_gem_gtt.h+2−5

 			u64 offset;
 			unsigned int size;
 		} partial;
+		struct intel_rotation_info rotation_info;
 	} params;
 	struct sg_table *pages;
-	union {
-		struct intel_rotation_info rotation_info;
-	};
 };
 extern const struct i915_ggtt_view i915_ggtt_view_normal;
 	if (a->type != b->type)
 		return false;
-	if (a->type == I915_GGTT_VIEW_PARTIAL)
+	if (a->type != I915_GGTT_VIEW_NORMAL)
 		return !memcmp(&a->params, &b->params, sizeof(a->params));
 	return true;
 }

drivers/gpu/drm/i915/i915_gem_stolen.c+2−1

 					 &reserved_size);
 		break;
 	default:
-		if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+		if (IS_BROADWELL(dev_priv) ||
+		    IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
 			bdw_get_stolen_reserved(dev_priv, &reserved_base,
 						&reserved_size);
 		else

drivers/gpu/drm/i915/i915_gem_tiling.c+4−0

 		return -EINVAL;
 	}
+	intel_runtime_pm_get(dev_priv);
 	mutex_lock(&dev->struct_mutex);
 	if (obj->pin_display || obj->framebuffer_references) {
 		ret = -EBUSY;
 	drm_gem_object_unreference(&obj->base);
 	mutex_unlock(&dev->struct_mutex);
+	intel_runtime_pm_put(dev_priv);
 	return ret;
 }

drivers/gpu/drm/i915/i915_gpu_error.c+35−5

 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+	if (HAS_CSR(dev)) {
+		struct intel_csr *csr = &dev_priv->csr;
+		err_printf(m, "DMC loaded: %s\n",
+			   yesno(csr->dmc_payload != NULL));
+		err_printf(m, "DMC fw version: %d.%d\n",
+			   CSR_VERSION_MAJOR(csr->version),
+			   CSR_VERSION_MINOR(csr->version));
+	}
 	err_printf(m, "EIR: 0x%08x\n", error->eir);
 	err_printf(m, "IER: 0x%08x\n", error->ier);
 	if (INTEL_INFO(dev)->gen >= 8) {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (INTEL_INFO(dev)->gen >= 6) {
-		ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
+		ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
 		ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
 		if (INTEL_INFO(dev)->gen >= 8)
 			gen8_record_semaphore_state(dev_priv, error, ring, ering);
 	ering->ctl = I915_READ_CTL(ring);
 	if (I915_NEED_GFX_HWS(dev)) {
-		int mmio;
+		i915_reg_t mmio;
 		if (IS_GEN7(dev)) {
 			switch (ring->id) {
 		list_for_each_entry(request, &ring->request_list, list) {
 			struct drm_i915_error_request *erq;
+			if (count >= error->ring[i].num_requests) {
+				/*
+				 * If the ring request list was changed in
+				 * between the point where the error request
+				 * list was created and dimensioned and this
+				 * point then just exit early to avoid crashes.
+				 *
+				 * We don't need to communicate that the
+				 * request list changed state during error
+				 * state capture and that the error state is
+				 * slightly incorrect as a consequence since we
+				 * are typically only interested in the request
+				 * list state at the point of error state
+				 * capture, not in any changes happening during
+				 * the capture.
+				 */
+				break;
+			}
 			erq = &error->ring[i].requests[count++];
 			erq->seqno = request->seqno;
 			erq->jiffies = request->emitted_jiffies;
 	if (IS_VALLEYVIEW(dev)) {
 		error->gtier[0] = I915_READ(GTIER);
 		error->ier = I915_READ(VLV_IER);
-		error->forcewake = I915_READ(FORCEWAKE_VLV);
+		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
 	}
 	if (IS_GEN7(dev))
 	}
 	if (IS_GEN6(dev)) {
-		error->forcewake = I915_READ(FORCEWAKE);
+		error->forcewake = I915_READ_FW(FORCEWAKE);
 		error->gab_ctl = I915_READ(GAB_CTL);
 		error->gfx_mode = I915_READ(GFX_MODE);
 	}
 	/* 2: Registers which belong to multiple generations */
 	if (INTEL_INFO(dev)->gen >= 7)
-		error->forcewake = I915_READ(FORCEWAKE_MT);
+		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
 	if (INTEL_INFO(dev)->gen >= 6) {
 		error->derrmr = I915_READ(DERRMR);

drivers/gpu/drm/i915/i915_guc_reg.h+27−26

@@ -26,7 +26,7 @@ · 25 unmodified lines
26		26
27	/* Definitions of GuC H/W registers, bits, etc */	27	/* Definitions of GuC H/W registers, bits, etc */
28		28
29	#define GUC_STATUS 0xc000	29	#define GUC_STATUS _MMIO(0xc000)
30	#define GS_BOOTROM_SHIFT 1	30	#define GS_BOOTROM_SHIFT 1
31	#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)	31	#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
32	#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)	32	#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
@@ -39,40 +39,41 @@ · 6 unmodified lines
39	#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)	39	#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
40	#define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT)	40	#define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT)
41		41
42	#define SOFT_SCRATCH(n) (0xc180 + ((n) * 4))	42	#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
43		43
44	#define UOS_RSA_SCRATCH(i) (0xc200 + (i) * 4)	44	#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
45	#define DMA_ADDR_0_LOW 0xc300	45	#define UOS_RSA_SCRATCH_MAX_COUNT 64
46	#define DMA_ADDR_0_HIGH 0xc304	46	#define DMA_ADDR_0_LOW _MMIO(0xc300)
47	#define DMA_ADDR_1_LOW 0xc308	47	#define DMA_ADDR_0_HIGH _MMIO(0xc304)
48	#define DMA_ADDR_1_HIGH 0xc30c	48	#define DMA_ADDR_1_LOW _MMIO(0xc308)
		49	#define DMA_ADDR_1_HIGH _MMIO(0xc30c)
49	#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)	50	#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
50	#define DMA_ADDRESS_SPACE_GTT (8 << 16)	51	#define DMA_ADDRESS_SPACE_GTT (8 << 16)
51	#define DMA_COPY_SIZE 0xc310	52	#define DMA_COPY_SIZE _MMIO(0xc310)
52	#define DMA_CTRL 0xc314	53	#define DMA_CTRL _MMIO(0xc314)
53	#define UOS_MOVE (1<<4)	54	#define UOS_MOVE (1<<4)
54	#define START_DMA (1<<0)	55	#define START_DMA (1<<0)
55	#define DMA_GUC_WOPCM_OFFSET 0xc340	56	#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
56	#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */	57	#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
57	#define GUC_MAX_IDLE_COUNT 0xC3E4	58	#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
58		59
59	#define GUC_WOPCM_SIZE 0xc050	60	#define GUC_WOPCM_SIZE _MMIO(0xc050)
60	#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */	61	#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
61		62
62	/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */	63	/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
63	#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)	64	#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
64		65
65	#define GEN8_GT_PM_CONFIG 0x138140	66	#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
66	#define GEN9LP_GT_PM_CONFIG 0x138140	67	#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
67	#define GEN9_GT_PM_CONFIG 0x13816c	68	#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
68	#define GT_DOORBELL_ENABLE (1<<0)	69	#define GT_DOORBELL_ENABLE (1<<0)
69		70
70	#define GEN8_GTCR 0x4274	71	#define GEN8_GTCR _MMIO(0x4274)
71	#define GEN8_GTCR_INVALIDATE (1<<0)	72	#define GEN8_GTCR_INVALIDATE (1<<0)
72		73
73	#define GUC_ARAT_C6DIS 0xA178	74	#define GUC_ARAT_C6DIS _MMIO(0xA178)
74		75
75	#define GUC_SHIM_CONTROL 0xc064	76	#define GUC_SHIM_CONTROL _MMIO(0xc064)
76	#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)	77	#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
77	#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)	78	#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
78	#define GUC_ENABLE_MIA_CACHING (1<<2)	79	#define GUC_ENABLE_MIA_CACHING (1<<2)
@@ -89,21 +90,21 @@ · 10 unmodified lines
89	GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA \| \	90	GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA \| \
90	GUC_ENABLE_MIA_CLOCK_GATING)	91	GUC_ENABLE_MIA_CLOCK_GATING)
91		92
92	#define HOST2GUC_INTERRUPT 0xc4c8	93	#define HOST2GUC_INTERRUPT _MMIO(0xc4c8)
93	#define HOST2GUC_TRIGGER (1<<0)	94	#define HOST2GUC_TRIGGER (1<<0)
94		95
95	#define DRBMISC1 0x1984	96	#define DRBMISC1 0x1984
96	#define DOORBELL_ENABLE (1<<0)	97	#define DOORBELL_ENABLE (1<<0)
97		98
98	#define GEN8_DRBREGL(x) (0x1000 + (x) * 8)	99	#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
99	#define GEN8_DRB_VALID (1<<0)	100	#define GEN8_DRB_VALID (1<<0)
100	#define GEN8_DRBREGU(x) (GEN8_DRBREGL(x) + 4)	101	#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
101		102
102	#define DE_GUCRMR 0x44054	103	#define DE_GUCRMR _MMIO(0x44054)
103		104
104	#define GUC_BCS_RCS_IER 0xC550	105	#define GUC_BCS_RCS_IER _MMIO(0xC550)
105	#define GUC_VCS2_VCS1_IER 0xC554	106	#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
106	#define GUC_WD_VECS_IER 0xC558	107	#define GUC_WD_VECS_IER _MMIO(0xC558)
107	#define GUC_PM_P24C_IER 0xC55C	108	#define GUC_PM_P24C_IER _MMIO(0xC55C)
108		109
109	#endif	110	#endif

drivers/gpu/drm/i915/i915_guc_submission.c+8−8

 #include "intel_guc.h"
 /**
- * DOC: GuC Client
+ * DOC: GuC-based command submission
  *
  * i915_guc_client:
  * We use the term client to avoid confusion with contexts. A i915_guc_client is
 	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
 	/* WaRsDisableCoarsePowerGating:skl,bxt */
 	if (!intel_enable_rc6(dev_priv->dev) ||
-	    (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
-	    (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) ||
+	    (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) ||
-	    (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+	    (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
 		data[1] = 0;
 	else
 		/* bit 0 and 1 are for Render and Media domain separately */
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct guc_doorbell_info *doorbell;
 	void *base;
-	int drbreg = GEN8_DRBREGL(client->doorbell_id);
+	i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id);
 	int value;
 	base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
 /**
  * i915_guc_submit() - Submit commands through GuC
  * @client:	the guc client where commands will go through
- * @ctx:	LRC where commands come from
+ * @rq:		request associated with the commands
- * @ring:	HW engine that will excute the commands
  *
  * Return:	0 if succeed
  */
  * 		The kernel client to replace ExecList submission is created with
  * 		NORMAL priority. Priority of a client for scheduler can be HIGH,
  * 		while a preemption context can use CRITICAL.
- * @ctx		the context to own the client (we use the default render context)
+ * @ctx:	the context that owns the client (we use the default render
+ * 		context)
  *
  * Return:	An i915_guc_client object if success.
  */

drivers/gpu/drm/i915/i915_irq.c+59−58

@@ -139,7 +139,8 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { · 138 unmodified lines
139	/*	139	/*
140	* We should clear IMR at preinstall/uninstall, and just check at postinstall.	140	* We should clear IMR at preinstall/uninstall, and just check at postinstall.
141	*/	141	*/
142	static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)	142	static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
		143	i915_reg_t reg)
143	{	144	{
144	u32 val = I915_READ(reg);	145	u32 val = I915_READ(reg);
145		146
@@ -147,7 +148,7 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg) · 1 unmodified line
147	return;	148	return;
148		149
149	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",	150	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
150	reg, val);	151	i915_mmio_reg_offset(reg), val);
151	I915_WRITE(reg, 0xffffffff);	152	I915_WRITE(reg, 0xffffffff);
152	POSTING_READ(reg);	153	POSTING_READ(reg);
153	I915_WRITE(reg, 0xffffffff);	154	I915_WRITE(reg, 0xffffffff);
@@ -283,17 +284,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) · 129 unmodified lines
283	ilk_update_gt_irq(dev_priv, mask, 0);	284	ilk_update_gt_irq(dev_priv, mask, 0);
284	}	285	}
285		286
286	static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)	287	static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
287	{	288	{
288	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;	289	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
289	}	290	}
290		291
291	static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)	292	static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
292	{	293	{
293	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;	294	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
294	}	295	}
295		296
296	static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)	297	static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
297	{	298	{
298	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;	299	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
299	}	300	}
@@ -350,7 +351,7 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) · 50 unmodified lines
350	void gen6_reset_rps_interrupts(struct drm_device *dev)	351	void gen6_reset_rps_interrupts(struct drm_device *dev)
351	{	352	{
352	struct drm_i915_private *dev_priv = dev->dev_private;	353	struct drm_i915_private *dev_priv = dev->dev_private;
353	uint32_t reg = gen6_pm_iir(dev_priv);	354	i915_reg_t reg = gen6_pm_iir(dev_priv);
354		355
355	spin_lock_irq(&dev_priv->irq_lock);	356	spin_lock_irq(&dev_priv->irq_lock);
356	I915_WRITE(reg, dev_priv->pm_rps_events);	357	I915_WRITE(reg, dev_priv->pm_rps_events);
@@ -477,7 +478,7 @@ static void · 120 unmodified lines
477	__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,	478	__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
478	u32 enable_mask, u32 status_mask)	479	u32 enable_mask, u32 status_mask)
479	{	480	{
480	u32 reg = PIPESTAT(pipe);	481	i915_reg_t reg = PIPESTAT(pipe);
481	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;	482	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
482		483
483	assert_spin_locked(&dev_priv->irq_lock);	484	assert_spin_locked(&dev_priv->irq_lock);
@@ -504,7 +505,7 @@ static void · 20 unmodified lines
504	__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,	505	__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
505	u32 enable_mask, u32 status_mask)	506	u32 enable_mask, u32 status_mask)
506	{	507	{
507	u32 reg = PIPESTAT(pipe);	508	i915_reg_t reg = PIPESTAT(pipe);
508	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;	509	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
509		510
510	assert_spin_locked(&dev_priv->irq_lock);	511	assert_spin_locked(&dev_priv->irq_lock);
@@ -665,8 +666,7 @@ static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) · 154 unmodified lines
665	static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)	666	static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
666	{	667	{
667	struct drm_i915_private *dev_priv = dev->dev_private;	668	struct drm_i915_private *dev_priv = dev->dev_private;
668	unsigned long high_frame;	669	i915_reg_t high_frame, low_frame;
669	unsigned long low_frame;
670	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;	670	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
671	struct intel_crtc *intel_crtc =	671	struct intel_crtc *intel_crtc =
672	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);	672	to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
@@ -717,9 +717,7 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) · 44 unmodified lines
717	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));	717	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
718	}	718	}
719		719
720	/* raw reads, only for fast reads of display block, no need for forcewake etc. */	720	/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
721	#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
722
723	static int __intel_get_crtc_scanline(struct intel_crtc *crtc)	721	static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
724	{	722	{
725	struct drm_device *dev = crtc->base.dev;	723	struct drm_device *dev = crtc->base.dev;
@@ -733,9 +731,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) · 7 unmodified lines
733	vtotal /= 2;	731	vtotal /= 2;
734		732
735	if (IS_GEN2(dev))	733	if (IS_GEN2(dev))
736	position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;	734	position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
737	else	735	else
738	position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;	736	position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
739		737
740	/*	738	/*
741	* On HSW, the DSL reg (0x70000) appears to return 0 if we	739	* On HSW, the DSL reg (0x70000) appears to return 0 if we
@@ -827,7 +825,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, · 85 unmodified lines
827	* We can split this into vertical and horizontal	825	* We can split this into vertical and horizontal
828	* scanout position.	826	* scanout position.
829	*/	827	*/
830	position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;	828	position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
831		829
832	/* convert to pixel counts */	830	/* convert to pixel counts */
833	vbl_start *= htotal;	831	vbl_start *= htotal;
@@ -1188,7 +1186,7 @@ static void ivybridge_parity_work(struct work_struct *work) · 354 unmodified lines
1188	POSTING_READ(GEN7_MISCCPCTL);	1186	POSTING_READ(GEN7_MISCCPCTL);
1189		1187
1190	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {	1188	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1191	u32 reg;	1189	i915_reg_t reg;
1192		1190
1193	slice--;	1191	slice--;
1194	if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))	1192	if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
@@ -1196,7 +1194,7 @@ static void ivybridge_parity_work(struct work_struct *work) · 1 unmodified line
1196		1194
1197	dev_priv->l3_parity.which_slice &= ~(1<<slice);	1195	dev_priv->l3_parity.which_slice &= ~(1<<slice);
1198		1196
1199	reg = GEN7_L3CDERRST1 + (slice * 0x200);	1197	reg = GEN7_L3CDERRST1(slice);
1200		1198
1201	error_status = I915_READ(reg);	1199	error_status = I915_READ(reg);
1202	row = GEN7_PARITY_ERROR_ROW(error_status);	1200	row = GEN7_PARITY_ERROR_ROW(error_status);
@@ -1290,70 +1288,69 @@ static void snb_gt_irq_handler(struct drm_device *dev, · 87 unmodified lines
1290	ivybridge_parity_error_irq_handler(dev, gt_iir);	1288	ivybridge_parity_error_irq_handler(dev, gt_iir);
1291	}	1289	}
1292		1290
		1291	static __always_inline void
		1292	gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
		1293	{
		1294	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
		1295	notify_ring(ring);
		1296	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
		1297	intel_lrc_irq_handler(ring);
		1298	}
		1299
1293	static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,	1300	static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1294	u32 master_ctl)	1301	u32 master_ctl)
1295	{	1302	{
1296	irqreturn_t ret = IRQ_NONE;	1303	irqreturn_t ret = IRQ_NONE;
1297		1304
1298	if (master_ctl & (GEN8_GT_RCS_IRQ \| GEN8_GT_BCS_IRQ)) {	1305	if (master_ctl & (GEN8_GT_RCS_IRQ \| GEN8_GT_BCS_IRQ)) {
1299	u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));	1306	u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
1300	if (tmp) {	1307	if (iir) {
1301	I915_WRITE_FW(GEN8_GT_IIR(0), tmp);	1308	I915_WRITE_FW(GEN8_GT_IIR(0), iir);
1302	ret = IRQ_HANDLED;	1309	ret = IRQ_HANDLED;
1303		1310
1304	if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))	1311	gen8_cs_irq_handler(&dev_priv->ring[RCS],
1305	intel_lrc_irq_handler(&dev_priv->ring[RCS]);	1312	iir, GEN8_RCS_IRQ_SHIFT);
1306	if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1307	notify_ring(&dev_priv->ring[RCS]);
1308		1313
1309	if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))	1314	gen8_cs_irq_handler(&dev_priv->ring[BCS],
1310	intel_lrc_irq_handler(&dev_priv->ring[BCS]);	1315	iir, GEN8_BCS_IRQ_SHIFT);
1311	if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1312	notify_ring(&dev_priv->ring[BCS]);
1313	} else	1316	} else
1314	DRM_ERROR("The master control interrupt lied (GT0)!\n");	1317	DRM_ERROR("The master control interrupt lied (GT0)!\n");
1315	}	1318	}
1316		1319
1317	if (master_ctl & (GEN8_GT_VCS1_IRQ \| GEN8_GT_VCS2_IRQ)) {	1320	if (master_ctl & (GEN8_GT_VCS1_IRQ \| GEN8_GT_VCS2_IRQ)) {
1318	u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));	1321	u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
1319	if (tmp) {	1322	if (iir) {
1320	I915_WRITE_FW(GEN8_GT_IIR(1), tmp);	1323	I915_WRITE_FW(GEN8_GT_IIR(1), iir);
1321	ret = IRQ_HANDLED;	1324	ret = IRQ_HANDLED;
1322		1325
1323	if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))	1326	gen8_cs_irq_handler(&dev_priv->ring[VCS],
1324	intel_lrc_irq_handler(&dev_priv->ring[VCS]);	1327	iir, GEN8_VCS1_IRQ_SHIFT);
1325	if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1326	notify_ring(&dev_priv->ring[VCS]);
1327		1328
1328	if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))	1329	gen8_cs_irq_handler(&dev_priv->ring[VCS2],
1329	intel_lrc_irq_handler(&dev_priv->ring[VCS2]);	1330	iir, GEN8_VCS2_IRQ_SHIFT);
1330	if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1331	notify_ring(&dev_priv->ring[VCS2]);
1332	} else	1331	} else
1333	DRM_ERROR("The master control interrupt lied (GT1)!\n");	1332	DRM_ERROR("The master control interrupt lied (GT1)!\n");
1334	}	1333	}
1335		1334
1336	if (master_ctl & GEN8_GT_VECS_IRQ) {	1335	if (master_ctl & GEN8_GT_VECS_IRQ) {
1337	u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));	1336	u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
1338	if (tmp) {	1337	if (iir) {
1339	I915_WRITE_FW(GEN8_GT_IIR(3), tmp);	1338	I915_WRITE_FW(GEN8_GT_IIR(3), iir);
1340	ret = IRQ_HANDLED;	1339	ret = IRQ_HANDLED;
1341		1340
1342	if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))	1341	gen8_cs_irq_handler(&dev_priv->ring[VECS],
1343	intel_lrc_irq_handler(&dev_priv->ring[VECS]);	1342	iir, GEN8_VECS_IRQ_SHIFT);
1344	if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1345	notify_ring(&dev_priv->ring[VECS]);
1346	} else	1343	} else
1347	DRM_ERROR("The master control interrupt lied (GT3)!\n");	1344	DRM_ERROR("The master control interrupt lied (GT3)!\n");
1348	}	1345	}
1349		1346
1350	if (master_ctl & GEN8_GT_PM_IRQ) {	1347	if (master_ctl & GEN8_GT_PM_IRQ) {
1351	u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));	1348	u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
1352	if (tmp & dev_priv->pm_rps_events) {	1349	if (iir & dev_priv->pm_rps_events) {
1353	I915_WRITE_FW(GEN8_GT_IIR(2),	1350	I915_WRITE_FW(GEN8_GT_IIR(2),
1354	tmp & dev_priv->pm_rps_events);	1351	iir & dev_priv->pm_rps_events);
1355	ret = IRQ_HANDLED;	1352	ret = IRQ_HANDLED;
1356	gen6_rps_irq_handler(dev_priv, tmp);	1353	gen6_rps_irq_handler(dev_priv, iir);
1357	} else	1354	} else
1358	DRM_ERROR("The master control interrupt lied (PM)!\n");	1355	DRM_ERROR("The master control interrupt lied (PM)!\n");
1359	}	1356	}
@@ -1625,7 +1622,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) · 265 unmodified lines
1625		1622
1626	spin_lock(&dev_priv->irq_lock);	1623	spin_lock(&dev_priv->irq_lock);
1627	for_each_pipe(dev_priv, pipe) {	1624	for_each_pipe(dev_priv, pipe) {
1628	int reg;	1625	i915_reg_t reg;
1629	u32 mask, iir_bit = 0;	1626	u32 mask, iir_bit = 0;
1630		1627
1631	/*	1628	/*
@@ -2354,9 +2351,13 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) · 722 unmodified lines
2354	spt_irq_handler(dev, pch_iir);	2351	spt_irq_handler(dev, pch_iir);
2355	else	2352	else
2356	cpt_irq_handler(dev, pch_iir);	2353	cpt_irq_handler(dev, pch_iir);
2357	} else	2354	} else {
2358	DRM_ERROR("The master control interrupt lied (SDE)!\n");	2355	/*
2359		2356	* Like on previous PCH there seems to be something
		2357	* fishy going on with forwarding PCH interrupts.
		2358	*/
		2359	DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
		2360	}
2360	}	2361	}
2361		2362
2362	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);	2363	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
@@ -3869,7 +3870,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) · 1506 unmodified lines
3869	DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);	3870	DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3870		3871
3871	for_each_pipe(dev_priv, pipe) {	3872	for_each_pipe(dev_priv, pipe) {
3872	int reg = PIPESTAT(pipe);	3873	i915_reg_t reg = PIPESTAT(pipe);
3873	pipe_stats[pipe] = I915_READ(reg);	3874	pipe_stats[pipe] = I915_READ(reg);
3874		3875
3875	/*	3876	/*
@@ -4050,7 +4051,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) · 174 unmodified lines
4050	DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);	4051	DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4051		4052
4052	for_each_pipe(dev_priv, pipe) {	4053	for_each_pipe(dev_priv, pipe) {
4053	int reg = PIPESTAT(pipe);	4054	i915_reg_t reg = PIPESTAT(pipe);
4054	pipe_stats[pipe] = I915_READ(reg);	4055	pipe_stats[pipe] = I915_READ(reg);
4055		4056
4056	/* Clear the PIPESTAT regs before the IIR /	4057	/* Clear the PIPESTAT regs before the IIR /
@@ -4272,7 +4273,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) · 215 unmodified lines
4272	DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);	4273	DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4273		4274
4274	for_each_pipe(dev_priv, pipe) {	4275	for_each_pipe(dev_priv, pipe) {
4275	int reg = PIPESTAT(pipe);	4276	i915_reg_t reg = PIPESTAT(pipe);
4276	pipe_stats[pipe] = I915_READ(reg);	4277	pipe_stats[pipe] = I915_READ(reg);
4277		4278
4278	/*	4279	/*

drivers/gpu/drm/i915/i915_params.c+8−2

 	.panel_use_ssc = -1,
 	.vbt_sdvo_panel_type = -1,
 	.enable_rc6 = -1,
+	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
 	.enable_hangcheck = true,
 	"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
 	"default: -1 (use per-chip default)");
+module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400);
+MODULE_PARM_DESC(enable_dc,
+	"Enable power-saving display C-states. "
+	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
 module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
 MODULE_PARM_DESC(enable_fbc,
 	"Enable frame buffer compression for power savings "
 module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
 MODULE_PARM_DESC(enable_ppgtt,
 	"Override PPGTT usage. "
-	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
+	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
 module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
 MODULE_PARM_DESC(enable_execlists,
 MODULE_PARM_DESC(preliminary_hw_support,
 	"Enable preliminary hardware support.");
-module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0600);
+module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400);
 MODULE_PARM_DESC(disable_power_well,
 	"Disable display power wells when possible "
 	"(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");

drivers/gpu/drm/i915/i915_reg.h+1370−1372

@@ -25,14 +25,43 @@ · 24 unmodified lines
25	#ifndef _I915_REG_H_	25	#ifndef _I915_REG_H_
26	#define _I915_REG_H_	26	#define _I915_REG_H_
27		27
		28	typedef struct {
		29	uint32_t reg;
		30	} i915_reg_t;
		31
		32	#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
		33
		34	#define INVALID_MMIO_REG _MMIO(0)
		35
		36	static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
		37	{
		38	return reg.reg;
		39	}
		40
		41	static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
		42	{
		43	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
		44	}
		45
		46	static inline bool i915_mmio_reg_valid(i915_reg_t reg)
		47	{
		48	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
		49	}
		50
28	#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))	51	#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
		52	#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
29	#define _PLANE(plane, a, b) _PIPE(plane, a, b)	53	#define _PLANE(plane, a, b) _PIPE(plane, a, b)
30	#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))	54	#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
		55	#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
		56	#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
31	#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))	57	#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
		58	#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
32	#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \	59	#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33	(pipe) == PIPE_B ? (b) : (c))	60	(pipe) == PIPE_B ? (b) : (c))
		61	#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
34	#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \	62	#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35	(port) == PORT_B ? (b) : (c))	63	(port) == PORT_B ? (b) : (c))
		64	#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
36		65
37	#define _MASKED_FIELD(mask, value) ({ \	66	#define _MASKED_FIELD(mask, value) ({ \
38	if (__builtin_constant_p(mask)) \	67	if (__builtin_constant_p(mask)) \
@@ -105,14 +134,14 @@ · 66 unmodified lines
105	#define GRDOM_RESET_STATUS (1<<1)	134	#define GRDOM_RESET_STATUS (1<<1)
106	#define GRDOM_RESET_ENABLE (1<<0)	135	#define GRDOM_RESET_ENABLE (1<<0)
107		136
108	#define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)	137	#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
109	#define ILK_GRDOM_FULL (0<<1)	138	#define ILK_GRDOM_FULL (0<<1)
110	#define ILK_GRDOM_RENDER (1<<1)	139	#define ILK_GRDOM_RENDER (1<<1)
111	#define ILK_GRDOM_MEDIA (3<<1)	140	#define ILK_GRDOM_MEDIA (3<<1)
112	#define ILK_GRDOM_MASK (3<<1)	141	#define ILK_GRDOM_MASK (3<<1)
113	#define ILK_GRDOM_RESET_ENABLE (1<<0)	142	#define ILK_GRDOM_RESET_ENABLE (1<<0)
114		143
115	#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */	144	#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
116	#define GEN6_MBC_SNPCR_SHIFT 21	145	#define GEN6_MBC_SNPCR_SHIFT 21
117	#define GEN6_MBC_SNPCR_MASK (3<<21)	146	#define GEN6_MBC_SNPCR_MASK (3<<21)
118	#define GEN6_MBC_SNPCR_MAX (0<<21)	147	#define GEN6_MBC_SNPCR_MAX (0<<21)
@@ -120,31 +149,31 @@ · 1 unmodified line
120	#define GEN6_MBC_SNPCR_LOW (2<<21)	149	#define GEN6_MBC_SNPCR_LOW (2<<21)
121	#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */	150	#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
122		151
123	#define VLV_G3DCTL 0x9024	152	#define VLV_G3DCTL _MMIO(0x9024)
124	#define VLV_GSCKGCTL 0x9028	153	#define VLV_GSCKGCTL _MMIO(0x9028)
125		154
126	#define GEN6_MBCTL 0x0907c	155	#define GEN6_MBCTL _MMIO(0x0907c)
127	#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)	156	#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
128	#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)	157	#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
129	#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)	158	#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
130	#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)	159	#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
131	#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)	160	#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
132		161
133	#define GEN6_GDRST 0x941c	162	#define GEN6_GDRST _MMIO(0x941c)
134	#define GEN6_GRDOM_FULL (1 << 0)	163	#define GEN6_GRDOM_FULL (1 << 0)
135	#define GEN6_GRDOM_RENDER (1 << 1)	164	#define GEN6_GRDOM_RENDER (1 << 1)
136	#define GEN6_GRDOM_MEDIA (1 << 2)	165	#define GEN6_GRDOM_MEDIA (1 << 2)
137	#define GEN6_GRDOM_BLT (1 << 3)	166	#define GEN6_GRDOM_BLT (1 << 3)
138		167
139	#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)	168	#define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228)
140	#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)	169	#define RING_PP_DIR_BASE_READ(ring) _MMIO((ring)->mmio_base+0x518)
141	#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)	170	#define RING_PP_DIR_DCLV(ring) _MMIO((ring)->mmio_base+0x220)
142	#define PP_DIR_DCLV_2G 0xffffffff	171	#define PP_DIR_DCLV_2G 0xffffffff
143		172
144	#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))	173	#define GEN8_RING_PDP_UDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4)
145	#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)	174	#define GEN8_RING_PDP_LDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8)
146		175
147	#define GEN8_R_PWR_CLK_STATE 0x20C8	176	#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
148	#define GEN8_RPCS_ENABLE (1 << 31)	177	#define GEN8_RPCS_ENABLE (1 << 31)
149	#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)	178	#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
150	#define GEN8_RPCS_S_CNT_SHIFT 15	179	#define GEN8_RPCS_S_CNT_SHIFT 15
@@ -157,7 +186,7 @@ · 6 unmodified lines
157	#define GEN8_RPCS_EU_MIN_SHIFT 0	186	#define GEN8_RPCS_EU_MIN_SHIFT 0
158	#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)	187	#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
159		188
160	#define GAM_ECOCHK 0x4090	189	#define GAM_ECOCHK _MMIO(0x4090)
161	#define BDW_DISABLE_HDC_INVALIDATION (1<<25)	190	#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
162	#define ECOCHK_SNB_BIT (1<<10)	191	#define ECOCHK_SNB_BIT (1<<10)
163	#define ECOCHK_DIS_TLB (1<<8)	192	#define ECOCHK_DIS_TLB (1<<8)
@@ -170,15 +199,15 @@ · 6 unmodified lines
170	#define ECOCHK_PPGTT_WT_HSW (0x2<<3)	199	#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
171	#define ECOCHK_PPGTT_WB_HSW (0x3<<3)	200	#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
172		201
173	#define GAC_ECO_BITS 0x14090	202	#define GAC_ECO_BITS _MMIO(0x14090)
174	#define ECOBITS_SNB_BIT (1<<13)	203	#define ECOBITS_SNB_BIT (1<<13)
175	#define ECOBITS_PPGTT_CACHE64B (3<<8)	204	#define ECOBITS_PPGTT_CACHE64B (3<<8)
176	#define ECOBITS_PPGTT_CACHE4B (0<<8)	205	#define ECOBITS_PPGTT_CACHE4B (0<<8)
177		206
178	#define GAB_CTL 0x24000	207	#define GAB_CTL _MMIO(0x24000)
179	#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)	208	#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
180		209
181	#define GEN6_STOLEN_RESERVED 0x1082C0	210	#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
182	#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)	211	#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
183	#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)	212	#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
184	#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)	213	#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
@@ -200,6 +229,7 @@ · 15 unmodified lines
200	#define VGA_ST01_MDA 0x3ba	229	#define VGA_ST01_MDA 0x3ba
201	#define VGA_ST01_CGA 0x3da	230	#define VGA_ST01_CGA 0x3da
202		231
		232	#define _VGA_MSR_WRITE _MMIO(0x3c2)
203	#define VGA_MSR_WRITE 0x3c2	233	#define VGA_MSR_WRITE 0x3c2
204	#define VGA_MSR_READ 0x3cc	234	#define VGA_MSR_READ 0x3cc
205	#define VGA_MSR_MEM_EN (1<<1)	235	#define VGA_MSR_MEM_EN (1<<1)
@@ -377,10 +407,12 @@ · 171 unmodified lines
377	#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)	407	#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
378	#define MI_BATCH_RESOURCE_STREAMER (1<<10)	408	#define MI_BATCH_RESOURCE_STREAMER (1<<10)
379		409
380	#define MI_PREDICATE_SRC0 (0x2400)	410	#define MI_PREDICATE_SRC0 _MMIO(0x2400)
381	#define MI_PREDICATE_SRC1 (0x2408)	411	#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
		412	#define MI_PREDICATE_SRC1 _MMIO(0x2408)
		413	#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
382		414
383	#define MI_PREDICATE_RESULT_2 (0x2214)	415	#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
384	#define LOWER_SLICE_ENABLED (1<<0)	416	#define LOWER_SLICE_ENABLED (1<<0)
385	#define LOWER_SLICE_DISABLED (0<<0)	417	#define LOWER_SLICE_DISABLED (0<<0)
386		418
@@ -509,49 +541,61 @@ · 122 unmodified lines
509	/*	541	/*
510	* Registers used only by the command parser	542	* Registers used only by the command parser
511	*/	543	*/
512	#define BCS_SWCTRL 0x22200	544	#define BCS_SWCTRL _MMIO(0x22200)
513		545
514	#define GPGPU_THREADS_DISPATCHED 0x2290	546	#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
515	#define HS_INVOCATION_COUNT 0x2300	547	#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
516	#define DS_INVOCATION_COUNT 0x2308	548	#define HS_INVOCATION_COUNT _MMIO(0x2300)
517	#define IA_VERTICES_COUNT 0x2310	549	#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
518	#define IA_PRIMITIVES_COUNT 0x2318	550	#define DS_INVOCATION_COUNT _MMIO(0x2308)
519	#define VS_INVOCATION_COUNT 0x2320	551	#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
520	#define GS_INVOCATION_COUNT 0x2328	552	#define IA_VERTICES_COUNT _MMIO(0x2310)
521	#define GS_PRIMITIVES_COUNT 0x2330	553	#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
522	#define CL_INVOCATION_COUNT 0x2338	554	#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
523	#define CL_PRIMITIVES_COUNT 0x2340	555	#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
524	#define PS_INVOCATION_COUNT 0x2348	556	#define VS_INVOCATION_COUNT _MMIO(0x2320)
525	#define PS_DEPTH_COUNT 0x2350	557	#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
		558	#define GS_INVOCATION_COUNT _MMIO(0x2328)
		559	#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
		560	#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
		561	#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
		562	#define CL_INVOCATION_COUNT _MMIO(0x2338)
		563	#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
		564	#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
		565	#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
		566	#define PS_INVOCATION_COUNT _MMIO(0x2348)
		567	#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
		568	#define PS_DEPTH_COUNT _MMIO(0x2350)
		569	#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
526		570
527	/* There are the 4 64-bit counter registers, one for each stream output */	571	/* There are the 4 64-bit counter registers, one for each stream output */
528	#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)	572	#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
		573	#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
529		574
530	#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)	575	#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
		576	#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
531		577
532	#define GEN7_3DPRIM_END_OFFSET 0x2420	578	#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
533	#define GEN7_3DPRIM_START_VERTEX 0x2430	579	#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
534	#define GEN7_3DPRIM_VERTEX_COUNT 0x2434	580	#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
535	#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438	581	#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
536	#define GEN7_3DPRIM_START_INSTANCE 0x243C	582	#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
537	#define GEN7_3DPRIM_BASE_VERTEX 0x2440	583	#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
538		584
539	#define GEN7_GPGPU_DISPATCHDIMX 0x2500	585	#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
540	#define GEN7_GPGPU_DISPATCHDIMY 0x2504	586	#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
541	#define GEN7_GPGPU_DISPATCHDIMZ 0x2508	587	#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
542		588
543	#define OACONTROL 0x2360	589	#define OACONTROL _MMIO(0x2360)
544		590
545	#define _GEN7_PIPEA_DE_LOAD_SL 0x70068	591	#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
546	#define _GEN7_PIPEB_DE_LOAD_SL 0x71068	592	#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
547	#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \	593	#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
548	_GEN7_PIPEA_DE_LOAD_SL, \
549	_GEN7_PIPEB_DE_LOAD_SL)
550		594
551	/*	595	/*
552	* Reset registers	596	* Reset registers
553	*/	597	*/
554	#define DEBUG_RESET_I830 0x6070	598	#define DEBUG_RESET_I830 _MMIO(0x6070)
555	#define DEBUG_RESET_FULL (1<<7)	599	#define DEBUG_RESET_FULL (1<<7)
556	#define DEBUG_RESET_RENDER (1<<8)	600	#define DEBUG_RESET_RENDER (1<<8)
557	#define DEBUG_RESET_DISPLAY (1<<9)	601	#define DEBUG_RESET_DISPLAY (1<<9)
@@ -559,7 +603,7 @@ · 1 unmodified line
559	/*	603	/*
560	* IOSF sideband	604	* IOSF sideband
561	*/	605	*/
562	#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)	606	#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
563	#define IOSF_DEVFN_SHIFT 24	607	#define IOSF_DEVFN_SHIFT 24
564	#define IOSF_OPCODE_SHIFT 16	608	#define IOSF_OPCODE_SHIFT 16
565	#define IOSF_PORT_SHIFT 8	609	#define IOSF_PORT_SHIFT 8
@@ -576,8 +620,8 @@ · 10 unmodified lines
576	#define IOSF_PORT_CCU 0xA9	620	#define IOSF_PORT_CCU 0xA9
577	#define IOSF_PORT_GPS_CORE 0x48	621	#define IOSF_PORT_GPS_CORE 0x48
578	#define IOSF_PORT_FLISDSI 0x1B	622	#define IOSF_PORT_FLISDSI 0x1B
579	#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)	623	#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
580	#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)	624	#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
581		625
582	/* See configdb bunit SB addr map */	626	/* See configdb bunit SB addr map */
583	#define BUNIT_REG_BISOC 0x11	627	#define BUNIT_REG_BISOC 0x11
@@ -609,6 +653,7 @@ · 25 unmodified lines
609		653
610	/* See the PUNIT HAS v0.8 for the below bits */	654	/* See the PUNIT HAS v0.8 for the below bits */
611	enum punit_power_well {	655	enum punit_power_well {
		656	/* These numbers are fixed and must match the position of the pw bits */
612	PUNIT_POWER_WELL_RENDER = 0,	657	PUNIT_POWER_WELL_RENDER = 0,
613	PUNIT_POWER_WELL_MEDIA = 1,	658	PUNIT_POWER_WELL_MEDIA = 1,
614	PUNIT_POWER_WELL_DISP2D = 3,	659	PUNIT_POWER_WELL_DISP2D = 3,
@@ -621,10 +666,12 @@ enum punit_power_well { · 6 unmodified lines
621	PUNIT_POWER_WELL_DPIO_RX1 = 11,	666	PUNIT_POWER_WELL_DPIO_RX1 = 11,
622	PUNIT_POWER_WELL_DPIO_CMN_D = 12,	667	PUNIT_POWER_WELL_DPIO_CMN_D = 12,
623		668
624	PUNIT_POWER_WELL_NUM,	669	/* Not actual bit groups. Used as IDs for lookup_power_well() */
		670	PUNIT_POWER_WELL_ALWAYS_ON,
625	};	671	};
626		672
627	enum skl_disp_power_wells {	673	enum skl_disp_power_wells {
		674	/* These numbers are fixed and must match the position of the pw bits */
628	SKL_DISP_PW_MISC_IO,	675	SKL_DISP_PW_MISC_IO,
629	SKL_DISP_PW_DDI_A_E,	676	SKL_DISP_PW_DDI_A_E,
630	SKL_DISP_PW_DDI_B,	677	SKL_DISP_PW_DDI_B,
@@ -632,6 +679,10 @@ enum skl_disp_power_wells { · 1 unmodified line
632	SKL_DISP_PW_DDI_D,	679	SKL_DISP_PW_DDI_D,
633	SKL_DISP_PW_1 = 14,	680	SKL_DISP_PW_1 = 14,
634	SKL_DISP_PW_2,	681	SKL_DISP_PW_2,
		682
		683	/* Not actual bit groups. Used as IDs for lookup_power_well() */
		684	SKL_DISP_PW_ALWAYS_ON,
		685	SKL_DISP_PW_DC_OFF,
635	};	686	};
636		687
637	#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))	688	#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
@@ -832,7 +883,7 @@ enum skl_disp_power_wells { · 194 unmodified lines
832	*/	883	*/
833	#define DPIO_DEVFN 0	884	#define DPIO_DEVFN 0
834		885
835	#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)	886	#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
836	#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */	887	#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
837	#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */	888	#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
838	#define DPIO_SFR_BYPASS (1<<1)	889	#define DPIO_SFR_BYPASS (1<<1)
@@ -1185,9 +1236,9 @@ enum skl_disp_power_wells { · 346 unmodified lines
1185	#define DPIO_UPAR_SHIFT 30	1236	#define DPIO_UPAR_SHIFT 30
1186		1237
1187	/* BXT PHY registers */	1238	/* BXT PHY registers */
1188	#define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b))	1239	#define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b))
1189		1240
1190	#define BXT_P_CR_GT_DISP_PWRON 0x138090	1241	#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1191	#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))	1242	#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1192		1243
1193	#define _PHY_CTL_FAMILY_EDP 0x64C80	1244	#define _PHY_CTL_FAMILY_EDP 0x64C80
@@ -1203,7 +1254,7 @@ enum skl_disp_power_wells { · 9 unmodified lines
1203	#define PORT_PLL_ENABLE (1 << 31)	1254	#define PORT_PLL_ENABLE (1 << 31)
1204	#define PORT_PLL_LOCK (1 << 30)	1255	#define PORT_PLL_LOCK (1 << 30)
1205	#define PORT_PLL_REF_SEL (1 << 27)	1256	#define PORT_PLL_REF_SEL (1 << 27)
1206	#define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B)	1257	#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1207		1258
1208	#define _PORT_PLL_EBB_0_A 0x162034	1259	#define _PORT_PLL_EBB_0_A 0x162034
1209	#define _PORT_PLL_EBB_0_B 0x6C034	1260	#define _PORT_PLL_EBB_0_B 0x6C034
@@ -1214,7 +1265,7 @@ enum skl_disp_power_wells { · 4 unmodified lines
1214	#define PORT_PLL_P2_SHIFT 8	1265	#define PORT_PLL_P2_SHIFT 8
1215	#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)	1266	#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1216	#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)	1267	#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1217	#define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \	1268	#define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
1218	_PORT_PLL_EBB_0_B, \	1269	_PORT_PLL_EBB_0_B, \
1219	_PORT_PLL_EBB_0_C)	1270	_PORT_PLL_EBB_0_C)
1220		1271
@@ -1223,7 +1274,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
1223	#define _PORT_PLL_EBB_4_C 0x6C344	1274	#define _PORT_PLL_EBB_4_C 0x6C344
1224	#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)	1275	#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1225	#define PORT_PLL_RECALIBRATE (1 << 14)	1276	#define PORT_PLL_RECALIBRATE (1 << 14)
1226	#define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \	1277	#define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
1227	_PORT_PLL_EBB_4_B, \	1278	_PORT_PLL_EBB_4_B, \
1228	_PORT_PLL_EBB_4_C)	1279	_PORT_PLL_EBB_4_C)
1229		1280
@@ -1259,7 +1310,7 @@ enum skl_disp_power_wells { · 29 unmodified lines
1259	#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \	1310	#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1260	_PORT_PLL_0_B, \	1311	_PORT_PLL_0_B, \
1261	_PORT_PLL_0_C)	1312	_PORT_PLL_0_C)
1262	#define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4)	1313	#define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
1263		1314
1264	/* BXT PHY common lane registers */	1315	/* BXT PHY common lane registers */
1265	#define _PORT_CL1CM_DW0_A 0x162000	1316	#define _PORT_CL1CM_DW0_A 0x162000
@@ -1297,7 +1348,7 @@ enum skl_disp_power_wells { · 31 unmodified lines
1297	_PORT_CL1CM_DW30_A)	1348	_PORT_CL1CM_DW30_A)
1298		1349
1299	/* Defined for PHY0 only */	1350	/* Defined for PHY0 only */
1300	#define BXT_PORT_CL2CM_DW6_BC 0x6C358	1351	#define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358)
1301	#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)	1352	#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1302		1353
1303	/* BXT PHY Ref registers */	1354	/* BXT PHY Ref registers */
@@ -1337,10 +1388,10 @@ enum skl_disp_power_wells { · 33 unmodified lines
1337	#define _PORT_PCS_DW10_GRP_A 0x162C28	1388	#define _PORT_PCS_DW10_GRP_A 0x162C28
1338	#define _PORT_PCS_DW10_GRP_B 0x6CC28	1389	#define _PORT_PCS_DW10_GRP_B 0x6CC28
1339	#define _PORT_PCS_DW10_GRP_C 0x6CE28	1390	#define _PORT_PCS_DW10_GRP_C 0x6CE28
1340	#define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \	1391	#define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
1341	_PORT_PCS_DW10_LN01_B, \	1392	_PORT_PCS_DW10_LN01_B, \
1342	_PORT_PCS_DW10_LN01_C)	1393	_PORT_PCS_DW10_LN01_C)
1343	#define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \	1394	#define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \
1344	_PORT_PCS_DW10_GRP_B, \	1395	_PORT_PCS_DW10_GRP_B, \
1345	_PORT_PCS_DW10_GRP_C)	1396	_PORT_PCS_DW10_GRP_C)
1346	#define TX2_SWING_CALC_INIT (1 << 31)	1397	#define TX2_SWING_CALC_INIT (1 << 31)
@@ -1357,13 +1408,13 @@ enum skl_disp_power_wells { · 10 unmodified lines
1357	#define _PORT_PCS_DW12_GRP_C 0x6CE30	1408	#define _PORT_PCS_DW12_GRP_C 0x6CE30
1358	#define LANESTAGGER_STRAP_OVRD (1 << 6)	1409	#define LANESTAGGER_STRAP_OVRD (1 << 6)
1359	#define LANE_STAGGER_MASK 0x1F	1410	#define LANE_STAGGER_MASK 0x1F
1360	#define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \	1411	#define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
1361	_PORT_PCS_DW12_LN01_B, \	1412	_PORT_PCS_DW12_LN01_B, \
1362	_PORT_PCS_DW12_LN01_C)	1413	_PORT_PCS_DW12_LN01_C)
1363	#define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \	1414	#define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
1364	_PORT_PCS_DW12_LN23_B, \	1415	_PORT_PCS_DW12_LN23_B, \
1365	_PORT_PCS_DW12_LN23_C)	1416	_PORT_PCS_DW12_LN23_C)
1366	#define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \	1417	#define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
1367	_PORT_PCS_DW12_GRP_B, \	1418	_PORT_PCS_DW12_GRP_B, \
1368	_PORT_PCS_DW12_GRP_C)	1419	_PORT_PCS_DW12_GRP_C)
1369		1420
@@ -1377,10 +1428,10 @@ enum skl_disp_power_wells { · 7 unmodified lines
1377	#define _PORT_TX_DW2_GRP_A 0x162D08	1428	#define _PORT_TX_DW2_GRP_A 0x162D08
1378	#define _PORT_TX_DW2_GRP_B 0x6CD08	1429	#define _PORT_TX_DW2_GRP_B 0x6CD08
1379	#define _PORT_TX_DW2_GRP_C 0x6CF08	1430	#define _PORT_TX_DW2_GRP_C 0x6CF08
1380	#define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \	1431	#define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \
1381	_PORT_TX_DW2_GRP_B, \	1432	_PORT_TX_DW2_GRP_B, \
1382	_PORT_TX_DW2_GRP_C)	1433	_PORT_TX_DW2_GRP_C)
1383	#define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \	1434	#define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \
1384	_PORT_TX_DW2_LN0_B, \	1435	_PORT_TX_DW2_LN0_B, \
1385	_PORT_TX_DW2_LN0_C)	1436	_PORT_TX_DW2_LN0_C)
1386	#define MARGIN_000_SHIFT 16	1437	#define MARGIN_000_SHIFT 16
@@ -1394,10 +1445,10 @@ enum skl_disp_power_wells { · 7 unmodified lines
1394	#define _PORT_TX_DW3_GRP_A 0x162D0C	1445	#define _PORT_TX_DW3_GRP_A 0x162D0C
1395	#define _PORT_TX_DW3_GRP_B 0x6CD0C	1446	#define _PORT_TX_DW3_GRP_B 0x6CD0C
1396	#define _PORT_TX_DW3_GRP_C 0x6CF0C	1447	#define _PORT_TX_DW3_GRP_C 0x6CF0C
1397	#define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \	1448	#define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \
1398	_PORT_TX_DW3_GRP_B, \	1449	_PORT_TX_DW3_GRP_B, \
1399	_PORT_TX_DW3_GRP_C)	1450	_PORT_TX_DW3_GRP_C)
1400	#define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \	1451	#define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \
1401	_PORT_TX_DW3_LN0_B, \	1452	_PORT_TX_DW3_LN0_B, \
1402	_PORT_TX_DW3_LN0_C)	1453	_PORT_TX_DW3_LN0_C)
1403	#define SCALE_DCOMP_METHOD (1 << 26)	1454	#define SCALE_DCOMP_METHOD (1 << 26)
@@ -1409,10 +1460,10 @@ enum skl_disp_power_wells { · 5 unmodified lines
1409	#define _PORT_TX_DW4_GRP_A 0x162D10	1460	#define _PORT_TX_DW4_GRP_A 0x162D10
1410	#define _PORT_TX_DW4_GRP_B 0x6CD10	1461	#define _PORT_TX_DW4_GRP_B 0x6CD10
1411	#define _PORT_TX_DW4_GRP_C 0x6CF10	1462	#define _PORT_TX_DW4_GRP_C 0x6CF10
1412	#define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \	1463	#define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \
1413	_PORT_TX_DW4_LN0_B, \	1464	_PORT_TX_DW4_LN0_B, \
1414	_PORT_TX_DW4_LN0_C)	1465	_PORT_TX_DW4_LN0_C)
1415	#define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \	1466	#define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \
1416	_PORT_TX_DW4_GRP_B, \	1467	_PORT_TX_DW4_GRP_B, \
1417	_PORT_TX_DW4_GRP_C)	1468	_PORT_TX_DW4_GRP_C)
1418	#define DEEMPH_SHIFT 24	1469	#define DEEMPH_SHIFT 24
@@ -1423,17 +1474,17 @@ enum skl_disp_power_wells { · 4 unmodified lines
1423	#define _PORT_TX_DW14_LN0_C 0x6C938	1474	#define _PORT_TX_DW14_LN0_C 0x6C938
1424	#define LATENCY_OPTIM_SHIFT 30	1475	#define LATENCY_OPTIM_SHIFT 30
1425	#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)	1476	#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
1426	#define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \	1477	#define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \
1427	_PORT_TX_DW14_LN0_B, \	1478	_PORT_TX_DW14_LN0_B, \
1428	_PORT_TX_DW14_LN0_C) + \	1479	_PORT_TX_DW14_LN0_C) + \
1429	_BXT_LANE_OFFSET(lane))	1480	_BXT_LANE_OFFSET(lane))
1430		1481
1431	/* UAIMI scratch pad register 1 */	1482	/* UAIMI scratch pad register 1 */
1432	#define UAIMI_SPR1 0x4F074	1483	#define UAIMI_SPR1 _MMIO(0x4F074)
1433	/* SKL VccIO mask */	1484	/* SKL VccIO mask */
1434	#define SKL_VCCIO_MASK 0x1	1485	#define SKL_VCCIO_MASK 0x1
1435	/* SKL balance leg register */	1486	/* SKL balance leg register */
1436	#define DISPIO_CR_TX_BMU_CR0 0x6C00C	1487	#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
1437	/* I_boost values */	1488	/* I_boost values */
1438	#define BALANCE_LEG_SHIFT(port) (8+3*(port))	1489	#define BALANCE_LEG_SHIFT(port) (8+3*(port))
1439	#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))	1490	#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
@@ -1450,7 +1501,7 @@ enum skl_disp_power_wells { · 10 unmodified lines
1450	* [0-15] @ 0x100000 gen6,vlv,chv	1501	* [0-15] @ 0x100000 gen6,vlv,chv
1451	* [0-31] @ 0x100000 gen7+	1502	* [0-31] @ 0x100000 gen7+
1452	*/	1503	*/
1453	#define FENCE_REG(i) (0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)	1504	#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
1454	#define I830_FENCE_START_MASK 0x07f80000	1505	#define I830_FENCE_START_MASK 0x07f80000
1455	#define I830_FENCE_TILING_Y_SHIFT 12	1506	#define I830_FENCE_TILING_Y_SHIFT 12
1456	#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)	1507	#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
@@ -1463,21 +1514,21 @@ enum skl_disp_power_wells { · 6 unmodified lines
1463	#define I915_FENCE_START_MASK 0x0ff00000	1514	#define I915_FENCE_START_MASK 0x0ff00000
1464	#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)	1515	#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1465		1516
1466	#define FENCE_REG_965_LO(i) (0x03000 + (i) * 8)	1517	#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
1467	#define FENCE_REG_965_HI(i) (0x03000 + (i) * 8 + 4)	1518	#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
1468	#define I965_FENCE_PITCH_SHIFT 2	1519	#define I965_FENCE_PITCH_SHIFT 2
1469	#define I965_FENCE_TILING_Y_SHIFT 1	1520	#define I965_FENCE_TILING_Y_SHIFT 1
1470	#define I965_FENCE_REG_VALID (1<<0)	1521	#define I965_FENCE_REG_VALID (1<<0)
1471	#define I965_FENCE_MAX_PITCH_VAL 0x0400	1522	#define I965_FENCE_MAX_PITCH_VAL 0x0400
1472		1523
1473	#define FENCE_REG_GEN6_LO(i) (0x100000 + (i) * 8)	1524	#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
1474	#define FENCE_REG_GEN6_HI(i) (0x100000 + (i) * 8 + 4)	1525	#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
1475	#define GEN6_FENCE_PITCH_SHIFT 32	1526	#define GEN6_FENCE_PITCH_SHIFT 32
1476	#define GEN7_FENCE_MAX_PITCH_VAL 0x0800	1527	#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1477		1528
1478		1529
1479	/* control register for cpu gtt access */	1530	/* control register for cpu gtt access */
1480	#define TILECTL 0x101000	1531	#define TILECTL _MMIO(0x101000)
1481	#define TILECTL_SWZCTL (1 << 0)	1532	#define TILECTL_SWZCTL (1 << 0)
1482	#define TILECTL_TLBPF (1 << 1)	1533	#define TILECTL_TLBPF (1 << 1)
1483	#define TILECTL_TLB_PREFETCH_DIS (1 << 2)	1534	#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
@@ -1486,30 +1537,30 @@ enum skl_disp_power_wells { · 2 unmodified lines
1486	/*	1537	/*
1487	* Instruction and interrupt control regs	1538	* Instruction and interrupt control regs
1488	*/	1539	*/
1489	#define PGTBL_CTL 0x02020	1540	#define PGTBL_CTL _MMIO(0x02020)
1490	#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */	1541	#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1491	#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */	1542	#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1492	#define PGTBL_ER 0x02024	1543	#define PGTBL_ER _MMIO(0x02024)
1493	#define PRB0_BASE (0x2030-0x30)	1544	#define PRB0_BASE (0x2030-0x30)
1494	#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */	1545	#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1495	#define PRB2_BASE (0x2050-0x30) /* gen3 */	1546	#define PRB2_BASE (0x2050-0x30) /* gen3 */
1496	#define SRB0_BASE (0x2100-0x30) /* gen2 */	1547	#define SRB0_BASE (0x2100-0x30) /* gen2 */
1497	#define SRB1_BASE (0x2110-0x30) /* gen2 */	1548	#define SRB1_BASE (0x2110-0x30) /* gen2 */
1498	#define SRB2_BASE (0x2120-0x30) /* 830 */	1549	#define SRB2_BASE (0x2120-0x30) /* 830 */
1499	#define SRB3_BASE (0x2130-0x30) /* 830 */	1550	#define SRB3_BASE (0x2130-0x30) /* 830 */
1500	#define RENDER_RING_BASE 0x02000	1551	#define RENDER_RING_BASE 0x02000
1501	#define BSD_RING_BASE 0x04000	1552	#define BSD_RING_BASE 0x04000
1502	#define GEN6_BSD_RING_BASE 0x12000	1553	#define GEN6_BSD_RING_BASE 0x12000
1503	#define GEN8_BSD2_RING_BASE 0x1c000	1554	#define GEN8_BSD2_RING_BASE 0x1c000
1504	#define VEBOX_RING_BASE 0x1a000	1555	#define VEBOX_RING_BASE 0x1a000
1505	#define BLT_RING_BASE 0x22000	1556	#define BLT_RING_BASE 0x22000
1506	#define RING_TAIL(base) ((base)+0x30)	1557	#define RING_TAIL(base) _MMIO((base)+0x30)
1507	#define RING_HEAD(base) ((base)+0x34)	1558	#define RING_HEAD(base) _MMIO((base)+0x34)
1508	#define RING_START(base) ((base)+0x38)	1559	#define RING_START(base) _MMIO((base)+0x38)
1509	#define RING_CTL(base) ((base)+0x3c)	1560	#define RING_CTL(base) _MMIO((base)+0x3c)
1510	#define RING_SYNC_0(base) ((base)+0x40)	1561	#define RING_SYNC_0(base) _MMIO((base)+0x40)
1511	#define RING_SYNC_1(base) ((base)+0x44)	1562	#define RING_SYNC_1(base) _MMIO((base)+0x44)
1512	#define RING_SYNC_2(base) ((base)+0x48)	1563	#define RING_SYNC_2(base) _MMIO((base)+0x48)
1513	#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))	1564	#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1514	#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))	1565	#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1515	#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))	1566	#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
@@ -1522,51 +1573,52 @@ enum skl_disp_power_wells { · 6 unmodified lines
1522	#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))	1573	#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1523	#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))	1574	#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1524	#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))	1575	#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1525	#define GEN6_NOSYNC 0	1576	#define GEN6_NOSYNC INVALID_MMIO_REG
1526	#define RING_PSMI_CTL(base) ((base)+0x50)	1577	#define RING_PSMI_CTL(base) _MMIO((base)+0x50)
1527	#define RING_MAX_IDLE(base) ((base)+0x54)	1578	#define RING_MAX_IDLE(base) _MMIO((base)+0x54)
1528	#define RING_HWS_PGA(base) ((base)+0x80)	1579	#define RING_HWS_PGA(base) _MMIO((base)+0x80)
1529	#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)	1580	#define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
1530	#define RING_RESET_CTL(base) ((base)+0xd0)	1581	#define RING_RESET_CTL(base) _MMIO((base)+0xd0)
1531	#define RESET_CTL_REQUEST_RESET (1 << 0)	1582	#define RESET_CTL_REQUEST_RESET (1 << 0)
1532	#define RESET_CTL_READY_TO_RESET (1 << 1)	1583	#define RESET_CTL_READY_TO_RESET (1 << 1)
1533		1584
1534	#define HSW_GTT_CACHE_EN 0x4024	1585	#define HSW_GTT_CACHE_EN _MMIO(0x4024)
1535	#define GTT_CACHE_EN_ALL 0xF0007FFF	1586	#define GTT_CACHE_EN_ALL 0xF0007FFF
1536	#define GEN7_WR_WATERMARK 0x4028	1587	#define GEN7_WR_WATERMARK _MMIO(0x4028)
1537	#define GEN7_GFX_PRIO_CTRL 0x402C	1588	#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
1538	#define ARB_MODE 0x4030	1589	#define ARB_MODE _MMIO(0x4030)
1539	#define ARB_MODE_SWIZZLE_SNB (1<<4)	1590	#define ARB_MODE_SWIZZLE_SNB (1<<4)
1540	#define ARB_MODE_SWIZZLE_IVB (1<<5)	1591	#define ARB_MODE_SWIZZLE_IVB (1<<5)
1541	#define GEN7_GFX_PEND_TLB0 0x4034	1592	#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
1542	#define GEN7_GFX_PEND_TLB1 0x4038	1593	#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
1543	/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */	1594	/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1544	#define GEN7_LRA_LIMITS(i) (0x403C + (i) * 4)	1595	#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
1545	#define GEN7_LRA_LIMITS_REG_NUM 13	1596	#define GEN7_LRA_LIMITS_REG_NUM 13
1546	#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070	1597	#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
1547	#define GEN7_GFX_MAX_REQ_COUNT 0x4074	1598	#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
1548		1599
1549	#define GAMTARBMODE 0x04a08	1600	#define GAMTARBMODE _MMIO(0x04a08)
1550	#define ARB_MODE_BWGTLB_DISABLE (1<<9)	1601	#define ARB_MODE_BWGTLB_DISABLE (1<<9)
1551	#define ARB_MODE_SWIZZLE_BDW (1<<1)	1602	#define ARB_MODE_SWIZZLE_BDW (1<<1)
1552	#define RENDER_HWS_PGA_GEN7 (0x04080)	1603	#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
1553	#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)	1604	#define RING_FAULT_REG(ring) _MMIO(0x4094 + 0x100*(ring)->id)
1554	#define RING_FAULT_GTTSEL_MASK (1<<11)	1605	#define RING_FAULT_GTTSEL_MASK (1<<11)
1555	#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)	1606	#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
1556	#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)	1607	#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
1557	#define RING_FAULT_VALID (1<<0)	1608	#define RING_FAULT_VALID (1<<0)
1558	#define DONE_REG 0x40b0	1609	#define DONE_REG _MMIO(0x40b0)
1559	#define GEN8_PRIVATE_PAT_LO 0x40e0	1610	#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
1560	#define GEN8_PRIVATE_PAT_HI (0x40e0 + 4)	1611	#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
1561	#define BSD_HWS_PGA_GEN7 (0x04180)	1612	#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
1562	#define BLT_HWS_PGA_GEN7 (0x04280)	1613	#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
1563	#define VEBOX_HWS_PGA_GEN7 (0x04380)	1614	#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
1564	#define RING_ACTHD(base) ((base)+0x74)	1615	#define RING_ACTHD(base) _MMIO((base)+0x74)
1565	#define RING_ACTHD_UDW(base) ((base)+0x5c)	1616	#define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
1566	#define RING_NOPID(base) ((base)+0x94)	1617	#define RING_NOPID(base) _MMIO((base)+0x94)
1567	#define RING_IMR(base) ((base)+0xa8)	1618	#define RING_IMR(base) _MMIO((base)+0xa8)
1568	#define RING_HWSTAM(base) ((base)+0x98)	1619	#define RING_HWSTAM(base) _MMIO((base)+0x98)
1569	#define RING_TIMESTAMP(base) ((base)+0x358)	1620	#define RING_TIMESTAMP(base) _MMIO((base)+0x358)
		1621	#define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
1570	#define TAIL_ADDR 0x001FFFF8	1622	#define TAIL_ADDR 0x001FFFF8
1571	#define HEAD_WRAP_COUNT 0xFFE00000	1623	#define HEAD_WRAP_COUNT 0xFFE00000
1572	#define HEAD_WRAP_ONE 0x00200000	1624	#define HEAD_WRAP_ONE 0x00200000
@@ -1583,57 +1635,65 @@ enum skl_disp_power_wells { · 10 unmodified lines
1583	#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */	1635	#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1584	#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */	1636	#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1585		1637
1586	#define GEN7_TLB_RD_ADDR 0x4700	1638	#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
1587		1639
1588	#if 0	1640	#if 0
1589	#define PRB0_TAIL 0x02030	1641	#define PRB0_TAIL _MMIO(0x2030)
1590	#define PRB0_HEAD 0x02034	1642	#define PRB0_HEAD _MMIO(0x2034)
1591	#define PRB0_START 0x02038	1643	#define PRB0_START _MMIO(0x2038)
1592	#define PRB0_CTL 0x0203c	1644	#define PRB0_CTL _MMIO(0x203c)
1593	#define PRB1_TAIL 0x02040 /* 915+ only */	1645	#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
1594	#define PRB1_HEAD 0x02044 /* 915+ only */	1646	#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
1595	#define PRB1_START 0x02048 /* 915+ only */	1647	#define PRB1_START _MMIO(0x2048) /* 915+ only */
1596	#define PRB1_CTL 0x0204c /* 915+ only */	1648	#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
1597	#endif	1649	#endif
1598	#define IPEIR_I965 0x02064	1650	#define IPEIR_I965 _MMIO(0x2064)
1599	#define IPEHR_I965 0x02068	1651	#define IPEHR_I965 _MMIO(0x2068)
1600	#define GEN7_SC_INSTDONE 0x07100	1652	#define GEN7_SC_INSTDONE _MMIO(0x7100)
1601	#define GEN7_SAMPLER_INSTDONE 0x0e160	1653	#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1602	#define GEN7_ROW_INSTDONE 0x0e164	1654	#define GEN7_ROW_INSTDONE _MMIO(0xe164)
1603	#define I915_NUM_INSTDONE_REG 4	1655	#define I915_NUM_INSTDONE_REG 4
1604	#define RING_IPEIR(base) ((base)+0x64)	1656	#define RING_IPEIR(base) _MMIO((base)+0x64)
1605	#define RING_IPEHR(base) ((base)+0x68)	1657	#define RING_IPEHR(base) _MMIO((base)+0x68)
1606	/*	1658	/*
1607	* On GEN4, only the render ring INSTDONE exists and has a different	1659	* On GEN4, only the render ring INSTDONE exists and has a different
1608	* layout than the GEN7+ version.	1660	* layout than the GEN7+ version.
1609	* The GEN2 counterpart of this register is GEN2_INSTDONE.	1661	* The GEN2 counterpart of this register is GEN2_INSTDONE.
1610	*/	1662	*/
1611	#define RING_INSTDONE(base) ((base)+0x6c)	1663	#define RING_INSTDONE(base) _MMIO((base)+0x6c)
1612	#define RING_INSTPS(base) ((base)+0x70)	1664	#define RING_INSTPS(base) _MMIO((base)+0x70)
1613	#define RING_DMA_FADD(base) ((base)+0x78)	1665	#define RING_DMA_FADD(base) _MMIO((base)+0x78)
1614	#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */	1666	#define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
1615	#define RING_INSTPM(base) ((base)+0xc0)	1667	#define RING_INSTPM(base) _MMIO((base)+0xc0)
1616	#define RING_MI_MODE(base) ((base)+0x9c)	1668	#define RING_MI_MODE(base) _MMIO((base)+0x9c)
1617	#define INSTPS 0x02070 /* 965+ only */	1669	#define INSTPS _MMIO(0x2070) /* 965+ only */
1618	#define GEN4_INSTDONE1 0x0207c /* 965+ only, aka INSTDONE_2 on SNB */	1670	#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
1619	#define ACTHD_I965 0x02074	1671	#define ACTHD_I965 _MMIO(0x2074)
1620	#define HWS_PGA 0x02080	1672	#define HWS_PGA _MMIO(0x2080)
1621	#define HWS_ADDRESS_MASK 0xfffff000	1673	#define HWS_ADDRESS_MASK 0xfffff000
1622	#define HWS_START_ADDRESS_SHIFT 4	1674	#define HWS_START_ADDRESS_SHIFT 4
1623	#define PWRCTXA 0x2088 /* 965GM+ only */	1675	#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
1624	#define PWRCTX_EN (1<<0)	1676	#define PWRCTX_EN (1<<0)
1625	#define IPEIR 0x02088	1677	#define IPEIR _MMIO(0x2088)
1626	#define IPEHR 0x0208c	1678	#define IPEHR _MMIO(0x208c)
1627	#define GEN2_INSTDONE 0x02090	1679	#define GEN2_INSTDONE _MMIO(0x2090)
1628	#define NOPID 0x02094	1680	#define NOPID _MMIO(0x2094)
1629	#define HWSTAM 0x02098	1681	#define HWSTAM _MMIO(0x2098)
1630	#define DMA_FADD_I8XX 0x020d0	1682	#define DMA_FADD_I8XX _MMIO(0x20d0)
1631	#define RING_BBSTATE(base) ((base)+0x110)	1683	#define RING_BBSTATE(base) _MMIO((base)+0x110)
1632	#define RING_BBADDR(base) ((base)+0x140)	1684	#define RING_BB_PPGTT (1 << 5)
1633	#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */	1685	#define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
1634		1686	#define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
1635	#define ERROR_GEN6 0x040a0	1687	#define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
1636	#define GEN7_ERR_INT 0x44040	1688	#define RING_BBADDR(base) _MMIO((base)+0x140)
		1689	#define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
		1690	#define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
		1691	#define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
		1692	#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
		1693	#define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
		1694
		1695	#define ERROR_GEN6 _MMIO(0x40a0)
		1696	#define GEN7_ERR_INT _MMIO(0x44040)
1637	#define ERR_INT_POISON (1<<31)	1697	#define ERR_INT_POISON (1<<31)
1638	#define ERR_INT_MMIO_UNCLAIMED (1<<13)	1698	#define ERR_INT_MMIO_UNCLAIMED (1<<13)
1639	#define ERR_INT_PIPE_CRC_DONE_C (1<<8)	1699	#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
@@ -1645,13 +1705,13 @@ enum skl_disp_power_wells { · 5 unmodified lines
1645	#define ERR_INT_FIFO_UNDERRUN_A (1<<0)	1705	#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1646	#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))	1706	#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
1647		1707
1648	#define GEN8_FAULT_TLB_DATA0 0x04b10	1708	#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
1649	#define GEN8_FAULT_TLB_DATA1 0x04b14	1709	#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
1650		1710
1651	#define FPGA_DBG 0x42300	1711	#define FPGA_DBG _MMIO(0x42300)
1652	#define FPGA_DBG_RM_NOCLAIM (1<<31)	1712	#define FPGA_DBG_RM_NOCLAIM (1<<31)
1653		1713
1654	#define DERRMR 0x44050	1714	#define DERRMR _MMIO(0x44050)
1655	/* Note that HBLANK events are reserved on bdw+ */	1715	/* Note that HBLANK events are reserved on bdw+ */
1656	#define DERRMR_PIPEA_SCANLINE (1<<0)	1716	#define DERRMR_PIPEA_SCANLINE (1<<0)
1657	#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)	1717	#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
@@ -1675,29 +1735,29 @@ enum skl_disp_power_wells { · 17 unmodified lines
1675	* for various sorts of correct behavior. The top 16 bits of each are	1735	* for various sorts of correct behavior. The top 16 bits of each are
1676	* the enables for writing to the corresponding low bit.	1736	* the enables for writing to the corresponding low bit.
1677	*/	1737	*/
1678	#define _3D_CHICKEN 0x02084	1738	#define _3D_CHICKEN _MMIO(0x2084)
1679	#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)	1739	#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1680	#define _3D_CHICKEN2 0x0208c	1740	#define _3D_CHICKEN2 _MMIO(0x208c)
1681	/* Disables pipelining of read flushes past the SF-WIZ interface.	1741	/* Disables pipelining of read flushes past the SF-WIZ interface.
1682	* Required on all Ironlake steppings according to the B-Spec, but the	1742	* Required on all Ironlake steppings according to the B-Spec, but the
1683	* particular danger of not doing so is not specified.	1743	* particular danger of not doing so is not specified.
1684	*/	1744	*/
1685	# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)	1745	# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1686	#define _3D_CHICKEN3 0x02090	1746	#define _3D_CHICKEN3 _MMIO(0x2090)
1687	#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)	1747	#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1688	#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)	1748	#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1689	#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */	1749	#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1690	#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */	1750	#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1691		1751
1692	#define MI_MODE 0x0209c	1752	#define MI_MODE _MMIO(0x209c)
1693	# define VS_TIMER_DISPATCH (1 << 6)	1753	# define VS_TIMER_DISPATCH (1 << 6)
1694	# define MI_FLUSH_ENABLE (1 << 12)	1754	# define MI_FLUSH_ENABLE (1 << 12)
1695	# define ASYNC_FLIP_PERF_DISABLE (1 << 14)	1755	# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1696	# define MODE_IDLE (1 << 9)	1756	# define MODE_IDLE (1 << 9)
1697	# define STOP_RING (1 << 8)	1757	# define STOP_RING (1 << 8)
1698		1758
1699	#define GEN6_GT_MODE 0x20d0	1759	#define GEN6_GT_MODE _MMIO(0x20d0)
1700	#define GEN7_GT_MODE 0x7008	1760	#define GEN7_GT_MODE _MMIO(0x7008)
1701	#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) \| ((lo) << 7))	1761	#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) \| ((lo) << 7))
1702	#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)	1762	#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1703	#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)	1763	#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
@@ -1707,9 +1767,9 @@ enum skl_disp_power_wells { · 3 unmodified lines
1707	#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))	1767	#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
1708	#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))	1768	#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
1709		1769
1710	#define GFX_MODE 0x02520	1770	#define GFX_MODE _MMIO(0x2520)
1711	#define GFX_MODE_GEN7 0x0229c	1771	#define GFX_MODE_GEN7 _MMIO(0x229c)
1712	#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)	1772	#define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c)
1713	#define GFX_RUN_LIST_ENABLE (1<<15)	1773	#define GFX_RUN_LIST_ENABLE (1<<15)
1714	#define GFX_INTERRUPT_STEERING (1<<14)	1774	#define GFX_INTERRUPT_STEERING (1<<14)
1715	#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)	1775	#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
@@ -1727,36 +1787,36 @@ enum skl_disp_power_wells { · 11 unmodified lines
1727	#define VLV_DISPLAY_BASE 0x180000	1787	#define VLV_DISPLAY_BASE 0x180000
1728	#define VLV_MIPI_BASE VLV_DISPLAY_BASE	1788	#define VLV_MIPI_BASE VLV_DISPLAY_BASE
1729		1789
1730	#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)	1790	#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
1731	#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)	1791	#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1732	#define SCPD0 0x0209c /* 915+ only */	1792	#define SCPD0 _MMIO(0x209c) /* 915+ only */
1733	#define IER 0x020a0	1793	#define IER _MMIO(0x20a0)
1734	#define IIR 0x020a4	1794	#define IIR _MMIO(0x20a4)
1735	#define IMR 0x020a8	1795	#define IMR _MMIO(0x20a8)
1736	#define ISR 0x020ac	1796	#define ISR _MMIO(0x20ac)
1737	#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)	1797	#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
1738	#define GINT_DIS (1<<22)	1798	#define GINT_DIS (1<<22)
1739	#define GCFG_DIS (1<<8)	1799	#define GCFG_DIS (1<<8)
1740	#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)	1800	#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1741	#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)	1801	#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1742	#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)	1802	#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1743	#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)	1803	#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1744	#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)	1804	#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1745	#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)	1805	#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1746	#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)	1806	#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1747	#define VLV_PCBR_ADDR_SHIFT 12	1807	#define VLV_PCBR_ADDR_SHIFT 12
1748		1808
1749	#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */	1809	#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1750	#define EIR 0x020b0	1810	#define EIR _MMIO(0x20b0)
1751	#define EMR 0x020b4	1811	#define EMR _MMIO(0x20b4)
1752	#define ESR 0x020b8	1812	#define ESR _MMIO(0x20b8)
1753	#define GM45_ERROR_PAGE_TABLE (1<<5)	1813	#define GM45_ERROR_PAGE_TABLE (1<<5)
1754	#define GM45_ERROR_MEM_PRIV (1<<4)	1814	#define GM45_ERROR_MEM_PRIV (1<<4)
1755	#define I915_ERROR_PAGE_TABLE (1<<4)	1815	#define I915_ERROR_PAGE_TABLE (1<<4)
1756	#define GM45_ERROR_CP_PRIV (1<<3)	1816	#define GM45_ERROR_CP_PRIV (1<<3)
1757	#define I915_ERROR_MEMORY_REFRESH (1<<1)	1817	#define I915_ERROR_MEMORY_REFRESH (1<<1)
1758	#define I915_ERROR_INSTRUCTION (1<<0)	1818	#define I915_ERROR_INSTRUCTION (1<<0)
1759	#define INSTPM 0x020c0	1819	#define INSTPM _MMIO(0x20c0)
1760	#define INSTPM_SELF_EN (1<<12) /* 915GM only */	1820	#define INSTPM_SELF_EN (1<<12) /* 915GM only */
1761	#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts	1821	#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1762	will not assert AGPBUSY# and will only	1822	will not assert AGPBUSY# and will only
@@ -1764,14 +1824,14 @@ enum skl_disp_power_wells { · 1 unmodified line
1764	#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */	1824	#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1765	#define INSTPM_TLB_INVALIDATE (1<<9)	1825	#define INSTPM_TLB_INVALIDATE (1<<9)
1766	#define INSTPM_SYNC_FLUSH (1<<5)	1826	#define INSTPM_SYNC_FLUSH (1<<5)
1767	#define ACTHD 0x020c8	1827	#define ACTHD _MMIO(0x20c8)
1768	#define MEM_MODE 0x020cc	1828	#define MEM_MODE _MMIO(0x20cc)
1769	#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */	1829	#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1770	#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */	1830	#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1771	#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */	1831	#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1772	#define FW_BLC 0x020d8	1832	#define FW_BLC _MMIO(0x20d8)
1773	#define FW_BLC2 0x020dc	1833	#define FW_BLC2 _MMIO(0x20dc)
1774	#define FW_BLC_SELF 0x020e0 /* 915+ only */	1834	#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1775	#define FW_BLC_SELF_EN_MASK (1<<31)	1835	#define FW_BLC_SELF_EN_MASK (1<<31)
1776	#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */	1836	#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1777	#define FW_BLC_SELF_EN (1<<15) /* 945 only */	1837	#define FW_BLC_SELF_EN (1<<15) /* 945 only */
@@ -1779,7 +1839,7 @@ enum skl_disp_power_wells { · 1 unmodified line
1779	#define MM_FIFO_WATERMARK 0x0001F000	1839	#define MM_FIFO_WATERMARK 0x0001F000
1780	#define LM_BURST_LENGTH 0x00000700	1840	#define LM_BURST_LENGTH 0x00000700
1781	#define LM_FIFO_WATERMARK 0x0000001F	1841	#define LM_FIFO_WATERMARK 0x0000001F
1782	#define MI_ARB_STATE 0x020e4 /* 915+ only */	1842	#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1783		1843
1784	/* Make render/texture TLB fetches lower priorty than associated data	1844	/* Make render/texture TLB fetches lower priorty than associated data
1785	* fetches. This is not turned on by default	1845	* fetches. This is not turned on by default
@@ -1843,11 +1903,11 @@ enum skl_disp_power_wells { · 57 unmodified lines
1843	#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */	1903	#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1844	#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */	1904	#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1845		1905
1846	#define MI_STATE 0x020e4 /* gen2 only */	1906	#define MI_STATE _MMIO(0x20e4) /* gen2 only */
1847	#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */	1907	#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1848	#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */	1908	#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1849		1909
1850	#define CACHE_MODE_0 0x02120 /* 915+ only */	1910	#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
1851	#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)	1911	#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1852	#define CM0_IZ_OPT_DISABLE (1<<6)	1912	#define CM0_IZ_OPT_DISABLE (1<<6)
1853	#define CM0_ZR_OPT_DISABLE (1<<5)	1913	#define CM0_ZR_OPT_DISABLE (1<<5)
@@ -1856,32 +1916,32 @@ enum skl_disp_power_wells { · 2 unmodified lines
1856	#define CM0_COLOR_EVICT_DISABLE (1<<3)	1916	#define CM0_COLOR_EVICT_DISABLE (1<<3)
1857	#define CM0_DEPTH_WRITE_DISABLE (1<<1)	1917	#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1858	#define CM0_RC_OP_FLUSH_DISABLE (1<<0)	1918	#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1859	#define GFX_FLSH_CNTL 0x02170 /* 915+ only */	1919	#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
1860	#define GFX_FLSH_CNTL_GEN6 0x101008	1920	#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
1861	#define GFX_FLSH_CNTL_EN (1<<0)	1921	#define GFX_FLSH_CNTL_EN (1<<0)
1862	#define ECOSKPD 0x021d0	1922	#define ECOSKPD _MMIO(0x21d0)
1863	#define ECO_GATING_CX_ONLY (1<<3)	1923	#define ECO_GATING_CX_ONLY (1<<3)
1864	#define ECO_FLIP_DONE (1<<0)	1924	#define ECO_FLIP_DONE (1<<0)
1865		1925
1866	#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */	1926	#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
1867	#define RC_OP_FLUSH_ENABLE (1<<0)	1927	#define RC_OP_FLUSH_ENABLE (1<<0)
1868	#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)	1928	#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1869	#define CACHE_MODE_1 0x7004 /* IVB+ */	1929	#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
1870	#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)	1930	#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1871	#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)	1931	#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1872	#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)	1932	#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
1873		1933
1874	#define GEN6_BLITTER_ECOSKPD 0x221d0	1934	#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
1875	#define GEN6_BLITTER_LOCK_SHIFT 16	1935	#define GEN6_BLITTER_LOCK_SHIFT 16
1876	#define GEN6_BLITTER_FBC_NOTIFY (1<<3)	1936	#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1877		1937
1878	#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050	1938	#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
1879	#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)	1939	#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
1880	#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)	1940	#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1881	#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)	1941	#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1882		1942
1883	/* Fuse readout registers for GT */	1943	/* Fuse readout registers for GT */
1884	#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)	1944	#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
1885	#define CHV_FGT_DISABLE_SS0 (1 << 10)	1945	#define CHV_FGT_DISABLE_SS0 (1 << 10)
1886	#define CHV_FGT_DISABLE_SS1 (1 << 11)	1946	#define CHV_FGT_DISABLE_SS1 (1 << 11)
1887	#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16	1947	#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
@@ -1893,7 +1953,7 @@ enum skl_disp_power_wells { · 5 unmodified lines
1893	#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28	1953	#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1894	#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)	1954	#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1895		1955
1896	#define GEN8_FUSE2 0x9120	1956	#define GEN8_FUSE2 _MMIO(0x9120)
1897	#define GEN8_F2_SS_DIS_SHIFT 21	1957	#define GEN8_F2_SS_DIS_SHIFT 21
1898	#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)	1958	#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
1899	#define GEN8_F2_S_ENA_SHIFT 25	1959	#define GEN8_F2_S_ENA_SHIFT 25
@@ -1902,22 +1962,22 @@ enum skl_disp_power_wells { · 2 unmodified lines
1902	#define GEN9_F2_SS_DIS_SHIFT 20	1962	#define GEN9_F2_SS_DIS_SHIFT 20
1903	#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)	1963	#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
1904		1964
1905	#define GEN8_EU_DISABLE0 0x9134	1965	#define GEN8_EU_DISABLE0 _MMIO(0x9134)
1906	#define GEN8_EU_DIS0_S0_MASK 0xffffff	1966	#define GEN8_EU_DIS0_S0_MASK 0xffffff
1907	#define GEN8_EU_DIS0_S1_SHIFT 24	1967	#define GEN8_EU_DIS0_S1_SHIFT 24
1908	#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)	1968	#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
1909		1969
1910	#define GEN8_EU_DISABLE1 0x9138	1970	#define GEN8_EU_DISABLE1 _MMIO(0x9138)
1911	#define GEN8_EU_DIS1_S1_MASK 0xffff	1971	#define GEN8_EU_DIS1_S1_MASK 0xffff
1912	#define GEN8_EU_DIS1_S2_SHIFT 16	1972	#define GEN8_EU_DIS1_S2_SHIFT 16
1913	#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)	1973	#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
1914		1974
1915	#define GEN8_EU_DISABLE2 0x913c	1975	#define GEN8_EU_DISABLE2 _MMIO(0x913c)
1916	#define GEN8_EU_DIS2_S2_MASK 0xff	1976	#define GEN8_EU_DIS2_S2_MASK 0xff
1917		1977
1918	#define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)	1978	#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
1919		1979
1920	#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050	1980	#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
1921	#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)	1981	#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1922	#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)	1982	#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1923	#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)	1983	#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
@@ -1995,9 +2055,9 @@ enum skl_disp_power_wells { · 71 unmodified lines
1995	#define I915_ASLE_INTERRUPT (1<<0)	2055	#define I915_ASLE_INTERRUPT (1<<0)
1996	#define I915_BSD_USER_INTERRUPT (1<<25)	2056	#define I915_BSD_USER_INTERRUPT (1<<25)
1997		2057
1998	#define GEN6_BSD_RNCID 0x12198	2058	#define GEN6_BSD_RNCID _MMIO(0x12198)
1999		2059
2000	#define GEN7_FF_THREAD_MODE 0x20a0	2060	#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2001	#define GEN7_FF_SCHED_MASK 0x0077070	2061	#define GEN7_FF_SCHED_MASK 0x0077070
2002	#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)	2062	#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2003	#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)	2063	#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
@@ -2018,9 +2078,9 @@ enum skl_disp_power_wells { · 14 unmodified lines
2018	* Framebuffer compression (915+ only)	2078	* Framebuffer compression (915+ only)
2019	*/	2079	*/
2020		2080
2021	#define FBC_CFB_BASE 0x03200 /* 4k page aligned */	2081	#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2022	#define FBC_LL_BASE 0x03204 /* 4k page aligned */	2082	#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2023	#define FBC_CONTROL 0x03208	2083	#define FBC_CONTROL _MMIO(0x3208)
2024	#define FBC_CTL_EN (1<<31)	2084	#define FBC_CTL_EN (1<<31)
2025	#define FBC_CTL_PERIODIC (1<<30)	2085	#define FBC_CTL_PERIODIC (1<<30)
2026	#define FBC_CTL_INTERVAL_SHIFT (16)	2086	#define FBC_CTL_INTERVAL_SHIFT (16)
@@ -2028,14 +2088,14 @@ enum skl_disp_power_wells { · 1 unmodified line
2028	#define FBC_CTL_C3_IDLE (1<<13)	2088	#define FBC_CTL_C3_IDLE (1<<13)
2029	#define FBC_CTL_STRIDE_SHIFT (5)	2089	#define FBC_CTL_STRIDE_SHIFT (5)
2030	#define FBC_CTL_FENCENO_SHIFT (0)	2090	#define FBC_CTL_FENCENO_SHIFT (0)
2031	#define FBC_COMMAND 0x0320c	2091	#define FBC_COMMAND _MMIO(0x320c)
2032	#define FBC_CMD_COMPRESS (1<<0)	2092	#define FBC_CMD_COMPRESS (1<<0)
2033	#define FBC_STATUS 0x03210	2093	#define FBC_STATUS _MMIO(0x3210)
2034	#define FBC_STAT_COMPRESSING (1<<31)	2094	#define FBC_STAT_COMPRESSING (1<<31)
2035	#define FBC_STAT_COMPRESSED (1<<30)	2095	#define FBC_STAT_COMPRESSED (1<<30)
2036	#define FBC_STAT_MODIFIED (1<<29)	2096	#define FBC_STAT_MODIFIED (1<<29)
2037	#define FBC_STAT_CURRENT_LINE_SHIFT (0)	2097	#define FBC_STAT_CURRENT_LINE_SHIFT (0)
2038	#define FBC_CONTROL2 0x03214	2098	#define FBC_CONTROL2 _MMIO(0x3214)
2039	#define FBC_CTL_FENCE_DBL (0<<4)	2099	#define FBC_CTL_FENCE_DBL (0<<4)
2040	#define FBC_CTL_IDLE_IMM (0<<2)	2100	#define FBC_CTL_IDLE_IMM (0<<2)
2041	#define FBC_CTL_IDLE_FULL (1<<2)	2101	#define FBC_CTL_IDLE_FULL (1<<2)
@@ -2043,17 +2103,17 @@ enum skl_disp_power_wells { · 1 unmodified line
2043	#define FBC_CTL_IDLE_DEBUG (3<<2)	2103	#define FBC_CTL_IDLE_DEBUG (3<<2)
2044	#define FBC_CTL_CPU_FENCE (1<<1)	2104	#define FBC_CTL_CPU_FENCE (1<<1)
2045	#define FBC_CTL_PLANE(plane) ((plane)<<0)	2105	#define FBC_CTL_PLANE(plane) ((plane)<<0)
2046	#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */	2106	#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
2047	#define FBC_TAG(i) (0x03300 + (i) * 4)	2107	#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
2048		2108
2049	#define FBC_STATUS2 0x43214	2109	#define FBC_STATUS2 _MMIO(0x43214)
2050	#define FBC_COMPRESSION_MASK 0x7ff	2110	#define FBC_COMPRESSION_MASK 0x7ff
2051		2111
2052	#define FBC_LL_SIZE (1536)	2112	#define FBC_LL_SIZE (1536)
2053		2113
2054	/* Framebuffer compression for GM45+ */	2114	/* Framebuffer compression for GM45+ */
2055	#define DPFC_CB_BASE 0x3200	2115	#define DPFC_CB_BASE _MMIO(0x3200)
2056	#define DPFC_CONTROL 0x3208	2116	#define DPFC_CONTROL _MMIO(0x3208)
2057	#define DPFC_CTL_EN (1<<31)	2117	#define DPFC_CTL_EN (1<<31)
2058	#define DPFC_CTL_PLANE(plane) ((plane)<<30)	2118	#define DPFC_CTL_PLANE(plane) ((plane)<<30)
2059	#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)	2119	#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
@@ -2064,37 +2124,37 @@ enum skl_disp_power_wells { · 4 unmodified lines
2064	#define DPFC_CTL_LIMIT_1X (0<<6)	2124	#define DPFC_CTL_LIMIT_1X (0<<6)
2065	#define DPFC_CTL_LIMIT_2X (1<<6)	2125	#define DPFC_CTL_LIMIT_2X (1<<6)
2066	#define DPFC_CTL_LIMIT_4X (2<<6)	2126	#define DPFC_CTL_LIMIT_4X (2<<6)
2067	#define DPFC_RECOMP_CTL 0x320c	2127	#define DPFC_RECOMP_CTL _MMIO(0x320c)
2068	#define DPFC_RECOMP_STALL_EN (1<<27)	2128	#define DPFC_RECOMP_STALL_EN (1<<27)
2069	#define DPFC_RECOMP_STALL_WM_SHIFT (16)	2129	#define DPFC_RECOMP_STALL_WM_SHIFT (16)
2070	#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)	2130	#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2071	#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)	2131	#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2072	#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)	2132	#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2073	#define DPFC_STATUS 0x3210	2133	#define DPFC_STATUS _MMIO(0x3210)
2074	#define DPFC_INVAL_SEG_SHIFT (16)	2134	#define DPFC_INVAL_SEG_SHIFT (16)
2075	#define DPFC_INVAL_SEG_MASK (0x07ff0000)	2135	#define DPFC_INVAL_SEG_MASK (0x07ff0000)
2076	#define DPFC_COMP_SEG_SHIFT (0)	2136	#define DPFC_COMP_SEG_SHIFT (0)
2077	#define DPFC_COMP_SEG_MASK (0x000003ff)	2137	#define DPFC_COMP_SEG_MASK (0x000003ff)
2078	#define DPFC_STATUS2 0x3214	2138	#define DPFC_STATUS2 _MMIO(0x3214)
2079	#define DPFC_FENCE_YOFF 0x3218	2139	#define DPFC_FENCE_YOFF _MMIO(0x3218)
2080	#define DPFC_CHICKEN 0x3224	2140	#define DPFC_CHICKEN _MMIO(0x3224)
2081	#define DPFC_HT_MODIFY (1<<31)	2141	#define DPFC_HT_MODIFY (1<<31)
2082		2142
2083	/* Framebuffer compression for Ironlake */	2143	/* Framebuffer compression for Ironlake */
2084	#define ILK_DPFC_CB_BASE 0x43200	2144	#define ILK_DPFC_CB_BASE _MMIO(0x43200)
2085	#define ILK_DPFC_CONTROL 0x43208	2145	#define ILK_DPFC_CONTROL _MMIO(0x43208)
2086	#define FBC_CTL_FALSE_COLOR (1<<10)	2146	#define FBC_CTL_FALSE_COLOR (1<<10)
2087	/* The bit 28-8 is reserved */	2147	/* The bit 28-8 is reserved */
2088	#define DPFC_RESERVED (0x1FFFFF00)	2148	#define DPFC_RESERVED (0x1FFFFF00)
2089	#define ILK_DPFC_RECOMP_CTL 0x4320c	2149	#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
2090	#define ILK_DPFC_STATUS 0x43210	2150	#define ILK_DPFC_STATUS _MMIO(0x43210)
2091	#define ILK_DPFC_FENCE_YOFF 0x43218	2151	#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
2092	#define ILK_DPFC_CHICKEN 0x43224	2152	#define ILK_DPFC_CHICKEN _MMIO(0x43224)
2093	#define ILK_FBC_RT_BASE 0x2128	2153	#define ILK_FBC_RT_BASE _MMIO(0x2128)
2094	#define ILK_FBC_RT_VALID (1<<0)	2154	#define ILK_FBC_RT_VALID (1<<0)
2095	#define SNB_FBC_FRONT_BUFFER (1<<1)	2155	#define SNB_FBC_FRONT_BUFFER (1<<1)
2096		2156
2097	#define ILK_DISPLAY_CHICKEN1 0x42000	2157	#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
2098	#define ILK_FBCQ_DIS (1<<22)	2158	#define ILK_FBCQ_DIS (1<<22)
2099	#define ILK_PABSTRETCH_DIS (1<<21)	2159	#define ILK_PABSTRETCH_DIS (1<<21)
2100		2160
@@ -2104,31 +2164,31 @@ enum skl_disp_power_wells { · 3 unmodified lines
2104	*	2164	*
2105	* The following two registers are of type GTTMMADR	2165	* The following two registers are of type GTTMMADR
2106	*/	2166	*/
2107	#define SNB_DPFC_CTL_SA 0x100100	2167	#define SNB_DPFC_CTL_SA _MMIO(0x100100)
2108	#define SNB_CPU_FENCE_ENABLE (1<<29)	2168	#define SNB_CPU_FENCE_ENABLE (1<<29)
2109	#define DPFC_CPU_FENCE_OFFSET 0x100104	2169	#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
2110		2170
2111	/* Framebuffer compression for Ivybridge */	2171	/* Framebuffer compression for Ivybridge */
2112	#define IVB_FBC_RT_BASE 0x7020	2172	#define IVB_FBC_RT_BASE _MMIO(0x7020)
2113		2173
2114	#define IPS_CTL 0x43408	2174	#define IPS_CTL _MMIO(0x43408)
2115	#define IPS_ENABLE (1 << 31)	2175	#define IPS_ENABLE (1 << 31)
2116		2176
2117	#define MSG_FBC_REND_STATE 0x50380	2177	#define MSG_FBC_REND_STATE _MMIO(0x50380)
2118	#define FBC_REND_NUKE (1<<2)	2178	#define FBC_REND_NUKE (1<<2)
2119	#define FBC_REND_CACHE_CLEAN (1<<1)	2179	#define FBC_REND_CACHE_CLEAN (1<<1)
2120		2180
2121	/*	2181	/*
2122	* GPIO regs	2182	* GPIO regs
2123	*/	2183	*/
2124	#define GPIOA 0x5010	2184	#define GPIOA _MMIO(0x5010)
2125	#define GPIOB 0x5014	2185	#define GPIOB _MMIO(0x5014)
2126	#define GPIOC 0x5018	2186	#define GPIOC _MMIO(0x5018)
2127	#define GPIOD 0x501c	2187	#define GPIOD _MMIO(0x501c)
2128	#define GPIOE 0x5020	2188	#define GPIOE _MMIO(0x5020)
2129	#define GPIOF 0x5024	2189	#define GPIOF _MMIO(0x5024)
2130	#define GPIOG 0x5028	2190	#define GPIOG _MMIO(0x5028)
2131	#define GPIOH 0x502c	2191	#define GPIOH _MMIO(0x502c)
2132	# define GPIO_CLOCK_DIR_MASK (1 << 0)	2192	# define GPIO_CLOCK_DIR_MASK (1 << 0)
2133	# define GPIO_CLOCK_DIR_IN (0 << 1)	2193	# define GPIO_CLOCK_DIR_IN (0 << 1)
2134	# define GPIO_CLOCK_DIR_OUT (1 << 1)	2194	# define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -2144,7 +2204,7 @@ enum skl_disp_power_wells { · 9 unmodified lines
2144	# define GPIO_DATA_VAL_IN (1 << 12)	2204	# define GPIO_DATA_VAL_IN (1 << 12)
2145	# define GPIO_DATA_PULLUP_DISABLE (1 << 13)	2205	# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2146		2206
2147	#define GMBUS0 (dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */	2207	#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2148	#define GMBUS_RATE_100KHZ (0<<8)	2208	#define GMBUS_RATE_100KHZ (0<<8)
2149	#define GMBUS_RATE_50KHZ (1<<8)	2209	#define GMBUS_RATE_50KHZ (1<<8)
2150	#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */	2210	#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
@@ -2163,7 +2223,7 @@ enum skl_disp_power_wells { · 12 unmodified lines
2163	#define GMBUS_PIN_2_BXT 2	2223	#define GMBUS_PIN_2_BXT 2
2164	#define GMBUS_PIN_3_BXT 3	2224	#define GMBUS_PIN_3_BXT 3
2165	#define GMBUS_NUM_PINS 7 /* including 0 */	2225	#define GMBUS_NUM_PINS 7 /* including 0 */
2166	#define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* command/status */	2226	#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2167	#define GMBUS_SW_CLR_INT (1<<31)	2227	#define GMBUS_SW_CLR_INT (1<<31)
2168	#define GMBUS_SW_RDY (1<<30)	2228	#define GMBUS_SW_RDY (1<<30)
2169	#define GMBUS_ENT (1<<29) /* enable timeout */	2229	#define GMBUS_ENT (1<<29) /* enable timeout */
@@ -2177,7 +2237,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
2177	#define GMBUS_SLAVE_ADDR_SHIFT 1	2237	#define GMBUS_SLAVE_ADDR_SHIFT 1
2178	#define GMBUS_SLAVE_READ (1<<0)	2238	#define GMBUS_SLAVE_READ (1<<0)
2179	#define GMBUS_SLAVE_WRITE (0<<0)	2239	#define GMBUS_SLAVE_WRITE (0<<0)
2180	#define GMBUS2 (dev_priv->gpio_mmio_base + 0x5108) /* status */	2240	#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
2181	#define GMBUS_INUSE (1<<15)	2241	#define GMBUS_INUSE (1<<15)
2182	#define GMBUS_HW_WAIT_PHASE (1<<14)	2242	#define GMBUS_HW_WAIT_PHASE (1<<14)
2183	#define GMBUS_STALL_TIMEOUT (1<<13)	2243	#define GMBUS_STALL_TIMEOUT (1<<13)
@@ -2185,14 +2245,14 @@ enum skl_disp_power_wells { · 1 unmodified line
2185	#define GMBUS_HW_RDY (1<<11)	2245	#define GMBUS_HW_RDY (1<<11)
2186	#define GMBUS_SATOER (1<<10)	2246	#define GMBUS_SATOER (1<<10)
2187	#define GMBUS_ACTIVE (1<<9)	2247	#define GMBUS_ACTIVE (1<<9)
2188	#define GMBUS3 (dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */	2248	#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2189	#define GMBUS4 (dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */	2249	#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2190	#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)	2250	#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2191	#define GMBUS_NAK_EN (1<<3)	2251	#define GMBUS_NAK_EN (1<<3)
2192	#define GMBUS_IDLE_EN (1<<2)	2252	#define GMBUS_IDLE_EN (1<<2)
2193	#define GMBUS_HW_WAIT_EN (1<<1)	2253	#define GMBUS_HW_WAIT_EN (1<<1)
2194	#define GMBUS_HW_RDY_EN (1<<0)	2254	#define GMBUS_HW_RDY_EN (1<<0)
2195	#define GMBUS5 (dev_priv->gpio_mmio_base + 0x5120) /* byte index */	2255	#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2196	#define GMBUS_2BYTE_INDEX_EN (1<<31)	2256	#define GMBUS_2BYTE_INDEX_EN (1<<31)
2197		2257
2198	/*	2258	/*
@@ -2201,11 +2261,11 @@ enum skl_disp_power_wells { · 2 unmodified lines
2201	#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)	2261	#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2202	#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)	2262	#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2203	#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)	2263	#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2204	#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)	2264	#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2205		2265
2206	#define VGA0 0x6000	2266	#define VGA0 _MMIO(0x6000)
2207	#define VGA1 0x6004	2267	#define VGA1 _MMIO(0x6004)
2208	#define VGA_PD 0x6010	2268	#define VGA_PD _MMIO(0x6010)
2209	#define VGA0_PD_P2_DIV_4 (1 << 7)	2269	#define VGA0_PD_P2_DIV_4 (1 << 7)
2210	#define VGA0_PD_P1_DIV_2 (1 << 5)	2270	#define VGA0_PD_P1_DIV_2 (1 << 5)
2211	#define VGA0_PD_P1_SHIFT 0	2271	#define VGA0_PD_P1_SHIFT 0
@@ -2241,9 +2301,9 @@ enum skl_disp_power_wells { · 29 unmodified lines
2241	#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000	2301	#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
2242		2302
2243	/* Additional CHV pll/phy registers */	2303	/* Additional CHV pll/phy registers */
2244	#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)	2304	#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
2245	#define DPLL_PORTD_READY_MASK (0xf)	2305	#define DPLL_PORTD_READY_MASK (0xf)
2246	#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)	2306	#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
2247	#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))	2307	#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
2248	#define PHY_LDO_DELAY_0NS 0x0	2308	#define PHY_LDO_DELAY_0NS 0x0
2249	#define PHY_LDO_DELAY_200NS 0x1	2309	#define PHY_LDO_DELAY_200NS 0x1
@@ -2254,7 +2314,7 @@ enum skl_disp_power_wells { · 4 unmodified lines
2254	#define PHY_CH_DEEP_PSR 0x7	2314	#define PHY_CH_DEEP_PSR 0x7
2255	#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6(phy)+3(ch)+2))	2315	#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6(phy)+3(ch)+2))
2256	#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))	2316	#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
2257	#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)	2317	#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
2258	#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))	2318	#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
2259	#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6(phy)+3(ch))))	2319	#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6(phy)+3(ch))))
2260	#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6(phy)+3(ch)+(spline))))	2320	#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6(phy)+3(ch)+(spline))))
@@ -2300,7 +2360,7 @@ enum skl_disp_power_wells { · 39 unmodified lines
2300	#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)	2360	#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2301	#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)	2361	#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2302	#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)	2362	#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2303	#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)	2363	#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
2304		2364
2305	/*	2365	/*
2306	* UDI pixel divider, controlling how many pixels are stuffed into a packet.	2366	* UDI pixel divider, controlling how many pixels are stuffed into a packet.
@@ -2339,12 +2399,12 @@ enum skl_disp_power_wells { · 32 unmodified lines
2339	#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f	2399	#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2340	#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0	2400	#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
2341		2401
2342	#define _FPA0 0x06040	2402	#define _FPA0 0x6040
2343	#define _FPA1 0x06044	2403	#define _FPA1 0x6044
2344	#define _FPB0 0x06048	2404	#define _FPB0 0x6048
2345	#define _FPB1 0x0604c	2405	#define _FPB1 0x604c
2346	#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)	2406	#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
2347	#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)	2407	#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
2348	#define FP_N_DIV_MASK 0x003f0000	2408	#define FP_N_DIV_MASK 0x003f0000
2349	#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000	2409	#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
2350	#define FP_N_DIV_SHIFT 16	2410	#define FP_N_DIV_SHIFT 16
@@ -2353,7 +2413,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
2353	#define FP_M2_DIV_MASK 0x0000003f	2413	#define FP_M2_DIV_MASK 0x0000003f
2354	#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff	2414	#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
2355	#define FP_M2_DIV_SHIFT 0	2415	#define FP_M2_DIV_SHIFT 0
2356	#define DPLL_TEST 0x606c	2416	#define DPLL_TEST _MMIO(0x606c)
2357	#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)	2417	#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2358	#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)	2418	#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2359	#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)	2419	#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
@@ -2364,12 +2424,12 @@ enum skl_disp_power_wells { · 4 unmodified lines
2364	#define DPLLA_TEST_N_BYPASS (1 << 3)	2424	#define DPLLA_TEST_N_BYPASS (1 << 3)
2365	#define DPLLA_TEST_M_BYPASS (1 << 2)	2425	#define DPLLA_TEST_M_BYPASS (1 << 2)
2366	#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)	2426	#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
2367	#define D_STATE 0x6104	2427	#define D_STATE _MMIO(0x6104)
2368	#define DSTATE_GFX_RESET_I830 (1<<6)	2428	#define DSTATE_GFX_RESET_I830 (1<<6)
2369	#define DSTATE_PLL_D3_OFF (1<<3)	2429	#define DSTATE_PLL_D3_OFF (1<<3)
2370	#define DSTATE_GFX_CLOCK_GATING (1<<1)	2430	#define DSTATE_GFX_CLOCK_GATING (1<<1)
2371	#define DSTATE_DOT_CLOCK_GATING (1<<0)	2431	#define DSTATE_DOT_CLOCK_GATING (1<<0)
2372	#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)	2432	#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
2373	# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */	2433	# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2374	# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */	2434	# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2375	# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */	2435	# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -2408,7 +2468,7 @@ enum skl_disp_power_wells { · 32 unmodified lines
2408	# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */	2468	# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2409	# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */	2469	# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2410		2470
2411	#define RENCLK_GATE_D1 0x6204	2471	#define RENCLK_GATE_D1 _MMIO(0x6204)
2412	# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */	2472	# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2413	# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */	2473	# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2414	# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)	2474	# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
@@ -2472,35 +2532,35 @@ enum skl_disp_power_wells { · 57 unmodified lines
2472	# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)	2532	# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2473	# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)	2533	# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2474		2534
2475	#define RENCLK_GATE_D2 0x6208	2535	#define RENCLK_GATE_D2 _MMIO(0x6208)
2476	#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)	2536	#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2477	#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)	2537	#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2478	#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)	2538	#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
2479		2539
2480	#define VDECCLK_GATE_D 0x620C /* g4x only */	2540	#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
2481	#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)	2541	#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2482		2542
2483	#define RAMCLK_GATE_D 0x6210 /* CRL only */	2543	#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
2484	#define DEUC 0x6214 /* CRL only */	2544	#define DEUC _MMIO(0x6214) /* CRL only */
2485		2545
2486	#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)	2546	#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
2487	#define FW_CSPWRDWNEN (1<<15)	2547	#define FW_CSPWRDWNEN (1<<15)
2488		2548
2489	#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)	2549	#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
2490		2550
2491	#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)	2551	#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
2492	#define CDCLK_FREQ_SHIFT 4	2552	#define CDCLK_FREQ_SHIFT 4
2493	#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)	2553	#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2494	#define CZCLK_FREQ_MASK 0xf	2554	#define CZCLK_FREQ_MASK 0xf
2495		2555
2496	#define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C)	2556	#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
2497	#define PFI_CREDIT_63 (9 << 28) /* chv only */	2557	#define PFI_CREDIT_63 (9 << 28) /* chv only */
2498	#define PFI_CREDIT_31 (8 << 28) /* chv only */	2558	#define PFI_CREDIT_31 (8 << 28) /* chv only */
2499	#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */	2559	#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2500	#define PFI_CREDIT_RESEND (1 << 27)	2560	#define PFI_CREDIT_RESEND (1 << 27)
2501	#define VGA_FAST_MODE_DISABLE (1 << 14)	2561	#define VGA_FAST_MODE_DISABLE (1 << 14)
2502		2562
2503	#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)	2563	#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
2504		2564
2505	/*	2565	/*
2506	* Palette regs	2566	* Palette regs
@@ -2508,8 +2568,8 @@ enum skl_disp_power_wells { · 1 unmodified line
2508	#define PALETTE_A_OFFSET 0xa000	2568	#define PALETTE_A_OFFSET 0xa000
2509	#define PALETTE_B_OFFSET 0xa800	2569	#define PALETTE_B_OFFSET 0xa800
2510	#define CHV_PALETTE_C_OFFSET 0xc000	2570	#define CHV_PALETTE_C_OFFSET 0xc000
2511	#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \	2571	#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
2512	dev_priv->info.display_mmio_offset + (i) * 4)	2572	dev_priv->info.display_mmio_offset + (i) * 4)
2513		2573
2514	/* MCH MMIO space */	2574	/* MCH MMIO space */
2515		2575
@@ -2527,37 +2587,37 @@ enum skl_disp_power_wells { · 11 unmodified lines
2527		2587
2528	#define MCHBAR_MIRROR_BASE_SNB 0x140000	2588	#define MCHBAR_MIRROR_BASE_SNB 0x140000
2529		2589
2530	#define CTG_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x34)	2590	#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
2531	#define ELK_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x48)	2591	#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
2532	#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)	2592	#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
2533	#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)	2593	#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
2534		2594
2535	/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */	2595	/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2536	#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)	2596	#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2537		2597
2538	/* 915-945 and GM965 MCH register controlling DRAM channel access */	2598	/* 915-945 and GM965 MCH register controlling DRAM channel access */
2539	#define DCC 0x10200	2599	#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
2540	#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)	2600	#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2541	#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)	2601	#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2542	#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)	2602	#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2543	#define DCC_ADDRESSING_MODE_MASK (3 << 0)	2603	#define DCC_ADDRESSING_MODE_MASK (3 << 0)
2544	#define DCC_CHANNEL_XOR_DISABLE (1 << 10)	2604	#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2545	#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)	2605	#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2546	#define DCC2 0x10204	2606	#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
2547	#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)	2607	#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2548		2608
2549	/* Pineview MCH register contains DDR3 setting */	2609	/* Pineview MCH register contains DDR3 setting */
2550	#define CSHRDDR3CTL 0x101a8	2610	#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
2551	#define CSHRDDR3CTL_DDR3 (1 << 2)	2611	#define CSHRDDR3CTL_DDR3 (1 << 2)
2552		2612
2553	/* 965 MCH register controlling DRAM channel configuration */	2613	/* 965 MCH register controlling DRAM channel configuration */
2554	#define C0DRB3 0x10206	2614	#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
2555	#define C1DRB3 0x10606	2615	#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
2556		2616
2557	/* snb MCH registers for reading the DRAM channel configuration */	2617	/* snb MCH registers for reading the DRAM channel configuration */
2558	#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)	2618	#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
2559	#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)	2619	#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2560	#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)	2620	#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
2561	#define MAD_DIMM_ECC_MASK (0x3 << 24)	2621	#define MAD_DIMM_ECC_MASK (0x3 << 24)
2562	#define MAD_DIMM_ECC_OFF (0x0 << 24)	2622	#define MAD_DIMM_ECC_OFF (0x0 << 24)
2563	#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)	2623	#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
@@ -2577,14 +2637,14 @@ enum skl_disp_power_wells { · 13 unmodified lines
2577	#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)	2637	#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2578		2638
2579	/* snb MCH registers for priority tuning */	2639	/* snb MCH registers for priority tuning */
2580	#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)	2640	#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2581	#define MCH_SSKPD_WM0_MASK 0x3f	2641	#define MCH_SSKPD_WM0_MASK 0x3f
2582	#define MCH_SSKPD_WM0_VAL 0xc	2642	#define MCH_SSKPD_WM0_VAL 0xc
2583		2643
2584	#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)	2644	#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
2585		2645
2586	/* Clocking configuration register */	2646	/* Clocking configuration register */
2587	#define CLKCFG 0x10c00	2647	#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
2588	#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */	2648	#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2589	#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */	2649	#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2590	#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */	2650	#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
@@ -2600,26 +2660,26 @@ enum skl_disp_power_wells { · 9 unmodified lines
2600	#define CLKCFG_MEM_800 (3 << 4)	2660	#define CLKCFG_MEM_800 (3 << 4)
2601	#define CLKCFG_MEM_MASK (7 << 4)	2661	#define CLKCFG_MEM_MASK (7 << 4)
2602		2662
2603	#define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38)	2663	#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
2604	#define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f)	2664	#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
2605		2665
2606	#define TSC1 0x11001	2666	#define TSC1 _MMIO(0x11001)
2607	#define TSE (1<<0)	2667	#define TSE (1<<0)
2608	#define TR1 0x11006	2668	#define TR1 _MMIO(0x11006)
2609	#define TSFS 0x11020	2669	#define TSFS _MMIO(0x11020)
2610	#define TSFS_SLOPE_MASK 0x0000ff00	2670	#define TSFS_SLOPE_MASK 0x0000ff00
2611	#define TSFS_SLOPE_SHIFT 8	2671	#define TSFS_SLOPE_SHIFT 8
2612	#define TSFS_INTR_MASK 0x000000ff	2672	#define TSFS_INTR_MASK 0x000000ff
2613		2673
2614	#define CRSTANDVID 0x11100	2674	#define CRSTANDVID _MMIO(0x11100)
2615	#define PXVFREQ(i) (0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */	2675	#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2616	#define PXVFREQ_PX_MASK 0x7f000000	2676	#define PXVFREQ_PX_MASK 0x7f000000
2617	#define PXVFREQ_PX_SHIFT 24	2677	#define PXVFREQ_PX_SHIFT 24
2618	#define VIDFREQ_BASE 0x11110	2678	#define VIDFREQ_BASE _MMIO(0x11110)
2619	#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */	2679	#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2620	#define VIDFREQ2 0x11114	2680	#define VIDFREQ2 _MMIO(0x11114)
2621	#define VIDFREQ3 0x11118	2681	#define VIDFREQ3 _MMIO(0x11118)
2622	#define VIDFREQ4 0x1111c	2682	#define VIDFREQ4 _MMIO(0x1111c)
2623	#define VIDFREQ_P0_MASK 0x1f000000	2683	#define VIDFREQ_P0_MASK 0x1f000000
2624	#define VIDFREQ_P0_SHIFT 24	2684	#define VIDFREQ_P0_SHIFT 24
2625	#define VIDFREQ_P0_CSCLK_MASK 0x00f00000	2685	#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
@@ -2631,8 +2691,8 @@ enum skl_disp_power_wells { · 5 unmodified lines
2631	#define VIDFREQ_P1_CSCLK_MASK 0x000000f0	2691	#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2632	#define VIDFREQ_P1_CSCLK_SHIFT 4	2692	#define VIDFREQ_P1_CSCLK_SHIFT 4
2633	#define VIDFREQ_P1_CRCLK_MASK 0x0000000f	2693	#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2634	#define INTTOEXT_BASE_ILK 0x11300	2694	#define INTTOEXT_BASE_ILK _MMIO(0x11300)
2635	#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */	2695	#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
2636	#define INTTOEXT_MAP3_SHIFT 24	2696	#define INTTOEXT_MAP3_SHIFT 24
2637	#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)	2697	#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2638	#define INTTOEXT_MAP2_SHIFT 16	2698	#define INTTOEXT_MAP2_SHIFT 16
@@ -2641,7 +2701,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
2641	#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)	2701	#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2642	#define INTTOEXT_MAP0_SHIFT 0	2702	#define INTTOEXT_MAP0_SHIFT 0
2643	#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)	2703	#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2644	#define MEMSWCTL 0x11170 /* Ironlake only */	2704	#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
2645	#define MEMCTL_CMD_MASK 0xe000	2705	#define MEMCTL_CMD_MASK 0xe000
2646	#define MEMCTL_CMD_SHIFT 13	2706	#define MEMCTL_CMD_SHIFT 13
2647	#define MEMCTL_CMD_RCLK_OFF 0	2707	#define MEMCTL_CMD_RCLK_OFF 0
@@ -2656,8 +2716,8 @@ enum skl_disp_power_wells { · 8 unmodified lines
2656	#define MEMCTL_FREQ_SHIFT 8	2716	#define MEMCTL_FREQ_SHIFT 8
2657	#define MEMCTL_SFCAVM (1<<7)	2717	#define MEMCTL_SFCAVM (1<<7)
2658	#define MEMCTL_TGT_VID_MASK 0x007f	2718	#define MEMCTL_TGT_VID_MASK 0x007f
2659	#define MEMIHYST 0x1117c	2719	#define MEMIHYST _MMIO(0x1117c)
2660	#define MEMINTREN 0x11180 /* 16 bits */	2720	#define MEMINTREN _MMIO(0x11180) /* 16 bits */
2661	#define MEMINT_RSEXIT_EN (1<<8)	2721	#define MEMINT_RSEXIT_EN (1<<8)
2662	#define MEMINT_CX_SUPR_EN (1<<7)	2722	#define MEMINT_CX_SUPR_EN (1<<7)
2663	#define MEMINT_CONT_BUSY_EN (1<<6)	2723	#define MEMINT_CONT_BUSY_EN (1<<6)
@@ -2667,7 +2727,7 @@ enum skl_disp_power_wells { · 3 unmodified lines
2667	#define MEMINT_UP_EVAL_EN (1<<2)	2727	#define MEMINT_UP_EVAL_EN (1<<2)
2668	#define MEMINT_DOWN_EVAL_EN (1<<1)	2728	#define MEMINT_DOWN_EVAL_EN (1<<1)
2669	#define MEMINT_SW_CMD_EN (1<<0)	2729	#define MEMINT_SW_CMD_EN (1<<0)
2670	#define MEMINTRSTR 0x11182 /* 16 bits */	2730	#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
2671	#define MEM_RSEXIT_MASK 0xc000	2731	#define MEM_RSEXIT_MASK 0xc000
2672	#define MEM_RSEXIT_SHIFT 14	2732	#define MEM_RSEXIT_SHIFT 14
2673	#define MEM_CONT_BUSY_MASK 0x3000	2733	#define MEM_CONT_BUSY_MASK 0x3000
@@ -2687,7 +2747,7 @@ enum skl_disp_power_wells { · 13 unmodified lines
2687	#define MEM_INT_STEER_CMR 1	2747	#define MEM_INT_STEER_CMR 1
2688	#define MEM_INT_STEER_SMI 2	2748	#define MEM_INT_STEER_SMI 2
2689	#define MEM_INT_STEER_SCI 3	2749	#define MEM_INT_STEER_SCI 3
2690	#define MEMINTRSTS 0x11184	2750	#define MEMINTRSTS _MMIO(0x11184)
2691	#define MEMINT_RSEXIT (1<<7)	2751	#define MEMINT_RSEXIT (1<<7)
2692	#define MEMINT_CONT_BUSY (1<<6)	2752	#define MEMINT_CONT_BUSY (1<<6)
2693	#define MEMINT_AVG_BUSY (1<<5)	2753	#define MEMINT_AVG_BUSY (1<<5)
@@ -2696,7 +2756,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
2696	#define MEMINT_UP_EVAL (1<<2)	2756	#define MEMINT_UP_EVAL (1<<2)
2697	#define MEMINT_DOWN_EVAL (1<<1)	2757	#define MEMINT_DOWN_EVAL (1<<1)
2698	#define MEMINT_SW_CMD (1<<0)	2758	#define MEMINT_SW_CMD (1<<0)
2699	#define MEMMODECTL 0x11190	2759	#define MEMMODECTL _MMIO(0x11190)
2700	#define MEMMODE_BOOST_EN (1<<31)	2760	#define MEMMODE_BOOST_EN (1<<31)
2701	#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */	2761	#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2702	#define MEMMODE_BOOST_FREQ_SHIFT 24	2762	#define MEMMODE_BOOST_FREQ_SHIFT 24
@@ -2713,8 +2773,8 @@ enum skl_disp_power_wells { · 10 unmodified lines
2713	#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */	2773	#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2714	#define MEMMODE_FMAX_SHIFT 4	2774	#define MEMMODE_FMAX_SHIFT 4
2715	#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */	2775	#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2716	#define RCBMAXAVG 0x1119c	2776	#define RCBMAXAVG _MMIO(0x1119c)
2717	#define MEMSWCTL2 0x1119e /* Cantiga only */	2777	#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
2718	#define SWMEMCMD_RENDER_OFF (0 << 13)	2778	#define SWMEMCMD_RENDER_OFF (0 << 13)
2719	#define SWMEMCMD_RENDER_ON (1 << 13)	2779	#define SWMEMCMD_RENDER_ON (1 << 13)
2720	#define SWMEMCMD_SWFREQ (2 << 13)	2780	#define SWMEMCMD_SWFREQ (2 << 13)
@@ -2726,11 +2786,11 @@ enum skl_disp_power_wells { · 5 unmodified lines
2726	#define SWFREQ_MASK 0x0380 /* P0-7 */	2786	#define SWFREQ_MASK 0x0380 /* P0-7 */
2727	#define SWFREQ_SHIFT 7	2787	#define SWFREQ_SHIFT 7
2728	#define TARVID_MASK 0x001f	2788	#define TARVID_MASK 0x001f
2729	#define MEMSTAT_CTG 0x111a0	2789	#define MEMSTAT_CTG _MMIO(0x111a0)
2730	#define RCBMINAVG 0x111a0	2790	#define RCBMINAVG _MMIO(0x111a0)
2731	#define RCUPEI 0x111b0	2791	#define RCUPEI _MMIO(0x111b0)
2732	#define RCDNEI 0x111b4	2792	#define RCDNEI _MMIO(0x111b4)
2733	#define RSTDBYCTL 0x111b8	2793	#define RSTDBYCTL _MMIO(0x111b8)
2734	#define RS1EN (1<<31)	2794	#define RS1EN (1<<31)
2735	#define RS2EN (1<<30)	2795	#define RS2EN (1<<30)
2736	#define RS3EN (1<<29)	2796	#define RS3EN (1<<29)
@@ -2774,10 +2834,10 @@ enum skl_disp_power_wells { · 37 unmodified lines
2774	#define RS_CSTATE_C367_RS2 (3<<4)	2834	#define RS_CSTATE_C367_RS2 (3<<4)
2775	#define REDSAVES (1<<3) /* no context save if was idle during rs0 */	2835	#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2776	#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */	2836	#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2777	#define VIDCTL 0x111c0	2837	#define VIDCTL _MMIO(0x111c0)
2778	#define VIDSTS 0x111c8	2838	#define VIDSTS _MMIO(0x111c8)
2779	#define VIDSTART 0x111cc /* 8 bits */	2839	#define VIDSTART _MMIO(0x111cc) /* 8 bits */
2780	#define MEMSTAT_ILK 0x111f8	2840	#define MEMSTAT_ILK _MMIO(0x111f8)
2781	#define MEMSTAT_VID_MASK 0x7f00	2841	#define MEMSTAT_VID_MASK 0x7f00
2782	#define MEMSTAT_VID_SHIFT 8	2842	#define MEMSTAT_VID_SHIFT 8
2783	#define MEMSTAT_PSTATE_MASK 0x00f8	2843	#define MEMSTAT_PSTATE_MASK 0x00f8
@@ -2788,55 +2848,55 @@ enum skl_disp_power_wells { · 4 unmodified lines
2788	#define MEMSTAT_SRC_CTL_TRB 1	2848	#define MEMSTAT_SRC_CTL_TRB 1
2789	#define MEMSTAT_SRC_CTL_THM 2	2849	#define MEMSTAT_SRC_CTL_THM 2
2790	#define MEMSTAT_SRC_CTL_STDBY 3	2850	#define MEMSTAT_SRC_CTL_STDBY 3
2791	#define RCPREVBSYTUPAVG 0x113b8	2851	#define RCPREVBSYTUPAVG _MMIO(0x113b8)
2792	#define RCPREVBSYTDNAVG 0x113bc	2852	#define RCPREVBSYTDNAVG _MMIO(0x113bc)
2793	#define PMMISC 0x11214	2853	#define PMMISC _MMIO(0x11214)
2794	#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */	2854	#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2795	#define SDEW 0x1124c	2855	#define SDEW _MMIO(0x1124c)
2796	#define CSIEW0 0x11250	2856	#define CSIEW0 _MMIO(0x11250)
2797	#define CSIEW1 0x11254	2857	#define CSIEW1 _MMIO(0x11254)
2798	#define CSIEW2 0x11258	2858	#define CSIEW2 _MMIO(0x11258)
2799	#define PEW(i) (0x1125c + (i) * 4) /* 5 registers */	2859	#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
2800	#define DEW(i) (0x11270 + (i) * 4) /* 3 registers */	2860	#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
2801	#define MCHAFE 0x112c0	2861	#define MCHAFE _MMIO(0x112c0)
2802	#define CSIEC 0x112e0	2862	#define CSIEC _MMIO(0x112e0)
2803	#define DMIEC 0x112e4	2863	#define DMIEC _MMIO(0x112e4)
2804	#define DDREC 0x112e8	2864	#define DDREC _MMIO(0x112e8)
2805	#define PEG0EC 0x112ec	2865	#define PEG0EC _MMIO(0x112ec)
2806	#define PEG1EC 0x112f0	2866	#define PEG1EC _MMIO(0x112f0)
2807	#define GFXEC 0x112f4	2867	#define GFXEC _MMIO(0x112f4)
2808	#define RPPREVBSYTUPAVG 0x113b8	2868	#define RPPREVBSYTUPAVG _MMIO(0x113b8)
2809	#define RPPREVBSYTDNAVG 0x113bc	2869	#define RPPREVBSYTDNAVG _MMIO(0x113bc)
2810	#define ECR 0x11600	2870	#define ECR _MMIO(0x11600)
2811	#define ECR_GPFE (1<<31)	2871	#define ECR_GPFE (1<<31)
2812	#define ECR_IMONE (1<<30)	2872	#define ECR_IMONE (1<<30)
2813	#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */	2873	#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2814	#define OGW0 0x11608	2874	#define OGW0 _MMIO(0x11608)
2815	#define OGW1 0x1160c	2875	#define OGW1 _MMIO(0x1160c)
2816	#define EG0 0x11610	2876	#define EG0 _MMIO(0x11610)
2817	#define EG1 0x11614	2877	#define EG1 _MMIO(0x11614)
2818	#define EG2 0x11618	2878	#define EG2 _MMIO(0x11618)
2819	#define EG3 0x1161c	2879	#define EG3 _MMIO(0x1161c)
2820	#define EG4 0x11620	2880	#define EG4 _MMIO(0x11620)
2821	#define EG5 0x11624	2881	#define EG5 _MMIO(0x11624)
2822	#define EG6 0x11628	2882	#define EG6 _MMIO(0x11628)
2823	#define EG7 0x1162c	2883	#define EG7 _MMIO(0x1162c)
2824	#define PXW(i) (0x11664 + (i) * 4) /* 4 registers */	2884	#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
2825	#define PXWL(i) (0x11680 + (i) * 4) /* 8 registers */	2885	#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
2826	#define LCFUSE02 0x116c0	2886	#define LCFUSE02 _MMIO(0x116c0)
2827	#define LCFUSE_HIV_MASK 0x000000ff	2887	#define LCFUSE_HIV_MASK 0x000000ff
2828	#define CSIPLL0 0x12c10	2888	#define CSIPLL0 _MMIO(0x12c10)
2829	#define DDRMPLL1 0X12c20	2889	#define DDRMPLL1 _MMIO(0X12c20)
2830	#define PEG_BAND_GAP_DATA 0x14d68	2890	#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
2831		2891
2832	#define GEN6_GT_THREAD_STATUS_REG 0x13805c	2892	#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
2833	#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7	2893	#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2834		2894
2835	#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)	2895	#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2836	#define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070)	2896	#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
2837	#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)	2897	#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
2838	#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)	2898	#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2839	#define BXT_RP_STATE_CAP 0x138170	2899	#define BXT_RP_STATE_CAP _MMIO(0x138170)
2840		2900
2841	#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)	2901	#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
2842	#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)	2902	#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
@@ -2850,7 +2910,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
2850	/*	2910	/*
2851	* Logical Context regs	2911	* Logical Context regs
2852	*/	2912	*/
2853	#define CCID 0x2180	2913	#define CCID _MMIO(0x2180)
2854	#define CCID_EN (1<<0)	2914	#define CCID_EN (1<<0)
2855	/*	2915	/*
2856	* Notes on SNB/IVB/VLV context size:	2916	* Notes on SNB/IVB/VLV context size:
@@ -2865,7 +2925,7 @@ enum skl_disp_power_wells { · 8 unmodified lines
2865	* - GT1 size just indicates how much of render context	2925	* - GT1 size just indicates how much of render context
2866	* doesn't need saving on GT1	2926	* doesn't need saving on GT1
2867	*/	2927	*/
2868	#define CXT_SIZE 0x21a0	2928	#define CXT_SIZE _MMIO(0x21a0)
2869	#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)	2929	#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
2870	#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)	2930	#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
2871	#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)	2931	#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
@@ -2874,7 +2934,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
2874	#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \	2934	#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
2875	GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \	2935	GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2876	GEN6_CXT_PIPELINE_SIZE(cxt_reg))	2936	GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2877	#define GEN7_CXT_SIZE 0x21a8	2937	#define GEN7_CXT_SIZE _MMIO(0x21a8)
2878	#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)	2938	#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
2879	#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)	2939	#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
2880	#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)	2940	#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
@@ -2894,23 +2954,23 @@ enum skl_disp_power_wells { · 13 unmodified lines
2894	/* Same as Haswell, but 72064 bytes now. */	2954	/* Same as Haswell, but 72064 bytes now. */
2895	#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)	2955	#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2896		2956
2897	#define CHV_CLK_CTL1 0x101100	2957	#define CHV_CLK_CTL1 _MMIO(0x101100)
2898	#define VLV_CLK_CTL2 0x101104	2958	#define VLV_CLK_CTL2 _MMIO(0x101104)
2899	#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28	2959	#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2900		2960
2901	/*	2961	/*
2902	* Overlay regs	2962	* Overlay regs
2903	*/	2963	*/
2904		2964
2905	#define OVADD 0x30000	2965	#define OVADD _MMIO(0x30000)
2906	#define DOVSTA 0x30008	2966	#define DOVSTA _MMIO(0x30008)
2907	#define OC_BUF (0x3<<20)	2967	#define OC_BUF (0x3<<20)
2908	#define OGAMC5 0x30010	2968	#define OGAMC5 _MMIO(0x30010)
2909	#define OGAMC4 0x30014	2969	#define OGAMC4 _MMIO(0x30014)
2910	#define OGAMC3 0x30018	2970	#define OGAMC3 _MMIO(0x30018)
2911	#define OGAMC2 0x3001c	2971	#define OGAMC2 _MMIO(0x3001c)
2912	#define OGAMC1 0x30020	2972	#define OGAMC1 _MMIO(0x30020)
2913	#define OGAMC0 0x30024	2973	#define OGAMC0 _MMIO(0x30024)
2914		2974
2915	/*	2975	/*
2916	* Display engine regs	2976	* Display engine regs
@@ -2970,28 +3030,18 @@ enum skl_disp_power_wells { · 53 unmodified lines
2970	#define _PIPE_CRC_RES_4_B_IVB 0x61070	3030	#define _PIPE_CRC_RES_4_B_IVB 0x61070
2971	#define _PIPE_CRC_RES_5_B_IVB 0x61074	3031	#define _PIPE_CRC_RES_5_B_IVB 0x61074
2972		3032
2973	#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)	3033	#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
2974	#define PIPE_CRC_RES_1_IVB(pipe) \	3034	#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
2975	_TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)	3035	#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
2976	#define PIPE_CRC_RES_2_IVB(pipe) \	3036	#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
2977	_TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)	3037	#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
2978	#define PIPE_CRC_RES_3_IVB(pipe) \	3038	#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
2979	_TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)	3039
2980	#define PIPE_CRC_RES_4_IVB(pipe) \	3040	#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
2981	_TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)	3041	#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
2982	#define PIPE_CRC_RES_5_IVB(pipe) \	3042	#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
2983	_TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)	3043	#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
2984		3044	#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
2985	#define PIPE_CRC_RES_RED(pipe) \
2986	_TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
2987	#define PIPE_CRC_RES_GREEN(pipe) \
2988	_TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
2989	#define PIPE_CRC_RES_BLUE(pipe) \
2990	_TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
2991	#define PIPE_CRC_RES_RES1_I915(pipe) \
2992	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
2993	#define PIPE_CRC_RES_RES2_G4X(pipe) \
2994	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
2995		3045
2996	/* Pipe A timing regs */	3046	/* Pipe A timing regs */
2997	#define _HTOTAL_A 0x60000	3047	#define _HTOTAL_A 0x60000
@@ -3023,20 +3073,20 @@ enum skl_disp_power_wells { · 25 unmodified lines
3023	#define CHV_TRANSCODER_C_OFFSET 0x63000	3073	#define CHV_TRANSCODER_C_OFFSET 0x63000
3024	#define TRANSCODER_EDP_OFFSET 0x6f000	3074	#define TRANSCODER_EDP_OFFSET 0x6f000
3025		3075
3026	#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \	3076	#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
3027	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \	3077	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3028	dev_priv->info.display_mmio_offset)	3078	dev_priv->info.display_mmio_offset)
3029		3079
3030	#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)	3080	#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
3031	#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)	3081	#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
3032	#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)	3082	#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
3033	#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)	3083	#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
3034	#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)	3084	#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
3035	#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)	3085	#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
3036	#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)	3086	#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
3037	#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)	3087	#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
3038	#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)	3088	#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
3039	#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)	3089	#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
3040		3090
3041	/* VLV eDP PSR registers */	3091	/* VLV eDP PSR registers */
3042	#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)	3092	#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
@@ -3052,14 +3102,14 @@ enum skl_disp_power_wells { · 9 unmodified lines
3052	#define VLV_EDP_PSR_DBL_FRAME (1<<10)	3102	#define VLV_EDP_PSR_DBL_FRAME (1<<10)
3053	#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)	3103	#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
3054	#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16	3104	#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
3055	#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)	3105	#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
3056		3106
3057	#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)	3107	#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
3058	#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)	3108	#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
3059	#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)	3109	#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
3060	#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)	3110	#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
3061	#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)	3111	#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
3062	#define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB)	3112	#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
3063		3113
3064	#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)	3114	#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
3065	#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)	3115	#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
@@ -3072,11 +3122,12 @@ enum skl_disp_power_wells { · 6 unmodified lines
3072	#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)	3122	#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
3073	#define VLV_EDP_PSR_EXIT (5<<0)	3123	#define VLV_EDP_PSR_EXIT (5<<0)
3074	#define VLV_EDP_PSR_IN_TRANS (1<<7)	3124	#define VLV_EDP_PSR_IN_TRANS (1<<7)
3075	#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)	3125	#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
3076		3126
3077	/* HSW+ eDP PSR registers */	3127	/* HSW+ eDP PSR registers */
3078	#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)	3128	#define HSW_EDP_PSR_BASE 0x64800
3079	#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)	3129	#define BDW_EDP_PSR_BASE 0x6f800
		3130	#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
3080	#define EDP_PSR_ENABLE (1<<31)	3131	#define EDP_PSR_ENABLE (1<<31)
3081	#define BDW_PSR_SINGLE_FRAME (1<<30)	3132	#define BDW_PSR_SINGLE_FRAME (1<<30)
3082	#define EDP_PSR_LINK_STANDBY (1<<27)	3133	#define EDP_PSR_LINK_STANDBY (1<<27)
@@ -3099,14 +3150,10 @@ enum skl_disp_power_wells { · 16 unmodified lines
3099	#define EDP_PSR_TP1_TIME_0us (3<<4)	3150	#define EDP_PSR_TP1_TIME_0us (3<<4)
3100	#define EDP_PSR_IDLE_FRAME_SHIFT 0	3151	#define EDP_PSR_IDLE_FRAME_SHIFT 0
3101		3152
3102	#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)	3153	#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
3103	#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)	3154	#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
3104	#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
3105	#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
3106	#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
3107	#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
3108		3155
3109	#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)	3156	#define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40)
3110	#define EDP_PSR_STATUS_STATE_MASK (7<<29)	3157	#define EDP_PSR_STATUS_STATE_MASK (7<<29)
3111	#define EDP_PSR_STATUS_STATE_IDLE (0<<29)	3158	#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3112	#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)	3159	#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
@@ -3130,15 +3177,15 @@ enum skl_disp_power_wells { · 17 unmodified lines
3130	#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)	3177	#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3131	#define EDP_PSR_STATUS_IDLE_MASK 0xf	3178	#define EDP_PSR_STATUS_IDLE_MASK 0xf
3132		3179
3133	#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)	3180	#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
3134	#define EDP_PSR_PERF_CNT_MASK 0xffffff	3181	#define EDP_PSR_PERF_CNT_MASK 0xffffff
3135		3182
3136	#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)	3183	#define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60)
3137	#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)	3184	#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3138	#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)	3185	#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3139	#define EDP_PSR_DEBUG_MASK_HPD (1<<25)	3186	#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3140		3187
3141	#define EDP_PSR2_CTL 0x6f900	3188	#define EDP_PSR2_CTL _MMIO(0x6f900)
3142	#define EDP_PSR2_ENABLE (1<<31)	3189	#define EDP_PSR2_ENABLE (1<<31)
3143	#define EDP_SU_TRACK_ENABLE (1<<30)	3190	#define EDP_SU_TRACK_ENABLE (1<<30)
3144	#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)	3191	#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
@@ -3153,9 +3200,9 @@ enum skl_disp_power_wells { · 8 unmodified lines
3153	#define EDP_PSR2_IDLE_MASK 0xf	3200	#define EDP_PSR2_IDLE_MASK 0xf
3154		3201
3155	/* VGA port control */	3202	/* VGA port control */
3156	#define ADPA 0x61100	3203	#define ADPA _MMIO(0x61100)
3157	#define PCH_ADPA 0xe1100	3204	#define PCH_ADPA _MMIO(0xe1100)
3158	#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)	3205	#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
3159		3206
3160	#define ADPA_DAC_ENABLE (1<<31)	3207	#define ADPA_DAC_ENABLE (1<<31)
3161	#define ADPA_DAC_DISABLE 0	3208	#define ADPA_DAC_DISABLE 0
@@ -3201,7 +3248,7 @@ enum skl_disp_power_wells { · 39 unmodified lines
3201		3248
3202		3249
3203	/* Hotplug control (945+ only) */	3250	/* Hotplug control (945+ only) */
3204	#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)	3251	#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
3205	#define PORTB_HOTPLUG_INT_EN (1 << 29)	3252	#define PORTB_HOTPLUG_INT_EN (1 << 29)
3206	#define PORTC_HOTPLUG_INT_EN (1 << 28)	3253	#define PORTC_HOTPLUG_INT_EN (1 << 28)
3207	#define PORTD_HOTPLUG_INT_EN (1 << 27)	3254	#define PORTD_HOTPLUG_INT_EN (1 << 27)
@@ -3231,7 +3278,7 @@ enum skl_disp_power_wells { · 23 unmodified lines
3231	#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)	3278	#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3232	#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)	3279	#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
3233		3280
3234	#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)	3281	#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
3235	/*	3282	/*
3236	* HDMI/DP bits are gen4+	3283	* HDMI/DP bits are gen4+
3237	*	3284	*
@@ -3296,21 +3343,23 @@ enum skl_disp_power_wells { · 58 unmodified lines
3296		3343
3297	/* SDVO and HDMI port control.	3344	/* SDVO and HDMI port control.
3298	* The same register may be used for SDVO or HDMI */	3345	* The same register may be used for SDVO or HDMI */
3299	#define GEN3_SDVOB 0x61140	3346	#define _GEN3_SDVOB 0x61140
3300	#define GEN3_SDVOC 0x61160	3347	#define _GEN3_SDVOC 0x61160
		3348	#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
		3349	#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
3301	#define GEN4_HDMIB GEN3_SDVOB	3350	#define GEN4_HDMIB GEN3_SDVOB
3302	#define GEN4_HDMIC GEN3_SDVOC	3351	#define GEN4_HDMIC GEN3_SDVOC
3303	#define VLV_HDMIB (VLV_DISPLAY_BASE + GEN4_HDMIB)	3352	#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
3304	#define VLV_HDMIC (VLV_DISPLAY_BASE + GEN4_HDMIC)	3353	#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
3305	#define CHV_HDMID (VLV_DISPLAY_BASE + 0x6116C)	3354	#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
3306	#define PCH_SDVOB 0xe1140	3355	#define PCH_SDVOB _MMIO(0xe1140)
3307	#define PCH_HDMIB PCH_SDVOB	3356	#define PCH_HDMIB PCH_SDVOB
3308	#define PCH_HDMIC 0xe1150	3357	#define PCH_HDMIC _MMIO(0xe1150)
3309	#define PCH_HDMID 0xe1160	3358	#define PCH_HDMID _MMIO(0xe1160)
3310		3359
3311	#define PORT_DFT_I9XX 0x61150	3360	#define PORT_DFT_I9XX _MMIO(0x61150)
3312	#define DC_BALANCE_RESET (1 << 25)	3361	#define DC_BALANCE_RESET (1 << 25)
3313	#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)	3362	#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
3314	#define DC_BALANCE_RESET_VLV (1 << 31)	3363	#define DC_BALANCE_RESET_VLV (1 << 31)
3315	#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) \| (0x3 << 0))	3364	#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) \| (0x3 << 0))
3316	#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */	3365	#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
@@ -3370,9 +3419,12 @@ enum skl_disp_power_wells { · 53 unmodified lines
3370		3419
3371		3420
3372	/* DVO port control */	3421	/* DVO port control */
3373	#define DVOA 0x61120	3422	#define _DVOA 0x61120
3374	#define DVOB 0x61140	3423	#define DVOA _MMIO(_DVOA)
3375	#define DVOC 0x61160	3424	#define _DVOB 0x61140
		3425	#define DVOB _MMIO(_DVOB)
		3426	#define _DVOC 0x61160
		3427	#define DVOC _MMIO(_DVOC)
3376	#define DVO_ENABLE (1 << 31)	3428	#define DVO_ENABLE (1 << 31)
3377	#define DVO_PIPE_B_SELECT (1 << 30)	3429	#define DVO_PIPE_B_SELECT (1 << 30)
3378	#define DVO_PIPE_STALL_UNUSED (0 << 28)	3430	#define DVO_PIPE_STALL_UNUSED (0 << 28)
@@ -3397,14 +3449,14 @@ enum skl_disp_power_wells { · 18 unmodified lines
3397	#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */	3449	#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3398	#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */	3450	#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3399	#define DVO_PRESERVE_MASK (0x7<<24)	3451	#define DVO_PRESERVE_MASK (0x7<<24)
3400	#define DVOA_SRCDIM 0x61124	3452	#define DVOA_SRCDIM _MMIO(0x61124)
3401	#define DVOB_SRCDIM 0x61144	3453	#define DVOB_SRCDIM _MMIO(0x61144)
3402	#define DVOC_SRCDIM 0x61164	3454	#define DVOC_SRCDIM _MMIO(0x61164)
3403	#define DVO_SRCDIM_HORIZONTAL_SHIFT 12	3455	#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3404	#define DVO_SRCDIM_VERTICAL_SHIFT 0	3456	#define DVO_SRCDIM_VERTICAL_SHIFT 0
3405		3457
3406	/* LVDS port control */	3458	/* LVDS port control */
3407	#define LVDS 0x61180	3459	#define LVDS _MMIO(0x61180)
3408	/*	3460	/*
3409	* Enables the LVDS port. This bit must be set before DPLLs are enabled, as	3461	* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3410	* the DPLL semantics change when the LVDS is assigned to that pipe.	3462	* the DPLL semantics change when the LVDS is assigned to that pipe.
@@ -3454,13 +3506,13 @@ enum skl_disp_power_wells { · 43 unmodified lines
3454	#define LVDS_B0B3_POWER_UP (3 << 2)	3506	#define LVDS_B0B3_POWER_UP (3 << 2)
3455		3507
3456	/* Video Data Island Packet control */	3508	/* Video Data Island Packet control */
3457	#define VIDEO_DIP_DATA 0x61178	3509	#define VIDEO_DIP_DATA _MMIO(0x61178)
3458	/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC	3510	/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3459	* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte	3511	* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3460	* of the infoframe structure specified by CEA-861. */	3512	* of the infoframe structure specified by CEA-861. */
3461	#define VIDEO_DIP_DATA_SIZE 32	3513	#define VIDEO_DIP_DATA_SIZE 32
3462	#define VIDEO_DIP_VSC_DATA_SIZE 36	3514	#define VIDEO_DIP_VSC_DATA_SIZE 36
3463	#define VIDEO_DIP_CTL 0x61170	3515	#define VIDEO_DIP_CTL _MMIO(0x61170)
3464	/* Pre HSW: */	3516	/* Pre HSW: */
3465	#define VIDEO_DIP_ENABLE (1 << 31)	3517	#define VIDEO_DIP_ENABLE (1 << 31)
3466	#define VIDEO_DIP_PORT(port) ((port) << 29)	3518	#define VIDEO_DIP_PORT(port) ((port) << 29)
@@ -3487,7 +3539,7 @@ enum skl_disp_power_wells { · 20 unmodified lines
3487	#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)	3539	#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
3488		3540
3489	/* Panel power sequencing */	3541	/* Panel power sequencing */
3490	#define PP_STATUS 0x61200	3542	#define PP_STATUS _MMIO(0x61200)
3491	#define PP_ON (1 << 31)	3543	#define PP_ON (1 << 31)
3492	/*	3544	/*
3493	* Indicates that all dependencies of the panel are on:	3545	* Indicates that all dependencies of the panel are on:
@@ -3513,14 +3565,14 @@ enum skl_disp_power_wells { · 19 unmodified lines
3513	#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)	3565	#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3514	#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)	3566	#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3515	#define PP_SEQUENCE_STATE_RESET (0xf << 0)	3567	#define PP_SEQUENCE_STATE_RESET (0xf << 0)
3516	#define PP_CONTROL 0x61204	3568	#define PP_CONTROL _MMIO(0x61204)
3517	#define POWER_TARGET_ON (1 << 0)	3569	#define POWER_TARGET_ON (1 << 0)
3518	#define PP_ON_DELAYS 0x61208	3570	#define PP_ON_DELAYS _MMIO(0x61208)
3519	#define PP_OFF_DELAYS 0x6120c	3571	#define PP_OFF_DELAYS _MMIO(0x6120c)
3520	#define PP_DIVISOR 0x61210	3572	#define PP_DIVISOR _MMIO(0x61210)
3521		3573
3522	/* Panel fitting */	3574	/* Panel fitting */
3523	#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)	3575	#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
3524	#define PFIT_ENABLE (1 << 31)	3576	#define PFIT_ENABLE (1 << 31)
3525	#define PFIT_PIPE_MASK (3 << 29)	3577	#define PFIT_PIPE_MASK (3 << 29)
3526	#define PFIT_PIPE_SHIFT 29	3578	#define PFIT_PIPE_SHIFT 29
@@ -3538,7 +3590,7 @@ enum skl_disp_power_wells { · 11 unmodified lines
3538	#define PFIT_SCALING_PROGRAMMED (1 << 26)	3590	#define PFIT_SCALING_PROGRAMMED (1 << 26)
3539	#define PFIT_SCALING_PILLAR (2 << 26)	3591	#define PFIT_SCALING_PILLAR (2 << 26)
3540	#define PFIT_SCALING_LETTER (3 << 26)	3592	#define PFIT_SCALING_LETTER (3 << 26)
3541	#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)	3593	#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
3542	/* Pre-965 */	3594	/* Pre-965 */
3543	#define PFIT_VERT_SCALE_SHIFT 20	3595	#define PFIT_VERT_SCALE_SHIFT 20
3544	#define PFIT_VERT_SCALE_MASK 0xfff00000	3596	#define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -3550,25 +3602,25 @@ enum skl_disp_power_wells { · 5 unmodified lines
3550	#define PFIT_HORIZ_SCALE_SHIFT_965 0	3602	#define PFIT_HORIZ_SCALE_SHIFT_965 0
3551	#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff	3603	#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3552		3604
3553	#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)	3605	#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
3554		3606
3555	#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)	3607	#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3556	#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)	3608	#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3557	#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \	3609	#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3558	_VLV_BLC_PWM_CTL2_B)	3610	_VLV_BLC_PWM_CTL2_B)
3559		3611
3560	#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)	3612	#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3561	#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)	3613	#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3562	#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \	3614	#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3563	_VLV_BLC_PWM_CTL_B)	3615	_VLV_BLC_PWM_CTL_B)
3564		3616
3565	#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)	3617	#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3566	#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)	3618	#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3567	#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \	3619	#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3568	_VLV_BLC_HIST_CTL_B)	3620	_VLV_BLC_HIST_CTL_B)
3569		3621
3570	/* Backlight control */	3622	/* Backlight control */
3571	#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */	3623	#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3572	#define BLM_PWM_ENABLE (1 << 31)	3624	#define BLM_PWM_ENABLE (1 << 31)
3573	#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */	3625	#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3574	#define BLM_PIPE_SELECT (1 << 29)	3626	#define BLM_PIPE_SELECT (1 << 29)
@@ -3591,7 +3643,7 @@ enum skl_disp_power_wells { · 16 unmodified lines
3591	#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)	3643	#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3592	#define BLM_PHASE_IN_INCR_SHIFT (0)	3644	#define BLM_PHASE_IN_INCR_SHIFT (0)
3593	#define BLM_PHASE_IN_INCR_MASK (0xff << 0)	3645	#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3594	#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)	3646	#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
3595	/*	3647	/*
3596	* This is the most significant 15 bits of the number of backlight cycles in a	3648	* This is the most significant 15 bits of the number of backlight cycles in a
3597	* complete cycle of the modulated backlight control.	3649	* complete cycle of the modulated backlight control.
@@ -3613,25 +3665,25 @@ enum skl_disp_power_wells { · 15 unmodified lines
3613	#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)	3665	#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3614	#define BLM_POLARITY_PNV (1 << 0) /* pnv only */	3666	#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3615		3667
3616	#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)	3668	#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
3617	#define BLM_HISTOGRAM_ENABLE (1 << 31)	3669	#define BLM_HISTOGRAM_ENABLE (1 << 31)
3618		3670
3619	/* New registers for PCH-split platforms. Safe where new bits show up, the	3671	/* New registers for PCH-split platforms. Safe where new bits show up, the
3620	* register layout machtes with gen4 BLC_PWM_CTL[12]. */	3672	* register layout machtes with gen4 BLC_PWM_CTL[12]. */
3621	#define BLC_PWM_CPU_CTL2 0x48250	3673	#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
3622	#define BLC_PWM_CPU_CTL 0x48254	3674	#define BLC_PWM_CPU_CTL _MMIO(0x48254)
3623		3675
3624	#define HSW_BLC_PWM2_CTL 0x48350	3676	#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
3625		3677
3626	/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is	3678	/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3627	* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */	3679	* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3628	#define BLC_PWM_PCH_CTL1 0xc8250	3680	#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
3629	#define BLM_PCH_PWM_ENABLE (1 << 31)	3681	#define BLM_PCH_PWM_ENABLE (1 << 31)
3630	#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)	3682	#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3631	#define BLM_PCH_POLARITY (1 << 29)	3683	#define BLM_PCH_POLARITY (1 << 29)
3632	#define BLC_PWM_PCH_CTL2 0xc8254	3684	#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
3633		3685
3634	#define UTIL_PIN_CTL 0x48400	3686	#define UTIL_PIN_CTL _MMIO(0x48400)
3635	#define UTIL_PIN_ENABLE (1 << 31)	3687	#define UTIL_PIN_ENABLE (1 << 31)
3636		3688
3637	#define UTIL_PIN_PIPE(x) ((x) << 29)	3689	#define UTIL_PIN_PIPE(x) ((x) << 29)
@@ -3651,18 +3703,18 @@ enum skl_disp_power_wells { · 13 unmodified lines
3651	#define _BXT_BLC_PWM_FREQ2 0xC8354	3703	#define _BXT_BLC_PWM_FREQ2 0xC8354
3652	#define _BXT_BLC_PWM_DUTY2 0xC8358	3704	#define _BXT_BLC_PWM_DUTY2 0xC8358
3653		3705
3654	#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \	3706	#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
3655	_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)	3707	_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
3656	#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \	3708	#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
3657	_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)	3709	_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
3658	#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \	3710	#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
3659	_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)	3711	_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
3660		3712
3661	#define PCH_GTC_CTL 0xe7000	3713	#define PCH_GTC_CTL _MMIO(0xe7000)
3662	#define PCH_GTC_ENABLE (1 << 31)	3714	#define PCH_GTC_ENABLE (1 << 31)
3663		3715
3664	/* TV port control */	3716	/* TV port control */
3665	#define TV_CTL 0x68000	3717	#define TV_CTL _MMIO(0x68000)
3666	/* Enables the TV encoder */	3718	/* Enables the TV encoder */
3667	# define TV_ENC_ENABLE (1 << 31)	3719	# define TV_ENC_ENABLE (1 << 31)
3668	/* Sources the TV encoder input from pipe B instead of A. */	3720	/* Sources the TV encoder input from pipe B instead of A. */
@@ -3729,7 +3781,7 @@ enum skl_disp_power_wells { · 60 unmodified lines
3729	# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)	3781	# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3730	# define TV_TEST_MODE_MASK (7 << 0)	3782	# define TV_TEST_MODE_MASK (7 << 0)
3731		3783
3732	#define TV_DAC 0x68004	3784	#define TV_DAC _MMIO(0x68004)
3733	# define TV_DAC_SAVE 0x00ffff00	3785	# define TV_DAC_SAVE 0x00ffff00
3734	/*	3786	/*
3735	* Reports that DAC state change logic has reported change (RO).	3787	* Reports that DAC state change logic has reported change (RO).
@@ -3780,13 +3832,13 @@ enum skl_disp_power_wells { · 44 unmodified lines
3780	* where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with	3832	* where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3781	* -1 (0x3) being the only legal negative value.	3833	* -1 (0x3) being the only legal negative value.
3782	*/	3834	*/
3783	#define TV_CSC_Y 0x68010	3835	#define TV_CSC_Y _MMIO(0x68010)
3784	# define TV_RY_MASK 0x07ff0000	3836	# define TV_RY_MASK 0x07ff0000
3785	# define TV_RY_SHIFT 16	3837	# define TV_RY_SHIFT 16
3786	# define TV_GY_MASK 0x00000fff	3838	# define TV_GY_MASK 0x00000fff
3787	# define TV_GY_SHIFT 0	3839	# define TV_GY_SHIFT 0
3788		3840
3789	#define TV_CSC_Y2 0x68014	3841	#define TV_CSC_Y2 _MMIO(0x68014)
3790	# define TV_BY_MASK 0x07ff0000	3842	# define TV_BY_MASK 0x07ff0000
3791	# define TV_BY_SHIFT 16	3843	# define TV_BY_SHIFT 16
3792	/*	3844	/*
@@ -3797,13 +3849,13 @@ enum skl_disp_power_wells { · 4 unmodified lines
3797	# define TV_AY_MASK 0x000003ff	3849	# define TV_AY_MASK 0x000003ff
3798	# define TV_AY_SHIFT 0	3850	# define TV_AY_SHIFT 0
3799		3851
3800	#define TV_CSC_U 0x68018	3852	#define TV_CSC_U _MMIO(0x68018)
3801	# define TV_RU_MASK 0x07ff0000	3853	# define TV_RU_MASK 0x07ff0000
3802	# define TV_RU_SHIFT 16	3854	# define TV_RU_SHIFT 16
3803	# define TV_GU_MASK 0x000007ff	3855	# define TV_GU_MASK 0x000007ff
3804	# define TV_GU_SHIFT 0	3856	# define TV_GU_SHIFT 0
3805		3857
3806	#define TV_CSC_U2 0x6801c	3858	#define TV_CSC_U2 _MMIO(0x6801c)
3807	# define TV_BU_MASK 0x07ff0000	3859	# define TV_BU_MASK 0x07ff0000
3808	# define TV_BU_SHIFT 16	3860	# define TV_BU_SHIFT 16
3809	/*	3861	/*
@@ -3814,13 +3866,13 @@ enum skl_disp_power_wells { · 4 unmodified lines
3814	# define TV_AU_MASK 0x000003ff	3866	# define TV_AU_MASK 0x000003ff
3815	# define TV_AU_SHIFT 0	3867	# define TV_AU_SHIFT 0
3816		3868
3817	#define TV_CSC_V 0x68020	3869	#define TV_CSC_V _MMIO(0x68020)
3818	# define TV_RV_MASK 0x0fff0000	3870	# define TV_RV_MASK 0x0fff0000
3819	# define TV_RV_SHIFT 16	3871	# define TV_RV_SHIFT 16
3820	# define TV_GV_MASK 0x000007ff	3872	# define TV_GV_MASK 0x000007ff
3821	# define TV_GV_SHIFT 0	3873	# define TV_GV_SHIFT 0
3822		3874
3823	#define TV_CSC_V2 0x68024	3875	#define TV_CSC_V2 _MMIO(0x68024)
3824	# define TV_BV_MASK 0x07ff0000	3876	# define TV_BV_MASK 0x07ff0000
3825	# define TV_BV_SHIFT 16	3877	# define TV_BV_SHIFT 16
3826	/*	3878	/*
@@ -3831,7 +3883,7 @@ enum skl_disp_power_wells { · 4 unmodified lines
3831	# define TV_AV_MASK 0x000007ff	3883	# define TV_AV_MASK 0x000007ff
3832	# define TV_AV_SHIFT 0	3884	# define TV_AV_SHIFT 0
3833		3885
3834	#define TV_CLR_KNOBS 0x68028	3886	#define TV_CLR_KNOBS _MMIO(0x68028)
3835	/* 2s-complement brightness adjustment */	3887	/* 2s-complement brightness adjustment */
3836	# define TV_BRIGHTNESS_MASK 0xff000000	3888	# define TV_BRIGHTNESS_MASK 0xff000000
3837	# define TV_BRIGHTNESS_SHIFT 24	3889	# define TV_BRIGHTNESS_SHIFT 24
@@ -3845,7 +3897,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
3845	# define TV_HUE_MASK 0x000000ff	3897	# define TV_HUE_MASK 0x000000ff
3846	# define TV_HUE_SHIFT 0	3898	# define TV_HUE_SHIFT 0
3847		3899
3848	#define TV_CLR_LEVEL 0x6802c	3900	#define TV_CLR_LEVEL _MMIO(0x6802c)
3849	/* Controls the DAC level for black */	3901	/* Controls the DAC level for black */
3850	# define TV_BLACK_LEVEL_MASK 0x01ff0000	3902	# define TV_BLACK_LEVEL_MASK 0x01ff0000
3851	# define TV_BLACK_LEVEL_SHIFT 16	3903	# define TV_BLACK_LEVEL_SHIFT 16
@@ -3853,7 +3905,7 @@ enum skl_disp_power_wells { · 1 unmodified line
3853	# define TV_BLANK_LEVEL_MASK 0x000001ff	3905	# define TV_BLANK_LEVEL_MASK 0x000001ff
3854	# define TV_BLANK_LEVEL_SHIFT 0	3906	# define TV_BLANK_LEVEL_SHIFT 0
3855		3907
3856	#define TV_H_CTL_1 0x68030	3908	#define TV_H_CTL_1 _MMIO(0x68030)
3857	/* Number of pixels in the hsync. */	3909	/* Number of pixels in the hsync. */
3858	# define TV_HSYNC_END_MASK 0x1fff0000	3910	# define TV_HSYNC_END_MASK 0x1fff0000
3859	# define TV_HSYNC_END_SHIFT 16	3911	# define TV_HSYNC_END_SHIFT 16
@@ -3861,7 +3913,7 @@ enum skl_disp_power_wells { · 1 unmodified line
3861	# define TV_HTOTAL_MASK 0x00001fff	3913	# define TV_HTOTAL_MASK 0x00001fff
3862	# define TV_HTOTAL_SHIFT 0	3914	# define TV_HTOTAL_SHIFT 0
3863		3915
3864	#define TV_H_CTL_2 0x68034	3916	#define TV_H_CTL_2 _MMIO(0x68034)
3865	/* Enables the colorburst (needed for non-component color) */	3917	/* Enables the colorburst (needed for non-component color) */
3866	# define TV_BURST_ENA (1 << 31)	3918	# define TV_BURST_ENA (1 << 31)
3867	/* Offset of the colorburst from the start of hsync, in pixels minus one. */	3919	/* Offset of the colorburst from the start of hsync, in pixels minus one. */
@@ -3871,7 +3923,7 @@ enum skl_disp_power_wells { · 3 unmodified lines
3871	# define TV_HBURST_LEN_SHIFT 0	3923	# define TV_HBURST_LEN_SHIFT 0
3872	# define TV_HBURST_LEN_MASK 0x0001fff	3924	# define TV_HBURST_LEN_MASK 0x0001fff
3873		3925
3874	#define TV_H_CTL_3 0x68038	3926	#define TV_H_CTL_3 _MMIO(0x68038)
3875	/* End of hblank, measured in pixels minus one from start of hsync */	3927	/* End of hblank, measured in pixels minus one from start of hsync */
3876	# define TV_HBLANK_END_SHIFT 16	3928	# define TV_HBLANK_END_SHIFT 16
3877	# define TV_HBLANK_END_MASK 0x1fff0000	3929	# define TV_HBLANK_END_MASK 0x1fff0000
@@ -3879,7 +3931,7 @@ enum skl_disp_power_wells { · 1 unmodified line
3879	# define TV_HBLANK_START_SHIFT 0	3931	# define TV_HBLANK_START_SHIFT 0
3880	# define TV_HBLANK_START_MASK 0x0001fff	3932	# define TV_HBLANK_START_MASK 0x0001fff
3881		3933
3882	#define TV_V_CTL_1 0x6803c	3934	#define TV_V_CTL_1 _MMIO(0x6803c)
3883	/* XXX */	3935	/* XXX */
3884	# define TV_NBR_END_SHIFT 16	3936	# define TV_NBR_END_SHIFT 16
3885	# define TV_NBR_END_MASK 0x07ff0000	3937	# define TV_NBR_END_MASK 0x07ff0000
@@ -3890,7 +3942,7 @@ enum skl_disp_power_wells { · 4 unmodified lines
3890	# define TV_VI_END_F2_SHIFT 0	3942	# define TV_VI_END_F2_SHIFT 0
3891	# define TV_VI_END_F2_MASK 0x0000003f	3943	# define TV_VI_END_F2_MASK 0x0000003f
3892		3944
3893	#define TV_V_CTL_2 0x68040	3945	#define TV_V_CTL_2 _MMIO(0x68040)
3894	/* Length of vsync, in half lines */	3946	/* Length of vsync, in half lines */
3895	# define TV_VSYNC_LEN_MASK 0x07ff0000	3947	# define TV_VSYNC_LEN_MASK 0x07ff0000
3896	# define TV_VSYNC_LEN_SHIFT 16	3948	# define TV_VSYNC_LEN_SHIFT 16
@@ -3906,7 +3958,7 @@ enum skl_disp_power_wells { · 9 unmodified lines
3906	# define TV_VSYNC_START_F2_MASK 0x0000007f	3958	# define TV_VSYNC_START_F2_MASK 0x0000007f
3907	# define TV_VSYNC_START_F2_SHIFT 0	3959	# define TV_VSYNC_START_F2_SHIFT 0
3908		3960
3909	#define TV_V_CTL_3 0x68044	3961	#define TV_V_CTL_3 _MMIO(0x68044)
3910	/* Enables generation of the equalization signal */	3962	/* Enables generation of the equalization signal */
3911	# define TV_EQUAL_ENA (1 << 31)	3963	# define TV_EQUAL_ENA (1 << 31)
3912	/* Length of vsync, in half lines */	3964	/* Length of vsync, in half lines */
@@ -3924,7 +3976,7 @@ enum skl_disp_power_wells { · 11 unmodified lines
3924	# define TV_VEQ_START_F2_MASK 0x000007f	3976	# define TV_VEQ_START_F2_MASK 0x000007f
3925	# define TV_VEQ_START_F2_SHIFT 0	3977	# define TV_VEQ_START_F2_SHIFT 0
3926		3978
3927	#define TV_V_CTL_4 0x68048	3979	#define TV_V_CTL_4 _MMIO(0x68048)
3928	/*	3980	/*
3929	* Offset to start of vertical colorburst, measured in one less than the	3981	* Offset to start of vertical colorburst, measured in one less than the
3930	* number of lines from vertical start.	3982	* number of lines from vertical start.
@@ -3938,7 +3990,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
3938	# define TV_VBURST_END_F1_MASK 0x000000ff	3990	# define TV_VBURST_END_F1_MASK 0x000000ff
3939	# define TV_VBURST_END_F1_SHIFT 0	3991	# define TV_VBURST_END_F1_SHIFT 0
3940		3992
3941	#define TV_V_CTL_5 0x6804c	3993	#define TV_V_CTL_5 _MMIO(0x6804c)
3942	/*	3994	/*
3943	* Offset to start of vertical colorburst, measured in one less than the	3995	* Offset to start of vertical colorburst, measured in one less than the
3944	* number of lines from vertical start.	3996	* number of lines from vertical start.
@@ -3952,7 +4004,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
3952	# define TV_VBURST_END_F2_MASK 0x000000ff	4004	# define TV_VBURST_END_F2_MASK 0x000000ff
3953	# define TV_VBURST_END_F2_SHIFT 0	4005	# define TV_VBURST_END_F2_SHIFT 0
3954		4006
3955	#define TV_V_CTL_6 0x68050	4007	#define TV_V_CTL_6 _MMIO(0x68050)
3956	/*	4008	/*
3957	* Offset to start of vertical colorburst, measured in one less than the	4009	* Offset to start of vertical colorburst, measured in one less than the
3958	* number of lines from vertical start.	4010	* number of lines from vertical start.
@@ -3966,7 +4018,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
3966	# define TV_VBURST_END_F3_MASK 0x000000ff	4018	# define TV_VBURST_END_F3_MASK 0x000000ff
3967	# define TV_VBURST_END_F3_SHIFT 0	4019	# define TV_VBURST_END_F3_SHIFT 0
3968		4020
3969	#define TV_V_CTL_7 0x68054	4021	#define TV_V_CTL_7 _MMIO(0x68054)
3970	/*	4022	/*
3971	* Offset to start of vertical colorburst, measured in one less than the	4023	* Offset to start of vertical colorburst, measured in one less than the
3972	* number of lines from vertical start.	4024	* number of lines from vertical start.
@@ -3980,7 +4032,7 @@ enum skl_disp_power_wells { · 7 unmodified lines
3980	# define TV_VBURST_END_F4_MASK 0x000000ff	4032	# define TV_VBURST_END_F4_MASK 0x000000ff
3981	# define TV_VBURST_END_F4_SHIFT 0	4033	# define TV_VBURST_END_F4_SHIFT 0
3982		4034
3983	#define TV_SC_CTL_1 0x68060	4035	#define TV_SC_CTL_1 _MMIO(0x68060)
3984	/* Turns on the first subcarrier phase generation DDA */	4036	/* Turns on the first subcarrier phase generation DDA */
3985	# define TV_SC_DDA1_EN (1 << 31)	4037	# define TV_SC_DDA1_EN (1 << 31)
3986	/* Turns on the first subcarrier phase generation DDA */	4038	/* Turns on the first subcarrier phase generation DDA */
@@ -4002,7 +4054,7 @@ enum skl_disp_power_wells { · 15 unmodified lines
4002	# define TV_SCDDA1_INC_MASK 0x00000fff	4054	# define TV_SCDDA1_INC_MASK 0x00000fff
4003	# define TV_SCDDA1_INC_SHIFT 0	4055	# define TV_SCDDA1_INC_SHIFT 0
4004		4056
4005	#define TV_SC_CTL_2 0x68064	4057	#define TV_SC_CTL_2 _MMIO(0x68064)
4006	/* Sets the rollover for the second subcarrier phase generation DDA */	4058	/* Sets the rollover for the second subcarrier phase generation DDA */
4007	# define TV_SCDDA2_SIZE_MASK 0x7fff0000	4059	# define TV_SCDDA2_SIZE_MASK 0x7fff0000
4008	# define TV_SCDDA2_SIZE_SHIFT 16	4060	# define TV_SCDDA2_SIZE_SHIFT 16
@@ -4010,7 +4062,7 @@ enum skl_disp_power_wells { · 1 unmodified line
4010	# define TV_SCDDA2_INC_MASK 0x00007fff	4062	# define TV_SCDDA2_INC_MASK 0x00007fff
4011	# define TV_SCDDA2_INC_SHIFT 0	4063	# define TV_SCDDA2_INC_SHIFT 0
4012		4064
4013	#define TV_SC_CTL_3 0x68068	4065	#define TV_SC_CTL_3 _MMIO(0x68068)
4014	/* Sets the rollover for the third subcarrier phase generation DDA */	4066	/* Sets the rollover for the third subcarrier phase generation DDA */
4015	# define TV_SCDDA3_SIZE_MASK 0x7fff0000	4067	# define TV_SCDDA3_SIZE_MASK 0x7fff0000
4016	# define TV_SCDDA3_SIZE_SHIFT 16	4068	# define TV_SCDDA3_SIZE_SHIFT 16
@@ -4018,7 +4070,7 @@ enum skl_disp_power_wells { · 1 unmodified line
4018	# define TV_SCDDA3_INC_MASK 0x00007fff	4070	# define TV_SCDDA3_INC_MASK 0x00007fff
4019	# define TV_SCDDA3_INC_SHIFT 0	4071	# define TV_SCDDA3_INC_SHIFT 0
4020		4072
4021	#define TV_WIN_POS 0x68070	4073	#define TV_WIN_POS _MMIO(0x68070)
4022	/* X coordinate of the display from the start of horizontal active */	4074	/* X coordinate of the display from the start of horizontal active */
4023	# define TV_XPOS_MASK 0x1fff0000	4075	# define TV_XPOS_MASK 0x1fff0000
4024	# define TV_XPOS_SHIFT 16	4076	# define TV_XPOS_SHIFT 16
@@ -4026,7 +4078,7 @@ enum skl_disp_power_wells { · 1 unmodified line
4026	# define TV_YPOS_MASK 0x00000fff	4078	# define TV_YPOS_MASK 0x00000fff
4027	# define TV_YPOS_SHIFT 0	4079	# define TV_YPOS_SHIFT 0
4028		4080
4029	#define TV_WIN_SIZE 0x68074	4081	#define TV_WIN_SIZE _MMIO(0x68074)
4030	/* Horizontal size of the display window, measured in pixels*/	4082	/* Horizontal size of the display window, measured in pixels*/
4031	# define TV_XSIZE_MASK 0x1fff0000	4083	# define TV_XSIZE_MASK 0x1fff0000
4032	# define TV_XSIZE_SHIFT 16	4084	# define TV_XSIZE_SHIFT 16
@@ -4038,7 +4090,7 @@ enum skl_disp_power_wells { · 5 unmodified lines
4038	# define TV_YSIZE_MASK 0x00000fff	4090	# define TV_YSIZE_MASK 0x00000fff
4039	# define TV_YSIZE_SHIFT 0	4091	# define TV_YSIZE_SHIFT 0
4040		4092
4041	#define TV_FILTER_CTL_1 0x68080	4093	#define TV_FILTER_CTL_1 _MMIO(0x68080)
4042	/*	4094	/*
4043	* Enables automatic scaling calculation.	4095	* Enables automatic scaling calculation.
4044	*	4096	*
@@ -4071,7 +4123,7 @@ enum skl_disp_power_wells { · 26 unmodified lines
4071	# define TV_HSCALE_FRAC_MASK 0x00003fff	4123	# define TV_HSCALE_FRAC_MASK 0x00003fff
4072	# define TV_HSCALE_FRAC_SHIFT 0	4124	# define TV_HSCALE_FRAC_SHIFT 0
4073		4125
4074	#define TV_FILTER_CTL_2 0x68084	4126	#define TV_FILTER_CTL_2 _MMIO(0x68084)
4075	/*	4127	/*
4076	* Sets the integer part of the 3.15 fixed-point vertical scaling factor.	4128	* Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4077	*	4129	*
@@ -4087,7 +4139,7 @@ enum skl_disp_power_wells { · 9 unmodified lines
4087	# define TV_VSCALE_FRAC_MASK 0x00007fff	4139	# define TV_VSCALE_FRAC_MASK 0x00007fff
4088	# define TV_VSCALE_FRAC_SHIFT 0	4140	# define TV_VSCALE_FRAC_SHIFT 0
4089		4141
4090	#define TV_FILTER_CTL_3 0x68088	4142	#define TV_FILTER_CTL_3 _MMIO(0x68088)
4091	/*	4143	/*
4092	* Sets the integer part of the 3.15 fixed-point vertical scaling factor.	4144	* Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4093	*	4145	*
@@ -4107,7 +4159,7 @@ enum skl_disp_power_wells { · 13 unmodified lines
4107	# define TV_VSCALE_IP_FRAC_MASK 0x00007fff	4159	# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4108	# define TV_VSCALE_IP_FRAC_SHIFT 0	4160	# define TV_VSCALE_IP_FRAC_SHIFT 0
4109		4161
4110	#define TV_CC_CONTROL 0x68090	4162	#define TV_CC_CONTROL _MMIO(0x68090)
4111	# define TV_CC_ENABLE (1 << 31)	4163	# define TV_CC_ENABLE (1 << 31)
4112	/*	4164	/*
4113	* Specifies which field to send the CC data in.	4165	* Specifies which field to send the CC data in.
@@ -4123,7 +4175,7 @@ enum skl_disp_power_wells { · 9 unmodified lines
4123	# define TV_CC_LINE_MASK 0x0000003f	4175	# define TV_CC_LINE_MASK 0x0000003f
4124	# define TV_CC_LINE_SHIFT 0	4176	# define TV_CC_LINE_SHIFT 0
4125		4177
4126	#define TV_CC_DATA 0x68094	4178	#define TV_CC_DATA _MMIO(0x68094)
4127	# define TV_CC_RDY (1 << 31)	4179	# define TV_CC_RDY (1 << 31)
4128	/* Second word of CC data to be transmitted. */	4180	/* Second word of CC data to be transmitted. */
4129	# define TV_CC_DATA_2_MASK 0x007f0000	4181	# define TV_CC_DATA_2_MASK 0x007f0000
@@ -4132,20 +4184,20 @@ enum skl_disp_power_wells { · 2 unmodified lines
4132	# define TV_CC_DATA_1_MASK 0x0000007f	4184	# define TV_CC_DATA_1_MASK 0x0000007f
4133	# define TV_CC_DATA_1_SHIFT 0	4185	# define TV_CC_DATA_1_SHIFT 0
4134		4186
4135	#define TV_H_LUMA(i) (0x68100 + (i) * 4) /* 60 registers */	4187	#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
4136	#define TV_H_CHROMA(i) (0x68200 + (i) * 4) /* 60 registers */	4188	#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
4137	#define TV_V_LUMA(i) (0x68300 + (i) * 4) /* 43 registers */	4189	#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
4138	#define TV_V_CHROMA(i) (0x68400 + (i) * 4) /* 43 registers */	4190	#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
4139		4191
4140	/* Display Port */	4192	/* Display Port */
4141	#define DP_A 0x64000 /* eDP */	4193	#define DP_A _MMIO(0x64000) /* eDP */
4142	#define DP_B 0x64100	4194	#define DP_B _MMIO(0x64100)
4143	#define DP_C 0x64200	4195	#define DP_C _MMIO(0x64200)
4144	#define DP_D 0x64300	4196	#define DP_D _MMIO(0x64300)
4145		4197
4146	#define VLV_DP_B (VLV_DISPLAY_BASE + DP_B)	4198	#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
4147	#define VLV_DP_C (VLV_DISPLAY_BASE + DP_C)	4199	#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
4148	#define CHV_DP_D (VLV_DISPLAY_BASE + DP_D)	4200	#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
4149		4201
4150	#define DP_PORT_EN (1 << 31)	4202	#define DP_PORT_EN (1 << 31)
4151	#define DP_PIPEB_SELECT (1 << 30)	4203	#define DP_PIPEB_SELECT (1 << 30)
@@ -4199,7 +4251,7 @@ enum skl_disp_power_wells { · 47 unmodified lines
4199		4251
4200	/* eDP */	4252	/* eDP */
4201	#define DP_PLL_FREQ_270MHZ (0 << 16)	4253	#define DP_PLL_FREQ_270MHZ (0 << 16)
4202	#define DP_PLL_FREQ_160MHZ (1 << 16)	4254	#define DP_PLL_FREQ_162MHZ (1 << 16)
4203	#define DP_PLL_FREQ_MASK (3 << 16)	4255	#define DP_PLL_FREQ_MASK (3 << 16)
4204		4256
4205	/* locked once port is enabled */	4257	/* locked once port is enabled */
@@ -4232,33 +4284,36 @@ enum skl_disp_power_wells { · 26 unmodified lines
4232	* is 20 bytes in each direction, hence the 5 fixed	4284	* is 20 bytes in each direction, hence the 5 fixed
4233	* data registers	4285	* data registers
4234	*/	4286	*/
4235	#define DPA_AUX_CH_CTL 0x64010	4287	#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
4236	#define DPA_AUX_CH_DATA1 0x64014	4288	#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
4237	#define DPA_AUX_CH_DATA2 0x64018	4289	#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
4238	#define DPA_AUX_CH_DATA3 0x6401c	4290	#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
4239	#define DPA_AUX_CH_DATA4 0x64020	4291	#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
4240	#define DPA_AUX_CH_DATA5 0x64024	4292	#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
4241		4293
4242	#define DPB_AUX_CH_CTL 0x64110	4294	#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
4243	#define DPB_AUX_CH_DATA1 0x64114	4295	#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
4244	#define DPB_AUX_CH_DATA2 0x64118	4296	#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
4245	#define DPB_AUX_CH_DATA3 0x6411c	4297	#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
4246	#define DPB_AUX_CH_DATA4 0x64120	4298	#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
4247	#define DPB_AUX_CH_DATA5 0x64124	4299	#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
4248		4300
4249	#define DPC_AUX_CH_CTL 0x64210	4301	#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
4250	#define DPC_AUX_CH_DATA1 0x64214	4302	#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
4251	#define DPC_AUX_CH_DATA2 0x64218	4303	#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
4252	#define DPC_AUX_CH_DATA3 0x6421c	4304	#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
4253	#define DPC_AUX_CH_DATA4 0x64220	4305	#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
4254	#define DPC_AUX_CH_DATA5 0x64224	4306	#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
4255		4307
4256	#define DPD_AUX_CH_CTL 0x64310	4308	#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
4257	#define DPD_AUX_CH_DATA1 0x64314	4309	#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
4258	#define DPD_AUX_CH_DATA2 0x64318	4310	#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
4259	#define DPD_AUX_CH_DATA3 0x6431c	4311	#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
4260	#define DPD_AUX_CH_DATA4 0x64320	4312	#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
4261	#define DPD_AUX_CH_DATA5 0x64324	4313	#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
		4314
		4315	#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
		4316	#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
4262		4317
4263	#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)	4318	#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4264	#define DP_AUX_CH_CTL_DONE (1 << 30)	4319	#define DP_AUX_CH_CTL_DONE (1 << 30)
@@ -4335,10 +4390,10 @@ enum skl_disp_power_wells { · 70 unmodified lines
4335	#define _PIPEB_LINK_N_G4X 0x71064	4390	#define _PIPEB_LINK_N_G4X 0x71064
4336	#define PIPEA_DP_LINK_N_MASK (0xffffff)	4391	#define PIPEA_DP_LINK_N_MASK (0xffffff)
4337		4392
4338	#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)	4393	#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4339	#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)	4394	#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4340	#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)	4395	#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4341	#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)	4396	#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
4342		4397
4343	/* Display & cursor control */	4398	/* Display & cursor control */
4344		4399
@@ -4454,15 +4509,15 @@ enum skl_disp_power_wells { · 109 unmodified lines
4454	*/	4509	*/
4455	#define PIPE_EDP_OFFSET 0x7f000	4510	#define PIPE_EDP_OFFSET 0x7f000
4456		4511
4457	#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \	4512	#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
4458	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \	4513	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4459	dev_priv->info.display_mmio_offset)	4514	dev_priv->info.display_mmio_offset)
4460		4515
4461	#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)	4516	#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
4462	#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)	4517	#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
4463	#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)	4518	#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
4464	#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)	4519	#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
4465	#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)	4520	#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
4466		4521
4467	#define _PIPE_MISC_A 0x70030	4522	#define _PIPE_MISC_A 0x70030
4468	#define _PIPE_MISC_B 0x71030	4523	#define _PIPE_MISC_B 0x71030
@@ -4474,9 +4529,9 @@ enum skl_disp_power_wells { · 5 unmodified lines
4474	#define PIPEMISC_DITHER_ENABLE (1<<4)	4529	#define PIPEMISC_DITHER_ENABLE (1<<4)
4475	#define PIPEMISC_DITHER_TYPE_MASK (3<<2)	4530	#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4476	#define PIPEMISC_DITHER_TYPE_SP (0<<2)	4531	#define PIPEMISC_DITHER_TYPE_SP (0<<2)
4477	#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)	4532	#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
4478		4533
4479	#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)	4534	#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
4480	#define PIPEB_LINE_COMPARE_INT_EN (1<<29)	4535	#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
4481	#define PIPEB_HLINE_INT_EN (1<<28)	4536	#define PIPEB_HLINE_INT_EN (1<<28)
4482	#define PIPEB_VBLANK_INT_EN (1<<27)	4537	#define PIPEB_VBLANK_INT_EN (1<<27)
@@ -4497,7 +4552,7 @@ enum skl_disp_power_wells { · 14 unmodified lines
4497	#define SPRITEE_FLIPDONE_INT_EN (1<<9)	4552	#define SPRITEE_FLIPDONE_INT_EN (1<<9)
4498	#define PLANEC_FLIPDONE_INT_EN (1<<8)	4553	#define PLANEC_FLIPDONE_INT_EN (1<<8)
4499		4554
4500	#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */	4555	#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4501	#define SPRITEF_INVALID_GTT_INT_EN (1<<27)	4556	#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4502	#define SPRITEE_INVALID_GTT_INT_EN (1<<26)	4557	#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4503	#define PLANEC_INVALID_GTT_INT_EN (1<<25)	4558	#define PLANEC_INVALID_GTT_INT_EN (1<<25)
@@ -4527,7 +4582,7 @@ enum skl_disp_power_wells { · 23 unmodified lines
4527	#define DPINVGTT_STATUS_MASK 0xff	4582	#define DPINVGTT_STATUS_MASK 0xff
4528	#define DPINVGTT_STATUS_MASK_CHV 0xfff	4583	#define DPINVGTT_STATUS_MASK_CHV 0xfff
4529		4584
4530	#define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)	4585	#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
4531	#define DSPARB_CSTART_MASK (0x7f << 7)	4586	#define DSPARB_CSTART_MASK (0x7f << 7)
4532	#define DSPARB_CSTART_SHIFT 7	4587	#define DSPARB_CSTART_SHIFT 7
4533	#define DSPARB_BSTART_MASK (0x7f)	4588	#define DSPARB_BSTART_MASK (0x7f)
@@ -4542,7 +4597,7 @@ enum skl_disp_power_wells { · 8 unmodified lines
4542	#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)	4597	#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4543	#define DSPARB_SPRITED_SHIFT_VLV 24	4598	#define DSPARB_SPRITED_SHIFT_VLV 24
4544	#define DSPARB_SPRITED_MASK_VLV (0xff << 24)	4599	#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
4545	#define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */	4600	#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4546	#define DSPARB_SPRITEA_HI_SHIFT_VLV 0	4601	#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4547	#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)	4602	#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4548	#define DSPARB_SPRITEB_HI_SHIFT_VLV 4	4603	#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
@@ -4555,14 +4610,14 @@ enum skl_disp_power_wells { · 6 unmodified lines
4555	#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)	4610	#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4556	#define DSPARB_SPRITEF_HI_SHIFT_VLV 20	4611	#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4557	#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)	4612	#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
4558	#define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */	4613	#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
4559	#define DSPARB_SPRITEE_SHIFT_VLV 0	4614	#define DSPARB_SPRITEE_SHIFT_VLV 0
4560	#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)	4615	#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4561	#define DSPARB_SPRITEF_SHIFT_VLV 8	4616	#define DSPARB_SPRITEF_SHIFT_VLV 8
4562	#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)	4617	#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
4563		4618
4564	/* pnv/gen4/g4x/vlv/chv */	4619	/* pnv/gen4/g4x/vlv/chv */
4565	#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)	4620	#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
4566	#define DSPFW_SR_SHIFT 23	4621	#define DSPFW_SR_SHIFT 23
4567	#define DSPFW_SR_MASK (0x1ff<<23)	4622	#define DSPFW_SR_MASK (0x1ff<<23)
4568	#define DSPFW_CURSORB_SHIFT 16	4623	#define DSPFW_CURSORB_SHIFT 16
@@ -4573,7 +4628,7 @@ enum skl_disp_power_wells { · 4 unmodified lines
4573	#define DSPFW_PLANEA_SHIFT 0	4628	#define DSPFW_PLANEA_SHIFT 0
4574	#define DSPFW_PLANEA_MASK (0x7f<<0)	4629	#define DSPFW_PLANEA_MASK (0x7f<<0)
4575	#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */	4630	#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4576	#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)	4631	#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
4577	#define DSPFW_FBC_SR_EN (1<<31) /* g4x */	4632	#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4578	#define DSPFW_FBC_SR_SHIFT 28	4633	#define DSPFW_FBC_SR_SHIFT 28
4579	#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */	4634	#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
@@ -4589,7 +4644,7 @@ enum skl_disp_power_wells { · 9 unmodified lines
4589	#define DSPFW_SPRITEA_SHIFT 0	4644	#define DSPFW_SPRITEA_SHIFT 0
4590	#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */	4645	#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4591	#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */	4646	#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4592	#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)	4647	#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
4593	#define DSPFW_HPLL_SR_EN (1<<31)	4648	#define DSPFW_HPLL_SR_EN (1<<31)
4594	#define PINEVIEW_SELF_REFRESH_EN (1<<30)	4649	#define PINEVIEW_SELF_REFRESH_EN (1<<30)
4595	#define DSPFW_CURSOR_SR_SHIFT 24	4650	#define DSPFW_CURSOR_SR_SHIFT 24
@@ -4600,14 +4655,14 @@ enum skl_disp_power_wells { · 4 unmodified lines
4600	#define DSPFW_HPLL_SR_MASK (0x1ff<<0)	4655	#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4601		4656
4602	/* vlv/chv */	4657	/* vlv/chv */
4603	#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)	4658	#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
4604	#define DSPFW_SPRITEB_WM1_SHIFT 16	4659	#define DSPFW_SPRITEB_WM1_SHIFT 16
4605	#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)	4660	#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4606	#define DSPFW_CURSORA_WM1_SHIFT 8	4661	#define DSPFW_CURSORA_WM1_SHIFT 8
4607	#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)	4662	#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4608	#define DSPFW_SPRITEA_WM1_SHIFT 0	4663	#define DSPFW_SPRITEA_WM1_SHIFT 0
4609	#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)	4664	#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4610	#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)	4665	#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
4611	#define DSPFW_PLANEB_WM1_SHIFT 24	4666	#define DSPFW_PLANEB_WM1_SHIFT 24
4612	#define DSPFW_PLANEB_WM1_MASK (0xff<<24)	4667	#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4613	#define DSPFW_PLANEA_WM1_SHIFT 16	4668	#define DSPFW_PLANEA_WM1_SHIFT 16
@@ -4616,11 +4671,11 @@ enum skl_disp_power_wells { · 2 unmodified lines
4616	#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)	4671	#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4617	#define DSPFW_CURSOR_SR_WM1_SHIFT 0	4672	#define DSPFW_CURSOR_SR_WM1_SHIFT 0
4618	#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)	4673	#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4619	#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)	4674	#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
4620	#define DSPFW_SR_WM1_SHIFT 0	4675	#define DSPFW_SR_WM1_SHIFT 0
4621	#define DSPFW_SR_WM1_MASK (0x1ff<<0)	4676	#define DSPFW_SR_WM1_MASK (0x1ff<<0)
4622	#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)	4677	#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
4623	#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */	4678	#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4624	#define DSPFW_SPRITED_WM1_SHIFT 24	4679	#define DSPFW_SPRITED_WM1_SHIFT 24
4625	#define DSPFW_SPRITED_WM1_MASK (0xff<<24)	4680	#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4626	#define DSPFW_SPRITED_SHIFT 16	4681	#define DSPFW_SPRITED_SHIFT 16
@@ -4629,7 +4684,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
4629	#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)	4684	#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4630	#define DSPFW_SPRITEC_SHIFT 0	4685	#define DSPFW_SPRITEC_SHIFT 0
4631	#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)	4686	#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
4632	#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)	4687	#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
4633	#define DSPFW_SPRITEF_WM1_SHIFT 24	4688	#define DSPFW_SPRITEF_WM1_SHIFT 24
4634	#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)	4689	#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4635	#define DSPFW_SPRITEF_SHIFT 16	4690	#define DSPFW_SPRITEF_SHIFT 16
@@ -4638,7 +4693,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
4638	#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)	4693	#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4639	#define DSPFW_SPRITEE_SHIFT 0	4694	#define DSPFW_SPRITEE_SHIFT 0
4640	#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)	4695	#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
4641	#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */	4696	#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4642	#define DSPFW_PLANEC_WM1_SHIFT 24	4697	#define DSPFW_PLANEC_WM1_SHIFT 24
4643	#define DSPFW_PLANEC_WM1_MASK (0xff<<24)	4698	#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4644	#define DSPFW_PLANEC_SHIFT 16	4699	#define DSPFW_PLANEC_SHIFT 16
@@ -4649,7 +4704,7 @@ enum skl_disp_power_wells { · 4 unmodified lines
4649	#define DSPFW_CURSORC_MASK (0x3f<<0)	4704	#define DSPFW_CURSORC_MASK (0x3f<<0)
4650		4705
4651	/* vlv/chv high order bits */	4706	/* vlv/chv high order bits */
4652	#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)	4707	#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
4653	#define DSPFW_SR_HI_SHIFT 24	4708	#define DSPFW_SR_HI_SHIFT 24
4654	#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */	4709	#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4655	#define DSPFW_SPRITEF_HI_SHIFT 23	4710	#define DSPFW_SPRITEF_HI_SHIFT 23
@@ -4670,7 +4725,7 @@ enum skl_disp_power_wells { · 14 unmodified lines
4670	#define DSPFW_SPRITEA_HI_MASK (1<<4)	4725	#define DSPFW_SPRITEA_HI_MASK (1<<4)
4671	#define DSPFW_PLANEA_HI_SHIFT 0	4726	#define DSPFW_PLANEA_HI_SHIFT 0
4672	#define DSPFW_PLANEA_HI_MASK (1<<0)	4727	#define DSPFW_PLANEA_HI_MASK (1<<0)
4673	#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)	4728	#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
4674	#define DSPFW_SR_WM1_HI_SHIFT 24	4729	#define DSPFW_SR_WM1_HI_SHIFT 24
4675	#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */	4730	#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4676	#define DSPFW_SPRITEF_WM1_HI_SHIFT 23	4731	#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
@@ -4693,7 +4748,7 @@ enum skl_disp_power_wells { · 16 unmodified lines
4693	#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)	4748	#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4694		4749
4695	/* drain latency register values*/	4750	/* drain latency register values*/
4696	#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))	4751	#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4697	#define DDL_CURSOR_SHIFT 24	4752	#define DDL_CURSOR_SHIFT 24
4698	#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))	4753	#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4699	#define DDL_PLANE_SHIFT 0	4754	#define DDL_PLANE_SHIFT 0
@@ -4701,7 +4756,7 @@ enum skl_disp_power_wells { · 1 unmodified line
4701	#define DDL_PRECISION_LOW (0<<7)	4756	#define DDL_PRECISION_LOW (0<<7)
4702	#define DRAIN_LATENCY_MASK 0x7f	4757	#define DRAIN_LATENCY_MASK 0x7f
4703		4758
4704	#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)	4759	#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
4705	#define CBR_PND_DEADLINE_DISABLE (1<<31)	4760	#define CBR_PND_DEADLINE_DISABLE (1<<31)
4706	#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)	4761	#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
4707		4762
@@ -4739,51 +4794,51 @@ enum skl_disp_power_wells { · 31 unmodified lines
4739	#define I965_CURSOR_DFT_WM 8	4794	#define I965_CURSOR_DFT_WM 8
4740		4795
4741	/* Watermark register definitions for SKL */	4796	/* Watermark register definitions for SKL */
4742	#define CUR_WM_A_0 0x70140	4797	#define _CUR_WM_A_0 0x70140
4743	#define CUR_WM_B_0 0x71140	4798	#define _CUR_WM_B_0 0x71140
4744	#define PLANE_WM_1_A_0 0x70240	4799	#define _PLANE_WM_1_A_0 0x70240
4745	#define PLANE_WM_1_B_0 0x71240	4800	#define _PLANE_WM_1_B_0 0x71240
4746	#define PLANE_WM_2_A_0 0x70340	4801	#define _PLANE_WM_2_A_0 0x70340
4747	#define PLANE_WM_2_B_0 0x71340	4802	#define _PLANE_WM_2_B_0 0x71340
4748	#define PLANE_WM_TRANS_1_A_0 0x70268	4803	#define _PLANE_WM_TRANS_1_A_0 0x70268
4749	#define PLANE_WM_TRANS_1_B_0 0x71268	4804	#define _PLANE_WM_TRANS_1_B_0 0x71268
4750	#define PLANE_WM_TRANS_2_A_0 0x70368	4805	#define _PLANE_WM_TRANS_2_A_0 0x70368
4751	#define PLANE_WM_TRANS_2_B_0 0x71368	4806	#define _PLANE_WM_TRANS_2_B_0 0x71368
4752	#define CUR_WM_TRANS_A_0 0x70168	4807	#define _CUR_WM_TRANS_A_0 0x70168
4753	#define CUR_WM_TRANS_B_0 0x71168	4808	#define _CUR_WM_TRANS_B_0 0x71168
4754	#define PLANE_WM_EN (1 << 31)	4809	#define PLANE_WM_EN (1 << 31)
4755	#define PLANE_WM_LINES_SHIFT 14	4810	#define PLANE_WM_LINES_SHIFT 14
4756	#define PLANE_WM_LINES_MASK 0x1f	4811	#define PLANE_WM_LINES_MASK 0x1f
4757	#define PLANE_WM_BLOCKS_MASK 0x3ff	4812	#define PLANE_WM_BLOCKS_MASK 0x3ff
4758		4813
4759	#define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)	4814	#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
4760	#define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))	4815	#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
4761	#define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)	4816	#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
4762		4817
4763	#define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)	4818	#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4764	#define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)	4819	#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
4765	#define _PLANE_WM_BASE(pipe, plane) \	4820	#define _PLANE_WM_BASE(pipe, plane) \
4766	_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))	4821	_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4767	#define PLANE_WM(pipe, plane, level) \	4822	#define PLANE_WM(pipe, plane, level) \
4768	(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))	4823	_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4769	#define _PLANE_WM_TRANS_1(pipe) \	4824	#define _PLANE_WM_TRANS_1(pipe) \
4770	_PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)	4825	_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
4771	#define _PLANE_WM_TRANS_2(pipe) \	4826	#define _PLANE_WM_TRANS_2(pipe) \
4772	_PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)	4827	_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
4773	#define PLANE_WM_TRANS(pipe, plane) \	4828	#define PLANE_WM_TRANS(pipe, plane) \
4774	_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))	4829	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
4775		4830
4776	/* define the Watermark register on Ironlake */	4831	/* define the Watermark register on Ironlake */
4777	#define WM0_PIPEA_ILK 0x45100	4832	#define WM0_PIPEA_ILK _MMIO(0x45100)
4778	#define WM0_PIPE_PLANE_MASK (0xffff<<16)	4833	#define WM0_PIPE_PLANE_MASK (0xffff<<16)
4779	#define WM0_PIPE_PLANE_SHIFT 16	4834	#define WM0_PIPE_PLANE_SHIFT 16
4780	#define WM0_PIPE_SPRITE_MASK (0xff<<8)	4835	#define WM0_PIPE_SPRITE_MASK (0xff<<8)
4781	#define WM0_PIPE_SPRITE_SHIFT 8	4836	#define WM0_PIPE_SPRITE_SHIFT 8
4782	#define WM0_PIPE_CURSOR_MASK (0xff)	4837	#define WM0_PIPE_CURSOR_MASK (0xff)
4783		4838
4784	#define WM0_PIPEB_ILK 0x45104	4839	#define WM0_PIPEB_ILK _MMIO(0x45104)
4785	#define WM0_PIPEC_IVB 0x45200	4840	#define WM0_PIPEC_IVB _MMIO(0x45200)
4786	#define WM1_LP_ILK 0x45108	4841	#define WM1_LP_ILK _MMIO(0x45108)
4787	#define WM1_LP_SR_EN (1<<31)	4842	#define WM1_LP_SR_EN (1<<31)
4788	#define WM1_LP_LATENCY_SHIFT 24	4843	#define WM1_LP_LATENCY_SHIFT 24
4789	#define WM1_LP_LATENCY_MASK (0x7f<<24)	4844	#define WM1_LP_LATENCY_MASK (0x7f<<24)
@@ -4793,13 +4848,13 @@ enum skl_disp_power_wells { · 3 unmodified lines
4793	#define WM1_LP_SR_MASK (0x7ff<<8)	4848	#define WM1_LP_SR_MASK (0x7ff<<8)
4794	#define WM1_LP_SR_SHIFT 8	4849	#define WM1_LP_SR_SHIFT 8
4795	#define WM1_LP_CURSOR_MASK (0xff)	4850	#define WM1_LP_CURSOR_MASK (0xff)
4796	#define WM2_LP_ILK 0x4510c	4851	#define WM2_LP_ILK _MMIO(0x4510c)
4797	#define WM2_LP_EN (1<<31)	4852	#define WM2_LP_EN (1<<31)
4798	#define WM3_LP_ILK 0x45110	4853	#define WM3_LP_ILK _MMIO(0x45110)
4799	#define WM3_LP_EN (1<<31)	4854	#define WM3_LP_EN (1<<31)
4800	#define WM1S_LP_ILK 0x45120	4855	#define WM1S_LP_ILK _MMIO(0x45120)
4801	#define WM2S_LP_IVB 0x45124	4856	#define WM2S_LP_IVB _MMIO(0x45124)
4802	#define WM3S_LP_IVB 0x45128	4857	#define WM3S_LP_IVB _MMIO(0x45128)
4803	#define WM1S_LP_EN (1<<31)	4858	#define WM1S_LP_EN (1<<31)
4804		4859
4805	#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \	4860	#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
@@ -4807,7 +4862,7 @@ enum skl_disp_power_wells { · 1 unmodified line
4807	((fbc) << WM1_LP_FBC_SHIFT) \| ((pri) << WM1_LP_SR_SHIFT) \| (cur))	4862	((fbc) << WM1_LP_FBC_SHIFT) \| ((pri) << WM1_LP_SR_SHIFT) \| (cur))
4808		4863
4809	/* Memory latency timer register */	4864	/* Memory latency timer register */
4810	#define MLTR_ILK 0x11222	4865	#define MLTR_ILK _MMIO(0x11222)
4811	#define MLTR_WM1_SHIFT 0	4866	#define MLTR_WM1_SHIFT 0
4812	#define MLTR_WM2_SHIFT 8	4867	#define MLTR_WM2_SHIFT 8
4813	/* the unit of memory self-refresh latency time is 0.5us */	4868	/* the unit of memory self-refresh latency time is 0.5us */
@@ -4815,7 +4870,7 @@ enum skl_disp_power_wells { · 1 unmodified line
4815		4870
4816		4871
4817	/* the address where we get all kinds of latency value */	4872	/* the address where we get all kinds of latency value */
4818	#define SSKPD 0x5d10	4873	#define SSKPD _MMIO(0x5d10)
4819	#define SSKPD_WM_MASK 0x3f	4874	#define SSKPD_WM_MASK 0x3f
4820	#define SSKPD_WM0_SHIFT 0	4875	#define SSKPD_WM0_SHIFT 0
4821	#define SSKPD_WM1_SHIFT 8	4876	#define SSKPD_WM1_SHIFT 8
@@ -4848,8 +4903,8 @@ enum skl_disp_power_wells { · 26 unmodified lines
4848	/* GM45+ just has to be different */	4903	/* GM45+ just has to be different */
4849	#define _PIPEA_FRMCOUNT_G4X 0x70040	4904	#define _PIPEA_FRMCOUNT_G4X 0x70040
4850	#define _PIPEA_FLIPCOUNT_G4X 0x70044	4905	#define _PIPEA_FLIPCOUNT_G4X 0x70044
4851	#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)	4906	#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4852	#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)	4907	#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
4853		4908
4854	/* Cursor A & B regs */	4909	/* Cursor A & B regs */
4855	#define _CURACNTR 0x70080	4910	#define _CURACNTR 0x70080
@@ -4887,7 +4942,7 @@ enum skl_disp_power_wells { · 31 unmodified lines
4887	#define CURSOR_POS_SIGN 0x8000	4942	#define CURSOR_POS_SIGN 0x8000
4888	#define CURSOR_X_SHIFT 0	4943	#define CURSOR_X_SHIFT 0
4889	#define CURSOR_Y_SHIFT 16	4944	#define CURSOR_Y_SHIFT 16
4890	#define CURSIZE 0x700a0	4945	#define CURSIZE _MMIO(0x700a0)
4891	#define _CURBCNTR 0x700c0	4946	#define _CURBCNTR 0x700c0
4892	#define _CURBBASE 0x700c4	4947	#define _CURBBASE 0x700c4
4893	#define _CURBPOS 0x700c8	4948	#define _CURBPOS 0x700c8
@@ -4896,7 +4951,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
4896	#define _CURBBASE_IVB 0x71084	4951	#define _CURBBASE_IVB 0x71084
4897	#define _CURBPOS_IVB 0x71088	4952	#define _CURBPOS_IVB 0x71088
4898		4953
4899	#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \	4954	#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
4900	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \	4955	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4901	dev_priv->info.display_mmio_offset)	4956	dev_priv->info.display_mmio_offset)
4902		4957
@@ -4957,16 +5012,16 @@ enum skl_disp_power_wells { · 54 unmodified lines
4957	#define _DSPAOFFSET 0x701A4 /* HSW */	5012	#define _DSPAOFFSET 0x701A4 /* HSW */
4958	#define _DSPASURFLIVE 0x701AC	5013	#define _DSPASURFLIVE 0x701AC
4959		5014
4960	#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)	5015	#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
4961	#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)	5016	#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
4962	#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)	5017	#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
4963	#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)	5018	#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
4964	#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)	5019	#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
4965	#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)	5020	#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
4966	#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)	5021	#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
4967	#define DSPLINOFF(plane) DSPADDR(plane)	5022	#define DSPLINOFF(plane) DSPADDR(plane)
4968	#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)	5023	#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
4969	#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)	5024	#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
4970		5025
4971	/* CHV pipe B blender and primary plane */	5026	/* CHV pipe B blender and primary plane */
4972	#define _CHV_BLEND_A 0x60a00	5027	#define _CHV_BLEND_A 0x60a00
@@ -4980,11 +5035,11 @@ enum skl_disp_power_wells { · 7 unmodified lines
4980	#define _PRIMCNSTALPHA_A 0x60a10	5035	#define _PRIMCNSTALPHA_A 0x60a10
4981	#define PRIM_CONST_ALPHA_ENABLE (1<<31)	5036	#define PRIM_CONST_ALPHA_ENABLE (1<<31)
4982		5037
4983	#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)	5038	#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
4984	#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)	5039	#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
4985	#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)	5040	#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
4986	#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)	5041	#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
4987	#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)	5042	#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
4988		5043
4989	/* Display/Sprite base address macros */	5044	/* Display/Sprite base address macros */
4990	#define DISP_BASEADDR_MASK (0xfffff000)	5045	#define DISP_BASEADDR_MASK (0xfffff000)
@@ -5002,9 +5057,10 @@ enum skl_disp_power_wells { · 11 unmodified lines
5002	* [10:1f] all	5057	* [10:1f] all
5003	* [30:32] all	5058	* [30:32] all
5004	*/	5059	*/
5005	#define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)	5060	#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5006	#define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)	5061	#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5007	#define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)	5062	#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
		5063	#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
5008		5064
5009	/* Pipe B */	5065	/* Pipe B */
5010	#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)	5066	#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
@@ -5086,18 +5142,18 @@ enum skl_disp_power_wells { · 75 unmodified lines
5086	#define _DVSBSCALE 0x73204	5142	#define _DVSBSCALE 0x73204
5087	#define _DVSBGAMC 0x73300	5143	#define _DVSBGAMC 0x73300
5088		5144
5089	#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)	5145	#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5090	#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)	5146	#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5091	#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)	5147	#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5092	#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)	5148	#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
5093	#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)	5149	#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
5094	#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)	5150	#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5095	#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)	5151	#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5096	#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)	5152	#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5097	#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)	5153	#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5098	#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)	5154	#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5099	#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)	5155	#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5100	#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)	5156	#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
5101		5157
5102	#define _SPRA_CTL 0x70280	5158	#define _SPRA_CTL 0x70280
5103	#define SPRITE_ENABLE (1<<31)	5159	#define SPRITE_ENABLE (1<<31)
@@ -5160,20 +5216,20 @@ enum skl_disp_power_wells { · 56 unmodified lines
5160	#define _SPRB_SCALE 0x71304	5216	#define _SPRB_SCALE 0x71304
5161	#define _SPRB_GAMC 0x71400	5217	#define _SPRB_GAMC 0x71400
5162		5218
5163	#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)	5219	#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5164	#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)	5220	#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5165	#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)	5221	#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5166	#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)	5222	#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
5167	#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)	5223	#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5168	#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)	5224	#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5169	#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)	5225	#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5170	#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)	5226	#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5171	#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)	5227	#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5172	#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)	5228	#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5173	#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)	5229	#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5174	#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)	5230	#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5175	#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)	5231	#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5176	#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)	5232	#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
5177		5233
5178	#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)	5234	#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
5179	#define SP_ENABLE (1<<31)	5235	#define SP_ENABLE (1<<31)
@@ -5223,18 +5279,18 @@ enum skl_disp_power_wells { · 43 unmodified lines
5223	#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)	5279	#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5224	#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)	5280	#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
5225		5281
5226	#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)	5282	#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5227	#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)	5283	#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5228	#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)	5284	#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5229	#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)	5285	#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5230	#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)	5286	#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5231	#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)	5287	#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5232	#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)	5288	#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5233	#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)	5289	#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5234	#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)	5290	#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5235	#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)	5291	#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5236	#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)	5292	#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5237	#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)	5293	#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
5238		5294
5239	/*	5295	/*
5240	* CHV pipe B sprite CSC	5296	* CHV pipe B sprite CSC
@@ -5243,29 +5299,29 @@ enum skl_disp_power_wells { · 2 unmodified lines
5243	* \|yg\| = \|c3 c4 c5\| x \|yg + yg_ioff\| + \|yg_ooff\|	5299	* \|yg\| = \|c3 c4 c5\| x \|yg + yg_ioff\| + \|yg_ooff\|
5244	* \|cb\| \|c6 c7 c8\| \|cb + cr_ioff\| \|cb_ooff\|	5300	* \|cb\| \|c6 c7 c8\| \|cb + cr_ioff\| \|cb_ooff\|
5245	*/	5301	*/
5246	#define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)	5302	#define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5247	#define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)	5303	#define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5248	#define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)	5304	#define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5249	#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */	5305	#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5250	#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */	5306	#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5251		5307
5252	#define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)	5308	#define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5253	#define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)	5309	#define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5254	#define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)	5310	#define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5255	#define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)	5311	#define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5256	#define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)	5312	#define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5257	#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */	5313	#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5258	#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */	5314	#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5259		5315
5260	#define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)	5316	#define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5261	#define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)	5317	#define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5262	#define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)	5318	#define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5263	#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */	5319	#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5264	#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */	5320	#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5265		5321
5266	#define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)	5322	#define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5267	#define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)	5323	#define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5268	#define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)	5324	#define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5269	#define SPCSC_OMAX(x) ((x) << 16) /* u10 */	5325	#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5270	#define SPCSC_OMIN(x) ((x) << 0) /* u10 */	5326	#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5271		5327
@@ -5346,7 +5402,7 @@ enum skl_disp_power_wells { · 74 unmodified lines
5346	#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)	5402	#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5347	#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)	5403	#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5348	#define PLANE_CTL(pipe, plane) \	5404	#define PLANE_CTL(pipe, plane) \
5349	_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))	5405	_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5350		5406
5351	#define _PLANE_STRIDE_1_B 0x71188	5407	#define _PLANE_STRIDE_1_B 0x71188
5352	#define _PLANE_STRIDE_2_B 0x71288	5408	#define _PLANE_STRIDE_2_B 0x71288
@@ -5358,7 +5414,7 @@ enum skl_disp_power_wells { · 5 unmodified lines
5358	#define _PLANE_STRIDE_3(pipe) \	5414	#define _PLANE_STRIDE_3(pipe) \
5359	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)	5415	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5360	#define PLANE_STRIDE(pipe, plane) \	5416	#define PLANE_STRIDE(pipe, plane) \
5361	_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))	5417	_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5362		5418
5363	#define _PLANE_POS_1_B 0x7118c	5419	#define _PLANE_POS_1_B 0x7118c
5364	#define _PLANE_POS_2_B 0x7128c	5420	#define _PLANE_POS_2_B 0x7128c
@@ -5367,7 +5423,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
5367	#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)	5423	#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5368	#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)	5424	#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5369	#define PLANE_POS(pipe, plane) \	5425	#define PLANE_POS(pipe, plane) \
5370	_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))	5426	_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5371		5427
5372	#define _PLANE_SIZE_1_B 0x71190	5428	#define _PLANE_SIZE_1_B 0x71190
5373	#define _PLANE_SIZE_2_B 0x71290	5429	#define _PLANE_SIZE_2_B 0x71290
@@ -5376,7 +5432,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
5376	#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)	5432	#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5377	#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)	5433	#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5378	#define PLANE_SIZE(pipe, plane) \	5434	#define PLANE_SIZE(pipe, plane) \
5379	_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))	5435	_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5380		5436
5381	#define _PLANE_SURF_1_B 0x7119c	5437	#define _PLANE_SURF_1_B 0x7119c
5382	#define _PLANE_SURF_2_B 0x7129c	5438	#define _PLANE_SURF_2_B 0x7129c
@@ -5385,35 +5441,35 @@ enum skl_disp_power_wells { · 2 unmodified lines
5385	#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)	5441	#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5386	#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)	5442	#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5387	#define PLANE_SURF(pipe, plane) \	5443	#define PLANE_SURF(pipe, plane) \
5388	_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))	5444	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5389		5445
5390	#define _PLANE_OFFSET_1_B 0x711a4	5446	#define _PLANE_OFFSET_1_B 0x711a4
5391	#define _PLANE_OFFSET_2_B 0x712a4	5447	#define _PLANE_OFFSET_2_B 0x712a4
5392	#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)	5448	#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5393	#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)	5449	#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5394	#define PLANE_OFFSET(pipe, plane) \	5450	#define PLANE_OFFSET(pipe, plane) \
5395	_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))	5451	_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5396		5452
5397	#define _PLANE_KEYVAL_1_B 0x71194	5453	#define _PLANE_KEYVAL_1_B 0x71194
5398	#define _PLANE_KEYVAL_2_B 0x71294	5454	#define _PLANE_KEYVAL_2_B 0x71294
5399	#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)	5455	#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5400	#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)	5456	#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5401	#define PLANE_KEYVAL(pipe, plane) \	5457	#define PLANE_KEYVAL(pipe, plane) \
5402	_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))	5458	_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5403		5459
5404	#define _PLANE_KEYMSK_1_B 0x71198	5460	#define _PLANE_KEYMSK_1_B 0x71198
5405	#define _PLANE_KEYMSK_2_B 0x71298	5461	#define _PLANE_KEYMSK_2_B 0x71298
5406	#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)	5462	#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5407	#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)	5463	#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5408	#define PLANE_KEYMSK(pipe, plane) \	5464	#define PLANE_KEYMSK(pipe, plane) \
5409	_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))	5465	_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5410		5466
5411	#define _PLANE_KEYMAX_1_B 0x711a0	5467	#define _PLANE_KEYMAX_1_B 0x711a0
5412	#define _PLANE_KEYMAX_2_B 0x712a0	5468	#define _PLANE_KEYMAX_2_B 0x712a0
5413	#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)	5469	#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5414	#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)	5470	#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5415	#define PLANE_KEYMAX(pipe, plane) \	5471	#define PLANE_KEYMAX(pipe, plane) \
5416	_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))	5472	_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5417		5473
5418	#define _PLANE_BUF_CFG_1_B 0x7127c	5474	#define _PLANE_BUF_CFG_1_B 0x7127c
5419	#define _PLANE_BUF_CFG_2_B 0x7137c	5475	#define _PLANE_BUF_CFG_2_B 0x7137c
@@ -5422,7 +5478,7 @@ enum skl_disp_power_wells { · 2 unmodified lines
5422	#define _PLANE_BUF_CFG_2(pipe) \	5478	#define _PLANE_BUF_CFG_2(pipe) \
5423	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)	5479	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5424	#define PLANE_BUF_CFG(pipe, plane) \	5480	#define PLANE_BUF_CFG(pipe, plane) \
5425	_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))	5481	_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5426		5482
5427	#define _PLANE_NV12_BUF_CFG_1_B 0x71278	5483	#define _PLANE_NV12_BUF_CFG_1_B 0x71278
5428	#define _PLANE_NV12_BUF_CFG_2_B 0x71378	5484	#define _PLANE_NV12_BUF_CFG_2_B 0x71378
@@ -5431,26 +5487,26 @@ enum skl_disp_power_wells { · 2 unmodified lines
5431	#define _PLANE_NV12_BUF_CFG_2(pipe) \	5487	#define _PLANE_NV12_BUF_CFG_2(pipe) \
5432	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)	5488	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5433	#define PLANE_NV12_BUF_CFG(pipe, plane) \	5489	#define PLANE_NV12_BUF_CFG(pipe, plane) \
5434	_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))	5490	_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5435		5491
5436	/* SKL new cursor registers */	5492	/* SKL new cursor registers */
5437	#define _CUR_BUF_CFG_A 0x7017c	5493	#define _CUR_BUF_CFG_A 0x7017c
5438	#define _CUR_BUF_CFG_B 0x7117c	5494	#define _CUR_BUF_CFG_B 0x7117c
5439	#define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)	5495	#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5440		5496
5441	/* VBIOS regs */	5497	/* VBIOS regs */
5442	#define VGACNTRL 0x71400	5498	#define VGACNTRL _MMIO(0x71400)
5443	# define VGA_DISP_DISABLE (1 << 31)	5499	# define VGA_DISP_DISABLE (1 << 31)
5444	# define VGA_2X_MODE (1 << 30)	5500	# define VGA_2X_MODE (1 << 30)
5445	# define VGA_PIPE_B_SELECT (1 << 29)	5501	# define VGA_PIPE_B_SELECT (1 << 29)
5446		5502
5447	#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)	5503	#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
5448		5504
5449	/* Ironlake */	5505	/* Ironlake */
5450		5506
5451	#define CPU_VGACNTRL 0x41000	5507	#define CPU_VGACNTRL _MMIO(0x41000)
5452		5508
5453	#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030	5509	#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
5454	#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)	5510	#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5455	#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */	5511	#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5456	#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */	5512	#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
@@ -5463,26 +5519,26 @@ enum skl_disp_power_wells { · 6 unmodified lines
5463	#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)	5519	#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
5464		5520
5465	/* refresh rate hardware control */	5521	/* refresh rate hardware control */
5466	#define RR_HW_CTL 0x45300	5522	#define RR_HW_CTL _MMIO(0x45300)
5467	#define RR_HW_LOW_POWER_FRAMES_MASK 0xff	5523	#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5468	#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00	5524	#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5469		5525
5470	#define FDI_PLL_BIOS_0 0x46000	5526	#define FDI_PLL_BIOS_0 _MMIO(0x46000)
5471	#define FDI_PLL_FB_CLOCK_MASK 0xff	5527	#define FDI_PLL_FB_CLOCK_MASK 0xff
5472	#define FDI_PLL_BIOS_1 0x46004	5528	#define FDI_PLL_BIOS_1 _MMIO(0x46004)
5473	#define FDI_PLL_BIOS_2 0x46008	5529	#define FDI_PLL_BIOS_2 _MMIO(0x46008)
5474	#define DISPLAY_PORT_PLL_BIOS_0 0x4600c	5530	#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
5475	#define DISPLAY_PORT_PLL_BIOS_1 0x46010	5531	#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
5476	#define DISPLAY_PORT_PLL_BIOS_2 0x46014	5532	#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
5477		5533
5478	#define PCH_3DCGDIS0 0x46020	5534	#define PCH_3DCGDIS0 _MMIO(0x46020)
5479	# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)	5535	# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5480	# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)	5536	# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5481		5537
5482	#define PCH_3DCGDIS1 0x46024	5538	#define PCH_3DCGDIS1 _MMIO(0x46024)
5483	# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)	5539	# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5484		5540
5485	#define FDI_PLL_FREQ_CTL 0x46030	5541	#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
5486	#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)	5542	#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5487	#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00	5543	#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5488	#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff	5544	#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
@@ -5519,14 +5575,14 @@ enum skl_disp_power_wells { · 30 unmodified lines
5519	#define _PIPEB_LINK_M2 0x61048	5575	#define _PIPEB_LINK_M2 0x61048
5520	#define _PIPEB_LINK_N2 0x6104c	5576	#define _PIPEB_LINK_N2 0x6104c
5521		5577
5522	#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)	5578	#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5523	#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)	5579	#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5524	#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)	5580	#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5525	#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)	5581	#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5526	#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)	5582	#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5527	#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)	5583	#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5528	#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)	5584	#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5529	#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)	5585	#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
5530		5586
5531	/* CPU panel fitter */	5587	/* CPU panel fitter */
5532	/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */	5588	/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
@@ -5549,11 +5605,11 @@ enum skl_disp_power_wells { · 16 unmodified lines
5549	#define _PFA_HSCALE 0x68090	5605	#define _PFA_HSCALE 0x68090
5550	#define _PFB_HSCALE 0x68890	5606	#define _PFB_HSCALE 0x68890
5551		5607
5552	#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)	5608	#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5553	#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)	5609	#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5554	#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)	5610	#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5555	#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)	5611	#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5556	#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)	5612	#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5557		5613
5558	#define _PSA_CTL 0x68180	5614	#define _PSA_CTL 0x68180
5559	#define _PSB_CTL 0x68980	5615	#define _PSB_CTL 0x68980
@@ -5563,9 +5619,9 @@ enum skl_disp_power_wells { · 3 unmodified lines
5563	#define _PSA_WIN_POS 0x68170	5619	#define _PSA_WIN_POS 0x68170
5564	#define _PSB_WIN_POS 0x68970	5620	#define _PSB_WIN_POS 0x68970
5565		5621
5566	#define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)	5622	#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5567	#define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)	5623	#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5568	#define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)	5624	#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5569		5625
5570	/*	5626	/*
5571	* Skylake scalers	5627	* Skylake scalers
@@ -5654,48 +5710,63 @@ enum skl_disp_power_wells { · 82 unmodified lines
5654	#define _PS_ECC_STAT_1C 0x691D0	5710	#define _PS_ECC_STAT_1C 0x691D0
5655		5711
5656	#define _ID(id, a, b) ((a) + (id)*((b)-(a)))	5712	#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5657	#define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \	5713	#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
5658	_ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \	5714	_ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5659	_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))	5715	_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5660	#define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \	5716	#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
5661	_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \	5717	_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5662	_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))	5718	_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5663	#define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \	5719	#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
5664	_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \	5720	_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5665	_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))	5721	_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5666	#define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \	5722	#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
5667	_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \	5723	_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5668	_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))	5724	_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5669	#define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \	5725	#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
5670	_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \	5726	_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5671	_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))	5727	_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5672	#define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \	5728	#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
5673	_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \	5729	_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5674	_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))	5730	_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5675	#define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \	5731	#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
5676	_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \	5732	_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5677	_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))	5733	_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5678	#define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \	5734	#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
5679	_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \	5735	_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5680	_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))	5736	_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5681	#define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \	5737	#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
5682	_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \	5738	_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5683	_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)	5739	_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
5684		5740
5685	/* legacy palette */	5741	/* legacy palette */
5686	#define _LGC_PALETTE_A 0x4a000	5742	#define _LGC_PALETTE_A 0x4a000
5687	#define _LGC_PALETTE_B 0x4a800	5743	#define _LGC_PALETTE_B 0x4a800
5688	#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)	5744	#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5689		5745
5690	#define _GAMMA_MODE_A 0x4a480	5746	#define _GAMMA_MODE_A 0x4a480
5691	#define _GAMMA_MODE_B 0x4ac80	5747	#define _GAMMA_MODE_B 0x4ac80
5692	#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)	5748	#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5693	#define GAMMA_MODE_MODE_MASK (3 << 0)	5749	#define GAMMA_MODE_MODE_MASK (3 << 0)
5694	#define GAMMA_MODE_MODE_8BIT (0 << 0)	5750	#define GAMMA_MODE_MODE_8BIT (0 << 0)
5695	#define GAMMA_MODE_MODE_10BIT (1 << 0)	5751	#define GAMMA_MODE_MODE_10BIT (1 << 0)
5696	#define GAMMA_MODE_MODE_12BIT (2 << 0)	5752	#define GAMMA_MODE_MODE_12BIT (2 << 0)
5697	#define GAMMA_MODE_MODE_SPLIT (3 << 0)	5753	#define GAMMA_MODE_MODE_SPLIT (3 << 0)
5698		5754
		5755	/* DMC/CSR */
		5756	#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
		5757	#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
		5758	#define CSR_HTP_ADDR_SKL 0x00500034
		5759	#define CSR_SSP_BASE _MMIO(0x8F074)
		5760	#define CSR_HTP_SKL _MMIO(0x8F004)
		5761	#define CSR_LAST_WRITE _MMIO(0x8F034)
		5762	#define CSR_LAST_WRITE_VALUE 0xc003b400
		5763	/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
		5764	#define CSR_MMIO_START_RANGE 0x80000
		5765	#define CSR_MMIO_END_RANGE 0x8FFFF
		5766	#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
		5767	#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
		5768	#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
		5769
5699	/* interrupts */	5770	/* interrupts */
5700	#define DE_MASTER_IRQ_CONTROL (1 << 31)	5771	#define DE_MASTER_IRQ_CONTROL (1 << 31)
5701	#define DE_SPRITEB_FLIP_DONE (1 << 29)	5772	#define DE_SPRITEB_FLIP_DONE (1 << 29)
@@ -5747,20 +5818,20 @@ enum skl_disp_power_wells { · 45 unmodified lines
5747	#define DE_PIPEA_VBLANK_IVB (1<<0)	5818	#define DE_PIPEA_VBLANK_IVB (1<<0)
5748	#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))	5819	#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
5749		5820
5750	#define VLV_MASTER_IER 0x4400c /* Gunit master IER */	5821	#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
5751	#define MASTER_INTERRUPT_ENABLE (1<<31)	5822	#define MASTER_INTERRUPT_ENABLE (1<<31)
5752		5823
5753	#define DEISR 0x44000	5824	#define DEISR _MMIO(0x44000)
5754	#define DEIMR 0x44004	5825	#define DEIMR _MMIO(0x44004)
5755	#define DEIIR 0x44008	5826	#define DEIIR _MMIO(0x44008)
5756	#define DEIER 0x4400c	5827	#define DEIER _MMIO(0x4400c)
5757		5828
5758	#define GTISR 0x44010	5829	#define GTISR _MMIO(0x44010)
5759	#define GTIMR 0x44014	5830	#define GTIMR _MMIO(0x44014)
5760	#define GTIIR 0x44018	5831	#define GTIIR _MMIO(0x44018)
5761	#define GTIER 0x4401c	5832	#define GTIER _MMIO(0x4401c)
5762		5833
5763	#define GEN8_MASTER_IRQ 0x44200	5834	#define GEN8_MASTER_IRQ _MMIO(0x44200)
5764	#define GEN8_MASTER_IRQ_CONTROL (1<<31)	5835	#define GEN8_MASTER_IRQ_CONTROL (1<<31)
5765	#define GEN8_PCU_IRQ (1<<30)	5836	#define GEN8_PCU_IRQ (1<<30)
5766	#define GEN8_DE_PCH_IRQ (1<<23)	5837	#define GEN8_DE_PCH_IRQ (1<<23)
@@ -5777,10 +5848,10 @@ enum skl_disp_power_wells { · 10 unmodified lines
5777	#define GEN8_GT_BCS_IRQ (1<<1)	5848	#define GEN8_GT_BCS_IRQ (1<<1)
5778	#define GEN8_GT_RCS_IRQ (1<<0)	5849	#define GEN8_GT_RCS_IRQ (1<<0)
5779		5850
5780	#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))	5851	#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5781	#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))	5852	#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5782	#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))	5853	#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5783	#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))	5854	#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
5784		5855
5785	#define GEN8_RCS_IRQ_SHIFT 0	5856	#define GEN8_RCS_IRQ_SHIFT 0
5786	#define GEN8_BCS_IRQ_SHIFT 16	5857	#define GEN8_BCS_IRQ_SHIFT 16
@@ -5789,10 +5860,10 @@ enum skl_disp_power_wells { · 2 unmodified lines
5789	#define GEN8_VECS_IRQ_SHIFT 0	5860	#define GEN8_VECS_IRQ_SHIFT 0
5790	#define GEN8_WD_IRQ_SHIFT 16	5861	#define GEN8_WD_IRQ_SHIFT 16
5791		5862
5792	#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))	5863	#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5793	#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))	5864	#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5794	#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))	5865	#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5795	#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))	5866	#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
5796	#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)	5867	#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5797	#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)	5868	#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5798	#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)	5869	#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
@@ -5825,10 +5896,10 @@ enum skl_disp_power_wells { · 26 unmodified lines
5825	GEN9_PIPE_PLANE2_FAULT \| \	5896	GEN9_PIPE_PLANE2_FAULT \| \
5826	GEN9_PIPE_PLANE1_FAULT)	5897	GEN9_PIPE_PLANE1_FAULT)
5827		5898
5828	#define GEN8_DE_PORT_ISR 0x44440	5899	#define GEN8_DE_PORT_ISR _MMIO(0x44440)
5829	#define GEN8_DE_PORT_IMR 0x44444	5900	#define GEN8_DE_PORT_IMR _MMIO(0x44444)
5830	#define GEN8_DE_PORT_IIR 0x44448	5901	#define GEN8_DE_PORT_IIR _MMIO(0x44448)
5831	#define GEN8_DE_PORT_IER 0x4444c	5902	#define GEN8_DE_PORT_IER _MMIO(0x4444c)
5832	#define GEN9_AUX_CHANNEL_D (1 << 27)	5903	#define GEN9_AUX_CHANNEL_D (1 << 27)
5833	#define GEN9_AUX_CHANNEL_C (1 << 26)	5904	#define GEN9_AUX_CHANNEL_C (1 << 26)
5834	#define GEN9_AUX_CHANNEL_B (1 << 25)	5905	#define GEN9_AUX_CHANNEL_B (1 << 25)
@@ -5842,23 +5913,23 @@ enum skl_disp_power_wells { · 7 unmodified lines
5842	#define BXT_DE_PORT_GMBUS (1 << 1)	5913	#define BXT_DE_PORT_GMBUS (1 << 1)
5843	#define GEN8_AUX_CHANNEL_A (1 << 0)	5914	#define GEN8_AUX_CHANNEL_A (1 << 0)
5844		5915
5845	#define GEN8_DE_MISC_ISR 0x44460	5916	#define GEN8_DE_MISC_ISR _MMIO(0x44460)
5846	#define GEN8_DE_MISC_IMR 0x44464	5917	#define GEN8_DE_MISC_IMR _MMIO(0x44464)
5847	#define GEN8_DE_MISC_IIR 0x44468	5918	#define GEN8_DE_MISC_IIR _MMIO(0x44468)
5848	#define GEN8_DE_MISC_IER 0x4446c	5919	#define GEN8_DE_MISC_IER _MMIO(0x4446c)
5849	#define GEN8_DE_MISC_GSE (1 << 27)	5920	#define GEN8_DE_MISC_GSE (1 << 27)
5850		5921
5851	#define GEN8_PCU_ISR 0x444e0	5922	#define GEN8_PCU_ISR _MMIO(0x444e0)
5852	#define GEN8_PCU_IMR 0x444e4	5923	#define GEN8_PCU_IMR _MMIO(0x444e4)
5853	#define GEN8_PCU_IIR 0x444e8	5924	#define GEN8_PCU_IIR _MMIO(0x444e8)
5854	#define GEN8_PCU_IER 0x444ec	5925	#define GEN8_PCU_IER _MMIO(0x444ec)
5855		5926
5856	#define ILK_DISPLAY_CHICKEN2 0x42004	5927	#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
5857	/* Required on all Ironlake and Sandybridge according to the B-Spec. */	5928	/* Required on all Ironlake and Sandybridge according to the B-Spec. */
5858	#define ILK_ELPIN_409_SELECT (1 << 25)	5929	#define ILK_ELPIN_409_SELECT (1 << 25)
5859	#define ILK_DPARB_GATE (1<<22)	5930	#define ILK_DPARB_GATE (1<<22)
5860	#define ILK_VSDPFD_FULL (1<<21)	5931	#define ILK_VSDPFD_FULL (1<<21)
5861	#define FUSE_STRAP 0x42014	5932	#define FUSE_STRAP _MMIO(0x42014)
5862	#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)	5933	#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5863	#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)	5934	#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5864	#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)	5935	#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
@@ -5867,18 +5938,18 @@ enum skl_disp_power_wells { · 2 unmodified lines
5867	#define HSW_CDCLK_LIMIT (1 << 24)	5938	#define HSW_CDCLK_LIMIT (1 << 24)
5868	#define ILK_DESKTOP (1 << 23)	5939	#define ILK_DESKTOP (1 << 23)
5869		5940
5870	#define ILK_DSPCLK_GATE_D 0x42020	5941	#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
5871	#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)	5942	#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5872	#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)	5943	#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5873	#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)	5944	#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5874	#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)	5945	#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5875	#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)	5946	#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5876		5947
5877	#define IVB_CHICKEN3 0x4200c	5948	#define IVB_CHICKEN3 _MMIO(0x4200c)
5878	# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)	5949	# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5879	# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)	5950	# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5880		5951
5881	#define CHICKEN_PAR1_1 0x42080	5952	#define CHICKEN_PAR1_1 _MMIO(0x42080)
5882	#define DPA_MASK_VBLANK_SRD (1 << 15)	5953	#define DPA_MASK_VBLANK_SRD (1 << 15)
5883	#define FORCE_ARB_IDLE_PLANES (1 << 14)	5954	#define FORCE_ARB_IDLE_PLANES (1 << 14)
5884		5955
@@ -5886,70 +5957,70 @@ enum skl_disp_power_wells { · 1 unmodified line
5886	#define _CHICKEN_PIPESL_1_B 0x420b4	5957	#define _CHICKEN_PIPESL_1_B 0x420b4
5887	#define HSW_FBCQ_DIS (1 << 22)	5958	#define HSW_FBCQ_DIS (1 << 22)
5888	#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)	5959	#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5889	#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)	5960	#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5890		5961
5891	#define DISP_ARB_CTL 0x45000	5962	#define DISP_ARB_CTL _MMIO(0x45000)
5892	#define DISP_TILE_SURFACE_SWIZZLING (1<<13)	5963	#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
5893	#define DISP_FBC_WM_DIS (1<<15)	5964	#define DISP_FBC_WM_DIS (1<<15)
5894	#define DISP_ARB_CTL2 0x45004	5965	#define DISP_ARB_CTL2 _MMIO(0x45004)
5895	#define DISP_DATA_PARTITION_5_6 (1<<6)	5966	#define DISP_DATA_PARTITION_5_6 (1<<6)
5896	#define DBUF_CTL 0x45008	5967	#define DBUF_CTL _MMIO(0x45008)
5897	#define DBUF_POWER_REQUEST (1<<31)	5968	#define DBUF_POWER_REQUEST (1<<31)
5898	#define DBUF_POWER_STATE (1<<30)	5969	#define DBUF_POWER_STATE (1<<30)
5899	#define GEN7_MSG_CTL 0x45010	5970	#define GEN7_MSG_CTL _MMIO(0x45010)
5900	#define WAIT_FOR_PCH_RESET_ACK (1<<1)	5971	#define WAIT_FOR_PCH_RESET_ACK (1<<1)
5901	#define WAIT_FOR_PCH_FLR_ACK (1<<0)	5972	#define WAIT_FOR_PCH_FLR_ACK (1<<0)
5902	#define HSW_NDE_RSTWRN_OPT 0x46408	5973	#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
5903	#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)	5974	#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
5904		5975
5905	#define SKL_DFSM 0x51000	5976	#define SKL_DFSM _MMIO(0x51000)
5906	#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)	5977	#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
5907	#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)	5978	#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
5908	#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)	5979	#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
5909	#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)	5980	#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
5910	#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)	5981	#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
5911		5982
5912	#define FF_SLICE_CS_CHICKEN2 0x20e4	5983	#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
5913	#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)	5984	#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
5914		5985
5915	/* GEN7 chicken */	5986	/* GEN7 chicken */
5916	#define GEN7_COMMON_SLICE_CHICKEN1 0x7010	5987	#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
5917	# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) \| (1<<26))	5988	# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) \| (1<<26))
5918	# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)	5989	# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
5919	#define COMMON_SLICE_CHICKEN2 0x7014	5990	#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
5920	# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)	5991	# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
5921		5992
5922	#define HIZ_CHICKEN 0x7018	5993	#define HIZ_CHICKEN _MMIO(0x7018)
5923	# define CHV_HZ_8X8_MODE_IN_1X (1<<15)	5994	# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
5924	# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)	5995	# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
5925		5996
5926	#define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308	5997	#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
5927	#define DISABLE_PIXEL_MASK_CAMMING (1<<14)	5998	#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
5928		5999
5929	#define GEN7_L3SQCREG1 0xB010	6000	#define GEN7_L3SQCREG1 _MMIO(0xB010)
5930	#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000	6001	#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5931		6002
5932	#define GEN8_L3SQCREG1 0xB100	6003	#define GEN8_L3SQCREG1 _MMIO(0xB100)
5933	#define BDW_WA_L3SQCREG1_DEFAULT 0x784000	6004	#define BDW_WA_L3SQCREG1_DEFAULT 0x784000
5934		6005
5935	#define GEN7_L3CNTLREG1 0xB01C	6006	#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
5936	#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C	6007	#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
5937	#define GEN7_L3AGDIS (1<<19)	6008	#define GEN7_L3AGDIS (1<<19)
5938	#define GEN7_L3CNTLREG2 0xB020	6009	#define GEN7_L3CNTLREG2 _MMIO(0xB020)
5939	#define GEN7_L3CNTLREG3 0xB024	6010	#define GEN7_L3CNTLREG3 _MMIO(0xB024)
5940		6011
5941	#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030	6012	#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
5942	#define GEN7_WA_L3_CHICKEN_MODE 0x20000000	6013	#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5943		6014
5944	#define GEN7_L3SQCREG4 0xb034	6015	#define GEN7_L3SQCREG4 _MMIO(0xb034)
5945	#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)	6016	#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5946		6017
5947	#define GEN8_L3SQCREG4 0xb118	6018	#define GEN8_L3SQCREG4 _MMIO(0xb118)
5948	#define GEN8_LQSC_RO_PERF_DIS (1<<27)	6019	#define GEN8_LQSC_RO_PERF_DIS (1<<27)
5949	#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)	6020	#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
5950		6021
5951	/* GEN8 chicken */	6022	/* GEN8 chicken */
5952	#define HDC_CHICKEN0 0x7300	6023	#define HDC_CHICKEN0 _MMIO(0x7300)
5953	#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)	6024	#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
5954	#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)	6025	#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
5955	#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)	6026	#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
@@ -5958,17 +6029,17 @@ enum skl_disp_power_wells { · 2 unmodified lines
5958	#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)	6029	#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
5959		6030
5960	/* GEN9 chicken */	6031	/* GEN9 chicken */
5961	#define SLICE_ECO_CHICKEN0 0x7308	6032	#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
5962	#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)	6033	#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
5963		6034
5964	/* WaCatErrorRejectionIssue */	6035	/* WaCatErrorRejectionIssue */
5965	#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030	6036	#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
5966	#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)	6037	#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5967		6038
5968	#define HSW_SCRATCH1 0xb038	6039	#define HSW_SCRATCH1 _MMIO(0xb038)
5969	#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)	6040	#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5970		6041
5971	#define BDW_SCRATCH1 0xb11c	6042	#define BDW_SCRATCH1 _MMIO(0xb11c)
5972	#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)	6043	#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
5973		6044
5974	/* PCH */	6045	/* PCH */
@@ -6062,12 +6133,12 @@ enum skl_disp_power_wells { · 87 unmodified lines
6062	SDE_FDI_RXB_CPT \| \	6133	SDE_FDI_RXB_CPT \| \
6063	SDE_FDI_RXA_CPT)	6134	SDE_FDI_RXA_CPT)
6064		6135
6065	#define SDEISR 0xc4000	6136	#define SDEISR _MMIO(0xc4000)
6066	#define SDEIMR 0xc4004	6137	#define SDEIMR _MMIO(0xc4004)
6067	#define SDEIIR 0xc4008	6138	#define SDEIIR _MMIO(0xc4008)
6068	#define SDEIER 0xc400c	6139	#define SDEIER _MMIO(0xc400c)
6069		6140
6070	#define SERR_INT 0xc4040	6141	#define SERR_INT _MMIO(0xc4040)
6071	#define SERR_INT_POISON (1<<31)	6142	#define SERR_INT_POISON (1<<31)
6072	#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)	6143	#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
6073	#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)	6144	#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
@@ -6075,7 +6146,7 @@ enum skl_disp_power_wells { · 1 unmodified line
6075	#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))	6146	#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
6076		6147
6077	/* digital port hotplug */	6148	/* digital port hotplug */
6078	#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */	6149	#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
6079	#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */	6150	#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
6080	#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */	6151	#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
6081	#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */	6152	#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
@@ -6112,42 +6183,42 @@ enum skl_disp_power_wells { · 30 unmodified lines
6112	#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)	6183	#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6113	#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)	6184	#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
6114		6185
6115	#define PCH_PORT_HOTPLUG2 0xc403C /* SHOTPLUG_CTL2 SPT+ */	6186	#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
6116	#define PORTE_HOTPLUG_ENABLE (1 << 4)	6187	#define PORTE_HOTPLUG_ENABLE (1 << 4)
6117	#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)	6188	#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
6118	#define PORTE_HOTPLUG_NO_DETECT (0 << 0)	6189	#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
6119	#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)	6190	#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
6120	#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)	6191	#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
6121		6192
6122	#define PCH_GPIOA 0xc5010	6193	#define PCH_GPIOA _MMIO(0xc5010)
6123	#define PCH_GPIOB 0xc5014	6194	#define PCH_GPIOB _MMIO(0xc5014)
6124	#define PCH_GPIOC 0xc5018	6195	#define PCH_GPIOC _MMIO(0xc5018)
6125	#define PCH_GPIOD 0xc501c	6196	#define PCH_GPIOD _MMIO(0xc501c)
6126	#define PCH_GPIOE 0xc5020	6197	#define PCH_GPIOE _MMIO(0xc5020)
6127	#define PCH_GPIOF 0xc5024	6198	#define PCH_GPIOF _MMIO(0xc5024)
6128		6199
6129	#define PCH_GMBUS0 0xc5100	6200	#define PCH_GMBUS0 _MMIO(0xc5100)
6130	#define PCH_GMBUS1 0xc5104	6201	#define PCH_GMBUS1 _MMIO(0xc5104)
6131	#define PCH_GMBUS2 0xc5108	6202	#define PCH_GMBUS2 _MMIO(0xc5108)
6132	#define PCH_GMBUS3 0xc510c	6203	#define PCH_GMBUS3 _MMIO(0xc510c)
6133	#define PCH_GMBUS4 0xc5110	6204	#define PCH_GMBUS4 _MMIO(0xc5110)
6134	#define PCH_GMBUS5 0xc5120	6205	#define PCH_GMBUS5 _MMIO(0xc5120)
6135		6206
6136	#define _PCH_DPLL_A 0xc6014	6207	#define _PCH_DPLL_A 0xc6014
6137	#define _PCH_DPLL_B 0xc6018	6208	#define _PCH_DPLL_B 0xc6018
6138	#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)	6209	#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6139		6210
6140	#define _PCH_FPA0 0xc6040	6211	#define _PCH_FPA0 0xc6040
6141	#define FP_CB_TUNE (0x3<<22)	6212	#define FP_CB_TUNE (0x3<<22)
6142	#define _PCH_FPA1 0xc6044	6213	#define _PCH_FPA1 0xc6044
6143	#define _PCH_FPB0 0xc6048	6214	#define _PCH_FPB0 0xc6048
6144	#define _PCH_FPB1 0xc604c	6215	#define _PCH_FPB1 0xc604c
6145	#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)	6216	#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6146	#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)	6217	#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
6147		6218
6148	#define PCH_DPLL_TEST 0xc606c	6219	#define PCH_DPLL_TEST _MMIO(0xc606c)
6149		6220
6150	#define PCH_DREF_CONTROL 0xC6200	6221	#define PCH_DREF_CONTROL _MMIO(0xC6200)
6151	#define DREF_CONTROL_MASK 0x7fc3	6222	#define DREF_CONTROL_MASK 0x7fc3
6152	#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)	6223	#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6153	#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)	6224	#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
@@ -6170,19 +6241,19 @@ enum skl_disp_power_wells { · 16 unmodified lines
6170	#define DREF_SSC4_DISABLE (0)	6241	#define DREF_SSC4_DISABLE (0)
6171	#define DREF_SSC4_ENABLE (1)	6242	#define DREF_SSC4_ENABLE (1)
6172		6243
6173	#define PCH_RAWCLK_FREQ 0xc6204	6244	#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
6174	#define FDL_TP1_TIMER_SHIFT 12	6245	#define FDL_TP1_TIMER_SHIFT 12
6175	#define FDL_TP1_TIMER_MASK (3<<12)	6246	#define FDL_TP1_TIMER_MASK (3<<12)
6176	#define FDL_TP2_TIMER_SHIFT 10	6247	#define FDL_TP2_TIMER_SHIFT 10
6177	#define FDL_TP2_TIMER_MASK (3<<10)	6248	#define FDL_TP2_TIMER_MASK (3<<10)
6178	#define RAWCLK_FREQ_MASK 0x3ff	6249	#define RAWCLK_FREQ_MASK 0x3ff
6179		6250
6180	#define PCH_DPLL_TMR_CFG 0xc6208	6251	#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
6181		6252
6182	#define PCH_SSC4_PARMS 0xc6210	6253	#define PCH_SSC4_PARMS _MMIO(0xc6210)
6183	#define PCH_SSC4_AUX_PARMS 0xc6214	6254	#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
6184		6255
6185	#define PCH_DPLL_SEL 0xc7000	6256	#define PCH_DPLL_SEL _MMIO(0xc7000)
6186	#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))	6257	#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
6187	#define TRANS_DPLLA_SEL(pipe) 0	6258	#define TRANS_DPLLA_SEL(pipe) 0
6188	#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))	6259	#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
@@ -6230,79 +6301,73 @@ enum skl_disp_power_wells { · 41 unmodified lines
6230	#define _VIDEO_DIP_DATA_B 0xe1208	6301	#define _VIDEO_DIP_DATA_B 0xe1208
6231	#define _VIDEO_DIP_GCP_B 0xe1210	6302	#define _VIDEO_DIP_GCP_B 0xe1210
6232		6303
6233	#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)	6304	#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6234	#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)	6305	#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6235	#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)	6306	#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6236		6307
6237	/* Per-transcoder DIP controls (VLV) */	6308	/* Per-transcoder DIP controls (VLV) */
6238	#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)	6309	#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6239	#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)	6310	#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6240	#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)	6311	#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6241		6312
6242	#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)	6313	#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6243	#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)	6314	#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6244	#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)	6315	#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6245		6316
6246	#define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)	6317	#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6247	#define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)	6318	#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6248	#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)	6319	#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6249		6320
6250	#define VLV_TVIDEO_DIP_CTL(pipe) \	6321	#define VLV_TVIDEO_DIP_CTL(pipe) \
6251	_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \	6322	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
6252	VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)	6323	_VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
6253	#define VLV_TVIDEO_DIP_DATA(pipe) \	6324	#define VLV_TVIDEO_DIP_DATA(pipe) \
6254	_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \	6325	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
6255	VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)	6326	_VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
6256	#define VLV_TVIDEO_DIP_GCP(pipe) \	6327	#define VLV_TVIDEO_DIP_GCP(pipe) \
6257	_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \	6328	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6258	VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)	6329	_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6259		6330
6260	/* Haswell DIP controls */	6331	/* Haswell DIP controls */
6261	#define HSW_VIDEO_DIP_CTL_A 0x60200	6332
6262	#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220	6333	#define _HSW_VIDEO_DIP_CTL_A 0x60200
6263	#define HSW_VIDEO_DIP_VS_DATA_A 0x60260	6334	#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6264	#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0	6335	#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
6265	#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0	6336	#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6266	#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320	6337	#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6267	#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240	6338	#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6268	#define HSW_VIDEO_DIP_VS_ECC_A 0x60280	6339	#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6269	#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0	6340	#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
6270	#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300	6341	#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6271	#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344	6342	#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6272	#define HSW_VIDEO_DIP_GCP_A 0x60210	6343	#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6273		6344	#define _HSW_VIDEO_DIP_GCP_A 0x60210
6274	#define HSW_VIDEO_DIP_CTL_B 0x61200	6345
6275	#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220	6346	#define _HSW_VIDEO_DIP_CTL_B 0x61200
6276	#define HSW_VIDEO_DIP_VS_DATA_B 0x61260	6347	#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6277	#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0	6348	#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
6278	#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0	6349	#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6279	#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320	6350	#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6280	#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240	6351	#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6281	#define HSW_VIDEO_DIP_VS_ECC_B 0x61280	6352	#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6282	#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0	6353	#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
6283	#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300	6354	#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6284	#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344	6355	#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6285	#define HSW_VIDEO_DIP_GCP_B 0x61210	6356	#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6286		6357	#define _HSW_VIDEO_DIP_GCP_B 0x61210
6287	#define HSW_TVIDEO_DIP_CTL(trans) \	6358
6288	_TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)	6359	#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6289	#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \	6360	#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6290	(_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)	6361	#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6291	#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \	6362	#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6292	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)	6363	#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6293	#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \	6364	#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
6294	(_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)	6365
6295	#define HSW_TVIDEO_DIP_GCP(trans) \	6366	#define _HSW_STEREO_3D_CTL_A 0x70020
6296	_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)	6367	#define S3D_ENABLE (1<<31)
6297	#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \	6368	#define _HSW_STEREO_3D_CTL_B 0x71020
6298	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)	6369
6299		6370	#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
6300	#define HSW_STEREO_3D_CTL_A 0x70020
6301	#define S3D_ENABLE (1<<31)
6302	#define HSW_STEREO_3D_CTL_B 0x71020
6303
6304	#define HSW_STEREO_3D_CTL(trans) \
6305	_PIPE2(trans, HSW_STEREO_3D_CTL_A)
6306		6371
6307	#define _PCH_TRANS_HTOTAL_B 0xe1000	6372	#define _PCH_TRANS_HTOTAL_B 0xe1000
6308	#define _PCH_TRANS_HBLANK_B 0xe1004	6373	#define _PCH_TRANS_HBLANK_B 0xe1004
@@ -6310,16 +6375,15 @@ enum skl_disp_power_wells { · 1 unmodified line
6310	#define _PCH_TRANS_VTOTAL_B 0xe100c	6375	#define _PCH_TRANS_VTOTAL_B 0xe100c
6311	#define _PCH_TRANS_VBLANK_B 0xe1010	6376	#define _PCH_TRANS_VBLANK_B 0xe1010
6312	#define _PCH_TRANS_VSYNC_B 0xe1014	6377	#define _PCH_TRANS_VSYNC_B 0xe1014
6313	#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028	6378	#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6314		6379
6315	#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)	6380	#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6316	#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)	6381	#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6317	#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)	6382	#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6318	#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)	6383	#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6319	#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)	6384	#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6320	#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)	6385	#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6321	#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \	6386	#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
6322	_PCH_TRANS_VSYNCSHIFT_B)
6323		6387
6324	#define _PCH_TRANSB_DATA_M1 0xe1030	6388	#define _PCH_TRANSB_DATA_M1 0xe1030
6325	#define _PCH_TRANSB_DATA_N1 0xe1034	6389	#define _PCH_TRANSB_DATA_N1 0xe1034
@@ -6330,19 +6394,19 @@ enum skl_disp_power_wells { · 4 unmodified lines
6330	#define _PCH_TRANSB_LINK_M2 0xe1048	6394	#define _PCH_TRANSB_LINK_M2 0xe1048
6331	#define _PCH_TRANSB_LINK_N2 0xe104c	6395	#define _PCH_TRANSB_LINK_N2 0xe104c
6332		6396
6333	#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)	6397	#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6334	#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)	6398	#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6335	#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)	6399	#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6336	#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)	6400	#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6337	#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)	6401	#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6338	#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)	6402	#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6339	#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)	6403	#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6340	#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)	6404	#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6341		6405
6342	#define _PCH_TRANSACONF 0xf0008	6406	#define _PCH_TRANSACONF 0xf0008
6343	#define _PCH_TRANSBCONF 0xf1008	6407	#define _PCH_TRANSBCONF 0xf1008
6344	#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)	6408	#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6345	#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */	6409	#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
6346	#define TRANS_DISABLE (0<<31)	6410	#define TRANS_DISABLE (0<<31)
6347	#define TRANS_ENABLE (1<<31)	6411	#define TRANS_ENABLE (1<<31)
6348	#define TRANS_STATE_MASK (1<<30)	6412	#define TRANS_STATE_MASK (1<<30)
@@ -6363,47 +6427,47 @@ enum skl_disp_power_wells { · 14 unmodified lines
6363		6427
6364	#define _TRANSA_CHICKEN1 0xf0060	6428	#define _TRANSA_CHICKEN1 0xf0060
6365	#define _TRANSB_CHICKEN1 0xf1060	6429	#define _TRANSB_CHICKEN1 0xf1060
6366	#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)	6430	#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6367	#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)	6431	#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
6368	#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)	6432	#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
6369	#define _TRANSA_CHICKEN2 0xf0064	6433	#define _TRANSA_CHICKEN2 0xf0064
6370	#define _TRANSB_CHICKEN2 0xf1064	6434	#define _TRANSB_CHICKEN2 0xf1064
6371	#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)	6435	#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6372	#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)	6436	#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6373	#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)	6437	#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6374	#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)	6438	#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6375	#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)	6439	#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6376	#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)	6440	#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
6377		6441
6378	#define SOUTH_CHICKEN1 0xc2000	6442	#define SOUTH_CHICKEN1 _MMIO(0xc2000)
6379	#define FDIA_PHASE_SYNC_SHIFT_OVR 19	6443	#define FDIA_PHASE_SYNC_SHIFT_OVR 19
6380	#define FDIA_PHASE_SYNC_SHIFT_EN 18	6444	#define FDIA_PHASE_SYNC_SHIFT_EN 18
6381	#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))	6445	#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6382	#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))	6446	#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6383	#define FDI_BC_BIFURCATION_SELECT (1 << 12)	6447	#define FDI_BC_BIFURCATION_SELECT (1 << 12)
6384	#define SPT_PWM_GRANULARITY (1<<0)	6448	#define SPT_PWM_GRANULARITY (1<<0)
6385	#define SOUTH_CHICKEN2 0xc2004	6449	#define SOUTH_CHICKEN2 _MMIO(0xc2004)
6386	#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)	6450	#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6387	#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)	6451	#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
6388	#define LPT_PWM_GRANULARITY (1<<5)	6452	#define LPT_PWM_GRANULARITY (1<<5)
6389	#define DPLS_EDP_PPS_FIX_DIS (1<<0)	6453	#define DPLS_EDP_PPS_FIX_DIS (1<<0)
6390		6454
6391	#define _FDI_RXA_CHICKEN 0xc200c	6455	#define _FDI_RXA_CHICKEN 0xc200c
6392	#define _FDI_RXB_CHICKEN 0xc2010	6456	#define _FDI_RXB_CHICKEN 0xc2010
6393	#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)	6457	#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6394	#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)	6458	#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
6395	#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)	6459	#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6396		6460
6397	#define SOUTH_DSPCLK_GATE_D 0xc2020	6461	#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
6398	#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)	6462	#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
6399	#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)	6463	#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
6400	#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)	6464	#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
6401	#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)	6465	#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
6402		6466
6403	/* CPU: FDI_TX */	6467	/* CPU: FDI_TX */
6404	#define _FDI_TXA_CTL 0x60100	6468	#define _FDI_TXA_CTL 0x60100
6405	#define _FDI_TXB_CTL 0x61100	6469	#define _FDI_TXB_CTL 0x61100
6406	#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)	6470	#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6407	#define FDI_TX_DISABLE (0<<31)	6471	#define FDI_TX_DISABLE (0<<31)
6408	#define FDI_TX_ENABLE (1<<31)	6472	#define FDI_TX_ENABLE (1<<31)
6409	#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)	6473	#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
@@ -6453,7 +6517,7 @@ enum skl_disp_power_wells { · 43 unmodified lines
6453	/* FDI_RX, FDI_X is hard-wired to Transcoder_X */	6517	/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6454	#define _FDI_RXA_CTL 0xf000c	6518	#define _FDI_RXA_CTL 0xf000c
6455	#define _FDI_RXB_CTL 0xf100c	6519	#define _FDI_RXB_CTL 0xf100c
6456	#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)	6520	#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6457	#define FDI_RX_ENABLE (1<<31)	6521	#define FDI_RX_ENABLE (1<<31)
6458	/* train, dp width same as FDI_TX */	6522	/* train, dp width same as FDI_TX */
6459	#define FDI_FS_ERRC_ENABLE (1<<27)	6523	#define FDI_FS_ERRC_ENABLE (1<<27)
@@ -6489,14 +6553,14 @@ enum skl_disp_power_wells { · 29 unmodified lines
6489	#define FDI_RX_TP1_TO_TP2_48 (2<<20)	6553	#define FDI_RX_TP1_TO_TP2_48 (2<<20)
6490	#define FDI_RX_TP1_TO_TP2_64 (3<<20)	6554	#define FDI_RX_TP1_TO_TP2_64 (3<<20)
6491	#define FDI_RX_FDI_DELAY_90 (0x90<<0)	6555	#define FDI_RX_FDI_DELAY_90 (0x90<<0)
6492	#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)	6556	#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6493		6557
6494	#define _FDI_RXA_TUSIZE1 0xf0030	6558	#define _FDI_RXA_TUSIZE1 0xf0030
6495	#define _FDI_RXA_TUSIZE2 0xf0038	6559	#define _FDI_RXA_TUSIZE2 0xf0038
6496	#define _FDI_RXB_TUSIZE1 0xf1030	6560	#define _FDI_RXB_TUSIZE1 0xf1030
6497	#define _FDI_RXB_TUSIZE2 0xf1038	6561	#define _FDI_RXB_TUSIZE2 0xf1038
6498	#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)	6562	#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6499	#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)	6563	#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6500		6564
6501	/* FDI_RX interrupt register format */	6565	/* FDI_RX interrupt register format */
6502	#define FDI_RX_INTER_LANE_ALIGN (1<<10)	6566	#define FDI_RX_INTER_LANE_ALIGN (1<<10)
@@ -6511,44 +6575,41 @@ enum skl_disp_power_wells { · 8 unmodified lines
6511	#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)	6575	#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6512	#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)	6576	#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6513		6577
6514	#define _FDI_RXA_IIR 0xf0014	6578	#define _FDI_RXA_IIR 0xf0014
6515	#define _FDI_RXA_IMR 0xf0018	6579	#define _FDI_RXA_IMR 0xf0018
6516	#define _FDI_RXB_IIR 0xf1014	6580	#define _FDI_RXB_IIR 0xf1014
6517	#define _FDI_RXB_IMR 0xf1018	6581	#define _FDI_RXB_IMR 0xf1018
6518	#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)	6582	#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6519	#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)	6583	#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6520		6584
6521	#define FDI_PLL_CTL_1 0xfe000	6585	#define FDI_PLL_CTL_1 _MMIO(0xfe000)
6522	#define FDI_PLL_CTL_2 0xfe004	6586	#define FDI_PLL_CTL_2 _MMIO(0xfe004)
6523		6587
6524	#define PCH_LVDS 0xe1180	6588	#define PCH_LVDS _MMIO(0xe1180)
6525	#define LVDS_DETECTED (1 << 1)	6589	#define LVDS_DETECTED (1 << 1)
6526		6590
6527	/* vlv has 2 sets of panel control regs. */	6591	/* vlv has 2 sets of panel control regs. */
6528	#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)	6592	#define _PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6529	#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)	6593	#define _PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6530	#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)	6594	#define _PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
6531	#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)	6595	#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
6532	#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)	6596	#define _PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6533	#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)	6597	#define _PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
6534		6598
6535	#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)	6599	#define _PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6536	#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)	6600	#define _PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6537	#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)	6601	#define _PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6538	#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)	6602	#define _PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6539	#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)	6603	#define _PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
6540		6604
6541	#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)	6605	#define VLV_PIPE_PP_STATUS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
6542	#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)	6606	#define VLV_PIPE_PP_CONTROL(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
6543	#define VLV_PIPE_PP_ON_DELAYS(pipe) \	6607	#define VLV_PIPE_PP_ON_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
6544	_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)	6608	#define VLV_PIPE_PP_OFF_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
6545	#define VLV_PIPE_PP_OFF_DELAYS(pipe) \	6609	#define VLV_PIPE_PP_DIVISOR(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
6546	_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)	6610
6547	#define VLV_PIPE_PP_DIVISOR(pipe) \	6611	#define _PCH_PP_STATUS 0xc7200
6548	_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)	6612	#define _PCH_PP_CONTROL 0xc7204
6549
6550	#define PCH_PP_STATUS 0xc7200
6551	#define PCH_PP_CONTROL 0xc7204
6552	#define PANEL_UNLOCK_REGS (0xabcd << 16)	6613	#define PANEL_UNLOCK_REGS (0xabcd << 16)
6553	#define PANEL_UNLOCK_MASK (0xffff << 16)	6614	#define PANEL_UNLOCK_MASK (0xffff << 16)
6554	#define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)	6615	#define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
@@ -6558,7 +6619,7 @@ enum skl_disp_power_wells { · 3 unmodified lines
6558	#define PANEL_POWER_RESET (1 << 1)	6619	#define PANEL_POWER_RESET (1 << 1)
6559	#define PANEL_POWER_OFF (0 << 0)	6620	#define PANEL_POWER_OFF (0 << 0)
6560	#define PANEL_POWER_ON (1 << 0)	6621	#define PANEL_POWER_ON (1 << 0)
6561	#define PCH_PP_ON_DELAYS 0xc7208	6622	#define _PCH_PP_ON_DELAYS 0xc7208
6562	#define PANEL_PORT_SELECT_MASK (3 << 30)	6623	#define PANEL_PORT_SELECT_MASK (3 << 30)
6563	#define PANEL_PORT_SELECT_LVDS (0 << 30)	6624	#define PANEL_PORT_SELECT_LVDS (0 << 30)
6564	#define PANEL_PORT_SELECT_DPA (1 << 30)	6625	#define PANEL_PORT_SELECT_DPA (1 << 30)
@@ -6569,52 +6630,64 @@ enum skl_disp_power_wells { · 4 unmodified lines
6569	#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)	6630	#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
6570	#define PANEL_LIGHT_ON_DELAY_SHIFT 0	6631	#define PANEL_LIGHT_ON_DELAY_SHIFT 0
6571		6632
6572	#define PCH_PP_OFF_DELAYS 0xc720c	6633	#define _PCH_PP_OFF_DELAYS 0xc720c
6573	#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)	6634	#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
6574	#define PANEL_POWER_DOWN_DELAY_SHIFT 16	6635	#define PANEL_POWER_DOWN_DELAY_SHIFT 16
6575	#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)	6636	#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
6576	#define PANEL_LIGHT_OFF_DELAY_SHIFT 0	6637	#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
6577		6638
6578	#define PCH_PP_DIVISOR 0xc7210	6639	#define _PCH_PP_DIVISOR 0xc7210
6579	#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)	6640	#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
6580	#define PP_REFERENCE_DIVIDER_SHIFT 8	6641	#define PP_REFERENCE_DIVIDER_SHIFT 8
6581	#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)	6642	#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
6582	#define PANEL_POWER_CYCLE_DELAY_SHIFT 0	6643	#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
6583		6644
		6645	#define PCH_PP_STATUS _MMIO(_PCH_PP_STATUS)
		6646	#define PCH_PP_CONTROL _MMIO(_PCH_PP_CONTROL)
		6647	#define PCH_PP_ON_DELAYS _MMIO(_PCH_PP_ON_DELAYS)
		6648	#define PCH_PP_OFF_DELAYS _MMIO(_PCH_PP_OFF_DELAYS)
		6649	#define PCH_PP_DIVISOR _MMIO(_PCH_PP_DIVISOR)
		6650
6584	/* BXT PPS changes - 2nd set of PPS registers */	6651	/* BXT PPS changes - 2nd set of PPS registers */
6585	#define _BXT_PP_STATUS2 0xc7300	6652	#define _BXT_PP_STATUS2 0xc7300
6586	#define _BXT_PP_CONTROL2 0xc7304	6653	#define _BXT_PP_CONTROL2 0xc7304
6587	#define _BXT_PP_ON_DELAYS2 0xc7308	6654	#define _BXT_PP_ON_DELAYS2 0xc7308
6588	#define _BXT_PP_OFF_DELAYS2 0xc730c	6655	#define _BXT_PP_OFF_DELAYS2 0xc730c
6589		6656
6590	#define BXT_PP_STATUS(n) _PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)	6657	#define BXT_PP_STATUS(n) _MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2)
6591	#define BXT_PP_CONTROL(n) _PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)	6658	#define BXT_PP_CONTROL(n) _MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2)
6592	#define BXT_PP_ON_DELAYS(n) _PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)	6659	#define BXT_PP_ON_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
6593	#define BXT_PP_OFF_DELAYS(n) _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)	6660	#define BXT_PP_OFF_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
6594		6661
6595	#define PCH_DP_B 0xe4100	6662	#define _PCH_DP_B 0xe4100
6596	#define PCH_DPB_AUX_CH_CTL 0xe4110	6663	#define PCH_DP_B _MMIO(_PCH_DP_B)
6597	#define PCH_DPB_AUX_CH_DATA1 0xe4114	6664	#define _PCH_DPB_AUX_CH_CTL 0xe4110
6598	#define PCH_DPB_AUX_CH_DATA2 0xe4118	6665	#define _PCH_DPB_AUX_CH_DATA1 0xe4114
6599	#define PCH_DPB_AUX_CH_DATA3 0xe411c	6666	#define _PCH_DPB_AUX_CH_DATA2 0xe4118
6600	#define PCH_DPB_AUX_CH_DATA4 0xe4120	6667	#define _PCH_DPB_AUX_CH_DATA3 0xe411c
6601	#define PCH_DPB_AUX_CH_DATA5 0xe4124	6668	#define _PCH_DPB_AUX_CH_DATA4 0xe4120
6602		6669	#define _PCH_DPB_AUX_CH_DATA5 0xe4124
6603	#define PCH_DP_C 0xe4200	6670
6604	#define PCH_DPC_AUX_CH_CTL 0xe4210	6671	#define _PCH_DP_C 0xe4200
6605	#define PCH_DPC_AUX_CH_DATA1 0xe4214	6672	#define PCH_DP_C _MMIO(_PCH_DP_C)
6606	#define PCH_DPC_AUX_CH_DATA2 0xe4218	6673	#define _PCH_DPC_AUX_CH_CTL 0xe4210
6607	#define PCH_DPC_AUX_CH_DATA3 0xe421c	6674	#define _PCH_DPC_AUX_CH_DATA1 0xe4214
6608	#define PCH_DPC_AUX_CH_DATA4 0xe4220	6675	#define _PCH_DPC_AUX_CH_DATA2 0xe4218
6609	#define PCH_DPC_AUX_CH_DATA5 0xe4224	6676	#define _PCH_DPC_AUX_CH_DATA3 0xe421c
6610		6677	#define _PCH_DPC_AUX_CH_DATA4 0xe4220
6611	#define PCH_DP_D 0xe4300	6678	#define _PCH_DPC_AUX_CH_DATA5 0xe4224
6612	#define PCH_DPD_AUX_CH_CTL 0xe4310	6679
6613	#define PCH_DPD_AUX_CH_DATA1 0xe4314	6680	#define _PCH_DP_D 0xe4300
6614	#define PCH_DPD_AUX_CH_DATA2 0xe4318	6681	#define PCH_DP_D _MMIO(_PCH_DP_D)
6615	#define PCH_DPD_AUX_CH_DATA3 0xe431c	6682	#define _PCH_DPD_AUX_CH_CTL 0xe4310
6616	#define PCH_DPD_AUX_CH_DATA4 0xe4320	6683	#define _PCH_DPD_AUX_CH_DATA1 0xe4314
6617	#define PCH_DPD_AUX_CH_DATA5 0xe4324	6684	#define _PCH_DPD_AUX_CH_DATA2 0xe4318
		6685	#define _PCH_DPD_AUX_CH_DATA3 0xe431c
		6686	#define _PCH_DPD_AUX_CH_DATA4 0xe4320
		6687	#define _PCH_DPD_AUX_CH_DATA5 0xe4324
		6688
		6689	#define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
		6690	#define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
6618		6691
6619	/* CPT */	6692	/* CPT */
6620	#define PORT_TRANS_A_SEL_CPT 0	6693	#define PORT_TRANS_A_SEL_CPT 0
@@ -6627,10 +6700,10 @@ enum skl_disp_power_wells { · 6 unmodified lines
6627	#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)	6700	#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6628	#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)	6701	#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
6629		6702
6630	#define TRANS_DP_CTL_A 0xe0300	6703	#define _TRANS_DP_CTL_A 0xe0300
6631	#define TRANS_DP_CTL_B 0xe1300	6704	#define _TRANS_DP_CTL_B 0xe1300
6632	#define TRANS_DP_CTL_C 0xe2300	6705	#define _TRANS_DP_CTL_C 0xe2300
6633	#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)	6706	#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
6634	#define TRANS_DP_OUTPUT_ENABLE (1<<31)	6707	#define TRANS_DP_OUTPUT_ENABLE (1<<31)
6635	#define TRANS_DP_PORT_SEL_B (0<<29)	6708	#define TRANS_DP_PORT_SEL_B (0<<29)
6636	#define TRANS_DP_PORT_SEL_C (1<<29)	6709	#define TRANS_DP_PORT_SEL_C (1<<29)
@@ -6683,40 +6756,40 @@ enum skl_disp_power_wells { · 46 unmodified lines
6683		6756
6684	#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)	6757	#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6685		6758
6686	#define VLV_PMWGICZ 0x1300a4	6759	#define VLV_PMWGICZ _MMIO(0x1300a4)
6687		6760
6688	#define FORCEWAKE 0xA18C	6761	#define FORCEWAKE _MMIO(0xA18C)
6689	#define FORCEWAKE_VLV 0x1300b0	6762	#define FORCEWAKE_VLV _MMIO(0x1300b0)
6690	#define FORCEWAKE_ACK_VLV 0x1300b4	6763	#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
6691	#define FORCEWAKE_MEDIA_VLV 0x1300b8	6764	#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
6692	#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc	6765	#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
6693	#define FORCEWAKE_ACK_HSW 0x130044	6766	#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
6694	#define FORCEWAKE_ACK 0x130090	6767	#define FORCEWAKE_ACK _MMIO(0x130090)
6695	#define VLV_GTLC_WAKE_CTRL 0x130090	6768	#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
6696	#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)	6769	#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6697	#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)	6770	#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6698	#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)	6771	#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6699		6772
6700	#define VLV_GTLC_PW_STATUS 0x130094	6773	#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
6701	#define VLV_GTLC_ALLOWWAKEACK (1 << 0)	6774	#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6702	#define VLV_GTLC_ALLOWWAKEERR (1 << 1)	6775	#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6703	#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)	6776	#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6704	#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)	6777	#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
6705	#define FORCEWAKE_MT 0xa188 /* multi-threaded */	6778	#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
6706	#define FORCEWAKE_MEDIA_GEN9 0xa270	6779	#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
6707	#define FORCEWAKE_RENDER_GEN9 0xa278	6780	#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
6708	#define FORCEWAKE_BLITTER_GEN9 0xa188	6781	#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
6709	#define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88	6782	#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
6710	#define FORCEWAKE_ACK_RENDER_GEN9 0x0D84	6783	#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
6711	#define FORCEWAKE_ACK_BLITTER_GEN9 0x130044	6784	#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
6712	#define FORCEWAKE_KERNEL 0x1	6785	#define FORCEWAKE_KERNEL 0x1
6713	#define FORCEWAKE_USER 0x2	6786	#define FORCEWAKE_USER 0x2
6714	#define FORCEWAKE_MT_ACK 0x130040	6787	#define FORCEWAKE_MT_ACK _MMIO(0x130040)
6715	#define ECOBUS 0xa180	6788	#define ECOBUS _MMIO(0xa180)
6716	#define FORCEWAKE_MT_ENABLE (1<<5)	6789	#define FORCEWAKE_MT_ENABLE (1<<5)
6717	#define VLV_SPAREG2H 0xA194	6790	#define VLV_SPAREG2H _MMIO(0xA194)
6718		6791
6719	#define GTFIFODBG 0x120000	6792	#define GTFIFODBG _MMIO(0x120000)
6720	#define GT_FIFO_SBDROPERR (1<<6)	6793	#define GT_FIFO_SBDROPERR (1<<6)
6721	#define GT_FIFO_BLOBDROPERR (1<<5)	6794	#define GT_FIFO_BLOBDROPERR (1<<5)
6722	#define GT_FIFO_SB_READ_ABORTERR (1<<4)	6795	#define GT_FIFO_SB_READ_ABORTERR (1<<4)
@@ -6725,23 +6798,23 @@ enum skl_disp_power_wells { · 2 unmodified lines
6725	#define GT_FIFO_IAWRERR (1<<1)	6798	#define GT_FIFO_IAWRERR (1<<1)
6726	#define GT_FIFO_IARDERR (1<<0)	6799	#define GT_FIFO_IARDERR (1<<0)
6727		6800
6728	#define GTFIFOCTL 0x120008	6801	#define GTFIFOCTL _MMIO(0x120008)
6729	#define GT_FIFO_FREE_ENTRIES_MASK 0x7f	6802	#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
6730	#define GT_FIFO_NUM_RESERVED_ENTRIES 20	6803	#define GT_FIFO_NUM_RESERVED_ENTRIES 20
6731	#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)	6804	#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6732	#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)	6805	#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
6733		6806
6734	#define HSW_IDICR 0x9008	6807	#define HSW_IDICR _MMIO(0x9008)
6735	#define IDIHASHMSK(x) (((x) & 0x3f) << 16)	6808	#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6736	#define HSW_EDRAM_PRESENT 0x120010	6809	#define HSW_EDRAM_PRESENT _MMIO(0x120010)
6737	#define EDRAM_ENABLED 0x1	6810	#define EDRAM_ENABLED 0x1
6738		6811
6739	#define GEN6_UCGCTL1 0x9400	6812	#define GEN6_UCGCTL1 _MMIO(0x9400)
6740	# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)	6813	# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
6741	# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)	6814	# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
6742	# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)	6815	# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
6743		6816
6744	#define GEN6_UCGCTL2 0x9404	6817	#define GEN6_UCGCTL2 _MMIO(0x9404)
6745	# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)	6818	# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
6746	# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)	6819	# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
6747	# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)	6820	# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
@@ -6749,30 +6822,30 @@ enum skl_disp_power_wells { · 1 unmodified line
6749	# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)	6822	# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
6750	# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)	6823	# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
6751		6824
6752	#define GEN6_UCGCTL3 0x9408	6825	#define GEN6_UCGCTL3 _MMIO(0x9408)
6753		6826
6754	#define GEN7_UCGCTL4 0x940c	6827	#define GEN7_UCGCTL4 _MMIO(0x940c)
6755	#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)	6828	#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6756		6829
6757	#define GEN6_RCGCTL1 0x9410	6830	#define GEN6_RCGCTL1 _MMIO(0x9410)
6758	#define GEN6_RCGCTL2 0x9414	6831	#define GEN6_RCGCTL2 _MMIO(0x9414)
6759	#define GEN6_RSTCTL 0x9420	6832	#define GEN6_RSTCTL _MMIO(0x9420)
6760		6833
6761	#define GEN8_UCGCTL6 0x9430	6834	#define GEN8_UCGCTL6 _MMIO(0x9430)
6762	#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)	6835	#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
6763	#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)	6836	#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
6764	#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)	6837	#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
6765		6838
6766	#define GEN6_GFXPAUSE 0xA000	6839	#define GEN6_GFXPAUSE _MMIO(0xA000)
6767	#define GEN6_RPNSWREQ 0xA008	6840	#define GEN6_RPNSWREQ _MMIO(0xA008)
6768	#define GEN6_TURBO_DISABLE (1<<31)	6841	#define GEN6_TURBO_DISABLE (1<<31)
6769	#define GEN6_FREQUENCY(x) ((x)<<25)	6842	#define GEN6_FREQUENCY(x) ((x)<<25)
6770	#define HSW_FREQUENCY(x) ((x)<<24)	6843	#define HSW_FREQUENCY(x) ((x)<<24)
6771	#define GEN9_FREQUENCY(x) ((x)<<23)	6844	#define GEN9_FREQUENCY(x) ((x)<<23)
6772	#define GEN6_OFFSET(x) ((x)<<19)	6845	#define GEN6_OFFSET(x) ((x)<<19)
6773	#define GEN6_AGGRESSIVE_TURBO (0<<15)	6846	#define GEN6_AGGRESSIVE_TURBO (0<<15)
6774	#define GEN6_RC_VIDEO_FREQ 0xA00C	6847	#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
6775	#define GEN6_RC_CONTROL 0xA090	6848	#define GEN6_RC_CONTROL _MMIO(0xA090)
6776	#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)	6849	#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
6777	#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)	6850	#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
6778	#define GEN6_RC_CTL_RC6_ENABLE (1<<18)	6851	#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
@@ -6782,16 +6855,16 @@ enum skl_disp_power_wells { · 3 unmodified lines
6782	#define GEN7_RC_CTL_TO_MODE (1<<28)	6855	#define GEN7_RC_CTL_TO_MODE (1<<28)
6783	#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)	6856	#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
6784	#define GEN6_RC_CTL_HW_ENABLE (1<<31)	6857	#define GEN6_RC_CTL_HW_ENABLE (1<<31)
6785	#define GEN6_RP_DOWN_TIMEOUT 0xA010	6858	#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
6786	#define GEN6_RP_INTERRUPT_LIMITS 0xA014	6859	#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
6787	#define GEN6_RPSTAT1 0xA01C	6860	#define GEN6_RPSTAT1 _MMIO(0xA01C)
6788	#define GEN6_CAGF_SHIFT 8	6861	#define GEN6_CAGF_SHIFT 8
6789	#define HSW_CAGF_SHIFT 7	6862	#define HSW_CAGF_SHIFT 7
6790	#define GEN9_CAGF_SHIFT 23	6863	#define GEN9_CAGF_SHIFT 23
6791	#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)	6864	#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
6792	#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)	6865	#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
6793	#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)	6866	#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
6794	#define GEN6_RP_CONTROL 0xA024	6867	#define GEN6_RP_CONTROL _MMIO(0xA024)
6795	#define GEN6_RP_MEDIA_TURBO (1<<11)	6868	#define GEN6_RP_MEDIA_TURBO (1<<11)
6796	#define GEN6_RP_MEDIA_MODE_MASK (3<<9)	6869	#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6797	#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)	6870	#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
@@ -6805,53 +6878,53 @@ enum skl_disp_power_wells { · 7 unmodified lines
6805	#define GEN6_RP_UP_BUSY_CONT (0x4<<3)	6878	#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
6806	#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)	6879	#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
6807	#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)	6880	#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
6808	#define GEN6_RP_UP_THRESHOLD 0xA02C	6881	#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
6809	#define GEN6_RP_DOWN_THRESHOLD 0xA030	6882	#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
6810	#define GEN6_RP_CUR_UP_EI 0xA050	6883	#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
6811	#define GEN6_CURICONT_MASK 0xffffff	6884	#define GEN6_CURICONT_MASK 0xffffff
6812	#define GEN6_RP_CUR_UP 0xA054	6885	#define GEN6_RP_CUR_UP _MMIO(0xA054)
6813	#define GEN6_CURBSYTAVG_MASK 0xffffff	6886	#define GEN6_CURBSYTAVG_MASK 0xffffff
6814	#define GEN6_RP_PREV_UP 0xA058	6887	#define GEN6_RP_PREV_UP _MMIO(0xA058)
6815	#define GEN6_RP_CUR_DOWN_EI 0xA05C	6888	#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
6816	#define GEN6_CURIAVG_MASK 0xffffff	6889	#define GEN6_CURIAVG_MASK 0xffffff
6817	#define GEN6_RP_CUR_DOWN 0xA060	6890	#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
6818	#define GEN6_RP_PREV_DOWN 0xA064	6891	#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
6819	#define GEN6_RP_UP_EI 0xA068	6892	#define GEN6_RP_UP_EI _MMIO(0xA068)
6820	#define GEN6_RP_DOWN_EI 0xA06C	6893	#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
6821	#define GEN6_RP_IDLE_HYSTERSIS 0xA070	6894	#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
6822	#define GEN6_RPDEUHWTC 0xA080	6895	#define GEN6_RPDEUHWTC _MMIO(0xA080)
6823	#define GEN6_RPDEUC 0xA084	6896	#define GEN6_RPDEUC _MMIO(0xA084)
6824	#define GEN6_RPDEUCSW 0xA088	6897	#define GEN6_RPDEUCSW _MMIO(0xA088)
6825	#define GEN6_RC_STATE 0xA094	6898	#define GEN6_RC_STATE _MMIO(0xA094)
6826	#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098	6899	#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
6827	#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C	6900	#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
6828	#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0	6901	#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
6829	#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8	6902	#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
6830	#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC	6903	#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
6831	#define GEN6_RC_SLEEP 0xA0B0	6904	#define GEN6_RC_SLEEP _MMIO(0xA0B0)
6832	#define GEN6_RCUBMABDTMR 0xA0B0	6905	#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
6833	#define GEN6_RC1e_THRESHOLD 0xA0B4	6906	#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
6834	#define GEN6_RC6_THRESHOLD 0xA0B8	6907	#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
6835	#define GEN6_RC6p_THRESHOLD 0xA0BC	6908	#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
6836	#define VLV_RCEDATA 0xA0BC	6909	#define VLV_RCEDATA _MMIO(0xA0BC)
6837	#define GEN6_RC6pp_THRESHOLD 0xA0C0	6910	#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
6838	#define GEN6_PMINTRMSK 0xA168	6911	#define GEN6_PMINTRMSK _MMIO(0xA168)
6839	#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)	6912	#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
6840	#define VLV_PWRDWNUPCTL 0xA294	6913	#define VLV_PWRDWNUPCTL _MMIO(0xA294)
6841	#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4	6914	#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
6842	#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8	6915	#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
6843	#define GEN9_PG_ENABLE 0xA210	6916	#define GEN9_PG_ENABLE _MMIO(0xA210)
6844	#define GEN9_RENDER_PG_ENABLE (1<<0)	6917	#define GEN9_RENDER_PG_ENABLE (1<<0)
6845	#define GEN9_MEDIA_PG_ENABLE (1<<1)	6918	#define GEN9_MEDIA_PG_ENABLE (1<<1)
6846		6919
6847	#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)	6920	#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
6848	#define PIXEL_OVERLAP_CNT_MASK (3 << 30)	6921	#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6849	#define PIXEL_OVERLAP_CNT_SHIFT 30	6922	#define PIXEL_OVERLAP_CNT_SHIFT 30
6850		6923
6851	#define GEN6_PMISR 0x44020	6924	#define GEN6_PMISR _MMIO(0x44020)
6852	#define GEN6_PMIMR 0x44024 /* rps_lock */	6925	#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
6853	#define GEN6_PMIIR 0x44028	6926	#define GEN6_PMIIR _MMIO(0x44028)
6854	#define GEN6_PMIER 0x4402C	6927	#define GEN6_PMIER _MMIO(0x4402C)
6855	#define GEN6_PM_MBOX_EVENT (1<<25)	6928	#define GEN6_PM_MBOX_EVENT (1<<25)
6856	#define GEN6_PM_THERMAL_EVENT (1<<24)	6929	#define GEN6_PM_THERMAL_EVENT (1<<24)
6857	#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)	6930	#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
@@ -6863,30 +6936,30 @@ enum skl_disp_power_wells { · 5 unmodified lines
6863	GEN6_PM_RP_DOWN_THRESHOLD \| \	6936	GEN6_PM_RP_DOWN_THRESHOLD \| \
6864	GEN6_PM_RP_DOWN_TIMEOUT)	6937	GEN6_PM_RP_DOWN_TIMEOUT)
6865		6938
6866	#define GEN7_GT_SCRATCH(i) (0x4F100 + (i) * 4)	6939	#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
6867	#define GEN7_GT_SCRATCH_REG_NUM 8	6940	#define GEN7_GT_SCRATCH_REG_NUM 8
6868		6941
6869	#define VLV_GTLC_SURVIVABILITY_REG 0x130098	6942	#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
6870	#define VLV_GFX_CLK_STATUS_BIT (1<<3)	6943	#define VLV_GFX_CLK_STATUS_BIT (1<<3)
6871	#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)	6944	#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6872		6945
6873	#define GEN6_GT_GFX_RC6_LOCKED 0x138104	6946	#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
6874	#define VLV_COUNTER_CONTROL 0x138104	6947	#define VLV_COUNTER_CONTROL _MMIO(0x138104)
6875	#define VLV_COUNT_RANGE_HIGH (1<<15)	6948	#define VLV_COUNT_RANGE_HIGH (1<<15)
6876	#define VLV_MEDIA_RC0_COUNT_EN (1<<5)	6949	#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6877	#define VLV_RENDER_RC0_COUNT_EN (1<<4)	6950	#define VLV_RENDER_RC0_COUNT_EN (1<<4)
6878	#define VLV_MEDIA_RC6_COUNT_EN (1<<1)	6951	#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6879	#define VLV_RENDER_RC6_COUNT_EN (1<<0)	6952	#define VLV_RENDER_RC6_COUNT_EN (1<<0)
6880	#define GEN6_GT_GFX_RC6 0x138108	6953	#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
6881	#define VLV_GT_RENDER_RC6 0x138108	6954	#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
6882	#define VLV_GT_MEDIA_RC6 0x13810C	6955	#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
6883		6956
6884	#define GEN6_GT_GFX_RC6p 0x13810C	6957	#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
6885	#define GEN6_GT_GFX_RC6pp 0x138110	6958	#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
6886	#define VLV_RENDER_C0_COUNT 0x138118	6959	#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
6887	#define VLV_MEDIA_C0_COUNT 0x13811C	6960	#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
6888		6961
6889	#define GEN6_PCODE_MAILBOX 0x138124	6962	#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
6890	#define GEN6_PCODE_READY (1<<31)	6963	#define GEN6_PCODE_READY (1<<31)
6891	#define GEN6_PCODE_WRITE_RC6VIDS 0x4	6964	#define GEN6_PCODE_WRITE_RC6VIDS 0x4
6892	#define GEN6_PCODE_READ_RC6VIDS 0x5	6965	#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -6909,12 +6982,12 @@ enum skl_disp_power_wells { · 16 unmodified lines
6909	#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17	6982	#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
6910	#define DISPLAY_IPS_CONTROL 0x19	6983	#define DISPLAY_IPS_CONTROL 0x19
6911	#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A	6984	#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6912	#define GEN6_PCODE_DATA 0x138128	6985	#define GEN6_PCODE_DATA _MMIO(0x138128)
6913	#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8	6986	#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6914	#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16	6987	#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6915	#define GEN6_PCODE_DATA1 0x13812C	6988	#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
6916		6989
6917	#define GEN6_GT_CORE_STATUS 0x138060	6990	#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
6918	#define GEN6_CORE_CPD_STATE_MASK (7<<4)	6991	#define GEN6_CORE_CPD_STATE_MASK (7<<4)
6919	#define GEN6_RCn_MASK 7	6992	#define GEN6_RCn_MASK 7
6920	#define GEN6_RC0 0	6993	#define GEN6_RC0 0
@@ -6922,26 +6995,26 @@ enum skl_disp_power_wells { · 1 unmodified line
6922	#define GEN6_RC6 3	6995	#define GEN6_RC6 3
6923	#define GEN6_RC7 4	6996	#define GEN6_RC7 4
6924		6997
6925	#define GEN8_GT_SLICE_INFO 0x138064	6998	#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
6926	#define GEN8_LSLICESTAT_MASK 0x7	6999	#define GEN8_LSLICESTAT_MASK 0x7
6927		7000
6928	#define CHV_POWER_SS0_SIG1 0xa720	7001	#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
6929	#define CHV_POWER_SS1_SIG1 0xa728	7002	#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
6930	#define CHV_SS_PG_ENABLE (1<<1)	7003	#define CHV_SS_PG_ENABLE (1<<1)
6931	#define CHV_EU08_PG_ENABLE (1<<9)	7004	#define CHV_EU08_PG_ENABLE (1<<9)
6932	#define CHV_EU19_PG_ENABLE (1<<17)	7005	#define CHV_EU19_PG_ENABLE (1<<17)
6933	#define CHV_EU210_PG_ENABLE (1<<25)	7006	#define CHV_EU210_PG_ENABLE (1<<25)
6934		7007
6935	#define CHV_POWER_SS0_SIG2 0xa724	7008	#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
6936	#define CHV_POWER_SS1_SIG2 0xa72c	7009	#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
6937	#define CHV_EU311_PG_ENABLE (1<<1)	7010	#define CHV_EU311_PG_ENABLE (1<<1)
6938		7011
6939	#define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4)	7012	#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
6940	#define GEN9_PGCTL_SLICE_ACK (1 << 0)	7013	#define GEN9_PGCTL_SLICE_ACK (1 << 0)
6941	#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))	7014	#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
6942		7015
6943	#define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8)	7016	#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
6944	#define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8)	7017	#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
6945	#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)	7018	#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
6946	#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)	7019	#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
6947	#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)	7020	#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
@@ -6951,18 +7024,17 @@ enum skl_disp_power_wells { · 3 unmodified lines
6951	#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)	7024	#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
6952	#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)	7025	#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
6953		7026
6954	#define GEN7_MISCCPCTL (0x9424)	7027	#define GEN7_MISCCPCTL _MMIO(0x9424)
6955	#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)	7028	#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6956	#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)	7029	#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
6957	#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)	7030	#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
6958	#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)	7031	#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
6959		7032
6960	#define GEN8_GARBCNTL 0xB004	7033	#define GEN8_GARBCNTL _MMIO(0xB004)
6961	#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)	7034	#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
6962		7035
6963	/* IVYBRIDGE DPF */	7036	/* IVYBRIDGE DPF */
6964	#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */	7037	#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
6965	#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
6966	#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)	7038	#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6967	#define GEN7_PARITY_ERROR_VALID (1<<13)	7039	#define GEN7_PARITY_ERROR_VALID (1<<13)
6968	#define GEN7_L3CDERRST1_BANK_MASK (3<<11)	7040	#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
@@ -6975,119 +7047,102 @@ enum skl_disp_power_wells { · 6 unmodified lines
6975	((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)	7047	((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6976	#define GEN7_L3CDERRST1_ENABLE (1<<7)	7048	#define GEN7_L3CDERRST1_ENABLE (1<<7)
6977		7049
6978	#define GEN7_L3LOG_BASE 0xB070	7050	#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
6979	#define HSW_L3LOG_BASE_SLICE1 0xB270
6980	#define GEN7_L3LOG_SIZE 0x80	7051	#define GEN7_L3LOG_SIZE 0x80
6981		7052
6982	#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */	7053	#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
6983	#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100	7054	#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
6984	#define GEN7_MAX_PS_THREAD_DEP (8<<12)	7055	#define GEN7_MAX_PS_THREAD_DEP (8<<12)
6985	#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)	7056	#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
6986	#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)	7057	#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
6987	#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)	7058	#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6988		7059
6989	#define GEN9_HALF_SLICE_CHICKEN5 0xe188	7060	#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
6990	#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)	7061	#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
6991	#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)	7062	#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
6992		7063
6993	#define GEN8_ROW_CHICKEN 0xe4f0	7064	#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
6994	#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)	7065	#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
6995	#define STALL_DOP_GATING_DISABLE (1<<5)	7066	#define STALL_DOP_GATING_DISABLE (1<<5)
6996		7067
6997	#define GEN7_ROW_CHICKEN2 0xe4f4	7068	#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
6998	#define GEN7_ROW_CHICKEN2_GT2 0xf4f4	7069	#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
6999	#define DOP_CLOCK_GATING_DISABLE (1<<0)	7070	#define DOP_CLOCK_GATING_DISABLE (1<<0)
7000		7071
7001	#define HSW_ROW_CHICKEN3 0xe49c	7072	#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
7002	#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)	7073	#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
7003		7074
7004	#define HALF_SLICE_CHICKEN2 0xe180	7075	#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
7005	#define GEN8_ST_PO_DISABLE (1<<13)	7076	#define GEN8_ST_PO_DISABLE (1<<13)
7006		7077
7007	#define HALF_SLICE_CHICKEN3 0xe184	7078	#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
7008	#define HSW_SAMPLE_C_PERFORMANCE (1<<9)	7079	#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
7009	#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)	7080	#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
7010	#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)	7081	#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
7011	#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)	7082	#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
7012		7083
7013	#define GEN9_HALF_SLICE_CHICKEN7 0xe194	7084	#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
7014	#define GEN9_ENABLE_YV12_BUGFIX (1<<4)	7085	#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
7015		7086
7016	/* Audio */	7087	/* Audio */
7017	#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)	7088	#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
7018	#define INTEL_AUDIO_DEVCL 0x808629FB	7089	#define INTEL_AUDIO_DEVCL 0x808629FB
7019	#define INTEL_AUDIO_DEVBLC 0x80862801	7090	#define INTEL_AUDIO_DEVBLC 0x80862801
7020	#define INTEL_AUDIO_DEVCTG 0x80862802	7091	#define INTEL_AUDIO_DEVCTG 0x80862802
7021		7092
7022	#define G4X_AUD_CNTL_ST 0x620B4	7093	#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
7023	#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)	7094	#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
7024	#define G4X_ELDV_DEVCTG (1 << 14)	7095	#define G4X_ELDV_DEVCTG (1 << 14)
7025	#define G4X_ELD_ADDR_MASK (0xf << 5)	7096	#define G4X_ELD_ADDR_MASK (0xf << 5)
7026	#define G4X_ELD_ACK (1 << 4)	7097	#define G4X_ELD_ACK (1 << 4)
7027	#define G4X_HDMIW_HDMIEDID 0x6210C	7098	#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
7028		7099
7029	#define _IBX_HDMIW_HDMIEDID_A 0xE2050	7100	#define _IBX_HDMIW_HDMIEDID_A 0xE2050
7030	#define _IBX_HDMIW_HDMIEDID_B 0xE2150	7101	#define _IBX_HDMIW_HDMIEDID_B 0xE2150
7031	#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \	7102	#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
7032	_IBX_HDMIW_HDMIEDID_A, \	7103	_IBX_HDMIW_HDMIEDID_B)
7033	_IBX_HDMIW_HDMIEDID_B)
7034	#define _IBX_AUD_CNTL_ST_A 0xE20B4	7104	#define _IBX_AUD_CNTL_ST_A 0xE20B4
7035	#define _IBX_AUD_CNTL_ST_B 0xE21B4	7105	#define _IBX_AUD_CNTL_ST_B 0xE21B4
7036	#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \	7106	#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
7037	_IBX_AUD_CNTL_ST_A, \	7107	_IBX_AUD_CNTL_ST_B)
7038	_IBX_AUD_CNTL_ST_B)
7039	#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)	7108	#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
7040	#define IBX_ELD_ADDRESS_MASK (0x1f << 5)	7109	#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
7041	#define IBX_ELD_ACK (1 << 4)	7110	#define IBX_ELD_ACK (1 << 4)
7042	#define IBX_AUD_CNTL_ST2 0xE20C0	7111	#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
7043	#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))	7112	#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
7044	#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))	7113	#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
7045		7114
7046	#define _CPT_HDMIW_HDMIEDID_A 0xE5050	7115	#define _CPT_HDMIW_HDMIEDID_A 0xE5050
7047	#define _CPT_HDMIW_HDMIEDID_B 0xE5150	7116	#define _CPT_HDMIW_HDMIEDID_B 0xE5150
7048	#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \	7117	#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
7049	_CPT_HDMIW_HDMIEDID_A, \
7050	_CPT_HDMIW_HDMIEDID_B)
7051	#define _CPT_AUD_CNTL_ST_A 0xE50B4	7118	#define _CPT_AUD_CNTL_ST_A 0xE50B4
7052	#define _CPT_AUD_CNTL_ST_B 0xE51B4	7119	#define _CPT_AUD_CNTL_ST_B 0xE51B4
7053	#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \	7120	#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
7054	_CPT_AUD_CNTL_ST_A, \	7121	#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
7055	_CPT_AUD_CNTL_ST_B)
7056	#define CPT_AUD_CNTRL_ST2 0xE50C0
7057		7122
7058	#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)	7123	#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
7059	#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)	7124	#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
7060	#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \	7125	#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
7061	_VLV_HDMIW_HDMIEDID_A, \
7062	_VLV_HDMIW_HDMIEDID_B)
7063	#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)	7126	#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
7064	#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)	7127	#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
7065	#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \	7128	#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
7066	_VLV_AUD_CNTL_ST_A, \	7129	#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
7067	_VLV_AUD_CNTL_ST_B)
7068	#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
7069		7130
7070	/* These are the 4 32-bit write offset registers for each stream	7131	/* These are the 4 32-bit write offset registers for each stream
7071	* output buffer. It determines the offset from the	7132	* output buffer. It determines the offset from the
7072	* 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.	7133	* 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7073	*/	7134	*/
7074	#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)	7135	#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
7075		7136
7076	#define _IBX_AUD_CONFIG_A 0xe2000	7137	#define _IBX_AUD_CONFIG_A 0xe2000
7077	#define _IBX_AUD_CONFIG_B 0xe2100	7138	#define _IBX_AUD_CONFIG_B 0xe2100
7078	#define IBX_AUD_CFG(pipe) _PIPE(pipe, \	7139	#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
7079	_IBX_AUD_CONFIG_A, \
7080	_IBX_AUD_CONFIG_B)
7081	#define _CPT_AUD_CONFIG_A 0xe5000	7140	#define _CPT_AUD_CONFIG_A 0xe5000
7082	#define _CPT_AUD_CONFIG_B 0xe5100	7141	#define _CPT_AUD_CONFIG_B 0xe5100
7083	#define CPT_AUD_CFG(pipe) _PIPE(pipe, \	7142	#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
7084	_CPT_AUD_CONFIG_A, \
7085	_CPT_AUD_CONFIG_B)
7086	#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)	7143	#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
7087	#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)	7144	#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
7088	#define VLV_AUD_CFG(pipe) _PIPE(pipe, \	7145	#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
7089	_VLV_AUD_CONFIG_A, \
7090	_VLV_AUD_CONFIG_B)
7091		7146
7092	#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)	7147	#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
7093	#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)	7148	#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
@@ -7112,72 +7167,62 @@ enum skl_disp_power_wells { · 18 unmodified lines
7112	/* HSW Audio */	7167	/* HSW Audio */
7113	#define _HSW_AUD_CONFIG_A 0x65000	7168	#define _HSW_AUD_CONFIG_A 0x65000
7114	#define _HSW_AUD_CONFIG_B 0x65100	7169	#define _HSW_AUD_CONFIG_B 0x65100
7115	#define HSW_AUD_CFG(pipe) _PIPE(pipe, \	7170	#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
7116	_HSW_AUD_CONFIG_A, \
7117	_HSW_AUD_CONFIG_B)
7118		7171
7119	#define _HSW_AUD_MISC_CTRL_A 0x65010	7172	#define _HSW_AUD_MISC_CTRL_A 0x65010
7120	#define _HSW_AUD_MISC_CTRL_B 0x65110	7173	#define _HSW_AUD_MISC_CTRL_B 0x65110
7121	#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \	7174	#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
7122	_HSW_AUD_MISC_CTRL_A, \
7123	_HSW_AUD_MISC_CTRL_B)
7124		7175
7125	#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4	7176	#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7126	#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4	7177	#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
7127	#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \	7178	#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
7128	_HSW_AUD_DIP_ELD_CTRL_ST_A, \
7129	_HSW_AUD_DIP_ELD_CTRL_ST_B)
7130		7179
7131	/* Audio Digital Converter */	7180	/* Audio Digital Converter */
7132	#define _HSW_AUD_DIG_CNVT_1 0x65080	7181	#define _HSW_AUD_DIG_CNVT_1 0x65080
7133	#define _HSW_AUD_DIG_CNVT_2 0x65180	7182	#define _HSW_AUD_DIG_CNVT_2 0x65180
7134	#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \	7183	#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
7135	_HSW_AUD_DIG_CNVT_1, \
7136	_HSW_AUD_DIG_CNVT_2)
7137	#define DIP_PORT_SEL_MASK 0x3	7184	#define DIP_PORT_SEL_MASK 0x3
7138		7185
7139	#define _HSW_AUD_EDID_DATA_A 0x65050	7186	#define _HSW_AUD_EDID_DATA_A 0x65050
7140	#define _HSW_AUD_EDID_DATA_B 0x65150	7187	#define _HSW_AUD_EDID_DATA_B 0x65150
7141	#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \	7188	#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
7142	_HSW_AUD_EDID_DATA_A, \
7143	_HSW_AUD_EDID_DATA_B)
7144		7189
7145	#define HSW_AUD_PIPE_CONV_CFG 0x6507c	7190	#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
7146	#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0	7191	#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
7147	#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))	7192	#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7148	#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))	7193	#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7149	#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))	7194	#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7150	#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))	7195	#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
7151		7196
7152	#define HSW_AUD_CHICKENBIT 0x65f10	7197	#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
7153	#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)	7198	#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7154		7199
7155	/* HSW Power Wells */	7200	/* HSW Power Wells */
7156	#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */	7201	#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */
7157	#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */	7202	#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */
7158	#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */	7203	#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */
7159	#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */	7204	#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */
7160	#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)	7205	#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7161	#define HSW_PWR_WELL_STATE_ENABLED (1<<30)	7206	#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
7162	#define HSW_PWR_WELL_CTL5 0x45410	7207	#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
7163	#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)	7208	#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7164	#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)	7209	#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
7165	#define HSW_PWR_WELL_FORCE_ON (1<<19)	7210	#define HSW_PWR_WELL_FORCE_ON (1<<19)
7166	#define HSW_PWR_WELL_CTL6 0x45414	7211	#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
7167		7212
7168	/* SKL Fuse Status */	7213	/* SKL Fuse Status */
7169	#define SKL_FUSE_STATUS 0x42000	7214	#define SKL_FUSE_STATUS _MMIO(0x42000)
7170	#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)	7215	#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7171	#define SKL_FUSE_PG0_DIST_STATUS (1<<27)	7216	#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7172	#define SKL_FUSE_PG1_DIST_STATUS (1<<26)	7217	#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7173	#define SKL_FUSE_PG2_DIST_STATUS (1<<25)	7218	#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7174		7219
7175	/* Per-pipe DDI Function Control */	7220	/* Per-pipe DDI Function Control */
7176	#define TRANS_DDI_FUNC_CTL_A 0x60400	7221	#define _TRANS_DDI_FUNC_CTL_A 0x60400
7177	#define TRANS_DDI_FUNC_CTL_B 0x61400	7222	#define _TRANS_DDI_FUNC_CTL_B 0x61400
7178	#define TRANS_DDI_FUNC_CTL_C 0x62400	7223	#define _TRANS_DDI_FUNC_CTL_C 0x62400
7179	#define TRANS_DDI_FUNC_CTL_EDP 0x6F400	7224	#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
7180	#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)	7225	#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
7181		7226
7182	#define TRANS_DDI_FUNC_ENABLE (1<<31)	7227	#define TRANS_DDI_FUNC_ENABLE (1<<31)
7183	/* Those bits are ignored by pipe EDP since it can only connect to DDI A */	7228	/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
@@ -7207,9 +7252,9 @@ enum skl_disp_power_wells { · 23 unmodified lines
7207	#define TRANS_DDI_BFI_ENABLE (1<<4)	7252	#define TRANS_DDI_BFI_ENABLE (1<<4)
7208		7253
7209	/* DisplayPort Transport Control */	7254	/* DisplayPort Transport Control */
7210	#define DP_TP_CTL_A 0x64040	7255	#define _DP_TP_CTL_A 0x64040
7211	#define DP_TP_CTL_B 0x64140	7256	#define _DP_TP_CTL_B 0x64140
7212	#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)	7257	#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
7213	#define DP_TP_CTL_ENABLE (1<<31)	7258	#define DP_TP_CTL_ENABLE (1<<31)
7214	#define DP_TP_CTL_MODE_SST (0<<27)	7259	#define DP_TP_CTL_MODE_SST (0<<27)
7215	#define DP_TP_CTL_MODE_MST (1<<27)	7260	#define DP_TP_CTL_MODE_MST (1<<27)
@@ -7225,9 +7270,9 @@ enum skl_disp_power_wells { · 9 unmodified lines
7225	#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)	7270	#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
7226		7271
7227	/* DisplayPort Transport Status */	7272	/* DisplayPort Transport Status */
7228	#define DP_TP_STATUS_A 0x64044	7273	#define _DP_TP_STATUS_A 0x64044
7229	#define DP_TP_STATUS_B 0x64144	7274	#define _DP_TP_STATUS_B 0x64144
7230	#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)	7275	#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
7231	#define DP_TP_STATUS_IDLE_DONE (1<<25)	7276	#define DP_TP_STATUS_IDLE_DONE (1<<25)
7232	#define DP_TP_STATUS_ACT_SENT (1<<24)	7277	#define DP_TP_STATUS_ACT_SENT (1<<24)
7233	#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)	7278	#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
@@ -7237,9 +7282,9 @@ enum skl_disp_power_wells { · 3 unmodified lines
7237	#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)	7282	#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
7238		7283
7239	/* DDI Buffer Control */	7284	/* DDI Buffer Control */
7240	#define DDI_BUF_CTL_A 0x64000	7285	#define _DDI_BUF_CTL_A 0x64000
7241	#define DDI_BUF_CTL_B 0x64100	7286	#define _DDI_BUF_CTL_B 0x64100
7242	#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)	7287	#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
7243	#define DDI_BUF_CTL_ENABLE (1<<31)	7288	#define DDI_BUF_CTL_ENABLE (1<<31)
7244	#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)	7289	#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
7245	#define DDI_BUF_EMP_MASK (0xf<<24)	7290	#define DDI_BUF_EMP_MASK (0xf<<24)
@@ -7252,17 +7297,17 @@ enum skl_disp_power_wells { · 6 unmodified lines
7252	#define DDI_INIT_DISPLAY_DETECTED (1<<0)	7297	#define DDI_INIT_DISPLAY_DETECTED (1<<0)
7253		7298
7254	/* DDI Buffer Translations */	7299	/* DDI Buffer Translations */
7255	#define DDI_BUF_TRANS_A 0x64E00	7300	#define _DDI_BUF_TRANS_A 0x64E00
7256	#define DDI_BUF_TRANS_B 0x64E60	7301	#define _DDI_BUF_TRANS_B 0x64E60
7257	#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8)	7302	#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
7258	#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4)	7303	#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
7259		7304
7260	/* Sideband Interface (SBI) is programmed indirectly, via	7305	/* Sideband Interface (SBI) is programmed indirectly, via
7261	* SBI_ADDR, which contains the register offset; and SBI_DATA,	7306	* SBI_ADDR, which contains the register offset; and SBI_DATA,
7262	* which contains the payload */	7307	* which contains the payload */
7263	#define SBI_ADDR 0xC6000	7308	#define SBI_ADDR _MMIO(0xC6000)
7264	#define SBI_DATA 0xC6004	7309	#define SBI_DATA _MMIO(0xC6004)
7265	#define SBI_CTL_STAT 0xC6008	7310	#define SBI_CTL_STAT _MMIO(0xC6008)
7266	#define SBI_CTL_DEST_ICLK (0x0<<16)	7311	#define SBI_CTL_DEST_ICLK (0x0<<16)
7267	#define SBI_CTL_DEST_MPHY (0x1<<16)	7312	#define SBI_CTL_DEST_MPHY (0x1<<16)
7268	#define SBI_CTL_OP_IORD (0x2<<8)	7313	#define SBI_CTL_OP_IORD (0x2<<8)
@@ -7293,12 +7338,12 @@ enum skl_disp_power_wells { · 24 unmodified lines
7293	#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)	7338	#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
7294		7339
7295	/* LPT PIXCLK_GATE */	7340	/* LPT PIXCLK_GATE */
7296	#define PIXCLK_GATE 0xC6020	7341	#define PIXCLK_GATE _MMIO(0xC6020)
7297	#define PIXCLK_GATE_UNGATE (1<<0)	7342	#define PIXCLK_GATE_UNGATE (1<<0)
7298	#define PIXCLK_GATE_GATE (0<<0)	7343	#define PIXCLK_GATE_GATE (0<<0)
7299		7344
7300	/* SPLL */	7345	/* SPLL */
7301	#define SPLL_CTL 0x46020	7346	#define SPLL_CTL _MMIO(0x46020)
7302	#define SPLL_PLL_ENABLE (1<<31)	7347	#define SPLL_PLL_ENABLE (1<<31)
7303	#define SPLL_PLL_SSC (1<<28)	7348	#define SPLL_PLL_SSC (1<<28)
7304	#define SPLL_PLL_NON_SSC (2<<28)	7349	#define SPLL_PLL_NON_SSC (2<<28)
@@ -7310,9 +7355,9 @@ enum skl_disp_power_wells { · 5 unmodified lines
7310	#define SPLL_PLL_FREQ_MASK (3<<26)	7355	#define SPLL_PLL_FREQ_MASK (3<<26)
7311		7356
7312	/* WRPLL */	7357	/* WRPLL */
7313	#define WRPLL_CTL1 0x46040	7358	#define _WRPLL_CTL1 0x46040
7314	#define WRPLL_CTL2 0x46060	7359	#define _WRPLL_CTL2 0x46060
7315	#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)	7360	#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
7316	#define WRPLL_PLL_ENABLE (1<<31)	7361	#define WRPLL_PLL_ENABLE (1<<31)
7317	#define WRPLL_PLL_SSC (1<<28)	7362	#define WRPLL_PLL_SSC (1<<28)
7318	#define WRPLL_PLL_NON_SSC (2<<28)	7363	#define WRPLL_PLL_NON_SSC (2<<28)
@@ -7329,9 +7374,9 @@ enum skl_disp_power_wells { · 10 unmodified lines
7329	#define WRPLL_DIVIDER_FB_MASK (0xff<<16)	7374	#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
7330		7375
7331	/* Port clock selection */	7376	/* Port clock selection */
7332	#define PORT_CLK_SEL_A 0x46100	7377	#define _PORT_CLK_SEL_A 0x46100
7333	#define PORT_CLK_SEL_B 0x46104	7378	#define _PORT_CLK_SEL_B 0x46104
7334	#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)	7379	#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
7335	#define PORT_CLK_SEL_LCPLL_2700 (0<<29)	7380	#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7336	#define PORT_CLK_SEL_LCPLL_1350 (1<<29)	7381	#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7337	#define PORT_CLK_SEL_LCPLL_810 (2<<29)	7382	#define PORT_CLK_SEL_LCPLL_810 (2<<29)
@@ -7343,18 +7388,18 @@ enum skl_disp_power_wells { · 5 unmodified lines
7343	#define PORT_CLK_SEL_MASK (7<<29)	7388	#define PORT_CLK_SEL_MASK (7<<29)
7344		7389
7345	/* Transcoder clock selection */	7390	/* Transcoder clock selection */
7346	#define TRANS_CLK_SEL_A 0x46140	7391	#define _TRANS_CLK_SEL_A 0x46140
7347	#define TRANS_CLK_SEL_B 0x46144	7392	#define _TRANS_CLK_SEL_B 0x46144
7348	#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)	7393	#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
7349	/* For each transcoder, we need to select the corresponding port clock */	7394	/* For each transcoder, we need to select the corresponding port clock */
7350	#define TRANS_CLK_SEL_DISABLED (0x0<<29)	7395	#define TRANS_CLK_SEL_DISABLED (0x0<<29)
7351	#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)	7396	#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
7352		7397
7353	#define TRANSA_MSA_MISC 0x60410	7398	#define _TRANSA_MSA_MISC 0x60410
7354	#define TRANSB_MSA_MISC 0x61410	7399	#define _TRANSB_MSA_MISC 0x61410
7355	#define TRANSC_MSA_MISC 0x62410	7400	#define _TRANSC_MSA_MISC 0x62410
7356	#define TRANS_EDP_MSA_MISC 0x6f410	7401	#define _TRANS_EDP_MSA_MISC 0x6f410
7357	#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)	7402	#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
7358		7403
7359	#define TRANS_MSA_SYNC_CLK (1<<0)	7404	#define TRANS_MSA_SYNC_CLK (1<<0)
7360	#define TRANS_MSA_6_BPC (0<<5)	7405	#define TRANS_MSA_6_BPC (0<<5)
@@ -7364,7 +7409,7 @@ enum skl_disp_power_wells { · 3 unmodified lines
7364	#define TRANS_MSA_16_BPC (4<<5)	7409	#define TRANS_MSA_16_BPC (4<<5)
7365		7410
7366	/* LCPLL Control */	7411	/* LCPLL Control */
7367	#define LCPLL_CTL 0x130040	7412	#define LCPLL_CTL _MMIO(0x130040)
7368	#define LCPLL_PLL_DISABLE (1<<31)	7413	#define LCPLL_PLL_DISABLE (1<<31)
7369	#define LCPLL_PLL_LOCK (1<<30)	7414	#define LCPLL_PLL_LOCK (1<<30)
7370	#define LCPLL_CLK_FREQ_MASK (3<<26)	7415	#define LCPLL_CLK_FREQ_MASK (3<<26)
@@ -7384,7 +7429,7 @@ enum skl_disp_power_wells { · 13 unmodified lines
7384	*/	7429	*/
7385		7430
7386	/* CDCLK_CTL */	7431	/* CDCLK_CTL */
7387	#define CDCLK_CTL 0x46000	7432	#define CDCLK_CTL _MMIO(0x46000)
7388	#define CDCLK_FREQ_SEL_MASK (3<<26)	7433	#define CDCLK_FREQ_SEL_MASK (3<<26)
7389	#define CDCLK_FREQ_450_432 (0<<26)	7434	#define CDCLK_FREQ_450_432 (0<<26)
7390	#define CDCLK_FREQ_540 (1<<26)	7435	#define CDCLK_FREQ_540 (1<<26)
@@ -7400,12 +7445,12 @@ enum skl_disp_power_wells { · 9 unmodified lines
7400	#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)	7445	#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
7401		7446
7402	/* LCPLL_CTL */	7447	/* LCPLL_CTL */
7403	#define LCPLL1_CTL 0x46010	7448	#define LCPLL1_CTL _MMIO(0x46010)
7404	#define LCPLL2_CTL 0x46014	7449	#define LCPLL2_CTL _MMIO(0x46014)
7405	#define LCPLL_PLL_ENABLE (1<<31)	7450	#define LCPLL_PLL_ENABLE (1<<31)
7406		7451
7407	/* DPLL control1 */	7452	/* DPLL control1 */
7408	#define DPLL_CTRL1 0x6C058	7453	#define DPLL_CTRL1 _MMIO(0x6C058)
7409	#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))	7454	#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7410	#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))	7455	#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
7411	#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))	7456	#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
@@ -7420,7 +7465,7 @@ enum skl_disp_power_wells { · 8 unmodified lines
7420	#define DPLL_CTRL1_LINK_RATE_2160 5	7465	#define DPLL_CTRL1_LINK_RATE_2160 5
7421		7466
7422	/* DPLL control2 */	7467	/* DPLL control2 */
7423	#define DPLL_CTRL2 0x6C05C	7468	#define DPLL_CTRL2 _MMIO(0x6C05C)
7424	#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))	7469	#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
7425	#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))	7470	#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
7426	#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)	7471	#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
@@ -7428,21 +7473,21 @@ enum skl_disp_power_wells { · 1 unmodified line
7428	#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))	7473	#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7429		7474
7430	/* DPLL Status */	7475	/* DPLL Status */
7431	#define DPLL_STATUS 0x6C060	7476	#define DPLL_STATUS _MMIO(0x6C060)
7432	#define DPLL_LOCK(id) (1<<((id)*8))	7477	#define DPLL_LOCK(id) (1<<((id)*8))
7433		7478
7434	/* DPLL cfg */	7479	/* DPLL cfg */
7435	#define DPLL1_CFGCR1 0x6C040	7480	#define _DPLL1_CFGCR1 0x6C040
7436	#define DPLL2_CFGCR1 0x6C048	7481	#define _DPLL2_CFGCR1 0x6C048
7437	#define DPLL3_CFGCR1 0x6C050	7482	#define _DPLL3_CFGCR1 0x6C050
7438	#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)	7483	#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7439	#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)	7484	#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
7440	#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)	7485	#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
7441	#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)	7486	#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7442		7487
7443	#define DPLL1_CFGCR2 0x6C044	7488	#define _DPLL1_CFGCR2 0x6C044
7444	#define DPLL2_CFGCR2 0x6C04C	7489	#define _DPLL2_CFGCR2 0x6C04C
7445	#define DPLL3_CFGCR2 0x6C054	7490	#define _DPLL3_CFGCR2 0x6C054
7446	#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)	7491	#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
7447	#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)	7492	#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
7448	#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)	7493	#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
@@ -7460,58 +7505,58 @@ enum skl_disp_power_wells { · 11 unmodified lines
7460	#define DPLL_CFGCR2_PDIV_7 (4<<2)	7505	#define DPLL_CFGCR2_PDIV_7 (4<<2)
7461	#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)	7506	#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7462		7507
7463	#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)	7508	#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
7464	#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)	7509	#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
7465		7510
7466	/* BXT display engine PLL */	7511	/* BXT display engine PLL */
7467	#define BXT_DE_PLL_CTL 0x6d000	7512	#define BXT_DE_PLL_CTL _MMIO(0x6d000)
7468	#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */	7513	#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7469	#define BXT_DE_PLL_RATIO_MASK 0xff	7514	#define BXT_DE_PLL_RATIO_MASK 0xff
7470		7515
7471	#define BXT_DE_PLL_ENABLE 0x46070	7516	#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
7472	#define BXT_DE_PLL_PLL_ENABLE (1 << 31)	7517	#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7473	#define BXT_DE_PLL_LOCK (1 << 30)	7518	#define BXT_DE_PLL_LOCK (1 << 30)
7474		7519
7475	/* GEN9 DC */	7520	/* GEN9 DC */
7476	#define DC_STATE_EN 0x45504	7521	#define DC_STATE_EN _MMIO(0x45504)
		7522	#define DC_STATE_DISABLE 0
7477	#define DC_STATE_EN_UPTO_DC5 (1<<0)	7523	#define DC_STATE_EN_UPTO_DC5 (1<<0)
7478	#define DC_STATE_EN_DC9 (1<<3)	7524	#define DC_STATE_EN_DC9 (1<<3)
7479	#define DC_STATE_EN_UPTO_DC6 (2<<0)	7525	#define DC_STATE_EN_UPTO_DC6 (2<<0)
7480	#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3	7526	#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7481		7527
7482	#define DC_STATE_DEBUG 0x45520	7528	#define DC_STATE_DEBUG _MMIO(0x45520)
7483	#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)	7529	#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7484		7530
7485	/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,	7531	/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7486	* since on HSW we can't write to it using I915_WRITE. */	7532	* since on HSW we can't write to it using I915_WRITE. */
7487	#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)	7533	#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7488	#define D_COMP_BDW 0x138144	7534	#define D_COMP_BDW _MMIO(0x138144)
7489	#define D_COMP_RCOMP_IN_PROGRESS (1<<9)	7535	#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7490	#define D_COMP_COMP_FORCE (1<<8)	7536	#define D_COMP_COMP_FORCE (1<<8)
7491	#define D_COMP_COMP_DISABLE (1<<0)	7537	#define D_COMP_COMP_DISABLE (1<<0)
7492		7538
7493	/* Pipe WM_LINETIME - watermark line time */	7539	/* Pipe WM_LINETIME - watermark line time */
7494	#define PIPE_WM_LINETIME_A 0x45270	7540	#define _PIPE_WM_LINETIME_A 0x45270
7495	#define PIPE_WM_LINETIME_B 0x45274	7541	#define _PIPE_WM_LINETIME_B 0x45274
7496	#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \	7542	#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
7497	PIPE_WM_LINETIME_B)
7498	#define PIPE_WM_LINETIME_MASK (0x1ff)	7543	#define PIPE_WM_LINETIME_MASK (0x1ff)
7499	#define PIPE_WM_LINETIME_TIME(x) ((x))	7544	#define PIPE_WM_LINETIME_TIME(x) ((x))
7500	#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)	7545	#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
7501	#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)	7546	#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
7502		7547
7503	/* SFUSE_STRAP */	7548	/* SFUSE_STRAP */
7504	#define SFUSE_STRAP 0xc2014	7549	#define SFUSE_STRAP _MMIO(0xc2014)
7505	#define SFUSE_STRAP_FUSE_LOCK (1<<13)	7550	#define SFUSE_STRAP_FUSE_LOCK (1<<13)
7506	#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)	7551	#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
7507	#define SFUSE_STRAP_DDIB_DETECTED (1<<2)	7552	#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7508	#define SFUSE_STRAP_DDIC_DETECTED (1<<1)	7553	#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7509	#define SFUSE_STRAP_DDID_DETECTED (1<<0)	7554	#define SFUSE_STRAP_DDID_DETECTED (1<<0)
7510		7555
7511	#define WM_MISC 0x45260	7556	#define WM_MISC _MMIO(0x45260)
7512	#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)	7557	#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7513		7558
7514	#define WM_DBG 0x45280	7559	#define WM_DBG _MMIO(0x45280)
7515	#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)	7560	#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7516	#define WM_DBG_DISALLOW_MAXFIFO (1<<1)	7561	#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7517	#define WM_DBG_DISALLOW_SPRITE (1<<2)	7562	#define WM_DBG_DISALLOW_SPRITE (1<<2)
@@ -7548,28 +7593,29 @@ enum skl_disp_power_wells { · 30 unmodified lines
7548	#define _PIPE_B_CSC_POSTOFF_ME 0x49144	7593	#define _PIPE_B_CSC_POSTOFF_ME 0x49144
7549	#define _PIPE_B_CSC_POSTOFF_LO 0x49148	7594	#define _PIPE_B_CSC_POSTOFF_LO 0x49148
7550		7595
7551	#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7552	#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7553	#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)

473 more lines aren’t shown here.

drivers/gpu/drm/i915/i915_sysfs.c+2−1

@@ -35,7 +35,8 @@ · 34 unmodified lines
35	#define dev_to_drm_minor(d) dev_get_drvdata((d))	35	#define dev_to_drm_minor(d) dev_get_drvdata((d))
36		36
37	#ifdef CONFIG_PM	37	#ifdef CONFIG_PM
38	static u32 calc_residency(struct drm_device *dev, const u32 reg)	38	static u32 calc_residency(struct drm_device *dev,
		39	i915_reg_t reg)
39	{	40	{
40	struct drm_i915_private *dev_priv = dev->dev_private;	41	struct drm_i915_private *dev_priv = dev->dev_private;
41	u64 raw_time; /* 32b value may overflow during fixed point math */	42	u64 raw_time; /* 32b value may overflow during fixed point math */

drivers/gpu/drm/i915/i915_trace.h+2−2

@@ -664,7 +664,7 @@ TRACE_EVENT(i915_flip_complete, · 663 unmodified lines
664	);	664	);
665		665
666	TRACE_EVENT_CONDITION(i915_reg_rw,	666	TRACE_EVENT_CONDITION(i915_reg_rw,
667	TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),	667	TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),
668		668
669	TP_ARGS(write, reg, val, len, trace),	669	TP_ARGS(write, reg, val, len, trace),
670		670
@@ -679,7 +679,7 @@ TRACE_EVENT_CONDITION(i915_reg_rw, · 8 unmodified lines
679		679
680	TP_fast_assign(	680	TP_fast_assign(
681	__entry->val = (u64)val;	681	__entry->val = (u64)val;
682	__entry->reg = reg;	682	__entry->reg = i915_mmio_reg_offset(reg);
683	__entry->write = write;	683	__entry->write = write;
684	__entry->len = len;	684	__entry->len = len;
685	),	685	),

drivers/gpu/drm/i915/i915_vgpu.c+3−3

@@ -69,13 +69,13 @@ void i915_check_vgpu(struct drm_device *dev) · 68 unmodified lines
69	if (!IS_HASWELL(dev))	69	if (!IS_HASWELL(dev))
70	return;	70	return;
71		71
72	magic = readq(dev_priv->regs + vgtif_reg(magic));	72	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
73	if (magic != VGT_MAGIC)	73	if (magic != VGT_MAGIC)
74	return;	74	return;
75		75
76	version = INTEL_VGT_IF_VERSION_ENCODE(	76	version = INTEL_VGT_IF_VERSION_ENCODE(
77	readw(dev_priv->regs + vgtif_reg(version_major)),	77	__raw_i915_read16(dev_priv, vgtif_reg(version_major)),
78	readw(dev_priv->regs + vgtif_reg(version_minor)));	78	__raw_i915_read16(dev_priv, vgtif_reg(version_minor)));
79	if (version != INTEL_VGT_IF_VERSION) {	79	if (version != INTEL_VGT_IF_VERSION) {
80	DRM_INFO("VGT interface version mismatch!\n");	80	DRM_INFO("VGT interface version mismatch!\n");
81	return;	81	return;

drivers/gpu/drm/i915/i915_vgpu.h+5−9

 	uint32_t g2v_notify;
 	uint32_t rsv6[7];
-	uint32_t pdp0_lo;
+	struct {
-	uint32_t pdp0_hi;
+		uint32_t lo;
-	uint32_t pdp1_lo;
+		uint32_t hi;
-	uint32_t pdp1_hi;
+	} pdp[4];
-	uint32_t pdp2_lo;
-	uint32_t pdp2_hi;
-	uint32_t pdp3_lo;
-	uint32_t pdp3_hi;
 	uint32_t execlist_context_descriptor_lo;
 	uint32_t execlist_context_descriptor_hi;
 } __packed;
 #define vgtif_reg(x) \
-	(VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)
+	_MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
 /* vGPU display status to be used by the host side */
 #define VGT_DRV_DISPLAY_NOT_READY 0

drivers/gpu/drm/i915/intel_atomic.c+1−2

 	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
 	crtc_state->update_pipe = false;
+	crtc_state->disable_lp_wm = false;
 	return &crtc_state->base;
 }
 				 * but since this plane is unchanged just do the
 				 * minimum required validation.
 				 */
-				if (plane->type == DRM_PLANE_TYPE_PRIMARY)
-					intel_crtc->atomic.wait_for_flips = true;
 				crtc_state->base.planes_changed = true;
 			}

drivers/gpu/drm/i915/intel_atomic_plane.c+2−0

 	state = &intel_state->base;
 	__drm_atomic_helper_plane_duplicate_state(plane, state);
+	intel_state->wait_req = NULL;
 	return state;
 }
 intel_plane_destroy_state(struct drm_plane *plane,
 			  struct drm_plane_state *state)
 {
+	WARN_ON(state && to_intel_plane_state(state)->wait_req);
 	drm_atomic_helper_plane_destroy_state(plane, state);
 }

drivers/gpu/drm/i915/intel_audio.c+65−37

@@ -161,9 +161,9 @@ static bool audio_rate_need_prog(struct intel_crtc *crtc, · 160 unmodified lines
161	}	161	}
162		162
163	static bool intel_eld_uptodate(struct drm_connector *connector,	163	static bool intel_eld_uptodate(struct drm_connector *connector,
164	int reg_eldv, uint32_t bits_eldv,	164	i915_reg_t reg_eldv, uint32_t bits_eldv,
165	int reg_elda, uint32_t bits_elda,	165	i915_reg_t reg_elda, uint32_t bits_elda,
166	int reg_edid)	166	i915_reg_t reg_edid)
167	{	167	{
168	struct drm_i915_private *dev_priv = connector->dev->dev_private;	168	struct drm_i915_private *dev_priv = connector->dev->dev_private;
169	uint8_t *eld = connector->eld;	169	uint8_t *eld = connector->eld;
@@ -364,8 +364,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder) · 194 unmodified lines
364	enum port port = intel_dig_port->port;	364	enum port port = intel_dig_port->port;
365	enum pipe pipe = intel_crtc->pipe;	365	enum pipe pipe = intel_crtc->pipe;
366	uint32_t tmp, eldv;	366	uint32_t tmp, eldv;
367	int aud_config;	367	i915_reg_t aud_config, aud_cntrl_st2;
368	int aud_cntrl_st2;
369		368
370	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",	369	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
371	port_name(port), pipe_name(pipe));	370	port_name(port), pipe_name(pipe));
@@ -416,10 +415,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector, · 44 unmodified lines
416	uint32_t eldv;	415	uint32_t eldv;
417	uint32_t tmp;	416	uint32_t tmp;
418	int len, i;	417	int len, i;
419	int hdmiw_hdmiedid;	418	i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
420	int aud_config;
421	int aud_cntl_st;
422	int aud_cntrl_st2;
423		419
424	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",	420	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
425	port_name(port), pipe_name(pipe), drm_eld_size(eld));	421	port_name(port), pipe_name(pipe), drm_eld_size(eld));
@@ -525,6 +521,10 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder) · 99 unmodified lines
525	dev_priv->display.audio_codec_enable(connector, intel_encoder,	521	dev_priv->display.audio_codec_enable(connector, intel_encoder,
526	adjusted_mode);	522	adjusted_mode);
527		523
		524	mutex_lock(&dev_priv->av_mutex);
		525	intel_dig_port->audio_connector = connector;
		526	mutex_unlock(&dev_priv->av_mutex);
		527
528	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)	528	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
529	acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);	529	acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
530	}	530	}
@@ -548,6 +548,10 @@ void intel_audio_codec_disable(struct intel_encoder *intel_encoder) · 17 unmodified lines
548	if (dev_priv->display.audio_codec_disable)	548	if (dev_priv->display.audio_codec_disable)
549	dev_priv->display.audio_codec_disable(intel_encoder);	549	dev_priv->display.audio_codec_disable(intel_encoder);
550		550
		551	mutex_lock(&dev_priv->av_mutex);
		552	intel_dig_port->audio_connector = NULL;
		553	mutex_unlock(&dev_priv->av_mutex);
		554
551	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)	555	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
552	acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);	556	acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
553	}	557	}
@@ -591,7 +595,7 @@ static void i915_audio_component_codec_wake_override(struct device *dev, · 37 unmodified lines
591	struct drm_i915_private *dev_priv = dev_to_i915(dev);	595	struct drm_i915_private *dev_priv = dev_to_i915(dev);
592	u32 tmp;	596	u32 tmp;
593		597
594	if (!IS_SKYLAKE(dev_priv))	598	if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
595	return;	599	return;
596		600
597	/*	601	/*
@@ -632,44 +636,40 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, · 34 unmodified lines
632	int port, int rate)	636	int port, int rate)
633	{	637	{
634	struct drm_i915_private *dev_priv = dev_to_i915(dev);	638	struct drm_i915_private *dev_priv = dev_to_i915(dev);
635	struct drm_device *drm_dev = dev_priv->dev;
636	struct intel_encoder *intel_encoder;	639	struct intel_encoder *intel_encoder;
637	struct intel_digital_port *intel_dig_port;
638	struct intel_crtc *crtc;	640	struct intel_crtc *crtc;
639	struct drm_display_mode *mode;	641	struct drm_display_mode *mode;
640	struct i915_audio_component *acomp = dev_priv->audio_component;	642	struct i915_audio_component *acomp = dev_priv->audio_component;
641	enum pipe pipe = -1;	643	enum pipe pipe = INVALID_PIPE;
642	u32 tmp;	644	u32 tmp;
643	int n;	645	int n;
		646	int err = 0;
644		647
645	/* HSW, BDW SKL need this fix */	648	/* HSW, BDW, SKL, KBL need this fix */
646	if (!IS_SKYLAKE(dev_priv) &&	649	if (!IS_SKYLAKE(dev_priv) &&
647	!IS_BROADWELL(dev_priv) &&	650	!IS_KABYLAKE(dev_priv) &&
648	!IS_HASWELL(dev_priv))	651	!IS_BROADWELL(dev_priv) &&
		652	!IS_HASWELL(dev_priv))
649	return 0;	653	return 0;
650		654
651	mutex_lock(&dev_priv->av_mutex);	655	mutex_lock(&dev_priv->av_mutex);
652	/* 1. get the pipe */	656	/* 1. get the pipe */
653	for_each_intel_encoder(drm_dev, intel_encoder) {	657	intel_encoder = dev_priv->dig_port_map[port];
654	if (intel_encoder->type != INTEL_OUTPUT_HDMI)	658	/* intel_encoder might be NULL for DP MST */
655	continue;	659	if (!intel_encoder \|\| !intel_encoder->base.crtc \|\|
656	intel_dig_port = enc_to_dig_port(&intel_encoder->base);	660	intel_encoder->type != INTEL_OUTPUT_HDMI) {
657	if (port == intel_dig_port->port) {	661	DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
658	crtc = to_intel_crtc(intel_encoder->base.crtc);	662	err = -ENODEV;
659	if (!crtc) {	663	goto unlock;
660	DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
661	continue;
662	}
663	pipe = crtc->pipe;
664	break;
665	}
666	}	664	}
667		665	crtc = to_intel_crtc(intel_encoder->base.crtc);
		666	pipe = crtc->pipe;
668	if (pipe == INVALID_PIPE) {	667	if (pipe == INVALID_PIPE) {
669	DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));	668	DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
670	mutex_unlock(&dev_priv->av_mutex);	669	err = -ENODEV;
671	return -ENODEV;	670	goto unlock;
672	}	671	}
		672
673	DRM_DEBUG_KMS("pipe %c connects port %c\n",	673	DRM_DEBUG_KMS("pipe %c connects port %c\n",
674	pipe_name(pipe), port_name(port));	674	pipe_name(pipe), port_name(port));
675	mode = &crtc->config->base.adjusted_mode;	675	mode = &crtc->config->base.adjusted_mode;
@@ -682,8 +682,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, · 6 unmodified lines
682	tmp = I915_READ(HSW_AUD_CFG(pipe));	682	tmp = I915_READ(HSW_AUD_CFG(pipe));
683	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;	683	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
684	I915_WRITE(HSW_AUD_CFG(pipe), tmp);	684	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
685	mutex_unlock(&dev_priv->av_mutex);	685	goto unlock;
686	return 0;
687	}	686	}
688		687
689	n = audio_config_get_n(mode, rate);	688	n = audio_config_get_n(mode, rate);
@@ -693,8 +692,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, · 3 unmodified lines
693	tmp = I915_READ(HSW_AUD_CFG(pipe));	692	tmp = I915_READ(HSW_AUD_CFG(pipe));
694	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;	693	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
695	I915_WRITE(HSW_AUD_CFG(pipe), tmp);	694	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
696	mutex_unlock(&dev_priv->av_mutex);	695	goto unlock;
697	return 0;
698	}	696	}
699		697
700	/* 3. set the N/CTS/M */	698	/* 3. set the N/CTS/M */
@@ -702,8 +700,37 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, · 1 unmodified line
702	tmp = audio_config_setup_n_reg(n, tmp);	700	tmp = audio_config_setup_n_reg(n, tmp);
703	I915_WRITE(HSW_AUD_CFG(pipe), tmp);	701	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
704		702
		703	unlock:
705	mutex_unlock(&dev_priv->av_mutex);	704	mutex_unlock(&dev_priv->av_mutex);
706	return 0;	705	return err;
		706	}
		707
		708	static int i915_audio_component_get_eld(struct device *dev, int port,
		709	bool *enabled,
		710	unsigned char *buf, int max_bytes)
		711	{
		712	struct drm_i915_private *dev_priv = dev_to_i915(dev);
		713	struct intel_encoder *intel_encoder;
		714	struct intel_digital_port *intel_dig_port;
		715	const u8 *eld;
		716	int ret = -EINVAL;
		717
		718	mutex_lock(&dev_priv->av_mutex);
		719	intel_encoder = dev_priv->dig_port_map[port];
		720	/* intel_encoder might be NULL for DP MST */
		721	if (intel_encoder) {
		722	ret = 0;
		723	intel_dig_port = enc_to_dig_port(&intel_encoder->base);
		724	*enabled = intel_dig_port->audio_connector != NULL;
		725	if (*enabled) {
		726	eld = intel_dig_port->audio_connector->eld;
		727	ret = drm_eld_size(eld);
		728	memcpy(buf, eld, min(max_bytes, ret));
		729	}
		730	}
		731
		732	mutex_unlock(&dev_priv->av_mutex);
		733	return ret;
707	}	734	}
708		735
709	static const struct i915_audio_component_ops i915_audio_component_ops = {	736	static const struct i915_audio_component_ops i915_audio_component_ops = {
@@ -713,6 +740,7 @@ static const struct i915_audio_component_ops i915_audio_component_ops = { · 3 unmodified lines
713	.codec_wake_override = i915_audio_component_codec_wake_override,	740	.codec_wake_override = i915_audio_component_codec_wake_override,
714	.get_cdclk_freq = i915_audio_component_get_cdclk_freq,	741	.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
715	.sync_audio_rate = i915_audio_component_sync_audio_rate,	742	.sync_audio_rate = i915_audio_component_sync_audio_rate,
		743	.get_eld = i915_audio_component_get_eld,
716	};	744	};
717		745
718	static int i915_audio_component_bind(struct device *i915_dev,	746	static int i915_audio_component_bind(struct device *i915_dev,

drivers/gpu/drm/i915/intel_crt.c+5−9

 	 * encoder's enable/disable callbacks */
 	struct intel_connector *connector;
 	bool force_hotplug_required;
-	u32 adpa_reg;
+	i915_reg_t adpa_reg;
 };
 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
 	uint32_t vsample;
 	uint32_t vblank, vblank_start, vblank_end;
 	uint32_t dsl;
-	uint32_t bclrpat_reg;
+	i915_reg_t bclrpat_reg, vtotal_reg,
-	uint32_t vtotal_reg;
+		vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
-	uint32_t vblank_reg;
-	uint32_t vsync_reg;
-	uint32_t pipeconf_reg;
-	uint32_t pipe_dsl_reg;
 	uint8_t	st00;
 	enum drm_connector_status status;
 		/* Wait for next Vblank to substitue
 		 * border color for Color info */
 		intel_wait_for_vblank(dev, pipe);
-		st00 = I915_READ8(VGA_MSR_WRITE);
+		st00 = I915_READ8(_VGA_MSR_WRITE);
 		status = ((st00 & (1 << 4)) != 0) ?
 			connector_status_connected :
 			connector_status_disconnected;
 		do {
 			count++;
 			/* Read the ST00 VGA status register */
-			st00 = I915_READ8(VGA_MSR_WRITE);
+			st00 = I915_READ8(_VGA_MSR_WRITE);
 			if (st00 & (1 << 4))
 				detect++;
 		} while ((I915_READ(pipe_dsl_reg) == dsl));

drivers/gpu/drm/i915/intel_csr.c+123−161

@@ -47,21 +47,10 @@ · 46 unmodified lines
47	MODULE_FIRMWARE(I915_CSR_SKL);	47	MODULE_FIRMWARE(I915_CSR_SKL);
48	MODULE_FIRMWARE(I915_CSR_BXT);	48	MODULE_FIRMWARE(I915_CSR_BXT);
49		49
50	/*	50	#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
51	* SKL CSR registers for DC5 and DC6	51
52	*/
53	#define CSR_PROGRAM(i) (0x80000 + (i) * 4)
54	#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
55	#define CSR_HTP_ADDR_SKL 0x00500034
56	#define CSR_SSP_BASE 0x8F074
57	#define CSR_HTP_SKL 0x8F004
58	#define CSR_LAST_WRITE 0x8F034
59	#define CSR_LAST_WRITE_VALUE 0xc003b400
60	/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
61	#define CSR_MAX_FW_SIZE 0x2FFF	52	#define CSR_MAX_FW_SIZE 0x2FFF
62	#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF	53	#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
63	#define CSR_MMIO_START_RANGE 0x80000
64	#define CSR_MMIO_END_RANGE 0x8FFFF
65		54
66	struct intel_css_header {	55	struct intel_css_header {
67	/* 0x09 for DMC */	56	/* 0x09 for DMC */
@@ -178,166 +167,134 @@ struct stepping_info { · 110 unmodified lines
178	};	167	};
179		168
180	static const struct stepping_info skl_stepping_info[] = {	169	static const struct stepping_info skl_stepping_info[] = {
181	{'A', '0'}, {'B', '0'}, {'C', '0'},	170	{'A', '0'}, {'B', '0'}, {'C', '0'},
182	{'D', '0'}, {'E', '0'}, {'F', '0'},	171	{'D', '0'}, {'E', '0'}, {'F', '0'},
183	{'G', '0'}, {'H', '0'}, {'I', '0'}	172	{'G', '0'}, {'H', '0'}, {'I', '0'}
184	};	173	};
185		174
186	static struct stepping_info bxt_stepping_info[] = {	175	static const struct stepping_info bxt_stepping_info[] = {
187	{'A', '0'}, {'A', '1'}, {'A', '2'},	176	{'A', '0'}, {'A', '1'}, {'A', '2'},
188	{'B', '0'}, {'B', '1'}, {'B', '2'}	177	{'B', '0'}, {'B', '1'}, {'B', '2'}
189	};	178	};
190		179
191	static char intel_get_stepping(struct drm_device *dev)	180	static const struct stepping_info intel_get_stepping_info(struct drm_device dev)
192	{
193	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
194	ARRAY_SIZE(skl_stepping_info)))
195	return skl_stepping_info[dev->pdev->revision].stepping;
196	else if (IS_BROXTON(dev) && (dev->pdev->revision <
197	ARRAY_SIZE(bxt_stepping_info)))
198	return bxt_stepping_info[dev->pdev->revision].stepping;
199	else
200	return -ENODATA;
201	}
202
203	static char intel_get_substepping(struct drm_device *dev)
204	{	181	{
205	if (IS_SKYLAKE(dev) && (dev->pdev->revision <	182	const struct stepping_info *si;
206	ARRAY_SIZE(skl_stepping_info)))	183	unsigned int size;
207	return skl_stepping_info[dev->pdev->revision].substepping;	184
208	else if (IS_BROXTON(dev) && (dev->pdev->revision <	185	if (IS_SKYLAKE(dev)) {
209	ARRAY_SIZE(bxt_stepping_info)))	186	size = ARRAY_SIZE(skl_stepping_info);
210	return bxt_stepping_info[dev->pdev->revision].substepping;	187	si = skl_stepping_info;
211	else	188	} else if (IS_BROXTON(dev)) {
212	return -ENODATA;	189	size = ARRAY_SIZE(bxt_stepping_info);
213	}	190	si = bxt_stepping_info;
214		191	} else {
215	/**	192	return NULL;
216	* intel_csr_load_status_get() - to get firmware loading status.	193	}
217	* @dev_priv: i915 device.
218	*
219	* This function helps to get the firmware loading status.
220	*
221	* Return: Firmware loading status.
222	*/
223	enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
224	{
225	enum csr_state state;
226		194
227	mutex_lock(&dev_priv->csr_lock);	195	if (INTEL_REVID(dev) < size)
228	state = dev_priv->csr.state;	196	return si + INTEL_REVID(dev);
229	mutex_unlock(&dev_priv->csr_lock);
230		197
231	return state;	198	return NULL;
232	}
233
234	/**
235	* intel_csr_load_status_set() - help to set firmware loading status.
236	* @dev_priv: i915 device.
237	* @state: enumeration of firmware loading status.
238	*
239	* Set the firmware loading status.
240	*/
241	void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
242	enum csr_state state)
243	{
244	mutex_lock(&dev_priv->csr_lock);
245	dev_priv->csr.state = state;
246	mutex_unlock(&dev_priv->csr_lock);
247	}	199	}
248		200
249	/**	201	/**
250	* intel_csr_load_program() - write the firmware from memory to register.	202	* intel_csr_load_program() - write the firmware from memory to register.
251	* @dev: drm device.	203	* @dev_priv: i915 drm device.
252	*	204	*
253	* CSR firmware is read from a .bin file and kept in internal memory one time.	205	* CSR firmware is read from a .bin file and kept in internal memory one time.
254	* Everytime display comes back from low power state this function is called to	206	* Everytime display comes back from low power state this function is called to
255	* copy the firmware from internal memory to registers.	207	* copy the firmware from internal memory to registers.
256	*/	208	*/
257	void intel_csr_load_program(struct drm_device *dev)	209	void intel_csr_load_program(struct drm_i915_private *dev_priv)
258	{	210	{
259	struct drm_i915_private *dev_priv = dev->dev_private;
260	u32 *payload = dev_priv->csr.dmc_payload;	211	u32 *payload = dev_priv->csr.dmc_payload;
261	uint32_t i, fw_size;	212	uint32_t i, fw_size;
262		213
263	if (!IS_GEN9(dev)) {	214	if (!IS_GEN9(dev_priv)) {
264	DRM_ERROR("No CSR support available for this platform\n");	215	DRM_ERROR("No CSR support available for this platform\n");
265	return;	216	return;
266	}	217	}
267		218
268	/*	219	if (!dev_priv->csr.dmc_payload) {
269	* FIXME: Firmware gets lost on S3/S4, but not when entering system	220	DRM_ERROR("Tried to program CSR with empty payload\n");
270	* standby or suspend-to-idle (which is just like forced runtime pm).
271	* Unfortunately the ACPI subsystem doesn't yet give us a way to
272	* differentiate this, hence figure it out with this hack.
273	*/
274	if (I915_READ(CSR_PROGRAM(0)))
275	return;	221	return;
		222	}
276		223
277	mutex_lock(&dev_priv->csr_lock);
278	fw_size = dev_priv->csr.dmc_fw_size;	224	fw_size = dev_priv->csr.dmc_fw_size;
279	for (i = 0; i < fw_size; i++)	225	for (i = 0; i < fw_size; i++)
280	I915_WRITE(CSR_PROGRAM(i), payload[i]);	226	I915_WRITE(CSR_PROGRAM(i), payload[i]);
281		227
282	for (i = 0; i < dev_priv->csr.mmio_count; i++) {	228	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
283	I915_WRITE(dev_priv->csr.mmioaddr[i],	229	I915_WRITE(dev_priv->csr.mmioaddr[i],
284	dev_priv->csr.mmiodata[i]);	230	dev_priv->csr.mmiodata[i]);
285	}	231	}
286
287	dev_priv->csr.state = FW_LOADED;
288	mutex_unlock(&dev_priv->csr_lock);
289	}	232	}
290		233
291	static void finish_csr_load(const struct firmware fw, void context)	234	static uint32_t parse_csr_fw(struct drm_i915_private dev_priv,
		235	const struct firmware *fw)
292	{	236	{
293	struct drm_i915_private *dev_priv = context;
294	struct drm_device *dev = dev_priv->dev;	237	struct drm_device *dev = dev_priv->dev;
295	struct intel_css_header *css_header;	238	struct intel_css_header *css_header;
296	struct intel_package_header *package_header;	239	struct intel_package_header *package_header;
297	struct intel_dmc_header *dmc_header;	240	struct intel_dmc_header *dmc_header;
298	struct intel_csr *csr = &dev_priv->csr;	241	struct intel_csr *csr = &dev_priv->csr;
299	char stepping = intel_get_stepping(dev);	242	const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
300	char substepping = intel_get_substepping(dev);	243	char stepping, substepping;
301	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;	244	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
302	uint32_t i;	245	uint32_t i;
303	uint32_t *dmc_payload;	246	uint32_t *dmc_payload;
304	bool fw_loaded = false;
305		247
306	if (!fw) {	248	if (!fw)
307	i915_firmware_load_error_print(csr->fw_path, 0);	249	return NULL;
308	goto out;
309	}
310		250
311	if ((stepping == -ENODATA) \|\| (substepping == -ENODATA)) {	251	if (!stepping_info) {
312	DRM_ERROR("Unknown stepping info, firmware loading failed\n");	252	DRM_ERROR("Unknown stepping info, firmware loading failed\n");
313	goto out;	253	return NULL;
314	}	254	}
315		255
		256	stepping = stepping_info->stepping;
		257	substepping = stepping_info->substepping;
		258
316	/* Extract CSS Header information*/	259	/* Extract CSS Header information*/
317	css_header = (struct intel_css_header *)fw->data;	260	css_header = (struct intel_css_header *)fw->data;
318	if (sizeof(struct intel_css_header) !=	261	if (sizeof(struct intel_css_header) !=
319	(css_header->header_len * 4)) {	262	(css_header->header_len * 4)) {
320	DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",	263	DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
321	(css_header->header_len * 4));	264	(css_header->header_len * 4));
322	goto out;	265	return NULL;
323	}	266	}
		267
		268	csr->version = css_header->version;
		269
		270	if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
		271	DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
		272	" please upgrade to v%u.%u or later"
		273	" [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
		274	CSR_VERSION_MAJOR(csr->version),
		275	CSR_VERSION_MINOR(csr->version),
		276	CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
		277	CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
		278	return NULL;
		279	}
		280
324	readcount += sizeof(struct intel_css_header);	281	readcount += sizeof(struct intel_css_header);
325		282
326	/* Extract Package Header information*/	283	/* Extract Package Header information*/
327	package_header = (struct intel_package_header *)	284	package_header = (struct intel_package_header *)
328	&fw->data[readcount];	285	&fw->data[readcount];
329	if (sizeof(struct intel_package_header) !=	286	if (sizeof(struct intel_package_header) !=
330	(package_header->header_len * 4)) {	287	(package_header->header_len * 4)) {
331	DRM_ERROR("Firmware has wrong package header length %u bytes\n",	288	DRM_ERROR("Firmware has wrong package header length %u bytes\n",
332	(package_header->header_len * 4));	289	(package_header->header_len * 4));
333	goto out;	290	return NULL;
334	}	291	}
335	readcount += sizeof(struct intel_package_header);	292	readcount += sizeof(struct intel_package_header);
336		293
337	/* Search for dmc_offset to find firware binary. */	294	/* Search for dmc_offset to find firware binary. */
338	for (i = 0; i < package_header->num_entries; i++) {	295	for (i = 0; i < package_header->num_entries; i++) {
339	if (package_header->fw_info[i].substepping == '*' &&	296	if (package_header->fw_info[i].substepping == '*' &&
340	stepping == package_header->fw_info[i].stepping) {	297	stepping == package_header->fw_info[i].stepping) {
341	dmc_offset = package_header->fw_info[i].offset;	298	dmc_offset = package_header->fw_info[i].offset;
342	break;	299	break;
343	} else if (stepping == package_header->fw_info[i].stepping &&	300	} else if (stepping == package_header->fw_info[i].stepping &&
@@ -345,12 +302,12 @@ static void finish_csr_load(const struct firmware fw, void context) · 1 unmodified line
345	dmc_offset = package_header->fw_info[i].offset;	302	dmc_offset = package_header->fw_info[i].offset;
346	break;	303	break;
347	} else if (package_header->fw_info[i].stepping == '*' &&	304	} else if (package_header->fw_info[i].stepping == '*' &&
348	package_header->fw_info[i].substepping == '*')	305	package_header->fw_info[i].substepping == '*')
349	dmc_offset = package_header->fw_info[i].offset;	306	dmc_offset = package_header->fw_info[i].offset;
350	}	307	}
351	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {	308	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
352	DRM_ERROR("Firmware not supported for %c stepping\n", stepping);	309	DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
353	goto out;	310	return NULL;
354	}	311	}
355	readcount += dmc_offset;	312	readcount += dmc_offset;
356		313
@@ -358,26 +315,26 @@ static void finish_csr_load(const struct firmware fw, void context) · 1 unmodified line
358	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];	315	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
359	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {	316	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
360	DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",	317	DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
361	(dmc_header->header_len));	318	(dmc_header->header_len));
362	goto out;	319	return NULL;
363	}	320	}
364	readcount += sizeof(struct intel_dmc_header);	321	readcount += sizeof(struct intel_dmc_header);
365		322
366	/* Cache the dmc header info. */	323	/* Cache the dmc header info. */
367	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {	324	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
368	DRM_ERROR("Firmware has wrong mmio count %u\n",	325	DRM_ERROR("Firmware has wrong mmio count %u\n",
369	dmc_header->mmio_count);	326	dmc_header->mmio_count);
370	goto out;	327	return NULL;
371	}	328	}
372	csr->mmio_count = dmc_header->mmio_count;	329	csr->mmio_count = dmc_header->mmio_count;
373	for (i = 0; i < dmc_header->mmio_count; i++) {	330	for (i = 0; i < dmc_header->mmio_count; i++) {
374	if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE \|\|	331	if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE \|\|
375	dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {	332	dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
376	DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",	333	DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
377	dmc_header->mmioaddr[i]);	334	dmc_header->mmioaddr[i]);
378	goto out;	335	return NULL;
379	}	336	}
380	csr->mmioaddr[i] = dmc_header->mmioaddr[i];	337	csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
381	csr->mmiodata[i] = dmc_header->mmiodata[i];	338	csr->mmiodata[i] = dmc_header->mmiodata[i];
382	}	339	}
383		340
@@ -385,56 +342,80 @@ static void finish_csr_load(const struct firmware fw, void context) · 1 unmodified line
385	nbytes = dmc_header->fw_size * 4;	342	nbytes = dmc_header->fw_size * 4;
386	if (nbytes > CSR_MAX_FW_SIZE) {	343	if (nbytes > CSR_MAX_FW_SIZE) {
387	DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);	344	DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
388	goto out;	345	return NULL;
389	}	346	}
390	csr->dmc_fw_size = dmc_header->fw_size;	347	csr->dmc_fw_size = dmc_header->fw_size;
391		348
392	csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);	349	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
393	if (!csr->dmc_payload) {	350	if (!dmc_payload) {
394	DRM_ERROR("Memory allocation failed for dmc payload\n");	351	DRM_ERROR("Memory allocation failed for dmc payload\n");
395	goto out;	352	return NULL;
396	}	353	}
397		354
398	dmc_payload = csr->dmc_payload;
399	memcpy(dmc_payload, &fw->data[readcount], nbytes);	355	memcpy(dmc_payload, &fw->data[readcount], nbytes);
400		356
		357	return dmc_payload;
		358	}
		359
		360	static void csr_load_work_fn(struct work_struct *work)
		361	{
		362	struct drm_i915_private *dev_priv;
		363	struct intel_csr *csr;
		364	const struct firmware *fw;
		365	int ret;
		366
		367	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
		368	csr = &dev_priv->csr;
		369
		370	ret = request_firmware(&fw, dev_priv->csr.fw_path,
		371	&dev_priv->dev->pdev->dev);
		372	if (!fw)
		373	goto out;
		374
		375	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
		376	if (!dev_priv->csr.dmc_payload)
		377	goto out;
		378
401	/* load csr program during system boot, as needed for DC states */	379	/* load csr program during system boot, as needed for DC states */
402	intel_csr_load_program(dev);	380	intel_csr_load_program(dev_priv);
403	fw_loaded = true;
404		381
405	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
406	out:	382	out:
407	if (fw_loaded)	383	if (dev_priv->csr.dmc_payload) {
408	intel_runtime_pm_put(dev_priv);	384	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
409	else	385
410	intel_csr_load_status_set(dev_priv, FW_FAILED);	386	DRM_INFO("Finished loading %s (v%u.%u)\n",
		387	dev_priv->csr.fw_path,
		388	CSR_VERSION_MAJOR(csr->version),
		389	CSR_VERSION_MINOR(csr->version));
		390	} else {
		391	DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
		392	}
411		393
412	release_firmware(fw);	394	release_firmware(fw);
413	}	395	}
414		396
415	/**	397	/**
416	* intel_csr_ucode_init() - initialize the firmware loading.	398	* intel_csr_ucode_init() - initialize the firmware loading.
417	* @dev: drm device.	399	* @dev_priv: i915 drm device.
418	*	400	*
419	* This function is called at the time of loading the display driver to read	401	* This function is called at the time of loading the display driver to read
420	* firmware from a .bin file and copied into a internal memory.	402	* firmware from a .bin file and copied into a internal memory.
421	*/	403	*/
422	void intel_csr_ucode_init(struct drm_device *dev)	404	void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
423	{	405	{
424	struct drm_i915_private *dev_priv = dev->dev_private;
425	struct intel_csr *csr = &dev_priv->csr;	406	struct intel_csr *csr = &dev_priv->csr;
426	int ret;
427		407
428	if (!HAS_CSR(dev))	408	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
		409
		410	if (!HAS_CSR(dev_priv))
429	return;	411	return;
430		412
431	if (IS_SKYLAKE(dev))	413	if (IS_SKYLAKE(dev_priv))
432	csr->fw_path = I915_CSR_SKL;	414	csr->fw_path = I915_CSR_SKL;
433	else if (IS_BROXTON(dev_priv))	415	else if (IS_BROXTON(dev_priv))
434	csr->fw_path = I915_CSR_BXT;	416	csr->fw_path = I915_CSR_BXT;
435	else {	417	else {
436	DRM_ERROR("Unexpected: no known CSR firmware for platform\n");	418	DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
437	intel_csr_load_status_set(dev_priv, FW_FAILED);
438	return;	419	return;
439	}	420	}
440		421
@@ -444,43 +425,24 @@ void intel_csr_ucode_init(struct drm_device *dev) · 3 unmodified lines
444	* Obtain a runtime pm reference, until CSR is loaded,	425	* Obtain a runtime pm reference, until CSR is loaded,
445	* to avoid entering runtime-suspend.	426	* to avoid entering runtime-suspend.
446	*/	427	*/
447	intel_runtime_pm_get(dev_priv);	428	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
448		429
449	/* CSR supported for platform, load firmware */	430	schedule_work(&dev_priv->csr.work);
450	ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
451	&dev_priv->dev->pdev->dev,
452	GFP_KERNEL, dev_priv,
453	finish_csr_load);
454	if (ret) {
455	i915_firmware_load_error_print(csr->fw_path, ret);
456	intel_csr_load_status_set(dev_priv, FW_FAILED);
457	}
458	}	431	}
459		432
460	/**	433	/**
461	* intel_csr_ucode_fini() - unload the CSR firmware.	434	* intel_csr_ucode_fini() - unload the CSR firmware.
462	* @dev: drm device.	435	* @dev_priv: i915 drm device.
463	*	436	*
464	* Firmmware unloading includes freeing the internal momory and reset the	437	* Firmmware unloading includes freeing the internal momory and reset the
465	* firmware loading status.	438	* firmware loading status.
466	*/	439	*/
467	void intel_csr_ucode_fini(struct drm_device *dev)	440	void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
468	{	441	{
469	struct drm_i915_private *dev_priv = dev->dev_private;	442	if (!HAS_CSR(dev_priv))
470
471	if (!HAS_CSR(dev))
472	return;	443	return;
473		444
474	intel_csr_load_status_set(dev_priv, FW_FAILED);	445	flush_work(&dev_priv->csr.work);
475	kfree(dev_priv->csr.dmc_payload);
476	}
477		446
478	void assert_csr_loaded(struct drm_i915_private *dev_priv)	447	kfree(dev_priv->csr.dmc_payload);
479	{
480	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
481	"CSR is not loaded.\n");
482	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
483	"CSR program storage start is NULL\n");
484	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
485	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
486	}	448	}

drivers/gpu/drm/i915/intel_ddi.c+83−59

 	{ 0x00002016, 0x000000A0, 0x0 },
 	{ 0x00005012, 0x0000009B, 0x0 },
 	{ 0x00007011, 0x00000088, 0x0 },
-	{ 0x00009010, 0x000000C7, 0x0 },
+	{ 0x80009010, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 	{ 0x00002016, 0x0000009B, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
-	{ 0x00007011, 0x000000C7, 0x0 },
+	{ 0x80007011, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 	{ 0x00002016, 0x000000DF, 0x0 },
-	{ 0x00005012, 0x000000C7, 0x0 },
+	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 };
 /* Skylake U */
 	{ 0x0000201B, 0x000000A2, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
 	{ 0x00007011, 0x00000087, 0x0 },
-	{ 0x80009010, 0x000000C7, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80009010, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 	{ 0x0000201B, 0x0000009D, 0x0 },
-	{ 0x00005012, 0x000000C7, 0x0 },
+	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
-	{ 0x00007011, 0x000000C7, 0x0 },
+	{ 0x80007011, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 	{ 0x00002016, 0x00000088, 0x0 },
-	{ 0x00005012, 0x000000C7, 0x0 },
+	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 };
 /* Skylake Y */
 	{ 0x00000018, 0x000000A2, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
 	{ 0x00007011, 0x00000087, 0x0 },
-	{ 0x80009010, 0x000000C7, 0x3 },	/* Uses I_boost level 0x3 */
+	{ 0x80009010, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
 	{ 0x00000018, 0x0000009D, 0x0 },
-	{ 0x00005012, 0x000000C7, 0x0 },
+	{ 0x80005012, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
-	{ 0x00007011, 0x000000C7, 0x0 },
+	{ 0x80007011, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
 	{ 0x00000018, 0x00000088, 0x0 },
-	{ 0x00005012, 0x000000C7, 0x0 },
+	{ 0x80005012, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
 };
 /*
 static bool
 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
 {
-	return intel_dig_port->hdmi.hdmi_reg;
+	return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
 }
 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
 		bxt_ddi_vswing_sequence(dev, hdmi_level, port,
 					INTEL_OUTPUT_HDMI);
 		return;
-	} else if (IS_SKYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		ddi_translations_fdi = NULL;
 		ddi_translations_dp =
 				skl_get_buf_trans_dp(dev, &n_dp_entries);
 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 				    enum port port)
 {
-	uint32_t reg = DDI_BUF_CTL(port);
+	i915_reg_t reg = DDI_BUF_CTL(port);
 	int i;
 	for (i = 0; i < 16; i++) {
 	/* Otherwise a < c && b >= d, do nothing */
 }
-static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
+static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
+				   i915_reg_t reg)
 {
 	int refclk = LC_FREQ;
 	int n, p, r;
 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 			       uint32_t dpll)
 {
-	uint32_t cfgcr1_reg, cfgcr2_reg;
+	i915_reg_t cfgcr1_reg, cfgcr2_reg;
 	uint32_t cfgcr1_val, cfgcr2_val;
 	uint32_t p0, p1, p2, dco_freq;
 		link_clock = 270000;
 		break;
 	case PORT_CLK_SEL_WRPLL1:
-		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
+		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
 		break;
 	case PORT_CLK_SEL_WRPLL2:
-		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
+		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
 		break;
 	case PORT_CLK_SEL_SPLL:
 		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 	if (INTEL_INFO(dev)->gen <= 8)
 		hsw_ddi_clock_get(encoder, pipe_config);
-	else if (IS_SKYLAKE(dev))
+	else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skl_ddi_clock_get(encoder, pipe_config);
 	else if (IS_BROXTON(dev))
 		bxt_ddi_clock_get(encoder, pipe_config);
 	struct intel_encoder *intel_encoder =
 		intel_ddi_get_crtc_new_encoder(crtc_state);
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		return skl_ddi_pll_select(intel_crtc, crtc_state,
 					  intel_encoder);
 	else if (IS_BROXTON(dev))
 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 				       enum transcoder cpu_transcoder)
 {
-	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
+	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 	uint32_t val = I915_READ(reg);
 	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 			iboost = dp_iboost;
 		} else {
 			ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
-			iboost = ddi_translations[port].i_boost;
+			iboost = ddi_translations[level].i_boost;
 		}
 	} else if (type == INTEL_OUTPUT_EDP) {
 		if (dp_iboost) {
 			iboost = dp_iboost;
 		} else {
 			ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
-			iboost = ddi_translations[port].i_boost;
+			iboost = ddi_translations[level].i_boost;
 		}
 	} else if (type == INTEL_OUTPUT_HDMI) {
 		if (hdmi_iboost) {
 			iboost = hdmi_iboost;
 		} else {
 			ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
-			iboost = ddi_translations[port].i_boost;
+			iboost = ddi_translations[level].i_boost;
 		}
 	} else {
 		return;
 	level = translate_signal_level(signal_levels);
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skl_ddi_set_iboost(dev, level, port, encoder->type);
 	else if (IS_BROXTON(dev))
 		bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
 	return DDI_BUF_TRANS_SELECT(level);
 }
-static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *pipe_config)
 {
-	struct drm_encoder *encoder = &intel_encoder->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct drm_device *dev = encoder->dev;
+	enum port port = intel_ddi_get_encoder_port(encoder);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
-	enum port port = intel_ddi_get_encoder_port(intel_encoder);
-	int type = intel_encoder->type;
-	int hdmi_level;
-	if (type == INTEL_OUTPUT_EDP) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-		intel_edp_panel_on(intel_dp);
-	}
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
-		uint32_t dpll = crtc->config->ddi_pll_sel;
+		uint32_t dpll = pipe_config->ddi_pll_sel;
 		uint32_t val;
 		/*
 		 * DPLL0 is used for eDP and is the only "private" DPLL (as
 		 * opposed to shared) on SKL
 		 */
-		if (type == INTEL_OUTPUT_EDP) {
+		if (encoder->type == INTEL_OUTPUT_EDP) {
 			WARN_ON(dpll != SKL_DPLL0);
 			val = I915_READ(DPLL_CTRL1);
 			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
 				 DPLL_CTRL1_SSC(dpll) |
 				 DPLL_CTRL1_LINK_RATE_MASK(dpll));
-			val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
+			val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
 			I915_WRITE(DPLL_CTRL1, val);
 			POSTING_READ(DPLL_CTRL1);
 		I915_WRITE(DPLL_CTRL2, val);
-	} else if (INTEL_INFO(dev)->gen < 9) {
+	} else if (INTEL_INFO(dev_priv)->gen < 9) {
-		WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
+		WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
-		I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
+		I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
 	}
+}
+static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+{
+	struct drm_encoder *encoder = &intel_encoder->base;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
+	enum port port = intel_ddi_get_encoder_port(intel_encoder);
+	int type = intel_encoder->type;
+	int hdmi_level;
+	if (type == INTEL_OUTPUT_EDP) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		intel_edp_panel_on(intel_dp);
+	}
+	intel_ddi_clk_select(intel_encoder, crtc->config);
 	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 		intel_edp_panel_off(intel_dp);
 	}
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
 					DPLL_CTRL2_DDI_CLK_OFF(port)));
 	else if (INTEL_INFO(dev)->gen < 9)
 };
 struct skl_dpll_regs {
-	u32 ctl, cfgcr1, cfgcr2;
+	i915_reg_t ctl, cfgcr1, cfgcr2;
 };
 /* this array is indexed by the *shared* pll id */
 	},
 	{
 		/* DPLL 2 */
-		.ctl = WRPLL_CTL1,
+		.ctl = WRPLL_CTL(0),
 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
 	},
 	{
 		/* DPLL 3 */
-		.ctl = WRPLL_CTL2,
+		.ctl = WRPLL_CTL(1),
 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
 	},
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t val = I915_READ(LCPLL_CTL);
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skl_shared_dplls_init(dev_priv);
 	else if (IS_BROXTON(dev))
 		bxt_shared_dplls_init(dev_priv);
 	else
 		hsw_shared_dplls_init(dev_priv);
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		int cdclk_freq;
 		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 		dev_priv->skl_boot_cdclk = cdclk_freq;
+		if (skl_sanitize_cdclk(dev_priv))
+			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 			DRM_ERROR("LCPLL1 is disabled\n");
-		else
-			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
 	} else if (IS_BROXTON(dev)) {
 		broxton_init_cdclk(dev);
 		broxton_ddi_phy_init(dev);
 	}
 }
-void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
+void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 {
-	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct intel_dp *intel_dp = &intel_dig_port->dp;
+	struct drm_i915_private *dev_priv =
-	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+		to_i915(intel_dig_port->base.base.dev);
 	enum port port = intel_dig_port->port;
 	uint32_t val;
 	bool wait = false;
 	intel_encoder->get_config = intel_ddi_get_config;
 	intel_dig_port->port = port;
+	dev_priv->dig_port_map[port] = intel_encoder;
 	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
 					  (DDI_BUF_PORT_REVERSAL |
 					   DDI_A_4_LANES);
+	/*
+	 * Bspec says that DDI_A_4_LANES is the only supported configuration
+	 * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
+	 * wasn't lit up at boot.  Force this bit on in our internal
+	 * configuration so that we use the proper lane count for our
+	 * calculations.
+	 */
+	if (IS_BROXTON(dev) && port == PORT_A) {
+		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
+			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
+			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
+		}
+	}
 	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 	intel_encoder->cloneable = 0;
 		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
 		 * interrupts to check the external panel connection.
 		 */
-		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
+		if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
-					 && port == PORT_B)
 			dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
 		else
 			dev_priv->hotplug.irq_port[port] = intel_dig_port;

drivers/gpu/drm/i915/intel_display.c+511−287

@@ -1096,7 +1096,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, · 1095 unmodified lines
1096	static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)	1096	static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1097	{	1097	{
1098	struct drm_i915_private *dev_priv = dev->dev_private;	1098	struct drm_i915_private *dev_priv = dev->dev_private;
1099	u32 reg = PIPEDSL(pipe);	1099	i915_reg_t reg = PIPEDSL(pipe);
1100	u32 line1, line2;	1100	u32 line1, line2;
1101	u32 line_mask;	1101	u32 line_mask;
1102		1102
@@ -1136,7 +1136,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) · 33 unmodified lines
1136	enum pipe pipe = crtc->pipe;	1136	enum pipe pipe = crtc->pipe;
1137		1137
1138	if (INTEL_INFO(dev)->gen >= 4) {	1138	if (INTEL_INFO(dev)->gen >= 4) {
1139	int reg = PIPECONF(cpu_transcoder);	1139	i915_reg_t reg = PIPECONF(cpu_transcoder);
1140		1140
1141	/* Wait for the Pipe State to go off */	1141	/* Wait for the Pipe State to go off */
1142	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,	1142	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
@@ -1286,7 +1286,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, · 143 unmodified lines
1286	enum pipe pipe)	1286	enum pipe pipe)
1287	{	1287	{
1288	struct drm_device *dev = dev_priv->dev;	1288	struct drm_device *dev = dev_priv->dev;
1289	int pp_reg;	1289	i915_reg_t pp_reg;
1290	u32 val;	1290	u32 val;
1291	enum pipe panel_pipe = PIPE_A;	1291	enum pipe panel_pipe = PIPE_A;
1292	bool locked = true;	1292	bool locked = true;
@@ -1481,8 +1481,7 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, · 188 unmodified lines
1481	return false;	1481	return false;
1482		1482
1483	if (HAS_PCH_CPT(dev_priv->dev)) {	1483	if (HAS_PCH_CPT(dev_priv->dev)) {
1484	u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);	1484	u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1485	u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1486	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)	1485	if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487	return false;	1486	return false;
1488	} else if (IS_CHERRYVIEW(dev_priv->dev)) {	1487	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
@@ -1546,12 +1545,13 @@ static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, · 57 unmodified lines
1546	}	1545	}
1547		1546
1548	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,	1547	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549	enum pipe pipe, int reg, u32 port_sel)	1548	enum pipe pipe, i915_reg_t reg,
		1549	u32 port_sel)
1550	{	1550	{
1551	u32 val = I915_READ(reg);	1551	u32 val = I915_READ(reg);
1552	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),	1552	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1553	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",	1553	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1554	reg, pipe_name(pipe));	1554	i915_mmio_reg_offset(reg), pipe_name(pipe));
1555		1555
1556	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0	1556	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1557	&& (val & DP_PIPEB_SELECT),	1557	&& (val & DP_PIPEB_SELECT),
@@ -1559,12 +1559,12 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, · 1 unmodified line
1559	}	1559	}
1560		1560
1561	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,	1561	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1562	enum pipe pipe, int reg)	1562	enum pipe pipe, i915_reg_t reg)
1563	{	1563	{
1564	u32 val = I915_READ(reg);	1564	u32 val = I915_READ(reg);
1565	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),	1565	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1566	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",	1566	"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1567	reg, pipe_name(pipe));	1567	i915_mmio_reg_offset(reg), pipe_name(pipe));
1568		1568
1569	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0	1569	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1570	&& (val & SDVO_PIPE_B_SELECT),	1570	&& (val & SDVO_PIPE_B_SELECT),
@@ -1600,7 +1600,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc, · 29 unmodified lines
1600	{	1600	{
1601	struct drm_device *dev = crtc->base.dev;	1601	struct drm_device *dev = crtc->base.dev;
1602	struct drm_i915_private *dev_priv = dev->dev_private;	1602	struct drm_i915_private *dev_priv = dev->dev_private;
1603	int reg = DPLL(crtc->pipe);	1603	i915_reg_t reg = DPLL(crtc->pipe);
1604	u32 dpll = pipe_config->dpll_hw_state.dpll;	1604	u32 dpll = pipe_config->dpll_hw_state.dpll;
1605		1605
1606	assert_pipe_disabled(dev_priv, crtc->pipe);	1606	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1689,7 +1689,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) · 82 unmodified lines
1689	{	1689	{
1690	struct drm_device *dev = crtc->base.dev;	1690	struct drm_device *dev = crtc->base.dev;
1691	struct drm_i915_private *dev_priv = dev->dev_private;	1691	struct drm_i915_private *dev_priv = dev->dev_private;
1692	int reg = DPLL(crtc->pipe);	1692	i915_reg_t reg = DPLL(crtc->pipe);
1693	u32 dpll = crtc->config->dpll_hw_state.dpll;	1693	u32 dpll = crtc->config->dpll_hw_state.dpll;
1694		1694
1695	assert_pipe_disabled(dev_priv, crtc->pipe);	1695	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1838,7 +1838,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, · 142 unmodified lines
1838	unsigned int expected_mask)	1838	unsigned int expected_mask)
1839	{	1839	{
1840	u32 port_mask;	1840	u32 port_mask;
1841	int dpll_reg;	1841	i915_reg_t dpll_reg;
1842		1842
1843	switch (dport->port) {	1843	switch (dport->port) {
1844	case PORT_B:	1844	case PORT_B:
@@ -1963,7 +1963,8 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, · 118 unmodified lines
1963	struct drm_device *dev = dev_priv->dev;	1963	struct drm_device *dev = dev_priv->dev;
1964	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];	1964	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1965	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	1965	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966	uint32_t reg, val, pipeconf_val;	1966	i915_reg_t reg;
		1967	uint32_t val, pipeconf_val;
1967		1968
1968	/* PCH only available on ILK+ */	1969	/* PCH only available on ILK+ */
1969	BUG_ON(!HAS_PCH_SPLIT(dev));	1970	BUG_ON(!HAS_PCH_SPLIT(dev));
@@ -2052,7 +2053,8 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, · 82 unmodified lines
2052	enum pipe pipe)	2053	enum pipe pipe)
2053	{	2054	{
2054	struct drm_device *dev = dev_priv->dev;	2055	struct drm_device *dev = dev_priv->dev;
2055	uint32_t reg, val;	2056	i915_reg_t reg;
		2057	uint32_t val;
2056		2058
2057	/* FDI relies on the transcoder */	2059	/* FDI relies on the transcoder */
2058	assert_fdi_tx_disabled(dev_priv, pipe);	2060	assert_fdi_tx_disabled(dev_priv, pipe);
@@ -2069,7 +2071,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, · 10 unmodified lines
2069	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))	2071	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2070	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));	2072	DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2071		2073
2072	if (!HAS_PCH_IBX(dev)) {	2074	if (HAS_PCH_CPT(dev)) {
2073	/* Workaround: Clear the timing override chicken bit again. */	2075	/* Workaround: Clear the timing override chicken bit again. */
2074	reg = TRANS_CHICKEN2(pipe);	2076	reg = TRANS_CHICKEN2(pipe);
2075	val = I915_READ(reg);	2077	val = I915_READ(reg);
@@ -2107,10 +2109,9 @@ static void intel_enable_pipe(struct intel_crtc *crtc) · 31 unmodified lines
2107	struct drm_device *dev = crtc->base.dev;	2109	struct drm_device *dev = crtc->base.dev;
2108	struct drm_i915_private *dev_priv = dev->dev_private;	2110	struct drm_i915_private *dev_priv = dev->dev_private;
2109	enum pipe pipe = crtc->pipe;	2111	enum pipe pipe = crtc->pipe;
2110	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,	2112	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2111	pipe);
2112	enum pipe pch_transcoder;	2113	enum pipe pch_transcoder;
2113	int reg;	2114	i915_reg_t reg;
2114	u32 val;	2115	u32 val;
2115		2116
2116	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));	2117	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
@@ -2171,7 +2172,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) · 54 unmodified lines
2171	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;	2172	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;	2173	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173	enum pipe pipe = crtc->pipe;	2174	enum pipe pipe = crtc->pipe;
2174	int reg;	2175	i915_reg_t reg;
2175	u32 val;	2176	u32 val;
2176		2177
2177	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));	2178	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
@@ -2270,20 +2271,20 @@ intel_fb_align_height(struct drm_device *dev, unsigned int height, · 92 unmodified lines
2270	fb_format_modifier, 0));	2271	fb_format_modifier, 0));
2271	}	2272	}
2272		2273
2273	static int	2274	static void
2274	intel_fill_fb_ggtt_view(struct i915_ggtt_view view, struct drm_framebuffer fb,	2275	intel_fill_fb_ggtt_view(struct i915_ggtt_view view, struct drm_framebuffer fb,
2275	const struct drm_plane_state *plane_state)	2276	const struct drm_plane_state *plane_state)
2276	{	2277	{
2277	struct intel_rotation_info *info = &view->rotation_info;	2278	struct intel_rotation_info *info = &view->params.rotation_info;
2278	unsigned int tile_height, tile_pitch;	2279	unsigned int tile_height, tile_pitch;
2279		2280
2280	*view = i915_ggtt_view_normal;	2281	*view = i915_ggtt_view_normal;
2281		2282
2282	if (!plane_state)	2283	if (!plane_state)
2283	return 0;	2284	return;
2284		2285
2285	if (!intel_rotation_90_or_270(plane_state->rotation))	2286	if (!intel_rotation_90_or_270(plane_state->rotation))
2286	return 0;	2287	return;
2287		2288
2288	*view = i915_ggtt_view_rotated;	2289	*view = i915_ggtt_view_rotated;
2289		2290
@@ -2310,8 +2311,6 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view view, struct drm_framebuffer fb, · 20 unmodified lines
2310	info->size_uv = info->width_pages_uv * info->height_pages_uv *	2311	info->size_uv = info->width_pages_uv * info->height_pages_uv *
2311	PAGE_SIZE;	2312	PAGE_SIZE;
2312	}	2313	}
2313
2314	return 0;
2315	}	2314	}
2316		2315
2317	static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)	2316	static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
@@ -2330,9 +2329,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) · 12 unmodified lines
2330	int	2329	int
2331	intel_pin_and_fence_fb_obj(struct drm_plane *plane,	2330	intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332	struct drm_framebuffer *fb,	2331	struct drm_framebuffer *fb,
2333	const struct drm_plane_state *plane_state,	2332	const struct drm_plane_state *plane_state)
2334	struct intel_engine_cs *pipelined,
2335	struct drm_i915_gem_request **pipelined_request)
2336	{	2333	{
2337	struct drm_device *dev = fb->dev;	2334	struct drm_device *dev = fb->dev;
2338	struct drm_i915_private *dev_priv = dev->dev_private;	2335	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2367,9 +2364,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, · 28 unmodified lines
2367	return -EINVAL;	2364	return -EINVAL;
2368	}	2365	}
2369		2366
2370	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);	2367	intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371	if (ret)
2372	return ret;
2373		2368
2374	/* Note that the w/a also requires 64 PTE of padding following the	2369	/* Note that the w/a also requires 64 PTE of padding following the
2375	* bo. We currently fill all unused PTE with the shadow page and so	2370	* bo. We currently fill all unused PTE with the shadow page and so
@@ -2388,11 +2383,10 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, · 12 unmodified lines
2388	*/	2383	*/
2389	intel_runtime_pm_get(dev_priv);	2384	intel_runtime_pm_get(dev_priv);
2390		2385
2391	dev_priv->mm.interruptible = false;	2386	ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2392	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,	2387	&view);
2393	pipelined_request, &view);
2394	if (ret)	2388	if (ret)
2395	goto err_interruptible;	2389	goto err_pm;
2396		2390
2397	/* Install a fence for tiled scan-out. Pre-i965 always needs a	2391	/* Install a fence for tiled scan-out. Pre-i965 always needs a
2398	* fence, whereas 965+ only requires a fence if using	2392	* fence, whereas 965+ only requires a fence if using
@@ -2418,14 +2412,12 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, · 19 unmodified lines
2418	i915_gem_object_pin_fence(obj);	2412	i915_gem_object_pin_fence(obj);
2419	}	2413	}
2420		2414
2421	dev_priv->mm.interruptible = true;
2422	intel_runtime_pm_put(dev_priv);	2415	intel_runtime_pm_put(dev_priv);
2423	return 0;	2416	return 0;
2424		2417
2425	err_unpin:	2418	err_unpin:
2426	i915_gem_object_unpin_from_display_plane(obj, &view);	2419	i915_gem_object_unpin_from_display_plane(obj, &view);
2427	err_interruptible:	2420	err_pm:
2428	dev_priv->mm.interruptible = true;
2429	intel_runtime_pm_put(dev_priv);	2421	intel_runtime_pm_put(dev_priv);
2430	return ret;	2422	return ret;
2431	}	2423	}
@@ -2435,12 +2427,10 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, · 3 unmodified lines
2435	{	2427	{
2436	struct drm_i915_gem_object *obj = intel_fb_obj(fb);	2428	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437	struct i915_ggtt_view view;	2429	struct i915_ggtt_view view;
2438	int ret;
2439		2430
2440	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));	2431	WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441		2432
2442	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);	2433	intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443	WARN_ONCE(ret, "Couldn't get view from plane state!");
2444		2434
2445	if (view.type == I915_GGTT_VIEW_NORMAL)	2435	if (view.type == I915_GGTT_VIEW_NORMAL)
2446	i915_gem_object_unpin_fence(obj);	2436	i915_gem_object_unpin_fence(obj);
@@ -2695,7 +2685,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, · 248 unmodified lines
2695	int plane = intel_crtc->plane;	2685	int plane = intel_crtc->plane;
2696	unsigned long linear_offset;	2686	unsigned long linear_offset;
2697	u32 dspcntr;	2687	u32 dspcntr;
2698	u32 reg = DSPCNTR(plane);	2688	i915_reg_t reg = DSPCNTR(plane);
2699	int pixel_size;	2689	int pixel_size;
2700		2690
2701	if (!visible \|\| !fb) {	2691	if (!visible \|\| !fb) {
@@ -2825,7 +2815,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, · 123 unmodified lines
2825	int plane = intel_crtc->plane;	2815	int plane = intel_crtc->plane;
2826	unsigned long linear_offset;	2816	unsigned long linear_offset;
2827	u32 dspcntr;	2817	u32 dspcntr;
2828	u32 reg = DSPCNTR(plane);	2818	i915_reg_t reg = DSPCNTR(plane);
2829	int pixel_size;	2819	int pixel_size;
2830		2820
2831	if (!visible \|\| !fb) {	2821	if (!visible \|\| !fb) {
@@ -2950,30 +2940,32 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, · 118 unmodified lines
2950	}	2940	}
2951	}	2941	}
2952		2942
2953	unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,	2943	u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2954	struct drm_i915_gem_object *obj,	2944	struct drm_i915_gem_object *obj,
2955	unsigned int plane)	2945	unsigned int plane)
2956	{	2946	{
2957	const struct i915_ggtt_view *view = &i915_ggtt_view_normal;	2947	struct i915_ggtt_view view;
2958	struct i915_vma *vma;	2948	struct i915_vma *vma;
2959	unsigned char *offset;	2949	u64 offset;
2960		2950
2961	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))	2951	intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2962	view = &i915_ggtt_view_rotated;	2952	intel_plane->base.state);
2963		2953
2964	vma = i915_gem_obj_to_ggtt_view(obj, view);	2954	vma = i915_gem_obj_to_ggtt_view(obj, &view);
2965	if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",	2955	if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2966	view->type))	2956	view.type))
2967	return -1;	2957	return -1;
2968		2958
2969	offset = (unsigned char *)vma->node.start;	2959	offset = vma->node.start;
2970		2960
2971	if (plane == 1) {	2961	if (plane == 1) {
2972	offset += vma->ggtt_view.rotation_info.uv_start_page *	2962	offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2973	PAGE_SIZE;	2963	PAGE_SIZE;
2974	}	2964	}
2975		2965
2976	return (unsigned long)offset;	2966	WARN_ON(upper_32_bits(offset));
		2967
		2968	return lower_32_bits(offset);
2977	}	2969	}
2978		2970
2979	static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)	2971	static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
@@ -3099,7 +3091,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, · 119 unmodified lines
3099	u32 tile_height, plane_offset, plane_size;	3091	u32 tile_height, plane_offset, plane_size;
3100	unsigned int rotation;	3092	unsigned int rotation;
3101	int x_offset, y_offset;	3093	int x_offset, y_offset;
3102	unsigned long surf_addr;	3094	u32 surf_addr;
3103	struct intel_crtc_state *crtc_state = intel_crtc->config;	3095	struct intel_crtc_state *crtc_state = intel_crtc->config;
3104	struct intel_plane_state *plane_state;	3096	struct intel_plane_state *plane_state;
3105	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;	3097	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
@@ -3227,10 +3219,9 @@ static void intel_update_primary_planes(struct drm_device *dev) · 121 unmodified lines
3227	struct intel_plane_state *plane_state;	3219	struct intel_plane_state *plane_state;
3228		3220
3229	drm_modeset_lock_crtc(crtc, &plane->base);	3221	drm_modeset_lock_crtc(crtc, &plane->base);
3230
3231	plane_state = to_intel_plane_state(plane->base.state);	3222	plane_state = to_intel_plane_state(plane->base.state);
3232		3223
3233	if (plane_state->base.fb)	3224	if (crtc->state->active && plane_state->base.fb)
3234	plane->commit_plane(&plane->base, plane_state);	3225	plane->commit_plane(&plane->base, plane_state);
3235		3226
3236	drm_modeset_unlock_crtc(crtc);	3227	drm_modeset_unlock_crtc(crtc);
@@ -3306,32 +3297,6 @@ void intel_finish_reset(struct drm_device *dev) · 69 unmodified lines
3306	drm_modeset_unlock_all(dev);	3297	drm_modeset_unlock_all(dev);
3307	}	3298	}
3308		3299
3309	static void
3310	intel_finish_fb(struct drm_framebuffer *old_fb)
3311	{
3312	struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3313	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3314	bool was_interruptible = dev_priv->mm.interruptible;
3315	int ret;
3316
3317	/* Big Hammer, we also need to ensure that any pending
3318	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
3319	* current scanout is retired before unpinning the old
3320	* framebuffer. Note that we rely on userspace rendering
3321	* into the buffer attached to the pipe they are waiting
3322	* on. If not, userspace generates a GPU hang with IPEHR
3323	* point to the MI_WAIT_FOR_EVENT.
3324	*
3325	* This should only fail upon a hung GPU, in which case we
3326	* can safely continue.
3327	*/
3328	dev_priv->mm.interruptible = false;
3329	ret = i915_gem_object_wait_rendering(obj, true);
3330	dev_priv->mm.interruptible = was_interruptible;
3331
3332	WARN_ON(ret);
3333	}
3334
3335	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)	3300	static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3336	{	3301	{
3337	struct drm_device *dev = crtc->dev;	3302	struct drm_device *dev = crtc->dev;
@@ -3401,7 +3366,8 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) · 63 unmodified lines
3401	struct drm_i915_private *dev_priv = dev->dev_private;	3366	struct drm_i915_private *dev_priv = dev->dev_private;
3402	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3367	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3403	int pipe = intel_crtc->pipe;	3368	int pipe = intel_crtc->pipe;
3404	u32 reg, temp;	3369	i915_reg_t reg;
		3370	u32 temp;
3405		3371
3406	/* enable normal train */	3372	/* enable normal train */
3407	reg = FDI_TX_CTL(pipe);	3373	reg = FDI_TX_CTL(pipe);
@@ -3443,7 +3409,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) · 35 unmodified lines
3443	struct drm_i915_private *dev_priv = dev->dev_private;	3409	struct drm_i915_private *dev_priv = dev->dev_private;
3444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3410	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445	int pipe = intel_crtc->pipe;	3411	int pipe = intel_crtc->pipe;
3446	u32 reg, temp, tries;	3412	i915_reg_t reg;
		3413	u32 temp, tries;
3447		3414
3448	/* FDI needs bits from pipe first */	3415	/* FDI needs bits from pipe first */
3449	assert_pipe_enabled(dev_priv, pipe);	3416	assert_pipe_enabled(dev_priv, pipe);
@@ -3543,7 +3510,8 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) · 93 unmodified lines
3543	struct drm_i915_private *dev_priv = dev->dev_private;	3510	struct drm_i915_private *dev_priv = dev->dev_private;
3544	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3511	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3545	int pipe = intel_crtc->pipe;	3512	int pipe = intel_crtc->pipe;
3546	u32 reg, temp, i, retry;	3513	i915_reg_t reg;
		3514	u32 temp, i, retry;
3547		3515
3548	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit	3516	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3549	for train result */	3517	for train result */
@@ -3675,7 +3643,8 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) · 125 unmodified lines
3675	struct drm_i915_private *dev_priv = dev->dev_private;	3643	struct drm_i915_private *dev_priv = dev->dev_private;
3676	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3644	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677	int pipe = intel_crtc->pipe;	3645	int pipe = intel_crtc->pipe;
3678	u32 reg, temp, i, j;	3646	i915_reg_t reg;
		3647	u32 temp, i, j;
3679		3648
3680	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit	3649	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3681	for train result */	3650	for train result */
@@ -3792,8 +3761,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) · 110 unmodified lines
3792	struct drm_device *dev = intel_crtc->base.dev;	3761	struct drm_device *dev = intel_crtc->base.dev;
3793	struct drm_i915_private *dev_priv = dev->dev_private;	3762	struct drm_i915_private *dev_priv = dev->dev_private;
3794	int pipe = intel_crtc->pipe;	3763	int pipe = intel_crtc->pipe;
3795	u32 reg, temp;	3764	i915_reg_t reg;
3796		3765	u32 temp;
3797		3766
3798	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */	3767	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3799	reg = FDI_RX_CTL(pipe);	3768	reg = FDI_RX_CTL(pipe);
@@ -3829,7 +3798,8 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) · 29 unmodified lines
3829	struct drm_device *dev = intel_crtc->base.dev;	3798	struct drm_device *dev = intel_crtc->base.dev;
3830	struct drm_i915_private *dev_priv = dev->dev_private;	3799	struct drm_i915_private *dev_priv = dev->dev_private;
3831	int pipe = intel_crtc->pipe;	3800	int pipe = intel_crtc->pipe;
3832	u32 reg, temp;	3801	i915_reg_t reg;
		3802	u32 temp;
3833		3803
3834	/* Switch from PCDclk to Rawclk */	3804	/* Switch from PCDclk to Rawclk */
3835	reg = FDI_RX_CTL(pipe);	3805	reg = FDI_RX_CTL(pipe);
@@ -3859,7 +3829,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) · 23 unmodified lines
3859	struct drm_i915_private *dev_priv = dev->dev_private;	3829	struct drm_i915_private *dev_priv = dev->dev_private;
3860	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3830	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3861	int pipe = intel_crtc->pipe;	3831	int pipe = intel_crtc->pipe;
3862	u32 reg, temp;	3832	i915_reg_t reg;
		3833	u32 temp;
3863		3834
3864	/* disable CPU FDI tx and PCH FDI rx */	3835	/* disable CPU FDI tx and PCH FDI rx */
3865	reg = FDI_TX_CTL(pipe);	3836	reg = FDI_TX_CTL(pipe);
@@ -3952,15 +3923,23 @@ static void page_flip_completed(struct intel_crtc *intel_crtc) · 86 unmodified lines
3952	work->pending_flip_obj);	3923	work->pending_flip_obj);
3953	}	3924	}
3954		3925
3955	void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)	3926	static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3956	{	3927	{
3957	struct drm_device *dev = crtc->dev;	3928	struct drm_device *dev = crtc->dev;
3958	struct drm_i915_private *dev_priv = dev->dev_private;	3929	struct drm_i915_private *dev_priv = dev->dev_private;
		3930	long ret;
3959		3931
3960	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));	3932	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3961	if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,	3933
3962	!intel_crtc_has_pending_flip(crtc),	3934	ret = wait_event_interruptible_timeout(
3963	60*HZ) == 0)) {	3935	dev_priv->pending_flip_queue,
		3936	!intel_crtc_has_pending_flip(crtc),
		3937	60*HZ);
		3938
		3939	if (ret < 0)
		3940	return ret;
		3941
		3942	if (ret == 0) {
3964	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3943	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3965		3944
3966	spin_lock_irq(&dev->event_lock);	3945	spin_lock_irq(&dev->event_lock);
@@ -3971,11 +3950,7 @@ void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) · 4 unmodified lines
3971	spin_unlock_irq(&dev->event_lock);	3950	spin_unlock_irq(&dev->event_lock);
3972	}	3951	}
3973		3952
3974	if (crtc->primary->fb) {	3953	return 0;
3975	mutex_lock(&dev->struct_mutex);
3976	intel_finish_fb(crtc->primary->fb);
3977	mutex_unlock(&dev->struct_mutex);
3978	}
3979	}	3954	}
3980		3955
3981	/* Program iCLKIP clock to the desired frequency */	3956	/* Program iCLKIP clock to the desired frequency */
@@ -4135,6 +4110,22 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) · 153 unmodified lines
4135	}	4110	}
4136	}	4111	}
4137		4112
		4113	/* Return which DP Port should be selected for Transcoder DP control */
		4114	static enum port
		4115	intel_trans_dp_port_sel(struct drm_crtc *crtc)
		4116	{
		4117	struct drm_device *dev = crtc->dev;
		4118	struct intel_encoder *encoder;
		4119
		4120	for_each_encoder_on_crtc(dev, crtc, encoder) {
		4121	if (encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
		4122	encoder->type == INTEL_OUTPUT_EDP)
		4123	return enc_to_dig_port(&encoder->base)->port;
		4124	}
		4125
		4126	return -1;
		4127	}
		4128
4138	/*	4129	/*
4139	* Enable PCH resources required for PCH ports:	4130	* Enable PCH resources required for PCH ports:
4140	* - PCH PLLs	4131	* - PCH PLLs
@@ -4149,7 +4140,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) · 8 unmodified lines
4149	struct drm_i915_private *dev_priv = dev->dev_private;	4140	struct drm_i915_private *dev_priv = dev->dev_private;
4150	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	4141	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151	int pipe = intel_crtc->pipe;	4142	int pipe = intel_crtc->pipe;
4152	u32 reg, temp;	4143	u32 temp;
4153		4144
4154	assert_pch_transcoder_disabled(dev_priv, pipe);	4145	assert_pch_transcoder_disabled(dev_priv, pipe);
4155		4146
@@ -4196,8 +4187,10 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) · 40 unmodified lines
4196		4187
4197	/* For PCH DP, enable TRANS_DP_CTL */	4188	/* For PCH DP, enable TRANS_DP_CTL */
4198	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {	4189	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
		4190	const struct drm_display_mode *adjusted_mode =
		4191	&intel_crtc->config->base.adjusted_mode;
4199	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;	4192	u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4200	reg = TRANS_DP_CTL(pipe);	4193	i915_reg_t reg = TRANS_DP_CTL(pipe);
4201	temp = I915_READ(reg);	4194	temp = I915_READ(reg);
4202	temp &= ~(TRANS_DP_PORT_SEL_MASK \|	4195	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
4203	TRANS_DP_SYNC_MASK \|	4196	TRANS_DP_SYNC_MASK \|
@@ -4205,19 +4198,19 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) · 1 unmodified line
4205	temp \|= TRANS_DP_OUTPUT_ENABLE;	4198	temp \|= TRANS_DP_OUTPUT_ENABLE;
4206	temp \|= bpc << 9; /* same format but at 11:9 */	4199	temp \|= bpc << 9; /* same format but at 11:9 */
4207		4200
4208	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)	4201	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4209	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;	4202	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
4210	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)	4203	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4211	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;	4204	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
4212		4205
4213	switch (intel_trans_dp_port_sel(crtc)) {	4206	switch (intel_trans_dp_port_sel(crtc)) {
4214	case PCH_DP_B:	4207	case PORT_B:
4215	temp \|= TRANS_DP_PORT_SEL_B;	4208	temp \|= TRANS_DP_PORT_SEL_B;
4216	break;	4209	break;
4217	case PCH_DP_C:	4210	case PORT_C:
4218	temp \|= TRANS_DP_PORT_SEL_C;	4211	temp \|= TRANS_DP_PORT_SEL_C;
4219	break;	4212	break;
4220	case PCH_DP_D:	4213	case PORT_D:
4221	temp \|= TRANS_DP_PORT_SEL_D;	4214	temp \|= TRANS_DP_PORT_SEL_D;
4222	break;	4215	break;
4223	default:	4216	default:
@@ -4357,7 +4350,7 @@ static void intel_shared_dpll_commit(struct drm_atomic_state *state) · 133 unmodified lines
4357	static void cpt_verify_modeset(struct drm_device *dev, int pipe)	4350	static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4358	{	4351	{
4359	struct drm_i915_private *dev_priv = dev->dev_private;	4352	struct drm_i915_private *dev_priv = dev->dev_private;
4360	int dslreg = PIPEDSL(pipe);	4353	i915_reg_t dslreg = PIPEDSL(pipe);
4361	u32 temp;	4354	u32 temp;
4362		4355
4363	temp = I915_READ(dslreg);	4356	temp = I915_READ(dslreg);
@@ -4667,7 +4660,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) · 303 unmodified lines
4667	}	4660	}
4668		4661
4669	for (i = 0; i < 256; i++) {	4662	for (i = 0; i < 256; i++) {
4670	u32 palreg;	4663	i915_reg_t palreg;
4671		4664
4672	if (HAS_GMCH_DISPLAY(dev))	4665	if (HAS_GMCH_DISPLAY(dev))
4673	palreg = PALETTE(pipe, i);	4666	palreg = PALETTE(pipe, i);
@@ -4746,9 +4739,9 @@ intel_post_enable_primary(struct drm_crtc *crtc) · 72 unmodified lines
4746	if (IS_GEN2(dev))	4739	if (IS_GEN2(dev))
4747	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);	4740	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4748		4741
4749	/* Underruns don't raise interrupts, so check manually. */	4742	/* Underruns don't always raise interrupts, so check manually. */
4750	if (HAS_GMCH_DISPLAY(dev))	4743	intel_check_cpu_fifo_underruns(dev_priv);
4751	i9xx_check_fifo_underruns(dev_priv);	4744	intel_check_pch_fifo_underruns(dev_priv);
4752	}	4745	}
4753		4746
4754	/**	4747	/**
@@ -4807,7 +4800,6 @@ static void intel_post_plane_update(struct intel_crtc *crtc) · 52 unmodified lines
4807	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;	4800	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4808	struct drm_device *dev = crtc->base.dev;	4801	struct drm_device *dev = crtc->base.dev;
4809	struct drm_i915_private *dev_priv = dev->dev_private;	4802	struct drm_i915_private *dev_priv = dev->dev_private;
4810	struct drm_plane *plane;
4811		4803
4812	if (atomic->wait_vblank)	4804	if (atomic->wait_vblank)
4813	intel_wait_for_vblank(dev, crtc->pipe);	4805	intel_wait_for_vblank(dev, crtc->pipe);
@@ -4826,10 +4818,6 @@ static void intel_post_plane_update(struct intel_crtc *crtc) · 12 unmodified lines
4826	if (atomic->post_enable_primary)	4818	if (atomic->post_enable_primary)
4827	intel_post_enable_primary(&crtc->base);	4819	intel_post_enable_primary(&crtc->base);
4828		4820
4829	drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4830	intel_update_sprite_watermarks(plane, &crtc->base,
4831	0, 0, 0, false, false);
4832
4833	memset(atomic, 0, sizeof(*atomic));	4821	memset(atomic, 0, sizeof(*atomic));
4834	}	4822	}
4835		4823
@@ -4838,20 +4826,6 @@ static void intel_pre_plane_update(struct intel_crtc *crtc) · 2 unmodified lines
4838	struct drm_device *dev = crtc->base.dev;	4826	struct drm_device *dev = crtc->base.dev;
4839	struct drm_i915_private *dev_priv = dev->dev_private;	4827	struct drm_i915_private *dev_priv = dev->dev_private;
4840	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;	4828	struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4841	struct drm_plane *p;
4842
4843	/* Track fb's for any planes being disabled */
4844	drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4845	struct intel_plane *plane = to_intel_plane(p);
4846
4847	mutex_lock(&dev->struct_mutex);
4848	i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4849	plane->frontbuffer_bit);
4850	mutex_unlock(&dev->struct_mutex);
4851	}
4852
4853	if (atomic->wait_for_flips)
4854	intel_crtc_wait_for_pending_flips(&crtc->base);
4855		4829
4856	if (atomic->disable_fbc)	4830	if (atomic->disable_fbc)
4857	intel_fbc_disable_crtc(crtc);	4831	intel_fbc_disable_crtc(crtc);
@@ -4899,6 +4873,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) · 41 unmodified lines
4899	if (WARN_ON(intel_crtc->active))	4873	if (WARN_ON(intel_crtc->active))
4900	return;	4874	return;
4901		4875
		4876	if (intel_crtc->config->has_pch_encoder)
		4877	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
		4878
4902	if (intel_crtc->config->has_pch_encoder)	4879	if (intel_crtc->config->has_pch_encoder)
4903	intel_prepare_shared_dpll(intel_crtc);	4880	intel_prepare_shared_dpll(intel_crtc);
4904		4881
@@ -4917,7 +4894,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) · 12 unmodified lines
4917	intel_crtc->active = true;	4894	intel_crtc->active = true;
4918		4895
4919	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);	4896	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4920	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4921		4897
4922	for_each_encoder_on_crtc(dev, crtc, encoder)	4898	for_each_encoder_on_crtc(dev, crtc, encoder)
4923	if (encoder->pre_enable)	4899	if (encoder->pre_enable)
@@ -4955,6 +4931,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) · 31 unmodified lines
4955		4931
4956	if (HAS_PCH_CPT(dev))	4932	if (HAS_PCH_CPT(dev))
4957	cpt_verify_modeset(dev, intel_crtc->pipe);	4933	cpt_verify_modeset(dev, intel_crtc->pipe);
		4934
		4935	/* Must wait for vblank to avoid spurious PCH FIFO underruns */
		4936	if (intel_crtc->config->has_pch_encoder)
		4937	intel_wait_for_vblank(dev, pipe);
		4938	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4958	}	4939	}
4959		4940
4960	/* IPS only exists on ULT machines and is tied to pipe A. */	4941	/* IPS only exists on ULT machines and is tied to pipe A. */
@@ -4977,6 +4958,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) · 16 unmodified lines
4977	if (WARN_ON(intel_crtc->active))	4958	if (WARN_ON(intel_crtc->active))
4978	return;	4959	return;
4979		4960
		4961	if (intel_crtc->config->has_pch_encoder)
		4962	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		4963	false);
		4964
4980	if (intel_crtc_to_shared_dpll(intel_crtc))	4965	if (intel_crtc_to_shared_dpll(intel_crtc))
4981	intel_enable_shared_dpll(intel_crtc);	4966	intel_enable_shared_dpll(intel_crtc);
4982		4967
@@ -5009,11 +4994,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) · 26 unmodified lines
5009	encoder->pre_enable(encoder);	4994	encoder->pre_enable(encoder);
5010	}	4995	}
5011		4996
5012	if (intel_crtc->config->has_pch_encoder) {	4997	if (intel_crtc->config->has_pch_encoder)
5013	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5014	true);
5015	dev_priv->display.fdi_link_train(crtc);	4998	dev_priv->display.fdi_link_train(crtc);
5016	}
5017		4999
5018	if (!is_dsi)	5000	if (!is_dsi)
5019	intel_ddi_enable_pipe_clock(intel_crtc);	5001	intel_ddi_enable_pipe_clock(intel_crtc);
@@ -5050,6 +5032,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) · 30 unmodified lines
5050	intel_opregion_notify_encoder(encoder, true);	5032	intel_opregion_notify_encoder(encoder, true);
5051	}	5033	}
5052		5034
		5035	if (intel_crtc->config->has_pch_encoder)
		5036	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		5037	true);
		5038
5053	/* If we change the relative order between pipe/planes enabling, we need	5039	/* If we change the relative order between pipe/planes enabling, we need
5054	* to change the workaround. */	5040	* to change the workaround. */
5055	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;	5041	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
@@ -5081,7 +5067,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) · 25 unmodified lines
5081	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5067	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082	struct intel_encoder *encoder;	5068	struct intel_encoder *encoder;
5083	int pipe = intel_crtc->pipe;	5069	int pipe = intel_crtc->pipe;
5084	u32 reg, temp;	5070
		5071	if (intel_crtc->config->has_pch_encoder)
		5072	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5085		5073
5086	for_each_encoder_on_crtc(dev, crtc, encoder)	5074	for_each_encoder_on_crtc(dev, crtc, encoder)
5087	encoder->disable(encoder);	5075	encoder->disable(encoder);
@@ -5089,9 +5077,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) · 1 unmodified line
5089	drm_crtc_vblank_off(crtc);	5077	drm_crtc_vblank_off(crtc);
5090	assert_vblank_disabled(crtc);	5078	assert_vblank_disabled(crtc);
5091		5079
5092	if (intel_crtc->config->has_pch_encoder)
5093	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5094
5095	intel_disable_pipe(intel_crtc);	5080	intel_disable_pipe(intel_crtc);
5096		5081
5097	ironlake_pfit_disable(intel_crtc, false);	5082	ironlake_pfit_disable(intel_crtc, false);
@@ -5107,6 +5092,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) · 9 unmodified lines
5107	ironlake_disable_pch_transcoder(dev_priv, pipe);	5092	ironlake_disable_pch_transcoder(dev_priv, pipe);
5108		5093
5109	if (HAS_PCH_CPT(dev)) {	5094	if (HAS_PCH_CPT(dev)) {
		5095	i915_reg_t reg;
		5096	u32 temp;
		5097
5110	/* disable TRANS_DP_CTL */	5098	/* disable TRANS_DP_CTL */
5111	reg = TRANS_DP_CTL(pipe);	5099	reg = TRANS_DP_CTL(pipe);
5112	temp = I915_READ(reg);	5100	temp = I915_READ(reg);
@@ -5123,6 +5111,8 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) · 10 unmodified lines
5123		5111
5124	ironlake_fdi_pll_disable(intel_crtc);	5112	ironlake_fdi_pll_disable(intel_crtc);
5125	}	5113	}
		5114
		5115	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5126	}	5116	}
5127		5117
5128	static void haswell_crtc_disable(struct drm_crtc *crtc)	5118	static void haswell_crtc_disable(struct drm_crtc *crtc)
@@ -5134,6 +5124,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) · 5 unmodified lines
5134	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;	5124	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5135	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);	5125	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5136		5126
		5127	if (intel_crtc->config->has_pch_encoder)
		5128	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		5129	false);
		5130
5137	for_each_encoder_on_crtc(dev, crtc, encoder) {	5131	for_each_encoder_on_crtc(dev, crtc, encoder) {
5138	intel_opregion_notify_encoder(encoder, false);	5132	intel_opregion_notify_encoder(encoder, false);
5139	encoder->disable(encoder);	5133	encoder->disable(encoder);
@@ -5142,9 +5136,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) · 2 unmodified lines
5142	drm_crtc_vblank_off(crtc);	5136	drm_crtc_vblank_off(crtc);
5143	assert_vblank_disabled(crtc);	5137	assert_vblank_disabled(crtc);
5144		5138
5145	if (intel_crtc->config->has_pch_encoder)
5146	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5147	false);
5148	intel_disable_pipe(intel_crtc);	5139	intel_disable_pipe(intel_crtc);
5149		5140
5150	if (intel_crtc->config->dp_encoder_is_mst)	5141	if (intel_crtc->config->dp_encoder_is_mst)
@@ -5169,6 +5160,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) · 18 unmodified lines
5169	for_each_encoder_on_crtc(dev, crtc, encoder)	5160	for_each_encoder_on_crtc(dev, crtc, encoder)
5170	if (encoder->post_disable)	5161	if (encoder->post_disable)
5171	encoder->post_disable(encoder);	5162	encoder->post_disable(encoder);
		5163
		5164	if (intel_crtc->config->has_pch_encoder)
		5165	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		5166	true);
5172	}	5167	}
5173		5168
5174	static void i9xx_pfit_enable(struct intel_crtc *crtc)	5169	static void i9xx_pfit_enable(struct intel_crtc *crtc)
@@ -5199,15 +5194,15 @@ static enum intel_display_power_domain port_to_power_domain(enum port port) · 24 unmodified lines
5199	{	5194	{
5200	switch (port) {	5195	switch (port) {
5201	case PORT_A:	5196	case PORT_A:
5202	return POWER_DOMAIN_PORT_DDI_A_4_LANES;	5197	return POWER_DOMAIN_PORT_DDI_A_LANES;
5203	case PORT_B:	5198	case PORT_B:
5204	return POWER_DOMAIN_PORT_DDI_B_4_LANES;	5199	return POWER_DOMAIN_PORT_DDI_B_LANES;
5205	case PORT_C:	5200	case PORT_C:
5206	return POWER_DOMAIN_PORT_DDI_C_4_LANES;	5201	return POWER_DOMAIN_PORT_DDI_C_LANES;
5207	case PORT_D:	5202	case PORT_D:
5208	return POWER_DOMAIN_PORT_DDI_D_4_LANES;	5203	return POWER_DOMAIN_PORT_DDI_D_LANES;
5209	case PORT_E:	5204	case PORT_E:
5210	return POWER_DOMAIN_PORT_DDI_E_2_LANES;	5205	return POWER_DOMAIN_PORT_DDI_E_LANES;
5211	default:	5206	default:
5212	MISSING_CASE(port);	5207	MISSING_CASE(port);
5213	return POWER_DOMAIN_PORT_OTHER;	5208	return POWER_DOMAIN_PORT_OTHER;
@@ -5302,13 +5297,11 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) · 88 unmodified lines
5302	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5297	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5303	enum pipe pipe = intel_crtc->pipe;	5298	enum pipe pipe = intel_crtc->pipe;
5304	unsigned long mask;	5299	unsigned long mask;
5305	enum transcoder transcoder;	5300	enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5306		5301
5307	if (!crtc->state->active)	5302	if (!crtc->state->active)
5308	return 0;	5303	return 0;
5309		5304
5310	transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5311
5312	mask = BIT(POWER_DOMAIN_PIPE(pipe));	5305	mask = BIT(POWER_DOMAIN_PIPE(pipe));
5313	mask \|= BIT(POWER_DOMAIN_TRANSCODER(transcoder));	5306	mask \|= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5314	if (intel_crtc->config->pch_pfit.enabled \|\|	5307	if (intel_crtc->config->pch_pfit.enabled \|\|
@@ -5395,7 +5388,7 @@ static void intel_update_max_cdclk(struct drm_device *dev) · 80 unmodified lines
5395	{	5388	{
5396	struct drm_i915_private *dev_priv = dev->dev_private;	5389	struct drm_i915_private *dev_priv = dev->dev_private;
5397		5390
5398	if (IS_SKYLAKE(dev)) {	5391	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
5399	u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;	5392	u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5400		5393
5401	if (limit == SKL_DFSM_CDCLK_LIMIT_675)	5394	if (limit == SKL_DFSM_CDCLK_LIMIT_675)
@@ -5812,32 +5805,16 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv) · 410 unmodified lines
5812	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)	5805	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5813	DRM_ERROR("DBuf power disable timeout\n");	5806	DRM_ERROR("DBuf power disable timeout\n");
5814		5807
5815	/*	5808	/* disable DPLL0 */
5816	* DMC assumes ownership of LCPLL and will get confused if we touch it.	5809	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5817	*/	5810	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5818	if (dev_priv->csr.dmc_payload) {	5811	DRM_ERROR("Couldn't disable DPLL0\n");
5819	/* disable DPLL0 */
5820	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5821	~LCPLL_PLL_ENABLE);
5822	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5823	DRM_ERROR("Couldn't disable DPLL0\n");
5824	}
5825
5826	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5827	}	5812	}
5828		5813
5829	void skl_init_cdclk(struct drm_i915_private *dev_priv)	5814	void skl_init_cdclk(struct drm_i915_private *dev_priv)
5830	{	5815	{
5831	u32 val;
5832	unsigned int required_vco;	5816	unsigned int required_vco;
5833		5817
5834	/* enable PCH reset handshake */
5835	val = I915_READ(HSW_NDE_RSTWRN_OPT);
5836	I915_WRITE(HSW_NDE_RSTWRN_OPT, val \| RESET_PCH_HANDSHAKE_ENABLE);
5837
5838	/* enable PG1 and Misc I/O */
5839	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5840
5841	/* DPLL0 not enabled (happens on early BIOS versions) */	5818	/* DPLL0 not enabled (happens on early BIOS versions) */
5842	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {	5819	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5843	/* enable DPLL0 */	5820	/* enable DPLL0 */
@@ -5858,6 +5835,45 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) · 14 unmodified lines
5858	DRM_ERROR("DBuf power enable timeout\n");	5835	DRM_ERROR("DBuf power enable timeout\n");
5859	}	5836	}
5860		5837
		5838	int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
		5839	{
		5840	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
		5841	uint32_t cdctl = I915_READ(CDCLK_CTL);
		5842	int freq = dev_priv->skl_boot_cdclk;
		5843
		5844	/*
		5845	* check if the pre-os intialized the display
		5846	* There is SWF18 scratchpad register defined which is set by the
		5847	* pre-os which can be used by the OS drivers to check the status
		5848	*/
		5849	if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
		5850	goto sanitize;
		5851
		5852	/* Is PLL enabled and locked ? */
		5853	if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
		5854	goto sanitize;
		5855
		5856	/* DPLL okay; verify the cdclock
		5857	*
		5858	* Noticed in some instances that the freq selection is correct but
		5859	* decimal part is programmed wrong from BIOS where pre-os does not
		5860	* enable display. Verify the same as well.
		5861	*/
		5862	if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) \| skl_cdclk_decimal(freq)))
		5863	/* All well; nothing to sanitize */
		5864	return false;
		5865	sanitize:
		5866	/*
		5867	* As of now initialize with max cdclk till
		5868	* we get dynamic cdclk support
		5869	* */
		5870	dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
		5871	skl_init_cdclk(dev_priv);
		5872
		5873	/* we did have to sanitize */
		5874	return true;
		5875	}
		5876
5861	/* Adjust CDclk dividers to allow high res or save power if possible */	5877	/* Adjust CDclk dividers to allow high res or save power if possible */
5862	static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)	5878	static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5863	{	5879	{
@@ -6322,7 +6338,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) · 458 unmodified lines
6322	return;	6338	return;
6323		6339
6324	if (to_intel_plane_state(crtc->primary->state)->visible) {	6340	if (to_intel_plane_state(crtc->primary->state)->visible) {
6325	intel_crtc_wait_for_pending_flips(crtc);	6341	WARN_ON(intel_crtc->unpin_work);
		6342
6326	intel_pre_disable_primary(crtc);	6343	intel_pre_disable_primary(crtc);
6327		6344
6328	intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));	6345	intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
@@ -6642,6 +6659,15 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc, · 313 unmodified lines
6642	pipe_config_supports_ips(dev_priv, pipe_config);	6659	pipe_config_supports_ips(dev_priv, pipe_config);
6643	}	6660	}
6644		6661
		6662	static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
		6663	{
		6664	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
		6665
		6666	/* GDG double wide on either pipe, otherwise pipe A only */
		6667	return INTEL_INFO(dev_priv)->gen < 4 &&
		6668	(crtc->pipe == PIPE_A \|\| IS_I915G(dev_priv));
		6669	}
		6670
6645	static int intel_crtc_compute_config(struct intel_crtc *crtc,	6671	static int intel_crtc_compute_config(struct intel_crtc *crtc,
6646	struct intel_crtc_state *pipe_config)	6672	struct intel_crtc_state *pipe_config)
6647	{	6673	{
@@ -6651,23 +6677,24 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, · 3 unmodified lines
6651		6677
6652	/* FIXME should check pixel clock limits on all platforms */	6678	/* FIXME should check pixel clock limits on all platforms */
6653	if (INTEL_INFO(dev)->gen < 4) {	6679	if (INTEL_INFO(dev)->gen < 4) {
6654	int clock_limit = dev_priv->max_cdclk_freq;	6680	int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6655		6681
6656	/*	6682	/*
6657	* Enable pixel doubling when the dot clock	6683	* Enable double wide mode when the dot clock
6658	* is > 90% of the (display) core speed.	6684	* is > 90% of the (display) core speed.
6659	*
6660	* GDG double wide on either pipe,
6661	* otherwise pipe A only.
6662	*/	6685	*/
6663	if ((crtc->pipe == PIPE_A \|\| IS_I915G(dev)) &&	6686	if (intel_crtc_supports_double_wide(crtc) &&
6664	adjusted_mode->crtc_clock > clock_limit * 9 / 10) {	6687	adjusted_mode->crtc_clock > clock_limit) {
6665	clock_limit *= 2;	6688	clock_limit *= 2;
6666	pipe_config->double_wide = true;	6689	pipe_config->double_wide = true;
6667	}	6690	}
6668		6691
6669	if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)	6692	if (adjusted_mode->crtc_clock > clock_limit) {
		6693	DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
		6694	adjusted_mode->crtc_clock, clock_limit,
		6695	yesno(pipe_config->double_wide));
6670	return -EINVAL;	6696	return -EINVAL;
		6697	}
6671	}	6698	}
6672		6699
6673	/*	6700	/*
@@ -7432,7 +7459,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, · 758 unmodified lines
7432	struct drm_device *dev = crtc->base.dev;	7459	struct drm_device *dev = crtc->base.dev;
7433	struct drm_i915_private *dev_priv = dev->dev_private;	7460	struct drm_i915_private *dev_priv = dev->dev_private;
7434	int pipe = crtc->pipe;	7461	int pipe = crtc->pipe;
7435	int dpll_reg = DPLL(crtc->pipe);	7462	i915_reg_t dpll_reg = DPLL(crtc->pipe);
7436	enum dpio_channel port = vlv_pipe_to_channel(pipe);	7463	enum dpio_channel port = vlv_pipe_to_channel(pipe);
7437	u32 loopfilter, tribuf_calcntr;	7464	u32 loopfilter, tribuf_calcntr;
7438	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;	7465	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
@@ -9350,8 +9377,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) · 1911 unmodified lines
9350		9377
9351	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");	9378	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9352	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");	9379	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9353	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");	9380	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9354	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");	9381	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9355	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");	9382	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9356	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,	9383	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9357	"CPU PWM1 enabled\n");	9384	"CPU PWM1 enabled\n");
@@ -9813,7 +9840,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, · 455 unmodified lines
9813		9840
9814	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;	9841	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9815		9842
9816	if (IS_SKYLAKE(dev))	9843	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
9817	skylake_get_ddi_pll(dev_priv, port, pipe_config);	9844	skylake_get_ddi_pll(dev_priv, port, pipe_config);
9818	else if (IS_BROXTON(dev))	9845	else if (IS_BROXTON(dev))
9819	bxt_get_ddi_pll(dev_priv, port, pipe_config);	9846	bxt_get_ddi_pll(dev_priv, port, pipe_config);
@@ -10154,20 +10181,17 @@ __intel_framebuffer_create(struct drm_device *dev, · 334 unmodified lines
10154	int ret;	10181	int ret;
10155		10182
10156	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);	10183	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10157	if (!intel_fb) {	10184	if (!intel_fb)
10158	drm_gem_object_unreference(&obj->base);
10159	return ERR_PTR(-ENOMEM);	10185	return ERR_PTR(-ENOMEM);
10160	}
10161		10186
10162	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);	10187	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10163	if (ret)	10188	if (ret)
10164	goto err;	10189	goto err;
10165		10190
10166	return &intel_fb->base;	10191	return &intel_fb->base;
		10192
10167	err:	10193	err:
10168	drm_gem_object_unreference(&obj->base);
10169	kfree(intel_fb);	10194	kfree(intel_fb);
10170
10171	return ERR_PTR(ret);	10195	return ERR_PTR(ret);
10172	}	10196	}
10173		10197
@@ -10207,6 +10231,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, · 33 unmodified lines
10207	struct drm_display_mode *mode,	10231	struct drm_display_mode *mode,
10208	int depth, int bpp)	10232	int depth, int bpp)
10209	{	10233	{
		10234	struct drm_framebuffer *fb;
10210	struct drm_i915_gem_object *obj;	10235	struct drm_i915_gem_object *obj;
10211	struct drm_mode_fb_cmd2 mode_cmd = { 0 };	10236	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10212		10237
@@ -10221,7 +10246,11 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, · 8 unmodified lines
10221	bpp);	10246	bpp);
10222	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);	10247	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10223		10248
10224	return intel_framebuffer_create(dev, &mode_cmd, obj);	10249	fb = intel_framebuffer_create(dev, &mode_cmd, obj);
		10250	if (IS_ERR(fb))
		10251	drm_gem_object_unreference_unlocked(&obj->base);
		10252
		10253	return fb;
10225	}	10254	}
10226		10255
10227	static struct drm_framebuffer *	10256	static struct drm_framebuffer *
@@ -11124,7 +11153,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, · 896 unmodified lines
11124	*/	11153	*/
11125	if (ring->id == RCS) {	11154	if (ring->id == RCS) {
11126	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));	11155	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11127	intel_ring_emit(ring, DERRMR);	11156	intel_ring_emit_reg(ring, DERRMR);
11128	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|	11157	intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE \|
11129	DERRMR_PIPEB_PRI_FLIP_DONE \|	11158	DERRMR_PIPEB_PRI_FLIP_DONE \|
11130	DERRMR_PIPEC_PRI_FLIP_DONE));	11159	DERRMR_PIPEC_PRI_FLIP_DONE));
@@ -11134,7 +11163,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, · 3 unmodified lines
11134	else	11163	else
11135	intel_ring_emit(ring, MI_STORE_REGISTER_MEM \|	11164	intel_ring_emit(ring, MI_STORE_REGISTER_MEM \|
11136	MI_SRM_LRM_GLOBAL_GTT);	11165	MI_SRM_LRM_GLOBAL_GTT);
11137	intel_ring_emit(ring, DERRMR);	11166	intel_ring_emit_reg(ring, DERRMR);
11138	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);	11167	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11139	if (IS_GEN8(dev)) {	11168	if (IS_GEN8(dev)) {
11140	intel_ring_emit(ring, 0);	11169	intel_ring_emit(ring, 0);
@@ -11179,13 +11208,14 @@ static bool use_mmio_flip(struct intel_engine_cs *ring, · 38 unmodified lines
11179	}	11208	}
11180		11209
11181	static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,	11210	static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
		11211	unsigned int rotation,
11182	struct intel_unpin_work *work)	11212	struct intel_unpin_work *work)
11183	{	11213	{
11184	struct drm_device *dev = intel_crtc->base.dev;	11214	struct drm_device *dev = intel_crtc->base.dev;
11185	struct drm_i915_private *dev_priv = dev->dev_private;	11215	struct drm_i915_private *dev_priv = dev->dev_private;
11186	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;	11216	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11187	const enum pipe pipe = intel_crtc->pipe;	11217	const enum pipe pipe = intel_crtc->pipe;
11188	u32 ctl, stride;	11218	u32 ctl, stride, tile_height;
11189		11219
11190	ctl = I915_READ(PLANE_CTL(pipe, 0));	11220	ctl = I915_READ(PLANE_CTL(pipe, 0));
11191	ctl &= ~PLANE_CTL_TILED_MASK;	11221	ctl &= ~PLANE_CTL_TILED_MASK;
@@ -11209,9 +11239,16 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, · 17 unmodified lines
11209	* The stride is either expressed as a multiple of 64 bytes chunks for	11239	* The stride is either expressed as a multiple of 64 bytes chunks for
11210	* linear buffers or in number of tiles for tiled buffers.	11240	* linear buffers or in number of tiles for tiled buffers.
11211	*/	11241	*/
11212	stride = fb->pitches[0] /	11242	if (intel_rotation_90_or_270(rotation)) {
11213	intel_fb_stride_alignment(dev, fb->modifier[0],	11243	/* stride = Surface height in tiles */
11214	fb->pixel_format);	11244	tile_height = intel_tile_height(dev, fb->pixel_format,
		11245	fb->modifier[0], 0);
		11246	stride = DIV_ROUND_UP(fb->height, tile_height);
		11247	} else {
		11248	stride = fb->pitches[0] /
		11249	intel_fb_stride_alignment(dev, fb->modifier[0],
		11250	fb->pixel_format);
		11251	}
11215		11252
11216	/*	11253	/*
11217	* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on	11254	* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
@@ -11232,10 +11269,9 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, · 14 unmodified lines
11232	struct intel_framebuffer *intel_fb =	11269	struct intel_framebuffer *intel_fb =
11233	to_intel_framebuffer(intel_crtc->base.primary->fb);	11270	to_intel_framebuffer(intel_crtc->base.primary->fb);
11234	struct drm_i915_gem_object *obj = intel_fb->obj;	11271	struct drm_i915_gem_object *obj = intel_fb->obj;
		11272	i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11235	u32 dspcntr;	11273	u32 dspcntr;
11236	u32 reg;
11237		11274
11238	reg = DSPCNTR(intel_crtc->plane);
11239	dspcntr = I915_READ(reg);	11275	dspcntr = I915_READ(reg);
11240		11276
11241	if (obj->tiling_mode != I915_TILING_NONE)	11277	if (obj->tiling_mode != I915_TILING_NONE)
@@ -11269,7 +11305,7 @@ static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) · 27 unmodified lines
11269	intel_pipe_update_start(crtc);	11305	intel_pipe_update_start(crtc);
11270		11306
11271	if (INTEL_INFO(mmio_flip->i915)->gen >= 9)	11307	if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11272	skl_do_mmio_flip(crtc, work);	11308	skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11273	else	11309	else
11274	/* use_mmio_flip() retricts MMIO flips to ilk+ */	11310	/* use_mmio_flip() retricts MMIO flips to ilk+ */
11275	ilk_do_mmio_flip(crtc, work);	11311	ilk_do_mmio_flip(crtc, work);
@@ -11296,10 +11332,7 @@ static void intel_mmio_flip_work_func(struct work_struct *work) · 20 unmodified lines
11296		11332
11297	static int intel_queue_mmio_flip(struct drm_device *dev,	11333	static int intel_queue_mmio_flip(struct drm_device *dev,
11298	struct drm_crtc *crtc,	11334	struct drm_crtc *crtc,
11299	struct drm_framebuffer *fb,	11335	struct drm_i915_gem_object *obj)
11300	struct drm_i915_gem_object *obj,
11301	struct intel_engine_cs *ring,
11302	uint32_t flags)
11303	{	11336	{
11304	struct intel_mmio_flip *mmio_flip;	11337	struct intel_mmio_flip *mmio_flip;
11305		11338
@@ -11310,6 +11343,7 @@ static int intel_queue_mmio_flip(struct drm_device *dev, · 4 unmodified lines
11310	mmio_flip->i915 = to_i915(dev);	11343	mmio_flip->i915 = to_i915(dev);
11311	mmio_flip->req = i915_gem_request_reference(obj->last_write_req);	11344	mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11312	mmio_flip->crtc = to_intel_crtc(crtc);	11345	mmio_flip->crtc = to_intel_crtc(crtc);
		11346	mmio_flip->rotation = crtc->primary->state->rotation;
11313		11347
11314	INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);	11348	INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11315	schedule_work(&mmio_flip->work);	11349	schedule_work(&mmio_flip->work);
@@ -11515,9 +11549,14 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, · 199 unmodified lines
11515	* synchronisation, so all we want here is to pin the framebuffer	11549	* synchronisation, so all we want here is to pin the framebuffer
11516	* into the display plane and skip any waits.	11550	* into the display plane and skip any waits.
11517	*/	11551	*/
		11552	if (!mmio_flip) {
		11553	ret = i915_gem_object_sync(obj, ring, &request);
		11554	if (ret)
		11555	goto cleanup_pending;
		11556	}
		11557
11518	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,	11558	ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11519	crtc->primary->state,	11559	crtc->primary->state);
11520	mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11521	if (ret)	11560	if (ret)
11522	goto cleanup_pending;	11561	goto cleanup_pending;
11523		11562
@@ -11526,8 +11565,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, · 2 unmodified lines
11526	work->gtt_offset += intel_crtc->dspaddr_offset;	11565	work->gtt_offset += intel_crtc->dspaddr_offset;
11527		11566
11528	if (mmio_flip) {	11567	if (mmio_flip) {
11529	ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,	11568	ret = intel_queue_mmio_flip(dev, crtc, obj);
11530	page_flip_flags);
11531	if (ret)	11569	if (ret)
11532	goto cleanup_unpin;	11570	goto cleanup_unpin;
11533		11571
@@ -11641,18 +11679,32 @@ retry: · 107 unmodified lines
11641	static bool intel_wm_need_update(struct drm_plane *plane,	11679	static bool intel_wm_need_update(struct drm_plane *plane,
11642	struct drm_plane_state *state)	11680	struct drm_plane_state *state)
11643	{	11681	{
11644	/* Update watermarks on tiling changes. */	11682	struct intel_plane_state *new = to_intel_plane_state(state);
		11683	struct intel_plane_state *cur = to_intel_plane_state(plane->state);
		11684
		11685	/* Update watermarks on tiling or size changes. */
11645	if (!plane->state->fb \|\| !state->fb \|\|	11686	if (!plane->state->fb \|\| !state->fb \|\|
11646	plane->state->fb->modifier[0] != state->fb->modifier[0] \|\|	11687	plane->state->fb->modifier[0] != state->fb->modifier[0] \|\|
11647	plane->state->rotation != state->rotation)	11688	plane->state->rotation != state->rotation \|\|
11648	return true;	11689	drm_rect_width(&new->src) != drm_rect_width(&cur->src) \|\|
11649		11690	drm_rect_height(&new->src) != drm_rect_height(&cur->src) \|\|
11650	if (plane->state->crtc_w != state->crtc_w)	11691	drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) \|\|
		11692	drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11651	return true;	11693	return true;
11652		11694
11653	return false;	11695	return false;
11654	}	11696	}
11655		11697
		11698	static bool needs_scaling(struct intel_plane_state *state)
		11699	{
		11700	int src_w = drm_rect_width(&state->src) >> 16;
		11701	int src_h = drm_rect_height(&state->src) >> 16;
		11702	int dst_w = drm_rect_width(&state->dst);
		11703	int dst_h = drm_rect_height(&state->dst);
		11704
		11705	return (src_w != dst_w \|\| src_h != dst_h);
		11706	}
		11707
11656	int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,	11708	int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11657	struct drm_plane_state *plane_state)	11709	struct drm_plane_state *plane_state)
11658	{	11710	{
@@ -11668,7 +11720,6 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, · 9 unmodified lines
11668	bool mode_changed = needs_modeset(crtc_state);	11720	bool mode_changed = needs_modeset(crtc_state);
11669	bool was_crtc_enabled = crtc->state->active;	11721	bool was_crtc_enabled = crtc->state->active;
11670	bool is_crtc_enabled = crtc_state->active;	11722	bool is_crtc_enabled = crtc_state->active;
11671
11672	bool turn_off, turn_on, visible, was_visible;	11723	bool turn_off, turn_on, visible, was_visible;
11673	struct drm_framebuffer *fb = plane_state->fb;	11724	struct drm_framebuffer *fb = plane_state->fb;
11674		11725
@@ -11681,14 +11732,6 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, · 6 unmodified lines
11681	return ret;	11732	return ret;
11682	}	11733	}
11683		11734
11684	/*
11685	* Disabling a plane is always okay; we just need to update
11686	* fb tracking in a special way since cleanup_fb() won't
11687	* get called by the plane helpers.
11688	*/
11689	if (old_plane_state->base.fb && !fb)
11690	intel_crtc->atomic.disabled_planes \|= 1 << i;
11691
11692	was_visible = old_plane_state->visible;	11735	was_visible = old_plane_state->visible;
11693	visible = to_intel_plane_state(plane_state)->visible;	11736	visible = to_intel_plane_state(plane_state)->visible;
11694		11737
@@ -11738,7 +11781,6 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, · 43 unmodified lines
11738		11781
11739	switch (plane->type) {	11782	switch (plane->type) {
11740	case DRM_PLANE_TYPE_PRIMARY:	11783	case DRM_PLANE_TYPE_PRIMARY:
11741	intel_crtc->atomic.wait_for_flips = true;
11742	intel_crtc->atomic.pre_disable_primary = turn_off;	11784	intel_crtc->atomic.pre_disable_primary = turn_off;
11743	intel_crtc->atomic.post_enable_primary = turn_on;	11785	intel_crtc->atomic.post_enable_primary = turn_on;
11744		11786
@@ -11786,11 +11828,23 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, · 41 unmodified lines
11786	case DRM_PLANE_TYPE_CURSOR:	11828	case DRM_PLANE_TYPE_CURSOR:
11787	break;	11829	break;
11788	case DRM_PLANE_TYPE_OVERLAY:	11830	case DRM_PLANE_TYPE_OVERLAY:
11789	if (turn_off && !mode_changed) {	11831	/*
		11832	* WaCxSRDisabledForSpriteScaling:ivb
		11833	*
		11834	* cstate->update_wm was already set above, so this flag will
		11835	* take effect when we commit and program watermarks.
		11836	*/
		11837	if (IS_IVYBRIDGE(dev) &&
		11838	needs_scaling(to_intel_plane_state(plane_state)) &&
		11839	!needs_scaling(old_plane_state)) {
		11840	to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
		11841	} else if (turn_off && !mode_changed) {
11790	intel_crtc->atomic.wait_vblank = true;	11842	intel_crtc->atomic.wait_vblank = true;
11791	intel_crtc->atomic.update_sprite_watermarks \|=	11843	intel_crtc->atomic.update_sprite_watermarks \|=
11792	1 << i;	11844	1 << i;
11793	}	11845	}
		11846
		11847	break;
11794	}	11848	}
11795	return 0;	11849	return 0;
11796	}	11850	}
@@ -11875,6 +11929,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, · 78 unmodified lines
11875	}	11929	}
11876		11930
11877	ret = 0;	11931	ret = 0;
		11932	if (dev_priv->display.compute_pipe_wm) {
		11933	ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
		11934	if (ret)
		11935	return ret;
		11936	}
		11937
11878	if (INTEL_INFO(dev)->gen >= 9) {	11938	if (INTEL_INFO(dev)->gen >= 9) {
11879	if (mode_changed)	11939	if (mode_changed)
11880	ret = skl_update_scaler_crtc(pipe_config);	11940	ret = skl_update_scaler_crtc(pipe_config);
@@ -12064,7 +12124,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, · 183 unmodified lines
12064	pipe_config->dpll_hw_state.pll9,	12124	pipe_config->dpll_hw_state.pll9,
12065	pipe_config->dpll_hw_state.pll10,	12125	pipe_config->dpll_hw_state.pll10,
12066	pipe_config->dpll_hw_state.pcsdw12);	12126	pipe_config->dpll_hw_state.pcsdw12);
12067	} else if (IS_SKYLAKE(dev)) {	12127	} else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
12068	DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "	12128	DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12069	"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",	12129	"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12070	pipe_config->ddi_pll_sel,	12130	pipe_config->ddi_pll_sel,
@@ -12322,6 +12382,18 @@ intel_modeset_update_crtc_state(struct drm_atomic_state *state) · 251 unmodified lines
12322	crtc->hwmode = crtc->state->adjusted_mode;	12382	crtc->hwmode = crtc->state->adjusted_mode;
12323	else	12383	else
12324	crtc->hwmode.crtc_clock = 0;	12384	crtc->hwmode.crtc_clock = 0;
		12385
		12386	/*
		12387	* Update legacy state to satisfy fbc code. This can
		12388	* be removed when fbc uses the atomic state.
		12389	*/
		12390	if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
		12391	struct drm_plane_state *plane_state = crtc->primary->state;
		12392
		12393	crtc->primary->fb = plane_state->fb;
		12394	crtc->x = plane_state->src_x >> 16;
		12395	crtc->y = plane_state->src_y >> 16;
		12396	}
12325	}	12397	}
12326	}	12398	}
12327		12399
@@ -12347,7 +12419,7 @@ static bool intel_fuzzy_clock_check(int clock1, int clock2) · 19 unmodified lines
12347	list_for_each_entry((intel_crtc), \	12419	list_for_each_entry((intel_crtc), \
12348	&(dev)->mode_config.crtc_list, \	12420	&(dev)->mode_config.crtc_list, \
12349	base.head) \	12421	base.head) \
12350	if (mask & (1 <<(intel_crtc)->pipe))	12422	for_each_if (mask & (1 <<(intel_crtc)->pipe))
12351		12423
12352	static bool	12424	static bool
12353	intel_compare_m_n(unsigned int m, unsigned int n,	12425	intel_compare_m_n(unsigned int m, unsigned int n,
@@ -13085,6 +13157,45 @@ static int intel_modeset_checks(struct drm_atomic_state *state) · 731 unmodified lines
13085	return 0;	13157	return 0;
13086	}	13158	}
13087		13159
		13160	/*
		13161	* Handle calculation of various watermark data at the end of the atomic check
		13162	* phase. The code here should be run after the per-crtc and per-plane 'check'
		13163	* handlers to ensure that all derived state has been updated.
		13164	*/
		13165	static void calc_watermark_data(struct drm_atomic_state *state)
		13166	{
		13167	struct drm_device *dev = state->dev;
		13168	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
		13169	struct drm_crtc *crtc;
		13170	struct drm_crtc_state *cstate;
		13171	struct drm_plane *plane;
		13172	struct drm_plane_state *pstate;
		13173
		13174	/*
		13175	* Calculate watermark configuration details now that derived
		13176	* plane/crtc state is all properly updated.
		13177	*/
		13178	drm_for_each_crtc(crtc, dev) {
		13179	cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
		13180	crtc->state;
		13181
		13182	if (cstate->active)
		13183	intel_state->wm_config.num_pipes_active++;
		13184	}
		13185	drm_for_each_legacy_plane(plane, dev) {
		13186	pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
		13187	plane->state;
		13188
		13189	if (!to_intel_plane_state(pstate)->visible)
		13190	continue;
		13191
		13192	intel_state->wm_config.sprites_enabled = true;
		13193	if (pstate->crtc_w != pstate->src_w >> 16 \|\|
		13194	pstate->crtc_h != pstate->src_h >> 16)
		13195	intel_state->wm_config.sprites_scaled = true;
		13196	}
		13197	}
		13198
13088	/**	13199	/**
13089	* intel_atomic_check - validate state object	13200	* intel_atomic_check - validate state object
13090	* @dev: drm device	13201	* @dev: drm device
@@ -13093,6 +13204,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state) · 2 unmodified lines
13093	static int intel_atomic_check(struct drm_device *dev,	13204	static int intel_atomic_check(struct drm_device *dev,
13094	struct drm_atomic_state *state)	13205	struct drm_atomic_state *state)
13095	{	13206	{
		13207	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13096	struct drm_crtc *crtc;	13208	struct drm_crtc *crtc;
13097	struct drm_crtc_state *crtc_state;	13209	struct drm_crtc_state *crtc_state;
13098	int ret, i;	13210	int ret, i;
@@ -13160,10 +13272,81 @@ static int intel_atomic_check(struct drm_device *dev, · 61 unmodified lines
13160	if (ret)	13272	if (ret)
13161	return ret;	13273	return ret;
13162	} else	13274	} else
13163	to_intel_atomic_state(state)->cdclk =	13275	intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13164	to_i915(state->dev)->cdclk_freq;
13165		13276
13166	return drm_atomic_helper_check_planes(state->dev, state);	13277	ret = drm_atomic_helper_check_planes(state->dev, state);
		13278	if (ret)
		13279	return ret;
		13280
		13281	calc_watermark_data(state);
		13282
		13283	return 0;
		13284	}
		13285
		13286	static int intel_atomic_prepare_commit(struct drm_device *dev,
		13287	struct drm_atomic_state *state,
		13288	bool async)
		13289	{
		13290	struct drm_i915_private *dev_priv = dev->dev_private;
		13291	struct drm_plane_state *plane_state;
		13292	struct drm_crtc_state *crtc_state;
		13293	struct drm_plane *plane;
		13294	struct drm_crtc *crtc;
		13295	int i, ret;
		13296
		13297	if (async) {
		13298	DRM_DEBUG_KMS("i915 does not yet support async commit\n");
		13299	return -EINVAL;
		13300	}
		13301
		13302	for_each_crtc_in_state(state, crtc, crtc_state, i) {
		13303	ret = intel_crtc_wait_for_pending_flips(crtc);
		13304	if (ret)
		13305	return ret;
		13306
		13307	if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
		13308	flush_workqueue(dev_priv->wq);
		13309	}
		13310
		13311	ret = mutex_lock_interruptible(&dev->struct_mutex);
		13312	if (ret)
		13313	return ret;
		13314
		13315	ret = drm_atomic_helper_prepare_planes(dev, state);
		13316	if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
		13317	u32 reset_counter;
		13318
		13319	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
		13320	mutex_unlock(&dev->struct_mutex);
		13321
		13322	for_each_plane_in_state(state, plane, plane_state, i) {
		13323	struct intel_plane_state *intel_plane_state =
		13324	to_intel_plane_state(plane_state);
		13325
		13326	if (!intel_plane_state->wait_req)
		13327	continue;
		13328
		13329	ret = __i915_wait_request(intel_plane_state->wait_req,
		13330	reset_counter, true,
		13331	NULL, NULL);
		13332
		13333	/* Swallow -EIO errors to allow updates during hw lockup. */
		13334	if (ret == -EIO)
		13335	ret = 0;
		13336
		13337	if (ret)
		13338	break;
		13339	}
		13340
		13341	if (!ret)
		13342	return 0;
		13343
		13344	mutex_lock(&dev->struct_mutex);
		13345	drm_atomic_helper_cleanup_planes(dev, state);
		13346	}
		13347
		13348	mutex_unlock(&dev->struct_mutex);
		13349	return ret;
13167	}	13350	}
13168		13351
13169	/**	13352	/**
@@ -13187,22 +13370,20 @@ static int intel_atomic_commit(struct drm_device *dev, · 17 unmodified lines
13187	bool async)	13370	bool async)
13188	{	13371	{
13189	struct drm_i915_private *dev_priv = dev->dev_private;	13372	struct drm_i915_private *dev_priv = dev->dev_private;
13190	struct drm_crtc *crtc;
13191	struct drm_crtc_state *crtc_state;	13373	struct drm_crtc_state *crtc_state;
		13374	struct drm_crtc *crtc;
13192	int ret = 0;	13375	int ret = 0;
13193	int i;	13376	int i;
13194	bool any_ms = false;	13377	bool any_ms = false;
13195		13378
13196	if (async) {	13379	ret = intel_atomic_prepare_commit(dev, state, async);
13197	DRM_DEBUG_KMS("i915 does not yet support async commit\n");	13380	if (ret) {
13198	return -EINVAL;	13381	DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13199	}
13200
13201	ret = drm_atomic_helper_prepare_planes(dev, state);
13202	if (ret)
13203	return ret;	13382	return ret;
		13383	}
13204		13384
13205	drm_atomic_helper_swap_state(dev, state);	13385	drm_atomic_helper_swap_state(dev, state);
		13386	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13206		13387
13207	for_each_crtc_in_state(state, crtc, crtc_state, i) {	13388	for_each_crtc_in_state(state, crtc, crtc_state, i) {
13208	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	13389	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -13240,6 +13421,9 @@ static int intel_atomic_commit(struct drm_device *dev, · 31 unmodified lines
13240	to_intel_crtc_state(crtc->state)->update_pipe;	13421	to_intel_crtc_state(crtc->state)->update_pipe;
13241	unsigned long put_domains = 0;	13422	unsigned long put_domains = 0;
13242		13423
		13424	if (modeset)
		13425	intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
		13426
13243	if (modeset && crtc->state->active) {	13427	if (modeset && crtc->state->active) {
13244	update_scanline_offset(to_intel_crtc(crtc));	13428	update_scanline_offset(to_intel_crtc(crtc));
13245	dev_priv->display.crtc_enable(crtc);	13429	dev_priv->display.crtc_enable(crtc);
@@ -13255,18 +13439,26 @@ static int intel_atomic_commit(struct drm_device *dev, · 9 unmodified lines
13255	if (!modeset)	13439	if (!modeset)
13256	intel_pre_plane_update(intel_crtc);	13440	intel_pre_plane_update(intel_crtc);
13257		13441
13258	drm_atomic_helper_commit_planes_on_crtc(crtc_state);	13442	if (crtc->state->active &&
		13443	(crtc->state->planes_changed \|\| update_pipe))
		13444	drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13259		13445
13260	if (put_domains)	13446	if (put_domains)
13261	modeset_put_power_domains(dev_priv, put_domains);	13447	modeset_put_power_domains(dev_priv, put_domains);
13262		13448
13263	intel_post_plane_update(intel_crtc);	13449	intel_post_plane_update(intel_crtc);
		13450
		13451	if (modeset)
		13452	intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13264	}	13453	}
13265		13454
13266	/* FIXME: add subpixel order */	13455	/* FIXME: add subpixel order */
13267		13456
13268	drm_atomic_helper_wait_for_vblanks(dev, state);	13457	drm_atomic_helper_wait_for_vblanks(dev, state);
		13458
		13459	mutex_lock(&dev->struct_mutex);
13269	drm_atomic_helper_cleanup_planes(dev, state);	13460	drm_atomic_helper_cleanup_planes(dev, state);
		13461	mutex_unlock(&dev->struct_mutex);
13270		13462
13271	if (any_ms)	13463	if (any_ms)
13272	intel_modeset_check_state(dev, state);	13464	intel_modeset_check_state(dev, state);
@@ -13435,6 +13627,8 @@ static void intel_shared_dpll_init(struct drm_device *dev) · 162 unmodified lines
13435	* bits. Some older platforms need special physical address handling for	13627	* bits. Some older platforms need special physical address handling for
13436	* cursor planes.	13628	* cursor planes.
13437	*	13629	*
		13630	* Must be called with struct_mutex held.
		13631	*
13438	* Returns 0 on success, negative error code on failure.	13632	* Returns 0 on success, negative error code on failure.
13439	*/	13633	*/
13440	int	13634	int
@@ -13445,28 +13639,58 @@ intel_prepare_plane_fb(struct drm_plane *plane, · 4 unmodified lines
13445	struct drm_framebuffer *fb = new_state->fb;	13639	struct drm_framebuffer *fb = new_state->fb;
13446	struct intel_plane *intel_plane = to_intel_plane(plane);	13640	struct intel_plane *intel_plane = to_intel_plane(plane);
13447	struct drm_i915_gem_object *obj = intel_fb_obj(fb);	13641	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13448	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);	13642	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13449	int ret = 0;	13643	int ret = 0;
13450		13644
13451	if (!obj)	13645	if (!obj && !old_obj)
13452	return 0;	13646	return 0;
13453		13647
13454	mutex_lock(&dev->struct_mutex);	13648	if (old_obj) {
		13649	struct drm_crtc_state *crtc_state =
		13650	drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
		13651
		13652	/* Big Hammer, we also need to ensure that any pending
		13653	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
		13654	* current scanout is retired before unpinning the old
		13655	* framebuffer. Note that we rely on userspace rendering
		13656	* into the buffer attached to the pipe they are waiting
		13657	* on. If not, userspace generates a GPU hang with IPEHR
		13658	* point to the MI_WAIT_FOR_EVENT.
		13659	*
		13660	* This should only fail upon a hung GPU, in which case we
		13661	* can safely continue.
		13662	*/
		13663	if (needs_modeset(crtc_state))
		13664	ret = i915_gem_object_wait_rendering(old_obj, true);
		13665
		13666	/* Swallow -EIO errors to allow updates during hw lockup. */
		13667	if (ret && ret != -EIO)
		13668	return ret;
		13669	}
13455		13670
13456	if (plane->type == DRM_PLANE_TYPE_CURSOR &&	13671	if (!obj) {
		13672	ret = 0;
		13673	} else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13457	INTEL_INFO(dev)->cursor_needs_physical) {	13674	INTEL_INFO(dev)->cursor_needs_physical) {
13458	int align = IS_I830(dev) ? 16 * 1024 : 256;	13675	int align = IS_I830(dev) ? 16 * 1024 : 256;
13459	ret = i915_gem_object_attach_phys(obj, align);	13676	ret = i915_gem_object_attach_phys(obj, align);
13460	if (ret)	13677	if (ret)
13461	DRM_DEBUG_KMS("failed to attach phys object\n");	13678	DRM_DEBUG_KMS("failed to attach phys object\n");
13462	} else {	13679	} else {
13463	ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);	13680	ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13464	}	13681	}
13465		13682
13466	if (ret == 0)	13683	if (ret == 0) {
13467	i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);	13684	if (obj) {
		13685	struct intel_plane_state *plane_state =
		13686	to_intel_plane_state(new_state);
13468		13687
13469	mutex_unlock(&dev->struct_mutex);	13688	i915_gem_request_assign(&plane_state->wait_req,
		13689	obj->last_write_req);
		13690	}
		13691
		13692	i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
		13693	}
13470		13694
13471	return ret;	13695	return ret;
13472	}	13696	}
@@ -13477,23 +13701,35 @@ intel_prepare_plane_fb(struct drm_plane *plane, · 4 unmodified lines
13477	* @fb: old framebuffer that was on plane	13701	* @fb: old framebuffer that was on plane
13478	*	13702	*
13479	* Cleans up a framebuffer that has just been removed from a plane.	13703	* Cleans up a framebuffer that has just been removed from a plane.
		13704	*
		13705	* Must be called with struct_mutex held.
13480	*/	13706	*/
13481	void	13707	void
13482	intel_cleanup_plane_fb(struct drm_plane *plane,	13708	intel_cleanup_plane_fb(struct drm_plane *plane,
13483	const struct drm_plane_state *old_state)	13709	const struct drm_plane_state *old_state)
13484	{	13710	{
13485	struct drm_device *dev = plane->dev;	13711	struct drm_device *dev = plane->dev;
13486	struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);	13712	struct intel_plane *intel_plane = to_intel_plane(plane);
		13713	struct intel_plane_state *old_intel_state;
		13714	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
		13715	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13487		13716
13488	if (!obj)	13717	old_intel_state = to_intel_plane_state(old_state);
		13718
		13719	if (!obj && !old_obj)
13489	return;	13720	return;
13490		13721
13491	if (plane->type != DRM_PLANE_TYPE_CURSOR \|\|	13722	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR \|\|
13492	!INTEL_INFO(dev)->cursor_needs_physical) {	13723	!INTEL_INFO(dev)->cursor_needs_physical))
13493	mutex_lock(&dev->struct_mutex);
13494	intel_unpin_fb_obj(old_state->fb, old_state);	13724	intel_unpin_fb_obj(old_state->fb, old_state);
13495	mutex_unlock(&dev->struct_mutex);	13725
13496	}	13726	/* prepare_fb aborted? */
		13727	if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) \|\|
		13728	(obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
		13729	i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
		13730
		13731	i915_gem_request_assign(&old_intel_state->wait_req, NULL);
		13732
13497	}	13733	}
13498		13734
13499	int	13735	int
@@ -13512,7 +13748,7 @@ skl_max_scale(struct intel_crtc intel_crtc, struct intel_crtc_state crtc_state · 12 unmodified lines
13512	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;	13748	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13513	cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;	13749	cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13514		13750
13515	if (!crtc_clock \|\| !cdclk)	13751	if (WARN_ON_ONCE(!crtc_clock \|\| cdclk < crtc_clock))
13516	return DRM_PLANE_HELPER_NO_SCALING;	13752	return DRM_PLANE_HELPER_NO_SCALING;
13517		13753
13518	/*	13754	/*
@@ -13560,18 +13796,8 @@ intel_commit_primary_plane(struct drm_plane *plane, · 41 unmodified lines
13560	struct drm_framebuffer *fb = state->base.fb;	13796	struct drm_framebuffer *fb = state->base.fb;
13561	struct drm_device *dev = plane->dev;	13797	struct drm_device *dev = plane->dev;
13562	struct drm_i915_private *dev_priv = dev->dev_private;	13798	struct drm_i915_private *dev_priv = dev->dev_private;
13563	struct intel_crtc *intel_crtc;
13564	struct drm_rect *src = &state->src;
13565		13799
13566	crtc = crtc ? crtc : plane->crtc;	13800	crtc = crtc ? crtc : plane->crtc;
13567	intel_crtc = to_intel_crtc(crtc);
13568
13569	plane->fb = fb;
13570	crtc->x = src->x1 >> 16;
13571	crtc->y = src->y1 >> 16;
13572
13573	if (!crtc->state->active)
13574	return;
13575		13801
13576	dev_priv->display.update_primary_plane(crtc, fb,	13802	dev_priv->display.update_primary_plane(crtc, fb,
13577	state->src.x1 >> 16,	13803	state->src.x1 >> 16,
@@ -13601,8 +13827,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, · 23 unmodified lines
13601	intel_update_watermarks(crtc);	13827	intel_update_watermarks(crtc);
13602		13828
13603	/* Perform vblank evasion around commit operation */	13829	/* Perform vblank evasion around commit operation */
13604	if (crtc->state->active)	13830	intel_pipe_update_start(intel_crtc);
13605	intel_pipe_update_start(intel_crtc);
13606		13831
13607	if (modeset)	13832	if (modeset)
13608	return;	13833	return;
@@ -13618,8 +13843,7 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc, · 9 unmodified lines
13618	{	13843	{
13619	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	13844	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13620		13845
13621	if (crtc->state->active)	13846	intel_pipe_update_end(intel_crtc);
13622	intel_pipe_update_end(intel_crtc);
13623	}	13847	}
13624		13848
13625	/**	13849	/**
@@ -14087,7 +14311,7 @@ static void intel_setup_outputs(struct drm_device *dev) · 461 unmodified lines
14087	*/	14311	*/
14088	found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;	14312	found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14089	/* WaIgnoreDDIAStrap: skl */	14313	/* WaIgnoreDDIAStrap: skl */
14090	if (found \|\| IS_SKYLAKE(dev))	14314	if (found \|\| IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
14091	intel_ddi_init(dev, PORT_A);	14315	intel_ddi_init(dev, PORT_A);
14092		14316
14093	/* DDI B, C and D detection is indicated by the SFUSE_STRAP	14317	/* DDI B, C and D detection is indicated by the SFUSE_STRAP
@@ -14103,7 +14327,7 @@ static void intel_setup_outputs(struct drm_device *dev) · 9 unmodified lines
14103	/*	14327	/*
14104	* On SKL we don't have a way to detect DDI-E so we rely on VBT.	14328	* On SKL we don't have a way to detect DDI-E so we rely on VBT.
14105	*/	14329	*/
14106	if (IS_SKYLAKE(dev) &&	14330	if ((IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) &&
14107	(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp \|\|	14331	(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp \|\|
14108	dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi \|\|	14332	dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi \|\|
14109	dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))	14333	dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
@@ -14118,7 +14342,7 @@ static void intel_setup_outputs(struct drm_device *dev) · 8 unmodified lines
14118		14342
14119	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {	14343	if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14120	/* PCH SDVOB multiplex with HDMIB */	14344	/* PCH SDVOB multiplex with HDMIB */
14121	found = intel_sdvo_init(dev, PCH_SDVOB, true);	14345	found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14122	if (!found)	14346	if (!found)
14123	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);	14347	intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14124	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))	14348	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
@@ -14174,7 +14398,7 @@ static void intel_setup_outputs(struct drm_device *dev) · 49 unmodified lines
14174		14398
14175	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {	14399	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14176	DRM_DEBUG_KMS("probing SDVOB\n");	14400	DRM_DEBUG_KMS("probing SDVOB\n");
14177	found = intel_sdvo_init(dev, GEN3_SDVOB, true);	14401	found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14178	if (!found && IS_G4X(dev)) {	14402	if (!found && IS_G4X(dev)) {
14179	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");	14403	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14180	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);	14404	intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
@@ -14188,7 +14412,7 @@ static void intel_setup_outputs(struct drm_device *dev) · 7 unmodified lines
14188		14412
14189	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {	14413	if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14190	DRM_DEBUG_KMS("probing SDVOC\n");	14414	DRM_DEBUG_KMS("probing SDVOC\n");
14191	found = intel_sdvo_init(dev, GEN3_SDVOC, false);	14415	found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14192	}	14416	}
14193		14417
14194	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {	14418	if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
@@ -14454,8 +14678,9 @@ static int intel_framebuffer_init(struct drm_device *dev, · 259 unmodified lines
14454	static struct drm_framebuffer *	14678	static struct drm_framebuffer *
14455	intel_user_framebuffer_create(struct drm_device *dev,	14679	intel_user_framebuffer_create(struct drm_device *dev,
14456	struct drm_file *filp,	14680	struct drm_file *filp,
14457	struct drm_mode_fb_cmd2 *user_mode_cmd)	14681	const struct drm_mode_fb_cmd2 *user_mode_cmd)
14458	{	14682	{
		14683	struct drm_framebuffer *fb;
14459	struct drm_i915_gem_object *obj;	14684	struct drm_i915_gem_object *obj;
14460	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;	14685	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14461		14686
@@ -14464,7 +14689,11 @@ intel_user_framebuffer_create(struct drm_device *dev, · 2 unmodified lines
14464	if (&obj->base == NULL)	14689	if (&obj->base == NULL)
14465	return ERR_PTR(-ENOENT);	14690	return ERR_PTR(-ENOENT);
14466		14691
14467	return intel_framebuffer_create(dev, &mode_cmd, obj);	14692	fb = intel_framebuffer_create(dev, &mode_cmd, obj);
		14693	if (IS_ERR(fb))
		14694	drm_gem_object_unreference_unlocked(&obj->base);
		14695
		14696	return fb;
14468	}	14697	}
14469		14698
14470	#ifndef CONFIG_DRM_FBDEV_EMULATION	14699	#ifndef CONFIG_DRM_FBDEV_EMULATION
@@ -14549,7 +14778,7 @@ static void intel_init_display(struct drm_device *dev) · 78 unmodified lines
14549	}	14778	}
14550		14779
14551	/* Returns the core display clock speed */	14780	/* Returns the core display clock speed */
14552	if (IS_SKYLAKE(dev))	14781	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
14553	dev_priv->display.get_display_clock_speed =	14782	dev_priv->display.get_display_clock_speed =
14554	skylake_get_display_clock_speed;	14783	skylake_get_display_clock_speed;
14555	else if (IS_BROXTON(dev))	14784	else if (IS_BROXTON(dev))
@@ -14838,7 +15067,7 @@ static void i915_disable_vga(struct drm_device *dev) · 282 unmodified lines
14838	{	15067	{
14839	struct drm_i915_private *dev_priv = dev->dev_private;	15068	struct drm_i915_private *dev_priv = dev->dev_private;
14840	u8 sr1;	15069	u8 sr1;
14841	u32 vga_reg = i915_vgacntrl_reg(dev);	15070	i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
14842		15071
14843	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */	15072	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14844	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);	15073	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
@@ -14954,9 +15183,6 @@ void intel_modeset_init(struct drm_device *dev) · 109 unmodified lines
14954	i915_disable_vga(dev);	15183	i915_disable_vga(dev);
14955	intel_setup_outputs(dev);	15184	intel_setup_outputs(dev);
14956		15185
14957	/* Just in case the BIOS is doing something questionable. */
14958	intel_fbc_disable(dev_priv);
14959
14960	drm_modeset_lock_all(dev);	15186	drm_modeset_lock_all(dev);
14961	intel_modeset_setup_hw_state(dev);	15187	intel_modeset_setup_hw_state(dev);
14962	drm_modeset_unlock_all(dev);	15188	drm_modeset_unlock_all(dev);
@@ -15043,10 +15269,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) · 80 unmodified lines
15043	{	15269	{
15044	struct drm_device *dev = crtc->base.dev;	15270	struct drm_device *dev = crtc->base.dev;
15045	struct drm_i915_private *dev_priv = dev->dev_private;	15271	struct drm_i915_private *dev_priv = dev->dev_private;
15046	u32 reg;	15272	i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15047		15273
15048	/* Clear any frame start delays used for debugging left by the BIOS */	15274	/* Clear any frame start delays used for debugging left by the BIOS */
15049	reg = PIPECONF(crtc->config->cpu_transcoder);
15050	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);	15275	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15051		15276
15052	/* restore vblank interrupts to correct state */	15277	/* restore vblank interrupts to correct state */
@@ -15200,7 +15425,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) · 147 unmodified lines
15200	void i915_redisable_vga_power_on(struct drm_device *dev)	15425	void i915_redisable_vga_power_on(struct drm_device *dev)
15201	{	15426	{
15202	struct drm_i915_private *dev_priv = dev->dev_private;	15427	struct drm_i915_private *dev_priv = dev->dev_private;
15203	u32 vga_reg = i915_vgacntrl_reg(dev);	15428	i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15204		15429
15205	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {	15430	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15206	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");	15431	DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
@@ -15239,7 +15464,7 @@ static void readout_plane_state(struct intel_crtc *crtc) · 32 unmodified lines
15239	struct intel_plane_state *plane_state =	15464	struct intel_plane_state *plane_state =
15240	to_intel_plane_state(primary->state);	15465	to_intel_plane_state(primary->state);
15241		15466
15242	plane_state->visible =	15467	plane_state->visible = crtc->active &&
15243	primary_get_hw_state(to_intel_plane(primary));	15468	primary_get_hw_state(to_intel_plane(primary));
15244		15469
15245	if (plane_state->visible)	15470	if (plane_state->visible)
@@ -15496,8 +15721,7 @@ void intel_modeset_gem_init(struct drm_device *dev) · 250 unmodified lines
15496	mutex_lock(&dev->struct_mutex);	15721	mutex_lock(&dev->struct_mutex);
15497	ret = intel_pin_and_fence_fb_obj(c->primary,	15722	ret = intel_pin_and_fence_fb_obj(c->primary,
15498	c->primary->fb,	15723	c->primary->fb,
15499	c->primary->state,	15724	c->primary->state);
15500	NULL, NULL);
15501	mutex_unlock(&dev->struct_mutex);	15725	mutex_unlock(&dev->struct_mutex);
15502	if (ret) {	15726	if (ret) {
15503	DRM_ERROR("failed to pin boot fb on pipe %d\n",	15727	DRM_ERROR("failed to pin boot fb on pipe %d\n",

drivers/gpu/drm/i915/intel_dp.c+431−609

@@ -541,7 +541,8 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) · 540 unmodified lines
541	}	541	}
542	}	542	}
543		543
544	static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)	544	static i915_reg_t
		545	_pp_ctrl_reg(struct intel_dp *intel_dp)
545	{	546	{
546	struct drm_device *dev = intel_dp_to_dev(intel_dp);	547	struct drm_device *dev = intel_dp_to_dev(intel_dp);
547		548
@@ -553,7 +554,8 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) · 5 unmodified lines
553	return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));	554	return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
554	}	555	}
555		556
556	static u32 _pp_stat_reg(struct intel_dp *intel_dp)	557	static i915_reg_t
		558	_pp_stat_reg(struct intel_dp *intel_dp)
557	{	559	{
558	struct drm_device *dev = intel_dp_to_dev(intel_dp);	560	struct drm_device *dev = intel_dp_to_dev(intel_dp);
559		561
@@ -582,7 +584,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code, · 22 unmodified lines
582		584
583	if (IS_VALLEYVIEW(dev)) {	585	if (IS_VALLEYVIEW(dev)) {
584	enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);	586	enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
585	u32 pp_ctrl_reg, pp_div_reg;	587	i915_reg_t pp_ctrl_reg, pp_div_reg;
586	u32 pp_div;	588	u32 pp_div;
587		589
588	pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);	590	pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
@@ -652,7 +654,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) · 63 unmodified lines
652	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	654	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
653	struct drm_device *dev = intel_dig_port->base.base.dev;	655	struct drm_device *dev = intel_dig_port->base.base.dev;
654	struct drm_i915_private *dev_priv = dev->dev_private;	656	struct drm_i915_private *dev_priv = dev->dev_private;
655	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;	657	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
656	uint32_t status;	658	uint32_t status;
657	bool done;	659	bool done;
658		660
@@ -750,7 +752,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, · 91 unmodified lines
750	else	752	else
751	precharge = 5;	753	precharge = 5;
752		754
753	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)	755	if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
754	timeout = DP_AUX_CH_CTL_TIME_OUT_600us;	756	timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
755	else	757	else
756	timeout = DP_AUX_CH_CTL_TIME_OUT_400us;	758	timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -789,8 +791,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, · 32 unmodified lines
789	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	791	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
790	struct drm_device *dev = intel_dig_port->base.base.dev;	792	struct drm_device *dev = intel_dig_port->base.base.dev;
791	struct drm_i915_private *dev_priv = dev->dev_private;	793	struct drm_i915_private *dev_priv = dev->dev_private;
792	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;	794	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
793	uint32_t ch_data = ch_ctl + 4;
794	uint32_t aux_clock_divider;	795	uint32_t aux_clock_divider;
795	int i, ret, recv_bytes;	796	int i, ret, recv_bytes;
796	uint32_t status;	797	uint32_t status;
@@ -854,7 +855,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, · 57 unmodified lines
854	for (try = 0; try < 5; try++) {	855	for (try = 0; try < 5; try++) {
855	/* Load the send data into the aux channel data registers */	856	/* Load the send data into the aux channel data registers */
856	for (i = 0; i < send_bytes; i += 4)	857	for (i = 0; i < send_bytes; i += 4)
857	I915_WRITE(ch_data + i,	858	I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
858	intel_dp_pack_aux(send + i,	859	intel_dp_pack_aux(send + i,
859	send_bytes - i));	860	send_bytes - i));
860		861
@@ -918,7 +919,7 @@ done: · 57 unmodified lines
918	recv_bytes = recv_size;	919	recv_bytes = recv_size;
919		920
920	for (i = 0; i < recv_bytes; i += 4)	921	for (i = 0; i < recv_bytes; i += 4)
921	intel_dp_unpack_aux(I915_READ(ch_data + i),	922	intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
922	recv + i, recv_bytes - i);	923	recv + i, recv_bytes - i);
923		924
924	ret = recv_bytes;	925	ret = recv_bytes;
@@ -1005,96 +1006,206 @@ intel_dp_aux_transfer(struct drm_dp_aux aux, struct drm_dp_aux_msg msg) · 80 unmodified lines
1005	return ret;	1006	return ret;
1006	}	1007	}
1007		1008
1008	static void	1009	static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1009	intel_dp_aux_init(struct intel_dp intel_dp, struct intel_connector connector)	1010	enum port port)
1010	{	1011	{
1011	struct drm_device *dev = intel_dp_to_dev(intel_dp);	1012	switch (port) {
1012	struct drm_i915_private *dev_priv = dev->dev_private;	1013	case PORT_B:
1013	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	1014	case PORT_C:
1014	enum port port = intel_dig_port->port;	1015	case PORT_D:
1015	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];	1016	return DP_AUX_CH_CTL(port);
1016	const char *name = NULL;	1017	default:
1017	uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;	1018	MISSING_CASE(port);
1018	int ret;	1019	return DP_AUX_CH_CTL(PORT_B);
		1020	}
		1021	}
1019		1022
1020	/* On SKL we don't have Aux for port E so we rely on VBT to set	1023	static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1021	* a proper alternate aux channel.	1024	enum port port, int index)
1022	*/	1025	{
1023	if (IS_SKYLAKE(dev) && port == PORT_E) {	1026	switch (port) {
1024	switch (info->alternate_aux_channel) {	1027	case PORT_B:
1025	case DP_AUX_B:	1028	case PORT_C:
1026	porte_aux_ctl_reg = DPB_AUX_CH_CTL;	1029	case PORT_D:
1027	break;	1030	return DP_AUX_CH_DATA(port, index);
1028	case DP_AUX_C:	1031	default:
1029	porte_aux_ctl_reg = DPC_AUX_CH_CTL;	1032	MISSING_CASE(port);
1030	break;	1033	return DP_AUX_CH_DATA(PORT_B, index);
1031	case DP_AUX_D:
1032	porte_aux_ctl_reg = DPD_AUX_CH_CTL;
1033	break;
1034	case DP_AUX_A:
1035	default:
1036	porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1037	}
1038	}	1034	}
		1035	}
1039		1036
		1037	static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
		1038	enum port port)
		1039	{
1040	switch (port) {	1040	switch (port) {
1041	case PORT_A:	1041	case PORT_A:
1042	intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;	1042	return DP_AUX_CH_CTL(port);
1043	name = "DPDDC-A";
1044	break;
1045	case PORT_B:	1043	case PORT_B:
1046	intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1047	name = "DPDDC-B";
1048	break;
1049	case PORT_C:	1044	case PORT_C:
1050	intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1051	name = "DPDDC-C";
1052	break;
1053	case PORT_D:	1045	case PORT_D:
1054	intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;	1046	return PCH_DP_AUX_CH_CTL(port);
1055	name = "DPDDC-D";
1056	break;
1057	case PORT_E:
1058	intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
1059	name = "DPDDC-E";
1060	break;
1061	default:	1047	default:
1062	BUG();	1048	MISSING_CASE(port);
		1049	return DP_AUX_CH_CTL(PORT_A);
1063	}	1050	}
		1051	}
1064		1052
1065	/*	1053	static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1066	* The AUX_CTL register is usually DP_CTL + 0x10.	1054	enum port port, int index)
1067	*	1055	{
1068	* On Haswell and Broadwell though:	1056	switch (port) {
1069	* - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU	1057	case PORT_A:
1070	* - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU	1058	return DP_AUX_CH_DATA(port, index);
1071	*	1059	case PORT_B:
1072	* Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.	1060	case PORT_C:
1073	*/	1061	case PORT_D:
1074	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)	1062	return PCH_DP_AUX_CH_DATA(port, index);
1075	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;	1063	default:
		1064	MISSING_CASE(port);
		1065	return DP_AUX_CH_DATA(PORT_A, index);
		1066	}
		1067	}
		1068
		1069	/*
		1070	* On SKL we don't have Aux for port E so we rely
		1071	* on VBT to set a proper alternate aux channel.
		1072	*/
		1073	static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
		1074	{
		1075	const struct ddi_vbt_port_info *info =
		1076	&dev_priv->vbt.ddi_port_info[PORT_E];
		1077
		1078	switch (info->alternate_aux_channel) {
		1079	case DP_AUX_A:
		1080	return PORT_A;
		1081	case DP_AUX_B:
		1082	return PORT_B;
		1083	case DP_AUX_C:
		1084	return PORT_C;
		1085	case DP_AUX_D:
		1086	return PORT_D;
		1087	default:
		1088	MISSING_CASE(info->alternate_aux_channel);
		1089	return PORT_A;
		1090	}
		1091	}
		1092
		1093	static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
		1094	enum port port)
		1095	{
		1096	if (port == PORT_E)
		1097	port = skl_porte_aux_port(dev_priv);
		1098
		1099	switch (port) {
		1100	case PORT_A:
		1101	case PORT_B:
		1102	case PORT_C:
		1103	case PORT_D:
		1104	return DP_AUX_CH_CTL(port);
		1105	default:
		1106	MISSING_CASE(port);
		1107	return DP_AUX_CH_CTL(PORT_A);
		1108	}
		1109	}
		1110
		1111	static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
		1112	enum port port, int index)
		1113	{
		1114	if (port == PORT_E)
		1115	port = skl_porte_aux_port(dev_priv);
		1116
		1117	switch (port) {
		1118	case PORT_A:
		1119	case PORT_B:
		1120	case PORT_C:
		1121	case PORT_D:
		1122	return DP_AUX_CH_DATA(port, index);
		1123	default:
		1124	MISSING_CASE(port);
		1125	return DP_AUX_CH_DATA(PORT_A, index);
		1126	}
		1127	}
		1128
		1129	static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
		1130	enum port port)
		1131	{
		1132	if (INTEL_INFO(dev_priv)->gen >= 9)
		1133	return skl_aux_ctl_reg(dev_priv, port);
		1134	else if (HAS_PCH_SPLIT(dev_priv))
		1135	return ilk_aux_ctl_reg(dev_priv, port);
		1136	else
		1137	return g4x_aux_ctl_reg(dev_priv, port);
		1138	}
		1139
		1140	static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
		1141	enum port port, int index)
		1142	{
		1143	if (INTEL_INFO(dev_priv)->gen >= 9)
		1144	return skl_aux_data_reg(dev_priv, port, index);
		1145	else if (HAS_PCH_SPLIT(dev_priv))
		1146	return ilk_aux_data_reg(dev_priv, port, index);
		1147	else
		1148	return g4x_aux_data_reg(dev_priv, port, index);
		1149	}
		1150
		1151	static void intel_aux_reg_init(struct intel_dp *intel_dp)
		1152	{
		1153	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
		1154	enum port port = dp_to_dig_port(intel_dp)->port;
		1155	int i;
		1156
		1157	intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
		1158	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
		1159	intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
		1160	}
		1161
		1162	static void
		1163	intel_dp_aux_fini(struct intel_dp *intel_dp)
		1164	{
		1165	drm_dp_aux_unregister(&intel_dp->aux);
		1166	kfree(intel_dp->aux.name);
		1167	}
		1168
		1169	static int
		1170	intel_dp_aux_init(struct intel_dp intel_dp, struct intel_connector connector)
		1171	{
		1172	struct drm_device *dev = intel_dp_to_dev(intel_dp);
		1173	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
		1174	enum port port = intel_dig_port->port;
		1175	int ret;
		1176
		1177	intel_aux_reg_init(intel_dp);
		1178
		1179	intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
		1180	if (!intel_dp->aux.name)
		1181	return -ENOMEM;
1076		1182
1077	intel_dp->aux.name = name;
1078	intel_dp->aux.dev = dev->dev;	1183	intel_dp->aux.dev = dev->dev;
1079	intel_dp->aux.transfer = intel_dp_aux_transfer;	1184	intel_dp->aux.transfer = intel_dp_aux_transfer;
1080		1185
1081	DRM_DEBUG_KMS("registering %s bus for %s\n", name,	1186	DRM_DEBUG_KMS("registering %s bus for %s\n",
		1187	intel_dp->aux.name,
1082	connector->base.kdev->kobj.name);	1188	connector->base.kdev->kobj.name);
1083		1189
1084	ret = drm_dp_aux_register(&intel_dp->aux);	1190	ret = drm_dp_aux_register(&intel_dp->aux);
1085	if (ret < 0) {	1191	if (ret < 0) {
1086	DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",	1192	DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1087	name, ret);	1193	intel_dp->aux.name, ret);
1088	return;	1194	kfree(intel_dp->aux.name);
		1195	return ret;
1089	}	1196	}
1090		1197
1091	ret = sysfs_create_link(&connector->base.kdev->kobj,	1198	ret = sysfs_create_link(&connector->base.kdev->kobj,
1092	&intel_dp->aux.ddc.dev.kobj,	1199	&intel_dp->aux.ddc.dev.kobj,
1093	intel_dp->aux.ddc.dev.kobj.name);	1200	intel_dp->aux.ddc.dev.kobj.name);
1094	if (ret < 0) {	1201	if (ret < 0) {
1095	DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);	1202	DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1096	drm_dp_aux_unregister(&intel_dp->aux);	1203	intel_dp->aux.name, ret);
		1204	intel_dp_aux_fini(intel_dp);
		1205	return ret;
1097	}	1206	}
		1207
		1208	return 0;
1098	}	1209	}
1099		1210
1100	static void	1211	static void
@@ -1186,10 +1297,13 @@ intel_dp_sink_rates(struct intel_dp intel_dp, const int *sink_rates) · 85 unmodified lines
1186	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;	1297	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1187	}	1298	}
1188		1299
1189	static bool intel_dp_source_supports_hbr2(struct drm_device *dev)	1300	bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1190	{	1301	{
		1302	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1303	struct drm_device *dev = dig_port->base.base.dev;
		1304
1191	/* WaDisableHBR2:skl */	1305	/* WaDisableHBR2:skl */
1192	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)	1306	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1193	return false;	1307	return false;
1194		1308
1195	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) \|\| IS_BROADWELL(dev) \|\|	1309	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) \|\| IS_BROADWELL(dev) \|\|
@@ -1200,14 +1314,16 @@ static bool intel_dp_source_supports_hbr2(struct drm_device *dev) · 4 unmodified lines
1200	}	1314	}
1201		1315
1202	static int	1316	static int
1203	intel_dp_source_rates(struct drm_device dev, const int *source_rates)	1317	intel_dp_source_rates(struct intel_dp intel_dp, const int *source_rates)
1204	{	1318	{
		1319	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		1320	struct drm_device *dev = dig_port->base.base.dev;
1205	int size;	1321	int size;
1206		1322
1207	if (IS_BROXTON(dev)) {	1323	if (IS_BROXTON(dev)) {
1208	*source_rates = bxt_rates;	1324	*source_rates = bxt_rates;
1209	size = ARRAY_SIZE(bxt_rates);	1325	size = ARRAY_SIZE(bxt_rates);
1210	} else if (IS_SKYLAKE(dev)) {	1326	} else if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
1211	*source_rates = skl_rates;	1327	*source_rates = skl_rates;
1212	size = ARRAY_SIZE(skl_rates);	1328	size = ARRAY_SIZE(skl_rates);
1213	} else {	1329	} else {
@@ -1216,7 +1332,7 @@ intel_dp_source_rates(struct drm_device dev, const int *source_rates) · 2 unmodified lines
1216	}	1332	}
1217		1333
1218	/* This depends on the fact that 5.4 is last value in the array */	1334	/* This depends on the fact that 5.4 is last value in the array */
1219	if (!intel_dp_source_supports_hbr2(dev))	1335	if (!intel_dp_source_supports_hbr2(intel_dp))
1220	size--;	1336	size--;
1221		1337
1222	return size;	1338	return size;
@@ -1281,12 +1397,11 @@ static int intersect_rates(const int *source_rates, int source_len, · 58 unmodified lines
1281	static int intel_dp_common_rates(struct intel_dp *intel_dp,	1397	static int intel_dp_common_rates(struct intel_dp *intel_dp,
1282	int *common_rates)	1398	int *common_rates)
1283	{	1399	{
1284	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1285	const int source_rates, sink_rates;	1400	const int source_rates, sink_rates;
1286	int source_len, sink_len;	1401	int source_len, sink_len;
1287		1402
1288	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);	1403	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1289	source_len = intel_dp_source_rates(dev, &source_rates);	1404	source_len = intel_dp_source_rates(intel_dp, &source_rates);
1290		1405
1291	return intersect_rates(source_rates, source_len,	1406	return intersect_rates(source_rates, source_len,
1292	sink_rates, sink_len,	1407	sink_rates, sink_len,
@@ -1311,7 +1426,6 @@ static void snprintf_int_array(char *str, size_t len, · 18 unmodified lines
1311		1426
1312	static void intel_dp_print_rates(struct intel_dp *intel_dp)	1427	static void intel_dp_print_rates(struct intel_dp *intel_dp)
1313	{	1428	{
1314	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1315	const int source_rates, sink_rates;	1429	const int source_rates, sink_rates;
1316	int source_len, sink_len, common_len;	1430	int source_len, sink_len, common_len;
1317	int common_rates[DP_MAX_SUPPORTED_RATES];	1431	int common_rates[DP_MAX_SUPPORTED_RATES];
@@ -1320,7 +1434,7 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) · 2 unmodified lines
1320	if ((drm_debug & DRM_UT_KMS) == 0)	1434	if ((drm_debug & DRM_UT_KMS) == 0)
1321	return;	1435	return;
1322		1436
1323	source_len = intel_dp_source_rates(dev, &source_rates);	1437	source_len = intel_dp_source_rates(intel_dp, &source_rates);
1324	snprintf_int_array(str, sizeof(str), source_rates, source_len);	1438	snprintf_int_array(str, sizeof(str), source_rates, source_len);
1325	DRM_DEBUG_KMS("source rates: %s\n", str);	1439	DRM_DEBUG_KMS("source rates: %s\n", str);
1326		1440
@@ -1362,8 +1476,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) · 35 unmodified lines
1362	return rate_to_index(rate, intel_dp->sink_rates);	1476	return rate_to_index(rate, intel_dp->sink_rates);
1363	}	1477	}
1364		1478
1365	static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,	1479	void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1366	uint8_t link_bw, uint8_t rate_select)	1480	uint8_t link_bw, uint8_t rate_select)
1367	{	1481	{
1368	if (intel_dp->num_sink_rates) {	1482	if (intel_dp->num_sink_rates) {
1369	*link_bw = 0;	1483	*link_bw = 0;
@@ -1423,7 +1537,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 53 unmodified lines
1423	return ret;	1537	return ret;
1424	}	1538	}
1425		1539
1426	if (!HAS_PCH_SPLIT(dev))	1540	if (HAS_GMCH_DISPLAY(dev))
1427	intel_gmch_panel_fitting(intel_crtc, pipe_config,	1541	intel_gmch_panel_fitting(intel_crtc, pipe_config,
1428	intel_connector->panel.fitting_mode);	1542	intel_connector->panel.fitting_mode);
1429	else	1543	else
@@ -1527,7 +1641,7 @@ found: · 97 unmodified lines
1527	&pipe_config->dp_m2_n2);	1641	&pipe_config->dp_m2_n2);
1528	}	1642	}
1529		1643
1530	if (IS_SKYLAKE(dev) && is_edp(intel_dp))	1644	if ((IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) && is_edp(intel_dp))
1531	skl_edp_set_pll_config(pipe_config);	1645	skl_edp_set_pll_config(pipe_config);
1532	else if (IS_BROXTON(dev))	1646	else if (IS_BROXTON(dev))
1533	/* handled in ddi */;	1647	/* handled in ddi */;
@@ -1539,37 +1653,6 @@ found: · 5 unmodified lines
1539	return true;	1653	return true;
1540	}	1654	}
1541		1655
1542	static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1543	{
1544	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1545	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1546	struct drm_device *dev = crtc->base.dev;
1547	struct drm_i915_private *dev_priv = dev->dev_private;
1548	u32 dpa_ctl;
1549
1550	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1551	crtc->config->port_clock);
1552	dpa_ctl = I915_READ(DP_A);
1553	dpa_ctl &= ~DP_PLL_FREQ_MASK;
1554
1555	if (crtc->config->port_clock == 162000) {
1556	/* For a long time we've carried around a ILK-DevA w/a for the
1557	* 160MHz clock. If we're really unlucky, it's still required.
1558	*/
1559	DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1560	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
1561	intel_dp->DP \|= DP_PLL_FREQ_160MHZ;
1562	} else {
1563	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
1564	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
1565	}
1566
1567	I915_WRITE(DP_A, dpa_ctl);
1568
1569	POSTING_READ(DP_A);
1570	udelay(500);
1571	}
1572
1573	void intel_dp_set_link_params(struct intel_dp *intel_dp,	1656	void intel_dp_set_link_params(struct intel_dp *intel_dp,
1574	const struct intel_crtc_state *pipe_config)	1657	const struct intel_crtc_state *pipe_config)
1575	{	1658	{
@@ -1614,9 +1697,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder) · 38 unmodified lines
1614	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;	1697	intel_dp->DP \|= DP_VOLTAGE_0_4 \| DP_PRE_EMPHASIS_0;
1615	intel_dp->DP \|= DP_PORT_WIDTH(crtc->config->lane_count);	1698	intel_dp->DP \|= DP_PORT_WIDTH(crtc->config->lane_count);
1616		1699
1617	if (crtc->config->has_audio)
1618	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
1619
1620	/* Split out the IBX/CPU vs CPT settings */	1700	/* Split out the IBX/CPU vs CPT settings */
1621		1701
1622	if (IS_GEN7(dev) && port == PORT_A) {	1702	if (IS_GEN7(dev) && port == PORT_A) {
@@ -1677,7 +1757,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, · 54 unmodified lines
1677	{	1757	{
1678	struct drm_device *dev = intel_dp_to_dev(intel_dp);	1758	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1679	struct drm_i915_private *dev_priv = dev->dev_private;	1759	struct drm_i915_private *dev_priv = dev->dev_private;
1680	u32 pp_stat_reg, pp_ctrl_reg;	1760	i915_reg_t pp_stat_reg, pp_ctrl_reg;
1681		1761
1682	lockdep_assert_held(&dev_priv->pps_mutex);	1762	lockdep_assert_held(&dev_priv->pps_mutex);
1683		1763
@@ -1767,7 +1847,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) · 83 unmodified lines
1767	struct drm_i915_private *dev_priv = dev->dev_private;	1847	struct drm_i915_private *dev_priv = dev->dev_private;
1768	enum intel_display_power_domain power_domain;	1848	enum intel_display_power_domain power_domain;
1769	u32 pp;	1849	u32 pp;
1770	u32 pp_stat_reg, pp_ctrl_reg;	1850	i915_reg_t pp_stat_reg, pp_ctrl_reg;
1771	bool need_to_disable = !intel_dp->want_panel_vdd;	1851	bool need_to_disable = !intel_dp->want_panel_vdd;
1772		1852
1773	lockdep_assert_held(&dev_priv->pps_mutex);	1853	lockdep_assert_held(&dev_priv->pps_mutex);
@@ -1843,7 +1923,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) · 69 unmodified lines
1843	struct intel_encoder *intel_encoder = &intel_dig_port->base;	1923	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1844	enum intel_display_power_domain power_domain;	1924	enum intel_display_power_domain power_domain;
1845	u32 pp;	1925	u32 pp;
1846	u32 pp_stat_reg, pp_ctrl_reg;	1926	i915_reg_t pp_stat_reg, pp_ctrl_reg;
1847		1927
1848	lockdep_assert_held(&dev_priv->pps_mutex);	1928	lockdep_assert_held(&dev_priv->pps_mutex);
1849		1929
@@ -1930,7 +2010,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) · 80 unmodified lines
1930	struct drm_device *dev = intel_dp_to_dev(intel_dp);	2010	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1931	struct drm_i915_private *dev_priv = dev->dev_private;	2011	struct drm_i915_private *dev_priv = dev->dev_private;
1932	u32 pp;	2012	u32 pp;
1933	u32 pp_ctrl_reg;	2013	i915_reg_t pp_ctrl_reg;
1934		2014
1935	lockdep_assert_held(&dev_priv->pps_mutex);	2015	lockdep_assert_held(&dev_priv->pps_mutex);
1936		2016
@@ -1992,7 +2072,7 @@ static void edp_panel_off(struct intel_dp *intel_dp) · 55 unmodified lines
1992	struct drm_i915_private *dev_priv = dev->dev_private;	2072	struct drm_i915_private *dev_priv = dev->dev_private;
1993	enum intel_display_power_domain power_domain;	2073	enum intel_display_power_domain power_domain;
1994	u32 pp;	2074	u32 pp;
1995	u32 pp_ctrl_reg;	2075	i915_reg_t pp_ctrl_reg;
1996		2076
1997	lockdep_assert_held(&dev_priv->pps_mutex);	2077	lockdep_assert_held(&dev_priv->pps_mutex);
1998		2078
@@ -2043,7 +2123,7 @@ static void _intel_edp_backlight_on(struct intel_dp *intel_dp) · 44 unmodified lines
2043	struct drm_device *dev = intel_dig_port->base.base.dev;	2123	struct drm_device *dev = intel_dig_port->base.base.dev;
2044	struct drm_i915_private *dev_priv = dev->dev_private;	2124	struct drm_i915_private *dev_priv = dev->dev_private;
2045	u32 pp;	2125	u32 pp;
2046	u32 pp_ctrl_reg;	2126	i915_reg_t pp_ctrl_reg;
2047		2127
2048	/*	2128	/*
2049	* If we enable the backlight right away following a panel power	2129	* If we enable the backlight right away following a panel power
@@ -2084,7 +2164,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp) · 34 unmodified lines
2084	struct drm_device *dev = intel_dp_to_dev(intel_dp);	2164	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2085	struct drm_i915_private *dev_priv = dev->dev_private;	2165	struct drm_i915_private *dev_priv = dev->dev_private;
2086	u32 pp;	2166	u32 pp;
2087	u32 pp_ctrl_reg;	2167	i915_reg_t pp_ctrl_reg;
2088		2168
2089	if (!is_edp(intel_dp))	2169	if (!is_edp(intel_dp))
2090	return;	2170	return;
@@ -2143,27 +2223,61 @@ static void intel_edp_backlight_power(struct intel_connector *connector, · 52 unmodified lines
2143	_intel_edp_backlight_off(intel_dp);	2223	_intel_edp_backlight_off(intel_dp);
2144	}	2224	}
2145		2225
		2226	static const char *state_string(bool enabled)
		2227	{
		2228	return enabled ? "on" : "off";
		2229	}
		2230
		2231	static void assert_dp_port(struct intel_dp *intel_dp, bool state)
		2232	{
		2233	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		2234	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
		2235	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
		2236
		2237	I915_STATE_WARN(cur_state != state,
		2238	"DP port %c state assertion failure (expected %s, current %s)\n",
		2239	port_name(dig_port->port),
		2240	state_string(state), state_string(cur_state));
		2241	}
		2242	#define assert_dp_port_disabled(d) assert_dp_port((d), false)
		2243
		2244	static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
		2245	{
		2246	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
		2247
		2248	I915_STATE_WARN(cur_state != state,
		2249	"eDP PLL state assertion failure (expected %s, current %s)\n",
		2250	state_string(state), state_string(cur_state));
		2251	}
		2252	#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
		2253	#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
		2254
2146	static void ironlake_edp_pll_on(struct intel_dp *intel_dp)	2255	static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2147	{	2256	{
2148	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	2257	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2149	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;	2258	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2150	struct drm_device *dev = crtc->dev;	2259	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2151	struct drm_i915_private *dev_priv = dev->dev_private;
2152	u32 dpa_ctl;
2153		2260
2154	assert_pipe_disabled(dev_priv,	2261	assert_pipe_disabled(dev_priv, crtc->pipe);
2155	to_intel_crtc(crtc)->pipe);	2262	assert_dp_port_disabled(intel_dp);
		2263	assert_edp_pll_disabled(dev_priv);
		2264
		2265	DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
		2266	crtc->config->port_clock);
		2267
		2268	intel_dp->DP &= ~DP_PLL_FREQ_MASK;
		2269
		2270	if (crtc->config->port_clock == 162000)
		2271	intel_dp->DP \|= DP_PLL_FREQ_162MHZ;
		2272	else
		2273	intel_dp->DP \|= DP_PLL_FREQ_270MHZ;
		2274
		2275	I915_WRITE(DP_A, intel_dp->DP);
		2276	POSTING_READ(DP_A);
		2277	udelay(500);
2156		2278
2157	DRM_DEBUG_KMS("\n");
2158	dpa_ctl = I915_READ(DP_A);
2159	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2160	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2161
2162	/* We don't adjust intel_dp->DP while tearing down the link, to
2163	* facilitate link retraining (e.g. after hotplug). Hence clear all
2164	* enable bits here to ensure that we don't enable too much. */
2165	intel_dp->DP &= ~(DP_PORT_EN \| DP_AUDIO_OUTPUT_ENABLE);
2166	intel_dp->DP \|= DP_PLL_ENABLE;	2279	intel_dp->DP \|= DP_PLL_ENABLE;
		2280
2167	I915_WRITE(DP_A, intel_dp->DP);	2281	I915_WRITE(DP_A, intel_dp->DP);
2168	POSTING_READ(DP_A);	2282	POSTING_READ(DP_A);
2169	udelay(200);	2283	udelay(200);
@@ -2172,24 +2286,18 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp) · 2 unmodified lines
2172	static void ironlake_edp_pll_off(struct intel_dp *intel_dp)	2286	static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2173	{	2287	{
2174	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	2288	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2175	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;	2289	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2176	struct drm_device *dev = crtc->dev;	2290	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2177	struct drm_i915_private *dev_priv = dev->dev_private;	2291
2178	u32 dpa_ctl;	2292	assert_pipe_disabled(dev_priv, crtc->pipe);
		2293	assert_dp_port_disabled(intel_dp);
		2294	assert_edp_pll_enabled(dev_priv);
2179		2295
2180	assert_pipe_disabled(dev_priv,	2296	DRM_DEBUG_KMS("disabling eDP PLL\n");
2181	to_intel_crtc(crtc)->pipe);
2182		2297
2183	dpa_ctl = I915_READ(DP_A);	2298	intel_dp->DP &= ~DP_PLL_ENABLE;
2184	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2185	"dp pll off, should be on\n");
2186	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2187		2299
2188	/* We can't rely on the value tracked for the DP register in	2300	I915_WRITE(DP_A, intel_dp->DP);
2189	* intel_dp->DP because link_down must not change that (otherwise link
2190	* re-training will fail. */
2191	dpa_ctl &= ~DP_PLL_ENABLE;
2192	I915_WRITE(DP_A, dpa_ctl);
2193	POSTING_READ(DP_A);	2301	POSTING_READ(DP_A);
2194	udelay(200);	2302	udelay(200);
2195	}	2303	}
@@ -2258,7 +2366,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, · 62 unmodified lines
2258	}	2366	}
2259		2367
2260	DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",	2368	DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2261	intel_dp->output_reg);	2369	i915_mmio_reg_offset(intel_dp->output_reg));
2262	} else if (IS_CHERRYVIEW(dev)) {	2370	} else if (IS_CHERRYVIEW(dev)) {
2263	*pipe = DP_PORT_TO_PIPE_CHV(tmp);	2371	*pipe = DP_PORT_TO_PIPE_CHV(tmp);
2264	} else {	2372	} else {
@@ -2321,7 +2429,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, · 56 unmodified lines
2321	intel_dp_get_m_n(crtc, pipe_config);	2429	intel_dp_get_m_n(crtc, pipe_config);
2322		2430
2323	if (port == PORT_A) {	2431	if (port == PORT_A) {
2324	if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)	2432	if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2325	pipe_config->port_clock = 162000;	2433	pipe_config->port_clock = 162000;
2326	else	2434	else
2327	pipe_config->port_clock = 270000;	2435	pipe_config->port_clock = 270000;
@@ -2386,6 +2494,8 @@ static void ilk_post_disable_dp(struct intel_encoder *encoder) · 58 unmodified lines
2386	enum port port = dp_to_dig_port(intel_dp)->port;	2494	enum port port = dp_to_dig_port(intel_dp)->port;
2387		2495
2388	intel_dp_link_down(intel_dp);	2496	intel_dp_link_down(intel_dp);
		2497
		2498	/* Only ilk+ has port A */
2389	if (port == PORT_A)	2499	if (port == PORT_A)
2390	ironlake_edp_pll_off(intel_dp);	2500	ironlake_edp_pll_off(intel_dp);
2391	}	2501	}
@@ -2545,6 +2655,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp) · 153 unmodified lines
2545	{	2655	{
2546	struct drm_device *dev = intel_dp_to_dev(intel_dp);	2656	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2547	struct drm_i915_private *dev_priv = dev->dev_private;	2657	struct drm_i915_private *dev_priv = dev->dev_private;
		2658	struct intel_crtc *crtc =
		2659	to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2548		2660
2549	/* enable with pattern 1 (as per spec) */	2661	/* enable with pattern 1 (as per spec) */
2550	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,	2662	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
@@ -2560,6 +2672,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp) · 9 unmodified lines
2560	* fail when the power sequencer is freshly used for this port.	2672	* fail when the power sequencer is freshly used for this port.
2561	*/	2673	*/
2562	intel_dp->DP \|= DP_PORT_EN;	2674	intel_dp->DP \|= DP_PORT_EN;
		2675	if (crtc->config->has_audio)
		2676	intel_dp->DP \|= DP_AUDIO_OUTPUT_ENABLE;
2563		2677
2564	I915_WRITE(intel_dp->output_reg, intel_dp->DP);	2678	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2565	POSTING_READ(intel_dp->output_reg);	2679	POSTING_READ(intel_dp->output_reg);
@@ -2572,6 +2686,8 @@ static void intel_enable_dp(struct intel_encoder *encoder) · 6 unmodified lines
2572	struct drm_i915_private *dev_priv = dev->dev_private;	2686	struct drm_i915_private *dev_priv = dev->dev_private;
2573	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);	2687	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2574	uint32_t dp_reg = I915_READ(intel_dp->output_reg);	2688	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
		2689	enum port port = dp_to_dig_port(intel_dp)->port;
		2690	enum pipe pipe = crtc->pipe;
2575		2691
2576	if (WARN_ON(dp_reg & DP_PORT_EN))	2692	if (WARN_ON(dp_reg & DP_PORT_EN))
2577	return;	2693	return;
@@ -2583,6 +2699,17 @@ static void intel_enable_dp(struct intel_encoder *encoder) · 5 unmodified lines
2583		2699
2584	intel_dp_enable_port(intel_dp);	2700	intel_dp_enable_port(intel_dp);
2585		2701
		2702	if (port == PORT_A && IS_GEN5(dev_priv)) {
		2703	/*
		2704	* Underrun reporting for the other pipe was disabled in
		2705	* g4x_pre_enable_dp(). The eDP PLL and port have now been
		2706	* enabled, so it's now safe to re-enable underrun reporting.
		2707	*/
		2708	intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
		2709	intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
		2710	intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
		2711	}
		2712
2586	edp_panel_vdd_on(intel_dp);	2713	edp_panel_vdd_on(intel_dp);
2587	edp_panel_on(intel_dp);	2714	edp_panel_on(intel_dp);
2588	edp_panel_vdd_off(intel_dp, true);	2715	edp_panel_vdd_off(intel_dp, true);
@@ -2605,7 +2732,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) · 16 unmodified lines
2605		2732
2606	if (crtc->config->has_audio) {	2733	if (crtc->config->has_audio) {
2607	DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",	2734	DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2608	pipe_name(crtc->pipe));	2735	pipe_name(pipe));
2609	intel_audio_codec_enable(encoder);	2736	intel_audio_codec_enable(encoder);
2610	}	2737	}
2611	}	2738	}
@@ -2628,16 +2755,29 @@ static void vlv_enable_dp(struct intel_encoder *encoder) · 16 unmodified lines
2628		2755
2629	static void g4x_pre_enable_dp(struct intel_encoder *encoder)	2756	static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2630	{	2757	{
		2758	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2631	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);	2759	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2632	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);	2760	enum port port = dp_to_dig_port(intel_dp)->port;
		2761	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2633		2762
2634	intel_dp_prepare(encoder);	2763	intel_dp_prepare(encoder);
2635		2764
		2765	if (port == PORT_A && IS_GEN5(dev_priv)) {
		2766	/*
		2767	* We get FIFO underruns on the other pipe when
		2768	* enabling the CPU eDP PLL, and when enabling CPU
		2769	* eDP port. We could potentially avoid the PLL
		2770	* underrun with a vblank wait just prior to enabling
		2771	* the PLL, but that doesn't appear to help the port
		2772	* enable case. Just sweep it all under the rug.
		2773	*/
		2774	intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
		2775	intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
		2776	}
		2777
2636	/* Only ilk+ has port A */	2778	/* Only ilk+ has port A */
2637	if (dport->port == PORT_A) {	2779	if (port == PORT_A)
2638	ironlake_set_pll_cpu_edp(intel_dp);
2639	ironlake_edp_pll_on(intel_dp);	2780	ironlake_edp_pll_on(intel_dp);
2640	}
2641	}	2781	}
2642		2782
2643	static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)	2783	static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
@@ -2645,7 +2785,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) · 1 unmodified line
2645	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	2785	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2646	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;	2786	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2647	enum pipe pipe = intel_dp->pps_pipe;	2787	enum pipe pipe = intel_dp->pps_pipe;
2648	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);	2788	i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2649		2789
2650	edp_panel_vdd_off_sync(intel_dp);	2790	edp_panel_vdd_off_sync(intel_dp);
2651		2791
@@ -3043,7 +3183,7 @@ intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, · 391 unmodified lines
3043	* Fetch AUX CH registers 0x202 - 0x207 which contain	3183	* Fetch AUX CH registers 0x202 - 0x207 which contain
3044	* link status information	3184	* link status information
3045	*/	3185	*/
3046	static bool	3186	bool
3047	intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])	3187	intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3048	{	3188	{
3049	return intel_dp_dpcd_read_wake(&intel_dp->aux,	3189	return intel_dp_dpcd_read_wake(&intel_dp->aux,
@@ -3053,7 +3193,7 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ · 3 unmodified lines
3053	}	3193	}
3054		3194
3055	/* These are source-specific values. */	3195	/* These are source-specific values. */
3056	static uint8_t	3196	uint8_t
3057	intel_dp_voltage_max(struct intel_dp *intel_dp)	3197	intel_dp_voltage_max(struct intel_dp *intel_dp)
3058	{	3198	{
3059	struct drm_device *dev = intel_dp_to_dev(intel_dp);	3199	struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -3076,7 +3216,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) · 16 unmodified lines
3076	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;	3216	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3077	}	3217	}
3078		3218
3079	static uint8_t	3219	uint8_t
3080	intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)	3220	intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3081	{	3221	{
3082	struct drm_device *dev = intel_dp_to_dev(intel_dp);	3222	struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -3418,38 +3558,6 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) · 335 unmodified lines
3418	return 0;	3558	return 0;
3419	}	3559	}
3420		3560
3421	static void
3422	intel_get_adjust_train(struct intel_dp *intel_dp,
3423	const uint8_t link_status[DP_LINK_STATUS_SIZE])
3424	{
3425	uint8_t v = 0;
3426	uint8_t p = 0;
3427	int lane;
3428	uint8_t voltage_max;
3429	uint8_t preemph_max;
3430
3431	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3432	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3433	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3434
3435	if (this_v > v)
3436	v = this_v;
3437	if (this_p > p)
3438	p = this_p;
3439	}
3440
3441	voltage_max = intel_dp_voltage_max(intel_dp);
3442	if (v >= voltage_max)
3443	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
3444
3445	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3446	if (p >= preemph_max)
3447	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3448
3449	for (lane = 0; lane < 4; lane++)
3450	intel_dp->train_set[lane] = v \| p;
3451	}
3452
3453	static uint32_t	3561	static uint32_t
3454	gen4_signal_levels(uint8_t train_set)	3562	gen4_signal_levels(uint8_t train_set)
3455	{	3563	{
@@ -3547,13 +3655,13 @@ gen7_edp_signal_levels(uint8_t train_set) · 91 unmodified lines
3547	}	3655	}
3548	}	3656	}
3549		3657
3550	/* Properly updates "DP" with the correct signal levels. */	3658	void
3551	static void	3659	intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3552	intel_dp_set_signal_levels(struct intel_dp intel_dp, uint32_t DP)
3553	{	3660	{
3554	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	3661	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3555	enum port port = intel_dig_port->port;	3662	enum port port = intel_dig_port->port;
3556	struct drm_device *dev = intel_dig_port->base.base.dev;	3663	struct drm_device *dev = intel_dig_port->base.base.dev;
		3664	struct drm_i915_private *dev_priv = to_i915(dev);
3557	uint32_t signal_levels, mask = 0;	3665	uint32_t signal_levels, mask = 0;
3558	uint8_t train_set = intel_dp->train_set[0];	3666	uint8_t train_set = intel_dp->train_set[0];
3559		3667
@@ -3588,74 +3696,27 @@ intel_dp_set_signal_levels(struct intel_dp intel_dp, uint32_t DP) · 28 unmodified lines
3588	(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>	3696	(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3589	DP_TRAIN_PRE_EMPHASIS_SHIFT);	3697	DP_TRAIN_PRE_EMPHASIS_SHIFT);
3590		3698
3591	DP = (DP & ~mask) \| signal_levels;	3699	intel_dp->DP = (intel_dp->DP & ~mask) \| signal_levels;
3592	}
3593		3700
3594	static bool	3701	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3595	intel_dp_set_link_train(struct intel_dp *intel_dp,
3596	uint32_t *DP,
3597	uint8_t dp_train_pat)
3598	{
3599	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3600	struct drm_i915_private *dev_priv =
3601	to_i915(intel_dig_port->base.base.dev);
3602	uint8_t buf[sizeof(intel_dp->train_set) + 1];
3603	int ret, len;
3604
3605	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3606
3607	I915_WRITE(intel_dp->output_reg, *DP);
3608	POSTING_READ(intel_dp->output_reg);	3702	POSTING_READ(intel_dp->output_reg);
3609
3610	buf[0] = dp_train_pat;
3611	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3612	DP_TRAINING_PATTERN_DISABLE) {
3613	/* don't write DP_TRAINING_LANEx_SET on disable */
3614	len = 1;
3615	} else {
3616	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3617	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3618	len = intel_dp->lane_count + 1;
3619	}
3620
3621	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3622	buf, len);
3623
3624	return ret == len;
3625	}
3626
3627	static bool
3628	intel_dp_reset_link_train(struct intel_dp intel_dp, uint32_t DP,
3629	uint8_t dp_train_pat)
3630	{
3631	if (!intel_dp->train_set_valid)
3632	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3633	intel_dp_set_signal_levels(intel_dp, DP);
3634	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3635	}	3703	}
3636		3704
3637	static bool	3705	void
3638	intel_dp_update_link_train(struct intel_dp intel_dp, uint32_t DP,	3706	intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3639	const uint8_t link_status[DP_LINK_STATUS_SIZE])	3707	uint8_t dp_train_pat)
3640	{	3708	{
3641	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	3709	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3642	struct drm_i915_private *dev_priv =	3710	struct drm_i915_private *dev_priv =
3643	to_i915(intel_dig_port->base.base.dev);	3711	to_i915(intel_dig_port->base.base.dev);
3644	int ret;
3645		3712
3646	intel_get_adjust_train(intel_dp, link_status);	3713	_intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3647	intel_dp_set_signal_levels(intel_dp, DP);
3648		3714
3649	I915_WRITE(intel_dp->output_reg, *DP);	3715	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3650	POSTING_READ(intel_dp->output_reg);	3716	POSTING_READ(intel_dp->output_reg);
3651
3652	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3653	intel_dp->train_set, intel_dp->lane_count);
3654
3655	return ret == intel_dp->lane_count;
3656	}	3717	}
3657		3718
3658	static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)	3719	void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3659	{	3720	{
3660	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	3721	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3661	struct drm_device *dev = intel_dig_port->base.base.dev;	3722	struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -3686,232 +3747,6 @@ static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) · 24 unmodified lines
3686	DRM_ERROR("Timed out waiting for DP idle patterns\n");	3747	DRM_ERROR("Timed out waiting for DP idle patterns\n");
3687	}	3748	}
3688		3749
3689	/* Enable corresponding port and start training pattern 1 */
3690	static void
3691	intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
3692	{
3693	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3694	struct drm_device *dev = encoder->dev;
3695	int i;
3696	uint8_t voltage;
3697	int voltage_tries, loop_tries;
3698	uint32_t DP = intel_dp->DP;
3699	uint8_t link_config[2];
3700	uint8_t link_bw, rate_select;
3701
3702	if (HAS_DDI(dev))
3703	intel_ddi_prepare_link_retrain(encoder);
3704
3705	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
3706	&link_bw, &rate_select);
3707
3708	/* Write the link configuration data */
3709	link_config[0] = link_bw;
3710	link_config[1] = intel_dp->lane_count;
3711	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3712	link_config[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3713	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3714	if (intel_dp->num_sink_rates)
3715	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3716	&rate_select, 1);
3717
3718	link_config[0] = 0;
3719	link_config[1] = DP_SET_ANSI_8B10B;
3720	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3721
3722	DP \|= DP_PORT_EN;
3723
3724	/* clock recovery */
3725	if (!intel_dp_reset_link_train(intel_dp, &DP,
3726	DP_TRAINING_PATTERN_1 \|
3727	DP_LINK_SCRAMBLING_DISABLE)) {
3728	DRM_ERROR("failed to enable link training\n");
3729	return;
3730	}
3731
3732	voltage = 0xff;
3733	voltage_tries = 0;
3734	loop_tries = 0;
3735	for (;;) {
3736	uint8_t link_status[DP_LINK_STATUS_SIZE];
3737
3738	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3739	if (!intel_dp_get_link_status(intel_dp, link_status)) {
3740	DRM_ERROR("failed to get link status\n");
3741	break;
3742	}
3743
3744	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3745	DRM_DEBUG_KMS("clock recovery OK\n");
3746	break;
3747	}
3748
3749	/*
3750	* if we used previously trained voltage and pre-emphasis values
3751	* and we don't get clock recovery, reset link training values
3752	*/
3753	if (intel_dp->train_set_valid) {
3754	DRM_DEBUG_KMS("clock recovery not ok, reset");
3755	/* clear the flag as we are not reusing train set */
3756	intel_dp->train_set_valid = false;
3757	if (!intel_dp_reset_link_train(intel_dp, &DP,
3758	DP_TRAINING_PATTERN_1 \|
3759	DP_LINK_SCRAMBLING_DISABLE)) {
3760	DRM_ERROR("failed to enable link training\n");
3761	return;
3762	}
3763	continue;
3764	}
3765
3766	/* Check to see if we've tried the max voltage */
3767	for (i = 0; i < intel_dp->lane_count; i++)
3768	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3769	break;
3770	if (i == intel_dp->lane_count) {
3771	++loop_tries;
3772	if (loop_tries == 5) {
3773	DRM_ERROR("too many full retries, give up\n");
3774	break;
3775	}
3776	intel_dp_reset_link_train(intel_dp, &DP,
3777	DP_TRAINING_PATTERN_1 \|
3778	DP_LINK_SCRAMBLING_DISABLE);
3779	voltage_tries = 0;
3780	continue;
3781	}
3782
3783	/* Check to see if we've tried the same voltage 5 times */
3784	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3785	++voltage_tries;
3786	if (voltage_tries == 5) {
3787	DRM_ERROR("too many voltage retries, give up\n");
3788	break;
3789	}
3790	} else
3791	voltage_tries = 0;
3792	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3793
3794	/* Update training set as requested by target */
3795	if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3796	DRM_ERROR("failed to update link training\n");
3797	break;
3798	}
3799	}
3800
3801	intel_dp->DP = DP;
3802	}
3803
3804	static void
3805	intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
3806	{
3807	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3808	struct drm_device *dev = dig_port->base.base.dev;
3809	bool channel_eq = false;
3810	int tries, cr_tries;
3811	uint32_t DP = intel_dp->DP;
3812	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3813
3814	/*
3815	* Training Pattern 3 for HBR2 or 1.2 devices that support it.
3816	*
3817	* Intel platforms that support HBR2 also support TPS3. TPS3 support is
3818	* also mandatory for downstream devices that support HBR2.
3819	*
3820	* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
3821	* supported but still not enabled.
3822	*/
3823	if (intel_dp_source_supports_hbr2(dev) &&
3824	drm_dp_tps3_supported(intel_dp->dpcd))
3825	training_pattern = DP_TRAINING_PATTERN_3;
3826	else if (intel_dp->link_rate == 540000)
3827	DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
3828
3829	/* channel equalization */
3830	if (!intel_dp_set_link_train(intel_dp, &DP,
3831	training_pattern \|
3832	DP_LINK_SCRAMBLING_DISABLE)) {
3833	DRM_ERROR("failed to start channel equalization\n");
3834	return;
3835	}
3836
3837	tries = 0;
3838	cr_tries = 0;
3839	channel_eq = false;
3840	for (;;) {
3841	uint8_t link_status[DP_LINK_STATUS_SIZE];
3842
3843	if (cr_tries > 5) {
3844	DRM_ERROR("failed to train DP, aborting\n");
3845	break;
3846	}
3847
3848	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3849	if (!intel_dp_get_link_status(intel_dp, link_status)) {
3850	DRM_ERROR("failed to get link status\n");
3851	break;
3852	}
3853
3854	/* Make sure clock is still ok */
3855	if (!drm_dp_clock_recovery_ok(link_status,
3856	intel_dp->lane_count)) {
3857	intel_dp->train_set_valid = false;
3858	intel_dp_link_training_clock_recovery(intel_dp);
3859	intel_dp_set_link_train(intel_dp, &DP,
3860	training_pattern \|
3861	DP_LINK_SCRAMBLING_DISABLE);
3862	cr_tries++;
3863	continue;
3864	}
3865
3866	if (drm_dp_channel_eq_ok(link_status,
3867	intel_dp->lane_count)) {
3868	channel_eq = true;
3869	break;
3870	}
3871
3872	/* Try 5 times, then try clock recovery if that fails */
3873	if (tries > 5) {
3874	intel_dp->train_set_valid = false;
3875	intel_dp_link_training_clock_recovery(intel_dp);
3876	intel_dp_set_link_train(intel_dp, &DP,
3877	training_pattern \|
3878	DP_LINK_SCRAMBLING_DISABLE);
3879	tries = 0;
3880	cr_tries++;
3881	continue;
3882	}
3883
3884	/* Update training set as requested by target */
3885	if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3886	DRM_ERROR("failed to update link training\n");
3887	break;
3888	}
3889	++tries;
3890	}
3891
3892	intel_dp_set_idle_link_train(intel_dp);
3893
3894	intel_dp->DP = DP;
3895
3896	if (channel_eq) {
3897	intel_dp->train_set_valid = true;
3898	DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3899	}
3900	}
3901
3902	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3903	{
3904	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3905	DP_TRAINING_PATTERN_DISABLE);
3906	}
3907
3908	void
3909	intel_dp_start_link_train(struct intel_dp *intel_dp)
3910	{
3911	intel_dp_link_training_clock_recovery(intel_dp);
3912	intel_dp_link_training_channel_equalization(intel_dp);
3913	}
3914
3915	static void	3750	static void
3916	intel_dp_link_down(struct intel_dp *intel_dp)	3751	intel_dp_link_down(struct intel_dp *intel_dp)
3917	{	3752	{
@@ -3954,6 +3789,13 @@ intel_dp_link_down(struct intel_dp *intel_dp) · 36 unmodified lines
3954	* matching HDMI port to be enabled on transcoder A.	3789	* matching HDMI port to be enabled on transcoder A.
3955	*/	3790	*/
3956	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {	3791	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
		3792	/*
		3793	* We get CPU/PCH FIFO underruns on the other pipe when
		3794	* doing the workaround. Sweep them under the rug.
		3795	*/
		3796	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		3797	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		3798
3957	/* always enable with pattern 1 (as per spec) */	3799	/* always enable with pattern 1 (as per spec) */
3958	DP &= ~(DP_PIPEB_SELECT \| DP_LINK_TRAIN_MASK);	3800	DP &= ~(DP_PIPEB_SELECT \| DP_LINK_TRAIN_MASK);
3959	DP \|= DP_PORT_EN \| DP_LINK_TRAIN_PAT_1;	3801	DP \|= DP_PORT_EN \| DP_LINK_TRAIN_PAT_1;
@@ -3963,9 +3805,15 @@ intel_dp_link_down(struct intel_dp *intel_dp) · 3 unmodified lines
3963	DP &= ~DP_PORT_EN;	3805	DP &= ~DP_PORT_EN;
3964	I915_WRITE(intel_dp->output_reg, DP);	3806	I915_WRITE(intel_dp->output_reg, DP);
3965	POSTING_READ(intel_dp->output_reg);	3807	POSTING_READ(intel_dp->output_reg);
		3808
		3809	intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
		3810	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		3811	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3966	}	3812	}
3967		3813
3968	msleep(intel_dp->panel_power_down_delay);	3814	msleep(intel_dp->panel_power_down_delay);
		3815
		3816	intel_dp->DP = DP;
3969	}	3817	}
3970		3818
3971	static bool	3819	static bool
@@ -4013,7 +3861,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) · 41 unmodified lines
4013	}	3861	}
4014		3862
4015	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",	3863	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4016	yesno(intel_dp_source_supports_hbr2(dev)),	3864	yesno(intel_dp_source_supports_hbr2(intel_dp)),
4017	yesno(drm_dp_tps3_supported(intel_dp->dpcd)));	3865	yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4018		3866
4019	/* Intermediate frequency support */	3867	/* Intermediate frequency support */
@@ -4103,9 +3951,12 @@ intel_dp_probe_mst(struct intel_dp *intel_dp) · 83 unmodified lines
4103	static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)	3951	static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
4104	{	3952	{
4105	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);	3953	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		3954	struct drm_device *dev = dig_port->base.base.dev;
4106	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);	3955	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4107	u8 buf;	3956	u8 buf;
4108	int ret = 0;	3957	int ret = 0;
		3958	int count = 0;
		3959	int attempts = 10;
4109		3960
4110	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {	3961	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
4111	DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");	3962	DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
@@ -4120,7 +3971,22 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) · 8 unmodified lines
4120	goto out;	3971	goto out;
4121	}	3972	}
4122		3973
4123	intel_dp->sink_crc.started = false;	3974	do {
		3975	intel_wait_for_vblank(dev, intel_crtc->pipe);
		3976
		3977	if (drm_dp_dpcd_readb(&intel_dp->aux,
		3978	DP_TEST_SINK_MISC, &buf) < 0) {
		3979	ret = -EIO;
		3980	goto out;
		3981	}
		3982	count = buf & DP_TEST_COUNT_MASK;
		3983	} while (--attempts && count);
		3984
		3985	if (attempts == 0) {
		3986	DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
		3987	ret = -ETIMEDOUT;
		3988	}
		3989
4124	out:	3990	out:
4125	hsw_enable_ips(intel_crtc);	3991	hsw_enable_ips(intel_crtc);
4126	return ret;	3992	return ret;
@@ -4129,27 +3995,26 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) · 2 unmodified lines
4129	static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)	3995	static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
4130	{	3996	{
4131	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);	3997	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
		3998	struct drm_device *dev = dig_port->base.base.dev;
4132	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);	3999	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4133	u8 buf;	4000	u8 buf;
4134	int ret;	4001	int ret;
4135		4002
4136	if (intel_dp->sink_crc.started) {
4137	ret = intel_dp_sink_crc_stop(intel_dp);
4138	if (ret)
4139	return ret;
4140	}
4141
4142	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)	4003	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4143	return -EIO;	4004	return -EIO;
4144		4005
4145	if (!(buf & DP_TEST_CRC_SUPPORTED))	4006	if (!(buf & DP_TEST_CRC_SUPPORTED))
4146	return -ENOTTY;	4007	return -ENOTTY;
4147		4008
4148	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
4149
4150	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)	4009	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4151	return -EIO;	4010	return -EIO;
4152		4011
		4012	if (buf & DP_TEST_SINK_START) {
		4013	ret = intel_dp_sink_crc_stop(intel_dp);
		4014	if (ret)
		4015	return ret;
		4016	}
		4017
4153	hsw_disable_ips(intel_crtc);	4018	hsw_disable_ips(intel_crtc);
4154		4019
4155	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,	4020	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
@@ -4158,7 +4023,7 @@ static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) · 2 unmodified lines
4158	return -EIO;	4023	return -EIO;
4159	}	4024	}
4160		4025
4161	intel_dp->sink_crc.started = true;	4026	intel_wait_for_vblank(dev, intel_crtc->pipe);
4162	return 0;	4027	return 0;
4163	}	4028	}
4164		4029
@@ -4170,7 +4035,6 @@ int intel_dp_sink_crc(struct intel_dp intel_dp, u8 crc) · 5 unmodified lines
4170	u8 buf;	4035	u8 buf;
4171	int count, ret;	4036	int count, ret;
4172	int attempts = 6;	4037	int attempts = 6;
4173	bool old_equal_new;
4174		4038
4175	ret = intel_dp_sink_crc_start(intel_dp);	4039	ret = intel_dp_sink_crc_start(intel_dp);
4176	if (ret)	4040	if (ret)
@@ -4186,35 +4050,17 @@ int intel_dp_sink_crc(struct intel_dp intel_dp, u8 crc) · 9 unmodified lines
4186	}	4050	}
4187	count = buf & DP_TEST_COUNT_MASK;	4051	count = buf & DP_TEST_COUNT_MASK;
4188		4052
4189	/*	4053	} while (--attempts && count == 0);
4190	* Count might be reset during the loop. In this case
4191	* last known count needs to be reset as well.
4192	*/
4193	if (count == 0)
4194	intel_dp->sink_crc.last_count = 0;
4195
4196	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4197	ret = -EIO;
4198	goto stop;
4199	}
4200
4201	old_equal_new = (count == intel_dp->sink_crc.last_count &&
4202	!memcmp(intel_dp->sink_crc.last_crc, crc,
4203	6 * sizeof(u8)));
4204
4205	} while (--attempts && (count == 0 \|\| old_equal_new));
4206
4207	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
4208	memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
4209		4054
4210	if (attempts == 0) {	4055	if (attempts == 0) {
4211	if (old_equal_new) {	4056	DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4212	DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");	4057	ret = -ETIMEDOUT;
4213	} else {	4058	goto stop;
4214	DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");	4059	}
4215	ret = -ETIMEDOUT;	4060
4216	goto stop;	4061	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4217	}	4062	ret = -EIO;
		4063	goto stop;
4218	}	4064	}
4219		4065
4220	stop:	4066	stop:
@@ -4314,13 +4160,6 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) · 93 unmodified lines
4314	uint8_t rxdata = 0;	4160	uint8_t rxdata = 0;
4315	int status = 0;	4161	int status = 0;
4316		4162
4317	intel_dp->compliance_test_active = 0;
4318	intel_dp->compliance_test_type = 0;
4319	intel_dp->compliance_test_data = 0;
4320
4321	intel_dp->aux.i2c_nack_count = 0;
4322	intel_dp->aux.i2c_defer_count = 0;
4323
4324	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);	4163	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4325	if (status <= 0) {	4164	if (status <= 0) {
4326	DRM_DEBUG_KMS("Could not read test request from sink\n");	4165	DRM_DEBUG_KMS("Could not read test request from sink\n");
@@ -4436,6 +4275,14 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) · 109 unmodified lines
4436		4275
4437	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));	4276	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4438		4277
		4278	/*
		4279	* Clearing compliance test variables to allow capturing
		4280	* of values for next automated test request.
		4281	*/
		4282	intel_dp->compliance_test_active = 0;
		4283	intel_dp->compliance_test_type = 0;
		4284	intel_dp->compliance_test_data = 0;
		4285
4439	if (!intel_encoder->base.crtc)	4286	if (!intel_encoder->base.crtc)
4440	return;	4287	return;
4441		4288
@@ -4466,7 +4313,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) · 24 unmodified lines
4466	DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");	4313	DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4467	}	4314	}
4468		4315
4469	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {	4316	/* if link training is requested we should perform it always */
		4317	if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) \|\|
		4318	(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4470	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",	4319	DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4471	intel_encoder->base.name);	4320	intel_encoder->base.name);
4472	intel_dp_start_link_train(intel_dp);	4321	intel_dp_start_link_train(intel_dp);
@@ -4684,41 +4533,6 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv, · 211 unmodified lines
4684	return g4x_digital_port_connected(dev_priv, port);	4533	return g4x_digital_port_connected(dev_priv, port);
4685	}	4534	}
4686		4535
4687	static enum drm_connector_status
4688	ironlake_dp_detect(struct intel_dp *intel_dp)
4689	{
4690	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4691	struct drm_i915_private *dev_priv = dev->dev_private;
4692	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4693
4694	if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4695	return connector_status_disconnected;
4696
4697	return intel_dp_detect_dpcd(intel_dp);
4698	}
4699
4700	static enum drm_connector_status
4701	g4x_dp_detect(struct intel_dp *intel_dp)
4702	{
4703	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4704	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4705
4706	/* Can't disconnect eDP, but you can close the lid... */
4707	if (is_edp(intel_dp)) {
4708	enum drm_connector_status status;
4709
4710	status = intel_panel_detect(dev);
4711	if (status == connector_status_unknown)
4712	status = connector_status_connected;
4713	return status;
4714	}
4715
4716	if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
4717	return connector_status_disconnected;
4718
4719	return intel_dp_detect_dpcd(intel_dp);
4720	}
4721
4722	static struct edid *	4536	static struct edid *
4723	intel_dp_get_edid(struct intel_dp *intel_dp)	4537	intel_dp_get_edid(struct intel_dp *intel_dp)
4724	{	4538	{
@@ -4791,12 +4605,19 @@ intel_dp_detect(struct drm_connector *connector, bool force) · 66 unmodified lines
4791	/* Can't disconnect eDP, but you can close the lid... */	4605	/* Can't disconnect eDP, but you can close the lid... */
4792	if (is_edp(intel_dp))	4606	if (is_edp(intel_dp))
4793	status = edp_detect(intel_dp);	4607	status = edp_detect(intel_dp);
4794	else if (HAS_PCH_SPLIT(dev))	4608	else if (intel_digital_port_connected(to_i915(dev),
4795	status = ironlake_dp_detect(intel_dp);	4609	dp_to_dig_port(intel_dp)))
		4610	status = intel_dp_detect_dpcd(intel_dp);
4796	else	4611	else
4797	status = g4x_dp_detect(intel_dp);	4612	status = connector_status_disconnected;
4798	if (status != connector_status_connected)	4613
		4614	if (status != connector_status_connected) {
		4615	intel_dp->compliance_test_active = 0;
		4616	intel_dp->compliance_test_type = 0;
		4617	intel_dp->compliance_test_data = 0;
		4618
4799	goto out;	4619	goto out;
		4620	}
4800		4621
4801	intel_dp_probe_oui(intel_dp);	4622	intel_dp_probe_oui(intel_dp);
4802		4623
@@ -4810,6 +4631,14 @@ intel_dp_detect(struct drm_connector *connector, bool force) · 7 unmodified lines
4810	goto out;	4631	goto out;
4811	}	4632	}
4812		4633
		4634	/*
		4635	* Clearing NACK and defer counts to get their exact values
		4636	* while reading EDID which are required by Compliance tests
		4637	* 4.2.2.4 and 4.2.2.5
		4638	*/
		4639	intel_dp->aux.i2c_nack_count = 0;
		4640	intel_dp->aux.i2c_defer_count = 0;
		4641
4813	intel_dp_set_edid(intel_dp);	4642	intel_dp_set_edid(intel_dp);
4814		4643
4815	if (intel_encoder->type != INTEL_OUTPUT_EDP)	4644	if (intel_encoder->type != INTEL_OUTPUT_EDP)
@@ -5014,7 +4843,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) · 198 unmodified lines
5014	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);	4843	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5015	struct intel_dp *intel_dp = &intel_dig_port->dp;	4844	struct intel_dp *intel_dp = &intel_dig_port->dp;
5016		4845
5017	drm_dp_aux_unregister(&intel_dp->aux);	4846	intel_dp_aux_fini(intel_dp);
5018	intel_dp_mst_encoder_cleanup(intel_dig_port);	4847	intel_dp_mst_encoder_cleanup(intel_dig_port);
5019	if (is_edp(intel_dp)) {	4848	if (is_edp(intel_dp)) {
5020	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);	4849	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
@@ -5204,25 +5033,6 @@ put_power: · 183 unmodified lines
5204	return ret;	5033	return ret;
5205	}	5034	}
5206		5035
5207	/* Return which DP Port should be selected for Transcoder DP control */
5208	int
5209	intel_trans_dp_port_sel(struct drm_crtc *crtc)
5210	{
5211	struct drm_device *dev = crtc->dev;
5212	struct intel_encoder *intel_encoder;
5213	struct intel_dp *intel_dp;
5214
5215	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5216	intel_dp = enc_to_intel_dp(&intel_encoder->base);
5217
5218	if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT \|\|
5219	intel_encoder->type == INTEL_OUTPUT_EDP)
5220	return intel_dp->output_reg;
5221	}
5222
5223	return -1;
5224	}
5225
5226	/* check the VBT to see whether the eDP is on another port */	5036	/* check the VBT to see whether the eDP is on another port */
5227	bool intel_dp_is_edp(struct drm_device *dev, enum port port)	5037	bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5228	{	5038	{
@@ -5294,7 +5104,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev, · 65 unmodified lines
5294	struct edp_power_seq cur, vbt, spec,	5104	struct edp_power_seq cur, vbt, spec,
5295	*final = &intel_dp->pps_delays;	5105	*final = &intel_dp->pps_delays;
5296	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;	5106	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5297	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;	5107	i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
5298		5108
5299	lockdep_assert_held(&dev_priv->pps_mutex);	5109	lockdep_assert_held(&dev_priv->pps_mutex);
5300		5110
@@ -5416,7 +5226,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, · 115 unmodified lines
5416	struct drm_i915_private *dev_priv = dev->dev_private;	5226	struct drm_i915_private *dev_priv = dev->dev_private;
5417	u32 pp_on, pp_off, pp_div, port_sel = 0;	5227	u32 pp_on, pp_off, pp_div, port_sel = 0;
5418	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);	5228	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5419	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;	5229	i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
5420	enum port port = dp_to_dig_port(intel_dp)->port;	5230	enum port port = dp_to_dig_port(intel_dp)->port;
5421	const struct edp_power_seq *seq = &intel_dp->pps_delays;	5231	const struct edp_power_seq *seq = &intel_dp->pps_delays;
5422		5232
@@ -5578,7 +5388,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) · 155 unmodified lines
5578	DRM_ERROR("Unsupported refreshrate type\n");	5388	DRM_ERROR("Unsupported refreshrate type\n");
5579	}	5389	}
5580	} else if (INTEL_INFO(dev)->gen > 6) {	5390	} else if (INTEL_INFO(dev)->gen > 6) {
5581	u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);	5391	i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5582	u32 val;	5392	u32 val;
5583		5393
5584	val = I915_READ(reg);	5394	val = I915_READ(reg);
@@ -5996,7 +5806,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 411 unmodified lines
5996	struct drm_device *dev = intel_encoder->base.dev;	5806	struct drm_device *dev = intel_encoder->base.dev;
5997	struct drm_i915_private *dev_priv = dev->dev_private;	5807	struct drm_i915_private *dev_priv = dev->dev_private;
5998	enum port port = intel_dig_port->port;	5808	enum port port = intel_dig_port->port;
5999	int type;	5809	int type, ret;
6000		5810
6001	intel_dp->pps_pipe = INVALID_PIPE;	5811	intel_dp->pps_pipe = INVALID_PIPE;
6002		5812
@@ -6017,6 +5827,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 14 unmodified lines
6017	else	5827	else
6018	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;	5828	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
6019		5829
		5830	if (HAS_DDI(dev))
		5831	intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
		5832
6020	/* Preserve the current hw state. */	5833	/* Preserve the current hw state. */
6021	intel_dp->DP = I915_READ(intel_dp->output_reg);	5834	intel_dp->DP = I915_READ(intel_dp->output_reg);
6022	intel_dp->attached_connector = intel_connector;	5835	intel_dp->attached_connector = intel_connector;
@@ -6068,7 +5881,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 45 unmodified lines
6068	break;	5881	break;
6069	case PORT_B:	5882	case PORT_B:
6070	intel_encoder->hpd_pin = HPD_PORT_B;	5883	intel_encoder->hpd_pin = HPD_PORT_B;
6071	if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))	5884	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
6072	intel_encoder->hpd_pin = HPD_PORT_A;	5885	intel_encoder->hpd_pin = HPD_PORT_A;
6073	break;	5886	break;
6074	case PORT_C:	5887	case PORT_C:
@@ -6094,7 +5907,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 19 unmodified lines
6094	pps_unlock(intel_dp);	5907	pps_unlock(intel_dp);
6095	}	5908	}
6096		5909
6097	intel_dp_aux_init(intel_dp, intel_connector);	5910	ret = intel_dp_aux_init(intel_dp, intel_connector);
		5911	if (ret)
		5912	goto fail;
6098		5913
6099	/* init MST on ports that can support it */	5914	/* init MST on ports that can support it */
6100	if (HAS_DP_MST(dev) &&	5915	if (HAS_DP_MST(dev) &&
@@ -6103,20 +5918,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 2 unmodified lines
6103	intel_connector->base.base.id);	5918	intel_connector->base.base.id);
6104		5919
6105	if (!intel_edp_init_connector(intel_dp, intel_connector)) {	5920	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6106	drm_dp_aux_unregister(&intel_dp->aux);	5921	intel_dp_aux_fini(intel_dp);
6107	if (is_edp(intel_dp)) {	5922	intel_dp_mst_encoder_cleanup(intel_dig_port);
6108	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);	5923	goto fail;
6109	/*
6110	* vdd might still be enabled do to the delayed vdd off.
6111	* Make sure vdd is actually turned off here.
6112	*/
6113	pps_lock(intel_dp);
6114	edp_panel_vdd_off_sync(intel_dp);
6115	pps_unlock(intel_dp);
6116	}
6117	drm_connector_unregister(connector);
6118	drm_connector_cleanup(connector);
6119	return false;
6120	}	5924	}
6121		5925
6122	intel_dp_add_properties(intel_dp, connector);	5926	intel_dp_add_properties(intel_dp, connector);
@@ -6133,10 +5937,27 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 10 unmodified lines
6133	i915_debugfs_connector_add(connector);	5937	i915_debugfs_connector_add(connector);
6134		5938
6135	return true;	5939	return true;
		5940
		5941	fail:
		5942	if (is_edp(intel_dp)) {
		5943	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		5944	/*
		5945	* vdd might still be enabled do to the delayed vdd off.
		5946	* Make sure vdd is actually turned off here.
		5947	*/
		5948	pps_lock(intel_dp);
		5949	edp_panel_vdd_off_sync(intel_dp);
		5950	pps_unlock(intel_dp);
		5951	}
		5952	drm_connector_unregister(connector);
		5953	drm_connector_cleanup(connector);
		5954
		5955	return false;
6136	}	5956	}
6137		5957
6138	void	5958	void
6139	intel_dp_init(struct drm_device *dev, int output_reg, enum port port)	5959	intel_dp_init(struct drm_device *dev,
		5960	i915_reg_t output_reg, enum port port)
6140	{	5961	{
6141	struct drm_i915_private *dev_priv = dev->dev_private;	5962	struct drm_i915_private *dev_priv = dev->dev_private;
6142	struct intel_digital_port *intel_dig_port;	5963	struct intel_digital_port *intel_dig_port;
@@ -6182,6 +6003,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) · 39 unmodified lines
6182	}	6003	}
6183		6004
6184	intel_dig_port->port = port;	6005	intel_dig_port->port = port;
		6006	dev_priv->dig_port_map[port] = intel_encoder;
6185	intel_dig_port->dp.output_reg = output_reg;	6007	intel_dig_port->dp.output_reg = output_reg;
6186		6008
6187	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;	6009	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;

drivers/gpu/drm/i915/intel_dp_link_training.c+323−0

@@ -0,0 +1,323 @@
	1	/*
	2	* Copyright © 2008-2015 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23
	24	#include "intel_drv.h"
	25
	26	static void
	27	intel_get_adjust_train(struct intel_dp *intel_dp,
	28	const uint8_t link_status[DP_LINK_STATUS_SIZE])
	29	{
	30	uint8_t v = 0;
	31	uint8_t p = 0;
	32	int lane;
	33	uint8_t voltage_max;
	34	uint8_t preemph_max;
	35
	36	for (lane = 0; lane < intel_dp->lane_count; lane++) {
	37	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
	38	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
	39
	40	if (this_v > v)
	41	v = this_v;
	42	if (this_p > p)
	43	p = this_p;
	44	}
	45
	46	voltage_max = intel_dp_voltage_max(intel_dp);
	47	if (v >= voltage_max)
	48	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
	49
	50	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	51	if (p >= preemph_max)
	52	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
	53
	54	for (lane = 0; lane < 4; lane++)
	55	intel_dp->train_set[lane] = v \| p;
	56	}
	57
	58	static bool
	59	intel_dp_set_link_train(struct intel_dp *intel_dp,
	60	uint8_t dp_train_pat)
	61	{
	62	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	63	int ret, len;
	64
	65	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
	66
	67	buf[0] = dp_train_pat;
	68	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
	69	DP_TRAINING_PATTERN_DISABLE) {
	70	/* don't write DP_TRAINING_LANEx_SET on disable */
	71	len = 1;
	72	} else {
	73	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
	74	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
	75	len = intel_dp->lane_count + 1;
	76	}
	77
	78	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
	79	buf, len);
	80
	81	return ret == len;
	82	}
	83
	84	static bool
	85	intel_dp_reset_link_train(struct intel_dp *intel_dp,
	86	uint8_t dp_train_pat)
	87	{
	88	if (!intel_dp->train_set_valid)
	89	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
	90	intel_dp_set_signal_levels(intel_dp);
	91	return intel_dp_set_link_train(intel_dp, dp_train_pat);
	92	}
	93
	94	static bool
	95	intel_dp_update_link_train(struct intel_dp *intel_dp)
	96	{
	97	int ret;
	98
	99	intel_dp_set_signal_levels(intel_dp);
	100
	101	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
	102	intel_dp->train_set, intel_dp->lane_count);
	103
	104	return ret == intel_dp->lane_count;
	105	}
	106
	107	/* Enable corresponding port and start training pattern 1 */
	108	static void
	109	intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
	110	{
	111	int i;
	112	uint8_t voltage;
	113	int voltage_tries, loop_tries;
	114	uint8_t link_config[2];
	115	uint8_t link_bw, rate_select;
	116
	117	if (intel_dp->prepare_link_retrain)
	118	intel_dp->prepare_link_retrain(intel_dp);
	119
	120	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
	121	&link_bw, &rate_select);
	122
	123	/* Write the link configuration data */
	124	link_config[0] = link_bw;
	125	link_config[1] = intel_dp->lane_count;
	126	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
	127	link_config[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	128	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
	129	if (intel_dp->num_sink_rates)
	130	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
	131	&rate_select, 1);
	132
	133	link_config[0] = 0;
	134	link_config[1] = DP_SET_ANSI_8B10B;
	135	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
	136
	137	intel_dp->DP \|= DP_PORT_EN;
	138
	139	/* clock recovery */
	140	if (!intel_dp_reset_link_train(intel_dp,
	141	DP_TRAINING_PATTERN_1 \|
	142	DP_LINK_SCRAMBLING_DISABLE)) {
	143	DRM_ERROR("failed to enable link training\n");
	144	return;
	145	}
	146
	147	voltage = 0xff;
	148	voltage_tries = 0;
	149	loop_tries = 0;
	150	for (;;) {
	151	uint8_t link_status[DP_LINK_STATUS_SIZE];
	152
	153	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
	154	if (!intel_dp_get_link_status(intel_dp, link_status)) {
	155	DRM_ERROR("failed to get link status\n");
	156	break;
	157	}
	158
	159	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
	160	DRM_DEBUG_KMS("clock recovery OK\n");
	161	break;
	162	}
	163
	164	/*
	165	* if we used previously trained voltage and pre-emphasis values
	166	* and we don't get clock recovery, reset link training values
	167	*/
	168	if (intel_dp->train_set_valid) {
	169	DRM_DEBUG_KMS("clock recovery not ok, reset");
	170	/* clear the flag as we are not reusing train set */
	171	intel_dp->train_set_valid = false;
	172	if (!intel_dp_reset_link_train(intel_dp,
	173	DP_TRAINING_PATTERN_1 \|
	174	DP_LINK_SCRAMBLING_DISABLE)) {
	175	DRM_ERROR("failed to enable link training\n");
	176	return;
	177	}
	178	continue;
	179	}
	180
	181	/* Check to see if we've tried the max voltage */
	182	for (i = 0; i < intel_dp->lane_count; i++)
	183	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
	184	break;
	185	if (i == intel_dp->lane_count) {
	186	++loop_tries;
	187	if (loop_tries == 5) {
	188	DRM_ERROR("too many full retries, give up\n");
	189	break;
	190	}
	191	intel_dp_reset_link_train(intel_dp,
	192	DP_TRAINING_PATTERN_1 \|
	193	DP_LINK_SCRAMBLING_DISABLE);
	194	voltage_tries = 0;
	195	continue;
	196	}
	197
	198	/* Check to see if we've tried the same voltage 5 times */
	199	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
	200	++voltage_tries;
	201	if (voltage_tries == 5) {
	202	DRM_ERROR("too many voltage retries, give up\n");
	203	break;
	204	}
	205	} else
	206	voltage_tries = 0;
	207	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	208
	209	/* Update training set as requested by target */
	210	intel_get_adjust_train(intel_dp, link_status);
	211	if (!intel_dp_update_link_train(intel_dp)) {
	212	DRM_ERROR("failed to update link training\n");
	213	break;
	214	}
	215	}
	216	}
	217
	218	static void
	219	intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
	220	{
	221	bool channel_eq = false;
	222	int tries, cr_tries;
	223	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
	224
	225	/*
	226	* Training Pattern 3 for HBR2 or 1.2 devices that support it.
	227	*
	228	* Intel platforms that support HBR2 also support TPS3. TPS3 support is
	229	* also mandatory for downstream devices that support HBR2.
	230	*
	231	* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
	232	* supported but still not enabled.
	233	*/
	234	if (intel_dp_source_supports_hbr2(intel_dp) &&
	235	drm_dp_tps3_supported(intel_dp->dpcd))
	236	training_pattern = DP_TRAINING_PATTERN_3;
	237	else if (intel_dp->link_rate == 540000)
	238	DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
	239
	240	/* channel equalization */
	241	if (!intel_dp_set_link_train(intel_dp,
	242	training_pattern \|
	243	DP_LINK_SCRAMBLING_DISABLE)) {
	244	DRM_ERROR("failed to start channel equalization\n");
	245	return;
	246	}
	247
	248	tries = 0;
	249	cr_tries = 0;
	250	channel_eq = false;
	251	for (;;) {
	252	uint8_t link_status[DP_LINK_STATUS_SIZE];
	253
	254	if (cr_tries > 5) {
	255	DRM_ERROR("failed to train DP, aborting\n");
	256	break;
	257	}
	258
	259	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
	260	if (!intel_dp_get_link_status(intel_dp, link_status)) {
	261	DRM_ERROR("failed to get link status\n");
	262	break;
	263	}
	264
	265	/* Make sure clock is still ok */
	266	if (!drm_dp_clock_recovery_ok(link_status,
	267	intel_dp->lane_count)) {
	268	intel_dp->train_set_valid = false;
	269	intel_dp_link_training_clock_recovery(intel_dp);
	270	intel_dp_set_link_train(intel_dp,
	271	training_pattern \|
	272	DP_LINK_SCRAMBLING_DISABLE);
	273	cr_tries++;
	274	continue;
	275	}
	276
	277	if (drm_dp_channel_eq_ok(link_status,
	278	intel_dp->lane_count)) {
	279	channel_eq = true;
	280	break;
	281	}
	282
	283	/* Try 5 times, then try clock recovery if that fails */
	284	if (tries > 5) {
	285	intel_dp->train_set_valid = false;
	286	intel_dp_link_training_clock_recovery(intel_dp);
	287	intel_dp_set_link_train(intel_dp,
	288	training_pattern \|
	289	DP_LINK_SCRAMBLING_DISABLE);
	290	tries = 0;
	291	cr_tries++;
	292	continue;
	293	}
	294
	295	/* Update training set as requested by target */
	296	intel_get_adjust_train(intel_dp, link_status);
	297	if (!intel_dp_update_link_train(intel_dp)) {
	298	DRM_ERROR("failed to update link training\n");
	299	break;
	300	}
	301	++tries;
	302	}
	303
	304	intel_dp_set_idle_link_train(intel_dp);
	305
	306	if (channel_eq) {
	307	intel_dp->train_set_valid = true;
	308	DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
	309	}
	310	}
	311
	312	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
	313	{
	314	intel_dp_set_link_train(intel_dp,
	315	DP_TRAINING_PATTERN_DISABLE);
	316	}
	317
	318	void
	319	intel_dp_start_link_train(struct intel_dp *intel_dp)
	320	{
	321	intel_dp_link_training_clock_recovery(intel_dp);
	322	intel_dp_link_training_channel_equalization(intel_dp);
	323	}

drivers/gpu/drm/i915/intel_dp_mst.c+9−9

@@ -173,20 +173,14 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) · 172 unmodified lines
173	intel_mst->port = found->port;	173	intel_mst->port = found->port;
174		174
175	if (intel_dp->active_mst_links == 0) {	175	if (intel_dp->active_mst_links == 0) {
176	enum port port = intel_ddi_get_encoder_port(encoder);	176	intel_ddi_clk_select(encoder, intel_crtc->config);
177		177
178	intel_dp_set_link_params(intel_dp, intel_crtc->config);	178	intel_dp_set_link_params(intel_dp, intel_crtc->config);
179		179
180	/* FIXME: add support for SKL */
181	if (INTEL_INFO(dev)->gen < 9)
182	I915_WRITE(PORT_CLK_SEL(port),
183	intel_crtc->config->ddi_pll_sel);
184
185	intel_ddi_init_dp_buf_reg(&intel_dig_port->base);	180	intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
186		181
187	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);	182	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
188		183
189
190	intel_dp_start_link_train(intel_dp);	184	intel_dp_start_link_train(intel_dp);
191	intel_dp_stop_link_train(intel_dp);	185	intel_dp_stop_link_train(intel_dp);
192	}	186	}
@@ -414,7 +408,10 @@ static void intel_connector_add_to_fbdev(struct intel_connector *connector) · 221 unmodified lines
414	{	408	{
415	#ifdef CONFIG_DRM_FBDEV_EMULATION	409	#ifdef CONFIG_DRM_FBDEV_EMULATION
416	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);	410	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
417	drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, &connector->base);	411
		412	if (dev_priv->fbdev)
		413	drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper,
		414	&connector->base);
418	#endif	415	#endif
419	}	416	}
420		417
@@ -422,7 +419,10 @@ static void intel_connector_remove_from_fbdev(struct intel_connector *connector) · 1 unmodified line
422	{	419	{
423	#ifdef CONFIG_DRM_FBDEV_EMULATION	420	#ifdef CONFIG_DRM_FBDEV_EMULATION
424	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);	421	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
425	drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, &connector->base);	422
		423	if (dev_priv->fbdev)
		424	drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper,
		425	&connector->base);
426	#endif	426	#endif
427	}	427	}
428		428

drivers/gpu/drm/i915/intel_drv.h+98−61

 struct intel_fbdev {
 	struct drm_fb_helper helper;
 	struct intel_framebuffer *fb;
-	struct list_head fbdev_list;
-	struct drm_display_mode *our_mode;
 	int preferred_bpp;
 };
 	unsigned int cdclk;
 	bool dpll_set;
 	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
+	struct intel_wm_config wm_config;
 };
 struct intel_plane_state {
 	int scaler_id;
 	struct drm_intel_sprite_colorkey ckey;
+	/* async flip related structures */
+	struct drm_i915_gem_request *wait_req;
 };
 struct intel_initial_plane_config {
 /* drm_mode->private_flags */
 #define I915_MODE_FLAG_INHERITED 1
+struct intel_pipe_wm {
+	struct intel_wm_level wm[5];
+	uint32_t linetime;
+	bool fbc_wm_enabled;
+	bool pipe_enabled;
+	bool sprites_enabled;
+	bool sprites_scaled;
+};
+struct skl_pipe_wm {
+	struct skl_wm_level wm[8];
+	struct skl_wm_level trans_wm;
+	uint32_t linetime;
+};
 struct intel_crtc_state {
 	struct drm_crtc_state base;
 	/* w/a for waiting 2 vblanks during crtc enable */
 	enum pipe hsw_workaround_pipe;
+	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
+	bool disable_lp_wm;
+	struct {
+		/*
+		 * optimal watermarks, programmed post-vblank when this state
+		 * is committed
+		 */
+		union {
+			struct intel_pipe_wm ilk;
+			struct skl_pipe_wm skl;
+		} optimal;
+	} wm;
 };
 struct vlv_wm_state {
 	bool cxsr;
 };
-struct intel_pipe_wm {
-	struct intel_wm_level wm[5];
-	uint32_t linetime;
-	bool fbc_wm_enabled;
-	bool pipe_enabled;
-	bool sprites_enabled;
-	bool sprites_scaled;
-};
 struct intel_mmio_flip {
 	struct work_struct work;
 	struct drm_i915_private *i915;
 	struct drm_i915_gem_request *req;
 	struct intel_crtc *crtc;
-};
+	unsigned int rotation;
-struct skl_pipe_wm {
-	struct skl_wm_level wm[8];
-	struct skl_wm_level trans_wm;
-	uint32_t linetime;
 };
 /*
  */
 struct intel_crtc_atomic_commit {
 	/* Sleepable operations to perform before commit */
-	bool wait_for_flips;
 	bool disable_fbc;
 	bool disable_ips;
 	bool disable_cxsr;
 	bool pre_disable_primary;
 	bool update_wm_pre, update_wm_post;
-	unsigned disabled_planes;
 	/* Sleepable operations to perform after commit */
 	unsigned fb_bits;
 	/* per-pipe watermark state */
 	struct {
 		/* watermarks currently being used  */
-		struct intel_pipe_wm active;
+		union {
-		/* SKL wm values currently in use */
+			struct intel_pipe_wm ilk;
-		struct skl_pipe_wm skl_active;
+			struct skl_pipe_wm skl;
+		} active;
 		/* allow CxSR on this pipe */
 		bool cxsr_allowed;
 	} wm;
 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 struct intel_hdmi {
-	u32 hdmi_reg;
+	i915_reg_t hdmi_reg;
 	int ddc_bus;
 	bool limited_color_range;
 	bool color_range_auto;
 	M2_N2
 };
-struct sink_crc {
-	bool started;
-	u8 last_crc[6];
-	int last_count;
-};
 struct intel_dp {
-	uint32_t output_reg;
+	i915_reg_t output_reg;
-	uint32_t aux_ch_ctl_reg;
+	i915_reg_t aux_ch_ctl_reg;
+	i915_reg_t aux_ch_data_reg[5];
 	uint32_t DP;
 	int link_rate;
 	uint8_t lane_count;
 	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 	uint8_t num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
-	struct sink_crc sink_crc;
 	struct drm_dp_aux aux;
 	uint8_t train_set[4];
 	int panel_power_up_delay;
 				     bool has_aux_irq,
 				     int send_bytes,
 				     uint32_t aux_clock_divider);
+	/* This is called before a link training is starterd */
+	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 	bool train_set_valid;
 	/* Displayport compliance testing */
 	struct intel_hdmi hdmi;
 	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 	bool release_cl2_override;
+	/* for communication with audio component; protected by av_mutex */
+	const struct drm_connector *audio_connector;
 };
 struct intel_dp_mst_encoder {
 					 enum pipe pipe);
 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 					 enum transcoder pch_transcoder);
-void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
+void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
+void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 /* i915_irq.c */
 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 /* intel_ddi.c */
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *pipe_config);
 void intel_prepare_ddi(struct drm_device *dev);
 void hsw_fdi_link_train(struct drm_crtc *crtc);
 void intel_ddi_init(struct drm_device *dev, enum port port);
 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 			  struct intel_crtc_state *crtc_state);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
-void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
+void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 void intel_ddi_get_config(struct intel_encoder *encoder,
 {
 	drm_wait_one_vblank(dev, pipe);
 }
+static inline void
+intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
+{
+	const struct intel_crtc *crtc =
+		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
+	if (crtc->active)
+		intel_wait_for_vblank(dev, pipe);
+}
 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 			 struct intel_digital_port *dport,
 				    struct drm_modeset_acquire_ctx *ctx);
 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			       struct drm_framebuffer *fb,
-			       const struct drm_plane_state *plane_state,
+			       const struct drm_plane_state *plane_state);
-			       struct intel_engine_cs *pipelined,
-			       struct drm_i915_gem_request **pipelined_request);
 struct drm_framebuffer *
 __intel_framebuffer_create(struct drm_device *dev,
 			   struct drm_mode_fb_cmd2 *mode_cmd,
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
+int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
+void skl_disable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_state *pipe_config);
-void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
-unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
-				     struct drm_i915_gem_object *obj,
+			   struct drm_i915_gem_object *obj,
-				     unsigned int plane);
+			   unsigned int plane);
 u32 skl_plane_ctl_format(uint32_t pixel_format);
 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
 u32 skl_plane_ctl_rotation(unsigned int rotation);
 /* intel_csr.c */
-void intel_csr_ucode_init(struct drm_device *dev);
+void intel_csr_ucode_init(struct drm_i915_private *);
-enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
+void intel_csr_load_program(struct drm_i915_private *);
-void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
+void intel_csr_ucode_fini(struct drm_i915_private *);
-					enum csr_state state);
-void intel_csr_load_program(struct drm_device *dev);
-void intel_csr_ucode_fini(struct drm_device *dev);
-void assert_csr_loaded(struct drm_i915_private *dev_priv);
 /* intel_dp.c */
-void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
+void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 			     struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
 					 struct intel_digital_port *port);
 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
+void
+intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       uint8_t dp_train_pat);
+void
+intel_dp_set_signal_levels(struct intel_dp *intel_dp);
+void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
+uint8_t
+intel_dp_voltage_max(struct intel_dp *intel_dp);
+uint8_t
+intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
+void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
+			   uint8_t *link_bw, uint8_t *rate_select);
+bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
+bool
+intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 /* legacy fbdev emulation in intel_fbdev.c */
 #ifdef CONFIG_DRM_FBDEV_EMULATION
 extern int intel_fbdev_init(struct drm_device *dev);
-extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
+extern void intel_fbdev_initial_config_async(struct drm_device *dev);
 extern void intel_fbdev_fini(struct drm_device *dev);
 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 	return 0;
 }
-static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
+static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
 {
 }
 			  enum fb_op_origin origin);
 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
-const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
 /* intel_hdmi.c */
-void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
+void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 			       struct intel_connector *intel_connector);
 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
-void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
+void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
+void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
+void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
+void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 void intel_suspend_hw(struct drm_device *dev);
 int ilk_wm_max_level(const struct drm_device *dev);
 void intel_update_watermarks(struct drm_crtc *crtc);
-void intel_update_sprite_watermarks(struct drm_plane *plane,
-				    struct drm_crtc *crtc,
-				    uint32_t sprite_width,
-				    uint32_t sprite_height,
-				    int pixel_size,
-				    bool enabled, bool scaled);
 void intel_init_pm(struct drm_device *dev);
 void intel_pm_setup(struct drm_device *dev);
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 /* intel_sdvo.c */
-bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
+bool intel_sdvo_init(struct drm_device *dev,
+		     i915_reg_t reg, enum port port);
 /* intel_sprite.c */

drivers/gpu/drm/i915/intel_dsi.c+23−22

 		DRM_ERROR("DPI FIFOs are not empty\n");
 }
-static void write_data(struct drm_i915_private *dev_priv, u32 reg,
+static void write_data(struct drm_i915_private *dev_priv,
+		       i915_reg_t reg,
 		       const u8 *data, u32 len)
 {
 	u32 i, j;
 	}
 }
-static void read_data(struct drm_i915_private *dev_priv, u32 reg,
+static void read_data(struct drm_i915_private *dev_priv,
+		      i915_reg_t reg,
 		      u8 *data, u32 len)
 {
 	u32 i, j;
 	struct mipi_dsi_packet packet;
 	ssize_t ret;
 	const u8 *header, *data;
-	u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
+	i915_reg_t data_reg, ctrl_reg;
+	u32 data_mask, ctrl_mask;
 	ret = mipi_dsi_create_packet(&packet, msg);
 	if (ret < 0)
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
-	u32 temp;
-	u32 port_ctrl;
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		u32 temp;
 		temp = I915_READ(VLV_CHICKEN_3);
 		temp &= ~PIXEL_OVERLAP_CNT_MASK |
 					intel_dsi->pixel_overlap <<
 	}
 	for_each_dsi_port(port, intel_dsi->ports) {
-		port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
+		i915_reg_t port_ctrl = IS_BROXTON(dev) ?
-						MIPI_PORT_CTRL(port);
+			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
+		u32 temp;
 		temp = I915_READ(port_ctrl);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
-	u32 temp;
-	u32 port_ctrl;
 	for_each_dsi_port(port, intel_dsi->ports) {
+		i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
+		u32 temp;
 		/* de-assert ip_tg_enable signal */
-		port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
-						MIPI_PORT_CTRL(port);
 		temp = I915_READ(port_ctrl);
 		I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 		POSTING_READ(port_ctrl);
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
-	u32 val;
-	u32 port_ctrl = 0;
 	DRM_DEBUG_KMS("\n");
 	for_each_dsi_port(port, intel_dsi->ports) {
+		/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
+		i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
+		u32 val;
 		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 							ULPS_STATE_ENTER);
 							ULPS_STATE_ENTER);
 		usleep_range(2000, 2500);
-		if (IS_BROXTON(dev))
-			port_ctrl = BXT_MIPI_PORT_CTRL(port);
-		else if (IS_VALLEYVIEW(dev))
-			/* Common bit for both MIPI Port A & MIPI Port C */
-			port_ctrl = MIPI_PORT_CTRL(PORT_A);
 		/* Wait till Clock lanes are in LP-00 state for MIPI Port A
 		 * only. MIPI Port C has no similar bit for checking
 		 */
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct drm_device *dev = encoder->base.dev;
 	enum intel_display_power_domain power_domain;
-	u32 dpi_enabled, func, ctrl_reg;
 	enum port port;
 	DRM_DEBUG_KMS("\n");
 	/* XXX: this only works for one DSI output */
 	for_each_dsi_port(port, intel_dsi->ports) {
+		i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
+			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
+		u32 dpi_enabled, func;
 		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
-		ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
-						MIPI_PORT_CTRL(port);
 		dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 		/* Due to some hardware limitations on BYT, MIPI Port C DPI

drivers/gpu/drm/i915/intel_dsi.h+1−1

@@ -117,7 +117,7 @@ static inline struct intel_dsi_host to_intel_dsi_host(struct mipi_dsi_host h) · 116 unmodified lines
117		117
118	#define for_each_dsi_port(__port, __ports_mask) \	118	#define for_each_dsi_port(__port, __ports_mask) \
119	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \	119	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
120	if ((__ports_mask) & (1 << (__port)))	120	for_each_if ((__ports_mask) & (1 << (__port)))
121		121
122	static inline struct intel_dsi enc_to_intel_dsi(struct drm_encoder encoder)	122	static inline struct intel_dsi enc_to_intel_dsi(struct drm_encoder encoder)
123	{	123	{

drivers/gpu/drm/i915/intel_dvo.c+11−16

@@ -44,6 +44,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 43 unmodified lines
44	.type = INTEL_DVO_CHIP_TMDS,	44	.type = INTEL_DVO_CHIP_TMDS,
45	.name = "sil164",	45	.name = "sil164",
46	.dvo_reg = DVOC,	46	.dvo_reg = DVOC,
		47	.dvo_srcdim_reg = DVOC_SRCDIM,
47	.slave_addr = SIL164_ADDR,	48	.slave_addr = SIL164_ADDR,
48	.dev_ops = &sil164_ops,	49	.dev_ops = &sil164_ops,
49	},	50	},
@@ -51,6 +52,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 1 unmodified line
51	.type = INTEL_DVO_CHIP_TMDS,	52	.type = INTEL_DVO_CHIP_TMDS,
52	.name = "ch7xxx",	53	.name = "ch7xxx",
53	.dvo_reg = DVOC,	54	.dvo_reg = DVOC,
		55	.dvo_srcdim_reg = DVOC_SRCDIM,
54	.slave_addr = CH7xxx_ADDR,	56	.slave_addr = CH7xxx_ADDR,
55	.dev_ops = &ch7xxx_ops,	57	.dev_ops = &ch7xxx_ops,
56	},	58	},
@@ -58,6 +60,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 1 unmodified line
58	.type = INTEL_DVO_CHIP_TMDS,	60	.type = INTEL_DVO_CHIP_TMDS,
59	.name = "ch7xxx",	61	.name = "ch7xxx",
60	.dvo_reg = DVOC,	62	.dvo_reg = DVOC,
		63	.dvo_srcdim_reg = DVOC_SRCDIM,
61	.slave_addr = 0x75, /* For some ch7010 */	64	.slave_addr = 0x75, /* For some ch7010 */
62	.dev_ops = &ch7xxx_ops,	65	.dev_ops = &ch7xxx_ops,
63	},	66	},
@@ -65,6 +68,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 1 unmodified line
65	.type = INTEL_DVO_CHIP_LVDS,	68	.type = INTEL_DVO_CHIP_LVDS,
66	.name = "ivch",	69	.name = "ivch",
67	.dvo_reg = DVOA,	70	.dvo_reg = DVOA,
		71	.dvo_srcdim_reg = DVOA_SRCDIM,
68	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */	72	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
69	.dev_ops = &ivch_ops,	73	.dev_ops = &ivch_ops,
70	},	74	},
@@ -72,6 +76,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 1 unmodified line
72	.type = INTEL_DVO_CHIP_TMDS,	76	.type = INTEL_DVO_CHIP_TMDS,
73	.name = "tfp410",	77	.name = "tfp410",
74	.dvo_reg = DVOC,	78	.dvo_reg = DVOC,
		79	.dvo_srcdim_reg = DVOC_SRCDIM,
75	.slave_addr = TFP410_ADDR,	80	.slave_addr = TFP410_ADDR,
76	.dev_ops = &tfp410_ops,	81	.dev_ops = &tfp410_ops,
77	},	82	},
@@ -79,6 +84,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 1 unmodified line
79	.type = INTEL_DVO_CHIP_LVDS,	84	.type = INTEL_DVO_CHIP_LVDS,
80	.name = "ch7017",	85	.name = "ch7017",
81	.dvo_reg = DVOC,	86	.dvo_reg = DVOC,
		87	.dvo_srcdim_reg = DVOC_SRCDIM,
82	.slave_addr = 0x75,	88	.slave_addr = 0x75,
83	.gpio = GMBUS_PIN_DPB,	89	.gpio = GMBUS_PIN_DPB,
84	.dev_ops = &ch7017_ops,	90	.dev_ops = &ch7017_ops,
@@ -87,6 +93,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { · 2 unmodified lines
87	.type = INTEL_DVO_CHIP_TMDS,	93	.type = INTEL_DVO_CHIP_TMDS,
88	.name = "ns2501",	94	.name = "ns2501",
89	.dvo_reg = DVOB,	95	.dvo_reg = DVOB,
		96	.dvo_srcdim_reg = DVOB_SRCDIM,
90	.slave_addr = NS2501_ADDR,	97	.slave_addr = NS2501_ADDR,
91	.dev_ops = &ns2501_ops,	98	.dev_ops = &ns2501_ops,
92	}	99	}
@@ -171,7 +178,7 @@ static void intel_disable_dvo(struct intel_encoder *encoder) · 78 unmodified lines
171	{	178	{
172	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;	179	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
173	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);	180	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
174	u32 dvo_reg = intel_dvo->dev.dvo_reg;	181	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
175	u32 temp = I915_READ(dvo_reg);	182	u32 temp = I915_READ(dvo_reg);
176		183
177	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);	184	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
@@ -184,7 +191,7 @@ static void intel_enable_dvo(struct intel_encoder *encoder) · 6 unmodified lines
184	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;	191	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
185	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);	192	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
186	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);	193	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
187	u32 dvo_reg = intel_dvo->dev.dvo_reg;	194	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
188	u32 temp = I915_READ(dvo_reg);	195	u32 temp = I915_READ(dvo_reg);
189		196
190	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,	197	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
@@ -255,20 +262,8 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder) · 64 unmodified lines
255	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);	262	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
256	int pipe = crtc->pipe;	263	int pipe = crtc->pipe;
257	u32 dvo_val;	264	u32 dvo_val;
258	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;	265	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
259		266	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
260	switch (dvo_reg) {
261	case DVOA:
262	default:
263	dvo_srcdim_reg = DVOA_SRCDIM;
264	break;
265	case DVOB:
266	dvo_srcdim_reg = DVOB_SRCDIM;
267	break;
268	case DVOC:
269	dvo_srcdim_reg = DVOC_SRCDIM;
270	break;
271	}
272		267
273	/* Save the data order, since I don't know what it should be set to. */	268	/* Save the data order, since I don't know what it should be set to. */
274	dvo_val = I915_READ(dvo_reg) &	269	dvo_val = I915_READ(dvo_reg) &

drivers/gpu/drm/i915/intel_fbc.c+73−123

 	return dev_priv->fbc.enable_fbc != NULL;
 }
+static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
+{
+	return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
+}
 /*
  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
 	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 }
-static void intel_fbc_nuke(struct drm_i915_private *dev_priv)
+/* This function forces a CFB recompression through the nuke operation. */
+static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 	POSTING_READ(MSG_FBC_REND_STATE);
 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset);
 	}
-	intel_fbc_nuke(dev_priv);
+	intel_fbc_recompress(dev_priv);
 	DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 }
 		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 	I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc));
-	intel_fbc_nuke(dev_priv);
+	intel_fbc_recompress(dev_priv);
 	DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 }
 	if (dev_priv->fbc.fbc_work == NULL)
 		return;
-	DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 	/* Synchronisation is provided by struct_mutex and checking of
 	 * dev_priv->fbc.fbc_work, so we can perform the cancellation
 	 * entirely asynchronously.
 	intel_fbc_cancel_work(dev_priv);
-	dev_priv->fbc.disable_fbc(dev_priv);
+	if (dev_priv->fbc.enabled)
+		dev_priv->fbc.disable_fbc(dev_priv);
 	dev_priv->fbc.crtc = NULL;
 }
 	mutex_unlock(&dev_priv->fbc.lock);
 }
-const char *intel_no_fbc_reason_str(enum no_fbc_reason reason)
-{
-	switch (reason) {
-	case FBC_OK:
-		return "FBC enabled but currently disabled in hardware";
-	case FBC_UNSUPPORTED:
-		return "unsupported by this chipset";
-	case FBC_NO_OUTPUT:
-		return "no output";
-	case FBC_STOLEN_TOO_SMALL:
-		return "not enough stolen memory";
-	case FBC_UNSUPPORTED_MODE:
-		return "mode incompatible with compression";
-	case FBC_MODE_TOO_LARGE:
-		return "mode too large for compression";
-	case FBC_BAD_PLANE:
-		return "FBC unsupported on plane";
-	case FBC_NOT_TILED:
-		return "framebuffer not tiled or fenced";
-	case FBC_MULTIPLE_PIPES:
-		return "more than one pipe active";
-	case FBC_MODULE_PARAM:
-		return "disabled per module param";
-	case FBC_CHIP_DEFAULT:
-		return "disabled per chip default";
-	case FBC_ROTATION:
-		return "rotation unsupported";
-	case FBC_IN_DBG_MASTER:
-		return "Kernel debugger is active";
-	case FBC_BAD_STRIDE:
-		return "framebuffer stride not supported";
-	case FBC_PIXEL_RATE:
-		return "pixel rate is too big";
-	case FBC_PIXEL_FORMAT:
-		return "pixel format is invalid";
-	default:
-		MISSING_CASE(reason);
-		return "unknown reason";
-	}
-}
 static void set_no_fbc_reason(struct drm_i915_private *dev_priv,
-			      enum no_fbc_reason reason)
+			      const char *reason)
 {
 	if (dev_priv->fbc.no_fbc_reason == reason)
 		return;
 	dev_priv->fbc.no_fbc_reason = reason;
-	DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason));
+	DRM_DEBUG_KMS("Disabling FBC: %s\n", reason);
+}
+static bool crtc_is_valid(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
+		return false;
+	if (!intel_crtc_active(&crtc->base))
+		return false;
+	if (!to_intel_plane_state(crtc->base.primary->state)->visible)
+		return false;
+	return true;
 }
 static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
 {
 	struct drm_crtc *crtc = NULL, *tmp_crtc;
 	enum pipe pipe;
-	bool pipe_a_only = false;
-	if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
-		pipe_a_only = true;
 	for_each_pipe(dev_priv, pipe) {
 		tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
-		if (intel_crtc_active(tmp_crtc) &&
+		if (crtc_is_valid(to_intel_crtc(tmp_crtc)))
-		    to_intel_plane_state(tmp_crtc->primary->state)->visible)
 			crtc = tmp_crtc;
-		if (pipe_a_only)
-			break;
 	}
-	if (!crtc || crtc->primary->fb == NULL)
+	if (!crtc)
 		return NULL;
 	return crtc;
 	 * reserved range size, so it always assumes the maximum (8mb) is used.
 	 * If we enable FBC using a CFB on that memory range we'll get FIFO
 	 * underruns, even if that range is not reserved by the BIOS. */
-	if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+	if (IS_BROADWELL(dev_priv) ||
+	    IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024;
 	else
 		end = dev_priv->gtt.stolen_usable_size;
 	if (INTEL_INFO(dev_priv)->gen >= 7)
 		lines = min(lines, 2048);
+	/* Hardware needs the full buffer stride, not just the active area. */
 	return lines * fb->pitches[0];
 }
  * __intel_fbc_update - enable/disable FBC as needed, unlocked
  * @dev_priv: i915 device instance
  *
- * Set up the framebuffer compression hardware at mode set time.  We
+ * This function completely reevaluates the status of FBC, then enables,
- * enable it if possible:
+ * disables or maintains it on the same state.
- *   - plane A only (on pre-965)
- *   - no pixel mulitply/line duplication
- *   - no alpha buffer discard
- *   - no dual wide
- *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
- *
- * We can't assume that any compression will take place (worst case),
- * so the compressed buffer has to be the same size as the uncompressed
- * one.  It also must reside (along with the line length buffer) in
- * stolen memory.
- *
- * We need to enable/disable FBC on a global basis.
  */
 static void __intel_fbc_update(struct drm_i915_private *dev_priv)
 {
-	struct drm_crtc *crtc = NULL;
+	struct drm_crtc *drm_crtc = NULL;
-	struct intel_crtc *intel_crtc;
+	struct intel_crtc *crtc;
 	struct drm_framebuffer *fb;
 	struct drm_i915_gem_object *obj;
 	const struct drm_display_mode *adjusted_mode;
 	WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
-	/* disable framebuffer compression in vGPU */
 	if (intel_vgpu_active(dev_priv->dev))
 		i915.enable_fbc = 0;
 	if (i915.enable_fbc < 0) {
-		set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT);
+		set_no_fbc_reason(dev_priv, "disabled per chip default");
 		goto out_disable;
 	}
 	if (!i915.enable_fbc) {
-		set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM);
+		set_no_fbc_reason(dev_priv, "disabled per module param");
 		goto out_disable;
 	}
-	/*
+	drm_crtc = intel_fbc_find_crtc(dev_priv);
-	 * If FBC is already on, we just have to verify that we can
+	if (!drm_crtc) {
-	 * keep it that way...
+		set_no_fbc_reason(dev_priv, "no output");
-	 * Need to disable if:
-	 *   - more than one pipe is active
-	 *   - changing FBC params (stride, fence, mode)
-	 *   - new fb is too large to fit in compressed buffer
-	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
-	 */
-	crtc = intel_fbc_find_crtc(dev_priv);
-	if (!crtc) {
-		set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT);
 		goto out_disable;
 	}
 	if (!multiple_pipes_ok(dev_priv)) {
-		set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES);
+		set_no_fbc_reason(dev_priv, "more than one pipe active");
 		goto out_disable;
 	}
-	intel_crtc = to_intel_crtc(crtc);
+	crtc = to_intel_crtc(drm_crtc);
-	fb = crtc->primary->fb;
+	fb = crtc->base.primary->fb;
 	obj = intel_fb_obj(fb);
-	adjusted_mode = &intel_crtc->config->base.adjusted_mode;
+	adjusted_mode = &crtc->config->base.adjusted_mode;
 	if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 	    (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
-		set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE);
+		set_no_fbc_reason(dev_priv, "incompatible mode");
 		goto out_disable;
 	}
-	if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) {
+	if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
-		set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE);
+		set_no_fbc_reason(dev_priv, "mode too large for compression");
 		goto out_disable;
 	}
 	if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) &&
-	    intel_crtc->plane != PLANE_A) {
+	    crtc->plane != PLANE_A) {
-		set_no_fbc_reason(dev_priv, FBC_BAD_PLANE);
+		set_no_fbc_reason(dev_priv, "FBC unsupported on plane");
 		goto out_disable;
 	}
 	 */
 	if (obj->tiling_mode != I915_TILING_X ||
 	    obj->fence_reg == I915_FENCE_REG_NONE) {
-		set_no_fbc_reason(dev_priv, FBC_NOT_TILED);
+		set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced");
 		goto out_disable;
 	}
 	if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
-	    crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) {
+	    crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) {
-		set_no_fbc_reason(dev_priv, FBC_ROTATION);
+		set_no_fbc_reason(dev_priv, "rotation unsupported");
 		goto out_disable;
 	}
 	if (!stride_is_valid(dev_priv, fb->pitches[0])) {
-		set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE);
+		set_no_fbc_reason(dev_priv, "framebuffer stride not supported");
 		goto out_disable;
 	}
 	if (!pixel_format_is_valid(fb)) {
-		set_no_fbc_reason(dev_priv, FBC_PIXEL_FORMAT);
+		set_no_fbc_reason(dev_priv, "pixel format is invalid");
-		goto out_disable;
-	}
-	/* If the kernel debugger is active, always disable compression */
-	if (in_dbg_master()) {
-		set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER);
 		goto out_disable;
 	}
 	/* WaFbcExceedCdClockThreshold:hsw,bdw */
 	if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
-	    ilk_pipe_pixel_rate(intel_crtc->config) >=
+	    ilk_pipe_pixel_rate(crtc->config) >=
 	    dev_priv->cdclk_freq * 95 / 100) {
-		set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE);
+		set_no_fbc_reason(dev_priv, "pixel rate is too big");
 		goto out_disable;
 	}
-	if (intel_fbc_setup_cfb(intel_crtc)) {
+	if (intel_fbc_setup_cfb(crtc)) {
-		set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL);
+		set_no_fbc_reason(dev_priv, "not enough stolen memory");
 		goto out_disable;
 	}
 	 * cannot be unpinned (and have its GTT offset and fence revoked)
 	 * without first being decoupled from the scanout and FBC disabled.
 	 */
-	if (dev_priv->fbc.crtc == intel_crtc &&
+	if (dev_priv->fbc.crtc == crtc &&
 	    dev_priv->fbc.fb_id == fb->base.id &&
-	    dev_priv->fbc.y == crtc->y)
+	    dev_priv->fbc.y == crtc->base.y)
 		return;
 	if (intel_fbc_enabled(dev_priv)) {
 		__intel_fbc_disable(dev_priv);
 	}
-	intel_fbc_schedule_enable(intel_crtc);
+	intel_fbc_schedule_enable(crtc);
-	dev_priv->fbc.no_fbc_reason = FBC_OK;
+	dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)";
 	return;
 out_disable:
 	enum pipe pipe;
 	mutex_init(&dev_priv->fbc.lock);
+	dev_priv->fbc.enabled = false;
 	if (!HAS_FBC(dev_priv)) {
-		dev_priv->fbc.enabled = false;
+		dev_priv->fbc.no_fbc_reason = "unsupported by this chipset";
-		dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED;
 		return;
 	}
 		dev_priv->fbc.possible_framebuffer_bits |=
 				INTEL_FRONTBUFFER_PRIMARY(pipe);
-		if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
+		if (fbc_on_pipe_a_only(dev_priv))
 			break;
 	}
 		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
 	}
-	dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv);
+	/* We still don't have any sort of hardware state readout for FBC, so
+	 * disable it in case the BIOS enabled it to make sure software matches
+	 * the hardware state. */
+	if (dev_priv->fbc.fbc_enabled(dev_priv))
+		dev_priv->fbc.disable_fbc(dev_priv);
 }

drivers/gpu/drm/i915/intel_fbdev.c+32−18

 {
 	struct intel_fbdev *ifbdev =
 		container_of(helper, struct intel_fbdev, helper);
-	struct drm_framebuffer *fb;
+	struct drm_framebuffer *fb = NULL;
 	struct drm_device *dev = helper->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_mode_fb_cmd2 mode_cmd = {};
 	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
 							  sizes->surface_depth);
+	mutex_lock(&dev->struct_mutex);
 	size = mode_cmd.pitches[0] * mode_cmd.height;
 	size = PAGE_ALIGN(size);
 	fb = __intel_framebuffer_create(dev, &mode_cmd, obj);
 	if (IS_ERR(fb)) {
+		drm_gem_object_unreference(&obj->base);
 		ret = PTR_ERR(fb);
-		goto out_unref;
+		goto out;
 	}
 	/* Flush everything out, we'll be doing GTT only from now on */
-	ret = intel_pin_and_fence_fb_obj(NULL, fb, NULL, NULL, NULL);
+	ret = intel_pin_and_fence_fb_obj(NULL, fb, NULL);
 	if (ret) {
 		DRM_ERROR("failed to pin obj: %d\n", ret);
-		goto out_fb;
+		goto out;
 	}
+	mutex_unlock(&dev->struct_mutex);
 	ifbdev->fb = to_intel_framebuffer(fb);
 	return 0;
-out_fb:
-	drm_framebuffer_remove(fb);
-out_unref:
-	drm_gem_object_unreference(&obj->base);
 out:
+	mutex_unlock(&dev->struct_mutex);
+	if (!IS_ERR_OR_NULL(fb))
+		drm_framebuffer_unreference(fb);
 	return ret;
 }
 	int size, ret;
 	bool prealloc = false;
-	mutex_lock(&dev->struct_mutex);
 	if (intel_fb &&
 	    (sizes->fb_width > intel_fb->base.width ||
 	     sizes->fb_height > intel_fb->base.height)) {
 		DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
 		ret = intelfb_alloc(helper, sizes);
 		if (ret)
-			goto out_unlock;
+			return ret;
 		intel_fb = ifbdev->fb;
 	} else {
 		DRM_DEBUG_KMS("re-using BIOS fb\n");
 	obj = intel_fb->obj;
 	size = obj->base.size;
+	mutex_lock(&dev->struct_mutex);
 	info = drm_fb_helper_alloc_fbi(helper);
 	if (IS_ERR(info)) {
+		DRM_ERROR("Failed to allocate fb_info\n");
 		ret = PTR_ERR(info);
 		goto out_unpin;
 	}
 		ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
 			   size);
 	if (!info->screen_base) {
+		DRM_ERROR("Failed to remap framebuffer into virtual memory\n");
 		ret = -ENOSPC;
 		goto out_destroy_fbi;
 	}
 	drm_fb_helper_release_fbi(helper);
 out_unpin:
 	i915_gem_object_ggtt_unpin(obj);
-	drm_gem_object_unreference(&obj->base);
-out_unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
 }
 	drm_fb_helper_fini(&ifbdev->helper);
-	drm_framebuffer_unregister_private(&ifbdev->fb->base);
+	if (ifbdev->fb) {
-	drm_framebuffer_remove(&ifbdev->fb->base);
+		drm_framebuffer_unregister_private(&ifbdev->fb->base);
+		drm_framebuffer_remove(&ifbdev->fb->base);
+	}
 }
 /*
 	return 0;
 }
-void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
+static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
 {
 	struct drm_i915_private *dev_priv = data;
 	struct intel_fbdev *ifbdev = dev_priv->fbdev;
 	/* Due to peculiar init order wrt to hpd handling this is separate. */
-	drm_fb_helper_initial_config(&ifbdev->helper, ifbdev->preferred_bpp);
+	if (drm_fb_helper_initial_config(&ifbdev->helper,
+					 ifbdev->preferred_bpp))
+		intel_fbdev_fini(dev_priv->dev);
+}
+void intel_fbdev_initial_config_async(struct drm_device *dev)
+{
+	async_schedule(intel_fbdev_initial_config, to_i915(dev));
 }
 void intel_fbdev_fini(struct drm_device *dev)
 	flush_work(&dev_priv->fbdev_suspend_work);
-	async_synchronize_full();
+	if (!current_is_async())
+		async_synchronize_full();
 	intel_fbdev_destroy(dev, dev_priv->fbdev);
 	kfree(dev_priv->fbdev);
 	dev_priv->fbdev = NULL;

drivers/gpu/drm/i915/intel_fifo_underrun.c+99−28

@@ -84,38 +84,21 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev) · 83 unmodified lines
84	return true;	84	return true;
85	}	85	}
86		86
87	/**	87	static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
88	* i9xx_check_fifo_underruns - check for fifo underruns
89	* @dev_priv: i915 device instance
90	*
91	* This function checks for fifo underruns on GMCH platforms. This needs to be
92	* done manually on modeset to make sure that we catch all underruns since they
93	* do not generate an interrupt by themselves on these platforms.
94	*/
95	void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)
96	{	88	{
97	struct intel_crtc *crtc;	89	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
98		90	i915_reg_t reg = PIPESTAT(crtc->pipe);
99	spin_lock_irq(&dev_priv->irq_lock);	91	u32 pipestat = I915_READ(reg) & 0xffff0000;
100
101	for_each_intel_crtc(dev_priv->dev, crtc) {
102	u32 reg = PIPESTAT(crtc->pipe);
103	u32 pipestat;
104
105	if (crtc->cpu_fifo_underrun_disabled)
106	continue;
107		92
108	pipestat = I915_READ(reg) & 0xffff0000;	93	assert_spin_locked(&dev_priv->irq_lock);
109	if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
110	continue;
111		94
112	I915_WRITE(reg, pipestat \| PIPE_FIFO_UNDERRUN_STATUS);	95	if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
113	POSTING_READ(reg);	96	return;
114		97
115	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));	98	I915_WRITE(reg, pipestat \| PIPE_FIFO_UNDERRUN_STATUS);
116	}	99	POSTING_READ(reg);
117		100
118	spin_unlock_irq(&dev_priv->irq_lock);	101	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
119	}	102	}
120		103
121	static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,	104	static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
@@ -123,7 +106,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, · 1 unmodified line
123	bool enable, bool old)	106	bool enable, bool old)
124	{	107	{
125	struct drm_i915_private *dev_priv = dev->dev_private;	108	struct drm_i915_private *dev_priv = dev->dev_private;
126	u32 reg = PIPESTAT(pipe);	109	i915_reg_t reg = PIPESTAT(pipe);
127	u32 pipestat = I915_READ(reg) & 0xffff0000;	110	u32 pipestat = I915_READ(reg) & 0xffff0000;
128		111
129	assert_spin_locked(&dev_priv->irq_lock);	112	assert_spin_locked(&dev_priv->irq_lock);
@@ -150,6 +133,23 @@ static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, · 20 unmodified lines
150	ironlake_disable_display_irq(dev_priv, bit);	133	ironlake_disable_display_irq(dev_priv, bit);
151	}	134	}
152		135
		136	static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
		137	{
		138	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
		139	enum pipe pipe = crtc->pipe;
		140	uint32_t err_int = I915_READ(GEN7_ERR_INT);
		141
		142	assert_spin_locked(&dev_priv->irq_lock);
		143
		144	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
		145	return;
		146
		147	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
		148	POSTING_READ(GEN7_ERR_INT);
		149
		150	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
		151	}
		152
153	static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,	153	static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
154	enum pipe pipe,	154	enum pipe pipe,
155	bool enable, bool old)	155	bool enable, bool old)
@@ -202,6 +202,24 @@ static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, · 46 unmodified lines
202	ibx_disable_display_interrupt(dev_priv, bit);	202	ibx_disable_display_interrupt(dev_priv, bit);
203	}	203	}
204		204
		205	static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
		206	{
		207	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
		208	enum transcoder pch_transcoder = (enum transcoder) crtc->pipe;
		209	uint32_t serr_int = I915_READ(SERR_INT);
		210
		211	assert_spin_locked(&dev_priv->irq_lock);
		212
		213	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
		214	return;
		215
		216	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
		217	POSTING_READ(SERR_INT);
		218
		219	DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
		220	transcoder_name(pch_transcoder));
		221	}
		222
205	static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,	223	static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
206	enum transcoder pch_transcoder,	224	enum transcoder pch_transcoder,
207	bool enable, bool old)	225	bool enable, bool old)
@@ -375,3 +393,56 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, · 167 unmodified lines
375	DRM_ERROR("PCH transcoder %c FIFO underrun\n",	393	DRM_ERROR("PCH transcoder %c FIFO underrun\n",
376	transcoder_name(pch_transcoder));	394	transcoder_name(pch_transcoder));
377	}	395	}
		396
		397	/**
		398	* intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
		399	* @dev_priv: i915 device instance
		400	*
		401	* Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
		402	* error interrupt may have been disabled, and so CPU fifo underruns won't
		403	* necessarily raise an interrupt, and on GMCH platforms where underruns never
		404	* raise an interrupt.
		405	*/
		406	void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
		407	{
		408	struct intel_crtc *crtc;
		409
		410	spin_lock_irq(&dev_priv->irq_lock);
		411
		412	for_each_intel_crtc(dev_priv->dev, crtc) {
		413	if (crtc->cpu_fifo_underrun_disabled)
		414	continue;
		415
		416	if (HAS_GMCH_DISPLAY(dev_priv))
		417	i9xx_check_fifo_underruns(crtc);
		418	else if (IS_GEN7(dev_priv))
		419	ivybridge_check_fifo_underruns(crtc);
		420	}
		421
		422	spin_unlock_irq(&dev_priv->irq_lock);
		423	}
		424
		425	/**
		426	* intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
		427	* @dev_priv: i915 device instance
		428	*
		429	* Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
		430	* error interrupt may have been disabled, and so PCH fifo underruns won't
		431	* necessarily raise an interrupt.
		432	*/
		433	void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
		434	{
		435	struct intel_crtc *crtc;
		436
		437	spin_lock_irq(&dev_priv->irq_lock);
		438
		439	for_each_intel_crtc(dev_priv->dev, crtc) {
		440	if (crtc->pch_fifo_underrun_disabled)
		441	continue;
		442
		443	if (HAS_PCH_CPT(dev_priv))
		444	cpt_check_pch_fifo_underruns(crtc);
		445	}
		446
		447	spin_unlock_irq(&dev_priv->irq_lock);
		448	}

drivers/gpu/drm/i915/intel_guc.h+7−1

 	uint16_t			guc_fw_minor_wanted;
 	uint16_t			guc_fw_major_found;
 	uint16_t			guc_fw_minor_found;
+	uint32_t header_size;
+	uint32_t header_offset;
+	uint32_t rsa_size;
+	uint32_t rsa_offset;
+	uint32_t ucode_size;
+	uint32_t ucode_offset;
 };
 struct intel_guc {
 	struct intel_guc_fw guc_fw;
 	uint32_t log_flags;
 	struct drm_i915_gem_object *log_obj;

drivers/gpu/drm/i915/intel_guc_fwif.h+72−0

@@ -122,6 +122,78 @@ · 121 unmodified lines
122		122
123	#define GUC_CTL_MAX_DWORDS (GUC_CTL_RSRVD + 1)	123	#define GUC_CTL_MAX_DWORDS (GUC_CTL_RSRVD + 1)
124		124
		125	/**
		126	* DOC: GuC Firmware Layout
		127	*
		128	* The GuC firmware layout looks like this:
		129	*
		130	* +-------------------------------+
		131	* \| guc_css_header \|
		132	* \| contains major/minor version \|
		133	* +-------------------------------+
		134	* \| uCode \|
		135	* +-------------------------------+
		136	* \| RSA signature \|
		137	* +-------------------------------+
		138	* \| modulus key \|
		139	* +-------------------------------+
		140	* \| exponent val \|
		141	* +-------------------------------+
		142	*
		143	* The firmware may or may not have modulus key and exponent data. The header,
		144	* uCode and RSA signature are must-have components that will be used by driver.
		145	* Length of each components, which is all in dwords, can be found in header.
		146	* In the case that modulus and exponent are not present in fw, a.k.a truncated
		147	* image, the length value still appears in header.
		148	*
		149	* Driver will do some basic fw size validation based on the following rules:
		150	*
		151	* 1. Header, uCode and RSA are must-have components.
		152	* 2. All firmware components, if they present, are in the sequence illustrated
		153	* in the layout table above.
		154	* 3. Length info of each component can be found in header, in dwords.
		155	* 4. Modulus and exponent key are not required by driver. They may not appear
		156	* in fw. So driver will load a truncated firmware in this case.
		157	*/
		158
		159	struct guc_css_header {
		160	uint32_t module_type;
		161	/* header_size includes all non-uCode bits, including css_header, rsa
		162	* key, modulus key and exponent data. */
		163	uint32_t header_size_dw;
		164	uint32_t header_version;
		165	uint32_t module_id;
		166	uint32_t module_vendor;
		167	union {
		168	struct {
		169	uint8_t day;
		170	uint8_t month;
		171	uint16_t year;
		172	};
		173	uint32_t date;
		174	};
		175	uint32_t size_dw; /* uCode plus header_size_dw */
		176	uint32_t key_size_dw;
		177	uint32_t modulus_size_dw;
		178	uint32_t exponent_size_dw;
		179	union {
		180	struct {
		181	uint8_t hour;
		182	uint8_t min;
		183	uint16_t sec;
		184	};
		185	uint32_t time;
		186	};
		187
		188	char username[8];
		189	char buildnumber[12];
		190	uint32_t device_id;
		191	uint32_t guc_sw_version;
		192	uint32_t prod_preprod_fw;
		193	uint32_t reserved[12];
		194	uint32_t header_info;
		195	} __packed;
		196
125	struct guc_doorbell_info {	197	struct guc_doorbell_info {
126	u32 db_status;	198	u32 db_status;
127	u32 cookie;	199	u32 cookie;

drivers/gpu/drm/i915/intel_guc_loader.c+67−38

 #include "intel_guc.h"
 /**
- * DOC: GuC
+ * DOC: GuC-specific firmware loader
  *
  * intel_guc:
  * Top level structure of guc. It handles firmware loading and manages client
 /*
  * Transfer the firmware image to RAM for execution by the microcontroller.
  *
- * GuC Firmware layout:
- * +-------------------------------+  ----
- * |          CSS header           |  128B
- * | contains major/minor version  |
- * +-------------------------------+  ----
- * |             uCode             |
- * +-------------------------------+  ----
- * |         RSA signature         |  256B
- * +-------------------------------+  ----
- *
  * Architecturally, the DMA engine is bidirectional, and can potentially even
  * transfer between GTT locations. This functionality is left out of the API
  * for now as there is no need for it.
  * Note that GuC needs the CSS header plus uKernel code to be copied by the
  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
  */
-#define UOS_CSS_HEADER_OFFSET		0
-#define UOS_VER_MINOR_OFFSET		0x44
-#define UOS_VER_MAJOR_OFFSET		0x46
-#define UOS_CSS_HEADER_SIZE		0x80
-#define UOS_RSA_SIG_SIZE		0x100
 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 	unsigned long offset;
 	struct sg_table *sg = fw_obj->pages;
-	u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
+	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 	int i, ret = 0;
-	/* uCode size, also is where RSA signature starts */
+	/* where RSA signature starts */
-	offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
+	offset = guc_fw->rsa_offset;
-	I915_WRITE(DMA_COPY_SIZE, ucode_size);
 	/* Copy RSA signature from the fw image to HW for verification */
-	sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
+	sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
-	for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
+	for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
+	/* The header plus uCode will be copied to WOPCM via DMA, excluding any
+	 * other components */
+	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 	/* Set the source address for the new blob */
-	offset = i915_gem_obj_ggtt_offset(fw_obj);
+	offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 	/* WaDisableMinuteIaClockGating:skl,bxt */
-	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 					      ~GUC_ENABLE_MIA_CLOCK_GATING));
 	}
 	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int err = 0;
+	if (!i915.enable_guc_submission)
+		return 0;
 	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 {
 	struct drm_i915_gem_object *obj;
 	const struct firmware *fw;
-	const u8 *css_header;
+	struct guc_css_header *css;
-	const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
+	size_t size;
-	const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
-			- 0x8000; /* 32k reserved (8K stack + 24k context) */
 	int err;
 	DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 	DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 		guc_fw->guc_fw_path, fw);
-	DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
-		fw->size, minsize, maxsize);
-	/* Check the size of the blob befoe examining buffer contents */
+	/* Check the size of the blob before examining buffer contents */
-	if (fw->size < minsize || fw->size > maxsize)
+	if (fw->size < sizeof(struct guc_css_header)) {
+		DRM_ERROR("Firmware header is missing\n");
 		goto fail;
+	}
+	css = (struct guc_css_header *)fw->data;
+	/* Firmware bits always start from header */
+	guc_fw->header_offset = 0;
+	guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+		css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
+	if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+		DRM_ERROR("CSS header definition mismatch\n");
+		goto fail;
+	}
+	/* then, uCode */
+	guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
+	guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+	/* now RSA */
+	if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
+		DRM_ERROR("RSA key size is bad\n");
+		goto fail;
+	}
+	guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
+	guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+	/* At least, it should have header, uCode and RSA. Size of all three. */
+	size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+	if (fw->size < size) {
+		DRM_ERROR("Missing firmware components\n");
+		goto fail;
+	}
+	/* Header and uCode will be loaded to WOPCM. Size of the two. */
+	size = guc_fw->header_size + guc_fw->ucode_size;
+	/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+	if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
+		DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+		goto fail;
+	}
 	/*
 	 * The GuC firmware image has the version number embedded at a well-known
 	 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 	 * in terms of bytes (u8).
 	 */
-	css_header = fw->data + UOS_CSS_HEADER_OFFSET;
+	guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
-	guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
+	guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
-	guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
 	if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 	    guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 		fw_path = "";	/* unknown device */
 	}
+	if (!i915.enable_guc_submission)
+		return;
 	guc_fw->guc_dev = dev;
 	guc_fw->guc_fw_path = fw_path;
 	guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;

drivers/gpu/drm/i915/intel_hdmi.c+47−30

 	}
 }
-static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
+static i915_reg_t
-			    enum transcoder cpu_transcoder,
+hsw_dip_data_reg(struct drm_i915_private *dev_priv,
-			    enum hdmi_infoframe_type type,
+		 enum transcoder cpu_transcoder,
-			    int i)
+		 enum hdmi_infoframe_type type,
+		 int i)
 {
 	switch (type) {
 	case HDMI_INFOFRAME_TYPE_AVI:
 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 	default:
 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
-		return 0;
+		return INVALID_MMIO_REG;
 	}
 }
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	int i;
 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
-	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	if ((val & VIDEO_DIP_ENABLE) == 0)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	int i;
 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 val = I915_READ(TVIDEO_DIP_CTL(intel_crtc->pipe));
-	u32 val = I915_READ(reg);
 	if ((val & VIDEO_DIP_ENABLE) == 0)
 		return false;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	int i;
 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
-	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(intel_crtc->pipe));
-	u32 val = I915_READ(reg);
 	if ((val & VIDEO_DIP_ENABLE) == 0)
 		return false;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
+	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
-	u32 data_reg;
+	i915_reg_t data_reg;
 	int i;
 	u32 val = I915_READ(ctl_reg);
 	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
-	if (data_reg == 0)
+	if (i915_mmio_reg_valid(data_reg))
 		return;
 	val &= ~hsw_infoframe_enable(type);
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
+	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder));
-	u32 val = I915_READ(ctl_reg);
 	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
-	u32 reg = VIDEO_DIP_CTL;
+	i915_reg_t reg = VIDEO_DIP_CTL;
 	u32 val = I915_READ(reg);
 	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
-	u32 reg, val = 0;
+	i915_reg_t reg;
+	u32 val = 0;
 	if (HAS_DDI(dev_priv))
 		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
-	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	assert_hdmi_port_disabled(intel_hdmi);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
+	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 	u32 val = I915_READ(reg);
 	assert_hdmi_port_disabled(intel_hdmi);
 	 * matching DP port to be enabled on transcoder A.
 	 */
 	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
+		/*
+		 * We get CPU/PCH FIFO underruns on the other pipe when
+		 * doing the workaround. Sweep them under the rug.
+		 */
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
+		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 		temp &= ~SDVO_PIPE_B_SELECT;
 		temp |= SDVO_ENABLE;
 		/*
 		temp &= ~SDVO_ENABLE;
 		I915_WRITE(intel_hdmi->hdmi_reg, temp);
 		POSTING_READ(intel_hdmi->hdmi_reg);
+		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 	}
 	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
 	struct edid *edid = NULL;
 	bool connected = false;
-	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
+	if (force) {
+		intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
-	if (force)
 		edid = drm_get_edid(connector,
 				    intel_gmbus_get_adapter(dev_priv,
 				    intel_hdmi->ddc_bus));
-	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
+		intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
+	}
 	to_intel_connector(connector)->detect_edid = edid;
 	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
 		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
 		 * interrupts to check the external panel connection.
 		 */
-		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
+		if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 			intel_encoder->hpd_pin = HPD_PORT_A;
 		else
 			intel_encoder->hpd_pin = HPD_PORT_B;
 	}
 }
-void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
+void intel_hdmi_init(struct drm_device *dev,
+		     i915_reg_t hdmi_reg, enum port port)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port;
 	struct intel_encoder *intel_encoder;
 	struct intel_connector *intel_connector;
 		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
 	intel_dig_port->port = port;
+	dev_priv->dig_port_map[port] = intel_encoder;
 	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
-	intel_dig_port->dp.output_reg = 0;
+	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
 	intel_hdmi_init_connector(intel_dig_port, intel_connector);
 }

drivers/gpu/drm/i915/intel_i2c.c+16−15

@@ -36,7 +36,7 @@ · 35 unmodified lines
36		36
37	struct gmbus_pin {	37	struct gmbus_pin {
38	const char *name;	38	const char *name;
39	int reg;	39	i915_reg_t reg;
40	};	40	};
41		41
42	/* Map gmbus pin pairs to names and registers. */	42	/* Map gmbus pin pairs to names and registers. */
@@ -63,9 +63,9 @@ static const struct gmbus_pin gmbus_pins_skl[] = { · 20 unmodified lines
63	};	63	};
64		64
65	static const struct gmbus_pin gmbus_pins_bxt[] = {	65	static const struct gmbus_pin gmbus_pins_bxt[] = {
66	[GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },	66	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
67	[GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },	67	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
68	[GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },	68	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
69	};	69	};
70		70
71	/* pin is expected to be valid */	71	/* pin is expected to be valid */
@@ -74,7 +74,7 @@ static const struct gmbus_pin get_gmbus_pin(struct drm_i915_private dev_priv, · 2 unmodified lines
74	{	74	{
75	if (IS_BROXTON(dev_priv))	75	if (IS_BROXTON(dev_priv))
76	return &gmbus_pins_bxt[pin];	76	return &gmbus_pins_bxt[pin];
77	else if (IS_SKYLAKE(dev_priv))	77	else if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv))
78	return &gmbus_pins_skl[pin];	78	return &gmbus_pins_skl[pin];
79	else if (IS_BROADWELL(dev_priv))	79	else if (IS_BROADWELL(dev_priv))
80	return &gmbus_pins_bdw[pin];	80	return &gmbus_pins_bdw[pin];
@@ -89,14 +89,15 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, · 8 unmodified lines
89		89
90	if (IS_BROXTON(dev_priv))	90	if (IS_BROXTON(dev_priv))
91	size = ARRAY_SIZE(gmbus_pins_bxt);	91	size = ARRAY_SIZE(gmbus_pins_bxt);
92	else if (IS_SKYLAKE(dev_priv))	92	else if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv))
93	size = ARRAY_SIZE(gmbus_pins_skl);	93	size = ARRAY_SIZE(gmbus_pins_skl);
94	else if (IS_BROADWELL(dev_priv))	94	else if (IS_BROADWELL(dev_priv))
95	size = ARRAY_SIZE(gmbus_pins_bdw);	95	size = ARRAY_SIZE(gmbus_pins_bdw);
96	else	96	else
97	size = ARRAY_SIZE(gmbus_pins);	97	size = ARRAY_SIZE(gmbus_pins);
98		98
99	return pin < size && get_gmbus_pin(dev_priv, pin)->reg;	99	return pin < size &&
		100	i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
100	}	101	}
101		102
102	/* Intel GPIO access functions */	103	/* Intel GPIO access functions */
@@ -240,9 +241,8 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) · 137 unmodified lines
240		241
241	algo = &bus->bit_algo;	242	algo = &bus->bit_algo;
242		243
243	bus->gpio_reg = dev_priv->gpio_mmio_base +	244	bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
244	get_gmbus_pin(dev_priv, pin)->reg;	245	i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
245
246	bus->adapter.algo_data = algo;	246	bus->adapter.algo_data = algo;
247	algo->setsda = set_data;	247	algo->setsda = set_data;
248	algo->setscl = set_clock;	248	algo->setscl = set_clock;
@@ -628,12 +628,13 @@ int intel_setup_gmbus(struct drm_device *dev) · 379 unmodified lines
628		628
629	if (HAS_PCH_NOP(dev))	629	if (HAS_PCH_NOP(dev))
630	return 0;	630	return 0;
631	else if (HAS_PCH_SPLIT(dev))	631
632	dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;	632	if (IS_VALLEYVIEW(dev))
633	else if (IS_VALLEYVIEW(dev))
634	dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;	633	dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
635	else	634	else if (!HAS_GMCH_DISPLAY(dev_priv))
636	dev_priv->gpio_mmio_base = 0;	635	dev_priv->gpio_mmio_base =
		636	i915_mmio_reg_offset(PCH_GPIOA) -
		637	i915_mmio_reg_offset(GPIOA);
637		638
638	mutex_init(&dev_priv->gmbus_mutex);	639	mutex_init(&dev_priv->gmbus_mutex);
639	init_waitqueue_head(&dev_priv->gmbus_wait_queue);	640	init_waitqueue_head(&dev_priv->gmbus_wait_queue);

drivers/gpu/drm/i915/intel_lrc.c+67−81

 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 #define GEN8_CTX_PRIVILEGE (1<<8)
-#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
+#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
+	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
+	(reg_state)[(pos)+1] = (val); \
+} while (0)
+#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\
 	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
 	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
 	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
-}
+} while (0)
-#define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
+#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
 	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
 	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
-}
+} while (0)
 enum {
 	ADVANCED_CONTEXT = 0,
 {
 	struct drm_device *dev = ring->dev;
-	return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-		(IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) &&
+		IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
 	       (ring->id == VCS || ring->id == VCS2);
 }
 		intel_logical_ring_emit(ringbuf, MI_NOOP);
 		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
-		intel_logical_ring_emit(ringbuf, INSTPM);
+		intel_logical_ring_emit_reg(ringbuf, INSTPM);
 		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 		intel_logical_ring_advance(ringbuf);
 	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
 	for (i = 0; i < w->count; i++) {
-		intel_logical_ring_emit(ringbuf, w->reg[i].addr);
+		intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
 		intel_logical_ring_emit(ringbuf, w->reg[i].value);
 	}
 	intel_logical_ring_emit(ringbuf, MI_NOOP);
 		batch[__index] = (cmd);					\
 	} while (0)
+#define wa_ctx_emit_reg(batch, index, reg) \
+	wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
 /*
  * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 	 * this batch updates GEN8_L3SQCREG4 with default value we need to
 	 * set this bit here to retain the WA during flush.
 	 */
-	if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
+	if (IS_SKL_REVID(ring->dev, 0, SKL_REVID_E0))
 		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
 	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
 				   MI_SRM_LRM_GLOBAL_GTT));
-	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
 	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
 	wa_ctx_emit(batch, index, 0);
 	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
 	wa_ctx_emit(batch, index, l3sqc4_flush);
 	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
 	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
 				   MI_SRM_LRM_GLOBAL_GTT));
-	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
 	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
 	wa_ctx_emit(batch, index, 0);
 	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
-	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
+	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
 	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
+	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
+		wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
 		wa_ctx_emit(batch, index,
 			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
 		wa_ctx_emit(batch, index, MI_NOOP);
 	}
 	/* WaDisableCtxRestoreArbitration:skl,bxt */
-	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
+	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
+	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
 	I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
 	I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
-	if (ring->status_page.obj) {
-		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
-			   (u32)ring->status_page.gfx_addr);
-		POSTING_READ(RING_HWS_PGA(ring->mmio_base));
-	}
 	I915_WRITE(RING_MODE_GEN7(ring),
 		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
 		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
-		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
+		intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_UDW(ring, i));
 		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
-		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
+		intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_LDW(ring, i));
 		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
 	}
 	i915_gem_batch_pool_init(dev, &ring->batch_pool);
 	init_waitqueue_head(&ring->irq_queue);
+	INIT_LIST_HEAD(&ring->buffers);
 	INIT_LIST_HEAD(&ring->execlist_queue);
 	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
 	spin_lock_init(&ring->execlist_lock);
 		ring->init_hw = gen8_init_render_ring;
 	ring->init_context = gen8_init_rcs_context;
 	ring->cleanup = intel_fini_pipe_control;
-	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		ring->get_seqno = bxt_a_get_seqno;
 		ring->set_seqno = bxt_a_set_seqno;
 	} else {
 		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
 	ring->init_hw = gen8_init_common_ring;
-	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		ring->get_seqno = bxt_a_get_seqno;
 		ring->set_seqno = bxt_a_set_seqno;
 	} else {
 		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 	ring->init_hw = gen8_init_common_ring;
-	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		ring->get_seqno = bxt_a_get_seqno;
 		ring->set_seqno = bxt_a_set_seqno;
 	} else {
 		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
 	ring->init_hw = gen8_init_common_ring;
-	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
+	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 		ring->get_seqno = bxt_a_get_seqno;
 		ring->set_seqno = bxt_a_set_seqno;
 	} else {
 	 * only for the first context restore: on a subsequent save, the GPU will
 	 * recreate this batchbuffer with new values (including all the missing
 	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
-	if (ring->id == RCS)
+	reg_state[CTX_LRI_HEADER_0] =
-		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
+		MI_LOAD_REGISTER_IMM(ring->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
-	else
+	ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(ring),
-		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
+		       _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
-	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
+					  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
-	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
+					  CTX_CTRL_RS_CTX_ENABLE));
-	reg_state[CTX_CONTEXT_CONTROL+1] =
+	ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(ring->mmio_base), 0);
-		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
+	ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(ring->mmio_base), 0);
-				   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
-				   CTX_CTRL_RS_CTX_ENABLE);
-	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
-	reg_state[CTX_RING_HEAD+1] = 0;
-	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
-	reg_state[CTX_RING_TAIL+1] = 0;
-	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
 	/* Ring buffer start address is not known until the buffer is pinned.
 	 * It is written to the context image in execlists_update_context()
 	 */
-	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
+	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, RING_START(ring->mmio_base), 0);
-	reg_state[CTX_RING_BUFFER_CONTROL+1] =
+	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, RING_CTL(ring->mmio_base),
-			((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
+		       ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
-	reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
+	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, RING_BBADDR_UDW(ring->mmio_base), 0);
-	reg_state[CTX_BB_HEAD_U+1] = 0;
+	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, RING_BBADDR(ring->mmio_base), 0);
-	reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
+	ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, RING_BBSTATE(ring->mmio_base),
-	reg_state[CTX_BB_HEAD_L+1] = 0;
+		       RING_BB_PPGTT);
-	reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
+	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(ring->mmio_base), 0);
-	reg_state[CTX_BB_STATE+1] = (1<<5);
+	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(ring->mmio_base), 0);
-	reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
+	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, RING_SBBSTATE(ring->mmio_base), 0);
-	reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
-	reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
-	reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
-	reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
-	reg_state[CTX_SECOND_BB_STATE+1] = 0;
 	if (ring->id == RCS) {
-		reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
+		ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(ring->mmio_base), 0);
-		reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
+		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(ring->mmio_base), 0);
-		reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
+		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, RING_INDIRECT_CTX_OFFSET(ring->mmio_base), 0);
-		reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
-		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
-		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
 		if (ring->wa_ctx.obj) {
 			struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
 			uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
 				0x01;
 		}
 	}
-	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
+	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
-	reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
+	ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(ring->mmio_base), 0);
-	reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
+	/* PDP values well be assigned later if needed */
-	reg_state[CTX_CTX_TIMESTAMP+1] = 0;
+	ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(ring, 3), 0);
-	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(ring, 3), 0);
-	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(ring, 2), 0);
-	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(ring, 2), 0);
-	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(ring, 1), 0);
-	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(ring, 1), 0);
-	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(ring, 0), 0);
-	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
+	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(ring, 0), 0);
-	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
 	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
 		/* 64b PPGTT (48bit canonical)
 	if (ring->id == RCS) {
 		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
-		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
+		ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
-		reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
+			       make_rpcs(dev));
 	}
 	kunmap_atomic(reg_state);

drivers/gpu/drm/i915/intel_lrc.h+12−7

 #define GEN8_CSB_PTR_MASK 0x07
 /* Execlists regs */
-#define RING_ELSP(ring)			((ring)->mmio_base+0x230)
+#define RING_ELSP(ring)				_MMIO((ring)->mmio_base + 0x230)
-#define RING_EXECLIST_STATUS_LO(ring)	((ring)->mmio_base+0x234)
+#define RING_EXECLIST_STATUS_LO(ring)		_MMIO((ring)->mmio_base + 0x234)
-#define RING_EXECLIST_STATUS_HI(ring)	((ring)->mmio_base+0x234 + 4)
+#define RING_EXECLIST_STATUS_HI(ring)		_MMIO((ring)->mmio_base + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
+#define RING_CONTEXT_CONTROL(ring)		_MMIO((ring)->mmio_base + 0x244)
 #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
-#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	((ring)->mmio_base+0x370 + (i) * 8)
+#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	((ring)->mmio_base+0x370 + (i) * 8 + 4)
+#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
-#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
+#define RING_CONTEXT_STATUS_PTR(ring)		_MMIO((ring)->mmio_base + 0x3a0)
 /* Logical Rings */
 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
 	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
 	ringbuf->tail += 4;
 }
+static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
+					       i915_reg_t reg)
+{
+	intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
+}
 /* Logical Ring Contexts */

drivers/gpu/drm/i915/intel_lvds.c+5−6

 	struct intel_encoder base;
 	bool is_dual_link;
-	u32 reg;
+	i915_reg_t reg;
 	u32 a3_power;
 	struct intel_lvds_connector *attached_connector;
 	struct intel_connector *intel_connector =
 		&lvds_encoder->attached_connector->base;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 ctl_reg, stat_reg;
+	i915_reg_t ctl_reg, stat_reg;
 	if (HAS_PCH_SPLIT(dev)) {
 		ctl_reg = PCH_PP_CONTROL;
 	struct drm_device *dev = encoder->base.dev;
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 ctl_reg, stat_reg;
+	i915_reg_t ctl_reg, stat_reg;
 	if (HAS_PCH_SPLIT(dev)) {
 		ctl_reg = PCH_PP_CONTROL;
 	struct drm_display_mode *downclock_mode = NULL;
 	struct edid *edid;
 	struct drm_crtc *crtc;
-	u32 lvds_reg;
+	i915_reg_t lvds_reg;
 	u32 lvds;
 	int pipe;
 	u8 pin;
 	DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
 		      lvds_encoder->is_dual_link ? "dual" : "single");
-	lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
+	lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
-				 LVDS_A3_POWER_MASK;
 	lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
 	if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {

drivers/gpu/drm/i915/intel_mocs.c+35−26

@@ -143,7 +143,7 @@ static bool get_mocs_settings(struct drm_device *dev, · 142 unmodified lines
143	{	143	{
144	bool result = false;	144	bool result = false;
145		145
146	if (IS_SKYLAKE(dev)) {	146	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
147	table->size = ARRAY_SIZE(skylake_mocs_table);	147	table->size = ARRAY_SIZE(skylake_mocs_table);
148	table->table = skylake_mocs_table;	148	table->table = skylake_mocs_table;
149	result = true;	149	result = true;
@@ -159,11 +159,30 @@ static bool get_mocs_settings(struct drm_device *dev, · 9 unmodified lines
159	return result;	159	return result;
160	}	160	}
161		161
		162	static i915_reg_t mocs_register(enum intel_ring_id ring, int index)
		163	{
		164	switch (ring) {
		165	case RCS:
		166	return GEN9_GFX_MOCS(index);
		167	case VCS:
		168	return GEN9_MFX0_MOCS(index);
		169	case BCS:
		170	return GEN9_BLT_MOCS(index);
		171	case VECS:
		172	return GEN9_VEBOX_MOCS(index);
		173	case VCS2:
		174	return GEN9_MFX1_MOCS(index);
		175	default:
		176	MISSING_CASE(ring);
		177	return INVALID_MMIO_REG;
		178	}
		179	}
		180
162	/**	181	/**
163	* emit_mocs_control_table() - emit the mocs control table	182	* emit_mocs_control_table() - emit the mocs control table
164	* @req: Request to set up the MOCS table for.	183	* @req: Request to set up the MOCS table for.
165	* @table: The values to program into the control regs.	184	* @table: The values to program into the control regs.
166	* @reg_base: The base for the engine that needs to be programmed.	185	* @ring: The engine for whom to emit the registers.
167	*	186	*
168	* This function simply emits a MI_LOAD_REGISTER_IMM command for the	187	* This function simply emits a MI_LOAD_REGISTER_IMM command for the
169	* given table starting at the given address.	188	* given table starting at the given address.
@@ -172,7 +191,7 @@ static bool get_mocs_settings(struct drm_device *dev, · 2 unmodified lines
172	*/	191	*/
173	static int emit_mocs_control_table(struct drm_i915_gem_request *req,	192	static int emit_mocs_control_table(struct drm_i915_gem_request *req,
174	const struct drm_i915_mocs_table *table,	193	const struct drm_i915_mocs_table *table,
175	u32 reg_base)	194	enum intel_ring_id ring)
176	{	195	{
177	struct intel_ringbuffer *ringbuf = req->ringbuf;	196	struct intel_ringbuffer *ringbuf = req->ringbuf;
178	unsigned int index;	197	unsigned int index;
@@ -191,7 +210,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req, · 12 unmodified lines
191	MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));	210	MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
192		211
193	for (index = 0; index < table->size; index++) {	212	for (index = 0; index < table->size; index++) {
194	intel_logical_ring_emit(ringbuf, reg_base + index * 4);	213	intel_logical_ring_emit_reg(ringbuf, mocs_register(ring, index));
195	intel_logical_ring_emit(ringbuf,	214	intel_logical_ring_emit(ringbuf,
196	table->table[index].control_value);	215	table->table[index].control_value);
197	}	216	}
@@ -205,7 +224,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req, · 7 unmodified lines
205	* that value to all the used entries.	224	* that value to all the used entries.
206	*/	225	*/
207	for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {	226	for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
208	intel_logical_ring_emit(ringbuf, reg_base + index * 4);	227	intel_logical_ring_emit_reg(ringbuf, mocs_register(ring, index));
209	intel_logical_ring_emit(ringbuf, table->table[0].control_value);	228	intel_logical_ring_emit(ringbuf, table->table[0].control_value);
210	}	229	}
211		230
@@ -253,7 +272,7 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req, · 41 unmodified lines
253	value = (table->table[count].l3cc_value & 0xffff) \|	272	value = (table->table[count].l3cc_value & 0xffff) \|
254	((table->table[count + 1].l3cc_value & 0xffff) << 16);	273	((table->table[count + 1].l3cc_value & 0xffff) << 16);
255		274
256	intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);	275	intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
257	intel_logical_ring_emit(ringbuf, value);	276	intel_logical_ring_emit(ringbuf, value);
258	}	277	}
259		278
@@ -270,7 +289,7 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req, · 10 unmodified lines
270	* they are reserved by the hardware.	289	* they are reserved by the hardware.
271	*/	290	*/
272	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {	291	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
273	intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);	292	intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
274	intel_logical_ring_emit(ringbuf, value);	293	intel_logical_ring_emit(ringbuf, value);
275		294
276	value = filler;	295	value = filler;
@@ -304,26 +323,16 @@ int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req) · 27 unmodified lines
304	int ret;	323	int ret;
305		324
306	if (get_mocs_settings(req->ring->dev, &t)) {	325	if (get_mocs_settings(req->ring->dev, &t)) {
307	/* Program the control registers */	326	struct drm_i915_private *dev_priv = req->i915;
308	ret = emit_mocs_control_table(req, &t, GEN9_GFX_MOCS_0);	327	struct intel_engine_cs *ring;
309	if (ret)	328	enum intel_ring_id ring_id;
310	return ret;
311
312	ret = emit_mocs_control_table(req, &t, GEN9_MFX0_MOCS_0);
313	if (ret)
314	return ret;
315		329
316	ret = emit_mocs_control_table(req, &t, GEN9_MFX1_MOCS_0);	330	/* Program the control registers */
317	if (ret)	331	for_each_ring(ring, dev_priv, ring_id) {
318	return ret;	332	ret = emit_mocs_control_table(req, &t, ring_id);
319		333	if (ret)
320	ret = emit_mocs_control_table(req, &t, GEN9_VEBOX_MOCS_0);	334	return ret;
321	if (ret)	335	}
322	return ret;
323
324	ret = emit_mocs_control_table(req, &t, GEN9_BLT_MOCS_0);
325	if (ret)
326	return ret;
327		336
328	/* Now program the l3cc registers */	337	/* Now program the l3cc registers */
329	ret = emit_mocs_l3cc_table(req, &t);	338	ret = emit_mocs_l3cc_table(req, &t);

drivers/gpu/drm/i915/intel_opregion.c+1−1

@@ -682,7 +682,7 @@ static void intel_didl_outputs(struct drm_device *dev) · 681 unmodified lines
682	}	682	}
683		683
684	if (!acpi_video_bus) {	684	if (!acpi_video_bus) {
685	DRM_ERROR("No ACPI video bus found\n");	685	DRM_DEBUG_KMS("No ACPI video bus found\n");
686	return;	686	return;
687	}	687	}
688		688

drivers/gpu/drm/i915/intel_overlay.c+1−1

@@ -749,7 +749,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, · 748 unmodified lines
749	if (ret != 0)	749	if (ret != 0)
750	return ret;	750	return ret;
751		751
752	ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL, NULL,	752	ret = i915_gem_object_pin_to_display_plane(new_bo, 0,
753	&i915_ggtt_view_normal);	753	&i915_ggtt_view_normal);
754	if (ret != 0)	754	if (ret != 0)
755	return ret;	755	return ret;

drivers/gpu/drm/i915/intel_pm.c+256−374

@@ -1708,13 +1708,6 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, · 1707 unmodified lines
1708	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;	1708	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709	}	1709	}
1710		1710
1711	struct skl_pipe_wm_parameters {
1712	bool active;
1713	uint32_t pipe_htotal;
1714	uint32_t pixel_rate; /* in KHz */
1715	struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1716	};
1717
1718	struct ilk_wm_maximums {	1711	struct ilk_wm_maximums {
1719	uint16_t pri;	1712	uint16_t pri;
1720	uint16_t spr;	1713	uint16_t spr;
@@ -1722,13 +1715,6 @@ struct ilk_wm_maximums { · 1 unmodified line
1722	uint16_t fbc;	1715	uint16_t fbc;
1723	};	1716	};
1724		1717
1725	/* used in computing the new watermarks state */
1726	struct intel_wm_config {
1727	unsigned int num_pipes_active;
1728	bool sprites_enabled;
1729	bool sprites_scaled;
1730	};
1731
1732	/*	1718	/*
1733	* For both WM_PIPE and WM_LP.	1719	* For both WM_PIPE and WM_LP.
1734	* mem_value must be in 0.1us units.	1720	* mem_value must be in 0.1us units.
@@ -1979,9 +1965,11 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, · 244 unmodified lines
1979	const struct intel_crtc *intel_crtc,	1965	const struct intel_crtc *intel_crtc,
1980	int level,	1966	int level,
1981	struct intel_crtc_state *cstate,	1967	struct intel_crtc_state *cstate,
		1968	struct intel_plane_state *pristate,
		1969	struct intel_plane_state *sprstate,
		1970	struct intel_plane_state *curstate,
1982	struct intel_wm_level *result)	1971	struct intel_wm_level *result)
1983	{	1972	{
1984	struct intel_plane *intel_plane;
1985	uint16_t pri_latency = dev_priv->wm.pri_latency[level];	1973	uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1986	uint16_t spr_latency = dev_priv->wm.spr_latency[level];	1974	uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1987	uint16_t cur_latency = dev_priv->wm.cur_latency[level];	1975	uint16_t cur_latency = dev_priv->wm.cur_latency[level];
@@ -1993,29 +1981,11 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, · 5 unmodified lines
1993	cur_latency *= 5;	1981	cur_latency *= 5;
1994	}	1982	}
1995		1983
1996	for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {	1984	result->pri_val = ilk_compute_pri_wm(cstate, pristate,
1997	struct intel_plane_state *pstate =	1985	pri_latency, level);
1998	to_intel_plane_state(intel_plane->base.state);	1986	result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
1999		1987	result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2000	switch (intel_plane->base.type) {	1988	result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2001	case DRM_PLANE_TYPE_PRIMARY:
2002	result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2003	pri_latency,
2004	level);
2005	result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2006	result->pri_val);
2007	break;
2008	case DRM_PLANE_TYPE_OVERLAY:
2009	result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2010	spr_latency);
2011	break;
2012	case DRM_PLANE_TYPE_CURSOR:
2013	result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2014	cur_latency);
2015	break;
2016	}
2017	}
2018
2019	result->enable = true;	1989	result->enable = true;
2020	}	1990	}
2021		1991
@@ -2274,34 +2244,19 @@ static void skl_setup_wm_latency(struct drm_device *dev) · 252 unmodified lines
2274	intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);	2244	intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2275	}	2245	}
2276		2246
2277	static void ilk_compute_wm_config(struct drm_device *dev,
2278	struct intel_wm_config *config)
2279	{
2280	struct intel_crtc *intel_crtc;
2281
2282	/* Compute the currently _active_ config */
2283	for_each_intel_crtc(dev, intel_crtc) {
2284	const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2285
2286	if (!wm->pipe_enabled)
2287	continue;
2288
2289	config->sprites_enabled \|= wm->sprites_enabled;
2290	config->sprites_scaled \|= wm->sprites_scaled;
2291	config->num_pipes_active++;
2292	}
2293	}
2294
2295	/* Compute new watermarks for the pipe */	2247	/* Compute new watermarks for the pipe */
2296	static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,	2248	static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2297	struct intel_pipe_wm *pipe_wm)	2249	struct drm_atomic_state *state)
2298	{	2250	{
2299	struct drm_crtc *crtc = cstate->base.crtc;	2251	struct intel_pipe_wm *pipe_wm;
2300	struct drm_device *dev = crtc->dev;	2252	struct drm_device *dev = intel_crtc->base.dev;
2301	const struct drm_i915_private *dev_priv = dev->dev_private;	2253	const struct drm_i915_private *dev_priv = dev->dev_private;
2302	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2254	struct intel_crtc_state *cstate = NULL;
2303	struct intel_plane *intel_plane;	2255	struct intel_plane *intel_plane;
		2256	struct drm_plane_state *ps;
		2257	struct intel_plane_state *pristate = NULL;
2304	struct intel_plane_state *sprstate = NULL;	2258	struct intel_plane_state *sprstate = NULL;
		2259	struct intel_plane_state *curstate = NULL;
2305	int level, max_level = ilk_wm_max_level(dev);	2260	int level, max_level = ilk_wm_max_level(dev);
2306	/* LP0 watermark maximums depend on this pipe alone */	2261	/* LP0 watermark maximums depend on this pipe alone */
2307	struct intel_wm_config config = {	2262	struct intel_wm_config config = {
@@ -2309,11 +2264,24 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, · 1 unmodified line
2309	};	2264	};
2310	struct ilk_wm_maximums max;	2265	struct ilk_wm_maximums max;
2311		2266
		2267	cstate = intel_atomic_get_crtc_state(state, intel_crtc);
		2268	if (IS_ERR(cstate))
		2269	return PTR_ERR(cstate);
		2270
		2271	pipe_wm = &cstate->wm.optimal.ilk;
		2272
2312	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {	2273	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2313	if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {	2274	ps = drm_atomic_get_plane_state(state,
2314	sprstate = to_intel_plane_state(intel_plane->base.state);	2275	&intel_plane->base);
2315	break;	2276	if (IS_ERR(ps))
2316	}	2277	return PTR_ERR(ps);
		2278
		2279	if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
		2280	pristate = to_intel_plane_state(ps);
		2281	else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
		2282	sprstate = to_intel_plane_state(ps);
		2283	else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
		2284	curstate = to_intel_plane_state(ps);
2317	}	2285	}
2318		2286
2319	config.sprites_enabled = sprstate->visible;	2287	config.sprites_enabled = sprstate->visible;
@@ -2322,7 +2290,7 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, · 2 unmodified lines
2322	drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);	2290	drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2323		2291
2324	pipe_wm->pipe_enabled = cstate->base.active;	2292	pipe_wm->pipe_enabled = cstate->base.active;
2325	pipe_wm->sprites_enabled = sprstate->visible;	2293	pipe_wm->sprites_enabled = config.sprites_enabled;
2326	pipe_wm->sprites_scaled = config.sprites_scaled;	2294	pipe_wm->sprites_scaled = config.sprites_scaled;
2327		2295
2328	/* ILK/SNB: LP2+ watermarks only w/o sprites */	2296	/* ILK/SNB: LP2+ watermarks only w/o sprites */
@@ -2333,24 +2301,27 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, · 4 unmodified lines
2333	if (config.sprites_scaled)	2301	if (config.sprites_scaled)
2334	max_level = 0;	2302	max_level = 0;
2335		2303
2336	ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);	2304	ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
		2305	pristate, sprstate, curstate, &pipe_wm->wm[0]);
2337		2306
2338	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))	2307	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
2339	pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);	2308	pipe_wm->linetime = hsw_compute_linetime_wm(dev,
		2309	&intel_crtc->base);
2340		2310
2341	/* LP0 watermarks always use 1/2 DDB partitioning */	2311	/* LP0 watermarks always use 1/2 DDB partitioning */
2342	ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);	2312	ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2343		2313
2344	/* At least LP0 must be valid */	2314	/* At least LP0 must be valid */
2345	if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))	2315	if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2346	return false;	2316	return -EINVAL;
2347		2317
2348	ilk_compute_wm_reg_maximums(dev, 1, &max);	2318	ilk_compute_wm_reg_maximums(dev, 1, &max);
2349		2319
2350	for (level = 1; level <= max_level; level++) {	2320	for (level = 1; level <= max_level; level++) {
2351	struct intel_wm_level wm = {};	2321	struct intel_wm_level wm = {};
2352		2322
2353	ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);	2323	ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
		2324	pristate, sprstate, curstate, &wm);
2354		2325
2355	/*	2326	/*
2356	* Disable any watermark level that exceeds the	2327	* Disable any watermark level that exceeds the
@@ -2363,7 +2334,7 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, · 6 unmodified lines
2363	pipe_wm->wm[level] = wm;	2334	pipe_wm->wm[level] = wm;
2364	}	2335	}
2365		2336
2366	return true;	2337	return 0;
2367	}	2338	}
2368		2339
2369	/*	2340	/*
@@ -2378,7 +2349,9 @@ static void ilk_merge_wm_level(struct drm_device *dev, · 8 unmodified lines
2378	ret_wm->enable = true;	2349	ret_wm->enable = true;
2379		2350
2380	for_each_intel_crtc(dev, intel_crtc) {	2351	for_each_intel_crtc(dev, intel_crtc) {
2381	const struct intel_pipe_wm *active = &intel_crtc->wm.active;	2352	const struct intel_crtc_state *cstate =
		2353	to_intel_crtc_state(intel_crtc->base.state);
		2354	const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2382	const struct intel_wm_level *wm = &active->wm[level];	2355	const struct intel_wm_level *wm = &active->wm[level];
2383		2356
2384	if (!active->pipe_enabled)	2357	if (!active->pipe_enabled)
@@ -2526,14 +2499,15 @@ static void ilk_compute_wm_results(struct drm_device *dev, · 141 unmodified lines
2526		2499
2527	/* LP0 register values */	2500	/* LP0 register values */
2528	for_each_intel_crtc(dev, intel_crtc) {	2501	for_each_intel_crtc(dev, intel_crtc) {
		2502	const struct intel_crtc_state *cstate =
		2503	to_intel_crtc_state(intel_crtc->base.state);
2529	enum pipe pipe = intel_crtc->pipe;	2504	enum pipe pipe = intel_crtc->pipe;
2530	const struct intel_wm_level *r =	2505	const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2531	&intel_crtc->wm.active.wm[0];
2532		2506
2533	if (WARN_ON(!r->enable))	2507	if (WARN_ON(!r->enable))
2534	continue;	2508	continue;
2535		2509
2536	results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;	2510	results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2537		2511
2538	results->wm_pipe[pipe] =	2512	results->wm_pipe[pipe] =
2539	(r->pri_val << WM0_PIPE_PLANE_SHIFT) \|	2513	(r->pri_val << WM0_PIPE_PLANE_SHIFT) \|
@@ -2755,18 +2729,40 @@ static bool ilk_disable_lp_wm(struct drm_device *dev) · 215 unmodified lines
2755	#define SKL_DDB_SIZE 896 /* in blocks */	2729	#define SKL_DDB_SIZE 896 /* in blocks */
2756	#define BXT_DDB_SIZE 512	2730	#define BXT_DDB_SIZE 512
2757		2731
		2732	/*
		2733	* Return the index of a plane in the SKL DDB and wm result arrays. Primary
		2734	* plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
		2735	* other universal planes are in indices 1..n. Note that this may leave unused
		2736	* indices between the top "sprite" plane and the cursor.
		2737	*/
		2738	static int
		2739	skl_wm_plane_id(const struct intel_plane *plane)
		2740	{
		2741	switch (plane->base.type) {
		2742	case DRM_PLANE_TYPE_PRIMARY:
		2743	return 0;
		2744	case DRM_PLANE_TYPE_CURSOR:
		2745	return PLANE_CURSOR;
		2746	case DRM_PLANE_TYPE_OVERLAY:
		2747	return plane->plane + 1;
		2748	default:
		2749	MISSING_CASE(plane->base.type);
		2750	return plane->plane;
		2751	}
		2752	}
		2753
2758	static void	2754	static void
2759	skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,	2755	skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2760	struct drm_crtc *for_crtc,	2756	const struct intel_crtc_state *cstate,
2761	const struct intel_wm_config *config,	2757	const struct intel_wm_config *config,
2762	const struct skl_pipe_wm_parameters *params,
2763	struct skl_ddb_entry alloc / out */)	2758	struct skl_ddb_entry alloc / out */)
2764	{	2759	{
		2760	struct drm_crtc *for_crtc = cstate->base.crtc;
2765	struct drm_crtc *crtc;	2761	struct drm_crtc *crtc;
2766	unsigned int pipe_size, ddb_size;	2762	unsigned int pipe_size, ddb_size;
2767	int nth_active_pipe;	2763	int nth_active_pipe;
2768		2764
2769	if (!params->active) {	2765	if (!cstate->base.active) {
2770	alloc->start = 0;	2766	alloc->start = 0;
2771	alloc->end = 0;	2767	alloc->end = 0;
2772	return;	2768	return;
@@ -2837,19 +2833,29 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, · 64 unmodified lines
2837	}	2833	}
2838		2834
2839	static unsigned int	2835	static unsigned int
2840	skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)	2836	skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
		2837	const struct drm_plane_state *pstate,
		2838	int y)
2841	{	2839	{
		2840	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
		2841	struct drm_framebuffer *fb = pstate->fb;
2842		2842
2843	/* for planar format */	2843	/* for planar format */
2844	if (p->y_bytes_per_pixel) {	2844	if (fb->pixel_format == DRM_FORMAT_NV12) {
2845	if (y) /* y-plane data rate */	2845	if (y) /* y-plane data rate */
2846	return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;	2846	return intel_crtc->config->pipe_src_w *
		2847	intel_crtc->config->pipe_src_h *
		2848	drm_format_plane_cpp(fb->pixel_format, 0);
2847	else /* uv-plane data rate */	2849	else /* uv-plane data rate */
2848	return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;	2850	return (intel_crtc->config->pipe_src_w/2) *
		2851	(intel_crtc->config->pipe_src_h/2) *
		2852	drm_format_plane_cpp(fb->pixel_format, 1);
2849	}	2853	}
2850		2854
2851	/* for packed formats */	2855	/* for packed formats */
2852	return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;	2856	return intel_crtc->config->pipe_src_w *
		2857	intel_crtc->config->pipe_src_h *
		2858	drm_format_plane_cpp(fb->pixel_format, 0);
2853	}	2859	}
2854		2860
2855	/*	2861	/*
@@ -2858,46 +2864,55 @@ skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) · 2 unmodified lines
2858	* 3 * 4096 * 8192 * 4 < 2^32	2864	* 3 * 4096 * 8192 * 4 < 2^32
2859	*/	2865	*/
2860	static unsigned int	2866	static unsigned int
2861	skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,	2867	skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2862	const struct skl_pipe_wm_parameters *params)
2863	{	2868	{
		2869	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
		2870	struct drm_device *dev = intel_crtc->base.dev;
		2871	const struct intel_plane *intel_plane;
2864	unsigned int total_data_rate = 0;	2872	unsigned int total_data_rate = 0;
2865	int plane;
2866		2873
2867	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {	2874	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2868	const struct intel_plane_wm_parameters *p;	2875	const struct drm_plane_state *pstate = intel_plane->base.state;
2869		2876
2870	p = &params->plane[plane];	2877	if (pstate->fb == NULL)
2871	if (!p->enabled)
2872	continue;	2878	continue;
2873		2879
2874	total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */	2880	if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2875	if (p->y_bytes_per_pixel) {	2881	continue;
2876	total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */	2882
2877	}	2883	/* packed/uv */
		2884	total_data_rate += skl_plane_relative_data_rate(cstate,
		2885	pstate,
		2886	0);
		2887
		2888	if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
		2889	/* y-plane */
		2890	total_data_rate += skl_plane_relative_data_rate(cstate,
		2891	pstate,
		2892	1);
2878	}	2893	}
2879		2894
2880	return total_data_rate;	2895	return total_data_rate;
2881	}	2896	}
2882		2897
2883	static void	2898	static void
2884	skl_allocate_pipe_ddb(struct drm_crtc *crtc,	2899	skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2885	const struct intel_wm_config *config,
2886	const struct skl_pipe_wm_parameters *params,
2887	struct skl_ddb_allocation ddb / out */)	2900	struct skl_ddb_allocation ddb / out */)
2888	{	2901	{
		2902	struct drm_crtc *crtc = cstate->base.crtc;
2889	struct drm_device *dev = crtc->dev;	2903	struct drm_device *dev = crtc->dev;
2890	struct drm_i915_private *dev_priv = dev->dev_private;	2904	struct drm_i915_private *dev_priv = to_i915(dev);
		2905	struct intel_wm_config *config = &dev_priv->wm.config;
2891	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2906	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		2907	struct intel_plane *intel_plane;
2892	enum pipe pipe = intel_crtc->pipe;	2908	enum pipe pipe = intel_crtc->pipe;
2893	struct skl_ddb_entry *alloc = &ddb->pipe[pipe];	2909	struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2894	uint16_t alloc_size, start, cursor_blocks;	2910	uint16_t alloc_size, start, cursor_blocks;
2895	uint16_t minimum[I915_MAX_PLANES];	2911	uint16_t minimum[I915_MAX_PLANES];
2896	uint16_t y_minimum[I915_MAX_PLANES];	2912	uint16_t y_minimum[I915_MAX_PLANES];
2897	unsigned int total_data_rate;	2913	unsigned int total_data_rate;
2898	int plane;
2899		2914
2900	skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);	2915	skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2901	alloc_size = skl_ddb_entry_size(alloc);	2916	alloc_size = skl_ddb_entry_size(alloc);
2902	if (alloc_size == 0) {	2917	if (alloc_size == 0) {
2903	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));	2918	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
@@ -2914,17 +2929,20 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, · 10 unmodified lines
2914	alloc->end -= cursor_blocks;	2929	alloc->end -= cursor_blocks;
2915		2930
2916	/* 1. Allocate the mininum required blocks for each active plane */	2931	/* 1. Allocate the mininum required blocks for each active plane */
2917	for_each_plane(dev_priv, pipe, plane) {	2932	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2918	const struct intel_plane_wm_parameters *p;	2933	struct drm_plane *plane = &intel_plane->base;
		2934	struct drm_framebuffer *fb = plane->state->fb;
		2935	int id = skl_wm_plane_id(intel_plane);
2919		2936
2920	p = &params->plane[plane];	2937	if (fb == NULL)
2921	if (!p->enabled)	2938	continue;
		2939	if (plane->type == DRM_PLANE_TYPE_CURSOR)
2922	continue;	2940	continue;
2923		2941
2924	minimum[plane] = 8;	2942	minimum[id] = 8;
2925	alloc_size -= minimum[plane];	2943	alloc_size -= minimum[id];
2926	y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;	2944	y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2927	alloc_size -= y_minimum[plane];	2945	alloc_size -= y_minimum[id];
2928	}	2946	}
2929		2947
2930	/*	2948	/*
@@ -2933,45 +2951,50 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, · 2 unmodified lines
2933	*	2951	*
2934	* FIXME: we may not allocate every single block here.	2952	* FIXME: we may not allocate every single block here.
2935	*/	2953	*/
2936	total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);	2954	total_data_rate = skl_get_total_relative_data_rate(cstate);
2937		2955
2938	start = alloc->start;	2956	start = alloc->start;
2939	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {	2957	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2940	const struct intel_plane_wm_parameters *p;	2958	struct drm_plane *plane = &intel_plane->base;
		2959	struct drm_plane_state *pstate = intel_plane->base.state;
2941	unsigned int data_rate, y_data_rate;	2960	unsigned int data_rate, y_data_rate;
2942	uint16_t plane_blocks, y_plane_blocks = 0;	2961	uint16_t plane_blocks, y_plane_blocks = 0;
		2962	int id = skl_wm_plane_id(intel_plane);
2943		2963
2944	p = &params->plane[plane];	2964	if (pstate->fb == NULL)
2945	if (!p->enabled)	2965	continue;
		2966	if (plane->type == DRM_PLANE_TYPE_CURSOR)
2946	continue;	2967	continue;
2947		2968
2948	data_rate = skl_plane_relative_data_rate(p, 0);	2969	data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
2949		2970
2950	/*	2971	/*
2951	* allocation for (packed formats) or (uv-plane part of planar format):	2972	* allocation for (packed formats) or (uv-plane part of planar format):
2952	* promote the expression to 64 bits to avoid overflowing, the	2973	* promote the expression to 64 bits to avoid overflowing, the
2953	* result is < available as data_rate / total_data_rate < 1	2974	* result is < available as data_rate / total_data_rate < 1
2954	*/	2975	*/
2955	plane_blocks = minimum[plane];	2976	plane_blocks = minimum[id];
2956	plane_blocks += div_u64((uint64_t)alloc_size * data_rate,	2977	plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2957	total_data_rate);	2978	total_data_rate);
2958		2979
2959	ddb->plane[pipe][plane].start = start;	2980	ddb->plane[pipe][id].start = start;
2960	ddb->plane[pipe][plane].end = start + plane_blocks;	2981	ddb->plane[pipe][id].end = start + plane_blocks;
2961		2982
2962	start += plane_blocks;	2983	start += plane_blocks;
2963		2984
2964	/*	2985	/*
2965	* allocation for y_plane part of planar format:	2986	* allocation for y_plane part of planar format:
2966	*/	2987	*/
2967	if (p->y_bytes_per_pixel) {	2988	if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
2968	y_data_rate = skl_plane_relative_data_rate(p, 1);	2989	y_data_rate = skl_plane_relative_data_rate(cstate,
2969	y_plane_blocks = y_minimum[plane];	2990	pstate,
		2991	1);
		2992	y_plane_blocks = y_minimum[id];
2970	y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,	2993	y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2971	total_data_rate);	2994	total_data_rate);
2972		2995
2973	ddb->y_plane[pipe][plane].start = start;	2996	ddb->y_plane[pipe][id].start = start;
2974	ddb->y_plane[pipe][plane].end = start + y_plane_blocks;	2997	ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2975		2998
2976	start += y_plane_blocks;	2999	start += y_plane_blocks;
2977	}	3000	}
@@ -3041,104 +3064,27 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, · 63 unmodified lines
3041	struct drm_device *dev = intel_crtc->base.dev;	3064	struct drm_device *dev = intel_crtc->base.dev;
3042	struct drm_i915_private *dev_priv = dev->dev_private;	3065	struct drm_i915_private *dev_priv = dev->dev_private;
3043	const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;	3066	const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3044	enum pipe pipe = intel_crtc->pipe;
3045
3046	if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3047	sizeof(new_ddb->plane[pipe])))
3048	return true;
3049		3067
3050	if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],	3068	/*
3051	sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))	3069	* If ddb allocation of pipes changed, it may require recalculation of
		3070	* watermarks
		3071	*/
		3072	if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3052	return true;	3073	return true;
3053		3074
3054	return false;	3075	return false;
3055	}	3076	}
3056		3077
3057	static void skl_compute_wm_global_parameters(struct drm_device *dev,
3058	struct intel_wm_config *config)
3059	{
3060	struct drm_crtc *crtc;
3061	struct drm_plane *plane;
3062
3063	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3064	config->num_pipes_active += to_intel_crtc(crtc)->active;
3065
3066	/* FIXME: I don't think we need those two global parameters on SKL */
3067	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3068	struct intel_plane *intel_plane = to_intel_plane(plane);
3069
3070	config->sprites_enabled \|= intel_plane->wm.enabled;
3071	config->sprites_scaled \|= intel_plane->wm.scaled;
3072	}
3073	}
3074
3075	static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3076	struct skl_pipe_wm_parameters *p)
3077	{
3078	struct drm_device *dev = crtc->dev;
3079	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3080	enum pipe pipe = intel_crtc->pipe;
3081	struct drm_plane *plane;
3082	struct drm_framebuffer *fb;
3083	int i = 1; /* Index for sprite planes start */
3084
3085	p->active = intel_crtc->active;
3086	if (p->active) {
3087	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3088	p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3089
3090	fb = crtc->primary->state->fb;
3091	/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3092	if (fb) {
3093	p->plane[0].enabled = true;
3094	p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3095	drm_format_plane_cpp(fb->pixel_format, 1) :
3096	drm_format_plane_cpp(fb->pixel_format, 0);
3097	p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3098	drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3099	p->plane[0].tiling = fb->modifier[0];
3100	} else {
3101	p->plane[0].enabled = false;
3102	p->plane[0].bytes_per_pixel = 0;
3103	p->plane[0].y_bytes_per_pixel = 0;
3104	p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3105	}
3106	p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3107	p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3108	p->plane[0].rotation = crtc->primary->state->rotation;
3109
3110	fb = crtc->cursor->state->fb;
3111	p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3112	if (fb) {
3113	p->plane[PLANE_CURSOR].enabled = true;
3114	p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3115	p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3116	p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3117	} else {
3118	p->plane[PLANE_CURSOR].enabled = false;
3119	p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3120	p->plane[PLANE_CURSOR].horiz_pixels = 64;
3121	p->plane[PLANE_CURSOR].vert_pixels = 64;
3122	}
3123	}
3124
3125	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3126	struct intel_plane *intel_plane = to_intel_plane(plane);
3127
3128	if (intel_plane->pipe == pipe &&
3129	plane->type == DRM_PLANE_TYPE_OVERLAY)
3130	p->plane[i++] = intel_plane->wm;
3131	}
3132	}
3133
3134	static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,	3078	static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3135	struct skl_pipe_wm_parameters *p,	3079	struct intel_crtc_state *cstate,
3136	struct intel_plane_wm_parameters *p_params,	3080	struct intel_plane *intel_plane,
3137	uint16_t ddb_allocation,	3081	uint16_t ddb_allocation,
3138	int level,	3082	int level,
3139	uint16_t out_blocks, / out */	3083	uint16_t out_blocks, / out */
3140	uint8_t out_lines / out */)	3084	uint8_t out_lines / out */)
3141	{	3085	{
		3086	struct drm_plane *plane = &intel_plane->base;
		3087	struct drm_framebuffer *fb = plane->state->fb;
3142	uint32_t latency = dev_priv->wm.skl_latency[level];	3088	uint32_t latency = dev_priv->wm.skl_latency[level];
3143	uint32_t method1, method2;	3089	uint32_t method1, method2;
3144	uint32_t plane_bytes_per_line, plane_blocks_per_line;	3090	uint32_t plane_bytes_per_line, plane_blocks_per_line;
@@ -3146,31 +3092,33 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 1 unmodified line
3146	uint32_t selected_result;	3092	uint32_t selected_result;
3147	uint8_t bytes_per_pixel;	3093	uint8_t bytes_per_pixel;
3148		3094
3149	if (latency == 0 \|\| !p->active \|\| !p_params->enabled)	3095	if (latency == 0 \|\| !cstate->base.active \|\| !fb)
3150	return false;	3096	return false;
3151		3097
3152	bytes_per_pixel = p_params->y_bytes_per_pixel ?	3098	bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3153	p_params->y_bytes_per_pixel :	3099	method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3154	p_params->bytes_per_pixel;
3155	method1 = skl_wm_method1(p->pixel_rate,
3156	bytes_per_pixel,	3100	bytes_per_pixel,
3157	latency);	3101	latency);
3158	method2 = skl_wm_method2(p->pixel_rate,	3102	method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3159	p->pipe_htotal,	3103	cstate->base.adjusted_mode.crtc_htotal,
3160	p_params->horiz_pixels,	3104	cstate->pipe_src_w,
3161	bytes_per_pixel,	3105	bytes_per_pixel,
3162	p_params->tiling,	3106	fb->modifier[0],
3163	latency);	3107	latency);
3164		3108
3165	plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;	3109	plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3166	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);	3110	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3167		3111
3168	if (p_params->tiling == I915_FORMAT_MOD_Y_TILED \|\|	3112	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED \|\|
3169	p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {	3113	fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3170	uint32_t min_scanlines = 4;	3114	uint32_t min_scanlines = 4;
3171	uint32_t y_tile_minimum;	3115	uint32_t y_tile_minimum;
3172	if (intel_rotation_90_or_270(p_params->rotation)) {	3116	if (intel_rotation_90_or_270(plane->state->rotation)) {
3173	switch (p_params->bytes_per_pixel) {	3117	int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
		3118	drm_format_plane_cpp(fb->pixel_format, 1) :
		3119	drm_format_plane_cpp(fb->pixel_format, 0);
		3120
		3121	switch (bpp) {
3174	case 1:	3122	case 1:
3175	min_scanlines = 16;	3123	min_scanlines = 16;
3176	break;	3124	break;
@@ -3194,8 +3142,8 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 17 unmodified lines
3194	res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);	3142	res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3195		3143
3196	if (level >= 1 && level <= 7) {	3144	if (level >= 1 && level <= 7) {
3197	if (p_params->tiling == I915_FORMAT_MOD_Y_TILED \|\|	3145	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED \|\|
3198	p_params->tiling == I915_FORMAT_MOD_Yf_TILED)	3146	fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3199	res_lines += 4;	3147	res_lines += 4;
3200	else	3148	else
3201	res_blocks++;	3149	res_blocks++;
@@ -3212,84 +3160,80 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 10 unmodified lines
3212		3160
3213	static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,	3161	static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3214	struct skl_ddb_allocation *ddb,	3162	struct skl_ddb_allocation *ddb,
3215	struct skl_pipe_wm_parameters *p,	3163	struct intel_crtc_state *cstate,
3216	enum pipe pipe,
3217	int level,	3164	int level,
3218	int num_planes,
3219	struct skl_wm_level *result)	3165	struct skl_wm_level *result)
3220	{	3166	{
		3167	struct drm_device *dev = dev_priv->dev;
		3168	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
		3169	struct intel_plane *intel_plane;
3221	uint16_t ddb_blocks;	3170	uint16_t ddb_blocks;
3222	int i;	3171	enum pipe pipe = intel_crtc->pipe;
		3172
		3173	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
		3174	int i = skl_wm_plane_id(intel_plane);
3223		3175
3224	for (i = 0; i < num_planes; i++) {
3225	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);	3176	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3226		3177
3227	result->plane_en[i] = skl_compute_plane_wm(dev_priv,	3178	result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3228	p, &p->plane[i],	3179	cstate,
		3180	intel_plane,
3229	ddb_blocks,	3181	ddb_blocks,
3230	level,	3182	level,
3231	&result->plane_res_b[i],	3183	&result->plane_res_b[i],
3232	&result->plane_res_l[i]);	3184	&result->plane_res_l[i]);
3233	}	3185	}
3234
3235	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3236	result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3237	&p->plane[PLANE_CURSOR],
3238	ddb_blocks, level,
3239	&result->plane_res_b[PLANE_CURSOR],
3240	&result->plane_res_l[PLANE_CURSOR]);
3241	}	3186	}
3242		3187
3243	static uint32_t	3188	static uint32_t
3244	skl_compute_linetime_wm(struct drm_crtc crtc, struct skl_pipe_wm_parameters p)	3189	skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3245	{	3190	{
3246	if (!to_intel_crtc(crtc)->active)	3191	if (!cstate->base.active)
3247	return 0;	3192	return 0;
3248		3193
3249	if (WARN_ON(p->pixel_rate == 0))	3194	if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3250	return 0;	3195	return 0;
3251		3196
3252	return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);	3197	return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
		3198	skl_pipe_pixel_rate(cstate));
3253	}	3199	}
3254		3200
3255	static void skl_compute_transition_wm(struct drm_crtc *crtc,	3201	static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3256	struct skl_pipe_wm_parameters *params,
3257	struct skl_wm_level trans_wm / out */)	3202	struct skl_wm_level trans_wm / out */)
3258	{	3203	{
		3204	struct drm_crtc *crtc = cstate->base.crtc;
3259	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3205	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3260	int i;	3206	struct intel_plane *intel_plane;
3261		3207
3262	if (!params->active)	3208	if (!cstate->base.active)
3263	return;	3209	return;
3264		3210
3265	/* Until we know more, just disable transition WMs */	3211	/* Until we know more, just disable transition WMs */
3266	for (i = 0; i < intel_num_planes(intel_crtc); i++)	3212	for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
		3213	int i = skl_wm_plane_id(intel_plane);
		3214
3267	trans_wm->plane_en[i] = false;	3215	trans_wm->plane_en[i] = false;
3268	trans_wm->plane_en[PLANE_CURSOR] = false;	3216	}
3269	}	3217	}
3270		3218
3271	static void skl_compute_pipe_wm(struct drm_crtc *crtc,	3219	static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3272	struct skl_ddb_allocation *ddb,	3220	struct skl_ddb_allocation *ddb,
3273	struct skl_pipe_wm_parameters *params,
3274	struct skl_pipe_wm *pipe_wm)	3221	struct skl_pipe_wm *pipe_wm)
3275	{	3222	{
3276	struct drm_device *dev = crtc->dev;	3223	struct drm_device *dev = cstate->base.crtc->dev;
3277	const struct drm_i915_private *dev_priv = dev->dev_private;	3224	const struct drm_i915_private *dev_priv = dev->dev_private;
3278	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279	int level, max_level = ilk_wm_max_level(dev);	3225	int level, max_level = ilk_wm_max_level(dev);
3280		3226
3281	for (level = 0; level <= max_level; level++) {	3227	for (level = 0; level <= max_level; level++) {
3282	skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,	3228	skl_compute_wm_level(dev_priv, ddb, cstate,
3283	level, intel_num_planes(intel_crtc),	3229	level, &pipe_wm->wm[level]);
3284	&pipe_wm->wm[level]);
3285	}	3230	}
3286	pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);	3231	pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3287		3232
3288	skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);	3233	skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3289	}	3234	}
3290		3235
3291	static void skl_compute_wm_results(struct drm_device *dev,	3236	static void skl_compute_wm_results(struct drm_device *dev,
3292	struct skl_pipe_wm_parameters *p,
3293	struct skl_pipe_wm *p_wm,	3237	struct skl_pipe_wm *p_wm,
3294	struct skl_wm_values *r,	3238	struct skl_wm_values *r,
3295	struct intel_crtc *intel_crtc)	3239	struct intel_crtc *intel_crtc)
@@ -3346,7 +3290,8 @@ static void skl_compute_wm_results(struct drm_device *dev, · 50 unmodified lines
3346	r->wm_linetime[pipe] = p_wm->linetime;	3290	r->wm_linetime[pipe] = p_wm->linetime;
3347	}	3291	}
3348		3292
3349	static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,	3293	static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
		3294	i915_reg_t reg,
3350	const struct skl_ddb_entry *entry)	3295	const struct skl_ddb_entry *entry)
3351	{	3296	{
3352	if (entry->end)	3297	if (entry->end)
@@ -3533,28 +3478,25 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv, · 180 unmodified lines
3533	}	3478	}
3534		3479
3535	static bool skl_update_pipe_wm(struct drm_crtc *crtc,	3480	static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3536	struct skl_pipe_wm_parameters *params,
3537	struct intel_wm_config *config,
3538	struct skl_ddb_allocation ddb, / out */	3481	struct skl_ddb_allocation ddb, / out */
3539	struct skl_pipe_wm pipe_wm / out */)	3482	struct skl_pipe_wm pipe_wm / out */)
3540	{	3483	{
3541	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3484	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3485	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3542		3486
3543	skl_compute_wm_pipe_parameters(crtc, params);	3487	skl_allocate_pipe_ddb(cstate, ddb);
3544	skl_allocate_pipe_ddb(crtc, config, params, ddb);	3488	skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3545	skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3546		3489
3547	if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))	3490	if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3548	return false;	3491	return false;
3549		3492
3550	intel_crtc->wm.skl_active = *pipe_wm;	3493	intel_crtc->wm.active.skl = *pipe_wm;
3551		3494
3552	return true;	3495	return true;
3553	}	3496	}
3554		3497
3555	static void skl_update_other_pipe_wm(struct drm_device *dev,	3498	static void skl_update_other_pipe_wm(struct drm_device *dev,
3556	struct drm_crtc *crtc,	3499	struct drm_crtc *crtc,
3557	struct intel_wm_config *config,
3558	struct skl_wm_values *r)	3500	struct skl_wm_values *r)
3559	{	3501	{
3560	struct intel_crtc *intel_crtc;	3502	struct intel_crtc *intel_crtc;
@@ -3575,7 +3517,6 @@ static void skl_update_other_pipe_wm(struct drm_device *dev, · 14 unmodified lines
3575	*/	3517	*/
3576	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,	3518	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3577	base.head) {	3519	base.head) {
3578	struct skl_pipe_wm_parameters params = {};
3579	struct skl_pipe_wm pipe_wm = {};	3520	struct skl_pipe_wm pipe_wm = {};
3580	bool wm_changed;	3521	bool wm_changed;
3581		3522
@@ -3586,7 +3527,6 @@ static void skl_update_other_pipe_wm(struct drm_device *dev, · 4 unmodified lines
3586	continue;	3527	continue;
3587		3528
3588	wm_changed = skl_update_pipe_wm(&intel_crtc->base,	3529	wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3589	&params, config,
3590	&r->ddb, &pipe_wm);	3530	&r->ddb, &pipe_wm);
3591		3531
3592	/*	3532	/*
@@ -3596,7 +3536,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev, · 3 unmodified lines
3596	*/	3536	*/
3597	WARN_ON(!wm_changed);	3537	WARN_ON(!wm_changed);
3598		3538
3599	skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);	3539	skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3600	r->dirty[intel_crtc->pipe] = true;	3540	r->dirty[intel_crtc->pipe] = true;
3601	}	3541	}
3602	}	3542	}
@@ -3626,10 +3566,9 @@ static void skl_update_wm(struct drm_crtc *crtc) · 23 unmodified lines
3626	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3566	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3627	struct drm_device *dev = crtc->dev;	3567	struct drm_device *dev = crtc->dev;
3628	struct drm_i915_private *dev_priv = dev->dev_private;	3568	struct drm_i915_private *dev_priv = dev->dev_private;
3629	struct skl_pipe_wm_parameters params = {};
3630	struct skl_wm_values *results = &dev_priv->wm.skl_results;	3569	struct skl_wm_values *results = &dev_priv->wm.skl_results;
3631	struct skl_pipe_wm pipe_wm = {};	3570	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3632	struct intel_wm_config config = {};	3571	struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3633		3572
3634		3573
3635	/* Clear all dirty flags */	3574	/* Clear all dirty flags */
@@ -3637,16 +3576,13 @@ static void skl_update_wm(struct drm_crtc *crtc) · 1 unmodified line
3637		3576
3638	skl_clear_wm(results, intel_crtc->pipe);	3577	skl_clear_wm(results, intel_crtc->pipe);
3639		3578
3640	skl_compute_wm_global_parameters(dev, &config);	3579	if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3641
3642	if (!skl_update_pipe_wm(crtc, &params, &config,
3643	&results->ddb, &pipe_wm))
3644	return;	3580	return;
3645		3581
3646	skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);	3582	skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3647	results->dirty[intel_crtc->pipe] = true;	3583	results->dirty[intel_crtc->pipe] = true;
3648		3584
3649	skl_update_other_pipe_wm(dev, crtc, &config, results);	3585	skl_update_other_pipe_wm(dev, crtc, results);
3650	skl_write_wm_values(dev_priv, results);	3586	skl_write_wm_values(dev_priv, results);
3651	skl_flush_wm_values(dev_priv, results);	3587	skl_flush_wm_values(dev_priv, results);
3652		3588
@@ -3654,71 +3590,23 @@ static void skl_update_wm(struct drm_crtc *crtc) · 1 unmodified line
3654	dev_priv->wm.skl_hw = *results;	3590	dev_priv->wm.skl_hw = *results;
3655	}	3591	}
3656		3592
3657	static void	3593	static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3658	skl_update_sprite_wm(struct drm_plane plane, struct drm_crtc crtc,
3659	uint32_t sprite_width, uint32_t sprite_height,
3660	int pixel_size, bool enabled, bool scaled)
3661	{
3662	struct intel_plane *intel_plane = to_intel_plane(plane);
3663	struct drm_framebuffer *fb = plane->state->fb;
3664
3665	intel_plane->wm.enabled = enabled;
3666	intel_plane->wm.scaled = scaled;
3667	intel_plane->wm.horiz_pixels = sprite_width;
3668	intel_plane->wm.vert_pixels = sprite_height;
3669	intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3670
3671	/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3672	intel_plane->wm.bytes_per_pixel =
3673	(fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3674	drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3675	intel_plane->wm.y_bytes_per_pixel =
3676	(fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3677	drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3678
3679	/*
3680	* Framebuffer can be NULL on plane disable, but it does not
3681	* matter for watermarks if we assume no tiling in that case.
3682	*/
3683	if (fb)
3684	intel_plane->wm.tiling = fb->modifier[0];
3685	intel_plane->wm.rotation = plane->state->rotation;
3686
3687	skl_update_wm(crtc);
3688	}
3689
3690	static void ilk_update_wm(struct drm_crtc *crtc)
3691	{	3594	{
3692	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3595	struct drm_device *dev = dev_priv->dev;
3693	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);	3596	struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3694	struct drm_device *dev = crtc->dev;
3695	struct drm_i915_private *dev_priv = dev->dev_private;
3696	struct ilk_wm_maximums max;	3597	struct ilk_wm_maximums max;
		3598	struct intel_wm_config *config = &dev_priv->wm.config;
3697	struct ilk_wm_values results = {};	3599	struct ilk_wm_values results = {};
3698	enum intel_ddb_partitioning partitioning;	3600	enum intel_ddb_partitioning partitioning;
3699	struct intel_pipe_wm pipe_wm = {};
3700	struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3701	struct intel_wm_config config = {};
3702
3703	WARN_ON(cstate->base.active != intel_crtc->active);
3704
3705	intel_compute_pipe_wm(cstate, &pipe_wm);
3706		3601
3707	if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))	3602	ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3708	return;	3603	ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
3709
3710	intel_crtc->wm.active = pipe_wm;
3711
3712	ilk_compute_wm_config(dev, &config);
3713
3714	ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3715	ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3716		3604
3717	/* 5/6 split only in single pipe config on IVB+ */	3605	/* 5/6 split only in single pipe config on IVB+ */
3718	if (INTEL_INFO(dev)->gen >= 7 &&	3606	if (INTEL_INFO(dev)->gen >= 7 &&
3719	config.num_pipes_active == 1 && config.sprites_enabled) {	3607	config->num_pipes_active == 1 && config->sprites_enabled) {
3720	ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);	3608	ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3721	ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);	3609	ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
3722		3610
3723	best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);	3611	best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3724	} else {	3612	} else {
@@ -3733,14 +3621,13 @@ static void ilk_update_wm(struct drm_crtc *crtc) · 8 unmodified lines
3733	ilk_write_wm_values(dev_priv, &results);	3621	ilk_write_wm_values(dev_priv, &results);
3734	}	3622	}
3735		3623
3736	static void	3624	static void ilk_update_wm(struct drm_crtc *crtc)
3737	ilk_update_sprite_wm(struct drm_plane *plane,
3738	struct drm_crtc *crtc,
3739	uint32_t sprite_width, uint32_t sprite_height,
3740	int pixel_size, bool enabled, bool scaled)
3741	{	3625	{
3742	struct drm_device *dev = plane->dev;	3626	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3743	struct intel_plane *intel_plane = to_intel_plane(plane);	3627	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		3628	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
		3629
		3630	WARN_ON(cstate->base.active != intel_crtc->active);
3744		3631
3745	/*	3632	/*
3746	* IVB workaround: must disable low power watermarks for at least	3633	* IVB workaround: must disable low power watermarks for at least
@@ -3749,10 +3636,14 @@ ilk_update_sprite_wm(struct drm_plane *plane, · 2 unmodified lines
3749	*	3636	*
3750	* WaCxSRDisabledForSpriteScaling:ivb	3637	* WaCxSRDisabledForSpriteScaling:ivb
3751	*/	3638	*/
3752	if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))	3639	if (cstate->disable_lp_wm) {
3753	intel_wait_for_vblank(dev, intel_plane->pipe);	3640	ilk_disable_lp_wm(crtc->dev);
		3641	intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
		3642	}
		3643
		3644	intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3754		3645
3755	ilk_update_wm(crtc);	3646	ilk_program_watermarks(dev_priv);
3756	}	3647	}
3757		3648
3758	static void skl_pipe_wm_active_state(uint32_t val,	3649	static void skl_pipe_wm_active_state(uint32_t val,
@@ -3805,7 +3696,8 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) · 46 unmodified lines
3805	struct drm_i915_private *dev_priv = dev->dev_private;	3696	struct drm_i915_private *dev_priv = dev->dev_private;
3806	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;	3697	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3807	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3698	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808	struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;	3699	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
		3700	struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3809	enum pipe pipe = intel_crtc->pipe;	3701	enum pipe pipe = intel_crtc->pipe;
3810	int level, i, max_level;	3702	int level, i, max_level;
3811	uint32_t temp;	3703	uint32_t temp;
@@ -3849,6 +3741,8 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) · 37 unmodified lines
3849		3741
3850	temp = hw->plane_trans[pipe][PLANE_CURSOR];	3742	temp = hw->plane_trans[pipe][PLANE_CURSOR];
3851	skl_pipe_wm_active_state(temp, active, true, true, i, 0);	3743	skl_pipe_wm_active_state(temp, active, true, true, i, 0);
		3744
		3745	intel_crtc->wm.active.skl = *active;
3852	}	3746	}
3853		3747
3854	void skl_wm_get_hw_state(struct drm_device *dev)	3748	void skl_wm_get_hw_state(struct drm_device *dev)
@@ -3868,9 +3762,10 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) · 13 unmodified lines
3868	struct drm_i915_private *dev_priv = dev->dev_private;	3762	struct drm_i915_private *dev_priv = dev->dev_private;
3869	struct ilk_wm_values *hw = &dev_priv->wm.hw;	3763	struct ilk_wm_values *hw = &dev_priv->wm.hw;
3870	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3764	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3871	struct intel_pipe_wm *active = &intel_crtc->wm.active;	3765	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
		3766	struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3872	enum pipe pipe = intel_crtc->pipe;	3767	enum pipe pipe = intel_crtc->pipe;
3873	static const unsigned int wm0_pipe_reg[] = {	3768	static const i915_reg_t wm0_pipe_reg[] = {
3874	[PIPE_A] = WM0_PIPEA_ILK,	3769	[PIPE_A] = WM0_PIPEA_ILK,
3875	[PIPE_B] = WM0_PIPEB_ILK,	3770	[PIPE_B] = WM0_PIPEB_ILK,
3876	[PIPE_C] = WM0_PIPEC_IVB,	3771	[PIPE_C] = WM0_PIPEC_IVB,
@@ -3907,6 +3802,8 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) · 30 unmodified lines
3907	for (level = 0; level <= max_level; level++)	3802	for (level = 0; level <= max_level; level++)
3908	active->wm[level].enable = true;	3803	active->wm[level].enable = true;
3909	}	3804	}
		3805
		3806	intel_crtc->wm.active.ilk = *active;
3910	}	3807	}
3911		3808
3912	#define _FW_WM(value, plane) \	3809	#define _FW_WM(value, plane) \
@@ -4132,21 +4029,6 @@ void intel_update_watermarks(struct drm_crtc *crtc) · 219 unmodified lines
4132	dev_priv->display.update_wm(crtc);	4029	dev_priv->display.update_wm(crtc);
4133	}	4030	}
4134		4031
4135	void intel_update_sprite_watermarks(struct drm_plane *plane,
4136	struct drm_crtc *crtc,
4137	uint32_t sprite_width,
4138	uint32_t sprite_height,
4139	int pixel_size,
4140	bool enabled, bool scaled)
4141	{
4142	struct drm_i915_private *dev_priv = plane->dev->dev_private;
4143
4144	if (dev_priv->display.update_sprite_wm)
4145	dev_priv->display.update_sprite_wm(plane, crtc,
4146	sprite_width, sprite_height,
4147	pixel_size, enabled, scaled);
4148	}
4149
4150	/**	4032	/**
4151	* Lock protecting IPS related data structures	4033	* Lock protecting IPS related data structures
4152	*/	4034	*/
@@ -4414,7 +4296,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) · 261 unmodified lines
4414	struct drm_i915_private *dev_priv = dev->dev_private;	4296	struct drm_i915_private *dev_priv = dev->dev_private;
4415		4297
4416	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */	4298	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4417	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))	4299	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4418	return;	4300	return;
4419		4301
4420	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));	4302	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -4689,7 +4571,8 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) · 268 unmodified lines
4689	dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;	4571	dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4690		4572
4691	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;	4573	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4692	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\| IS_SKYLAKE(dev)) {	4574	if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev) \|\|
		4575	IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
4693	ret = sandybridge_pcode_read(dev_priv,	4576	ret = sandybridge_pcode_read(dev_priv,
4694	HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,	4577	HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4695	&ddcc_status);	4578	&ddcc_status);
@@ -4701,7 +4584,7 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) · 5 unmodified lines
4701	dev_priv->rps.max_freq);	4584	dev_priv->rps.max_freq);
4702	}	4585	}
4703		4586
4704	if (IS_SKYLAKE(dev)) {	4587	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
4705	/* Store the frequency values in 16.66 MHZ units, which is	4588	/* Store the frequency values in 16.66 MHZ units, which is
4706	the natural hardware unit for SKL */	4589	the natural hardware unit for SKL */
4707	dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;	4590	dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
@@ -4738,7 +4621,7 @@ static void gen9_enable_rps(struct drm_device *dev) · 30 unmodified lines
4738	gen6_init_rps_frequencies(dev);	4621	gen6_init_rps_frequencies(dev);
4739		4622
4740	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */	4623	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4741	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {	4624	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4742	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);	4625	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4743	return;	4626	return;
4744	}	4627	}
@@ -4806,8 +4689,8 @@ static void gen9_enable_rc6(struct drm_device *dev) · 61 unmodified lines
4806	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?	4689	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4807	"on" : "off");	4690	"on" : "off");
4808	/* WaRsUseTimeoutMode */	4691	/* WaRsUseTimeoutMode */
4809	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) \|\|	4692	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) \|\|
4810	(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {	4693	IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4811	I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */	4694	I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4812	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE \|	4695	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE \|
4813	GEN7_RC_CTL_TO_MODE \|	4696	GEN7_RC_CTL_TO_MODE \|
@@ -5055,7 +4938,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) · 241 unmodified lines
5055	/* convert DDR frequency from units of 266.6MHz to bandwidth */	4938	/* convert DDR frequency from units of 266.6MHz to bandwidth */
5056	min_ring_freq = mult_frac(min_ring_freq, 8, 3);	4939	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5057		4940
5058	if (IS_SKYLAKE(dev)) {	4941	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
5059	/* Convert GT frequency to 50 HZ units */	4942	/* Convert GT frequency to 50 HZ units */
5060	min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;	4943	min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5061	max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;	4944	max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
@@ -5073,7 +4956,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) · 11 unmodified lines
5073	int diff = max_gpu_freq - gpu_freq;	4956	int diff = max_gpu_freq - gpu_freq;
5074	unsigned int ia_freq = 0, ring_freq = 0;	4957	unsigned int ia_freq = 0, ring_freq = 0;
5075		4958
5076	if (IS_SKYLAKE(dev)) {	4959	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) {
5077	/*	4960	/*
5078	* ring_freq = 2 * GT. ring_freq is in 100MHz units	4961	* ring_freq = 2 * GT. ring_freq is in 100MHz units
5079	* No floor required for ring frequency on SKL.	4962	* No floor required for ring frequency on SKL.
@@ -6201,7 +6084,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) · 1121 unmodified lines
6201	} else if (INTEL_INFO(dev)->gen >= 9) {	6084	} else if (INTEL_INFO(dev)->gen >= 9) {
6202	gen9_enable_rc6(dev);	6085	gen9_enable_rc6(dev);
6203	gen9_enable_rps(dev);	6086	gen9_enable_rps(dev);
6204	if (IS_SKYLAKE(dev))	6087	if (IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev))
6205	__gen6_update_ring_freq(dev);	6088	__gen6_update_ring_freq(dev);
6206	} else if (IS_BROADWELL(dev)) {	6089	} else if (IS_BROADWELL(dev)) {
6207	gen8_enable_rps(dev);	6090	gen8_enable_rps(dev);
@@ -7057,7 +6940,6 @@ void intel_init_pm(struct drm_device *dev) · 849 unmodified lines
7057	dev_priv->display.init_clock_gating =	6940	dev_priv->display.init_clock_gating =
7058	bxt_init_clock_gating;	6941	bxt_init_clock_gating;
7059	dev_priv->display.update_wm = skl_update_wm;	6942	dev_priv->display.update_wm = skl_update_wm;
7060	dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7061	} else if (HAS_PCH_SPLIT(dev)) {	6943	} else if (HAS_PCH_SPLIT(dev)) {
7062	ilk_setup_wm_latency(dev);	6944	ilk_setup_wm_latency(dev);
7063		6945
@@ -7066,7 +6948,7 @@ void intel_init_pm(struct drm_device *dev) · 2 unmodified lines
7066	(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&	6948	(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7067	dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {	6949	dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7068	dev_priv->display.update_wm = ilk_update_wm;	6950	dev_priv->display.update_wm = ilk_update_wm;
7069	dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;	6951	dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7070	} else {	6952	} else {
7071	DRM_DEBUG_KMS("Failed to read display plane latency. "	6953	DRM_DEBUG_KMS("Failed to read display plane latency. "
7072	"Disable CxSR\n");	6954	"Disable CxSR\n");

drivers/gpu/drm/i915/intel_psr.c+52−25

 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
+	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 	uint32_t *data = (uint32_t *) vsc_psr;
 	unsigned int i;
 			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 }
+static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				       enum port port)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return DP_AUX_CH_CTL(port);
+	else
+		return EDP_PSR_AUX_CTL;
+}
+static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
+					enum port port, int index)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return DP_AUX_CH_DATA(port, index);
+	else
+		return EDP_PSR_AUX_DATA(index);
+}
 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t aux_clock_divider;
-	uint32_t aux_data_reg, aux_ctl_reg;
+	i915_reg_t aux_ctl_reg;
 	int precharge = 0x3;
 	static const uint8_t aux_msg[] = {
 		[0] = DP_AUX_NATIVE_WRITE << 4,
 		[3] = 1 - 1,
 		[4] = DP_SET_POWER_D0,
 	};
+	enum port port = dig_port->port;
 	int i;
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
 				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 				DP_AUX_FRAME_SYNC_ENABLE);
-	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
+	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
-				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
-	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-		I915_WRITE(aux_data_reg + i,
+		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 	if (INTEL_INFO(dev)->gen >= 9) {
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
-		/* It doesn't mean we shouldn't send TPS patters, so let's
-		   send the minimal TP1 possible and skip TP2. */
-		val |= EDP_PSR_TP1_TIME_100us;
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
-		val |= EDP_PSR_SKIP_AUX_EXIT;
 		/* Sink should be able to train with the 5 or 6 idle patterns */
 		idle_frames += 4;
 	}
-	I915_WRITE(EDP_PSR_CTL(dev), val |
+	I915_WRITE(EDP_PSR_CTL, val |
 		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
 		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 		}
 		/* Avoid continuous PSR exit by masking memup and hpd */
-		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 			   EDP_PSR_DEBUG_MASK_HPD);
 		/* Enable PSR on the panel */
 		vlv_psr_enable_source(intel_dp);
 	}
+	/*
+	 * FIXME: Activation should happen immediately since this function
+	 * is just called after pipe is fully trained and enabled.
+	 * However on every platform we face issues when first activation
+	 * follows a modeset so quickly.
+	 *     - On VLV/CHV we get bank screen on first activation
+	 *     - On HSW/BDW we get a recoverable frozen screen until next
+	 *       exit-activate sequence.
+	 */
+	if (INTEL_INFO(dev)->gen < 9)
+		schedule_delayed_work(&dev_priv->psr.work,
+				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 	dev_priv->psr.enabled = intel_dp;
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (dev_priv->psr.active) {
-		I915_WRITE(EDP_PSR_CTL(dev),
+		I915_WRITE(EDP_PSR_CTL,
-			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
+			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 		/* Wait till PSR is idle */
-		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
+		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
 			DRM_ERROR("Timed out waiting for PSR Idle State\n");
 		dev_priv->psr.active = false;
 	} else {
-		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	}
 }
 	 * and be ready for re-enable.
 	 */
 	if (HAS_DDI(dev_priv->dev)) {
-		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 			return;
 		return;
 	if (HAS_DDI(dev)) {
-		val = I915_READ(EDP_PSR_CTL(dev));
+		val = I915_READ(EDP_PSR_CTL);
 		WARN_ON(!(val & EDP_PSR_ENABLE));
-		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
+		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 	} else {
 		val = I915_READ(VLV_PSRCTL(pipe));
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
-	int delay_ms = HAS_DDI(dev) ? 100 : 500;
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
 	}
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
-		schedule_delayed_work(&dev_priv->psr.work,
+		if (!work_busy(&dev_priv->psr.work.work))
-				      msecs_to_jiffies(delay_ms));
+			schedule_delayed_work(&dev_priv->psr.work,
+					      msecs_to_jiffies(100));
 	mutex_unlock(&dev_priv->psr.lock);
 }
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
+		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 	mutex_init(&dev_priv->psr.lock);
 }

drivers/gpu/drm/i915/intel_ringbuffer.c+100−56

@@ -481,7 +481,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *ring) · 480 unmodified lines
481	{	481	{
482	struct drm_device *dev = ring->dev;	482	struct drm_device *dev = ring->dev;
483	struct drm_i915_private *dev_priv = ring->dev->dev_private;	483	struct drm_i915_private *dev_priv = ring->dev->dev_private;
484	u32 mmio = 0;	484	i915_reg_t mmio;
485		485
486	/* The ring status page addresses are no longer next to the rest of	486	/* The ring status page addresses are no longer next to the rest of
487	* the ring registers as of gen7.	487	* the ring registers as of gen7.
@@ -524,7 +524,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *ring) · 36 unmodified lines
524	* invalidating the TLB?	524	* invalidating the TLB?
525	*/	525	*/
526	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {	526	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
527	u32 reg = RING_INSTPM(ring->mmio_base);	527	i915_reg_t reg = RING_INSTPM(ring->mmio_base);
528		528
529	/* ring should be idle before issuing a sync flush*/	529	/* ring should be idle before issuing a sync flush*/
530	WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);	530	WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
@@ -733,7 +733,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) · 202 unmodified lines
733		733
734	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));	734	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
735	for (i = 0; i < w->count; i++) {	735	for (i = 0; i < w->count; i++) {
736	intel_ring_emit(ring, w->reg[i].addr);	736	intel_ring_emit_reg(ring, w->reg[i].addr);
737	intel_ring_emit(ring, w->reg[i].value);	737	intel_ring_emit(ring, w->reg[i].value);
738	}	738	}
739	intel_ring_emit(ring, MI_NOOP);	739	intel_ring_emit(ring, MI_NOOP);
@@ -766,7 +766,8 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) · 26 unmodified lines
766	}	766	}
767		767
768	static int wa_add(struct drm_i915_private *dev_priv,	768	static int wa_add(struct drm_i915_private *dev_priv,
769	const u32 addr, const u32 mask, const u32 val)	769	i915_reg_t addr,
		770	const u32 mask, const u32 val)
770	{	771	{
771	const u32 idx = dev_priv->workarounds.count;	772	const u32 idx = dev_priv->workarounds.count;
772		773
@@ -924,17 +925,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) · 151 unmodified lines
924	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,	925	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
925	GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);	926	GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
926		927
927	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 \|\|	928	/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
928	INTEL_REVID(dev) == SKL_REVID_B0)) \|\|	929	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) \|\|
929	(IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {	930	IS_BXT_REVID(dev, 0, BXT_REVID_A1))
930	/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
931	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,	931	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
932	GEN9_DG_MIRROR_FIX_ENABLE);	932	GEN9_DG_MIRROR_FIX_ENABLE);
933	}
934		933
935	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) \|\|	934	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
936	(IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {	935	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) \|\|
937	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */	936	IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
938	WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,	937	WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
939	GEN9_RHWO_OPTIMIZATION_DISABLE);	938	GEN9_RHWO_OPTIMIZATION_DISABLE);
940	/*	939	/*
@@ -944,12 +943,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) · 3 unmodified lines
944	*/	943	*/
945	}	944	}
946		945
947	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) \|\|	946	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
948	IS_BROXTON(dev)) {	947	if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) \|\| IS_BROXTON(dev))
949	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
950	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,	948	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
951	GEN9_ENABLE_YV12_BUGFIX);	949	GEN9_ENABLE_YV12_BUGFIX);
952	}
953		950
954	/* Wa4x4STCOptimizationDisable:skl,bxt */	951	/* Wa4x4STCOptimizationDisable:skl,bxt */
955	/* WaDisablePartialResolveInVc:skl,bxt */	952	/* WaDisablePartialResolveInVc:skl,bxt */
@@ -961,24 +958,22 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) · 5 unmodified lines
961	GEN9_CCS_TLB_PREFETCH_ENABLE);	958	GEN9_CCS_TLB_PREFETCH_ENABLE);
962		959
963	/* WaDisableMaskBasedCammingInRCC:skl,bxt */	960	/* WaDisableMaskBasedCammingInRCC:skl,bxt */
964	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) \|\|	961	if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) \|\|
965	(IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))	962	IS_BXT_REVID(dev, 0, BXT_REVID_A1))
966	WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,	963	WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
967	PIXEL_MASK_CAMMING_DISABLE);	964	PIXEL_MASK_CAMMING_DISABLE);
968		965
969	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */	966	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
970	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;	967	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
971	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) \|\|	968	if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) \|\|
972	(IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))	969	IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
973	tmp \|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;	970	tmp \|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
974	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);	971	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
975		972
976	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */	973	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
977	if (IS_SKYLAKE(dev) \|\|	974	if (IS_SKYLAKE(dev) \|\| IS_BXT_REVID(dev, 0, BXT_REVID_B0))
978	(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
979	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,	975	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
980	GEN8_SAMPLER_POWER_BYPASS_DIS);	976	GEN8_SAMPLER_POWER_BYPASS_DIS);
981	}
982		977
983	/* WaDisableSTUnitPowerOptimization:skl,bxt */	978	/* WaDisableSTUnitPowerOptimization:skl,bxt */
984	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);	979	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
@@ -1038,7 +1033,7 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) · 53 unmodified lines
1038	if (ret)	1033	if (ret)
1039	return ret;	1034	return ret;
1040		1035
1041	if (INTEL_REVID(dev) <= SKL_REVID_D0) {	1036	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1042	/* WaDisableHDCInvalidation:skl */	1037	/* WaDisableHDCInvalidation:skl */
1043	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) \|	1038	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) \|
1044	BDW_DISABLE_HDC_INVALIDATION);	1039	BDW_DISABLE_HDC_INVALIDATION);
@@ -1051,23 +1046,23 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) · 6 unmodified lines
1051	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes	1046	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1052	* involving this register should also be added to WA batch as required.	1047	* involving this register should also be added to WA batch as required.
1053	*/	1048	*/
1054	if (INTEL_REVID(dev) <= SKL_REVID_E0)	1049	if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1055	/* WaDisableLSQCROPERFforOCL:skl */	1050	/* WaDisableLSQCROPERFforOCL:skl */
1056	I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) \|	1051	I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) \|
1057	GEN8_LQSC_RO_PERF_DIS);	1052	GEN8_LQSC_RO_PERF_DIS);
1058		1053
1059	/* WaEnableGapsTsvCreditFix:skl */	1054	/* WaEnableGapsTsvCreditFix:skl */
1060	if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {	1055	if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1061	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) \|	1056	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) \|
1062	GEN9_GAPS_TSV_CREDIT_DISABLE));	1057	GEN9_GAPS_TSV_CREDIT_DISABLE));
1063	}	1058	}
1064		1059
1065	/* WaDisablePowerCompilerClockGating:skl */	1060	/* WaDisablePowerCompilerClockGating:skl */
1066	if (INTEL_REVID(dev) == SKL_REVID_B0)	1061	if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1067	WA_SET_BIT_MASKED(HIZ_CHICKEN,	1062	WA_SET_BIT_MASKED(HIZ_CHICKEN,
1068	BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);	1063	BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1069		1064
1070	if (INTEL_REVID(dev) <= SKL_REVID_D0) {	1065	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1071	/*	1066	/*
1072	*Use Force Non-Coherent whenever executing a 3D context. This	1067	*Use Force Non-Coherent whenever executing a 3D context. This
1073	* is a workaround for a possible hang in the unlikely event	1068	* is a workaround for a possible hang in the unlikely event
@@ -1078,19 +1073,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) · 4 unmodified lines
1078	HDC_FORCE_NON_COHERENT);	1073	HDC_FORCE_NON_COHERENT);
1079	}	1074	}
1080		1075
1081	if (INTEL_REVID(dev) == SKL_REVID_C0 \|\|	1076	/* WaBarrierPerformanceFixDisable:skl */
1082	INTEL_REVID(dev) == SKL_REVID_D0)	1077	if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1083	/* WaBarrierPerformanceFixDisable:skl */
1084	WA_SET_BIT_MASKED(HDC_CHICKEN0,	1078	WA_SET_BIT_MASKED(HDC_CHICKEN0,
1085	HDC_FENCE_DEST_SLM_DISABLE \|	1079	HDC_FENCE_DEST_SLM_DISABLE \|
1086	HDC_BARRIER_PERFORMANCE_DISABLE);	1080	HDC_BARRIER_PERFORMANCE_DISABLE);
1087		1081
1088	/* WaDisableSbeCacheDispatchPortSharing:skl */	1082	/* WaDisableSbeCacheDispatchPortSharing:skl */
1089	if (INTEL_REVID(dev) <= SKL_REVID_F0) {	1083	if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1090	WA_SET_BIT_MASKED(	1084	WA_SET_BIT_MASKED(
1091	GEN7_HALF_SLICE_CHICKEN1,	1085	GEN7_HALF_SLICE_CHICKEN1,
1092	GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);	1086	GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1093	}
1094		1087
1095	return skl_tune_iz_hashing(ring);	1088	return skl_tune_iz_hashing(ring);
1096	}	1089	}
@@ -1107,11 +1100,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) · 10 unmodified lines
1107		1100
1108	/* WaStoreMultiplePTEenable:bxt */	1101	/* WaStoreMultiplePTEenable:bxt */
1109	/* This is a requirement according to Hardware specification */	1102	/* This is a requirement according to Hardware specification */
1110	if (INTEL_REVID(dev) == BXT_REVID_A0)	1103	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1111	I915_WRITE(TILECTL, I915_READ(TILECTL) \| TILECTL_TLBPF);	1104	I915_WRITE(TILECTL, I915_READ(TILECTL) \| TILECTL_TLBPF);
1112		1105
1113	/* WaSetClckGatingDisableMedia:bxt */	1106	/* WaSetClckGatingDisableMedia:bxt */
1114	if (INTEL_REVID(dev) == BXT_REVID_A0) {	1107	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1115	I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &	1108	I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1116	~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));	1109	~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1117	}	1110	}
@@ -1121,7 +1114,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) · 3 unmodified lines
1121	STALL_DOP_GATING_DISABLE);	1114	STALL_DOP_GATING_DISABLE);
1122		1115
1123	/* WaDisableSbeCacheDispatchPortSharing:bxt */	1116	/* WaDisableSbeCacheDispatchPortSharing:bxt */
1124	if (INTEL_REVID(dev) <= BXT_REVID_B0) {	1117	if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1125	WA_SET_BIT_MASKED(	1118	WA_SET_BIT_MASKED(
1126	GEN7_HALF_SLICE_CHICKEN1,	1119	GEN7_HALF_SLICE_CHICKEN1,
1127	GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);	1120	GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1319,11 +1312,13 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req, · 191 unmodified lines
1319	return ret;	1312	return ret;
1320		1313
1321	for_each_ring(useless, dev_priv, i) {	1314	for_each_ring(useless, dev_priv, i) {
1322	u32 mbox_reg = signaller->semaphore.mbox.signal[i];	1315	i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1323	if (mbox_reg != GEN6_NOSYNC) {	1316
		1317	if (i915_mmio_reg_valid(mbox_reg)) {
1324	u32 seqno = i915_gem_request_get_seqno(signaller_req);	1318	u32 seqno = i915_gem_request_get_seqno(signaller_req);
		1319
1325	intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));	1320	intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1326	intel_ring_emit(signaller, mbox_reg);	1321	intel_ring_emit_reg(signaller, mbox_reg);
1327	intel_ring_emit(signaller, seqno);	1322	intel_ring_emit(signaller, seqno);
1328	}	1323	}
1329	}	1324	}
@@ -2004,11 +1999,35 @@ static int init_phys_status_page(struct intel_engine_cs *ring) · 674 unmodified lines
2004		1999
2005	void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)	2000	void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2006	{	2001	{
2007	iounmap(ringbuf->virtual_start);	2002	if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
		2003	vunmap(ringbuf->virtual_start);
		2004	else
		2005	iounmap(ringbuf->virtual_start);
2008	ringbuf->virtual_start = NULL;	2006	ringbuf->virtual_start = NULL;
2009	i915_gem_object_ggtt_unpin(ringbuf->obj);	2007	i915_gem_object_ggtt_unpin(ringbuf->obj);
2010	}	2008	}
2011		2009
		2010	static u32 vmap_obj(struct drm_i915_gem_object obj)
		2011	{
		2012	struct sg_page_iter sg_iter;
		2013	struct page **pages;
		2014	void *addr;
		2015	int i;
		2016
		2017	pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
		2018	if (pages == NULL)
		2019	return NULL;
		2020
		2021	i = 0;
		2022	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
		2023	pages[i++] = sg_page_iter_page(&sg_iter);
		2024
		2025	addr = vmap(pages, i, 0, PAGE_KERNEL);
		2026	drm_free_large(pages);
		2027
		2028	return addr;
		2029	}
		2030
2012	int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,	2031	int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2013	struct intel_ringbuffer *ringbuf)	2032	struct intel_ringbuffer *ringbuf)
2014	{	2033	{
@@ -2016,21 +2035,39 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, · 1 unmodified line
2016	struct drm_i915_gem_object *obj = ringbuf->obj;	2035	struct drm_i915_gem_object *obj = ringbuf->obj;
2017	int ret;	2036	int ret;
2018		2037
2019	ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);	2038	if (HAS_LLC(dev_priv) && !obj->stolen) {
2020	if (ret)	2039	ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2021	return ret;	2040	if (ret)
		2041	return ret;
2022		2042
2023	ret = i915_gem_object_set_to_gtt_domain(obj, true);	2043	ret = i915_gem_object_set_to_cpu_domain(obj, true);
2024	if (ret) {	2044	if (ret) {
2025	i915_gem_object_ggtt_unpin(obj);	2045	i915_gem_object_ggtt_unpin(obj);
2026	return ret;	2046	return ret;
2027	}	2047	}
		2048
		2049	ringbuf->virtual_start = vmap_obj(obj);
		2050	if (ringbuf->virtual_start == NULL) {
		2051	i915_gem_object_ggtt_unpin(obj);
		2052	return -ENOMEM;
		2053	}
		2054	} else {
		2055	ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
		2056	if (ret)
		2057	return ret;
2028		2058
2029	ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +	2059	ret = i915_gem_object_set_to_gtt_domain(obj, true);
2030	i915_gem_obj_ggtt_offset(obj), ringbuf->size);	2060	if (ret) {
2031	if (ringbuf->virtual_start == NULL) {	2061	i915_gem_object_ggtt_unpin(obj);
2032	i915_gem_object_ggtt_unpin(obj);	2062	return ret;
2033	return -EINVAL;	2063	}
		2064
		2065	ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
		2066	i915_gem_obj_ggtt_offset(obj), ringbuf->size);
		2067	if (ringbuf->virtual_start == NULL) {
		2068	i915_gem_object_ggtt_unpin(obj);
		2069	return -EINVAL;
		2070	}
2034	}	2071	}
2035		2072
2036	return 0;	2073	return 0;
@@ -2070,10 +2107,14 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) · 33 unmodified lines
2070	int ret;	2107	int ret;
2071		2108
2072	ring = kzalloc(sizeof(*ring), GFP_KERNEL);	2109	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2073	if (ring == NULL)	2110	if (ring == NULL) {
		2111	DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
		2112	engine->name);
2074	return ERR_PTR(-ENOMEM);	2113	return ERR_PTR(-ENOMEM);
		2114	}
2075		2115
2076	ring->ring = engine;	2116	ring->ring = engine;
		2117	list_add(&ring->link, &engine->buffers);
2077		2118
2078	ring->size = size;	2119	ring->size = size;
2079	/* Workaround an erratum on the i830 which causes a hang if	2120	/* Workaround an erratum on the i830 which causes a hang if
@@ -2089,8 +2130,9 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) · 9 unmodified lines
2089		2130
2090	ret = intel_alloc_ringbuffer_obj(engine->dev, ring);	2131	ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2091	if (ret) {	2132	if (ret) {
2092	DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",	2133	DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2093	engine->name, ret);	2134	engine->name, ret);
		2135	list_del(&ring->link);
2094	kfree(ring);	2136	kfree(ring);
2095	return ERR_PTR(ret);	2137	return ERR_PTR(ret);
2096	}	2138	}
@@ -2102,6 +2144,7 @@ void · 5 unmodified lines
2102	intel_ringbuffer_free(struct intel_ringbuffer *ring)	2144	intel_ringbuffer_free(struct intel_ringbuffer *ring)
2103	{	2145	{
2104	intel_destroy_ringbuffer_obj(ring);	2146	intel_destroy_ringbuffer_obj(ring);
		2147	list_del(&ring->link);
2105	kfree(ring);	2148	kfree(ring);
2106	}	2149	}
2107		2150
@@ -2117,6 +2160,7 @@ static int intel_init_ring_buffer(struct drm_device *dev, · 9 unmodified lines
2117	INIT_LIST_HEAD(&ring->active_list);	2160	INIT_LIST_HEAD(&ring->active_list);
2118	INIT_LIST_HEAD(&ring->request_list);	2161	INIT_LIST_HEAD(&ring->request_list);
2119	INIT_LIST_HEAD(&ring->execlist_queue);	2162	INIT_LIST_HEAD(&ring->execlist_queue);
		2163	INIT_LIST_HEAD(&ring->buffers);
2120	i915_gem_batch_pool_init(dev, &ring->batch_pool);	2164	i915_gem_batch_pool_init(dev, &ring->batch_pool);
2121	memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));	2165	memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2122		2166

drivers/gpu/drm/i915/intel_ringbuffer.h+8−1

 	void __iomem *virtual_start;
 	struct intel_engine_cs *ring;
+	struct list_head link;
 	u32 head;
 	u32 tail;
 	u32		mmio_base;
 	struct		drm_device *dev;
 	struct intel_ringbuffer *buffer;
+	struct list_head buffers;
 	/*
 	 * A pool of objects to use as shadow copies of client batch buffers
 				/* our mbox written by others */
 				u32		wait[I915_NUM_RINGS];
 				/* mboxes this ring signals to */
-				u32		signal[I915_NUM_RINGS];
+				i915_reg_t	signal[I915_NUM_RINGS];
 			} mbox;
 			u64		signal_ggtt[I915_NUM_RINGS];
 		};
 	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
 	ringbuf->tail += 4;
 }
+static inline void intel_ring_emit_reg(struct intel_engine_cs *ring,
+				       i915_reg_t reg)
+{
+	intel_ring_emit(ring, i915_mmio_reg_offset(reg));
+}
 static inline void intel_ring_advance(struct intel_engine_cs *ring)
 {
 	struct intel_ringbuffer *ringbuf = ring->buffer;

drivers/gpu/drm/i915/intel_runtime_pm.c+283−209

@@ -49,21 +49,18 @@ · 48 unmodified lines
49	* present for a given platform.	49	* present for a given platform.
50	*/	50	*/
51		51
52	#define GEN9_ENABLE_DC5(dev) 0
53	#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
54
55	#define for_each_power_well(i, power_well, domain_mask, power_domains) \	52	#define for_each_power_well(i, power_well, domain_mask, power_domains) \
56	for (i = 0; \	53	for (i = 0; \
57	i < (power_domains)->power_well_count && \	54	i < (power_domains)->power_well_count && \
58	((power_well) = &(power_domains)->power_wells[i]); \	55	((power_well) = &(power_domains)->power_wells[i]); \
59	i++) \	56	i++) \
60	if ((power_well)->domains & (domain_mask))	57	for_each_if ((power_well)->domains & (domain_mask))
61		58
62	#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \	59	#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63	for (i = (power_domains)->power_well_count - 1; \	60	for (i = (power_domains)->power_well_count - 1; \
64	i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\	61	i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
65	i--) \	62	i--) \
66	if ((power_well)->domains & (domain_mask))	63	for_each_if ((power_well)->domains & (domain_mask))
67		64
68	bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,	65	bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
69	int power_well_id);	66	int power_well_id);
@@ -244,12 +241,6 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, · 174 unmodified lines
244	gen8_irq_power_well_post_enable(dev_priv,	241	gen8_irq_power_well_post_enable(dev_priv,
245	1 << PIPE_C \| 1 << PIPE_B);	242	1 << PIPE_C \| 1 << PIPE_B);
246	}	243	}
247
248	if (power_well->data == SKL_DISP_PW_1) {
249	if (!dev_priv->power_domains.initializing)
250	intel_prepare_ddi(dev);
251	gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
252	}
253	}	244	}
254		245
255	static void hsw_set_power_well(struct drm_i915_private *dev_priv,	246	static void hsw_set_power_well(struct drm_i915_private *dev_priv,
@@ -292,58 +283,38 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, · 36 unmodified lines
292	BIT(POWER_DOMAIN_TRANSCODER_C) \| \	283	BIT(POWER_DOMAIN_TRANSCODER_C) \| \
293	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) \| \	284	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) \| \
294	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) \| \	285	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) \| \
295	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	286	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
296	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \	287	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
297	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \	288	BIT(POWER_DOMAIN_PORT_DDI_D_LANES) \| \
298	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \	289	BIT(POWER_DOMAIN_PORT_DDI_E_LANES) \| \
299	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) \| \
300	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) \| \
301	BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) \| \
302	BIT(POWER_DOMAIN_AUX_B) \| \	290	BIT(POWER_DOMAIN_AUX_B) \| \
303	BIT(POWER_DOMAIN_AUX_C) \| \	291	BIT(POWER_DOMAIN_AUX_C) \| \
304	BIT(POWER_DOMAIN_AUX_D) \| \	292	BIT(POWER_DOMAIN_AUX_D) \| \
305	BIT(POWER_DOMAIN_AUDIO) \| \	293	BIT(POWER_DOMAIN_AUDIO) \| \
306	BIT(POWER_DOMAIN_VGA) \| \	294	BIT(POWER_DOMAIN_VGA) \| \
307	BIT(POWER_DOMAIN_INIT))	295	BIT(POWER_DOMAIN_INIT))
308	#define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
309	SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS \| \
310	BIT(POWER_DOMAIN_PLLS) \| \
311	BIT(POWER_DOMAIN_PIPE_A) \| \
312	BIT(POWER_DOMAIN_TRANSCODER_EDP) \| \
313	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) \| \
314	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) \| \
315	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) \| \
316	BIT(POWER_DOMAIN_AUX_A) \| \
317	BIT(POWER_DOMAIN_INIT))
318	#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \	296	#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
319	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) \| \	297	BIT(POWER_DOMAIN_PORT_DDI_A_LANES) \| \
320	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) \| \	298	BIT(POWER_DOMAIN_PORT_DDI_E_LANES) \| \
321	BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) \| \
322	BIT(POWER_DOMAIN_INIT))	299	BIT(POWER_DOMAIN_INIT))
323	#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \	300	#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
324	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	301	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
325	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \
326	BIT(POWER_DOMAIN_INIT))	302	BIT(POWER_DOMAIN_INIT))
327	#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \	303	#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
328	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \	304	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
329	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \
330	BIT(POWER_DOMAIN_INIT))	305	BIT(POWER_DOMAIN_INIT))
331	#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \	306	#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
332	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) \| \	307	BIT(POWER_DOMAIN_PORT_DDI_D_LANES) \| \
333	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) \| \
334	BIT(POWER_DOMAIN_INIT))	308	BIT(POWER_DOMAIN_INIT))
335	#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \	309	#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
336	SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS \| \	310	SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS \| \
337	BIT(POWER_DOMAIN_PLLS) \| \	311	BIT(POWER_DOMAIN_MODESET) \| \
		312	BIT(POWER_DOMAIN_AUX_A) \| \
338	BIT(POWER_DOMAIN_INIT))	313	BIT(POWER_DOMAIN_INIT))
339	#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \	314	#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
340	(POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS \| \	315	(POWER_DOMAIN_MASK & ~( \
341	SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS \| \	316	SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS \| \
342	SKL_DISPLAY_DDI_A_E_POWER_DOMAINS \| \	317	SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) \| \
343	SKL_DISPLAY_DDI_B_POWER_DOMAINS \| \
344	SKL_DISPLAY_DDI_C_POWER_DOMAINS \| \
345	SKL_DISPLAY_DDI_D_POWER_DOMAINS \| \
346	SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) \| \
347	BIT(POWER_DOMAIN_INIT))	318	BIT(POWER_DOMAIN_INIT))
348		319
349	#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \	320	#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -354,10 +325,8 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, · 4 unmodified lines
354	BIT(POWER_DOMAIN_TRANSCODER_C) \| \	325	BIT(POWER_DOMAIN_TRANSCODER_C) \| \
355	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) \| \	326	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) \| \
356	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) \| \	327	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) \| \
357	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	328	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
358	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \	329	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
359	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \
360	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \
361	BIT(POWER_DOMAIN_AUX_B) \| \	330	BIT(POWER_DOMAIN_AUX_B) \| \
362	BIT(POWER_DOMAIN_AUX_C) \| \	331	BIT(POWER_DOMAIN_AUX_C) \| \
363	BIT(POWER_DOMAIN_AUDIO) \| \	332	BIT(POWER_DOMAIN_AUDIO) \| \
@@ -369,11 +338,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, · 5 unmodified lines
369	BIT(POWER_DOMAIN_PIPE_A) \| \	338	BIT(POWER_DOMAIN_PIPE_A) \| \
370	BIT(POWER_DOMAIN_TRANSCODER_EDP) \| \	339	BIT(POWER_DOMAIN_TRANSCODER_EDP) \| \
371	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) \| \	340	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) \| \
372	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) \| \	341	BIT(POWER_DOMAIN_PORT_DDI_A_LANES) \| \
373	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) \| \
374	BIT(POWER_DOMAIN_AUX_A) \| \	342	BIT(POWER_DOMAIN_AUX_A) \| \
375	BIT(POWER_DOMAIN_PLLS) \| \	343	BIT(POWER_DOMAIN_PLLS) \| \
376	BIT(POWER_DOMAIN_INIT))	344	BIT(POWER_DOMAIN_INIT))
		345	#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
		346	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS \| \
		347	BIT(POWER_DOMAIN_MODESET) \| \
		348	BIT(POWER_DOMAIN_AUX_A) \| \
		349	BIT(POWER_DOMAIN_INIT))
377	#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \	350	#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
378	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS \| \	351	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS \| \
379	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) \| \	352	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) \| \
@@ -417,46 +390,74 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) · 37 unmodified lines
417	*/	390	*/
418	}	391	}
419		392
420	void bxt_enable_dc9(struct drm_i915_private *dev_priv)	393	static void gen9_set_dc_state_debugmask_memory_up(
		394	struct drm_i915_private *dev_priv)
421	{	395	{
422	uint32_t val;	396	uint32_t val;
423		397
424	assert_can_enable_dc9(dev_priv);	398	/* The below bit doesn't need to be cleared ever afterwards */
		399	val = I915_READ(DC_STATE_DEBUG);
		400	if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
		401	val \|= DC_STATE_DEBUG_MASK_MEMORY_UP;
		402	I915_WRITE(DC_STATE_DEBUG, val);
		403	POSTING_READ(DC_STATE_DEBUG);
		404	}
		405	}
425		406
426	DRM_DEBUG_KMS("Enabling DC9\n");	407	static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
		408	{
		409	uint32_t val;
		410	uint32_t mask;
		411
		412	mask = DC_STATE_EN_UPTO_DC5;
		413	if (IS_BROXTON(dev_priv))
		414	mask \|= DC_STATE_EN_DC9;
		415	else
		416	mask \|= DC_STATE_EN_UPTO_DC6;
		417
		418	WARN_ON_ONCE(state & ~mask);
		419
		420	if (i915.enable_dc == 0)
		421	state = DC_STATE_DISABLE;
		422	else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
		423	state = DC_STATE_EN_UPTO_DC5;
		424
		425	if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
		426	gen9_set_dc_state_debugmask_memory_up(dev_priv);
427		427
428	val = I915_READ(DC_STATE_EN);	428	val = I915_READ(DC_STATE_EN);
429	val \|= DC_STATE_EN_DC9;	429	DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
		430	val & mask, state);
		431	val &= ~mask;
		432	val \|= state;
430	I915_WRITE(DC_STATE_EN, val);	433	I915_WRITE(DC_STATE_EN, val);
431	POSTING_READ(DC_STATE_EN);	434	POSTING_READ(DC_STATE_EN);
432	}	435	}
433		436
434	void bxt_disable_dc9(struct drm_i915_private *dev_priv)	437	void bxt_enable_dc9(struct drm_i915_private *dev_priv)
435	{	438	{
436	uint32_t val;	439	assert_can_enable_dc9(dev_priv);
		440
		441	DRM_DEBUG_KMS("Enabling DC9\n");
		442
		443	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
		444	}
437		445
		446	void bxt_disable_dc9(struct drm_i915_private *dev_priv)
		447	{
438	assert_can_disable_dc9(dev_priv);	448	assert_can_disable_dc9(dev_priv);
439		449
440	DRM_DEBUG_KMS("Disabling DC9\n");	450	DRM_DEBUG_KMS("Disabling DC9\n");
441		451
442	val = I915_READ(DC_STATE_EN);	452	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
443	val &= ~DC_STATE_EN_DC9;
444	I915_WRITE(DC_STATE_EN, val);
445	POSTING_READ(DC_STATE_EN);
446	}	453	}
447		454
448	static void gen9_set_dc_state_debugmask_memory_up(	455	static void assert_csr_loaded(struct drm_i915_private *dev_priv)
449	struct drm_i915_private *dev_priv)
450	{	456	{
451	uint32_t val;	457	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
452		458	"CSR program storage start is NULL\n");
453	/* The below bit doesn't need to be cleared ever afterwards */	459	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
454	val = I915_READ(DC_STATE_DEBUG);	460	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
455	if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
456	val \|= DC_STATE_DEBUG_MASK_MEMORY_UP;
457	I915_WRITE(DC_STATE_DEBUG, val);
458	POSTING_READ(DC_STATE_DEBUG);
459	}
460	}	461	}
461		462
462	static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)	463	static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
@@ -479,8 +480,6 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) · 16 unmodified lines
479		480
480	static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)	481	static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
481	{	482	{
482	bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
483	SKL_DISP_PW_2);
484	/*	483	/*
485	* During initialization, the firmware may not be loaded yet.	484	* During initialization, the firmware may not be loaded yet.
486	* We still want to make sure that the DC enabling flag is cleared.	485	* We still want to make sure that the DC enabling flag is cleared.
@@ -488,40 +487,17 @@ static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) · 1 unmodified line
488	if (dev_priv->power_domains.initializing)	487	if (dev_priv->power_domains.initializing)
489	return;	488	return;
490		489
491	WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
492	WARN_ONCE(dev_priv->pm.suspended,	490	WARN_ONCE(dev_priv->pm.suspended,
493	"Disabling of DC5 while platform is runtime-suspended should never happen.\n");	491	"Disabling of DC5 while platform is runtime-suspended should never happen.\n");
494	}	492	}
495		493
496	static void gen9_enable_dc5(struct drm_i915_private *dev_priv)	494	static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
497	{	495	{
498	uint32_t val;
499
500	assert_can_enable_dc5(dev_priv);	496	assert_can_enable_dc5(dev_priv);
501		497
502	DRM_DEBUG_KMS("Enabling DC5\n");	498	DRM_DEBUG_KMS("Enabling DC5\n");
503		499
504	gen9_set_dc_state_debugmask_memory_up(dev_priv);	500	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
505
506	val = I915_READ(DC_STATE_EN);
507	val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
508	val \|= DC_STATE_EN_UPTO_DC5;
509	I915_WRITE(DC_STATE_EN, val);
510	POSTING_READ(DC_STATE_EN);
511	}
512
513	static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
514	{
515	uint32_t val;
516
517	assert_can_disable_dc5(dev_priv);
518
519	DRM_DEBUG_KMS("Disabling DC5\n");
520
521	val = I915_READ(DC_STATE_EN);
522	val &= ~DC_STATE_EN_UPTO_DC5;
523	I915_WRITE(DC_STATE_EN, val);
524	POSTING_READ(DC_STATE_EN);
525	}	501	}
526		502
527	static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)	503	static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
@@ -547,40 +523,37 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) · 19 unmodified lines
547	if (dev_priv->power_domains.initializing)	523	if (dev_priv->power_domains.initializing)
548	return;	524	return;
549		525
550	assert_csr_loaded(dev_priv);
551	WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),	526	WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
552	"DC6 already programmed to be disabled.\n");	527	"DC6 already programmed to be disabled.\n");
553	}	528	}
554		529
555	static void skl_enable_dc6(struct drm_i915_private *dev_priv)	530	static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
556	{	531	{
557	uint32_t val;	532	assert_can_disable_dc5(dev_priv);
		533
		534	if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
		535	assert_can_disable_dc6(dev_priv);
558		536
		537	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
		538	}
		539
		540	void skl_enable_dc6(struct drm_i915_private *dev_priv)
		541	{
559	assert_can_enable_dc6(dev_priv);	542	assert_can_enable_dc6(dev_priv);
560		543
561	DRM_DEBUG_KMS("Enabling DC6\n");	544	DRM_DEBUG_KMS("Enabling DC6\n");
562		545
563	gen9_set_dc_state_debugmask_memory_up(dev_priv);	546	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
564		547
565	val = I915_READ(DC_STATE_EN);
566	val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
567	val \|= DC_STATE_EN_UPTO_DC6;
568	I915_WRITE(DC_STATE_EN, val);
569	POSTING_READ(DC_STATE_EN);
570	}	548	}
571		549
572	static void skl_disable_dc6(struct drm_i915_private *dev_priv)	550	void skl_disable_dc6(struct drm_i915_private *dev_priv)
573	{	551	{
574	uint32_t val;
575
576	assert_can_disable_dc6(dev_priv);	552	assert_can_disable_dc6(dev_priv);
577		553
578	DRM_DEBUG_KMS("Disabling DC6\n");	554	DRM_DEBUG_KMS("Disabling DC6\n");
579		555
580	val = I915_READ(DC_STATE_EN);	556	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
581	val &= ~DC_STATE_EN_UPTO_DC6;
582	I915_WRITE(DC_STATE_EN, val);
583	POSTING_READ(DC_STATE_EN);
584	}	557	}
585		558
586	static void skl_set_power_well(struct drm_i915_private *dev_priv,	559	static void skl_set_power_well(struct drm_i915_private *dev_priv,
@@ -630,20 +603,16 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, · 43 unmodified lines
630	!I915_READ(HSW_PWR_WELL_BIOS),	603	!I915_READ(HSW_PWR_WELL_BIOS),
631	"Invalid for power well status to be enabled, unless done by the BIOS, \	604	"Invalid for power well status to be enabled, unless done by the BIOS, \
632	when request is to disable!\n");	605	when request is to disable!\n");
633	if ((GEN9_ENABLE_DC5(dev) \|\| SKL_ENABLE_DC6(dev)) &&	606	if (power_well->data == SKL_DISP_PW_2) {
634	power_well->data == SKL_DISP_PW_2) {	607	/*
635	if (SKL_ENABLE_DC6(dev)) {	608	* DDI buffer programming unnecessary during
636	skl_disable_dc6(dev_priv);	609	* driver-load/resume as it's already done
637	/*	610	* during modeset initialization then. It's
638	* DDI buffer programming unnecessary during driver-load/resume	611	* also invalid here as encoder list is still
639	* as it's already done during modeset initialization then.	612	* uninitialized.
640	* It's also invalid here as encoder list is still uninitialized.	613	*/
641	*/	614	if (!dev_priv->power_domains.initializing)
642	if (!dev_priv->power_domains.initializing)	615	intel_prepare_ddi(dev);
643	intel_prepare_ddi(dev);
644	} else {
645	gen9_disable_dc5(dev_priv);
646	}
647	}	616	}
648	I915_WRITE(HSW_PWR_WELL_DRIVER, tmp \| req_mask);	617	I915_WRITE(HSW_PWR_WELL_DRIVER, tmp \| req_mask);
649	}	618	}
@@ -658,34 +627,9 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, · 8 unmodified lines
658	}	627	}
659	} else {	628	} else {
660	if (enable_requested) {	629	if (enable_requested) {
661	if (IS_SKYLAKE(dev) &&	630	I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
662	(power_well->data == SKL_DISP_PW_1) &&	631	POSTING_READ(HSW_PWR_WELL_DRIVER);
663	(intel_csr_load_status_get(dev_priv) == FW_LOADED))	632	DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
664	DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
665	else {
666	I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
667	POSTING_READ(HSW_PWR_WELL_DRIVER);
668	DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
669	}
670
671	if ((GEN9_ENABLE_DC5(dev) \|\| SKL_ENABLE_DC6(dev)) &&
672	power_well->data == SKL_DISP_PW_2) {
673	enum csr_state state;
674	/* TODO: wait for a completion event or
675	* similar here instead of busy
676	* waiting using wait_for function.
677	*/
678	wait_for((state = intel_csr_load_status_get(dev_priv)) !=
679	FW_UNINITIALIZED, 1000);
680	if (state != FW_LOADED)
681	DRM_DEBUG("CSR firmware not ready (%d)\n",
682	state);
683	else
684	if (SKL_ENABLE_DC6(dev))
685	skl_enable_dc6(dev_priv);
686	else
687	gen9_enable_dc5(dev_priv);
688	}
689	}	633	}
690	}	634	}
691		635
@@ -760,6 +704,41 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv, · 68 unmodified lines
760	skl_set_power_well(dev_priv, power_well, false);	704	skl_set_power_well(dev_priv, power_well, false);
761	}	705	}
762		706
		707	static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
		708	struct i915_power_well *power_well)
		709	{
		710	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
		711	}
		712
		713	static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
		714	struct i915_power_well *power_well)
		715	{
		716	gen9_disable_dc5_dc6(dev_priv);
		717	}
		718
		719	static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
		720	struct i915_power_well *power_well)
		721	{
		722	if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
		723	skl_enable_dc6(dev_priv);
		724	else
		725	gen9_enable_dc5(dev_priv);
		726	}
		727
		728	static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
		729	struct i915_power_well *power_well)
		730	{
		731	if (power_well->count > 0) {
		732	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
		733	} else {
		734	if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 &&
		735	i915.enable_dc != 1)
		736	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
		737	else
		738	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
		739	}
		740	}
		741
763	static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,	742	static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
764	struct i915_power_well *power_well)	743	struct i915_power_well *power_well)
765	{	744	{
@@ -974,10 +953,12 @@ static struct i915_power_well lookup_power_well(struct drm_i915_private dev_pr · 208 unmodified lines
974	int power_well_id)	953	int power_well_id)
975	{	954	{
976	struct i915_power_domains *power_domains = &dev_priv->power_domains;	955	struct i915_power_domains *power_domains = &dev_priv->power_domains;
977	struct i915_power_well *power_well;
978	int i;	956	int i;
979		957
980	for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {	958	for (i = 0; i < power_domains->power_well_count; i++) {
		959	struct i915_power_well *power_well;
		960
		961	power_well = &power_domains->power_wells[i];
981	if (power_well->data == power_well_id)	962	if (power_well->data == power_well_id)
982	return power_well;	963	return power_well;
983	}	964	}
@@ -1458,7 +1439,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 474 unmodified lines
1458	for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {	1439	for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1459	WARN_ON(!power_well->count);	1440	WARN_ON(!power_well->count);
1460		1441
1461	if (!--power_well->count && i915.disable_power_well)	1442	if (!--power_well->count)
1462	intel_power_well_disable(dev_priv, power_well);	1443	intel_power_well_disable(dev_priv, power_well);
1463	}	1444	}
1464		1445
@@ -1470,14 +1451,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 5 unmodified lines
1470	#define HSW_ALWAYS_ON_POWER_DOMAINS ( \	1451	#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1471	BIT(POWER_DOMAIN_PIPE_A) \| \	1452	BIT(POWER_DOMAIN_PIPE_A) \| \
1472	BIT(POWER_DOMAIN_TRANSCODER_EDP) \| \	1453	BIT(POWER_DOMAIN_TRANSCODER_EDP) \| \
1473	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) \| \	1454	BIT(POWER_DOMAIN_PORT_DDI_A_LANES) \| \
1474	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) \| \	1455	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
1475	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	1456	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
1476	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \	1457	BIT(POWER_DOMAIN_PORT_DDI_D_LANES) \| \
1477	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \
1478	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \
1479	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) \| \
1480	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) \| \
1481	BIT(POWER_DOMAIN_PORT_CRT) \| \	1458	BIT(POWER_DOMAIN_PORT_CRT) \| \
1482	BIT(POWER_DOMAIN_PLLS) \| \	1459	BIT(POWER_DOMAIN_PLLS) \| \
1483	BIT(POWER_DOMAIN_AUX_A) \| \	1460	BIT(POWER_DOMAIN_AUX_A) \| \
@@ -1501,49 +1478,42 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 17 unmodified lines
1501	#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK	1478	#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1502		1479
1503	#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \	1480	#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1504	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	1481	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
1505	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \	1482	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
1506	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \
1507	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \
1508	BIT(POWER_DOMAIN_PORT_CRT) \| \	1483	BIT(POWER_DOMAIN_PORT_CRT) \| \
1509	BIT(POWER_DOMAIN_AUX_B) \| \	1484	BIT(POWER_DOMAIN_AUX_B) \| \
1510	BIT(POWER_DOMAIN_AUX_C) \| \	1485	BIT(POWER_DOMAIN_AUX_C) \| \
1511	BIT(POWER_DOMAIN_INIT))	1486	BIT(POWER_DOMAIN_INIT))
1512		1487
1513	#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \	1488	#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1514	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	1489	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
1515	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \
1516	BIT(POWER_DOMAIN_AUX_B) \| \	1490	BIT(POWER_DOMAIN_AUX_B) \| \
1517	BIT(POWER_DOMAIN_INIT))	1491	BIT(POWER_DOMAIN_INIT))
1518		1492
1519	#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \	1493	#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1520	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \	1494	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
1521	BIT(POWER_DOMAIN_AUX_B) \| \	1495	BIT(POWER_DOMAIN_AUX_B) \| \
1522	BIT(POWER_DOMAIN_INIT))	1496	BIT(POWER_DOMAIN_INIT))
1523		1497
1524	#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \	1498	#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1525	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \	1499	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
1526	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \
1527	BIT(POWER_DOMAIN_AUX_C) \| \	1500	BIT(POWER_DOMAIN_AUX_C) \| \
1528	BIT(POWER_DOMAIN_INIT))	1501	BIT(POWER_DOMAIN_INIT))
1529		1502
1530	#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \	1503	#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1531	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \	1504	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
1532	BIT(POWER_DOMAIN_AUX_C) \| \	1505	BIT(POWER_DOMAIN_AUX_C) \| \
1533	BIT(POWER_DOMAIN_INIT))	1506	BIT(POWER_DOMAIN_INIT))
1534		1507
1535	#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \	1508	#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1536	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) \| \	1509	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) \| \
1537	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) \| \	1510	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) \| \
1538	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) \| \
1539	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) \| \
1540	BIT(POWER_DOMAIN_AUX_B) \| \	1511	BIT(POWER_DOMAIN_AUX_B) \| \
1541	BIT(POWER_DOMAIN_AUX_C) \| \	1512	BIT(POWER_DOMAIN_AUX_C) \| \
1542	BIT(POWER_DOMAIN_INIT))	1513	BIT(POWER_DOMAIN_INIT))
1543		1514
1544	#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \	1515	#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1545	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) \| \	1516	BIT(POWER_DOMAIN_PORT_DDI_D_LANES) \| \
1546	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) \| \
1547	BIT(POWER_DOMAIN_AUX_D) \| \	1517	BIT(POWER_DOMAIN_AUX_D) \| \
1548	BIT(POWER_DOMAIN_INIT))	1518	BIT(POWER_DOMAIN_INIT))
1549		1519
@@ -1591,6 +1561,13 @@ static const struct i915_power_well_ops skl_power_well_ops = { · 41 unmodified lines
1591	.is_enabled = skl_power_well_enabled,	1561	.is_enabled = skl_power_well_enabled,
1592	};	1562	};
1593		1563
		1564	static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
		1565	.sync_hw = gen9_dc_off_power_well_sync_hw,
		1566	.enable = gen9_dc_off_power_well_enable,
		1567	.disable = gen9_dc_off_power_well_disable,
		1568	.is_enabled = gen9_dc_off_power_well_enabled,
		1569	};
		1570
1594	static struct i915_power_well hsw_power_wells[] = {	1571	static struct i915_power_well hsw_power_wells[] = {
1595	{	1572	{
1596	.name = "always-on",	1573	.name = "always-on",
@@ -1646,6 +1623,7 @@ static struct i915_power_well vlv_power_wells[] = { · 49 unmodified lines
1646	.always_on = 1,	1623	.always_on = 1,
1647	.domains = VLV_ALWAYS_ON_POWER_DOMAINS,	1624	.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1648	.ops = &i9xx_always_on_power_well_ops,	1625	.ops = &i9xx_always_on_power_well_ops,
		1626	.data = PUNIT_POWER_WELL_ALWAYS_ON,
1649	},	1627	},
1650	{	1628	{
1651	.name = "display",	1629	.name = "display",
@@ -1747,19 +1725,28 @@ static struct i915_power_well skl_power_wells[] = { · 95 unmodified lines
1747	.always_on = 1,	1725	.always_on = 1,
1748	.domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,	1726	.domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1749	.ops = &i9xx_always_on_power_well_ops,	1727	.ops = &i9xx_always_on_power_well_ops,
		1728	.data = SKL_DISP_PW_ALWAYS_ON,
1750	},	1729	},
1751	{	1730	{
1752	.name = "power well 1",	1731	.name = "power well 1",
1753	.domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,	1732	/* Handled by the DMC firmware */
		1733	.domains = 0,
1754	.ops = &skl_power_well_ops,	1734	.ops = &skl_power_well_ops,
1755	.data = SKL_DISP_PW_1,	1735	.data = SKL_DISP_PW_1,
1756	},	1736	},
1757	{	1737	{
1758	.name = "MISC IO power well",	1738	.name = "MISC IO power well",
1759	.domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,	1739	/* Handled by the DMC firmware */
		1740	.domains = 0,
1760	.ops = &skl_power_well_ops,	1741	.ops = &skl_power_well_ops,
1761	.data = SKL_DISP_PW_MISC_IO,	1742	.data = SKL_DISP_PW_MISC_IO,
1762	},	1743	},
		1744	{
		1745	.name = "DC off",
		1746	.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
		1747	.ops = &gen9_dc_off_power_well_ops,
		1748	.data = SKL_DISP_PW_DC_OFF,
		1749	},
1763	{	1750	{
1764	.name = "power well 2",	1751	.name = "power well 2",
1765	.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,	1752	.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
@@ -1792,6 +1779,34 @@ static struct i915_power_well skl_power_wells[] = { · 26 unmodified lines
1792	},	1779	},
1793	};	1780	};
1794		1781
		1782	void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
		1783	{
		1784	struct i915_power_well *well;
		1785
		1786	if (!IS_SKYLAKE(dev_priv))
		1787	return;
		1788
		1789	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
		1790	intel_power_well_enable(dev_priv, well);
		1791
		1792	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
		1793	intel_power_well_enable(dev_priv, well);
		1794	}
		1795
		1796	void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
		1797	{
		1798	struct i915_power_well *well;
		1799
		1800	if (!IS_SKYLAKE(dev_priv))
		1801	return;
		1802
		1803	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
		1804	intel_power_well_disable(dev_priv, well);
		1805
		1806	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
		1807	intel_power_well_disable(dev_priv, well);
		1808	}
		1809
1795	static struct i915_power_well bxt_power_wells[] = {	1810	static struct i915_power_well bxt_power_wells[] = {
1796	{	1811	{
1797	.name = "always-on",	1812	.name = "always-on",
@@ -1805,12 +1820,18 @@ static struct i915_power_well bxt_power_wells[] = { · 7 unmodified lines
1805	.ops = &skl_power_well_ops,	1820	.ops = &skl_power_well_ops,
1806	.data = SKL_DISP_PW_1,	1821	.data = SKL_DISP_PW_1,
1807	},	1822	},
		1823	{
		1824	.name = "DC off",
		1825	.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
		1826	.ops = &gen9_dc_off_power_well_ops,
		1827	.data = SKL_DISP_PW_DC_OFF,
		1828	},
1808	{	1829	{
1809	.name = "power well 2",	1830	.name = "power well 2",
1810	.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,	1831	.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1811	.ops = &skl_power_well_ops,	1832	.ops = &skl_power_well_ops,
1812	.data = SKL_DISP_PW_2,	1833	.data = SKL_DISP_PW_2,
1813	}	1834	},
1814	};	1835	};
1815		1836
1816	static int	1837	static int
@@ -1859,7 +1880,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) · 42 unmodified lines
1859	set_power_wells(power_domains, hsw_power_wells);	1880	set_power_wells(power_domains, hsw_power_wells);
1860	} else if (IS_BROADWELL(dev_priv->dev)) {	1881	} else if (IS_BROADWELL(dev_priv->dev)) {
1861	set_power_wells(power_domains, bdw_power_wells);	1882	set_power_wells(power_domains, bdw_power_wells);
1862	} else if (IS_SKYLAKE(dev_priv->dev)) {	1883	} else if (IS_SKYLAKE(dev_priv->dev) \|\| IS_KABYLAKE(dev_priv->dev)) {
1863	set_power_wells(power_domains, skl_power_wells);	1884	set_power_wells(power_domains, skl_power_wells);
1864	} else if (IS_BROXTON(dev_priv->dev)) {	1885	} else if (IS_BROXTON(dev_priv->dev)) {
1865	set_power_wells(power_domains, bxt_power_wells);	1886	set_power_wells(power_domains, bxt_power_wells);
@@ -1874,21 +1895,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) · 8 unmodified lines
1874	return 0;	1895	return 0;
1875	}	1896	}
1876		1897
1877	static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1878	{
1879	struct drm_device *dev = dev_priv->dev;
1880	struct device *device = &dev->pdev->dev;
1881
1882	if (!HAS_RUNTIME_PM(dev))
1883	return;
1884
1885	if (!intel_enable_rc6(dev))
1886	return;
1887
1888	/* Make sure we're not suspended first. */
1889	pm_runtime_get_sync(device);
1890	}
1891
1892	/**	1898	/**
1893	* intel_power_domains_fini - finalizes the power domain structures	1899	* intel_power_domains_fini - finalizes the power domain structures
1894	* @dev_priv: i915 device instance	1900	* @dev_priv: i915 device instance
@@ -1899,15 +1905,17 @@ static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) · 4 unmodified lines
1899	*/	1905	*/
1900	void intel_power_domains_fini(struct drm_i915_private *dev_priv)	1906	void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1901	{	1907	{
1902	intel_runtime_pm_disable(dev_priv);
1903
1904	/* The i915.ko module is still not prepared to be loaded when	1908	/* The i915.ko module is still not prepared to be loaded when
1905	* the power well is not enabled, so just enable it in case	1909	* the power well is not enabled, so just enable it in case
1906	* we're going to unload/reload. */	1910	* we're going to unload/reload. */
1907	intel_display_set_init_power(dev_priv, true);	1911	intel_display_set_init_power(dev_priv, true);
		1912
		1913	/* Remove the refcount we took to keep power well support disabled. */
		1914	if (!i915.disable_power_well)
		1915	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1908	}	1916	}
1909		1917
1910	static void intel_power_domains_resume(struct drm_i915_private *dev_priv)	1918	static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
1911	{	1919	{
1912	struct i915_power_domains *power_domains = &dev_priv->power_domains;	1920	struct i915_power_domains *power_domains = &dev_priv->power_domains;
1913	struct i915_power_well *power_well;	1921	struct i915_power_well *power_well;
@@ -1922,6 +1930,47 @@ static void intel_power_domains_resume(struct drm_i915_private *dev_priv) · 8 unmodified lines
1922	mutex_unlock(&power_domains->lock);	1930	mutex_unlock(&power_domains->lock);
1923	}	1931	}
1924		1932
		1933	static void skl_display_core_init(struct drm_i915_private *dev_priv,
		1934	bool resume)
		1935	{
		1936	struct i915_power_domains *power_domains = &dev_priv->power_domains;
		1937	uint32_t val;
		1938
		1939	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
		1940
		1941	/* enable PCH reset handshake */
		1942	val = I915_READ(HSW_NDE_RSTWRN_OPT);
		1943	I915_WRITE(HSW_NDE_RSTWRN_OPT, val \| RESET_PCH_HANDSHAKE_ENABLE);
		1944
		1945	/* enable PG1 and Misc I/O */
		1946	mutex_lock(&power_domains->lock);
		1947	skl_pw1_misc_io_init(dev_priv);
		1948	mutex_unlock(&power_domains->lock);
		1949

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