Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Ingo Molnar: "Three fixes: - A boot crash fix with certain configs - a MAINTAINERS entry update - Documentation typo fixes" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/Documentation: Fix various typos in Documentation/x86/ files x86/amd_nb: Fix boot crash on non-AMD systems MAINTAINERS: Update the Calgary IOMMU entry

Linus Torvalds committed 10 years ago

Commit a017f582 parents 369da7f c76a0934 files · +8 −8Browse files

Unified · Split

4 files

Documentation/x86/intel_mpx.txt +3 −3
Documentation/x86/tlb.txt +2 −2
Documentation/x86/x86_64/machinecheck +1 −1
arch/x86/kernel/amd_nb.c +2 −2

Documentation/x86/intel_mpx.txt+3−3

@@ -45,7 +45,7 @@ is how we expect the compiler, application and kernel to work together. · 44 unmodified lines
45	45	MPX-instrumented.
46	46	3) The kernel detects that the CPU has MPX, allows the new prctl() to
47	47	succeed, and notes the location of the bounds directory. Userspace is
48		− expected to keep the bounds directory at that locationWe note it
	48	+ expected to keep the bounds directory at that location. We note it
49	49	instead of reading it each time because the 'xsave' operation needed
50	50	to access the bounds directory register is an expensive operation.
51	51	4) If the application needs to spill bounds out of the 4 registers, it
@@ -167,7 +167,7 @@ If a #BR is generated due to a bounds violation caused by MPX. · 115 unmodified lines
167	167	We need to decode MPX instructions to get violation address and
168	168	set this address into extended struct siginfo.
169	169
170		−The _sigfault feild of struct siginfo is extended as follow:
	170	+The _sigfault field of struct siginfo is extended as follow:
171	171
172	172	87 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
173	173	88 struct {
@@ -240,5 +240,5 @@ them at the same bounds table. · 66 unmodified lines
240	240	This is allowed architecturally. See more information "Intel(R) Architecture
241	241	Instruction Set Extensions Programming Reference" (9.3.4).
242	242
243		−However, if users did this, the kernel might be fooled in to unmaping an
	243	+However, if users did this, the kernel might be fooled in to unmapping an
244	244	in-use bounds table since it does not recognize sharing.

Documentation/x86/tlb.txt+2−2

@@ -5,7 +5,7 @@ memory, it has two choices: · 4 unmodified lines
5	5	from areas other than the one we are trying to flush will be
6	6	destroyed and must be refilled later, at some cost.
7	7	2. Use the invlpg instruction to invalidate a single page at a
8		− time. This could potentialy cost many more instructions, but
	8	+ time. This could potentially cost many more instructions, but
9	9	it is a much more precise operation, causing no collateral
10	10	damage to other TLB entries.
11	11
@@ -19,7 +19,7 @@ Which method to do depends on a few things: · 7 unmodified lines
19	19	work.
20	20	3. The size of the TLB. The larger the TLB, the more collateral
21	21	damage we do with a full flush. So, the larger the TLB, the
22		− more attrative an individual flush looks. Data and
	22	+ more attractive an individual flush looks. Data and
23	23	instructions have separate TLBs, as do different page sizes.
24	24	4. The microarchitecture. The TLB has become a multi-level
25	25	cache on modern CPUs, and the global flushes have become more

Documentation/x86/x86_64/machinecheck+1−1

@@ -36,7 +36,7 @@ between all CPUs. · 35 unmodified lines
36	36
37	37	check_interval
38	38	How often to poll for corrected machine check errors, in seconds
39		− (Note output is hexademical). Default 5 minutes. When the poller
	39	+ (Note output is hexadecimal). Default 5 minutes. When the poller
40	40	finds MCEs it triggers an exponential speedup (poll more often) on
41	41	the polling interval. When the poller stops finding MCEs, it
42	42	triggers an exponential backoff (poll less often) on the polling

arch/x86/kernel/amd_nb.c+2−2

@@ -71,8 +71,8 @@ int amd_cache_northbridges(void) · 70 unmodified lines
71	71	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
72	72	i++;
73	73
74		− if (i == 0)
75		− return 0;
	74	+ if (!i)
	75	+ return -ENODEV;
76	76
77	77	nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
78	78	if (!nb)