History

Merge tag 'drm-fixes-2026-03-21' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie: "Regular weekly pull request, from sunny San Diego. Usual suspects in xe/i915/amdgpu with small fixes all over, then some minor fixes across a few other drivers. It's probably a bit on the heavy side, but most of the fix seem well contained, core: - drm_dev_unplug UAF fix pagemap: - lock handling fix xe: - A number of teardown fixes - Skip over non-leaf PTE for PRL generation - Fix an uninitialized variable - Fix a missing runtime PM reference i915/display: - Fix #15771: Screen corruption and stuttering on P14s w/ 3K display - Fix for PSR entry setup frames count on rejected commit - Fix OOPS if firmware is not loaded and suspend is attempted - Fix unlikely NULL deref due to DC6 on probe amdgpu: - Fix gamma 2.2 colorop TFs - BO list fix - LTO fix - DC FP fix - DisplayID handling fix - DCN 2.01 fix - MMHUB boundary fixes - ISP fix - TLB fence fix - Hainan pm fix radeon: - Hainan pm fix vmwgfx: - memory leak fix - doc warning fix imagination: - deadlock fix - interrupt handling fixes dw-hdmi-qp: - multi channel audio fix" * tag 'drm-fixes-2026-03-21' of https://gitlab.freedesktop.org/drm/kernel: (40 commits) drm/xe: Fix missing runtime PM reference in ccs_mode_store drm/xe: Open-code GGTT MMIO access protection drm/xe/lrc: Fix uninitialized new_ts when capturing context timestamp drm/xe/oa: Allow reading after disabling OA stream drm/xe: Skip over non leaf pte for PRL generation drm/xe/guc: Ensure CT state transitions via STOP before DISABLED drm/xe: Trigger queue cleanup if not in wedged mode 2 drm/xe: Forcefully tear down exec queues in GuC submit fini drm/xe: Always kill exec queues in xe_guc_submit_pause_abort drm/xe/guc: Fail immediately on GuC load error drm/i915/gt: Check set_default_submission() before deferencing drm/radeon: apply state adjust rules to some additional HAINAN vairants drm/amdgpu: apply state adjust rules to some additional HAINAN vairants drm/amdgpu: rework how we handle TLB fences drm/bridge: dw-hdmi-qp: fix multi-channel audio output drm: Fix use-after-free on framebuffers and property blobs when calling drm_dev_unplug drm/amdgpu: Fix ISP segfault issue in kernel v7.0 drm/amdgpu/gmc9.0: add bounds checking for cid drm/amdgpu/mmhub4.2.0: add bounds checking for cid drm/amdgpu/mmhub4.1.0: add bounds checking for cid ...

Linus Torvalds committed 7 months ago

Commit a0c83172 parents 42bddab a6e773241 files · +325 −167Browse files

Unified · Split

41 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +4 −0
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +6 −1
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +2 −0
  4. drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +14 −7
  5. drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c +2 −2
  6. drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +6 −3
  7. drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +2 −1
  8. drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +2 −1
  9. drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c +2 −1
  10. drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +2 −1
  11. drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c +2 −1
  12. drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +2 −1
  13. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +3 −3
  14. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c +3 −3
  15. drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +4 −4
  16. drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +3 −0
  17. drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +3 −1
  18. drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +1 −1
  19. drivers/gpu/drm/drm_file.c +4 −1
  20. drivers/gpu/drm/drm_mode_config.c +6 −3
  21. drivers/gpu/drm/drm_pagemap_util.c +5 −9
  22. drivers/gpu/drm/i915/display/intel_display_power_well.c +1 −1
  23. drivers/gpu/drm/i915/display/intel_display_types.h +1 −0
  24. drivers/gpu/drm/i915/display/intel_dmc.c +1 −2
  25. drivers/gpu/drm/i915/display/intel_psr.c +5 −2
  26. drivers/gpu/drm/i915/gt/intel_engine_cs.c +2 −1
  27. drivers/gpu/drm/imagination/pvr_device.c +0 −17
  28. drivers/gpu/drm/imagination/pvr_power.c +39 −12
  29. drivers/gpu/drm/radeon/si_dpm.c +3 −1
  30. drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +57 −36
  31. drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +2 −1
  32. drivers/gpu/drm/xe/xe_ggtt.c +4 −6
  33. drivers/gpu/drm/xe/xe_ggtt_types.h +4 −1
  34. drivers/gpu/drm/xe/xe_gt_ccs_mode.c +2 −0
  35. drivers/gpu/drm/xe/xe_guc.c +27 −5
  36. drivers/gpu/drm/xe/xe_guc.h +1 −0
  37. drivers/gpu/drm/xe/xe_guc_ct.c +1 −0
  38. drivers/gpu/drm/xe/xe_guc_submit.c +61 −25
  39. drivers/gpu/drm/xe/xe_lrc.c +2 −2
  40. drivers/gpu/drm/xe/xe_oa.c +5 −2
  41. drivers/gpu/drm/xe/xe_pt.c +29 −9
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c+4−0
@@ -36,6 +36,7 @@ · 35 unmodified lines
36 36
37#define AMDGPU_BO_LIST_MAX_PRIORITY 32u37#define AMDGPU_BO_LIST_MAX_PRIORITY 32u
38#define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1)38#define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1)
39#define AMDGPU_BO_LIST_MAX_ENTRIES (128 * 1024)
39 40
40static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu)41static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu)
41{42{
@@ -188,6 +189,9 @@ int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in, · 146 unmodified lines
188 const uint32_t bo_number = in->bo_number;189 const uint32_t bo_number = in->bo_number;
189 struct drm_amdgpu_bo_list_entry *info;190 struct drm_amdgpu_bo_list_entry *info;
190 191
192 if (bo_number > AMDGPU_BO_LIST_MAX_ENTRIES)
193 return -EINVAL;
194
191 /* copy the handle array from userspace to a kernel buffer */195 /* copy the handle array from userspace to a kernel buffer */
192 if (likely(info_size == bo_info_size)) {196 if (likely(info_size == bo_info_size)) {
193 info = vmemdup_array_user(uptr, bo_number, info_size);197 info = vmemdup_array_user(uptr, bo_number, info_size);
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+6−1
@@ -1069,7 +1069,10 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, · 1068 unmodified lines
1069 }1069 }
1070 1070
1071 /* Prepare a TLB flush fence to be attached to PTs */1071 /* Prepare a TLB flush fence to be attached to PTs */
1072 if (!params->unlocked) {1072 /* The check for need_tlb_fence should be dropped once we
1073 * sort out the issues with KIQ/MES TLB invalidation timeouts.
1074 */
1075 if (!params->unlocked && vm->need_tlb_fence) {
1073 amdgpu_vm_tlb_fence_create(params->adev, vm, fence);1076 amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
1074 1077
1075 /* Makes sure no PD/PT is freed before the flush */1078 /* Makes sure no PD/PT is freed before the flush */
@@ -2602,6 +2605,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 1526 unmodified lines
2602 ttm_lru_bulk_move_init(&vm->lru_bulk_move);2605 ttm_lru_bulk_move_init(&vm->lru_bulk_move);
2603 2606
2604 vm->is_compute_context = false;2607 vm->is_compute_context = false;
2608 vm->need_tlb_fence = amdgpu_userq_enabled(&adev->ddev);
2605 2609
2606 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &2610 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2607 AMDGPU_VM_USE_CPU_FOR_GFX);2611 AMDGPU_VM_USE_CPU_FOR_GFX);
@@ -2739,6 +2743,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 131 unmodified lines
2739 dma_fence_put(vm->last_update);2743 dma_fence_put(vm->last_update);
2740 vm->last_update = dma_fence_get_stub();2744 vm->last_update = dma_fence_get_stub();
2741 vm->is_compute_context = true;2745 vm->is_compute_context = true;
2746 vm->need_tlb_fence = true;
2742 2747
2743unreserve_bo:2748unreserve_bo:
2744 amdgpu_bo_unreserve(vm->root.bo);2749 amdgpu_bo_unreserve(vm->root.bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+2−0
@@ -441,6 +441,8 @@ struct amdgpu_vm { · 440 unmodified lines
441 struct ttm_lru_bulk_move lru_bulk_move;441 struct ttm_lru_bulk_move lru_bulk_move;
442 /* Flag to indicate if VM is used for compute */442 /* Flag to indicate if VM is used for compute */
443 bool is_compute_context;443 bool is_compute_context;
444 /* Flag to indicate if VM needs a TLB fence (KFD or KGD) */
445 bool need_tlb_fence;
444 446
445 /* Memory partition number, -1 means any partition */447 /* Memory partition number, -1 means any partition */
446 int8_t mem_id;448 int8_t mem_id;
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+14−7
@@ -662,28 +662,35 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, · 661 unmodified lines
662 } else {662 } else {
663 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {663 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
664 case IP_VERSION(9, 0, 0):664 case IP_VERSION(9, 0, 0):
665 mmhub_cid = mmhub_client_ids_vega10[cid][rw];665 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega10) ?
666 mmhub_client_ids_vega10[cid][rw] : NULL;
666 break;667 break;
667 case IP_VERSION(9, 3, 0):668 case IP_VERSION(9, 3, 0):
668 mmhub_cid = mmhub_client_ids_vega12[cid][rw];669 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega12) ?
670 mmhub_client_ids_vega12[cid][rw] : NULL;
669 break;671 break;
670 case IP_VERSION(9, 4, 0):672 case IP_VERSION(9, 4, 0):
671 mmhub_cid = mmhub_client_ids_vega20[cid][rw];673 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega20) ?
674 mmhub_client_ids_vega20[cid][rw] : NULL;
672 break;675 break;
673 case IP_VERSION(9, 4, 1):676 case IP_VERSION(9, 4, 1):
674 mmhub_cid = mmhub_client_ids_arcturus[cid][rw];677 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_arcturus) ?
678 mmhub_client_ids_arcturus[cid][rw] : NULL;
675 break;679 break;
676 case IP_VERSION(9, 1, 0):680 case IP_VERSION(9, 1, 0):
677 case IP_VERSION(9, 2, 0):681 case IP_VERSION(9, 2, 0):
678 mmhub_cid = mmhub_client_ids_raven[cid][rw];682 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_raven) ?
683 mmhub_client_ids_raven[cid][rw] : NULL;
679 break;684 break;
680 case IP_VERSION(1, 5, 0):685 case IP_VERSION(1, 5, 0):
681 case IP_VERSION(2, 4, 0):686 case IP_VERSION(2, 4, 0):
682 mmhub_cid = mmhub_client_ids_renoir[cid][rw];687 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_renoir) ?
688 mmhub_client_ids_renoir[cid][rw] : NULL;
683 break;689 break;
684 case IP_VERSION(1, 8, 0):690 case IP_VERSION(1, 8, 0):
685 case IP_VERSION(9, 4, 2):691 case IP_VERSION(9, 4, 2):
686 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];692 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_aldebaran) ?
693 mmhub_client_ids_aldebaran[cid][rw] : NULL;
687 break;694 break;
688 default:695 default:
689 mmhub_cid = NULL;696 mmhub_cid = NULL;
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c+2−2
@@ -129,7 +129,7 @@ static int isp_genpd_add_device(struct device *dev, void *data) · 128 unmodified lines
129 if (!pdev)129 if (!pdev)
130 return -EINVAL;130 return -EINVAL;
131 131
132 if (!dev->type->name) {132 if (!dev->type || !dev->type->name) {
133 drm_dbg(&adev->ddev, "Invalid device type to add\n");133 drm_dbg(&adev->ddev, "Invalid device type to add\n");
134 goto exit;134 goto exit;
135 }135 }
@@ -165,7 +165,7 @@ static int isp_genpd_remove_device(struct device *dev, void *data) · 29 unmodified lines
165 if (!pdev)165 if (!pdev)
166 return -EINVAL;166 return -EINVAL;
167 167
168 if (!dev->type->name) {168 if (!dev->type || !dev->type->name) {
169 drm_dbg(&adev->ddev, "Invalid device type to remove\n");169 drm_dbg(&adev->ddev, "Invalid device type to remove\n");
170 goto exit;170 goto exit;
171 }171 }
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c+6−3
@@ -154,14 +154,17 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, · 153 unmodified lines
154 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {154 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
155 case IP_VERSION(2, 0, 0):155 case IP_VERSION(2, 0, 0):
156 case IP_VERSION(2, 0, 2):156 case IP_VERSION(2, 0, 2):
157 mmhub_cid = mmhub_client_ids_navi1x[cid][rw];157 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_navi1x) ?
158 mmhub_client_ids_navi1x[cid][rw] : NULL;
158 break;159 break;
159 case IP_VERSION(2, 1, 0):160 case IP_VERSION(2, 1, 0):
160 case IP_VERSION(2, 1, 1):161 case IP_VERSION(2, 1, 1):
161 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];162 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_sienna_cichlid) ?
163 mmhub_client_ids_sienna_cichlid[cid][rw] : NULL;
162 break;164 break;
163 case IP_VERSION(2, 1, 2):165 case IP_VERSION(2, 1, 2):
164 mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];166 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_beige_goby) ?
167 mmhub_client_ids_beige_goby[cid][rw] : NULL;
165 break;168 break;
166 default:169 default:
167 mmhub_cid = NULL;170 mmhub_cid = NULL;
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c+2−1
@@ -94,7 +94,8 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, · 93 unmodified lines
94 case IP_VERSION(2, 3, 0):94 case IP_VERSION(2, 3, 0):
95 case IP_VERSION(2, 4, 0):95 case IP_VERSION(2, 4, 0):
96 case IP_VERSION(2, 4, 1):96 case IP_VERSION(2, 4, 1):
97 mmhub_cid = mmhub_client_ids_vangogh[cid][rw];97 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vangogh) ?
98 mmhub_client_ids_vangogh[cid][rw] : NULL;
98 break;99 break;
99 default:100 default:
100 mmhub_cid = NULL;101 mmhub_cid = NULL;
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c+2−1
@@ -110,7 +110,8 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, · 109 unmodified lines
110 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {110 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
111 case IP_VERSION(3, 0, 0):111 case IP_VERSION(3, 0, 0):
112 case IP_VERSION(3, 0, 1):112 case IP_VERSION(3, 0, 1):
113 mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw];113 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_0) ?
114 mmhub_client_ids_v3_0_0[cid][rw] : NULL;
114 break;115 break;
115 default:116 default:
116 mmhub_cid = NULL;117 mmhub_cid = NULL;
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c+2−1
@@ -117,7 +117,8 @@ mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, · 116 unmodified lines
117 117
118 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {118 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
119 case IP_VERSION(3, 0, 1):119 case IP_VERSION(3, 0, 1):
120 mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];120 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_1) ?
121 mmhub_client_ids_v3_0_1[cid][rw] : NULL;
121 break;122 break;
122 default:123 default:
123 mmhub_cid = NULL;124 mmhub_cid = NULL;
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c+2−1
@@ -108,7 +108,8 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, · 107 unmodified lines
108 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",108 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
109 status);109 status);
110 110
111 mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw];111 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_2) ?
112 mmhub_client_ids_v3_0_2[cid][rw] : NULL;
112 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",113 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
113 mmhub_cid ? mmhub_cid : "unknown", cid);114 mmhub_cid ? mmhub_cid : "unknown", cid);
114 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",115 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c+2−1
@@ -102,7 +102,8 @@ mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, · 101 unmodified lines
102 status);102 status);
103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
104 case IP_VERSION(4, 1, 0):104 case IP_VERSION(4, 1, 0):
105 mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw];105 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_1_0) ?
106 mmhub_client_ids_v4_1_0[cid][rw] : NULL;
106 break;107 break;
107 default:108 default:
108 mmhub_cid = NULL;109 mmhub_cid = NULL;
drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c+2−1
@@ -688,7 +688,8 @@ mmhub_v4_2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, · 687 unmodified lines
688 status);688 status);
689 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {689 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
690 case IP_VERSION(4, 2, 0):690 case IP_VERSION(4, 2, 0):
691 mmhub_cid = mmhub_client_ids_v4_2_0[cid][rw];691 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_2_0) ?
692 mmhub_client_ids_v4_2_0[cid][rw] : NULL;
692 break;693 break;
693 default:694 default:
694 mmhub_cid = NULL;695 mmhub_cid = NULL;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+3−3
@@ -2554,7 +2554,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) · 2553 unmodified lines
2554 fw_meta_info_params.fw_inst_const = adev->dm.dmub_fw->data +2554 fw_meta_info_params.fw_inst_const = adev->dm.dmub_fw->data +
2555 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +2555 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2556 PSP_HEADER_BYTES_256;2556 PSP_HEADER_BYTES_256;
2557 fw_meta_info_params.fw_bss_data = region_params.bss_data_size ? adev->dm.dmub_fw->data +2557 fw_meta_info_params.fw_bss_data = fw_meta_info_params.bss_data_size ? adev->dm.dmub_fw->data +
2558 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +2558 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2559 le32_to_cpu(hdr->inst_const_bytes) : NULL;2559 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2560 fw_meta_info_params.custom_psp_footer_size = 0;2560 fw_meta_info_params.custom_psp_footer_size = 0;
@@ -13119,7 +13119,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, · 10558 unmodified lines
13119 u16 min_vfreq;13119 u16 min_vfreq;
13120 u16 max_vfreq;13120 u16 max_vfreq;
13121 13121
13122 if (edid == NULL || edid->extensions == 0)13122 if (!edid || !edid->extensions)
13123 return;13123 return;
13124 13124
13125 /* Find DisplayID extension */13125 /* Find DisplayID extension */
@@ -13129,7 +13129,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, · 3 unmodified lines
13129 break;13129 break;
13130 }13130 }
13131 13131
13132 if (edid_ext == NULL)13132 if (i == edid->extensions)
13133 return;13133 return;
13134 13134
13135 while (j < EDID_LENGTH) {13135 while (j < EDID_LENGTH) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c+3−3
@@ -37,19 +37,19 @@ const u64 amdgpu_dm_supported_degam_tfs = · 36 unmodified lines
37 BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |37 BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
38 BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |38 BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
39 BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |39 BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
40 BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);40 BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
41 41
42const u64 amdgpu_dm_supported_shaper_tfs =42const u64 amdgpu_dm_supported_shaper_tfs =
43 BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |43 BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |
44 BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |44 BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |
45 BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |45 BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |
46 BIT(DRM_COLOROP_1D_CURVE_GAMMA22);46 BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
47 47
48const u64 amdgpu_dm_supported_blnd_tfs =48const u64 amdgpu_dm_supported_blnd_tfs =
49 BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |49 BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
50 BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |50 BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
51 BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |51 BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
52 BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);52 BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
53 53
54#define MAX_COLOR_PIPELINE_OPS 1054#define MAX_COLOR_PIPELINE_OPS 10
55 55
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c+4−4
@@ -255,6 +255,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p · 254 unmodified lines
255 BREAK_TO_DEBUGGER();255 BREAK_TO_DEBUGGER();
256 return NULL;256 return NULL;
257 }257 }
258 if (ctx->dce_version == DCN_VERSION_2_01) {
259 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
260 return &clk_mgr->base;
261 }
258 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {262 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
259 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);263 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
260 return &clk_mgr->base;264 return &clk_mgr->base;
@@ -267,10 +271,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p · 6 unmodified lines
267 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);271 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
268 return &clk_mgr->base;272 return &clk_mgr->base;
269 }273 }
270 if (ctx->dce_version == DCN_VERSION_2_01) {
271 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
272 return &clk_mgr->base;
273 }
274 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);274 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
275 return &clk_mgr->base;275 return &clk_mgr->base;
276 }276 }
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c+3−0
@@ -1785,7 +1785,10 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_valid · 1784 unmodified lines
1785 1785
1786 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);1786 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1787 1787
1788 DC_FP_START();
1788 dcn32_override_min_req_memclk(dc, context);1789 dcn32_override_min_req_memclk(dc, context);
1790 DC_FP_END();
1791
1789 dcn32_override_min_req_dcfclk(dc, context);1792 dcn32_override_min_req_dcfclk(dc, context);
1790 1793
1791 BW_VAL_TRACE_END_WATERMARKS();1794 BW_VAL_TRACE_END_WATERMARKS();
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c+3−1
@@ -3454,9 +3454,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, · 3453 unmodified lines
3454 if (adev->asic_type == CHIP_HAINAN) {3454 if (adev->asic_type == CHIP_HAINAN) {
3455 if ((adev->pdev->revision == 0x81) ||3455 if ((adev->pdev->revision == 0x81) ||
3456 (adev->pdev->revision == 0xC3) ||3456 (adev->pdev->revision == 0xC3) ||
3457 (adev->pdev->device == 0x6660) ||
3457 (adev->pdev->device == 0x6664) ||3458 (adev->pdev->device == 0x6664) ||
3458 (adev->pdev->device == 0x6665) ||3459 (adev->pdev->device == 0x6665) ||
3459 (adev->pdev->device == 0x6667)) {3460 (adev->pdev->device == 0x6667) ||
3461 (adev->pdev->device == 0x666F)) {
3460 max_sclk = 75000;3462 max_sclk = 75000;
3461 }3463 }
3462 if ((adev->pdev->revision == 0xC3) ||3464 if ((adev->pdev->revision == 0xC3) ||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c+1−1
@@ -848,7 +848,7 @@ static int dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp *hdmi, · 847 unmodified lines
848 848
849 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1);849 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1);
850 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1);850 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1);
851 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[4], 1);851 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[7], 1);
852 852
853 /* Enable ACR, AUDI, AMD */853 /* Enable ACR, AUDI, AMD */
854 dw_hdmi_qp_mod(hdmi,854 dw_hdmi_qp_mod(hdmi,
drivers/gpu/drm/drm_file.c+4−1
@@ -233,6 +233,7 @@ static void drm_events_release(struct drm_file *file_priv) · 232 unmodified lines
233void drm_file_free(struct drm_file *file)233void drm_file_free(struct drm_file *file)
234{234{
235 struct drm_device *dev;235 struct drm_device *dev;
236 int idx;
236 237
237 if (!file)238 if (!file)
238 return;239 return;
@@ -249,9 +250,11 @@ void drm_file_free(struct drm_file *file) · 10 unmodified lines
249 250
250 drm_events_release(file);251 drm_events_release(file);
251 252
252 if (drm_core_check_feature(dev, DRIVER_MODESET)) {253 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
254 drm_dev_enter(dev, &idx)) {
253 drm_fb_release(file);255 drm_fb_release(file);
254 drm_property_destroy_user_blobs(dev, file);256 drm_property_destroy_user_blobs(dev, file);
257 drm_dev_exit(idx);
255 }258 }
256 259
257 if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))260 if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
drivers/gpu/drm/drm_mode_config.c+6−3
@@ -577,10 +577,13 @@ void drm_mode_config_cleanup(struct drm_device *dev) · 576 unmodified lines
577 */577 */
578 WARN_ON(!list_empty(&dev->mode_config.fb_list));578 WARN_ON(!list_empty(&dev->mode_config.fb_list));
579 list_for_each_entry_safe(fb, fbt, &dev->mode_config.fb_list, head) {579 list_for_each_entry_safe(fb, fbt, &dev->mode_config.fb_list, head) {
580 struct drm_printer p = drm_dbg_printer(dev, DRM_UT_KMS, "[leaked fb]");580 if (list_empty(&fb->filp_head) || drm_framebuffer_read_refcount(fb) > 1) {
581 struct drm_printer p = drm_dbg_printer(dev, DRM_UT_KMS, "[leaked fb]");
581 582
582 drm_printf(&p, "framebuffer[%u]:\n", fb->base.id);583 drm_printf(&p, "framebuffer[%u]:\n", fb->base.id);
583 drm_framebuffer_print_info(&p, 1, fb);584 drm_framebuffer_print_info(&p, 1, fb);
585 }
586 list_del_init(&fb->filp_head);
584 drm_framebuffer_free(&fb->base.refcount);587 drm_framebuffer_free(&fb->base.refcount);
585 }588 }
586 589
drivers/gpu/drm/drm_pagemap_util.c+5−9
@@ -65,18 +65,14 @@ static void drm_pagemap_cache_fini(void *arg) · 64 unmodified lines
65 drm_dbg(cache->shrinker->drm, "Destroying dpagemap cache.\n");65 drm_dbg(cache->shrinker->drm, "Destroying dpagemap cache.\n");
66 spin_lock(&cache->lock);66 spin_lock(&cache->lock);
67 dpagemap = cache->dpagemap;67 dpagemap = cache->dpagemap;
68 if (!dpagemap) {68 cache->dpagemap = NULL;
69 spin_unlock(&cache->lock);69 if (dpagemap && !drm_pagemap_shrinker_cancel(dpagemap))
70 goto out;70 dpagemap = NULL;
71 }71 spin_unlock(&cache->lock);
72 72
73 if (drm_pagemap_shrinker_cancel(dpagemap)) {73 if (dpagemap)
74 cache->dpagemap = NULL;
75 spin_unlock(&cache->lock);
76 drm_pagemap_destroy(dpagemap, false);74 drm_pagemap_destroy(dpagemap, false);
77 }
78 75
79out:
80 mutex_destroy(&cache->lookup_mutex);76 mutex_destroy(&cache->lookup_mutex);
81 kfree(cache);77 kfree(cache);
82}78}
drivers/gpu/drm/i915/display/intel_display_power_well.c+1−1
@@ -806,7 +806,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state) · 805 unmodified lines
806 power_domains->dc_state, val & mask);806 power_domains->dc_state, val & mask);
807 807
808 enable_dc6 = state & DC_STATE_EN_UPTO_DC6;808 enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
809 dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;809 dc6_was_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6;
810 if (!dc6_was_enabled && enable_dc6)810 if (!dc6_was_enabled && enable_dc6)
811 intel_dmc_update_dc6_allowed_count(display, true);811 intel_dmc_update_dc6_allowed_count(display, true);
812 812
drivers/gpu/drm/i915/display/intel_display_types.h+1−0
@@ -1186,6 +1186,7 @@ struct intel_crtc_state { · 1185 unmodified lines
1186 u32 dc3co_exitline;1186 u32 dc3co_exitline;
1187 u16 su_y_granularity;1187 u16 su_y_granularity;
1188 u8 active_non_psr_pipes;1188 u8 active_non_psr_pipes;
1189 u8 entry_setup_frames;
1189 const char *no_psr_reason;1190 const char *no_psr_reason;
1190 1191
1191 /*1192 /*
drivers/gpu/drm/i915/display/intel_dmc.c+1−2
@@ -1599,8 +1599,7 @@ static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 * · 1598 unmodified lines
1599 return false;1599 return false;
1600 1600
1601 mutex_lock(&power_domains->lock);1601 mutex_lock(&power_domains->lock);
1602 dc6_enabled = intel_de_read(display, DC_STATE_EN) &1602 dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6;
1603 DC_STATE_EN_UPTO_DC6;
1604 if (dc6_enabled)1603 if (dc6_enabled)
1605 intel_dmc_update_dc6_allowed_count(display, false);1604 intel_dmc_update_dc6_allowed_count(display, false);
1606 1605
drivers/gpu/drm/i915/display/intel_psr.c+5−2
@@ -1717,7 +1717,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, · 1716 unmodified lines
1717 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);1717 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
1718 1718
1719 if (entry_setup_frames >= 0) {1719 if (entry_setup_frames >= 0) {
1720 intel_dp->psr.entry_setup_frames = entry_setup_frames;1720 crtc_state->entry_setup_frames = entry_setup_frames;
1721 } else {1721 } else {
1722 crtc_state->no_psr_reason = "PSR setup timing not met";1722 crtc_state->no_psr_reason = "PSR setup timing not met";
1723 drm_dbg_kms(display->drm,1723 drm_dbg_kms(display->drm,
@@ -1815,7 +1815,7 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, · 91 unmodified lines
1815{1815{
1816 struct intel_display *display = to_intel_display(intel_dp);1816 struct intel_display *display = to_intel_display(intel_dp);
1817 1817
1818 return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 &&1818 return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
1819 !crtc_state->has_sel_update);1819 !crtc_state->has_sel_update);
1820}1820}
1821 1821
@@ -2189,6 +2189,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, · 367 unmodified lines
2189 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;2189 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
2190 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;2190 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;
2191 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;2191 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;
2192 intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
2192 2193
2193 if (!psr_interrupt_error_check(intel_dp))2194 if (!psr_interrupt_error_check(intel_dp))
2194 return;2195 return;
@@ -3109,6 +3110,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, · 914 unmodified lines
3109 * - Display WA #1136: skl, bxt3110 * - Display WA #1136: skl, bxt
3110 */3111 */
3111 if (intel_crtc_needs_modeset(new_crtc_state) ||3112 if (intel_crtc_needs_modeset(new_crtc_state) ||
3113 new_crtc_state->update_m_n ||
3114 new_crtc_state->update_lrr ||
3112 !new_crtc_state->has_psr ||3115 !new_crtc_state->has_psr ||
3113 !new_crtc_state->active_planes ||3116 !new_crtc_state->active_planes ||
3114 new_crtc_state->has_sel_update != psr->sel_update_enabled ||3117 new_crtc_state->has_sel_update != psr->sel_update_enabled ||
drivers/gpu/drm/i915/gt/intel_engine_cs.c+2−1
@@ -1967,7 +1967,8 @@ void intel_engines_reset_default_submission(struct intel_gt *gt) · 1966 unmodified lines
1967 if (engine->sanitize)1967 if (engine->sanitize)
1968 engine->sanitize(engine);1968 engine->sanitize(engine);
1969 1969
1970 engine->set_default_submission(engine);1970 if (engine->set_default_submission)
1971 engine->set_default_submission(engine);
1971 }1972 }
1972}1973}
1973 1974
drivers/gpu/drm/imagination/pvr_device.c+0−17
@@ -225,29 +225,12 @@ static irqreturn_t pvr_device_irq_thread_handler(int irq, void *data) · 224 unmodified lines
225 }225 }
226 226
227 if (pvr_dev->has_safety_events) {227 if (pvr_dev->has_safety_events) {
228 int err;
229
230 /*
231 * Ensure the GPU is powered on since some safety events (such
232 * as ECC faults) can happen outside of job submissions, which
233 * are otherwise the only time a power reference is held.
234 */
235 err = pvr_power_get(pvr_dev);
236 if (err) {
237 drm_err_ratelimited(drm_dev,
238 "%s: could not take power reference (%d)\n",
239 __func__, err);
240 return ret;
241 }
242
243 while (pvr_device_safety_irq_pending(pvr_dev)) {228 while (pvr_device_safety_irq_pending(pvr_dev)) {
244 pvr_device_safety_irq_clear(pvr_dev);229 pvr_device_safety_irq_clear(pvr_dev);
245 pvr_device_handle_safety_events(pvr_dev);230 pvr_device_handle_safety_events(pvr_dev);
246 231
247 ret = IRQ_HANDLED;232 ret = IRQ_HANDLED;
248 }233 }
249
250 pvr_power_put(pvr_dev);
251 }234 }
252 235
253 return ret;236 return ret;
drivers/gpu/drm/imagination/pvr_power.c+39−12
@@ -90,11 +90,11 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) · 89 unmodified lines
90}90}
91 91
92static int92static int
93pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset)93pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend)
94{94{
95 if (!hard_reset) {95 int err;
96 int err;
97 96
97 if (!hard_reset) {
98 cancel_delayed_work_sync(&pvr_dev->watchdog.work);98 cancel_delayed_work_sync(&pvr_dev->watchdog.work);
99 99
100 err = pvr_power_request_idle(pvr_dev);100 err = pvr_power_request_idle(pvr_dev);
@@ -106,29 +106,47 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset) · 5 unmodified lines
106 return err;106 return err;
107 }107 }
108 108
109 return pvr_fw_stop(pvr_dev);109 if (rpm_suspend) {
110 /* This also waits for late processing of GPU or firmware IRQs in other cores */
111 disable_irq(pvr_dev->irq);
112 }
113
114 err = pvr_fw_stop(pvr_dev);
115 if (err && rpm_suspend)
116 enable_irq(pvr_dev->irq);
117
118 return err;
110}119}
111 120
112static int121static int
113pvr_power_fw_enable(struct pvr_device *pvr_dev)122pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume)
114{123{
115 int err;124 int err;
116 125
126 if (rpm_resume)
127 enable_irq(pvr_dev->irq);
128
117 err = pvr_fw_start(pvr_dev);129 err = pvr_fw_start(pvr_dev);
118 if (err)130 if (err)
119 return err;131 goto out;
120 132
121 err = pvr_wait_for_fw_boot(pvr_dev);133 err = pvr_wait_for_fw_boot(pvr_dev);
122 if (err) {134 if (err) {
123 drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n");135 drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n");
124 pvr_fw_stop(pvr_dev);136 pvr_fw_stop(pvr_dev);
125 return err;137 goto out;
126 }138 }
127 139
128 queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work,140 queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work,
129 msecs_to_jiffies(WATCHDOG_TIME_MS));141 msecs_to_jiffies(WATCHDOG_TIME_MS));
130 142
131 return 0;143 return 0;
144
145out:
146 if (rpm_resume)
147 disable_irq(pvr_dev->irq);
148
149 return err;
132}150}
133 151
134bool152bool
@@ -361,7 +379,7 @@ pvr_power_device_suspend(struct device *dev) · 226 unmodified lines
361 return -EIO;379 return -EIO;
362 380
363 if (pvr_dev->fw_dev.booted) {381 if (pvr_dev->fw_dev.booted) {
364 err = pvr_power_fw_disable(pvr_dev, false);382 err = pvr_power_fw_disable(pvr_dev, false, true);
365 if (err)383 if (err)
366 goto err_drm_dev_exit;384 goto err_drm_dev_exit;
367 }385 }
@@ -391,7 +409,7 @@ pvr_power_device_resume(struct device *dev) · 23 unmodified lines
391 goto err_drm_dev_exit;409 goto err_drm_dev_exit;
392 410
393 if (pvr_dev->fw_dev.booted) {411 if (pvr_dev->fw_dev.booted) {
394 err = pvr_power_fw_enable(pvr_dev);412 err = pvr_power_fw_enable(pvr_dev, true);
395 if (err)413 if (err)
396 goto err_power_off;414 goto err_power_off;
397 }415 }
@@ -510,7 +528,16 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) · 112 unmodified lines
510 }528 }
511 529
512 /* Disable IRQs for the duration of the reset. */530 /* Disable IRQs for the duration of the reset. */
513 disable_irq(pvr_dev->irq);531 if (hard_reset) {
532 disable_irq(pvr_dev->irq);
533 } else {
534 /*
535 * Soft reset is triggered as a response to a FW command to the Host and is
536 * processed from the threaded IRQ handler. This code cannot (nor needs to)
537 * wait for any IRQ processing to complete.
538 */
539 disable_irq_nosync(pvr_dev->irq);
540 }
514 541
515 do {542 do {
516 if (hard_reset) {543 if (hard_reset) {
@@ -518,7 +545,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) · 1 unmodified line
518 queues_disabled = true;545 queues_disabled = true;
519 }546 }
520 547
521 err = pvr_power_fw_disable(pvr_dev, hard_reset);548 err = pvr_power_fw_disable(pvr_dev, hard_reset, false);
522 if (!err) {549 if (!err) {
523 if (hard_reset) {550 if (hard_reset) {
524 pvr_dev->fw_dev.booted = false;551 pvr_dev->fw_dev.booted = false;
@@ -541,7 +568,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) · 16 unmodified lines
541 568
542 pvr_fw_irq_clear(pvr_dev);569 pvr_fw_irq_clear(pvr_dev);
543 570
544 err = pvr_power_fw_enable(pvr_dev);571 err = pvr_power_fw_enable(pvr_dev, false);
545 }572 }
546 573
547 if (err && hard_reset)574 if (err && hard_reset)
drivers/gpu/drm/radeon/si_dpm.c+3−1
@@ -2915,9 +2915,11 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, · 2914 unmodified lines
2915 if (rdev->family == CHIP_HAINAN) {2915 if (rdev->family == CHIP_HAINAN) {
2916 if ((rdev->pdev->revision == 0x81) ||2916 if ((rdev->pdev->revision == 0x81) ||
2917 (rdev->pdev->revision == 0xC3) ||2917 (rdev->pdev->revision == 0xC3) ||
2918 (rdev->pdev->device == 0x6660) ||
2918 (rdev->pdev->device == 0x6664) ||2919 (rdev->pdev->device == 0x6664) ||
2919 (rdev->pdev->device == 0x6665) ||2920 (rdev->pdev->device == 0x6665) ||
2920 (rdev->pdev->device == 0x6667)) {2921 (rdev->pdev->device == 0x6667) ||
2922 (rdev->pdev->device == 0x666F)) {
2921 max_sclk = 75000;2923 max_sclk = 75000;
2922 }2924 }
2923 if ((rdev->pdev->revision == 0xC3) ||2925 if ((rdev->pdev->revision == 0xC3) ||
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h+57−36
@@ -96,12 +96,17 @@ struct vmwgfx_hash_item { · 95 unmodified lines
96 96
97struct vmw_res_func;97struct vmw_res_func;
98 98
99struct vmw_bo;
100struct vmw_bo;
101struct vmw_resource_dirty;
102
99/**103/**
100 * struct vmw-resource - base class for hardware resources104 * struct vmw_resource - base class for hardware resources
101 *105 *
102 * @kref: For refcounting.106 * @kref: For refcounting.
103 * @dev_priv: Pointer to the device private for this resource. Immutable.107 * @dev_priv: Pointer to the device private for this resource. Immutable.
104 * @id: Device id. Protected by @dev_priv::resource_lock.108 * @id: Device id. Protected by @dev_priv::resource_lock.
109 * @used_prio: Priority for this resource.
105 * @guest_memory_size: Guest memory buffer size. Immutable.110 * @guest_memory_size: Guest memory buffer size. Immutable.
106 * @res_dirty: Resource contains data not yet in the guest memory buffer.111 * @res_dirty: Resource contains data not yet in the guest memory buffer.
107 * Protected by resource reserved.112 * Protected by resource reserved.
@@ -117,18 +122,16 @@ struct vmw_res_func; · 9 unmodified lines
117 * pin-count greater than zero. It is not on the resource LRU lists and its122 * pin-count greater than zero. It is not on the resource LRU lists and its
118 * guest memory buffer is pinned. Hence it can't be evicted.123 * guest memory buffer is pinned. Hence it can't be evicted.
119 * @func: Method vtable for this resource. Immutable.124 * @func: Method vtable for this resource. Immutable.
120 * @mob_node; Node for the MOB guest memory rbtree. Protected by125 * @mob_node: Node for the MOB guest memory rbtree. Protected by
121 * @guest_memory_bo reserved.126 * @guest_memory_bo reserved.
122 * @lru_head: List head for the LRU list. Protected by @dev_priv::resource_lock.127 * @lru_head: List head for the LRU list. Protected by @dev_priv::resource_lock.
123 * @binding_head: List head for the context binding list. Protected by128 * @binding_head: List head for the context binding list. Protected by
124 * the @dev_priv::binding_mutex129 * the @dev_priv::binding_mutex
130 * @dirty: resource's dirty tracker
125 * @res_free: The resource destructor.131 * @res_free: The resource destructor.
126 * @hw_destroy: Callback to destroy the resource on the device, as part of132 * @hw_destroy: Callback to destroy the resource on the device, as part of
127 * resource destruction.133 * resource destruction.
128 */134 */
129struct vmw_bo;
130struct vmw_bo;
131struct vmw_resource_dirty;
132struct vmw_resource {135struct vmw_resource {
133 struct kref kref;136 struct kref kref;
134 struct vmw_private *dev_priv;137 struct vmw_private *dev_priv;
@@ -196,8 +199,8 @@ struct vmw_surface_offset; · 61 unmodified lines
196 * @quality_level: Quality level.199 * @quality_level: Quality level.
197 * @autogen_filter: Filter for automatically generated mipmaps.200 * @autogen_filter: Filter for automatically generated mipmaps.
198 * @array_size: Number of array elements for a 1D/2D texture. For cubemap201 * @array_size: Number of array elements for a 1D/2D texture. For cubemap
199 texture number of faces * array_size. This should be 0 for pre202 * texture number of faces * array_size. This should be 0 for pre
200 SM4 device.203 * SM4 device.
201 * @buffer_byte_stride: Buffer byte stride.204 * @buffer_byte_stride: Buffer byte stride.
202 * @num_sizes: Size of @sizes. For GB surface this should always be 1.205 * @num_sizes: Size of @sizes. For GB surface this should always be 1.
203 * @base_size: Surface dimension.206 * @base_size: Surface dimension.
@@ -265,18 +268,24 @@ struct vmw_fifo_state { · 61 unmodified lines
265struct vmw_res_cache_entry {268struct vmw_res_cache_entry {
266 uint32_t handle;269 uint32_t handle;
267 struct vmw_resource *res;270 struct vmw_resource *res;
271 /* private: */
268 void *private;272 void *private;
273 /* public: */
269 unsigned short valid_handle;274 unsigned short valid_handle;
270 unsigned short valid;275 unsigned short valid;
271};276};
272 277
273/**278/**
274 * enum vmw_dma_map_mode - indicate how to perform TTM page dma mappings.279 * enum vmw_dma_map_mode - indicate how to perform TTM page dma mappings.
280 * @vmw_dma_alloc_coherent: Use TTM coherent pages
281 * @vmw_dma_map_populate: Unmap from DMA just after unpopulate
282 * @vmw_dma_map_bind: Unmap from DMA just before unbind
275 */283 */
276enum vmw_dma_map_mode {284enum vmw_dma_map_mode {
277 vmw_dma_alloc_coherent, /* Use TTM coherent pages */285 vmw_dma_alloc_coherent,
278 vmw_dma_map_populate, /* Unmap from DMA just after unpopulate */286 vmw_dma_map_populate,
279 vmw_dma_map_bind, /* Unmap from DMA just before unbind */287 vmw_dma_map_bind,
288 /* private: */
280 vmw_dma_map_max289 vmw_dma_map_max
281};290};
282 291
@@ -284,8 +293,11 @@ enum vmw_dma_map_mode { · 1 unmodified line
284 * struct vmw_sg_table - Scatter/gather table for binding, with additional293 * struct vmw_sg_table - Scatter/gather table for binding, with additional
285 * device-specific information.294 * device-specific information.
286 *295 *
296 * @mode: which page mapping mode to use
297 * @pages: Array of page pointers to the pages.
298 * @addrs: DMA addresses to the pages if coherent pages are used.
287 * @sgt: Pointer to a struct sg_table with binding information299 * @sgt: Pointer to a struct sg_table with binding information
288 * @num_regions: Number of regions with device-address contiguous pages300 * @num_pages: Number of @pages
289 */301 */
290struct vmw_sg_table {302struct vmw_sg_table {
291 enum vmw_dma_map_mode mode;303 enum vmw_dma_map_mode mode;
@@ -353,6 +365,7 @@ struct vmw_ctx_validation_info; · 61 unmodified lines
353 * than from user-space365 * than from user-space
354 * @fp: If @kernel is false, points to the file of the client. Otherwise366 * @fp: If @kernel is false, points to the file of the client. Otherwise
355 * NULL367 * NULL
368 * @filp: DRM state for this file
356 * @cmd_bounce: Command bounce buffer used for command validation before369 * @cmd_bounce: Command bounce buffer used for command validation before
357 * copying to fifo space370 * copying to fifo space
358 * @cmd_bounce_size: Current command bounce buffer size371 * @cmd_bounce_size: Current command bounce buffer size
@@ -729,7 +742,7 @@ extern void vmw_svga_disable(struct vmw_private *dev_priv); · 370 unmodified lines
729bool vmwgfx_supported(struct vmw_private *vmw);742bool vmwgfx_supported(struct vmw_private *vmw);
730 743
731 744
732/**745/*
733 * GMR utilities - vmwgfx_gmr.c746 * GMR utilities - vmwgfx_gmr.c
734 */747 */
735 748
@@ -739,7 +752,7 @@ extern int vmw_gmr_bind(struct vmw_private *dev_priv, · 3 unmodified lines
739 int gmr_id);752 int gmr_id);
740extern void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id);753extern void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id);
741 754
742/**755/*
743 * User handles756 * User handles
744 */757 */
745struct vmw_user_object {758struct vmw_user_object {
@@ -759,7 +772,7 @@ void *vmw_user_object_map_size(struct vmw_user_object *uo, size_t size); · 13 unmodified lines
759void vmw_user_object_unmap(struct vmw_user_object *uo);772void vmw_user_object_unmap(struct vmw_user_object *uo);
760bool vmw_user_object_is_mapped(struct vmw_user_object *uo);773bool vmw_user_object_is_mapped(struct vmw_user_object *uo);
761 774
762/**775/*
763 * Resource utilities - vmwgfx_resource.c776 * Resource utilities - vmwgfx_resource.c
764 */777 */
765struct vmw_user_resource_conv;778struct vmw_user_resource_conv;
@@ -819,7 +832,7 @@ static inline bool vmw_resource_mob_attached(const struct vmw_resource *res) · 53 unmodified lines
819 return !RB_EMPTY_NODE(&res->mob_node);832 return !RB_EMPTY_NODE(&res->mob_node);
820}833}
821 834
822/**835/*
823 * GEM related functionality - vmwgfx_gem.c836 * GEM related functionality - vmwgfx_gem.c
824 */837 */
825struct vmw_bo_params;838struct vmw_bo_params;
@@ -833,7 +846,7 @@ extern int vmw_gem_object_create_ioctl(struct drm_device *dev, void *data, · 7 unmodified lines
833 struct drm_file *filp);846 struct drm_file *filp);
834extern void vmw_debugfs_gem_init(struct vmw_private *vdev);847extern void vmw_debugfs_gem_init(struct vmw_private *vdev);
835 848
836/**849/*
837 * Misc Ioctl functionality - vmwgfx_ioctl.c850 * Misc Ioctl functionality - vmwgfx_ioctl.c
838 */851 */
839 852
@@ -846,7 +859,7 @@ extern int vmw_present_ioctl(struct drm_device *dev, void *data, · 6 unmodified lines
846extern int vmw_present_readback_ioctl(struct drm_device *dev, void *data,859extern int vmw_present_readback_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file_priv);860 struct drm_file *file_priv);
848 861
849/**862/*
850 * Fifo utilities - vmwgfx_fifo.c863 * Fifo utilities - vmwgfx_fifo.c
851 */864 */
852 865
@@ -880,9 +893,11 @@ extern int vmw_cmd_flush(struct vmw_private *dev_priv, · 27 unmodified lines
880 893
881 894
882/**895/**
883 * vmw_fifo_caps - Returns the capabilities of the FIFO command896 * vmw_fifo_caps - Get the capabilities of the FIFO command
884 * queue or 0 if fifo memory isn't present.897 * queue or 0 if fifo memory isn't present.
885 * @dev_priv: The device private context898 * @dev_priv: The device private context
899 *
900 * Returns: capabilities of the FIFO command or %0 if fifo memory not present
886 */901 */
887static inline uint32_t vmw_fifo_caps(const struct vmw_private *dev_priv)902static inline uint32_t vmw_fifo_caps(const struct vmw_private *dev_priv)
888{903{
@@ -893,9 +908,11 @@ static inline uint32_t vmw_fifo_caps(const struct vmw_private *dev_priv) · 4 unmodified lines
893 908
894 909
895/**910/**
896 * vmw_is_cursor_bypass3_enabled - Returns TRUE iff Cursor Bypass 3911 * vmw_is_cursor_bypass3_enabled - check Cursor Bypass 3 enabled setting
897 * is enabled in the FIFO.912 * in the FIFO.
898 * @dev_priv: The device private context913 * @dev_priv: The device private context
914 *
915 * Returns: %true iff Cursor Bypass 3 is enabled in the FIFO
899 */916 */
900static inline bool917static inline bool
901vmw_is_cursor_bypass3_enabled(const struct vmw_private *dev_priv)918vmw_is_cursor_bypass3_enabled(const struct vmw_private *dev_priv)
@@ -903,7 +920,7 @@ vmw_is_cursor_bypass3_enabled(const struct vmw_private *dev_priv) · 1 unmodified line
903 return (vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_CURSOR_BYPASS_3) != 0;920 return (vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_CURSOR_BYPASS_3) != 0;
904}921}
905 922
906/**923/*
907 * TTM buffer object driver - vmwgfx_ttm_buffer.c924 * TTM buffer object driver - vmwgfx_ttm_buffer.c
908 */925 */
909 926
@@ -927,7 +944,7 @@ extern void vmw_piter_start(struct vmw_piter *viter, · 17 unmodified lines
927 *944 *
928 * @viter: Pointer to the iterator to advance.945 * @viter: Pointer to the iterator to advance.
929 *946 *
930 * Returns false if past the list of pages, true otherwise.947 * Returns: false if past the list of pages, true otherwise.
931 */948 */
932static inline bool vmw_piter_next(struct vmw_piter *viter)949static inline bool vmw_piter_next(struct vmw_piter *viter)
933{950{
@@ -939,7 +956,7 @@ static inline bool vmw_piter_next(struct vmw_piter *viter) · 5 unmodified lines
939 *956 *
940 * @viter: Pointer to the iterator957 * @viter: Pointer to the iterator
941 *958 *
942 * Returns the DMA address of the page pointed to by @viter.959 * Returns: the DMA address of the page pointed to by @viter.
943 */960 */
944static inline dma_addr_t vmw_piter_dma_addr(struct vmw_piter *viter)961static inline dma_addr_t vmw_piter_dma_addr(struct vmw_piter *viter)
945{962{
@@ -951,14 +968,14 @@ static inline dma_addr_t vmw_piter_dma_addr(struct vmw_piter *viter) · 5 unmodified lines
951 *968 *
952 * @viter: Pointer to the iterator969 * @viter: Pointer to the iterator
953 *970 *
954 * Returns the DMA address of the page pointed to by @viter.971 * Returns: the DMA address of the page pointed to by @viter.
955 */972 */
956static inline struct page *vmw_piter_page(struct vmw_piter *viter)973static inline struct page *vmw_piter_page(struct vmw_piter *viter)
957{974{
958 return viter->pages[viter->i];975 return viter->pages[viter->i];
959}976}
960 977
961/**978/*
962 * Command submission - vmwgfx_execbuf.c979 * Command submission - vmwgfx_execbuf.c
963 */980 */
964 981
@@ -993,7 +1010,7 @@ extern int vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, · 28 unmodified lines
993 int32_t out_fence_fd);1010 int32_t out_fence_fd);
994bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd);1011bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd);
995 1012
996/**1013/*
997 * IRQs and wating - vmwgfx_irq.c1014 * IRQs and wating - vmwgfx_irq.c
998 */1015 */
999 1016
@@ -1016,7 +1033,7 @@ bool vmw_generic_waiter_add(struct vmw_private *dev_priv, u32 flag, · 16 unmodified lines
1016bool vmw_generic_waiter_remove(struct vmw_private *dev_priv,1033bool vmw_generic_waiter_remove(struct vmw_private *dev_priv,
1017 u32 flag, int *waiter_count);1034 u32 flag, int *waiter_count);
1018 1035
1019/**1036/*
1020 * Kernel modesetting - vmwgfx_kms.c1037 * Kernel modesetting - vmwgfx_kms.c
1021 */1038 */
1022 1039
@@ -1048,7 +1065,7 @@ extern int vmw_resource_pin(struct vmw_resource *res, bool interruptible); · 25 unmodified lines
1048extern void vmw_resource_unpin(struct vmw_resource *res);1065extern void vmw_resource_unpin(struct vmw_resource *res);
1049extern enum vmw_res_type vmw_res_type(const struct vmw_resource *res);1066extern enum vmw_res_type vmw_res_type(const struct vmw_resource *res);
1050 1067
1051/**1068/*
1052 * Overlay control - vmwgfx_overlay.c1069 * Overlay control - vmwgfx_overlay.c
1053 */1070 */
1054 1071
@@ -1063,20 +1080,20 @@ int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id); · 8 unmodified lines
1063int vmw_overlay_num_overlays(struct vmw_private *dev_priv);1080int vmw_overlay_num_overlays(struct vmw_private *dev_priv);
1064int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv);1081int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv);
1065 1082
1066/**1083/*
1067 * GMR Id manager1084 * GMR Id manager
1068 */1085 */
1069 1086
1070int vmw_gmrid_man_init(struct vmw_private *dev_priv, int type);1087int vmw_gmrid_man_init(struct vmw_private *dev_priv, int type);
1071void vmw_gmrid_man_fini(struct vmw_private *dev_priv, int type);1088void vmw_gmrid_man_fini(struct vmw_private *dev_priv, int type);
1072 1089
1073/**1090/*
1074 * System memory manager1091 * System memory manager
1075 */1092 */
1076int vmw_sys_man_init(struct vmw_private *dev_priv);1093int vmw_sys_man_init(struct vmw_private *dev_priv);
1077void vmw_sys_man_fini(struct vmw_private *dev_priv);1094void vmw_sys_man_fini(struct vmw_private *dev_priv);
1078 1095
1079/**1096/*
1080 * Prime - vmwgfx_prime.c1097 * Prime - vmwgfx_prime.c
1081 */1098 */
1082 1099
@@ -1292,7 +1309,7 @@ extern void vmw_cmdbuf_irqthread(struct vmw_cmdbuf_man *man); · 209 unmodified lines
1292 * @line: The current line of the blit.1309 * @line: The current line of the blit.
1293 * @line_offset: Offset of the current line segment.1310 * @line_offset: Offset of the current line segment.
1294 * @cpp: Bytes per pixel (granularity information).1311 * @cpp: Bytes per pixel (granularity information).
1295 * @memcpy: Which memcpy function to use.1312 * @do_cpy: Which memcpy function to use.
1296 */1313 */
1297struct vmw_diff_cpy {1314struct vmw_diff_cpy {
1298 struct drm_rect rect;1315 struct drm_rect rect;
@@ -1380,13 +1397,14 @@ vm_fault_t vmw_bo_vm_mkwrite(struct vm_fault *vmf); · 81 unmodified lines
1380 1397
1381/**1398/**
1382 * VMW_DEBUG_KMS - Debug output for kernel mode-setting1399 * VMW_DEBUG_KMS - Debug output for kernel mode-setting
1400 * @fmt: format string for the args
1383 *1401 *
1384 * This macro is for debugging vmwgfx mode-setting code.1402 * This macro is for debugging vmwgfx mode-setting code.
1385 */1403 */
1386#define VMW_DEBUG_KMS(fmt, ...) \1404#define VMW_DEBUG_KMS(fmt, ...) \
1387 DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)1405 DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)
1388 1406
1389/**1407/*
1390 * Inline helper functions1408 * Inline helper functions
1391 */1409 */
1392 1410
@@ -1417,11 +1435,13 @@ static inline void vmw_fifo_resource_dec(struct vmw_private *dev_priv) · 24 unmodified lines
1417 1435
1418/**1436/**
1419 * vmw_fifo_mem_read - Perform a MMIO read from the fifo memory1437 * vmw_fifo_mem_read - Perform a MMIO read from the fifo memory
1420 *1438 * @vmw: The device private structure
1421 * @fifo_reg: The fifo register to read from1439 * @fifo_reg: The fifo register to read from
1422 *1440 *
1423 * This function is intended to be equivalent to ioread32() on1441 * This function is intended to be equivalent to ioread32() on
1424 * memremap'd memory, but without byteswapping.1442 * memremap'd memory, but without byteswapping.
1443 *
1444 * Returns: the value read
1425 */1445 */
1426static inline u32 vmw_fifo_mem_read(struct vmw_private *vmw, uint32 fifo_reg)1446static inline u32 vmw_fifo_mem_read(struct vmw_private *vmw, uint32 fifo_reg)
1427{1447{
@@ -1431,8 +1451,9 @@ static inline u32 vmw_fifo_mem_read(struct vmw_private *vmw, uint32 fifo_reg) · 3 unmodified lines
1431 1451
1432/**1452/**
1433 * vmw_fifo_mem_write - Perform a MMIO write to volatile memory1453 * vmw_fifo_mem_write - Perform a MMIO write to volatile memory
1434 *1454 * @vmw: The device private structure
1435 * @addr: The fifo register to write to1455 * @fifo_reg: The fifo register to write to
1456 * @value: The value to write
1436 *1457 *
1437 * This function is intended to be equivalent to iowrite32 on1458 * This function is intended to be equivalent to iowrite32 on
1438 * memremap'd memory, but without byteswapping.1459 * memremap'd memory, but without byteswapping.
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c+2−1
@@ -771,7 +771,8 @@ err_out: · 770 unmodified lines
771 ret = vmw_bo_dirty_add(bo);771 ret = vmw_bo_dirty_add(bo);
772 if (!ret && surface && surface->res.func->dirty_alloc) {772 if (!ret && surface && surface->res.func->dirty_alloc) {
773 surface->res.coherent = true;773 surface->res.coherent = true;
774 ret = surface->res.func->dirty_alloc(&surface->res);774 if (surface->res.dirty == NULL)
775 ret = surface->res.func->dirty_alloc(&surface->res);
775 }776 }
776 ttm_bo_unreserve(&bo->tbo);777 ttm_bo_unreserve(&bo->tbo);
777 }778 }
drivers/gpu/drm/xe/xe_ggtt.c+4−6
@@ -313,6 +313,8 @@ static void dev_fini_ggtt(void *arg) · 312 unmodified lines
313{313{
314 struct xe_ggtt *ggtt = arg;314 struct xe_ggtt *ggtt = arg;
315 315
316 scoped_guard(mutex, &ggtt->lock)
317 ggtt->flags &= ~XE_GGTT_FLAGS_ONLINE;
316 drain_workqueue(ggtt->wq);318 drain_workqueue(ggtt->wq);
317}319}
318 320
@@ -377,6 +379,7 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt) · 58 unmodified lines
377 if (err)379 if (err)
378 return err;380 return err;
379 381
382 ggtt->flags |= XE_GGTT_FLAGS_ONLINE;
380 err = devm_add_action_or_reset(xe->drm.dev, dev_fini_ggtt, ggtt);383 err = devm_add_action_or_reset(xe->drm.dev, dev_fini_ggtt, ggtt);
381 if (err)384 if (err)
382 return err;385 return err;
@@ -410,13 +413,10 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt) · 27 unmodified lines
410static void ggtt_node_remove(struct xe_ggtt_node *node)413static void ggtt_node_remove(struct xe_ggtt_node *node)
411{414{
412 struct xe_ggtt *ggtt = node->ggtt;415 struct xe_ggtt *ggtt = node->ggtt;
413 struct xe_device *xe = tile_to_xe(ggtt->tile);
414 bool bound;416 bool bound;
415 int idx;
416
417 bound = drm_dev_enter(&xe->drm, &idx);
418 417
419 mutex_lock(&ggtt->lock);418 mutex_lock(&ggtt->lock);
419 bound = ggtt->flags & XE_GGTT_FLAGS_ONLINE;
420 if (bound)420 if (bound)
421 xe_ggtt_clear(ggtt, node->base.start, node->base.size);421 xe_ggtt_clear(ggtt, node->base.start, node->base.size);
422 drm_mm_remove_node(&node->base);422 drm_mm_remove_node(&node->base);
@@ -429,8 +429,6 @@ static void ggtt_node_remove(struct xe_ggtt_node *node) · 6 unmodified lines
429 if (node->invalidate_on_remove)429 if (node->invalidate_on_remove)
430 xe_ggtt_invalidate(ggtt);430 xe_ggtt_invalidate(ggtt);
431 431
432 drm_dev_exit(idx);
433
434free_node:432free_node:
435 xe_ggtt_node_fini(node);433 xe_ggtt_node_fini(node);
436}434}
drivers/gpu/drm/xe/xe_ggtt_types.h+4−1
@@ -28,11 +28,14 @@ struct xe_ggtt { · 27 unmodified lines
28 /** @size: Total usable size of this GGTT */28 /** @size: Total usable size of this GGTT */
29 u64 size;29 u64 size;
30 30
31#define XE_GGTT_FLAGS_64K BIT(0)31#define XE_GGTT_FLAGS_64K BIT(0)
32#define XE_GGTT_FLAGS_ONLINE BIT(1)
32 /**33 /**
33 * @flags: Flags for this GGTT34 * @flags: Flags for this GGTT
34 * Acceptable flags:35 * Acceptable flags:
35 * - %XE_GGTT_FLAGS_64K - if PTE size is 64K. Otherwise, regular is 4K.36 * - %XE_GGTT_FLAGS_64K - if PTE size is 64K. Otherwise, regular is 4K.
37 * - %XE_GGTT_FLAGS_ONLINE - is GGTT online, protected by ggtt->lock
38 * after init
36 */39 */
37 unsigned int flags;40 unsigned int flags;
38 /** @scratch: Internal object allocation used as a scratch page */41 /** @scratch: Internal object allocation used as a scratch page */
drivers/gpu/drm/xe/xe_gt_ccs_mode.c+2−0
@@ -12,6 +12,7 @@ · 11 unmodified lines
12#include "xe_gt_printk.h"12#include "xe_gt_printk.h"
13#include "xe_gt_sysfs.h"13#include "xe_gt_sysfs.h"
14#include "xe_mmio.h"14#include "xe_mmio.h"
15#include "xe_pm.h"
15#include "xe_sriov.h"16#include "xe_sriov.h"
16 17
17static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)18static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
@@ -150,6 +151,7 @@ ccs_mode_store(struct device *kdev, struct device_attribute *attr, · 132 unmodified lines
150 xe_gt_info(gt, "Setting compute mode to %d\n", num_engines);151 xe_gt_info(gt, "Setting compute mode to %d\n", num_engines);
151 gt->ccs_mode = num_engines;152 gt->ccs_mode = num_engines;
152 xe_gt_record_user_engines(gt);153 xe_gt_record_user_engines(gt);
154 guard(xe_pm_runtime)(xe);
153 xe_gt_reset(gt);155 xe_gt_reset(gt);
154 }156 }
155 157
drivers/gpu/drm/xe/xe_guc.c+27−5
@@ -1124,14 +1124,14 @@ static int guc_wait_ucode(struct xe_guc *guc) · 1123 unmodified lines
1124 struct xe_guc_pc *guc_pc = &gt->uc.guc.pc;1124 struct xe_guc_pc *guc_pc = &gt->uc.guc.pc;
1125 u32 before_freq, act_freq, cur_freq;1125 u32 before_freq, act_freq, cur_freq;
1126 u32 status = 0, tries = 0;1126 u32 status = 0, tries = 0;
1127 int load_result, ret;
1127 ktime_t before;1128 ktime_t before;
1128 u64 delta_ms;1129 u64 delta_ms;
1129 int ret;
1130 1130
1131 before_freq = xe_guc_pc_get_act_freq(guc_pc);1131 before_freq = xe_guc_pc_get_act_freq(guc_pc);
1132 before = ktime_get();1132 before = ktime_get();
1133 1133
1134 ret = poll_timeout_us(ret = guc_load_done(gt, &status, &tries), ret,1134 ret = poll_timeout_us(load_result = guc_load_done(gt, &status, &tries), load_result,
1135 10 * USEC_PER_MSEC,1135 10 * USEC_PER_MSEC,
1136 GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false);1136 GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false);
1137 1137
@@ -1139,7 +1139,7 @@ static int guc_wait_ucode(struct xe_guc *guc) · 1 unmodified line
1139 act_freq = xe_guc_pc_get_act_freq(guc_pc);1139 act_freq = xe_guc_pc_get_act_freq(guc_pc);
1140 cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc);1140 cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc);
1141 1141
1142 if (ret) {1142 if (ret || load_result <= 0) {
1143 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n",1143 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n",
1144 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc),1144 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc),
1145 xe_guc_pc_get_cur_freq_fw(guc_pc));1145 xe_guc_pc_get_cur_freq_fw(guc_pc));
@@ -1347,15 +1347,37 @@ int xe_guc_enable_communication(struct xe_guc *guc) · 201 unmodified lines
1347 return 0;1347 return 0;
1348}1348}
1349 1349
1350int xe_guc_suspend(struct xe_guc *guc)1350/**
1351 * xe_guc_softreset() - Soft reset GuC
1352 * @guc: The GuC object
1353 *
1354 * Send soft reset command to GuC through mmio send.
1355 *
1356 * Return: 0 if success, otherwise error code
1357 */
1358int xe_guc_softreset(struct xe_guc *guc)
1351{1359{
1352 struct xe_gt *gt = guc_to_gt(guc);
1353 u32 action[] = {1360 u32 action[] = {
1354 XE_GUC_ACTION_CLIENT_SOFT_RESET,1361 XE_GUC_ACTION_CLIENT_SOFT_RESET,
1355 };1362 };
1356 int ret;1363 int ret;
1357 1364
1365 if (!xe_uc_fw_is_running(&guc->fw))
1366 return 0;
1367
1358 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));1368 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
1369 if (ret)
1370 return ret;
1371
1372 return 0;
1373}
1374
1375int xe_guc_suspend(struct xe_guc *guc)
1376{
1377 struct xe_gt *gt = guc_to_gt(guc);
1378 int ret;
1379
1380 ret = xe_guc_softreset(guc);
1359 if (ret) {1381 if (ret) {
1360 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret));1382 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret));
1361 return ret;1383 return ret;
drivers/gpu/drm/xe/xe_guc.h+1−0
@@ -44,6 +44,7 @@ int xe_guc_opt_in_features_enable(struct xe_guc *guc); · 43 unmodified lines
44void xe_guc_runtime_suspend(struct xe_guc *guc);44void xe_guc_runtime_suspend(struct xe_guc *guc);
45void xe_guc_runtime_resume(struct xe_guc *guc);45void xe_guc_runtime_resume(struct xe_guc *guc);
46int xe_guc_suspend(struct xe_guc *guc);46int xe_guc_suspend(struct xe_guc *guc);
47int xe_guc_softreset(struct xe_guc *guc);
47void xe_guc_notify(struct xe_guc *guc);48void xe_guc_notify(struct xe_guc *guc);
48int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);49int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
49int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);50int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
drivers/gpu/drm/xe/xe_guc_ct.c+1−0
@@ -345,6 +345,7 @@ static void guc_action_disable_ct(void *arg) · 344 unmodified lines
345{345{
346 struct xe_guc_ct *ct = arg;346 struct xe_guc_ct *ct = arg;
347 347
348 xe_guc_ct_stop(ct);
348 guc_ct_change_state(ct, XE_GUC_CT_STATE_DISABLED);349 guc_ct_change_state(ct, XE_GUC_CT_STATE_DISABLED);
349}350}
350 351
drivers/gpu/drm/xe/xe_guc_submit.c+61−25
@@ -48,6 +48,8 @@ · 47 unmodified lines
48 48
49#define XE_GUC_EXEC_QUEUE_CGP_CONTEXT_ERROR_LEN 649#define XE_GUC_EXEC_QUEUE_CGP_CONTEXT_ERROR_LEN 6
50 50
51static int guc_submit_reset_prepare(struct xe_guc *guc);
52
51static struct xe_guc *53static struct xe_guc *
52exec_queue_to_guc(struct xe_exec_queue *q)54exec_queue_to_guc(struct xe_exec_queue *q)
53{55{
@@ -239,7 +241,7 @@ static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q) · 185 unmodified lines
239 EXEC_QUEUE_STATE_BANNED));241 EXEC_QUEUE_STATE_BANNED));
240}242}
241 243
242static void guc_submit_fini(struct drm_device *drm, void *arg)244static void guc_submit_sw_fini(struct drm_device *drm, void *arg)
243{245{
244 struct xe_guc *guc = arg;246 struct xe_guc *guc = arg;
245 struct xe_device *xe = guc_to_xe(guc);247 struct xe_device *xe = guc_to_xe(guc);
@@ -257,6 +259,19 @@ static void guc_submit_fini(struct drm_device *drm, void *arg) · 11 unmodified lines
257 xa_destroy(&guc->submission_state.exec_queue_lookup);259 xa_destroy(&guc->submission_state.exec_queue_lookup);
258}260}
259 261
262static void guc_submit_fini(void *arg)
263{
264 struct xe_guc *guc = arg;
265
266 /* Forcefully kill any remaining exec queues */
267 xe_guc_ct_stop(&guc->ct);
268 guc_submit_reset_prepare(guc);
269 xe_guc_softreset(guc);
270 xe_guc_submit_stop(guc);
271 xe_uc_fw_sanitize(&guc->fw);
272 xe_guc_submit_pause_abort(guc);
273}
274
260static void guc_submit_wedged_fini(void *arg)275static void guc_submit_wedged_fini(void *arg)
261{276{
262 struct xe_guc *guc = arg;277 struct xe_guc *guc = arg;
@@ -326,7 +341,11 @@ int xe_guc_submit_init(struct xe_guc *guc, unsigned int num_ids) · 63 unmodified lines
326 341
327 guc->submission_state.initialized = true;342 guc->submission_state.initialized = true;
328 343
329 return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc);344 err = drmm_add_action_or_reset(&xe->drm, guc_submit_sw_fini, guc);
345 if (err)
346 return err;
347
348 return devm_add_action_or_reset(xe->drm.dev, guc_submit_fini, guc);
330}349}
331 350
332/*351/*
@@ -1252,6 +1271,7 @@ static void disable_scheduling_deregister(struct xe_guc *guc, · 919 unmodified lines
1252 */1271 */
1253void xe_guc_submit_wedge(struct xe_guc *guc)1272void xe_guc_submit_wedge(struct xe_guc *guc)
1254{1273{
1274 struct xe_device *xe = guc_to_xe(guc);
1255 struct xe_gt *gt = guc_to_gt(guc);1275 struct xe_gt *gt = guc_to_gt(guc);
1256 struct xe_exec_queue *q;1276 struct xe_exec_queue *q;
1257 unsigned long index;1277 unsigned long index;
@@ -1266,20 +1286,28 @@ void xe_guc_submit_wedge(struct xe_guc *guc) · 8 unmodified lines
1266 if (!guc->submission_state.initialized)1286 if (!guc->submission_state.initialized)
1267 return;1287 return;
1268 1288
1269 err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,1289 if (xe->wedged.mode == 2) {
1270 guc_submit_wedged_fini, guc);1290 err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
1271 if (err) {1291 guc_submit_wedged_fini, guc);
1272 xe_gt_err(gt, "Failed to register clean-up in wedged.mode=%s; "1292 if (err) {
1273 "Although device is wedged.\n",1293 xe_gt_err(gt, "Failed to register clean-up on wedged.mode=2; "
1274 xe_wedged_mode_to_string(XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET));1294 "Although device is wedged.\n");
1275 return;1295 return;
1276 }1296 }
1277 1297
1278 mutex_lock(&guc->submission_state.lock);1298 mutex_lock(&guc->submission_state.lock);
1279 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)1299 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1280 if (xe_exec_queue_get_unless_zero(q))1300 if (xe_exec_queue_get_unless_zero(q))
1281 set_exec_queue_wedged(q);1301 set_exec_queue_wedged(q);
1282 mutex_unlock(&guc->submission_state.lock);1302 mutex_unlock(&guc->submission_state.lock);
1303 } else {
1304 /* Forcefully kill any remaining exec queues, signal fences */
1305 guc_submit_reset_prepare(guc);
1306 xe_guc_submit_stop(guc);
1307 xe_guc_softreset(guc);
1308 xe_uc_fw_sanitize(&guc->fw);
1309 xe_guc_submit_pause_abort(guc);
1310 }
1283}1311}
1284 1312
1285static bool guc_submit_hint_wedged(struct xe_guc *guc)1313static bool guc_submit_hint_wedged(struct xe_guc *guc)
@@ -2230,6 +2258,7 @@ static const struct xe_exec_queue_ops guc_exec_queue_ops = { · 944 unmodified lines
2230static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)2258static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)
2231{2259{
2232 struct xe_gpu_scheduler *sched = &q->guc->sched;2260 struct xe_gpu_scheduler *sched = &q->guc->sched;
2261 bool do_destroy = false;
2233 2262
2234 /* Stop scheduling + flush any DRM scheduler operations */2263 /* Stop scheduling + flush any DRM scheduler operations */
2235 xe_sched_submission_stop(sched);2264 xe_sched_submission_stop(sched);
@@ -2237,7 +2266,7 @@ static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) · 1 unmodified line
2237 /* Clean up lost G2H + reset engine state */2266 /* Clean up lost G2H + reset engine state */
2238 if (exec_queue_registered(q)) {2267 if (exec_queue_registered(q)) {
2239 if (exec_queue_destroyed(q))2268 if (exec_queue_destroyed(q))
2240 __guc_exec_queue_destroy(guc, q);2269 do_destroy = true;
2241 }2270 }
2242 if (q->guc->suspend_pending) {2271 if (q->guc->suspend_pending) {
2243 set_exec_queue_suspended(q);2272 set_exec_queue_suspended(q);
@@ -2273,18 +2302,15 @@ static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) · 29 unmodified lines
2273 xe_guc_exec_queue_trigger_cleanup(q);2302 xe_guc_exec_queue_trigger_cleanup(q);
2274 }2303 }
2275 }2304 }
2305
2306 if (do_destroy)
2307 __guc_exec_queue_destroy(guc, q);
2276}2308}
2277 2309
2278int xe_guc_submit_reset_prepare(struct xe_guc *guc)2310static int guc_submit_reset_prepare(struct xe_guc *guc)
2279{2311{
2280 int ret;2312 int ret;
2281 2313
2282 if (xe_gt_WARN_ON(guc_to_gt(guc), vf_recovery(guc)))
2283 return 0;
2284
2285 if (!guc->submission_state.initialized)
2286 return 0;
2287
2288 /*2314 /*
2289 * Using an atomic here rather than submission_state.lock as this2315 * Using an atomic here rather than submission_state.lock as this
2290 * function can be called while holding the CT lock (engine reset2316 * function can be called while holding the CT lock (engine reset
@@ -2299,6 +2325,17 @@ int xe_guc_submit_reset_prepare(struct xe_guc *guc) · 8 unmodified lines
2299 return ret;2325 return ret;
2300}2326}
2301 2327
2328int xe_guc_submit_reset_prepare(struct xe_guc *guc)
2329{
2330 if (xe_gt_WARN_ON(guc_to_gt(guc), vf_recovery(guc)))
2331 return 0;
2332
2333 if (!guc->submission_state.initialized)
2334 return 0;
2335
2336 return guc_submit_reset_prepare(guc);
2337}
2338
2302void xe_guc_submit_reset_wait(struct xe_guc *guc)2339void xe_guc_submit_reset_wait(struct xe_guc *guc)
2303{2340{
2304 wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) ||2341 wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) ||
@@ -2695,8 +2732,7 @@ void xe_guc_submit_pause_abort(struct xe_guc *guc) · 390 unmodified lines
2695 continue;2732 continue;
2696 2733
2697 xe_sched_submission_start(sched);2734 xe_sched_submission_start(sched);
2698 if (exec_queue_killed_or_banned_or_wedged(q))2735 guc_exec_queue_kill(q);
2699 xe_guc_exec_queue_trigger_cleanup(q);
2700 }2736 }
2701 mutex_unlock(&guc->submission_state.lock);2737 mutex_unlock(&guc->submission_state.lock);
2702}2738}
drivers/gpu/drm/xe/xe_lrc.c+2−2
@@ -2413,14 +2413,14 @@ static int get_ctx_timestamp(struct xe_lrc *lrc, u32 engine_id, u64 *reg_ctx_ts) · 2412 unmodified lines
2413 * @lrc: Pointer to the lrc.2413 * @lrc: Pointer to the lrc.
2414 *2414 *
2415 * Return latest ctx timestamp. With support for active contexts, the2415 * Return latest ctx timestamp. With support for active contexts, the
2416 * calculation may bb slightly racy, so follow a read-again logic to ensure that2416 * calculation may be slightly racy, so follow a read-again logic to ensure that
2417 * the context is still active before returning the right timestamp.2417 * the context is still active before returning the right timestamp.
2418 *2418 *
2419 * Returns: New ctx timestamp value2419 * Returns: New ctx timestamp value
2420 */2420 */
2421u64 xe_lrc_timestamp(struct xe_lrc *lrc)2421u64 xe_lrc_timestamp(struct xe_lrc *lrc)
2422{2422{
2423 u64 lrc_ts, reg_ts, new_ts;2423 u64 lrc_ts, reg_ts, new_ts = lrc->ctx_timestamp;
2424 u32 engine_id;2424 u32 engine_id;
2425 2425
2426 lrc_ts = xe_lrc_ctx_timestamp(lrc);2426 lrc_ts = xe_lrc_ctx_timestamp(lrc);
drivers/gpu/drm/xe/xe_oa.c+5−2
@@ -543,8 +543,7 @@ static ssize_t xe_oa_read(struct file *file, char __user *buf, · 542 unmodified lines
543 size_t offset = 0;543 size_t offset = 0;
544 int ret;544 int ret;
545 545
546 /* Can't read from disabled streams */546 if (!stream->sample)
547 if (!stream->enabled || !stream->sample)
548 return -EINVAL;547 return -EINVAL;
549 548
550 if (!(file->f_flags & O_NONBLOCK)) {549 if (!(file->f_flags & O_NONBLOCK)) {
@@ -1460,6 +1459,10 @@ static void xe_oa_stream_disable(struct xe_oa_stream *stream) · 909 unmodified lines
1460 1459
1461 if (stream->sample)1460 if (stream->sample)
1462 hrtimer_cancel(&stream->poll_check_timer);1461 hrtimer_cancel(&stream->poll_check_timer);
1462
1463 /* Update stream->oa_buffer.tail to allow any final reports to be read */
1464 if (xe_oa_buffer_check_unlocked(stream))
1465 wake_up(&stream->poll_wq);
1463}1466}
1464 1467
1465static int xe_oa_enable_preempt_timeslice(struct xe_oa_stream *stream)1468static int xe_oa_enable_preempt_timeslice(struct xe_oa_stream *stream)
drivers/gpu/drm/xe/xe_pt.c+29−9
@@ -1655,14 +1655,35 @@ static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset, · 1654 unmodified lines
1655 XE_WARN_ON(!level);1655 XE_WARN_ON(!level);
1656 /* Check for leaf node */1656 /* Check for leaf node */
1657 if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&1657 if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&
1658 (!xe_child->base.children || !xe_child->base.children[first])) {1658 xe_child->level <= MAX_HUGEPTE_LEVEL) {
1659 struct iosys_map *leaf_map = &xe_child->bo->vmap;1659 struct iosys_map *leaf_map = &xe_child->bo->vmap;
1660 pgoff_t count = xe_pt_num_entries(addr, next, xe_child->level, walk);1660 pgoff_t count = xe_pt_num_entries(addr, next, xe_child->level, walk);
1661 1661
1662 for (pgoff_t i = 0; i < count; i++) {1662 for (pgoff_t i = 0; i < count; i++) {
1663 u64 pte = xe_map_rd(xe, leaf_map, (first + i) * sizeof(u64), u64);1663 u64 pte;
1664 int ret;1664 int ret;
1665 1665
1666 /*
1667 * If not a leaf pt, skip unless non-leaf pt is interleaved between
1668 * leaf ptes which causes the page walk to skip over the child leaves
1669 */
1670 if (xe_child->base.children && xe_child->base.children[first + i]) {
1671 u64 pt_size = 1ULL << walk->shifts[xe_child->level];
1672 bool edge_pt = (i == 0 && !IS_ALIGNED(addr, pt_size)) ||
1673 (i == count - 1 && !IS_ALIGNED(next, pt_size));
1674
1675 if (!edge_pt) {
1676 xe_page_reclaim_list_abort(xe_walk->tile->primary_gt,
1677 xe_walk->prl,
1678 "PT is skipped by walk at level=%u offset=%lu",
1679 xe_child->level, first + i);
1680 break;
1681 }
1682 continue;
1683 }
1684
1685 pte = xe_map_rd(xe, leaf_map, (first + i) * sizeof(u64), u64);
1686
1666 /*1687 /*
1667 * In rare scenarios, pte may not be written yet due to racy conditions.1688 * In rare scenarios, pte may not be written yet due to racy conditions.
1668 * In such cases, invalidate the PRL and fallback to full PPC invalidation.1689 * In such cases, invalidate the PRL and fallback to full PPC invalidation.
@@ -1674,9 +1695,8 @@ static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset, · 5 unmodified lines
1674 }1695 }
1675 1696
1676 /* Ensure it is a defined page */1697 /* Ensure it is a defined page */
1677 xe_tile_assert(xe_walk->tile,1698 xe_tile_assert(xe_walk->tile, xe_child->level == 0 ||
1678 xe_child->level == 0 ||1699 (pte & (XE_PDE_PS_2M | XE_PDPE_PS_1G)));
1679 (pte & (XE_PTE_PS64 | XE_PDE_PS_2M | XE_PDPE_PS_1G)));
1680 1700
1681 /* An entry should be added for 64KB but contigious 4K have XE_PTE_PS64 */1701 /* An entry should be added for 64KB but contigious 4K have XE_PTE_PS64 */
1682 if (pte & XE_PTE_PS64)1702 if (pte & XE_PTE_PS64)
@@ -1701,11 +1721,11 @@ static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset, · 18 unmodified lines
1701 killed = xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk);1721 killed = xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk);
1702 1722
1703 /*1723 /*
1704 * Verify PRL is active and if entry is not a leaf pte (base.children conditions),1724 * Verify if any PTE are potentially dropped at non-leaf levels, either from being
1705 * there is a potential need to invalidate the PRL if any PTE (num_live) are dropped.1725 * killed or the page walk covers the region.
1706 */1726 */
1707 if (xe_walk->prl && level > 1 && xe_child->num_live &&1727 if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&
1708 xe_child->base.children && xe_child->base.children[first]) {1728 xe_child->level > MAX_HUGEPTE_LEVEL && xe_child->num_live) {
1709 bool covered = xe_pt_covers(addr, next, xe_child->level, &xe_walk->base);1729 bool covered = xe_pt_covers(addr, next, xe_child->level, &xe_walk->base);
1710 1730
1711 /*1731 /*