Merge branch 'pci/endpoint'

- Convert PCI device data so pci-epf-test works correctly on big-endian endpoint systems (Niklas Cassel) - Add BAR_RESIZABLE type to endpoint framework (Niklas Cassel) - Add pci_epc_bar_size_to_rebar_cap() to convert a size to the Resizable BAR Capability so endpoint drivers can configure what the Capability register advertises (Niklas Cassel) - Add DWC core support for EPF drivers to set BAR_RESIZABLE type and size via dw_pcie_ep_set_bar() (Niklas Cassel) - Describe TI AM65x (keystone) BARs 2 and 5 as Resizable, not Fixed (Niklas Cassel) - Reduce TI AM65x (keystone) BAR alignment requirement from 1MB to 64KB (Niklas Cassel) - Describe Rockchip rk3568 and rk3588 BARs as Resizable, not Fixed (Niklas Cassel) - Drop unused devm_pci_epc_destroy() (Zijun Hu) - Fix pci-epf-test double free that causes an oops if the host reboots and PERST# deassertion restarts endpoint BAR allocation (Christian Bruel) - Drop dw_pcie_ep_find_ext_capability() and use dw_pcie_find_ext_capability() instead (Niklas Cassel) * pci/endpoint: PCI: dwc: ep: Remove superfluous function dw_pcie_ep_find_ext_capability() PCI: endpoint: pci-epf-test: Fix double free that causes kernel to oops PCI: endpoint: Remove unused devm_pci_epc_destroy() PCI: dw-rockchip: Describe Resizable BARs as Resizable BARs PCI: keystone: Specify correct alignment requirement PCI: keystone: Describe Resizable BARs as Resizable BARs PCI: dwc: ep: Allow EPF drivers to configure the size of Resizable BARs PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability() PCI: endpoint: Add pci_epc_bar_size_to_rebar_cap() PCI: endpoint: Allow EPF drivers to configure the size of Resizable BARs PCI: endpoint: pci-epf-test: Handle endianness properly

Bjorn Helgaas committed 1 year ago

Commit a113afb2 parents b810fec a60a7088 files · +301 −132Browse files

Unified · Split

8 files

Documentation/PCI/endpoint/pci-endpoint.rst +3 −4
drivers/pci/controller/dwc/pci-keystone.c +3 −3
drivers/pci/controller/dwc/pcie-designware-ep.c +169 −35
drivers/pci/controller/dwc/pcie-dw-rockchip.c +11 −11
drivers/pci/endpoint/functions/pci-epf-test.c +75 −53
drivers/pci/endpoint/pci-epc-core.c +31 −25
drivers/pci/endpoint/pci-epf-core.c +4 −0
include/linux/pci-epc.h +5 −1

Documentation/PCI/endpoint/pci-endpoint.rst+3−4

@@ -57,11 +57,10 @@ by the PCI controller driver. · 56 unmodified lines
57	57	The PCI controller driver can then create a new EPC device by invoking
58	58	devm_pci_epc_create()/pci_epc_create().
59	59
60		−* devm_pci_epc_destroy()/pci_epc_destroy()
	60	+* pci_epc_destroy()
61	61
62		− The PCI controller driver can destroy the EPC device created by either
63		− devm_pci_epc_create() or pci_epc_create() using devm_pci_epc_destroy() or
64		− pci_epc_destroy().
	62	+ The PCI controller driver can destroy the EPC device created by
	63	+ pci_epc_create() using pci_epc_destroy().
65	64
66	65	* pci_epc_linkup()
67	66

drivers/pci/controller/dwc/pci-keystone.c+3−3

@@ -966,11 +966,11 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { · 965 unmodified lines
966	966	.msix_capable = true,
967	967	.bar[BAR_0] = { .type = BAR_RESERVED, },
968	968	.bar[BAR_1] = { .type = BAR_RESERVED, },
969		− .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
	969	+ .bar[BAR_2] = { .type = BAR_RESIZABLE, },
970	970	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
971	971	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, },
972		− .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
973		− .align = SZ_1M,
	972	+ .bar[BAR_5] = { .type = BAR_RESIZABLE, },
	973	+ .align = SZ_64K,
974	974	};
975	975
976	976	static const struct pci_epc_features*

drivers/pci/controller/dwc/pcie-designware-ep.c+169−35

@@ -205,6 +205,125 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, · 204 unmodified lines
205	205	ep->bar_to_atu[bar] = 0;
206	206	}
207	207
	208	+static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci,
	209	+ enum pci_barno bar)
	210	+{
	211	+ u32 reg, bar_index;
	212	+ unsigned int offset, nbars;
	213	+ int i;
	214	+
	215	+ offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
	216	+ if (!offset)
	217	+ return offset;
	218	+
	219	+ reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
	220	+ nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT;
	221	+
	222	+ for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) {
	223	+ reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
	224	+ bar_index = reg & PCI_REBAR_CTRL_BAR_IDX;
	225	+ if (bar_index == bar)
	226	+ return offset;
	227	+ }
	228	+
	229	+ return 0;
	230	+}
	231	+
	232	+static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_ep *ep, u8 func_no,
	233	+ struct pci_epf_bar *epf_bar)
	234	+{
	235	+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	236	+ enum pci_barno bar = epf_bar->barno;
	237	+ size_t size = epf_bar->size;
	238	+ int flags = epf_bar->flags;
	239	+ u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
	240	+ unsigned int rebar_offset;
	241	+ u32 rebar_cap, rebar_ctrl;
	242	+ int ret;
	243	+
	244	+ rebar_offset = dw_pcie_ep_get_rebar_offset(pci, bar);
	245	+ if (!rebar_offset)
	246	+ return -EINVAL;
	247	+
	248	+ ret = pci_epc_bar_size_to_rebar_cap(size, &rebar_cap);
	249	+ if (ret)
	250	+ return ret;
	251	+
	252	+ dw_pcie_dbi_ro_wr_en(pci);
	253	+
	254	+ /*
	255	+ * A BAR mask should not be written for a resizable BAR. The BAR mask
	256	+ * is automatically derived by the controller every time the "selected
	257	+ * size" bits are updated, see "Figure 3-26 Resizable BAR Example for
	258	+ * 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write
	259	+ * BIT(0) to set the BAR enable bit.
	260	+ */
	261	+ dw_pcie_ep_writel_dbi2(ep, func_no, reg, BIT(0));
	262	+ dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
	263	+
	264	+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
	265	+ dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0);
	266	+ dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
	267	+ }
	268	+
	269	+ /*
	270	+ * Bits 31:0 in PCI_REBAR_CAP define "supported sizes" bits for sizes
	271	+ * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes"
	272	+ * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB.
	273	+ */
	274	+ rebar_ctrl = dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL);
	275	+ rebar_ctrl &= ~GENMASK(31, 16);
	276	+ dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl);
	277	+
	278	+ /*
	279	+ * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically
	280	+ * updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR
	281	+ * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a.
	282	+ */
	283	+ dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap);
	284	+
	285	+ dw_pcie_dbi_ro_wr_dis(pci);
	286	+
	287	+ return 0;
	288	+}
	289	+
	290	+static int dw_pcie_ep_set_bar_programmable(struct dw_pcie_ep *ep, u8 func_no,
	291	+ struct pci_epf_bar *epf_bar)
	292	+{
	293	+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	294	+ enum pci_barno bar = epf_bar->barno;
	295	+ size_t size = epf_bar->size;
	296	+ int flags = epf_bar->flags;
	297	+ u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
	298	+
	299	+ dw_pcie_dbi_ro_wr_en(pci);
	300	+
	301	+ dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1));
	302	+ dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
	303	+
	304	+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
	305	+ dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1));
	306	+ dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
	307	+ }
	308	+
	309	+ dw_pcie_dbi_ro_wr_dis(pci);
	310	+
	311	+ return 0;
	312	+}
	313	+
	314	+static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(struct dw_pcie_ep *ep,
	315	+ enum pci_barno bar)
	316	+{
	317	+ const struct pci_epc_features *epc_features;
	318	+
	319	+ if (!ep->ops->get_features)
	320	+ return BAR_PROGRAMMABLE;
	321	+
	322	+ epc_features = ep->ops->get_features(ep);
	323	+
	324	+ return epc_features->bar[bar].type;
	325	+}
	326	+
208	327	static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
209	328	struct pci_epf_bar *epf_bar)
210	329	{
@@ -212,9 +331,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, · 1 unmodified line
212	331	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
213	332	enum pci_barno bar = epf_bar->barno;
214	333	size_t size = epf_bar->size;
	334	+ enum pci_epc_bar_type bar_type;
215	335	int flags = epf_bar->flags;
216	336	int ret, type;
217		− u32 reg;
218	337
219	338	/*
220	339	* DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs
@@ -246,19 +365,30 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, · 25 unmodified lines
246	365	goto config_atu;
247	366	}
248	367
249		− reg = PCI_BASE_ADDRESS_0 + (4 * bar);
250		−
251		− dw_pcie_dbi_ro_wr_en(pci);
252		−
253		− dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1));
254		− dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
255		−
256		− if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
257		− dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1));
258		− dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
	368	+ bar_type = dw_pcie_ep_get_bar_type(ep, bar);
	369	+ switch (bar_type) {
	370	+ case BAR_FIXED:
	371	+ /*
	372	+ * There is no need to write a BAR mask for a fixed BAR (except
	373	+ * to write 1 to the LSB of the BAR mask register, to enable the
	374	+ * BAR). Write the BAR mask regardless. (The fixed bits in the
	375	+ * BAR mask register will be read-only anyway.)
	376	+ */
	377	+ fallthrough;
	378	+ case BAR_PROGRAMMABLE:
	379	+ ret = dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar);
	380	+ break;
	381	+ case BAR_RESIZABLE:
	382	+ ret = dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar);
	383	+ break;
	384	+ default:
	385	+ ret = -EINVAL;
	386	+ dev_err(pci->dev, "Invalid BAR type\n");
	387	+ break;
259	388	}
260	389
261		− dw_pcie_dbi_ro_wr_dis(pci);
	390	+ if (ret)
	391	+ return ret;
262	392
263	393	config_atu:
264	394	if (!(flags & PCI_BASE_ADDRESS_SPACE))
@@ -690,31 +820,15 @@ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) · 425 unmodified lines
690	820	}
691	821	EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit);
692	822
693		−static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
694		−{
695		− u32 header;
696		− int pos = PCI_CFG_SPACE_SIZE;
697		−
698		− while (pos) {
699		− header = dw_pcie_readl_dbi(pci, pos);
700		− if (PCI_EXT_CAP_ID(header) == cap)
701		− return pos;
702		−
703		− pos = PCI_EXT_CAP_NEXT(header);
704		− if (!pos)
705		− break;
706		− }
707		−
708		− return 0;
709		−}
710		−
711	823	static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
712	824	{
	825	+ struct dw_pcie_ep *ep = &pci->ep;
713	826	unsigned int offset;
714	827	unsigned int nbars;
715		− u32 reg, i;
	828	+ enum pci_barno bar;
	829	+ u32 reg, i, val;
716	830
717		− offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
	831	+ offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
718	832
719	833	dw_pcie_dbi_ro_wr_en(pci);
720	834
@@ -727,9 +841,29 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) · 6 unmodified lines
727	841	* PCIe r6.0, sec 7.8.6.2 require us to support at least one
728	842	* size in the range from 1 MB to 512 GB. Advertise support
729	843	* for 1 MB BAR size only.
	844	+ *
	845	+ * For a BAR that has been configured via dw_pcie_ep_set_bar(),
	846	+ * advertise support for only that size instead.
730	847	*/
731		− for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
732		− dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4));
	848	+ for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) {
	849	+ /*
	850	+ * While the RESBAR_CAP_REG_* fields are sticky, the
	851	+ * RESBAR_CTRL_REG_BAR_SIZE field is non-sticky (it is
	852	+ * sticky in certain versions of DWC PCIe, but not all).
	853	+ *
	854	+ * RESBAR_CTRL_REG_BAR_SIZE is updated automatically by
	855	+ * the controller when RESBAR_CAP_REG is written, which
	856	+ * is why RESBAR_CAP_REG is written here.
	857	+ */
	858	+ val = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
	859	+ bar = val & PCI_REBAR_CTRL_BAR_IDX;
	860	+ if (ep->epf_bar[bar])
	861	+ pci_epc_bar_size_to_rebar_cap(ep->epf_bar[bar]->size, &val);
	862	+ else
	863	+ val = BIT(4);
	864	+
	865	+ dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val);
	866	+ }
733	867	}
734	868
735	869	dw_pcie_setup(pci);
@@ -817,7 +951,7 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) · 81 unmodified lines
817	951	if (ep->ops->init)
818	952	ep->ops->init(ep);
819	953
820		− ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
	954	+ ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
821	955
822	956	/*
823	957	* PTM responder capability can be disabled only after disabling

drivers/pci/controller/dwc/pcie-dw-rockchip.c+11−11

@@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { · 272 unmodified lines
273	273	.msi_capable = true,
274	274	.msix_capable = true,
275	275	.align = SZ_64K,
276		− .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
277		− .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
278		− .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
279		− .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
280		− .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
281		− .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
	276	+ .bar[BAR_0] = { .type = BAR_RESIZABLE, },
	277	+ .bar[BAR_1] = { .type = BAR_RESIZABLE, },
	278	+ .bar[BAR_2] = { .type = BAR_RESIZABLE, },
	279	+ .bar[BAR_3] = { .type = BAR_RESIZABLE, },
	280	+ .bar[BAR_4] = { .type = BAR_RESIZABLE, },
	281	+ .bar[BAR_5] = { .type = BAR_RESIZABLE, },
282	282	};
283	283
284	284	/*
@@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { · 8 unmodified lines
293	293	.msi_capable = true,
294	294	.msix_capable = true,
295	295	.align = SZ_64K,
296		− .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
297		− .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
298		− .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
299		− .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
	296	+ .bar[BAR_0] = { .type = BAR_RESIZABLE, },
	297	+ .bar[BAR_1] = { .type = BAR_RESIZABLE, },
	298	+ .bar[BAR_2] = { .type = BAR_RESIZABLE, },
	299	+ .bar[BAR_3] = { .type = BAR_RESIZABLE, },
300	300	.bar[BAR_4] = { .type = BAR_RESERVED, },
301		− .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
	301	+ .bar[BAR_5] = { .type = BAR_RESIZABLE, },
302	302	};
303	303
304	304	static const struct pci_epc_features *

drivers/pci/endpoint/functions/pci-epf-test.c+75−53

@@ -66,17 +66,17 @@ struct pci_epf_test { · 65 unmodified lines
66	66	};
67	67
68	68	struct pci_epf_test_reg {
69		− u32 magic;
70		− u32 command;
71		− u32 status;
72		− u64 src_addr;
73		− u64 dst_addr;
74		− u32 size;
75		− u32 checksum;
76		− u32 irq_type;
77		− u32 irq_number;
78		− u32 flags;
79		− u32 caps;
	69	+ __le32 magic;
	70	+ __le32 command;
	71	+ __le32 status;
	72	+ __le64 src_addr;
	73	+ __le64 dst_addr;
	74	+ __le32 size;
	75	+ __le32 checksum;
	76	+ __le32 irq_type;
	77	+ __le32 irq_number;
	78	+ __le32 flags;
	79	+ __le32 caps;
80	80	} __packed;
81	81
82	82	static struct pci_epf_header test_header = {
@@ -324,13 +324,17 @@ static void pci_epf_test_copy(struct pci_epf_test *epf_test, · 241 unmodified lines
324	324	struct pci_epc *epc = epf->epc;
325	325	struct device *dev = &epf->dev;
326	326	struct pci_epc_map src_map, dst_map;
327		− u64 src_addr = reg->src_addr;
328		− u64 dst_addr = reg->dst_addr;
329		− size_t copy_size = reg->size;
	327	+ u64 src_addr = le64_to_cpu(reg->src_addr);
	328	+ u64 dst_addr = le64_to_cpu(reg->dst_addr);
	329	+ size_t orig_size, copy_size;
330	330	ssize_t map_size = 0;
	331	+ u32 flags = le32_to_cpu(reg->flags);
	332	+ u32 status = 0;
331	333	void copy_buf = NULL, buf;
332	334
333		− if (reg->flags & FLAG_USE_DMA) {
	335	+ orig_size = copy_size = le32_to_cpu(reg->size);
	336	+
	337	+ if (flags & FLAG_USE_DMA) {
334	338	if (!dma_has_cap(DMA_MEMCPY, epf_test->dma_chan_tx->device->cap_mask)) {
335	339	dev_err(dev, "DMA controller doesn't support MEMCPY\n");
336	340	ret = -EINVAL;
@@ -350,7 +354,7 @@ static void pci_epf_test_copy(struct pci_epf_test *epf_test, · 13 unmodified lines
350	354	src_addr, copy_size, &src_map);
351	355	if (ret) {
352	356	dev_err(dev, "Failed to map source address\n");
353		− reg->status = STATUS_SRC_ADDR_INVALID;
	357	+ status = STATUS_SRC_ADDR_INVALID;
354	358	goto free_buf;
355	359	}
356	360
@@ -358,7 +362,7 @@ static void pci_epf_test_copy(struct pci_epf_test *epf_test, · 1 unmodified line
358	362	dst_addr, copy_size, &dst_map);
359	363	if (ret) {
360	364	dev_err(dev, "Failed to map destination address\n");
361		− reg->status = STATUS_DST_ADDR_INVALID;
	365	+ status = STATUS_DST_ADDR_INVALID;
362	366	pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no,
363	367	&src_map);
364	368	goto free_buf;
@@ -367,7 +371,7 @@ static void pci_epf_test_copy(struct pci_epf_test *epf_test, · 2 unmodified lines
367	371	map_size = min_t(size_t, dst_map.pci_size, src_map.pci_size);
368	372
369	373	ktime_get_ts64(&start);
370		− if (reg->flags & FLAG_USE_DMA) {
	374	+ if (flags & FLAG_USE_DMA) {
371	375	ret = pci_epf_test_data_transfer(epf_test,
372	376	dst_map.phys_addr, src_map.phys_addr,
373	377	map_size, 0, DMA_MEM_TO_MEM);
@@ -391,8 +395,8 @@ static void pci_epf_test_copy(struct pci_epf_test *epf_test, · 17 unmodified lines
391	395	map_size = 0;
392	396	}
393	397
394		− pci_epf_test_print_rate(epf_test, "COPY", reg->size, &start,
395		− &end, reg->flags & FLAG_USE_DMA);
	398	+ pci_epf_test_print_rate(epf_test, "COPY", orig_size, &start, &end,
	399	+ flags & FLAG_USE_DMA);
396	400
397	401	unmap:
398	402	if (map_size) {
@@ -405,9 +409,10 @@ free_buf: · 6 unmodified lines
405	409
406	410	set_status:
407	411	if (!ret)
408		− reg->status \|= STATUS_COPY_SUCCESS;
	412	+ status \|= STATUS_COPY_SUCCESS;
409	413	else
410		− reg->status \|= STATUS_COPY_FAIL;
	414	+ status \|= STATUS_COPY_FAIL;
	415	+ reg->status = cpu_to_le32(status);
411	416	}
412	417
413	418	static void pci_epf_test_read(struct pci_epf_test *epf_test,
@@ -423,9 +428,14 @@ static void pci_epf_test_read(struct pci_epf_test *epf_test, · 9 unmodified lines
423	428	struct pci_epc *epc = epf->epc;
424	429	struct device *dev = &epf->dev;
425	430	struct device *dma_dev = epf->epc->dev.parent;
426		− u64 src_addr = reg->src_addr;
427		− size_t src_size = reg->size;
	431	+ u64 src_addr = le64_to_cpu(reg->src_addr);
	432	+ size_t orig_size, src_size;
428	433	ssize_t map_size = 0;
	434	+ u32 flags = le32_to_cpu(reg->flags);
	435	+ u32 checksum = le32_to_cpu(reg->checksum);
	436	+ u32 status = 0;
	437	+
	438	+ orig_size = src_size = le32_to_cpu(reg->size);
429	439
430	440	src_buf = kzalloc(src_size, GFP_KERNEL);
431	441	if (!src_buf) {
@@ -439,12 +449,12 @@ static void pci_epf_test_read(struct pci_epf_test *epf_test, · 7 unmodified lines
439	449	src_addr, src_size, &map);
440	450	if (ret) {
441	451	dev_err(dev, "Failed to map address\n");
442		− reg->status = STATUS_SRC_ADDR_INVALID;
	452	+ status = STATUS_SRC_ADDR_INVALID;
443	453	goto free_buf;
444	454	}
445	455
446	456	map_size = map.pci_size;
447		− if (reg->flags & FLAG_USE_DMA) {
	457	+ if (flags & FLAG_USE_DMA) {
448	458	dst_phys_addr = dma_map_single(dma_dev, buf, map_size,
449	459	DMA_FROM_DEVICE);
450	460	if (dma_mapping_error(dma_dev, dst_phys_addr)) {
@@ -481,11 +491,11 @@ static void pci_epf_test_read(struct pci_epf_test *epf_test, · 30 unmodified lines
481	491	map_size = 0;
482	492	}
483	493
484		− pci_epf_test_print_rate(epf_test, "READ", reg->size, &start,
485		− &end, reg->flags & FLAG_USE_DMA);
	494	+ pci_epf_test_print_rate(epf_test, "READ", orig_size, &start, &end,
	495	+ flags & FLAG_USE_DMA);
486	496
487		− crc32 = crc32_le(~0, src_buf, reg->size);
488		− if (crc32 != reg->checksum)
	497	+ crc32 = crc32_le(~0, src_buf, orig_size);
	498	+ if (crc32 != checksum)
489	499	ret = -EIO;
490	500
491	501	unmap:
@@ -497,9 +507,10 @@ free_buf: · 5 unmodified lines
497	507
498	508	set_status:
499	509	if (!ret)
500		− reg->status \|= STATUS_READ_SUCCESS;
	510	+ status \|= STATUS_READ_SUCCESS;
501	511	else
502		− reg->status \|= STATUS_READ_FAIL;
	512	+ status \|= STATUS_READ_FAIL;
	513	+ reg->status = cpu_to_le32(status);
503	514	}
504	515
505	516	static void pci_epf_test_write(struct pci_epf_test *epf_test,
@@ -514,9 +525,13 @@ static void pci_epf_test_write(struct pci_epf_test *epf_test, · 8 unmodified lines
514	525	struct pci_epc *epc = epf->epc;
515	526	struct device *dev = &epf->dev;
516	527	struct device *dma_dev = epf->epc->dev.parent;
517		− u64 dst_addr = reg->dst_addr;
518		− size_t dst_size = reg->size;
	528	+ u64 dst_addr = le64_to_cpu(reg->dst_addr);
	529	+ size_t orig_size, dst_size;
519	530	ssize_t map_size = 0;
	531	+ u32 flags = le32_to_cpu(reg->flags);
	532	+ u32 status = 0;
	533	+
	534	+ orig_size = dst_size = le32_to_cpu(reg->size);
520	535
521	536	dst_buf = kzalloc(dst_size, GFP_KERNEL);
522	537	if (!dst_buf) {
@@ -524,7 +539,7 @@ static void pci_epf_test_write(struct pci_epf_test *epf_test, · 1 unmodified line
524	539	goto set_status;
525	540	}
526	541	get_random_bytes(dst_buf, dst_size);
527		− reg->checksum = crc32_le(~0, dst_buf, dst_size);
	542	+ reg->checksum = cpu_to_le32(crc32_le(~0, dst_buf, dst_size));
528	543	buf = dst_buf;
529	544
530	545	while (dst_size) {
@@ -532,12 +547,12 @@ static void pci_epf_test_write(struct pci_epf_test *epf_test, · 1 unmodified line
532	547	dst_addr, dst_size, &map);
533	548	if (ret) {
534	549	dev_err(dev, "Failed to map address\n");
535		− reg->status = STATUS_DST_ADDR_INVALID;
	550	+ status = STATUS_DST_ADDR_INVALID;
536	551	goto free_buf;
537	552	}
538	553
539	554	map_size = map.pci_size;
540		− if (reg->flags & FLAG_USE_DMA) {
	555	+ if (flags & FLAG_USE_DMA) {
541	556	src_phys_addr = dma_map_single(dma_dev, buf, map_size,
542	557	DMA_TO_DEVICE);
543	558	if (dma_mapping_error(dma_dev, src_phys_addr)) {
@@ -576,8 +591,8 @@ static void pci_epf_test_write(struct pci_epf_test *epf_test, · 32 unmodified lines
576	591	map_size = 0;
577	592	}
578	593
579		− pci_epf_test_print_rate(epf_test, "WRITE", reg->size, &start,
580		− &end, reg->flags & FLAG_USE_DMA);
	594	+ pci_epf_test_print_rate(epf_test, "WRITE", orig_size, &start, &end,
	595	+ flags & FLAG_USE_DMA);
581	596
582	597	/*
583	598	* wait 1ms inorder for the write to complete. Without this delay L3
@@ -594,9 +609,10 @@ free_buf: · 10 unmodified lines
594	609
595	610	set_status:
596	611	if (!ret)
597		− reg->status \|= STATUS_WRITE_SUCCESS;
	612	+ status \|= STATUS_WRITE_SUCCESS;
598	613	else
599		− reg->status \|= STATUS_WRITE_FAIL;
	614	+ status \|= STATUS_WRITE_FAIL;
	615	+ reg->status = cpu_to_le32(status);
600	616	}
601	617
602	618	static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
@@ -605,39 +621,42 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, · 2 unmodified lines
605	621	struct pci_epf *epf = epf_test->epf;
606	622	struct device *dev = &epf->dev;
607	623	struct pci_epc *epc = epf->epc;
608		− u32 status = reg->status \| STATUS_IRQ_RAISED;
	624	+ u32 status = le32_to_cpu(reg->status);
	625	+ u32 irq_number = le32_to_cpu(reg->irq_number);
	626	+ u32 irq_type = le32_to_cpu(reg->irq_type);
609	627	int count;
610	628
611	629	/*
612	630	* Set the status before raising the IRQ to ensure that the host sees
613	631	* the updated value when it gets the IRQ.
614	632	*/
615		− WRITE_ONCE(reg->status, status);
	633	+ status \|= STATUS_IRQ_RAISED;
	634	+ WRITE_ONCE(reg->status, cpu_to_le32(status));
616	635
617		− switch (reg->irq_type) {
	636	+ switch (irq_type) {
618	637	case IRQ_TYPE_INTX:
619	638	pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
620	639	PCI_IRQ_INTX, 0);
621	640	break;
622	641	case IRQ_TYPE_MSI:
623	642	count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
624		− if (reg->irq_number > count \|\| count <= 0) {
	643	+ if (irq_number > count \|\| count <= 0) {
625	644	dev_err(dev, "Invalid MSI IRQ number %d / %d\n",
626		− reg->irq_number, count);
	645	+ irq_number, count);
627	646	return;
628	647	}
629	648	pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
630		− PCI_IRQ_MSI, reg->irq_number);
	649	+ PCI_IRQ_MSI, irq_number);
631	650	break;
632	651	case IRQ_TYPE_MSIX:
633	652	count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
634		− if (reg->irq_number > count \|\| count <= 0) {
	653	+ if (irq_number > count \|\| count <= 0) {
635	654	dev_err(dev, "Invalid MSIX IRQ number %d / %d\n",
636		− reg->irq_number, count);
	655	+ irq_number, count);
637	656	return;
638	657	}
639	658	pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
640		− PCI_IRQ_MSIX, reg->irq_number);
	659	+ PCI_IRQ_MSIX, irq_number);
641	660	break;
642	661	default:
643	662	dev_err(dev, "Failed to raise IRQ, unknown type\n");
@@ -654,21 +673,22 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) · 10 unmodified lines
654	673	struct device *dev = &epf->dev;
655	674	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
656	675	struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
	676	+ u32 irq_type = le32_to_cpu(reg->irq_type);
657	677
658		− command = READ_ONCE(reg->command);
	678	+ command = le32_to_cpu(READ_ONCE(reg->command));
659	679	if (!command)
660	680	goto reset_handler;
661	681
662	682	WRITE_ONCE(reg->command, 0);
663	683	WRITE_ONCE(reg->status, 0);
664	684
665		− if ((READ_ONCE(reg->flags) & FLAG_USE_DMA) &&
	685	+ if ((le32_to_cpu(READ_ONCE(reg->flags)) & FLAG_USE_DMA) &&
666	686	!epf_test->dma_supported) {
667	687	dev_err(dev, "Cannot transfer data using DMA\n");
668	688	goto reset_handler;
669	689	}
670	690
671		− if (reg->irq_type > IRQ_TYPE_MSIX) {
	691	+ if (irq_type > IRQ_TYPE_MSIX) {
672	692	dev_err(dev, "Failed to detect IRQ type\n");
673	693	goto reset_handler;
674	694	}
@@ -718,6 +738,7 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) · 43 unmodified lines
718	738	if (ret) {
719	739	pci_epf_free_space(epf, epf_test->reg[bar], bar,
720	740	PRIMARY_INTERFACE);
	741	+ epf_test->reg[bar] = NULL;
721	742	dev_err(dev, "Failed to set BAR%d\n", bar);
722	743	if (bar == test_reg_bar)
723	744	return ret;
@@ -909,6 +930,7 @@ static void pci_epf_test_free_space(struct pci_epf *epf) · 185 unmodified lines
909	930
910	931	pci_epf_free_space(epf, epf_test->reg[bar], bar,
911	932	PRIMARY_INTERFACE);
	933	+ epf_test->reg[bar] = NULL;
912	934	}
913	935	}
914	936

drivers/pci/endpoint/pci-epc-core.c+31−25

@@ -25,13 +25,6 @@ static void devm_pci_epc_release(struct device dev, void res) · 24 unmodified lines
25	25	pci_epc_destroy(epc);
26	26	}
27	27
28		−static int devm_pci_epc_match(struct device dev, void res, void *match_data)
29		−{
30		− struct pci_epc **epc = res;
31		−
32		− return *epc == match_data;
33		−}
34		−
35	28	/**
36	29	* pci_epc_put() - release the PCI endpoint controller
37	30	* @epc: epc returned by pci_epc_get()
@@ -609,6 +602,10 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, · 571 unmodified lines
609	602	if (!epc_features)
610	603	return -EINVAL;
611	604
	605	+ if (epc_features->bar[bar].type == BAR_RESIZABLE &&
	606	+ (epf_bar->size < SZ_1M \|\| (u64)epf_bar->size > (SZ_128G * 1024)))
	607	+ return -EINVAL;
	608	+
612	609	if (epc_features->bar[bar].type == BAR_FIXED &&
613	610	(epc_features->bar[bar].fixed_size != epf_bar->size))
614	611	return -EINVAL;
@@ -634,6 +631,33 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, · 19 unmodified lines
634	631	}
635	632	EXPORT_SYMBOL_GPL(pci_epc_set_bar);
636	633
	634	+/**
	635	+ * pci_epc_bar_size_to_rebar_cap() - convert a size to the representation used
	636	+ * by the Resizable BAR Capability Register
	637	+ * @size: the size to convert
	638	+ * @cap: where to store the result
	639	+ *
	640	+ * Returns 0 on success and a negative error code in case of error.
	641	+ */
	642	+int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap)
	643	+{
	644	+ /*
	645	+ * As per PCIe r6.0, sec 7.8.6.2, min size for a resizable BAR is 1 MB,
	646	+ * thus disallow a requested BAR size smaller than 1 MB.
	647	+ * Disallow a requested BAR size larger than 128 TB.
	648	+ */
	649	+ if (size < SZ_1M \|\| (u64)size > (SZ_128G * 1024))
	650	+ return -EINVAL;
	651	+
	652	+ *cap = ilog2(size) - ilog2(SZ_1M);
	653	+
	654	+ /* Sizes in REBAR_CAP start at BIT(4). */
	655	+ cap = BIT(cap + 4);
	656	+
	657	+ return 0;
	658	+}
	659	+EXPORT_SYMBOL_GPL(pci_epc_bar_size_to_rebar_cap);
	660	+
637	661	/**
638	662	* pci_epc_write_header() - write standard configuration header
639	663	* @epc: the EPC device to which the configuration header should be written
@@ -931,24 +955,6 @@ void pci_epc_destroy(struct pci_epc *epc) · 291 unmodified lines
931	955	}
932	956	EXPORT_SYMBOL_GPL(pci_epc_destroy);
933	957
934		−/**
935		− * devm_pci_epc_destroy() - destroy the EPC device
936		− * @dev: device that wants to destroy the EPC
937		− * @epc: the EPC device that has to be destroyed
938		− *
939		− * Invoke to destroy the devres associated with this
940		− * pci_epc and destroy the EPC device.
941		− */
942		−void devm_pci_epc_destroy(struct device dev, struct pci_epc epc)
943		−{
944		− int r;
945		−
946		− r = devres_release(dev, devm_pci_epc_release, devm_pci_epc_match,
947		− epc);
948		− dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
949		−}
950		−EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
951		−
952	958	static void pci_epc_release(struct device *dev)
953	959	{
954	960	kfree(to_pci_epc(dev));

drivers/pci/endpoint/pci-epf-core.c+4−0

@@ -274,6 +274,10 @@ void pci_epf_alloc_space(struct pci_epf epf, size_t size, enum pci_barno bar, · 273 unmodified lines
274	274	if (size < 128)
275	275	size = 128;
276	276
	277	+ /* According to PCIe base spec, min size for a resizable BAR is 1 MB. */
	278	+ if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M)
	279	+ size = SZ_1M;
	280	+
277	281	if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) {
278	282	if (size > bar_fixed_size) {
279	283	dev_err(&epf->dev,

include/linux/pci-epc.h+5−1

@@ -188,11 +188,15 @@ struct pci_epc { · 187 unmodified lines
188	188	* enum pci_epc_bar_type - configurability of endpoint BAR
189	189	* @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
190	190	* @BAR_FIXED: The BAR mask is fixed by the hardware.
	191	+ * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
	192	+ * NOTE: An EPC driver can currently only set a single supported
	193	+ * size.
191	194	* @BAR_RESERVED: The BAR should not be touched by an EPF driver.
192	195	*/
193	196	enum pci_epc_bar_type {
194	197	BAR_PROGRAMMABLE = 0,
195	198	BAR_FIXED,
	199	+ BAR_RESIZABLE,
196	200	BAR_RESERVED,
197	201	};
198	202
@@ -257,7 +261,6 @@ __devm_pci_epc_create(struct device dev, const struct pci_epc_ops ops, · 58 unmodified lines
257	261	struct pci_epc *
258	262	__pci_epc_create(struct device dev, const struct pci_epc_ops ops,
259	263	struct module *owner);
260		−void devm_pci_epc_destroy(struct device dev, struct pci_epc epc);
261	264	void pci_epc_destroy(struct pci_epc *epc);
262	265	int pci_epc_add_epf(struct pci_epc epc, struct pci_epf epf,
263	266	enum pci_epc_interface_type type);
@@ -271,6 +274,7 @@ void pci_epc_remove_epf(struct pci_epc epc, struct pci_epf epf, · 7 unmodified lines
271	274	enum pci_epc_interface_type type);
272	275	int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
273	276	struct pci_epf_header *hdr);
	277	+int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap);
274	278	int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
275	279	struct pci_epf_bar *epf_bar);
276	280	void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,