History

Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull clocksource updates from Ingo Molnar: "Misc clocksource/clockevent driver updates that came in a bit late but are ready for v5.2" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: misc: atmel_tclib: Do not probe already used TCBs clocksource/drivers/timer-atmel-tcb: Convert tc_clksrc_suspend|resume() to static clocksource/drivers/tcb_clksrc: Rename the file for consistency clocksource/drivers/timer-atmel-pit: Rework Kconfig option clocksource/drivers/tcb_clksrc: Move Kconfig option ARM: at91: Implement clocksource selection clocksource/drivers/tcb_clksrc: Use tcb as sched_clock clocksource/drivers/tcb_clksrc: Stop depending on atmel_tclib ARM: at91: move SoC specific definitions to SoC folder clocksource/drivers/timer-milbeaut: Cleanup common register accesses clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/tegra: Rework for compensation of suspend time clocksource/drivers/sp804: Add COMPILE_TEST to CONFIG_ARM_TIMER_SP804 clocksource/drivers/sun4i: Add a compatible for suniv dt-bindings: timer: Add Allwinner suniv timer

Linus Torvalds committed 7 years ago

Commit a13f9502 parents d9351ea ea7a5f912 files · +202 −136Browse files

Unified · Split

12 files
  1. Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +3 −1
  2. arch/arm/mach-at91/Kconfig +23 −0
  3. drivers/clocksource/Kconfig +12 −2
  4. drivers/clocksource/Makefile +1 −1
  5. drivers/clocksource/timer-atmel-tcb.c +85 −41
  6. drivers/clocksource/timer-milbeaut.c +47 −19
  7. drivers/clocksource/timer-sun4i.c +4 −1
  8. drivers/clocksource/timer-tegra20.c +20 −43
  9. drivers/misc/Kconfig +0 −24
  10. drivers/misc/atmel_tclib.c +4 −1
  11. drivers/pwm/pwm-atmel-tcb.c +1 −1
  12. include/soc/at91/atmel_tcb.h +2 −2
Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt+3−1
@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller · 1 unmodified line
22
33 Required properties:
44
5−- compatible : should be "allwinner,sun4i-a10-timer"
5+- compatible : should be one of the following:
6+ "allwinner,sun4i-a10-timer"
7+ "allwinner,suniv-f1c100s-timer"
68 - reg : Specifies base physical address and size of the registers.
79 - interrupts : The interrupt of the first timer
810 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
arch/arm/mach-at91/Kconfig+23−0
@@ -104,6 +104,29 @@ config SOC_AT91SAM9 · 103 unmodified lines
104104 AT91SAM9X35
105105 AT91SAM9XE
106106
107+comment "Clocksource driver selection"
108+
109+config ATMEL_CLOCKSOURCE_PIT
110+ bool "Periodic Interval Timer (PIT) support"
111+ depends on SOC_AT91SAM9 || SOC_SAMA5
112+ default SOC_AT91SAM9 || SOC_SAMA5
113+ select ATMEL_PIT
114+ help
115+ Select this to get a clocksource based on the Atmel Periodic Interval
116+ Timer. It has a relatively low resolution and the TC Block clocksource
117+ should be preferred.
118+
119+config ATMEL_CLOCKSOURCE_TCB
120+ bool "Timer Counter Blocks (TCB) support"
121+ default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5
122+ select ATMEL_TCB_CLKSRC
123+ help
124+ Select this to get a high precision clocksource based on a
125+ TC block with a 5+ MHz base clock rate.
126+ On platforms with 16-bit counters, two timer channels are combined
127+ to make a single 32-bit timer.
128+ It can also be used as a clock event device supporting oneshot mode.
129+
107130 config HAVE_AT91_UTMI
108131 bool
109132
drivers/clocksource/Kconfig+12−2
@@ -387,7 +387,7 @@ config ARM_GLOBAL_TIMER · 386 unmodified lines
387387 This options enables support for the ARM global timer unit
388388
389389 config ARM_TIMER_SP804
390− bool "Support for Dual Timer SP804 module"
390+ bool "Support for Dual Timer SP804 module" if COMPILE_TEST
391391 depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
392392 select CLKSRC_MMIO
393393 select TIMER_OF if OF
@@ -407,8 +407,11 @@ config ARMV7M_SYSTICK · 13 unmodified lines
407407 This options enables support for the ARMv7M system timer unit
408408
409409 config ATMEL_PIT
410+ bool "Atmel PIT support" if COMPILE_TEST
411+ depends on HAS_IOMEM
410412 select TIMER_OF if OF
411− def_bool SOC_AT91SAM9 || SOC_SAMA5
413+ help
414+ Support for the Periodic Interval Timer found on Atmel SoCs.
412415
413416 config ATMEL_ST
414417 bool "Atmel ST timer support" if COMPILE_TEST
@@ -418,6 +421,13 @@ config ATMEL_ST · 3 unmodified lines
418421 help
419422 Support for the Atmel ST timer.
420423
424+config ATMEL_TCB_CLKSRC
425+ bool "Atmel TC Block timer driver" if COMPILE_TEST
426+ depends on HAS_IOMEM
427+ select TIMER_OF if OF
428+ help
429+ Support for Timer Counter Blocks on Atmel SoCs.
430+
421431 config CLKSRC_EXYNOS_MCT
422432 bool "Exynos multi core timer driver" if COMPILE_TEST
423433 depends on ARM || ARM64
drivers/clocksource/Makefile+1−1
@@ -3,7 +3,7 @@ obj-$(CONFIG_TIMER_OF) += timer-of.o · 2 unmodified lines
33 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
44 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
55 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
6−obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
6+obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
77 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
88 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
99 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
drivers/clocksource/timer-atmel-tcb.crenamed from drivers/clocksource/tcb_clksrc.c+85−41
@@ -9,9 +9,11 @@ · 8 unmodified lines
99 #include <linux/err.h>
1010 #include <linux/ioport.h>
1111 #include <linux/io.h>
12−#include <linux/platform_device.h>
12+#include <linux/of_address.h>
13+#include <linux/of_irq.h>
14+#include <linux/sched_clock.h>
1315 #include <linux/syscore_ops.h>
14−#include <linux/atmel_tc.h>
16+#include <soc/at91/atmel_tcb.h>
1517
1618
1719 /*
@@ -28,13 +30,6 @@ · 10 unmodified lines
2830 * source, used in either periodic or oneshot mode. This runs
2931 * at 32 KiHZ, and can handle delays of up to two seconds.
3032 *
31− * A boot clocksource and clockevent source are also currently needed,
32− * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
33− * this code can be used when init_timers() is called, well before most
34− * devices are set up. (Some low end AT91 parts, which can run uClinux,
35− * have only the timers in one TC block... they currently don't support
36− * the tclib code, because of that initialization issue.)
37− *
3833 * REVISIT behavior during system suspend states... we should disable
3934 * all clocks and save the power. Easily done for clockevent devices,
4035 * but clocksources won't necessarily get the needed notifications.
@@ -112,7 +107,6 @@ static void tc_clksrc_resume(struct clocksource *cs) · 71 unmodified lines
112107 }
113108
114109 static struct clocksource clksrc = {
115− .name = "tcb_clksrc",
116110 .rating = 200,
117111 .read = tc_get_cycles,
118112 .mask = CLOCKSOURCE_MASK(32),
@@ -121,6 +115,16 @@ static struct clocksource clksrc = { · 2 unmodified lines
121115 .resume = tc_clksrc_resume,
122116 };
123117
118+static u64 notrace tc_sched_clock_read(void)
119+{
120+ return tc_get_cycles(&clksrc);
121+}
122+
123+static u64 notrace tc_sched_clock_read32(void)
124+{
125+ return tc_get_cycles32(&clksrc);
126+}
127+
124128 #ifdef CONFIG_GENERIC_CLOCKEVENTS
125129
126130 struct tc_clkevt_device {
@@ -214,7 +218,6 @@ static int tc_next_event(unsigned long delta, struct clock_event_device *d) · 87 unmodified lines
214218
215219 static struct tc_clkevt_device clkevt = {
216220 .clkevt = {
217− .name = "tc_clkevt",
218221 .features = CLOCK_EVT_FEAT_PERIODIC |
219222 CLOCK_EVT_FEAT_ONESHOT,
220223 /* Should be lower than at91rm9200's system timer */
@@ -330,39 +333,74 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id · 109 unmodified lines
330333 writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
331334 }
332335
333−static int __init tcb_clksrc_init(void)
334−{
335− static char bootinfo[] __initdata
336− = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
336+static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
337+
338+static const struct of_device_id atmel_tcb_of_match[] = {
339+ { .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
340+ { .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, },
341+ { /* sentinel */ }
342+};
337343
338− struct platform_device *pdev;
339− struct atmel_tc *tc;
344+static int __init tcb_clksrc_init(struct device_node *node)
345+{
346+ struct atmel_tc tc;
340347 struct clk *t0_clk;
348+ const struct of_device_id *match;
349+ u64 (*tc_sched_clock)(void);
341350 u32 rate, divided_rate = 0;
342351 int best_divisor_idx = -1;
343352 int clk32k_divisor_idx = -1;
353+ int bits;
344354 int i;
345355 int ret;
346356
347− tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
348− if (!tc) {
349− pr_debug("can't alloc TC for clocksource\n");
350− return -ENODEV;
357+ /* Protect against multiple calls */
358+ if (tcaddr)
359+ return 0;
360+
361+ tc.regs = of_iomap(node->parent, 0);
362+ if (!tc.regs)
363+ return -ENXIO;
364+
365+ t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
366+ if (IS_ERR(t0_clk))
367+ return PTR_ERR(t0_clk);
368+
369+ tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
370+ if (IS_ERR(tc.slow_clk))
371+ return PTR_ERR(tc.slow_clk);
372+
373+ tc.clk[0] = t0_clk;
374+ tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
375+ if (IS_ERR(tc.clk[1]))
376+ tc.clk[1] = t0_clk;
377+ tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
378+ if (IS_ERR(tc.clk[2]))
379+ tc.clk[2] = t0_clk;
380+
381+ tc.irq[2] = of_irq_get(node->parent, 2);
382+ if (tc.irq[2] <= 0) {
383+ tc.irq[2] = of_irq_get(node->parent, 0);
384+ if (tc.irq[2] <= 0)
385+ return -EINVAL;
351386 }
352− tcaddr = tc->regs;
353− pdev = tc->pdev;
354387
355− t0_clk = tc->clk[0];
388+ match = of_match_node(atmel_tcb_of_match, node->parent);
389+ bits = (uintptr_t)match->data;
390+
391+ for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
392+ writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
393+
356394 ret = clk_prepare_enable(t0_clk);
357395 if (ret) {
358396 pr_debug("can't enable T0 clk\n");
359− goto err_free_tc;
397+ return ret;
360398 }
361399
362400 /* How fast will we be counting? Pick something over 5 MHz. */
363401 rate = (u32) clk_get_rate(t0_clk);
364− for (i = 0; i < 5; i++) {
365− unsigned divisor = atmel_tc_divisors[i];
402+ for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
403+ unsigned divisor = atmel_tcb_divisors[i];
366404 unsigned tmp;
367405
368406 /* remember 32 KiHz clock for later */
@@ -381,27 +419,31 @@ static int __init tcb_clksrc_init(void) · 12 unmodified lines
381419 best_divisor_idx = i;
382420 }
383421
384−
385− printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
386− divided_rate / 1000000,
422+ clksrc.name = kbasename(node->parent->full_name);
423+ clkevt.clkevt.name = kbasename(node->parent->full_name);
424+ pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
387425 ((divided_rate % 1000000) + 500) / 1000);
388426
389− if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
427+ tcaddr = tc.regs;
428+
429+ if (bits == 32) {
390430 /* use apropriate function to read 32 bit counter */
391431 clksrc.read = tc_get_cycles32;
392432 /* setup ony channel 0 */
393− tcb_setup_single_chan(tc, best_divisor_idx);
433+ tcb_setup_single_chan(&tc, best_divisor_idx);
434+ tc_sched_clock = tc_sched_clock_read32;
394435 } else {
395− /* tclib will give us three clocks no matter what the
436+ /* we have three clocks no matter what the
396437 * underlying platform supports.
397438 */
398− ret = clk_prepare_enable(tc->clk[1]);
439+ ret = clk_prepare_enable(tc.clk[1]);
399440 if (ret) {
400441 pr_debug("can't enable T1 clk\n");
401442 goto err_disable_t0;
402443 }
403444 /* setup both channel 0 & 1 */
404− tcb_setup_dual_chan(tc, best_divisor_idx);
445+ tcb_setup_dual_chan(&tc, best_divisor_idx);
446+ tc_sched_clock = tc_sched_clock_read;
405447 }
406448
407449 /* and away we go! */
@@ -410,24 +452,26 @@ static int __init tcb_clksrc_init(void) · 2 unmodified lines
410452 goto err_disable_t1;
411453
412454 /* channel 2: periodic and oneshot timer support */
413− ret = setup_clkevents(tc, clk32k_divisor_idx);
455+ ret = setup_clkevents(&tc, clk32k_divisor_idx);
414456 if (ret)
415457 goto err_unregister_clksrc;
416458
459+ sched_clock_register(tc_sched_clock, 32, divided_rate);
460+
417461 return 0;
418462
419463 err_unregister_clksrc:
420464 clocksource_unregister(&clksrc);
421465
422466 err_disable_t1:
423− if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
424− clk_disable_unprepare(tc->clk[1]);
467+ if (bits != 32)
468+ clk_disable_unprepare(tc.clk[1]);
425469
426470 err_disable_t0:
427471 clk_disable_unprepare(t0_clk);
428472
429−err_free_tc:
430− atmel_tc_free(tc);
473+ tcaddr = NULL;
474+
431475 return ret;
432476 }
433−arch_initcall(tcb_clksrc_init);
477+TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
drivers/clocksource/timer-milbeaut.c+47−19
@@ -26,8 +26,8 @@ · 25 unmodified lines
2626 #define MLB_TMR_TMCSR_CSL_DIV2 0
2727 #define MLB_TMR_DIV_CNT 2
2828
29−#define MLB_TMR_SRC_CH (1)
30−#define MLB_TMR_EVT_CH (0)
29+#define MLB_TMR_SRC_CH 1
30+#define MLB_TMR_EVT_CH 0
3131
3232 #define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
3333 #define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
@@ -43,6 +43,8 @@ · 9 unmodified lines
4343 #define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
4444
4545 #define MLB_TIMER_RATING 500
46+#define MLB_TIMER_ONESHOT 0
47+#define MLB_TIMER_PERIODIC 1
4648
4749 static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
4850 {
@@ -59,27 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id) · 10 unmodified lines
5961 return IRQ_HANDLED;
6062 }
6163
62−static int mlb_set_state_periodic(struct clock_event_device *clk)
64+static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
6365 {
64− struct timer_of *to = to_timer_of(clk);
6566 u32 val = MLB_TMR_TMCSR_CSL_DIV2;
6667
68+ val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
69+ if (periodic)
70+ val |= MLB_TMR_TMCSR_RELD;
6771 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
72+}
6873
69− writel_relaxed(to->of_clk.period, timer_of_base(to) +
70− MLB_TMR_EVT_TMRLR1_OFS);
71− val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
72− MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
74+static void mlb_evt_timer_stop(struct timer_of *to)
75+{
76+ u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
77+
78+ val &= ~MLB_TMR_TMCSR_CNTE;
7379 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
80+}
81+
82+static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long cnt)
83+{
84+ writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
85+}
86+
87+static int mlb_set_state_periodic(struct clock_event_device *clk)
88+{
89+ struct timer_of *to = to_timer_of(clk);
90+
91+ mlb_evt_timer_stop(to);
92+ mlb_evt_timer_register_count(to, to->of_clk.period);
93+ mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
7494 return 0;
7595 }
7696
7797 static int mlb_set_state_oneshot(struct clock_event_device *clk)
7898 {
7999 struct timer_of *to = to_timer_of(clk);
80− u32 val = MLB_TMR_TMCSR_CSL_DIV2;
81100
82− writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
101+ mlb_evt_timer_stop(to);
102+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
103+ return 0;
104+}
105+
106+static int mlb_set_state_shutdown(struct clock_event_device *clk)
107+{
108+ struct timer_of *to = to_timer_of(clk);
109+
110+ mlb_evt_timer_stop(to);
83111 return 0;
84112 }
85113
@@ -88,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event, · 2 unmodified lines
88116 {
89117 struct timer_of *to = to_timer_of(clk);
90118
91− writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
92− writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
93− MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
94− MLB_TMR_TMCSR_TRG, timer_of_base(to) +
95− MLB_TMR_EVT_TMCSR_OFS);
119+ mlb_evt_timer_stop(to);
120+ mlb_evt_timer_register_count(to, event);
121+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
96122 return 0;
97123 }
98124
99125 static int mlb_config_clock_source(struct timer_of *to)
100126 {
101− writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
102− writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
127+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
128+
129+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
103130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
104131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
105− writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
106− MLB_TMR_SRC_TMCSR_OFS);
132+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
133+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
107134 return 0;
108135 }
109136
@@ -123,6 +150,7 @@ static struct timer_of to = { · 13 unmodified lines
123150 .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
124151 .set_state_oneshot = mlb_set_state_oneshot,
125152 .set_state_periodic = mlb_set_state_periodic,
153+ .set_state_shutdown = mlb_set_state_shutdown,
126154 .set_next_event = mlb_clkevt_next_event,
127155 },
128156
drivers/clocksource/timer-sun4i.c+4−1
@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) · 185 unmodified lines
186186 */
187187 if (of_machine_is_compatible("allwinner,sun4i-a10") ||
188188 of_machine_is_compatible("allwinner,sun5i-a13") ||
189− of_machine_is_compatible("allwinner,sun5i-a10s"))
189+ of_machine_is_compatible("allwinner,sun5i-a10s") ||
190+ of_machine_is_compatible("allwinner,suniv-f1c100s"))
190191 sched_clock_register(sun4i_timer_sched_read, 32,
191192 timer_of_rate(&to));
192193
@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node) · 25 unmodified lines
218219 }
219220 TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
220221 sun4i_timer_init);
222+TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
223+ sun4i_timer_init);
drivers/clocksource/timer-tegra20.c+20−43
@@ -60,9 +60,6 @@ · 59 unmodified lines
6060 static u32 usec_config;
6161 static void __iomem *timer_reg_base;
6262 #ifdef CONFIG_ARM
63−static void __iomem *rtc_base;
64−static struct timespec64 persistent_ts;
65−static u64 persistent_ms, last_persistent_ms;
6663 static struct delay_timer tegra_delay_timer;
6764 #endif
6865
@@ -199,40 +196,30 @@ static unsigned long tegra_delay_timer_read_counter_long(void) · 130 unmodified lines
199196 return readl(timer_reg_base + TIMERUS_CNTR_1US);
200197 }
201198
199+static struct timer_of suspend_rtc_to = {
200+ .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
201+};
202+
202203 /*
203204 * tegra_rtc_read - Reads the Tegra RTC registers
204205 * Care must be taken that this funciton is not called while the
205206 * tegra_rtc driver could be executing to avoid race conditions
206207 * on the RTC shadow register
207208 */
208−static u64 tegra_rtc_read_ms(void)
209+static u64 tegra_rtc_read_ms(struct clocksource *cs)
209210 {
210− u32 ms = readl(rtc_base + RTC_MILLISECONDS);
211− u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
211+ u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
212+ u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
212213 return (u64)s * MSEC_PER_SEC + ms;
213214 }
214215
215−/*
216− * tegra_read_persistent_clock64 - Return time from a persistent clock.
217− *
218− * Reads the time from a source which isn't disabled during PM, the
219− * 32k sync timer. Convert the cycles elapsed since last read into
220− * nsecs and adds to a monotonically increasing timespec64.
221− * Care must be taken that this funciton is not called while the
222− * tegra_rtc driver could be executing to avoid race conditions
223− * on the RTC shadow register
224− */
225−static void tegra_read_persistent_clock64(struct timespec64 *ts)
226−{
227− u64 delta;
228−
229− last_persistent_ms = persistent_ms;
230− persistent_ms = tegra_rtc_read_ms();
231− delta = persistent_ms - last_persistent_ms;
232−
233− timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
234− *ts = persistent_ts;
235−}
216+static struct clocksource suspend_rtc_clocksource = {
217+ .name = "tegra_suspend_timer",
218+ .rating = 200,
219+ .read = tegra_rtc_read_ms,
220+ .mask = CLOCKSOURCE_MASK(32),
221+ .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
222+};
236223 #endif
237224
238225 static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
@@ -385,25 +372,15 @@ out: · 146 unmodified lines
385372
386373 static int __init tegra20_init_rtc(struct device_node *np)
387374 {
388− struct clk *clk;
375+ int ret;
389376
390− rtc_base = of_iomap(np, 0);
391− if (!rtc_base) {
392− pr_err("Can't map RTC registers\n");
393− return -ENXIO;
394− }
377+ ret = timer_of_init(np, &suspend_rtc_to);
378+ if (ret)
379+ return ret;
395380
396− /*
397− * rtc registers are used by read_persistent_clock, keep the rtc clock
398− * enabled
399− */
400− clk = of_clk_get(np, 0);
401− if (IS_ERR(clk))
402− pr_warn("Unable to get rtc-tegra clock\n");
403− else
404− clk_prepare_enable(clk);
381+ clocksource_register_hz(&suspend_rtc_clocksource, 1000);
405382
406− return register_persistent_clock(tegra_read_persistent_clock64);
383+ return 0;
407384 }
408385 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
409386 #endif
drivers/misc/Kconfig+0−24
@@ -59,30 +59,6 @@ config ATMEL_TCLIB · 58 unmodified lines
5959 blocks found on many Atmel processors. This facilitates using
6060 these blocks by different drivers despite processor differences.
6161
62−config ATMEL_TCB_CLKSRC
63− bool "TC Block Clocksource"
64− depends on ATMEL_TCLIB
65− default y
66− help
67− Select this to get a high precision clocksource based on a
68− TC block with a 5+ MHz base clock rate. Two timer channels
69− are combined to make a single 32-bit timer.
70−
71− When GENERIC_CLOCKEVENTS is defined, the third timer channel
72− may be used as a clock event device supporting oneshot mode
73− (delays of up to two seconds) based on the 32 KiHz clock.
74−
75−config ATMEL_TCB_CLKSRC_BLOCK
76− int
77− depends on ATMEL_TCB_CLKSRC
78− default 0
79− range 0 1
80− help
81− Some chips provide more than one TC block, so you have the
82− choice of which one to use for the clock framework. The other
83− TC can be used for other purposes, such as PWM generation and
84− interval timing.
85−
8662 config DUMMY_IRQ
8763 tristate "Dummy IRQ handler"
8864 default n
drivers/misc/atmel_tclib.c+4−1
@@ -1,4 +1,3 @@
1−#include <linux/atmel_tc.h>
21 #include <linux/clk.h>
32 #include <linux/err.h>
43 #include <linux/init.h>
@@ -10,6 +9,7 @@ · 5 unmodified lines
109 #include <linux/slab.h>
1110 #include <linux/export.h>
1211 #include <linux/of.h>
12+#include <soc/at91/atmel_tcb.h>
1313
1414 /*
1515 * This is a thin library to solve the problem of how to portably allocate
@@ -111,6 +111,9 @@ static int __init tc_probe(struct platform_device *pdev) · 95 unmodified lines
111111 struct resource *r;
112112 unsigned int i;
113113
114+ if (of_get_child_count(pdev->dev.of_node))
115+ return -EBUSY;
116+
114117 irq = platform_get_irq(pdev, 0);
115118 if (irq < 0)
116119 return -EINVAL;
drivers/pwm/pwm-atmel-tcb.c+1−1
@@ -17,10 +17,10 @@ · 16 unmodified lines
1717 #include <linux/ioport.h>
1818 #include <linux/io.h>
1919 #include <linux/platform_device.h>
20−#include <linux/atmel_tc.h>
2120 #include <linux/pwm.h>
2221 #include <linux/of_device.h>
2322 #include <linux/slab.h>
23+#include <soc/at91/atmel_tcb.h>
2424
2525 #define NPWM 6
2626
include/soc/at91/atmel_tcb.hrenamed from include/linux/atmel_tc.h+2−2
@@ -7,8 +7,8 @@ · 6 unmodified lines
77 * (at your option) any later version.
88 */
99
10−#ifndef ATMEL_TC_H
11−#define ATMEL_TC_H
10+#ifndef __SOC_ATMEL_TCB_H
11+#define __SOC_ATMEL_TCB_H
1212
1313 #include <linux/compiler.h>
1414 #include <linux/list.h>