Merge tag 'spi-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown: "The main focus of this release from a framework point of view has been spi-mem where we've acquired support for a few new hardware features which enable better performance on suitable hardware. Otherwise mostly thanks to Arnd's cleanup efforts on old platforms we've removed several obsolete drivers which just about balance out the newer drivers we've added this cycle. Summary: - Allow drivers to flag if they are unidirectional. - Support for DTR mode and hardware acceleration of dummy cycles in spi-mem. - Support for Allwinder H616, Intel Lightning Mountain, nVidia Tegra QuadSPI, Realtek RTL838x and RTL839x. - Removal of obsolete EFM32, Txx9 and SIRF Prima and Atlas drivers" * tag 'spi-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (76 commits) spi: Skip zero-length transfers in spi_transfer_one_message() spi: dw: Avoid stack content exposure spi: cadence-quadspi: Use spi_mem_dtr_supports_op() spi: spi-mem: add spi_mem_dtr_supports_op() spi: atmel-quadspi: Disable the QSPI IP at suspend() spi: pxa2xx: Add IDs for the controllers found on Intel Lynxpoint spi: pxa2xx: Fix the controller numbering for Wildcat Point spi: Change provied to provided in the file spi.h spi: mediatek: add set_cs_timing support spi: support CS timing for HW & SW mode spi: add power control when set_cs_timing spi: stm32: make spurious and overrun interrupts visible spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC spi: stm32: defer probe for reset spi: stm32: driver uses reset controller only at init spi: stm32h7: ensure message are smaller than max size spi: stm32: use bitfield macros spi: stm32: do not mandate cs_gpio spi: stm32: properly handle 0 byte transfer spi: clps711xx: remove redundant white-space ...

Linus Torvalds committed 5 years ago

Commit a2590d62 parents d656005 eec262d45 files · +2518 −2544Browse files

Unified · Split

45 files

Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +1 −0
Documentation/devicetree/bindings/spi/cadence-quadspi.txt +1 −0
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +117 −0
Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml +41 −0
Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml +1 −0
Documentation/devicetree/bindings/spi/spi-controller.yaml +4 −2
Documentation/devicetree/bindings/spi/spi-sirf.txt +0 −42
MAINTAINERS +8 −0
drivers/spi/Kconfig +11 −22
drivers/spi/Makefile +2 −3
drivers/spi/atmel-quadspi.c +1 −0
drivers/spi/spi-atmel.c +1 −1
drivers/spi/spi-au1550.c +27 −26
drivers/spi/spi-bcm-qspi.c +1 −1
drivers/spi/spi-bcm2835.c +5 −3
drivers/spi/spi-bcm2835aux.c +1 −1
drivers/spi/spi-cadence-quadspi.c +290 −43
drivers/spi/spi-clps711x.c +1 −1
drivers/spi/spi-dw-bt1.c +1 −1
drivers/spi/spi-efm32.c +0 −462
drivers/spi/spi-fsl-spi.c +1 −1
drivers/spi/spi-hisi-sfc-v3xx.c +26 −7
drivers/spi/spi-imx.c +1 −1
drivers/spi/spi-mem.c +20 −3
drivers/spi/spi-mpc52xx.c +3 −1
drivers/spi/spi-mt65xx.c +56 −16
drivers/spi/spi-orion.c +50 −5
drivers/spi/spi-pxa2xx-pci.c +21 −8
drivers/spi/spi-pxa2xx.c +4 −0
drivers/spi/spi-qcom-qspi.c +1 −2
drivers/spi/spi-realtek-rtl.c +209 −0
drivers/spi/spi-rockchip.c +1 −1
drivers/spi/spi-rpc-if.c +5 −8
drivers/spi/spi-sh-msiof.c +11 −3
drivers/spi/spi-sirf.c +0 −1236
drivers/spi/spi-stm32.c +60 −90
drivers/spi/spi-synquacer.c +4 −0
drivers/spi/spi-tegra210-quad.c +1410 −0
drivers/spi/spi-txx9.c +0 −477
drivers/spi/spi.c +48 −11
include/linux/platform_data/efm32-spi.h +0 −15
include/linux/spi/spi-mem.h +9 −0
include/linux/spi/spi.h +22 −22
include/uapi/linux/spi/spi.h +41 −0
include/uapi/linux/spi/spidev.h +1 −29

Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml+1−0

@@ -25,6 +25,7 @@ properties: · 24 unmodified lines
25	25	- enum:
26	26	- allwinner,sun8i-r40-spi
27	27	- allwinner,sun50i-h6-spi
	28	+ - allwinner,sun50i-h616-spi
28	29	- const: allwinner,sun8i-h3-spi
29	30
30	31	reg:

Documentation/devicetree/bindings/spi/cadence-quadspi.txtrenamed from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt+1−0

@@ -5,6 +5,7 @@ Required properties: · 4 unmodified lines
5	5	Generic default - "cdns,qspi-nor".
6	6	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7	7	For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
	8	+ For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
8	9	- reg : Contains two entries, each of which is a tuple consisting of a
9	10	physical address and length. The first entry is the address and
10	11	length of the controller register set. The second entry is the

Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml+117−0

@@ -0,0 +1,117 @@
	1	+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Tegra Quad SPI Controller
	8	+
	9	+maintainers:
	10	+ - Thierry Reding <thierry.reding@gmail.com>
	11	+ - Jonathan Hunter <jonathanh@nvidia.com>
	12	+
	13	+allOf:
	14	+ - $ref: "spi-controller.yaml#"
	15	+
	16	+properties:
	17	+ compatible:
	18	+ enum:
	19	+ - nvidia,tegra210-qspi
	20	+ - nvidia,tegra186-qspi
	21	+ - nvidia,tegra194-qspi
	22	+
	23	+ reg:
	24	+ maxItems: 1
	25	+
	26	+ interrupts:
	27	+ maxItems: 1
	28	+
	29	+ clock-names:
	30	+ items:
	31	+ - const: qspi
	32	+ - const: qspi_out
	33	+
	34	+ clocks:
	35	+ maxItems: 2
	36	+
	37	+ resets:
	38	+ maxItems: 1
	39	+
	40	+ dmas:
	41	+ maxItems: 2
	42	+
	43	+ dma-names:
	44	+ items:
	45	+ - const: rx
	46	+ - const: tx
	47	+
	48	+patternProperties:
	49	+ "@[0-9a-f]+":
	50	+ type: object
	51	+
	52	+ properties:
	53	+ spi-rx-bus-width:
	54	+ enum: [1, 2, 4]
	55	+
	56	+ spi-tx-bus-width:
	57	+ enum: [1, 2, 4]
	58	+
	59	+ nvidia,tx-clk-tap-delay:
	60	+ description:
	61	+ Delays the clock going out to device with this tap value.
	62	+ Tap value varies based on platform design trace lengths from Tegra
	63	+ QSPI to corresponding slave device.
	64	+ $ref: /schemas/types.yaml#/definitions/uint32
	65	+ minimum: 0
	66	+ maximum: 31
	67	+
	68	+ nvidia,rx-clk-tap-delay:
	69	+ description:
	70	+ Delays the clock coming in from the device with this tap value.
	71	+ Tap value varies based on platform design trace lengths from Tegra
	72	+ QSPI to corresponding slave device.
	73	+ $ref: /schemas/types.yaml#/definitions/uint32
	74	+ minimum: 0
	75	+ maximum: 255
	76	+
	77	+ required:
	78	+ - reg
	79	+
	80	+required:
	81	+ - compatible
	82	+ - reg
	83	+ - interrupts
	84	+ - clock-names
	85	+ - clocks
	86	+ - resets
	87	+
	88	+unevaluatedProperties: false
	89	+
	90	+examples:
	91	+ - \|
	92	+ #include <dt-bindings/clock/tegra210-car.h>
	93	+ #include <dt-bindings/reset/tegra210-car.h>
	94	+ #include <dt-bindings/interrupt-controller/arm-gic.h>
	95	+ spi@70410000 {
	96	+ compatible = "nvidia,tegra210-qspi";
	97	+ reg = <0x70410000 0x1000>;
	98	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	99	+ #address-cells = <1>;
	100	+ #size-cells = <0>;
	101	+ clocks = <&tegra_car TEGRA210_CLK_QSPI>,
	102	+ <&tegra_car TEGRA210_CLK_QSPI_PM>;
	103	+ clock-names = "qspi", "qspi_out";
	104	+ resets = <&tegra_car 211>;
	105	+ dmas = <&apbdma 5>, <&apbdma 5>;
	106	+ dma-names = "rx", "tx";
	107	+
	108	+ flash@0 {
	109	+ compatible = "spi-nor";
	110	+ reg = <0>;
	111	+ spi-max-frequency = <104000000>;
	112	+ spi-tx-bus-width = <2>;
	113	+ spi-rx-bus-width = <2>;
	114	+ nvidia,tx-clk-tap-delay = <0>;
	115	+ nvidia,rx-clk-tap-delay = <0>;
	116	+ };
	117	+ };

Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml+41−0

@@ -0,0 +1,41 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/spi/realtek,rtl-spi.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Realtek RTL838x/RTL839x SPI controller
	8	+
	9	+maintainers:
	10	+ - Bert Vermeulen <bert@biot.com>
	11	+ - Birger Koblitz <mail@birger-koblitz.de>
	12	+
	13	+allOf:
	14	+ - $ref: "spi-controller.yaml#"
	15	+
	16	+properties:
	17	+ compatible:
	18	+ oneOf:
	19	+ - const: realtek,rtl8380-spi
	20	+ - const: realtek,rtl8382-spi
	21	+ - const: realtek,rtl8391-spi
	22	+ - const: realtek,rtl8392-spi
	23	+ - const: realtek,rtl8393-spi
	24	+
	25	+ reg:
	26	+ maxItems: 1
	27	+
	28	+required:
	29	+ - compatible
	30	+ - reg
	31	+
	32	+unevaluatedProperties: false
	33	+
	34	+examples:
	35	+ - \|
	36	+ spi: spi@1200 {
	37	+ compatible = "realtek,rtl8382-spi";
	38	+ reg = <0x1200 0x100>;
	39	+ #address-cells = <1>;
	40	+ #size-cells = <0>;
	41	+ };

Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml+1−0

@@ -47,6 +47,7 @@ properties: · 46 unmodified lines
47	47	- renesas,msiof-r8a77980 # R-Car V3H
48	48	- renesas,msiof-r8a77990 # R-Car E3
49	49	- renesas,msiof-r8a77995 # R-Car D3
	50	+ - renesas,msiof-r8a779a0 # R-Car V3U
50	51	- const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2
51	52	# compatible device
52	53	- items:

Documentation/devicetree/bindings/spi/spi-controller.yaml+4−2

@@ -152,8 +152,9 @@ patternProperties: · 151 unmodified lines
152	152	spi-rx-bus-width:
153	153	description:
154	154	Bus width to the SPI bus used for read transfers.
	155	+ If 0 is provided, then no RX will be possible on this device.
155	156	$ref: /schemas/types.yaml#/definitions/uint32
156		− enum: [1, 2, 4, 8]
	157	+ enum: [0, 1, 2, 4, 8]
157	158	default: 1
158	159
159	160	spi-rx-delay-us:
@@ -163,8 +164,9 @@ patternProperties: · 3 unmodified lines
163	164	spi-tx-bus-width:
164	165	description:
165	166	Bus width to the SPI bus used for write transfers.
	167	+ If 0 is provided, then no TX will be possible on this device.
166	168	$ref: /schemas/types.yaml#/definitions/uint32
167		− enum: [1, 2, 4, 8]
	169	+ enum: [0, 1, 2, 4, 8]
168	170	default: 1
169	171
170	172	spi-tx-delay-us:

Documentation/devicetree/bindings/spi/spi-sirf.txt+0−42

@@ -1,42 +0,0 @@
1		−* CSR SiRFprimaII Serial Peripheral Interface
2		−
3		−Required properties:
4		−- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp"
5		− or "sirf,atlas7-usp"
6		−- reg : Offset and length of the register set for the device
7		−- interrupts : Should contain SPI interrupt
8		−- resets: phandle to the reset controller asserting this device in
9		− reset
10		− See ../reset/reset.txt for details.
11		−- dmas : Must contain an entry for each entry in clock-names.
12		− See ../dma/dma.txt for details.
13		−- dma-names : Must include the following entries:
14		− - rx
15		− - tx
16		−- clocks : Must contain an entry for each entry in clock-names.
17		− See ../clocks/clock-bindings.txt for details.
18		−
19		−- #address-cells: Number of cells required to define a chip select
20		− address on the SPI bus. Should be set to 1.
21		−- #size-cells: Should be zero.
22		−
23		−Optional properties:
24		−- spi-max-frequency: Specifies maximum SPI clock frequency,
25		− Units - Hz. Definition as per
26		− Documentation/devicetree/bindings/spi/spi-bus.txt
27		−- cs-gpios: should specify GPIOs used for chipselects.
28		−
29		−Example:
30		−
31		−spi0: spi@b00d0000 {
32		− compatible = "sirf,prima2-spi";
33		− reg = <0xb00d0000 0x10000>;
34		− interrupts = <15>;
35		− dmas = <&dmac1 9>,
36		− <&dmac1 4>;
37		− dma-names = "rx", "tx";
38		− #address-cells = <1>;
39		− #size-cells = <0>;
40		− clocks = <&clks 19>;
41		− resets = <&rstc 26>;
42		−};

MAINTAINERS+8−0

@@ -17537,6 +17537,14 @@ M: Laxman Dewangan <ldewangan@nvidia.com> · 17536 unmodified lines
17537	17537	S: Supported
17538	17538	F: drivers/spi/spi-tegra*
17539	17539
	17540	+TEGRA QUAD SPI DRIVER
	17541	+M: Thierry Reding <thierry.reding@gmail.com>
	17542	+M: Jonathan Hunter <jonathanh@nvidia.com>
	17543	+M: Sowjanya Komatineni <skomatineni@nvidia.com>
	17544	+L: linux-tegra@vger.kernel.org
	17545	+S: Maintained
	17546	+F: drivers/spi/spi-tegra210-quad.c
	17547	+
17540	17548	TEGRA VIDEO DRIVER
17541	17549	M: Thierry Reding <thierry.reding@gmail.com>
17542	17550	M: Jonathan Hunter <jonathanh@nvidia.com>

drivers/spi/Kconfig+11−22

@@ -203,7 +203,7 @@ config SPI_CADENCE · 202 unmodified lines
203	203
204	204	config SPI_CADENCE_QUADSPI
205	205	tristate "Cadence Quad SPI controller"
206		− depends on OF && (ARM \|\| ARM64 \|\| COMPILE_TEST)
	206	+ depends on OF && (ARM \|\| ARM64 \|\| X86 \|\| COMPILE_TEST)
207	207	help
208	208	Enable support for the Cadence Quad SPI Flash controller.
209	209
@@ -292,13 +292,6 @@ config SPI_DLN2 · 82 unmodified lines
292	292	This driver can also be built as a module. If so, the module
293	293	will be called spi-dln2.
294	294
295		−config SPI_EFM32
296		− tristate "EFM32 SPI controller"
297		− depends on OF && ARM && (ARCH_EFM32 \|\| COMPILE_TEST)
298		− select SPI_BITBANG
299		− help
300		− Driver for the spi controller found on Energy Micro's EFM32 SoCs.
301		−
302	295	config SPI_EP93XX
303	296	tristate "Cirrus Logic EP93xx SPI controller"
304	297	depends on ARCH_EP93XX \|\| COMPILE_TEST
@@ -649,7 +642,7 @@ config SPI_RPCIF · 344 unmodified lines
649	642	tristate "Renesas RPC-IF SPI driver"
650	643	depends on RENESAS_RPCIF
651	644	help
652		− SPI driver for Renesas R-Car Gen3 RPC-IF.
	645	+ SPI driver for Renesas R-Car Gen3 or RZ/G2 RPC-IF.
653	646
654	647	config SPI_RSPI
655	648	tristate "Renesas RSPI/QSPI controller"
@@ -750,13 +743,6 @@ config SPI_SIFIVE · 94 unmodified lines
750	743	help
751	744	This exposes the SPI controller IP from SiFive.
752	745
753		−config SPI_SIRF
754		− tristate "CSR SiRFprimaII SPI controller"
755		− depends on SIRF_DMA
756		− select SPI_BITBANG
757		− help
758		− SPI driver for CSR SiRFprimaII SoCs
759		−
760	746	config SPI_SLAVE_MT27XX
761	747	tristate "MediaTek SPI slave device"
762	748	depends on ARCH_MEDIATEK \|\| COMPILE_TEST
@@ -842,6 +828,15 @@ config SPI_MXS · 79 unmodified lines
842	828	help
843	829	SPI driver for Freescale MXS devices.
844	830
	831	+config SPI_TEGRA210_QUAD
	832	+ tristate "NVIDIA Tegra QSPI Controller"
	833	+ depends on ARCH_TEGRA \|\| COMPILE_TEST
	834	+ depends on RESET_CONTROLLER
	835	+ help
	836	+ QSPI driver for NVIDIA Tegra QSPI Controller interface. This
	837	+ controller is different from the SPI controller and is available
	838	+ on Tegra SoCs starting from Tegra210.
	839	+
845	840	config SPI_TEGRA114
846	841	tristate "NVIDIA Tegra114 SPI Controller"
847	842	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) \|\| COMPILE_TEST
@@ -884,12 +879,6 @@ config SPI_TOPCLIFF_PCH · 36 unmodified lines
884	879	This driver also supports the ML7213/ML7223/ML7831, a companion chip
885	880	for the Atom E6xx series and compatible with the Intel EG20T PCH.
886	881
887		−config SPI_TXX9
888		− tristate "Toshiba TXx9 SPI controller"
889		− depends on GPIOLIB && (CPU_TX49XX \|\| COMPILE_TEST)
890		− help
891		− SPI driver for Toshiba TXx9 MIPS SoCs
892		−
893	882	config SPI_UNIPHIER
894	883	tristate "Socionext UniPhier SPI Controller"
895	884	depends on (ARCH_UNIPHIER \|\| COMPILE_TEST) && OF

drivers/spi/Makefile+2−3

@@ -42,7 +42,6 @@ spi-dw-$(CONFIG_SPI_DW_DMA) += spi-dw-dma.o · 41 unmodified lines
42	42	obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.o
43	43	obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
44	44	obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
45		−obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
46	45	obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
47	46	obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
48	47	obj-$(CONFIG_SPI_FSI) += spi-fsi.o
@@ -94,6 +93,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o · 45 unmodified lines
94	93	obj-$(CONFIG_SPI_QUP) += spi-qup.o
95	94	obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
96	95	obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
	96	+obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
97	97	obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
98	98	obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
99	99	obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
@@ -105,7 +105,6 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o · 5 unmodified lines
105	105	obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
106	106	obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
107	107	obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
108		−obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
109	108	obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
110	109	obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
111	110	obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
@@ -115,6 +114,7 @@ obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o · 3 unmodified lines
115	114	obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
116	115	obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
117	116	obj-$(CONFIG_SPI_SYNQUACER) += spi-synquacer.o
	117	+obj-$(CONFIG_SPI_TEGRA210_QUAD) += spi-tegra210-quad.o
118	118	obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
119	119	obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
120	120	obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
@@ -122,7 +122,6 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o · 1 unmodified line
122	122	spi-thunderx-objs := spi-cavium.o spi-cavium-thunderx.o
123	123	obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
124	124	obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
125		−obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
126	125	obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
127	126	obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
128	127	obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o

drivers/spi/atmel-quadspi.c+1−0

@@ -657,6 +657,7 @@ static int __maybe_unused atmel_qspi_suspend(struct device *dev) · 656 unmodified lines
657	657	struct spi_controller *ctrl = dev_get_drvdata(dev);
658	658	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
659	659
	660	+ atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
660	661	clk_disable_unprepare(aq->qspick);
661	662	clk_disable_unprepare(aq->pclk);
662	663

drivers/spi/spi-atmel.c+1−1

@@ -1590,7 +1590,7 @@ static int atmel_spi_probe(struct platform_device *pdev) · 1589 unmodified lines
1590	1590	if (ret == 0) {
1591	1591	as->use_dma = true;
1592	1592	} else if (ret == -EPROBE_DEFER) {
1593		− return ret;
	1593	+ goto out_unmap_regs;
1594	1594	}
1595	1595	} else if (as->caps.has_pdc_support) {
1596	1596	as->use_pdc = true;

drivers/spi/spi-au1550.c+27−26

@@ -26,7 +26,7 @@ · 25 unmodified lines
26	26
27	27	#include <asm/mach-au1x00/au1550_spi.h>
28	28
29		−static unsigned usedma = 1;
	29	+static unsigned int usedma = 1;
30	30	module_param(usedma, uint, 0644);
31	31
32	32	/*
@@ -43,9 +43,9 @@ struct au1550_spi { · 10 unmodified lines
43	43	volatile psc_spi_t __iomem *regs;
44	44	int irq;
45	45
46		− unsigned len;
47		− unsigned tx_count;
48		− unsigned rx_count;
	46	+ unsigned int len;
	47	+ unsigned int tx_count;
	48	+ unsigned int rx_count;
49	49	const u8 *tx;
50	50	u8 *rx;
51	51
@@ -56,14 +56,14 @@ struct au1550_spi { · 4 unmodified lines
56	56
57	57	struct completion master_done;
58	58
59		− unsigned usedma;
	59	+ unsigned int usedma;
60	60	u32 dma_tx_id;
61	61	u32 dma_rx_id;
62	62	u32 dma_tx_ch;
63	63	u32 dma_rx_ch;
64	64
65	65	u8 *dma_rx_tmpbuf;
66		− unsigned dma_rx_tmpbuf_size;
	66	+ unsigned int dma_rx_tmpbuf_size;
67	67	u32 dma_rx_tmpbuf_addr;
68	68
69	69	struct spi_master *master;
@@ -74,8 +74,7 @@ struct au1550_spi { · 4 unmodified lines
74	74
75	75
76	76	/* we use an 8-bit memory device for dma transfers to/from spi fifo */
77		−static dbdev_tab_t au1550_spi_mem_dbdev =
78		−{
	77	+static dbdev_tab_t au1550_spi_mem_dbdev = {
79	78	.dev_id = DBDMA_MEM_CHAN,
80	79	.dev_flags = DEV_FLAGS_ANYUSE\|DEV_FLAGS_SYNC,
81	80	.dev_tsize = 0,
@@ -99,7 +98,7 @@ static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw); · 17 unmodified lines
99	98	* BRG valid range is 4..63
100	99	* DIV valid range is 0..3
101	100	*/
102		−static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
	101	+static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
103	102	{
104	103	u32 mainclk_hz = hw->pdata->mainclk_hz;
105	104	u32 div, brg;
@@ -161,7 +160,7 @@ static void au1550_spi_reset_fifos(struct au1550_spi *hw) · 55 unmodified lines
161	160	static void au1550_spi_chipsel(struct spi_device *spi, int value)
162	161	{
163	162	struct au1550_spi *hw = spi_master_get_devdata(spi->master);
164		− unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
	163	+ unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
165	164	u32 cfg, stat;
166	165
167	166	switch (value) {
@@ -221,7 +220,7 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) · 53 unmodified lines
221	220	static int au1550_spi_setupxfer(struct spi_device spi, struct spi_transfer t)
222	221	{
223	222	struct au1550_spi *hw = spi_master_get_devdata(spi->master);
224		− unsigned bpw, hz;
	223	+ unsigned int bpw, hz;
225	224	u32 cfg, stat;
226	225
227	226	if (t) {
@@ -276,7 +275,7 @@ static int au1550_spi_setupxfer(struct spi_device spi, struct spi_transfer t) · 48 unmodified lines
276	275	* spi master done event irq is not generated unless rx fifo is empty (emptied)
277	276	* so we need rx tmp buffer to use for rx dma if user does not provide one
278	277	*/
279		−static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
	278	+static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
280	279	{
281	280	hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
282	281	if (!hw->dma_rx_tmpbuf)
@@ -399,10 +398,10 @@ static int au1550_spi_dma_txrxb(struct spi_device spi, struct spi_transfer t) · 116 unmodified lines
399	398	DMA_FROM_DEVICE);
400	399	}
401	400	/* unmap buffers if mapped above */
402		− if (t->rx_buf && t->rx_dma == 0 )
	401	+ if (t->rx_buf && t->rx_dma == 0)
403	402	dma_unmap_single(hw->dev, dma_rx_addr, t->len,
404	403	DMA_FROM_DEVICE);
405		− if (t->tx_buf && t->tx_dma == 0 )
	404	+ if (t->tx_buf && t->tx_dma == 0)
406	405	dma_unmap_single(hw->dev, dma_tx_addr, t->len,
407	406	DMA_TO_DEVICE);
408	407
@@ -447,8 +446,8 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) · 38 unmodified lines
447	446	"dma transfer: receive FIFO overflow!\n");
448	447	else
449	448	dev_err(hw->dev,
450		− "dma transfer: unexpected SPI error "
451		− "(event=0x%x stat=0x%x)!\n", evnt, stat);
	449	+ "dma transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
	450	+ evnt, stat);
452	451
453	452	complete(&hw->master_done);
454	453	return IRQ_HANDLED;
@@ -493,12 +492,12 @@ static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ · 38 unmodified lines
493	492	wmb(); /* drain writebuffer */ \
494	493	}
495	494
496		−AU1550_SPI_RX_WORD(8,0xff)
497		−AU1550_SPI_RX_WORD(16,0xffff)
498		−AU1550_SPI_RX_WORD(32,0xffffff)
499		−AU1550_SPI_TX_WORD(8,0xff)
500		−AU1550_SPI_TX_WORD(16,0xffff)
501		−AU1550_SPI_TX_WORD(32,0xffffff)
	495	+AU1550_SPI_RX_WORD(8, 0xff)
	496	+AU1550_SPI_RX_WORD(16, 0xffff)
	497	+AU1550_SPI_RX_WORD(32, 0xffffff)
	498	+AU1550_SPI_TX_WORD(8, 0xff)
	499	+AU1550_SPI_TX_WORD(16, 0xffff)
	500	+AU1550_SPI_TX_WORD(32, 0xffffff)
502	501
503	502	static int au1550_spi_pio_txrxb(struct spi_device spi, struct spi_transfer t)
504	503	{
@@ -567,8 +566,8 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) · 62 unmodified lines
567	566	au1550_spi_mask_ack_all(hw);
568	567	au1550_spi_reset_fifos(hw);
569	568	dev_err(hw->dev,
570		− "pio transfer: unexpected SPI error "
571		− "(event=0x%x stat=0x%x)!\n", evnt, stat);
	569	+ "pio transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
	570	+ evnt, stat);
572	571	complete(&hw->master_done);
573	572	return IRQ_HANDLED;
574	573	}
@@ -636,12 +635,14 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) · 61 unmodified lines
636	635	static int au1550_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
637	636	{
638	637	struct au1550_spi *hw = spi_master_get_devdata(spi->master);
	638	+
639	639	return hw->txrx_bufs(spi, t);
640	640	}
641	641
642	642	static irqreturn_t au1550_spi_irq(int irq, void *dev)
643	643	{
644	644	struct au1550_spi *hw = dev;
	645	+
645	646	return hw->irq_callback(hw);
646	647	}
647	648
@@ -872,6 +873,7 @@ static int au1550_spi_probe(struct platform_device *pdev) · 224 unmodified lines
872	873	{
873	874	int min_div = (2 << 0) * (2 * (4 + 1));
874	875	int max_div = (2 << 3) * (2 * (63 + 1));
	876	+
875	877	master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
876	878	master->min_speed_hz =
877	879	hw->pdata->mainclk_hz / (max_div + 1) + 1;
@@ -972,8 +974,7 @@ static int __init au1550_spi_init(void) · 94 unmodified lines
972	974	if (usedma) {
973	975	ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
974	976	if (!ddma_memid)
975		− printk(KERN_ERR "au1550-spi: cannot add memory"
976		− "dbdma device\n");
	977	+ printk(KERN_ERR "au1550-spi: cannot add memory dbdma device\n");
977	978	}
978	979	return platform_driver_register(&au1550_spi_drv);
979	980	}

drivers/spi/spi-bcm-qspi.c+1−1

@@ -881,7 +881,7 @@ static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi, · 880 unmodified lines
881	881	* when using flex mode we need to send
882	882	* the upper address byte to bspi
883	883	*/
884		− if (bcm_qspi_bspi_ver_three(qspi) == false) {
	884	+ if (!bcm_qspi_bspi_ver_three(qspi)) {
885	885	addr = from & 0xff000000;
886	886	bcm_qspi_write(qspi, BSPI,
887	887	BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);

drivers/spi/spi-bcm2835.c+5−3

@@ -386,7 +386,7 @@ static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) · 385 unmodified lines
386	386	/* Transfer complete - reset SPI HW */
387	387	bcm2835_spi_reset_hw(bs);
388	388	/* wake up the framework */
389		− complete(&bs->ctlr->xfer_completion);
	389	+ spi_finalize_current_transfer(bs->ctlr);
390	390	}
391	391
392	392	return IRQ_HANDLED;
@@ -608,7 +608,7 @@ static void bcm2835_spi_dma_rx_done(void *data) · 215 unmodified lines
608	608	bcm2835_spi_reset_hw(bs);
609	609
610	610	/* and mark as completed */;
611		− complete(&ctlr->xfer_completion);
	611	+ spi_finalize_current_transfer(ctlr);
612	612	}
613	613
614	614	/**
@@ -640,7 +640,7 @@ static void bcm2835_spi_dma_tx_done(void *data) · 25 unmodified lines
640	640
641	641	bcm2835_spi_undo_prologue(bs);
642	642	bcm2835_spi_reset_hw(bs);
643		− complete(&ctlr->xfer_completion);
	643	+ spi_finalize_current_transfer(ctlr);
644	644	}
645	645
646	646	/**
@@ -1307,6 +1307,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev) · 660 unmodified lines
1307	1307	return dev_err_probe(&pdev->dev, PTR_ERR(bs->clk),
1308	1308	"could not get clk\n");
1309	1309
	1310	+ ctlr->max_speed_hz = clk_get_rate(bs->clk) / 2;
	1311	+
1310	1312	bs->irq = platform_get_irq(pdev, 0);
1311	1313	if (bs->irq <= 0)
1312	1314	return bs->irq ? bs->irq : -ENODEV;

drivers/spi/spi-bcm2835aux.c+1−1

@@ -254,7 +254,7 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) · 253 unmodified lines
254	254	/* and if rx_len is 0 then disable interrupts and wake up completion */
255	255	if (!bs->rx_len) {
256	256	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
257		− complete(&master->xfer_completion);
	257	+ spi_finalize_current_transfer(master);
258	258	}
259	259
260	260	return IRQ_HANDLED;

drivers/spi/spi-cadence-quadspi.c+290−43

@@ -52,6 +52,7 @@ struct cqspi_flash_pdata { · 51 unmodified lines
52	52	u8 inst_width;
53	53	u8 addr_width;
54	54	u8 data_width;
	55	+ bool dtr;
55	56	u8 cs;
56	57	};
57	58
@@ -75,6 +76,7 @@ struct cqspi_st { · 17 unmodified lines
75	76	bool is_decoded_cs;
76	77	u32 fifo_depth;
77	78	u32 fifo_width;
	79	+ u32 num_chipselect;
78	80	bool rclk_en;
79	81	u32 trigger_address;
80	82	u32 wr_delay;
@@ -111,6 +113,8 @@ struct cqspi_driver_platdata { · 30 unmodified lines
111	113	#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
112	114	#define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
113	115	#define CQSPI_REG_CONFIG_BAUD_LSB 19
	116	+#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
	117	+#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
114	118	#define CQSPI_REG_CONFIG_IDLE_LSB 31
115	119	#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
116	120	#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
@@ -173,6 +177,9 @@ struct cqspi_driver_platdata { · 56 unmodified lines
173	177	#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
174	178	#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
175	179
	180	+#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
	181	+#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
	182	+
176	183	#define CQSPI_REG_IRQSTATUS 0x40
177	184	#define CQSPI_REG_IRQMASK 0x44
178	185
@@ -188,6 +195,7 @@ struct cqspi_driver_platdata { · 9 unmodified lines
188	195	#define CQSPI_REG_CMDCTRL 0x90
189	196	#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
190	197	#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
	198	+#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
191	199	#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
192	200	#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
193	201	#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
@@ -198,6 +206,7 @@ struct cqspi_driver_platdata { · 4 unmodified lines
198	206	#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
199	207	#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
200	208	#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
	209	+#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
201	210
202	211	#define CQSPI_REG_INDIRECTWR 0x70
203	212	#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
@@ -214,6 +223,14 @@ struct cqspi_driver_platdata { · 10 unmodified lines
214	223	#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
215	224	#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
216	225
	226	+#define CQSPI_REG_POLLING_STATUS 0xB0
	227	+#define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
	228	+
	229	+#define CQSPI_REG_OP_EXT_LOWER 0xE0
	230	+#define CQSPI_REG_OP_EXT_READ_LSB 24
	231	+#define CQSPI_REG_OP_EXT_WRITE_LSB 16
	232	+#define CQSPI_REG_OP_EXT_STIG_LSB 0
	233	+
217	234	/* Interrupt status bits */
218	235	#define CQSPI_REG_IRQ_MODE_ERR BIT(0)
219	236	#define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
@@ -288,6 +305,80 @@ static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) · 68 unmodified lines
288	305	return rdreg;
289	306	}
290	307
	308	+static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
	309	+{
	310	+ unsigned int dummy_clk;
	311	+
	312	+ dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
	313	+ if (dtr)
	314	+ dummy_clk /= 2;
	315	+
	316	+ return dummy_clk;
	317	+}
	318	+
	319	+static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
	320	+ const struct spi_mem_op *op)
	321	+{
	322	+ f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
	323	+ f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
	324	+ f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
	325	+ f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
	326	+
	327	+ switch (op->data.buswidth) {
	328	+ case 0:
	329	+ break;
	330	+ case 1:
	331	+ f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
	332	+ break;
	333	+ case 2:
	334	+ f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
	335	+ break;
	336	+ case 4:
	337	+ f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
	338	+ break;
	339	+ case 8:
	340	+ f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
	341	+ break;
	342	+ default:
	343	+ return -EINVAL;
	344	+ }
	345	+
	346	+ /* Right now we only support 8-8-8 DTR mode. */
	347	+ if (f_pdata->dtr) {
	348	+ switch (op->cmd.buswidth) {
	349	+ case 0:
	350	+ break;
	351	+ case 8:
	352	+ f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL;
	353	+ break;
	354	+ default:
	355	+ return -EINVAL;
	356	+ }
	357	+
	358	+ switch (op->addr.buswidth) {
	359	+ case 0:
	360	+ break;
	361	+ case 8:
	362	+ f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL;
	363	+ break;
	364	+ default:
	365	+ return -EINVAL;
	366	+ }
	367	+
	368	+ switch (op->data.buswidth) {
	369	+ case 0:
	370	+ break;
	371	+ case 8:
	372	+ f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
	373	+ break;
	374	+ default:
	375	+ return -EINVAL;
	376	+ }
	377	+ }
	378	+
	379	+ return 0;
	380	+}
	381	+
291	382	static int cqspi_wait_idle(struct cqspi_st *cqspi)
292	383	{
293	384	const unsigned int poll_idle_retry = 3;
@@ -345,19 +436,85 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) · 51 unmodified lines
345	436	return cqspi_wait_idle(cqspi);
346	437	}
347	438
	439	+static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
	440	+ const struct spi_mem_op *op,
	441	+ unsigned int shift)
	442	+{
	443	+ struct cqspi_st *cqspi = f_pdata->cqspi;
	444	+ void __iomem *reg_base = cqspi->iobase;
	445	+ unsigned int reg;
	446	+ u8 ext;
	447	+
	448	+ if (op->cmd.nbytes != 2)
	449	+ return -EINVAL;
	450	+
	451	+ /* Opcode extension is the LSB. */
	452	+ ext = op->cmd.opcode & 0xff;
	453	+
	454	+ reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
	455	+ reg &= ~(0xff << shift);
	456	+ reg \|= ext << shift;
	457	+ writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
	458	+
	459	+ return 0;
	460	+}
	461	+
	462	+static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
	463	+ const struct spi_mem_op *op, unsigned int shift,
	464	+ bool enable)
	465	+{
	466	+ struct cqspi_st *cqspi = f_pdata->cqspi;
	467	+ void __iomem *reg_base = cqspi->iobase;
	468	+ unsigned int reg;
	469	+ int ret;
	470	+
	471	+ reg = readl(reg_base + CQSPI_REG_CONFIG);
	472	+
	473	+ /*
	474	+ * We enable dual byte opcode here. The callers have to set up the
	475	+ * extension opcode based on which type of operation it is.
	476	+ */
	477	+ if (enable) {
	478	+ reg \|= CQSPI_REG_CONFIG_DTR_PROTO;
	479	+ reg \|= CQSPI_REG_CONFIG_DUAL_OPCODE;
	480	+
	481	+ /* Set up command opcode extension. */
	482	+ ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
	483	+ if (ret)
	484	+ return ret;
	485	+ } else {
	486	+ reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
	487	+ reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
	488	+ }
	489	+
	490	+ writel(reg, reg_base + CQSPI_REG_CONFIG);
	491	+
	492	+ return cqspi_wait_idle(cqspi);
	493	+}
	494	+
348	495	static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
349	496	const struct spi_mem_op *op)
350	497	{
351	498	struct cqspi_st *cqspi = f_pdata->cqspi;
352	499	void __iomem *reg_base = cqspi->iobase;
353	500	u8 *rxbuf = op->data.buf.in;
354		− u8 opcode = op->cmd.opcode;
	501	+ u8 opcode;
355	502	size_t n_rx = op->data.nbytes;
356	503	unsigned int rdreg;
357	504	unsigned int reg;
	505	+ unsigned int dummy_clk;
358	506	size_t read_len;
359	507	int status;
360	508
	509	+ status = cqspi_set_protocol(f_pdata, op);
	510	+ if (status)
	511	+ return status;
	512	+
	513	+ status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
	514	+ f_pdata->dtr);
	515	+ if (status)
	516	+ return status;
	517	+
361	518	if (!n_rx \|\| n_rx > CQSPI_STIG_DATA_LEN_MAX \|\| !rxbuf) {
362	519	dev_err(&cqspi->pdev->dev,
363	520	"Invalid input argument, len %zu rxbuf 0x%p\n",
@@ -365,11 +522,24 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, · 1 unmodified line
365	522	return -EINVAL;
366	523	}
367	524
	525	+ if (f_pdata->dtr)
	526	+ opcode = op->cmd.opcode >> 8;
	527	+ else
	528	+ opcode = op->cmd.opcode;
	529	+
368	530	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
369	531
370	532	rdreg = cqspi_calc_rdreg(f_pdata);
371	533	writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
372	534
	535	+ dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
	536	+ if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
	537	+ return -EOPNOTSUPP;
	538	+
	539	+ if (dummy_clk)
	540	+ reg \|= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
	541	+ << CQSPI_REG_CMDCTRL_DUMMY_LSB;
	542	+
373	543	reg \|= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
374	544
375	545	/* 0 means 1 byte. */
@@ -401,12 +571,22 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, · 25 unmodified lines
401	571	{
402	572	struct cqspi_st *cqspi = f_pdata->cqspi;
403	573	void __iomem *reg_base = cqspi->iobase;
404		− const u8 opcode = op->cmd.opcode;
	574	+ u8 opcode;
405	575	const u8 *txbuf = op->data.buf.out;
406	576	size_t n_tx = op->data.nbytes;
407	577	unsigned int reg;
408	578	unsigned int data;
409	579	size_t write_len;
	580	+ int ret;
	581	+
	582	+ ret = cqspi_set_protocol(f_pdata, op);
	583	+ if (ret)
	584	+ return ret;
	585	+
	586	+ ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
	587	+ f_pdata->dtr);
	588	+ if (ret)
	589	+ return ret;
410	590
411	591	if (n_tx > CQSPI_STIG_DATA_LEN_MAX \|\| (n_tx && !txbuf)) {
412	592	dev_err(&cqspi->pdev->dev,
@@ -415,6 +595,14 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, · 2 unmodified lines
415	595	return -EINVAL;
416	596	}
417	597
	598	+ reg = cqspi_calc_rdreg(f_pdata);
	599	+ writel(reg, reg_base + CQSPI_REG_RD_INSTR);
	600	+
	601	+ if (f_pdata->dtr)
	602	+ opcode = op->cmd.opcode >> 8;
	603	+ else
	604	+ opcode = op->cmd.opcode;
	605	+
418	606	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
419	607
420	608	if (op->addr.nbytes) {
@@ -454,14 +642,27 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, · 33 unmodified lines
454	642	void __iomem *reg_base = cqspi->iobase;
455	643	unsigned int dummy_clk = 0;
456	644	unsigned int reg;
	645	+ int ret;
	646	+ u8 opcode;
	647	+
	648	+ ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
	649	+ f_pdata->dtr);
	650	+ if (ret)
	651	+ return ret;
457	652
458		− reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
	653	+ if (f_pdata->dtr)
	654	+ opcode = op->cmd.opcode >> 8;
	655	+ else
	656	+ opcode = op->cmd.opcode;
	657	+
	658	+ reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
459	659	reg \|= cqspi_calc_rdreg(f_pdata);
460	660
461	661	/* Setup dummy clock cycles */
462		− dummy_clk = op->dummy.nbytes * 8;
	662	+ dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
	663	+
463	664	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
464		− dummy_clk = CQSPI_DUMMY_CLKS_MAX;
	665	+ return -EOPNOTSUPP;
465	666
466	667	if (dummy_clk)
467	668	reg \|= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
@@ -573,15 +774,43 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, · 105 unmodified lines
573	774	const struct spi_mem_op *op)
574	775	{
575	776	unsigned int reg;
	777	+ int ret;
576	778	struct cqspi_st *cqspi = f_pdata->cqspi;
577	779	void __iomem *reg_base = cqspi->iobase;
	780	+ u8 opcode;
	781	+
	782	+ ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
	783	+ f_pdata->dtr);
	784	+ if (ret)
	785	+ return ret;
	786	+
	787	+ if (f_pdata->dtr)
	788	+ opcode = op->cmd.opcode >> 8;
	789	+ else
	790	+ opcode = op->cmd.opcode;
578	791
579	792	/* Set opcode. */
580		− reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
	793	+ reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
	794	+ reg \|= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
	795	+ reg \|= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
581	796	writel(reg, reg_base + CQSPI_REG_WR_INSTR);
582	797	reg = cqspi_calc_rdreg(f_pdata);
583	798	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
584	799
	800	+ if (f_pdata->dtr) {
	801	+ /*
	802	+ * Some flashes like the cypress Semper flash expect a 4-byte
	803	+ * dummy address with the Read SR command in DTR mode, but this
	804	+ * controller does not support sending address with the Read SR
	805	+ * command. So, disable write completion polling on the
	806	+ * controller's side. spi-nor will take care of polling the
	807	+ * status register.
	808	+ */
	809	+ reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
	810	+ reg \|= CQSPI_REG_WR_DISABLE_AUTO_POLL;
	811	+ writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
	812	+ }
	813	+
585	814	reg = readl(reg_base + CQSPI_REG_SIZE);
586	815	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
587	816	reg \|= (op->addr.nbytes - 1);
@@ -835,35 +1064,6 @@ static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, · 247 unmodified lines
835	1064	cqspi_controller_enable(cqspi, 1);
836	1065	}
837	1066
838		−static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
839		− const struct spi_mem_op *op)
840		−{
841		− f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
842		− f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
843		− f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
844		−
845		− if (op->data.dir == SPI_MEM_DATA_IN) {
846		− switch (op->data.buswidth) {
847		− case 1:
848		− f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
849		− break;
850		− case 2:
851		− f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
852		− break;
853		− case 4:
854		− f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
855		− break;
856		− case 8:
857		− f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
858		− break;
859		− default:
860		− return -EINVAL;
861		− }
862		− }
863		−
864		− return 0;
865		−}
866		−
867	1067	static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
868	1068	const struct spi_mem_op *op)
869	1069	{
@@ -881,7 +1081,16 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, · 11 unmodified lines
881	1081	if (ret)
882	1082	return ret;
883	1083
884		− if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) {
	1084	+ /*
	1085	+ * Some flashes like the Cypress Semper flash expect a dummy 4-byte
	1086	+ * address (all 0s) with the read status register command in DTR mode.
	1087	+ * But this controller does not support sending dummy address bytes to
	1088	+ * the flash when it is polling the write completion register in DTR
	1089	+ * mode. So, we can not use direct mode when in DTR mode for writing
	1090	+ * data.
	1091	+ */
	1092	+ if (!f_pdata->dtr && cqspi->use_direct_mode &&
	1093	+ ((to + len) <= cqspi->ahb_size)) {
885	1094	memcpy_toio(cqspi->ahb_base + to, buf, len);
886	1095	return cqspi_wait_idle(cqspi);
887	1096	}
@@ -942,7 +1151,7 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, · 54 unmodified lines
942	1151
943	1152	dma_async_issue_pending(cqspi->rx_chan);
944	1153	if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
945		− msecs_to_jiffies(len))) {
	1154	+ msecs_to_jiffies(max_t(size_t, len, 500)))) {
946	1155	dmaengine_terminate_sync(cqspi->rx_chan);
947	1156	dev_err(dev, "DMA wait_for_completion_timeout\n");
948	1157	ret = -ETIMEDOUT;
@@ -1010,6 +1219,26 @@ static int cqspi_exec_mem_op(struct spi_mem mem, const struct spi_mem_op op) · 61 unmodified lines
1010	1219	return ret;
1011	1220	}
1012	1221
	1222	+static bool cqspi_supports_mem_op(struct spi_mem *mem,
	1223	+ const struct spi_mem_op *op)
	1224	+{
	1225	+ bool all_true, all_false;
	1226	+
	1227	+ all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
	1228	+ op->data.dtr;
	1229	+ all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
	1230	+ !op->data.dtr;
	1231	+
	1232	+ /* Mixed DTR modes not supported. */
	1233	+ if (!(all_true \|\| all_false))
	1234	+ return false;
	1235	+
	1236	+ if (all_true)
	1237	+ return spi_mem_dtr_supports_op(mem, op);
	1238	+ else
	1239	+ return spi_mem_default_supports_op(mem, op);
	1240	+}
	1241	+
1013	1242	static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1014	1243	struct cqspi_flash_pdata *f_pdata,
1015	1244	struct device_node *np)
@@ -1070,6 +1299,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) · 54 unmodified lines
1070	1299	return -ENXIO;
1071	1300	}
1072	1301
	1302	+ if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
	1303	+ cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
	1304	+
1073	1305	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1074	1306
1075	1307	return 0;
@@ -1101,10 +1333,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) · 25 unmodified lines
1101	1333	writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1102	1334	cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1103	1335
1104		− /* Enable Direct Access Controller */
1105		− reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1106		− reg \|= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1107		− writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
	1336	+ /* Disable direct access controller */
	1337	+ if (!cqspi->use_direct_mode) {
	1338	+ reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
	1339	+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
	1340	+ writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
	1341	+ }
1108	1342
1109	1343	cqspi_controller_enable(cqspi, 1);
1110	1344	}
@@ -1138,6 +1372,7 @@ static const char cqspi_get_name(struct spi_mem mem) · 27 unmodified lines
1138	1372	static const struct spi_controller_mem_ops cqspi_mem_ops = {
1139	1373	.exec_op = cqspi_exec_mem_op,
1140	1374	.get_name = cqspi_get_name,
	1375	+ .supports_op = cqspi_supports_mem_op,
1141	1376	};
1142	1377
1143	1378	static int cqspi_setup_flash(struct cqspi_st *cqspi)
@@ -1279,13 +1514,14 @@ static int cqspi_probe(struct platform_device *pdev) · 135 unmodified lines
1279	1514	reset_control_deassert(rstc_ocp);
1280	1515
1281	1516	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
	1517	+ master->max_speed_hz = cqspi->master_ref_clk_hz;
1282	1518	ddata = of_device_get_match_data(dev);
1283	1519	if (ddata) {
1284	1520	if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1285		− cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
	1521	+ cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1286	1522	cqspi->master_ref_clk_hz);
1287	1523	if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1288		− master->mode_bits \|= SPI_RX_OCTAL;
	1524	+ master->mode_bits \|= SPI_RX_OCTAL \| SPI_TX_OCTAL;
1289	1525	if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1290	1526	cqspi->use_direct_mode = true;
1291	1527	}
@@ -1302,6 +1538,8 @@ static int cqspi_probe(struct platform_device *pdev) · 10 unmodified lines
1302	1538	cqspi->current_cs = -1;
1303	1539	cqspi->sclk = 0;
1304	1540
	1541	+ master->num_chipselect = cqspi->num_chipselect;
	1542	+
1305	1543	ret = cqspi_setup_flash(cqspi);
1306	1544	if (ret) {
1307	1545	dev_err(dev, "failed to setup flash parameters %d\n", ret);
@@ -1390,6 +1628,10 @@ static const struct cqspi_driver_platdata am654_ospi = { · 82 unmodified lines
1390	1628	.quirks = CQSPI_NEEDS_WR_DELAY,
1391	1629	};
1392	1630
	1631	+static const struct cqspi_driver_platdata intel_lgm_qspi = {
	1632	+ .quirks = CQSPI_DISABLE_DAC_MODE,
	1633	+};
	1634	+
1393	1635	static const struct of_device_id cqspi_dt_ids[] = {
1394	1636	{
1395	1637	.compatible = "cdns,qspi-nor",
@@ -1403,6 +1645,10 @@ static const struct of_device_id cqspi_dt_ids[] = { · 7 unmodified lines
1403	1645	.compatible = "ti,am654-ospi",
1404	1646	.data = &am654_ospi,
1405	1647	},
	1648	+ {
	1649	+ .compatible = "intel,lgm-qspi",
	1650	+ .data = &intel_lgm_qspi,
	1651	+ },
1406	1652	{ /* end of table */ }
1407	1653	};
1408	1654
@@ -1427,3 +1673,4 @@ MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); · 18 unmodified lines
1427	1673	MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1428	1674	MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1429	1675	MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
	1676	+MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");

drivers/spi/spi-clps711x.c+1−1

@@ -104,7 +104,7 @@ static int spi_clps711x_probe(struct platform_device *pdev) · 103 unmodified lines
104	104	master->use_gpio_descriptors = true;
105	105	master->bus_num = -1;
106	106	master->mode_bits = SPI_CPHA \| SPI_CS_HIGH;
107		− master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
	107	+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
108	108	master->dev.of_node = pdev->dev.of_node;
109	109	master->prepare_message = spi_clps711x_prepare_message;
110	110	master->transfer_one = spi_clps711x_transfer_one;

drivers/spi/spi-dw-bt1.c+1−1

@@ -84,7 +84,7 @@ static void dw_spi_bt1_dirmap_copy_from_map(void to, void __iomem from, size_t · 83 unmodified lines
84	84	if (shift) {
85	85	chunk = min_t(size_t, 4 - shift, len);
86	86	data = readl_relaxed(from - shift);
87		− memcpy(to, &data + shift, chunk);
	87	+ memcpy(to, (char *)&data + shift, chunk);
88	88	from += chunk;
89	89	to += chunk;
90	90	len -= chunk;

drivers/spi/spi-efm32.c+0−462

@@ -1,462 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix
4		− */
5		−#include <linux/kernel.h>
6		−#include <linux/io.h>
7		−#include <linux/spi/spi.h>
8		−#include <linux/spi/spi_bitbang.h>
9		−#include <linux/interrupt.h>
10		−#include <linux/platform_device.h>
11		−#include <linux/clk.h>
12		−#include <linux/err.h>
13		−#include <linux/module.h>
14		−#include <linux/platform_data/efm32-spi.h>
15		−#include <linux/of.h>
16		−
17		−#define DRIVER_NAME "efm32-spi"
18		−
19		−#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
20		−
21		−#define REG_CTRL 0x00
22		−#define REG_CTRL_SYNC 0x0001
23		−#define REG_CTRL_CLKPOL 0x0100
24		−#define REG_CTRL_CLKPHA 0x0200
25		−#define REG_CTRL_MSBF 0x0400
26		−#define REG_CTRL_TXBIL 0x1000
27		−
28		−#define REG_FRAME 0x04
29		−#define REG_FRAME_DATABITS__MASK 0x000f
30		−#define REG_FRAME_DATABITS(n) ((n) - 3)
31		−
32		−#define REG_CMD 0x0c
33		−#define REG_CMD_RXEN 0x0001
34		−#define REG_CMD_RXDIS 0x0002
35		−#define REG_CMD_TXEN 0x0004
36		−#define REG_CMD_TXDIS 0x0008
37		−#define REG_CMD_MASTEREN 0x0010
38		−
39		−#define REG_STATUS 0x10
40		−#define REG_STATUS_TXENS 0x0002
41		−#define REG_STATUS_TXC 0x0020
42		−#define REG_STATUS_TXBL 0x0040
43		−#define REG_STATUS_RXDATAV 0x0080
44		−
45		−#define REG_CLKDIV 0x14
46		−
47		−#define REG_RXDATAX 0x18
48		−#define REG_RXDATAX_RXDATA__MASK 0x01ff
49		−#define REG_RXDATAX_PERR 0x4000
50		−#define REG_RXDATAX_FERR 0x8000
51		−
52		−#define REG_TXDATA 0x34
53		−
54		−#define REG_IF 0x40
55		−#define REG_IF_TXBL 0x0002
56		−#define REG_IF_RXDATAV 0x0004
57		−
58		−#define REG_IFS 0x44
59		−#define REG_IFC 0x48
60		−#define REG_IEN 0x4c
61		−
62		−#define REG_ROUTE 0x54
63		−#define REG_ROUTE_RXPEN 0x0001
64		−#define REG_ROUTE_TXPEN 0x0002
65		−#define REG_ROUTE_CLKPEN 0x0008
66		−#define REG_ROUTE_LOCATION__MASK 0x0700
67		−#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
68		−
69		−struct efm32_spi_ddata {
70		− struct spi_bitbang bitbang;
71		−
72		− spinlock_t lock;
73		−
74		− struct clk *clk;
75		− void __iomem *base;
76		− unsigned int rxirq, txirq;
77		− struct efm32_spi_pdata pdata;
78		−
79		− /* irq data */
80		− struct completion done;
81		− const u8 *tx_buf;
82		− u8 *rx_buf;
83		− unsigned tx_len, rx_len;
84		−};
85		−
86		−#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev))
87		−#define efm32_spi_vdbg(ddata, format, arg...) \
88		− dev_vdbg(ddata_to_dev(ddata), format, ##arg)
89		−
90		−static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
91		− u32 value, unsigned offset)
92		−{
93		− writel_relaxed(value, ddata->base + offset);
94		−}
95		−
96		−static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
97		−{
98		− return readl_relaxed(ddata->base + offset);
99		−}
100		−
101		−static int efm32_spi_setup_transfer(struct spi_device *spi,
102		− struct spi_transfer *t)
103		−{
104		− struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
105		−
106		− unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
107		− unsigned speed = t->speed_hz ?: spi->max_speed_hz;
108		− unsigned long clkfreq = clk_get_rate(ddata->clk);
109		− u32 clkdiv;
110		−
111		− efm32_spi_write32(ddata, REG_CTRL_SYNC \| REG_CTRL_MSBF \|
112		− (spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) \|
113		− (spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);
114		−
115		− efm32_spi_write32(ddata,
116		− REG_FRAME_DATABITS(bpw), REG_FRAME);
117		−
118		− if (2 * speed >= clkfreq)
119		− clkdiv = 0;
120		− else
121		− clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);
122		−
123		− if (clkdiv > (1U << 21))
124		− return -EINVAL;
125		−
126		− efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
127		− efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
128		− efm32_spi_write32(ddata, REG_CMD_RXEN \| REG_CMD_TXEN, REG_CMD);
129		−
130		− return 0;
131		−}
132		−
133		−static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
134		−{
135		− u8 val = 0;
136		−
137		− if (ddata->tx_buf) {
138		− val = *ddata->tx_buf;
139		− ddata->tx_buf++;
140		− }
141		−
142		− ddata->tx_len--;
143		− efm32_spi_write32(ddata, val, REG_TXDATA);
144		− efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
145		−}
146		−
147		−static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
148		−{
149		− u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
150		− efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);
151		−
152		− if (ddata->rx_buf) {
153		− *ddata->rx_buf = rxdata;
154		− ddata->rx_buf++;
155		− }
156		−
157		− ddata->rx_len--;
158		−}
159		−
160		−static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
161		−{
162		− while (ddata->tx_len &&
163		− ddata->tx_len + 2 > ddata->rx_len &&
164		− efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
165		− efm32_spi_tx_u8(ddata);
166		− }
167		−}
168		−
169		−static int efm32_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
170		−{
171		− struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
172		− int ret = -EBUSY;
173		−
174		− spin_lock_irq(&ddata->lock);
175		−
176		− if (ddata->tx_buf \|\| ddata->rx_buf)
177		− goto out_unlock;
178		−
179		− ddata->tx_buf = t->tx_buf;
180		− ddata->rx_buf = t->rx_buf;
181		− ddata->tx_len = ddata->rx_len =
182		− t->len * DIV_ROUND_UP(t->bits_per_word, 8);
183		−
184		− efm32_spi_filltx(ddata);
185		−
186		− reinit_completion(&ddata->done);
187		−
188		− efm32_spi_write32(ddata, REG_IF_TXBL \| REG_IF_RXDATAV, REG_IEN);
189		−
190		− spin_unlock_irq(&ddata->lock);
191		−
192		− wait_for_completion(&ddata->done);
193		−
194		− spin_lock_irq(&ddata->lock);
195		−
196		− ret = t->len - max(ddata->tx_len, ddata->rx_len);
197		−
198		− efm32_spi_write32(ddata, 0, REG_IEN);
199		− ddata->tx_buf = ddata->rx_buf = NULL;
200		−
201		−out_unlock:
202		− spin_unlock_irq(&ddata->lock);
203		−
204		− return ret;
205		−}
206		−
207		−static irqreturn_t efm32_spi_rxirq(int irq, void *data)
208		−{
209		− struct efm32_spi_ddata *ddata = data;
210		− irqreturn_t ret = IRQ_NONE;
211		−
212		− spin_lock(&ddata->lock);
213		−
214		− while (ddata->rx_len > 0 &&
215		− efm32_spi_read32(ddata, REG_STATUS) &
216		− REG_STATUS_RXDATAV) {
217		− efm32_spi_rx_u8(ddata);
218		−
219		− ret = IRQ_HANDLED;
220		− }
221		−
222		− if (!ddata->rx_len) {
223		− u32 ien = efm32_spi_read32(ddata, REG_IEN);
224		−
225		− ien &= ~REG_IF_RXDATAV;
226		−
227		− efm32_spi_write32(ddata, ien, REG_IEN);
228		−
229		− complete(&ddata->done);
230		− }
231		−
232		− spin_unlock(&ddata->lock);
233		−
234		− return ret;
235		−}
236		−
237		−static irqreturn_t efm32_spi_txirq(int irq, void *data)
238		−{
239		− struct efm32_spi_ddata *ddata = data;
240		−
241		− efm32_spi_vdbg(ddata,
242		− "%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
243		− __func__, ddata->tx_len, ddata->rx_len,
244		− efm32_spi_read32(ddata, REG_IF),
245		− efm32_spi_read32(ddata, REG_STATUS));
246		−
247		− spin_lock(&ddata->lock);
248		−
249		− efm32_spi_filltx(ddata);
250		−
251		− efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
252		− __func__, ddata->tx_len, ddata->rx_len);
253		−
254		− if (!ddata->tx_len) {
255		− u32 ien = efm32_spi_read32(ddata, REG_IEN);
256		−
257		− ien &= ~REG_IF_TXBL;
258		−
259		− efm32_spi_write32(ddata, ien, REG_IEN);
260		− efm32_spi_vdbg(ddata, "disable TXBL\n");
261		− }
262		−
263		− spin_unlock(&ddata->lock);
264		−
265		− return IRQ_HANDLED;
266		−}
267		−
268		−static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
269		−{
270		− u32 reg = efm32_spi_read32(ddata, REG_ROUTE);
271		−
272		− return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
273		−}
274		−
275		−static void efm32_spi_probe_dt(struct platform_device *pdev,
276		− struct spi_master master, struct efm32_spi_ddata ddata)
277		−{
278		− struct device_node *np = pdev->dev.of_node;
279		− u32 location;
280		− int ret;
281		−
282		− ret = of_property_read_u32(np, "energymicro,location", &location);
283		−
284		− if (ret)
285		− /* fall back to wrongly namespaced property */
286		− ret = of_property_read_u32(np, "efm32,location", &location);
287		−
288		− if (ret)
289		− /* fall back to old and (wrongly) generic property "location" */
290		− ret = of_property_read_u32(np, "location", &location);
291		−
292		− if (!ret) {
293		− dev_dbg(&pdev->dev, "using location %u\n", location);
294		− } else {
295		− /* default to location configured in hardware */
296		− location = efm32_spi_get_configured_location(ddata);
297		−
298		− dev_info(&pdev->dev, "fall back to location %u\n", location);
299		− }
300		−
301		− ddata->pdata.location = location;
302		−}
303		−
304		−static int efm32_spi_probe(struct platform_device *pdev)
305		−{
306		− struct efm32_spi_ddata *ddata;
307		− struct resource *res;
308		− int ret;
309		− struct spi_master *master;
310		− struct device_node *np = pdev->dev.of_node;
311		−
312		− if (!np)
313		− return -EINVAL;
314		−
315		− master = spi_alloc_master(&pdev->dev, sizeof(*ddata));
316		− if (!master) {
317		− dev_dbg(&pdev->dev,
318		− "failed to allocate spi master controller\n");
319		− return -ENOMEM;
320		− }
321		− platform_set_drvdata(pdev, master);
322		−
323		− master->dev.of_node = pdev->dev.of_node;
324		−
325		− master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
326		− master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
327		− master->use_gpio_descriptors = true;
328		−
329		− ddata = spi_master_get_devdata(master);
330		−
331		− ddata->bitbang.master = master;
332		− ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
333		− ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
334		−
335		− spin_lock_init(&ddata->lock);
336		− init_completion(&ddata->done);
337		−
338		− ddata->clk = devm_clk_get(&pdev->dev, NULL);
339		− if (IS_ERR(ddata->clk)) {
340		− ret = PTR_ERR(ddata->clk);
341		− dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
342		− goto err;
343		− }
344		−
345		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
346		− if (!res) {
347		− ret = -ENODEV;
348		− dev_err(&pdev->dev, "failed to determine base address\n");
349		− goto err;
350		− }
351		−
352		− if (resource_size(res) < 0x60) {
353		− ret = -EINVAL;
354		− dev_err(&pdev->dev, "memory resource too small\n");
355		− goto err;
356		− }
357		−
358		− ddata->base = devm_ioremap_resource(&pdev->dev, res);
359		− if (IS_ERR(ddata->base)) {
360		− ret = PTR_ERR(ddata->base);
361		− goto err;
362		− }
363		−
364		− ret = platform_get_irq(pdev, 0);
365		− if (ret <= 0)
366		− goto err;
367		−
368		− ddata->rxirq = ret;
369		−
370		− ret = platform_get_irq(pdev, 1);
371		− if (ret <= 0)
372		− ret = ddata->rxirq + 1;
373		−
374		− ddata->txirq = ret;
375		−
376		− ret = clk_prepare_enable(ddata->clk);
377		− if (ret < 0) {
378		− dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
379		− goto err;
380		− }
381		−
382		− efm32_spi_probe_dt(pdev, master, ddata);
383		−
384		− efm32_spi_write32(ddata, 0, REG_IEN);
385		− efm32_spi_write32(ddata, REG_ROUTE_TXPEN \| REG_ROUTE_RXPEN \|
386		− REG_ROUTE_CLKPEN \|
387		− REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
388		−
389		− ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
390		− 0, DRIVER_NAME " rx", ddata);
391		− if (ret) {
392		− dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
393		− goto err_disable_clk;
394		− }
395		−
396		− ret = request_irq(ddata->txirq, efm32_spi_txirq,
397		− 0, DRIVER_NAME " tx", ddata);
398		− if (ret) {
399		− dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
400		− goto err_free_rx_irq;
401		− }
402		−
403		− ret = spi_bitbang_start(&ddata->bitbang);
404		− if (ret) {
405		− dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
406		−
407		− free_irq(ddata->txirq, ddata);
408		−err_free_rx_irq:
409		− free_irq(ddata->rxirq, ddata);
410		−err_disable_clk:
411		− clk_disable_unprepare(ddata->clk);
412		−err:
413		− spi_master_put(master);
414		− }
415		−
416		− return ret;
417		−}
418		−
419		−static int efm32_spi_remove(struct platform_device *pdev)
420		−{
421		− struct spi_master *master = platform_get_drvdata(pdev);
422		− struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);
423		−
424		− spi_bitbang_stop(&ddata->bitbang);
425		−
426		− efm32_spi_write32(ddata, 0, REG_IEN);
427		−
428		− free_irq(ddata->txirq, ddata);
429		− free_irq(ddata->rxirq, ddata);
430		− clk_disable_unprepare(ddata->clk);
431		− spi_master_put(master);
432		−
433		− return 0;
434		−}
435		−
436		−static const struct of_device_id efm32_spi_dt_ids[] = {
437		− {
438		− .compatible = "energymicro,efm32-spi",
439		− }, {
440		− /* doesn't follow the "vendor,device" scheme, don't use */
441		− .compatible = "efm32,spi",
442		− }, {
443		− /* sentinel */
444		− }
445		−};
446		−MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);
447		−
448		−static struct platform_driver efm32_spi_driver = {
449		− .probe = efm32_spi_probe,
450		− .remove = efm32_spi_remove,
451		−
452		− .driver = {
453		− .name = DRIVER_NAME,
454		− .of_match_table = efm32_spi_dt_ids,
455		− },
456		−};
457		−module_platform_driver(efm32_spi_driver);
458		−
459		−MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
460		−MODULE_DESCRIPTION("EFM32 SPI driver");
461		−MODULE_LICENSE("GPL v2");
462		−MODULE_ALIAS("platform:" DRIVER_NAME);

drivers/spi/spi-fsl-spi.c+1−1

@@ -695,7 +695,7 @@ static void fsl_spi_cs_control(struct spi_device *spi, bool on) · 694 unmodified lines
695	695
696	696	if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
697	697	return;
698		− iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs);
	698	+ iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
699	699	}
700	700	}
701	701

drivers/spi/spi-hisi-sfc-v3xx.c+26−7

@@ -19,6 +19,8 @@ · 18 unmodified lines
19	19
20	20	#define HISI_SFC_V3XX_VERSION (0x1f8)
21	21
	22	+#define HISI_SFC_V3XX_GLB_CFG (0x100)
	23	+#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
22	24	#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
23	25	#define HISI_SFC_V3XX_INT_STAT (0x124)
24	26	#define HISI_SFC_V3XX_INT_MASK (0x128)
@@ -75,6 +77,7 @@ struct hisi_sfc_v3xx_host { · 50 unmodified lines
75	77	void __iomem *regbase;
76	78	int max_cmd_dword;
77	79	struct completion *completion;
	80	+ u8 address_mode;
78	81	int irq;
79	82	};
80	83
@@ -168,10 +171,18 @@ static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem, · 87 unmodified lines
168	171	static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
169	172	const struct spi_mem_op *op)
170	173	{
	174	+ struct spi_device *spi = mem->spi;
	175	+ struct hisi_sfc_v3xx_host *host;
	176	+
	177	+ host = spi_controller_get_devdata(spi->master);
	178	+
171	179	if (op->data.buswidth > 4 \|\| op->dummy.buswidth > 4 \|\|
172	180	op->addr.buswidth > 4 \|\| op->cmd.buswidth > 4)
173	181	return false;
174	182
	183	+ if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
	184	+ return false;
	185	+
175	186	return spi_mem_default_supports_op(mem, op);
176	187	}
177	188
@@ -416,7 +427,7 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev) · 238 unmodified lines
416	427	struct device *dev = &pdev->dev;
417	428	struct hisi_sfc_v3xx_host *host;
418	429	struct spi_controller *ctlr;
419		− u32 version;
	430	+ u32 version, glb_config;
420	431	int ret;
421	432
422	433	ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
@@ -463,16 +474,24 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev) · 40 unmodified lines
463	474	ctlr->num_chipselect = 1;
464	475	ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
465	476
	477	+ /*
	478	+ * The address mode of the controller is either 3 or 4,
	479	+ * which is indicated by the address mode bit in
	480	+ * the global config register. The register is read only
	481	+ * for the OS driver.
	482	+ */
	483	+ glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
	484	+ if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
	485	+ host->address_mode = 4;
	486	+ else
	487	+ host->address_mode = 3;
	488	+
466	489	version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
467	490
468		− switch (version) {
469		− case 0x351:
	491	+ if (version >= 0x351)
470	492	host->max_cmd_dword = 64;
471		− break;
472		− default:
	493	+ else
473	494	host->max_cmd_dword = 16;
474		− break;
475		− }
476	495
477	496	ret = devm_spi_register_controller(dev, ctlr);
478	497	if (ret)

drivers/spi/spi-imx.c+1−1

@@ -1685,7 +1685,7 @@ static int spi_imx_probe(struct platform_device *pdev) · 1684 unmodified lines
1685	1685	master->dev.of_node = pdev->dev.of_node;
1686	1686	ret = spi_bitbang_start(&spi_imx->bitbang);
1687	1687	if (ret) {
1688		− dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
	1688	+ dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1689	1689	goto out_bitbang_start;
1690	1690	}
1691	1691

drivers/spi/spi-mem.c+20−3

@@ -137,8 +137,8 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) · 136 unmodified lines
137	137	return -ENOTSUPP;
138	138	}
139	139
140		−bool spi_mem_default_supports_op(struct spi_mem *mem,
141		− const struct spi_mem_op *op)
	140	+static bool spi_mem_check_buswidth(struct spi_mem *mem,
	141	+ const struct spi_mem_op *op)
142	142	{
143	143	if (spi_check_buswidth_req(mem, op->cmd.buswidth, true))
144	144	return false;
@@ -156,13 +156,29 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, · 11 unmodified lines
156	156	op->data.dir == SPI_MEM_DATA_OUT))
157	157	return false;
158	158
	159	+ return true;
	160	+}
	161	+
	162	+bool spi_mem_dtr_supports_op(struct spi_mem *mem,
	163	+ const struct spi_mem_op *op)
	164	+{
	165	+ if (op->cmd.nbytes != 2)
	166	+ return false;
	167	+
	168	+ return spi_mem_check_buswidth(mem, op);
	169	+}
	170	+EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
	171	+
	172	+bool spi_mem_default_supports_op(struct spi_mem *mem,
	173	+ const struct spi_mem_op *op)
	174	+{
159	175	if (op->cmd.dtr \|\| op->addr.dtr \|\| op->dummy.dtr \|\| op->data.dtr)
160	176	return false;
161	177
162	178	if (op->cmd.nbytes != 1)
163	179	return false;
164	180
165		− return true;
	181	+ return spi_mem_check_buswidth(mem, op);
166	182	}
167	183	EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
168	184
@@ -354,6 +370,7 @@ int spi_mem_exec_op(struct spi_mem mem, const struct spi_mem_op op) · 185 unmodified lines
354	370	xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
355	371	xfers[xferpos].len = op->dummy.nbytes;
356	372	xfers[xferpos].tx_nbits = op->dummy.buswidth;
	373	+ xfers[xferpos].dummy_data = 1;
357	374	spi_message_add_tail(&xfers[xferpos], &msg);
358	375	xferpos++;
359	376	totalxferlen += op->dummy.nbytes;

drivers/spi/spi-mpc52xx.c+3−1

@@ -248,7 +248,9 @@ static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, · 247 unmodified lines
248	248	ms->len--;
249	249	if (ms->len == 0) {
250	250	ms->timestamp = get_tbl();
251		− ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
	251	+ if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
	252	+ ms->timestamp += ms->transfer->delay.value *
	253	+ tb_ticks_per_usec;
252	254	ms->state = mpc52xx_spi_fsmstate_wait;
253	255	return FSM_CONTINUE;
254	256	}

drivers/spi/spi-mt65xx.c+56−16

@@ -287,7 +287,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) · 286 unmodified lines
287	287	static void mtk_spi_prepare_transfer(struct spi_master *master,
288	288	struct spi_transfer *xfer)
289	289	{
290		− u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
	290	+ u32 spi_clk_hz, div, sck_time, reg_val;
291	291	struct mtk_spi *mdata = spi_master_get_devdata(master);
292	292
293	293	spi_clk_hz = clk_get_rate(mdata->spi_clk);
@@ -297,32 +297,25 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, · 3 unmodified lines
297	297	div = 1;
298	298
299	299	sck_time = (div + 1) / 2;
300		− cs_time = sck_time * 2;
301	300
302	301	if (mdata->dev_comp->enhance_timing) {
303		− reg_val = (((sck_time - 1) & 0xffff)
	302	+ reg_val = readl(mdata->base + SPI_CFG2_REG);
	303	+ reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
	304	+ reg_val \|= (((sck_time - 1) & 0xffff)
304	305	<< SPI_CFG2_SCK_HIGH_OFFSET);
	306	+ reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
305	307	reg_val \|= (((sck_time - 1) & 0xffff)
306	308	<< SPI_CFG2_SCK_LOW_OFFSET);
307	309	writel(reg_val, mdata->base + SPI_CFG2_REG);
308		− reg_val = (((cs_time - 1) & 0xffff)
309		− << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
310		− reg_val \|= (((cs_time - 1) & 0xffff)
311		− << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
312		− writel(reg_val, mdata->base + SPI_CFG0_REG);
313	310	} else {
314		− reg_val = (((sck_time - 1) & 0xff)
	311	+ reg_val = readl(mdata->base + SPI_CFG0_REG);
	312	+ reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
	313	+ reg_val \|= (((sck_time - 1) & 0xff)
315	314	<< SPI_CFG0_SCK_HIGH_OFFSET);
	315	+ reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
316	316	reg_val \|= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
317		− reg_val \|= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
318		− reg_val \|= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
319	317	writel(reg_val, mdata->base + SPI_CFG0_REG);
320	318	}
321		−
322		− reg_val = readl(mdata->base + SPI_CFG1_REG);
323		− reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
324		− reg_val \|= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
325		− writel(reg_val, mdata->base + SPI_CFG1_REG);
326	319	}
327	320
328	321	static void mtk_spi_setup_packet(struct spi_master *master)
@@ -513,6 +506,52 @@ static bool mtk_spi_can_dma(struct spi_master *master, · 184 unmodified lines
513	506	(unsigned long)xfer->rx_buf % 4 == 0);
514	507	}
515	508
	509	+static int mtk_spi_set_hw_cs_timing(struct spi_device *spi,
	510	+ struct spi_delay *setup,
	511	+ struct spi_delay *hold,
	512	+ struct spi_delay *inactive)
	513	+{
	514	+ struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
	515	+ u16 setup_dly, hold_dly, inactive_dly;
	516	+ u32 reg_val;
	517	+
	518	+ if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) \|\|
	519	+ (hold && hold->unit != SPI_DELAY_UNIT_SCK) \|\|
	520	+ (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
	521	+ dev_err(&spi->dev,
	522	+ "Invalid delay unit, should be SPI_DELAY_UNIT_SCK\n");
	523	+ return -EINVAL;
	524	+ }
	525	+
	526	+ setup_dly = setup ? setup->value : 1;
	527	+ hold_dly = hold ? hold->value : 1;
	528	+ inactive_dly = inactive ? inactive->value : 1;
	529	+
	530	+ reg_val = readl(mdata->base + SPI_CFG0_REG);
	531	+ if (mdata->dev_comp->enhance_timing) {
	532	+ reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
	533	+ reg_val \|= (((hold_dly - 1) & 0xffff)
	534	+ << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
	535	+ reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
	536	+ reg_val \|= (((setup_dly - 1) & 0xffff)
	537	+ << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
	538	+ } else {
	539	+ reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
	540	+ reg_val \|= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
	541	+ reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
	542	+ reg_val \|= (((setup_dly - 1) & 0xff)
	543	+ << SPI_CFG0_CS_SETUP_OFFSET);
	544	+ }
	545	+ writel(reg_val, mdata->base + SPI_CFG0_REG);
	546	+
	547	+ reg_val = readl(mdata->base + SPI_CFG1_REG);
	548	+ reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
	549	+ reg_val \|= (((inactive_dly - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
	550	+ writel(reg_val, mdata->base + SPI_CFG1_REG);
	551	+
	552	+ return 0;
	553	+}
	554	+
516	555	static int mtk_spi_setup(struct spi_device *spi)
517	556	{
518	557	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
@@ -644,6 +683,7 @@ static int mtk_spi_probe(struct platform_device *pdev) · 125 unmodified lines
644	683	master->transfer_one = mtk_spi_transfer_one;
645	684	master->can_dma = mtk_spi_can_dma;
646	685	master->setup = mtk_spi_setup;
	686	+ master->set_cs_timing = mtk_spi_set_hw_cs_timing;
647	687
648	688	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
649	689	if (!of_id) {

drivers/spi/spi-orion.c+50−5

@@ -96,10 +96,16 @@ struct orion_spi { · 95 unmodified lines
96	96	struct clk *clk;
97	97	struct clk *axi_clk;
98	98	const struct orion_spi_dev *devdata;
	99	+ struct device *dev;
99	100
100	101	struct orion_child_options child[ORION_NUM_CHIPSELECTS];
101	102	};
102	103
	104	+#ifdef CONFIG_PM
	105	+static int orion_spi_runtime_suspend(struct device *dev);
	106	+static int orion_spi_runtime_resume(struct device *dev);
	107	+#endif
	108	+
103	109	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
104	110	{
105	111	return orion_spi->base + reg;
@@ -369,8 +375,15 @@ orion_spi_write_read_8bit(struct spi_device *spi, · 263 unmodified lines
369	375	{
370	376	void __iomem tx_reg, rx_reg, *int_reg;
371	377	struct orion_spi *orion_spi;
	378	+ bool cs_single_byte;
	379	+
	380	+ cs_single_byte = spi->mode & SPI_CS_WORD;
372	381
373	382	orion_spi = spi_master_get_devdata(spi->master);
	383	+
	384	+ if (cs_single_byte)
	385	+ orion_spi_set_cs(spi, 0);
	386	+
374	387	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
375	388	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
376	389	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
@@ -384,6 +397,11 @@ orion_spi_write_read_8bit(struct spi_device *spi, · 7 unmodified lines
384	397	writel(0, tx_reg);
385	398
386	399	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	400	+ if (cs_single_byte) {
	401	+ orion_spi_set_cs(spi, 1);
	402	+ /* Satisfy some SLIC devices requirements */
	403	+ udelay(4);
	404	+ }
387	405	dev_err(&spi->dev, "TXS timed out\n");
388	406	return -1;
389	407	}
@@ -391,6 +409,12 @@ orion_spi_write_read_8bit(struct spi_device *spi, · 1 unmodified line
391	409	if (rx_buf && *rx_buf)
392	410	(rx_buf)++ = readl(rx_reg);
393	411
	412	+ if (cs_single_byte) {
	413	+ orion_spi_set_cs(spi, 1);
	414	+ /* Satisfy some SLIC devices requirements */
	415	+ udelay(4);
	416	+ }
	417	+
394	418	return 1;
395	419	}
396	420
@@ -401,6 +425,11 @@ orion_spi_write_read_16bit(struct spi_device *spi, · 4 unmodified lines
401	425	void __iomem tx_reg, rx_reg, *int_reg;
402	426	struct orion_spi *orion_spi;
403	427
	428	+ if (spi->mode & SPI_CS_WORD) {
	429	+ dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n");
	430	+ return -1;
	431	+ }
	432	+
404	433	orion_spi = spi_master_get_devdata(spi->master);
405	434	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
406	435	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
@@ -440,12 +469,13 @@ orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer) · 33 unmodified lines
440	469	orion_spi = spi_master_get_devdata(spi->master);
441	470
442	471	/*
443		− * Use SPI direct write mode if base address is available. Otherwise
444		− * fall back to PIO mode for this transfer.
	472	+ * Use SPI direct write mode if base address is available
	473	+ * and SPI_CS_WORD flag is not set.
	474	+ * Otherwise fall back to PIO mode for this transfer.
445	475	*/
446	476	vaddr = orion_spi->child[cs].direct_access.vaddr;
447	477
448		− if (vaddr && xfer->tx_buf && word_len == 8) {
	478	+ if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) {
449	479	unsigned int cnt = count / 4;
450	480	unsigned int rem = count % 4;
451	481
@@ -507,7 +537,21 @@ static int orion_spi_transfer_one(struct spi_master *master, · 55 unmodified lines
507	537
508	538	static int orion_spi_setup(struct spi_device *spi)
509	539	{
510		− return orion_spi_setup_transfer(spi, NULL);
	540	+ int ret;
	541	+#ifdef CONFIG_PM
	542	+ struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);
	543	+ struct device *dev = orion_spi->dev;
	544	+
	545	+ orion_spi_runtime_resume(dev);
	546	+#endif
	547	+
	548	+ ret = orion_spi_setup_transfer(spi, NULL);
	549	+
	550	+#ifdef CONFIG_PM
	551	+ orion_spi_runtime_suspend(dev);
	552	+#endif
	553	+
	554	+ return ret;
511	555	}
512	556
513	557	static int orion_spi_reset(struct orion_spi *orion_spi)
@@ -616,7 +660,7 @@ static int orion_spi_probe(struct platform_device *pdev) · 102 unmodified lines
616	660	}
617	661
618	662	/* we support all 4 SPI modes and LSB first option */
619		− master->mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_LSB_FIRST;
	663	+ master->mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_LSB_FIRST \| SPI_CS_WORD;
620	664	master->set_cs = orion_spi_set_cs;
621	665	master->transfer_one = orion_spi_transfer_one;
622	666	master->num_chipselect = ORION_NUM_CHIPSELECTS;
@@ -630,6 +674,7 @@ static int orion_spi_probe(struct platform_device *pdev) · 7 unmodified lines
630	674
631	675	spi = spi_master_get_devdata(master);
632	676	spi->master = master;
	677	+ spi->dev = &pdev->dev;
633	678
634	679	of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
635	680	devdata = (of_id) ? of_id->data : &orion_spi_dev_data;

drivers/spi/spi-pxa2xx-pci.c+21−8

@@ -21,7 +21,8 @@ enum { · 20 unmodified lines
21	21	PORT_BSW1,
22	22	PORT_BSW2,
23	23	PORT_CE4100,
24		− PORT_LPT,
	24	+ PORT_LPT0,
	25	+ PORT_LPT1,
25	26	};
26	27
27	28	struct pxa_spi_info {
@@ -57,8 +58,10 @@ static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 }; · 29 unmodified lines
57	58	static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
58	59	static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
59	60
60		−static struct dw_dma_slave lpt_tx_param = { .dst_id = 0 };
61		−static struct dw_dma_slave lpt_rx_param = { .src_id = 1 };
	61	+static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
	62	+static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
	63	+static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
	64	+static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
62	65
63	66	static bool lpss_dma_filter(struct dma_chan chan, void param)
64	67	{
@@ -185,12 +188,19 @@ static struct pxa_spi_info spi_info_configs[] = { · 120 unmodified lines
185	188	.num_chipselect = 1,
186	189	.max_clk_rate = 50000000,
187	190	},
188		− [PORT_LPT] = {
	191	+ [PORT_LPT0] = {
189	192	.type = LPSS_LPT_SSP,
190	193	.port_id = 0,
191	194	.setup = lpss_spi_setup,
192		− .tx_param = &lpt_tx_param,
193		− .rx_param = &lpt_rx_param,
	195	+ .tx_param = &lpt0_tx_param,
	196	+ .rx_param = &lpt0_rx_param,
	197	+ },
	198	+ [PORT_LPT1] = {
	199	+ .type = LPSS_LPT_SSP,
	200	+ .port_id = 1,
	201	+ .setup = lpss_spi_setup,
	202	+ .tx_param = &lpt1_tx_param,
	203	+ .rx_param = &lpt1_rx_param,
194	204	},
195	205	};
196	206
@@ -285,8 +295,11 @@ static const struct pci_device_id pxa2xx_spi_pci_devices[] = { · 88 unmodified lines
285	295	{ PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
286	296	{ PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
287	297	{ PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
288		− { PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT },
289		− { },
	298	+ { PCI_VDEVICE(INTEL, 0x9c65), PORT_LPT0 },
	299	+ { PCI_VDEVICE(INTEL, 0x9c66), PORT_LPT1 },
	300	+ { PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
	301	+ { PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
	302	+ { }
290	303	};
291	304	MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
292	305

drivers/spi/spi-pxa2xx.c+4−0

@@ -1492,6 +1492,10 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { · 1491 unmodified lines
1492	1492	{ PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
1493	1493	{ PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
1494	1494	{ PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
	1495	+ /* ADL-P */
	1496	+ { PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP },
	1497	+ { PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP },
	1498	+ { PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP },
1495	1499	/* APL */
1496	1500	{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1497	1501	{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },

drivers/spi/spi-qcom-qspi.c+1−2

@@ -511,8 +511,7 @@ static int qcom_qspi_probe(struct platform_device *pdev) · 510 unmodified lines
511	511	ret = platform_get_irq(pdev, 0);
512	512	if (ret < 0)
513	513	return ret;
514		− ret = devm_request_irq(dev, ret, qcom_qspi_irq,
515		− IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
	514	+ ret = devm_request_irq(dev, ret, qcom_qspi_irq, 0, dev_name(dev), ctrl);
516	515	if (ret) {
517	516	dev_err(dev, "Failed to request irq %d\n", ret);
518	517	return ret;

drivers/spi/spi-realtek-rtl.c+209−0

@@ -0,0 +1,209 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+
	3	+#include <linux/module.h>
	4	+#include <linux/platform_device.h>
	5	+#include <linux/mod_devicetable.h>
	6	+#include <linux/spi/spi.h>
	7	+
	8	+struct rtspi {
	9	+ void __iomem *base;
	10	+};
	11	+
	12	+/* SPI Flash Configuration Register */
	13	+#define RTL_SPI_SFCR 0x00
	14	+#define RTL_SPI_SFCR_RBO BIT(28)
	15	+#define RTL_SPI_SFCR_WBO BIT(27)
	16	+
	17	+/* SPI Flash Control and Status Register */
	18	+#define RTL_SPI_SFCSR 0x08
	19	+#define RTL_SPI_SFCSR_CSB0 BIT(31)
	20	+#define RTL_SPI_SFCSR_CSB1 BIT(30)
	21	+#define RTL_SPI_SFCSR_RDY BIT(27)
	22	+#define RTL_SPI_SFCSR_CS BIT(24)
	23	+#define RTL_SPI_SFCSR_LEN_MASK ~(0x03 << 28)
	24	+#define RTL_SPI_SFCSR_LEN1 (0x00 << 28)
	25	+#define RTL_SPI_SFCSR_LEN4 (0x03 << 28)
	26	+
	27	+/* SPI Flash Data Register */
	28	+#define RTL_SPI_SFDR 0x0c
	29	+
	30	+#define REG(x) (rtspi->base + x)
	31	+
	32	+
	33	+static void rt_set_cs(struct spi_device *spi, bool active)
	34	+{
	35	+ struct rtspi *rtspi = spi_controller_get_devdata(spi->controller);
	36	+ u32 value;
	37	+
	38	+ /* CS0 bit is active low */
	39	+ value = readl(REG(RTL_SPI_SFCSR));
	40	+ if (active)
	41	+ value \|= RTL_SPI_SFCSR_CSB0;
	42	+ else
	43	+ value &= ~RTL_SPI_SFCSR_CSB0;
	44	+ writel(value, REG(RTL_SPI_SFCSR));
	45	+}
	46	+
	47	+static void set_size(struct rtspi *rtspi, int size)
	48	+{
	49	+ u32 value;
	50	+
	51	+ value = readl(REG(RTL_SPI_SFCSR));
	52	+ value &= RTL_SPI_SFCSR_LEN_MASK;
	53	+ if (size == 4)
	54	+ value \|= RTL_SPI_SFCSR_LEN4;
	55	+ else if (size == 1)
	56	+ value \|= RTL_SPI_SFCSR_LEN1;
	57	+ writel(value, REG(RTL_SPI_SFCSR));
	58	+}
	59	+
	60	+static inline void wait_ready(struct rtspi *rtspi)
	61	+{
	62	+ while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))
	63	+ cpu_relax();
	64	+}
	65	+static void send4(struct rtspi rtspi, const u32 buf)
	66	+{
	67	+ wait_ready(rtspi);
	68	+ set_size(rtspi, 4);
	69	+ writel(*buf, REG(RTL_SPI_SFDR));
	70	+}
	71	+
	72	+static void send1(struct rtspi rtspi, const u8 buf)
	73	+{
	74	+ wait_ready(rtspi);
	75	+ set_size(rtspi, 1);
	76	+ writel(buf[0] << 24, REG(RTL_SPI_SFDR));
	77	+}
	78	+
	79	+static void rcv4(struct rtspi rtspi, u32 buf)
	80	+{
	81	+ wait_ready(rtspi);
	82	+ set_size(rtspi, 4);
	83	+ *buf = readl(REG(RTL_SPI_SFDR));
	84	+}
	85	+
	86	+static void rcv1(struct rtspi rtspi, u8 buf)
	87	+{
	88	+ wait_ready(rtspi);
	89	+ set_size(rtspi, 1);
	90	+ *buf = readl(REG(RTL_SPI_SFDR)) >> 24;
	91	+}
	92	+
	93	+static int transfer_one(struct spi_controller ctrl, struct spi_device spi,
	94	+ struct spi_transfer *xfer)
	95	+{
	96	+ struct rtspi *rtspi = spi_controller_get_devdata(ctrl);
	97	+ void *rx_buf;
	98	+ const void *tx_buf;
	99	+ int cnt;
	100	+
	101	+ tx_buf = xfer->tx_buf;
	102	+ rx_buf = xfer->rx_buf;
	103	+ cnt = xfer->len;
	104	+ if (tx_buf) {
	105	+ while (cnt >= 4) {
	106	+ send4(rtspi, tx_buf);
	107	+ tx_buf += 4;
	108	+ cnt -= 4;
	109	+ }
	110	+ while (cnt) {
	111	+ send1(rtspi, tx_buf);
	112	+ tx_buf++;
	113	+ cnt--;
	114	+ }
	115	+ } else if (rx_buf) {
	116	+ while (cnt >= 4) {
	117	+ rcv4(rtspi, rx_buf);
	118	+ rx_buf += 4;
	119	+ cnt -= 4;
	120	+ }
	121	+ while (cnt) {
	122	+ rcv1(rtspi, rx_buf);
	123	+ rx_buf++;
	124	+ cnt--;
	125	+ }
	126	+ }
	127	+
	128	+ spi_finalize_current_transfer(ctrl);
	129	+
	130	+ return 0;
	131	+}
	132	+
	133	+static void init_hw(struct rtspi *rtspi)
	134	+{
	135	+ u32 value;
	136	+
	137	+ /* Turn on big-endian byte ordering */
	138	+ value = readl(REG(RTL_SPI_SFCR));
	139	+ value \|= RTL_SPI_SFCR_RBO \| RTL_SPI_SFCR_WBO;
	140	+ writel(value, REG(RTL_SPI_SFCR));
	141	+
	142	+ value = readl(REG(RTL_SPI_SFCSR));
	143	+ /* Permanently disable CS1, since it's never used */
	144	+ value \|= RTL_SPI_SFCSR_CSB1;
	145	+ /* Select CS0 for use */
	146	+ value &= RTL_SPI_SFCSR_CS;
	147	+ writel(value, REG(RTL_SPI_SFCSR));
	148	+}
	149	+
	150	+static int realtek_rtl_spi_probe(struct platform_device *pdev)
	151	+{
	152	+ struct spi_controller *ctrl;
	153	+ struct rtspi *rtspi;
	154	+ int err;
	155	+
	156	+ ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));
	157	+ if (!ctrl) {
	158	+ dev_err(&pdev->dev, "Error allocating SPI controller\n");
	159	+ return -ENOMEM;
	160	+ }
	161	+ platform_set_drvdata(pdev, ctrl);
	162	+ rtspi = spi_controller_get_devdata(ctrl);
	163	+
	164	+ rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
	165	+ if (IS_ERR(rtspi->base)) {
	166	+ dev_err(&pdev->dev, "Could not map SPI register address");
	167	+ return -ENOMEM;
	168	+ }
	169	+
	170	+ init_hw(rtspi);
	171	+
	172	+ ctrl->dev.of_node = pdev->dev.of_node;
	173	+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
	174	+ ctrl->set_cs = rt_set_cs;
	175	+ ctrl->transfer_one = transfer_one;
	176	+
	177	+ err = devm_spi_register_controller(&pdev->dev, ctrl);
	178	+ if (err) {
	179	+ dev_err(&pdev->dev, "Could not register SPI controller\n");
	180	+ return -ENODEV;
	181	+ }
	182	+
	183	+ return 0;
	184	+}
	185	+
	186	+
	187	+static const struct of_device_id realtek_rtl_spi_of_ids[] = {
	188	+ { .compatible = "realtek,rtl8380-spi" },
	189	+ { .compatible = "realtek,rtl8382-spi" },
	190	+ { .compatible = "realtek,rtl8391-spi" },
	191	+ { .compatible = "realtek,rtl8392-spi" },
	192	+ { .compatible = "realtek,rtl8393-spi" },
	193	+ { /* sentinel */ }
	194	+};
	195	+MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids);
	196	+
	197	+static struct platform_driver realtek_rtl_spi_driver = {
	198	+ .probe = realtek_rtl_spi_probe,
	199	+ .driver = {
	200	+ .name = "realtek-rtl-spi",
	201	+ .of_match_table = realtek_rtl_spi_of_ids,
	202	+ },
	203	+};
	204	+
	205	+module_platform_driver(realtek_rtl_spi_driver);
	206	+
	207	+MODULE_LICENSE("GPL v2");
	208	+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
	209	+MODULE_DESCRIPTION("Realtek RTL SPI driver");

drivers/spi/spi-rockchip.c+1−1

@@ -566,7 +566,7 @@ static int rockchip_spi_slave_abort(struct spi_controller *ctlr) · 565 unmodified lines
566	566	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
567	567
568	568	rs->slave_abort = true;
569		− complete(&ctlr->xfer_completion);
	569	+ spi_finalize_current_transfer(ctlr);
570	570
571	571	return 0;
572	572	}

drivers/spi/spi-rpc-if.c+5−8

@@ -176,15 +176,14 @@ static int rpcif_spi_remove(struct platform_device *pdev) · 175 unmodified lines
176	176	return 0;
177	177	}
178	178
179		−#ifdef CONFIG_PM_SLEEP
180		−static int rpcif_spi_suspend(struct device *dev)
	179	+static int __maybe_unused rpcif_spi_suspend(struct device *dev)
181	180	{
182	181	struct spi_controller *ctlr = dev_get_drvdata(dev);
183	182
184	183	return spi_controller_suspend(ctlr);
185	184	}
186	185
187		−static int rpcif_spi_resume(struct device *dev)
	186	+static int __maybe_unused rpcif_spi_resume(struct device *dev)
188	187	{
189	188	struct spi_controller *ctlr = dev_get_drvdata(dev);
190	189
@@ -192,17 +191,15 @@ static int rpcif_spi_resume(struct device *dev) · 1 unmodified line
192	191	}
193	192
194	193	static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend, rpcif_spi_resume);
195		−#define DEV_PM_OPS (&rpcif_spi_pm_ops)
196		−#else
197		−#define DEV_PM_OPS NULL
198		−#endif
199	194
200	195	static struct platform_driver rpcif_spi_driver = {
201	196	.probe = rpcif_spi_probe,
202	197	.remove = rpcif_spi_remove,
203	198	.driver = {
204	199	.name = "rpc-if-spi",
205		− .pm = DEV_PM_OPS,
	200	+#ifdef CONFIG_PM_SLEEP
	201	+ .pm = &rpcif_spi_pm_ops,
	202	+#endif
206	203	},
207	204	};
208	205	module_platform_driver(rpcif_spi_driver);

drivers/spi/spi-sh-msiof.c+11−3

@@ -259,11 +259,13 @@ static const u32 sh_msiof_spi_div_array[] = { · 258 unmodified lines
259	259	};
260	260
261	261	static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
262		− unsigned long parent_rate, u32 spi_hz)
	262	+ struct spi_transfer *t)
263	263	{
	264	+ unsigned long parent_rate = clk_get_rate(p->clk);
	265	+ unsigned int div_pow = p->min_div_pow;
	266	+ u32 spi_hz = t->speed_hz;
264	267	unsigned long div;
265	268	u32 brps, scr;
266		− unsigned int div_pow = p->min_div_pow;
267	269
268	270	if (!spi_hz \|\| !parent_rate) {
269	271	WARN(1, "Invalid clock rate parameters %lu and %u\n",
@@ -292,6 +294,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, · 22 unmodified lines
292	294	brps = 32;
293	295	}
294	296
	297	+ t->effective_speed_hz = parent_rate / (brps << div_pow);
	298	+
295	299	scr = sh_msiof_spi_div_array[div_pow] \| SISCR_BRPS(brps);
296	300	sh_msiof_write(p, SITSCR, scr);
297	301	if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
@@ -923,7 +927,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, · 625 unmodified lines
923	927
924	928	/* setup clocks (clock already enabled in chipselect()) */
925	929	if (!spi_controller_is_slave(p->ctlr))
926		− sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
	930	+ sh_msiof_spi_set_clk_regs(p, t);
927	931
928	932	while (ctlr->dma_tx && len > 15) {
929	933	/*
@@ -1258,6 +1262,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) · 328 unmodified lines
1258	1262	const struct sh_msiof_chipdata *chipdata;
1259	1263	struct sh_msiof_spi_info *info;
1260	1264	struct sh_msiof_spi_priv *p;
	1265	+ unsigned long clksrc;
1261	1266	int i;
1262	1267	int ret;
1263	1268
@@ -1333,6 +1338,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) · 69 unmodified lines
1333	1338	/* init controller code */
1334	1339	ctlr->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
1335	1340	ctlr->mode_bits \|= SPI_LSB_FIRST \| SPI_3WIRE;
	1341	+ clksrc = clk_get_rate(p->clk);
	1342	+ ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024);
	1343	+ ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow);
1336	1344	ctlr->flags = chipdata->ctlr_flags;
1337	1345	ctlr->bus_num = pdev->id;
1338	1346	ctlr->num_chipselect = p->info->num_chipselect;

drivers/spi/spi-sirf.c+0−1236

@@ -1,1236 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-or-later
2		−/*
3		− * SPI bus driver for CSR SiRFprimaII
4		− *
5		− * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6		− */
7		−
8		−#include <linux/module.h>
9		−#include <linux/kernel.h>
10		−#include <linux/slab.h>
11		−#include <linux/clk.h>
12		−#include <linux/completion.h>
13		−#include <linux/interrupt.h>
14		−#include <linux/io.h>
15		−#include <linux/of.h>
16		−#include <linux/bitops.h>
17		−#include <linux/err.h>
18		−#include <linux/platform_device.h>
19		−#include <linux/of_gpio.h>
20		−#include <linux/spi/spi.h>
21		−#include <linux/spi/spi_bitbang.h>
22		−#include <linux/dmaengine.h>
23		−#include <linux/dma-direction.h>
24		−#include <linux/dma-mapping.h>
25		−#include <linux/reset.h>
26		−
27		−#define DRIVER_NAME "sirfsoc_spi"
28		−/* SPI CTRL register defines */
29		−#define SIRFSOC_SPI_SLV_MODE BIT(16)
30		−#define SIRFSOC_SPI_CMD_MODE BIT(17)
31		−#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
32		−#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
33		−#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
34		−#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
35		−#define SIRFSOC_SPI_TRAN_MSB BIT(22)
36		−#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
37		−#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
38		−#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
39		−#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
40		−#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
41		−#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
42		−#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
43		−#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
44		−#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
45		−#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
46		−
47		−/* Interrupt Enable */
48		−#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
49		−#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
50		−#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
51		−#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
52		−#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
53		−#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
54		−#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
55		−#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
56		−#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
57		−#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
58		−#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
59		−
60		−/* Interrupt status */
61		−#define SIRFSOC_SPI_RX_DONE BIT(0)
62		−#define SIRFSOC_SPI_TX_DONE BIT(1)
63		−#define SIRFSOC_SPI_RX_OFLOW BIT(2)
64		−#define SIRFSOC_SPI_TX_UFLOW BIT(3)
65		−#define SIRFSOC_SPI_RX_IO_DMA BIT(4)
66		−#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
67		−#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
68		−#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
69		−#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
70		−#define SIRFSOC_SPI_FRM_END BIT(10)
71		−
72		−/* TX RX enable */
73		−#define SIRFSOC_SPI_RX_EN BIT(0)
74		−#define SIRFSOC_SPI_TX_EN BIT(1)
75		−#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
76		−
77		−#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
78		−#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
79		−
80		−/* FIFO OPs */
81		−#define SIRFSOC_SPI_FIFO_RESET BIT(0)
82		−#define SIRFSOC_SPI_FIFO_START BIT(1)
83		−
84		−/* FIFO CTRL */
85		−#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
86		−#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
87		−#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
88		−/* USP related */
89		−#define SIRFSOC_USP_SYNC_MODE BIT(0)
90		−#define SIRFSOC_USP_SLV_MODE BIT(1)
91		−#define SIRFSOC_USP_LSB BIT(4)
92		−#define SIRFSOC_USP_EN BIT(5)
93		−#define SIRFSOC_USP_RXD_FALLING_EDGE BIT(6)
94		−#define SIRFSOC_USP_TXD_FALLING_EDGE BIT(7)
95		−#define SIRFSOC_USP_CS_HIGH_VALID BIT(9)
96		−#define SIRFSOC_USP_SCLK_IDLE_STAT BIT(11)
97		−#define SIRFSOC_USP_TFS_IO_MODE BIT(14)
98		−#define SIRFSOC_USP_TFS_IO_INPUT BIT(19)
99		−
100		−#define SIRFSOC_USP_RXD_DELAY_LEN_MASK 0xFF
101		−#define SIRFSOC_USP_TXD_DELAY_LEN_MASK 0xFF
102		−#define SIRFSOC_USP_RXD_DELAY_OFFSET 0
103		−#define SIRFSOC_USP_TXD_DELAY_OFFSET 8
104		−#define SIRFSOC_USP_RXD_DELAY_LEN 1
105		−#define SIRFSOC_USP_TXD_DELAY_LEN 1
106		−#define SIRFSOC_USP_CLK_DIVISOR_OFFSET 21
107		−#define SIRFSOC_USP_CLK_DIVISOR_MASK 0x3FF
108		−#define SIRFSOC_USP_CLK_10_11_MASK 0x3
109		−#define SIRFSOC_USP_CLK_10_11_OFFSET 30
110		−#define SIRFSOC_USP_CLK_12_15_MASK 0xF
111		−#define SIRFSOC_USP_CLK_12_15_OFFSET 24
112		−
113		−#define SIRFSOC_USP_TX_DATA_OFFSET 0
114		−#define SIRFSOC_USP_TX_SYNC_OFFSET 8
115		−#define SIRFSOC_USP_TX_FRAME_OFFSET 16
116		−#define SIRFSOC_USP_TX_SHIFTER_OFFSET 24
117		−
118		−#define SIRFSOC_USP_TX_DATA_MASK 0xFF
119		−#define SIRFSOC_USP_TX_SYNC_MASK 0xFF
120		−#define SIRFSOC_USP_TX_FRAME_MASK 0xFF
121		−#define SIRFSOC_USP_TX_SHIFTER_MASK 0x1F
122		−
123		−#define SIRFSOC_USP_RX_DATA_OFFSET 0
124		−#define SIRFSOC_USP_RX_FRAME_OFFSET 8
125		−#define SIRFSOC_USP_RX_SHIFTER_OFFSET 16
126		−
127		−#define SIRFSOC_USP_RX_DATA_MASK 0xFF
128		−#define SIRFSOC_USP_RX_FRAME_MASK 0xFF
129		−#define SIRFSOC_USP_RX_SHIFTER_MASK 0x1F
130		−#define SIRFSOC_USP_CS_HIGH_VALUE BIT(1)
131		−
132		−#define SIRFSOC_SPI_FIFO_SC_OFFSET 0
133		−#define SIRFSOC_SPI_FIFO_LC_OFFSET 10
134		−#define SIRFSOC_SPI_FIFO_HC_OFFSET 20
135		−
136		−#define SIRFSOC_SPI_FIFO_FULL_MASK(s) (1 << ((s)->fifo_full_offset))
137		−#define SIRFSOC_SPI_FIFO_EMPTY_MASK(s) (1 << ((s)->fifo_full_offset + 1))
138		−#define SIRFSOC_SPI_FIFO_THD_MASK(s) ((s)->fifo_size - 1)
139		−#define SIRFSOC_SPI_FIFO_THD_OFFSET 2
140		−#define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val) \
141		− ((val) & (s)->fifo_level_chk_mask)
142		−
143		−enum sirf_spi_type {
144		− SIRF_REAL_SPI,
145		− SIRF_USP_SPI_P2,
146		− SIRF_USP_SPI_A7,
147		−};
148		−
149		−/*
150		− * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
151		− * due to the limitation of dma controller
152		− */
153		−
154		−#define ALIGNED(x) (!((u32)x & 0x3))
155		−#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
156		− ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
157		−
158		−#define SIRFSOC_MAX_CMD_BYTES 4
159		−#define SIRFSOC_SPI_DEFAULT_FRQ 1000000
160		−
161		−struct sirf_spi_register {
162		− /SPI and USP-SPI common/
163		− u32 tx_rx_en;
164		− u32 int_en;
165		− u32 int_st;
166		− u32 tx_dma_io_ctrl;
167		− u32 tx_dma_io_len;
168		− u32 txfifo_ctrl;
169		− u32 txfifo_level_chk;
170		− u32 txfifo_op;
171		− u32 txfifo_st;
172		− u32 txfifo_data;
173		− u32 rx_dma_io_ctrl;
174		− u32 rx_dma_io_len;
175		− u32 rxfifo_ctrl;
176		− u32 rxfifo_level_chk;
177		− u32 rxfifo_op;
178		− u32 rxfifo_st;
179		− u32 rxfifo_data;
180		− /SPI self/
181		− u32 spi_ctrl;
182		− u32 spi_cmd;
183		− u32 spi_dummy_delay_ctrl;
184		− /USP-SPI self/
185		− u32 usp_mode1;
186		− u32 usp_mode2;
187		− u32 usp_tx_frame_ctrl;
188		− u32 usp_rx_frame_ctrl;
189		− u32 usp_pin_io_data;
190		− u32 usp_risc_dsp_mode;
191		− u32 usp_async_param_reg;
192		− u32 usp_irda_x_mode_div;
193		− u32 usp_sm_cfg;
194		− u32 usp_int_en_clr;
195		−};
196		−
197		−static const struct sirf_spi_register real_spi_register = {
198		− .tx_rx_en = 0x8,
199		− .int_en = 0xc,
200		− .int_st = 0x10,
201		− .tx_dma_io_ctrl = 0x100,
202		− .tx_dma_io_len = 0x104,
203		− .txfifo_ctrl = 0x108,
204		− .txfifo_level_chk = 0x10c,
205		− .txfifo_op = 0x110,
206		− .txfifo_st = 0x114,
207		− .txfifo_data = 0x118,
208		− .rx_dma_io_ctrl = 0x120,
209		− .rx_dma_io_len = 0x124,
210		− .rxfifo_ctrl = 0x128,
211		− .rxfifo_level_chk = 0x12c,
212		− .rxfifo_op = 0x130,
213		− .rxfifo_st = 0x134,
214		− .rxfifo_data = 0x138,
215		− .spi_ctrl = 0x0,
216		− .spi_cmd = 0x4,
217		− .spi_dummy_delay_ctrl = 0x144,
218		−};
219		−
220		−static const struct sirf_spi_register usp_spi_register = {
221		− .tx_rx_en = 0x10,
222		− .int_en = 0x14,
223		− .int_st = 0x18,
224		− .tx_dma_io_ctrl = 0x100,
225		− .tx_dma_io_len = 0x104,
226		− .txfifo_ctrl = 0x108,
227		− .txfifo_level_chk = 0x10c,
228		− .txfifo_op = 0x110,
229		− .txfifo_st = 0x114,
230		− .txfifo_data = 0x118,
231		− .rx_dma_io_ctrl = 0x120,
232		− .rx_dma_io_len = 0x124,
233		− .rxfifo_ctrl = 0x128,
234		− .rxfifo_level_chk = 0x12c,
235		− .rxfifo_op = 0x130,
236		− .rxfifo_st = 0x134,
237		− .rxfifo_data = 0x138,
238		− .usp_mode1 = 0x0,
239		− .usp_mode2 = 0x4,
240		− .usp_tx_frame_ctrl = 0x8,
241		− .usp_rx_frame_ctrl = 0xc,
242		− .usp_pin_io_data = 0x1c,
243		− .usp_risc_dsp_mode = 0x20,
244		− .usp_async_param_reg = 0x24,
245		− .usp_irda_x_mode_div = 0x28,
246		− .usp_sm_cfg = 0x2c,
247		− .usp_int_en_clr = 0x140,
248		−};
249		−
250		−struct sirfsoc_spi {
251		− struct spi_bitbang bitbang;
252		− struct completion rx_done;
253		− struct completion tx_done;
254		−
255		− void __iomem *base;
256		− u32 ctrl_freq; /* SPI controller clock speed */
257		− struct clk *clk;
258		−
259		− /* rx & tx bufs from the spi_transfer */
260		− const void *tx;
261		− void *rx;
262		−
263		− /* place received word into rx buffer */
264		− void (rx_word) (struct sirfsoc_spi );
265		− /* get word from tx buffer for sending */
266		− void (tx_word) (struct sirfsoc_spi );
267		−
268		− /* number of words left to be tranmitted/received */
269		− unsigned int left_tx_word;
270		− unsigned int left_rx_word;
271		−
272		− /* rx & tx DMA channels */
273		− struct dma_chan *rx_chan;
274		− struct dma_chan *tx_chan;
275		− dma_addr_t src_start;
276		− dma_addr_t dst_start;
277		− int word_width; /* in bytes */
278		−
279		− /*
280		− * if tx size is not more than 4 and rx size is NULL, use
281		− * command model
282		− */
283		− bool tx_by_cmd;
284		− bool hw_cs;
285		− enum sirf_spi_type type;
286		− const struct sirf_spi_register *regs;
287		− unsigned int fifo_size;
288		− /* fifo empty offset is (fifo full offset + 1)*/
289		− unsigned int fifo_full_offset;
290		− /* fifo_level_chk_mask is (fifo_size/4 - 1) */
291		− unsigned int fifo_level_chk_mask;
292		− unsigned int dat_max_frm_len;
293		−};
294		−
295		−struct sirf_spi_comp_data {
296		− const struct sirf_spi_register *regs;
297		− enum sirf_spi_type type;
298		− unsigned int dat_max_frm_len;
299		− unsigned int fifo_size;
300		− void (hwinit)(struct sirfsoc_spi sspi);
301		−};
302		−
303		−static void sirfsoc_usp_hwinit(struct sirfsoc_spi *sspi)
304		−{
305		− /* reset USP and let USP can operate */
306		− writel(readl(sspi->base + sspi->regs->usp_mode1) &
307		− ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
308		− writel(readl(sspi->base + sspi->regs->usp_mode1) \|
309		− SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
310		−}
311		−
312		−static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
313		−{
314		− u32 data;
315		− u8 *rx = sspi->rx;
316		−
317		− data = readl(sspi->base + sspi->regs->rxfifo_data);
318		−
319		− if (rx) {
320		− *rx++ = (u8) data;
321		− sspi->rx = rx;
322		− }
323		−
324		− sspi->left_rx_word--;
325		−}
326		−
327		−static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
328		−{
329		− u32 data = 0;
330		− const u8 *tx = sspi->tx;
331		−
332		− if (tx) {
333		− data = *tx++;
334		− sspi->tx = tx;
335		− }
336		− writel(data, sspi->base + sspi->regs->txfifo_data);
337		− sspi->left_tx_word--;
338		−}
339		−
340		−static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
341		−{
342		− u32 data;
343		− u16 *rx = sspi->rx;
344		−
345		− data = readl(sspi->base + sspi->regs->rxfifo_data);
346		−
347		− if (rx) {
348		− *rx++ = (u16) data;
349		− sspi->rx = rx;
350		− }
351		−
352		− sspi->left_rx_word--;
353		−}
354		−
355		−static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
356		−{
357		− u32 data = 0;
358		− const u16 *tx = sspi->tx;
359		−
360		− if (tx) {
361		− data = *tx++;
362		− sspi->tx = tx;
363		− }
364		−
365		− writel(data, sspi->base + sspi->regs->txfifo_data);
366		− sspi->left_tx_word--;
367		−}
368		−
369		−static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
370		−{
371		− u32 data;
372		− u32 *rx = sspi->rx;
373		−
374		− data = readl(sspi->base + sspi->regs->rxfifo_data);
375		−
376		− if (rx) {
377		− *rx++ = (u32) data;
378		− sspi->rx = rx;
379		− }
380		−
381		− sspi->left_rx_word--;
382		−
383		−}
384		−
385		−static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
386		−{
387		− u32 data = 0;
388		− const u32 *tx = sspi->tx;
389		−
390		− if (tx) {
391		− data = *tx++;
392		− sspi->tx = tx;
393		− }
394		−
395		− writel(data, sspi->base + sspi->regs->txfifo_data);
396		− sspi->left_tx_word--;
397		−}
398		−
399		−static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
400		−{
401		− struct sirfsoc_spi *sspi = dev_id;
402		− u32 spi_stat;
403		−
404		− spi_stat = readl(sspi->base + sspi->regs->int_st);
405		− if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI
406		− && (spi_stat & SIRFSOC_SPI_FRM_END)) {
407		− complete(&sspi->tx_done);
408		− writel(0x0, sspi->base + sspi->regs->int_en);
409		− writel(readl(sspi->base + sspi->regs->int_st),
410		− sspi->base + sspi->regs->int_st);
411		− return IRQ_HANDLED;
412		− }
413		− /* Error Conditions */
414		− if (spi_stat & SIRFSOC_SPI_RX_OFLOW \|\|
415		− spi_stat & SIRFSOC_SPI_TX_UFLOW) {
416		− complete(&sspi->tx_done);
417		− complete(&sspi->rx_done);
418		− switch (sspi->type) {
419		− case SIRF_REAL_SPI:
420		− case SIRF_USP_SPI_P2:
421		− writel(0x0, sspi->base + sspi->regs->int_en);
422		− break;
423		− case SIRF_USP_SPI_A7:
424		− writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
425		− break;
426		− }
427		− writel(readl(sspi->base + sspi->regs->int_st),
428		− sspi->base + sspi->regs->int_st);
429		− return IRQ_HANDLED;
430		− }
431		− if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
432		− complete(&sspi->tx_done);
433		− while (!(readl(sspi->base + sspi->regs->int_st) &
434		− SIRFSOC_SPI_RX_IO_DMA))
435		− cpu_relax();
436		− complete(&sspi->rx_done);
437		− switch (sspi->type) {
438		− case SIRF_REAL_SPI:
439		− case SIRF_USP_SPI_P2:
440		− writel(0x0, sspi->base + sspi->regs->int_en);
441		− break;
442		− case SIRF_USP_SPI_A7:
443		− writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
444		− break;
445		− }
446		− writel(readl(sspi->base + sspi->regs->int_st),
447		− sspi->base + sspi->regs->int_st);
448		−
449		− return IRQ_HANDLED;
450		−}
451		−
452		−static void spi_sirfsoc_dma_fini_callback(void *data)
453		−{
454		− struct completion *dma_complete = data;
455		−
456		− complete(dma_complete);
457		−}
458		−
459		−static void spi_sirfsoc_cmd_transfer(struct spi_device *spi,
460		− struct spi_transfer *t)
461		−{
462		− struct sirfsoc_spi *sspi;
463		− int timeout = t->len * 10;
464		− u32 cmd;
465		−
466		− sspi = spi_master_get_devdata(spi->master);
467		− writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
468		− writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
469		− memcpy(&cmd, sspi->tx, t->len);
470		− if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
471		− cmd = cpu_to_be32(cmd) >>
472		− ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
473		− if (sspi->word_width == 2 && t->len == 4 &&
474		− (!(spi->mode & SPI_LSB_FIRST)))
475		− cmd = ((cmd & 0xffff) << 16) \| (cmd >> 16);
476		− writel(cmd, sspi->base + sspi->regs->spi_cmd);
477		− writel(SIRFSOC_SPI_FRM_END_INT_EN,
478		− sspi->base + sspi->regs->int_en);
479		− writel(SIRFSOC_SPI_CMD_TX_EN,
480		− sspi->base + sspi->regs->tx_rx_en);
481		− if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
482		− dev_err(&spi->dev, "cmd transfer timeout\n");
483		− return;
484		− }
485		− sspi->left_rx_word -= t->len;
486		−}
487		−
488		−static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
489		− struct spi_transfer *t)
490		−{
491		− struct sirfsoc_spi *sspi;
492		− struct dma_async_tx_descriptor rx_desc, tx_desc;
493		− int timeout = t->len * 10;
494		−
495		− sspi = spi_master_get_devdata(spi->master);
496		− writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
497		− writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
498		− switch (sspi->type) {
499		− case SIRF_REAL_SPI:
500		− writel(SIRFSOC_SPI_FIFO_START,
501		− sspi->base + sspi->regs->rxfifo_op);
502		− writel(SIRFSOC_SPI_FIFO_START,
503		− sspi->base + sspi->regs->txfifo_op);
504		− writel(0, sspi->base + sspi->regs->int_en);
505		− break;
506		− case SIRF_USP_SPI_P2:
507		− writel(0x0, sspi->base + sspi->regs->rxfifo_op);
508		− writel(0x0, sspi->base + sspi->regs->txfifo_op);
509		− writel(0, sspi->base + sspi->regs->int_en);
510		− break;
511		− case SIRF_USP_SPI_A7:
512		− writel(0x0, sspi->base + sspi->regs->rxfifo_op);
513		− writel(0x0, sspi->base + sspi->regs->txfifo_op);
514		− writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
515		− break;
516		− }
517		− writel(readl(sspi->base + sspi->regs->int_st),
518		− sspi->base + sspi->regs->int_st);
519		− if (sspi->left_tx_word < sspi->dat_max_frm_len) {
520		− switch (sspi->type) {
521		− case SIRF_REAL_SPI:
522		− writel(readl(sspi->base + sspi->regs->spi_ctrl) \|
523		− SIRFSOC_SPI_ENA_AUTO_CLR \|
524		− SIRFSOC_SPI_MUL_DAT_MODE,
525		− sspi->base + sspi->regs->spi_ctrl);
526		− writel(sspi->left_tx_word - 1,
527		− sspi->base + sspi->regs->tx_dma_io_len);
528		− writel(sspi->left_tx_word - 1,
529		− sspi->base + sspi->regs->rx_dma_io_len);
530		− break;
531		− case SIRF_USP_SPI_P2:
532		− case SIRF_USP_SPI_A7:
533		− /USP simulate SPI, tx/rx_dma_io_len indicates bytes/
534		− writel(sspi->left_tx_word * sspi->word_width,
535		− sspi->base + sspi->regs->tx_dma_io_len);
536		− writel(sspi->left_tx_word * sspi->word_width,
537		− sspi->base + sspi->regs->rx_dma_io_len);
538		− break;
539		− }
540		− } else {
541		− if (sspi->type == SIRF_REAL_SPI)
542		− writel(readl(sspi->base + sspi->regs->spi_ctrl),
543		− sspi->base + sspi->regs->spi_ctrl);
544		− writel(0, sspi->base + sspi->regs->tx_dma_io_len);
545		− writel(0, sspi->base + sspi->regs->rx_dma_io_len);
546		− }
547		− sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
548		− (t->tx_buf != t->rx_buf) ?
549		− DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
550		− rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
551		− sspi->dst_start, t->len, DMA_DEV_TO_MEM,
552		− DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
553		− rx_desc->callback = spi_sirfsoc_dma_fini_callback;
554		− rx_desc->callback_param = &sspi->rx_done;
555		−
556		− sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
557		− (t->tx_buf != t->rx_buf) ?
558		− DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
559		− tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
560		− sspi->src_start, t->len, DMA_MEM_TO_DEV,
561		− DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
562		− tx_desc->callback = spi_sirfsoc_dma_fini_callback;
563		− tx_desc->callback_param = &sspi->tx_done;
564		−
565		− dmaengine_submit(tx_desc);
566		− dmaengine_submit(rx_desc);
567		− dma_async_issue_pending(sspi->tx_chan);
568		− dma_async_issue_pending(sspi->rx_chan);
569		− writel(SIRFSOC_SPI_RX_EN \| SIRFSOC_SPI_TX_EN,
570		− sspi->base + sspi->regs->tx_rx_en);
571		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
572		− sspi->type == SIRF_USP_SPI_A7) {
573		− writel(SIRFSOC_SPI_FIFO_START,
574		− sspi->base + sspi->regs->rxfifo_op);
575		− writel(SIRFSOC_SPI_FIFO_START,
576		− sspi->base + sspi->regs->txfifo_op);
577		− }
578		− if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
579		− dev_err(&spi->dev, "transfer timeout\n");
580		− dmaengine_terminate_all(sspi->rx_chan);
581		− } else
582		− sspi->left_rx_word = 0;
583		− /*
584		− * we only wait tx-done event if transferring by DMA. for PIO,
585		− * we get rx data by writing tx data, so if rx is done, tx has
586		− * done earlier
587		− */
588		− if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
589		− dev_err(&spi->dev, "transfer timeout\n");
590		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
591		− sspi->type == SIRF_USP_SPI_A7)
592		− writel(0, sspi->base + sspi->regs->tx_rx_en);
593		− dmaengine_terminate_all(sspi->tx_chan);
594		− }
595		− dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
596		− dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
597		− /* TX, RX FIFO stop */
598		− writel(0, sspi->base + sspi->regs->rxfifo_op);
599		− writel(0, sspi->base + sspi->regs->txfifo_op);
600		− if (sspi->left_tx_word >= sspi->dat_max_frm_len)
601		− writel(0, sspi->base + sspi->regs->tx_rx_en);
602		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
603		− sspi->type == SIRF_USP_SPI_A7)
604		− writel(0, sspi->base + sspi->regs->tx_rx_en);
605		−}
606		−
607		−static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
608		− struct spi_transfer *t)
609		−{
610		− struct sirfsoc_spi *sspi;
611		− int timeout = t->len * 10;
612		− unsigned int data_units;
613		−
614		− sspi = spi_master_get_devdata(spi->master);
615		− do {
616		− writel(SIRFSOC_SPI_FIFO_RESET,
617		− sspi->base + sspi->regs->rxfifo_op);
618		− writel(SIRFSOC_SPI_FIFO_RESET,
619		− sspi->base + sspi->regs->txfifo_op);
620		− switch (sspi->type) {
621		− case SIRF_USP_SPI_P2:
622		− writel(0x0, sspi->base + sspi->regs->rxfifo_op);
623		− writel(0x0, sspi->base + sspi->regs->txfifo_op);
624		− writel(0, sspi->base + sspi->regs->int_en);
625		− writel(readl(sspi->base + sspi->regs->int_st),
626		− sspi->base + sspi->regs->int_st);
627		− writel(min((sspi->left_tx_word * sspi->word_width),
628		− sspi->fifo_size),
629		− sspi->base + sspi->regs->tx_dma_io_len);
630		− writel(min((sspi->left_rx_word * sspi->word_width),
631		− sspi->fifo_size),
632		− sspi->base + sspi->regs->rx_dma_io_len);
633		− break;
634		− case SIRF_USP_SPI_A7:
635		− writel(0x0, sspi->base + sspi->regs->rxfifo_op);
636		− writel(0x0, sspi->base + sspi->regs->txfifo_op);
637		− writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
638		− writel(readl(sspi->base + sspi->regs->int_st),
639		− sspi->base + sspi->regs->int_st);
640		− writel(min((sspi->left_tx_word * sspi->word_width),
641		− sspi->fifo_size),
642		− sspi->base + sspi->regs->tx_dma_io_len);
643		− writel(min((sspi->left_rx_word * sspi->word_width),
644		− sspi->fifo_size),
645		− sspi->base + sspi->regs->rx_dma_io_len);
646		− break;
647		− case SIRF_REAL_SPI:
648		− writel(SIRFSOC_SPI_FIFO_START,
649		− sspi->base + sspi->regs->rxfifo_op);
650		− writel(SIRFSOC_SPI_FIFO_START,
651		− sspi->base + sspi->regs->txfifo_op);
652		− writel(0, sspi->base + sspi->regs->int_en);
653		− writel(readl(sspi->base + sspi->regs->int_st),
654		− sspi->base + sspi->regs->int_st);
655		− writel(readl(sspi->base + sspi->regs->spi_ctrl) \|
656		− SIRFSOC_SPI_MUL_DAT_MODE \|
657		− SIRFSOC_SPI_ENA_AUTO_CLR,
658		− sspi->base + sspi->regs->spi_ctrl);
659		− data_units = sspi->fifo_size / sspi->word_width;
660		− writel(min(sspi->left_tx_word, data_units) - 1,
661		− sspi->base + sspi->regs->tx_dma_io_len);
662		− writel(min(sspi->left_rx_word, data_units) - 1,
663		− sspi->base + sspi->regs->rx_dma_io_len);
664		− break;
665		− }
666		− while (!((readl(sspi->base + sspi->regs->txfifo_st)
667		− & SIRFSOC_SPI_FIFO_FULL_MASK(sspi))) &&
668		− sspi->left_tx_word)
669		− sspi->tx_word(sspi);
670		− writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN \|
671		− SIRFSOC_SPI_TX_UFLOW_INT_EN \|
672		− SIRFSOC_SPI_RX_OFLOW_INT_EN \|
673		− SIRFSOC_SPI_RX_IO_DMA_INT_EN,
674		− sspi->base + sspi->regs->int_en);
675		− writel(SIRFSOC_SPI_RX_EN \| SIRFSOC_SPI_TX_EN,
676		− sspi->base + sspi->regs->tx_rx_en);
677		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
678		− sspi->type == SIRF_USP_SPI_A7) {
679		− writel(SIRFSOC_SPI_FIFO_START,
680		− sspi->base + sspi->regs->rxfifo_op);
681		− writel(SIRFSOC_SPI_FIFO_START,
682		− sspi->base + sspi->regs->txfifo_op);
683		− }
684		− if (!wait_for_completion_timeout(&sspi->tx_done, timeout) \|\|
685		− !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
686		− dev_err(&spi->dev, "transfer timeout\n");
687		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
688		− sspi->type == SIRF_USP_SPI_A7)
689		− writel(0, sspi->base + sspi->regs->tx_rx_en);
690		− break;
691		− }
692		− while (!((readl(sspi->base + sspi->regs->rxfifo_st)
693		− & SIRFSOC_SPI_FIFO_EMPTY_MASK(sspi))) &&
694		− sspi->left_rx_word)
695		− sspi->rx_word(sspi);
696		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
697		− sspi->type == SIRF_USP_SPI_A7)
698		− writel(0, sspi->base + sspi->regs->tx_rx_en);
699		− writel(0, sspi->base + sspi->regs->rxfifo_op);
700		− writel(0, sspi->base + sspi->regs->txfifo_op);
701		− } while (sspi->left_tx_word != 0 \|\| sspi->left_rx_word != 0);
702		−}
703		−
704		−static int spi_sirfsoc_transfer(struct spi_device spi, struct spi_transfer t)
705		−{
706		− struct sirfsoc_spi *sspi;
707		−
708		− sspi = spi_master_get_devdata(spi->master);
709		− sspi->tx = t->tx_buf;
710		− sspi->rx = t->rx_buf;
711		− sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
712		− reinit_completion(&sspi->rx_done);
713		− reinit_completion(&sspi->tx_done);
714		− /*
715		− * in the transfer, if transfer data using command register with rx_buf
716		− * null, just fill command data into command register and wait for its
717		− * completion.
718		− */
719		− if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd)
720		− spi_sirfsoc_cmd_transfer(spi, t);
721		− else if (IS_DMA_VALID(t))
722		− spi_sirfsoc_dma_transfer(spi, t);
723		− else
724		− spi_sirfsoc_pio_transfer(spi, t);
725		−
726		− return t->len - sspi->left_rx_word * sspi->word_width;
727		−}
728		−
729		−static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
730		−{
731		− struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
732		−
733		− if (sspi->hw_cs) {
734		− u32 regval;
735		−
736		− switch (sspi->type) {
737		− case SIRF_REAL_SPI:
738		− regval = readl(sspi->base + sspi->regs->spi_ctrl);
739		− switch (value) {
740		− case BITBANG_CS_ACTIVE:
741		− if (spi->mode & SPI_CS_HIGH)
742		− regval \|= SIRFSOC_SPI_CS_IO_OUT;
743		− else
744		− regval &= ~SIRFSOC_SPI_CS_IO_OUT;
745		− break;
746		− case BITBANG_CS_INACTIVE:
747		− if (spi->mode & SPI_CS_HIGH)
748		− regval &= ~SIRFSOC_SPI_CS_IO_OUT;
749		− else
750		− regval \|= SIRFSOC_SPI_CS_IO_OUT;
751		− break;
752		− }
753		− writel(regval, sspi->base + sspi->regs->spi_ctrl);
754		− break;
755		− case SIRF_USP_SPI_P2:
756		− case SIRF_USP_SPI_A7:
757		− regval = readl(sspi->base +
758		− sspi->regs->usp_pin_io_data);
759		− switch (value) {
760		− case BITBANG_CS_ACTIVE:
761		− if (spi->mode & SPI_CS_HIGH)
762		− regval \|= SIRFSOC_USP_CS_HIGH_VALUE;
763		− else
764		− regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
765		− break;
766		− case BITBANG_CS_INACTIVE:
767		− if (spi->mode & SPI_CS_HIGH)
768		− regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
769		− else
770		− regval \|= SIRFSOC_USP_CS_HIGH_VALUE;
771		− break;
772		− }
773		− writel(regval,
774		− sspi->base + sspi->regs->usp_pin_io_data);
775		− break;
776		− }
777		− } else {
778		− switch (value) {
779		− case BITBANG_CS_ACTIVE:
780		− gpio_direction_output(spi->cs_gpio,
781		− spi->mode & SPI_CS_HIGH ? 1 : 0);
782		− break;
783		− case BITBANG_CS_INACTIVE:
784		− gpio_direction_output(spi->cs_gpio,
785		− spi->mode & SPI_CS_HIGH ? 0 : 1);
786		− break;
787		− }
788		− }
789		−}
790		−
791		−static int spi_sirfsoc_config_mode(struct spi_device *spi)
792		−{
793		− struct sirfsoc_spi *sspi;
794		− u32 regval, usp_mode1;
795		−
796		− sspi = spi_master_get_devdata(spi->master);
797		− regval = readl(sspi->base + sspi->regs->spi_ctrl);
798		− usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1);
799		− if (!(spi->mode & SPI_CS_HIGH)) {
800		− regval \|= SIRFSOC_SPI_CS_IDLE_STAT;
801		− usp_mode1 &= ~SIRFSOC_USP_CS_HIGH_VALID;
802		− } else {
803		− regval &= ~SIRFSOC_SPI_CS_IDLE_STAT;
804		− usp_mode1 \|= SIRFSOC_USP_CS_HIGH_VALID;
805		− }
806		− if (!(spi->mode & SPI_LSB_FIRST)) {
807		− regval \|= SIRFSOC_SPI_TRAN_MSB;
808		− usp_mode1 &= ~SIRFSOC_USP_LSB;
809		− } else {
810		− regval &= ~SIRFSOC_SPI_TRAN_MSB;
811		− usp_mode1 \|= SIRFSOC_USP_LSB;
812		− }
813		− if (spi->mode & SPI_CPOL) {
814		− regval \|= SIRFSOC_SPI_CLK_IDLE_STAT;
815		− usp_mode1 \|= SIRFSOC_USP_SCLK_IDLE_STAT;
816		− } else {
817		− regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT;
818		− usp_mode1 &= ~SIRFSOC_USP_SCLK_IDLE_STAT;
819		− }
820		− /*
821		− * Data should be driven at least 1/2 cycle before the fetch edge
822		− * to make sure that data gets stable at the fetch edge.
823		− */
824		− if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) \|\|
825		− (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) {
826		− regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
827		− usp_mode1 \|= (SIRFSOC_USP_TXD_FALLING_EDGE \|
828		− SIRFSOC_USP_RXD_FALLING_EDGE);
829		− } else {
830		− regval \|= SIRFSOC_SPI_DRV_POS_EDGE;
831		− usp_mode1 &= ~(SIRFSOC_USP_RXD_FALLING_EDGE \|
832		− SIRFSOC_USP_TXD_FALLING_EDGE);
833		− }
834		− writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
835		− SIRFSOC_SPI_FIFO_SC_OFFSET) \|
836		− (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
837		− SIRFSOC_SPI_FIFO_LC_OFFSET) \|
838		− (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
839		− SIRFSOC_SPI_FIFO_HC_OFFSET),
840		− sspi->base + sspi->regs->txfifo_level_chk);
841		− writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
842		− SIRFSOC_SPI_FIFO_SC_OFFSET) \|
843		− (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
844		− SIRFSOC_SPI_FIFO_LC_OFFSET) \|
845		− (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
846		− SIRFSOC_SPI_FIFO_HC_OFFSET),
847		− sspi->base + sspi->regs->rxfifo_level_chk);
848		− /*
849		− * it should never set to hardware cs mode because in hardware cs mode,
850		− * cs signal can't controlled by driver.
851		− */
852		− switch (sspi->type) {
853		− case SIRF_REAL_SPI:
854		− regval \|= SIRFSOC_SPI_CS_IO_MODE;
855		− writel(regval, sspi->base + sspi->regs->spi_ctrl);
856		− break;
857		− case SIRF_USP_SPI_P2:
858		− case SIRF_USP_SPI_A7:
859		− usp_mode1 \|= SIRFSOC_USP_SYNC_MODE;
860		− usp_mode1 \|= SIRFSOC_USP_TFS_IO_MODE;
861		− usp_mode1 &= ~SIRFSOC_USP_TFS_IO_INPUT;
862		− writel(usp_mode1, sspi->base + sspi->regs->usp_mode1);
863		− break;
864		− }
865		−
866		− return 0;
867		−}
868		−
869		−static int
870		−spi_sirfsoc_setup_transfer(struct spi_device spi, struct spi_transfer t)
871		−{
872		− struct sirfsoc_spi *sspi;
873		− u8 bits_per_word = 0;
874		− int hz = 0;
875		− u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2;
876		−
877		− sspi = spi_master_get_devdata(spi->master);
878		−
879		− bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
880		− hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
881		−
882		− usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1;
883		− if (regval > 0xFFFF \|\| regval < 0) {
884		− dev_err(&spi->dev, "Speed %d not supported\n", hz);
885		− return -EINVAL;
886		− }
887		− switch (bits_per_word) {
888		− case 8:
889		− regval \|= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
890		− sspi->rx_word = spi_sirfsoc_rx_word_u8;
891		− sspi->tx_word = spi_sirfsoc_tx_word_u8;
892		− break;
893		− case 12:
894		− case 16:
895		− regval \|= (bits_per_word == 12) ?
896		− SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
897		− SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
898		− sspi->rx_word = spi_sirfsoc_rx_word_u16;
899		− sspi->tx_word = spi_sirfsoc_tx_word_u16;
900		− break;
901		− case 32:
902		− regval \|= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
903		− sspi->rx_word = spi_sirfsoc_rx_word_u32;
904		− sspi->tx_word = spi_sirfsoc_tx_word_u32;
905		− break;
906		− default:
907		− dev_err(&spi->dev, "bpw %d not supported\n", bits_per_word);
908		− return -EINVAL;
909		− }
910		− sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
911		− txfifo_ctrl = (((sspi->fifo_size / 2) &
912		− SIRFSOC_SPI_FIFO_THD_MASK(sspi))
913		− << SIRFSOC_SPI_FIFO_THD_OFFSET) \|
914		− (sspi->word_width >> 1);
915		− rxfifo_ctrl = (((sspi->fifo_size / 2) &
916		− SIRFSOC_SPI_FIFO_THD_MASK(sspi))
917		− << SIRFSOC_SPI_FIFO_THD_OFFSET) \|
918		− (sspi->word_width >> 1);
919		− writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl);
920		− writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl);
921		− if (sspi->type == SIRF_USP_SPI_P2 \|\|
922		− sspi->type == SIRF_USP_SPI_A7) {
923		− tx_frm_ctl = 0;
924		− tx_frm_ctl \|= ((bits_per_word - 1) & SIRFSOC_USP_TX_DATA_MASK)
925		− << SIRFSOC_USP_TX_DATA_OFFSET;
926		− tx_frm_ctl \|= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
927		− - 1) & SIRFSOC_USP_TX_SYNC_MASK) <<
928		− SIRFSOC_USP_TX_SYNC_OFFSET;
929		− tx_frm_ctl \|= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
930		− + 2 - 1) & SIRFSOC_USP_TX_FRAME_MASK) <<
931		− SIRFSOC_USP_TX_FRAME_OFFSET;
932		− tx_frm_ctl \|= ((bits_per_word - 1) &
933		− SIRFSOC_USP_TX_SHIFTER_MASK) <<
934		− SIRFSOC_USP_TX_SHIFTER_OFFSET;
935		− rx_frm_ctl = 0;
936		− rx_frm_ctl \|= ((bits_per_word - 1) & SIRFSOC_USP_RX_DATA_MASK)
937		− << SIRFSOC_USP_RX_DATA_OFFSET;
938		− rx_frm_ctl \|= ((bits_per_word + 1 + SIRFSOC_USP_RXD_DELAY_LEN
939		− + 2 - 1) & SIRFSOC_USP_RX_FRAME_MASK) <<
940		− SIRFSOC_USP_RX_FRAME_OFFSET;
941		− rx_frm_ctl \|= ((bits_per_word - 1)
942		− & SIRFSOC_USP_RX_SHIFTER_MASK) <<
943		− SIRFSOC_USP_RX_SHIFTER_OFFSET;
944		− writel(tx_frm_ctl \| (((usp_mode2 >> 10) &
945		− SIRFSOC_USP_CLK_10_11_MASK) <<
946		− SIRFSOC_USP_CLK_10_11_OFFSET),
947		− sspi->base + sspi->regs->usp_tx_frame_ctrl);
948		− writel(rx_frm_ctl \| (((usp_mode2 >> 12) &
949		− SIRFSOC_USP_CLK_12_15_MASK) <<
950		− SIRFSOC_USP_CLK_12_15_OFFSET),
951		− sspi->base + sspi->regs->usp_rx_frame_ctrl);
952		− writel(readl(sspi->base + sspi->regs->usp_mode2) \|
953		− ((usp_mode2 & SIRFSOC_USP_CLK_DIVISOR_MASK) <<
954		− SIRFSOC_USP_CLK_DIVISOR_OFFSET) \|
955		− (SIRFSOC_USP_RXD_DELAY_LEN <<
956		− SIRFSOC_USP_RXD_DELAY_OFFSET) \|
957		− (SIRFSOC_USP_TXD_DELAY_LEN <<
958		− SIRFSOC_USP_TXD_DELAY_OFFSET),
959		− sspi->base + sspi->regs->usp_mode2);
960		− }
961		− if (sspi->type == SIRF_REAL_SPI)
962		− writel(regval, sspi->base + sspi->regs->spi_ctrl);
963		− spi_sirfsoc_config_mode(spi);
964		− if (sspi->type == SIRF_REAL_SPI) {
965		− if (t && t->tx_buf && !t->rx_buf &&
966		− (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
967		− sspi->tx_by_cmd = true;
968		− writel(readl(sspi->base + sspi->regs->spi_ctrl) \|
969		− (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) \|
970		− SIRFSOC_SPI_CMD_MODE),
971		− sspi->base + sspi->regs->spi_ctrl);
972		− } else {
973		− sspi->tx_by_cmd = false;
974		− writel(readl(sspi->base + sspi->regs->spi_ctrl) &
975		− ~SIRFSOC_SPI_CMD_MODE,
976		− sspi->base + sspi->regs->spi_ctrl);
977		− }
978		− }
979		− if (IS_DMA_VALID(t)) {
980		− /* Enable DMA mode for RX, TX */
981		− writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl);
982		− writel(SIRFSOC_SPI_RX_DMA_FLUSH,
983		− sspi->base + sspi->regs->rx_dma_io_ctrl);
984		− } else {
985		− /* Enable IO mode for RX, TX */
986		− writel(SIRFSOC_SPI_IO_MODE_SEL,
987		− sspi->base + sspi->regs->tx_dma_io_ctrl);
988		− writel(SIRFSOC_SPI_IO_MODE_SEL,
989		− sspi->base + sspi->regs->rx_dma_io_ctrl);
990		− }
991		− return 0;
992		−}
993		−
994		−static int spi_sirfsoc_setup(struct spi_device *spi)
995		−{
996		− struct sirfsoc_spi *sspi;
997		− int ret = 0;
998		−
999		− sspi = spi_master_get_devdata(spi->master);
1000		− if (spi->cs_gpio == -ENOENT)
1001		− sspi->hw_cs = true;
1002		− else {
1003		− sspi->hw_cs = false;
1004		− if (!spi_get_ctldata(spi)) {
1005		− void *cs = kmalloc(sizeof(int), GFP_KERNEL);
1006		− if (!cs) {
1007		− ret = -ENOMEM;
1008		− goto exit;
1009		− }
1010		− ret = gpio_is_valid(spi->cs_gpio);
1011		− if (!ret) {
1012		− dev_err(&spi->dev, "no valid gpio\n");
1013		− ret = -ENOENT;
1014		− goto exit;
1015		− }
1016		− ret = gpio_request(spi->cs_gpio, DRIVER_NAME);
1017		− if (ret) {
1018		− dev_err(&spi->dev, "failed to request gpio\n");
1019		− goto exit;
1020		− }
1021		− spi_set_ctldata(spi, cs);
1022		− }
1023		− }
1024		− spi_sirfsoc_config_mode(spi);
1025		− spi_sirfsoc_chipselect(spi, BITBANG_CS_INACTIVE);
1026		−exit:
1027		− return ret;
1028		−}
1029		−
1030		−static void spi_sirfsoc_cleanup(struct spi_device *spi)
1031		−{
1032		− if (spi_get_ctldata(spi)) {
1033		− gpio_free(spi->cs_gpio);
1034		− kfree(spi_get_ctldata(spi));
1035		− }
1036		−}
1037		−
1038		−static const struct sirf_spi_comp_data sirf_real_spi = {
1039		− .regs = &real_spi_register,
1040		− .type = SIRF_REAL_SPI,
1041		− .dat_max_frm_len = 64 * 1024,
1042		− .fifo_size = 256,
1043		−};
1044		−
1045		−static const struct sirf_spi_comp_data sirf_usp_spi_p2 = {
1046		− .regs = &usp_spi_register,
1047		− .type = SIRF_USP_SPI_P2,
1048		− .dat_max_frm_len = 1024 * 1024,
1049		− .fifo_size = 128,
1050		− .hwinit = sirfsoc_usp_hwinit,
1051		−};
1052		−
1053		−static const struct sirf_spi_comp_data sirf_usp_spi_a7 = {
1054		− .regs = &usp_spi_register,
1055		− .type = SIRF_USP_SPI_A7,
1056		− .dat_max_frm_len = 1024 * 1024,
1057		− .fifo_size = 512,
1058		− .hwinit = sirfsoc_usp_hwinit,
1059		−};
1060		−
1061		−static const struct of_device_id spi_sirfsoc_of_match[] = {
1062		− { .compatible = "sirf,prima2-spi", .data = &sirf_real_spi},
1063		− { .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2},
1064		− { .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7},
1065		− {}
1066		−};
1067		−MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
1068		−
1069		−static int spi_sirfsoc_probe(struct platform_device *pdev)
1070		−{
1071		− struct sirfsoc_spi *sspi;
1072		− struct spi_master *master;
1073		− const struct sirf_spi_comp_data *spi_comp_data;
1074		− int irq;
1075		− int ret;
1076		− const struct of_device_id *match;
1077		−
1078		− ret = device_reset(&pdev->dev);
1079		− if (ret) {
1080		− dev_err(&pdev->dev, "SPI reset failed!\n");
1081		− return ret;
1082		− }
1083		−
1084		− master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
1085		− if (!master) {
1086		− dev_err(&pdev->dev, "Unable to allocate SPI master\n");
1087		− return -ENOMEM;
1088		− }
1089		− match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node);
1090		− platform_set_drvdata(pdev, master);
1091		− sspi = spi_master_get_devdata(master);
1092		− sspi->fifo_full_offset = ilog2(sspi->fifo_size);
1093		− spi_comp_data = match->data;
1094		− sspi->regs = spi_comp_data->regs;
1095		− sspi->type = spi_comp_data->type;
1096		− sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1;
1097		− sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len;
1098		− sspi->fifo_size = spi_comp_data->fifo_size;
1099		− sspi->base = devm_platform_ioremap_resource(pdev, 0);
1100		− if (IS_ERR(sspi->base)) {
1101		− ret = PTR_ERR(sspi->base);
1102		− goto free_master;
1103		− }
1104		− irq = platform_get_irq(pdev, 0);
1105		− if (irq < 0) {
1106		− ret = -ENXIO;
1107		− goto free_master;
1108		− }
1109		− ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
1110		− DRIVER_NAME, sspi);
1111		− if (ret)
1112		− goto free_master;
1113		−
1114		− sspi->bitbang.master = master;
1115		− sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
1116		− sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
1117		− sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
1118		− sspi->bitbang.master->setup = spi_sirfsoc_setup;
1119		− sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup;
1120		− master->bus_num = pdev->id;
1121		− master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LSB_FIRST \| SPI_CS_HIGH;
1122		− master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(12) \|
1123		− SPI_BPW_MASK(16) \| SPI_BPW_MASK(32);
1124		− master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
1125		− master->flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX;
1126		− sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
1127		−
1128		− /* request DMA channels */
1129		− sspi->rx_chan = dma_request_chan(&pdev->dev, "rx");
1130		− if (IS_ERR(sspi->rx_chan)) {
1131		− dev_err(&pdev->dev, "can not allocate rx dma channel\n");
1132		− ret = PTR_ERR(sspi->rx_chan);
1133		− goto free_master;
1134		− }
1135		− sspi->tx_chan = dma_request_chan(&pdev->dev, "tx");
1136		− if (IS_ERR(sspi->tx_chan)) {
1137		− dev_err(&pdev->dev, "can not allocate tx dma channel\n");
1138		− ret = PTR_ERR(sspi->tx_chan);
1139		− goto free_rx_dma;
1140		− }
1141		−
1142		− sspi->clk = clk_get(&pdev->dev, NULL);
1143		− if (IS_ERR(sspi->clk)) {
1144		− ret = PTR_ERR(sspi->clk);
1145		− goto free_tx_dma;
1146		− }
1147		− clk_prepare_enable(sspi->clk);
1148		− if (spi_comp_data->hwinit)
1149		− spi_comp_data->hwinit(sspi);
1150		− sspi->ctrl_freq = clk_get_rate(sspi->clk);
1151		−
1152		− init_completion(&sspi->rx_done);
1153		− init_completion(&sspi->tx_done);
1154		−
1155		− ret = spi_bitbang_start(&sspi->bitbang);
1156		− if (ret)
1157		− goto free_clk;
1158		− dev_info(&pdev->dev, "registered, bus number = %d\n", master->bus_num);
1159		−
1160		− return 0;
1161		−free_clk:
1162		− clk_disable_unprepare(sspi->clk);
1163		− clk_put(sspi->clk);
1164		−free_tx_dma:
1165		− dma_release_channel(sspi->tx_chan);
1166		−free_rx_dma:
1167		− dma_release_channel(sspi->rx_chan);
1168		−free_master:
1169		− spi_master_put(master);
1170		−
1171		− return ret;
1172		−}
1173		−
1174		−static int spi_sirfsoc_remove(struct platform_device *pdev)
1175		−{
1176		− struct spi_master *master;
1177		− struct sirfsoc_spi *sspi;
1178		−
1179		− master = platform_get_drvdata(pdev);
1180		− sspi = spi_master_get_devdata(master);
1181		− spi_bitbang_stop(&sspi->bitbang);
1182		− clk_disable_unprepare(sspi->clk);
1183		− clk_put(sspi->clk);
1184		− dma_release_channel(sspi->rx_chan);
1185		− dma_release_channel(sspi->tx_chan);
1186		− spi_master_put(master);
1187		− return 0;
1188		−}
1189		−
1190		−#ifdef CONFIG_PM_SLEEP
1191		−static int spi_sirfsoc_suspend(struct device *dev)
1192		−{
1193		− struct spi_master *master = dev_get_drvdata(dev);
1194		− struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
1195		− int ret;
1196		−
1197		− ret = spi_master_suspend(master);
1198		− if (ret)
1199		− return ret;
1200		−
1201		− clk_disable(sspi->clk);
1202		− return 0;
1203		−}
1204		−
1205		−static int spi_sirfsoc_resume(struct device *dev)
1206		−{
1207		− struct spi_master *master = dev_get_drvdata(dev);
1208		− struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
1209		−
1210		− clk_enable(sspi->clk);
1211		− writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
1212		− writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
1213		− writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
1214		− writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op);
1215		− return 0;
1216		−}
1217		−#endif
1218		−
1219		−static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
1220		− spi_sirfsoc_resume);
1221		−
1222		−static struct platform_driver spi_sirfsoc_driver = {
1223		− .driver = {
1224		− .name = DRIVER_NAME,
1225		− .pm = &spi_sirfsoc_pm_ops,
1226		− .of_match_table = spi_sirfsoc_of_match,
1227		− },
1228		− .probe = spi_sirfsoc_probe,
1229		− .remove = spi_sirfsoc_remove,
1230		−};
1231		−module_platform_driver(spi_sirfsoc_driver);
1232		−MODULE_DESCRIPTION("SiRF SoC SPI master driver");
1233		−MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
1234		−MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
1235		−MODULE_AUTHOR("Qipan Li <Qipan.Li@csr.com>");
1236		−MODULE_LICENSE("GPL v2");

drivers/spi/spi-stm32.c+60−90

@@ -5,6 +5,7 @@ · 4 unmodified lines
5	5	// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6	6	// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7	7
	8	+#include <linux/bitfield.h>
8	9	#include <linux/debugfs.h>
9	10	#include <linux/clk.h>
10	11	#include <linux/delay.h>
@@ -94,27 +95,22 @@ · 83 unmodified lines
94	95	#define STM32H7_SPI_CR1_SSI BIT(12)
95	96
96	97	/* STM32H7_SPI_CR2 bit fields */
97		−#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
98	98	#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
	99	+#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
99	100
100	101	/* STM32H7_SPI_CFG1 bit fields */
101		−#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
102	102	#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103		−#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
104	103	#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
105	104	#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
106	105	#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
107		−#define STM32H7_SPI_CFG1_MBR_SHIFT 28
108	106	#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
	107	+#define STM32H7_SPI_CFG1_MBR_SHIFT 28
109	108	#define STM32H7_SPI_CFG1_MBR_MIN 0
110	109	#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
111	110
112	111	/* STM32H7_SPI_CFG2 bit fields */
113		−#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
114	112	#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
115		−#define STM32H7_SPI_CFG2_COMM_SHIFT 17
116	113	#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
117		−#define STM32H7_SPI_CFG2_SP_SHIFT 19
118	114	#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
119	115	#define STM32H7_SPI_CFG2_MASTER BIT(22)
120	116	#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
@@ -140,7 +136,6 @@ · 19 unmodified lines
140	136	#define STM32H7_SPI_SR_OVR BIT(6)
141	137	#define STM32H7_SPI_SR_MODF BIT(9)
142	138	#define STM32H7_SPI_SR_SUSP BIT(11)
143		−#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
144	139	#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
145	140	#define STM32H7_SPI_SR_RXWNE BIT(15)
146	141
@@ -167,8 +162,6 @@ · 20 unmodified lines
167	162	#define SPI_3WIRE_TX 3
168	163	#define SPI_3WIRE_RX 4
169	164
170		−#define SPI_1HZ_NS 1000000000
171		−
172	165	/*
173	166	* use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
174	167	* without fifo buffers.
@@ -268,7 +261,6 @@ struct stm32_spi_cfg { · 93 unmodified lines
268	261	* @base: virtual memory area
269	262	* @clk: hw kernel clock feeding the SPI clock generator
270	263	* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
271		− * @rst: SPI controller reset line
272	264	* @lock: prevent I/O concurrent access
273	265	* @irq: SPI controller interrupt line
274	266	* @fifo_size: size of the embedded fifo in bytes
@@ -294,7 +286,6 @@ struct stm32_spi { · 19 unmodified lines
294	286	void __iomem *base;
295	287	struct clk *clk;
296	288	u32 clk_rate;
297		− struct reset_control *rst;
298	289	spinlock_t lock; /* prevent I/O concurrent access */
299	290	int irq;
300	291	unsigned int fifo_size;
@@ -417,9 +408,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) · 116 unmodified lines
417	408	stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
418	409
419	410	cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
420		− max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
421		− STM32H7_SPI_CFG1_DSIZE_SHIFT;
422		− max_bpw += 1;
	411	+ max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
423	412
424	413	spin_unlock_irqrestore(&spi->lock, flags);
425	414
@@ -473,34 +462,14 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, · 47 unmodified lines
473	462	*/
474	463	static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
475	464	{
476		− u32 fthlv, half_fifo, packet;
	465	+ u32 packet, bpw;
477	466
478	467	/* data packet should not exceed 1/2 of fifo space */
479		− half_fifo = (spi->fifo_size / 2);
480		−
481		− /* data_packet should not exceed transfer length */
482		− if (half_fifo > xfer_len)
483		− packet = xfer_len;
484		− else
485		− packet = half_fifo;
486		−
487		− if (spi->cur_bpw <= 8)
488		− fthlv = packet;
489		− else if (spi->cur_bpw <= 16)
490		− fthlv = packet / 2;
491		− else
492		− fthlv = packet / 4;
	468	+ packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
493	469
494	470	/* align packet size with data registers access */
495		− if (spi->cur_bpw > 8)
496		− fthlv += (fthlv % 2) ? 1 : 0;
497		− else
498		− fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
499		−
500		− if (!fthlv)
501		− fthlv = 1;
502		−
503		− return fthlv;
	471	+ bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
	472	+ return DIV_ROUND_UP(packet, bpw);
504	473	}
505	474
506	475	/**
@@ -607,8 +576,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi) · 100 unmodified lines
607	576	static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
608	577	{
609	578	u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
610		− u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
611		− STM32H7_SPI_SR_RXPLVL_SHIFT;
	579	+ u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
612	580
613	581	while ((spi->rx_len > 0) &&
614	582	((sr & STM32H7_SPI_SR_RXP) \|\|
@@ -635,8 +603,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) · 20 unmodified lines
635	603	}
636	604
637	605	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
638		− rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
639		− STM32H7_SPI_SR_RXPLVL_SHIFT;
	606	+ rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
640	607	}
641	608
642	609	dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@@ -928,8 +895,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) · 285 unmodified lines
928	895	mask \|= STM32H7_SPI_SR_RXP;
929	896
930	897	if (!(sr & mask)) {
931		− dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
932		− sr, ier);
	898	+ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
	899	+ sr, ier);
933	900	spin_unlock_irqrestore(&spi->lock, flags);
934	901	return IRQ_NONE;
935	902	}
@@ -956,15 +923,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) · 20 unmodified lines
956	923	}
957	924
958	925	if (sr & STM32H7_SPI_SR_OVR) {
959		− dev_warn(spi->dev, "Overrun: received value discarded\n");
960		− if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
961		− stm32h7_spi_read_rxfifo(spi, false);
962		− /*
963		− * If overrun is detected while using DMA, it means that
964		− * something went wrong, so stop the current transfer
965		− */
966		− if (spi->cur_usedma)
967		− end = true;
	926	+ dev_err(spi->dev, "Overrun: RX data lost\n");
	927	+ end = true;
968	928	}
969	929
970	930	if (sr & STM32H7_SPI_SR_EOT) {
@@ -1028,10 +988,24 @@ static int stm32_spi_prepare_msg(struct spi_master *master, · 57 unmodified lines
1028	988	clrb \|= spi->cfg->regs->lsb_first.mask;
1029	989
1030	990	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1031		− spi_dev->mode & SPI_CPOL,
1032		− spi_dev->mode & SPI_CPHA,
1033		− spi_dev->mode & SPI_LSB_FIRST,
1034		− spi_dev->mode & SPI_CS_HIGH);
	991	+ !!(spi_dev->mode & SPI_CPOL),
	992	+ !!(spi_dev->mode & SPI_CPHA),
	993	+ !!(spi_dev->mode & SPI_LSB_FIRST),
	994	+ !!(spi_dev->mode & SPI_CS_HIGH));
	995	+
	996	+ /* On STM32H7, messages should not exceed a maximum size setted
	997	+ * afterward via the set_number_of_data function. In order to
	998	+ * ensure that, split large messages into several messages
	999	+ */
	1000	+ if (spi->cfg->set_number_of_data) {
	1001	+ int ret;
	1002	+
	1003	+ ret = spi_split_transfers_maxsize(master, msg,
	1004	+ STM32H7_SPI_TSIZE_MAX,
	1005	+ GFP_KERNEL \| GFP_DMA);
	1006	+ if (ret)
	1007	+ return ret;
	1008	+ }
1035	1009
1036	1010	spin_lock_irqsave(&spi->lock, flags);
1037	1011
@@ -1405,15 +1379,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi) · 367 unmodified lines
1405	1379	bpw = spi->cur_bpw - 1;
1406	1380
1407	1381	cfg1_clrb \|= STM32H7_SPI_CFG1_DSIZE;
1408		− cfg1_setb \|= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
1409		− STM32H7_SPI_CFG1_DSIZE;
	1382	+ cfg1_setb \|= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1410	1383
1411	1384	spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1412	1385	fthlv = spi->cur_fthlv - 1;
1413	1386
1414	1387	cfg1_clrb \|= STM32H7_SPI_CFG1_FTHLV;
1415		− cfg1_setb \|= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
1416		− STM32H7_SPI_CFG1_FTHLV;
	1388	+ cfg1_setb \|= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1417	1389
1418	1390	writel_relaxed(
1419	1391	(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
@@ -1431,8 +1403,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) · 11 unmodified lines
1431	1403	u32 clrb = 0, setb = 0;
1432	1404
1433	1405	clrb \|= spi->cfg->regs->br.mask;
1434		− setb \|= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1435		− spi->cfg->regs->br.mask;
	1406	+ setb \|= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1436	1407
1437	1408	writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1438	1409	~clrb) \| setb,
@@ -1523,8 +1494,7 @@ static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) · 84 unmodified lines
1523	1494	}
1524	1495
1525	1496	cfg2_clrb \|= STM32H7_SPI_CFG2_COMM;
1526		− cfg2_setb \|= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
1527		− STM32H7_SPI_CFG2_COMM;
	1497	+ cfg2_setb \|= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1528	1498
1529	1499	writel_relaxed(
1530	1500	(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
@@ -1546,15 +1516,16 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) · 15 unmodified lines
1546	1516
1547	1517	cfg2_clrb \|= STM32H7_SPI_CFG2_MIDI;
1548	1518	if ((len > 1) && (spi->cur_midi > 0)) {
1549		− u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1550		− u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1551		− (u32)STM32H7_SPI_CFG2_MIDI >>
1552		− STM32H7_SPI_CFG2_MIDI_SHIFT);
	1519	+ u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
	1520	+ u32 midi = min_t(u32,
	1521	+ DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
	1522	+ FIELD_GET(STM32H7_SPI_CFG2_MIDI,
	1523	+ STM32H7_SPI_CFG2_MIDI));
	1524	+
1553	1525
1554	1526	dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1555	1527	sck_period_ns, midi, midi * sck_period_ns);
1556		− cfg2_setb \|= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
1557		− STM32H7_SPI_CFG2_MIDI;
	1528	+ cfg2_setb \|= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1558	1529	}
1559	1530
1560	1531	writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
@@ -1569,14 +1540,8 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) · 8 unmodified lines
1569	1540	*/
1570	1541	static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1571	1542	{
1572		− u32 cr2_clrb = 0, cr2_setb = 0;
1573		−
1574		− if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
1575		− STM32H7_SPI_CR2_TSIZE_SHIFT)) {
1576		− cr2_clrb \|= STM32H7_SPI_CR2_TSIZE;
1577		− cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
1578		− writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1579		− ~cr2_clrb) \| cr2_setb,
	1543	+ if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
	1544	+ writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1580	1545	spi->base + STM32H7_SPI_CR2);
1581	1546	} else {
1582	1547	return -EMSGSIZE;
@@ -1677,6 +1642,10 @@ static int stm32_spi_transfer_one(struct spi_master *master, · 94 unmodified lines
1677	1642	struct stm32_spi *spi = spi_master_get_devdata(master);
1678	1643	int ret;
1679	1644
	1645	+ /* Don't do anything on 0 bytes transfers */
	1646	+ if (transfer->len == 0)
	1647	+ return 0;
	1648	+
1680	1649	spi->tx_buf = transfer->tx_buf;
1681	1650	spi->rx_buf = transfer->rx_buf;
1682	1651	spi->tx_len = spi->tx_buf ? transfer->len : 0;
@@ -1831,6 +1800,7 @@ static int stm32_spi_probe(struct platform_device *pdev) · 148 unmodified lines
1831	1800	struct spi_master *master;
1832	1801	struct stm32_spi *spi;
1833	1802	struct resource *res;
	1803	+ struct reset_control *rst;
1834	1804	int ret;
1835	1805
1836	1806	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
@@ -1892,11 +1862,17 @@ static int stm32_spi_probe(struct platform_device *pdev) · 55 unmodified lines
1892	1862	goto err_clk_disable;
1893	1863	}
1894	1864
1895		− spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1896		− if (!IS_ERR(spi->rst)) {
1897		− reset_control_assert(spi->rst);
	1865	+ rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
	1866	+ if (rst) {
	1867	+ if (IS_ERR(rst)) {
	1868	+ ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
	1869	+ "failed to get reset\n");
	1870	+ goto err_clk_disable;
	1871	+ }
	1872	+
	1873	+ reset_control_assert(rst);
1898	1874	udelay(2);
1899		− reset_control_deassert(spi->rst);
	1875	+ reset_control_deassert(rst);
1900	1876	}
1901	1877
1902	1878	if (spi->cfg->has_fifo)
@@ -1960,12 +1936,6 @@ static int stm32_spi_probe(struct platform_device *pdev) · 57 unmodified lines
1960	1936	goto err_pm_disable;
1961	1937	}
1962	1938
1963		− if (!master->cs_gpiods) {
1964		− dev_err(&pdev->dev, "no CS gpios available\n");
1965		− ret = -EINVAL;
1966		− goto err_pm_disable;
1967		− }
1968		−
1969	1939	dev_info(&pdev->dev, "driver initialized\n");
1970	1940
1971	1941	return 0;

drivers/spi/spi-synquacer.c+4−0

@@ -490,6 +490,10 @@ static void synquacer_spi_set_cs(struct spi_device *spi, bool enable) · 489 unmodified lines
490	490	val &= ~(SYNQUACER_HSSPI_DMPSEL_CS_MASK <<
491	491	SYNQUACER_HSSPI_DMPSEL_CS_SHIFT);
492	492	val \|= spi->chip_select << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT;
	493	+
	494	+ if (!enable)
	495	+ val \|= SYNQUACER_HSSPI_DMSTOP_STOP;
	496	+
493	497	writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
494	498	}
495	499

drivers/spi/spi-tegra210-quad.c+1410−0

@@ -0,0 +1,1410 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+//
	3	+// Copyright (C) 2020 NVIDIA CORPORATION.
	4	+
	5	+#include <linux/clk.h>
	6	+#include <linux/completion.h>
	7	+#include <linux/delay.h>
	8	+#include <linux/dmaengine.h>
	9	+#include <linux/dma-mapping.h>
	10	+#include <linux/dmapool.h>
	11	+#include <linux/err.h>
	12	+#include <linux/interrupt.h>
	13	+#include <linux/io.h>
	14	+#include <linux/iopoll.h>
	15	+#include <linux/kernel.h>
	16	+#include <linux/kthread.h>
	17	+#include <linux/module.h>
	18	+#include <linux/platform_device.h>
	19	+#include <linux/pm_runtime.h>
	20	+#include <linux/of.h>
	21	+#include <linux/of_device.h>
	22	+#include <linux/reset.h>
	23	+#include <linux/spi/spi.h>
	24	+
	25	+#define QSPI_COMMAND1 0x000
	26	+#define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
	27	+#define QSPI_PACKED BIT(5)
	28	+#define QSPI_INTERFACE_WIDTH_MASK (0x03 << 7)
	29	+#define QSPI_INTERFACE_WIDTH(x) (((x) & 0x03) << 7)
	30	+#define QSPI_INTERFACE_WIDTH_SINGLE QSPI_INTERFACE_WIDTH(0)
	31	+#define QSPI_INTERFACE_WIDTH_DUAL QSPI_INTERFACE_WIDTH(1)
	32	+#define QSPI_INTERFACE_WIDTH_QUAD QSPI_INTERFACE_WIDTH(2)
	33	+#define QSPI_SDR_DDR_SEL BIT(9)
	34	+#define QSPI_TX_EN BIT(11)
	35	+#define QSPI_RX_EN BIT(12)
	36	+#define QSPI_CS_SW_VAL BIT(20)
	37	+#define QSPI_CS_SW_HW BIT(21)
	38	+#define QSPI_CONTROL_MODE_0 (0 << 28)
	39	+#define QSPI_CONTROL_MODE_3 (3 << 28)
	40	+#define QSPI_CONTROL_MODE_MASK (3 << 28)
	41	+#define QSPI_M_S BIT(30)
	42	+#define QSPI_PIO BIT(31)
	43	+
	44	+#define QSPI_COMMAND2 0x004
	45	+#define QSPI_TX_TAP_DELAY(x) (((x) & 0x3f) << 10)
	46	+#define QSPI_RX_TAP_DELAY(x) (((x) & 0xff) << 0)
	47	+
	48	+#define QSPI_CS_TIMING1 0x008
	49	+#define QSPI_SETUP_HOLD(setup, hold) (((setup) << 4) \| (hold))
	50	+
	51	+#define QSPI_CS_TIMING2 0x00c
	52	+#define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1f) << 0)
	53	+#define CS_ACTIVE_BETWEEN_PACKETS_0 BIT(5)
	54	+
	55	+#define QSPI_TRANS_STATUS 0x010
	56	+#define QSPI_BLK_CNT(val) (((val) >> 0) & 0xffff)
	57	+#define QSPI_RDY BIT(30)
	58	+
	59	+#define QSPI_FIFO_STATUS 0x014
	60	+#define QSPI_RX_FIFO_EMPTY BIT(0)
	61	+#define QSPI_RX_FIFO_FULL BIT(1)
	62	+#define QSPI_TX_FIFO_EMPTY BIT(2)
	63	+#define QSPI_TX_FIFO_FULL BIT(3)
	64	+#define QSPI_RX_FIFO_UNF BIT(4)
	65	+#define QSPI_RX_FIFO_OVF BIT(5)
	66	+#define QSPI_TX_FIFO_UNF BIT(6)
	67	+#define QSPI_TX_FIFO_OVF BIT(7)
	68	+#define QSPI_ERR BIT(8)
	69	+#define QSPI_TX_FIFO_FLUSH BIT(14)
	70	+#define QSPI_RX_FIFO_FLUSH BIT(15)
	71	+#define QSPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7f)
	72	+#define QSPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7f)
	73	+
	74	+#define QSPI_FIFO_ERROR (QSPI_RX_FIFO_UNF \| \
	75	+ QSPI_RX_FIFO_OVF \| \
	76	+ QSPI_TX_FIFO_UNF \| \
	77	+ QSPI_TX_FIFO_OVF)
	78	+#define QSPI_FIFO_EMPTY (QSPI_RX_FIFO_EMPTY \| \
	79	+ QSPI_TX_FIFO_EMPTY)
	80	+
	81	+#define QSPI_TX_DATA 0x018
	82	+#define QSPI_RX_DATA 0x01c
	83	+
	84	+#define QSPI_DMA_CTL 0x020
	85	+#define QSPI_TX_TRIG(n) (((n) & 0x3) << 15)
	86	+#define QSPI_TX_TRIG_1 QSPI_TX_TRIG(0)
	87	+#define QSPI_TX_TRIG_4 QSPI_TX_TRIG(1)
	88	+#define QSPI_TX_TRIG_8 QSPI_TX_TRIG(2)
	89	+#define QSPI_TX_TRIG_16 QSPI_TX_TRIG(3)
	90	+
	91	+#define QSPI_RX_TRIG(n) (((n) & 0x3) << 19)
	92	+#define QSPI_RX_TRIG_1 QSPI_RX_TRIG(0)
	93	+#define QSPI_RX_TRIG_4 QSPI_RX_TRIG(1)
	94	+#define QSPI_RX_TRIG_8 QSPI_RX_TRIG(2)
	95	+#define QSPI_RX_TRIG_16 QSPI_RX_TRIG(3)
	96	+
	97	+#define QSPI_DMA_EN BIT(31)
	98	+
	99	+#define QSPI_DMA_BLK 0x024
	100	+#define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0)
	101	+
	102	+#define QSPI_TX_FIFO 0x108
	103	+#define QSPI_RX_FIFO 0x188
	104	+
	105	+#define QSPI_FIFO_DEPTH 64
	106	+
	107	+#define QSPI_INTR_MASK 0x18c
	108	+#define QSPI_INTR_RX_FIFO_UNF_MASK BIT(25)
	109	+#define QSPI_INTR_RX_FIFO_OVF_MASK BIT(26)
	110	+#define QSPI_INTR_TX_FIFO_UNF_MASK BIT(27)
	111	+#define QSPI_INTR_TX_FIFO_OVF_MASK BIT(28)
	112	+#define QSPI_INTR_RDY_MASK BIT(29)
	113	+#define QSPI_INTR_RX_TX_FIFO_ERR (QSPI_INTR_RX_FIFO_UNF_MASK \| \
	114	+ QSPI_INTR_RX_FIFO_OVF_MASK \| \
	115	+ QSPI_INTR_TX_FIFO_UNF_MASK \| \
	116	+ QSPI_INTR_TX_FIFO_OVF_MASK)
	117	+
	118	+#define QSPI_MISC_REG 0x194
	119	+#define QSPI_NUM_DUMMY_CYCLE(x) (((x) & 0xff) << 0)
	120	+#define QSPI_DUMMY_CYCLES_MAX 0xff
	121	+
	122	+#define DATA_DIR_TX BIT(0)
	123	+#define DATA_DIR_RX BIT(1)
	124	+
	125	+#define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
	126	+#define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024)
	127	+
	128	+struct tegra_qspi_client_data {
	129	+ int tx_clk_tap_delay;
	130	+ int rx_clk_tap_delay;
	131	+};
	132	+
	133	+struct tegra_qspi {
	134	+ struct device *dev;
	135	+ struct spi_master *master;
	136	+ /* lock to protect data accessed by irq */
	137	+ spinlock_t lock;
	138	+
	139	+ struct clk *clk;
	140	+ struct reset_control *rst;
	141	+ void __iomem *base;
	142	+ phys_addr_t phys;
	143	+ unsigned int irq;
	144	+
	145	+ u32 cur_speed;
	146	+ unsigned int cur_pos;
	147	+ unsigned int words_per_32bit;
	148	+ unsigned int bytes_per_word;
	149	+ unsigned int curr_dma_words;
	150	+ unsigned int cur_direction;
	151	+
	152	+ unsigned int cur_rx_pos;
	153	+ unsigned int cur_tx_pos;
	154	+
	155	+ unsigned int dma_buf_size;
	156	+ unsigned int max_buf_size;
	157	+ bool is_curr_dma_xfer;
	158	+
	159	+ struct completion rx_dma_complete;
	160	+ struct completion tx_dma_complete;
	161	+
	162	+ u32 tx_status;
	163	+ u32 rx_status;
	164	+ u32 status_reg;
	165	+ bool is_packed;
	166	+ bool use_dma;
	167	+
	168	+ u32 command1_reg;
	169	+ u32 dma_control_reg;
	170	+ u32 def_command1_reg;
	171	+ u32 def_command2_reg;
	172	+ u32 spi_cs_timing1;
	173	+ u32 spi_cs_timing2;
	174	+ u8 dummy_cycles;
	175	+
	176	+ struct completion xfer_completion;
	177	+ struct spi_transfer *curr_xfer;
	178	+
	179	+ struct dma_chan *rx_dma_chan;
	180	+ u32 *rx_dma_buf;
	181	+ dma_addr_t rx_dma_phys;
	182	+ struct dma_async_tx_descriptor *rx_dma_desc;
	183	+
	184	+ struct dma_chan *tx_dma_chan;
	185	+ u32 *tx_dma_buf;
	186	+ dma_addr_t tx_dma_phys;
	187	+ struct dma_async_tx_descriptor *tx_dma_desc;
	188	+};
	189	+
	190	+static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset)
	191	+{
	192	+ return readl(tqspi->base + offset);
	193	+}
	194	+
	195	+static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset)
	196	+{
	197	+ writel(value, tqspi->base + offset);
	198	+
	199	+ /* read back register to make sure that register writes completed */
	200	+ if (offset != QSPI_TX_FIFO)
	201	+ readl(tqspi->base + QSPI_COMMAND1);
	202	+}
	203	+
	204	+static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi)
	205	+{
	206	+ u32 value;
	207	+
	208	+ /* write 1 to clear status register */
	209	+ value = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS);
	210	+ tegra_qspi_writel(tqspi, value, QSPI_TRANS_STATUS);
	211	+
	212	+ value = tegra_qspi_readl(tqspi, QSPI_INTR_MASK);
	213	+ if (!(value & QSPI_INTR_RDY_MASK)) {
	214	+ value \|= (QSPI_INTR_RDY_MASK \| QSPI_INTR_RX_TX_FIFO_ERR);
	215	+ tegra_qspi_writel(tqspi, value, QSPI_INTR_MASK);
	216	+ }
	217	+
	218	+ /* clear fifo status error if any */
	219	+ value = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
	220	+ if (value & QSPI_ERR)
	221	+ tegra_qspi_writel(tqspi, QSPI_ERR \| QSPI_FIFO_ERROR, QSPI_FIFO_STATUS);
	222	+}
	223	+
	224	+static unsigned int
	225	+tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi tqspi, struct spi_transfer t)
	226	+{
	227	+ unsigned int max_word, max_len, total_fifo_words;
	228	+ unsigned int remain_len = t->len - tqspi->cur_pos;
	229	+ unsigned int bits_per_word = t->bits_per_word;
	230	+
	231	+ tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
	232	+
	233	+ /*
	234	+ * Tegra QSPI controller supports packed or unpacked mode transfers.
	235	+ * Packed mode is used for data transfers using 8, 16, or 32 bits per
	236	+ * word with a minimum transfer of 1 word and for all other transfers
	237	+ * unpacked mode will be used.
	238	+ */
	239	+
	240	+ if ((bits_per_word == 8 \|\| bits_per_word == 16 \|\|
	241	+ bits_per_word == 32) && t->len > 3) {
	242	+ tqspi->is_packed = true;
	243	+ tqspi->words_per_32bit = 32 / bits_per_word;
	244	+ } else {
	245	+ tqspi->is_packed = false;
	246	+ tqspi->words_per_32bit = 1;
	247	+ }
	248	+
	249	+ if (tqspi->is_packed) {
	250	+ max_len = min(remain_len, tqspi->max_buf_size);
	251	+ tqspi->curr_dma_words = max_len / tqspi->bytes_per_word;
	252	+ total_fifo_words = (max_len + 3) / 4;
	253	+ } else {
	254	+ max_word = (remain_len - 1) / tqspi->bytes_per_word + 1;
	255	+ max_word = min(max_word, tqspi->max_buf_size / 4);
	256	+ tqspi->curr_dma_words = max_word;
	257	+ total_fifo_words = max_word;
	258	+ }
	259	+
	260	+ return total_fifo_words;
	261	+}
	262	+
	263	+static unsigned int
	264	+tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi tqspi, struct spi_transfer t)
	265	+{
	266	+ unsigned int written_words, fifo_words_left, count;
	267	+ unsigned int len, tx_empty_count, max_n_32bit, i;
	268	+ u8 tx_buf = (u8 )t->tx_buf + tqspi->cur_tx_pos;
	269	+ u32 fifo_status;
	270	+
	271	+ fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
	272	+ tx_empty_count = QSPI_TX_FIFO_EMPTY_COUNT(fifo_status);
	273	+
	274	+ if (tqspi->is_packed) {
	275	+ fifo_words_left = tx_empty_count * tqspi->words_per_32bit;
	276	+ written_words = min(fifo_words_left, tqspi->curr_dma_words);
	277	+ len = written_words * tqspi->bytes_per_word;
	278	+ max_n_32bit = DIV_ROUND_UP(len, 4);
	279	+ for (count = 0; count < max_n_32bit; count++) {
	280	+ u32 x = 0;
	281	+
	282	+ for (i = 0; (i < 4) && len; i++, len--)
	283	+ x \|= (u32)(tx_buf++) << (i 8);
	284	+ tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
	285	+ }
	286	+
	287	+ tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word;
	288	+ } else {
	289	+ unsigned int write_bytes;
	290	+ u8 bytes_per_word = tqspi->bytes_per_word;
	291	+
	292	+ max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count);
	293	+ written_words = max_n_32bit;
	294	+ len = written_words * tqspi->bytes_per_word;
	295	+ if (len > t->len - tqspi->cur_pos)
	296	+ len = t->len - tqspi->cur_pos;
	297	+ write_bytes = len;
	298	+ for (count = 0; count < max_n_32bit; count++) {
	299	+ u32 x = 0;
	300	+
	301	+ for (i = 0; len && (i < bytes_per_word); i++, len--)
	302	+ x \|= (u32)(tx_buf++) << (i 8);
	303	+ tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
	304	+ }
	305	+
	306	+ tqspi->cur_tx_pos += write_bytes;
	307	+ }
	308	+
	309	+ return written_words;
	310	+}
	311	+
	312	+static unsigned int
	313	+tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi tqspi, struct spi_transfer t)
	314	+{
	315	+ u8 rx_buf = (u8 )t->rx_buf + tqspi->cur_rx_pos;
	316	+ unsigned int len, rx_full_count, count, i;
	317	+ unsigned int read_words = 0;
	318	+ u32 fifo_status, x;
	319	+
	320	+ fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
	321	+ rx_full_count = QSPI_RX_FIFO_FULL_COUNT(fifo_status);
	322	+ if (tqspi->is_packed) {
	323	+ len = tqspi->curr_dma_words * tqspi->bytes_per_word;
	324	+ for (count = 0; count < rx_full_count; count++) {
	325	+ x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO);
	326	+
	327	+ for (i = 0; len && (i < 4); i++, len--)
	328	+ rx_buf++ = (x >> i 8) & 0xff;
	329	+ }
	330	+
	331	+ read_words += tqspi->curr_dma_words;
	332	+ tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
	333	+ } else {
	334	+ u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
	335	+ u8 bytes_per_word = tqspi->bytes_per_word;
	336	+ unsigned int read_bytes;
	337	+
	338	+ len = rx_full_count * bytes_per_word;
	339	+ if (len > t->len - tqspi->cur_pos)
	340	+ len = t->len - tqspi->cur_pos;
	341	+ read_bytes = len;
	342	+ for (count = 0; count < rx_full_count; count++) {
	343	+ x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO) & rx_mask;
	344	+
	345	+ for (i = 0; len && (i < bytes_per_word); i++, len--)
	346	+ rx_buf++ = (x >> (i 8)) & 0xff;
	347	+ }
	348	+
	349	+ read_words += rx_full_count;
	350	+ tqspi->cur_rx_pos += read_bytes;
	351	+ }
	352	+
	353	+ return read_words;
	354	+}
	355	+
	356	+static void
	357	+tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi tqspi, struct spi_transfer t)
	358	+{
	359	+ dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys,
	360	+ tqspi->dma_buf_size, DMA_TO_DEVICE);
	361	+
	362	+ /*
	363	+ * In packed mode, each word in FIFO may contain multiple packets
	364	+ * based on bits per word. So all bytes in each FIFO word are valid.
	365	+ *
	366	+ * In unpacked mode, each word in FIFO contains single packet and
	367	+ * based on bits per word any remaining bits in FIFO word will be
	368	+ * ignored by the hardware and are invalid bits.
	369	+ */
	370	+ if (tqspi->is_packed) {
	371	+ tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
	372	+ } else {
	373	+ u8 tx_buf = (u8 )t->tx_buf + tqspi->cur_tx_pos;
	374	+ unsigned int i, count, consume, write_bytes;
	375	+
	376	+ /*
	377	+ * Fill tx_dma_buf to contain single packet in each word based
	378	+ * on bits per word from SPI core tx_buf.
	379	+ */
	380	+ consume = tqspi->curr_dma_words * tqspi->bytes_per_word;
	381	+ if (consume > t->len - tqspi->cur_pos)
	382	+ consume = t->len - tqspi->cur_pos;
	383	+ write_bytes = consume;
	384	+ for (count = 0; count < tqspi->curr_dma_words; count++) {
	385	+ u32 x = 0;
	386	+
	387	+ for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--)
	388	+ x \|= (u32)(tx_buf++) << (i 8);
	389	+ tqspi->tx_dma_buf[count] = x;
	390	+ }
	391	+
	392	+ tqspi->cur_tx_pos += write_bytes;
	393	+ }
	394	+
	395	+ dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys,
	396	+ tqspi->dma_buf_size, DMA_TO_DEVICE);
	397	+}
	398	+
	399	+static void
	400	+tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi tqspi, struct spi_transfer t)
	401	+{
	402	+ dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys,
	403	+ tqspi->dma_buf_size, DMA_FROM_DEVICE);
	404	+
	405	+ if (tqspi->is_packed) {
	406	+ tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
	407	+ } else {
	408	+ unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos;
	409	+ u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
	410	+ unsigned int i, count, consume, read_bytes;
	411	+
	412	+ /*
	413	+ * Each FIFO word contains single data packet.
	414	+ * Skip invalid bits in each FIFO word based on bits per word
	415	+ * and align bytes while filling in SPI core rx_buf.
	416	+ */
	417	+ consume = tqspi->curr_dma_words * tqspi->bytes_per_word;
	418	+ if (consume > t->len - tqspi->cur_pos)
	419	+ consume = t->len - tqspi->cur_pos;
	420	+ read_bytes = consume;
	421	+ for (count = 0; count < tqspi->curr_dma_words; count++) {
	422	+ u32 x = tqspi->rx_dma_buf[count] & rx_mask;
	423	+
	424	+ for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--)
	425	+ rx_buf++ = (x >> (i 8)) & 0xff;
	426	+ }
	427	+
	428	+ tqspi->cur_rx_pos += read_bytes;
	429	+ }
	430	+
	431	+ dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys,
	432	+ tqspi->dma_buf_size, DMA_FROM_DEVICE);
	433	+}
	434	+
	435	+static void tegra_qspi_dma_complete(void *args)
	436	+{
	437	+ struct completion *dma_complete = args;
	438	+
	439	+ complete(dma_complete);
	440	+}
	441	+
	442	+static int tegra_qspi_start_tx_dma(struct tegra_qspi tqspi, struct spi_transfer t, int len)
	443	+{
	444	+ dma_addr_t tx_dma_phys;
	445	+
	446	+ reinit_completion(&tqspi->tx_dma_complete);
	447	+
	448	+ if (tqspi->is_packed)
	449	+ tx_dma_phys = t->tx_dma;
	450	+ else
	451	+ tx_dma_phys = tqspi->tx_dma_phys;
	452	+
	453	+ tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys,
	454	+ len, DMA_MEM_TO_DEV,
	455	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	456	+
	457	+ if (!tqspi->tx_dma_desc) {
	458	+ dev_err(tqspi->dev, "Unable to get TX descriptor\n");
	459	+ return -EIO;
	460	+ }
	461	+
	462	+ tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete;
	463	+ tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete;
	464	+ dmaengine_submit(tqspi->tx_dma_desc);
	465	+ dma_async_issue_pending(tqspi->tx_dma_chan);
	466	+
	467	+ return 0;
	468	+}
	469	+
	470	+static int tegra_qspi_start_rx_dma(struct tegra_qspi tqspi, struct spi_transfer t, int len)
	471	+{
	472	+ dma_addr_t rx_dma_phys;
	473	+
	474	+ reinit_completion(&tqspi->rx_dma_complete);
	475	+
	476	+ if (tqspi->is_packed)
	477	+ rx_dma_phys = t->rx_dma;
	478	+ else
	479	+ rx_dma_phys = tqspi->rx_dma_phys;
	480	+
	481	+ tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys,
	482	+ len, DMA_DEV_TO_MEM,
	483	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	484	+
	485	+ if (!tqspi->rx_dma_desc) {
	486	+ dev_err(tqspi->dev, "Unable to get RX descriptor\n");
	487	+ return -EIO;
	488	+ }
	489	+
	490	+ tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete;
	491	+ tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete;
	492	+ dmaengine_submit(tqspi->rx_dma_desc);
	493	+ dma_async_issue_pending(tqspi->rx_dma_chan);
	494	+
	495	+ return 0;
	496	+}
	497	+
	498	+static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic)
	499	+{
	500	+ void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS;
	501	+ u32 val;
	502	+
	503	+ val = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
	504	+ if ((val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY)
	505	+ return 0;
	506	+
	507	+ val \|= QSPI_RX_FIFO_FLUSH \| QSPI_TX_FIFO_FLUSH;
	508	+ tegra_qspi_writel(tqspi, val, QSPI_FIFO_STATUS);
	509	+
	510	+ if (!atomic)
	511	+ return readl_relaxed_poll_timeout(addr, val,
	512	+ (val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY,
	513	+ 1000, 1000000);
	514	+
	515	+ return readl_relaxed_poll_timeout_atomic(addr, val,
	516	+ (val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY,
	517	+ 1000, 1000000);
	518	+}
	519	+
	520	+static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi)
	521	+{
	522	+ u32 intr_mask;
	523	+
	524	+ intr_mask = tegra_qspi_readl(tqspi, QSPI_INTR_MASK);
	525	+ intr_mask &= ~(QSPI_INTR_RDY_MASK \| QSPI_INTR_RX_TX_FIFO_ERR);
	526	+ tegra_qspi_writel(tqspi, intr_mask, QSPI_INTR_MASK);
	527	+}
	528	+
	529	+static int tegra_qspi_dma_map_xfer(struct tegra_qspi tqspi, struct spi_transfer t)
	530	+{
	531	+ u8 tx_buf = (u8 )t->tx_buf + tqspi->cur_tx_pos;
	532	+ u8 rx_buf = (u8 )t->rx_buf + tqspi->cur_rx_pos;
	533	+ unsigned int len;
	534	+
	535	+ len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
	536	+
	537	+ if (t->tx_buf) {
	538	+ t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE);
	539	+ if (dma_mapping_error(tqspi->dev, t->tx_dma))
	540	+ return -ENOMEM;
	541	+ }
	542	+
	543	+ if (t->rx_buf) {
	544	+ t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE);
	545	+ if (dma_mapping_error(tqspi->dev, t->rx_dma)) {
	546	+ dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
	547	+ return -ENOMEM;
	548	+ }
	549	+ }
	550	+
	551	+ return 0;
	552	+}
	553	+
	554	+static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi tqspi, struct spi_transfer t)
	555	+{
	556	+ unsigned int len;
	557	+
	558	+ len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
	559	+
	560	+ dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
	561	+ dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE);
	562	+}
	563	+
	564	+static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi tqspi, struct spi_transfer t)
	565	+{
	566	+ struct dma_slave_config dma_sconfig = { 0 };
	567	+ unsigned int len;
	568	+ u8 dma_burst;
	569	+ int ret = 0;
	570	+ u32 val;
	571	+
	572	+ if (tqspi->is_packed) {
	573	+ ret = tegra_qspi_dma_map_xfer(tqspi, t);
	574	+ if (ret < 0)
	575	+ return ret;
	576	+ }
	577	+
	578	+ val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1);
	579	+ tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK);
	580	+
	581	+ tegra_qspi_unmask_irq(tqspi);
	582	+
	583	+ if (tqspi->is_packed)
	584	+ len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
	585	+ else
	586	+ len = tqspi->curr_dma_words * 4;
	587	+
	588	+ /* set attention level based on length of transfer */
	589	+ val = 0;
	590	+ if (len & 0xf) {
	591	+ val \|= QSPI_TX_TRIG_1 \| QSPI_RX_TRIG_1;
	592	+ dma_burst = 1;
	593	+ } else if (((len) >> 4) & 0x1) {
	594	+ val \|= QSPI_TX_TRIG_4 \| QSPI_RX_TRIG_4;
	595	+ dma_burst = 4;
	596	+ } else {
	597	+ val \|= QSPI_TX_TRIG_8 \| QSPI_RX_TRIG_8;
	598	+ dma_burst = 8;
	599	+ }
	600	+
	601	+ tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
	602	+ tqspi->dma_control_reg = val;
	603	+
	604	+ dma_sconfig.device_fc = true;
	605	+ if (tqspi->cur_direction & DATA_DIR_TX) {
	606	+ dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO;
	607	+ dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	608	+ dma_sconfig.dst_maxburst = dma_burst;
	609	+ ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig);
	610	+ if (ret < 0) {
	611	+ dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
	612	+ return ret;
	613	+ }
	614	+
	615	+ tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t);
	616	+ ret = tegra_qspi_start_tx_dma(tqspi, t, len);
	617	+ if (ret < 0) {
	618	+ dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret);
	619	+ return ret;
	620	+ }
	621	+ }
	622	+
	623	+ if (tqspi->cur_direction & DATA_DIR_RX) {
	624	+ dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO;
	625	+ dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	626	+ dma_sconfig.src_maxburst = dma_burst;
	627	+ ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig);
	628	+ if (ret < 0) {
	629	+ dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
	630	+ return ret;
	631	+ }
	632	+
	633	+ dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys,
	634	+ tqspi->dma_buf_size,
	635	+ DMA_FROM_DEVICE);
	636	+
	637	+ ret = tegra_qspi_start_rx_dma(tqspi, t, len);
	638	+ if (ret < 0) {
	639	+ dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret);
	640	+ if (tqspi->cur_direction & DATA_DIR_TX)
	641	+ dmaengine_terminate_all(tqspi->tx_dma_chan);
	642	+ return ret;
	643	+ }
	644	+ }
	645	+
	646	+ tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
	647	+
	648	+ tqspi->is_curr_dma_xfer = true;
	649	+ tqspi->dma_control_reg = val;
	650	+ val \|= QSPI_DMA_EN;
	651	+ tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
	652	+
	653	+ return ret;
	654	+}
	655	+
	656	+static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi qspi, struct spi_transfer t)
	657	+{
	658	+ u32 val;
	659	+ unsigned int cur_words;
	660	+
	661	+ if (qspi->cur_direction & DATA_DIR_TX)
	662	+ cur_words = tegra_qspi_fill_tx_fifo_from_client_txbuf(qspi, t);
	663	+ else
	664	+ cur_words = qspi->curr_dma_words;
	665	+
	666	+ val = QSPI_DMA_BLK_SET(cur_words - 1);
	667	+ tegra_qspi_writel(qspi, val, QSPI_DMA_BLK);
	668	+
	669	+ tegra_qspi_unmask_irq(qspi);
	670	+
	671	+ qspi->is_curr_dma_xfer = false;
	672	+ val = qspi->command1_reg;
	673	+ val \|= QSPI_PIO;
	674	+ tegra_qspi_writel(qspi, val, QSPI_COMMAND1);
	675	+
	676	+ return 0;
	677	+}
	678	+
	679	+static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
	680	+{
	681	+ if (tqspi->tx_dma_buf) {
	682	+ dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
	683	+ tqspi->tx_dma_buf, tqspi->tx_dma_phys);
	684	+ tqspi->tx_dma_buf = NULL;
	685	+ }
	686	+
	687	+ if (tqspi->tx_dma_chan) {
	688	+ dma_release_channel(tqspi->tx_dma_chan);
	689	+ tqspi->tx_dma_chan = NULL;
	690	+ }
	691	+
	692	+ if (tqspi->rx_dma_buf) {
	693	+ dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
	694	+ tqspi->rx_dma_buf, tqspi->rx_dma_phys);
	695	+ tqspi->rx_dma_buf = NULL;
	696	+ }
	697	+
	698	+ if (tqspi->rx_dma_chan) {
	699	+ dma_release_channel(tqspi->rx_dma_chan);
	700	+ tqspi->rx_dma_chan = NULL;
	701	+ }
	702	+}
	703	+
	704	+static int tegra_qspi_init_dma(struct tegra_qspi *tqspi)
	705	+{
	706	+ struct dma_chan *dma_chan;
	707	+ dma_addr_t dma_phys;
	708	+ u32 *dma_buf;
	709	+ int err;
	710	+
	711	+ dma_chan = dma_request_chan(tqspi->dev, "rx");
	712	+ if (IS_ERR(dma_chan)) {
	713	+ err = PTR_ERR(dma_chan);
	714	+ goto err_out;
	715	+ }
	716	+
	717	+ tqspi->rx_dma_chan = dma_chan;
	718	+
	719	+ dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
	720	+ if (!dma_buf) {
	721	+ err = -ENOMEM;
	722	+ goto err_out;
	723	+ }
	724	+
	725	+ tqspi->rx_dma_buf = dma_buf;
	726	+ tqspi->rx_dma_phys = dma_phys;
	727	+
	728	+ dma_chan = dma_request_chan(tqspi->dev, "tx");
	729	+ if (IS_ERR(dma_chan)) {
	730	+ err = PTR_ERR(dma_chan);
	731	+ goto err_out;
	732	+ }
	733	+
	734	+ tqspi->tx_dma_chan = dma_chan;
	735	+
	736	+ dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
	737	+ if (!dma_buf) {
	738	+ err = -ENOMEM;
	739	+ goto err_out;
	740	+ }
	741	+
	742	+ tqspi->tx_dma_buf = dma_buf;
	743	+ tqspi->tx_dma_phys = dma_phys;
	744	+ tqspi->use_dma = true;
	745	+
	746	+ return 0;
	747	+
	748	+err_out:
	749	+ tegra_qspi_deinit_dma(tqspi);
	750	+
	751	+ if (err != -EPROBE_DEFER) {
	752	+ dev_err(tqspi->dev, "cannot use DMA: %d\n", err);
	753	+ dev_err(tqspi->dev, "falling back to PIO\n");
	754	+ return 0;
	755	+ }
	756	+
	757	+ return err;
	758	+}
	759	+
	760	+static u32 tegra_qspi_setup_transfer_one(struct spi_device spi, struct spi_transfer t,
	761	+ bool is_first_of_msg)
	762	+{
	763	+ struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
	764	+ struct tegra_qspi_client_data *cdata = spi->controller_data;
	765	+ u32 command1, command2, speed = t->speed_hz;
	766	+ u8 bits_per_word = t->bits_per_word;
	767	+ u32 tx_tap = 0, rx_tap = 0;
	768	+ int req_mode;
	769	+
	770	+ if (speed != tqspi->cur_speed) {
	771	+ clk_set_rate(tqspi->clk, speed);
	772	+ tqspi->cur_speed = speed;
	773	+ }
	774	+
	775	+ tqspi->cur_pos = 0;
	776	+ tqspi->cur_rx_pos = 0;
	777	+ tqspi->cur_tx_pos = 0;
	778	+ tqspi->curr_xfer = t;
	779	+
	780	+ if (is_first_of_msg) {
	781	+ tegra_qspi_mask_clear_irq(tqspi);
	782	+
	783	+ command1 = tqspi->def_command1_reg;
	784	+ command1 \|= QSPI_BIT_LENGTH(bits_per_word - 1);
	785	+
	786	+ command1 &= ~QSPI_CONTROL_MODE_MASK;
	787	+ req_mode = spi->mode & 0x3;
	788	+ if (req_mode == SPI_MODE_3)
	789	+ command1 \|= QSPI_CONTROL_MODE_3;
	790	+ else
	791	+ command1 \|= QSPI_CONTROL_MODE_0;
	792	+
	793	+ if (spi->mode & SPI_CS_HIGH)
	794	+ command1 \|= QSPI_CS_SW_VAL;
	795	+ else
	796	+ command1 &= ~QSPI_CS_SW_VAL;
	797	+ tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
	798	+
	799	+ if (cdata && cdata->tx_clk_tap_delay)
	800	+ tx_tap = cdata->tx_clk_tap_delay;
	801	+
	802	+ if (cdata && cdata->rx_clk_tap_delay)
	803	+ rx_tap = cdata->rx_clk_tap_delay;
	804	+
	805	+ command2 = QSPI_TX_TAP_DELAY(tx_tap) \| QSPI_RX_TAP_DELAY(rx_tap);
	806	+ if (command2 != tqspi->def_command2_reg)
	807	+ tegra_qspi_writel(tqspi, command2, QSPI_COMMAND2);
	808	+
	809	+ } else {
	810	+ command1 = tqspi->command1_reg;
	811	+ command1 &= ~QSPI_BIT_LENGTH(~0);
	812	+ command1 \|= QSPI_BIT_LENGTH(bits_per_word - 1);
	813	+ }
	814	+
	815	+ command1 &= ~QSPI_SDR_DDR_SEL;
	816	+
	817	+ return command1;
	818	+}
	819	+
	820	+static int tegra_qspi_start_transfer_one(struct spi_device *spi,
	821	+ struct spi_transfer *t, u32 command1)
	822	+{
	823	+ struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
	824	+ unsigned int total_fifo_words;
	825	+ u8 bus_width = 0;
	826	+ int ret;
	827	+
	828	+ total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t);
	829	+
	830	+ command1 &= ~QSPI_PACKED;
	831	+ if (tqspi->is_packed)
	832	+ command1 \|= QSPI_PACKED;
	833	+ tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
	834	+
	835	+ tqspi->cur_direction = 0;
	836	+
	837	+ command1 &= ~(QSPI_TX_EN \| QSPI_RX_EN);
	838	+ if (t->rx_buf) {
	839	+ command1 \|= QSPI_RX_EN;
	840	+ tqspi->cur_direction \|= DATA_DIR_RX;
	841	+ bus_width = t->rx_nbits;
	842	+ }
	843	+
	844	+ if (t->tx_buf) {
	845	+ command1 \|= QSPI_TX_EN;
	846	+ tqspi->cur_direction \|= DATA_DIR_TX;
	847	+ bus_width = t->tx_nbits;
	848	+ }
	849	+
	850	+ command1 &= ~QSPI_INTERFACE_WIDTH_MASK;
	851	+
	852	+ if (bus_width == SPI_NBITS_QUAD)
	853	+ command1 \|= QSPI_INTERFACE_WIDTH_QUAD;
	854	+ else if (bus_width == SPI_NBITS_DUAL)
	855	+ command1 \|= QSPI_INTERFACE_WIDTH_DUAL;
	856	+ else
	857	+ command1 \|= QSPI_INTERFACE_WIDTH_SINGLE;
	858	+
	859	+ tqspi->command1_reg = command1;
	860	+
	861	+ tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG);
	862	+
	863	+ ret = tegra_qspi_flush_fifos(tqspi, false);
	864	+ if (ret < 0)
	865	+ return ret;
	866	+
	867	+ if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH)
	868	+ ret = tegra_qspi_start_dma_based_transfer(tqspi, t);
	869	+ else
	870	+ ret = tegra_qspi_start_cpu_based_transfer(tqspi, t);
	871	+
	872	+ return ret;
	873	+}
	874	+
	875	+static struct tegra_qspi_client_data tegra_qspi_parse_cdata_dt(struct spi_device spi)
	876	+{
	877	+ struct tegra_qspi_client_data *cdata;
	878	+ struct device_node *slave_np = spi->dev.of_node;
	879	+
	880	+ cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
	881	+ if (!cdata)
	882	+ return NULL;
	883	+
	884	+ of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
	885	+ &cdata->tx_clk_tap_delay);
	886	+ of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
	887	+ &cdata->rx_clk_tap_delay);
	888	+ return cdata;
	889	+}
	890	+
	891	+static void tegra_qspi_cleanup(struct spi_device *spi)
	892	+{
	893	+ struct tegra_qspi_client_data *cdata = spi->controller_data;
	894	+
	895	+ spi->controller_data = NULL;
	896	+ kfree(cdata);
	897	+}
	898	+
	899	+static int tegra_qspi_setup(struct spi_device *spi)
	900	+{
	901	+ struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
	902	+ struct tegra_qspi_client_data *cdata = spi->controller_data;
	903	+ unsigned long flags;
	904	+ u32 val;
	905	+ int ret;
	906	+
	907	+ ret = pm_runtime_resume_and_get(tqspi->dev);
	908	+ if (ret < 0) {
	909	+ dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret);
	910	+ return ret;
	911	+ }
	912	+
	913	+ if (!cdata) {
	914	+ cdata = tegra_qspi_parse_cdata_dt(spi);
	915	+ spi->controller_data = cdata;
	916	+ }
	917	+
	918	+ spin_lock_irqsave(&tqspi->lock, flags);
	919	+
	920	+ /* keep default cs state to inactive */
	921	+ val = tqspi->def_command1_reg;
	922	+ if (spi->mode & SPI_CS_HIGH)
	923	+ val &= ~QSPI_CS_SW_VAL;
	924	+ else
	925	+ val \|= QSPI_CS_SW_VAL;
	926	+
	927	+ tqspi->def_command1_reg = val;
	928	+ tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
	929	+
	930	+ spin_unlock_irqrestore(&tqspi->lock, flags);
	931	+
	932	+ pm_runtime_put(tqspi->dev);
	933	+
	934	+ return 0;
	935	+}
	936	+
	937	+static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi)
	938	+{
	939	+ dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n");
	940	+ dev_dbg(tqspi->dev, "Command1: 0x%08x \| Command2: 0x%08x\n",
	941	+ tegra_qspi_readl(tqspi, QSPI_COMMAND1),
	942	+ tegra_qspi_readl(tqspi, QSPI_COMMAND2));
	943	+ dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x \| DMA_BLK: 0x%08x\n",
	944	+ tegra_qspi_readl(tqspi, QSPI_DMA_CTL),
	945	+ tegra_qspi_readl(tqspi, QSPI_DMA_BLK));
	946	+ dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x \| MISC: 0x%08x\n",
	947	+ tegra_qspi_readl(tqspi, QSPI_INTR_MASK),
	948	+ tegra_qspi_readl(tqspi, QSPI_MISC_REG));
	949	+ dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x \| FIFO_STATUS: 0x%08x\n",
	950	+ tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS),
	951	+ tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS));
	952	+}
	953	+
	954	+static void tegra_qspi_handle_error(struct tegra_qspi *tqspi)
	955	+{
	956	+ dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg);
	957	+ tegra_qspi_dump_regs(tqspi);
	958	+ tegra_qspi_flush_fifos(tqspi, true);
	959	+ reset_control_assert(tqspi->rst);
	960	+ udelay(2);
	961	+ reset_control_deassert(tqspi->rst);
	962	+}
	963	+
	964	+static void tegra_qspi_transfer_end(struct spi_device *spi)
	965	+{
	966	+ struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
	967	+ int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
	968	+
	969	+ if (cs_val)
	970	+ tqspi->command1_reg \|= QSPI_CS_SW_VAL;
	971	+ else
	972	+ tqspi->command1_reg &= ~QSPI_CS_SW_VAL;
	973	+ tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
	974	+ tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
	975	+}
	976	+
	977	+static int tegra_qspi_transfer_one_message(struct spi_master master, struct spi_message msg)
	978	+{
	979	+ struct tegra_qspi *tqspi = spi_master_get_devdata(master);
	980	+ struct spi_device *spi = msg->spi;
	981	+ struct spi_transfer *transfer;
	982	+ bool is_first_msg = true;
	983	+ int ret;
	984	+
	985	+ msg->status = 0;
	986	+ msg->actual_length = 0;
	987	+ tqspi->tx_status = 0;
	988	+ tqspi->rx_status = 0;
	989	+
	990	+ list_for_each_entry(transfer, &msg->transfers, transfer_list) {
	991	+ struct spi_transfer *xfer = transfer;
	992	+ u8 dummy_bytes = 0;
	993	+ u32 cmd1;
	994	+
	995	+ tqspi->dummy_cycles = 0;
	996	+ /*
	997	+ * Tegra QSPI hardware supports dummy bytes transfer after actual transfer
	998	+ * bytes based on programmed dummy clock cycles in the QSPI_MISC register.
	999	+ * So, check if the next transfer is dummy data transfer and program dummy
	1000	+ * clock cycles along with the current transfer and skip next transfer.
	1001	+ */
	1002	+ if (!list_is_last(&xfer->transfer_list, &msg->transfers)) {
	1003	+ struct spi_transfer *next_xfer;
	1004	+
	1005	+ next_xfer = list_next_entry(xfer, transfer_list);
	1006	+ if (next_xfer->dummy_data) {
	1007	+ u32 dummy_cycles = next_xfer->len * 8 / next_xfer->tx_nbits;
	1008	+
	1009	+ if (dummy_cycles <= QSPI_DUMMY_CYCLES_MAX) {
	1010	+ tqspi->dummy_cycles = dummy_cycles;
	1011	+ dummy_bytes = next_xfer->len;
	1012	+ transfer = next_xfer;
	1013	+ }
	1014	+ }
	1015	+ }
	1016	+
	1017	+ reinit_completion(&tqspi->xfer_completion);
	1018	+
	1019	+ cmd1 = tegra_qspi_setup_transfer_one(spi, xfer, is_first_msg);
	1020	+
	1021	+ ret = tegra_qspi_start_transfer_one(spi, xfer, cmd1);
	1022	+ if (ret < 0) {
	1023	+ dev_err(tqspi->dev, "failed to start transfer: %d\n", ret);
	1024	+ goto complete_xfer;
	1025	+ }
	1026	+
	1027	+ is_first_msg = false;
	1028	+ ret = wait_for_completion_timeout(&tqspi->xfer_completion,
	1029	+ QSPI_DMA_TIMEOUT);
	1030	+ if (WARN_ON(ret == 0)) {
	1031	+ dev_err(tqspi->dev, "transfer timeout: %d\n", ret);
	1032	+ if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX))
	1033	+ dmaengine_terminate_all(tqspi->tx_dma_chan);
	1034	+ if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX))
	1035	+ dmaengine_terminate_all(tqspi->rx_dma_chan);
	1036	+ tegra_qspi_handle_error(tqspi);
	1037	+ ret = -EIO;
	1038	+ goto complete_xfer;
	1039	+ }
	1040	+
	1041	+ if (tqspi->tx_status \|\| tqspi->rx_status) {
	1042	+ tegra_qspi_handle_error(tqspi);
	1043	+ ret = -EIO;
	1044	+ goto complete_xfer;
	1045	+ }
	1046	+
	1047	+ msg->actual_length += xfer->len + dummy_bytes;
	1048	+
	1049	+complete_xfer:
	1050	+ if (ret < 0) {
	1051	+ tegra_qspi_transfer_end(spi);
	1052	+ spi_transfer_delay_exec(xfer);
	1053	+ goto exit;
	1054	+ }
	1055	+
	1056	+ if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
	1057	+ /* de-activate CS after last transfer only when cs_change is not set */
	1058	+ if (!xfer->cs_change) {
	1059	+ tegra_qspi_transfer_end(spi);
	1060	+ spi_transfer_delay_exec(xfer);
	1061	+ }
	1062	+ } else if (xfer->cs_change) {
	1063	+ /* de-activated CS between the transfers only when cs_change is set */
	1064	+ tegra_qspi_transfer_end(spi);
	1065	+ spi_transfer_delay_exec(xfer);
	1066	+ }
	1067	+ }
	1068	+
	1069	+ ret = 0;
	1070	+exit:
	1071	+ msg->status = ret;
	1072	+ spi_finalize_current_message(master);
	1073	+ return ret;
	1074	+}
	1075	+
	1076	+static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi)
	1077	+{
	1078	+ struct spi_transfer *t = tqspi->curr_xfer;
	1079	+ unsigned long flags;
	1080	+
	1081	+ spin_lock_irqsave(&tqspi->lock, flags);
	1082	+
	1083	+ if (tqspi->tx_status \|\| tqspi->rx_status) {
	1084	+ tegra_qspi_handle_error(tqspi);
	1085	+ complete(&tqspi->xfer_completion);
	1086	+ goto exit;
	1087	+ }
	1088	+
	1089	+ if (tqspi->cur_direction & DATA_DIR_RX)
	1090	+ tegra_qspi_read_rx_fifo_to_client_rxbuf(tqspi, t);
	1091	+
	1092	+ if (tqspi->cur_direction & DATA_DIR_TX)
	1093	+ tqspi->cur_pos = tqspi->cur_tx_pos;
	1094	+ else
	1095	+ tqspi->cur_pos = tqspi->cur_rx_pos;
	1096	+
	1097	+ if (tqspi->cur_pos == t->len) {
	1098	+ complete(&tqspi->xfer_completion);
	1099	+ goto exit;
	1100	+ }
	1101	+
	1102	+ tegra_qspi_calculate_curr_xfer_param(tqspi, t);
	1103	+ tegra_qspi_start_cpu_based_transfer(tqspi, t);
	1104	+exit:
	1105	+ spin_unlock_irqrestore(&tqspi->lock, flags);
	1106	+ return IRQ_HANDLED;
	1107	+}
	1108	+
	1109	+static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi)
	1110	+{
	1111	+ struct spi_transfer *t = tqspi->curr_xfer;
	1112	+ unsigned int total_fifo_words;
	1113	+ unsigned long flags;
	1114	+ long wait_status;
	1115	+ int err = 0;
	1116	+
	1117	+ if (tqspi->cur_direction & DATA_DIR_TX) {
	1118	+ if (tqspi->tx_status) {
	1119	+ dmaengine_terminate_all(tqspi->tx_dma_chan);
	1120	+ err += 1;
	1121	+ } else {
	1122	+ wait_status = wait_for_completion_interruptible_timeout(
	1123	+ &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT);
	1124	+ if (wait_status <= 0) {
	1125	+ dmaengine_terminate_all(tqspi->tx_dma_chan);
	1126	+ dev_err(tqspi->dev, "failed TX DMA transfer\n");
	1127	+ err += 1;
	1128	+ }
	1129	+ }
	1130	+ }
	1131	+
	1132	+ if (tqspi->cur_direction & DATA_DIR_RX) {
	1133	+ if (tqspi->rx_status) {
	1134	+ dmaengine_terminate_all(tqspi->rx_dma_chan);
	1135	+ err += 2;
	1136	+ } else {
	1137	+ wait_status = wait_for_completion_interruptible_timeout(
	1138	+ &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT);
	1139	+ if (wait_status <= 0) {
	1140	+ dmaengine_terminate_all(tqspi->rx_dma_chan);
	1141	+ dev_err(tqspi->dev, "failed RX DMA transfer\n");
	1142	+ err += 2;
	1143	+ }
	1144	+ }
	1145	+ }
	1146	+
	1147	+ spin_lock_irqsave(&tqspi->lock, flags);
	1148	+
	1149	+ if (err) {
	1150	+ tegra_qspi_dma_unmap_xfer(tqspi, t);
	1151	+ tegra_qspi_handle_error(tqspi);
	1152	+ complete(&tqspi->xfer_completion);
	1153	+ goto exit;
	1154	+ }
	1155	+
	1156	+ if (tqspi->cur_direction & DATA_DIR_RX)
	1157	+ tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(tqspi, t);
	1158	+
	1159	+ if (tqspi->cur_direction & DATA_DIR_TX)
	1160	+ tqspi->cur_pos = tqspi->cur_tx_pos;
	1161	+ else
	1162	+ tqspi->cur_pos = tqspi->cur_rx_pos;
	1163	+
	1164	+ if (tqspi->cur_pos == t->len) {
	1165	+ tegra_qspi_dma_unmap_xfer(tqspi, t);
	1166	+ complete(&tqspi->xfer_completion);
	1167	+ goto exit;
	1168	+ }
	1169	+
	1170	+ tegra_qspi_dma_unmap_xfer(tqspi, t);
	1171	+
	1172	+ /* continue transfer in current message */
	1173	+ total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t);
	1174	+ if (total_fifo_words > QSPI_FIFO_DEPTH)
	1175	+ err = tegra_qspi_start_dma_based_transfer(tqspi, t);
	1176	+ else
	1177	+ err = tegra_qspi_start_cpu_based_transfer(tqspi, t);
	1178	+
	1179	+exit:
	1180	+ spin_unlock_irqrestore(&tqspi->lock, flags);
	1181	+ return IRQ_HANDLED;
	1182	+}
	1183	+
	1184	+static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
	1185	+{
	1186	+ struct tegra_qspi *tqspi = context_data;
	1187	+
	1188	+ tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
	1189	+
	1190	+ if (tqspi->cur_direction & DATA_DIR_TX)
	1191	+ tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF \| QSPI_TX_FIFO_OVF);
	1192	+
	1193	+ if (tqspi->cur_direction & DATA_DIR_RX)
	1194	+ tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF \| QSPI_RX_FIFO_UNF);
	1195	+
	1196	+ tegra_qspi_mask_clear_irq(tqspi);
	1197	+
	1198	+ if (!tqspi->is_curr_dma_xfer)
	1199	+ return handle_cpu_based_xfer(tqspi);
	1200	+
	1201	+ return handle_dma_based_xfer(tqspi);
	1202	+}
	1203	+
	1204	+static const struct of_device_id tegra_qspi_of_match[] = {
	1205	+ { .compatible = "nvidia,tegra210-qspi", },
	1206	+ { .compatible = "nvidia,tegra186-qspi", },
	1207	+ { .compatible = "nvidia,tegra194-qspi", },
	1208	+ {}
	1209	+};
	1210	+
	1211	+MODULE_DEVICE_TABLE(of, tegra_qspi_of_match);
	1212	+
	1213	+static int tegra_qspi_probe(struct platform_device *pdev)
	1214	+{
	1215	+ struct spi_master *master;
	1216	+ struct tegra_qspi *tqspi;
	1217	+ struct resource *r;
	1218	+ int ret, qspi_irq;
	1219	+ int bus_num;
	1220	+
	1221	+ master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi));
	1222	+ if (!master)
	1223	+ return -ENOMEM;
	1224	+
	1225	+ platform_set_drvdata(pdev, master);
	1226	+ tqspi = spi_master_get_devdata(master);
	1227	+
	1228	+ master->mode_bits = SPI_MODE_0 \| SPI_MODE_3 \| SPI_CS_HIGH \|
	1229	+ SPI_TX_DUAL \| SPI_RX_DUAL \| SPI_TX_QUAD \| SPI_RX_QUAD;
	1230	+ master->bits_per_word_mask = SPI_BPW_MASK(32) \| SPI_BPW_MASK(16) \| SPI_BPW_MASK(8);
	1231	+ master->setup = tegra_qspi_setup;
	1232	+ master->cleanup = tegra_qspi_cleanup;
	1233	+ master->transfer_one_message = tegra_qspi_transfer_one_message;
	1234	+ master->num_chipselect = 1;
	1235	+ master->auto_runtime_pm = true;
	1236	+
	1237	+ bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
	1238	+ if (bus_num >= 0)
	1239	+ master->bus_num = bus_num;
	1240	+
	1241	+ tqspi->master = master;
	1242	+ tqspi->dev = &pdev->dev;
	1243	+ spin_lock_init(&tqspi->lock);
	1244	+
	1245	+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	1246	+ tqspi->base = devm_ioremap_resource(&pdev->dev, r);
	1247	+ if (IS_ERR(tqspi->base))
	1248	+ return PTR_ERR(tqspi->base);
	1249	+
	1250	+ tqspi->phys = r->start;
	1251	+ qspi_irq = platform_get_irq(pdev, 0);
	1252	+ tqspi->irq = qspi_irq;
	1253	+
	1254	+ tqspi->clk = devm_clk_get(&pdev->dev, "qspi");
	1255	+ if (IS_ERR(tqspi->clk)) {
	1256	+ ret = PTR_ERR(tqspi->clk);
	1257	+ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
	1258	+ return ret;
	1259	+ }
	1260	+
	1261	+ tqspi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	1262	+ if (IS_ERR(tqspi->rst)) {
	1263	+ ret = PTR_ERR(tqspi->rst);
	1264	+ dev_err(&pdev->dev, "failed to get reset control: %d\n", ret);
	1265	+ return ret;
	1266	+ }
	1267	+
	1268	+ tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2;
	1269	+ tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN;
	1270	+
	1271	+ ret = tegra_qspi_init_dma(tqspi);
	1272	+ if (ret < 0)
	1273	+ return ret;
	1274	+
	1275	+ if (tqspi->use_dma)
	1276	+ tqspi->max_buf_size = tqspi->dma_buf_size;
	1277	+
	1278	+ init_completion(&tqspi->tx_dma_complete);
	1279	+ init_completion(&tqspi->rx_dma_complete);
	1280	+ init_completion(&tqspi->xfer_completion);
	1281	+
	1282	+ pm_runtime_enable(&pdev->dev);
	1283	+ ret = pm_runtime_resume_and_get(&pdev->dev);
	1284	+ if (ret < 0) {
	1285	+ dev_err(&pdev->dev, "failed to get runtime PM: %d\n", ret);
	1286	+ goto exit_pm_disable;
	1287	+ }
	1288	+
	1289	+ reset_control_assert(tqspi->rst);
	1290	+ udelay(2);
	1291	+ reset_control_deassert(tqspi->rst);
	1292	+
	1293	+ tqspi->def_command1_reg = QSPI_M_S \| QSPI_CS_SW_HW \| QSPI_CS_SW_VAL;
	1294	+ tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
	1295	+ tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1);
	1296	+ tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2);
	1297	+ tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2);
	1298	+
	1299	+ pm_runtime_put(&pdev->dev);
	1300	+
	1301	+ ret = request_threaded_irq(tqspi->irq, NULL,
	1302	+ tegra_qspi_isr_thread, IRQF_ONESHOT,
	1303	+ dev_name(&pdev->dev), tqspi);
	1304	+ if (ret < 0) {
	1305	+ dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret);
	1306	+ goto exit_pm_disable;
	1307	+ }
	1308	+
	1309	+ master->dev.of_node = pdev->dev.of_node;
	1310	+ ret = spi_register_master(master);
	1311	+ if (ret < 0) {
	1312	+ dev_err(&pdev->dev, "failed to register master: %d\n", ret);
	1313	+ goto exit_free_irq;
	1314	+ }
	1315	+
	1316	+ return 0;
	1317	+
	1318	+exit_free_irq:
	1319	+ free_irq(qspi_irq, tqspi);
	1320	+exit_pm_disable:
	1321	+ pm_runtime_disable(&pdev->dev);
	1322	+ tegra_qspi_deinit_dma(tqspi);
	1323	+ return ret;
	1324	+}
	1325	+
	1326	+static int tegra_qspi_remove(struct platform_device *pdev)
	1327	+{
	1328	+ struct spi_master *master = platform_get_drvdata(pdev);
	1329	+ struct tegra_qspi *tqspi = spi_master_get_devdata(master);
	1330	+
	1331	+ spi_unregister_master(master);
	1332	+ free_irq(tqspi->irq, tqspi);
	1333	+ pm_runtime_disable(&pdev->dev);
	1334	+ tegra_qspi_deinit_dma(tqspi);
	1335	+
	1336	+ return 0;
	1337	+}
	1338	+
	1339	+static int __maybe_unused tegra_qspi_suspend(struct device *dev)
	1340	+{
	1341	+ struct spi_master *master = dev_get_drvdata(dev);
	1342	+
	1343	+ return spi_master_suspend(master);
	1344	+}
	1345	+
	1346	+static int __maybe_unused tegra_qspi_resume(struct device *dev)
	1347	+{
	1348	+ struct spi_master *master = dev_get_drvdata(dev);
	1349	+ struct tegra_qspi *tqspi = spi_master_get_devdata(master);
	1350	+ int ret;
	1351	+
	1352	+ ret = pm_runtime_resume_and_get(dev);
	1353	+ if (ret < 0) {
	1354	+ dev_err(dev, "failed to get runtime PM: %d\n", ret);
	1355	+ return ret;
	1356	+ }
	1357	+
	1358	+ tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
	1359	+ tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2);
	1360	+ pm_runtime_put(dev);
	1361	+
	1362	+ return spi_master_resume(master);
	1363	+}
	1364	+
	1365	+static int __maybe_unused tegra_qspi_runtime_suspend(struct device *dev)
	1366	+{
	1367	+ struct spi_master *master = dev_get_drvdata(dev);
	1368	+ struct tegra_qspi *tqspi = spi_master_get_devdata(master);
	1369	+
	1370	+ /* flush all write which are in PPSB queue by reading back */
	1371	+ tegra_qspi_readl(tqspi, QSPI_COMMAND1);
	1372	+
	1373	+ clk_disable_unprepare(tqspi->clk);
	1374	+
	1375	+ return 0;
	1376	+}
	1377	+
	1378	+static int __maybe_unused tegra_qspi_runtime_resume(struct device *dev)
	1379	+{
	1380	+ struct spi_master *master = dev_get_drvdata(dev);
	1381	+ struct tegra_qspi *tqspi = spi_master_get_devdata(master);
	1382	+ int ret;
	1383	+
	1384	+ ret = clk_prepare_enable(tqspi->clk);
	1385	+ if (ret < 0)
	1386	+ dev_err(tqspi->dev, "failed to enable clock: %d\n", ret);
	1387	+
	1388	+ return ret;
	1389	+}
	1390	+
	1391	+static const struct dev_pm_ops tegra_qspi_pm_ops = {
	1392	+ SET_RUNTIME_PM_OPS(tegra_qspi_runtime_suspend, tegra_qspi_runtime_resume, NULL)
	1393	+ SET_SYSTEM_SLEEP_PM_OPS(tegra_qspi_suspend, tegra_qspi_resume)
	1394	+};
	1395	+
	1396	+static struct platform_driver tegra_qspi_driver = {
	1397	+ .driver = {
	1398	+ .name = "tegra-qspi",
	1399	+ .pm = &tegra_qspi_pm_ops,
	1400	+ .of_match_table = tegra_qspi_of_match,
	1401	+ },
	1402	+ .probe = tegra_qspi_probe,
	1403	+ .remove = tegra_qspi_remove,
	1404	+};
	1405	+module_platform_driver(tegra_qspi_driver);
	1406	+
	1407	+MODULE_ALIAS("platform:qspi-tegra");
	1408	+MODULE_DESCRIPTION("NVIDIA Tegra QSPI Controller Driver");
	1409	+MODULE_AUTHOR("Sowjanya Komatineni <skomatineni@nvidia.com>");
	1410	+MODULE_LICENSE("GPL v2");

drivers/spi/spi-txx9.c+0−477

@@ -1,477 +0,0 @@
1		−/*
2		− * TXx9 SPI controller driver.
3		− *
4		− * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
5		− * Copyright (C) 2000-2001 Toshiba Corporation
6		− *
7		− * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8		− * terms of the GNU General Public License version 2. This program is
9		− * licensed "as is" without any warranty of any kind, whether express
10		− * or implied.
11		− *
12		− * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13		− *
14		− * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
15		− */
16		−#include <linux/init.h>
17		−#include <linux/delay.h>
18		−#include <linux/errno.h>
19		−#include <linux/interrupt.h>
20		−#include <linux/platform_device.h>
21		−#include <linux/sched.h>
22		−#include <linux/spinlock.h>
23		−#include <linux/workqueue.h>
24		−#include <linux/spi/spi.h>
25		−#include <linux/err.h>
26		−#include <linux/clk.h>
27		−#include <linux/io.h>
28		−#include <linux/module.h>
29		−#include <linux/gpio/machine.h>
30		−#include <linux/gpio/consumer.h>
31		−
32		−
33		−#define SPI_FIFO_SIZE 4
34		−#define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
35		−#define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
36		−
37		−#define TXx9_SPMCR 0x00
38		−#define TXx9_SPCR0 0x04
39		−#define TXx9_SPCR1 0x08
40		−#define TXx9_SPFS 0x0c
41		−#define TXx9_SPSR 0x14
42		−#define TXx9_SPDR 0x18
43		−
44		−/* SPMCR : SPI Master Control */
45		−#define TXx9_SPMCR_OPMODE 0xc0
46		−#define TXx9_SPMCR_CONFIG 0x40
47		−#define TXx9_SPMCR_ACTIVE 0x80
48		−#define TXx9_SPMCR_SPSTP 0x02
49		−#define TXx9_SPMCR_BCLR 0x01
50		−
51		−/* SPCR0 : SPI Control 0 */
52		−#define TXx9_SPCR0_TXIFL_MASK 0xc000
53		−#define TXx9_SPCR0_RXIFL_MASK 0x3000
54		−#define TXx9_SPCR0_SIDIE 0x0800
55		−#define TXx9_SPCR0_SOEIE 0x0400
56		−#define TXx9_SPCR0_RBSIE 0x0200
57		−#define TXx9_SPCR0_TBSIE 0x0100
58		−#define TXx9_SPCR0_IFSPSE 0x0010
59		−#define TXx9_SPCR0_SBOS 0x0004
60		−#define TXx9_SPCR0_SPHA 0x0002
61		−#define TXx9_SPCR0_SPOL 0x0001
62		−
63		−/* SPSR : SPI Status */
64		−#define TXx9_SPSR_TBSI 0x8000
65		−#define TXx9_SPSR_RBSI 0x4000
66		−#define TXx9_SPSR_TBS_MASK 0x3800
67		−#define TXx9_SPSR_RBS_MASK 0x0700
68		−#define TXx9_SPSR_SPOE 0x0080
69		−#define TXx9_SPSR_IFSD 0x0008
70		−#define TXx9_SPSR_SIDLE 0x0004
71		−#define TXx9_SPSR_STRDY 0x0002
72		−#define TXx9_SPSR_SRRDY 0x0001
73		−
74		−
75		−struct txx9spi {
76		− struct work_struct work;
77		− spinlock_t lock; /* protect 'queue' */
78		− struct list_head queue;
79		− wait_queue_head_t waitq;
80		− void __iomem *membase;
81		− int baseclk;
82		− struct clk *clk;
83		− struct gpio_desc *last_chipselect;
84		− int last_chipselect_val;
85		−};
86		−
87		−static u32 txx9spi_rd(struct txx9spi *c, int reg)
88		−{
89		− return __raw_readl(c->membase + reg);
90		−}
91		−static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
92		−{
93		− __raw_writel(val, c->membase + reg);
94		−}
95		−
96		−static void txx9spi_cs_func(struct spi_device spi, struct txx9spi c,
97		− int on, unsigned int cs_delay)
98		−{
99		− /*
100		− * The GPIO descriptor will track polarity inversion inside
101		− * gpiolib.
102		− */
103		− if (on) {
104		− /* deselect the chip with cs_change hint in last transfer */
105		− if (c->last_chipselect)
106		− gpiod_set_value(c->last_chipselect,
107		− !c->last_chipselect_val);
108		− c->last_chipselect = spi->cs_gpiod;
109		− c->last_chipselect_val = on;
110		− } else {
111		− c->last_chipselect = NULL;
112		− ndelay(cs_delay); /* CS Hold Time */
113		− }
114		− gpiod_set_value(spi->cs_gpiod, on);
115		− ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
116		−}
117		−
118		−static int txx9spi_setup(struct spi_device *spi)
119		−{
120		− struct txx9spi *c = spi_master_get_devdata(spi->master);
121		−
122		− if (!spi->max_speed_hz)
123		− return -EINVAL;
124		−
125		− /* deselect chip */
126		− spin_lock(&c->lock);
127		− txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
128		− spin_unlock(&c->lock);
129		−
130		− return 0;
131		−}
132		−
133		−static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
134		−{
135		− struct txx9spi *c = dev_id;
136		−
137		− /* disable rx intr */
138		− txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
139		− TXx9_SPCR0);
140		− wake_up(&c->waitq);
141		− return IRQ_HANDLED;
142		−}
143		−
144		−static void txx9spi_work_one(struct txx9spi c, struct spi_message m)
145		−{
146		− struct spi_device *spi = m->spi;
147		− struct spi_transfer *t;
148		− unsigned int cs_delay;
149		− unsigned int cs_change = 1;
150		− int status = 0;
151		− u32 mcr;
152		− u32 prev_speed_hz = 0;
153		− u8 prev_bits_per_word = 0;
154		−
155		− /* CS setup/hold/recovery time in nsec */
156		− cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
157		−
158		− mcr = txx9spi_rd(c, TXx9_SPMCR);
159		− if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
160		− dev_err(&spi->dev, "Bad mode.\n");
161		− status = -EIO;
162		− goto exit;
163		− }
164		− mcr &= ~(TXx9_SPMCR_OPMODE \| TXx9_SPMCR_SPSTP \| TXx9_SPMCR_BCLR);
165		−
166		− /* enter config mode */
167		− txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
168		− txx9spi_wr(c, TXx9_SPCR0_SBOS
169		− \| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
170		− \| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
171		− \| 0x08,
172		− TXx9_SPCR0);
173		−
174		− list_for_each_entry(t, &m->transfers, transfer_list) {
175		− const void *txbuf = t->tx_buf;
176		− void *rxbuf = t->rx_buf;
177		− u32 data;
178		− unsigned int len = t->len;
179		− unsigned int wsize;
180		− u32 speed_hz = t->speed_hz;
181		− u8 bits_per_word = t->bits_per_word;
182		−
183		− wsize = bits_per_word >> 3; /* in bytes */
184		−
185		− if (prev_speed_hz != speed_hz
186		− \|\| prev_bits_per_word != bits_per_word) {
187		− int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
188		−
189		− n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
190		− /* enter config mode */
191		− txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR,
192		− TXx9_SPMCR);
193		− txx9spi_wr(c, (n << 8) \| bits_per_word, TXx9_SPCR1);
194		− /* enter active mode */
195		− txx9spi_wr(c, mcr \| TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
196		−
197		− prev_speed_hz = speed_hz;
198		− prev_bits_per_word = bits_per_word;
199		− }
200		−
201		− if (cs_change)
202		− txx9spi_cs_func(spi, c, 1, cs_delay);
203		− cs_change = t->cs_change;
204		− while (len) {
205		− unsigned int count = SPI_FIFO_SIZE;
206		− int i;
207		− u32 cr0;
208		−
209		− if (len < count * wsize)
210		− count = len / wsize;
211		− /* now tx must be idle... */
212		− while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
213		− cpu_relax();
214		− cr0 = txx9spi_rd(c, TXx9_SPCR0);
215		− cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
216		− cr0 \|= (count - 1) << 12;
217		− /* enable rx intr */
218		− cr0 \|= TXx9_SPCR0_RBSIE;
219		− txx9spi_wr(c, cr0, TXx9_SPCR0);
220		− /* send */
221		− for (i = 0; i < count; i++) {
222		− if (txbuf) {
223		− data = (wsize == 1)
224		− ? (const u8 )txbuf
225		− : (const u16 )txbuf;
226		− txx9spi_wr(c, data, TXx9_SPDR);
227		− txbuf += wsize;
228		− } else
229		− txx9spi_wr(c, 0, TXx9_SPDR);
230		− }
231		− /* wait all rx data */
232		− wait_event(c->waitq,
233		− txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
234		− /* receive */
235		− for (i = 0; i < count; i++) {
236		− data = txx9spi_rd(c, TXx9_SPDR);
237		− if (rxbuf) {
238		− if (wsize == 1)
239		− (u8 )rxbuf = data;
240		− else
241		− (u16 )rxbuf = data;
242		− rxbuf += wsize;
243		− }
244		− }
245		− len -= count * wsize;
246		− }
247		− m->actual_length += t->len;
248		− spi_transfer_delay_exec(t);
249		−
250		− if (!cs_change)
251		− continue;
252		− if (t->transfer_list.next == &m->transfers)
253		− break;
254		− /* sometimes a short mid-message deselect of the chip
255		− * may be needed to terminate a mode or command
256		− */
257		− txx9spi_cs_func(spi, c, 0, cs_delay);
258		− }
259		−
260		−exit:
261		− m->status = status;
262		− if (m->complete)
263		− m->complete(m->context);
264		−
265		− /* normally deactivate chipselect ... unless no error and
266		− * cs_change has hinted that the next message will probably
267		− * be for this chip too.
268		− */
269		− if (!(status == 0 && cs_change))
270		− txx9spi_cs_func(spi, c, 0, cs_delay);
271		−
272		− /* enter config mode */
273		− txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
274		−}
275		−
276		−static void txx9spi_work(struct work_struct *work)
277		−{
278		− struct txx9spi *c = container_of(work, struct txx9spi, work);
279		− unsigned long flags;
280		−
281		− spin_lock_irqsave(&c->lock, flags);
282		− while (!list_empty(&c->queue)) {
283		− struct spi_message *m;
284		−
285		− m = container_of(c->queue.next, struct spi_message, queue);
286		− list_del_init(&m->queue);
287		− spin_unlock_irqrestore(&c->lock, flags);
288		−
289		− txx9spi_work_one(c, m);
290		−
291		− spin_lock_irqsave(&c->lock, flags);
292		− }
293		− spin_unlock_irqrestore(&c->lock, flags);
294		−}
295		−
296		−static int txx9spi_transfer(struct spi_device spi, struct spi_message m)
297		−{
298		− struct spi_master *master = spi->master;
299		− struct txx9spi *c = spi_master_get_devdata(master);
300		− struct spi_transfer *t;
301		− unsigned long flags;
302		−
303		− m->actual_length = 0;
304		−
305		− /* check each transfer's parameters */
306		− list_for_each_entry(t, &m->transfers, transfer_list) {
307		− if (!t->tx_buf && !t->rx_buf && t->len)
308		− return -EINVAL;
309		− }
310		−
311		− spin_lock_irqsave(&c->lock, flags);
312		− list_add_tail(&m->queue, &c->queue);
313		− schedule_work(&c->work);
314		− spin_unlock_irqrestore(&c->lock, flags);
315		−
316		− return 0;
317		−}
318		−
319		−/*
320		− * Chip select uses GPIO only, further the driver is using the chip select
321		− * numer (from the device tree "reg" property, and this can only come from
322		− * device tree since this i MIPS and there is no way to pass platform data) as
323		− * the GPIO number. As the platform has only one GPIO controller (the txx9 GPIO
324		− * chip) it is thus using the chip select number as an offset into that chip.
325		− * This chip has a maximum of 16 GPIOs 0..15 and this is what all platforms
326		− * register.
327		− *
328		− * We modernized this behaviour by explicitly converting that offset to an
329		− * offset on the GPIO chip using a GPIO descriptor machine table of the same
330		− * size as the txx9 GPIO chip with a 1-to-1 mapping of chip select to GPIO
331		− * offset.
332		− *
333		− * This is admittedly a hack, but it is countering the hack of using "reg" to
334		− * contain a GPIO offset when it should be using "cs-gpios" as the SPI bindings
335		− * state.
336		− */
337		−static struct gpiod_lookup_table txx9spi_cs_gpio_table = {
338		− .dev_id = "spi0",
339		− .table = {
340		− GPIO_LOOKUP_IDX("TXx9", 0, "cs", 0, GPIO_ACTIVE_LOW),
341		− GPIO_LOOKUP_IDX("TXx9", 1, "cs", 1, GPIO_ACTIVE_LOW),
342		− GPIO_LOOKUP_IDX("TXx9", 2, "cs", 2, GPIO_ACTIVE_LOW),
343		− GPIO_LOOKUP_IDX("TXx9", 3, "cs", 3, GPIO_ACTIVE_LOW),
344		− GPIO_LOOKUP_IDX("TXx9", 4, "cs", 4, GPIO_ACTIVE_LOW),
345		− GPIO_LOOKUP_IDX("TXx9", 5, "cs", 5, GPIO_ACTIVE_LOW),
346		− GPIO_LOOKUP_IDX("TXx9", 6, "cs", 6, GPIO_ACTIVE_LOW),
347		− GPIO_LOOKUP_IDX("TXx9", 7, "cs", 7, GPIO_ACTIVE_LOW),
348		− GPIO_LOOKUP_IDX("TXx9", 8, "cs", 8, GPIO_ACTIVE_LOW),
349		− GPIO_LOOKUP_IDX("TXx9", 9, "cs", 9, GPIO_ACTIVE_LOW),
350		− GPIO_LOOKUP_IDX("TXx9", 10, "cs", 10, GPIO_ACTIVE_LOW),
351		− GPIO_LOOKUP_IDX("TXx9", 11, "cs", 11, GPIO_ACTIVE_LOW),
352		− GPIO_LOOKUP_IDX("TXx9", 12, "cs", 12, GPIO_ACTIVE_LOW),
353		− GPIO_LOOKUP_IDX("TXx9", 13, "cs", 13, GPIO_ACTIVE_LOW),
354		− GPIO_LOOKUP_IDX("TXx9", 14, "cs", 14, GPIO_ACTIVE_LOW),
355		− GPIO_LOOKUP_IDX("TXx9", 15, "cs", 15, GPIO_ACTIVE_LOW),
356		− { },
357		− },
358		−};
359		−
360		−static int txx9spi_probe(struct platform_device *dev)
361		−{
362		− struct spi_master *master;
363		− struct txx9spi *c;
364		− struct resource *res;
365		− int ret = -ENODEV;
366		− u32 mcr;
367		− int irq;
368		−
369		− master = spi_alloc_master(&dev->dev, sizeof(*c));
370		− if (!master)
371		− return ret;
372		− c = spi_master_get_devdata(master);
373		− platform_set_drvdata(dev, master);
374		−
375		− INIT_WORK(&c->work, txx9spi_work);
376		− spin_lock_init(&c->lock);
377		− INIT_LIST_HEAD(&c->queue);
378		− init_waitqueue_head(&c->waitq);
379		−
380		− c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
381		− if (IS_ERR(c->clk)) {
382		− ret = PTR_ERR(c->clk);
383		− c->clk = NULL;
384		− goto exit;
385		− }
386		− ret = clk_prepare_enable(c->clk);
387		− if (ret) {
388		− c->clk = NULL;
389		− goto exit;
390		− }
391		− c->baseclk = clk_get_rate(c->clk);
392		− master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
393		− master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
394		−
395		− res = platform_get_resource(dev, IORESOURCE_MEM, 0);
396		− c->membase = devm_ioremap_resource(&dev->dev, res);
397		− if (IS_ERR(c->membase))
398		− goto exit_busy;
399		−
400		− /* enter config mode */
401		− mcr = txx9spi_rd(c, TXx9_SPMCR);
402		− mcr &= ~(TXx9_SPMCR_OPMODE \| TXx9_SPMCR_SPSTP \| TXx9_SPMCR_BCLR);
403		− txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
404		−
405		− irq = platform_get_irq(dev, 0);
406		− if (irq < 0)
407		− goto exit_busy;
408		− ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
409		− "spi_txx9", c);
410		− if (ret)
411		− goto exit;
412		−
413		− c->last_chipselect = NULL;
414		−
415		− dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
416		− (unsigned long long)res->start, irq,
417		− (c->baseclk + 500000) / 1000000);
418		−
419		− gpiod_add_lookup_table(&txx9spi_cs_gpio_table);
420		−
421		− /* the spi->mode bits understood by this driver: */
422		− master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
423		−
424		− master->bus_num = dev->id;
425		− master->setup = txx9spi_setup;
426		− master->transfer = txx9spi_transfer;
427		− master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
428		− master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
429		− master->use_gpio_descriptors = true;
430		−
431		− ret = devm_spi_register_master(&dev->dev, master);
432		− if (ret)
433		− goto exit;
434		− return 0;
435		−exit_busy:
436		− ret = -EBUSY;
437		−exit:
438		− clk_disable_unprepare(c->clk);
439		− spi_master_put(master);
440		− return ret;
441		−}
442		−
443		−static int txx9spi_remove(struct platform_device *dev)
444		−{
445		− struct spi_master *master = platform_get_drvdata(dev);
446		− struct txx9spi *c = spi_master_get_devdata(master);
447		−
448		− flush_work(&c->work);
449		− clk_disable_unprepare(c->clk);
450		− return 0;
451		−}
452		−
453		−/* work with hotplug and coldplug */
454		−MODULE_ALIAS("platform:spi_txx9");
455		−
456		−static struct platform_driver txx9spi_driver = {
457		− .probe = txx9spi_probe,
458		− .remove = txx9spi_remove,
459		− .driver = {
460		− .name = "spi_txx9",
461		− },
462		−};
463		−
464		−static int __init txx9spi_init(void)
465		−{
466		− return platform_driver_register(&txx9spi_driver);
467		−}
468		−subsys_initcall(txx9spi_init);
469		−
470		−static void __exit txx9spi_exit(void)
471		−{
472		− platform_driver_unregister(&txx9spi_driver);
473		−}
474		−module_exit(txx9spi_exit);
475		−
476		−MODULE_DESCRIPTION("TXx9 SPI Driver");
477		−MODULE_LICENSE("GPL");

drivers/spi/spi.c+48−11

@@ -810,7 +810,8 @@ static void spi_set_cs(struct spi_device *spi, bool enable) · 809 unmodified lines
810	810	spi->controller->last_cs_enable = enable;
811	811	spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
812	812
813		− if (!spi->controller->set_cs_timing) {
	813	+ if (spi->cs_gpiod \|\| gpio_is_valid(spi->cs_gpio) \|\|
	814	+ !spi->controller->set_cs_timing) {
814	815	if (enable1)
815	816	spi_delay_exec(&spi->controller->cs_setup, NULL);
816	817	else
@@ -841,7 +842,8 @@ static void spi_set_cs(struct spi_device *spi, bool enable) · 24 unmodified lines
841	842	spi->controller->set_cs(spi, !enable);
842	843	}
843	844
844		− if (!spi->controller->set_cs_timing) {
	845	+ if (spi->cs_gpiod \|\| gpio_is_valid(spi->cs_gpio) \|\|
	846	+ !spi->controller->set_cs_timing) {
845	847	if (!enable1)
846	848	spi_delay_exec(&spi->controller->cs_inactive, NULL);
847	849	}
@@ -1267,7 +1269,7 @@ static int spi_transfer_one_message(struct spi_controller *ctlr, · 419 unmodified lines
1267	1269	ptp_read_system_prets(xfer->ptp_sts);
1268	1270	}
1269	1271
1270		− if (xfer->tx_buf \|\| xfer->rx_buf) {
	1272	+ if ((xfer->tx_buf \|\| xfer->rx_buf) && xfer->len) {
1271	1273	reinit_completion(&ctlr->xfer_completion);
1272	1274
1273	1275	fallback_pio:
@@ -1945,6 +1947,9 @@ static int of_spi_parse_dt(struct spi_controller ctlr, struct spi_device spi, · 671 unmodified lines
1945	1947	/* Device DUAL/QUAD mode */
1946	1948	if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) {
1947	1949	switch (value) {
	1950	+ case 0:
	1951	+ spi->mode \|= SPI_NO_TX;
	1952	+ break;
1948	1953	case 1:
1949	1954	break;
1950	1955	case 2:
@@ -1966,6 +1971,9 @@ static int of_spi_parse_dt(struct spi_controller ctlr, struct spi_device spi, · 15 unmodified lines
1966	1971
1967	1972	if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) {
1968	1973	switch (value) {
	1974	+ case 0:
	1975	+ spi->mode \|= SPI_NO_RX;
	1976	+ break;
1969	1977	case 1:
1970	1978	break;
1971	1979	case 2:
@@ -3333,12 +3341,16 @@ int spi_setup(struct spi_device *spi) · 1361 unmodified lines
3333	3341	unsigned bad_bits, ugly_bits;
3334	3342	int status;
3335	3343
3336		− /* check mode to prevent that DUAL and QUAD set at the same time
	3344	+ /*
	3345	+ * check mode to prevent that any two of DUAL, QUAD and NO_MOSI/MISO
	3346	+ * are set at the same time
3337	3347	*/
3338		− if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) \|\|
3339		− ((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) {
	3348	+ if ((hweight_long(spi->mode &
	3349	+ (SPI_TX_DUAL \| SPI_TX_QUAD \| SPI_NO_TX)) > 1) \|\|
	3350	+ (hweight_long(spi->mode &
	3351	+ (SPI_RX_DUAL \| SPI_RX_QUAD \| SPI_NO_RX)) > 1)) {
3340	3352	dev_err(&spi->dev,
3341		− "setup: can not select dual and quad at the same time\n");
	3353	+ "setup: can not select any two of dual, quad and no-rx/tx at the same time\n");
3342	3354	return -EINVAL;
3343	3355	}
3344	3356	/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
@@ -3352,7 +3364,8 @@ int spi_setup(struct spi_device *spi) · 7 unmodified lines
3352	3364	* SPI_CS_WORD has a fallback software implementation,
3353	3365	* so it is ignored here.
3354	3366	*/
3355		− bad_bits = spi->mode & ~(spi->controller->mode_bits \| SPI_CS_WORD);
	3367	+ bad_bits = spi->mode & ~(spi->controller->mode_bits \| SPI_CS_WORD \|
	3368	+ SPI_NO_TX \| SPI_NO_RX);
3356	3369	/* nothing prevents from working with active-high CS in case if it
3357	3370	* is driven by GPIO.
3358	3371	*/
@@ -3449,11 +3462,31 @@ EXPORT_SYMBOL_GPL(spi_setup); · 90 unmodified lines
3449	3462	int spi_set_cs_timing(struct spi_device spi, struct spi_delay setup,
3450	3463	struct spi_delay hold, struct spi_delay inactive)
3451	3464	{
	3465	+ struct device *parent = spi->controller->dev.parent;
3452	3466	size_t len;
	3467	+ int status;
	3468	+
	3469	+ if (spi->controller->set_cs_timing &&
	3470	+ !(spi->cs_gpiod \|\| gpio_is_valid(spi->cs_gpio))) {
	3471	+ if (spi->controller->auto_runtime_pm) {
	3472	+ status = pm_runtime_get_sync(parent);
	3473	+ if (status < 0) {
	3474	+ pm_runtime_put_noidle(parent);
	3475	+ dev_err(&spi->controller->dev, "Failed to power device: %d\n",
	3476	+ status);
	3477	+ return status;
	3478	+ }
3453	3479
3454		− if (spi->controller->set_cs_timing)
3455		− return spi->controller->set_cs_timing(spi, setup, hold,
3456		− inactive);
	3480	+ status = spi->controller->set_cs_timing(spi, setup,
	3481	+ hold, inactive);
	3482	+ pm_runtime_mark_last_busy(parent);
	3483	+ pm_runtime_put_autosuspend(parent);
	3484	+ return status;
	3485	+ } else {
	3486	+ return spi->controller->set_cs_timing(spi, setup, hold,
	3487	+ inactive);
	3488	+ }
	3489	+ }
3457	3490
3458	3491	if ((setup && setup->unit == SPI_DELAY_UNIT_SCK) \|\|
3459	3492	(hold && hold->unit == SPI_DELAY_UNIT_SCK) \|\|
@@ -3615,6 +3648,8 @@ static int __spi_validate(struct spi_device spi, struct spi_message message) · 155 unmodified lines
3615	3648	* 2. check tx/rx_nbits match the mode in spi_device
3616	3649	*/
3617	3650	if (xfer->tx_buf) {
	3651	+ if (spi->mode & SPI_NO_TX)
	3652	+ return -EINVAL;
3618	3653	if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
3619	3654	xfer->tx_nbits != SPI_NBITS_DUAL &&
3620	3655	xfer->tx_nbits != SPI_NBITS_QUAD)
@@ -3628,6 +3663,8 @@ static int __spi_validate(struct spi_device spi, struct spi_message message) · 7 unmodified lines
3628	3663	}
3629	3664	/* check transfer rx_nbits */
3630	3665	if (xfer->rx_buf) {
	3666	+ if (spi->mode & SPI_NO_RX)
	3667	+ return -EINVAL;
3631	3668	if (xfer->rx_nbits != SPI_NBITS_SINGLE &&
3632	3669	xfer->rx_nbits != SPI_NBITS_DUAL &&
3633	3670	xfer->rx_nbits != SPI_NBITS_QUAD)

include/linux/platform_data/efm32-spi.h+0−15

@@ -1,15 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0 */
2		−#ifndef __LINUX_PLATFORM_DATA_EFM32_SPI_H__
3		−#define __LINUX_PLATFORM_DATA_EFM32_SPI_H__
4		−
5		−#include <linux/types.h>
6		−
7		−/**
8		− * struct efm32_spi_pdata
9		− * @location: pinmux location for the I/O pins (to be written to the ROUTE
10		− * register)
11		− */
12		−struct efm32_spi_pdata {
13		− u8 location;
14		−};
15		−#endif /* ifndef __LINUX_PLATFORM_DATA_EFM32_SPI_H__ */

include/linux/spi/spi-mem.h+9−0

@@ -311,6 +311,9 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, · 310 unmodified lines
311	311	bool spi_mem_default_supports_op(struct spi_mem *mem,
312	312	const struct spi_mem_op *op);
313	313
	314	+bool spi_mem_dtr_supports_op(struct spi_mem *mem,
	315	+ const struct spi_mem_op *op);
	316	+
314	317	#else
315	318	static inline int
316	319	spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
@@ -334,6 +337,12 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, · 17 unmodified lines
334	337	return false;
335	338	}
336	339
	340	+static inline
	341	+bool spi_mem_dtr_supports_op(struct spi_mem *mem,
	342	+ const struct spi_mem_op *op)
	343	+{
	344	+ return false;
	345	+}
337	346	#endif /* CONFIG_SPI_MEM */
338	347
339	348	int spi_mem_adjust_op_size(struct spi_mem mem, struct spi_mem_op op);

include/linux/spi/spi.h+22−22

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	6	#ifndef __LINUX_SPI_H
7	7	#define __LINUX_SPI_H
8	8
	9	+#include <linux/bits.h>
9	10	#include <linux/device.h>
10	11	#include <linux/mod_devicetable.h>
11	12	#include <linux/slab.h>
@@ -15,6 +16,8 @@ · 3 unmodified lines
15	16	#include <linux/gpio/consumer.h>
16	17	#include <linux/ptp_clock_kernel.h>
17	18
	19	+#include <uapi/linux/spi/spi.h>
	20	+
18	21	struct dma_chan;
19	22	struct property_entry;
20	23	struct spi_controller;
@@ -164,28 +167,19 @@ struct spi_device { · 143 unmodified lines
164	167	u8 chip_select;
165	168	u8 bits_per_word;
166	169	bool rt;
	170	+#define SPI_NO_TX BIT(31) /* no transmit wire */
	171	+#define SPI_NO_RX BIT(30) /* no receive wire */
	172	+ /*
	173	+ * All bits defined above should be covered by SPI_MODE_KERNEL_MASK.
	174	+ * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart,
	175	+ * which is defined in 'include/uapi/linux/spi/spi.h'.
	176	+ * The bits defined here are from bit 31 downwards, while in
	177	+ * SPI_MODE_USER_MASK are from 0 upwards.
	178	+ * These bits must not overlap. A static assert check should make sure of that.
	179	+ * If adding extra bits, make sure to decrease the bit index below as well.
	180	+ */
	181	+#define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1))
167	182	u32 mode;
168		−#define SPI_CPHA 0x01 /* clock phase */
169		−#define SPI_CPOL 0x02 /* clock polarity */
170		−#define SPI_MODE_0 (0\|0) /* (original MicroWire) */
171		−#define SPI_MODE_1 (0\|SPI_CPHA)
172		−#define SPI_MODE_2 (SPI_CPOL\|0)
173		−#define SPI_MODE_3 (SPI_CPOL\|SPI_CPHA)
174		−#define SPI_MODE_X_MASK (SPI_CPOL\|SPI_CPHA)
175		−#define SPI_CS_HIGH 0x04 /* chipselect active high? */
176		−#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
177		−#define SPI_3WIRE 0x10 /* SI/SO signals shared */
178		−#define SPI_LOOP 0x20 /* loopback mode */
179		−#define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
180		−#define SPI_READY 0x80 /* slave pulls low to pause */
181		−#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
182		−#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
183		−#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
184		−#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
185		−#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
186		−#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
187		−#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
188		−#define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */
189	183	int irq;
190	184	void *controller_state;
191	185	void *controller_data;
@@ -208,6 +202,10 @@ struct spi_device { · 16 unmodified lines
208	202	*/
209	203	};
210	204
	205	+/* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */
	206	+static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0,
	207	+ "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap");
	208	+
211	209	static inline struct spi_device to_spi_device(struct device dev)
212	210	{
213	211	return dev ? container_of(dev, struct spi_device, dev) : NULL;
@@ -624,7 +622,7 @@ struct spi_controller { · 410 unmodified lines
624	622
625	623	/*
626	624	* These hooks are for drivers that use a generic implementation
627		− * of transfer_one_message() provied by the core.
	625	+ * of transfer_one_message() provided by the core.
628	626	*/
629	627	void (set_cs)(struct spi_device spi, bool enable);
630	628	int (transfer_one)(struct spi_controller ctlr, struct spi_device *spi,
@@ -827,6 +825,7 @@ extern void spi_res_release(struct spi_controller *ctlr, · 196 unmodified lines
827	825	* transfer. If 0 the default (from @spi_device) is used.
828	826	* @bits_per_word: select a bits_per_word other than the device default
829	827	* for this transfer. If 0 the default (from @spi_device) is used.
	828	+ * @dummy_data: indicates transfer is dummy bytes transfer.
830	829	* @cs_change: affects chipselect after this transfer completes
831	830	* @cs_change_delay: delay between cs deassert and assert when
832	831	* @cs_change is set and @spi_transfer is not the last in @spi_message
@@ -939,6 +938,7 @@ struct spi_transfer { · 106 unmodified lines
939	938	struct sg_table tx_sg;
940	939	struct sg_table rx_sg;
941	940
	941	+ unsigned dummy_data:1;
942	942	unsigned cs_change:1;
943	943	unsigned tx_nbits:3;
944	944	unsigned rx_nbits:3;

include/uapi/linux/spi/spi.h+41−0

@@ -0,0 +1,41 @@
	1	+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
	2	+#ifndef _UAPI_SPI_H
	3	+#define _UAPI_SPI_H
	4	+
	5	+#include <linux/const.h>
	6	+
	7	+#define SPI_CPHA _BITUL(0) /* clock phase */
	8	+#define SPI_CPOL _BITUL(1) /* clock polarity */
	9	+
	10	+#define SPI_MODE_0 (0\|0) /* (original MicroWire) */
	11	+#define SPI_MODE_1 (0\|SPI_CPHA)
	12	+#define SPI_MODE_2 (SPI_CPOL\|0)
	13	+#define SPI_MODE_3 (SPI_CPOL\|SPI_CPHA)
	14	+#define SPI_MODE_X_MASK (SPI_CPOL\|SPI_CPHA)
	15	+
	16	+#define SPI_CS_HIGH _BITUL(2) /* chipselect active high? */
	17	+#define SPI_LSB_FIRST _BITUL(3) /* per-word bits-on-wire */
	18	+#define SPI_3WIRE _BITUL(4) /* SI/SO signals shared */
	19	+#define SPI_LOOP _BITUL(5) /* loopback mode */
	20	+#define SPI_NO_CS _BITUL(6) /* 1 dev/bus, no chipselect */
	21	+#define SPI_READY _BITUL(7) /* slave pulls low to pause */
	22	+#define SPI_TX_DUAL _BITUL(8) /* transmit with 2 wires */
	23	+#define SPI_TX_QUAD _BITUL(9) /* transmit with 4 wires */
	24	+#define SPI_RX_DUAL _BITUL(10) /* receive with 2 wires */
	25	+#define SPI_RX_QUAD _BITUL(11) /* receive with 4 wires */
	26	+#define SPI_CS_WORD _BITUL(12) /* toggle cs after each word */
	27	+#define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */
	28	+#define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */
	29	+#define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */
	30	+
	31	+/*
	32	+ * All the bits defined above should be covered by SPI_MODE_USER_MASK.
	33	+ * The SPI_MODE_USER_MASK has the SPI_MODE_KERNEL_MASK counterpart in
	34	+ * 'include/linux/spi/spi.h'. The bits defined here are from bit 0 upwards
	35	+ * while in SPI_MODE_KERNEL_MASK they are from the other end downwards.
	36	+ * These bits must not overlap. A static assert check should make sure of that.
	37	+ * If adding extra bits, make sure to increase the bit index below as well.
	38	+ */
	39	+#define SPI_MODE_USER_MASK (_BITUL(16) - 1)
	40	+
	41	+#endif /* _UAPI_SPI_H */

include/uapi/linux/spi/spidev.h+1−29

@@ -25,35 +25,7 @@ · 24 unmodified lines
25	25
26	26	#include <linux/types.h>
27	27	#include <linux/ioctl.h>
28		−
29		−/* User space versions of kernel symbols for SPI clocking modes,
30		− * matching <linux/spi/spi.h>
31		− */
32		−
33		−#define SPI_CPHA 0x01
34		−#define SPI_CPOL 0x02
35		−
36		−#define SPI_MODE_0 (0\|0)
37		−#define SPI_MODE_1 (0\|SPI_CPHA)
38		−#define SPI_MODE_2 (SPI_CPOL\|0)
39		−#define SPI_MODE_3 (SPI_CPOL\|SPI_CPHA)
40		−
41		−#define SPI_CS_HIGH 0x04
42		−#define SPI_LSB_FIRST 0x08
43		−#define SPI_3WIRE 0x10
44		−#define SPI_LOOP 0x20
45		−#define SPI_NO_CS 0x40
46		−#define SPI_READY 0x80
47		−#define SPI_TX_DUAL 0x100
48		−#define SPI_TX_QUAD 0x200
49		−#define SPI_RX_DUAL 0x400
50		−#define SPI_RX_QUAD 0x800
51		−#define SPI_CS_WORD 0x1000
52		−#define SPI_TX_OCTAL 0x2000
53		−#define SPI_RX_OCTAL 0x4000
54		−#define SPI_3WIRE_HIZ 0x8000
55		−
56		−/---------------------------------------------------------------------------/
	28	+#include <linux/spi/spi.h>
57	29
58	30	/* IOCTL commands */
59	31