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drivers/perf: arm_pmu: Request PMU SPIs with IRQF_PER_CPU

Since the PMU register interface is banked per CPU, CPU PMU interrrupts cannot be handled by a CPU other than the one with the PMU asserting the interrupt. This means that migrating PMU SPIs, as we do during a CPU hotplug operation doesn't make any sense and can lead to the IRQ being disabled entirely if we route a spurious IRQ to the new affinity target. This has been observed in practice on AMD Seattle, where CPUs on the non-boot cluster appear to take a spurious PMU IRQ when coming online, which is routed to CPU0 where it cannot be handled. This patch passes IRQF_PERCPU for PMU SPIs and forcefully sets their affinity prior to requesting them, ensuring that they cannot be migrated during hotplug events. This interacts badly with the DB8500 erratum workaround that ping-pongs the interrupt affinity from the handler, so we avoid passing IRQF_PERCPU in that case by allowing the IRQ flags to be overridden in the platdata.

Will Deacon committed 9 years ago

Commit a3287c41 parent d0153c73 files · +32 −14Browse files

Unified · Split

3 files
  1. arch/arm/mach-ux500/cpu-db8500.c +1 −0
  2. drivers/perf/arm_pmu.c +27 −14
  3. include/linux/perf/arm_pmu.h +4 −0
arch/arm/mach-ux500/cpu-db8500.c+1−0
@@ -133,6 +133,7 @@ static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) · 132 unmodified lines
133 133
134static struct arm_pmu_platdata db8500_pmu_platdata = {134static struct arm_pmu_platdata db8500_pmu_platdata = {
135 .handle_irq = db8500_pmu_handler,135 .handle_irq = db8500_pmu_handler,
136 .irq_flags = IRQF_NOBALANCING | IRQF_NO_THREAD,
136};137};
137 138
138static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {139static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
drivers/perf/arm_pmu.c+27−14
@@ -569,22 +569,41 @@ int armpmu_request_irq(struct arm_pmu *armpmu, int cpu) · 568 unmodified lines
569 if (irq != other_irq) {569 if (irq != other_irq) {
570 pr_warn("mismatched PPIs detected.\n");570 pr_warn("mismatched PPIs detected.\n");
571 err = -EINVAL;571 err = -EINVAL;
572 goto err_out;
572 }573 }
573 } else {574 } else {
574 err = request_irq(irq, handler,575 struct arm_pmu_platdata *platdata = armpmu_get_platdata(armpmu);
575 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",576 unsigned long irq_flags;
577
578 err = irq_force_affinity(irq, cpumask_of(cpu));
579
580 if (err && num_possible_cpus() > 1) {
581 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
582 irq, cpu);
583 goto err_out;
584 }
585
586 if (platdata && platdata->irq_flags) {
587 irq_flags = platdata->irq_flags;
588 } else {
589 irq_flags = IRQF_PERCPU |
590 IRQF_NOBALANCING |
591 IRQF_NO_THREAD;
592 }
593
594 err = request_irq(irq, handler, irq_flags, "arm-pmu",
576 per_cpu_ptr(&hw_events->percpu_pmu, cpu));595 per_cpu_ptr(&hw_events->percpu_pmu, cpu));
577 }596 }
578 597
579 if (err) {598 if (err)
580 pr_err("unable to request IRQ%d for ARM PMU counters\n",599 goto err_out;
581 irq);
582 return err;
583 }
584 600
585 cpumask_set_cpu(cpu, &armpmu->active_irqs);601 cpumask_set_cpu(cpu, &armpmu->active_irqs);
586
587 return 0;602 return 0;
603
604err_out:
605 pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
606 return err;
588}607}
589 608
590int armpmu_request_irqs(struct arm_pmu *armpmu)609int armpmu_request_irqs(struct arm_pmu *armpmu)
@@ -628,12 +647,6 @@ static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) · 37 unmodified lines
628 enable_percpu_irq(irq, IRQ_TYPE_NONE);647 enable_percpu_irq(irq, IRQ_TYPE_NONE);
629 return 0;648 return 0;
630 }649 }
631
632 if (irq_force_affinity(irq, cpumask_of(cpu)) &&
633 num_possible_cpus() > 1) {
634 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
635 irq, cpu);
636 }
637 }650 }
638 651
639 return 0;652 return 0;
include/linux/perf/arm_pmu.h+4−0
@@ -24,10 +24,14 @@ · 23 unmodified lines
24 * interrupt and passed the address of the low level handler,24 * interrupt and passed the address of the low level handler,
25 * and can be used to implement any platform specific handling25 * and can be used to implement any platform specific handling
26 * before or after calling it.26 * before or after calling it.
27 *
28 * @irq_flags: if non-zero, these flags will be passed to request_irq
29 * when requesting interrupts for this PMU device.
27 */30 */
28struct arm_pmu_platdata {31struct arm_pmu_platdata {
29 irqreturn_t (*handle_irq)(int irq, void *dev,32 irqreturn_t (*handle_irq)(int irq, void *dev,
30 irq_handler_t pmu_handler);33 irq_handler_t pmu_handler);
34 unsigned long irq_flags;
31};35};
32 36
33#ifdef CONFIG_ARM_PMU37#ifdef CONFIG_ARM_PMU

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