Since the PMU register interface is banked per CPU, CPU PMU interrrupts cannot be handled by a CPU other than the one with the PMU asserting the interrupt. This means that migrating PMU SPIs, as we do during a CPU hotplug operation doesn't make any sense and can lead to the IRQ being disabled entirely if we route a spurious IRQ to the new affinity target. This has been observed in practice on AMD Seattle, where CPUs on the non-boot cluster appear to take a spurious PMU IRQ when coming online, which is routed to CPU0 where it cannot be handled. This patch passes IRQF_PERCPU for PMU SPIs and forcefully sets their affinity prior to requesting them, ensuring that they cannot be migrated during hotplug events. This interacts badly with the DB8500 erratum workaround that ping-pongs the interrupt affinity from the handler, so we avoid passing IRQF_PERCPU in that case by allowing the IRQ flags to be overridden in the platdata.
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| @@ -24,10 +24,14 @@ · 23 unmodified lines | ||
| 24 | 24 | * interrupt and passed the address of the low level handler, |
| 25 | 25 | * and can be used to implement any platform specific handling |
| 26 | 26 | * before or after calling it. |
| 27 | + * | |
| 28 | + * @irq_flags: if non-zero, these flags will be passed to request_irq | |
| 29 | + * when requesting interrupts for this PMU device. | |
| 27 | 30 | */ |
| 28 | 31 | struct arm_pmu_platdata { |
| 29 | 32 | irqreturn_t (*handle_irq)(int irq, void *dev, |
| 30 | 33 | irq_handler_t pmu_handler); |
| 34 | + unsigned long irq_flags; | |
| 31 | 35 | }; |
| 32 | 36 | |
| 33 | 37 | #ifdef CONFIG_ARM_PMU |