Fix ~36 single-word typos in the IRQ, irqchip and irqdomain code comments.
Unified · Split
| @@ -71,7 +71,7 @@ static void vic_init_hw(struct aspeed_vic *vic) · 70 unmodified lines | |||
| 71 | writel(0, vic->base + AVIC_INT_SELECT); | 71 | writel(0, vic->base + AVIC_INT_SELECT); |
| 72 | writel(0, vic->base + AVIC_INT_SELECT + 4); | 72 | writel(0, vic->base + AVIC_INT_SELECT + 4); |
| 73 | 73 | ||
| 74 | /* Some interrupts have a programable high/low level trigger | 74 | /* Some interrupts have a programmable high/low level trigger |
| 75 | * (4 GPIO direct inputs), for now we assume this was configured | 75 | * (4 GPIO direct inputs), for now we assume this was configured |
| 76 | * by firmware. We read which ones are edge now. | 76 | * by firmware. We read which ones are edge now. |
| 77 | */ | 77 | */ |
| @@ -203,7 +203,7 @@ static int __init avic_of_init(struct device_node *node, · 125 unmodified lines | |||
| 203 | } | 203 | } |
| 204 | vic->base = regs; | 204 | vic->base = regs; |
| 205 | 205 | ||
| 206 | /* Initialize soures, all masked */ | 206 | /* Initialize sources, all masked */ |
| 207 | vic_init_hw(vic); | 207 | vic_init_hw(vic); |
| 208 | 208 | ||
| 209 | /* Ready to receive interrupts */ | 209 | /* Ready to receive interrupts */ |
| @@ -309,7 +309,7 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, · 308 unmodified lines | |||
| 309 | 309 | ||
| 310 | if (data->can_wake) { | 310 | if (data->can_wake) { |
| 311 | /* This IRQ chip can wake the system, set all | 311 | /* This IRQ chip can wake the system, set all |
| 312 | * relevant child interupts in wake_enabled mask | 312 | * relevant child interrupts in wake_enabled mask |
| 313 | */ | 313 | */ |
| 314 | gc->wake_enabled = 0xffffffff; | 314 | gc->wake_enabled = 0xffffffff; |
| 315 | gc->wake_enabled &= ~gc->unused; | 315 | gc->wake_enabled &= ~gc->unused; |
| @@ -176,7 +176,7 @@ gx_intc_init(struct device_node *node, struct device_node *parent) · 175 unmodified lines | |||
| 176 | writel(0x0, reg_base + GX_INTC_NEN63_32); | 176 | writel(0x0, reg_base + GX_INTC_NEN63_32); |
| 177 | 177 | ||
| 178 | /* | 178 | /* |
| 179 | * Initial mask reg with all unmasked, because we only use enalbe reg | 179 | * Initial mask reg with all unmasked, because we only use enable reg |
| 180 | */ | 180 | */ |
| 181 | writel(0x0, reg_base + GX_INTC_NMASK31_00); | 181 | writel(0x0, reg_base + GX_INTC_NMASK31_00); |
| 182 | writel(0x0, reg_base + GX_INTC_NMASK63_32); | 182 | writel(0x0, reg_base + GX_INTC_NMASK63_32); |
| @@ -371,7 +371,7 @@ static int __init gicv2m_init_one(struct fwnode_handle *fwnode, · 370 unmodified lines | |||
| 371 | * the MSI data is the absolute value within the range from | 371 | * the MSI data is the absolute value within the range from |
| 372 | * spi_start to (spi_start + num_spis). | 372 | * spi_start to (spi_start + num_spis). |
| 373 | * | 373 | * |
| 374 | * Broadom NS2 GICv2m implementation has an erratum where the MSI data | 374 | * Broadcom NS2 GICv2m implementation has an erratum where the MSI data |
| 375 | * is 'spi_number - 32' | 375 | * is 'spi_number - 32' |
| 376 | * | 376 | * |
| 377 | * Reading that register fails on the Graviton implementation | 377 | * Reading that register fails on the Graviton implementation |
| @@ -1492,7 +1492,7 @@ static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) · 1491 unmodified lines | |||
| 1492 | * | 1492 | * |
| 1493 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | 1493 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI |
| 1494 | * value or to 1023, depending on the enable bit. But that | 1494 | * value or to 1023, depending on the enable bit. But that |
| 1495 | * would be issueing a mapping for an /existing/ DevID+EventID | 1495 | * would be issuing a mapping for an /existing/ DevID+EventID |
| 1496 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | 1496 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI |
| 1497 | * to the /same/ vPE, using this opportunity to adjust the | 1497 | * to the /same/ vPE, using this opportunity to adjust the |
| 1498 | * doorbell. Mouahahahaha. We loves it, Precious. | 1498 | * doorbell. Mouahahahaha. We loves it, Precious. |
| @@ -3122,7 +3122,7 @@ static void its_cpu_init_lpis(void) · 1623 unmodified lines | |||
| 3122 | 3122 | ||
| 3123 | /* | 3123 | /* |
| 3124 | * It's possible for CPU to receive VLPIs before it is | 3124 | * It's possible for CPU to receive VLPIs before it is |
| 3125 | * sheduled as a vPE, especially for the first CPU, and the | 3125 | * scheduled as a vPE, especially for the first CPU, and the |
| 3126 | * VLPI with INTID larger than 2^(IDbits+1) will be considered | 3126 | * VLPI with INTID larger than 2^(IDbits+1) will be considered |
| 3127 | * as out of range and dropped by GIC. | 3127 | * as out of range and dropped by GIC. |
| 3128 | * So we initialize IDbits to known value to avoid VLPI drop. | 3128 | * So we initialize IDbits to known value to avoid VLPI drop. |
| @@ -3616,7 +3616,7 @@ static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, · 487 unmodified lines | |||
| 3616 | 3616 | ||
| 3617 | /* | 3617 | /* |
| 3618 | * If all interrupts have been freed, start mopping the | 3618 | * If all interrupts have been freed, start mopping the |
| 3619 | * floor. This is conditionned on the device not being shared. | 3619 | * floor. This is conditioned on the device not being shared. |
| 3620 | */ | 3620 | */ |
| 3621 | if (!its_dev->shared && | 3621 | if (!its_dev->shared && |
| 3622 | bitmap_empty(its_dev->event_map.lpi_map, | 3622 | bitmap_empty(its_dev->event_map.lpi_map, |
| @@ -4194,7 +4194,7 @@ static int its_sgi_set_affinity(struct irq_data *d, · 571 unmodified lines | |||
| 4194 | { | 4194 | { |
| 4195 | /* | 4195 | /* |
| 4196 | * There is no notion of affinity for virtual SGIs, at least | 4196 | * There is no notion of affinity for virtual SGIs, at least |
| 4197 | * not on the host (since they can only be targetting a vPE). | 4197 | * not on the host (since they can only be targeting a vPE). |
| 4198 | * Tell the kernel we've done whatever it asked for. | 4198 | * Tell the kernel we've done whatever it asked for. |
| 4199 | */ | 4199 | */ |
| 4200 | irq_data_update_effective_affinity(d, mask_val); | 4200 | irq_data_update_effective_affinity(d, mask_val); |
| @@ -4239,7 +4239,7 @@ static int its_sgi_get_irqchip_state(struct irq_data *d, · 38 unmodified lines | |||
| 4239 | /* | 4239 | /* |
| 4240 | * Locking galore! We can race against two different events: | 4240 | * Locking galore! We can race against two different events: |
| 4241 | * | 4241 | * |
| 4242 | * - Concurent vPE affinity change: we must make sure it cannot | 4242 | * - Concurrent vPE affinity change: we must make sure it cannot |
| 4243 | * happen, or we'll talk to the wrong redistributor. This is | 4243 | * happen, or we'll talk to the wrong redistributor. This is |
| 4244 | * identical to what happens with vLPIs. | 4244 | * identical to what happens with vLPIs. |
| 4245 | * | 4245 | * |
| @@ -1379,7 +1379,7 @@ static int gic_irq_domain_translate(struct irq_domain *d, · 1378 unmodified lines | |||
| 1379 | 1379 | ||
| 1380 | /* | 1380 | /* |
| 1381 | * Make it clear that broken DTs are... broken. | 1381 | * Make it clear that broken DTs are... broken. |
| 1382 | * Partitionned PPIs are an unfortunate exception. | 1382 | * Partitioned PPIs are an unfortunate exception. |
| 1383 | */ | 1383 | */ |
| 1384 | WARN_ON(*type == IRQ_TYPE_NONE && | 1384 | WARN_ON(*type == IRQ_TYPE_NONE && |
| 1385 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); | 1385 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); |
| @@ -163,7 +163,7 @@ static void pch_pic_reset(struct pch_pic *priv) · 162 unmodified lines | |||
| 163 | int i; | 163 | int i; |
| 164 | 164 | ||
| 165 | for (i = 0; i < PIC_COUNT; i++) { | 165 | for (i = 0; i < PIC_COUNT; i++) { |
| 166 | /* Write vectore ID */ | 166 | /* Write vectored ID */ |
| 167 | writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i)); | 167 | writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i)); |
| 168 | /* Hardcode route to HT0 Lo */ | 168 | /* Hardcode route to HT0 Lo */ |
| 169 | writeb(1, priv->base + PCH_INT_ROUTE(i)); | 169 | writeb(1, priv->base + PCH_INT_ROUTE(i)); |
| @@ -227,7 +227,7 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, · 226 unmodified lines | |||
| 227 | 227 | ||
| 228 | /* | 228 | /* |
| 229 | * Get the hwirq number assigned to this channel through | 229 | * Get the hwirq number assigned to this channel through |
| 230 | * a pointer the channel_irq table. The added benifit of this | 230 | * a pointer the channel_irq table. The added benefit of this |
| 231 | * method is that we can also retrieve the channel index with | 231 | * method is that we can also retrieve the channel index with |
| 232 | * it, using the table base. | 232 | * it, using the table base. |
| 233 | */ | 233 | */ |
| @@ -217,7 +217,7 @@ static void mtk_cirq_resume(void) · 216 unmodified lines | |||
| 217 | { | 217 | { |
| 218 | u32 value; | 218 | u32 value; |
| 219 | 219 | ||
| 220 | /* flush recored interrupts, will send signals to parent controller */ | 220 | /* flush recorded interrupts, will send signals to parent controller */ |
| 221 | value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); | 221 | value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); |
| 222 | writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); | 222 | writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); |
| 223 | 223 | ||
| @@ -58,7 +58,7 @@ struct icoll_priv { · 57 unmodified lines | |||
| 58 | static struct icoll_priv icoll_priv; | 58 | static struct icoll_priv icoll_priv; |
| 59 | static struct irq_domain *icoll_domain; | 59 | static struct irq_domain *icoll_domain; |
| 60 | 60 | ||
| 61 | /* calculate bit offset depending on number of intterupt per register */ | 61 | /* calculate bit offset depending on number of interrupt per register */ |
| 62 | static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) | 62 | static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) |
| 63 | { | 63 | { |
| 64 | /* | 64 | /* |
| @@ -68,7 +68,7 @@ static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) · 3 unmodified lines | |||
| 68 | return bit << ((d->hwirq & 3) << 3); | 68 | return bit << ((d->hwirq & 3) << 3); |
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | /* calculate mem offset depending on number of intterupt per register */ | 71 | /* calculate mem offset depending on number of interrupt per register */ |
| 72 | static void __iomem *icoll_intr_reg(struct irq_data *d) | 72 | static void __iomem *icoll_intr_reg(struct irq_data *d) |
| 73 | { | 73 | { |
| 74 | /* offset = hwirq / intr_per_reg * 0x10 */ | 74 | /* offset = hwirq / intr_per_reg * 0x10 */ |
| @@ -189,7 +189,7 @@ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) · 188 unmodified lines | |||
| 189 | * 3) spurious irq | 189 | * 3) spurious irq |
| 190 | * So if we immediately get a reading of 0, check the irq-pending reg | 190 | * So if we immediately get a reading of 0, check the irq-pending reg |
| 191 | * to differentiate between 2 and 3. We only do this once to avoid | 191 | * to differentiate between 2 and 3. We only do this once to avoid |
| 192 | * the extra check in the common case of 1 hapening after having | 192 | * the extra check in the common case of 1 happening after having |
| 193 | * read the vector-reg once. | 193 | * read the vector-reg once. |
| 194 | */ | 194 | */ |
| 195 | hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; | 195 | hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; |
| @@ -78,7 +78,7 @@ struct ti_sci_inta_vint_desc { · 77 unmodified lines | |||
| 78 | * struct ti_sci_inta_irq_domain - Structure representing a TISCI based | 78 | * struct ti_sci_inta_irq_domain - Structure representing a TISCI based |
| 79 | * Interrupt Aggregator IRQ domain. | 79 | * Interrupt Aggregator IRQ domain. |
| 80 | * @sci: Pointer to TISCI handle | 80 | * @sci: Pointer to TISCI handle |
| 81 | * @vint: TISCI resource pointer representing IA inerrupts. | 81 | * @vint: TISCI resource pointer representing IA interrupts. |
| 82 | * @global_event: TISCI resource pointer representing global events. | 82 | * @global_event: TISCI resource pointer representing global events. |
| 83 | * @vint_list: List of the vints active in the system | 83 | * @vint_list: List of the vints active in the system |
| 84 | * @vint_mutex: Mutex to protect vint_list | 84 | * @vint_mutex: Mutex to protect vint_list |
| @@ -163,7 +163,7 @@ static struct syscore_ops vic_syscore_ops = { · 162 unmodified lines | |||
| 163 | }; | 163 | }; |
| 164 | 164 | ||
| 165 | /** | 165 | /** |
| 166 | * vic_pm_init - initicall to register VIC pm | 166 | * vic_pm_init - initcall to register VIC pm |
| 167 | * | 167 | * |
| 168 | * This is called via late_initcall() to register | 168 | * This is called via late_initcall() to register |
| 169 | * the resources for the VICs due to the early | 169 | * the resources for the VICs due to the early |
| @@ -397,7 +397,7 @@ static void __init vic_clear_interrupts(void __iomem *base) · 227 unmodified lines | |||
| 397 | /* | 397 | /* |
| 398 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | 398 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. |
| 399 | * The original cell has 32 interrupts, while the modified one has 64, | 399 | * The original cell has 32 interrupts, while the modified one has 64, |
| 400 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | 400 | * replicating two blocks 0x00..0x1f in 0x20..0x3f. In that case |
| 401 | * the probe function is called twice, with base set to offset 000 | 401 | * the probe function is called twice, with base set to offset 000 |
| 402 | * and 020 within the page. We call this "second block". | 402 | * and 020 within the page. We call this "second block". |
| 403 | */ | 403 | */ |
| @@ -210,7 +210,7 @@ static int __init xilinx_intc_of_init(struct device_node *intc, · 209 unmodified lines | |||
| 210 | 210 | ||
| 211 | /* | 211 | /* |
| 212 | * Disable all external interrupts until they are | 212 | * Disable all external interrupts until they are |
| 213 | * explicity requested. | 213 | * explicitly requested. |
| 214 | */ | 214 | */ |
| 215 | xintc_write(irqc, IER, 0); | 215 | xintc_write(irqc, IER, 0); |
| 216 | 216 | ||
| @@ -116,7 +116,7 @@ enum { · 115 unmodified lines | |||
| 116 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity | 116 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity |
| 117 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to | 117 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
| 118 | * support stacked irqchips, which indicates skipping | 118 | * support stacked irqchips, which indicates skipping |
| 119 | * all descendent irqchips. | 119 | * all descendant irqchips. |
| 120 | */ | 120 | */ |
| 121 | enum { | 121 | enum { |
| 122 | IRQ_SET_MASK_OK = 0, | 122 | IRQ_SET_MASK_OK = 0, |
| @@ -302,7 +302,7 @@ static inline bool irqd_is_level_type(struct irq_data *d) · 179 unmodified lines | |||
| 302 | 302 | ||
| 303 | /* | 303 | /* |
| 304 | * Must only be called of irqchip.irq_set_affinity() or low level | 304 | * Must only be called of irqchip.irq_set_affinity() or low level |
| 305 | * hieararchy domain allocation functions. | 305 | * hierarchy domain allocation functions. |
| 306 | */ | 306 | */ |
| 307 | static inline void irqd_set_single_target(struct irq_data *d) | 307 | static inline void irqd_set_single_target(struct irq_data *d) |
| 308 | { | 308 | { |
| @@ -32,7 +32,7 @@ struct pt_regs; · 31 unmodified lines | |||
| 32 | * @last_unhandled: aging timer for unhandled count | 32 | * @last_unhandled: aging timer for unhandled count |
| 33 | * @irqs_unhandled: stats field for spurious unhandled interrupts | 33 | * @irqs_unhandled: stats field for spurious unhandled interrupts |
| 34 | * @threads_handled: stats field for deferred spurious detection of threaded handlers | 34 | * @threads_handled: stats field for deferred spurious detection of threaded handlers |
| 35 | * @threads_handled_last: comparator field for deferred spurious detection of theraded handlers | 35 | * @threads_handled_last: comparator field for deferred spurious detection of threaded handlers |
| 36 | * @lock: locking for SMP | 36 | * @lock: locking for SMP |
| 37 | * @affinity_hint: hint to user space for preferred irq affinity | 37 | * @affinity_hint: hint to user space for preferred irq affinity |
| 38 | * @affinity_notify: context for notification of affinity changes | 38 | * @affinity_notify: context for notification of affinity changes |
| @@ -808,7 +808,7 @@ void handle_edge_irq(struct irq_desc *desc) · 807 unmodified lines | |||
| 808 | /* | 808 | /* |
| 809 | * When another irq arrived while we were handling | 809 | * When another irq arrived while we were handling |
| 810 | * one, we could have masked the irq. | 810 | * one, we could have masked the irq. |
| 811 | * Renable it, if it was not disabled in meantime. | 811 | * Reenable it, if it was not disabled in meantime. |
| 812 | */ | 812 | */ |
| 813 | if (unlikely(desc->istate & IRQS_PENDING)) { | 813 | if (unlikely(desc->istate & IRQS_PENDING)) { |
| 814 | if (!irqd_irq_disabled(&desc->irq_data) && | 814 | if (!irqd_irq_disabled(&desc->irq_data) && |
| @@ -13,7 +13,7 @@ · 12 unmodified lines | |||
| 13 | 13 | ||
| 14 | /* | 14 | /* |
| 15 | * What should we do if we get a hw irq event on an illegal vector? | 15 | * What should we do if we get a hw irq event on an illegal vector? |
| 16 | * Each architecture has to answer this themself. | 16 | * Each architecture has to answer this themselves. |
| 17 | */ | 17 | */ |
| 18 | static void ack_bad(struct irq_data *data) | 18 | static void ack_bad(struct irq_data *data) |
| 19 | { | 19 | { |
| @@ -31,7 +31,7 @@ static int __init irq_affinity_setup(char *str) · 30 unmodified lines | |||
| 31 | cpulist_parse(str, irq_default_affinity); | 31 | cpulist_parse(str, irq_default_affinity); |
| 32 | /* | 32 | /* |
| 33 | * Set at least the boot cpu. We don't want to end up with | 33 | * Set at least the boot cpu. We don't want to end up with |
| 34 | * bugreports caused by random comandline masks | 34 | * bugreports caused by random commandline masks |
| 35 | */ | 35 | */ |
| 36 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); | 36 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); |
| 37 | return 1; | 37 | return 1; |
| @@ -62,7 +62,7 @@ EXPORT_SYMBOL_GPL(irqchip_fwnode_ops); · 61 unmodified lines | |||
| 62 | * @name: Optional user provided domain name | 62 | * @name: Optional user provided domain name |
| 63 | * @pa: Optional user-provided physical address | 63 | * @pa: Optional user-provided physical address |
| 64 | * | 64 | * |
| 65 | * Allocate a struct irqchip_fwid, and return a poiner to the embedded | 65 | * Allocate a struct irqchip_fwid, and return a pointer to the embedded |
| 66 | * fwnode_handle (or NULL on failure). | 66 | * fwnode_handle (or NULL on failure). |
| 67 | * | 67 | * |
| 68 | * Note: The types IRQCHIP_FWNODE_NAMED and IRQCHIP_FWNODE_NAMED_ID are | 68 | * Note: The types IRQCHIP_FWNODE_NAMED and IRQCHIP_FWNODE_NAMED_ID are |
| @@ -665,7 +665,7 @@ unsigned int irq_create_mapping_affinity(struct irq_domain *domain, · 596 unmodified lines | |||
| 665 | 665 | ||
| 666 | pr_debug("irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); | 666 | pr_debug("irq_create_mapping(0x%p, 0x%lx)\n", domain, hwirq); |
| 667 | 667 | ||
| 668 | /* Look for default domain if nececssary */ | 668 | /* Look for default domain if necessary */ |
| 669 | if (domain == NULL) | 669 | if (domain == NULL) |
| 670 | domain = irq_default_domain; | 670 | domain = irq_default_domain; |
| 671 | if (domain == NULL) { | 671 | if (domain == NULL) { |
| @@ -906,7 +906,7 @@ unsigned int irq_find_mapping(struct irq_domain *domain, · 234 unmodified lines | |||
| 906 | { | 906 | { |
| 907 | struct irq_data *data; | 907 | struct irq_data *data; |
| 908 | 908 | ||
| 909 | /* Look for default domain if nececssary */ | 909 | /* Look for default domain if necessary */ |
| 910 | if (domain == NULL) | 910 | if (domain == NULL) |
| 911 | domain = irq_default_domain; | 911 | domain = irq_default_domain; |
| 912 | if (domain == NULL) | 912 | if (domain == NULL) |
| @@ -1436,7 +1436,7 @@ int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain, · 523 unmodified lines | |||
| 1436 | * The whole process to setup an IRQ has been split into two steps. | 1436 | * The whole process to setup an IRQ has been split into two steps. |
| 1437 | * The first step, __irq_domain_alloc_irqs(), is to allocate IRQ | 1437 | * The first step, __irq_domain_alloc_irqs(), is to allocate IRQ |
| 1438 | * descriptor and required hardware resources. The second step, | 1438 | * descriptor and required hardware resources. The second step, |
| 1439 | * irq_domain_activate_irq(), is to program hardwares with preallocated | 1439 | * irq_domain_activate_irq(), is to program the hardware with preallocated |
| 1440 | * resources. In this way, it's easier to rollback when failing to | 1440 | * resources. In this way, it's easier to rollback when failing to |
| 1441 | * allocate resources. | 1441 | * allocate resources. |
| 1442 | */ | 1442 | */ |
| @@ -326,7 +326,7 @@ static bool irq_set_affinity_deactivated(struct irq_data *data, · 325 unmodified lines | |||
| 326 | * If the interrupt is not yet activated, just store the affinity | 326 | * If the interrupt is not yet activated, just store the affinity |
| 327 | * mask and do not call the chip driver at all. On activation the | 327 | * mask and do not call the chip driver at all. On activation the |
| 328 | * driver has to make sure anyway that the interrupt is in a | 328 | * driver has to make sure anyway that the interrupt is in a |
| 329 | * useable state so startup works. | 329 | * usable state so startup works. |
| 330 | */ | 330 | */ |
| 331 | if (!IS_ENABLED(CONFIG_IRQ_DOMAIN_HIERARCHY) || | 331 | if (!IS_ENABLED(CONFIG_IRQ_DOMAIN_HIERARCHY) || |
| 332 | irqd_is_activated(data) || !irqd_affinity_on_activate(data)) | 332 | irqd_is_activated(data) || !irqd_affinity_on_activate(data)) |
| @@ -1054,7 +1054,7 @@ again: · 721 unmodified lines | |||
| 1054 | * to IRQS_INPROGRESS and the irq line is masked forever. | 1054 | * to IRQS_INPROGRESS and the irq line is masked forever. |
| 1055 | * | 1055 | * |
| 1056 | * This also serializes the state of shared oneshot handlers | 1056 | * This also serializes the state of shared oneshot handlers |
| 1057 | * versus "desc->threads_onehsot |= action->thread_mask;" in | 1057 | * versus "desc->threads_oneshot |= action->thread_mask;" in |
| 1058 | * irq_wake_thread(). See the comment there which explains the | 1058 | * irq_wake_thread(). See the comment there which explains the |
| 1059 | * serialization. | 1059 | * serialization. |
| 1060 | */ | 1060 | */ |
| @@ -1909,7 +1909,7 @@ static struct irqaction *__free_irq(struct irq_desc *desc, void *dev_id) · 848 unmodified lines | |||
| 1909 | /* Last action releases resources */ | 1909 | /* Last action releases resources */ |
| 1910 | if (!desc->action) { | 1910 | if (!desc->action) { |
| 1911 | /* | 1911 | /* |
| 1912 | * Reaquire bus lock as irq_release_resources() might | 1912 | * Reacquire bus lock as irq_release_resources() might |
| 1913 | * require it to deallocate resources over the slow bus. | 1913 | * require it to deallocate resources over the slow bus. |
| 1914 | */ | 1914 | */ |
| 1915 | chip_bus_lock(desc); | 1915 | chip_bus_lock(desc); |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | |||
| 5 | * | 5 | * |
| 6 | * This file is licensed under GPLv2. | 6 | * This file is licensed under GPLv2. |
| 7 | * | 7 | * |
| 8 | * This file contains common code to support Message Signalled Interrupt for | 8 | * This file contains common code to support Message Signaled Interrupts for |
| 9 | * PCI compatible and non PCI compatible devices. | 9 | * PCI compatible and non PCI compatible devices. |
| 10 | */ | 10 | */ |
| 11 | #include <linux/types.h> | 11 | #include <linux/types.h> |
| @@ -485,7 +485,7 @@ static inline void irq_timings_store(int irq, struct irqt_stat *irqs, u64 ts) · 484 unmodified lines | |||
| 485 | 485 | ||
| 486 | /* | 486 | /* |
| 487 | * The interrupt triggered more than one second apart, that | 487 | * The interrupt triggered more than one second apart, that |
| 488 | * ends the sequence as predictible for our purpose. In this | 488 | * ends the sequence as predictable for our purpose. In this |
| 489 | * case, assume we have the beginning of a sequence and the | 489 | * case, assume we have the beginning of a sequence and the |
| 490 | * timestamp is the first value. As it is impossible to | 490 | * timestamp is the first value. As it is impossible to |
| 491 | * predict anything at this point, return. | 491 | * predict anything at this point, return. |