Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Ingo Molnar: "A CR4-shadow 32-bit init fix, plus two typo fixes" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: Init per-cpu shadow copy of CR4 on 32-bit CPUs too x86/platform/intel-mid: Fix trivial printk message typo in intel_mid_arch_setup() x86/cpu/intel: Fix trivial typo in intel_tlb_table[]

Linus Torvalds committed 11 years ago

Commit a38ecbb2 parents 640c0f5 5b2bdbc3 files · +9 −3Browse files

Unified · Split

3 files

arch/x86/kernel/cpu/common.c +6 −0
arch/x86/kernel/cpu/intel.c +2 −2
arch/x86/platform/intel-mid/intel-mid.c +1 −1

arch/x86/kernel/cpu/common.c+6−0

@@ -1396,6 +1396,12 @@ void cpu_init(void) · 1395 unmodified lines
1396	1396
1397	1397	wait_for_master_cpu(cpu);
1398	1398
	1399	+ /*
	1400	+ * Initialize the CR4 shadow before doing anything that could
	1401	+ * try to read it.
	1402	+ */
	1403	+ cr4_init_shadow();
	1404	+
1399	1405	show_ucode_info_early();
1400	1406
1401	1407	printk(KERN_INFO "Initializing CPU#%d\n", cpu);

arch/x86/kernel/cpu/intel.c+2−2

@@ -565,8 +565,8 @@ static const struct _tlb_table intel_tlb_table[] = { · 564 unmodified lines
565	565	{ 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
566	566	{ 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
567	567	{ 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
568		− { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
569		− { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
	568	+ { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
	569	+ { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
570	570	{ 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
571	571	{ 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
572	572	{ 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },

arch/x86/platform/intel-mid/intel-mid.c+1−1

@@ -130,7 +130,7 @@ static void intel_mid_arch_setup(void) · 129 unmodified lines
130	130	intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
131	131	else {
132	132	intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
133		− pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");
	133	+ pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
134	134	}
135	135
136	136	out: