History

Merge tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/soc

ARM: Marvell MMP SoC patches for v5.5 This tag includes initial support for the Marvell MMP3 processor. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet and Dell Wyse 3020/Tx0D thin clients. * tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp: MAINTAINERS: mmp: add Git repository ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h ARM: mmp: move cputype.h to include/linux/soc/ ARM: mmp: add SMP support ARM: mmp: add support for MMP3 SoC ARM: mmp: define MMP_CHIPID by the means of CIU_REG() ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE ARM: mmp: map the PGU as well ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP ARM: l2c: add definition for FWA in PL310 aux register

Olof Johansson committed 7 years ago

Commit a4e86632 parents da0c9ea 759c28324 files · +174 −142Browse files

Unified · Split

24 files
  1. MAINTAINERS +2 −0
  2. arch/arm/include/asm/hardware/cache-l2x0.h +2 −0
  3. arch/arm/mach-mmp/Kconfig +20 −2
  4. arch/arm/mach-mmp/Makefile +4 −0
  5. arch/arm/mach-mmp/addr-map.h +7 −0
  6. arch/arm/mach-mmp/common.c +17 −2
  7. arch/arm/mach-mmp/common.h +1 −0
  8. arch/arm/mach-mmp/devices.c +1 −1
  9. arch/arm/mach-mmp/mmp-dt.c +2 −3
  10. arch/arm/mach-mmp/mmp2-dt.c +3 −4
  11. arch/arm/mach-mmp/mmp2.c +1 −1
  12. arch/arm/mach-mmp/mmp3.c +29 −0
  13. arch/arm/mach-mmp/platsmp.c +32 −0
  14. arch/arm/mach-mmp/pm-mmp2.c +1 −1
  15. arch/arm/mach-mmp/pm-pxa910.c +1 −1
  16. arch/arm/mach-mmp/pxa168.c +1 −1
  17. arch/arm/mach-mmp/pxa910.c +1 −1
  18. arch/arm/mach-mmp/regs-usb.h +0 −94
  19. arch/arm/mach-mmp/time.c +14 −29
  20. arch/arm/mm/Kconfig +1 −1
  21. drivers/clk/Kconfig +5 −0
  22. drivers/clk/mmp/Makefile +1 −1
  23. include/Kbuild +1 −0
  24. include/linux/soc/mmp/cputype.h +27 −0
MAINTAINERS+2−0
@@ -10909,9 +10909,11 @@ F: drivers/media/radio/radio-miropcm20* · 10908 unmodified lines
10909MMP SUPPORT10909MMP SUPPORT
10910R: Lubomir Rintel <lkundrak@v3.sk>10910R: Lubomir Rintel <lkundrak@v3.sk>
10911L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)10911L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
10912T: git git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp.git
10912S: Odd Fixes10913S: Odd Fixes
10913F: arch/arm/boot/dts/mmp*10914F: arch/arm/boot/dts/mmp*
10914F: arch/arm/mach-mmp/10915F: arch/arm/mach-mmp/
10916F: linux/soc/mmp/
10915 10917
10916MMU GATHER AND TLB INVALIDATION10918MMU GATHER AND TLB INVALIDATION
10917M: Will Deacon <will@kernel.org>10919M: Will Deacon <will@kernel.org>
arch/arm/include/asm/hardware/cache-l2x0.h+2−0
@@ -118,6 +118,8 @@ · 117 unmodified lines
118#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */118#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
119#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)119#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
120#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)120#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
121#define L310_AUX_CTRL_FWA_SHIFT 23
122#define L310_AUX_CTRL_FWA_MASK (3 << 23)
121#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */123#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
122#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)124#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
123#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)125#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
arch/arm/mach-mmp/Kconfig+20−2
@@ -1,13 +1,13 @@
1# SPDX-License-Identifier: GPL-2.0-only1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig ARCH_MMP2menuconfig ARCH_MMP
3 bool "Marvell PXA168/910/MMP2"3 bool "Marvell PXA168/910/MMP2/MMP3"
4 depends on ARCH_MULTI_V5 || ARCH_MULTI_V74 depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
5 select GPIO_PXA5 select GPIO_PXA
6 select GPIOLIB6 select GPIOLIB
7 select PINCTRL7 select PINCTRL
8 select PLAT_PXA8 select PLAT_PXA
9 help9 help
10 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.10 Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.
11 11
12if ARCH_MMP12if ARCH_MMP
13 13
@@ -129,6 +129,24 @@ config MACH_MMP2_DT · 115 unmodified lines
129 Include support for Marvell MMP2 based platforms using129 Include support for Marvell MMP2 based platforms using
130 the device tree.130 the device tree.
131 131
132config MACH_MMP3_DT
133 bool "Support MMP3 (ARMv7) platforms"
134 depends on ARCH_MULTI_V7
135 select ARM_GIC
136 select HAVE_ARM_SCU if SMP
137 select HAVE_ARM_TWD if SMP
138 select CACHE_L2X0
139 select PINCTRL
140 select PINCTRL_SINGLE
141 select ARCH_HAS_RESET_CONTROLLER
142 select CPU_PJ4B
143 select PM_GENERIC_DOMAINS if PM
144 select PM_GENERIC_DOMAINS_OF if PM && OF
145 help
146 Say 'Y' here if you want to include support for platforms
147 with Marvell MMP3 processor, also known as PXA2128 or
148 Armada 620.
149
132endmenu150endmenu
133 151
134config CPU_PXA168152config CPU_PXA168
arch/arm/mach-mmp/Makefile+4−0
@@ -22,6 +22,9 @@ ifeq ($(CONFIG_PM),y) · 21 unmodified lines
22obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o22obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
23obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o23obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
24endif24endif
25ifeq ($(CONFIG_SMP),y)
26obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o
27endif
25 28
26# board support29# board support
27obj-$(CONFIG_MACH_ASPENITE) += aspenite.o30obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
@@ -34,5 +37,6 @@ obj-$(CONFIG_MACH_FLINT) += flint.o · 6 unmodified lines
34obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o37obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
35obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o38obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
36obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o39obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
40obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
37obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o41obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
38obj-$(CONFIG_MACH_GPLUGD) += gplugd.o42obj-$(CONFIG_MACH_GPLUGD) += gplugd.o
arch/arm/mach-mmp/addr-map.h+7−0
@@ -20,6 +20,10 @@ · 19 unmodified lines
20#define AXI_VIRT_BASE IOMEM(0xfe200000)20#define AXI_VIRT_BASE IOMEM(0xfe200000)
21#define AXI_PHYS_SIZE 0x0020000021#define AXI_PHYS_SIZE 0x00200000
22 22
23#define PGU_PHYS_BASE 0xe0000000
24#define PGU_VIRT_BASE IOMEM(0xfe400000)
25#define PGU_PHYS_SIZE 0x00100000
26
23/* Static Memory Controller - Chip Select 0 and 1 */27/* Static Memory Controller - Chip Select 0 and 1 */
24#define SMC_CS0_PHYS_BASE 0x8000000028#define SMC_CS0_PHYS_BASE 0x80000000
25#define SMC_CS0_PHYS_SIZE 0x1000000029#define SMC_CS0_PHYS_SIZE 0x10000000
@@ -38,4 +42,7 @@ · 12 unmodified lines
38#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)42#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)
39#define CIU_REG(x) (CIU_VIRT_BASE + (x))43#define CIU_REG(x) (CIU_VIRT_BASE + (x))
40 44
45#define SCU_VIRT_BASE (PGU_VIRT_BASE)
46#define SCU_REG(x) (SCU_VIRT_BASE + (x))
47
41#endif /* __ASM_MACH_ADDR_MAP_H */48#endif /* __ASM_MACH_ADDR_MAP_H */
arch/arm/mach-mmp/common.c+17−2
@@ -13,11 +13,11 @@ · 12 unmodified lines
13#include <asm/mach/map.h>13#include <asm/mach/map.h>
14#include <asm/system_misc.h>14#include <asm/system_misc.h>
15#include "addr-map.h"15#include "addr-map.h"
16#include "cputype.h"16#include <linux/soc/mmp/cputype.h>
17 17
18#include "common.h"18#include "common.h"
19 19
20#define MMP_CHIPID (AXI_VIRT_BASE + 0x82c00)20#define MMP_CHIPID CIU_REG(0x00)
21 21
22unsigned int mmp_chip_id;22unsigned int mmp_chip_id;
23EXPORT_SYMBOL(mmp_chip_id);23EXPORT_SYMBOL(mmp_chip_id);
@@ -36,6 +36,15 @@ static struct map_desc standard_io_desc[] __initdata = { · 12 unmodified lines
36 },36 },
37};37};
38 38
39static struct map_desc mmp2_io_desc[] __initdata = {
40 {
41 .pfn = __phys_to_pfn(PGU_PHYS_BASE),
42 .virtual = (unsigned long)PGU_VIRT_BASE,
43 .length = PGU_PHYS_SIZE,
44 .type = MT_DEVICE,
45 },
46};
47
39void __init mmp_map_io(void)48void __init mmp_map_io(void)
40{49{
41 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));50 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
@@ -44,6 +53,12 @@ void __init mmp_map_io(void) · 2 unmodified lines
44 mmp_chip_id = __raw_readl(MMP_CHIPID);53 mmp_chip_id = __raw_readl(MMP_CHIPID);
45}54}
46 55
56void __init mmp2_map_io(void)
57{
58 mmp_map_io();
59 iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
60}
61
47void mmp_restart(enum reboot_mode mode, const char *cmd)62void mmp_restart(enum reboot_mode mode, const char *cmd)
48{63{
49 soft_restart(0);64 soft_restart(0);
arch/arm/mach-mmp/common.h+1−0
@@ -5,4 +5,5 @@ · 4 unmodified lines
5extern void mmp_timer_init(int irq, unsigned long rate);5extern void mmp_timer_init(int irq, unsigned long rate);
6 6
7extern void __init mmp_map_io(void);7extern void __init mmp_map_io(void);
8extern void __init mmp2_map_io(void);
8extern void mmp_restart(enum reboot_mode, const char *);9extern void mmp_restart(enum reboot_mode, const char *);
arch/arm/mach-mmp/devices.c+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
11#include <asm/irq.h>11#include <asm/irq.h>
12#include "irqs.h"12#include "irqs.h"
13#include "devices.h"13#include "devices.h"
14#include "cputype.h"14#include <linux/soc/mmp/cputype.h>
15#include "regs-usb.h"15#include "regs-usb.h"
16 16
17int __init pxa_register_device(struct pxa_device_desc *desc,17int __init pxa_register_device(struct pxa_device_desc *desc,
arch/arm/mach-mmp/mmp-dt.c+2−3
@@ -9,14 +9,13 @@ · 8 unmodified lines
9#include <linux/irqchip.h>9#include <linux/irqchip.h>
10#include <linux/of_platform.h>10#include <linux/of_platform.h>
11#include <linux/clk-provider.h>11#include <linux/clk-provider.h>
12#include <linux/clocksource.h>
12#include <asm/mach/arch.h>13#include <asm/mach/arch.h>
13#include <asm/mach/time.h>14#include <asm/mach/time.h>
14#include <asm/hardware/cache-tauros2.h>15#include <asm/hardware/cache-tauros2.h>
15 16
16#include "common.h"17#include "common.h"
17 18
18extern void __init mmp_dt_init_timer(void);
19
20static const char *const pxa168_dt_board_compat[] __initconst = {19static const char *const pxa168_dt_board_compat[] __initconst = {
21 "mrvl,pxa168-aspenite",20 "mrvl,pxa168-aspenite",
22 NULL,21 NULL,
@@ -32,8 +31,8 @@ static void __init mmp_init_time(void) · 9 unmodified lines
32#ifdef CONFIG_CACHE_TAUROS231#ifdef CONFIG_CACHE_TAUROS2
33 tauros2_init(0);32 tauros2_init(0);
34#endif33#endif
35 mmp_dt_init_timer();
36 of_clk_init(NULL);34 of_clk_init(NULL);
35 timer_probe();
37}36}
38 37
39DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")38DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
arch/arm/mach-mmp/mmp2-dt.c+3−4
@@ -10,21 +10,20 @@ · 9 unmodified lines
10#include <linux/irqchip.h>10#include <linux/irqchip.h>
11#include <linux/of_platform.h>11#include <linux/of_platform.h>
12#include <linux/clk-provider.h>12#include <linux/clk-provider.h>
13#include <linux/clocksource.h>
13#include <asm/mach/arch.h>14#include <asm/mach/arch.h>
14#include <asm/mach/time.h>15#include <asm/mach/time.h>
15#include <asm/hardware/cache-tauros2.h>16#include <asm/hardware/cache-tauros2.h>
16 17
17#include "common.h"18#include "common.h"
18 19
19extern void __init mmp_dt_init_timer(void);
20
21static void __init mmp_init_time(void)20static void __init mmp_init_time(void)
22{21{
23#ifdef CONFIG_CACHE_TAUROS222#ifdef CONFIG_CACHE_TAUROS2
24 tauros2_init(0);23 tauros2_init(0);
25#endif24#endif
26 of_clk_init(NULL);25 of_clk_init(NULL);
27 mmp_dt_init_timer();26 timer_probe();
28}27}
29 28
30static const char *const mmp2_dt_board_compat[] __initconst = {29static const char *const mmp2_dt_board_compat[] __initconst = {
@@ -33,7 +32,7 @@ static const char *const mmp2_dt_board_compat[] __initconst = { · 2 unmodified lines
33};32};
34 33
35DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")34DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
36 .map_io = mmp_map_io,35 .map_io = mmp2_map_io,
37 .init_time = mmp_init_time,36 .init_time = mmp_init_time,
38 .dt_compat = mmp2_dt_board_compat,37 .dt_compat = mmp2_dt_board_compat,
39MACHINE_END38MACHINE_END
arch/arm/mach-mmp/mmp2.c+1−1
@@ -20,7 +20,7 @@ · 19 unmodified lines
20#include <asm/mach/time.h>20#include <asm/mach/time.h>
21#include "addr-map.h"21#include "addr-map.h"
22#include "regs-apbc.h"22#include "regs-apbc.h"
23#include "cputype.h"23#include <linux/soc/mmp/cputype.h>
24#include "irqs.h"24#include "irqs.h"
25#include "mfp.h"25#include "mfp.h"
26#include "devices.h"26#include "devices.h"
arch/arm/mach-mmp/mmp3.c+29−0
@@ -0,0 +1,29 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Marvell MMP3 aka PXA2128 aka 88AP2128 support
4 *
5 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
6 */
7
8#include <linux/io.h>
9#include <linux/irqchip.h>
10#include <linux/of_platform.h>
11#include <linux/clk-provider.h>
12#include <asm/mach/arch.h>
13#include <asm/hardware/cache-l2x0.h>
14
15#include "common.h"
16
17static const char *const mmp3_dt_board_compat[] __initconst = {
18 "marvell,mmp3",
19 NULL,
20};
21
22DT_MACHINE_START(MMP2_DT, "Marvell MMP3")
23 .map_io = mmp2_map_io,
24 .dt_compat = mmp3_dt_board_compat,
25 .l2c_aux_val = 1 << L310_AUX_CTRL_FWA_SHIFT |
26 L310_AUX_CTRL_DATA_PREFETCH |
27 L310_AUX_CTRL_INSTR_PREFETCH,
28 .l2c_aux_mask = 0xc20fffff,
29MACHINE_END
arch/arm/mach-mmp/platsmp.c+32−0
@@ -0,0 +1,32 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
4 */
5#include <linux/io.h>
6#include <asm/smp_scu.h>
7#include <asm/smp.h>
8#include "addr-map.h"
9
10#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
11
12static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
13{
14 /*
15 * Apparently, the boot ROM on the second core spins on this
16 * register becoming non-zero and then jumps to the address written
17 * there. No IPIs involved.
18 */
19 __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
20 return 0;
21}
22
23static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
24{
25 scu_enable(SCU_VIRT_BASE);
26}
27
28static const struct smp_operations mmp3_smp_ops __initconst = {
29 .smp_prepare_cpus = mmp3_smp_prepare_cpus,
30 .smp_boot_secondary = mmp3_boot_secondary,
31};
32CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
arch/arm/mach-mmp/pm-mmp2.c+1−1
@@ -17,7 +17,7 @@ · 16 unmodified lines
17#include <linux/interrupt.h>17#include <linux/interrupt.h>
18#include <asm/mach-types.h>18#include <asm/mach-types.h>
19 19
20#include "cputype.h"20#include <linux/soc/mmp/cputype.h>
21#include "addr-map.h"21#include "addr-map.h"
22#include "pm-mmp2.h"22#include "pm-mmp2.h"
23#include "regs-icu.h"23#include "regs-icu.h"
arch/arm/mach-mmp/pm-pxa910.c+1−1
@@ -18,7 +18,7 @@ · 17 unmodified lines
18#include <asm/mach-types.h>18#include <asm/mach-types.h>
19#include <asm/outercache.h>19#include <asm/outercache.h>
20 20
21#include "cputype.h"21#include <linux/soc/mmp/cputype.h>
22#include "addr-map.h"22#include "addr-map.h"
23#include "pm-pxa910.h"23#include "pm-pxa910.h"
24#include "regs-icu.h"24#include "regs-icu.h"
arch/arm/mach-mmp/pxa168.c+1−1
@@ -21,7 +21,7 @@ · 20 unmodified lines
21#include "addr-map.h"21#include "addr-map.h"
22#include "clock.h"22#include "clock.h"
23#include "common.h"23#include "common.h"
24#include "cputype.h"24#include <linux/soc/mmp/cputype.h>
25#include "devices.h"25#include "devices.h"
26#include "irqs.h"26#include "irqs.h"
27#include "mfp.h"27#include "mfp.h"
arch/arm/mach-mmp/pxa910.c+1−1
@@ -18,7 +18,7 @@ · 17 unmodified lines
18#include <asm/mach/time.h>18#include <asm/mach/time.h>
19#include "addr-map.h"19#include "addr-map.h"
20#include "regs-apbc.h"20#include "regs-apbc.h"
21#include "cputype.h"21#include <linux/soc/mmp/cputype.h>
22#include "irqs.h"22#include "irqs.h"
23#include "mfp.h"23#include "mfp.h"
24#include "devices.h"24#include "devices.h"
arch/arm/mach-mmp/regs-usb.h+0−94
@@ -121,100 +121,6 @@ · 120 unmodified lines
121 121
122#define UTMI_OTG_ADDON_OTG_ON (1 << 0)122#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
123 123
124/* For MMP3 USB Phy */
125#define USB2_PLL_REG0 0x4
126#define USB2_PLL_REG1 0x8
127#define USB2_TX_REG0 0x10
128#define USB2_TX_REG1 0x14
129#define USB2_TX_REG2 0x18
130#define USB2_RX_REG0 0x20
131#define USB2_RX_REG1 0x24
132#define USB2_RX_REG2 0x28
133#define USB2_ANA_REG0 0x30
134#define USB2_ANA_REG1 0x34
135#define USB2_ANA_REG2 0x38
136#define USB2_DIG_REG0 0x3C
137#define USB2_DIG_REG1 0x40
138#define USB2_DIG_REG2 0x44
139#define USB2_DIG_REG3 0x48
140#define USB2_TEST_REG0 0x4C
141#define USB2_TEST_REG1 0x50
142#define USB2_TEST_REG2 0x54
143#define USB2_CHARGER_REG0 0x58
144#define USB2_OTG_REG0 0x5C
145#define USB2_PHY_MON0 0x60
146#define USB2_RESETVE_REG0 0x64
147#define USB2_ICID_REG0 0x78
148#define USB2_ICID_REG1 0x7C
149
150/* USB2_PLL_REG0 */
151/* This is for Ax stepping */
152#define USB2_PLL_FBDIV_SHIFT_MMP3 0
153#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
154
155#define USB2_PLL_REFDIV_SHIFT_MMP3 8
156#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
157
158#define USB2_PLL_VDD12_SHIFT_MMP3 12
159#define USB2_PLL_VDD18_SHIFT_MMP3 14
160
161/* This is for B0 stepping */
162#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
163#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
164#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
165#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
166#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
167
168#define USB2_PLL_CAL12_SHIFT_MMP3 0
169#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
170
171#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
172
173#define USB2_PLL_KVCO_SHIFT_MMP3 4
174#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
175
176#define USB2_PLL_ICP_SHIFT_MMP3 8
177#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
178
179#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
180
181#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
182#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
183
184#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
185
186/* USB2_TX_REG0 */
187#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
188#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
189
190#define USB2_TX_RCAL_START_SHIFT_MMP3 13
191
192/* USB2_TX_REG1 */
193#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
194#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
195
196#define USB2_TX_AMP_SHIFT_MMP3 4
197#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
198
199#define USB2_TX_VDD12_SHIFT_MMP3 8
200#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
201
202/* USB2_TX_REG2 */
203#define USB2_TX_DRV_SLEWRATE_SHIFT 10
204
205/* USB2_RX_REG0 */
206#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
207#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
208
209#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
210#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
211
212/* USB2_ANA_REG1*/
213#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
214
215/* USB2_OTG_REG0 */
216#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
217
218/* fsic registers */124/* fsic registers */
219#define FSIC_MISC 0x4125#define FSIC_MISC 0x4
220#define FSIC_INT 0x28126#define FSIC_INT 0x28
arch/arm/mach-mmp/time.c+14−29
@@ -33,7 +33,7 @@ · 32 unmodified lines
33#include "regs-timers.h"33#include "regs-timers.h"
34#include "regs-apbc.h"34#include "regs-apbc.h"
35#include "irqs.h"35#include "irqs.h"
36#include "cputype.h"36#include <linux/soc/mmp/cputype.h>
37#include "clock.h"37#include "clock.h"
38 38
39#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE39#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
@@ -155,7 +155,8 @@ static void __init timer_config(void) · 115 unmodified lines
155 155
156 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */156 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
157 157
158 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :158 ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
159 (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
159 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));160 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
160 __raw_writel(ccr, mmp_timer_base + TMR_CCR);161 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
161 162
@@ -195,30 +196,17 @@ void __init mmp_timer_init(int irq, unsigned long rate) · 33 unmodified lines
195 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);196 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
196}197}
197 198
198#ifdef CONFIG_OF199static int __init mmp_dt_init_timer(struct device_node *np)
199static const struct of_device_id mmp_timer_dt_ids[] = {
200 { .compatible = "mrvl,mmp-timer", },
201 {}
202};
203
204void __init mmp_dt_init_timer(void)
205{200{
206 struct device_node *np;
207 struct clk *clk;201 struct clk *clk;
208 int irq, ret;202 int irq, ret;
209 unsigned long rate;203 unsigned long rate;
210 204
211 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
212 if (!np) {
213 ret = -ENODEV;
214 goto out;
215 }
216
217 clk = of_clk_get(np, 0);205 clk = of_clk_get(np, 0);
218 if (!IS_ERR(clk)) {206 if (!IS_ERR(clk)) {
219 ret = clk_prepare_enable(clk);207 ret = clk_prepare_enable(clk);
220 if (ret)208 if (ret)
221 goto out;209 return ret;
222 rate = clk_get_rate(clk) / 2;210 rate = clk_get_rate(clk) / 2;
223 } else if (cpu_is_pj4()) {211 } else if (cpu_is_pj4()) {
224 rate = 6500000;212 rate = 6500000;
@@ -227,18 +215,15 @@ void __init mmp_dt_init_timer(void) · 2 unmodified lines
227 }215 }
228 216
229 irq = irq_of_parse_and_map(np, 0);217 irq = irq_of_parse_and_map(np, 0);
230 if (!irq) {218 if (!irq)
231 ret = -EINVAL;219 return -EINVAL;
232 goto out;220
233 }
234 mmp_timer_base = of_iomap(np, 0);221 mmp_timer_base = of_iomap(np, 0);
235 if (!mmp_timer_base) {222 if (!mmp_timer_base)
236 ret = -ENOMEM;223 return -ENOMEM;
237 goto out;224
238 }
239 mmp_timer_init(irq, rate);225 mmp_timer_init(irq, rate);
240 return;226 return 0;
241out:
242 pr_err("Failed to get timer from device tree with error:%d\n", ret);
243}227}
244#endif228
229TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
arch/arm/mm/Kconfig+1−1
@@ -1041,7 +1041,7 @@ endif · 1040 unmodified lines
1041 1041
1042config CACHE_TAUROS21042config CACHE_TAUROS2
1043 bool "Enable the Tauros2 L2 cache controller"1043 bool "Enable the Tauros2 L2 cache controller"
1044 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)1044 depends on (CPU_MOHAWK || CPU_PJ4)
1045 default y1045 default y
1046 select OUTER_CACHE1046 select OUTER_CACHE
1047 help1047 help
drivers/clk/Kconfig+5−0
@@ -292,6 +292,11 @@ config COMMON_CLK_STM32H7 · 291 unmodified lines
292 help292 help
293 Support for stm32h7 SoC family clocks293 Support for stm32h7 SoC family clocks
294 294
295config COMMON_CLK_MMP2
296 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
297 help
298 Support for Marvell MMP2 and MMP3 SoC clocks
299
295config COMMON_CLK_BD718XX300config COMMON_CLK_BD718XX
296 tristate "Clock driver for ROHM BD718x7 PMIC"301 tristate "Clock driver for ROHM BD718x7 PMIC"
297 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528302 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528
drivers/clk/mmp/Makefile+1−1
@@ -8,7 +8,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o · 7 unmodified lines
8obj-$(CONFIG_RESET_CONTROLLER) += reset.o8obj-$(CONFIG_RESET_CONTROLLER) += reset.o
9 9
10obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o10obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
11obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o11obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o
12 12
13obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o13obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
14obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o14obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
include/Kbuild+1−0
@@ -633,6 +633,7 @@ header-test- += linux/soc/amlogic/meson-canvas.h · 632 unmodified lines
633header-test- += linux/soc/brcmstb/brcmstb.h633header-test- += linux/soc/brcmstb/brcmstb.h
634header-test- += linux/soc/ixp4xx/npe.h634header-test- += linux/soc/ixp4xx/npe.h
635header-test- += linux/soc/mediatek/infracfg.h635header-test- += linux/soc/mediatek/infracfg.h
636header-test- += linux/soc/mmp/cputype.h
636header-test- += linux/soc/qcom/smd-rpm.h637header-test- += linux/soc/qcom/smd-rpm.h
637header-test- += linux/soc/qcom/smem.h638header-test- += linux/soc/qcom/smem.h
638header-test- += linux/soc/qcom/smem_state.h639header-test- += linux/soc/qcom/smem_state.h
include/linux/soc/mmp/cputype.hrenamed from arch/arm/mach-mmp/cputype.h+27−0
@@ -18,6 +18,8 @@ · 17 unmodified lines
18 * MMP2 Z0 0x560f5811 0x00F0041018 * MMP2 Z0 0x560f5811 0x00F00410
19 * MMP2 Z1 0x560f5811 0x00E0041019 * MMP2 Z1 0x560f5811 0x00E00410
20 * MMP2 A0 0x560f5811 0x00A0A61020 * MMP2 A0 0x560f5811 0x00A0A610
21 * MMP3 A0 0x562f5842 0x00A02128
22 * MMP3 B0 0x562f5842 0x00B02128
21 */23 */
22 24
23extern unsigned int mmp_chip_id;25extern unsigned int mmp_chip_id;
@@ -55,4 +57,29 @@ static inline int cpu_is_mmp2(void) · 31 unmodified lines
55#define cpu_is_mmp2() (0)57#define cpu_is_mmp2() (0)
56#endif58#endif
57 59
60#ifdef CONFIG_MACH_MMP3_DT
61static inline int cpu_is_mmp3(void)
62{
63 return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
64 ((mmp_chip_id & 0xffff) == 0x2128);
65}
66
67static inline int cpu_is_mmp3_a0(void)
68{
69 return (cpu_is_mmp3() &&
70 ((mmp_chip_id & 0x00ff0000) == 0x00a00000));
71}
72
73static inline int cpu_is_mmp3_b0(void)
74{
75 return (cpu_is_mmp3() &&
76 ((mmp_chip_id & 0x00ff0000) == 0x00b00000));
77}
78
79#else
80#define cpu_is_mmp3() (0)
81#define cpu_is_mmp3_a0() (0)
82#define cpu_is_mmp3_b0() (0)
83#endif
84
58#endif /* __ASM_MACH_CPUTYPE_H */85#endif /* __ASM_MACH_CPUTYPE_H */

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