PCI BAR IO memory should never be mapped as WB, however prior to this the PAT bits were set WB and it was typically overridden by MTRR registers set by the firmware. Set PCI P2PDMA memory to be UC as this is what it currently, typically, ends up being mapped as on x86 after the MTRR registers override the cache setting. Future use-cases may need to generalize this by adding flags to select the caching type, as some P2PDMA cases may not want UC. However, those use-cases are not upstream yet and this can be changed when they arrive.
Unified · Split
| @@ -217,7 +217,10 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid) · 216 unmodified lines | |||
| 217 | } | 217 | } |
| 218 | break; | 218 | break; |
| 219 | case MEMORY_DEVICE_DEVDAX: | 219 | case MEMORY_DEVICE_DEVDAX: |
| 220 | need_devmap_managed = false; | ||
| 221 | break; | ||
| 220 | case MEMORY_DEVICE_PCI_P2PDMA: | 222 | case MEMORY_DEVICE_PCI_P2PDMA: |
| 223 | params.pgprot = pgprot_noncached(params.pgprot); | ||
| 221 | need_devmap_managed = false; | 224 | need_devmap_managed = false; |
| 222 | break; | 225 | break; |
| 223 | default: | 226 | default: |