Pull dmaengine updates from Vinod Koul: "Here are the changes this time around, couple of new drivers and updates to few more: - New drivers for SiFive PDMA, Socionext Milbeaut HDMAC and XDMAC, Freescale dpaa2 qDMA - Support for X1000 in JZ4780 - Xilinx dma updates and support for Xilinx AXI MCDM controller - New bindings for rcar R8A774B1 - Minor updates to dw, dma-jz4780, ti-edma, sprd drivers" * tag 'dmaengine-5.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (61 commits) dmaengine: Fix Kconfig indentation dmaengine: sf-pdma: move macro to header file dmaengine: sf-pdma: replace /** with /* for non-function comment dmaengine: ti: edma: fix missed failure handling dmaengine: mmp_pdma: add missed of_dma_controller_free dmaengine: mmp_tdma: add missed of_dma_controller_free dmaengine: sprd: Add wrap address support for link-list mode MAINTAINERS: Add Green as SiFive PDMA driver maintainer dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA dmaengine: zx: remove: removed dmam_pool_destroy dmaengine: mediatek: hsdma_probe: fixed a memory leak when devm_request_irq fails dmaengine: iop-adma: clean up an indentation issue dmaengine: milbeaut-xdmac: remove redundant error log dmaengine: milbeaut-hdmac: remove redundant error log dmaengine: dma-jz4780: add missed clk_disable_unprepare in remove dmaengine: JZ4780: Add support for the X1000. dt-bindings: dmaengine: Add X1000 bindings. dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support dmaengine: xilinx_dma: Extend dma_config struct to store irq routine handle ...
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| @@ -118,6 +118,9 @@ enum sprd_dma_int_type { · 117 unmodified lines | |||
| 118 | * struct sprd_dma_linklist - DMA link-list address structure | 118 | * struct sprd_dma_linklist - DMA link-list address structure |
| 119 | * @virt_addr: link-list virtual address to configure link-list node | 119 | * @virt_addr: link-list virtual address to configure link-list node |
| 120 | * @phy_addr: link-list physical address to link DMA transfer | 120 | * @phy_addr: link-list physical address to link DMA transfer |
| 121 | * @wrap_addr: the wrap address for link-list mode, which means once the | ||
| 122 | * transfer address reaches the wrap address, the next transfer address | ||
| 123 | * will jump to the address specified by wrap_to register. | ||
| 121 | * | 124 | * |
| 122 | * The Spreadtrum DMA controller supports the link-list mode, that means slaves | 125 | * The Spreadtrum DMA controller supports the link-list mode, that means slaves |
| 123 | * can supply several groups configurations (each configuration represents one | 126 | * can supply several groups configurations (each configuration represents one |
| @@ -181,6 +184,7 @@ enum sprd_dma_int_type { · 57 unmodified lines | |||
| 181 | struct sprd_dma_linklist { | 184 | struct sprd_dma_linklist { |
| 182 | unsigned long virt_addr; | 185 | unsigned long virt_addr; |
| 183 | phys_addr_t phy_addr; | 186 | phys_addr_t phy_addr; |
| 187 | phys_addr_t wrap_addr; | ||
| 184 | }; | 188 | }; |
| 185 | 189 | ||
| 186 | #endif | 190 | #endif |