History

Merge tag 'drm-next-2022-12-13' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "The biggest highlight is that the accel subsystem framework is merged. Hopefully for 6.3 we will be able to line up a driver to use it. In drivers land, i915 enables DG2 support by default now, and nouveau has a big stability refactoring and initial ampere support, AMD includes new hw IP support and should build on ARM again. There is also an ofdrm driver to take over offb on platforms it's used. Stuff outside my tree, the dma-buf patches hit a few places, the vc4 firmware changes also do, and i915 has some interactions with MEI for discrete GPUs. I think all of those should have been acked/reviewed by relevant parties. New driver: - ofdrm - replacement for offb fbdev: - add support for nomodeset fourcc: - add Vivante tiled modifier core: - atomic-helpers: CRTC primary plane test fixes, fb access hooks - connector: TV API consistency, cmdline parser improvements - send connector hotplug on cleanup - sort makefile objects tests: - sort kunit tests - improve DP-MST tests - add kunit helpers to create a device sched: - module param for scheduling policy - refcounting fix buddy: - add back random seed log ttm: - convert ttm_resource to size_t - optimize pool allocations edid: - HFVSDB parsing support fixes - logging/debug improvements - DSC quirks dma-buf: - Add unlocked vmap and attachment mapping - move drivers to common locking convention - locking improvements firmware: - new API for rPI firmware and vc4 xilinx: - zynqmp: displayport bridge support - dpsub fix bridge: - adv7533: Remove dynamic lane switching - it6505: Runtime PM support, sync improvements - ps8640: Handle AUX defer messages - tc358775: Drop soft-reset over I2C panel: - panel-edp: Add INX N116BGE-EA2 C2 and C4 support. - Jadard JD9365DA-H3 - NewVision NV3051D amdgpu: - DCN support on ARM - DCN 2.1 secure display - Sienna Cichlid mode2 reset fixes - new GC 11.x firmware versions - drop AMD specific DSC workarounds in favour of drm code - clang warning fixes - scheduler rework - SR-IOV fixes - GPUVM locking fixes - fix memory leak in CS IOCTL error path - flexible array updates - enable new GC/PSP/SMU/NBIO IP - GFX preemption support for gfx9 amdkfd: - cache size fixes - userptr fixes - enable cooperative launch on gfx 10.3 - enable GC 11.0.4 KFD support radeon: - replace kmap with kmap_local_page - ACPI ref count fix - HDA audio notifier support i915: - DG2 enabled by default - MTL enablement work - hotplug refactoring - VBT improvements - Display and watermark refactoring - ADL-P workaround - temp disable runtime_pm for discrete- - fix for A380 as a secondary GPU - Wa_18017747507 for DG2 - CS timestamp support fixes for gen5 and earlier - never purge busy TTM objects - use i915_sg_dma_sizes for all backends - demote GuC kernel contexts to normal priority - gvt: refactor for new MDEV interface - enable DC power states on eDP ports - fix gen 2/3 workarounds nouveau: - fix page fault handling - Ampere acceleration support - driver stability improvements - nva3 backlight support msm: - MSM_INFO_GET_FLAGS support - DPU: XR30 and P010 image formats - Qualcomm SM6115 support - DSI PHY support for QCM2290 - HDMI: refactored dev init path - remove exclusive-fence hack - fix speed-bin detection - enable clamp to idle on 7c3 - improved hangcheck detection vmwgfx: - fb and cursor refactoring - convert to generic hashtable - cursor improvements etnaviv: - hw workarounds - softpin MMU fixes ast: - atomic gamma LUT support - convert to SHMEM lcdif: - support YUV planes - Increase DMA burst size - FIFO threshold tuning meson: - fix return type of cvbs mode_valid mgag200: - fix PLL setup on some revisions sun4i: - A100 and D1 support udl: - modesetting improvements - hot unplug support vc4: - support PAL-M - fix regression preventing 4K @ 60Hz - fix NULL ptr deref v3d: - switch to drm managed resources renesas: - RZ/G2L DSI support - DU Kconfig cleanup mediatek: - fixup dpi and hdmi - MT8188 dpi support - MT8195 AFBC support tegra: - NVDEC hardware on Tegra234 SoC hdlcd: - switch to drm managed resources ingenic: - fix registration error path hisilicon: - convert to drm_mode_init maildp: - use managed resources mtk: - use drm_mode_init rockchip: - use drm_mode_copy" * tag 'drm-next-2022-12-13' of git://anongit.freedesktop.org/drm/drm: (1397 commits) drm/amdgpu: fix mmhub register base coding error drm/amdgpu: add tmz support for GC IP v11.0.4 drm/amdgpu: enable GFX Clock Gating control for GC IP v11.0.4 drm/amdgpu: enable GFX Power Gating for GC IP v11.0.4 drm/amdgpu: enable GFX IP v11.0.4 CG support drm/amdgpu: Make amdgpu_ring_mux functions as static drm/amdgpu: generally allow over-commit during BO allocation drm/amd/display: fix array index out of bound error in DCN32 DML drm/amd/display: 3.2.215 drm/amd/display: set optimized required for comp buf changes drm/amd/display: Add debug option to skip PSR CRTC disable drm/amd/display: correct DML calc error of UrgentLatency drm/amd/display: correct static_screen_event_mask drm/amd/display: Ensure commit_streams returns the DC return code drm/amd/display: read invalid ddc pin status cause engine busy drm/amd/display: Bypass DET swath fill check for max clocks drm/amd/display: Disable uclk pstate for subvp pipes drm/amd/display: Fix DCN2.1 default DSC clocks drm/amd/display: Enable dp_hdmi21_pcon support drm/amd/display: prevent seamless boot on displays that don't have the preferred dig ...

Linus Torvalds committed 3 years ago

Commit a5945332 parents cdb9d35 66efff51498 files · +50470 −29875Browse files

Showing the changes to include/uapi (5 of 1498 files). Show all

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5 files
  1. include/uapi/drm/amdgpu_drm.h +14 −0
  2. include/uapi/drm/drm_fourcc.h +29 −0
  3. include/uapi/drm/drm_mode.h +62 −1
  4. include/uapi/drm/i915_drm.h +36 −26
  5. include/uapi/drm/msm_drm.h +1 −0
include/uapi/drm/amdgpu_drm.h+14−0
@@ -144,6 +144,20 @@ extern "C" { · 143 unmodified lines
144 * content.144 * content.
145 */145 */
146#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)146#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
147/* Flag that BO is shared coherently between multiple devices or CPU threads.
148 * May depend on GPU instructions to flush caches explicitly
149 *
150 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
151 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
152 */
153#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
154/* Flag that BO should not be cached by GPU. Coherent without having to flush
155 * GPU caches explicitly
156 *
157 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
158 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
159 */
160#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
147 161
148struct drm_amdgpu_gem_create_in {162struct drm_amdgpu_gem_create_in {
149 /** the requested memory size */163 /** the requested memory size */
include/uapi/drm/drm_fourcc.h+29−0
@@ -744,6 +744,35 @@ extern "C" { · 743 unmodified lines
744 */744 */
745#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)745#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
746 746
747/*
748 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
749 * the color buffer tiling modifiers defined above. When TS is present it's a
750 * separate buffer containing the clear/compression status of each tile. The
751 * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
752 * tile size in bytes covered by one entry in the status buffer and s is the
753 * number of status bits per entry.
754 * We reserve the top 8 bits of the Vivante modifier space for tile status
755 * clear/compression modifiers, as future cores might add some more TS layout
756 * variations.
757 */
758#define VIVANTE_MOD_TS_64_4 (1ULL << 48)
759#define VIVANTE_MOD_TS_64_2 (2ULL << 48)
760#define VIVANTE_MOD_TS_128_4 (3ULL << 48)
761#define VIVANTE_MOD_TS_256_4 (4ULL << 48)
762#define VIVANTE_MOD_TS_MASK (0xfULL << 48)
763
764/*
765 * Vivante compression modifiers. Those depend on a TS modifier being present
766 * as the TS bits get reinterpreted as compression tags instead of simple
767 * clear markers when compression is enabled.
768 */
769#define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)
770#define VIVANTE_MOD_COMP_MASK (0xfULL << 52)
771
772/* Masking out the extension bits will yield the base modifier. */
773#define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \
774 VIVANTE_MOD_COMP_MASK)
775
747/* NVIDIA frame buffer modifiers */776/* NVIDIA frame buffer modifiers */
748 777
749/*778/*
include/uapi/drm/drm_mode.h+62−1
@@ -935,12 +935,31 @@ struct hdr_output_metadata { · 934 unmodified lines
935 };935 };
936};936};
937 937
938/**
939 * DRM_MODE_PAGE_FLIP_EVENT
940 *
941 * Request that the kernel sends back a vblank event (see
942 * struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the
943 * page-flip is done.
944 */
938#define DRM_MODE_PAGE_FLIP_EVENT 0x01945#define DRM_MODE_PAGE_FLIP_EVENT 0x01
946/**
947 * DRM_MODE_PAGE_FLIP_ASYNC
948 *
949 * Request that the page-flip is performed as soon as possible, ie. with no
950 * delay due to waiting for vblank. This may cause tearing to be visible on
951 * the screen.
952 */
939#define DRM_MODE_PAGE_FLIP_ASYNC 0x02953#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
940#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4954#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
941#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8955#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
942#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \956#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
943 DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)957 DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
958/**
959 * DRM_MODE_PAGE_FLIP_FLAGS
960 *
961 * Bitmask of flags suitable for &drm_mode_crtc_page_flip_target.flags.
962 */
944#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \963#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
945 DRM_MODE_PAGE_FLIP_ASYNC | \964 DRM_MODE_PAGE_FLIP_ASYNC | \
946 DRM_MODE_PAGE_FLIP_TARGET)965 DRM_MODE_PAGE_FLIP_TARGET)
@@ -1034,11 +1053,53 @@ struct drm_mode_destroy_dumb { · 87 unmodified lines
1034 __u32 handle;1053 __u32 handle;
1035};1054};
1036 1055
1037/* page-flip flags are valid, plus: */1056/**
1057 * DRM_MODE_ATOMIC_TEST_ONLY
1058 *
1059 * Do not apply the atomic commit, instead check whether the hardware supports
1060 * this configuration.
1061 *
1062 * See &drm_mode_config_funcs.atomic_check for more details on test-only
1063 * commits.
1064 */
1038#define DRM_MODE_ATOMIC_TEST_ONLY 0x01001065#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
1066/**
1067 * DRM_MODE_ATOMIC_NONBLOCK
1068 *
1069 * Do not block while applying the atomic commit. The &DRM_IOCTL_MODE_ATOMIC
1070 * IOCTL returns immediately instead of waiting for the changes to be applied
1071 * in hardware. Note, the driver will still check that the update can be
1072 * applied before retuning.
1073 */
1039#define DRM_MODE_ATOMIC_NONBLOCK 0x02001074#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
1075/**
1076 * DRM_MODE_ATOMIC_ALLOW_MODESET
1077 *
1078 * Allow the update to result in temporary or transient visible artifacts while
1079 * the update is being applied. Applying the update may also take significantly
1080 * more time than a page flip. All visual artifacts will disappear by the time
1081 * the update is completed, as signalled through the vblank event's timestamp
1082 * (see struct drm_event_vblank).
1083 *
1084 * This flag must be set when the KMS update might cause visible artifacts.
1085 * Without this flag such KMS update will return a EINVAL error. What kind of
1086 * update may cause visible artifacts depends on the driver and the hardware.
1087 * User-space that needs to know beforehand if an update might cause visible
1088 * artifacts can use &DRM_MODE_ATOMIC_TEST_ONLY without
1089 * &DRM_MODE_ATOMIC_ALLOW_MODESET to see if it fails.
1090 *
1091 * To the best of the driver's knowledge, visual artifacts are guaranteed to
1092 * not appear when this flag is not set. Some sinks might display visual
1093 * artifacts outside of the driver's control.
1094 */
1040#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x04001095#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
1041 1096
1097/**
1098 * DRM_MODE_ATOMIC_FLAGS
1099 *
1100 * Bitfield of flags accepted by the &DRM_IOCTL_MODE_ATOMIC IOCTL in
1101 * &drm_mode_atomic.flags.
1102 */
1042#define DRM_MODE_ATOMIC_FLAGS (\1103#define DRM_MODE_ATOMIC_FLAGS (\
1043 DRM_MODE_PAGE_FLIP_EVENT |\1104 DRM_MODE_PAGE_FLIP_EVENT |\
1044 DRM_MODE_PAGE_FLIP_ASYNC |\1105 DRM_MODE_PAGE_FLIP_ASYNC |\
include/uapi/drm/i915_drm.h+36−26
@@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait { · 644 unmodified lines
645 */645 */
646#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)646#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
647 647
648/*
649 * Query the status of HuC load.
650 *
651 * The query can fail in the following scenarios with the listed error codes:
652 * -ENODEV if HuC is not present on this platform,
653 * -EOPNOTSUPP if HuC firmware usage is disabled,
654 * -ENOPKG if HuC firmware fetch failed,
655 * -ENOEXEC if HuC firmware is invalid or mismatched,
656 * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
657 * -EIO if the FW transfer or the FW authentication failed.
658 *
659 * If the IOCTL is successful, the returned parameter will be set to one of the
660 * following values:
661 * * 0 if HuC firmware load is not complete,
662 * * 1 if HuC firmware is authenticated and running.
663 */
648#define I915_PARAM_HUC_STATUS 42664#define I915_PARAM_HUC_STATUS 42
649 665
650/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of666/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
@@ -749,6 +765,12 @@ typedef struct drm_i915_irq_wait { · 98 unmodified lines
749/* Query if the kernel supports the I915_USERPTR_PROBE flag. */765/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
750#define I915_PARAM_HAS_USERPTR_PROBE 56766#define I915_PARAM_HAS_USERPTR_PROBE 56
751 767
768/*
769 * Frequency of the timestamps in OA reports. This used to be the same as the CS
770 * timestamp frequency, but differs on some platforms.
771 */
772#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
773
752/* Must be kept compact -- no holes and well documented */774/* Must be kept compact -- no holes and well documented */
753 775
754/**776/**
@@ -2650,6 +2672,10 @@ enum drm_i915_oa_format { · 1895 unmodified lines
2650 I915_OA_FORMAT_A12_B8_C8,2672 I915_OA_FORMAT_A12_B8_C8,
2651 I915_OA_FORMAT_A32u40_A4u32_B8_C8,2673 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
2652 2674
2675 /* DG2 */
2676 I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
2677 I915_OA_FORMAT_A24u40_A14u32_B8_C8,
2678
2653 I915_OA_FORMAT_MAX /* non-ABI */2679 I915_OA_FORMAT_MAX /* non-ABI */
2654};2680};
2655 2681
@@ -3493,27 +3519,13 @@ struct drm_i915_gem_create_ext { · 837 unmodified lines
3493 *3519 *
3494 * The (page-aligned) allocated size for the object will be returned.3520 * The (page-aligned) allocated size for the object will be returned.
3495 *3521 *
3496 * DG2 64K min page size implications:3522 * On platforms like DG2/ATS the kernel will always use 64K or larger
3497 *3523 * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
3498 * On discrete platforms, starting from DG2, we have to contend with GTT3524 * minimum of 64K GTT alignment for such objects.
3499 * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
3500 * objects. Specifically the hardware only supports 64K or larger GTT
3501 * page sizes for such memory. The kernel will already ensure that all
3502 * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
3503 * sizes underneath.
3504 *
3505 * Note that the returned size here will always reflect any required
3506 * rounding up done by the kernel, i.e 4K will now become 64K on devices
3507 * such as DG2. The kernel will always select the largest minimum
3508 * page-size for the set of possible placements as the value to use when
3509 * rounding up the @size.
3510 *
3511 * Special DG2 GTT address alignment requirement:
3512 *
3513 * The GTT alignment will also need to be at least 2M for such objects.
3514 *3525 *
3515 * Note that due to how the hardware implements 64K GTT page support, we3526 * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
3516 * have some further complications:3527 * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
3528 * where we had the following complications:
3517 *3529 *
3518 * 1) The entire PDE (which covers a 2MB virtual address range), must3530 * 1) The entire PDE (which covers a 2MB virtual address range), must
3519 * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same3531 * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
@@ -3522,12 +3534,10 @@ struct drm_i915_gem_create_ext { · 2 unmodified lines
3522 * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM3534 * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
3523 * objects.3535 * objects.
3524 *3536 *
3525 * To keep things simple for userland, we mandate that any GTT mappings3537 * However on actual production HW this was completely changed to now
3526 * must be aligned to and rounded up to 2MB. The kernel will internally3538 * allow setting a TLB hint at the PTE level (see PS64), which is a lot
3527 * pad them out to the next 2MB boundary. As this only wastes virtual3539 * more flexible than the above. With this the 2M restriction was
3528 * address space and avoids userland having to copy any needlessly3540 * dropped where we now only require 64K.
3529 * complicated PDE sharing scheme (coloring) and only affects DG2, this
3530 * is deemed to be a good compromise.
3531 */3541 */
3532 __u64 size;3542 __u64 size;
3533 3543
include/uapi/drm/msm_drm.h+1−0
@@ -138,6 +138,7 @@ struct drm_msm_gem_new { · 137 unmodified lines
138#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */138#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
139#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */139#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
140#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */140#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
141#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
141 142
142struct drm_msm_gem_info {143struct drm_msm_gem_info {
143 __u32 handle; /* in */144 __u32 handle; /* in */