History

tty/synclink: remove leftover bits of non-PCI card support

Since commit 1355cba9c3ba ("tty/synclink: remove ISA support"), the synlink driver only supports PCI card. Remove any leftover dead code to support other cards.

Christoph Hellwig committed 6 years ago

Commit a5e06911 parent a3241891 file · +109 −241Browse files

Unified · Split

drivers/tty/synclink.c+109−241
@@ -252,7 +252,6 @@ struct mgsl_struct { · 251 unmodified lines
252252
253253 char device_name[25]; /* device instance name */
254254
255− unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
256255 unsigned char bus; /* expansion bus number (zero based) */
257256 unsigned char function; /* PCI device number */
258257
@@ -3432,15 +3431,9 @@ static inline void line_info(struct seq_file *m, struct mgsl_struct *info) · 3173 unmodified lines
34323431 char stat_buf[30];
34333432 unsigned long flags;
34343433
3435− if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3436− seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3437− info->device_name, info->io_base, info->irq_level,
3438− info->phys_memory_base, info->phys_lcr_base);
3439− } else {
3440− seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3441− info->device_name, info->io_base,
3442− info->irq_level, info->dma_level);
3443− }
3434+ seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3435+ info->device_name, info->io_base, info->irq_level,
3436+ info->phys_memory_base, info->phys_lcr_base);
34443437
34453438 /* output current serial signal states */
34463439 spin_lock_irqsave(&info->irq_spinlock,flags);
@@ -3556,54 +3549,27 @@ static int mgsl_allocate_dma_buffers(struct mgsl_struct *info) · 109 unmodified lines
35563549 if ( info->max_frame_size % DMABUFFERSIZE )
35573550 BuffersPerFrame++;
35583551
3559− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3560− /*
3561− * The PCI adapter has 256KBytes of shared memory to use.
3562− * This is 64 PAGE_SIZE buffers.
3563− *
3564− * The first page is used for padding at this time so the
3565− * buffer list does not begin at offset 0 of the PCI
3566− * adapter's shared memory.
3567− *
3568− * The 2nd page is used for the buffer list. A 4K buffer
3569− * list can hold 128 DMA_BUFFER structures at 32 bytes
3570− * each.
3571− *
3572− * This leaves 62 4K pages.
3573− *
3574− * The next N pages are used for transmit frame(s). We
3575− * reserve enough 4K page blocks to hold the required
3576− * number of transmit dma buffers (num_tx_dma_buffers),
3577− * each of MaxFrameSize size.
3578− *
3579− * Of the remaining pages (62-N), determine how many can
3580− * be used to receive full MaxFrameSize inbound frames
3581− */
3582− info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3583− info->rx_buffer_count = 62 - info->tx_buffer_count;
3584− } else {
3585− /* Calculate the number of PAGE_SIZE buffers needed for */
3586− /* receive and transmit DMA buffers. */
3587−
3588−
3589− /* Calculate the number of DMA buffers necessary to */
3590− /* hold 7 max size receive frames and one max size transmit frame. */
3591− /* The receive buffer count is bumped by one so we avoid an */
3592− /* End of List condition if all receive buffers are used when */
3593− /* using linked list DMA buffers. */
3594−
3595− info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3596− info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3597−
3598− /*
3599− * limit total TxBuffers & RxBuffers to 62 4K total
3600− * (ala PCI Allocation)
3601− */
3602−
3603− if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3604− info->rx_buffer_count = 62 - info->tx_buffer_count;
3605−
3606− }
3552+ /*
3553+ * The PCI adapter has 256KBytes of shared memory to use. This is 64
3554+ * PAGE_SIZE buffers.
3555+ *
3556+ * The first page is used for padding at this time so the buffer list
3557+ * does not begin at offset 0 of the PCI adapter's shared memory.
3558+ *
3559+ * The 2nd page is used for the buffer list. A 4K buffer list can hold
3560+ * 128 DMA_BUFFER structures at 32 bytes each.
3561+ *
3562+ * This leaves 62 4K pages.
3563+ *
3564+ * The next N pages are used for transmit frame(s). We reserve enough
3565+ * 4K page blocks to hold the required number of transmit dma buffers
3566+ * (num_tx_dma_buffers), each of MaxFrameSize size.
3567+ *
3568+ * Of the remaining pages (62-N), determine how many can be used to
3569+ * receive full MaxFrameSize inbound frames
3570+ */
3571+ info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3572+ info->rx_buffer_count = 62 - info->tx_buffer_count;
36073573
36083574 if ( debug_level >= DEBUG_LEVEL_INFO )
36093575 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
@@ -3652,23 +3618,10 @@ static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info ) · 42 unmodified lines
36523618 {
36533619 unsigned int i;
36543620
3655− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3656− /* PCI adapter uses shared memory. */
3657− info->buffer_list = info->memory_base + info->last_mem_alloc;
3658− info->buffer_list_phys = info->last_mem_alloc;
3659− info->last_mem_alloc += BUFFERLISTSIZE;
3660− } else {
3661− /* ISA adapter uses system memory. */
3662− /* The buffer lists are allocated as a common buffer that both */
3663− /* the processor and adapter can access. This allows the driver to */
3664− /* inspect portions of the buffer while other portions are being */
3665− /* updated by the adapter using Bus Master DMA. */
3666−
3667− info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3668− if (info->buffer_list == NULL)
3669− return -ENOMEM;
3670− info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3671− }
3621+ /* PCI adapter uses shared memory. */
3622+ info->buffer_list = info->memory_base + info->last_mem_alloc;
3623+ info->buffer_list_phys = info->last_mem_alloc;
3624+ info->last_mem_alloc += BUFFERLISTSIZE;
36723625
36733626 /* We got the memory for the buffer entry lists. */
36743627 /* Initialize the memory block to all zeros. */
@@ -3734,9 +3687,6 @@ static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info ) · 59 unmodified lines
37343687 */
37353688 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
37363689 {
3737− if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3738− dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3739−
37403690 info->buffer_list = NULL;
37413691 info->rx_buffer_list = NULL;
37423692 info->tx_buffer_list = NULL;
@@ -3762,24 +3712,13 @@ static void mgsl_free_buffer_list_memory( struct mgsl_struct *info ) · 19 unmodified lines
37623712 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
37633713 {
37643714 int i;
3765− u32 phys_addr;
37663715
37673716 /* Allocate page sized buffers for the receive buffer list */
37683717
37693718 for ( i = 0; i < Buffercount; i++ ) {
3770− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3771− /* PCI adapter uses shared memory buffers. */
3772− BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3773− phys_addr = info->last_mem_alloc;
3774− info->last_mem_alloc += DMABUFFERSIZE;
3775− } else {
3776− /* ISA adapter uses system memory. */
3777− BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3778− if (BufferList[i].virt_addr == NULL)
3779− return -ENOMEM;
3780− phys_addr = (u32)(BufferList[i].dma_addr);
3781− }
3782− BufferList[i].phys_addr = phys_addr;
3719+ BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3720+ BufferList[i].phys_addr = info->last_mem_alloc;
3721+ info->last_mem_alloc += DMABUFFERSIZE;
37833722 }
37843723
37853724 return 0;
@@ -3807,8 +3746,6 @@ static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *Buf · 21 unmodified lines
38073746 if ( BufferList ) {
38083747 for ( i = 0 ; i < Buffercount ; i++ ) {
38093748 if ( BufferList[i].virt_addr ) {
3810− if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3811− dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
38123749 BufferList[i].virt_addr = NULL;
38133750 }
38143751 }
@@ -4040,58 +3977,40 @@ static int mgsl_claim_resources(struct mgsl_struct *info) · 225 unmodified lines
40403977 }
40413978 info->irq_requested = true;
40423979
4043− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4044− if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4045− printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4046− __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4047− goto errout;
4048− }
4049− info->shared_mem_requested = true;
4050− if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4051− printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4052− __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4053− goto errout;
4054− }
4055− info->lcr_mem_requested = true;
4056−
4057− info->memory_base = ioremap(info->phys_memory_base,
4058− 0x40000);
4059− if (!info->memory_base) {
4060− printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4061− __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4062− goto errout;
4063− }
4064−
4065− if ( !mgsl_memory_test(info) ) {
4066− printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4067− __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4068− goto errout;
4069− }
4070−
4071− info->lcr_base = ioremap(info->phys_lcr_base,
4072− PAGE_SIZE);
4073− if (!info->lcr_base) {
4074− printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4075− __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4076− goto errout;
4077− }
4078− info->lcr_base += info->lcr_offset;
3980+ if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
3981+ printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
3982+ __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3983+ goto errout;
3984+ }
3985+ info->shared_mem_requested = true;
3986+ if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
3987+ printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
3988+ __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
3989+ goto errout;
3990+ }
3991+ info->lcr_mem_requested = true;
3992+
3993+ info->memory_base = ioremap(info->phys_memory_base, 0x40000);
3994+ if (!info->memory_base) {
3995+ printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
3996+ __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3997+ goto errout;
3998+ }
40793999
4080− } else {
4081− /* claim DMA channel */
4000+ if ( !mgsl_memory_test(info) ) {
4001+ printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4002+ __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4003+ goto errout;
4004+ }
40824005
4083− if (request_dma(info->dma_level,info->device_name) < 0){
4084− printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4085− __FILE__,__LINE__,info->device_name, info->dma_level );
4086− goto errout;
4087− }
4088− info->dma_requested = true;
4089−
4090− /* ISA adapter uses bus master DMA */
4091− set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4092− enable_dma(info->dma_level);
4006+ info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE);
4007+ if (!info->lcr_base) {
4008+ printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4009+ __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4010+ goto errout;
40934011 }
4094−
4012+ info->lcr_base += info->lcr_offset;
4013+
40954014 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
40964015 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
40974016 __FILE__,__LINE__,info->device_name, info->dma_level );
@@ -4200,16 +4119,10 @@ static void mgsl_add_device( struct mgsl_struct *info ) · 102 unmodified lines
42004119 else if ( info->max_frame_size > 65535 )
42014120 info->max_frame_size = 65535;
42024121
4203− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4204− printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4205− info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4206− info->phys_memory_base, info->phys_lcr_base,
4207− info->max_frame_size );
4208− } else {
4209− printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4210− info->device_name, info->io_base, info->irq_level, info->dma_level,
4211− info->max_frame_size );
4212− }
4122+ printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4123+ info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4124+ info->phys_memory_base, info->phys_lcr_base,
4125+ info->max_frame_size );
42134126
42144127 #if SYNCLINK_GENERIC_HDLC
42154128 hdlcdev_init(info);
@@ -4420,8 +4333,7 @@ static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd ) · 204 unmodified lines
44204333 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
44214334
44224335 /* Read to flush write to CCAR */
4423− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4424− inw( info->io_base + CCAR );
4336+ inw( info->io_base + CCAR );
44254337
44264338 } /* end of usc_RTCmd() */
44274339
@@ -4445,8 +4357,7 @@ static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd ) · 17 unmodified lines
44454357 outw( Cmd + info->mbre_bit, info->io_base );
44464358
44474359 /* Read to flush write to DCAR */
4448− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4449− inw( info->io_base );
4360+ inw( info->io_base );
44504361
44514362 } /* end of usc_DmaCmd() */
44524363
@@ -4475,8 +4386,7 @@ static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) · 22 unmodified lines
44754386 outw( RegValue, info->io_base );
44764387
44774388 /* Read to flush write to DCAR */
4478− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4479− inw( info->io_base );
4389+ inw( info->io_base );
44804390
44814391 } /* end of usc_OutDmaReg() */
44824392
@@ -4528,8 +4438,7 @@ static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) · 45 unmodified lines
45284438 outw( RegValue, info->io_base + CCAR );
45294439
45304440 /* Read to flush write to CCAR */
4531− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4532− inw( info->io_base + CCAR );
4441+ inw( info->io_base + CCAR );
45334442
45344443 } /* end of usc_OutReg() */
45354444
@@ -4728,10 +4637,7 @@ static void usc_set_sdlc_mode( struct mgsl_struct *info ) · 192 unmodified lines
47284637
47294638 RegValue = usc_InReg( info, RICR ) & 0xc0;
47304639
4731− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4732− usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4733− else
4734− usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4640+ usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
47354641
47364642 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
47374643
@@ -4792,10 +4698,7 @@ static void usc_set_sdlc_mode( struct mgsl_struct *info ) · 54 unmodified lines
47924698 * 0000 0000 0011 0110 = 0x0036
47934699 */
47944700
4795− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4796− usc_OutReg( info, TICR, 0x0736 );
4797− else
4798− usc_OutReg( info, TICR, 0x1436 );
4701+ usc_OutReg( info, TICR, 0x0736 );
47994702
48004703 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
48014704 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
@@ -4885,10 +4788,7 @@ static void usc_set_sdlc_mode( struct mgsl_struct *info ) · 83 unmodified lines
48854788 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
48864789 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
48874790
4888− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4889− XtalSpeed = 11059200;
4890− else
4891− XtalSpeed = 14745600;
4791+ XtalSpeed = 11059200;
48924792
48934793 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
48944794 DpllDivisor = 16;
@@ -5011,13 +4911,8 @@ static void usc_set_sdlc_mode( struct mgsl_struct *info ) · 116 unmodified lines
50114911 * 0110 0000 0000 1011 = 0x600b
50124912 */
50134913
5014− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5015− /* PCI adapter does not need DMA wait state */
5016− usc_OutDmaReg( info, DCR, 0xa00b );
5017− }
5018− else
5019− usc_OutDmaReg( info, DCR, 0x800b );
5020−
4914+ /* PCI adapter does not need DMA wait state */
4915+ usc_OutDmaReg( info, DCR, 0xa00b );
50214916
50224917 /* Receive DMA mode Register (RDMR)
50234918 *
@@ -5109,12 +5004,8 @@ static void usc_set_sdlc_mode( struct mgsl_struct *info ) · 85 unmodified lines
51095004 * <7..0> 0x00 Maximum number of clock cycles per bus grant
51105005 */
51115006
5112− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5113− /* don't limit bus occupancy on PCI adapter */
5114− usc_OutDmaReg( info, BDCR, 0x0000 );
5115− }
5116− else
5117− usc_OutDmaReg( info, BDCR, 0x2000 );
5007+ /* don't limit bus occupancy on PCI adapter */
5008+ usc_OutDmaReg( info, BDCR, 0x0000 );
51185009
51195010 usc_stop_transmitter(info);
51205011 usc_stop_receiver(info);
@@ -5155,10 +5046,7 @@ static void usc_enable_loopback(struct mgsl_struct *info, int enable) · 34 unmodified lines
51555046 /* Write 16-bit Time Constant for BRG0 */
51565047 /* use clock speed if available, otherwise use 8 for diagnostics */
51575048 if (info->params.clock_speed) {
5158− if (info->bus_type == MGSL_BUS_TYPE_PCI)
5159− usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5160− else
5161− usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5049+ usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
51625050 } else
51635051 usc_OutReg(info, TC0R, (u16)8);
51645052
@@ -5201,10 +5089,7 @@ static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate ) · 36 unmodified lines
52015089 u16 Tc;
52025090
52035091 if ( data_rate ) {
5204− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5205− XtalSpeed = 11059200;
5206− else
5207− XtalSpeed = 14745600;
5092+ XtalSpeed = 11059200;
52085093
52095094
52105095 /* Tc = (Xtal/Speed) - 1 */
@@ -5682,44 +5567,38 @@ static void usc_load_txfifo( struct mgsl_struct *info ) · 471 unmodified lines
56825567 */
56835568 static void usc_reset( struct mgsl_struct *info )
56845569 {
5685− if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5686− int i;
5687− u32 readval;
5570+ int i;
5571+ u32 readval;
56885572
5689− /* Set BIT30 of Misc Control Register */
5690− /* (Local Control Register 0x50) to force reset of USC. */
5573+ /* Set BIT30 of Misc Control Register */
5574+ /* (Local Control Register 0x50) to force reset of USC. */
56915575
5692− volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5693− u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5576+ volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5577+ u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
56945578
5695− info->misc_ctrl_value |= BIT30;
5696− *MiscCtrl = info->misc_ctrl_value;
5579+ info->misc_ctrl_value |= BIT30;
5580+ *MiscCtrl = info->misc_ctrl_value;
56975581
5698− /*
5699− * Force at least 170ns delay before clearing
5700− * reset bit. Each read from LCR takes at least
5701− * 30ns so 10 times for 300ns to be safe.
5702− */
5703− for(i=0;i<10;i++)
5704− readval = *MiscCtrl;
5705−
5706− info->misc_ctrl_value &= ~BIT30;
5707− *MiscCtrl = info->misc_ctrl_value;
5708−
5709− *LCR0BRDR = BUS_DESCRIPTOR(
5710− 1, // Write Strobe Hold (0-3)
5711− 2, // Write Strobe Delay (0-3)
5712− 2, // Read Strobe Delay (0-3)
5713− 0, // NWDD (Write data-data) (0-3)
5714− 4, // NWAD (Write Addr-data) (0-31)
5715− 0, // NXDA (Read/Write Data-Addr) (0-3)
5716− 0, // NRDD (Read Data-Data) (0-3)
5717− 5 // NRAD (Read Addr-Data) (0-31)
5718− );
5719− } else {
5720− /* do HW reset */
5721− outb( 0,info->io_base + 8 );
5722− }
5582+ /*
5583+ * Force at least 170ns delay before clearing reset bit. Each read from
5584+ * LCR takes at least 30ns so 10 times for 300ns to be safe.
5585+ */
5586+ for(i=0;i<10;i++)
5587+ readval = *MiscCtrl;
5588+
5589+ info->misc_ctrl_value &= ~BIT30;
5590+ *MiscCtrl = info->misc_ctrl_value;
5591+
5592+ *LCR0BRDR = BUS_DESCRIPTOR(
5593+ 1, // Write Strobe Hold (0-3)
5594+ 2, // Write Strobe Delay (0-3)
5595+ 2, // Read Strobe Delay (0-3)
5596+ 0, // NWDD (Write data-data) (0-3)
5597+ 4, // NWAD (Write Addr-data) (0-31)
5598+ 0, // NXDA (Read/Write Data-Addr) (0-3)
5599+ 0, // NRDD (Read Data-Data) (0-3)
5600+ 5 // NRAD (Read Addr-Data) (0-31)
5601+ );
57235602
57245603 info->mbre_bit = 0;
57255604 info->loopback_bits = 0;
@@ -6228,11 +6107,7 @@ static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate ) · 502 unmodified lines
62286107 * ClkSpeed = 921600 (ISA), 691200 (PCI)
62296108 */
62306109
6231− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6232− usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6233− else
6234− usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6235−
6110+ usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
62366111
62376112 /*
62386113 * Hardware Configuration Register (HCR)
@@ -6837,10 +6712,7 @@ static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, · 598 unmodified lines
68376712
68386713 /* Actually copy data from source buffer to DMA buffer. */
68396714 /* Also set the data count for this individual DMA buffer. */
6840− if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6841− mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6842− else
6843− memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6715+ mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
68446716
68456717 pBufEntry->count = Copycount;
68466718
@@ -7315,9 +7187,6 @@ static bool mgsl_memory_test( struct mgsl_struct *info ) · 468 unmodified lines
73157187 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
73167188 unsigned long * TestAddr;
73177189
7318− if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7319− return true;
7320−
73217190 TestAddr = (unsigned long *)info->memory_base;
73227191
73237192 /* Test data lines with test pattern at one location. */
@@ -8003,7 +7872,6 @@ static int synclink_init_one (struct pci_dev *dev, · 679 unmodified lines
80037872 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
80047873 info->phys_lcr_base &= ~(PAGE_SIZE-1);
80057874
8006− info->bus_type = MGSL_BUS_TYPE_PCI;
80077875 info->io_addr_size = 8;
80087876 info->irq_flags = IRQF_SHARED;
80097877