History

Merge tag 'amd-drm-next-6.20-2026-01-30' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.20-2026-01-30: amdgpu: - Misc cleanups - SMU 13 fixes - SMU 14 fixes - GPUVM fault filter fix - USB4 fixes - DC FP guard fixes - Powergating fix - JPEG ring reset fix - RAS fixes - Xclk fix for soc21 APUs - Fix COND_EXEC handling for GC 11 - UserQ fixes - MQD size alignment fixes - SMU feature interface cleanup - GC 10-12 KGQ init fixes - GC 11-12 KGQ reset fixes amdkfd: - Fix device snapshot reporting - GC 12.1 trap handler fixes - MQD size alignment fixes Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 9 months ago

Commit a60f6272 parents 502d2d8 0a6d6ed75 files · +743 −576Browse files

Unified · Split

75 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu.h +8 −0
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +3 −5
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +10 −8
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +6 −1
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +3 −2
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +0 −9
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +0 −3
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +4 −0
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +11 −0
  10. drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +1 −1
  11. drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +14 −11
  12. drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +14 −11
  13. drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +13 −14
  14. drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +2 −1
  15. drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +3 −15
  16. drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +3 −15
  17. drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +3 −14
  18. drivers/gpu/drm/amd/amdgpu/soc21.c +7 −1
  19. drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +1 −1
  20. drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +103 −94
  21. drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +18 −7
  22. drivers/gpu/drm/amd/amdkfd/kfd_debug.c +1 −0
  23. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +2 −2
  24. drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +1 −1
  25. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +7 −2
  26. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +3 −3
  27. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +2 −1
  28. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +2 −1
  29. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +6 −19
  30. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +6 −7
  31. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +8 −24
  32. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +2 −1
  33. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +2 −1
  34. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 −1
  35. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +2 −2
  36. drivers/gpu/drm/amd/display/dc/core/dc.c +1 −1
  37. drivers/gpu/drm/amd/display/dc/core/dc_stream.c +13 −0
  38. drivers/gpu/drm/amd/display/dc/dc.h +2 −1
  39. drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +18 −0
  40. drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +4 −0
  41. drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +2 −3
  42. drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h +2 −0
  43. drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +12 −4
  44. drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +1 −0
  45. drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +1 −0
  46. drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +1 −0
  47. drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +1 −0
  48. drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +0 −2
  49. drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +0 −2
  50. drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +1 −1
  51. drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +2 −0
  52. drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +49 −6
  53. drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +3 −0
  54. drivers/gpu/drm/amd/display/include/dpcd_defs.h +1 −0
  55. drivers/gpu/drm/amd/include/mes_v12_api_def.h +4 −2
  56. drivers/gpu/drm/amd/pm/amdgpu_dpm.c +4 −3
  57. drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +11 −25
  58. drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +169 −6
  59. drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +1 −0
  60. drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +1 −0
  61. drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +3 −8
  62. drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +43 −49
  63. drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +43 −46
  64. drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +3 −2
  65. drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +3 −8
  66. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +3 −2
  67. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +15 −20
  68. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +3 −9
  69. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +38 −42
  70. drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +3 −2
  71. drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +3 −47
  72. drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +2 −2
  73. drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +2 −4
  74. drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +1 −1
  75. include/uapi/linux/kfd_ioctl.h +2 −0
drivers/gpu/drm/amd/amdgpu/amdgpu.h+8−0
@@ -1239,6 +1239,14 @@ struct amdgpu_device { · 1238 unmodified lines
12391239 struct amdgpu_kfd_dev kfd;
12401240 };
12411241
1242+/*
1243+ * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t))
1244+ * as fence address and writes a 32 bit fence value to this address.
1245+ * Driver needs to allocate at least 4 DWs extra memory in addition to
1246+ * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety.
1247+ */
1248+#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))
1249+
12421250 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
12431251 uint8_t ip, uint8_t inst)
12441252 {
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c+3−5
@@ -60,11 +60,9 @@ static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b) · 59 unmodified lines
6060 {
6161 const struct amdgpu_bo_list_entry *a = _a, *b = _b;
6262
63− if (a->priority > b->priority)
64− return 1;
65− if (a->priority < b->priority)
66− return -1;
67− return 0;
63+ BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX);
64+
65+ return (int)a->priority - (int)b->priority;
6866 }
6967
7068 int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+10−8
@@ -385,6 +385,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, · 384 unmodified lines
385385 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
386386 struct amdgpu_ring *ring = &kiq->ring;
387387 u32 domain = AMDGPU_GEM_DOMAIN_GTT;
388+ u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size);
389+ u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size);
388390
389391 #if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
390392 /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
@@ -424,17 +426,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, · 33 unmodified lines
424426 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
425427 ring = &adev->gfx.gfx_ring[i];
426428 if (!ring->mqd_obj) {
427− r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
428− domain, &ring->mqd_obj,
429+ r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size),
430+ PAGE_SIZE, domain, &ring->mqd_obj,
429431 &ring->mqd_gpu_addr, &ring->mqd_ptr);
430432 if (r) {
431433 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
432434 return r;
433435 }
434436
435− ring->mqd_size = mqd_size;
437+ ring->mqd_size = gfx_mqd_size;
436438 /* prepare MQD backup */
437− adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL);
439+ adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL);
438440 if (!adev->gfx.me.mqd_backup[i]) {
439441 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
440442 return -ENOMEM;
@@ -448,17 +450,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, · 7 unmodified lines
448450 j = i + xcc_id * adev->gfx.num_compute_rings;
449451 ring = &adev->gfx.compute_ring[j];
450452 if (!ring->mqd_obj) {
451− r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
452− domain, &ring->mqd_obj,
453+ r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size),
454+ PAGE_SIZE, domain, &ring->mqd_obj,
453455 &ring->mqd_gpu_addr, &ring->mqd_ptr);
454456 if (r) {
455457 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
456458 return r;
457459 }
458460
459− ring->mqd_size = mqd_size;
461+ ring->mqd_size = compute_mqd_size;
460462 /* prepare MQD backup */
461− adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL);
463+ adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL);
462464 if (!adev->gfx.mec.mqd_backup[j]) {
463465 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
464466 return -ENOMEM;
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+6−1
@@ -498,8 +498,13 @@ void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, · 497 unmodified lines
498498
499499 if (adev->irq.retry_cam_enabled)
500500 return;
501+ else if (adev->irq.ih1.ring_size)
502+ ih = &adev->irq.ih1;
503+ else if (adev->irq.ih_soft.enabled)
504+ ih = &adev->irq.ih_soft;
505+ else
506+ return;
501507
502− ih = &adev->irq.ih1;
503508 /* Get the WPTR of the last entry in IH ring */
504509 last_wptr = amdgpu_ih_get_wptr(adev, ih);
505510 /* Order wptr with ring data. */
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c+3−2
@@ -235,7 +235,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, · 234 unmodified lines
235235
236236 amdgpu_ring_ib_begin(ring);
237237
238− if (ring->funcs->emit_gfx_shadow)
238+ if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow)
239239 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
240240 init_shadow, vmid);
241241
@@ -291,7 +291,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, · 49 unmodified lines
291291 fence_flags | AMDGPU_FENCE_FLAG_64BIT);
292292 }
293293
294− if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) {
294+ if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec &&
295+ adev->gfx.cp_gfx_shadow) {
295296 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
296297 amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);
297298 }
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c+0−9
@@ -115,9 +115,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) · 114 unmodified lines
115115
116116 adev->mes.adev = adev;
117117
118− idr_init(&adev->mes.pasid_idr);
119− idr_init(&adev->mes.gang_id_idr);
120− idr_init(&adev->mes.queue_id_idr);
121118 ida_init(&adev->mes.doorbell_ida);
122119 spin_lock_init(&adev->mes.queue_id_lock);
123120 mutex_init(&adev->mes.mutex_hidden);
@@ -252,9 +249,6 @@ error: · 128 unmodified lines
252249 &adev->mes.hung_queue_db_array_cpu_addr[i]);
253250 }
254251
255− idr_destroy(&adev->mes.pasid_idr);
256− idr_destroy(&adev->mes.gang_id_idr);
257− idr_destroy(&adev->mes.queue_id_idr);
258252 ida_destroy(&adev->mes.doorbell_ida);
259253 mutex_destroy(&adev->mes.mutex_hidden);
260254 return r;
@@ -283,9 +277,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) · 22 unmodified lines
283277
284278 amdgpu_mes_doorbell_free(adev);
285279
286− idr_destroy(&adev->mes.pasid_idr);
287− idr_destroy(&adev->mes.gang_id_idr);
288− idr_destroy(&adev->mes.queue_id_idr);
289280 ida_destroy(&adev->mes.doorbell_ida);
290281 mutex_destroy(&adev->mes.mutex_hidden);
291282 }
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h+0−3
@@ -77,9 +77,6 @@ struct amdgpu_mes { · 76 unmodified lines
7777
7878 struct mutex mutex_hidden;
7979
80− struct idr pasid_idr;
81− struct idr gang_id_idr;
82− struct idr queue_id_idr;
8380 struct ida doorbell_ida;
8481
8582 spinlock_t queue_id_lock;
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+4−0
@@ -1712,6 +1712,10 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) · 1711 unmodified lines
17121712 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
17131713 control->ras_num_bad_pages,
17141714 ras->bad_page_cnt_threshold);
1715+ if (amdgpu_bad_page_threshold != 0 &&
1716+ control->ras_num_bad_pages >= ras->bad_page_cnt_threshold)
1717+ amdgpu_dpm_send_rma_reason(adev);
1718+
17151719 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
17161720 amdgpu_bad_page_threshold != 0) {
17171721 if (hdr->version >= RAS_TABLE_VER_V2_1) {
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c+11−0
@@ -932,6 +932,17 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, · 931 unmodified lines
932932 drm_file_err(filp, "invalidate userq queue va or size\n");
933933 return -EINVAL;
934934 }
935+
936+ if (!is_power_of_2(args->in.queue_size)) {
937+ drm_file_err(filp, "Queue size must be a power of 2\n");
938+ return -EINVAL;
939+ }
940+
941+ if (args->in.queue_size < AMDGPU_GPU_PAGE_SIZE) {
942+ drm_file_err(filp, "Queue size smaller than AMDGPU_GPU_PAGE_SIZE\n");
943+ return -EINVAL;
944+ }
945+
935946 if (!args->in.wptr_va || !args->in.rptr_va) {
936947 drm_file_err(filp, "invalidate userq queue rptr or wptr\n");
937948 return -EINVAL;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+1−1
@@ -6880,7 +6880,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) · 6879 unmodified lines
68806880 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
68816881 /* reset the ring */
68826882 ring->wptr = 0;
6883− *ring->wptr_cpu_addr = 0;
6883+ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
68846884 amdgpu_ring_clear_ring(ring);
68856885 }
68866886
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+14−11
@@ -4214,7 +4214,7 @@ static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) · 4213 unmodified lines
42144214 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
42154215 /* reset the ring */
42164216 ring->wptr = 0;
4217− *ring->wptr_cpu_addr = 0;
4217+ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
42184218 amdgpu_ring_clear_ring(ring);
42194219 }
42204220
@@ -6828,11 +6828,12 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, · 2607 unmodified lines
68286828 struct amdgpu_fence *timedout_fence)
68296829 {
68306830 struct amdgpu_device *adev = ring->adev;
6831+ bool use_mmio = false;
68316832 int r;
68326833
68336834 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
68346835
6835− r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0);
6836+ r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0);
68366837 if (r) {
68376838
68386839 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
@@ -6841,16 +6842,18 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, · 2 unmodified lines
68416842 return r;
68426843 }
68436844
6844− r = gfx_v11_0_kgq_init_queue(ring, true);
6845− if (r) {
6846− dev_err(adev->dev, "failed to init kgq\n");
6847− return r;
6848− }
6845+ if (use_mmio) {
6846+ r = gfx_v11_0_kgq_init_queue(ring, true);
6847+ if (r) {
6848+ dev_err(adev->dev, "failed to init kgq\n");
6849+ return r;
6850+ }
68496851
6850− r = amdgpu_mes_map_legacy_queue(adev, ring, 0);
6851− if (r) {
6852− dev_err(adev->dev, "failed to remap kgq\n");
6853− return r;
6852+ r = amdgpu_mes_map_legacy_queue(adev, ring, 0);
6853+ if (r) {
6854+ dev_err(adev->dev, "failed to remap kgq\n");
6855+ return r;
6856+ }
68546857 }
68556858
68566859 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c+14−11
@@ -3085,7 +3085,7 @@ static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) · 3084 unmodified lines
30853085 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
30863086 /* reset the ring */
30873087 ring->wptr = 0;
3088− *ring->wptr_cpu_addr = 0;
3088+ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
30893089 amdgpu_ring_clear_ring(ring);
30903090 }
30913091
@@ -5292,11 +5292,12 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, · 2200 unmodified lines
52925292 struct amdgpu_fence *timedout_fence)
52935293 {
52945294 struct amdgpu_device *adev = ring->adev;
5295+ bool use_mmio = false;
52955296 int r;
52965297
52975298 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
52985299
5299− r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0);
5300+ r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0);
53005301 if (r) {
53015302 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
53025303 r = gfx_v12_reset_gfx_pipe(ring);
@@ -5304,16 +5305,18 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, · 1 unmodified line
53045305 return r;
53055306 }
53065307
5307− r = gfx_v12_0_kgq_init_queue(ring, true);
5308− if (r) {
5309− dev_err(adev->dev, "failed to init kgq\n");
5310− return r;
5311− }
5308+ if (use_mmio) {
5309+ r = gfx_v12_0_kgq_init_queue(ring, true);
5310+ if (r) {
5311+ dev_err(adev->dev, "failed to init kgq\n");
5312+ return r;
5313+ }
53125314
5313− r = amdgpu_mes_map_legacy_queue(adev, ring, 0);
5314− if (r) {
5315− dev_err(adev->dev, "failed to remap kgq\n");
5316− return r;
5315+ r = amdgpu_mes_map_legacy_queue(adev, ring, 0);
5316+ if (r) {
5317+ dev_err(adev->dev, "failed to remap kgq\n");
5318+ return r;
5319+ }
53175320 }
53185321
53195322 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c+13−14
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 #include "amdgpu_psp.h"
3131 #include "amdgpu_smu.h"
3232 #include "amdgpu_atomfirmware.h"
33+#include "amdgpu_userq_fence.h"
3334 #include "imu_v12_1.h"
3435 #include "soc_v1_0.h"
3536 #include "gfx_v12_1_pkt.h"
@@ -2235,7 +2236,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, · 2199 unmodified lines
22352236 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
22362237
22372238 mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size :
2238− sizeof(struct v12_1_compute_mqd);
2239+ AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size);
22392240
22402241 mqd->cp_hqd_active = prop->hqd_active;
22412242
@@ -3602,25 +3603,23 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, · 1360 unmodified lines
36023603 struct amdgpu_irq_src *source,
36033604 struct amdgpu_iv_entry *entry)
36043605 {
3605− int i, xcc_id;
3606+ u32 doorbell_offset = entry->src_data[0];
36063607 u8 me_id, pipe_id, queue_id;
36073608 struct amdgpu_ring *ring;
3608− uint32_t mes_queue_id = entry->src_data[0];
3609+ int i, xcc_id;
36093610
36103611 DRM_DEBUG("IH: CP EOP\n");
36113612
3612− if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
3613− struct amdgpu_mes_queue *queue;
3613+ if (adev->enable_mes && doorbell_offset) {
3614+ struct amdgpu_userq_fence_driver *fence_drv = NULL;
3615+ struct xarray *xa = &adev->userq_xa;
3616+ unsigned long flags;
36143617
3615− mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
3616−
3617− spin_lock(&adev->mes.queue_id_lock);
3618− queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
3619− if (queue) {
3620− DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
3621− amdgpu_fence_process(queue->ring);
3622− }
3623− spin_unlock(&adev->mes.queue_id_lock);
3618+ xa_lock_irqsave(xa, flags);
3619+ fence_drv = xa_load(xa, doorbell_offset);
3620+ if (fence_drv)
3621+ amdgpu_userq_fence_driver_process(fence_drv);
3622+ xa_unlock_irqrestore(xa, flags);
36243623 } else {
36253624 me_id = (entry->ring_id & 0x0c) >> 2;
36263625 pipe_id = (entry->ring_id & 0x03) >> 0;
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c+2−1
@@ -289,7 +289,8 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, · 288 unmodified lines
289289 return -ENOMEM;
290290 }
291291
292− r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size);
292+ r = amdgpu_userq_create_object(uq_mgr, &queue->mqd,
293+ AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size));
293294 if (r) {
294295 DRM_ERROR("Failed to create MQD object for userqueue\n");
295296 goto free_props;
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c+3−15
@@ -1704,24 +1704,12 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, · 1703 unmodified lines
17041704 struct amdgpu_irq_src *source,
17051705 struct amdgpu_iv_entry *entry)
17061706 {
1707− uint32_t mes_queue_id = entry->src_data[0];
1708−
17091707 DRM_DEBUG("IH: SDMA trap\n");
17101708
1711− if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1712− struct amdgpu_mes_queue *queue;
1713−
1714− mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1715−
1716− spin_lock(&adev->mes.queue_id_lock);
1717− queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1718− if (queue) {
1719− DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1720− amdgpu_fence_process(queue->ring);
1721− }
1722− spin_unlock(&adev->mes.queue_id_lock);
1709+ if (drm_WARN_ON_ONCE(&adev->ddev,
1710+ adev->enable_mes &&
1711+ (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
17231712 return 0;
1724− }
17251713
17261714 switch (entry->client_id) {
17271715 case SOC15_IH_CLIENTID_SDMA0:
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+3−15
@@ -1617,24 +1617,12 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, · 1616 unmodified lines
16171617 struct amdgpu_irq_src *source,
16181618 struct amdgpu_iv_entry *entry)
16191619 {
1620− uint32_t mes_queue_id = entry->src_data[0];
1621−
16221620 DRM_DEBUG("IH: SDMA trap\n");
16231621
1624− if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1625− struct amdgpu_mes_queue *queue;
1626−
1627− mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1628−
1629− spin_lock(&adev->mes.queue_id_lock);
1630− queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1631− if (queue) {
1632− DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1633− amdgpu_fence_process(queue->ring);
1634− }
1635− spin_unlock(&adev->mes.queue_id_lock);
1622+ if (drm_WARN_ON_ONCE(&adev->ddev,
1623+ adev->enable_mes &&
1624+ (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
16361625 return 0;
1637− }
16381626
16391627 switch (entry->client_id) {
16401628 case SOC15_IH_CLIENTID_SDMA0:
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c+3−14
@@ -1494,24 +1494,13 @@ static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev, · 1493 unmodified lines
14941494 struct amdgpu_iv_entry *entry)
14951495 {
14961496 int inst, instances, queue, xcc_id = 0;
1497− uint32_t mes_queue_id = entry->src_data[0];
14981497
14991498 DRM_DEBUG("IH: SDMA trap\n");
15001499
1501− if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1502− struct amdgpu_mes_queue *queue;
1503−
1504− mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1505−
1506− spin_lock(&adev->mes.queue_id_lock);
1507− queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1508− if (queue) {
1509− DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1510− amdgpu_fence_process(queue->ring);
1511− }
1512− spin_unlock(&adev->mes.queue_id_lock);
1500+ if (drm_WARN_ON_ONCE(&adev->ddev,
1501+ adev->enable_mes &&
1502+ (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
15131503 return 0;
1514− }
15151504
15161505 queue = entry->ring_id & 0xf;
15171506 if (adev->gfx.funcs && adev->gfx.funcs->ih_node_to_logical_xcc)
drivers/gpu/drm/amd/amdgpu/soc21.c+7−1
@@ -256,7 +256,13 @@ static u32 soc21_get_config_memsize(struct amdgpu_device *adev) · 255 unmodified lines
256256
257257 static u32 soc21_get_xclk(struct amdgpu_device *adev)
258258 {
259− return adev->clock.spll.reference_freq;
259+ u32 reference_clock = adev->clock.spll.reference_freq;
260+
261+ /* reference clock is actually 99.81 Mhz rather than 100 Mhz */
262+ if ((adev->flags & AMD_IS_APU) && reference_clock == 10000)
263+ return 9981;
264+
265+ return reference_clock;
260266 }
261267
262268
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c+1−1
@@ -1742,11 +1742,11 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, · 1741 unmodified lines
17421742 goto unlock;
17431743 }
17441744
1745− r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me);
17461745 if (pg_state)
17471746 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
17481747 AMD_PG_STATE_GATE);
17491748 mutex_unlock(&adev->jpeg.jpeg_pg_lock);
1749+ r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me);
17501750
17511751 unlock:
17521752 mutex_unlock(&vinst->engine_reset_mutex);
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h+103−94
@@ -4587,14 +4587,14 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { · 4586 unmodified lines
45874587 };
45884588
45894589 static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {
4590− 0xbfa00001, 0xbfa003ac,
4590+ 0xbfa00001, 0xbfa003be,
45914591 0xb0804009, 0xb8f8f804,
45924592 0x9178ff78, 0x00008c00,
45934593 0xb8fbf811, 0x8b6eff78,
45944594 0x00004000, 0xbfa10008,
45954595 0x8b6eff7b, 0x00000080,
45964596 0xbfa20018, 0x8b6ea07b,
4597− 0xbfa200d1, 0xbf830010,
4597+ 0xbfa200da, 0xbf830010,
45984598 0xb8fbf811, 0xbfa0fffb,
45994599 0x8b6eff7b, 0x00000bd0,
46004600 0xbfa20010, 0xb8eef812,
@@ -4605,7 +4605,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { · 4 unmodified lines
46054605 0xf0000000, 0xbfa20005,
46064606 0x8b6fff6f, 0x00000200,
46074607 0xbfa20002, 0x8b6ea07b,
4608− 0xbfa200bb, 0x9177ff77,
4608+ 0xbfa200c4, 0x9177ff77,
46094609 0x007fc000, 0xb8fa04a1,
46104610 0x847a967a, 0x8c777a77,
46114611 0xb8fa0421, 0x847a957a,
@@ -4632,43 +4632,46 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { · 20 unmodified lines
46324632 0xbfa00002, 0x806c846c,
46334633 0x826d806d, 0x8b6dff6d,
46344634 0x01ffffff, 0xb8fbf811,
4635− 0xbf0d847b, 0xbfa20078,
4635+ 0xbf0d847b, 0xbfa20081,
46364636 0xf4003eb6, 0xf8000000,
46374637 0xbfc70000, 0xf4003bb6,
46384638 0xf8000008, 0x8b76ff7a,
46394639 0x80000000, 0xbfa20027,
46404640 0x9376ff7a, 0x00060019,
46414641 0x81f9a376, 0xbf0b8179,
4642− 0xbfa20068, 0x81f9ac76,
4643− 0xbf0b8179, 0xbfa20062,
4642+ 0xbfa2006e, 0x81f9ac76,
4643+ 0xbf0b8179, 0xbfa20068,
46444644 0x81f9b776, 0xbf0b8179,
4645− 0xbfa2005f, 0x8b76ff7a,
4645+ 0xbfa20065, 0x8b76ff7a,
46464646 0x000001ff, 0xbf06ff76,
4647− 0x000000fe, 0xbfa2005d,
4647+ 0x000000fe, 0xbfa20063,
46484648 0xbf06ff76, 0x000000ff,
4649− 0xbfa20057, 0xbf06ff76,
4650− 0x000000fa, 0xbfa20054,
4649+ 0xbfa2005d, 0xbf06ff76,
4650+ 0x000000fa, 0xbfa2005a,
46514651 0x81f9ff76, 0x000000e9,
4652− 0xbf0b8179, 0xbfa20050,
4652+ 0xbf0b8179, 0xbfa20056,
46534653 0x8b76ff7b, 0xffff0000,
46544654 0xbf06ff76, 0xbf860000,
4655− 0xbfa10051, 0x9376ff7b,
4655+ 0xbfa1005a, 0x9376ff7b,
46564656 0x0002000e, 0x8b79ff7b,
46574657 0x00003f00, 0x85798679,
46584658 0x8c767976, 0xb9763b01,
4659− 0xbfa00049, 0x8b76ff7a,
4659+ 0xbfa00052, 0x8b76ff7a,
46604660 0xfc000000, 0xbf06ff76,
4661− 0xd4000000, 0xbfa20013,
4661+ 0xd4000000, 0xbfa20019,
46624662 0xbf06ff76, 0xc8000000,
4663− 0xbfa20027, 0x8b76ff7a,
4663+ 0xbfa2002d, 0x8b76ff7a,
46644664 0xff000000, 0xbf06ff76,
4665− 0xcf000000, 0xbfa20039,
4665+ 0xcf000000, 0xbfa2003f,
46664666 0x8b79ff7a, 0xffff0000,
4667+ 0xbf06ff79, 0xcc330000,
4668+ 0xbfa2003d, 0xbf06ff79,
4669+ 0xcc880000, 0xbfa2003a,
46674670 0xbf06ff79, 0xcc350000,
4668− 0xbfa20037, 0xbf06ff79,
4669− 0xcc3a0000, 0xbfa20034,
4671+ 0xbfa2003a, 0xbf06ff79,
4672+ 0xcc3a0000, 0xbfa20037,
46704673 0xbf06ff76, 0xcc000000,
4671− 0xbfa10031, 0x8b76ff7b,
4674+ 0xbfa10034, 0x8b76ff7b,
46724675 0x000001ff, 0xbf06ff76,
46734676 0x000000ff, 0xbfa20029,
46744677 0xbf06ff76, 0x000000fa,
@@ -4691,86 +4694,92 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { · 16 unmodified lines
46914694 0x000001ff, 0xbf06ff76,
46924695 0x000000ff, 0xbfa20003,
46934696 0xbfc70000, 0xbefb006e,
4694− 0xbfa0ffad, 0xbfc70000,
4695− 0xbefb006f, 0xbfa0ffaa,
4696− 0xbfc70000, 0x857a9677,
4697− 0xb97a04a1, 0x857a9577,
4698− 0xb97a0421, 0x857a8e77,
4699− 0xb97a3021, 0x8bfe7e7e,
4700− 0x8bea6a6a, 0x85788978,
4701− 0xb9783244, 0xbe804a6c,
4702− 0xb8faf802, 0xbf0d987a,
4703− 0xbfa10001, 0xbfb00000,
4704− 0x8b6dff6d, 0x01ffffff,
4705− 0xbefa0080, 0xb97a0151,
4706− 0x9177ff77, 0x007fc000,
4707− 0xb8fa04a1, 0x847a967a,
4708− 0x8c777a77, 0xb8fa0421,
4709− 0x847a957a, 0x8c777a77,
4710− 0xb8fa3021, 0x847a8e7a,
4711− 0x8c777a77, 0xb980f821,
4712− 0x00000000, 0xbf0d847b,
4713− 0xbfa20078, 0xf4003eb6,
4714− 0xf8000000, 0xbfc70000,
4715− 0xf4003bb6, 0xf8000008,
4716− 0x8b76ff7a, 0x80000000,
4717− 0xbfa20027, 0x9376ff7a,
4718− 0x00060019, 0x81f9a376,
4697+ 0xbfa0ffa7, 0xbfc70000,
4698+ 0xbefb006f, 0xbfa0ffa4,
4699+ 0x80ec886c, 0x82ed806d,
4700+ 0xbfa0fff7, 0xbfc70000,
4701+ 0x857a9677, 0xb97a04a1,
4702+ 0x857a9577, 0xb97a0421,
4703+ 0x857a8e77, 0xb97a3021,
4704+ 0x8bfe7e7e, 0x8bea6a6a,
4705+ 0x85788978, 0xb9783244,
4706+ 0xbe804a6c, 0xb8faf802,
4707+ 0xbf0d987a, 0xbfa10001,
4708+ 0xbfb00000, 0x8b6dff6d,
4709+ 0x01ffffff, 0xbefa0080,
4710+ 0xb97a0151, 0x9177ff77,
4711+ 0x007fc000, 0xb8fa04a1,
4712+ 0x847a967a, 0x8c777a77,
4713+ 0xb8fa0421, 0x847a957a,
4714+ 0x8c777a77, 0xb8fa3021,
4715+ 0x847a8e7a, 0x8c777a77,
4716+ 0xb980f821, 0x00000000,
4717+ 0xbf0d847b, 0xbfa20081,
4718+ 0xf4003eb6, 0xf8000000,
4719+ 0xbfc70000, 0xf4003bb6,
4720+ 0xf8000008, 0x8b76ff7a,
4721+ 0x80000000, 0xbfa20027,
4722+ 0x9376ff7a, 0x00060019,
4723+ 0x81f9a376, 0xbf0b8179,
4724+ 0xbfa2006e, 0x81f9ac76,
47194725 0xbf0b8179, 0xbfa20068,
4720− 0x81f9ac76, 0xbf0b8179,
4721− 0xbfa20062, 0x81f9b776,
4722− 0xbf0b8179, 0xbfa2005f,
4723− 0x8b76ff7a, 0x000001ff,
4724− 0xbf06ff76, 0x000000fe,
4726+ 0x81f9b776, 0xbf0b8179,
4727+ 0xbfa20065, 0x8b76ff7a,
4728+ 0x000001ff, 0xbf06ff76,
4729+ 0x000000fe, 0xbfa20063,
4730+ 0xbf06ff76, 0x000000ff,
47254731 0xbfa2005d, 0xbf06ff76,
4726− 0x000000ff, 0xbfa20057,
4732+ 0x000000fa, 0xbfa2005a,
4733+ 0x81f9ff76, 0x000000e9,
4734+ 0xbf0b8179, 0xbfa20056,
4735+ 0x8b76ff7b, 0xffff0000,
4736+ 0xbf06ff76, 0xbf860000,
4737+ 0xbfa1005a, 0x9376ff7b,
4738+ 0x0002000e, 0x8b79ff7b,
4739+ 0x00003f00, 0x85798679,
4740+ 0x8c767976, 0xb9763b01,
4741+ 0xbfa00052, 0x8b76ff7a,
4742+ 0xfc000000, 0xbf06ff76,
4743+ 0xd4000000, 0xbfa20019,
4744+ 0xbf06ff76, 0xc8000000,
4745+ 0xbfa2002d, 0x8b76ff7a,
4746+ 0xff000000, 0xbf06ff76,
4747+ 0xcf000000, 0xbfa2003f,
4748+ 0x8b79ff7a, 0xffff0000,
4749+ 0xbf06ff79, 0xcc330000,
4750+ 0xbfa2003d, 0xbf06ff79,
4751+ 0xcc880000, 0xbfa2003a,
4752+ 0xbf06ff79, 0xcc350000,
4753+ 0xbfa2003a, 0xbf06ff79,
4754+ 0xcc3a0000, 0xbfa20037,
4755+ 0xbf06ff76, 0xcc000000,
4756+ 0xbfa10034, 0x8b76ff7b,
4757+ 0x000001ff, 0xbf06ff76,
4758+ 0x000000ff, 0xbfa20029,
47274759 0xbf06ff76, 0x000000fa,
4728− 0xbfa20054, 0x81f9ff76,
4729− 0x000000e9, 0xbf0b8179,
4730− 0xbfa20050, 0x8b76ff7b,
4731− 0xffff0000, 0xbf06ff76,
4732− 0xbf860000, 0xbfa10051,
4733− 0x9376ff7b, 0x0002000e,
4734− 0x8b79ff7b, 0x00003f00,
4735− 0x85798679, 0x8c767976,
4736− 0xb9763b01, 0xbfa00049,
4737− 0x8b76ff7a, 0xfc000000,
4738− 0xbf06ff76, 0xd4000000,
4739− 0xbfa20013, 0xbf06ff76,
4740− 0xc8000000, 0xbfa20027,
4741− 0x8b76ff7a, 0xff000000,
4742− 0xbf06ff76, 0xcf000000,
4743− 0xbfa20039, 0x8b79ff7a,
4744− 0xffff0000, 0xbf06ff79,
4745− 0xcc350000, 0xbfa20037,
4746− 0xbf06ff79, 0xcc3a0000,
4747− 0xbfa20034, 0xbf06ff76,
4748− 0xcc000000, 0xbfa10031,
4749− 0x8b76ff7b, 0x000001ff,
4750− 0xbf06ff76, 0x000000ff,
4751− 0xbfa20029, 0xbf06ff76,
4752− 0x000000fa, 0xbfa20026,
4753− 0x81f6ff76, 0x000000e9,
4754− 0xbf0b8176, 0xbfa20022,
4755− 0x8b76ff7b, 0x0003fe00,
4756− 0xbf06ff76, 0x0001fe00,
4757− 0xbfa2001d, 0x8b76ff7b,
4758− 0x07fc0000, 0xbf06ff76,
4759− 0x03fc0000, 0xbfa20018,
4760− 0xbfa00014, 0x9376ff7a,
4761− 0x00040016, 0x81f68176,
4762− 0xbf0b8176, 0xbfa20012,
4763− 0x9376ff7a, 0x00050011,
4760+ 0xbfa20026, 0x81f6ff76,
4761+ 0x000000e9, 0xbf0b8176,
4762+ 0xbfa20022, 0x8b76ff7b,
4763+ 0x0003fe00, 0xbf06ff76,
4764+ 0x0001fe00, 0xbfa2001d,
4765+ 0x8b76ff7b, 0x07fc0000,
4766+ 0xbf06ff76, 0x03fc0000,
4767+ 0xbfa20018, 0xbfa00014,
4768+ 0x9376ff7a, 0x00040016,
47644769 0x81f68176, 0xbf0b8176,
4765− 0xbfa2000d, 0x8b76ff7a,
4766− 0x000001ff, 0xbf06ff76,
4767− 0x000000ff, 0xbfa20008,
4768− 0x8b76ff7b, 0x000001ff,
4770+ 0xbfa20012, 0x9376ff7a,
4771+ 0x00050011, 0x81f68176,
4772+ 0xbf0b8176, 0xbfa2000d,
4773+ 0x8b76ff7a, 0x000001ff,
47694774 0xbf06ff76, 0x000000ff,
4770− 0xbfa20003, 0xbfc70000,
4771− 0xbefb006e, 0xbfa0ffad,
4772− 0xbfc70000, 0xbefb006f,
4773− 0xbfa0ffaa, 0xbfc70000,
4775+ 0xbfa20008, 0x8b76ff7b,
4776+ 0x000001ff, 0xbf06ff76,
4777+ 0x000000ff, 0xbfa20003,
4778+ 0xbfc70000, 0xbefb006e,
4779+ 0xbfa0ffa7, 0xbfc70000,
4780+ 0xbefb006f, 0xbfa0ffa4,
4781+ 0x80ec886c, 0x82ed806d,
4782+ 0xbfa0fff7, 0xbfc70000,
47744783 0xbeee007e, 0xbeef007f,
47754784 0xbefe0180, 0xbefe4d84,
47764785 0xbf8a0000, 0x8b7aff7f,
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm+18−7
@@ -37,6 +37,7 @@ · 36 unmodified lines
3737 #define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3)
3838 #define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3)
3939 #define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12)
40+#define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3)
4041
4142 #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised
4243 #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12)
@@ -375,9 +376,9 @@ L_TRAP_CASE: · 332 unmodified lines
375376 L_EXIT_TRAP:
376377 s_and_b32 ttmp1, ttmp1, ADDRESS_HI32_MASK
377378
378−#if HAVE_BANKED_VGPRS
379+#if HAVE_INSTRUCTION_FIXUP
379380 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)
380− fixup_vgpr_bank_selection()
381+ fixup_instruction()
381382 #endif
382383
383384 #if HAVE_XNACK
@@ -418,8 +419,8 @@ L_HAVE_VGPRS: · 34 unmodified lines
418419 save_and_clear_xnack_state_priv(s_save_tmp)
419420 #endif
420421
421−#if HAVE_BANKED_VGPRS
422− fixup_vgpr_bank_selection()
422+#if HAVE_INSTRUCTION_FIXUP
423+ fixup_instruction()
423424 #endif
424425
425426 /* inform SPI the readiness and wait for SPI's go signal */
@@ -1400,8 +1401,8 @@ L_BARRIER_RESTORE_LOOP: · 974 unmodified lines
14001401 L_BARRIER_RESTORE_DONE:
14011402 end
14021403
1403−#if HAVE_BANKED_VGPRS
1404−function fixup_vgpr_bank_selection
1404+#if HAVE_INSTRUCTION_FIXUP
1405+function fixup_instruction
14051406 // PC read may fault if memory violation has been asserted.
14061407 // In this case no further progress is expected so fixup is not needed.
14071408 s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT
@@ -1480,8 +1481,13 @@ L_FIXUP_NOT_VOP12C: · 72 unmodified lines
14801481 s_cmp_eq_u32 ttmp10, 0xcf000000 // If 31:24 = 0xcf, this is VOPD3
14811482 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If VOPD3, 3 DWORD inst
14821483 // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD, or VOPD3.
1483− // Might be in VOP3P, but we must ensure we are not VOP3PX2
1484+ // Check if we are in the middle of VOP3PX.
14841485 s_and_b32 ttmp13, ttmp14, 0xffff0000 // Bits 31:16
1486+ s_cmp_eq_u32 ttmp13, 0xcc330000 // If 31:16 = 0xcc33, this is 8 bytes past VOP3PX
1487+ s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE
1488+ s_cmp_eq_u32 ttmp13, 0xcc880000 // If 31:16 = 0xcc88, this is 8 bytes past VOP3PX
1489+ s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE
1490+ // Might be in VOP3P, but we must ensure we are not VOP3PX2
14851491 s_cmp_eq_u32 ttmp13, 0xcc350000 // If 31:16 = 0xcc35, this is VOP3PX2
14861492 s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed
14871493 s_cmp_eq_u32 ttmp13, 0xcc3a0000 // If 31:16 = 0xcc3a, this is VOP3PX2
@@ -1542,6 +1548,11 @@ L_FIXUP_THREE_DWORD: · 54 unmodified lines
15421548 s_mov_b32 ttmp15, ttmp3 // Move possible S_SET_VGPR_MSB into ttmp15
15431549 s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB
15441550
1551+L_FIXUP_VOP3PX_MIDDLE:
1552+ s_sub_co_u32 ttmp0, ttmp0, 8 // Rewind PC 8 bytes to beginning of instruction
1553+ s_sub_co_ci_u32 ttmp1, ttmp1, 0
1554+ s_branch L_FIXUP_TWO_DWORD // 2 DWORD inst (2nd half of a 4 DWORD inst)
1555+
15451556 L_FIXUP_DONE:
15461557 s_wait_kmcnt 0 // Ensure load of ttmp2 and ttmp3 is done
15471558 end
drivers/gpu/drm/amd/amdkfd/kfd_debug.c+1−0
@@ -1108,6 +1108,7 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, · 1107 unmodified lines
11081108 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask);
11091109 device_info.capability = topo_dev->node_props.capability;
11101110 device_info.debug_prop = topo_dev->node_props.debug_prop;
1111+ device_info.capability2 = topo_dev->node_props.capability2;
11111112
11121113 if (exception_clear_mask)
11131114 pdd->exception_status &= ~exception_clear_mask;
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+2−2
@@ -676,7 +676,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, · 675 unmodified lines
676676
677677 /* Temporarily release dqm lock to avoid a circular lock dependency */
678678 dqm_unlock(dqm);
679− q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
679+ q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties);
680680 dqm_lock(dqm);
681681
682682 if (!q->mqd_mem_obj) {
@@ -2002,7 +2002,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, · 1319 unmodified lines
20022002 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
20032003 q->properties.tba_addr = qpd->tba_addr;
20042004 q->properties.tma_addr = qpd->tma_addr;
2005− q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
2005+ q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties);
20062006 if (!q->mqd_mem_obj) {
20072007 retval = -ENOMEM;
20082008 goto out_deallocate_doorbell;
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c+1−1
@@ -130,7 +130,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, · 129 unmodified lines
130130
131131 kq->queue->device = dev;
132132
133− kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr->dev,
133+ kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr,
134134 &kq->queue->properties);
135135 if (!kq->queue->mqd_mem_obj)
136136 goto err_allocate_mqd;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c+7−2
@@ -46,9 +46,10 @@ int pipe_priority_map[] = { · 45 unmodified lines
4646 KFD_PIPE_PRIORITY_CS_HIGH
4747 };
4848
49−struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properties *q)
49+struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q)
5050 {
5151 struct kfd_mem_obj *mqd_mem_obj;
52+ struct kfd_node *dev = mm->dev;
5253
5354 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
5455 if (!mqd_mem_obj)
@@ -61,10 +62,11 @@ struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properti · 6 unmodified lines
6162 return mqd_mem_obj;
6263 }
6364
64−struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev,
65+struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm,
6566 struct queue_properties *q)
6667 {
6768 struct kfd_mem_obj *mqd_mem_obj;
69+ struct kfd_node *dev = mm->dev;
6870 uint64_t offset;
6971
7072 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
@@ -290,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj, · 219 unmodified lines
290292 uint64_t kfd_mqd_stride(struct mqd_manager *mm,
291293 struct queue_properties *q)
292294 {
295+ if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0))
296+ return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
297+
293298 return mm->mqd_size;
294299 }
295300
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h+3−3
@@ -68,7 +68,7 @@ · 67 unmodified lines
6868 */
6969 extern int pipe_priority_map[];
7070 struct mqd_manager {
71− struct kfd_mem_obj* (*allocate_mqd)(struct kfd_node *kfd,
71+ struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm,
7272 struct queue_properties *q);
7373
7474 void (*init_mqd)(struct mqd_manager *mm, void **mqd,
@@ -153,10 +153,10 @@ struct mqd_user_context_save_area_header { · 78 unmodified lines
153153 uint32_t wave_state_size;
154154 };
155155
156−struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev,
156+struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm,
157157 struct queue_properties *q);
158158
159−struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev,
159+struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm,
160160 struct queue_properties *q);
161161 void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
162162 struct kfd_mem_obj *mqd_mem_obj);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c+2−1
@@ -73,9 +73,10 @@ static void set_priority(struct cik_mqd *m, struct queue_properties *q) · 72 unmodified lines
7373 m->cp_hqd_queue_priority = q->priority;
7474 }
7575
76−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
76+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
7777 struct queue_properties *q)
7878 {
79+ struct kfd_node *kfd = mm->dev;
7980 struct kfd_mem_obj *mqd_mem_obj;
8081
8182 if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd),
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c+2−1
@@ -73,9 +73,10 @@ static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) · 72 unmodified lines
7373 m->cp_hqd_queue_priority = q->priority;
7474 }
7575
76−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
76+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
7777 struct queue_properties *q)
7878 {
79+ struct kfd_node *kfd = mm->dev;
7980 struct kfd_mem_obj *mqd_mem_obj;
8081
8182 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c+6−19
@@ -99,22 +99,14 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) · 98 unmodified lines
9999 m->cp_hqd_queue_priority = q->priority;
100100 }
101101
102−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
102+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
103103 struct queue_properties *q)
104104 {
105+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
106+ struct kfd_node *node = mm->dev;
105107 struct kfd_mem_obj *mqd_mem_obj;
106− int size;
107−
108− /*
109− * MES write to areas beyond MQD size. So allocate
110− * 1 PAGE_SIZE memory for MQD is MES is enabled.
111− */
112− if (node->kfd->shared_resources.enable_mes)
113− size = PAGE_SIZE;
114− else
115− size = sizeof(struct v11_compute_mqd);
116108
117− if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
109+ if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
118110 return NULL;
119111
120112 return mqd_mem_obj;
@@ -126,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, · 5 unmodified lines
126118 {
127119 uint64_t addr;
128120 struct v11_compute_mqd *m;
129− int size;
121+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
130122 uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
131123
132124 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
133125 addr = mqd_mem_obj->gpu_addr;
134126
135− if (mm->dev->kfd->shared_resources.enable_mes)
136− size = PAGE_SIZE;
137− else
138− size = sizeof(struct v11_compute_mqd);
139−
140− memset(m, 0, size);
127+ memset(m, 0, mqd_size);
141128
142129 m->header = 0xC0310800;
143130 m->compute_pipelinestat_enable = 1;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c+6−7
@@ -80,16 +80,14 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) · 79 unmodified lines
8080 m->cp_hqd_queue_priority = q->priority;
8181 }
8282
83−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
83+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
8484 struct queue_properties *q)
8585 {
86+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
87+ struct kfd_node *node = mm->dev;
8688 struct kfd_mem_obj *mqd_mem_obj;
8789
88− /*
89− * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond
90− * struct MQD size.
91− */
92− if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj))
90+ if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
9391 return NULL;
9492
9593 return mqd_mem_obj;
@@ -101,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, · 5 unmodified lines
10199 {
102100 uint64_t addr;
103101 struct v12_compute_mqd *m;
102+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
104103
105104 m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr;
106105 addr = mqd_mem_obj->gpu_addr;
107106
108− memset(m, 0, PAGE_SIZE);
107+ memset(m, 0, mqd_size);
109108
110109 m->header = 0xC0310800;
111110 m->compute_pipelinestat_enable = 1;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c+8−24
@@ -32,17 +32,6 @@ · 31 unmodified lines
3232 #include "amdgpu_amdkfd.h"
3333 #include "kfd_device_queue_manager.h"
3434
35−#define MQD_SIZE (2 * PAGE_SIZE)
36−
37−static uint64_t mqd_stride_v12_1(struct mqd_manager *mm,
38− struct queue_properties *q)
39−{
40− if (q->type == KFD_QUEUE_TYPE_COMPUTE)
41− return MQD_SIZE;
42− else
43− return PAGE_SIZE;
44−}
45−
4635 static inline struct v12_1_compute_mqd *get_mqd(void *mqd)
4736 {
4837 return (struct v12_1_compute_mqd *)mqd;
@@ -145,23 +134,17 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q · 96 unmodified lines
145134 m->cp_hqd_queue_priority = q->priority;
146135 }
147136
148−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
137+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
149138 struct queue_properties *q)
150139 {
140+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
141+ struct kfd_node *node = mm->dev;
151142 struct kfd_mem_obj *mqd_mem_obj;
152− unsigned int size;
153143
154− /*
155− * Allocate two PAGE_SIZE memory for Compute MQD as MES writes to areas beyond
156− * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE.
157− * For SDMA MQD, we allocate 1 Page_size.
158− */
159144 if (q->type == KFD_QUEUE_TYPE_COMPUTE)
160− size = MQD_SIZE * NUM_XCC(node->xcc_mask);
161− else
162− size = PAGE_SIZE;
145+ mqd_size *= NUM_XCC(node->xcc_mask);
163146
164− if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
147+ if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
165148 return NULL;
166149
167150 return mqd_mem_obj;
@@ -173,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, · 5 unmodified lines
173156 {
174157 uint64_t addr;
175158 struct v12_1_compute_mqd *m;
159+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
176160
177161 m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr;
178162 addr = mqd_mem_obj->gpu_addr;
179163
180− memset(m, 0, MQD_SIZE);
164+ memset(m, 0, mqd_size);
181165
182166 m->header = 0xC0310800;
183167 m->compute_pipelinestat_enable = 1;
@@ -680,7 +664,7 @@ struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, · 496 unmodified lines
680664 mqd->is_occupied = kfd_is_occupied_cp;
681665 mqd->mqd_size = sizeof(struct v12_1_compute_mqd);
682666 mqd->get_wave_state = get_wave_state_v12_1;
683− mqd->mqd_stride = mqd_stride_v12_1;
667+ mqd->mqd_stride = kfd_mqd_stride;
684668 #if defined(CONFIG_DEBUG_FS)
685669 mqd->debugfs_show_mqd = debugfs_show_mqd;
686670 #endif
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c+2−1
@@ -120,10 +120,11 @@ static bool mqd_on_vram(struct amdgpu_device *adev) · 119 unmodified lines
120120 }
121121 }
122122
123−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
123+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
124124 struct queue_properties *q)
125125 {
126126 int retval;
127+ struct kfd_node *node = mm->dev;
127128 struct kfd_mem_obj *mqd_mem_obj = NULL;
128129
129130 /* For V9 only, due to a HW bug, the control stack of a user mode
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c+2−1
@@ -76,9 +76,10 @@ static void set_priority(struct vi_mqd *m, struct queue_properties *q) · 75 unmodified lines
7676 m->cp_hqd_queue_priority = q->priority;
7777 }
7878
79−static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
79+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
8080 struct queue_properties *q)
8181 {
82+ struct kfd_node *kfd = mm->dev;
8283 struct kfd_mem_obj *mqd_mem_obj;
8384
8485 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+1−1
@@ -11867,7 +11867,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, · 11866 unmodified lines
1186711867 * check tiling flags when the FB doesn't have a modifier.
1186811868 */
1186911869 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
11870− if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) {
11870+ if (adev->family == AMDGPU_FAMILY_GC_12_0_0) {
1187111871 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0;
1187211872 } else if (adev->family >= AMDGPU_FAMILY_AI) {
1187311873 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c+2−2
@@ -278,7 +278,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, · 277 unmodified lines
278278 if (!dcc->enable)
279279 return 0;
280280
281− if (adev->family < AMDGPU_FAMILY_GC_12_0_0 &&
281+ if (adev->family != AMDGPU_FAMILY_GC_12_0_0 &&
282282 format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
283283 return -EINVAL;
284284
@@ -901,7 +901,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, · 616 unmodified lines
901901 upper_32_bits(chroma_addr);
902902 }
903903
904− if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) {
904+ if (adev->family == AMDGPU_FAMILY_GC_12_0_0) {
905905 ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format,
906906 rotation, plane_size,
907907 tiling_info, dcc,
drivers/gpu/drm/amd/display/dc/core/dc.c+1−1
@@ -7506,7 +7506,7 @@ struct dc_update_scratch_space *dc_update_planes_and_stream_init( · 7505 unmodified lines
75067506 .stream = stream,
75077507 .stream_update = stream_update,
75087508 .update_v3 = version >= DCN_VERSION_4_01 || version == DCN_VERSION_3_2 || version == DCN_VERSION_3_21,
7509− .do_clear_update_flags = version >= DCN_VERSION_3_2 || version == DCN_VERSION_3_01,
7509+ .do_clear_update_flags = version >= DCN_VERSION_1_0,
75107510 };
75117511
75127512 return scratch;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c+13−0
@@ -515,6 +515,19 @@ bool dc_stream_program_cursor_position( · 514 unmodified lines
515515 }
516516 }
517517
518+ /* apply manual trigger */
519+ int i;
520+
521+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
522+ struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
523+
524+ /* trigger event on first pipe with current stream */
525+ if (stream == pipe_ctx->stream) {
526+ pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
527+ break;
528+ }
529+ }
530+
518531 return true;
519532 }
520533
drivers/gpu/drm/amd/display/dc/dc.h+2−1
@@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; · 62 unmodified lines
6363 struct dcn_optc_reg_state;
6464 struct dcn_dccg_reg_state;
6565
66−#define DC_VER "3.2.366"
66+#define DC_VER "3.2.367"
6767
6868 /**
6969 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
@@ -1210,6 +1210,7 @@ struct dc_debug_options { · 1140 unmodified lines
12101210 bool disable_deferred_minimal_transitions;
12111211 unsigned int num_fast_flips_to_steady_state_override;
12121212 bool enable_dmu_recovery;
1213+ unsigned int force_vmin_threshold;
12131214 };
12141215
12151216
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c+18−0
@@ -944,3 +944,21 @@ void hubbub1_construct(struct hubbub *hubbub, · 943 unmodified lines
944944 hubbub1->debug_test_index_pstate = 0xB;
945945 }
946946
947+void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv)
948+{
949+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
950+
951+ if (refdiv > 0)
952+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv);
953+
954+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0);
955+}
956+
957+void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value)
958+{
959+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
960+
961+ REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value);
962+ REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value);
963+}
964+
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h+4−0
@@ -519,4 +519,8 @@ bool hubbub1_program_pstate_watermarks( · 518 unmodified lines
519519 unsigned int refclk_mhz,
520520 bool safe_to_lower);
521521
522+void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv);
523+
524+void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value);
525+
522526 #endif
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c+2−3
@@ -2678,8 +2678,7 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, · 2677 unmodified lines
26782678 uint32_t fb_base_value;
26792679 uint32_t fb_offset_value;
26802680
2681− REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
2682− REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
2681+ dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value);
26832682
26842683 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
26852684 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
@@ -3474,7 +3473,7 @@ void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, · 788 unmodified lines
34743473 triggers, params->num_frames);
34753474 }
34763475
3477−static void dcn10_config_stereo_parameters(
3476+void dcn10_config_stereo_parameters(
34783477 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
34793478 {
34803479 enum view_3d_format view_format = stream->view_format;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h+2−0
@@ -217,5 +217,7 @@ void dcn10_update_visual_confirm_color( · 216 unmodified lines
217217 void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
218218 struct dc_plane_state *plane_state,
219219 bool clear_tiling);
220+void dcn10_config_stereo_parameters(
221+ struct dc_stream_state *stream, struct crtc_stereo_flags *flags);
220222
221223 #endif /* __DC_HWSS_DCN10_H__ */
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c+12−4
@@ -46,6 +46,7 @@ · 45 unmodified lines
4646 #include "dchubbub.h"
4747 #include "reg_helper.h"
4848 #include "dcn10/dcn10_cm_common.h"
49+#include "dcn10/dcn10_hubbub.h"
4950 #include "vm_helper.h"
5051 #include "dccg.h"
5152 #include "dc_dmub_srv.h"
@@ -3058,9 +3059,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 3006 unmodified lines
30583059 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
30593060 }
30603061 } else {
3061− if (dccg->funcs->enable_symclk_se)
3062− dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
3062+ if (dccg->funcs->enable_symclk_se && link_enc) {
3063+ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA
3064+ && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN
3065+ && !link->link_status.link_active) {
3066+ if (dccg->funcs->disable_symclk_se)
3067+ dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
30633068 link_enc->transmitter - TRANSMITTER_UNIPHY_A);
3069+ } else
3070+ dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
3071+ link_enc->transmitter - TRANSMITTER_UNIPHY_A);
3072+ }
30643073 }
30653074
30663075 if (dc->res_pool->dccg->funcs->set_pixel_rate_div)
@@ -3145,8 +3154,7 @@ void dcn20_fpga_init_hw(struct dc *dc) · 78 unmodified lines
31453154 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
31463155 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
31473156
3148− REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
3149− REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
3157+ dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);
31503158 if (REG(REFCLK_CNTL))
31513159 REG_WRITE(REFCLK_CNTL, 0);
31523160 //
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c+1−0
@@ -39,6 +39,7 @@ · 38 unmodified lines
3939 #include "dccg.h"
4040 #include "clk_mgr.h"
4141 #include "reg_helper.h"
42+#include "dcn10/dcn10_hubbub.h"
4243
4344 #define CTX \
4445 hws->ctx
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c+1−0
@@ -36,6 +36,7 @@ · 35 unmodified lines
3636 #include "dcn10/dcn10_cm_common.h"
3737 #include "dcn30/dcn30_cm_common.h"
3838 #include "reg_helper.h"
39+#include "dcn10/dcn10_hubbub.h"
3940 #include "abm.h"
4041 #include "clk_mgr.h"
4142 #include "hubp.h"
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c+1−0
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "dce/dce_hwseq.h"
3333 #include "clk_mgr.h"
3434 #include "reg_helper.h"
35+#include "dcn10/dcn10_hubbub.h"
3536 #include "abm.h"
3637 #include "hubp.h"
3738 #include "dchubbub.h"
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c+1−0
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "dce/dce_hwseq.h"
3333 #include "clk_mgr.h"
3434 #include "reg_helper.h"
35+#include "dcn10/dcn10_hubbub.h"
3536 #include "abm.h"
3637 #include "hubp.h"
3738 #include "dchubbub.h"
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c+0−2
@@ -2022,9 +2022,7 @@ bool dcn20_fast_validate_bw( · 2021 unmodified lines
20222022
20232023 dcn20_merge_pipes_for_validate(dc, context);
20242024
2025− DC_FP_START();
20262025 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
2027− DC_FP_END();
20282026
20292027 *pipe_cnt_out = pipe_cnt;
20302028
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c+0−2
@@ -785,9 +785,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, · 784 unmodified lines
785785
786786 dcn20_merge_pipes_for_validate(dc, context);
787787
788− DC_FP_START();
789788 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
790− DC_FP_END();
791789
792790 *pipe_cnt_out = pipe_cnt;
793791
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c+1−1
@@ -1772,7 +1772,7 @@ static int dcn401_get_power_profile(const struct dc_state *context) · 1771 unmodified lines
17721772 return dpm_level;
17731773 }
17741774
1775−static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1775+unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
17761776 {
17771777 return pipe_ctx->global_sync.dcn4x.vstartup_lines;
17781778 }
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h+2−0
@@ -28,6 +28,8 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, · 27 unmodified lines
2828
2929 void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
3030
31+unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
32+
3133 /* Following are definitions for run time init of reg offsets */
3234
3335 /* HUBP */
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h+49−6
@@ -139,6 +139,33 @@ · 138 unmodified lines
139139 */
140140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
141141
142+/**
143+ *
144+ * dirty rect cmd version legacy
145+ */
146+#define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0
147+/**
148+ * dirty rect cmd version with multi edp support
149+ */
150+#define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1
151+/**
152+ * dirty rect cmd version with external monitor support
153+ */
154+#define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2
155+
156+/**
157+ *
158+ * Cursor update cmd version legacy
159+ */
160+#define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0
161+/**
162+ * Cursor update cmd version with multi edp support
163+ */
164+#define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1
165+/**
166+ * Cursor update cmd version with external monitor support
167+ */
168+#define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2
142169
143170 /**
144171 * ABM control version legacy
@@ -3929,7 +3956,7 @@ struct dmub_cmd_update_dirty_rect_data { · 3784 unmodified lines
39293956 */
39303957 union dmub_psr_su_debug_flags debug_flags;
39313958 /**
3932− * OTG HW instance.
3959+ * Pipe index.
39333960 */
39343961 uint8_t pipe_idx;
39353962 /**
@@ -3937,7 +3964,7 @@ struct dmub_cmd_update_dirty_rect_data { · 1 unmodified line
39373964 */
39383965 uint8_t dirty_rect_count;
39393966 /**
3940− * PSR control version.
3967+ * dirty rects cmd version.
39413968 */
39423969 uint8_t cmd_version;
39433970 /**
@@ -3946,6 +3973,14 @@ struct dmub_cmd_update_dirty_rect_data { · 2 unmodified lines
39463973 * Currently the support is only for 0 or 1
39473974 */
39483975 uint8_t panel_inst;
3976+ /**
3977+ * OTG HW instance
3978+ */
3979+ uint8_t otg_inst;
3980+ /**
3981+ * Padding for 4 byte alignment
3982+ */
3983+ uint8_t padding[3];
39493984 };
39503985
39513986 /**
@@ -4071,11 +4106,11 @@ struct dmub_cmd_update_cursor_payload0 { · 119 unmodified lines
40714106 */
40724107 uint8_t enable;
40734108 /**
4074− * OTG HW instance.
4109+ * Pipe index.
40754110 */
40764111 uint8_t pipe_idx;
40774112 /**
4078− * PSR control version.
4113+ * Cursor update cmd version.
40794114 */
40804115 uint8_t cmd_version;
40814116 /**
@@ -4089,6 +4124,14 @@ struct dmub_cmd_update_cursor_payload0 { · 7 unmodified lines
40894124 * Registers contains Hubp & Dpp modules
40904125 */
40914126 struct dmub_cursor_position_cfg position_cfg;
4127+ /**
4128+ * OTG HW instance
4129+ */
4130+ uint8_t otg_inst;
4131+ /**
4132+ * Padding for 4 byte alignment
4133+ */
4134+ uint8_t padding[3];
40924135 };
40934136
40944137 struct dmub_cmd_update_cursor_payload1 {
@@ -6629,9 +6672,9 @@ struct dmub_cmd_pr_copy_settings_data { · 2534 unmodified lines
66296672 */
66306673 uint8_t su_y_granularity;
66316674 /**
6632− * @pad: Align structure to 4 byte boundary.
6675+ * @main_link_activity_option: Indicates main link activity option selected
66336676 */
6634− uint8_t pad;
6677+ uint8_t main_link_activity_option;
66356678 };
66366679
66376680 /**
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c+3−0
@@ -419,6 +419,9 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu · 418 unmodified lines
419419 boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;
420420 boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
421421 boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
422+ boot_options.bits.bootcrc_en_at_preos = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_preos;
423+ boot_options.bits.bootcrc_en_at_S0i3 = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_S0i3;
424+ boot_options.bits.bootcrc_boot_mode = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_boot_mode;
422425
423426 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
424427 }
drivers/gpu/drm/amd/display/include/dpcd_defs.h+1−0
@@ -224,6 +224,7 @@ enum dpcd_psr_sink_states { · 223 unmodified lines
224224 #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379
225225 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
226226 #define DP_SINK_EMISSION_RATE 0x37E
227+#define DP_SINK_PR_FRAME_SKIP_COUNT 0x337
227228
228229 /* Remove once drm_dp_helper.h is updated upstream */
229230 #ifndef DP_TOTAL_LTTPR_CNT
drivers/gpu/drm/amd/include/mes_v12_api_def.h+4−2
@@ -492,8 +492,10 @@ union MESAPI__SUSPEND { · 491 unmodified lines
492492 union MES_API_HEADER header;
493493 /* false - suspend all gangs; true - specific gang */
494494 struct {
495− uint32_t suspend_all_gangs : 1;
496− uint32_t reserved : 31;
495+ uint32_t suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs)
496+ uint32_t query_status : 1;
497+ uint32_t suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs)
498+ uint32_t reserved : 29;
497499 };
498500 /* gang_context_addr is valid only if suspend_all = false */
499501
drivers/gpu/drm/amd/pm/amdgpu_dpm.c+4−3
@@ -80,15 +80,15 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, · 79 unmodified lines
8080 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
8181 bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN;
8282
83+ mutex_lock(&adev->pm.mutex);
84+
8385 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&
8486 (!is_vcn || adev->vcn.num_vcn_inst == 1)) {
8587 dev_dbg(adev->dev, "IP block%d already in the target %s state!",
8688 block_type, gate ? "gate" : "ungate");
87− return 0;
89+ goto out_unlock;
8890 }
8991
90− mutex_lock(&adev->pm.mutex);
91−
9292 switch (block_type) {
9393 case AMD_IP_BLOCK_TYPE_UVD:
9494 case AMD_IP_BLOCK_TYPE_VCE:
@@ -115,6 +115,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, · 20 unmodified lines
115115 if (!ret)
116116 atomic_set(&adev->pm.pwr_state[block_type], pwr_state);
117117
118+out_unlock:
118119 mutex_unlock(&adev->pm.mutex);
119120
120121 return ret;
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+11−25
@@ -619,6 +619,9 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms · 618 unmodified lines
619619 struct smu_context *smu = adev->powerplay.pp_handle;
620620 int ret = -EOPNOTSUPP;
621621
622+ if (!smu)
623+ return ret;
624+
622625 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg)
623626 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg);
624627
@@ -688,12 +691,8 @@ static int smu_sys_set_pp_table(void *handle, · 63 unmodified lines
688691 return ret;
689692 }
690693
691−static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
694+static int smu_init_driver_allowed_feature_mask(struct smu_context *smu)
692695 {
693− struct smu_feature *feature = &smu->smu_feature;
694− uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
695− int ret = 0;
696−
697696 /*
698697 * With SCPM enabled, the allowed featuremasks setting(via
699698 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
@@ -702,22 +701,13 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) · 2 unmodified lines
702701 * such scenario.
703702 */
704703 if (smu->adev->scpm_enabled) {
705− bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
704+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
706705 return 0;
707706 }
708707
709− bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
708+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
710709
711− ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
712− SMU_FEATURE_MAX/32);
713− if (ret)
714− return ret;
715−
716− bitmap_or(feature->allowed, feature->allowed,
717− (unsigned long *)allowed_feature_mask,
718− feature->feature_num);
719−
720− return ret;
710+ return smu_init_allowed_features(smu);
721711 }
722712
723713 static int smu_set_funcs(struct amdgpu_device *adev)
@@ -1365,9 +1355,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) · 641 unmodified lines
13651355 int i, ret;
13661356
13671357 smu->pool_size = adev->pm.smu_prv_buffer_size;
1368− smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1369− bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1370− bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1358+ smu_feature_init(smu, SMU_FEATURE_MAX);
13711359
13721360 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
13731361 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
@@ -1656,7 +1644,6 @@ static void smu_wbrf_fini(struct smu_context *smu) · 282 unmodified lines
16561644
16571645 static int smu_smc_hw_setup(struct smu_context *smu)
16581646 {
1659− struct smu_feature *feature = &smu->smu_feature;
16601647 struct amdgpu_device *adev = smu->adev;
16611648 uint8_t pcie_gen = 0, pcie_width = 0;
16621649 uint64_t features_supported;
@@ -1819,9 +1806,8 @@ static int smu_smc_hw_setup(struct smu_context *smu) · 156 unmodified lines
18191806 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
18201807 return ret;
18211808 }
1822− bitmap_copy(feature->supported,
1823− (unsigned long *)&features_supported,
1824− feature->feature_num);
1809+ smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED,
1810+ (unsigned long *)&features_supported);
18251811
18261812 if (!smu_is_dpm_running(smu))
18271813 dev_info(adev->dev, "dpm has been disabled\n");
@@ -1952,7 +1938,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block) · 124 unmodified lines
19521938 if (!smu->pm_enabled)
19531939 return 0;
19541940
1955− ret = smu_get_driver_allowed_feature_mask(smu);
1941+ ret = smu_init_driver_allowed_feature_mask(smu);
19561942 if (ret)
19571943 return ret;
19581944
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h+169−6
@@ -472,10 +472,20 @@ struct smu_power_context { · 471 unmodified lines
472472 };
473473
474474 #define SMU_FEATURE_MAX (64)
475+
476+struct smu_feature_bits {
477+ DECLARE_BITMAP(bits, SMU_FEATURE_MAX);
478+};
479+
480+enum smu_feature_list {
481+ SMU_FEATURE_LIST_SUPPORTED,
482+ SMU_FEATURE_LIST_ALLOWED,
483+ SMU_FEATURE_LIST_MAX,
484+};
485+
475486 struct smu_feature {
476487 uint32_t feature_num;
477− DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
478− DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
488+ struct smu_feature_bits bits[SMU_FEATURE_LIST_MAX];
479489 };
480490
481491 struct smu_clocks {
@@ -802,11 +812,10 @@ struct pptable_funcs { · 320 unmodified lines
802812 int (*run_btc)(struct smu_context *smu);
803813
804814 /**
805− * @get_allowed_feature_mask: Get allowed feature mask.
806− * &feature_mask: Array to store feature mask.
807− * &num: Elements in &feature_mask.
815+ * @init_allowed_features: Initialize allowed features bitmap.
816+ * Directly sets allowed features using smu_feature wrapper functions.
808817 */
809− int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
818+ int (*init_allowed_features)(struct smu_context *smu);
810819
811820 /**
812821 * @get_current_power_state: Get the current power state.
@@ -1974,4 +1983,158 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms · 1161 unmodified lines
19741983
19751984 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id);
19761985 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id);
1986+
1987+static inline bool smu_feature_bits_is_set(const struct smu_feature_bits *bits,
1988+ unsigned int bit)
1989+{
1990+ if (bit >= SMU_FEATURE_MAX)
1991+ return false;
1992+
1993+ return test_bit(bit, bits->bits);
1994+}
1995+
1996+static inline void smu_feature_bits_set_bit(struct smu_feature_bits *bits,
1997+ unsigned int bit)
1998+{
1999+ if (bit < SMU_FEATURE_MAX)
2000+ __set_bit(bit, bits->bits);
2001+}
2002+
2003+static inline void smu_feature_bits_clear_bit(struct smu_feature_bits *bits,
2004+ unsigned int bit)
2005+{
2006+ if (bit < SMU_FEATURE_MAX)
2007+ __clear_bit(bit, bits->bits);
2008+}
2009+
2010+static inline void smu_feature_bits_clearall(struct smu_feature_bits *bits)
2011+{
2012+ bitmap_zero(bits->bits, SMU_FEATURE_MAX);
2013+}
2014+
2015+static inline void smu_feature_bits_fill(struct smu_feature_bits *bits)
2016+{
2017+ bitmap_fill(bits->bits, SMU_FEATURE_MAX);
2018+}
2019+
2020+static inline bool
2021+smu_feature_bits_test_mask(const struct smu_feature_bits *bits,
2022+ const unsigned long *mask)
2023+{
2024+ return bitmap_intersects(bits->bits, mask, SMU_FEATURE_MAX);
2025+}
2026+
2027+static inline void smu_feature_bits_from_arr32(struct smu_feature_bits *bits,
2028+ const uint32_t *arr,
2029+ unsigned int nbits)
2030+{
2031+ bitmap_from_arr32(bits->bits, arr, nbits);
2032+}
2033+
2034+static inline void
2035+smu_feature_bits_to_arr32(const struct smu_feature_bits *bits, uint32_t *arr,
2036+ unsigned int nbits)
2037+{
2038+ bitmap_to_arr32(arr, bits->bits, nbits);
2039+}
2040+
2041+static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits,
2042+ unsigned int nbits)
2043+{
2044+ return bitmap_empty(bits->bits, nbits);
2045+}
2046+
2047+static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,
2048+ const unsigned long *src,
2049+ unsigned int nbits)
2050+{
2051+ bitmap_copy(dst->bits, src, nbits);
2052+}
2053+
2054+static inline struct smu_feature_bits *
2055+__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list)
2056+{
2057+ if (unlikely(list >= SMU_FEATURE_LIST_MAX)) {
2058+ dev_warn(smu->adev->dev, "Invalid feature list: %d\n", list);
2059+ return &smu->smu_feature.bits[SMU_FEATURE_LIST_SUPPORTED];
2060+ }
2061+
2062+ return &smu->smu_feature.bits[list];
2063+}
2064+
2065+static inline bool smu_feature_list_is_set(struct smu_context *smu,
2066+ enum smu_feature_list list,
2067+ unsigned int bit)
2068+{
2069+ if (bit >= smu->smu_feature.feature_num)
2070+ return false;
2071+
2072+ return smu_feature_bits_is_set(__smu_feature_get_list(smu, list), bit);
2073+}
2074+
2075+static inline void smu_feature_list_set_bit(struct smu_context *smu,
2076+ enum smu_feature_list list,
2077+ unsigned int bit)
2078+{
2079+ if (bit >= smu->smu_feature.feature_num)
2080+ return;
2081+
2082+ smu_feature_bits_set_bit(__smu_feature_get_list(smu, list), bit);
2083+}
2084+
2085+static inline void smu_feature_list_clear_bit(struct smu_context *smu,
2086+ enum smu_feature_list list,
2087+ unsigned int bit)
2088+{
2089+ if (bit >= smu->smu_feature.feature_num)
2090+ return;
2091+
2092+ smu_feature_bits_clear_bit(__smu_feature_get_list(smu, list), bit);
2093+}
2094+
2095+static inline void smu_feature_list_set_all(struct smu_context *smu,
2096+ enum smu_feature_list list)
2097+{
2098+ smu_feature_bits_fill(__smu_feature_get_list(smu, list));
2099+}
2100+
2101+static inline void smu_feature_list_clear_all(struct smu_context *smu,
2102+ enum smu_feature_list list)
2103+{
2104+ smu_feature_bits_clearall(__smu_feature_get_list(smu, list));
2105+}
2106+
2107+static inline bool smu_feature_list_is_empty(struct smu_context *smu,
2108+ enum smu_feature_list list)
2109+{
2110+ return smu_feature_bits_empty(__smu_feature_get_list(smu, list),
2111+ smu->smu_feature.feature_num);
2112+}
2113+
2114+static inline void smu_feature_list_set_bits(struct smu_context *smu,
2115+ enum smu_feature_list dst_list,
2116+ const unsigned long *src)
2117+{
2118+ smu_feature_bits_copy(__smu_feature_get_list(smu, dst_list), src,
2119+ smu->smu_feature.feature_num);
2120+}
2121+
2122+static inline void smu_feature_list_to_arr32(struct smu_context *smu,
2123+ enum smu_feature_list list,
2124+ uint32_t *arr)
2125+{
2126+ smu_feature_bits_to_arr32(__smu_feature_get_list(smu, list), arr,
2127+ smu->smu_feature.feature_num);
2128+}
2129+
2130+static inline void smu_feature_init(struct smu_context *smu, int feature_num)
2131+{
2132+ if (!feature_num || smu->smu_feature.feature_num != 0)
2133+ return;
2134+
2135+ smu->smu_feature.feature_num = feature_num;
2136+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_SUPPORTED);
2137+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
2138+}
2139+
19772140 #endif
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h+1−0
@@ -55,6 +55,7 @@ · 54 unmodified lines
5555 #define SMUQ10_TO_UINT(x) ((x) >> 10)
5656 #define SMUQ10_FRAC(x) ((x) & 0x3ff)
5757 #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
58+#define SMU_V13_SOFT_FREQ_ROUND(x) ((x) + 1)
5859
5960 extern const int pmfw_decoded_link_speed[5];
6061 extern const int pmfw_decoded_link_width[7];
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h+1−0
@@ -56,6 +56,7 @@ extern const int decoded_link_width[8]; · 55 unmodified lines
5656
5757 #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx])
5858 #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx])
59+#define SMU_V14_SOFT_FREQ_ROUND(x) ((x) + 1)
5960
6061 struct smu_14_0_max_sustainable_clocks {
6162 uint32_t display_clock;
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c+3−8
@@ -345,14 +345,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu) · 344 unmodified lines
345345 }
346346
347347 static int
348−arcturus_get_allowed_feature_mask(struct smu_context *smu,
349− uint32_t *feature_mask, uint32_t num)
348+arcturus_init_allowed_features(struct smu_context *smu)
350349 {
351− if (num > 2)
352− return -EINVAL;
353−
354− /* pptable will handle the features to enable */
355− memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
350+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
356351
357352 return 0;
358353 }
@@ -1877,7 +1872,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, · 1518 unmodified lines
18771872
18781873 static const struct pptable_funcs arcturus_ppt_funcs = {
18791874 /* init dpm */
1880− .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1875+ .init_allowed_features = arcturus_init_allowed_features,
18811876 /* btc */
18821877 .run_btc = arcturus_run_btc,
18831878 /* dpm/clk tables */
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c+43−49
@@ -275,89 +275,83 @@ static bool is_asic_secure(struct smu_context *smu) · 274 unmodified lines
275275 }
276276
277277 static int
278−navi10_get_allowed_feature_mask(struct smu_context *smu,
279− uint32_t *feature_mask, uint32_t num)
278+navi10_init_allowed_features(struct smu_context *smu)
280279 {
281280 struct amdgpu_device *adev = smu->adev;
282281
283− if (num > 2)
284− return -EINVAL;
285−
286− memset(feature_mask, 0, sizeof(uint32_t) * num);
287−
288− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
289− | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
290− | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
291− | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
292− | FEATURE_MASK(FEATURE_PPT_BIT)
293− | FEATURE_MASK(FEATURE_TDC_BIT)
294− | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
295− | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
296− | FEATURE_MASK(FEATURE_VR0HOT_BIT)
297− | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
298− | FEATURE_MASK(FEATURE_THERMAL_BIT)
299− | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
300− | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
301− | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
302− | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
303− | FEATURE_MASK(FEATURE_BACO_BIT)
304− | FEATURE_MASK(FEATURE_GFX_SS_BIT)
305− | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
306− | FEATURE_MASK(FEATURE_FW_CTF_BIT)
307− | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
308− | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
282+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
283+
284+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);
285+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
286+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);
287+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
288+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);
289+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);
290+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT);
291+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT);
292+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
293+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
294+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);
295+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT);
296+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
297+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);
298+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
299+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
300+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);
301+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);
302+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
303+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);
304+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT);
309305
310306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
307+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
312308
313309 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
310+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
315311
316312 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
313+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);
318314
319315 if (adev->pm.pp_feature & PP_ULV_MASK)
320− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
316+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
321317
322318 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
319+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
324320
325321 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
322+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
327323
328324 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
325+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);
330326
331327 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
328+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);
333329
334330 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
331+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT);
336332
337333 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
334+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT);
339335
340336 if (smu->dc_controlled_by_gpio)
341− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
337+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);
342338
343339 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
340+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
345341
346− /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347342 if (!(is_asic_secure(smu) &&
348343 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
349344 (adev->rev_id == 0)) &&
350− (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352− | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353− | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
345+ (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
346+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
347+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
348+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
349+ }
354350
355− /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356351 if (is_asic_secure(smu) &&
357352 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
358353 (adev->rev_id == 0))
359− *(uint64_t *)feature_mask &=
360− ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
354+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
361355
362356 return 0;
363357 }
@@ -3277,7 +3271,7 @@ static int navi10_set_config_table(struct smu_context *smu, · 2913 unmodified lines
32773271 }
32783272
32793273 static const struct pptable_funcs navi10_ppt_funcs = {
3280− .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3274+ .init_allowed_features = navi10_init_allowed_features,
32813275 .set_default_dpm_table = navi10_set_default_dpm_table,
32823276 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
32833277 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+43−46
@@ -276,85 +276,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = { · 275 unmodified lines
276276 };
277277
278278 static int
279−sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
280− uint32_t *feature_mask, uint32_t num)
279+sienna_cichlid_init_allowed_features(struct smu_context *smu)
281280 {
282281 struct amdgpu_device *adev = smu->adev;
283282
284− if (num > 2)
285− return -EINVAL;
286−
287− memset(feature_mask, 0, sizeof(uint32_t) * num);
288−
289− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290− | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
291− | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
292− | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293− | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
294− | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
295− | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
296− | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
297− | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
298− | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
299− | FEATURE_MASK(FEATURE_GFX_SS_BIT)
300− | FEATURE_MASK(FEATURE_VR0HOT_BIT)
301− | FEATURE_MASK(FEATURE_PPT_BIT)
302− | FEATURE_MASK(FEATURE_TDC_BIT)
303− | FEATURE_MASK(FEATURE_BACO_BIT)
304− | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
305− | FEATURE_MASK(FEATURE_FW_CTF_BIT)
306− | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
307− | FEATURE_MASK(FEATURE_THERMAL_BIT)
308− | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
283+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
284+
285+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);
286+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
287+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
288+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
289+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);
290+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
291+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT);
292+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
293+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
294+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);
295+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);
296+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
297+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);
298+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);
299+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
300+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);
301+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
302+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
303+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);
304+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);
309305
310306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
311− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
307+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
308+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT);
313309 }
314310
315311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
316312 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
317313 !(adev->flags & AMD_IS_APU))
318− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
314+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT);
319315
320− if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
321− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
322− | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
323− | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
316+ if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
317+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
318+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
319+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
320+ }
324321
325322 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
326− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
327324
328325 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
329− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);
330327
331328 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
332− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
329+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
333330
334331 if (adev->pm.pp_feature & PP_ULV_MASK)
335− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
336333
337334 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
338− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
339336
340337 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
341− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
342339
343340 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
344− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);
345342
346343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
347− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);
348345
349346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350347 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
351− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT);
352349
353350 if (smu->dc_controlled_by_gpio)
354− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);
355352
356353 if (amdgpu_device_should_use_aspm(adev))
357− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
358355
359356 return 0;
360357 }
@@ -3085,7 +3082,7 @@ out: · 2724 unmodified lines
30853082 }
30863083
30873084 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3088− .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3085+ .init_allowed_features = sienna_cichlid_init_allowed_features,
30893086 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
30903087 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
30913088 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c+3−2
@@ -750,12 +750,13 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) · 749 unmodified lines
750750 int ret = 0;
751751 uint32_t feature_mask[2];
752752
753− if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
753+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
754+ feature->feature_num < 64) {
754755 ret = -EINVAL;
755756 goto failed;
756757 }
757758
758− bitmap_to_arr32(feature_mask, feature->allowed, 64);
759+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
759760
760761 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
761762 feature_mask[1], NULL);
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+3−8
@@ -329,14 +329,9 @@ static int aldebaran_init_smc_tables(struct smu_context *smu) · 328 unmodified lines
329329 return smu_v13_0_init_smc_tables(smu);
330330 }
331331
332−static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
333− uint32_t *feature_mask, uint32_t num)
332+static int aldebaran_init_allowed_features(struct smu_context *smu)
334333 {
335− if (num > 2)
336− return -EINVAL;
337−
338− /* pptable will handle the features to enable */
339− memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
334+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
340335
341336 return 0;
342337 }
@@ -1967,7 +1962,7 @@ static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, · 1624 unmodified lines
19671962
19681963 static const struct pptable_funcs aldebaran_ppt_funcs = {
19691964 /* init dpm */
1970− .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1965+ .init_allowed_features = aldebaran_init_allowed_features,
19711966 /* dpm/clk tables */
19721967 .set_default_dpm_table = aldebaran_set_default_dpm_table,
19731968 .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c+3−2
@@ -761,11 +761,11 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu) · 760 unmodified lines
761761 int ret = 0;
762762 uint32_t feature_mask[2];
763763
764− if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
764+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
765765 feature->feature_num < 64)
766766 return -EINVAL;
767767
768− bitmap_to_arr32(feature_mask, feature->allowed, 64);
768+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
769769
770770 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
771771 feature_mask[1], NULL);
@@ -1554,6 +1554,7 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, · 782 unmodified lines
15541554 return clk_id;
15551555
15561556 if (max > 0) {
1557+ max = SMU_V13_SOFT_FREQ_ROUND(max);
15571558 if (automatic)
15581559 param = (uint32_t)((clk_id << 16) | 0xffff);
15591560 else
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c+15−20
@@ -287,49 +287,44 @@ static const uint8_t smu_v13_0_0_throttler_map[] = { · 286 unmodified lines
287287 };
288288
289289 static int
290−smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
291− uint32_t *feature_mask, uint32_t num)
290+smu_v13_0_0_init_allowed_features(struct smu_context *smu)
292291 {
293292 struct amdgpu_device *adev = smu->adev;
294293
295− if (num > 2)
296− return -EINVAL;
297−
298− memset(feature_mask, 0xff, sizeof(uint32_t) * num);
294+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
299295
300296 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
301− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
302− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
297+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
298+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
303299 }
304300
305301 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
306302 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
307− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
303+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
308304
309305 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
310− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
306+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
311307
312− /* PMFW 78.58 contains a critical fix for gfxoff feature */
313308 if ((smu->smc_fw_version < 0x004e3a00) ||
314309 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
315− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
310+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
316311
317312 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
318− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
319− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
320− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
313+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
314+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
315+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
321316 }
322317
323318 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
324− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
319+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
325320
326321 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
327− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
328− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
322+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
323+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
329324 }
330325
331326 if (!(adev->pm.pp_feature & PP_ULV_MASK))
332− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
327+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
333328
334329 return 0;
335330 }
@@ -3130,7 +3125,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, · 2794 unmodified lines
31303125 }
31313126
31323127 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
3133− .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
3128+ .init_allowed_features = smu_v13_0_0_init_allowed_features,
31343129 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
31353130 .i2c_init = smu_v13_0_0_i2c_control_init,
31363131 .i2c_fini = smu_v13_0_0_i2c_control_fini,
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c+3−9
@@ -742,15 +742,9 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu) · 741 unmodified lines
742742 return smu_v13_0_fini_smc_tables(smu);
743743 }
744744
745−static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
746− uint32_t *feature_mask,
747− uint32_t num)
745+static int smu_v13_0_6_init_allowed_features(struct smu_context *smu)
748746 {
749− if (num > 2)
750− return -EINVAL;
751−
752− /* pptable will handle the features to enable */
753− memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
747+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
754748
755749 return 0;
756750 }
@@ -3836,7 +3830,7 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras · 3079 unmodified lines
38363830
38373831 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
38383832 /* init dpm */
3839− .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3833+ .init_allowed_features = smu_v13_0_6_init_allowed_features,
38403834 /* dpm/clk tables */
38413835 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
38423836 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c+38−42
@@ -265,71 +265,67 @@ static const uint8_t smu_v13_0_7_throttler_map[] = { · 264 unmodified lines
265265 };
266266
267267 static int
268−smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
269− uint32_t *feature_mask, uint32_t num)
268+smu_v13_0_7_init_allowed_features(struct smu_context *smu)
270269 {
271270 struct amdgpu_device *adev = smu->adev;
272271
273− if (num > 2)
274− return -EINVAL;
275−
276− memset(feature_mask, 0, sizeof(uint32_t) * num);
272+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
277273
278− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
274+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT);
279275
280276 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
281− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
282− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
283− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
277+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
278+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
279+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
284280 }
285281
286282 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
287− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
283+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
288284
289285 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
290− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
291− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
292− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
293− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
286+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
287+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
288+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
289+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
294290 }
295291
296− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
292+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
297293
298294 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
299− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
295+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
300296
301297 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
302− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
298+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
303299
304300 if (adev->pm.pp_feature & PP_ULV_MASK)
305− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
306−
307− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
308− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
309− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
310− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
311− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
312− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
313− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
314− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
315− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
316− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
317− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
318− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
319− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
320− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
321− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
322− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
323− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
324− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
325− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
301+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
302+
303+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
304+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
305+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT);
306+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT);
307+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
308+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
309+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT);
310+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
311+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
312+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
313+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
314+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
315+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT);
316+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
317+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT);
318+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT);
319+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT);
320+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT);
321+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
326322
327323 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
328− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
324+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT);
329325
330326 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
331327 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
332− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
328+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
333329
334330 return 0;
335331 }
@@ -2736,7 +2732,7 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, · 2400 unmodified lines
27362732 }
27372733
27382734 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
2739− .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
2735+ .init_allowed_features = smu_v13_0_7_init_allowed_features,
27402736 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
27412737 .is_dpm_running = smu_v13_0_7_is_dpm_running,
27422738 .init_microcode = smu_v13_0_init_microcode,
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c+3−2
@@ -746,11 +746,11 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu) · 745 unmodified lines
746746 int ret = 0;
747747 uint32_t feature_mask[2];
748748
749− if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
749+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
750750 feature->feature_num < 64)
751751 return -EINVAL;
752752
753− bitmap_to_arr32(feature_mask, feature->allowed, 64);
753+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
754754
755755 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
756756 feature_mask[1], NULL);
@@ -1177,6 +1177,7 @@ int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, · 420 unmodified lines
11771177 return clk_id;
11781178
11791179 if (max > 0) {
1180+ max = SMU_V14_SOFT_FREQ_ROUND(max);
11801181 if (automatic)
11811182 param = (uint32_t)((clk_id << 16) | 0xffff);
11821183 else
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c+3−47
@@ -264,53 +264,9 @@ static const uint8_t smu_v14_0_2_throttler_map[] = { · 263 unmodified lines
264264 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
265265 };
266266
267−static int
268−smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
269− uint32_t *feature_mask, uint32_t num)
267+static int smu_v14_0_2_init_allowed_features(struct smu_context *smu)
270268 {
271− struct amdgpu_device *adev = smu->adev;
272− /*u32 smu_version;*/
273−
274− if (num > 2)
275− return -EINVAL;
276−
277− memset(feature_mask, 0xff, sizeof(uint32_t) * num);
278−
279− if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
280− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
281− *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
282− }
283−#if 0
284− if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
285− !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
286− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
287−
288− if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
289− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
290−
291− /* PMFW 78.58 contains a critical fix for gfxoff feature */
292− smu_cmn_get_smc_version(smu, NULL, &smu_version);
293− if ((smu_version < 0x004e3a00) ||
294− !(adev->pm.pp_feature & PP_GFXOFF_MASK))
295− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
296−
297− if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
298− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
299− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
300− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
301− }
302−
303− if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
304− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
305−
306− if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
307− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
308− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
309− }
310−
311− if (!(adev->pm.pp_feature & PP_ULV_MASK))
312− *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
313−#endif
269+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
314270
315271 return 0;
316272 }
@@ -2796,7 +2752,7 @@ static int smu_v14_0_2_set_power_limit(struct smu_context *smu, · 2479 unmodified lines
27962752 }
27972753
27982754 static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
2799− .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask,
2755+ .init_allowed_features = smu_v14_0_2_init_allowed_features,
28002756 .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
28012757 .i2c_init = smu_v14_0_2_i2c_control_init,
28022758 .i2c_fini = smu_v14_0_2_i2c_control_fini,
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c+2−2
@@ -715,11 +715,11 @@ int smu_v15_0_set_allowed_mask(struct smu_context *smu) · 714 unmodified lines
715715 int ret = 0;
716716 uint32_t feature_mask[2];
717717
718− if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
718+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
719719 feature->feature_num < 64)
720720 return -EINVAL;
721721
722− bitmap_to_arr32(feature_mask, feature->allowed, 64);
722+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
723723
724724 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
725725 feature_mask[1], NULL);
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c+2−4
@@ -677,7 +677,6 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu, · 676 unmodified lines
677677 int smu_cmn_feature_is_supported(struct smu_context *smu,
678678 enum smu_feature_mask mask)
679679 {
680− struct smu_feature *feature = &smu->smu_feature;
681680 int feature_id;
682681
683682 feature_id = smu_cmn_to_asic_specific_index(smu,
@@ -686,9 +685,8 @@ int smu_cmn_feature_is_supported(struct smu_context *smu, · 2 unmodified lines
686685 if (feature_id < 0)
687686 return 0;
688687
689− WARN_ON(feature_id > feature->feature_num);
690−
691− return test_bit(feature_id, feature->supported);
688+ return smu_feature_list_is_set(smu, SMU_FEATURE_LIST_SUPPORTED,
689+ feature_id);
692690 }
693691
694692 static int __smu_get_enabled_features(struct smu_context *smu,
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h+1−1
@@ -70,7 +70,7 @@ · 69 unmodified lines
7070 #define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu)
7171 #define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu)
7272 #define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu)
73−#define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num)
73+#define smu_init_allowed_features(smu) smu_ppt_funcs(init_allowed_features, 0, smu)
7474 #define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
7575 #define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
7676 #define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu)
include/uapi/linux/kfd_ioctl.h+2−0
@@ -149,6 +149,8 @@ struct kfd_dbg_device_info_entry { · 148 unmodified lines
149149 __u32 num_xcc;
150150 __u32 capability;
151151 __u32 debug_prop;
152+ __u32 capability2;
153+ __u32 pad;
152154 };
153155
154156 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */