Merge tag 'xtensa-next-20141215' of git://github.com/czankel/xtensa-linux

Pull Xtensa fixes from Chris Zankel: - fix nommu support - remove s6000 variant and s6105 platform - fix permissions for kmapped pages so that copy_to_user_page works with them - add power management menu to Kconfig to allow use of runtime PM - disable linker optimizations because of a linker bug - fix sparse error * tag 'xtensa-next-20141215' of git://github.com/czankel/xtensa-linux: xtensa: disable link optimization xtensa/uaccess: fix sparse errors xtensa: fix kmap_prot definition xtensa: add power management menu to Kconfig xtensa: remove s6000 variant and s6105 platform xtensa: make PLATFORM_DEFAULT_MEM parameters configurable xtensa: nommu: clean up memory map dump xtensa: nommu: reserve memory below PLATFORM_DEFAULT_MEM_START xtensa: nommu: set up cache and atomctl in initialize_mmu xtensa: move vecbase SR initialization to _startup xtensa: nommu: fix uImage load address xtensa: nommu: fix load address definitions xtensa: nommu: fix Image.elf reset code and ld script xtensa: nommu: add MMU dependency to DEBUG_TLB_SANITY xtensa: nommu: don't build most of the cache flushing code xtensa: nommu: don't provide arch_get_unmapped_area xtensa: nommu: provide MAP_UNINITIALIZED definition xtensa: nommu: provide _PAGE_CHG_MASK definition xtensa: nommu: provide __invalidate_dcache_page_alias stub xtensa: nommu: move init_mmu stub to nommu_context.h

Linus Torvalds committed 11 years ago

Commit a643fc72 parents 0db2812 1f2fdbd41 files · +149 −3042Browse files

Unified · Split

41 files

arch/xtensa/Kconfig +42 −14
arch/xtensa/Kconfig.debug +2 −2
arch/xtensa/Makefile +0 −1
arch/xtensa/boot/boot-elf/boot.lds.S +2 −0
arch/xtensa/boot/boot-elf/bootstrap.S +4 −6
arch/xtensa/boot/boot-uboot/Makefile +4 −0
arch/xtensa/configs/iss_defconfig +1 −2
arch/xtensa/configs/s6105_defconfig +0 −615
arch/xtensa/include/asm/cacheflush.h +5 −2
arch/xtensa/include/asm/highmem.h +1 −1
arch/xtensa/include/asm/initialize_mmu.h +36 −4
arch/xtensa/include/asm/mmu_context.h +0 −4
arch/xtensa/include/asm/nommu_context.h +4 −0
arch/xtensa/include/asm/page.h +6 −6
arch/xtensa/include/asm/pgtable.h +1 −0
arch/xtensa/include/asm/uaccess.h +2 −2
arch/xtensa/include/asm/vectors.h +4 −3
arch/xtensa/include/uapi/asm/mman.h +6 −0
arch/xtensa/kernel/head.S +5 −0
arch/xtensa/kernel/syscall.c +2 −0
arch/xtensa/mm/Makefile +2 −2
arch/xtensa/mm/init.c +18 −1
arch/xtensa/platforms/s6105/Makefile +0 −3
arch/xtensa/platforms/s6105/device.c +0 −161
arch/xtensa/platforms/s6105/include/platform/gpio.h +0 −27
arch/xtensa/platforms/s6105/include/platform/hardware.h +0 −11
arch/xtensa/platforms/s6105/include/platform/serial.h +0 −8
arch/xtensa/platforms/s6105/setup.c +0 −73
arch/xtensa/platforms/xtfpga/include/platform/hardware.h +2 −2
arch/xtensa/variants/s6000/Makefile +0 −4
arch/xtensa/variants/s6000/delay.c +0 −25
arch/xtensa/variants/s6000/dmac.c +0 −173
arch/xtensa/variants/s6000/gpio.c +0 −230
arch/xtensa/variants/s6000/include/variant/core.h +0 −431
arch/xtensa/variants/s6000/include/variant/dmac.h +0 −387
arch/xtensa/variants/s6000/include/variant/gpio.h +0 −6
arch/xtensa/variants/s6000/include/variant/hardware.h +0 −259
arch/xtensa/variants/s6000/include/variant/irq.h +0 −8
arch/xtensa/variants/s6000/include/variant/tie-asm.h +0 −304
arch/xtensa/variants/s6000/include/variant/tie.h +0 −191
arch/xtensa/variants/s6000/irq.c +0 −74

arch/xtensa/Kconfig+42−14

@@ -98,12 +98,6 @@ config XTENSA_VARIANT_DC233C · 97 unmodified lines
98	98	help
99	99	This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
100	100
101		−config XTENSA_VARIANT_S6000
102		− bool "s6000 - Stretch software configurable processor"
103		− select VARIANT_IRQ_SWITCH
104		− select ARCH_REQUIRE_GPIOLIB
105		− select XTENSA_CALIBRATE_CCOUNT
106		−
107	101	config XTENSA_VARIANT_CUSTOM
108	102	bool "Custom Xtensa processor configuration"
109	103	select MAY_HAVE_SMP
@@ -126,7 +120,6 @@ config XTENSA_VARIANT_NAME · 16 unmodified lines
126	120	default "dc232b" if XTENSA_VARIANT_DC232B
127	121	default "dc233c" if XTENSA_VARIANT_DC233C
128	122	default "fsf" if XTENSA_VARIANT_FSF
129		− default "s6000" if XTENSA_VARIANT_S6000
130	123	default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
131	124
132	125	config XTENSA_VARIANT_MMU
@@ -191,7 +184,6 @@ config HOTPLUG_CPU · 58 unmodified lines
191	184
192	185	config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
193	186	bool "Initialize Xtensa MMU inside the Linux kernel code"
194		− depends on MMU
195	187	default y
196	188	help
197	189	Earlier version initialized the MMU in the exception vector
@@ -311,15 +303,10 @@ config XTENSA_PLATFORM_XT2000 · 113 unmodified lines
311	303	XT2000 is the name of Tensilica's feature-rich emulation platform.
312	304	This hardware is capable of running a full Linux distribution.
313	305
314		−config XTENSA_PLATFORM_S6105
315		− bool "S6105"
316		− select HAVE_IDE
317		− select SERIAL_CONSOLE
318		− select NO_IOPORT_MAP
319		−
320	306	config XTENSA_PLATFORM_XTFPGA
321	307	bool "XTFPGA"
322	308	select ETHOC if ETHERNET
	309	+ select PLATFORM_WANT_DEFAULT_MEM
323	310	select SERIAL_CONSOLE
324	311	select XTENSA_CALIBRATE_CCOUNT
325	312	help
@@ -406,6 +393,41 @@ source "drivers/pcmcia/Kconfig" · 80 unmodified lines
406	393
407	394	source "drivers/pci/hotplug/Kconfig"
408	395
	396	+config PLATFORM_WANT_DEFAULT_MEM
	397	+ def_bool n
	398	+
	399	+config DEFAULT_MEM_START
	400	+ hex "Physical address of the default memory area start"
	401	+ depends on PLATFORM_WANT_DEFAULT_MEM
	402	+ default 0x00000000 if MMU
	403	+ default 0x40000000 if !MMU
	404	+ help
	405	+ This is a fallback start address of the default memory area, it is
	406	+ used when no physical memory size is passed through DTB or through
	407	+ boot parameter from bootloader.
	408	+
	409	+ In noMMU configuration the following parameters are derived from it:
	410	+ - kernel load address;
	411	+ - kernel entry point address;
	412	+ - relocatable vectors base address;
	413	+ - uBoot load address;
	414	+ - TASK_SIZE.
	415	+
	416	+ If unsure, leave the default value here.
	417	+
	418	+config DEFAULT_MEM_SIZE
	419	+ hex "Maximal size of the default memory area"
	420	+ depends on PLATFORM_WANT_DEFAULT_MEM
	421	+ default 0x04000000
	422	+ help
	423	+ This is a fallback size of the default memory area, it is used when
	424	+ no physical memory size is passed through DTB or through boot
	425	+ parameter from bootloader.
	426	+
	427	+ It's also used for TASK_SIZE calculation in noMMU configuration.
	428	+
	429	+ If unsure, leave the default value here.
	430	+
409	431	endmenu
410	432
411	433	menu "Executable file formats"
@@ -414,6 +436,12 @@ source "fs/Kconfig.binfmt" · 2 unmodified lines
414	436
415	437	endmenu
416	438
	439	+menu "Power management options"
	440	+
	441	+source "kernel/power/Kconfig"
	442	+
	443	+endmenu
	444	+
417	445	source "net/Kconfig"
418	446
419	447	source "drivers/Kconfig"

arch/xtensa/Kconfig.debug+2−2

@@ -4,7 +4,7 @@ source "lib/Kconfig.debug" · 3 unmodified lines
4	4
5	5	config DEBUG_TLB_SANITY
6	6	bool "Debug TLB sanity"
7		− depends on DEBUG_KERNEL
	7	+ depends on DEBUG_KERNEL && MMU
8	8	help
9	9	Enable this to turn on TLB sanity check on each entry to userspace.
10	10	This check can spot missing TLB invalidation/wrong PTE permissions/
@@ -14,7 +14,7 @@ config DEBUG_TLB_SANITY · 3 unmodified lines
14	14
15	15	config LD_NO_RELAX
16	16	bool "Disable linker relaxation"
17		− default n
	17	+ default y
18	18	help
19	19	Enable this function to disable link-time optimizations.
20	20	The default linker behavior is to combine identical literal

arch/xtensa/Makefile+0−1

@@ -35,7 +35,6 @@ endif · 34 unmodified lines
35	35
36	36	platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000
37	37	platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss
38		−platform-$(CONFIG_XTENSA_PLATFORM_S6105) := s6105
39	38	platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA) := xtfpga
40	39
41	40	PLATFORM = $(platform-y)

arch/xtensa/boot/boot-elf/boot.lds.S+2−0

@@ -41,6 +41,7 @@ SECTIONS · 40 unmodified lines
41	41	__bss_end = .;
42	42	}
43	43
	44	+#ifdef CONFIG_MMU
44	45	/*
45	46	* This is a remapped copy of the Reset Vector Code.
46	47	* It keeps gdb in sync with the PC after switching
@@ -51,4 +52,5 @@ SECTIONS · 4 unmodified lines
51	52	{
52	53	*(.ResetVector.remapped_text)
53	54	}
	55	+#endif
54	56	}

arch/xtensa/boot/boot-elf/bootstrap.S+4−6

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	20	#include <asm/page.h>
21	21	#include <asm/cacheasm.h>
22	22	#include <asm/initialize_mmu.h>
	23	+#include <asm/vectors.h>
23	24	#include <linux/linkage.h>
24	25
25	26	.section .ResetVector.text, "ax"
@@ -34,12 +35,7 @@ _ResetVector: · 8 unmodified lines
34	35
35	36	.align 4
36	37	RomInitAddr:
37		−#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \
38		− XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
39		− .word 0x00003000
40		−#else
41		− .word 0xd0003000
42		−#endif
	38	+ .word LOAD_MEMORY_ADDRESS
43	39	RomBootParam:
44	40	.word _bootparam
45	41	_bootparam:
@@ -79,6 +75,7 @@ reset: · 33 unmodified lines
79	75	movi a4, 0
80	76	jx a0
81	77
	78	+#ifdef CONFIG_MMU
82	79	.align 4
83	80
84	81	.section .ResetVector.remapped_text, "x"
@@ -102,3 +99,4 @@ _RemappedSetupMMU: · 17 unmodified lines
102	99	#endif
103	100
104	101	.end no-absolute-literals
	102	+#endif

arch/xtensa/boot/boot-uboot/Makefile+4−0

@@ -4,11 +4,15 @@ · 3 unmodified lines
4	4	# for more details.
5	5	#
6	6
	7	+ifdef CONFIG_MMU
7	8	ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
8	9	UIMAGE_LOADADDR = 0x00003000
9	10	else
10	11	UIMAGE_LOADADDR = 0xd0003000
11	12	endif
	13	+else
	14	+UIMAGE_LOADADDR = $(shell printf "0x%x" $$(( ${CONFIG_DEFAULT_MEM_START} + 0x3000 )) )
	15	+endif
12	16	UIMAGE_COMPRESSION = gzip
13	17
14	18	$(obj)/../uImage: vmlinux.bin.gz FORCE

arch/xtensa/configs/iss_defconfig+1−2

@@ -143,7 +143,6 @@ CONFIG_MMU=y · 142 unmodified lines
143	143	#
144	144	CONFIG_XTENSA_VARIANT_FSF=y
145	145	# CONFIG_XTENSA_VARIANT_DC232B is not set
146		−# CONFIG_XTENSA_VARIANT_S6000 is not set
147	146	# CONFIG_XTENSA_UNALIGNED_USER is not set
148	147	# CONFIG_PREEMPT is not set
149	148	CONFIG_XTENSA_CALIBRATE_CCOUNT=y
@@ -161,7 +160,6 @@ CONFIG_XTENSA_ISS_NETWORK=y · 11 unmodified lines
161	160	#
162	161	CONFIG_XTENSA_PLATFORM_ISS=y
163	162	# CONFIG_XTENSA_PLATFORM_XT2000 is not set
164		−# CONFIG_XTENSA_PLATFORM_S6105 is not set
165	163	# CONFIG_GENERIC_CALIBRATE_DELAY is not set
166	164	CONFIG_CMDLINE_BOOL=y
167	165	CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target"
@@ -759,3 +757,4 @@ CONFIG_GENERIC_FIND_LAST_BIT=y · 591 unmodified lines
759	757	CONFIG_HAS_IOMEM=y
760	758	CONFIG_HAS_DMA=y
761	759	CONFIG_NLATTR=y
	760	+CONFIG_LD_NO_RELAX=y

arch/xtensa/configs/s6105_defconfig+0−615

@@ -1,615 +0,0 @@
1		−#
2		−# Automatically generated make config: don't edit
3		−# Linux kernel version: 2.6.29-rc7-s6
4		−# Tue Mar 10 11:09:26 2009
5		−#
6		−# CONFIG_FRAME_POINTER is not set
7		−CONFIG_ZONE_DMA=y
8		−CONFIG_XTENSA=y
9		−CONFIG_RWSEM_XCHGADD_ALGORITHM=y
10		−CONFIG_GENERIC_FIND_NEXT_BIT=y
11		−CONFIG_GENERIC_HWEIGHT=y
12		−# CONFIG_ARCH_HAS_ILOG2_U32 is not set
13		−# CONFIG_ARCH_HAS_ILOG2_U64 is not set
14		−CONFIG_NO_IOPORT_MAP=y
15		−CONFIG_HZ=100
16		−CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
17		−
18		−#
19		−# General setup
20		−#
21		−CONFIG_EXPERIMENTAL=y
22		−CONFIG_BROKEN_ON_SMP=y
23		−CONFIG_INIT_ENV_ARG_LIMIT=32
24		−CONFIG_LOCALVERSION=""
25		−CONFIG_LOCALVERSION_AUTO=y
26		−CONFIG_SYSVIPC=y
27		−CONFIG_SYSVIPC_SYSCTL=y
28		−# CONFIG_POSIX_MQUEUE is not set
29		−# CONFIG_BSD_PROCESS_ACCT is not set
30		−# CONFIG_TASKSTATS is not set
31		−# CONFIG_AUDIT is not set
32		−
33		−#
34		−# RCU Subsystem
35		−#
36		−# CONFIG_CLASSIC_RCU is not set
37		−# CONFIG_TREE_RCU is not set
38		−CONFIG_PREEMPT_RCU=y
39		−# CONFIG_RCU_TRACE is not set
40		−# CONFIG_TREE_RCU_TRACE is not set
41		−# CONFIG_PREEMPT_RCU_TRACE is not set
42		−CONFIG_IKCONFIG=y
43		−CONFIG_IKCONFIG_PROC=y
44		−CONFIG_LOG_BUF_SHIFT=16
45		−# CONFIG_GROUP_SCHED is not set
46		−# CONFIG_CGROUPS is not set
47		−# CONFIG_SYSFS_DEPRECATED_V2 is not set
48		−# CONFIG_RELAY is not set
49		−# CONFIG_NAMESPACES is not set
50		−CONFIG_BLK_DEV_INITRD=y
51		−CONFIG_INITRAMFS_SOURCE=""
52		−CONFIG_CC_OPTIMIZE_FOR_SIZE=y
53		−CONFIG_SYSCTL=y
54		−CONFIG_EXPERT=y
55		−CONFIG_SYSCTL_SYSCALL=y
56		−CONFIG_KALLSYMS=y
57		−# CONFIG_KALLSYMS_ALL is not set
58		−# CONFIG_KALLSYMS_EXTRA_PASS is not set
59		−# CONFIG_HOTPLUG is not set
60		−CONFIG_PRINTK=y
61		−CONFIG_BUG=y
62		−CONFIG_ELF_CORE=y
63		−# CONFIG_COMPAT_BRK is not set
64		−CONFIG_BASE_FULL=y
65		−CONFIG_FUTEX=y
66		−CONFIG_ANON_INODES=y
67		−CONFIG_EPOLL=y
68		−CONFIG_SIGNALFD=y
69		−CONFIG_TIMERFD=y
70		−CONFIG_EVENTFD=y
71		−CONFIG_AIO=y
72		−CONFIG_VM_EVENT_COUNTERS=y
73		−CONFIG_SLAB=y
74		−# CONFIG_SLUB is not set
75		−# CONFIG_SLOB is not set
76		−# CONFIG_PROFILING is not set
77		−# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
78		−CONFIG_SLABINFO=y
79		−CONFIG_RT_MUTEXES=y
80		−CONFIG_BASE_SMALL=0
81		−# CONFIG_MODULES is not set
82		−CONFIG_BLOCK=y
83		−# CONFIG_LBD is not set
84		−# CONFIG_BLK_DEV_IO_TRACE is not set
85		−# CONFIG_BLK_DEV_BSG is not set
86		−# CONFIG_BLK_DEV_INTEGRITY is not set
87		−
88		−#
89		−# IO Schedulers
90		−#
91		−CONFIG_IOSCHED_NOOP=y
92		−# CONFIG_IOSCHED_AS is not set
93		−# CONFIG_IOSCHED_DEADLINE is not set
94		−CONFIG_IOSCHED_CFQ=y
95		−# CONFIG_DEFAULT_AS is not set
96		−# CONFIG_DEFAULT_DEADLINE is not set
97		−CONFIG_DEFAULT_CFQ=y
98		−# CONFIG_DEFAULT_NOOP is not set
99		−CONFIG_DEFAULT_IOSCHED="cfq"
100		−# CONFIG_FREEZER is not set
101		−# CONFIG_MMU is not set
102		−CONFIG_VARIANT_IRQ_SWITCH=y
103		−
104		−#
105		−# Processor type and features
106		−#
107		−# CONFIG_XTENSA_VARIANT_FSF is not set
108		−# CONFIG_XTENSA_VARIANT_DC232B is not set
109		−CONFIG_XTENSA_VARIANT_S6000=y
110		−# CONFIG_XTENSA_UNALIGNED_USER is not set
111		−CONFIG_PREEMPT=y
112		−# CONFIG_HIGHMEM is not set
113		−CONFIG_XTENSA_CALIBRATE_CCOUNT=y
114		−CONFIG_SERIAL_CONSOLE=y
115		−# CONFIG_XTENSA_ISS_NETWORK is not set
116		−
117		−#
118		−# Bus options
119		−#
120		−# CONFIG_PCI is not set
121		−# CONFIG_ARCH_SUPPORTS_MSI is not set
122		−
123		−#
124		−# Platform options
125		−#
126		−# CONFIG_XTENSA_PLATFORM_ISS is not set
127		−# CONFIG_XTENSA_PLATFORM_XT2000 is not set
128		−CONFIG_XTENSA_PLATFORM_S6105=y
129		−CONFIG_GENERIC_CALIBRATE_DELAY=y
130		−CONFIG_CMDLINE_BOOL=y
131		−CONFIG_CMDLINE="console=ttyS1,38400 debug bootmem_debug loglevel=7"
132		−CONFIG_SELECT_MEMORY_MODEL=y
133		−CONFIG_FLATMEM_MANUAL=y
134		−# CONFIG_DISCONTIGMEM_MANUAL is not set
135		−# CONFIG_SPARSEMEM_MANUAL is not set
136		−CONFIG_FLATMEM=y
137		−CONFIG_FLAT_NODE_MEM_MAP=y
138		−CONFIG_PAGEFLAGS_EXTENDED=y
139		−CONFIG_SPLIT_PTLOCK_CPUS=4
140		−# CONFIG_PHYS_ADDR_T_64BIT is not set
141		−CONFIG_ZONE_DMA_FLAG=1
142		−CONFIG_VIRT_TO_BUS=y
143		−
144		−#
145		−# Executable file formats
146		−#
147		−CONFIG_KCORE_ELF=y
148		−CONFIG_BINFMT_FLAT=y
149		−# CONFIG_BINFMT_ZFLAT is not set
150		−# CONFIG_BINFMT_SHARED_FLAT is not set
151		−# CONFIG_HAVE_AOUT is not set
152		−# CONFIG_BINFMT_MISC is not set
153		−CONFIG_NET=y
154		−
155		−#
156		−# Networking options
157		−#
158		−CONFIG_COMPAT_NET_DEV_OPS=y
159		−CONFIG_PACKET=y
160		−# CONFIG_PACKET_MMAP is not set
161		−CONFIG_UNIX=y
162		−# CONFIG_NET_KEY is not set
163		−CONFIG_INET=y
164		−# CONFIG_IP_MULTICAST is not set
165		−# CONFIG_IP_ADVANCED_ROUTER is not set
166		−CONFIG_IP_FIB_HASH=y
167		−# CONFIG_IP_PNP is not set
168		−# CONFIG_NET_IPIP is not set
169		−# CONFIG_NET_IPGRE is not set
170		−# CONFIG_ARPD is not set
171		−# CONFIG_SYN_COOKIES is not set
172		−# CONFIG_INET_AH is not set
173		−# CONFIG_INET_ESP is not set
174		−# CONFIG_INET_IPCOMP is not set
175		−# CONFIG_INET_XFRM_TUNNEL is not set
176		−# CONFIG_INET_TUNNEL is not set
177		−# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
178		−# CONFIG_INET_XFRM_MODE_TUNNEL is not set
179		−# CONFIG_INET_XFRM_MODE_BEET is not set
180		−# CONFIG_INET_LRO is not set
181		−# CONFIG_INET_DIAG is not set
182		−# CONFIG_TCP_CONG_ADVANCED is not set
183		−CONFIG_TCP_CONG_CUBIC=y
184		−CONFIG_DEFAULT_TCP_CONG="cubic"
185		−# CONFIG_TCP_MD5SIG is not set
186		−# CONFIG_IPV6 is not set
187		−# CONFIG_NETWORK_SECMARK is not set
188		−# CONFIG_NETFILTER is not set
189		−# CONFIG_IP_DCCP is not set
190		−# CONFIG_IP_SCTP is not set
191		−# CONFIG_TIPC is not set
192		−# CONFIG_ATM is not set
193		−# CONFIG_BRIDGE is not set
194		−# CONFIG_NET_DSA is not set
195		−# CONFIG_VLAN_8021Q is not set
196		−# CONFIG_DECNET is not set
197		−# CONFIG_LLC2 is not set
198		−# CONFIG_IPX is not set
199		−# CONFIG_ATALK is not set
200		−# CONFIG_X25 is not set
201		−# CONFIG_LAPB is not set
202		−# CONFIG_ECONET is not set
203		−# CONFIG_WAN_ROUTER is not set
204		−# CONFIG_NET_SCHED is not set
205		−# CONFIG_DCB is not set
206		−
207		−#
208		−# Network testing
209		−#
210		−# CONFIG_NET_PKTGEN is not set
211		−# CONFIG_HAMRADIO is not set
212		−# CONFIG_CAN is not set
213		−# CONFIG_IRDA is not set
214		−# CONFIG_BT is not set
215		−# CONFIG_AF_RXRPC is not set
216		−# CONFIG_PHONET is not set
217		−# CONFIG_WIRELESS is not set
218		−# CONFIG_WIMAX is not set
219		−# CONFIG_RFKILL is not set
220		−# CONFIG_NET_9P is not set
221		−
222		−#
223		−# Device Drivers
224		−#
225		−
226		−#
227		−# Generic Driver Options
228		−#
229		−CONFIG_STANDALONE=y
230		−CONFIG_PREVENT_FIRMWARE_BUILD=y
231		−# CONFIG_DEBUG_DRIVER is not set
232		−# CONFIG_DEBUG_DEVRES is not set
233		−# CONFIG_SYS_HYPERVISOR is not set
234		−# CONFIG_CONNECTOR is not set
235		−# CONFIG_MTD is not set
236		−# CONFIG_PARPORT is not set
237		−CONFIG_BLK_DEV=y
238		−# CONFIG_BLK_DEV_COW_COMMON is not set
239		−# CONFIG_BLK_DEV_LOOP is not set
240		−# CONFIG_BLK_DEV_NBD is not set
241		−CONFIG_BLK_DEV_RAM=y
242		−CONFIG_BLK_DEV_RAM_COUNT=16
243		−CONFIG_BLK_DEV_RAM_SIZE=4096
244		−# CONFIG_BLK_DEV_XIP is not set
245		−# CONFIG_CDROM_PKTCDVD is not set
246		−# CONFIG_ATA_OVER_ETH is not set
247		−# CONFIG_BLK_DEV_HD is not set
248		−# CONFIG_MISC_DEVICES is not set
249		−CONFIG_HAVE_IDE=y
250		−# CONFIG_IDE is not set
251		−
252		−#
253		−# SCSI device support
254		−#
255		−# CONFIG_RAID_ATTRS is not set
256		−# CONFIG_SCSI is not set
257		−# CONFIG_SCSI_DMA is not set
258		−# CONFIG_SCSI_NETLINK is not set
259		−# CONFIG_ATA is not set
260		−# CONFIG_MD is not set
261		−CONFIG_NETDEVICES=y
262		−# CONFIG_DUMMY is not set
263		−# CONFIG_BONDING is not set
264		−# CONFIG_MACVLAN is not set
265		−# CONFIG_EQUALIZER is not set
266		−# CONFIG_TUN is not set
267		−# CONFIG_VETH is not set
268		−CONFIG_PHYLIB=y
269		−
270		−#
271		−# MII PHY device drivers
272		−#
273		−# CONFIG_MARVELL_PHY is not set
274		−# CONFIG_DAVICOM_PHY is not set
275		−# CONFIG_QSEMI_PHY is not set
276		−# CONFIG_LXT_PHY is not set
277		−# CONFIG_CICADA_PHY is not set
278		−# CONFIG_VITESSE_PHY is not set
279		−CONFIG_SMSC_PHY=y
280		−# CONFIG_BROADCOM_PHY is not set
281		−# CONFIG_ICPLUS_PHY is not set
282		−# CONFIG_REALTEK_PHY is not set
283		−# CONFIG_NATIONAL_PHY is not set
284		−# CONFIG_STE10XP is not set
285		−# CONFIG_LSI_ET1011C_PHY is not set
286		−# CONFIG_FIXED_PHY is not set
287		−# CONFIG_MDIO_BITBANG is not set
288		−# CONFIG_NET_ETHERNET is not set
289		−CONFIG_NETDEV_1000=y
290		−CONFIG_S6GMAC=y
291		−# CONFIG_NETDEV_10000 is not set
292		−
293		−#
294		−# Wireless LAN
295		−#
296		−# CONFIG_WLAN_PRE80211 is not set
297		−# CONFIG_WLAN_80211 is not set
298		−# CONFIG_IWLWIFI_LEDS is not set
299		−
300		−#
301		−# Enable WiMAX (Networking options) to see the WiMAX drivers
302		−#
303		−# CONFIG_WAN is not set
304		−# CONFIG_PPP is not set
305		−# CONFIG_SLIP is not set
306		−# CONFIG_NETCONSOLE is not set
307		−# CONFIG_NETPOLL is not set
308		−# CONFIG_NET_POLL_CONTROLLER is not set
309		−# CONFIG_ISDN is not set
310		−# CONFIG_PHONE is not set
311		−
312		−#
313		−# Input device support
314		−#
315		−# CONFIG_INPUT is not set
316		−
317		−#
318		−# Hardware I/O ports
319		−#
320		−# CONFIG_SERIO is not set
321		−# CONFIG_GAMEPORT is not set
322		−
323		−#
324		−# Character devices
325		−#
326		−# CONFIG_VT is not set
327		−# CONFIG_DEVKMEM is not set
328		−# CONFIG_SERIAL_NONSTANDARD is not set
329		−
330		−#
331		−# Serial drivers
332		−#
333		−CONFIG_SERIAL_8250=y
334		−CONFIG_SERIAL_8250_CONSOLE=y
335		−CONFIG_SERIAL_8250_NR_UARTS=2
336		−CONFIG_SERIAL_8250_RUNTIME_UARTS=2
337		−# CONFIG_SERIAL_8250_EXTENDED is not set
338		−
339		−#
340		−# Non-8250 serial port support
341		−#
342		−CONFIG_SERIAL_CORE=y
343		−CONFIG_SERIAL_CORE_CONSOLE=y
344		−CONFIG_UNIX98_PTYS=y
345		−# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
346		−# CONFIG_LEGACY_PTYS is not set
347		−# CONFIG_IPMI_HANDLER is not set
348		−# CONFIG_HW_RANDOM is not set
349		−# CONFIG_R3964 is not set
350		−# CONFIG_RAW_DRIVER is not set
351		−# CONFIG_TCG_TPM is not set
352		−# CONFIG_I2C is not set
353		−# CONFIG_SPI is not set
354		−CONFIG_ARCH_REQUIRE_GPIOLIB=y
355		−CONFIG_GPIOLIB=y
356		−# CONFIG_DEBUG_GPIO is not set
357		−# CONFIG_GPIO_SYSFS is not set
358		−
359		−#
360		−# Memory mapped GPIO expanders:
361		−#
362		−
363		−#
364		−# I2C GPIO expanders:
365		−#
366		−
367		−#
368		−# PCI GPIO expanders:
369		−#
370		−
371		−#
372		−# SPI GPIO expanders:
373		−#
374		−# CONFIG_W1 is not set
375		−# CONFIG_POWER_SUPPLY is not set
376		−# CONFIG_HWMON is not set
377		−# CONFIG_THERMAL is not set
378		−# CONFIG_THERMAL_HWMON is not set
379		−# CONFIG_WATCHDOG is not set
380		−CONFIG_SSB_POSSIBLE=y
381		−
382		−#
383		−# Sonics Silicon Backplane
384		−#
385		−# CONFIG_SSB is not set
386		−
387		−#
388		−# Multifunction device drivers
389		−#
390		−# CONFIG_MFD_CORE is not set
391		−# CONFIG_MFD_SM501 is not set
392		−# CONFIG_HTC_PASIC3 is not set
393		−# CONFIG_MFD_TMIO is not set
394		−# CONFIG_REGULATOR is not set
395		−
396		−#
397		−# Multimedia devices
398		−#
399		−
400		−#
401		−# Multimedia core support
402		−#
403		−# CONFIG_VIDEO_DEV is not set
404		−# CONFIG_DVB_CORE is not set
405		−# CONFIG_VIDEO_MEDIA is not set
406		−
407		−#
408		−# Multimedia drivers
409		−#
410		−# CONFIG_DAB is not set
411		−
412		−#
413		−# Graphics support
414		−#
415		−# CONFIG_VGASTATE is not set
416		−# CONFIG_VIDEO_OUTPUT_CONTROL is not set
417		−# CONFIG_FB is not set
418		−# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
419		−
420		−#
421		−# Display device support
422		−#
423		−# CONFIG_DISPLAY_SUPPORT is not set
424		−# CONFIG_SOUND is not set
425		−# CONFIG_USB_SUPPORT is not set
426		−# CONFIG_MMC is not set
427		−# CONFIG_MEMSTICK is not set
428		−# CONFIG_NEW_LEDS is not set
429		−# CONFIG_ACCESSIBILITY is not set
430		−CONFIG_RTC_LIB=y
431		−CONFIG_RTC_CLASS=y
432		−CONFIG_RTC_HCTOSYS=y
433		−CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
434		−# CONFIG_RTC_DEBUG is not set
435		−
436		−#
437		−# RTC interfaces
438		−#
439		−# CONFIG_RTC_INTF_SYSFS is not set
440		−# CONFIG_RTC_INTF_PROC is not set
441		−# CONFIG_RTC_INTF_DEV is not set
442		−# CONFIG_RTC_DRV_TEST is not set
443		−
444		−#
445		−# I2C RTC drivers
446		−#
447		−# CONFIG_RTC_DRV_DS1307 is not set
448		−# CONFIG_RTC_DRV_DS1374 is not set
449		−# CONFIG_RTC_DRV_DS1672 is not set
450		−# CONFIG_RTC_DRV_MAX6900 is not set
451		−# CONFIG_RTC_DRV_RS5C372 is not set
452		−# CONFIG_RTC_DRV_ISL1208 is not set
453		−# CONFIG_RTC_DRV_X1205 is not set
454		−# CONFIG_RTC_DRV_PCF8563 is not set
455		−# CONFIG_RTC_DRV_PCF8583 is not set
456		−CONFIG_RTC_DRV_M41T80=y
457		−# CONFIG_RTC_DRV_M41T80_WDT is not set
458		−# CONFIG_RTC_DRV_S35390A is not set
459		−# CONFIG_RTC_DRV_FM3130 is not set
460		−# CONFIG_RTC_DRV_RX8581 is not set
461		−
462		−#
463		−# SPI RTC drivers
464		−#
465		−
466		−#
467		−# Platform RTC drivers
468		−#
469		−# CONFIG_RTC_DRV_DS1286 is not set
470		−# CONFIG_RTC_DRV_DS1511 is not set
471		−# CONFIG_RTC_DRV_DS1553 is not set
472		−# CONFIG_RTC_DRV_DS1742 is not set
473		−# CONFIG_RTC_DRV_STK17TA8 is not set
474		−# CONFIG_RTC_DRV_M48T86 is not set
475		−# CONFIG_RTC_DRV_M48T35 is not set
476		−# CONFIG_RTC_DRV_M48T59 is not set
477		−# CONFIG_RTC_DRV_BQ4802 is not set
478		−# CONFIG_RTC_DRV_V3020 is not set
479		−
480		−#
481		−# on-CPU RTC drivers
482		−#
483		−# CONFIG_DMADEVICES is not set
484		−# CONFIG_UIO is not set
485		−# CONFIG_STAGING is not set
486		−
487		−#
488		−# File systems
489		−#
490		−# CONFIG_EXT2_FS is not set
491		−# CONFIG_EXT3_FS is not set
492		−# CONFIG_EXT4_FS is not set
493		−# CONFIG_REISERFS_FS is not set
494		−# CONFIG_JFS_FS is not set
495		−# CONFIG_FS_POSIX_ACL is not set
496		−CONFIG_FILE_LOCKING=y
497		−# CONFIG_XFS_FS is not set
498		−# CONFIG_OCFS2_FS is not set
499		−# CONFIG_BTRFS_FS is not set
500		−# CONFIG_DNOTIFY is not set
501		−# CONFIG_INOTIFY is not set
502		−# CONFIG_QUOTA is not set
503		−# CONFIG_AUTOFS_FS is not set
504		−# CONFIG_AUTOFS4_FS is not set
505		−# CONFIG_FUSE_FS is not set
506		−
507		−#
508		−# CD-ROM/DVD Filesystems
509		−#
510		−# CONFIG_ISO9660_FS is not set
511		−# CONFIG_UDF_FS is not set
512		−
513		−#
514		−# DOS/FAT/NT Filesystems
515		−#
516		−# CONFIG_MSDOS_FS is not set
517		−# CONFIG_VFAT_FS is not set
518		−# CONFIG_NTFS_FS is not set
519		−
520		−#
521		−# Pseudo filesystems
522		−#
523		−CONFIG_PROC_FS=y
524		−CONFIG_PROC_SYSCTL=y
525		−CONFIG_SYSFS=y
526		−# CONFIG_TMPFS is not set
527		−# CONFIG_HUGETLB_PAGE is not set
528		−# CONFIG_CONFIGFS_FS is not set
529		−# CONFIG_MISC_FILESYSTEMS is not set
530		−# CONFIG_NETWORK_FILESYSTEMS is not set
531		−
532		−#
533		−# Partition Types
534		−#
535		−# CONFIG_PARTITION_ADVANCED is not set
536		−CONFIG_MSDOS_PARTITION=y
537		−# CONFIG_NLS is not set
538		−# CONFIG_DLM is not set
539		−
540		−#
541		−# Kernel hacking
542		−#
543		−CONFIG_PRINTK_TIME=y
544		−# CONFIG_ENABLE_WARN_DEPRECATED is not set
545		−# CONFIG_ENABLE_MUST_CHECK is not set
546		−CONFIG_FRAME_WARN=1024
547		−# CONFIG_MAGIC_SYSRQ is not set
548		−# CONFIG_UNUSED_SYMBOLS is not set
549		−# CONFIG_DEBUG_FS is not set
550		−# CONFIG_HEADERS_CHECK is not set
551		−CONFIG_DEBUG_KERNEL=y
552		−CONFIG_DEBUG_SHIRQ=y
553		−CONFIG_DETECT_SOFTLOCKUP=y
554		−# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
555		−CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
556		−# CONFIG_SCHED_DEBUG is not set
557		−# CONFIG_SCHEDSTATS is not set
558		−# CONFIG_TIMER_STATS is not set
559		−# CONFIG_DEBUG_OBJECTS is not set
560		−# CONFIG_DEBUG_SLAB is not set
561		−# CONFIG_DEBUG_RT_MUTEXES is not set
562		−# CONFIG_RT_MUTEX_TESTER is not set
563		−CONFIG_DEBUG_SPINLOCK=y
564		−CONFIG_DEBUG_MUTEXES=y
565		−CONFIG_DEBUG_SPINLOCK_SLEEP=y
566		−# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
567		−# CONFIG_DEBUG_KOBJECT is not set
568		−# CONFIG_DEBUG_INFO is not set
569		−# CONFIG_DEBUG_VM is not set
570		−CONFIG_DEBUG_NOMMU_REGIONS=y
571		−# CONFIG_DEBUG_MEMORY_INIT is not set
572		−# CONFIG_DEBUG_LIST is not set
573		−# CONFIG_DEBUG_SG is not set
574		−# CONFIG_DEBUG_NOTIFIERS is not set
575		−# CONFIG_BOOT_PRINTK_DELAY is not set
576		−# CONFIG_RCU_TORTURE_TEST is not set
577		−# CONFIG_BACKTRACE_SELF_TEST is not set
578		−# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
579		−# CONFIG_FAULT_INJECTION is not set
580		−# CONFIG_SYSCTL_SYSCALL_CHECK is not set
581		−
582		−#
583		−# Tracers
584		−#
585		−# CONFIG_PREEMPT_TRACER is not set
586		−# CONFIG_SCHED_TRACER is not set
587		−# CONFIG_CONTEXT_SWITCH_TRACER is not set
588		−# CONFIG_BOOT_TRACER is not set
589		−# CONFIG_TRACE_BRANCH_PROFILING is not set
590		−# CONFIG_DYNAMIC_DEBUG is not set
591		−# CONFIG_SAMPLES is not set
592		−
593		−#
594		−# Security options
595		−#
596		−# CONFIG_KEYS is not set
597		−# CONFIG_SECURITY is not set
598		−# CONFIG_SECURITYFS is not set
599		−# CONFIG_SECURITY_FILE_CAPABILITIES is not set
600		−# CONFIG_CRYPTO is not set
601		−
602		−#
603		−# Library routines
604		−#
605		−CONFIG_GENERIC_FIND_LAST_BIT=y
606		−# CONFIG_CRC_CCITT is not set
607		−# CONFIG_CRC16 is not set
608		−# CONFIG_CRC_T10DIF is not set
609		−# CONFIG_CRC_ITU_T is not set
610		−# CONFIG_CRC32 is not set
611		−# CONFIG_CRC7 is not set
612		−# CONFIG_LIBCRC32C is not set
613		−CONFIG_PLIST=y
614		−CONFIG_HAS_IOMEM=y
615		−CONFIG_HAS_DMA=y

arch/xtensa/include/asm/cacheflush.h+5−2

@@ -67,6 +67,8 @@ extern void __invalidate_dcache_page_alias(unsigned long, unsigned long); · 66 unmodified lines
67	67	#else
68	68	static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
69	69	unsigned long phys) { }
	70	+static inline void __invalidate_dcache_page_alias(unsigned long virt,
	71	+ unsigned long phys) { }
70	72	#endif
71	73	#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
72	74	extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
@@ -84,7 +86,8 @@ static inline void __invalidate_icache_page_alias(unsigned long virt, · 11 unmodified lines
84	86	* (see also Documentation/cachetlb.txt)
85	87	*/
86	88
87		−#if (DCACHE_WAY_SIZE > PAGE_SIZE) \|\| defined(CONFIG_SMP)
	89	+#if defined(CONFIG_MMU) && \
	90	+ ((DCACHE_WAY_SIZE > PAGE_SIZE) \|\| defined(CONFIG_SMP))
88	91
89	92	#ifdef CONFIG_SMP
90	93	void flush_cache_all(void);
@@ -150,7 +153,7 @@ void local_flush_cache_page(struct vm_area_struct *vma, · 59 unmodified lines
150	153	#define flush_dcache_mmap_lock(mapping) do { } while (0)
151	154	#define flush_dcache_mmap_unlock(mapping) do { } while (0)
152	155
153		−#if (DCACHE_WAY_SIZE > PAGE_SIZE)
	156	+#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
154	157
155	158	extern void copy_to_user_page(struct vm_area_struct, struct page,
156	159	unsigned long, void, const void, unsigned long);

arch/xtensa/include/asm/highmem.h+1−1

@@ -25,7 +25,7 @@ · 24 unmodified lines
25	25	#define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
26	26	#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
27	27
28		−#define kmap_prot PAGE_KERNEL
	28	+#define kmap_prot PAGE_KERNEL_EXEC
29	29
30	30	#if DCACHE_WAY_SIZE > PAGE_SIZE
31	31	#define get_pkmap_color get_pkmap_color

arch/xtensa/include/asm/initialize_mmu.h+36−4

@@ -26,8 +26,16 @@ · 25 unmodified lines
26	26	#include <asm/pgtable.h>
27	27	#include <asm/vectors.h>
28	28
	29	+#if XCHAL_HAVE_PTP_MMU
29	30	#define CA_BYPASS (_PAGE_CA_BYPASS \| _PAGE_HW_WRITE \| _PAGE_HW_EXEC)
30	31	#define CA_WRITEBACK (_PAGE_CA_WB \| _PAGE_HW_WRITE \| _PAGE_HW_EXEC)
	32	+#else
	33	+#define CA_WRITEBACK (0x4)
	34	+#endif
	35	+
	36	+#ifndef XCHAL_SPANNING_WAY
	37	+#define XCHAL_SPANNING_WAY 0
	38	+#endif
31	39
32	40	#ifdef __ASSEMBLY__
33	41
@@ -75,7 +83,7 @@ · 41 unmodified lines
75	83
76	84	/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
77	85
78		− movi a2, 0x40000006
	86	+ movi a2, 0x40000000 \| XCHAL_SPANNING_WAY
79	87	idtlb a2
80	88	iitlb a2
81	89	isync
@@ -141,9 +149,6 @@ · 59 unmodified lines
141	149	jx a4
142	150
143	151	1:
144		− movi a2, VECBASE_RESET_VADDR
145		− wsr a2, vecbase
146		−
147	152	/* Step 5: remove temporary mapping. */
148	153	idtlb a7
149	154	iitlb a7
@@ -156,6 +161,33 @@ · 6 unmodified lines
156	161	#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
157	162	XCHAL_HAVE_SPANNING_WAY */
158	163
	164	+#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
	165	+ /* Enable data and instruction cache in the DEFAULT_MEMORY region
	166	+ * if the processor has DTLB and ITLB.
	167	+ */
	168	+
	169	+ movi a5, PLATFORM_DEFAULT_MEM_START \| XCHAL_SPANNING_WAY
	170	+ movi a6, ~_PAGE_ATTRIB_MASK
	171	+ movi a7, CA_WRITEBACK
	172	+ movi a8, 0x20000000
	173	+ movi a9, PLATFORM_DEFAULT_MEM_SIZE
	174	+ j 2f
	175	+1:
	176	+ sub a9, a9, a8
	177	+2:
	178	+ rdtlb1 a3, a5
	179	+ ritlb1 a4, a5
	180	+ and a3, a3, a6
	181	+ and a4, a4, a6
	182	+ or a3, a3, a7
	183	+ or a4, a4, a7
	184	+ wdtlb a3, a5
	185	+ witlb a4, a5
	186	+ add a5, a5, a8
	187	+ bltu a8, a9, 1b
	188	+
	189	+#endif
	190	+
159	191	.endm
160	192
161	193	#endif /__ASSEMBLY__/

arch/xtensa/include/asm/mmu_context.h+0−4

@@ -50,11 +50,7 @@ DECLARE_PER_CPU(unsigned long, asid_cache); · 49 unmodified lines
50	50	#define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
51	51	#define ASID_INSERT(x) (0x03020001 \| (((x) & ASID_MASK) << 8))
52	52
53		−#ifdef CONFIG_MMU
54	53	void init_mmu(void);
55		−#else
56		−static inline void init_mmu(void) { }
57		−#endif
58	54
59	55	static inline void set_rasid_register (unsigned long val)
60	56	{

arch/xtensa/include/asm/nommu_context.h+4−0

@@ -1,3 +1,7 @@
	1	+static inline void init_mmu(void)
	2	+{
	3	+}
	4	+
1	5	static inline void enter_lazy_tlb(struct mm_struct mm, struct task_struct tsk)
2	6	{
3	7	}

arch/xtensa/include/asm/page.h+6−6

@@ -20,10 +20,10 @@ · 19 unmodified lines
20	20	* Fixed TLB translations in the processor.
21	21	*/
22	22
23		−#define XCHAL_KSEG_CACHED_VADDR 0xd0000000
24		−#define XCHAL_KSEG_BYPASS_VADDR 0xd8000000
25		−#define XCHAL_KSEG_PADDR 0x00000000
26		−#define XCHAL_KSEG_SIZE 0x08000000
	23	+#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
	24	+#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
	25	+#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000)
	26	+#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
27	27
28	28	/*
29	29	* PAGE_SHIFT determines the page size
@@ -37,7 +37,7 @@ · 7 unmodified lines
37	37	#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
38	38	#define MAX_MEM_PFN XCHAL_KSEG_SIZE
39	39	#else
40		−#define PAGE_OFFSET 0
	40	+#define PAGE_OFFSET __XTENSA_UL_CONST(0)
41	41	#define MAX_MEM_PFN (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
42	42	#endif
43	43
@@ -145,7 +145,7 @@ extern void copy_page(void to, void from); · 101 unmodified lines
145	145	* some extra work
146	146	*/
147	147
148		−#if DCACHE_WAY_SIZE > PAGE_SIZE
	148	+#if defined(CONFIG_MMU) && DCACHE_WAY_SIZE > PAGE_SIZE
149	149	extern void clear_page_alias(void *vaddr, unsigned long paddr);
150	150	extern void copy_page_alias(void to, void from,
151	151	unsigned long to_paddr, unsigned long from_paddr);

arch/xtensa/include/asm/pgtable.h+1−0

@@ -178,6 +178,7 @@ · 177 unmodified lines
178	178
179	179	#else /* no mmu */
180	180
	181	+# define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
181	182	# define PAGE_NONE __pgprot(0)
182	183	# define PAGE_SHARED __pgprot(0)
183	184	# define PAGE_COPY __pgprot(0)

arch/xtensa/include/asm/uaccess.h+2−2

@@ -320,7 +320,7 @@ __asm__ __volatile__( \ · 319 unmodified lines
320	320	({ \
321	321	long __gu_err, __gu_val; \
322	322	__get_user_size(__gu_val,(ptr),(size),__gu_err); \
323		− (x) = (__typeof__(*(ptr)))__gu_val; \
	323	+ (x) = (__force __typeof__(*(ptr)))__gu_val; \
324	324	__gu_err; \
325	325	})
326	326
@@ -330,7 +330,7 @@ __asm__ __volatile__( \ · 3 unmodified lines
330	330	const __typeof__((ptr)) __gu_addr = (ptr); \
331	331	if (access_ok(VERIFY_READ,__gu_addr,size)) \
332	332	__get_user_size(__gu_val,__gu_addr,(size),__gu_err); \
333		− (x) = (__typeof__(*(ptr)))__gu_val; \
	333	+ (x) = (__force __typeof__(*(ptr)))__gu_val; \
334	334	__gu_err; \
335	335	})
336	336

arch/xtensa/include/asm/vectors.h+4−3

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	19	#define _XTENSA_VECTORS_H
20	20
21	21	#include <variant/core.h>
	22	+#include <platform/hardware.h>
22	23
23	24	#define XCHAL_KIO_CACHED_VADDR 0xe0000000
24	25	#define XCHAL_KIO_BYPASS_VADDR 0xf0000000
@@ -51,13 +52,13 @@ · 26 unmodified lines
51	52	/* MMU Not being used - Virtual == Physical */
52	53
53	54	/* VECBASE */
54		− #define VIRTUAL_MEMORY_ADDRESS 0x00002000
	55	+ #define VIRTUAL_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x2000)
55	56
56	57	/* Location of the start of the kernel text, _start */
57		− #define KERNELOFFSET 0x00003000
	58	+ #define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x3000)
58	59
59	60	/* Loaded just above possibly live vectors */
60		− #define LOAD_MEMORY_ADDRESS 0x00003000
	61	+ #define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000)
61	62
62	63	#endif /* CONFIG_MMU */
63	64

arch/xtensa/include/uapi/asm/mman.h+6−0

@@ -55,6 +55,12 @@ · 54 unmodified lines
55	55	#define MAP_NONBLOCK 0x20000 /* do not block on IO */
56	56	#define MAP_STACK 0x40000 /* give out an address that is best suited for process/thread stacks */
57	57	#define MAP_HUGETLB 0x80000 /* create a huge page mapping */
	58	+#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED
	59	+# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be
	60	+ * uninitialized */
	61	+#else
	62	+# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */
	63	+#endif
58	64
59	65	/*
60	66	* Flags for msync

arch/xtensa/kernel/head.S+5−0

@@ -112,6 +112,11 @@ ENTRY(_startup) · 111 unmodified lines
112	112
113	113	movi a0, 0
114	114
	115	+#if XCHAL_HAVE_VECBASE
	116	+ movi a2, VECBASE_RESET_VADDR
	117	+ wsr a2, vecbase
	118	+#endif
	119	+
115	120	/* Clear debugging registers. */
116	121
117	122	#if XCHAL_HAVE_DEBUG

arch/xtensa/kernel/syscall.c+2−0

@@ -57,6 +57,7 @@ asmlinkage long xtensa_fadvise64_64(int fd, int advice, · 56 unmodified lines
57	57	return sys_fadvise64_64(fd, offset, len, advice);
58	58	}
59	59
	60	+#ifdef CONFIG_MMU
60	61	unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
61	62	unsigned long len, unsigned long pgoff, unsigned long flags)
62	63	{
@@ -93,3 +94,4 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, · 30 unmodified lines
93	94	addr = COLOUR_ALIGN(addr, pgoff);
94	95	}
95	96	}
	97	+#endif

arch/xtensa/mm/Makefile+2−2

@@ -2,6 +2,6 @@ · 1 unmodified line
2	2	# Makefile for the Linux/Xtensa-specific parts of the memory manager.
3	3	#
4	4
5		−obj-y := init.o cache.o misc.o
6		−obj-$(CONFIG_MMU) += fault.o mmu.o tlb.o
	5	+obj-y := init.o misc.o
	6	+obj-$(CONFIG_MMU) += cache.o fault.o mmu.o tlb.o
7	7	obj-$(CONFIG_HIGHMEM) += highmem.o

arch/xtensa/mm/init.c+18−1

@@ -239,6 +239,17 @@ void __init bootmem_init(void) · 238 unmodified lines
239	239	unsigned long bootmap_start, bootmap_size;
240	240	int i;
241	241
	242	+ /* Reserve all memory below PLATFORM_DEFAULT_MEM_START, as memory
	243	+ * accounting doesn't work for pages below that address.
	244	+ *
	245	+ * If PLATFORM_DEFAULT_MEM_START is zero reserve page at address 0:
	246	+ * successfull allocations should never return NULL.
	247	+ */
	248	+ if (PLATFORM_DEFAULT_MEM_START)
	249	+ mem_reserve(0, PLATFORM_DEFAULT_MEM_START, 0);
	250	+ else
	251	+ mem_reserve(0, 1, 0);
	252	+
242	253	sysmem_dump();
243	254	max_low_pfn = max_pfn = 0;
244	255	min_low_pfn = ~0;
@@ -332,18 +343,24 @@ void __init mem_init(void) · 87 unmodified lines
332	343	" pkmap : 0x%08lx - 0x%08lx (%5lu kB)\n"
333	344	" fixmap : 0x%08lx - 0x%08lx (%5lu kB)\n"
334	345	#endif
	346	+#ifdef CONFIG_MMU
335	347	" vmalloc : 0x%08x - 0x%08x (%5u MB)\n"
336		− " lowmem : 0x%08x - 0x%08lx (%5lu MB)\n",
	348	+#endif
	349	+ " lowmem : 0x%08lx - 0x%08lx (%5lu MB)\n",
337	350	#ifdef CONFIG_HIGHMEM
338	351	PKMAP_BASE, PKMAP_BASE + LAST_PKMAP * PAGE_SIZE,
339	352	(LAST_PKMAP*PAGE_SIZE) >> 10,
340	353	FIXADDR_START, FIXADDR_TOP,
341	354	(FIXADDR_TOP - FIXADDR_START) >> 10,
342	355	#endif
	356	+#ifdef CONFIG_MMU
343	357	VMALLOC_START, VMALLOC_END,
344	358	(VMALLOC_END - VMALLOC_START) >> 20,
345	359	PAGE_OFFSET, PAGE_OFFSET +
346	360	(max_low_pfn - min_low_pfn) * PAGE_SIZE,
	361	+#else
	362	+ min_low_pfn * PAGE_SIZE, max_low_pfn * PAGE_SIZE,
	363	+#endif
347	364	((max_low_pfn - min_low_pfn) * PAGE_SIZE) >> 20);
348	365	}
349	366

arch/xtensa/platforms/s6105/Makefile+0−3

@@ -1,3 +0,0 @@
1		−# Makefile for the Stretch S6105 eval board
2		−
3		−obj-y := setup.o device.o

arch/xtensa/platforms/s6105/device.c+0−161

@@ -1,161 +0,0 @@
1		−/*
2		− * s6105 platform devices
3		− *
4		− * Copyright (c) 2009 emlix GmbH
5		− */
6		−
7		−#include <linux/kernel.h>
8		−#include <linux/gpio.h>
9		−#include <linux/init.h>
10		−#include <linux/irq.h>
11		−#include <linux/phy.h>
12		−#include <linux/platform_device.h>
13		−#include <linux/serial.h>
14		−#include <linux/serial_8250.h>
15		−
16		−#include <variant/hardware.h>
17		−#include <variant/dmac.h>
18		−
19		−#include <platform/gpio.h>
20		−
21		−#define GPIO3_INTNUM 3
22		−#define UART_INTNUM 4
23		−#define GMAC_INTNUM 5
24		−
25		−static const signed char gpio3_irq_mappings[] = {
26		− S6_INTC_GPIO(3),
27		− -1
28		−};
29		−
30		−static const signed char uart_irq_mappings[] = {
31		− S6_INTC_UART(0),
32		− S6_INTC_UART(1),
33		− -1,
34		−};
35		−
36		−static const signed char gmac_irq_mappings[] = {
37		− S6_INTC_GMAC_STAT,
38		− S6_INTC_GMAC_ERR,
39		− S6_INTC_DMA_HOSTTERMCNT(0),
40		− S6_INTC_DMA_HOSTTERMCNT(1),
41		− -1
42		−};
43		−
44		−const signed char *platform_irq_mappings[NR_IRQS] = {
45		− [GPIO3_INTNUM] = gpio3_irq_mappings,
46		− [UART_INTNUM] = uart_irq_mappings,
47		− [GMAC_INTNUM] = gmac_irq_mappings,
48		−};
49		−
50		−static struct plat_serial8250_port serial_platform_data[] = {
51		− {
52		− .membase = (void *)S6_REG_UART + 0x0000,
53		− .mapbase = S6_REG_UART + 0x0000,
54		− .irq = UART_INTNUM,
55		− .uartclk = S6_SCLK,
56		− .regshift = 2,
57		− .iotype = SERIAL_IO_MEM,
58		− .flags = ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST,
59		− },
60		− {
61		− .membase = (void *)S6_REG_UART + 0x1000,
62		− .mapbase = S6_REG_UART + 0x1000,
63		− .irq = UART_INTNUM,
64		− .uartclk = S6_SCLK,
65		− .regshift = 2,
66		− .iotype = SERIAL_IO_MEM,
67		− .flags = ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST,
68		− },
69		− { },
70		−};
71		−
72		−static struct resource s6_gmac_resource[] = {
73		− {
74		− .name = "mem",
75		− .start = (resource_size_t)S6_REG_GMAC,
76		− .end = (resource_size_t)S6_REG_GMAC + 0x10000 - 1,
77		− .flags = IORESOURCE_MEM,
78		− },
79		− {
80		− .name = "dma",
81		− .start = (resource_size_t)
82		− DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX),
83		− .end = (resource_size_t)
84		− DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX) + 0x100 - 1,
85		− .flags = IORESOURCE_DMA,
86		− },
87		− {
88		− .name = "dma",
89		− .start = (resource_size_t)
90		− DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX),
91		− .end = (resource_size_t)
92		− DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX) + 0x100 - 1,
93		− .flags = IORESOURCE_DMA,
94		− },
95		− {
96		− .name = "io",
97		− .start = (resource_size_t)S6_MEM_GMAC,
98		− .end = (resource_size_t)S6_MEM_GMAC + 0x2000000 - 1,
99		− .flags = IORESOURCE_IO,
100		− },
101		− {
102		− .name = "irq",
103		− .start = (resource_size_t)GMAC_INTNUM,
104		− .flags = IORESOURCE_IRQ,
105		− },
106		− {
107		− .name = "irq",
108		− .start = (resource_size_t)PHY_POLL,
109		− .flags = IORESOURCE_IRQ,
110		− },
111		−};
112		−
113		−static int __init prepare_phy_irq(int pin)
114		−{
115		− int irq;
116		− if (gpio_request(pin, "s6gmac_phy") < 0)
117		− goto fail;
118		− if (gpio_direction_input(pin) < 0)
119		− goto free;
120		− irq = gpio_to_irq(pin);
121		− if (irq < 0)
122		− goto free;
123		− if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
124		− goto free;
125		− return irq;
126		−free:
127		− gpio_free(pin);
128		−fail:
129		− return PHY_POLL;
130		−}
131		−
132		−static struct platform_device platform_devices[] = {
133		− {
134		− .name = "serial8250",
135		− .id = PLAT8250_DEV_PLATFORM,
136		− .dev = {
137		− .platform_data = serial_platform_data,
138		− },
139		− },
140		− {
141		− .name = "s6gmac",
142		− .id = 0,
143		− .resource = s6_gmac_resource,
144		− .num_resources = ARRAY_SIZE(s6_gmac_resource),
145		− },
146		− {
147		− I2C_BOARD_INFO("m41t62", S6I2C_ADDR_M41T62),
148		− },
149		−};
150		−
151		−static int __init device_init(void)
152		−{
153		− int i;
154		−
155		− s6_gmac_resource[5].start = prepare_phy_irq(GPIO_PHY_IRQ);
156		−
157		− for (i = 0; i < ARRAY_SIZE(platform_devices); i++)
158		− platform_device_register(&platform_devices[i]);
159		− return 0;
160		−}
161		−arch_initcall_sync(device_init);

arch/xtensa/platforms/s6105/include/platform/gpio.h+0−27

@@ -1,27 +0,0 @@
1		−#ifndef __ASM_XTENSA_S6105_GPIO_H
2		−#define __ASM_XTENSA_S6105_GPIO_H
3		−
4		−#define GPIO_BP_TEMP_ALARM 0
5		−#define GPIO_PB_RESET_IN 1
6		−#define GPIO_EXP_IRQ 2
7		−#define GPIO_TRIGGER_IRQ 3
8		−#define GPIO_RTC_IRQ 4
9		−#define GPIO_PHY_IRQ 5
10		−#define GPIO_IMAGER_RESET 6
11		−#define GPIO_SD_IRQ 7
12		−#define GPIO_MINI_BOOT_INH 8
13		−#define GPIO_BOARD_RESET 9
14		−#define GPIO_EXP_PRESENT 10
15		−#define GPIO_LED1_NGREEN 12
16		−#define GPIO_LED1_RED 13
17		−#define GPIO_LED0_NGREEN 14
18		−#define GPIO_LED0_NRED 15
19		−#define GPIO_SPI_CS0 16
20		−#define GPIO_SPI_CS1 17
21		−#define GPIO_SPI_CS3 19
22		−#define GPIO_SPI_CS4 20
23		−#define GPIO_SD_WP 21
24		−#define GPIO_BP_RESET 22
25		−#define GPIO_ALARM_OUT 23
26		−
27		−#endif /* __ASM_XTENSA_S6105_GPIO_H */

arch/xtensa/platforms/s6105/include/platform/hardware.h+0−11

@@ -1,11 +0,0 @@
1		−#ifndef __XTENSA_S6105_HARDWARE_H
2		−#define __XTENSA_S6105_HARDWARE_H
3		−
4		−#define PLATFORM_DEFAULT_MEM_START 0x40000000
5		−#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
6		−
7		−#define MAX_DMA_ADDRESS 0
8		−
9		−#define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x1000)
10		−
11		−#endif /* __XTENSA_S6105_HARDWARE_H */

arch/xtensa/platforms/s6105/include/platform/serial.h+0−8

@@ -1,8 +0,0 @@
1		−#ifndef __ASM_XTENSA_S6105_SERIAL_H
2		−#define __ASM_XTENSA_S6105_SERIAL_H
3		−
4		−#include <variant/hardware.h>
5		−
6		−#define BASE_BAUD (S6_SCLK / 16)
7		−
8		−#endif /* __ASM_XTENSA_S6105_SERIAL_H */

arch/xtensa/platforms/s6105/setup.c+0−73

@@ -1,73 +0,0 @@
1		−/*
2		− * s6105 control routines
3		− *
4		− * Copyright (c) 2009 emlix GmbH
5		− */
6		−#include <linux/irq.h>
7		−#include <linux/io.h>
8		−#include <linux/gpio.h>
9		−
10		−#include <asm/bootparam.h>
11		−
12		−#include <variant/hardware.h>
13		−#include <variant/gpio.h>
14		−
15		−#include <platform/gpio.h>
16		−
17		−void platform_halt(void)
18		−{
19		− local_irq_disable();
20		− while (1)
21		− ;
22		−}
23		−
24		−void platform_power_off(void)
25		−{
26		− platform_halt();
27		−}
28		−
29		−void platform_restart(void)
30		−{
31		− platform_halt();
32		−}
33		−
34		−void __init platform_setup(char **cmdline)
35		−{
36		− unsigned long reg;
37		−
38		− reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL);
39		− reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC \|
40		− S6_GREG1_PLLSEL_GMII_MASK << S6_GREG1_PLLSEL_GMII);
41		− reg \|= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC \|
42		− S6_GREG1_PLLSEL_GMII_125MHZ << S6_GREG1_PLLSEL_GMII;
43		− writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL);
44		−
45		− reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE);
46		− reg &= ~(1 << S6_GREG1_BLOCK_SB);
47		− reg &= ~(1 << S6_GREG1_BLOCK_GMAC);
48		− writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE);
49		−
50		− reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA);
51		− reg \|= 1 << S6_GREG1_BLOCK_SB;
52		− reg \|= 1 << S6_GREG1_BLOCK_GMAC;
53		− writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA);
54		−
55		− printk(KERN_NOTICE "S6105 on Stretch S6000 - "
56		− "Copyright (C) 2009 emlix GmbH <info@emlix.com>\n");
57		−}
58		−
59		−void __init platform_init(bp_tag_t *first)
60		−{
61		− s6_gpio_init(0);
62		− gpio_request(GPIO_LED1_NGREEN, "led1_green");
63		− gpio_request(GPIO_LED1_RED, "led1_red");
64		− gpio_direction_output(GPIO_LED1_NGREEN, 1);
65		−}
66		−
67		−void platform_heartbeat(void)
68		−{
69		− static unsigned int c;
70		−
71		− if (!(++c & 0x4F))
72		− gpio_direction_output(GPIO_LED1_RED, !(c & 0x10));
73		−}

arch/xtensa/platforms/xtfpga/include/platform/hardware.h+2−2

@@ -17,8 +17,8 @@ · 16 unmodified lines
17	17
18	18	/* Memory configuration. */
19	19
20		−#define PLATFORM_DEFAULT_MEM_START 0x00000000
21		−#define PLATFORM_DEFAULT_MEM_SIZE 0x04000000
	20	+#define PLATFORM_DEFAULT_MEM_START CONFIG_DEFAULT_MEM_START
	21	+#define PLATFORM_DEFAULT_MEM_SIZE CONFIG_DEFAULT_MEM_SIZE
22	22
23	23	/* Interrupt configuration. */
24	24

arch/xtensa/variants/s6000/Makefile+0−4

@@ -1,4 +0,0 @@
1		−# s6000 Makefile
2		−
3		−obj-y += irq.o gpio.o dmac.o
4		−obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o

arch/xtensa/variants/s6000/delay.c+0−25

@@ -1,25 +0,0 @@
1		−#include <asm/timex.h>
2		−#include <asm/io.h>
3		−#include <variant/hardware.h>
4		−
5		−#define LOOPS 10
6		−void platform_calibrate_ccount(void)
7		−{
8		− u32 uninitialized_var(a);
9		− u32 uninitialized_var(u);
10		− u32 b;
11		− u32 tstamp = S6_REG_GREG1 + S6_GREG1_GLOBAL_TIMER;
12		− int i = LOOPS+1;
13		− do {
14		− u32 t = u;
15		− asm volatile(
16		− "1: l32i %0, %2, 0 ;"
17		− " beq %0, %1, 1b ;"
18		− : "=&a"(u) : "a"(t), "a"(tstamp));
19		− b = get_ccount();
20		− if (i == LOOPS)
21		− a = b;
22		− } while (--i >= 0);
23		− b -= a;
24		− ccount_freq = b * (100000UL / LOOPS);
25		−}

arch/xtensa/variants/s6000/dmac.c+0−173

@@ -1,173 +0,0 @@
1		−/*
2		− * Authors: Oskar Schirmer <oskar@scara.com>
3		− * Daniel Gloeckner <dg@emlix.com>
4		− * (c) 2008 emlix GmbH http://www.emlix.com
5		− *
6		− * This program is free software; you can redistribute it and/or modify it
7		− * under the terms of the GNU General Public License as published by the
8		− * Free Software Foundation; either version 2 of the License, or (at your
9		− * option) any later version.
10		− */
11		−
12		−#include <linux/kernel.h>
13		−#include <linux/io.h>
14		−#include <linux/types.h>
15		−#include <linux/errno.h>
16		−#include <linux/spinlock.h>
17		−#include <asm/cacheflush.h>
18		−#include <variant/dmac.h>
19		−
20		−/* DMA engine lookup */
21		−
22		−struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
23		−
24		−
25		−/* DMA control, per engine */
26		−
27		−void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
28		−{
29		− if (xtensa_need_flush_dma_source(src)) {
30		− u32 base = src;
31		− u32 span = size;
32		− u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
33		− if (chunk && (size > chunk)) {
34		− s32 skip =
35		− readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
36		− u32 gaps = (size+chunk-1)/chunk - 1;
37		− if (skip >= 0) {
38		− span += gaps * skip;
39		− } else if (-skip > chunk) {
40		− s32 decr = gaps * (chunk + skip);
41		− base += decr;
42		− span = chunk - decr;
43		− } else {
44		− span = max(span + gaps * skip,
45		− (chunk + skip) * gaps - skip);
46		− }
47		− }
48		− flush_dcache_unaligned(base, span);
49		− }
50		− if (xtensa_need_invalidate_dma_destination(dst)) {
51		− u32 base = dst;
52		− u32 span = size;
53		− u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
54		− if (chunk && (size > chunk)) {
55		− s32 skip =
56		− readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
57		− u32 gaps = (size+chunk-1)/chunk - 1;
58		− if (skip >= 0) {
59		− span += gaps * skip;
60		− } else if (-skip > chunk) {
61		− s32 decr = gaps * (chunk + skip);
62		− base += decr;
63		− span = chunk - decr;
64		− } else {
65		− span = max(span + gaps * skip,
66		− (chunk + skip) * gaps - skip);
67		− }
68		− }
69		− invalidate_dcache_unaligned(base, span);
70		− }
71		− s6dmac_put_fifo(dmac, chan, src, dst, size);
72		−}
73		−
74		−void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
75		−{
76		− unsigned long flags;
77		− spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
78		− spin_lock_irqsave(spinl, flags);
79		− _s6dmac_disable_error_irqs(dmac, mask);
80		− spin_unlock_irqrestore(spinl, flags);
81		−}
82		−
83		−u32 s6dmac_int_sources(u32 dmac, u32 channel)
84		−{
85		− u32 mask, ret, tmp;
86		− mask = 1 << channel;
87		−
88		− tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
89		− tmp &= mask;
90		− writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
91		− ret = tmp >> channel;
92		−
93		− tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
94		− tmp &= mask;
95		− writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
96		− ret \|= (tmp >> channel) << 1;
97		−
98		− tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
99		− tmp &= mask;
100		− writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
101		− ret \|= (tmp >> channel) << 2;
102		−
103		− tmp = readl(dmac + S6_DMA_INTRAW0);
104		− tmp &= (mask << S6_DMA_INT0_OVER) \| (mask << S6_DMA_INT0_UNDER);
105		− writel(tmp, dmac + S6_DMA_INTCLEAR0);
106		−
107		− if (tmp & (mask << S6_DMA_INT0_UNDER))
108		− ret \|= 1 << 3;
109		− if (tmp & (mask << S6_DMA_INT0_OVER))
110		− ret \|= 1 << 4;
111		−
112		− tmp = readl(dmac + S6_DMA_MASTERERRINFO);
113		− mask <<= S6_DMA_INT1_CHANNEL;
114		− if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
115		− == channel)
116		− mask \|= 1 << S6_DMA_INT1_MASTER;
117		− if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
118		− == channel)
119		− mask \|= 1 << (S6_DMA_INT1_MASTER + 1);
120		− if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
121		− == channel)
122		− mask \|= 1 << (S6_DMA_INT1_MASTER + 2);
123		−
124		− tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
125		− writel(tmp, dmac + S6_DMA_INTCLEAR1);
126		− ret \|= ((tmp >> channel) & 1) << 5;
127		− ret \|= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
128		−
129		− return ret;
130		−}
131		−
132		−void s6dmac_release_chan(u32 dmac, int chan)
133		−{
134		− if (chan >= 0)
135		− s6dmac_disable_chan(dmac, chan);
136		−}
137		−
138		−
139		−/* global init */
140		−
141		−static inline void __init dmac_init(u32 dmac, u8 chan_nb)
142		−{
143		− s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
144		− spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
145		− s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
146		− writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
147		− dmac + S6_DMA_INTCLEAR1);
148		−}
149		−
150		−static inline void __init dmac_master(u32 dmac,
151		− u32 m0start, u32 m0end, u32 m1start, u32 m1end)
152		−{
153		− writel(m0start, dmac + S6_DMA_MASTER0START);
154		− writel(m0end - 1, dmac + S6_DMA_MASTER0END);
155		− writel(m1start, dmac + S6_DMA_MASTER1START);
156		− writel(m1end - 1, dmac + S6_DMA_MASTER1END);
157		−}
158		−
159		−static void __init s6_dmac_init(void)
160		−{
161		− dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);
162		− dmac_master(S6_REG_LMSDMA,
163		− S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC);
164		− dmac_init(S6_REG_NIDMA, S6_NIDMA_NB);
165		− dmac_init(S6_REG_DPDMA, S6_DPDMA_NB);
166		− dmac_master(S6_REG_DPDMA,
167		− S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA);
168		− dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB);
169		− dmac_master(S6_REG_HIFDMA,
170		− S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX);
171		−}
172		−
173		−arch_initcall(s6_dmac_init);

arch/xtensa/variants/s6000/gpio.c+0−230

@@ -1,230 +0,0 @@
1		−/*
2		− * s6000 gpio driver
3		− *
4		− * Copyright (c) 2009 emlix GmbH
5		− * Authors: Oskar Schirmer <oskar@scara.com>
6		− * Johannes Weiner <hannes@cmpxchg.org>
7		− * Daniel Gloeckner <dg@emlix.com>
8		− */
9		−#include <linux/bitops.h>
10		−#include <linux/kernel.h>
11		−#include <linux/module.h>
12		−#include <linux/init.h>
13		−#include <linux/io.h>
14		−#include <linux/irq.h>
15		−#include <linux/gpio.h>
16		−
17		−#include <variant/hardware.h>
18		−
19		−#define IRQ_BASE XTENSA_NR_IRQS
20		−
21		−#define S6_GPIO_DATA 0x000
22		−#define S6_GPIO_IS 0x404
23		−#define S6_GPIO_IBE 0x408
24		−#define S6_GPIO_IEV 0x40C
25		−#define S6_GPIO_IE 0x410
26		−#define S6_GPIO_RIS 0x414
27		−#define S6_GPIO_MIS 0x418
28		−#define S6_GPIO_IC 0x41C
29		−#define S6_GPIO_AFSEL 0x420
30		−#define S6_GPIO_DIR 0x800
31		−#define S6_GPIO_BANK(nr) ((nr) * 0x1000)
32		−#define S6_GPIO_MASK(nr) (4 << (nr))
33		−#define S6_GPIO_OFFSET(nr) \
34		− (S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
35		−
36		−static int direction_input(struct gpio_chip *chip, unsigned int off)
37		−{
38		− writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
39		− return 0;
40		−}
41		−
42		−static int get(struct gpio_chip *chip, unsigned int off)
43		−{
44		− return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
45		−}
46		−
47		−static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
48		−{
49		− unsigned rel = S6_GPIO_OFFSET(off);
50		− writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
51		− writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
52		− return 0;
53		−}
54		−
55		−static void set(struct gpio_chip *chip, unsigned int off, int val)
56		−{
57		− writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
58		−}
59		−
60		−static int to_irq(struct gpio_chip *chip, unsigned offset)
61		−{
62		− if (offset < 8)
63		− return offset + IRQ_BASE;
64		− return -EINVAL;
65		−}
66		−
67		−static struct gpio_chip gpiochip = {
68		− .owner = THIS_MODULE,
69		− .direction_input = direction_input,
70		− .get = get,
71		− .direction_output = direction_output,
72		− .set = set,
73		− .to_irq = to_irq,
74		− .base = 0,
75		− .ngpio = 24,
76		− .can_sleep = 0, /* no blocking io needed */
77		− .exported = 0, /* no exporting to userspace */
78		−};
79		−
80		−int s6_gpio_init(u32 afsel)
81		−{
82		− writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL);
83		− writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL);
84		− writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL);
85		− return gpiochip_add(&gpiochip);
86		−}
87		−
88		−static void ack(struct irq_data *d)
89		−{
90		− writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
91		−}
92		−
93		−static void mask(struct irq_data *d)
94		−{
95		− u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
96		− r &= ~(1 << (d->irq - IRQ_BASE));
97		− writeb(r, S6_REG_GPIO + S6_GPIO_IE);
98		−}
99		−
100		−static void unmask(struct irq_data *d)
101		−{
102		− u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
103		− m \|= 1 << (d->irq - IRQ_BASE);
104		− writeb(m, S6_REG_GPIO + S6_GPIO_IE);
105		−}
106		−
107		−static int set_type(struct irq_data *d, unsigned int type)
108		−{
109		− const u8 m = 1 << (d->irq - IRQ_BASE);
110		− irq_flow_handler_t handler;
111		− u8 reg;
112		−
113		− if (type == IRQ_TYPE_PROBE) {
114		− if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m)
115		− \|\| (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m)
116		− \|\| readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR
117		− + S6_GPIO_MASK(irq - IRQ_BASE)))
118		− return 0;
119		− type = IRQ_TYPE_EDGE_BOTH;
120		− }
121		−
122		− reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
123		− if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH)) {
124		− reg \|= m;
125		− handler = handle_level_irq;
126		− } else {
127		− reg &= ~m;
128		− handler = handle_edge_irq;
129		− }
130		− writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
131		− __irq_set_handler_locked(irq, handler);
132		−
133		− reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
134		− if (type & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_EDGE_RISING))
135		− reg \|= m;
136		− else
137		− reg &= ~m;
138		− writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
139		−
140		− reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
141		− if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
142		− reg \|= m;
143		− else
144		− reg &= ~m;
145		− writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
146		− return 0;
147		−}
148		−
149		−static struct irq_chip gpioirqs = {
150		− .name = "GPIO",
151		− .irq_ack = ack,
152		− .irq_mask = mask,
153		− .irq_unmask = unmask,
154		− .irq_set_type = set_type,
155		−};
156		−
157		−static u8 demux_masks[4];
158		−
159		−static void demux_irqs(unsigned int irq, struct irq_desc *desc)
160		−{
161		− struct irq_chip *chip = irq_desc_get_chip(desc);
162		− u8 *mask = irq_desc_get_handler_data(desc);
163		− u8 pending;
164		− int cirq;
165		−
166		− chip->irq_mask(&desc->irq_data);
167		− chip->irq_ack(&desc->irq_data);
168		− pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
169		− cirq = IRQ_BASE - 1;
170		− while (pending) {
171		− int n = ffs(pending);
172		− cirq += n;
173		− pending >>= n;
174		− generic_handle_irq(cirq);
175		− }
176		− chip->irq_unmask(&desc->irq_data);
177		−}
178		−
179		−extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
180		−
181		−void __init variant_init_irq(void)
182		−{
183		− int irq, n;
184		− writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE);
185		− for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) {
186		− const signed char *mapping = platform_irq_mappings[irq];
187		− int alone = 1;
188		− u8 mask;
189		− if (!mapping)
190		− continue;
191		− for(mask = 0; *mapping != -1; mapping++)
192		− switch (*mapping) {
193		− case S6_INTC_GPIO(0):
194		− mask \|= 1 << 0;
195		− break;
196		− case S6_INTC_GPIO(1):
197		− mask \|= 1 << 1;
198		− break;
199		− case S6_INTC_GPIO(2):
200		− mask \|= 1 << 2;
201		− break;
202		− case S6_INTC_GPIO(3):
203		− mask \|= 0x1f << 3;
204		− break;
205		− default:
206		− alone = 0;
207		− }
208		− if (mask) {
209		− int cirq, i;
210		− if (!alone) {
211		− printk(KERN_ERR "chained irq chips can't share"
212		− " parent irq %i\n", irq);
213		− continue;
214		− }
215		− demux_masks[n] = mask;
216		− cirq = IRQ_BASE - 1;
217		− do {
218		− i = ffs(mask);
219		− cirq += i;
220		− mask >>= i;
221		− irq_set_chip(cirq, &gpioirqs);
222		− irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
223		− } while (mask);
224		− irq_set_handler_data(irq, demux_masks + n);
225		− irq_set_chained_handler(irq, demux_irqs);
226		− if (++n == ARRAY_SIZE(demux_masks))
227		− break;
228		− }
229		− }
230		−}

arch/xtensa/variants/s6000/include/variant/core.h+0−431

@@ -1,431 +0,0 @@
1		−/*
2		− * Xtensa processor core configuration information.
3		− *
4		− * This file is subject to the terms and conditions of the GNU General Public
5		− * License. See the file "COPYING" in the main directory of this archive
6		− * for more details.
7		− *
8		− * Copyright (c) 1999-2008 Tensilica Inc.
9		− */
10		−
11		−#ifndef _XTENSA_CORE_CONFIGURATION_H
12		−#define _XTENSA_CORE_CONFIGURATION_H
13		−
14		−
15		−/****************************************************************************
16		− Parameters Useful for Any Code, USER or PRIVILEGED
17		− ****************************************************************************/
18		−
19		−/*
20		− * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21		− * configured, and a value of 0 otherwise. These macros are always defined.
22		− */
23		−
24		−
25		−/*----------------------------------------------------------------------
26		− ISA
27		− ----------------------------------------------------------------------*/
28		−
29		−#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
30		−#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
31		−#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
32		−#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
33		−#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
34		−#define XCHAL_HAVE_DEBUG 1 /* debug option */
35		−#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36		−#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
37		−#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
38		−#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
39		−#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
40		−#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
41		−#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
42		−#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
43		−#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
44		−#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
45		−#define XCHAL_HAVE_L32R 1 /* L32R instruction */
46		−#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
47		−#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
48		−#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
49		−#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B.W18 or B.W15 instr's */
50		−#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
51		−#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
52		−#define XCHAL_HAVE_ABS 1 /* ABS instruction */
53		−/#define XCHAL_HAVE_POPC 0/ /* POPC instruction */
54		−/#define XCHAL_HAVE_CRC 0/ /* CRC instruction */
55		−#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
56		−#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
57		−#define XCHAL_HAVE_SPECULATION 0 /* speculation */
58		−#define XCHAL_HAVE_FULL_RESET 0 /* all regs/state reset */
59		−#define XCHAL_NUM_CONTEXTS 1 /* */
60		−#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
61		−#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
62		−#define XCHAL_HAVE_PRID 0 /* processor ID register */
63		−#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
64		−#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
65		−#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
66		−#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
67		−#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
68		−#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
69		−#define XCHAL_HAVE_FP 1 /* floating point pkg */
70		−#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
71		−#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
72		−#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
73		−
74		−
75		−/*----------------------------------------------------------------------
76		− MISC
77		− ----------------------------------------------------------------------*/
78		−
79		−#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
80		−#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
81		−#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
82		−/* In T1050, applies to selected core load and store instructions (see ISA): */
83		−#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
84		−#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
85		−
86		−#define XCHAL_SW_VERSION 701001 /* sw version of this header */
87		−
88		−#define XCHAL_CORE_ID "stretch_bali" /* alphanum core name
89		− (CoreID) set in the Xtensa
90		− Processor Generator */
91		−
92		−#define XCHAL_BUILD_UNIQUE_ID 0x000104B9 /* 22-bit sw build ID */
93		−
94		−/*
95		− * These definitions describe the hardware targeted by this software.
96		− */
97		−#define XCHAL_HW_CONFIGID0 0xC2F3F9FE /* ConfigID hi 32 bits*/
98		−#define XCHAL_HW_CONFIGID1 0x054104B9 /* ConfigID lo 32 bits*/
99		−#define XCHAL_HW_VERSION_NAME "LX1.0.2" /* full version name */
100		−#define XCHAL_HW_VERSION_MAJOR 2100 /* major ver# of targeted hw */
101		−#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
102		−#define XCHAL_HW_VERSION 210002 /* major100+minor /
103		−#define XCHAL_HW_REL_LX1 1
104		−#define XCHAL_HW_REL_LX1_0 1
105		−#define XCHAL_HW_REL_LX1_0_2 1
106		−#define XCHAL_HW_CONFIGID_RELIABLE 1
107		−/* If software targets a range of hardware versions, these are the bounds: */
108		−#define XCHAL_HW_MIN_VERSION_MAJOR 2100 /* major v of earliest tgt hw */
109		−#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
110		−#define XCHAL_HW_MIN_VERSION 210002 /* earliest targeted hw */
111		−#define XCHAL_HW_MAX_VERSION_MAJOR 2100 /* major v of latest tgt hw */
112		−#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
113		−#define XCHAL_HW_MAX_VERSION 210002 /* latest targeted hw */
114		−
115		−
116		−/*----------------------------------------------------------------------
117		− CACHE
118		− ----------------------------------------------------------------------*/
119		−
120		−#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
121		−#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
122		−#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
123		−#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
124		−
125		−#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */
126		−#define XCHAL_DCACHE_SIZE 32768 /* D-cache size in bytes or 0 */
127		−
128		−#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
129		−
130		−
131		−
132		−
133		−/****************************************************************************
134		− Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
135		− ****************************************************************************/
136		−
137		−
138		−#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
139		−
140		−/*----------------------------------------------------------------------
141		− CACHE
142		− ----------------------------------------------------------------------*/
143		−
144		−#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
145		−
146		−/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
147		−
148		−/* Number of cache sets in log2(lines per way): */
149		−#define XCHAL_ICACHE_SETWIDTH 9
150		−#define XCHAL_DCACHE_SETWIDTH 10
151		−
152		−/* Cache set associativity (number of ways): */
153		−#define XCHAL_ICACHE_WAYS 4
154		−#define XCHAL_DCACHE_WAYS 2
155		−
156		−/* Cache features: */
157		−#define XCHAL_ICACHE_LINE_LOCKABLE 1
158		−#define XCHAL_DCACHE_LINE_LOCKABLE 0
159		−#define XCHAL_ICACHE_ECC_PARITY 0
160		−#define XCHAL_DCACHE_ECC_PARITY 0
161		−
162		−/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
163		−#define XCHAL_CA_BITS 4
164		−
165		−
166		−/*----------------------------------------------------------------------
167		− INTERNAL I/D RAM/ROMs and XLMI
168		− ----------------------------------------------------------------------*/
169		−
170		−#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
171		−#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
172		−#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
173		−#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
174		−#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
175		−#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
176		−
177		−/* Data RAM 0: */
178		−#define XCHAL_DATARAM0_VADDR 0x3FFF0000
179		−#define XCHAL_DATARAM0_PADDR 0x3FFF0000
180		−#define XCHAL_DATARAM0_SIZE 65536
181		−#define XCHAL_DATARAM0_ECC_PARITY 0
182		−
183		−/* XLMI Port 0: */
184		−#define XCHAL_XLMI0_VADDR 0x37F80000
185		−#define XCHAL_XLMI0_PADDR 0x37F80000
186		−#define XCHAL_XLMI0_SIZE 262144
187		−#define XCHAL_XLMI0_ECC_PARITY 0
188		−
189		−
190		−/*----------------------------------------------------------------------
191		− INTERRUPTS and TIMERS
192		− ----------------------------------------------------------------------*/
193		−
194		−#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
195		−#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
196		−#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
197		−#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
198		−#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
199		−#define XCHAL_NUM_INTERRUPTS 27 /* number of interrupts */
200		−#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
201		−#define XCHAL_NUM_EXTINTERRUPTS 20 /* num of external interrupts */
202		−#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
203		− (not including level zero) */
204		−#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
205		− /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
206		−
207		−/* Masks of interrupts at each interrupt level: */
208		−#define XCHAL_INTLEVEL1_MASK 0x01F07FFF
209		−#define XCHAL_INTLEVEL2_MASK 0x02018000
210		−#define XCHAL_INTLEVEL3_MASK 0x04060000
211		−#define XCHAL_INTLEVEL4_MASK 0x00000000
212		−#define XCHAL_INTLEVEL5_MASK 0x00080000
213		−#define XCHAL_INTLEVEL6_MASK 0x00000000
214		−#define XCHAL_INTLEVEL7_MASK 0x00000000
215		−
216		−/* Masks of interrupts at each range 1..n of interrupt levels: */
217		−#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x01F07FFF
218		−#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x03F1FFFF
219		−#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x07F7FFFF
220		−#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x07F7FFFF
221		−#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x07FFFFFF
222		−#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x07FFFFFF
223		−#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x07FFFFFF
224		−
225		−/* Level of each interrupt: */
226		−#define XCHAL_INT0_LEVEL 1
227		−#define XCHAL_INT1_LEVEL 1
228		−#define XCHAL_INT2_LEVEL 1
229		−#define XCHAL_INT3_LEVEL 1
230		−#define XCHAL_INT4_LEVEL 1
231		−#define XCHAL_INT5_LEVEL 1
232		−#define XCHAL_INT6_LEVEL 1
233		−#define XCHAL_INT7_LEVEL 1
234		−#define XCHAL_INT8_LEVEL 1
235		−#define XCHAL_INT9_LEVEL 1
236		−#define XCHAL_INT10_LEVEL 1
237		−#define XCHAL_INT11_LEVEL 1
238		−#define XCHAL_INT12_LEVEL 1
239		−#define XCHAL_INT13_LEVEL 1
240		−#define XCHAL_INT14_LEVEL 1
241		−#define XCHAL_INT15_LEVEL 2
242		−#define XCHAL_INT16_LEVEL 2
243		−#define XCHAL_INT17_LEVEL 3
244		−#define XCHAL_INT18_LEVEL 3
245		−#define XCHAL_INT19_LEVEL 5
246		−#define XCHAL_INT20_LEVEL 1
247		−#define XCHAL_INT21_LEVEL 1
248		−#define XCHAL_INT22_LEVEL 1
249		−#define XCHAL_INT23_LEVEL 1
250		−#define XCHAL_INT24_LEVEL 1
251		−#define XCHAL_INT25_LEVEL 2
252		−#define XCHAL_INT26_LEVEL 3
253		−#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
254		−#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
255		−#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
256		− EXCSAVE/EPS/EPC_n, RFI n) */
257		−
258		−/* Type of each interrupt: */
259		−#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260		−#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261		−#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
262		−#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
263		−#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
264		−#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
265		−#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
266		−#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
267		−#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
268		−#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
269		−#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
270		−#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
271		−#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
272		−#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
273		−#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
274		−#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
275		−#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
276		−#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
277		−#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
278		−#define XCHAL_INT19_TYPE XTHAL_INTTYPE_NMI
279		−#define XCHAL_INT20_TYPE XTHAL_INTTYPE_SOFTWARE
280		−#define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE
281		−#define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE
282		−#define XCHAL_INT23_TYPE XTHAL_INTTYPE_SOFTWARE
283		−#define XCHAL_INT24_TYPE XTHAL_INTTYPE_TIMER
284		−#define XCHAL_INT25_TYPE XTHAL_INTTYPE_TIMER
285		−#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER
286		−
287		−/* Masks of interrupts for each type of interrupt: */
288		−#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xF8000000
289		−#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00F00000
290		−#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
291		−#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0007FFFF
292		−#define XCHAL_INTTYPE_MASK_TIMER 0x07000000
293		−#define XCHAL_INTTYPE_MASK_NMI 0x00080000
294		−#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
295		−
296		−/* Interrupt numbers assigned to specific interrupt sources: */
297		−#define XCHAL_TIMER0_INTERRUPT 24 /* CCOMPARE0 */
298		−#define XCHAL_TIMER1_INTERRUPT 25 /* CCOMPARE1 */
299		−#define XCHAL_TIMER2_INTERRUPT 26 /* CCOMPARE2 */
300		−#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
301		−#define XCHAL_NMI_INTERRUPT 19 /* non-maskable interrupt */
302		−
303		−/* Interrupt numbers for levels at which only one interrupt is configured: */
304		−#define XCHAL_INTLEVEL5_NUM 19
305		−/* (There are many interrupts each at level(s) 1, 2, 3.) */
306		−
307		−
308		−/*
309		− * External interrupt vectors/levels.
310		− * These macros describe how Xtensa processor interrupt numbers
311		− * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
312		− * map to external BInterrupt<n> pins, for those interrupts
313		− * configured as external (level-triggered, edge-triggered, or NMI).
314		− * See the Xtensa processor databook for more details.
315		− */
316		−
317		−/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
318		−#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
319		−#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
320		−#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
321		−#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
322		−#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
323		−#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
324		−#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
325		−#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
326		−#define XCHAL_EXTINT8_NUM 8 /* (intlevel 1) */
327		−#define XCHAL_EXTINT9_NUM 9 /* (intlevel 1) */
328		−#define XCHAL_EXTINT10_NUM 10 /* (intlevel 1) */
329		−#define XCHAL_EXTINT11_NUM 11 /* (intlevel 1) */
330		−#define XCHAL_EXTINT12_NUM 12 /* (intlevel 1) */
331		−#define XCHAL_EXTINT13_NUM 13 /* (intlevel 1) */
332		−#define XCHAL_EXTINT14_NUM 14 /* (intlevel 1) */
333		−#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */
334		−#define XCHAL_EXTINT16_NUM 16 /* (intlevel 2) */
335		−#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */
336		−#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */
337		−#define XCHAL_EXTINT19_NUM 19 /* (intlevel 5) */
338		−
339		−
340		−/*----------------------------------------------------------------------
341		− EXCEPTIONS and VECTORS
342		− ----------------------------------------------------------------------*/
343		−
344		−#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
345		− number: 1 == XEA1 (old)
346		− 2 == XEA2 (new)
347		− 0 == XEAX (extern) */
348		−#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
349		−#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
350		−#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
351		−#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
352		−#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
353		−#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */
354		−#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */
355		−
356		−#define XCHAL_RESET_VECOFS 0x00000000
357		−#define XCHAL_RESET_VECTOR_VADDR 0x3FFE03D0
358		−#define XCHAL_RESET_VECTOR_PADDR 0x3FFE03D0
359		−#define XCHAL_USER_VECOFS 0x00000000
360		−#define XCHAL_USER_VECTOR_VADDR 0x40000220
361		−#define XCHAL_USER_VECTOR_PADDR 0x40000220
362		−#define XCHAL_KERNEL_VECOFS 0x00000000
363		−#define XCHAL_KERNEL_VECTOR_VADDR 0x40000200
364		−#define XCHAL_KERNEL_VECTOR_PADDR 0x40000200
365		−#define XCHAL_DOUBLEEXC_VECOFS 0x00000000
366		−#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400002A0
367		−#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400002A0
368		−#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
369		−#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
370		−#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
371		−#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
372		−#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
373		−#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
374		−#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
375		−#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
376		−#define XCHAL_INTLEVEL2_VECOFS 0x00000000
377		−#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000240
378		−#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000240
379		−#define XCHAL_INTLEVEL3_VECOFS 0x00000000
380		−#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x40000260
381		−#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x40000260
382		−#define XCHAL_INTLEVEL4_VECOFS 0x00000000
383		−#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000390
384		−#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000390
385		−#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
386		−#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
387		−#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
388		−#define XCHAL_NMI_VECOFS 0x00000000
389		−#define XCHAL_NMI_VECTOR_VADDR 0x400003B0
390		−#define XCHAL_NMI_VECTOR_PADDR 0x400003B0
391		−#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
392		−#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
393		−#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
394		−
395		−
396		−/*----------------------------------------------------------------------
397		− DEBUG
398		− ----------------------------------------------------------------------*/
399		−
400		−#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
401		−#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
402		−#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
403		−#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
404		−
405		−
406		−/*----------------------------------------------------------------------
407		− MMU
408		− ----------------------------------------------------------------------*/
409		−
410		−/* See core-matmap.h header file for more details. */
411		−
412		−#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
413		−#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
414		−#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
415		−#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
416		−#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
417		−#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
418		−#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
419		− [autorefill] and protection)
420		− usable for an MMU-based OS */
421		−/* If none of the above last 4 are set, it's a custom TLB configuration. */
422		−
423		−#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
424		−#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
425		−#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
426		−
427		−#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
428		−
429		−
430		−#endif /* _XTENSA_CORE_CONFIGURATION_H */
431		−

arch/xtensa/variants/s6000/include/variant/dmac.h+0−387

@@ -1,387 +0,0 @@
1		−/*
2		− * include/asm-xtensa/variant-s6000/dmac.h
3		− *
4		− * This file is subject to the terms and conditions of the GNU General Public
5		− * License. See the file "COPYING" in the main directory of this archive
6		− * for more details.
7		− *
8		− * Copyright (C) 2006 Tensilica Inc.
9		− * Copyright (C) 2008 Emlix GmbH <info@emlix.com>
10		− * Authors: Fabian Godehardt <fg@emlix.com>
11		− * Oskar Schirmer <oskar@scara.com>
12		− * Daniel Gloeckner <dg@emlix.com>
13		− */
14		−
15		−#ifndef __ASM_XTENSA_S6000_DMAC_H
16		−#define __ASM_XTENSA_S6000_DMAC_H
17		−#include <linux/io.h>
18		−#include <variant/hardware.h>
19		−
20		−/* DMA global */
21		−
22		−#define S6_DMA_INTSTAT0 0x000
23		−#define S6_DMA_INTSTAT1 0x004
24		−#define S6_DMA_INTENABLE0 0x008
25		−#define S6_DMA_INTENABLE1 0x00C
26		−#define S6_DMA_INTRAW0 0x010
27		−#define S6_DMA_INTRAW1 0x014
28		−#define S6_DMA_INTCLEAR0 0x018
29		−#define S6_DMA_INTCLEAR1 0x01C
30		−#define S6_DMA_INTSET0 0x020
31		−#define S6_DMA_INTSET1 0x024
32		−#define S6_DMA_INT0_UNDER 0
33		−#define S6_DMA_INT0_OVER 16
34		−#define S6_DMA_INT1_CHANNEL 0
35		−#define S6_DMA_INT1_MASTER 16
36		−#define S6_DMA_INT1_MASTER_MASK 7
37		−#define S6_DMA_TERMCNTIRQSTAT 0x028
38		−#define S6_DMA_TERMCNTIRQCLR 0x02C
39		−#define S6_DMA_TERMCNTIRQSET 0x030
40		−#define S6_DMA_PENDCNTIRQSTAT 0x034
41		−#define S6_DMA_PENDCNTIRQCLR 0x038
42		−#define S6_DMA_PENDCNTIRQSET 0x03C
43		−#define S6_DMA_LOWWMRKIRQSTAT 0x040
44		−#define S6_DMA_LOWWMRKIRQCLR 0x044
45		−#define S6_DMA_LOWWMRKIRQSET 0x048
46		−#define S6_DMA_MASTERERRINFO 0x04C
47		−#define S6_DMA_MASTERERR_CHAN(n) (4*(n))
48		−#define S6_DMA_MASTERERR_CHAN_MASK 0xF
49		−#define S6_DMA_DESCRFIFO0 0x050
50		−#define S6_DMA_DESCRFIFO1 0x054
51		−#define S6_DMA_DESCRFIFO2 0x058
52		−#define S6_DMA_DESCRFIFO2_AUTODISABLE 24
53		−#define S6_DMA_DESCRFIFO3 0x05C
54		−#define S6_DMA_MASTER0START 0x060
55		−#define S6_DMA_MASTER0END 0x064
56		−#define S6_DMA_MASTER1START 0x068
57		−#define S6_DMA_MASTER1END 0x06C
58		−#define S6_DMA_NEXTFREE 0x070
59		−#define S6_DMA_NEXTFREE_CHAN 0
60		−#define S6_DMA_NEXTFREE_CHAN_MASK 0x1F
61		−#define S6_DMA_NEXTFREE_ENA 16
62		−#define S6_DMA_NEXTFREE_ENA_MASK ((1 << 16) - 1)
63		−#define S6_DMA_DPORTCTRLGRP(p) ((p) * 4 + 0x074)
64		−#define S6_DMA_DPORTCTRLGRP_FRAMEREP 0
65		−#define S6_DMA_DPORTCTRLGRP_NRCHANS 1
66		−#define S6_DMA_DPORTCTRLGRP_NRCHANS_1 0
67		−#define S6_DMA_DPORTCTRLGRP_NRCHANS_3 1
68		−#define S6_DMA_DPORTCTRLGRP_NRCHANS_4 2
69		−#define S6_DMA_DPORTCTRLGRP_NRCHANS_2 3
70		−#define S6_DMA_DPORTCTRLGRP_ENA 31
71		−
72		−
73		−/* DMA per channel */
74		−
75		−#define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100)
76		−#define DMA_INDEX_CHNL(addr) (((addr) >> 8) & 0xF)
77		−#define DMA_MASK_DMAC(addr) ((addr) & 0xFFFF0000)
78		−#define S6_DMA_CHNCTRL 0x000
79		−#define S6_DMA_CHNCTRL_ENABLE 0
80		−#define S6_DMA_CHNCTRL_PAUSE 1
81		−#define S6_DMA_CHNCTRL_PRIO 2
82		−#define S6_DMA_CHNCTRL_PRIO_MASK 3
83		−#define S6_DMA_CHNCTRL_PERIPHXFER 4
84		−#define S6_DMA_CHNCTRL_PERIPHENA 5
85		−#define S6_DMA_CHNCTRL_SRCINC 6
86		−#define S6_DMA_CHNCTRL_DSTINC 7
87		−#define S6_DMA_CHNCTRL_BURSTLOG 8
88		−#define S6_DMA_CHNCTRL_BURSTLOG_MASK 7
89		−#define S6_DMA_CHNCTRL_DESCFIFODEPTH 12
90		−#define S6_DMA_CHNCTRL_DESCFIFODEPTH_MASK 0x1F
91		−#define S6_DMA_CHNCTRL_DESCFIFOFULL 17
92		−#define S6_DMA_CHNCTRL_BWCONSEL 18
93		−#define S6_DMA_CHNCTRL_BWCONENA 19
94		−#define S6_DMA_CHNCTRL_PENDGCNTSTAT 20
95		−#define S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK 0x3F
96		−#define S6_DMA_CHNCTRL_LOWWMARK 26
97		−#define S6_DMA_CHNCTRL_LOWWMARK_MASK 0xF
98		−#define S6_DMA_CHNCTRL_TSTAMP 30
99		−#define S6_DMA_TERMCNTNB 0x004
100		−#define S6_DMA_TERMCNTNB_MASK 0xFFFF
101		−#define S6_DMA_TERMCNTTMO 0x008
102		−#define S6_DMA_TERMCNTSTAT 0x00C
103		−#define S6_DMA_TERMCNTSTAT_MASK 0xFF
104		−#define S6_DMA_CMONCHUNK 0x010
105		−#define S6_DMA_SRCSKIP 0x014
106		−#define S6_DMA_DSTSKIP 0x018
107		−#define S6_DMA_CUR_SRC 0x024
108		−#define S6_DMA_CUR_DST 0x028
109		−#define S6_DMA_TIMESTAMP 0x030
110		−
111		−/* DMA channel lists */
112		−
113		−#define S6_DPDMA_CHAN(stream, channel) (4 * (stream) + (channel))
114		−#define S6_DPDMA_NB 16
115		−
116		−#define S6_HIFDMA_GMACTX 0
117		−#define S6_HIFDMA_GMACRX 1
118		−#define S6_HIFDMA_I2S0 2
119		−#define S6_HIFDMA_I2S1 3
120		−#define S6_HIFDMA_EGIB 4
121		−#define S6_HIFDMA_PCITX 5
122		−#define S6_HIFDMA_PCIRX 6
123		−#define S6_HIFDMA_NB 7
124		−
125		−#define S6_NIDMA_NB 4
126		−
127		−#define S6_LMSDMA_NB 12
128		−
129		−/* controller access */
130		−
131		−#define S6_DMAC_NB 4
132		−#define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB)
133		−
134		−struct s6dmac_ctrl {
135		− u32 dmac;
136		− spinlock_t lock;
137		− u8 chan_nb;
138		−};
139		−
140		−extern struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
141		−
142		−
143		−/* DMA control, per channel */
144		−
145		−static inline int s6dmac_fifo_full(u32 dmac, int chan)
146		−{
147		− return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
148		− & (1 << S6_DMA_CHNCTRL_DESCFIFOFULL)) && 1;
149		−}
150		−
151		−static inline int s6dmac_termcnt_irq(u32 dmac, int chan)
152		−{
153		− u32 m = 1 << chan;
154		− int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1;
155		− if (r)
156		− writel(m, dmac + S6_DMA_TERMCNTIRQCLR);
157		− return r;
158		−}
159		−
160		−static inline int s6dmac_pendcnt_irq(u32 dmac, int chan)
161		−{
162		− u32 m = 1 << chan;
163		− int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1;
164		− if (r)
165		− writel(m, dmac + S6_DMA_PENDCNTIRQCLR);
166		− return r;
167		−}
168		−
169		−static inline int s6dmac_lowwmark_irq(u32 dmac, int chan)
170		−{
171		− int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0;
172		− if (r)
173		− writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR);
174		− return r;
175		−}
176		−
177		−static inline u32 s6dmac_pending_count(u32 dmac, int chan)
178		−{
179		− return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
180		− >> S6_DMA_CHNCTRL_PENDGCNTSTAT)
181		− & S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK;
182		−}
183		−
184		−static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n)
185		−{
186		− n &= S6_DMA_TERMCNTNB_MASK;
187		− n \|= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)
188		− & ~S6_DMA_TERMCNTNB_MASK;
189		− writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
190		−}
191		−
192		−static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan)
193		−{
194		− return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB))
195		− & S6_DMA_TERMCNTNB_MASK;
196		−}
197		−
198		−static inline u32 s6dmac_timestamp(u32 dmac, int chan)
199		−{
200		− return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP);
201		−}
202		−
203		−static inline u32 s6dmac_cur_src(u32 dmac, int chan)
204		−{
205		− return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC);
206		−}
207		−
208		−static inline u32 s6dmac_cur_dst(u32 dmac, int chan)
209		−{
210		− return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST);
211		−}
212		−
213		−static inline void s6dmac_disable_chan(u32 dmac, int chan)
214		−{
215		− u32 ctrl;
216		− writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
217		− & ~(1 << S6_DMA_CHNCTRL_ENABLE),
218		− DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
219		− do
220		− ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
221		− while (ctrl & (1 << S6_DMA_CHNCTRL_ENABLE));
222		−}
223		−
224		−static inline void s6dmac_set_stride_skip(u32 dmac, int chan,
225		− int comchunk, /* 0: disable scatter/gather */
226		− int srcskip, int dstskip)
227		−{
228		− writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
229		− writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
230		− writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
231		−}
232		−
233		−static inline void s6dmac_enable_chan(u32 dmac, int chan,
234		− int prio, /* 0 (highest) .. 3 (lowest) */
235		− int periphxfer, /* <0: disable p.req.line, 0..1: mode */
236		− int srcinc, int dstinc, /* 0: dont increment src/dst address */
237		− int comchunk, /* 0: disable scatter/gather */
238		− int srcskip, int dstskip,
239		− int burstsize, /* 4 for I2S, 7 for everything else */
240		− int bandwidthconserve, /* <0: disable, 0..1: select */
241		− int lowwmark, /* 0..15 */
242		− int timestamp, /* 0: disable timestamp */
243		− int enable) /* 0: disable for now */
244		−{
245		− writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
246		− writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO);
247		− writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK,
248		− DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
249		− s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip);
250		− writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) \|
251		− (prio << S6_DMA_CHNCTRL_PRIO) \|
252		− (((periphxfer > 0) ? 1 : 0) << S6_DMA_CHNCTRL_PERIPHXFER) \|
253		− (((periphxfer < 0) ? 0 : 1) << S6_DMA_CHNCTRL_PERIPHENA) \|
254		− ((srcinc ? 1 : 0) << S6_DMA_CHNCTRL_SRCINC) \|
255		− ((dstinc ? 1 : 0) << S6_DMA_CHNCTRL_DSTINC) \|
256		− (burstsize << S6_DMA_CHNCTRL_BURSTLOG) \|
257		− (((bandwidthconserve > 0) ? 1 : 0) << S6_DMA_CHNCTRL_BWCONSEL) \|
258		− (((bandwidthconserve < 0) ? 0 : 1) << S6_DMA_CHNCTRL_BWCONENA) \|
259		− (lowwmark << S6_DMA_CHNCTRL_LOWWMARK) \|
260		− ((timestamp ? 1 : 0) << S6_DMA_CHNCTRL_TSTAMP),
261		− DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
262		−}
263		−
264		−
265		−/* DMA control, per engine */
266		−
267		−static inline unsigned _dmac_addr_index(u32 dmac)
268		−{
269		− unsigned i = S6_DMAC_INDEX(dmac);
270		− if (s6dmac_ctrl[i].dmac != dmac)
271		− BUG();
272		− return i;
273		−}
274		−
275		−static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask)
276		−{
277		− writel(mask, dmac + S6_DMA_TERMCNTIRQCLR);
278		− writel(mask, dmac + S6_DMA_PENDCNTIRQCLR);
279		− writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR);
280		− writel(readl(dmac + S6_DMA_INTENABLE0)
281		− & ~((mask << S6_DMA_INT0_UNDER) \| (mask << S6_DMA_INT0_OVER)),
282		− dmac + S6_DMA_INTENABLE0);
283		− writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL),
284		− dmac + S6_DMA_INTENABLE1);
285		− writel((mask << S6_DMA_INT0_UNDER) \| (mask << S6_DMA_INT0_OVER),
286		− dmac + S6_DMA_INTCLEAR0);
287		− writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1);
288		−}
289		−
290		−/*
291		− * request channel from specified engine
292		− * with chan<0, accept any channel
293		− * further parameters see s6dmac_enable_chan
294		− * returns < 0 upon error, channel nb otherwise
295		− */
296		−static inline int s6dmac_request_chan(u32 dmac, int chan,
297		− int prio,
298		− int periphxfer,
299		− int srcinc, int dstinc,
300		− int comchunk,
301		− int srcskip, int dstskip,
302		− int burstsize,
303		− int bandwidthconserve,
304		− int lowwmark,
305		− int timestamp,
306		− int enable)
307		−{
308		− int r = chan;
309		− unsigned long flags;
310		− spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
311		− spin_lock_irqsave(spinl, flags);
312		− if (r < 0) {
313		− r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN)
314		− & S6_DMA_NEXTFREE_CHAN_MASK;
315		− }
316		− if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) {
317		− if (chan < 0)
318		− r = -EBUSY;
319		− else
320		− r = -ENXIO;
321		− } else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA)
322		− >> r) & 1) {
323		− r = -EBUSY;
324		− } else {
325		− s6dmac_enable_chan(dmac, r, prio, periphxfer,
326		− srcinc, dstinc, comchunk, srcskip, dstskip, burstsize,
327		− bandwidthconserve, lowwmark, timestamp, enable);
328		− }
329		− spin_unlock_irqrestore(spinl, flags);
330		− return r;
331		−}
332		−
333		−static inline void s6dmac_put_fifo(u32 dmac, int chan,
334		− u32 src, u32 dst, u32 size)
335		−{
336		− unsigned long flags;
337		− spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
338		− spin_lock_irqsave(spinl, flags);
339		− writel(src, dmac + S6_DMA_DESCRFIFO0);
340		− writel(dst, dmac + S6_DMA_DESCRFIFO1);
341		− writel(size, dmac + S6_DMA_DESCRFIFO2);
342		− writel(chan, dmac + S6_DMA_DESCRFIFO3);
343		− spin_unlock_irqrestore(spinl, flags);
344		−}
345		−
346		−static inline u32 s6dmac_channel_enabled(u32 dmac, int chan)
347		−{
348		− return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) &
349		− (1 << S6_DMA_CHNCTRL_ENABLE);
350		−}
351		−
352		−/*
353		− * group 1-4 data port channels
354		− * with port=0..3, nrch=1-4 channels,
355		− * frrep=0/1 (dis- or enable frame repeat)
356		− */
357		−static inline void s6dmac_dp_setup_group(u32 dmac, int port,
358		− int nrch, int frrep)
359		−{
360		− static const u8 mask[4] = {0, 3, 1, 2};
361		− BUG_ON(dmac != S6_REG_DPDMA);
362		− if ((port < 0) \|\| (port > 3) \|\| (nrch < 1) \|\| (nrch > 4))
363		− return;
364		− writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS)
365		− \| ((frrep ? 1 : 0) << S6_DMA_DPORTCTRLGRP_FRAMEREP),
366		− dmac + S6_DMA_DPORTCTRLGRP(port));
367		−}
368		−
369		−static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable)
370		−{
371		− u32 tmp;
372		− BUG_ON(dmac != S6_REG_DPDMA);
373		− tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port));
374		− if (enable)
375		− tmp \|= (1 << S6_DMA_DPORTCTRLGRP_ENA);
376		− else
377		− tmp &= ~(1 << S6_DMA_DPORTCTRLGRP_ENA);
378		− writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port));
379		−}
380		−
381		−extern void s6dmac_put_fifo_cache(u32 dmac, int chan,
382		− u32 src, u32 dst, u32 size);
383		−extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask);
384		−extern u32 s6dmac_int_sources(u32 dmac, u32 channel);
385		−extern void s6dmac_release_chan(u32 dmac, int chan);
386		−
387		−#endif /* __ASM_XTENSA_S6000_DMAC_H */

arch/xtensa/variants/s6000/include/variant/gpio.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef _XTENSA_VARIANT_S6000_GPIO_H
2		−#define _XTENSA_VARIANT_S6000_GPIO_H
3		−
4		−extern int s6_gpio_init(u32 afsel);
5		−
6		−#endif /* _XTENSA_VARIANT_S6000_GPIO_H */

arch/xtensa/variants/s6000/include/variant/hardware.h+0−259

@@ -1,259 +0,0 @@
1		−#ifndef __XTENSA_S6000_HARDWARE_H
2		−#define __XTENSA_S6000_HARDWARE_H
3		−
4		−#define S6_SCLK 1843200
5		−
6		−#define S6_MEM_REG 0x20000000
7		−#define S6_MEM_EFI 0x33F00000
8		−#define S6_MEM_PCIE_DATARAM1 0x34000000
9		−#define S6_MEM_XLMI 0x37F80000
10		−#define S6_MEM_PIF_DATARAM1 0x37FFC000
11		−#define S6_MEM_GMAC 0x38000000
12		−#define S6_MEM_I2S 0x3A000000
13		−#define S6_MEM_EGIB 0x3C000000
14		−#define S6_MEM_PCIE_CFG 0x3E000000
15		−#define S6_MEM_PIF_DATARAM 0x3FFE0000
16		−#define S6_MEM_XLMI_DATARAM 0x3FFF0000
17		−#define S6_MEM_DDR 0x40000000
18		−#define S6_MEM_PCIE_APER 0xC0000000
19		−#define S6_MEM_AUX 0xF0000000
20		−
21		−/* Device addresses */
22		−
23		−#define S6_REG_SCB S6_MEM_REG
24		−#define S6_REG_NB (S6_REG_SCB + 0x10000)
25		−#define S6_REG_LMSDMA (S6_REG_SCB + 0x20000)
26		−#define S6_REG_NI (S6_REG_SCB + 0x30000)
27		−#define S6_REG_NIDMA (S6_REG_SCB + 0x40000)
28		−#define S6_REG_NS (S6_REG_SCB + 0x50000)
29		−#define S6_REG_DDR (S6_REG_SCB + 0x60000)
30		−#define S6_REG_GREG1 (S6_REG_SCB + 0x70000)
31		−#define S6_REG_DP (S6_REG_SCB + 0x80000)
32		−#define S6_REG_DPDMA (S6_REG_SCB + 0x90000)
33		−#define S6_REG_EGIB (S6_REG_SCB + 0xA0000)
34		−#define S6_REG_PCIE (S6_REG_SCB + 0xB0000)
35		−#define S6_REG_I2S (S6_REG_SCB + 0xC0000)
36		−#define S6_REG_GMAC (S6_REG_SCB + 0xD0000)
37		−#define S6_REG_HIFDMA (S6_REG_SCB + 0xE0000)
38		−#define S6_REG_GREG2 (S6_REG_SCB + 0xF0000)
39		−
40		−#define S6_REG_APB S6_REG_SCB
41		−#define S6_REG_UART (S6_REG_APB + 0x0000)
42		−#define S6_REG_INTC (S6_REG_APB + 0x2000)
43		−#define S6_REG_SPI (S6_REG_APB + 0x3000)
44		−#define S6_REG_I2C (S6_REG_APB + 0x4000)
45		−#define S6_REG_GPIO (S6_REG_APB + 0x8000)
46		−
47		−/* Global register block */
48		−
49		−#define S6_GREG1_PLL_LOCKCLEAR 0x000
50		−#define S6_GREG1_PLL_LOCK_SYS 0
51		−#define S6_GREG1_PLL_LOCK_IO 1
52		−#define S6_GREG1_PLL_LOCK_AIM 2
53		−#define S6_GREG1_PLL_LOCK_DP0 3
54		−#define S6_GREG1_PLL_LOCK_DP2 4
55		−#define S6_GREG1_PLL_LOCK_DDR 5
56		−#define S6_GREG1_PLL_LOCKSTAT 0x004
57		−#define S6_GREG1_PLL_LOCKSTAT_CURLOCK 0
58		−#define S6_GREG1_PLL_LOCKSTAT_EVERUNLCK 8
59		−#define S6_GREG1_PLLSEL 0x010
60		−#define S6_GREG1_PLLSEL_AIM 0
61		−#define S6_GREG1_PLLSEL_AIM_DDR2 0
62		−#define S6_GREG1_PLLSEL_AIM_300MHZ 1
63		−#define S6_GREG1_PLLSEL_AIM_240MHZ 2
64		−#define S6_GREG1_PLLSEL_AIM_200MHZ 3
65		−#define S6_GREG1_PLLSEL_AIM_150MHZ 4
66		−#define S6_GREG1_PLLSEL_AIM_120MHZ 5
67		−#define S6_GREG1_PLLSEL_AIM_40MHZ 6
68		−#define S6_GREG1_PLLSEL_AIM_PLLAIMREF 7
69		−#define S6_GREG1_PLLSEL_AIM_MASK 7
70		−#define S6_GREG1_PLLSEL_DDR 8
71		−#define S6_GREG1_PLLSEL_DDR_HS 0
72		−#define S6_GREG1_PLLSEL_DDR_333MHZ 1
73		−#define S6_GREG1_PLLSEL_DDR_250MHZ 2
74		−#define S6_GREG1_PLLSEL_DDR_200MHZ 3
75		−#define S6_GREG1_PLLSEL_DDR_167MHZ 4
76		−#define S6_GREG1_PLLSEL_DDR_100MHZ 5
77		−#define S6_GREG1_PLLSEL_DDR_33MHZ 6
78		−#define S6_GREG1_PLLSEL_DDR_PLLIOREF 7
79		−#define S6_GREG1_PLLSEL_DDR_MASK 7
80		−#define S6_GREG1_PLLSEL_GMAC 16
81		−#define S6_GREG1_PLLSEL_GMAC_125MHZ 0
82		−#define S6_GREG1_PLLSEL_GMAC_25MHZ 1
83		−#define S6_GREG1_PLLSEL_GMAC_2500KHZ 2
84		−#define S6_GREG1_PLLSEL_GMAC_EXTERN 3
85		−#define S6_GREG1_PLLSEL_GMAC_MASK 3
86		−#define S6_GREG1_PLLSEL_GMII 18
87		−#define S6_GREG1_PLLSEL_GMII_111MHZ 0
88		−#define S6_GREG1_PLLSEL_GMII_IOREF 1
89		−#define S6_GREG1_PLLSEL_GMII_NONE 2
90		−#define S6_GREG1_PLLSEL_GMII_125MHZ 3
91		−#define S6_GREG1_PLLSEL_GMII_MASK 3
92		−#define S6_GREG1_SYSUNLOCKCNT 0x020
93		−#define S6_GREG1_IOUNLOCKCNT 0x024
94		−#define S6_GREG1_AIMUNLOCKCNT 0x028
95		−#define S6_GREG1_DP0UNLOCKCNT 0x02C
96		−#define S6_GREG1_DP2UNLOCKCNT 0x030
97		−#define S6_GREG1_DDRUNLOCKCNT 0x034
98		−#define S6_GREG1_CLKBAL0 0x040
99		−#define S6_GREG1_CLKBAL0_LSGB 0
100		−#define S6_GREG1_CLKBAL0_LSPX 8
101		−#define S6_GREG1_CLKBAL0_MEMDO 16
102		−#define S6_GREG1_CLKBAL0_HSXT1 24
103		−#define S6_GREG1_CLKBAL1 0x044
104		−#define S6_GREG1_CLKBAL1_HSISEF 0
105		−#define S6_GREG1_CLKBAL1_HSNI 8
106		−#define S6_GREG1_CLKBAL1_HSNS 16
107		−#define S6_GREG1_CLKBAL1_HSISEFCFG 24
108		−#define S6_GREG1_CLKBAL2 0x048
109		−#define S6_GREG1_CLKBAL2_LSNB 0
110		−#define S6_GREG1_CLKBAL2_LSSB 8
111		−#define S6_GREG1_CLKBAL2_LSREST 24
112		−#define S6_GREG1_CLKBAL3 0x04C
113		−#define S6_GREG1_CLKBAL3_ISEFXAD 0
114		−#define S6_GREG1_CLKBAL3_ISEFLMS 8
115		−#define S6_GREG1_CLKBAL3_ISEFISEF 16
116		−#define S6_GREG1_CLKBAL3_DDRDD 24
117		−#define S6_GREG1_CLKBAL4 0x050
118		−#define S6_GREG1_CLKBAL4_DDRDP 0
119		−#define S6_GREG1_CLKBAL4_DDRDO 8
120		−#define S6_GREG1_CLKBAL4_DDRNB 16
121		−#define S6_GREG1_CLKBAL4_DDRLMS 24
122		−#define S6_GREG1_BLOCKENA 0x100
123		−#define S6_GREG1_BLOCK_DDR 0
124		−#define S6_GREG1_BLOCK_DP 1
125		−#define S6_GREG1_BLOCK_NSNI 2
126		−#define S6_GREG1_BLOCK_PCIE 3
127		−#define S6_GREG1_BLOCK_GMAC 4
128		−#define S6_GREG1_BLOCK_I2S 5
129		−#define S6_GREG1_BLOCK_EGIB 6
130		−#define S6_GREG1_BLOCK_SB 7
131		−#define S6_GREG1_BLOCK_XT1 8
132		−#define S6_GREG1_CLKGATE 0x104
133		−#define S6_GREG1_BGATE_AIMNORTH 9
134		−#define S6_GREG1_BGATE_AIMEAST 10
135		−#define S6_GREG1_BGATE_AIMWEST 11
136		−#define S6_GREG1_BGATE_AIMSOUTH 12
137		−#define S6_GREG1_CHIPRES 0x108
138		−#define S6_GREG1_CHIPRES_SOFTRES 0
139		−#define S6_GREG1_CHIPRES_LOSTLOCK 1
140		−#define S6_GREG1_RESETCAUSE 0x10C
141		−#define S6_GREG1_RESETCAUSE_RESETN 0
142		−#define S6_GREG1_RESETCAUSE_GLOBAL 1
143		−#define S6_GREG1_RESETCAUSE_WDOGTIMER 2
144		−#define S6_GREG1_RESETCAUSE_SWCHIP 3
145		−#define S6_GREG1_RESETCAUSE_PLLSYSLOSS 4
146		−#define S6_GREG1_RESETCAUSE_PCIE 5
147		−#define S6_GREG1_RESETCAUSE_CREATEDGLOB 6
148		−#define S6_GREG1_REFCLOCKCNT 0x110
149		−#define S6_GREG1_RESETTIMER 0x114
150		−#define S6_GREG1_NMITIMER 0x118
151		−#define S6_GREG1_GLOBAL_TIMER 0x11C
152		−#define S6_GREG1_TIMER0 0x180
153		−#define S6_GREG1_TIMER1 0x184
154		−#define S6_GREG1_UARTCLOCKSEL 0x204
155		−#define S6_GREG1_CHIPVERSPACKG 0x208
156		−#define S6_GREG1_CHIPVERSPACKG_CHIPVID 0
157		−#define S6_GREG1_CHIPVERSPACKG_PACKSEL 8
158		−#define S6_GREG1_ONDIETERMCTRL 0x20C
159		−#define S6_GREG1_ONDIETERMCTRL_WEST 0
160		−#define S6_GREG1_ONDIETERMCTRL_NORTH 2
161		−#define S6_GREG1_ONDIETERMCTRL_EAST 4
162		−#define S6_GREG1_ONDIETERMCTRL_SOUTH 6
163		−#define S6_GREG1_ONDIETERMCTRL_NONE 0
164		−#define S6_GREG1_ONDIETERMCTRL_75OHM 2
165		−#define S6_GREG1_ONDIETERMCTRL_MASK 3
166		−#define S6_GREG1_BOOT_CFG0 0x210
167		−#define S6_GREG1_BOOT_CFG0_AIMSTRONG 1
168		−#define S6_GREG1_BOOT_CFG0_MINIBOOTDL 2
169		−#define S6_GREG1_BOOT_CFG0_OCDGPIO8SET 5
170		−#define S6_GREG1_BOOT_CFG0_OCDGPIOENA 6
171		−#define S6_GREG1_BOOT_CFG0_DOWNSTREAM 7
172		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV 8
173		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_300MHZ 1
174		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_240MHZ 2
175		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_200MHZ 3
176		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_150MHZ 4
177		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_120MHZ 5
178		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_40MHZ 6
179		−#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK 7
180		−#define S6_GREG1_BOOT_CFG0_BALHSLMS 12
181		−#define S6_GREG1_BOOT_CFG0_BALHSNB 18
182		−#define S6_GREG1_BOOT_CFG0_BALHSXAD 24
183		−#define S6_GREG1_BOOT_CFG1 0x214
184		−#define S6_GREG1_BOOT_CFG1_PCIE1LANE 1
185		−#define S6_GREG1_BOOT_CFG1_MPLLPRESCALE 2
186		−#define S6_GREG1_BOOT_CFG1_MPLLNCY 4
187		−#define S6_GREG1_BOOT_CFG1_MPLLNCY5 9
188		−#define S6_GREG1_BOOT_CFG1_BALHSREST 14
189		−#define S6_GREG1_BOOT_CFG1_BALHSPSMEMS 20
190		−#define S6_GREG1_BOOT_CFG1_BALLSGI 26
191		−#define S6_GREG1_BOOT_CFG2 0x218
192		−#define S6_GREG1_BOOT_CFG2_PEID 0
193		−#define S6_GREG1_BOOT_CFG3 0x21C
194		−#define S6_GREG1_DRAMBUSYHOLDOF 0x220
195		−#define S6_GREG1_DRAMBUSYHOLDOF_XT0 0
196		−#define S6_GREG1_DRAMBUSYHOLDOF_XT1 4
197		−#define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK 7
198		−#define S6_GREG1_PCIEBAR1SIZE 0x224
199		−#define S6_GREG1_PCIEBAR2SIZE 0x228
200		−#define S6_GREG1_PCIEVENDOR 0x22C
201		−#define S6_GREG1_PCIEDEVICE 0x230
202		−#define S6_GREG1_PCIEREV 0x234
203		−#define S6_GREG1_PCIECLASS 0x238
204		−#define S6_GREG1_XT1DCACHEMISS 0x240
205		−#define S6_GREG1_XT1ICACHEMISS 0x244
206		−#define S6_GREG1_HWSEMAPHORE(n) (0x400 + 4 * (n))
207		−#define S6_GREG1_HWSEMAPHORE_NB 16
208		−
209		−/* peripheral interrupt numbers */
210		−
211		−#define S6_INTC_GPIO(n) (n) /* 0..3 */
212		−#define S6_INTC_I2C 4
213		−#define S6_INTC_SPI 5
214		−#define S6_INTC_NB_ERR 6
215		−#define S6_INTC_DMA_LMSERR 7
216		−#define S6_INTC_DMA_LMSLOWWMRK(n) (8 + (n)) /* 0..11 */
217		−#define S6_INTC_DMA_LMSPENDCNT(n) (20 + (n)) /* 0..11 */
218		−#define S6_INTC_DMA HOSTLOWWMRK(n) (32 + (n)) /* 0..6 */
219		−#define S6_INTC_DMA_HOSTPENDCNT(n) (39 + (n)) /* 0..6 */
220		−#define S6_INTC_DMA_HOSTERR 46
221		−#define S6_INTC_UART(n) (47 + (n)) /* 0..1 */
222		−#define S6_INTC_XAD 49
223		−#define S6_INTC_NI_ERR 50
224		−#define S6_INTC_NI_INFIFOFULL 51
225		−#define S6_INTC_DMA_NIERR 52
226		−#define S6_INTC_DMA_NILOWWMRK(n) (53 + (n)) /* 0..3 */
227		−#define S6_INTC_DMA_NIPENDCNT(n) (57 + (n)) /* 0..3 */
228		−#define S6_INTC_DDR 61
229		−#define S6_INTC_NS_ERR 62
230		−#define S6_INTC_EFI_CFGERR 63
231		−#define S6_INTC_EFI_ISEFTEST 64
232		−#define S6_INTC_EFI_WRITEERR 65
233		−#define S6_INTC_NMI_TIMER 66
234		−#define S6_INTC_PLLLOCK_SYS 67
235		−#define S6_INTC_PLLLOCK_IO 68
236		−#define S6_INTC_PLLLOCK_AIM 69
237		−#define S6_INTC_PLLLOCK_DP0 70
238		−#define S6_INTC_PLLLOCK_DP2 71
239		−#define S6_INTC_I2S_ERR 72
240		−#define S6_INTC_GMAC_STAT 73
241		−#define S6_INTC_GMAC_ERR 74
242		−#define S6_INTC_GIB_ERR 75
243		−#define S6_INTC_PCIE_ERR 76
244		−#define S6_INTC_PCIE_MSI(n) (77 + (n)) /* 0..3 */
245		−#define S6_INTC_PCIE_INTA 81
246		−#define S6_INTC_PCIE_INTB 82
247		−#define S6_INTC_PCIE_INTC 83
248		−#define S6_INTC_PCIE_INTD 84
249		−#define S6_INTC_SW(n) (85 + (n)) /* 0..9 */
250		−#define S6_INTC_SW_ENABLE(n) (85 + 256 + (n))
251		−#define S6_INTC_DMA_DP_ERR 95
252		−#define S6_INTC_DMA_DPLOWWMRK(n) (96 + (n)) /* 0..3 */
253		−#define S6_INTC_DMA_DPPENDCNT(n) (100 + (n)) /* 0..3 */
254		−#define S6_INTC_DMA_DPTERMCNT(n) (104 + (n)) /* 0..3 */
255		−#define S6_INTC_TIMER0 108
256		−#define S6_INTC_TIMER1 109
257		−#define S6_INTC_DMA_HOSTTERMCNT(n) (110 + (n)) /* 0..6 */
258		−
259		−#endif /* __XTENSA_S6000_HARDWARE_H */

arch/xtensa/variants/s6000/include/variant/irq.h+0−8

@@ -1,8 +0,0 @@
1		−#ifndef _XTENSA_S6000_IRQ_H
2		−#define _XTENSA_S6000_IRQ_H
3		−
4		−#define VARIANT_NR_IRQS 8 /* GPIO interrupts */
5		−
6		−extern void variant_irq_enable(unsigned int irq);
7		−
8		−#endif /* __XTENSA_S6000_IRQ_H */

arch/xtensa/variants/s6000/include/variant/tie-asm.h+0−304

@@ -1,304 +0,0 @@
1		−/*
2		− * This header file contains assembly-language definitions (assembly
3		− * macros, etc.) for this specific Xtensa processor's TIE extensions
4		− * and options. It is customized to this Xtensa processor configuration.
5		− *
6		− * This file is subject to the terms and conditions of the GNU General Public
7		− * License. See the file "COPYING" in the main directory of this archive
8		− * for more details.
9		− *
10		− * Copyright (C) 1999-2008 Tensilica Inc.
11		− */
12		−
13		−#ifndef _XTENSA_CORE_TIE_ASM_H
14		−#define _XTENSA_CORE_TIE_ASM_H
15		−
16		−/* Selection parameter values for save-area save/restore macros: */
17		−/* Option vs. TIE: */
18		−#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19		−#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20		−/* Whether used automatically by compiler: */
21		−#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22		−#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23		−/* ABI handling across function calls: */
24		−#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25		−#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26		−#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27		−/* Misc */
28		−#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29		−
30		−
31		−
32		−/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33		− * (not including zero-overhead loop registers).
34		− * Save area ptr (clobbered): ptr (16 byte aligned)
35		− * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36		− */
37		− .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38		− xchal_sa_start \continue, \ofs
39		− .ifeq (XTHAL_SAS_OPT \| XTHAL_SAS_NOCC \| XTHAL_SAS_CALR) & ~\select
40		− xchal_sa_align \ptr, 0, 1024-4, 4, 4
41		− rsr \at1, BR // boolean option
42		− s32i \at1, \ptr, .Lxchal_ofs_ + 0
43		− .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44		− .endif
45		− .endm // xchal_ncp_store
46		−
47		−/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48		− * (not including zero-overhead loop registers).
49		− * Save area ptr (clobbered): ptr (16 byte aligned)
50		− * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51		− */
52		− .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53		− xchal_sa_start \continue, \ofs
54		− .ifeq (XTHAL_SAS_OPT \| XTHAL_SAS_NOCC \| XTHAL_SAS_CALR) & ~\select
55		− xchal_sa_align \ptr, 0, 1024-4, 4, 4
56		− l32i \at1, \ptr, .Lxchal_ofs_ + 0
57		− wsr \at1, BR // boolean option
58		− .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59		− .endif
60		− .endm // xchal_ncp_load
61		−
62		−
63		−
64		−#define XCHAL_NCP_NUM_ATMPS 1
65		−
66		−
67		−
68		−/* Macro to save the state of TIE coprocessor FPU.
69		− * Save area ptr (clobbered): ptr (16 byte aligned)
70		− * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
71		− */
72		−#define xchal_cp_FPU_store xchal_cp0_store
73		−/* #define xchal_cp_FPU_store_a2 xchal_cp0_store a2 a3 a4 a5 a6 */
74		− .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
75		− xchal_sa_start \continue, \ofs
76		− .ifeq (XTHAL_SAS_TIE \| XTHAL_SAS_NOCC \| XTHAL_SAS_CALR) & ~\select
77		− xchal_sa_align \ptr, 0, 0, 1, 16
78		− rur232 \at1 // FCR
79		− s32i \at1, \ptr, 0
80		− rur233 \at1 // FSR
81		− s32i \at1, \ptr, 4
82		− SSI f0, \ptr, 8
83		− SSI f1, \ptr, 12
84		− SSI f2, \ptr, 16
85		− SSI f3, \ptr, 20
86		− SSI f4, \ptr, 24
87		− SSI f5, \ptr, 28
88		− SSI f6, \ptr, 32
89		− SSI f7, \ptr, 36
90		− SSI f8, \ptr, 40
91		− SSI f9, \ptr, 44
92		− SSI f10, \ptr, 48
93		− SSI f11, \ptr, 52
94		− SSI f12, \ptr, 56
95		− SSI f13, \ptr, 60
96		− SSI f14, \ptr, 64
97		− SSI f15, \ptr, 68
98		− .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
99		− .endif
100		− .endm // xchal_cp0_store
101		−
102		−/* Macro to restore the state of TIE coprocessor FPU.
103		− * Save area ptr (clobbered): ptr (16 byte aligned)
104		− * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
105		− */
106		−#define xchal_cp_FPU_load xchal_cp0_load
107		−/* #define xchal_cp_FPU_load_a2 xchal_cp0_load a2 a3 a4 a5 a6 */
108		− .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
109		− xchal_sa_start \continue, \ofs
110		− .ifeq (XTHAL_SAS_TIE \| XTHAL_SAS_NOCC \| XTHAL_SAS_CALR) & ~\select
111		− xchal_sa_align \ptr, 0, 0, 1, 16
112		− l32i \at1, \ptr, 0
113		− wur232 \at1 // FCR
114		− l32i \at1, \ptr, 4
115		− wur233 \at1 // FSR
116		− LSI f0, \ptr, 8
117		− LSI f1, \ptr, 12
118		− LSI f2, \ptr, 16
119		− LSI f3, \ptr, 20
120		− LSI f4, \ptr, 24
121		− LSI f5, \ptr, 28
122		− LSI f6, \ptr, 32
123		− LSI f7, \ptr, 36
124		− LSI f8, \ptr, 40
125		− LSI f9, \ptr, 44
126		− LSI f10, \ptr, 48
127		− LSI f11, \ptr, 52
128		− LSI f12, \ptr, 56
129		− LSI f13, \ptr, 60
130		− LSI f14, \ptr, 64
131		− LSI f15, \ptr, 68
132		− .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
133		− .endif
134		− .endm // xchal_cp0_load
135		−
136		−#define XCHAL_CP0_NUM_ATMPS 1
137		−
138		−/* Macro to save the state of TIE coprocessor XAD.
139		− * Save area ptr (clobbered): ptr (16 byte aligned)
140		− * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
141		− */
142		−#define xchal_cp_XAD_store xchal_cp6_store
143		−/* #define xchal_cp_XAD_store_a2 xchal_cp6_store a2 a3 a4 a5 a6 */
144		− .macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
145		− xchal_sa_start \continue, \ofs
146		− .ifeq (XTHAL_SAS_TIE \| XTHAL_SAS_NOCC \| XTHAL_SAS_CALR) & ~\select
147		− xchal_sa_align \ptr, 0, 0, 1, 16
148		− rur0 \at1 // LDCBHI
149		− s32i \at1, \ptr, 0
150		− rur1 \at1 // LDCBLO
151		− s32i \at1, \ptr, 4
152		− rur2 \at1 // STCBHI
153		− s32i \at1, \ptr, 8
154		− rur3 \at1 // STCBLO
155		− s32i \at1, \ptr, 12
156		− rur8 \at1 // LDBRBASE
157		− s32i \at1, \ptr, 16
158		− rur9 \at1 // LDBROFF
159		− s32i \at1, \ptr, 20
160		− rur10 \at1 // LDBRINC
161		− s32i \at1, \ptr, 24
162		− rur11 \at1 // STBRBASE
163		− s32i \at1, \ptr, 28
164		− rur12 \at1 // STBROFF
165		− s32i \at1, \ptr, 32
166		− rur13 \at1 // STBRINC
167		− s32i \at1, \ptr, 36
168		− rur24 \at1 // SCRATCH0
169		− s32i \at1, \ptr, 40
170		− rur25 \at1 // SCRATCH1
171		− s32i \at1, \ptr, 44
172		− rur26 \at1 // SCRATCH2
173		− s32i \at1, \ptr, 48
174		− rur27 \at1 // SCRATCH3
175		− s32i \at1, \ptr, 52
176		− WRAS128I wra0, \ptr, 64
177		− WRAS128I wra1, \ptr, 80
178		− WRAS128I wra2, \ptr, 96
179		− WRAS128I wra3, \ptr, 112
180		− WRAS128I wra4, \ptr, 128
181		− WRAS128I wra5, \ptr, 144
182		− WRAS128I wra6, \ptr, 160
183		− WRAS128I wra7, \ptr, 176
184		− WRAS128I wra8, \ptr, 192
185		− WRAS128I wra9, \ptr, 208
186		− WRAS128I wra10, \ptr, 224
187		− WRAS128I wra11, \ptr, 240
188		− WRAS128I wra12, \ptr, 256
189		− WRAS128I wra13, \ptr, 272
190		− WRAS128I wra14, \ptr, 288
191		− WRAS128I wra15, \ptr, 304
192		− WRBS128I wrb0, \ptr, 320
193		− WRBS128I wrb1, \ptr, 336
194		− WRBS128I wrb2, \ptr, 352
195		− WRBS128I wrb3, \ptr, 368
196		− WRBS128I wrb4, \ptr, 384
197		− WRBS128I wrb5, \ptr, 400
198		− WRBS128I wrb6, \ptr, 416
199		− WRBS128I wrb7, \ptr, 432
200		− WRBS128I wrb8, \ptr, 448
201		− WRBS128I wrb9, \ptr, 464
202		− WRBS128I wrb10, \ptr, 480
203		− WRBS128I wrb11, \ptr, 496
204		− WRBS128I wrb12, \ptr, 512
205		− WRBS128I wrb13, \ptr, 528
206		− WRBS128I wrb14, \ptr, 544
207		− WRBS128I wrb15, \ptr, 560
208		− .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
209		− .endif
210		− .endm // xchal_cp6_store
211		−
212		−/* Macro to restore the state of TIE coprocessor XAD.
213		− * Save area ptr (clobbered): ptr (16 byte aligned)
214		− * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
215		− */
216		−#define xchal_cp_XAD_load xchal_cp6_load
217		−/* #define xchal_cp_XAD_load_a2 xchal_cp6_load a2 a3 a4 a5 a6 */
218		− .macro xchal_cp6_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
219		− xchal_sa_start \continue, \ofs
220		− .ifeq (XTHAL_SAS_TIE \| XTHAL_SAS_NOCC \| XTHAL_SAS_CALR) & ~\select
221		− xchal_sa_align \ptr, 0, 0, 1, 16
222		− l32i \at1, \ptr, 0
223		− wur0 \at1 // LDCBHI
224		− l32i \at1, \ptr, 4
225		− wur1 \at1 // LDCBLO
226		− l32i \at1, \ptr, 8
227		− wur2 \at1 // STCBHI
228		− l32i \at1, \ptr, 12
229		− wur3 \at1 // STCBLO
230		− l32i \at1, \ptr, 16
231		− wur8 \at1 // LDBRBASE
232		− l32i \at1, \ptr, 20
233		− wur9 \at1 // LDBROFF
234		− l32i \at1, \ptr, 24
235		− wur10 \at1 // LDBRINC
236		− l32i \at1, \ptr, 28
237		− wur11 \at1 // STBRBASE
238		− l32i \at1, \ptr, 32
239		− wur12 \at1 // STBROFF
240		− l32i \at1, \ptr, 36
241		− wur13 \at1 // STBRINC
242		− l32i \at1, \ptr, 40
243		− wur24 \at1 // SCRATCH0
244		− l32i \at1, \ptr, 44
245		− wur25 \at1 // SCRATCH1
246		− l32i \at1, \ptr, 48
247		− wur26 \at1 // SCRATCH2
248		− l32i \at1, \ptr, 52
249		− wur27 \at1 // SCRATCH3
250		− WRBL128I wrb0, \ptr, 320
251		− WRBL128I wrb1, \ptr, 336
252		− WRBL128I wrb2, \ptr, 352
253		− WRBL128I wrb3, \ptr, 368
254		− WRBL128I wrb4, \ptr, 384
255		− WRBL128I wrb5, \ptr, 400
256		− WRBL128I wrb6, \ptr, 416
257		− WRBL128I wrb7, \ptr, 432
258		− WRBL128I wrb8, \ptr, 448
259		− WRBL128I wrb9, \ptr, 464
260		− WRBL128I wrb10, \ptr, 480
261		− WRBL128I wrb11, \ptr, 496
262		− WRBL128I wrb12, \ptr, 512
263		− WRBL128I wrb13, \ptr, 528
264		− WRBL128I wrb14, \ptr, 544
265		− WRBL128I wrb15, \ptr, 560
266		− WRAL128I wra0, \ptr, 64
267		− WRAL128I wra1, \ptr, 80
268		− WRAL128I wra2, \ptr, 96
269		− WRAL128I wra3, \ptr, 112
270		− WRAL128I wra4, \ptr, 128
271		− WRAL128I wra5, \ptr, 144
272		− WRAL128I wra6, \ptr, 160
273		− WRAL128I wra7, \ptr, 176
274		− WRAL128I wra8, \ptr, 192
275		− WRAL128I wra9, \ptr, 208
276		− WRAL128I wra10, \ptr, 224
277		− WRAL128I wra11, \ptr, 240
278		− WRAL128I wra12, \ptr, 256
279		− WRAL128I wra13, \ptr, 272
280		− WRAL128I wra14, \ptr, 288
281		− WRAL128I wra15, \ptr, 304
282		− .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
283		− .endif
284		− .endm // xchal_cp6_load
285		−
286		−#define XCHAL_CP6_NUM_ATMPS 1
287		−#define XCHAL_SA_NUM_ATMPS 1
288		−
289		− /* Empty macros for unconfigured coprocessors: */
290		− .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
291		− .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
292		− .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
293		− .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
294		− .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
295		− .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
296		− .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
297		− .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
298		− .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
299		− .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
300		− .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
301		− .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
302		−
303		−#endif /_XTENSA_CORE_TIE_ASM_H/
304		−

arch/xtensa/variants/s6000/include/variant/tie.h+0−191

@@ -1,191 +0,0 @@
1		−/*
2		− * This header file describes this specific Xtensa processor's TIE extensions
3		− * that extend basic Xtensa core functionality. It is customized to this
4		− * Xtensa processor configuration.
5		− *
6		− * This file is subject to the terms and conditions of the GNU General Public
7		− * License. See the file "COPYING" in the main directory of this archive
8		− * for more details.
9		− *
10		− * Copyright (C) 1999-2008 Tensilica Inc.
11		− */
12		−
13		−#ifndef _XTENSA_CORE_TIE_H
14		−#define _XTENSA_CORE_TIE_H
15		−
16		−#define XCHAL_CP_NUM 2 /* number of coprocessors */
17		−#define XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */
18		−#define XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */
19		−#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20		−
21		−/* Basic parameters of each coprocessor: */
22		−#define XCHAL_CP0_NAME "FPU"
23		−#define XCHAL_CP0_IDENT FPU
24		−#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
25		−#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
26		−#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
27		−#define XCHAL_CP6_NAME "XAD"
28		−#define XCHAL_CP6_IDENT XAD
29		−#define XCHAL_CP6_SA_SIZE 576 /* size of state save area */
30		−#define XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */
31		−#define XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */
32		−
33		−/* Filler info for unassigned coprocessors, to simplify arrays etc: */
34		−#define XCHAL_CP1_SA_SIZE 0
35		−#define XCHAL_CP1_SA_ALIGN 1
36		−#define XCHAL_CP2_SA_SIZE 0
37		−#define XCHAL_CP2_SA_ALIGN 1
38		−#define XCHAL_CP3_SA_SIZE 0
39		−#define XCHAL_CP3_SA_ALIGN 1
40		−#define XCHAL_CP4_SA_SIZE 0
41		−#define XCHAL_CP4_SA_ALIGN 1
42		−#define XCHAL_CP5_SA_SIZE 0
43		−#define XCHAL_CP5_SA_ALIGN 1
44		−#define XCHAL_CP7_SA_SIZE 0
45		−#define XCHAL_CP7_SA_ALIGN 1
46		−
47		−/* Save area for non-coprocessor optional and custom (TIE) state: */
48		−#define XCHAL_NCP_SA_SIZE 4
49		−#define XCHAL_NCP_SA_ALIGN 4
50		−
51		−/* Total save area for optional and custom state (NCP + CPn): */
52		−#define XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */
53		−#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
54		−
55		−/*
56		− * Detailed contents of save areas.
57		− * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
58		− * before expanding the XCHAL_xxx_SA_LIST() macros.
59		− *
60		− * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
61		− * dbnum,base,regnum,bitsz,gapsz,reset,x...)
62		− *
63		− * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
64		− * ccused = set if used by compiler without special options or code
65		− * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
66		− * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
67		− * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
68		− * name = lowercase reg name (no quotes)
69		− * galign = group byte alignment (power of 2) (galign >= align)
70		− * align = register byte alignment (power of 2)
71		− * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
72		− * (not including any pad bytes required to galign this or next reg)
73		− * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
74		− * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
75		− * regnum = reg index in regfile, or special/TIE-user reg number
76		− * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
77		− * gapsz = intervening bits, if bitsz bits not stored contiguously
78		− * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
79		− * reset = register reset value (or 0 if undefined at reset)
80		− * x = reserved for future use (0 until then)
81		− *
82		− * To filter out certain registers, e.g. to expand only the non-global
83		− * registers used by the compiler, you can do something like this:
84		− *
85		− * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
86		− * #define SELCC0(p...)
87		− * #define SELCC1(abikind,p...) SELAK##abikind(p)
88		− * #define SELAK0(p...) REG(p)
89		− * #define SELAK1(p...) REG(p)
90		− * #define SELAK2(p...)
91		− * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
92		− * ...what you want to expand...
93		− */
94		−
95		−#define XCHAL_NCP_SA_NUM 1
96		−#define XCHAL_NCP_SA_LIST(s) \
97		− XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)
98		−
99		−#define XCHAL_CP0_SA_NUM 18
100		−#define XCHAL_CP0_SA_LIST(s) \
101		− XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
102		− XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
103		− XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
104		− XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
105		− XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
106		− XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
107		− XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
108		− XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
109		− XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
110		− XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
111		− XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
112		− XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
113		− XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
114		− XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
115		− XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
116		− XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
117		− XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
118		− XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
119		−
120		−#define XCHAL_CP1_SA_NUM 0
121		−#define XCHAL_CP1_SA_LIST(s) /* empty */
122		−
123		−#define XCHAL_CP2_SA_NUM 0
124		−#define XCHAL_CP2_SA_LIST(s) /* empty */
125		−
126		−#define XCHAL_CP3_SA_NUM 0
127		−#define XCHAL_CP3_SA_LIST(s) /* empty */
128		−
129		−#define XCHAL_CP4_SA_NUM 0
130		−#define XCHAL_CP4_SA_LIST(s) /* empty */
131		−
132		−#define XCHAL_CP5_SA_NUM 0
133		−#define XCHAL_CP5_SA_LIST(s) /* empty */
134		−
135		−#define XCHAL_CP6_SA_NUM 46
136		−#define XCHAL_CP6_SA_LIST(s) \
137		− XCHAL_SA_REG(s,0,0,1,0, ldcbhi,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
138		− XCHAL_SA_REG(s,0,0,1,0, ldcblo, 4, 4, 4,0x0301, ur,1 , 32,0,0,0) \
139		− XCHAL_SA_REG(s,0,0,1,0, stcbhi, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
140		− XCHAL_SA_REG(s,0,0,1,0, stcblo, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
141		− XCHAL_SA_REG(s,0,0,1,0, ldbrbase, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
142		− XCHAL_SA_REG(s,0,0,1,0, ldbroff, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
143		− XCHAL_SA_REG(s,0,0,1,0, ldbrinc, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
144		− XCHAL_SA_REG(s,0,0,1,0, stbrbase, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
145		− XCHAL_SA_REG(s,0,0,1,0, stbroff, 4, 4, 4,0x030C, ur,12 , 32,0,0,0) \
146		− XCHAL_SA_REG(s,0,0,1,0, stbrinc, 4, 4, 4,0x030D, ur,13 , 32,0,0,0) \
147		− XCHAL_SA_REG(s,0,0,1,0, scratch0, 4, 4, 4,0x0318, ur,24 , 32,0,0,0) \
148		− XCHAL_SA_REG(s,0,0,1,0, scratch1, 4, 4, 4,0x0319, ur,25 , 32,0,0,0) \
149		− XCHAL_SA_REG(s,0,0,1,0, scratch2, 4, 4, 4,0x031A, ur,26 , 32,0,0,0) \
150		− XCHAL_SA_REG(s,0,0,1,0, scratch3, 4, 4, 4,0x031B, ur,27 , 32,0,0,0) \
151		− XCHAL_SA_REG(s,0,0,2,0, wra0,16,16,16,0x1010, wra,0 ,128,0,0,0) \
152		− XCHAL_SA_REG(s,0,0,2,0, wra1,16,16,16,0x1011, wra,1 ,128,0,0,0) \
153		− XCHAL_SA_REG(s,0,0,2,0, wra2,16,16,16,0x1012, wra,2 ,128,0,0,0) \
154		− XCHAL_SA_REG(s,0,0,2,0, wra3,16,16,16,0x1013, wra,3 ,128,0,0,0) \
155		− XCHAL_SA_REG(s,0,0,2,0, wra4,16,16,16,0x1014, wra,4 ,128,0,0,0) \
156		− XCHAL_SA_REG(s,0,0,2,0, wra5,16,16,16,0x1015, wra,5 ,128,0,0,0) \
157		− XCHAL_SA_REG(s,0,0,2,0, wra6,16,16,16,0x1016, wra,6 ,128,0,0,0) \
158		− XCHAL_SA_REG(s,0,0,2,0, wra7,16,16,16,0x1017, wra,7 ,128,0,0,0) \
159		− XCHAL_SA_REG(s,0,0,2,0, wra8,16,16,16,0x1018, wra,8 ,128,0,0,0) \
160		− XCHAL_SA_REG(s,0,0,2,0, wra9,16,16,16,0x1019, wra,9 ,128,0,0,0) \
161		− XCHAL_SA_REG(s,0,0,2,0, wra10,16,16,16,0x101A, wra,10 ,128,0,0,0) \
162		− XCHAL_SA_REG(s,0,0,2,0, wra11,16,16,16,0x101B, wra,11 ,128,0,0,0) \
163		− XCHAL_SA_REG(s,0,0,2,0, wra12,16,16,16,0x101C, wra,12 ,128,0,0,0) \
164		− XCHAL_SA_REG(s,0,0,2,0, wra13,16,16,16,0x101D, wra,13 ,128,0,0,0) \
165		− XCHAL_SA_REG(s,0,0,2,0, wra14,16,16,16,0x101E, wra,14 ,128,0,0,0) \
166		− XCHAL_SA_REG(s,0,0,2,0, wra15,16,16,16,0x101F, wra,15 ,128,0,0,0) \
167		− XCHAL_SA_REG(s,0,0,2,0, wrb0,16,16,16,0x1020, wrb,0 ,128,0,0,0) \
168		− XCHAL_SA_REG(s,0,0,2,0, wrb1,16,16,16,0x1021, wrb,1 ,128,0,0,0) \
169		− XCHAL_SA_REG(s,0,0,2,0, wrb2,16,16,16,0x1022, wrb,2 ,128,0,0,0) \
170		− XCHAL_SA_REG(s,0,0,2,0, wrb3,16,16,16,0x1023, wrb,3 ,128,0,0,0) \
171		− XCHAL_SA_REG(s,0,0,2,0, wrb4,16,16,16,0x1024, wrb,4 ,128,0,0,0) \
172		− XCHAL_SA_REG(s,0,0,2,0, wrb5,16,16,16,0x1025, wrb,5 ,128,0,0,0) \
173		− XCHAL_SA_REG(s,0,0,2,0, wrb6,16,16,16,0x1026, wrb,6 ,128,0,0,0) \
174		− XCHAL_SA_REG(s,0,0,2,0, wrb7,16,16,16,0x1027, wrb,7 ,128,0,0,0) \
175		− XCHAL_SA_REG(s,0,0,2,0, wrb8,16,16,16,0x1028, wrb,8 ,128,0,0,0) \
176		− XCHAL_SA_REG(s,0,0,2,0, wrb9,16,16,16,0x1029, wrb,9 ,128,0,0,0) \
177		− XCHAL_SA_REG(s,0,0,2,0, wrb10,16,16,16,0x102A, wrb,10 ,128,0,0,0) \
178		− XCHAL_SA_REG(s,0,0,2,0, wrb11,16,16,16,0x102B, wrb,11 ,128,0,0,0) \
179		− XCHAL_SA_REG(s,0,0,2,0, wrb12,16,16,16,0x102C, wrb,12 ,128,0,0,0) \
180		− XCHAL_SA_REG(s,0,0,2,0, wrb13,16,16,16,0x102D, wrb,13 ,128,0,0,0) \
181		− XCHAL_SA_REG(s,0,0,2,0, wrb14,16,16,16,0x102E, wrb,14 ,128,0,0,0) \
182		− XCHAL_SA_REG(s,0,0,2,0, wrb15,16,16,16,0x102F, wrb,15 ,128,0,0,0)
183		−
184		−#define XCHAL_CP7_SA_NUM 0
185		−#define XCHAL_CP7_SA_LIST(s) /* empty */
186		−
187		−/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
188		−#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
189		−
190		−#endif /_XTENSA_CORE_TIE_H/
191		−

arch/xtensa/variants/s6000/irq.c+0−74

@@ -1,74 +0,0 @@
1		−/*
2		− * s6000 irq crossbar
3		− *
4		− * Copyright (c) 2009 emlix GmbH
5		− * Authors: Johannes Weiner <hannes@cmpxchg.org>
6		− * Oskar Schirmer <oskar@scara.com>
7		− */
8		−#include <linux/io.h>
9		−#include <asm/irq.h>
10		−#include <variant/hardware.h>
11		−
12		−/* S6_REG_INTC */
13		−#define INTC_STATUS 0x000
14		−#define INTC_RAW 0x010
15		−#define INTC_STATUS_AG 0x100
16		−#define INTC_CFG(n) (0x200 + 4 * (n))
17		−
18		−/*
19		− * The s6000 has a crossbar that multiplexes interrupt output lines
20		− * from the peripherals to input lines on the xtensa core.
21		− *
22		− * We leave the mapping decisions to the platform as it depends on the
23		− * actually connected peripherals which distribution makes sense.
24		− */
25		−extern const signed char *platform_irq_mappings[NR_IRQS];
26		−
27		−static unsigned long scp_to_intc_enable[] = {
28		−#define TO_INTC_ENABLE(n) (((n) << 1) + 1)
29		− TO_INTC_ENABLE(0),
30		− TO_INTC_ENABLE(1),
31		− TO_INTC_ENABLE(2),
32		− TO_INTC_ENABLE(3),
33		− TO_INTC_ENABLE(4),
34		− TO_INTC_ENABLE(5),
35		− TO_INTC_ENABLE(6),
36		− TO_INTC_ENABLE(7),
37		− TO_INTC_ENABLE(8),
38		− TO_INTC_ENABLE(9),
39		− TO_INTC_ENABLE(10),
40		− TO_INTC_ENABLE(11),
41		− TO_INTC_ENABLE(12),
42		− -1,
43		− -1,
44		− TO_INTC_ENABLE(13),
45		− -1,
46		− TO_INTC_ENABLE(14),
47		− -1,
48		− TO_INTC_ENABLE(15),
49		−#undef TO_INTC_ENABLE
50		−};
51		−
52		−static void irq_set(unsigned int irq, int enable)
53		−{
54		− unsigned long en;
55		− const signed char *m = platform_irq_mappings[irq];
56		−
57		− if (!m)
58		− return;
59		− en = enable ? scp_to_intc_enable[irq] : 0;
60		− while (*m >= 0) {
61		− writel(en, S6_REG_INTC + INTC_CFG(*m));
62		− m++;
63		− }
64		−}
65		−
66		−void variant_irq_enable(unsigned int irq)
67		−{
68		− irq_set(irq, 1);
69		−}
70		−
71		−void variant_irq_disable(unsigned int irq)
72		−{
73		− irq_set(irq, 0);
74		−}