Merge tag 'drm-next-2021-09-10' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "Just an initial bunch of fixes for the merge window, amdgpu is most of them with a few ttm fixes and an fbdev avoid multiply overflow fix. core: - Make some dma-buf config options depend on DMA_SHARED_BUFFER - Handle multiplication overflow of fbdev xres/yres in the core ttm: - Fix ttm_bo_move_memcpy() when ttm_resource is subclassed - Fix ttm deadlock if target BO isn't idle - ttm build fix - ttm docs fix dma-buf: - config option fixes fbdev: - limit resolutions to avoid int overflow i915: - stddef change. amdgpu: - Misc cleanups, typo fixes - EEPROM fix - Add some new PCI IDs - Scatter/Gather display support for Yellow Carp - PCIe DPM fix for RKL platforms - RAS fix amdkfd: - SVM fix vc4: - static function fix mgag200: - fix uninit var panfrost: - lock_region fixes" * tag 'drm-next-2021-09-10' of git://anongit.freedesktop.org/drm/drm: (36 commits) drm/ttm: Fix a deadlock if the target BO is not idle during swap fbmem: don't allow too huge resolutions dma-buf: DMABUF_SYSFS_STATS should depend on DMA_SHARED_BUFFER dma-buf: DMABUF_DEBUG should depend on DMA_SHARED_BUFFER drm/i915: use linux/stddef.h due to "isystem: trim/fixup stdarg.h and other headers" dma-buf: DMABUF_MOVE_NOTIFY should depend on DMA_SHARED_BUFFER drm/amdkfd: drop process ref count when xnack disable drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode drm/amdgpu: fix fdinfo race with process exit drm/amdgpu: Fix a deadlock if previous GEM object allocation fails drm/amdgpu: stop scheduler when calling hw_fini (v2) drm/amdgpu: Clear RAS interrupt status on aldebaran drm/amd/display: Initialize lt_settings on instantiation drm/amd/display: cleanup idents after a revert drm/amd/display: Fix memory leak reported by coverity drm/ttm: Fix ttm_bo_move_memcpy() for subclassed struct ttm_resource drm/amdgpu/swsmu: fix spelling mistake "minimun" -> "minimum" drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform drm/amdgpu: show both cmd id and name when psp cmd failed drm/amd/display: setup system context for APUs ...

Linus Torvalds committed 5 years ago

Commit a668acb2 parents 4396a73 70982ee41 files · +233 −132Browse files

Unified · Split

41 files

Documentation/gpu/drm-mm.rst +1 −1
drivers/dma-buf/Kconfig +3 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +33 −17
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +17 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c +9 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +8 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +10 −13
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +2 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +4 −4
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +14 −17
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +3 −3
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +2 −0
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h +1 −0
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +25 −5
drivers/gpu/drm/amd/amdgpu/vi.c +1 −8
drivers/gpu/drm/amd/amdkfd/kfd_svm.c +2 −1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 −1
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +3 −3
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c +5 −1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c +2 −2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +1 −1
drivers/gpu/drm/amd/pm/amdgpu_pm.c +4 −4
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +24 −0
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +16 −1
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +2 −4
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +4 −4
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +1 −1
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +1 −1
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +2 −3
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +1 −1
drivers/gpu/drm/i915/gt/intel_gt_requests.h +1 −1
drivers/gpu/drm/mgag200/mgag200_pll.c +1 −0
drivers/gpu/drm/panfrost/panfrost_mmu.c +11 −20
drivers/gpu/drm/panfrost/panfrost_regs.h +2 −0
drivers/gpu/drm/ttm/ttm_bo.c +3 −3
drivers/gpu/drm/ttm/ttm_bo_util.c +3 −4
drivers/gpu/drm/ttm/ttm_tt.c +0 −1
drivers/gpu/drm/vc4/vc4_hdmi.c +1 −1
drivers/video/fbdev/core/fbmem.c +6 −0
include/drm/ttm/ttm_tt.h +2 −1

Documentation/gpu/drm-mm.rst+1−1

@@ -37,7 +37,7 @@ TTM initialization · 36 unmodified lines
37	37	This section is outdated.
38	38
39	39	Drivers wishing to support TTM must pass a filled :c:type:`ttm_bo_driver
40		−<ttm_bo_driver>` structure to ttm_bo_device_init, together with an
	40	+<ttm_bo_driver>` structure to ttm_device_init, together with an
41	41	initialized global reference to the memory manager. The ttm_bo_driver
42	42	structure contains several fields with function pointers for
43	43	initializing the TTM, allocating and freeing memory, waiting for command

drivers/dma-buf/Kconfig+3−1

@@ -42,6 +42,7 @@ config UDMABUF · 41 unmodified lines
42	42	config DMABUF_MOVE_NOTIFY
43	43	bool "Move notify between drivers (EXPERIMENTAL)"
44	44	default n
	45	+ depends on DMA_SHARED_BUFFER
45	46	help
46	47	Don't pin buffers if the dynamic DMA-buf interface is available on
47	48	both the exporter as well as the importer. This fixes a security
@@ -52,6 +53,7 @@ config DMABUF_MOVE_NOTIFY · 4 unmodified lines
52	53
53	54	config DMABUF_DEBUG
54	55	bool "DMA-BUF debug checks"
	56	+ depends on DMA_SHARED_BUFFER
55	57	default y if DMA_API_DEBUG
56	58	help
57	59	This option enables additional checks for DMA-BUF importers and
@@ -74,7 +76,7 @@ menuconfig DMABUF_HEAPS · 16 unmodified lines
74	76
75	77	menuconfig DMABUF_SYSFS_STATS
76	78	bool "DMA-BUF sysfs statistics"
77		− select DMA_SHARED_BUFFER
	79	+ depends on DMA_SHARED_BUFFER
78	80	help
79	81	Choose this option to enable DMA-BUF sysfs statistics
80	82	in location /sys/kernel/dmabuf/buffers.

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c+33−17

@@ -468,14 +468,18 @@ bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *ade · 467 unmodified lines
468	468	return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
469	469	}
470	470
471		−/*
472		− * Helper function to query RAS EEPROM address
473		− *
474		− * @adev: amdgpu_device pointer
	471	+/**
	472	+ * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
	473	+ * adev: amdgpu_device pointer
	474	+ * i2c_address: pointer to u8; if not NULL, will contain
	475	+ * the RAS EEPROM address if the function returns true
475	476	*
476		− * Return true if vbios supports ras rom address reporting
	477	+ * Return true if VBIOS supports RAS EEPROM address reporting,
	478	+ * else return false. If true and @i2c_address is not NULL,
	479	+ * will contain the RAS ROM address.
477	480	*/
478		−bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device adev, uint8_t i2c_address)
	481	+bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
	482	+ u8 *i2c_address)
479	483	{
480	484	struct amdgpu_mode_info *mode_info = &adev->mode_info;
481	485	int index;
@@ -483,27 +487,39 @@ bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device adev, uint8_t i2c_a · 1 unmodified line
483	487	union firmware_info *firmware_info;
484	488	u8 frev, crev;
485	489
486		− if (i2c_address == NULL)
487		− return false;
488		−
489		− *i2c_address = 0;
490		−
491	490	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
492		− firmwareinfo);
	491	+ firmwareinfo);
493	492
494	493	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
495		− index, &size, &frev, &crev, &data_offset)) {
	494	+ index, &size, &frev, &crev,
	495	+ &data_offset)) {
496	496	/* support firmware_info 3.4 + */
497	497	if ((frev == 3 && crev >=4) \|\| (frev > 3)) {
498	498	firmware_info = (union firmware_info *)
499	499	(mode_info->atom_context->bios + data_offset);
500		− *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
	500	+ /* The ras_rom_i2c_slave_addr should ideally
	501	+ * be a 19-bit EEPROM address, which would be
	502	+ * used as is by the driver; see top of
	503	+ * amdgpu_eeprom.c.
	504	+ *
	505	+ * When this is the case, 0 is of course a
	506	+ * valid RAS EEPROM address, in which case,
	507	+ * we'll drop the first "if (firm...)" and only
	508	+ * leave the check for the pointer.
	509	+ *
	510	+ * The reason this works right now is because
	511	+ * ras_rom_i2c_slave_addr contains the EEPROM
	512	+ * device type qualifier 1010b in the top 4
	513	+ * bits.
	514	+ */
	515	+ if (firmware_info->v34.ras_rom_i2c_slave_addr) {
	516	+ if (i2c_address)
	517	+ *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
	518	+ return true;
	519	+ }
501	520	}
502	521	}
503	522
504		− if (*i2c_address != 0)
505		− return true;
506		−
507	523	return false;
508	524	}
509	525

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+1−0

@@ -522,6 +522,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, · 521 unmodified lines
522	522	break;
523	523	case CHIP_RENOIR:
524	524	case CHIP_VANGOGH:
	525	+ case CHIP_YELLOW_CARP:
525	526	domain \|= AMDGPU_GEM_DOMAIN_GTT;
526	527	break;
527	528

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+17−0

@@ -1181,7 +1181,12 @@ static const struct pci_device_id pciidlist[] = { · 1180 unmodified lines
1181	1181	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1182	1182	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1183	1183	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
	1184	+ {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
	1185	+ {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
	1186	+ {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1184	1187	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
	1188	+ {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
	1189	+ {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1185	1190	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1186	1191	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1187	1192	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
@@ -1197,6 +1202,11 @@ static const struct pci_device_id pciidlist[] = { · 9 unmodified lines
1197	1202	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1198	1203	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1199	1204	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
	1205	+ {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
	1206	+ {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
	1207	+ {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
	1208	+ {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
	1209	+ {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1200	1210	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1201	1211
1202	1212	/* DIMGREY_CAVEFISH */
@@ -1204,6 +1214,13 @@ static const struct pci_device_id pciidlist[] = { · 1 unmodified line
1204	1214	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1205	1215	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1206	1216	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1217	+ {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1218	+ {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1219	+ {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1220	+ {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1221	+ {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1222	+ {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
	1223	+ {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1207	1224	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1208	1225
1209	1226	/* Aldebaran */

drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c+9−2

@@ -59,6 +59,7 @@ void amdgpu_show_fdinfo(struct seq_file m, struct file f) · 58 unmodified lines
59	59	uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0;
60	60	struct drm_file *file = f->private_data;
61	61	struct amdgpu_device *adev = drm_to_adev(file->minor->dev);
	62	+ struct amdgpu_bo *root;
62	63	int ret;
63	64
64	65	ret = amdgpu_file_to_fpriv(f, &fpriv);
@@ -69,13 +70,19 @@ void amdgpu_show_fdinfo(struct seq_file m, struct file f) · 4 unmodified lines
69	70	dev = PCI_SLOT(adev->pdev->devfn);
70	71	fn = PCI_FUNC(adev->pdev->devfn);
71	72
72		− ret = amdgpu_bo_reserve(fpriv->vm.root.bo, false);
	73	+ root = amdgpu_bo_ref(fpriv->vm.root.bo);
	74	+ if (!root)
	75	+ return;
	76	+
	77	+ ret = amdgpu_bo_reserve(root, false);
73	78	if (ret) {
74	79	DRM_ERROR("Fail to reserve bo\n");
75	80	return;
76	81	}
77	82	amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem);
78		− amdgpu_bo_unreserve(fpriv->vm.root.bo);
	83	+ amdgpu_bo_unreserve(root);
	84	+ amdgpu_bo_unref(&root);
	85	+
79	86	seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus,
80	87	dev, fn, fpriv->vm.pasid);
81	88	seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL);

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+8−0

@@ -552,6 +552,9 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) · 551 unmodified lines
552	552	if (!ring \|\| !ring->fence_drv.initialized)
553	553	continue;
554	554
	555	+ if (!ring->no_scheduler)
	556	+ drm_sched_stop(&ring->sched, NULL);
	557	+
555	558	/* You can't wait for HW to signal if it's gone */
556	559	if (!drm_dev_is_unplugged(&adev->ddev))
557	560	r = amdgpu_fence_wait_empty(ring);
@@ -611,6 +614,11 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev) · 53 unmodified lines
611	614	if (!ring \|\| !ring->fence_drv.initialized)
612	615	continue;
613	616
	617	+ if (!ring->no_scheduler) {
	618	+ drm_sched_resubmit_jobs(&ring->sched);
	619	+ drm_sched_start(&ring->sched, true);
	620	+ }
	621	+
614	622	/* enable the interrupt */
615	623	if (ring->fence_drv.irq_src)
616	624	amdgpu_irq_get(adev, ring->fence_drv.irq_src,

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+10−13

@@ -341,21 +341,18 @@ retry: · 340 unmodified lines
341	341	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
342	342	initial_domain,
343	343	flags, ttm_bo_type_device, resv, &gobj);
344		− if (r) {
345		− if (r != -ERESTARTSYS) {
346		− if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
347		− flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
348		− goto retry;
349		− }
	344	+ if (r && r != -ERESTARTSYS) {
	345	+ if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
	346	+ flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
	347	+ goto retry;
	348	+ }
350	349
351		− if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
352		− initial_domain \|= AMDGPU_GEM_DOMAIN_GTT;
353		− goto retry;
354		− }
355		− DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
356		− size, initial_domain, args->in.alignment, r);
	350	+ if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
	351	+ initial_domain \|= AMDGPU_GEM_DOMAIN_GTT;
	352	+ goto retry;
357	353	}
358		− return r;
	354	+ DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
	355	+ size, initial_domain, args->in.alignment, r);
359	356	}
360	357
361	358	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {

drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c+2−2

@@ -118,7 +118,7 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *res) · 117 unmodified lines
118	118	* @man: TTM memory type manager
119	119	* @tbo: TTM BO we need this range for
120	120	* @place: placement flags and restrictions
121		− * @mem: the resulting mem object
	121	+ * @res: the resulting mem object
122	122	*
123	123	* Dummy, allocate the node but no space for it yet.
124	124	*/
@@ -182,7 +182,7 @@ err_out: · 57 unmodified lines
182	182	* amdgpu_gtt_mgr_del - free ranges
183	183	*
184	184	* @man: TTM memory type manager
185		− * @mem: TTM memory object
	185	+ * @res: TTM memory object
186	186	*
187	187	* Free the allocated GTT again.
188	188	*/

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+4−4

@@ -469,10 +469,10 @@ psp_cmd_submit_buf(struct psp_context *psp, · 468 unmodified lines
469	469	*/
470	470	if (!skip_unsupport && (psp->cmd_buf_mem->resp.status \|\| !timeout) && !ras_intr) {
471	471	if (ucode)
472		− DRM_WARN("failed to load ucode (%s) ",
473		− amdgpu_ucode_name(ucode->ucode_id));
474		− DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n",
475		− psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
	472	+ DRM_WARN("failed to load ucode %s(0x%X) ",
	473	+ amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
	474	+ DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
	475	+ psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
476	476	psp->cmd_buf_mem->resp.status);
477	477	if (!timeout) {
478	478	ret = -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+14−17

@@ -114,27 +114,24 @@ static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, · 113 unmodified lines
114	114	static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
115	115	struct amdgpu_ras_eeprom_control *control)
116	116	{
117		− uint8_t ras_rom_i2c_slave_addr;
	117	+ u8 i2c_addr;
118	118
119	119	if (!control)
120	120	return false;
121	121
122		− control->i2c_address = 0;
123		−
124		− if (amdgpu_atomfirmware_ras_rom_addr(adev, &ras_rom_i2c_slave_addr))
125		− {
126		− switch (ras_rom_i2c_slave_addr) {
127		− case 0xA0:
128		− control->i2c_address = 0;
129		− return true;
130		− case 0xA8:
131		− control->i2c_address = 0x40000;
132		− return true;
133		− default:
134		− dev_warn(adev->dev, "RAS EEPROM I2C slave address %02x not supported",
135		− ras_rom_i2c_slave_addr);
136		− return false;
137		− }
	122	+ if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
	123	+ /* The address given by VBIOS is an 8-bit, wire-format
	124	+ * address, i.e. the most significant byte.
	125	+ *
	126	+ * Normalize it to a 19-bit EEPROM address. Remove the
	127	+ * device type identifier and make it a 7-bit address;
	128	+ * then make it a 19-bit EEPROM address. See top of
	129	+ * amdgpu_eeprom.c.
	130	+ */
	131	+ i2c_addr = (i2c_addr & 0x0F) >> 1;
	132	+ control->i2c_address = ((u32) i2c_addr) << 16;
	133	+
	134	+ return true;
138	135	}
139	136
140	137	switch (adev->asic_type) {

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+3−3

@@ -361,7 +361,7 @@ static void amdgpu_vram_mgr_virt_start(struct ttm_resource *mem, · 360 unmodified lines
361	361	* @man: TTM memory type manager
362	362	* @tbo: TTM BO we need this range for
363	363	* @place: placement flags and restrictions
364		− * @mem: the resulting mem object
	364	+ * @res: the resulting mem object
365	365	*
366	366	* Allocate VRAM for the given BO.
367	367	*/
@@ -487,7 +487,7 @@ error_sub: · 119 unmodified lines
487	487	* amdgpu_vram_mgr_del - free ranges
488	488	*
489	489	* @man: TTM memory type manager
490		− * @mem: TTM memory object
	490	+ * @res: TTM memory object
491	491	*
492	492	* Free the allocated VRAM again.
493	493	*/
@@ -522,7 +522,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, · 28 unmodified lines
522	522	* amdgpu_vram_mgr_alloc_sgt - allocate and fill a sg table
523	523	*
524	524	* @adev: amdgpu device pointer
525		− * @mem: TTM memory object
	525	+ * @res: TTM memory object
526	526	* @offset: byte offset from the base of VRAM BO
527	527	* @length: number of bytes to export in sg_table
528	528	* @dev: the other device

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c+2−0

@@ -258,6 +258,8 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) · 257 unmodified lines
258	258	amdgpu_virt_fini_data_exchange(adev);
259	259	atomic_set(&adev->in_gpu_reset, 1);
260	260
	261	+ xgpu_ai_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);
	262	+
261	263	do {
262	264	if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
263	265	goto flr_done;

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h+1−0

@@ -37,6 +37,7 @@ enum idh_request { · 36 unmodified lines
37	37	IDH_REQ_GPU_RESET_ACCESS,
38	38
39	39	IDH_LOG_VF_ERROR = 200,
	40	+ IDH_READY_TO_RESET = 201,
40	41	};
41	42
42	43	enum idh_event {

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c+25−5

@@ -85,11 +85,14 @@ · 84 unmodified lines
85	85	#define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015
86	86	#define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2
87	87
88		−#define mmBIF_DOORBELL_INT_CNTL_ALDE 0x3878
	88	+#define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe
89	89	#define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2
90	90	#define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
91	91	#define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
92	92
	93	+#define mmBIF_INTR_CNTL_ALDE 0x0101
	94	+#define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2
	95	+
93	96	static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
94	97	void *ras_error_status);
95	98
@@ -440,14 +443,23 @@ static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, · 344 unmodified lines
440	443	*/
441	444	uint32_t bif_intr_cntl;
442	445
443		− bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
	446	+ if (adev->asic_type == CHIP_ALDEBARAN)
	447	+ bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
	448	+ else
	449	+ bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
	450	+
444	451	if (state == AMDGPU_IRQ_STATE_ENABLE) {
445	452	/* set interrupt vector select bit to 0 to select
446	453	* vetcor 1 for bare metal case */
447	454	bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
448	455	BIF_INTR_CNTL,
449	456	RAS_INTR_VEC_SEL, 0);
450		− WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
	457	+
	458	+ if (adev->asic_type == CHIP_ALDEBARAN)
	459	+ WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
	460	+ else
	461	+ WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
	462	+
451	463	}
452	464
453	465	return 0;
@@ -476,14 +488,22 @@ static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *ade · 22 unmodified lines
476	488	*/
477	489	uint32_t bif_intr_cntl;
478	490
479		− bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
	491	+ if (adev->asic_type == CHIP_ALDEBARAN)
	492	+ bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
	493	+ else
	494	+ bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
	495	+
480	496	if (state == AMDGPU_IRQ_STATE_ENABLE) {
481	497	/* set interrupt vector select bit to 0 to select
482	498	* vetcor 1 for bare metal case */
483	499	bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
484	500	BIF_INTR_CNTL,
485	501	RAS_INTR_VEC_SEL, 0);
486		− WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
	502	+
	503	+ if (adev->asic_type == CHIP_ALDEBARAN)
	504	+ WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
	505	+ else
	506	+ WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
487	507	}
488	508
489	509	return 0;

drivers/gpu/drm/amd/amdgpu/vi.c+1−8

@@ -904,14 +904,7 @@ static bool vi_asic_supports_baco(struct amdgpu_device *adev) · 903 unmodified lines
904	904	case CHIP_POLARIS11:
905	905	case CHIP_POLARIS12:
906	906	case CHIP_TOPAZ:
907		− /* Disable BACO support for the specific polaris12 SKU temporarily */
908		− if ((adev->pdev->device == 0x699F) &&
909		− (adev->pdev->revision == 0xC7) &&
910		− (adev->pdev->subsystem_vendor == 0x1028) &&
911		− (adev->pdev->subsystem_device == 0x0039))
912		− return false;
913		− else
914		− return amdgpu_dpm_is_baco_supported(adev);
	907	+ return amdgpu_dpm_is_baco_supported(adev);
915	908	default:
916	909	return false;
917	910	}

drivers/gpu/drm/amd/amdkfd/kfd_svm.c+2−1

@@ -2484,7 +2484,8 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, · 2483 unmodified lines
2484	2484	}
2485	2485	if (!p->xnack_enabled) {
2486	2486	pr_debug("XNACK not enabled for pasid 0x%x\n", pasid);
2487		− return -EFAULT;
	2487	+ r = -EFAULT;
	2488	+ goto out;
2488	2489	}
2489	2490	svms = &p->svms;
2490	2491

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+1−1

@@ -1200,7 +1200,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 1199 unmodified lines
1200	1200	dc_hardware_init(adev->dm.dc);
1201	1201
1202	1202	#if defined(CONFIG_DRM_AMD_DC_DCN)
1203		− if (adev->apu_flags) {
	1203	+ if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1204	1204	struct dc_phy_addr_space_config pa_config;
1205	1205
1206	1206	mmhub_read_system_context(adev, &pa_config);

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+3−3

@@ -1561,7 +1561,7 @@ bool dc_link_dp_perform_link_training_skip_aux( · 1560 unmodified lines
1561	1561	struct dc_link *link,
1562	1562	const struct dc_link_settings *link_setting)
1563	1563	{
1564		− struct link_training_settings lt_settings;
	1564	+ struct link_training_settings lt_settings = {0};
1565	1565
1566	1566	dp_decide_training_settings(
1567	1567	link,
@@ -1707,7 +1707,7 @@ enum link_training_result dc_link_dp_perform_link_training( · 139 unmodified lines
1707	1707	bool skip_video_pattern)
1708	1708	{
1709	1709	enum link_training_result status = LINK_TRAINING_SUCCESS;
1710		− struct link_training_settings lt_settings;
	1710	+ struct link_training_settings lt_settings = {0};
1711	1711	enum dp_link_encoding encoding =
1712	1712	dp_get_link_encoding_format(link_settings);
1713	1713
@@ -1923,7 +1923,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt( · 209 unmodified lines
1923	1923	struct dc_link_settings *link_settings,
1924	1924	struct dc_link_training_overrides *lt_overrides)
1925	1925	{
1926		− struct link_training_settings lt_settings;
	1926	+ struct link_training_settings lt_settings = {0};
1927	1927	enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1928	1928	enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1929	1929	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c+5−1

@@ -510,8 +510,12 @@ static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id · 509 unmodified lines
510	510	vpg = dcn303_vpg_create(ctx, vpg_inst);
511	511	afmt = dcn303_afmt_create(ctx, afmt_inst);
512	512
513		− if (!enc1 \|\| !vpg \|\| !afmt)
	513	+ if (!enc1 \|\| !vpg \|\| !afmt) {
	514	+ kfree(enc1);
	515	+ kfree(vpg);
	516	+ kfree(afmt);
514	517	return NULL;
	518	+ }
515	519
516	520	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
517	521	&se_shift, &se_mask);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c+2−2

@@ -109,7 +109,7 @@ bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl) · 108 unmodified lines
109	109	union dmub_rb_cmd cmd;
110	110
111	111	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
112		− return 0;
	112	+ return false;
113	113
114	114	return cmd.panel_cntl.data.is_backlight_on;
115	115	}
@@ -119,7 +119,7 @@ bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl) · 3 unmodified lines
119	119	union dmub_rb_cmd cmd;
120	120
121	121	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
122		− return 0;
	122	+ return false;
123	123
124	124	return cmd.panel_cntl.data.is_powered_on;
125	125	}

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c+1−1

@@ -2641,7 +2641,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP · 2640 unmodified lines
2641	2641	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
2642	2642	if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
2643	2643	if (mode_lib->vba.DRAMClockChangeWatermark >
2644		− dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
	2644	+ dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
2645	2645	mode_lib->vba.MinTTUVBlank[k] += 25;
2646	2646	}
2647	2647	}

drivers/gpu/drm/amd/pm/amdgpu_pm.c+4−4

@@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ · 2004 unmodified lines
2005	2005	static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2006	2006	AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
2007	2007	AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
2008		− AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC),
2009		− AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC),
2010		− AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC),
2011		− AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC),
	2008	+ AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
	2009	+ AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
	2010	+ AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
	2011	+ AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
2012	2012	AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
2013	2013	AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),
2014	2014	AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC\|ATTR_FLAG_ONEVF),

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h+24−0

@@ -1335,6 +1335,30 @@ enum smu_cmn2asic_mapping_type { · 1334 unmodified lines
1335	1335	#define WORKLOAD_MAP(profile, workload) \
1336	1336	[profile] = {1, (workload)}
1337	1337
	1338	+/**
	1339	+ * smu_memcpy_trailing - Copy the end of one structure into the middle of another
	1340	+ *
	1341	+ * @dst: Pointer to destination struct
	1342	+ * @first_dst_member: The member name in @dst where the overwrite begins
	1343	+ * @last_dst_member: The member name in @dst where the overwrite ends after
	1344	+ * @src: Pointer to the source struct
	1345	+ * @first_src_member: The member name in @src where the copy begins
	1346	+ *
	1347	+ */
	1348	+#define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \
	1349	+ src, first_src_member) \
	1350	+({ \
	1351	+ size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \
	1352	+ size_t __src_size = sizeof(*(src)) - __src_offset; \
	1353	+ size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \
	1354	+ size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
	1355	+ __dst_offset; \
	1356	+ BUILD_BUG_ON(__src_size != __dst_size); \
	1357	+ __builtin_memcpy((u8 *)(dst) + __dst_offset, \
	1358	+ (u8 *)(src) + __src_offset, \
	1359	+ __dst_size); \
	1360	+})
	1361	+
1338	1362	#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1339	1363	int smu_get_power_limit(void *handle,
1340	1364	uint32_t *limit,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c+16−1

@@ -27,6 +27,9 @@ · 26 unmodified lines
27	27	#include <linux/pci.h>
28	28	#include <linux/slab.h>
29	29	#include <asm/div64.h>
	30	+#if IS_ENABLED(CONFIG_X86_64)
	31	+#include <asm/intel-family.h>
	32	+#endif
30	33	#include <drm/amdgpu_drm.h>
31	34	#include "ppatomctrl.h"
32	35	#include "atombios.h"
@@ -1733,6 +1736,17 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) · 1700 unmodified lines
1733	1736	return result;
1734	1737	}
1735	1738
	1739	+static bool intel_core_rkl_chk(void)
	1740	+{
	1741	+#if IS_ENABLED(CONFIG_X86_64)
	1742	+ struct cpuinfo_x86 *c = &cpu_data(0);
	1743	+
	1744	+ return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE);
	1745	+#else
	1746	+ return false;
	1747	+#endif
	1748	+}
	1749	+
1736	1750	static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1737	1751	{
1738	1752	struct smu7_hwmgr data = (struct smu7_hwmgr )(hwmgr->backend);
@@ -1758,7 +1772,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) · 19 unmodified lines
1758	1772
1759	1773	data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1760	1774	data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1761		− data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
	1775	+ data->pcie_dpm_key_disabled =
	1776	+ intel_core_rkl_chk() \|\| !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
1762	1777	/* need to set voltage control types before EVV patching */
1763	1778	data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1764	1779	data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c+2−4

@@ -483,10 +483,8 @@ static int arcturus_append_powerplay_table(struct smu_context *smu) · 482 unmodified lines
483	483
484	484	if ((smc_dpm_table->table_header.format_revision == 4) &&
485	485	(smc_dpm_table->table_header.content_revision == 6))
486		− memcpy(&smc_pptable->MaxVoltageStepGfx,
487		− &smc_dpm_table->maxvoltagestepgfx,
488		− sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
489		−
	486	+ smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
	487	+ smc_dpm_table, maxvoltagestepgfx);
490	488	return 0;
491	489	}
492	490

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c+4−4

@@ -431,16 +431,16 @@ static int navi10_append_powerplay_table(struct smu_context *smu) · 430 unmodified lines
431	431
432	432	switch (smc_dpm_table->table_header.content_revision) {
433	433	case 5: /* nv10 and nv14 */
434		− memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
435		− sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
	434	+ smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
	435	+ smc_dpm_table, I2cControllers);
436	436	break;
437	437	case 7: /* nv12 */
438	438	ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
439	439	(uint8_t **)&smc_dpm_table_v4_7);
440	440	if (ret)
441	441	return ret;
442		− memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
443		− sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
	442	+ smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
	443	+ smc_dpm_table_v4_7, I2cControllers);
444	444	break;
445	445	default:
446	446	dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c+1−1

@@ -1869,7 +1869,7 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB · 1868 unmodified lines
1869	1869	} else {
1870	1870	if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1871	1871	dev_err(smu->adev->dev,
1872		− "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
	1872	+ "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1873	1873	smu->gfx_actual_hard_min_freq,
1874	1874	smu->gfx_actual_soft_max_freq);
1875	1875	return -EINVAL;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c+1−1

@@ -426,7 +426,7 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu, · 425 unmodified lines
426	426	} else {
427	427	if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
428	428	dev_err(smu->adev->dev,
429		− "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
	429	+ "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
430	430	smu->gfx_actual_hard_min_freq,
431	431	smu->gfx_actual_soft_max_freq);
432	432	return -EINVAL;

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+2−3

@@ -409,9 +409,8 @@ static int aldebaran_append_powerplay_table(struct smu_context *smu) · 408 unmodified lines
409	409
410	410	if ((smc_dpm_table->table_header.format_revision == 4) &&
411	411	(smc_dpm_table->table_header.content_revision == 10))
412		− memcpy(&smc_pptable->GfxMaxCurrent,
413		− &smc_dpm_table->GfxMaxCurrent,
414		− sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent));
	412	+ smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
	413	+ smc_dpm_table, GfxMaxCurrent);
415	414	return 0;
416	415	}
417	416

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c+1−1

@@ -731,7 +731,7 @@ static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM · 730 unmodified lines
731	731	} else {
732	732	if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
733	733	dev_err(smu->adev->dev,
734		− "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
	734	+ "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
735	735	smu->gfx_actual_hard_min_freq,
736	736	smu->gfx_actual_soft_max_freq);
737	737	return -EINVAL;

drivers/gpu/drm/i915/gt/intel_gt_requests.h+1−1

@@ -6,7 +6,7 @@ · 5 unmodified lines
6	6	#ifndef INTEL_GT_REQUESTS_H
7	7	#define INTEL_GT_REQUESTS_H
8	8
9		−#include <stddef.h>
	9	+#include <linux/stddef.h>
10	10
11	11	struct intel_engine_cs;
12	12	struct intel_gt;

drivers/gpu/drm/mgag200/mgag200_pll.c+1−0

@@ -124,6 +124,7 @@ static int mgag200_pixpll_compute_g200se_00(struct mgag200_pll *pixpll, long clo · 123 unmodified lines
124	124	unsigned int computed;
125	125
126	126	m = n = p = s = 0;
	127	+ delta = 0xffffffff;
127	128	permitteddelta = clock * 5 / 1000;
128	129
129	130	for (testp = 8; testp > 0; testp /= 2) {

drivers/gpu/drm/panfrost/panfrost_mmu.c+11−20

@@ -58,25 +58,16 @@ static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd) · 57 unmodified lines
58	58	}
59	59
60	60	static void lock_region(struct panfrost_device *pfdev, u32 as_nr,
61		− u64 iova, size_t size)
	61	+ u64 iova, u64 size)
62	62	{
63	63	u8 region_width;
64	64	u64 region = iova & PAGE_MASK;
65		− /*
66		− * fls returns:
67		− * 1 .. 32
68		− *
69		− * 10 + fls(num_pages)
70		− * results in the range (11 .. 42)
71		− */
72		−
73		− size = round_up(size, PAGE_SIZE);
74	65
75		− region_width = 10 + fls(size >> PAGE_SHIFT);
76		− if ((size >> PAGE_SHIFT) != (1ul << (region_width - 11))) {
77		− /* not pow2, so must go up to the next pow2 */
78		− region_width += 1;
79		− }
	66	+ /* The size is encoded as ceil(log2) minus(1), which may be calculated
	67	+ * with fls. The size must be clamped to hardware bounds.
	68	+ */
	69	+ size = max_t(u64, size, AS_LOCK_REGION_MIN_SIZE);
	70	+ region_width = fls64(size - 1) - 1;
80	71	region \|= region_width;
81	72
82	73	/* Lock the region that needs to be updated */
@@ -87,7 +78,7 @@ static void lock_region(struct panfrost_device *pfdev, u32 as_nr, · 4 unmodified lines
87	78
88	79
89	80	static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr,
90		− u64 iova, size_t size, u32 op)
	81	+ u64 iova, u64 size, u32 op)
91	82	{
92	83	if (as_nr < 0)
93	84	return 0;
@@ -104,7 +95,7 @@ static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr, · 10 unmodified lines
104	95
105	96	static int mmu_hw_do_operation(struct panfrost_device *pfdev,
106	97	struct panfrost_mmu *mmu,
107		− u64 iova, size_t size, u32 op)
	98	+ u64 iova, u64 size, u32 op)
108	99	{
109	100	int ret;
110	101
@@ -121,7 +112,7 @@ static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_m · 10 unmodified lines
121	112	u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
122	113	u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
123	114
124		− mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0UL, AS_COMMAND_FLUSH_MEM);
	115	+ mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
125	116
126	117	mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
127	118	mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);
@@ -137,7 +128,7 @@ static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_m · 9 unmodified lines
137	128
138	129	static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
139	130	{
140		− mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0UL, AS_COMMAND_FLUSH_MEM);
	131	+ mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
141	132
142	133	mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
143	134	mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
@@ -251,7 +242,7 @@ static size_t get_pgsize(u64 addr, size_t size) · 107 unmodified lines
251	242
252	243	static void panfrost_mmu_flush_range(struct panfrost_device *pfdev,
253	244	struct panfrost_mmu *mmu,
254		− u64 iova, size_t size)
	245	+ u64 iova, u64 size)
255	246	{
256	247	if (mmu->as < 0)
257	248	return;

drivers/gpu/drm/panfrost/panfrost_regs.h+2−0

@@ -316,6 +316,8 @@ · 315 unmodified lines
316	316	#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8)
317	317	#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8)
318	318
	319	+#define AS_LOCK_REGION_MIN_SIZE (1ULL << 15)
	320	+
319	321	#define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
320	322	#define gpu_read(dev, reg) readl(dev->iomem + reg)
321	323

drivers/gpu/drm/ttm/ttm_bo.c+3−3

@@ -1160,9 +1160,9 @@ int ttm_bo_swapout(struct ttm_buffer_object bo, struct ttm_operation_ctx ctx, · 1159 unmodified lines
1160	1160	}
1161	1161
1162	1162	if (bo->deleted) {
1163		− ttm_bo_cleanup_refs(bo, false, false, locked);
	1163	+ ret = ttm_bo_cleanup_refs(bo, false, false, locked);
1164	1164	ttm_bo_put(bo);
1165		− return 0;
	1165	+ return ret == -EBUSY ? -ENOSPC : ret;
1166	1166	}
1167	1167
1168	1168	ttm_bo_del_from_lru(bo);
@@ -1216,7 +1216,7 @@ out: · 47 unmodified lines
1216	1216	if (locked)
1217	1217	dma_resv_unlock(bo->base.resv);
1218	1218	ttm_bo_put(bo);
1219		− return ret;
	1219	+ return ret == -EBUSY ? -ENOSPC : ret;
1220	1220	}
1221	1221
1222	1222	void ttm_bo_tt_destroy(struct ttm_buffer_object *bo)

drivers/gpu/drm/ttm/ttm_bo_util.c+3−4

@@ -143,7 +143,6 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, · 142 unmodified lines
143	143	struct ttm_resource *src_mem = bo->resource;
144	144	struct ttm_resource_manager *src_man =
145	145	ttm_manager_type(bdev, src_mem->mem_type);
146		− struct ttm_resource src_copy = *src_mem;
147	146	union {
148	147	struct ttm_kmap_iter_tt tt;
149	148	struct ttm_kmap_iter_linear_io io;
@@ -173,11 +172,11 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, · 23 unmodified lines
173	172	}
174	173
175	174	ttm_move_memcpy(bo, dst_mem->num_pages, dst_iter, src_iter);
176		− src_copy = *src_mem;
177		− ttm_bo_move_sync_cleanup(bo, dst_mem);
178	175
179	176	if (!src_iter->ops->maps_tt)
180		− ttm_kmap_iter_linear_io_fini(&_src_iter.io, bdev, &src_copy);
	177	+ ttm_kmap_iter_linear_io_fini(&_src_iter.io, bdev, src_mem);
	178	+ ttm_bo_move_sync_cleanup(bo, dst_mem);
	179	+
181	180	out_src_iter:
182	181	if (!dst_iter->ops->maps_tt)
183	182	ttm_kmap_iter_linear_io_fini(&_dst_iter.io, bdev, dst_mem);

drivers/gpu/drm/ttm/ttm_tt.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	32	#define pr_fmt(fmt) "[TTM] " fmt
33	33
34	34	#include <linux/sched.h>
35		−#include <linux/pagemap.h>
36	35	#include <linux/shmem_fs.h>
37	36	#include <linux/file.h>
38	37	#include <drm/drm_cache.h>

drivers/gpu/drm/vc4/vc4_hdmi.c+1−1

@@ -1462,7 +1462,7 @@ static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { · 1461 unmodified lines
1462	1462	.audio_startup = vc4_hdmi_audio_startup,
1463	1463	};
1464	1464
1465		−struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
	1465	+static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1466	1466	.ops = &vc4_hdmi_codec_ops,
1467	1467	.max_i2s_channels = 8,
1468	1468	.i2s = 1,

drivers/video/fbdev/core/fbmem.c+6−0

@@ -962,6 +962,7 @@ fb_set_var(struct fb_info info, struct fb_var_screeninfo var) · 961 unmodified lines
962	962	struct fb_var_screeninfo old_var;
963	963	struct fb_videomode mode;
964	964	struct fb_event event;
	965	+ u32 unused;
965	966
966	967	if (var->activate & FB_ACTIVATE_INV_MODE) {
967	968	struct fb_videomode mode1, mode2;
@@ -1008,6 +1009,11 @@ fb_set_var(struct fb_info info, struct fb_var_screeninfo var) · 40 unmodified lines
1008	1009	if (var->xres < 8 \|\| var->yres < 8)
1009	1010	return -EINVAL;
1010	1011
	1012	+ /* Too huge resolution causes multiplication overflow. */
	1013	+ if (check_mul_overflow(var->xres, var->yres, &unused) \|\|
	1014	+ check_mul_overflow(var->xres_virtual, var->yres_virtual, &unused))
	1015	+ return -EINVAL;
	1016	+
1011	1017	ret = info->fbops->fb_check_var(var, info);
1012	1018
1013	1019	if (ret)

include/drm/ttm/ttm_tt.h+2−1

@@ -27,11 +27,12 @@ · 26 unmodified lines
27	27	#ifndef _TTM_TT_H_
28	28	#define _TTM_TT_H_
29	29
	30	+#include <linux/pagemap.h>
30	31	#include <linux/types.h>
31	32	#include <drm/ttm/ttm_caching.h>
32	33	#include <drm/ttm/ttm_kmap_iter.h>
33	34
34		−struct ttm_bo_device;
	35	+struct ttm_device;
35	36	struct ttm_tt;
36	37	struct ttm_resource;
37	38	struct ttm_buffer_object;