History

Merge tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "Lots of stuff in here, though it hasn't been too insane this merge apart from dealing with the security fun. uapi: - export different colorspace properties on DP vs HDMI - new fourcc for ARM 16x16 block format - syncobj: allow querying last submitted timeline value - DRM_FORMAT_BIG_ENDIAN defined as unsigned core: - allow using gem vma manager in ttm - connector/encoder/bridge doc fixes - allow more than 3 encoders for a connector - displayport mst suspend/resume reprobing support - vram lazy unmapping, uniform vram mm and gem vram - edid cleanups + AVI informframe bar info - displayport helpers - dpcd parser added dp_cec: - Allow a connector to be associated with a cec device ttm: - pipelining with no_gpu_wait fix - always keep BOs on the LRU sched: - allow free_job routine to sleep i915: - Block userptr from mappable GTT - i915 perf uapi versioning - OA stream dynamic reconfiguration - make context persistence optional - introduce DRM_I915_UNSTABLE Kconfig - add fake lmem testing under unstable - BT.2020 support for DP MSA - struct mutex elimination - Tigerlake display/PLL/power management improvements - Jasper Lake PCH support - refactor PMU for multiple GPUs - Icelake firmware update - Split out vga + switcheroo code amdgpu: - implement dma-buf import/export without helpers - vega20 RAS enablement - DC i2c over aux fixes - renoir GPU reset - DC HDCP support - BACO support for CI/VI asics - MSI-X support - Arcturus EEPROM support - Arcturus VCN encode support - VCN dynamic powergating on RV/RV2 amdkfd: - add navi12/14/renoir support to kfd radeon: - SI dpm fix ported from amdgpu - fix bad DMA on ppc platforms gma500: - memory leak fixes qxl: - convert to new gem mmap exynos: - build warning fix komeda: - add aclk sysfs attribute v3d: - userspace cleanup uapi change i810: - fix for underflow in dispatch ioctls ast: - refactor show_cursor mgag200: - refactor show_cursor arcgpu: - encoder finding improvements mediatek: - mipi_tx, dsi and partial crtc support for MT8183 SoC - rotation support meson: - add suspend/resume support omap: - misc refactors tegra: - DisplayPort support for Tegra 210, 186 and 194. - IOMMU-backed DMA API fixes panfrost: - fix lockdep issue - simplify devfreq integration rcar-du: - R8A774B1 SoC support - fixes for H2 ES2.0 sun4i: - vcc-dsi regulator support virtio-gpu: - vmexit vs spinlock fix - move to gem shmem helpers - handle large command buffers with cma" * tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm: (1855 commits) drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10 drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhub drm/amd/amdgpu/sriov skip RLCG s/r list for arcturus VF. drm/amd/amdgpu/sriov temporarily skip ras,dtm,hdcp for arcturus VF drm/amdgpu/gfx10: re-init clear state buffer after gpu reset merge fix for "ftrace: Rework event_create_dir()" drm/amdgpu: Update Arcturus golden registers drm/amdgpu/gfx10: fix out-of-bound mqd_backup array access drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhalt Revert "drm/amd/display: enable S/G for RAVEN chip" drm/amdgpu: disable gfxoff on original raven drm/amdgpu: remove experimental flag for Navi14 drm/amdgpu: disable gfxoff when using register read interface drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2) drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2 drm/radeon: fix bad DMA from INTERRUPT_CNTL2 drm/amd/display: Fix debugfs on MST connectors drm/amdgpu/nv: add asic func for fetching vbios from rom directly drm/amdgpu: put flush_delayed_work at first drm/amdgpu/vcn2.5: fix the enc loop with hw fini ...

Linus Torvalds committed 6 years ago

Commit a6ed68d2 parents 8c39f71 acc61b81122 files · +61274 −29902Browse files

Showing the changes to include/uapi (7 of 1122 files). Show all

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7 files
  1. include/uapi/drm/amdgpu_drm.h +2 −0
  2. include/uapi/drm/drm.h +2 −1
  3. include/uapi/drm/drm_fourcc.h +26 −2
  4. include/uapi/drm/exynos_drm.h +1 −1
  5. include/uapi/drm/i915_drm.h +125 −3
  6. include/uapi/drm/omap_drm.h +9 −9
  7. include/uapi/drm/v3d_drm.h +5 −3
include/uapi/drm/amdgpu_drm.h+2−0
@@ -500,6 +500,8 @@ struct drm_amdgpu_gem_op { · 499 unmodified lines
500#define AMDGPU_VM_MTYPE_CC (3 << 5)500#define AMDGPU_VM_MTYPE_CC (3 << 5)
501/* Use UC MTYPE instead of default MTYPE */501/* Use UC MTYPE instead of default MTYPE */
502#define AMDGPU_VM_MTYPE_UC (4 << 5)502#define AMDGPU_VM_MTYPE_UC (4 << 5)
503/* Use RW MTYPE instead of default MTYPE */
504#define AMDGPU_VM_MTYPE_RW (5 << 5)
503 505
504struct drm_amdgpu_gem_va {506struct drm_amdgpu_gem_va {
505 /** GEM object handle */507 /** GEM object handle */
include/uapi/drm/drm.h+2−1
@@ -778,11 +778,12 @@ struct drm_syncobj_array { · 777 unmodified lines
778 __u32 pad;778 __u32 pad;
779};779};
780 780
781#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */
781struct drm_syncobj_timeline_array {782struct drm_syncobj_timeline_array {
782 __u64 handles;783 __u64 handles;
783 __u64 points;784 __u64 points;
784 __u32 count_handles;785 __u32 count_handles;
785 __u32 pad;786 __u32 flags;
786};787};
787 788
788 789
include/uapi/drm/drm_fourcc.h+26−2
@@ -69,7 +69,7 @@ extern "C" { · 68 unmodified lines
69#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \69#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
70 ((__u32)(c) << 16) | ((__u32)(d) << 24))70 ((__u32)(c) << 16) | ((__u32)(d) << 24))
71 71
72#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */72#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
73 73
74/* Reserve 0 for the invalid format specifier */74/* Reserve 0 for the invalid format specifier */
75#define DRM_FORMAT_INVALID 075#define DRM_FORMAT_INVALID 0
@@ -648,7 +648,21 @@ extern "C" { · 572 unmodified lines
648 * Further information on the use of AFBC modifiers can be found in648 * Further information on the use of AFBC modifiers can be found in
649 * Documentation/gpu/afbc.rst649 * Documentation/gpu/afbc.rst
650 */650 */
651#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)651
652/*
653 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
654 * modifiers) denote the category for modifiers. Currently we have only two
655 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
656 * different categories.
657 */
658#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
659 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
660
661#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
662#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
663
664#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
665 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
652 666
653/*667/*
654 * AFBC superblock size668 * AFBC superblock size
@@ -742,6 +756,16 @@ extern "C" { · 87 unmodified lines
742 */756 */
743#define AFBC_FORMAT_MOD_BCH (1ULL << 11)757#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
744 758
759/*
760 * Arm 16x16 Block U-Interleaved modifier
761 *
762 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
763 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
764 * in the block are reordered.
765 */
766#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
767 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
768
745/*769/*
746 * Allwinner tiled modifier770 * Allwinner tiled modifier
747 *771 *
include/uapi/drm/exynos_drm.h+1−1
@@ -68,7 +68,7 @@ struct drm_exynos_gem_info { · 67 unmodified lines
68/**68/**
69 * A structure for user connection request of virtual display.69 * A structure for user connection request of virtual display.
70 *70 *
71 * @connection: indicate whether doing connetion or not by user.71 * @connection: indicate whether doing connection or not by user.
72 * @extensions: if this value is 1 then the vidi driver would need additional72 * @extensions: if this value is 1 then the vidi driver would need additional
73 * 128bytes edid data.73 * 128bytes edid data.
74 * @edid: the edid data pointer from user side.74 * @edid: the edid data pointer from user side.
include/uapi/drm/i915_drm.h+125−3
@@ -611,6 +611,13 @@ typedef struct drm_i915_irq_wait { · 610 unmodified lines
611 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.611 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
612 */612 */
613#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53613#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
614
615/*
616 * Revision of the i915-perf uAPI. The value returned helps determine what
617 * i915-perf features are available. See drm_i915_perf_property_id.
618 */
619#define I915_PARAM_PERF_REVISION 54
620
614/* Must be kept compact -- no holes and well documented */621/* Must be kept compact -- no holes and well documented */
615 622
616typedef struct drm_i915_getparam {623typedef struct drm_i915_getparam {
@@ -1565,6 +1572,21 @@ struct drm_i915_gem_context_param { · 948 unmodified lines
1565 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)1572 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1566 */1573 */
1567#define I915_CONTEXT_PARAM_ENGINES 0xa1574#define I915_CONTEXT_PARAM_ENGINES 0xa
1575
1576/*
1577 * I915_CONTEXT_PARAM_PERSISTENCE:
1578 *
1579 * Allow the context and active rendering to survive the process until
1580 * completion. Persistence allows fire-and-forget clients to queue up a
1581 * bunch of work, hand the output over to a display server and then quit.
1582 * If the context is marked as not persistent, upon closing (either via
1583 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
1584 * or process termination), the context and any outstanding requests will be
1585 * cancelled (and exported fences for cancelled requests marked as -EIO).
1586 *
1587 * By default, new contexts allow persistence.
1588 */
1589#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1568/* Must be kept compact -- no holes and well documented */1590/* Must be kept compact -- no holes and well documented */
1569 1591
1570 __u64 value;1592 __u64 value;
@@ -1844,23 +1866,31 @@ enum drm_i915_perf_property_id { · 273 unmodified lines
1844 * Open the stream for a specific context handle (as used with1866 * Open the stream for a specific context handle (as used with
1845 * execbuffer2). A stream opened for a specific context this way1867 * execbuffer2). A stream opened for a specific context this way
1846 * won't typically require root privileges.1868 * won't typically require root privileges.
1869 *
1870 * This property is available in perf revision 1.
1847 */1871 */
1848 DRM_I915_PERF_PROP_CTX_HANDLE = 1,1872 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1849 1873
1850 /**1874 /**
1851 * A value of 1 requests the inclusion of raw OA unit reports as1875 * A value of 1 requests the inclusion of raw OA unit reports as
1852 * part of stream samples.1876 * part of stream samples.
1877 *
1878 * This property is available in perf revision 1.
1853 */1879 */
1854 DRM_I915_PERF_PROP_SAMPLE_OA,1880 DRM_I915_PERF_PROP_SAMPLE_OA,
1855 1881
1856 /**1882 /**
1857 * The value specifies which set of OA unit metrics should be1883 * The value specifies which set of OA unit metrics should be
1858 * be configured, defining the contents of any OA unit reports.1884 * be configured, defining the contents of any OA unit reports.
1885 *
1886 * This property is available in perf revision 1.
1859 */1887 */
1860 DRM_I915_PERF_PROP_OA_METRICS_SET,1888 DRM_I915_PERF_PROP_OA_METRICS_SET,
1861 1889
1862 /**1890 /**
1863 * The value specifies the size and layout of OA unit reports.1891 * The value specifies the size and layout of OA unit reports.
1892 *
1893 * This property is available in perf revision 1.
1864 */1894 */
1865 DRM_I915_PERF_PROP_OA_FORMAT,1895 DRM_I915_PERF_PROP_OA_FORMAT,
1866 1896
@@ -1870,9 +1900,22 @@ enum drm_i915_perf_property_id { · 3 unmodified lines
1870 * from this exponent as follows:1900 * from this exponent as follows:
1871 *1901 *
1872 * 80ns * 2^(period_exponent + 1)1902 * 80ns * 2^(period_exponent + 1)
1903 *
1904 * This property is available in perf revision 1.
1873 */1905 */
1874 DRM_I915_PERF_PROP_OA_EXPONENT,1906 DRM_I915_PERF_PROP_OA_EXPONENT,
1875 1907
1908 /**
1909 * Specifying this property is only valid when specify a context to
1910 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
1911 * will hold preemption of the particular context we want to gather
1912 * performance data about. The execbuf2 submissions must include a
1913 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
1914 *
1915 * This property is available in perf revision 3.
1916 */
1917 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
1918
1876 DRM_I915_PERF_PROP_MAX /* non-ABI */1919 DRM_I915_PERF_PROP_MAX /* non-ABI */
1877};1920};
1878 1921
@@ -1901,6 +1944,8 @@ struct drm_i915_perf_open_param { · 22 unmodified lines
1901 * to close and re-open a stream with the same configuration.1944 * to close and re-open a stream with the same configuration.
1902 *1945 *
1903 * It's undefined whether any pending data for the stream will be lost.1946 * It's undefined whether any pending data for the stream will be lost.
1947 *
1948 * This ioctl is available in perf revision 1.
1904 */1949 */
1905#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)1950#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1906 1951
@@ -1908,9 +1953,24 @@ struct drm_i915_perf_open_param { · 1 unmodified line
1908 * Disable data capture for a stream.1953 * Disable data capture for a stream.
1909 *1954 *
1910 * It is an error to try and read a stream that is disabled.1955 * It is an error to try and read a stream that is disabled.
1956 *
1957 * This ioctl is available in perf revision 1.
1911 */1958 */
1912#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)1959#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1913 1960
1961/**
1962 * Change metrics_set captured by a stream.
1963 *
1964 * If the stream is bound to a specific context, the configuration change
1965 * will performed inline with that context such that it takes effect before
1966 * the next execbuf submission.
1967 *
1968 * Returns the previously bound metrics set id, or a negative error code.
1969 *
1970 * This ioctl is available in perf revision 2.
1971 */
1972#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
1973
1914/**1974/**
1915 * Common to all i915 perf records1975 * Common to all i915 perf records
1916 */1976 */
@@ -1984,6 +2044,7 @@ struct drm_i915_query_item { · 67 unmodified lines
1984 __u64 query_id;2044 __u64 query_id;
1985#define DRM_I915_QUERY_TOPOLOGY_INFO 12045#define DRM_I915_QUERY_TOPOLOGY_INFO 1
1986#define DRM_I915_QUERY_ENGINE_INFO 22046#define DRM_I915_QUERY_ENGINE_INFO 2
2047#define DRM_I915_QUERY_PERF_CONFIG 3
1987/* Must be kept compact -- no holes and well documented */2048/* Must be kept compact -- no holes and well documented */
1988 2049
1989 /*2050 /*
@@ -1995,9 +2056,18 @@ struct drm_i915_query_item { · 5 unmodified lines
1995 __s32 length;2056 __s32 length;
1996 2057
1997 /*2058 /*
1998 * Unused for now. Must be cleared to zero.2059 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2060 *
2061 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2062 * following :
2063 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2064 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2065 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
1999 */2066 */
2000 __u32 flags;2067 __u32 flags;
2068#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2069#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2070#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2001 2071
2002 /*2072 /*
2003 * Data will be written at the location pointed by data_ptr when the2073 * Data will be written at the location pointed by data_ptr when the
@@ -2033,8 +2103,10 @@ struct drm_i915_query { · 29 unmodified lines
2033 * (data[X / 8] >> (X % 8)) & 12103 * (data[X / 8] >> (X % 8)) & 1
2034 *2104 *
2035 * - the subslice mask for each slice with one bit per subslice telling2105 * - the subslice mask for each slice with one bit per subslice telling
2036 * whether a subslice is available. The availability of subslice Y in slice2106 * whether a subslice is available. Gen12 has dual-subslices, which are
2037 * X can be queried with the following formula :2107 * similar to two gen11 subslices. For gen12, this array represents dual-
2108 * subslices. The availability of subslice Y in slice X can be queried
2109 * with the following formula :
2038 *2110 *
2039 * (data[subslice_offset +2111 * (data[subslice_offset +
2040 * X * subslice_stride +2112 * X * subslice_stride +
@@ -2123,6 +2195,56 @@ struct drm_i915_query_engine_info { · 82 unmodified lines
2123 struct drm_i915_engine_info engines[];2195 struct drm_i915_engine_info engines[];
2124};2196};
2125 2197
2198/*
2199 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2200 */
2201struct drm_i915_query_perf_config {
2202 union {
2203 /*
2204 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2205 * this fields to the number of configurations available.
2206 */
2207 __u64 n_configs;
2208
2209 /*
2210 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2211 * i915 will use the value in this field as configuration
2212 * identifier to decide what data to write into config_ptr.
2213 */
2214 __u64 config;
2215
2216 /*
2217 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2218 * i915 will use the value in this field as configuration
2219 * identifier to decide what data to write into config_ptr.
2220 *
2221 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2222 */
2223 char uuid[36];
2224 };
2225
2226 /*
2227 * Unused for now. Must be cleared to zero.
2228 */
2229 __u32 flags;
2230
2231 /*
2232 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2233 * write an array of __u64 of configuration identifiers.
2234 *
2235 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2236 * write a struct drm_i915_perf_oa_config. If the following fields of
2237 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2238 * the associated pointers the values of submitted when the
2239 * configuration was created :
2240 *
2241 * - n_mux_regs
2242 * - n_boolean_regs
2243 * - n_flex_regs
2244 */
2245 __u8 data[];
2246};
2247
2126#if defined(__cplusplus)2248#if defined(__cplusplus)
2127}2249}
2128#endif2250#endif
include/uapi/drm/omap_drm.h+9−9
@@ -38,20 +38,20 @@ struct drm_omap_param { · 37 unmodified lines
38 __u64 value; /* in (set_param), out (get_param) */38 __u64 value; /* in (set_param), out (get_param) */
39};39};
40 40
41#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable (phys contiguous) */41/* Scanout buffer, consumable by DSS */
42#define OMAP_BO_CACHE_MASK 0x00000006 /* cache type mask, see cache modes */42#define OMAP_BO_SCANOUT 0x00000001
43#define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
44 43
45/* cache modes */44/* Buffer CPU caching mode: cached, write-combining or uncached. */
46#define OMAP_BO_CACHED 0x00000000 /* default */45#define OMAP_BO_CACHED 0x00000000
47#define OMAP_BO_WC 0x00000002 /* write-combine */46#define OMAP_BO_WC 0x00000002
48#define OMAP_BO_UNCACHED 0x00000004 /* strongly-ordered (uncached) */47#define OMAP_BO_UNCACHED 0x00000004
48#define OMAP_BO_CACHE_MASK 0x00000006
49 49
50/* tiled modes */50/* Use TILER for the buffer. The TILER container unit can be 8, 16 or 32 bits. */
51#define OMAP_BO_TILED_8 0x0000010051#define OMAP_BO_TILED_8 0x00000100
52#define OMAP_BO_TILED_16 0x0000020052#define OMAP_BO_TILED_16 0x00000200
53#define OMAP_BO_TILED_32 0x0000030053#define OMAP_BO_TILED_32 0x00000300
54#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32)54#define OMAP_BO_TILED_MASK 0x00000f00
55 55
56union omap_gem_size {56union omap_gem_size {
57 __u32 bytes; /* (for non-tiled formats) */57 __u32 bytes; /* (for non-tiled formats) */
include/uapi/drm/v3d_drm.h+5−3
@@ -48,6 +48,8 @@ extern "C" { · 47 unmodified lines
48#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)48#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
49#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)49#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
50 50
51#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
52
51/**53/**
52 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D54 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
53 * engine.55 * engine.
@@ -61,7 +63,7 @@ extern "C" { · 7 unmodified lines
61 * flushed by the time the render done IRQ happens, which is the63 * flushed by the time the render done IRQ happens, which is the
62 * trigger for out_sync. Any dirtying of cachelines by the job (only64 * trigger for out_sync. Any dirtying of cachelines by the job (only
63 * possible using TMU writes) must be flushed by the caller using the65 * possible using TMU writes) must be flushed by the caller using the
64 * CL's cache flush commands.66 * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
65 */67 */
66struct drm_v3d_submit_cl {68struct drm_v3d_submit_cl {
67 /* Pointer to the binner command list.69 /* Pointer to the binner command list.
@@ -124,8 +126,7 @@ struct drm_v3d_submit_cl { · 56 unmodified lines
124 /* Number of BO handles passed in (size is that times 4). */126 /* Number of BO handles passed in (size is that times 4). */
125 __u32 bo_handle_count;127 __u32 bo_handle_count;
126 128
127 /* Pad, must be zero-filled. */129 __u32 flags;
128 __u32 pad;
129};130};
130 131
131/**132/**
@@ -193,6 +194,7 @@ enum drm_v3d_param { · 61 unmodified lines
193 DRM_V3D_PARAM_V3D_CORE0_IDENT2,194 DRM_V3D_PARAM_V3D_CORE0_IDENT2,
194 DRM_V3D_PARAM_SUPPORTS_TFU,195 DRM_V3D_PARAM_SUPPORTS_TFU,
195 DRM_V3D_PARAM_SUPPORTS_CSD,196 DRM_V3D_PARAM_SUPPORTS_CSD,
197 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
196};198};
197 199
198struct drm_v3d_get_param {200struct drm_v3d_get_param {