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Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next

Merge an immutable branch between MFD, GPIO, Input and PWM to resolve conflicts for the merge window pull request.

Dmitry Torokhov committed 1 year ago

Commit a7bee4e2 parents 61c6fef 45ee66c13062 files · +592656 −260656Browse files

Showing the changes to include/uapi (73 of 13062 files). Show all

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73 files
  1. include/uapi/asm-generic/socket.h +2 −0
  2. include/uapi/drm/amdgpu_drm.h +317 −0
  3. include/uapi/drm/asahi_drm.h +1194 −0
  4. include/uapi/drm/drm.h +4 −0
  5. include/uapi/drm/drm_fourcc.h +45 −0
  6. include/uapi/drm/nova_drm.h +101 −0
  7. include/uapi/drm/panthor_drm.h +23 −0
  8. include/uapi/drm/virtgpu_drm.h +6 −0
  9. include/uapi/drm/xe_drm.h +10 −1
  10. include/uapi/linux/blktrace_api.h +1 −1
  11. include/uapi/linux/bpf.h +14 −7
  12. include/uapi/linux/cec-funcs.h +20 −20
  13. include/uapi/linux/devlink.h +15 −0
  14. include/uapi/linux/dm-ioctl.h +7 −2
  15. include/uapi/linux/ethtool.h +69 −65
  16. include/uapi/linux/ethtool_netlink_generated.h +14 −0
  17. include/uapi/linux/fib_rules.h +2 −2
  18. include/uapi/linux/fs.h +1 −0
  19. include/uapi/linux/fscrypt.h +4 −2
  20. include/uapi/linux/fuse.h +5 −1
  21. include/uapi/linux/futex.h +8 −1
  22. include/uapi/linux/if_addr.h +2 −2
  23. include/uapi/linux/if_addrlabel.h +2 −2
  24. include/uapi/linux/if_alg.h +3 −3
  25. include/uapi/linux/if_arcnet.h +3 −3
  26. include/uapi/linux/if_bonding.h +3 −3
  27. include/uapi/linux/if_bridge.h +6 −4
  28. include/uapi/linux/if_fc.h +3 −3
  29. include/uapi/linux/if_hippi.h +3 −3
  30. include/uapi/linux/if_link.h +15 −0
  31. include/uapi/linux/if_packet.h +2 −2
  32. include/uapi/linux/if_plip.h +2 −2
  33. include/uapi/linux/if_slip.h +2 −2
  34. include/uapi/linux/if_x25.h +3 −3
  35. include/uapi/linux/if_xdp.h +3 −3
  36. include/uapi/linux/input-event-codes.h +2 −1
  37. include/uapi/linux/io_uring.h +11 −1
  38. include/uapi/linux/ip6_tunnel.h +2 −2
  39. include/uapi/linux/isst_if.h +26 −0
  40. include/uapi/linux/kfd_ioctl.h +5 −0
  41. include/uapi/linux/kvm.h +4 −0
  42. include/uapi/linux/media/amlogic/c3-isp-config.h +564 −0
  43. include/uapi/linux/neighbour.h +2 −2
  44. include/uapi/linux/net_dropmon.h +2 −2
  45. include/uapi/linux/net_tstamp.h +3 −3
  46. include/uapi/linux/netdev.h +1 −0
  47. include/uapi/linux/netfilter/nf_tables.h +22 −0
  48. include/uapi/linux/netfilter/nfnetlink.h +2 −0
  49. include/uapi/linux/netlink_diag.h +2 −2
  50. include/uapi/linux/nl80211.h +6 −0
  51. include/uapi/linux/ovpn.h +109 −0
  52. include/uapi/linux/pci_regs.h +11 −1
  53. include/uapi/linux/perf_event.h +334 −323
  54. include/uapi/linux/pidfd.h +17 −1
  55. include/uapi/linux/pkt_cls.h +3 −2
  56. include/uapi/linux/pkt_sched.h +3 −2
  57. include/uapi/linux/prctl.h +7 −0
  58. include/uapi/linux/ptrace.h +6 −1
  59. include/uapi/linux/rxrpc.h +65 −12
  60. include/uapi/linux/snmp.h +1 −0
  61. include/uapi/linux/stat.h +6 −2
  62. include/uapi/linux/taskstats.h +29 −18
  63. include/uapi/linux/tcp.h +1 −0
  64. include/uapi/linux/tiocl.h +1 −0
  65. include/uapi/linux/ublk_cmd.h +137 −0
  66. include/uapi/linux/udp.h +1 −0
  67. include/uapi/linux/videodev2.h +16 −2
  68. include/uapi/linux/virtio_gpu.h +2 −1
  69. include/uapi/linux/virtio_rtc.h +237 −0
  70. include/uapi/linux/vt.h +11 −0
  71. include/uapi/linux/wireguard.h +9 −0
  72. include/uapi/misc/amd-apml.h +152 −0
  73. include/uapi/rdma/ib_user_verbs.h +16 −0
include/uapi/asm-generic/socket.h+2−0
@@ -145,6 +145,8 @@ · 144 unmodified lines
145145
146146 #define SO_RCVPRIORITY 82
147147
148+#define SO_PASSRIGHTS 83
149+
148150 #if !defined(__KERNEL__)
149151
150152 #if __BITS_PER_LONG == 64 || (defined(__x86_64__) && defined(__ILP32__))
include/uapi/drm/amdgpu_drm.h+317−0
@@ -54,6 +54,9 @@ extern "C" { · 53 unmodified lines
5454 #define DRM_AMDGPU_VM 0x13
5555 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
5656 #define DRM_AMDGPU_SCHED 0x15
57+#define DRM_AMDGPU_USERQ 0x16
58+#define DRM_AMDGPU_USERQ_SIGNAL 0x17
59+#define DRM_AMDGPU_USERQ_WAIT 0x18
5760
5861 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
5962 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -71,6 +74,9 @@ extern "C" { · 11 unmodified lines
7174 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
7275 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
7376 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
77+#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
78+#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
79+#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
7480
7581 /**
7682 * DOC: memory domains
@@ -319,6 +325,260 @@ union drm_amdgpu_ctx { · 242 unmodified lines
319325 union drm_amdgpu_ctx_out out;
320326 };
321327
328+/* user queue IOCTL operations */
329+#define AMDGPU_USERQ_OP_CREATE 1
330+#define AMDGPU_USERQ_OP_FREE 2
331+
332+/* queue priority levels */
333+/* low < normal low < normal high < high */
334+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
335+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
336+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
337+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
338+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
339+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
340+/* for queues that need access to protected content */
341+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
342+
343+/*
344+ * This structure is a container to pass input configuration
345+ * info for all supported userqueue related operations.
346+ * For operation AMDGPU_USERQ_OP_CREATE: user is expected
347+ * to set all fields, excep the parameter 'queue_id'.
348+ * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
349+ * to be set is 'queue_id', eveything else is ignored.
350+ */
351+struct drm_amdgpu_userq_in {
352+ /** AMDGPU_USERQ_OP_* */
353+ __u32 op;
354+ /** Queue id passed for operation USERQ_OP_FREE */
355+ __u32 queue_id;
356+ /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
357+ __u32 ip_type;
358+ /**
359+ * @doorbell_handle: the handle of doorbell GEM object
360+ * associated with this userqueue client.
361+ */
362+ __u32 doorbell_handle;
363+ /**
364+ * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
365+ * Kernel will generate absolute doorbell offset using doorbell_handle
366+ * and doorbell_offset in the doorbell bo.
367+ */
368+ __u32 doorbell_offset;
369+ /**
370+ * @flags: flags used for queue parameters
371+ */
372+ __u32 flags;
373+ /**
374+ * @queue_va: Virtual address of the GPU memory which holds the queue
375+ * object. The queue holds the workload packets.
376+ */
377+ __u64 queue_va;
378+ /**
379+ * @queue_size: Size of the queue in bytes, this needs to be 256-byte
380+ * aligned.
381+ */
382+ __u64 queue_size;
383+ /**
384+ * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
385+ * This object must be at least 8 byte in size and aligned to 8-byte offset.
386+ */
387+ __u64 rptr_va;
388+ /**
389+ * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
390+ * This object must be at least 8 byte in size and aligned to 8-byte offset.
391+ *
392+ * Queue, RPTR and WPTR can come from the same object, as long as the size
393+ * and alignment related requirements are met.
394+ */
395+ __u64 wptr_va;
396+ /**
397+ * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
398+ * the GPU to uniquely define and identify a usermode queue.
399+ *
400+ * MQD data can be of different size for different GPU IP/engine and
401+ * their respective versions/revisions, so this points to a __u64 *
402+ * which holds IP specific MQD of this usermode queue.
403+ */
404+ __u64 mqd;
405+ /**
406+ * @size: size of MQD data in bytes, it must match the MQD structure
407+ * size of the respective engine/revision defined in UAPI for ex, for
408+ * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
409+ */
410+ __u64 mqd_size;
411+};
412+
413+/* The structure to carry output of userqueue ops */
414+struct drm_amdgpu_userq_out {
415+ /**
416+ * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
417+ * queue ID to represent the newly created userqueue in the system, otherwise
418+ * it should be ignored.
419+ */
420+ __u32 queue_id;
421+ __u32 _pad;
422+};
423+
424+union drm_amdgpu_userq {
425+ struct drm_amdgpu_userq_in in;
426+ struct drm_amdgpu_userq_out out;
427+};
428+
429+/* GFX V11 IP specific MQD parameters */
430+struct drm_amdgpu_userq_mqd_gfx11 {
431+ /**
432+ * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
433+ * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
434+ */
435+ __u64 shadow_va;
436+ /**
437+ * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
438+ * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
439+ */
440+ __u64 csa_va;
441+};
442+
443+/* GFX V11 SDMA IP specific MQD parameters */
444+struct drm_amdgpu_userq_mqd_sdma_gfx11 {
445+ /**
446+ * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
447+ * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
448+ * to get the size.
449+ */
450+ __u64 csa_va;
451+};
452+
453+/* GFX V11 Compute IP specific MQD parameters */
454+struct drm_amdgpu_userq_mqd_compute_gfx11 {
455+ /**
456+ * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
457+ * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
458+ * to get the size.
459+ */
460+ __u64 eop_va;
461+};
462+
463+/* userq signal/wait ioctl */
464+struct drm_amdgpu_userq_signal {
465+ /**
466+ * @queue_id: Queue handle used by the userq fence creation function
467+ * to retrieve the WPTR.
468+ */
469+ __u32 queue_id;
470+ __u32 pad;
471+ /**
472+ * @syncobj_handles: The list of syncobj handles submitted by the user queue
473+ * job to be signaled.
474+ */
475+ __u64 syncobj_handles;
476+ /**
477+ * @num_syncobj_handles: A count that represents the number of syncobj handles in
478+ * @syncobj_handles.
479+ */
480+ __u64 num_syncobj_handles;
481+ /**
482+ * @bo_read_handles: The list of BO handles that the submitted user queue job
483+ * is using for read only. This will update BO fences in the kernel.
484+ */
485+ __u64 bo_read_handles;
486+ /**
487+ * @bo_write_handles: The list of BO handles that the submitted user queue job
488+ * is using for write only. This will update BO fences in the kernel.
489+ */
490+ __u64 bo_write_handles;
491+ /**
492+ * @num_bo_read_handles: A count that represents the number of read BO handles in
493+ * @bo_read_handles.
494+ */
495+ __u32 num_bo_read_handles;
496+ /**
497+ * @num_bo_write_handles: A count that represents the number of write BO handles in
498+ * @bo_write_handles.
499+ */
500+ __u32 num_bo_write_handles;
501+};
502+
503+struct drm_amdgpu_userq_fence_info {
504+ /**
505+ * @va: A gpu address allocated for each queue which stores the
506+ * read pointer (RPTR) value.
507+ */
508+ __u64 va;
509+ /**
510+ * @value: A 64 bit value represents the write pointer (WPTR) of the
511+ * queue commands which compared with the RPTR value to signal the
512+ * fences.
513+ */
514+ __u64 value;
515+};
516+
517+struct drm_amdgpu_userq_wait {
518+ /**
519+ * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the
520+ * wait queue and maintain the fence driver references in it.
521+ */
522+ __u32 waitq_id;
523+ __u32 pad;
524+ /**
525+ * @syncobj_handles: The list of syncobj handles submitted by the user queue
526+ * job to get the va/value pairs.
527+ */
528+ __u64 syncobj_handles;
529+ /**
530+ * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
531+ * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
532+ */
533+ __u64 syncobj_timeline_handles;
534+ /**
535+ * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
536+ * user queue job for the corresponding @syncobj_timeline_handles.
537+ */
538+ __u64 syncobj_timeline_points;
539+ /**
540+ * @bo_read_handles: The list of read BO handles submitted by the user queue
541+ * job to get the va/value pairs.
542+ */
543+ __u64 bo_read_handles;
544+ /**
545+ * @bo_write_handles: The list of write BO handles submitted by the user queue
546+ * job to get the va/value pairs.
547+ */
548+ __u64 bo_write_handles;
549+ /**
550+ * @num_syncobj_timeline_handles: A count that represents the number of timeline
551+ * syncobj handles in @syncobj_timeline_handles.
552+ */
553+ __u16 num_syncobj_timeline_handles;
554+ /**
555+ * @num_fences: This field can be used both as input and output. As input it defines
556+ * the maximum number of fences that can be returned and as output it will specify
557+ * how many fences were actually returned from the ioctl.
558+ */
559+ __u16 num_fences;
560+ /**
561+ * @num_syncobj_handles: A count that represents the number of syncobj handles in
562+ * @syncobj_handles.
563+ */
564+ __u32 num_syncobj_handles;
565+ /**
566+ * @num_bo_read_handles: A count that represents the number of read BO handles in
567+ * @bo_read_handles.
568+ */
569+ __u32 num_bo_read_handles;
570+ /**
571+ * @num_bo_write_handles: A count that represents the number of write BO handles in
572+ * @bo_write_handles.
573+ */
574+ __u32 num_bo_write_handles;
575+ /**
576+ * @out_fences: The field is a return value from the ioctl containing the list of
577+ * address/value pairs to wait for.
578+ */
579+ __u64 out_fences;
580+};
581+
322582 /* vm ioctl */
323583 #define AMDGPU_VM_OP_RESERVE_VMID 1
324584 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
@@ -599,6 +859,19 @@ struct drm_amdgpu_gem_va { · 274 unmodified lines
599859 __u64 offset_in_bo;
600860 /** Specify mapping size. Must be correctly aligned. */
601861 __u64 map_size;
862+ /**
863+ * vm_timeline_point is a sequence number used to add new timeline point.
864+ */
865+ __u64 vm_timeline_point;
866+ /**
867+ * The vm page table update fence is installed in given vm_timeline_syncobj_out
868+ * at vm_timeline_point.
869+ */
870+ __u32 vm_timeline_syncobj_out;
871+ /** the number of syncobj handles in @input_fence_syncobj_handles */
872+ __u32 num_syncobj_handles;
873+ /** Array of sync object handle to wait for given input fences */
874+ __u64 input_fence_syncobj_handles;
602875 };
603876
604877 #define AMDGPU_HW_IP_GFX 0
@@ -940,6 +1213,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { · 335 unmodified lines
9401213 #define AMDGPU_INFO_MAX_IBS 0x22
9411214 /* query last page fault info */
9421215 #define AMDGPU_INFO_GPUVM_FAULT 0x23
1216+/* query FW object size and alignment */
1217+#define AMDGPU_INFO_UQ_FW_AREAS 0x24
9431218
9441219 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
9451220 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -1093,6 +1368,7 @@ struct drm_amdgpu_info_vbios { · 147 unmodified lines
10931368 #define AMDGPU_VRAM_TYPE_DDR5 10
10941369 #define AMDGPU_VRAM_TYPE_LPDDR4 11
10951370 #define AMDGPU_VRAM_TYPE_LPDDR5 12
1371+#define AMDGPU_VRAM_TYPE_HBM3E 13
10961372
10971373 struct drm_amdgpu_info_device {
10981374 /** PCI Device ID */
@@ -1198,6 +1474,9 @@ struct drm_amdgpu_info_device { · 99 unmodified lines
11981474 __u32 csa_size;
11991475 /* context save area base virtual alignment for gfx11 */
12001476 __u32 csa_alignment;
1477+ /* Userq IP mask (1 << AMDGPU_HW_IP_*) */
1478+ __u32 userq_ip_mask;
1479+ __u32 pad;
12011480 };
12021481
12031482 struct drm_amdgpu_info_hw_ip {
@@ -1216,6 +1495,27 @@ struct drm_amdgpu_info_hw_ip { · 12 unmodified lines
12161495 __u32 ip_discovery_version;
12171496 };
12181497
1498+/* GFX metadata BO sizes and alignment info (in bytes) */
1499+struct drm_amdgpu_info_uq_fw_areas_gfx {
1500+ /* shadow area size */
1501+ __u32 shadow_size;
1502+ /* shadow area base virtual mem alignment */
1503+ __u32 shadow_alignment;
1504+ /* context save area size */
1505+ __u32 csa_size;
1506+ /* context save area base virtual mem alignment */
1507+ __u32 csa_alignment;
1508+};
1509+
1510+/* IP specific fw related information used in the
1511+ * subquery AMDGPU_INFO_UQ_FW_AREAS
1512+ */
1513+struct drm_amdgpu_info_uq_fw_areas {
1514+ union {
1515+ struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
1516+ };
1517+};
1518+
12191519 struct drm_amdgpu_info_num_handles {
12201520 /** Max handles as supported by firmware for UVD */
12211521 __u32 uvd_max_handles;
@@ -1279,6 +1579,23 @@ struct drm_amdgpu_info_gpuvm_fault { · 57 unmodified lines
12791579 __u32 vmhub;
12801580 };
12811581
1582+struct drm_amdgpu_info_uq_metadata_gfx {
1583+ /* shadow area size for gfx11 */
1584+ __u32 shadow_size;
1585+ /* shadow area base virtual alignment for gfx11 */
1586+ __u32 shadow_alignment;
1587+ /* context save area size for gfx11 */
1588+ __u32 csa_size;
1589+ /* context save area base virtual alignment for gfx11 */
1590+ __u32 csa_alignment;
1591+};
1592+
1593+struct drm_amdgpu_info_uq_metadata {
1594+ union {
1595+ struct drm_amdgpu_info_uq_metadata_gfx gfx;
1596+ };
1597+};
1598+
12821599 /*
12831600 * Supported GPU families
12841601 */
include/uapi/drm/asahi_drm.h+1194−0
@@ -0,0 +1,1194 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright (C) The Asahi Linux Contributors
4+ * Copyright (C) 2018-2023 Collabora Ltd.
5+ * Copyright (C) 2014-2018 Broadcom
6+ */
7+#ifndef _ASAHI_DRM_H_
8+#define _ASAHI_DRM_H_
9+
10+#include "drm.h"
11+
12+#if defined(__cplusplus)
13+extern "C" {
14+#endif
15+
16+/**
17+ * DOC: Introduction to the Asahi UAPI
18+ *
19+ * This documentation describes the Asahi IOCTLs.
20+ *
21+ * Just a few generic rules about the data passed to the Asahi IOCTLs (cribbed
22+ * from Panthor):
23+ *
24+ * - Structures must be aligned on 64-bit/8-byte. If the object is not
25+ * naturally aligned, a padding field must be added.
26+ * - Fields must be explicitly aligned to their natural type alignment with
27+ * pad[0..N] fields.
28+ * - All padding fields will be checked by the driver to make sure they are
29+ * zeroed.
30+ * - Flags can be added, but not removed/replaced.
31+ * - New fields can be added to the main structures (the structures
32+ * directly passed to the ioctl). Those fields can be added at the end of
33+ * the structure, or replace existing padding fields. Any new field being
34+ * added must preserve the behavior that existed before those fields were
35+ * added when a value of zero is passed.
36+ * - New fields can be added to indirect objects (objects pointed by the
37+ * main structure), iff those objects are passed a size to reflect the
38+ * size known by the userspace driver (see
39+ * drm_asahi_cmd_header::size).
40+ * - If the kernel driver is too old to know some fields, those will be
41+ * ignored if zero, and otherwise rejected (and so will be zero on output).
42+ * - If userspace is too old to know some fields, those will be zeroed
43+ * (input) before the structure is parsed by the kernel driver.
44+ * - Each new flag/field addition must come with a driver version update so
45+ * the userspace driver doesn't have to guess which flags are supported.
46+ * - Structures should not contain unions, as this would defeat the
47+ * extensibility of such structures.
48+ * - IOCTLs can't be removed or replaced. New IOCTL IDs should be placed
49+ * at the end of the drm_asahi_ioctl_id enum.
50+ */
51+
52+/**
53+ * enum drm_asahi_ioctl_id - IOCTL IDs
54+ *
55+ * Place new ioctls at the end, don't re-order, don't replace or remove entries.
56+ *
57+ * These IDs are not meant to be used directly. Use the DRM_IOCTL_ASAHI_xxx
58+ * definitions instead.
59+ */
60+enum drm_asahi_ioctl_id {
61+ /** @DRM_ASAHI_GET_PARAMS: Query device properties. */
62+ DRM_ASAHI_GET_PARAMS = 0,
63+
64+ /** @DRM_ASAHI_GET_TIME: Query device time. */
65+ DRM_ASAHI_GET_TIME,
66+
67+ /** @DRM_ASAHI_VM_CREATE: Create a GPU VM address space. */
68+ DRM_ASAHI_VM_CREATE,
69+
70+ /** @DRM_ASAHI_VM_DESTROY: Destroy a VM. */
71+ DRM_ASAHI_VM_DESTROY,
72+
73+ /** @DRM_ASAHI_VM_BIND: Bind/unbind memory to a VM. */
74+ DRM_ASAHI_VM_BIND,
75+
76+ /** @DRM_ASAHI_GEM_CREATE: Create a buffer object. */
77+ DRM_ASAHI_GEM_CREATE,
78+
79+ /**
80+ * @DRM_ASAHI_GEM_MMAP_OFFSET: Get offset to pass to mmap() to map a
81+ * given GEM handle.
82+ */
83+ DRM_ASAHI_GEM_MMAP_OFFSET,
84+
85+ /** @DRM_ASAHI_GEM_BIND_OBJECT: Bind memory as a special object */
86+ DRM_ASAHI_GEM_BIND_OBJECT,
87+
88+ /** @DRM_ASAHI_QUEUE_CREATE: Create a scheduling queue. */
89+ DRM_ASAHI_QUEUE_CREATE,
90+
91+ /** @DRM_ASAHI_QUEUE_DESTROY: Destroy a scheduling queue. */
92+ DRM_ASAHI_QUEUE_DESTROY,
93+
94+ /** @DRM_ASAHI_SUBMIT: Submit commands to a queue. */
95+ DRM_ASAHI_SUBMIT,
96+};
97+
98+#define DRM_ASAHI_MAX_CLUSTERS 64
99+
100+/**
101+ * struct drm_asahi_params_global - Global parameters.
102+ *
103+ * This struct may be queried by drm_asahi_get_params.
104+ */
105+struct drm_asahi_params_global {
106+ /** @features: Feature bits from drm_asahi_feature */
107+ __u64 features;
108+
109+ /** @gpu_generation: GPU generation, e.g. 13 for G13G */
110+ __u32 gpu_generation;
111+
112+ /** @gpu_variant: GPU variant as a character, e.g. 'C' for G13C */
113+ __u32 gpu_variant;
114+
115+ /**
116+ * @gpu_revision: GPU revision in BCD, e.g. 0x00 for 'A0' or
117+ * 0x21 for 'C1'
118+ */
119+ __u32 gpu_revision;
120+
121+ /** @chip_id: Chip ID in BCD, e.g. 0x8103 for T8103 */
122+ __u32 chip_id;
123+
124+ /** @num_dies: Number of dies in the SoC */
125+ __u32 num_dies;
126+
127+ /** @num_clusters_total: Number of GPU clusters (across all dies) */
128+ __u32 num_clusters_total;
129+
130+ /**
131+ * @num_cores_per_cluster: Number of logical cores per cluster
132+ * (including inactive/nonexistent)
133+ */
134+ __u32 num_cores_per_cluster;
135+
136+ /** @max_frequency_khz: Maximum GPU core clock frequency */
137+ __u32 max_frequency_khz;
138+
139+ /** @core_masks: Bitmask of present/enabled cores per cluster */
140+ __u64 core_masks[DRM_ASAHI_MAX_CLUSTERS];
141+
142+ /**
143+ * @vm_start: VM range start VMA. Together with @vm_end, this defines
144+ * the window of valid GPU VAs. Userspace is expected to subdivide VAs
145+ * out of this window.
146+ *
147+ * This window contains all virtual addresses that userspace needs to
148+ * know about. There may be kernel-internal GPU VAs outside this range,
149+ * but that detail is not relevant here.
150+ */
151+ __u64 vm_start;
152+
153+ /** @vm_end: VM range end VMA */
154+ __u64 vm_end;
155+
156+ /**
157+ * @vm_kernel_min_size: Minimum kernel VMA window size.
158+ *
159+ * When creating a VM, userspace is required to carve out a section of
160+ * virtual addresses (within the range given by @vm_start and
161+ * @vm_end). The kernel will allocate various internal structures
162+ * within the specified VA range.
163+ *
164+ * Allowing userspace to choose the VA range for the kernel, rather than
165+ * the kernel reserving VAs and requiring userspace to cope, can assist
166+ * in implementing SVM.
167+ */
168+ __u64 vm_kernel_min_size;
169+
170+ /**
171+ * @max_commands_per_submission: Maximum number of supported commands
172+ * per submission. This mirrors firmware limits. Userspace must split up
173+ * larger command buffers, which may require inserting additional
174+ * synchronization.
175+ */
176+ __u32 max_commands_per_submission;
177+
178+ /**
179+ * @max_attachments: Maximum number of drm_asahi_attachment's per
180+ * command
181+ */
182+ __u32 max_attachments;
183+
184+ /**
185+ * @command_timestamp_frequency_hz: Timebase frequency for timestamps
186+ * written during command execution, specified via drm_asahi_timestamp
187+ * structures. As this rate is controlled by the firmware, it is a
188+ * queryable parameter.
189+ *
190+ * Userspace must divide by this frequency to convert timestamps to
191+ * seconds, rather than hardcoding a particular firmware's rate.
192+ */
193+ __u64 command_timestamp_frequency_hz;
194+};
195+
196+/**
197+ * enum drm_asahi_feature - Feature bits
198+ *
199+ * This covers only features that userspace cannot infer from the architecture
200+ * version. Most features don't need to be here.
201+ */
202+enum drm_asahi_feature {
203+ /**
204+ * @DRM_ASAHI_FEATURE_SOFT_FAULTS: GPU has "soft fault" enabled. Shader
205+ * loads of unmapped memory will return zero. Shader stores to unmapped
206+ * memory will be silently discarded. Note that only shader load/store
207+ * is affected. Other hardware units are not affected, notably including
208+ * texture sampling.
209+ *
210+ * Soft fault is set when initializing the GPU and cannot be runtime
211+ * toggled. Therefore, it is exposed as a feature bit and not a
212+ * userspace-settable flag on the VM. When soft fault is enabled,
213+ * userspace can speculate memory accesses more aggressively.
214+ */
215+ DRM_ASAHI_FEATURE_SOFT_FAULTS = (1UL) << 0,
216+};
217+
218+/**
219+ * struct drm_asahi_get_params - Arguments passed to DRM_IOCTL_ASAHI_GET_PARAMS
220+ */
221+struct drm_asahi_get_params {
222+ /** @param_group: Parameter group to fetch (MBZ) */
223+ __u32 param_group;
224+
225+ /** @pad: MBZ */
226+ __u32 pad;
227+
228+ /** @pointer: User pointer to write parameter struct */
229+ __u64 pointer;
230+
231+ /**
232+ * @size: Size of the user buffer. In case of older userspace, this may
233+ * be less than sizeof(struct drm_asahi_params_global). The kernel will
234+ * not write past the length specified here, allowing extensibility.
235+ */
236+ __u64 size;
237+};
238+
239+/**
240+ * struct drm_asahi_vm_create - Arguments passed to DRM_IOCTL_ASAHI_VM_CREATE
241+ */
242+struct drm_asahi_vm_create {
243+ /**
244+ * @kernel_start: Start of the kernel-reserved address range. See
245+ * drm_asahi_params_global::vm_kernel_min_size.
246+ *
247+ * Both @kernel_start and @kernel_end must be within the range of
248+ * valid VAs given by drm_asahi_params_global::vm_start and
249+ * drm_asahi_params_global::vm_end. The size of the kernel range
250+ * (@kernel_end - @kernel_start) must be at least
251+ * drm_asahi_params_global::vm_kernel_min_size.
252+ *
253+ * Userspace must not bind any memory on this VM into this reserved
254+ * range, it is for kernel use only.
255+ */
256+ __u64 kernel_start;
257+
258+ /**
259+ * @kernel_end: End of the kernel-reserved address range. See
260+ * @kernel_start.
261+ */
262+ __u64 kernel_end;
263+
264+ /** @vm_id: Returned VM ID */
265+ __u32 vm_id;
266+
267+ /** @pad: MBZ */
268+ __u32 pad;
269+};
270+
271+/**
272+ * struct drm_asahi_vm_destroy - Arguments passed to DRM_IOCTL_ASAHI_VM_DESTROY
273+ */
274+struct drm_asahi_vm_destroy {
275+ /** @vm_id: VM ID to be destroyed */
276+ __u32 vm_id;
277+
278+ /** @pad: MBZ */
279+ __u32 pad;
280+};
281+
282+/**
283+ * enum drm_asahi_gem_flags - Flags for GEM creation
284+ */
285+enum drm_asahi_gem_flags {
286+ /**
287+ * @DRM_ASAHI_GEM_WRITEBACK: BO should be CPU-mapped as writeback.
288+ *
289+ * Map as writeback instead of write-combine. This optimizes for CPU
290+ * reads.
291+ */
292+ DRM_ASAHI_GEM_WRITEBACK = (1L << 0),
293+
294+ /**
295+ * @DRM_ASAHI_GEM_VM_PRIVATE: BO is private to this GPU VM (no exports).
296+ */
297+ DRM_ASAHI_GEM_VM_PRIVATE = (1L << 1),
298+};
299+
300+/**
301+ * struct drm_asahi_gem_create - Arguments passed to DRM_IOCTL_ASAHI_GEM_CREATE
302+ */
303+struct drm_asahi_gem_create {
304+ /** @size: Size of the BO */
305+ __u64 size;
306+
307+ /** @flags: Combination of drm_asahi_gem_flags flags. */
308+ __u32 flags;
309+
310+ /**
311+ * @vm_id: VM ID to assign to the BO, if DRM_ASAHI_GEM_VM_PRIVATE is set
312+ */
313+ __u32 vm_id;
314+
315+ /** @handle: Returned GEM handle for the BO */
316+ __u32 handle;
317+
318+ /** @pad: MBZ */
319+ __u32 pad;
320+};
321+
322+/**
323+ * struct drm_asahi_gem_mmap_offset - Arguments passed to
324+ * DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET
325+ */
326+struct drm_asahi_gem_mmap_offset {
327+ /** @handle: Handle for the object being mapped. */
328+ __u32 handle;
329+
330+ /** @flags: Must be zero */
331+ __u32 flags;
332+
333+ /** @offset: The fake offset to use for subsequent mmap call */
334+ __u64 offset;
335+};
336+
337+/**
338+ * enum drm_asahi_bind_flags - Flags for GEM binding
339+ */
340+enum drm_asahi_bind_flags {
341+ /**
342+ * @DRM_ASAHI_BIND_UNBIND: Instead of binding a GEM object to the range,
343+ * simply unbind the GPU VMA range.
344+ */
345+ DRM_ASAHI_BIND_UNBIND = (1L << 0),
346+
347+ /** @DRM_ASAHI_BIND_READ: Map BO with GPU read permission */
348+ DRM_ASAHI_BIND_READ = (1L << 1),
349+
350+ /** @DRM_ASAHI_BIND_WRITE: Map BO with GPU write permission */
351+ DRM_ASAHI_BIND_WRITE = (1L << 2),
352+
353+ /**
354+ * @DRM_ASAHI_BIND_SINGLE_PAGE: Map a single page of the BO repeatedly
355+ * across the VA range.
356+ *
357+ * This is useful to fill a VA range with scratch pages or zero pages.
358+ * It is intended as a mechanism to accelerate sparse.
359+ */
360+ DRM_ASAHI_BIND_SINGLE_PAGE = (1L << 3),
361+};
362+
363+/**
364+ * struct drm_asahi_gem_bind_op - Description of a single GEM bind operation.
365+ */
366+struct drm_asahi_gem_bind_op {
367+ /** @flags: Combination of drm_asahi_bind_flags flags. */
368+ __u32 flags;
369+
370+ /** @handle: GEM object to bind (except for UNBIND) */
371+ __u32 handle;
372+
373+ /**
374+ * @offset: Offset into the object (except for UNBIND).
375+ *
376+ * For a regular bind, this is the beginning of the region of the GEM
377+ * object to bind.
378+ *
379+ * For a single-page bind, this is the offset to the single page that
380+ * will be repeatedly bound.
381+ *
382+ * Must be page-size aligned.
383+ */
384+ __u64 offset;
385+
386+ /**
387+ * @range: Number of bytes to bind/unbind to @addr.
388+ *
389+ * Must be page-size aligned.
390+ */
391+ __u64 range;
392+
393+ /**
394+ * @addr: Address to bind to.
395+ *
396+ * Must be page-size aligned.
397+ */
398+ __u64 addr;
399+};
400+
401+/**
402+ * struct drm_asahi_vm_bind - Arguments passed to
403+ * DRM_IOCTL_ASAHI_VM_BIND
404+ */
405+struct drm_asahi_vm_bind {
406+ /** @vm_id: The ID of the VM to bind to */
407+ __u32 vm_id;
408+
409+ /** @num_binds: number of binds in this IOCTL. */
410+ __u32 num_binds;
411+
412+ /**
413+ * @stride: Stride in bytes between consecutive binds. This allows
414+ * extensibility of drm_asahi_gem_bind_op.
415+ */
416+ __u32 stride;
417+
418+ /** @pad: MBZ */
419+ __u32 pad;
420+
421+ /**
422+ * @userptr: User pointer to an array of @num_binds structures of type
423+ * @drm_asahi_gem_bind_op and size @stride bytes.
424+ */
425+ __u64 userptr;
426+};
427+
428+/**
429+ * enum drm_asahi_bind_object_op - Special object bind operation
430+ */
431+enum drm_asahi_bind_object_op {
432+ /** @DRM_ASAHI_BIND_OBJECT_OP_BIND: Bind a BO as a special GPU object */
433+ DRM_ASAHI_BIND_OBJECT_OP_BIND = 0,
434+
435+ /** @DRM_ASAHI_BIND_OBJECT_OP_UNBIND: Unbind a special GPU object */
436+ DRM_ASAHI_BIND_OBJECT_OP_UNBIND = 1,
437+};
438+
439+/**
440+ * enum drm_asahi_bind_object_flags - Special object bind flags
441+ */
442+enum drm_asahi_bind_object_flags {
443+ /**
444+ * @DRM_ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS: Map a BO as a timestamp
445+ * buffer.
446+ */
447+ DRM_ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS = (1L << 0),
448+};
449+
450+/**
451+ * struct drm_asahi_gem_bind_object - Arguments passed to
452+ * DRM_IOCTL_ASAHI_GEM_BIND_OBJECT
453+ */
454+struct drm_asahi_gem_bind_object {
455+ /** @op: Bind operation (enum drm_asahi_bind_object_op) */
456+ __u32 op;
457+
458+ /** @flags: Combination of drm_asahi_bind_object_flags flags. */
459+ __u32 flags;
460+
461+ /** @handle: GEM object to bind/unbind (BIND) */
462+ __u32 handle;
463+
464+ /** @vm_id: The ID of the VM to operate on (MBZ currently) */
465+ __u32 vm_id;
466+
467+ /** @offset: Offset into the object (BIND only) */
468+ __u64 offset;
469+
470+ /** @range: Number of bytes to bind/unbind (BIND only) */
471+ __u64 range;
472+
473+ /** @object_handle: Object handle (out for BIND, in for UNBIND) */
474+ __u32 object_handle;
475+
476+ /** @pad: MBZ */
477+ __u32 pad;
478+};
479+
480+/**
481+ * enum drm_asahi_cmd_type - Command type
482+ */
483+enum drm_asahi_cmd_type {
484+ /**
485+ * @DRM_ASAHI_CMD_RENDER: Render command, executing on the render
486+ * subqueue. Combined vertex and fragment operation.
487+ *
488+ * Followed by a @drm_asahi_cmd_render payload.
489+ */
490+ DRM_ASAHI_CMD_RENDER = 0,
491+
492+ /**
493+ * @DRM_ASAHI_CMD_COMPUTE: Compute command on the compute subqueue.
494+ *
495+ * Followed by a @drm_asahi_cmd_compute payload.
496+ */
497+ DRM_ASAHI_CMD_COMPUTE = 1,
498+
499+ /**
500+ * @DRM_ASAHI_SET_VERTEX_ATTACHMENTS: Software command to set
501+ * attachments for subsequent vertex shaders in the same submit.
502+ *
503+ * Followed by (possibly multiple) @drm_asahi_attachment payloads.
504+ */
505+ DRM_ASAHI_SET_VERTEX_ATTACHMENTS = 2,
506+
507+ /**
508+ * @DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS: Software command to set
509+ * attachments for subsequent fragment shaders in the same submit.
510+ *
511+ * Followed by (possibly multiple) @drm_asahi_attachment payloads.
512+ */
513+ DRM_ASAHI_SET_FRAGMENT_ATTACHMENTS = 3,
514+
515+ /**
516+ * @DRM_ASAHI_SET_COMPUTE_ATTACHMENTS: Software command to set
517+ * attachments for subsequent compute shaders in the same submit.
518+ *
519+ * Followed by (possibly multiple) @drm_asahi_attachment payloads.
520+ */
521+ DRM_ASAHI_SET_COMPUTE_ATTACHMENTS = 4,
522+};
523+
524+/**
525+ * enum drm_asahi_priority - Scheduling queue priority.
526+ *
527+ * These priorities are forwarded to the firmware to influence firmware
528+ * scheduling. The exact policy is ultimately decided by firmware, but
529+ * these enums allow userspace to communicate the intentions.
530+ */
531+enum drm_asahi_priority {
532+ /** @DRM_ASAHI_PRIORITY_LOW: Low priority queue. */
533+ DRM_ASAHI_PRIORITY_LOW = 0,
534+
535+ /** @DRM_ASAHI_PRIORITY_MEDIUM: Medium priority queue. */
536+ DRM_ASAHI_PRIORITY_MEDIUM = 1,
537+
538+ /**
539+ * @DRM_ASAHI_PRIORITY_HIGH: High priority queue.
540+ *
541+ * Reserved for future extension.
542+ */
543+ DRM_ASAHI_PRIORITY_HIGH = 2,
544+
545+ /**
546+ * @DRM_ASAHI_PRIORITY_REALTIME: Real-time priority queue.
547+ *
548+ * Reserved for future extension.
549+ */
550+ DRM_ASAHI_PRIORITY_REALTIME = 3,
551+};
552+
553+/**
554+ * struct drm_asahi_queue_create - Arguments passed to
555+ * DRM_IOCTL_ASAHI_QUEUE_CREATE
556+ */
557+struct drm_asahi_queue_create {
558+ /** @flags: MBZ */
559+ __u32 flags;
560+
561+ /** @vm_id: The ID of the VM this queue is bound to */
562+ __u32 vm_id;
563+
564+ /** @priority: One of drm_asahi_priority */
565+ __u32 priority;
566+
567+ /** @queue_id: The returned queue ID */
568+ __u32 queue_id;
569+
570+ /**
571+ * @usc_exec_base: GPU base address for all USC binaries (shaders) on
572+ * this queue. USC addresses are 32-bit relative to this 64-bit base.
573+ *
574+ * This sets the following registers on all queue commands:
575+ *
576+ * USC_EXEC_BASE_TA (vertex)
577+ * USC_EXEC_BASE_ISP (fragment)
578+ * USC_EXEC_BASE_CP (compute)
579+ *
580+ * While the hardware lets us configure these independently per command,
581+ * we do not have a use case for this. Instead, we expect userspace to
582+ * fix a 4GiB VA carveout for USC memory and pass its base address here.
583+ */
584+ __u64 usc_exec_base;
585+};
586+
587+/**
588+ * struct drm_asahi_queue_destroy - Arguments passed to
589+ * DRM_IOCTL_ASAHI_QUEUE_DESTROY
590+ */
591+struct drm_asahi_queue_destroy {
592+ /** @queue_id: The queue ID to be destroyed */
593+ __u32 queue_id;
594+
595+ /** @pad: MBZ */
596+ __u32 pad;
597+};
598+
599+/**
600+ * enum drm_asahi_sync_type - Sync item type
601+ */
602+enum drm_asahi_sync_type {
603+ /** @DRM_ASAHI_SYNC_SYNCOBJ: Binary sync object */
604+ DRM_ASAHI_SYNC_SYNCOBJ = 0,
605+
606+ /** @DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ: Timeline sync object */
607+ DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ = 1,
608+};
609+
610+/**
611+ * struct drm_asahi_sync - Sync item
612+ */
613+struct drm_asahi_sync {
614+ /** @sync_type: One of drm_asahi_sync_type */
615+ __u32 sync_type;
616+
617+ /** @handle: The sync object handle */
618+ __u32 handle;
619+
620+ /** @timeline_value: Timeline value for timeline sync objects */
621+ __u64 timeline_value;
622+};
623+
624+/**
625+ * define DRM_ASAHI_BARRIER_NONE - Command index for no barrier
626+ *
627+ * This special value may be passed in to drm_asahi_command::vdm_barrier or
628+ * drm_asahi_command::cdm_barrier to indicate that the respective subqueue
629+ * should not wait on any previous work.
630+ */
631+#define DRM_ASAHI_BARRIER_NONE (0xFFFFu)
632+
633+/**
634+ * struct drm_asahi_cmd_header - Top level command structure
635+ *
636+ * This struct is core to the command buffer definition and therefore is not
637+ * extensible.
638+ */
639+struct drm_asahi_cmd_header {
640+ /** @cmd_type: One of drm_asahi_cmd_type */
641+ __u16 cmd_type;
642+
643+ /**
644+ * @size: Size of this command, not including this header.
645+ *
646+ * For hardware commands, this enables extensibility of commands without
647+ * requiring extra command types. Passing a command that is shorter
648+ * than expected is explicitly allowed for backwards-compatibility.
649+ * Truncated fields will be zeroed.
650+ *
651+ * For the synthetic attachment setting commands, this implicitly
652+ * encodes the number of attachments. These commands take multiple
653+ * fixed-size @drm_asahi_attachment structures as their payload, so size
654+ * equals number of attachments * sizeof(struct drm_asahi_attachment).
655+ */
656+ __u16 size;
657+
658+ /**
659+ * @vdm_barrier: VDM (render) command index to wait on.
660+ *
661+ * Barriers are indices relative to the beginning of a given submit. A
662+ * barrier of 0 waits on commands submitted to the respective subqueue
663+ * in previous submit ioctls. A barrier of N waits on N previous
664+ * commands on the subqueue within the current submit ioctl. As a
665+ * special case, passing @DRM_ASAHI_BARRIER_NONE avoids waiting on any
666+ * commands in the subqueue.
667+ *
668+ * Examples:
669+ *
670+ * 0: This waits on all previous work.
671+ *
672+ * NONE: This does not wait for anything on this subqueue.
673+ *
674+ * 1: This waits on the first render command in the submit.
675+ * This is valid only if there are multiple render commands in the
676+ * same submit.
677+ *
678+ * Barriers are valid only for hardware commands. Synthetic software
679+ * commands to set attachments must pass NONE here.
680+ */
681+ __u16 vdm_barrier;
682+
683+ /**
684+ * @cdm_barrier: CDM (compute) command index to wait on.
685+ *
686+ * See @vdm_barrier, and replace VDM/render with CDM/compute.
687+ */
688+ __u16 cdm_barrier;
689+};
690+
691+/**
692+ * struct drm_asahi_submit - Arguments passed to DRM_IOCTL_ASAHI_SUBMIT
693+ */
694+struct drm_asahi_submit {
695+ /**
696+ * @syncs: An optional pointer to an array of drm_asahi_sync. The first
697+ * @in_sync_count elements are in-syncs, then the remaining
698+ * @out_sync_count elements are out-syncs. Using a single array with
699+ * explicit partitioning simplifies handling.
700+ */
701+ __u64 syncs;
702+
703+ /**
704+ * @cmdbuf: Pointer to the command buffer to submit.
705+ *
706+ * This is a flat command buffer. By design, it contains no CPU
707+ * pointers, which makes it suitable for a virtgpu wire protocol without
708+ * requiring any serializing/deserializing step.
709+ *
710+ * It consists of a series of commands. Each command begins with a
711+ * fixed-size @drm_asahi_cmd_header header and is followed by a
712+ * variable-length payload according to the type and size in the header.
713+ *
714+ * The combined count of "real" hardware commands must be nonzero and at
715+ * most drm_asahi_params_global::max_commands_per_submission.
716+ */
717+ __u64 cmdbuf;
718+
719+ /** @flags: Flags for command submission (MBZ) */
720+ __u32 flags;
721+
722+ /** @queue_id: The queue ID to be submitted to */
723+ __u32 queue_id;
724+
725+ /**
726+ * @in_sync_count: Number of sync objects to wait on before starting
727+ * this job.
728+ */
729+ __u32 in_sync_count;
730+
731+ /**
732+ * @out_sync_count: Number of sync objects to signal upon completion of
733+ * this job.
734+ */
735+ __u32 out_sync_count;
736+
737+ /** @cmdbuf_size: Command buffer size in bytes */
738+ __u32 cmdbuf_size;
739+
740+ /** @pad: MBZ */
741+ __u32 pad;
742+};
743+
744+/**
745+ * struct drm_asahi_attachment - Describe an "attachment".
746+ *
747+ * Attachments are any memory written by shaders, notably including render
748+ * target attachments written by the end-of-tile program. This is purely a hint
749+ * about the accessed memory regions. It is optional to specify, which is
750+ * fortunate as it cannot be specified precisely with bindless access anyway.
751+ * But where possible, it's probably a good idea for userspace to include these
752+ * hints, forwarded to the firmware.
753+ *
754+ * This struct is implicitly sized and therefore is not extensible.
755+ */
756+struct drm_asahi_attachment {
757+ /** @pointer: Base address of the attachment */
758+ __u64 pointer;
759+
760+ /** @size: Size of the attachment in bytes */
761+ __u64 size;
762+
763+ /** @pad: MBZ */
764+ __u32 pad;
765+
766+ /** @flags: MBZ */
767+ __u32 flags;
768+};
769+
770+enum drm_asahi_render_flags {
771+ /**
772+ * @DRM_ASAHI_RENDER_VERTEX_SCRATCH: A vertex stage shader uses scratch
773+ * memory.
774+ */
775+ DRM_ASAHI_RENDER_VERTEX_SCRATCH = (1U << 0),
776+
777+ /**
778+ * @DRM_ASAHI_RENDER_PROCESS_EMPTY_TILES: Process even empty tiles.
779+ * This must be set when clearing render targets.
780+ */
781+ DRM_ASAHI_RENDER_PROCESS_EMPTY_TILES = (1U << 1),
782+
783+ /**
784+ * @DRM_ASAHI_RENDER_NO_VERTEX_CLUSTERING: Run vertex stage on a single
785+ * cluster (on multi-cluster GPUs)
786+ *
787+ * This harms performance but can workaround certain sync/coherency
788+ * bugs, and therefore is useful for debugging.
789+ */
790+ DRM_ASAHI_RENDER_NO_VERTEX_CLUSTERING = (1U << 2),
791+
792+ /**
793+ * @DRM_ASAHI_RENDER_DBIAS_IS_INT: Use integer depth bias formula.
794+ *
795+ * Graphics specifications contain two alternate formulas for depth
796+ * bias, a float formula used with floating-point depth buffers and an
797+ * integer formula using with unorm depth buffers. This flag specifies
798+ * that the integer formula should be used. If omitted, the float
799+ * formula is used instead.
800+ *
801+ * This corresponds to bit 18 of the relevant hardware control register,
802+ * so we match that here for efficiency.
803+ */
804+ DRM_ASAHI_RENDER_DBIAS_IS_INT = (1U << 18),
805+};
806+
807+/**
808+ * struct drm_asahi_zls_buffer - Describe a depth or stencil buffer.
809+ *
810+ * These fields correspond to hardware registers in the ZLS (Z Load/Store) unit.
811+ * There are three hardware registers for each field respectively for loads,
812+ * stores, and partial renders. In practice, it makes sense to set all to the
813+ * same values, except in exceptional cases not yet implemented in userspace, so
814+ * we do not duplicate here for simplicity/efficiency.
815+ *
816+ * This struct is embedded in other structs and therefore is not extensible.
817+ */
818+struct drm_asahi_zls_buffer {
819+ /** @base: Base address of the buffer */
820+ __u64 base;
821+
822+ /**
823+ * @comp_base: If the load buffer is compressed, address of the
824+ * compression metadata section.
825+ */
826+ __u64 comp_base;
827+
828+ /**
829+ * @stride: If layered rendering is enabled, the number of bytes
830+ * between each layer of the buffer.
831+ */
832+ __u32 stride;
833+
834+ /**
835+ * @comp_stride: If layered rendering is enabled, the number of bytes
836+ * between each layer of the compression metadata.
837+ */
838+ __u32 comp_stride;
839+};
840+
841+/**
842+ * struct drm_asahi_timestamp - Describe a timestamp write.
843+ *
844+ * The firmware can optionally write the GPU timestamp at render pass
845+ * granularities, but it needs to be mapped specially via
846+ * DRM_IOCTL_ASAHI_GEM_BIND_OBJECT. This structure therefore describes where to
847+ * write as a handle-offset pair, rather than a GPU address like normal.
848+ *
849+ * This struct is embedded in other structs and therefore is not extensible.
850+ */
851+struct drm_asahi_timestamp {
852+ /**
853+ * @handle: Handle of the timestamp buffer, or 0 to skip this
854+ * timestamp. If nonzero, this must equal the value returned in
855+ * drm_asahi_gem_bind_object::object_handle.
856+ */
857+ __u32 handle;
858+
859+ /** @offset: Offset to write into the timestamp buffer */
860+ __u32 offset;
861+};
862+
863+/**
864+ * struct drm_asahi_timestamps - Describe timestamp writes.
865+ *
866+ * Each operation that can be timestamped, can be timestamped at the start and
867+ * end. Therefore, drm_asahi_timestamp structs always come in pairs, bundled
868+ * together into drm_asahi_timestamps.
869+ *
870+ * This struct is embedded in other structs and therefore is not extensible.
871+ */
872+struct drm_asahi_timestamps {
873+ /** @start: Timestamp recorded at the start of the operation */
874+ struct drm_asahi_timestamp start;
875+
876+ /** @end: Timestamp recorded at the end of the operation */
877+ struct drm_asahi_timestamp end;
878+};
879+
880+/**
881+ * struct drm_asahi_helper_program - Describe helper program configuration.
882+ *
883+ * The helper program is a compute-like kernel required for various hardware
884+ * functionality. Its most important role is dynamically allocating
885+ * scratch/stack memory for individual subgroups, by partitioning a static
886+ * allocation shared for the whole device. It is supplied by userspace via
887+ * drm_asahi_helper_program and internally dispatched by the hardware as needed.
888+ *
889+ * This struct is embedded in other structs and therefore is not extensible.
890+ */
891+struct drm_asahi_helper_program {
892+ /**
893+ * @binary: USC address to the helper program binary. This is a tagged
894+ * pointer with configuration in the bottom bits.
895+ */
896+ __u32 binary;
897+
898+ /** @cfg: Additional configuration bits for the helper program. */
899+ __u32 cfg;
900+
901+ /**
902+ * @data: Data passed to the helper program. This value is not
903+ * interpreted by the kernel, firmware, or hardware in any way. It is
904+ * simply a sideband for userspace, set with the submit ioctl and read
905+ * via special registers inside the helper program.
906+ *
907+ * In practice, userspace will pass a 64-bit GPU VA here pointing to the
908+ * actual arguments, which presumably don't fit in 64-bits.
909+ */
910+ __u64 data;
911+};
912+
913+/**
914+ * struct drm_asahi_bg_eot - Describe a background or end-of-tile program.
915+ *
916+ * The background and end-of-tile programs are dispatched by the hardware at the
917+ * beginning and end of rendering. As the hardware "tilebuffer" is simply local
918+ * memory, these programs are necessary to implement API-level render targets.
919+ * The fragment-like background program is responsible for loading either the
920+ * clear colour or the existing render target contents, while the compute-like
921+ * end-of-tile program stores the tilebuffer contents to memory.
922+ *
923+ * This struct is embedded in other structs and therefore is not extensible.
924+ */
925+struct drm_asahi_bg_eot {
926+ /**
927+ * @usc: USC address of the hardware USC words binding resources
928+ * (including images and uniforms) and the program itself. Note this is
929+ * an additional layer of indirection compared to the helper program,
930+ * avoiding the need for a sideband for data. This is a tagged pointer
931+ * with additional configuration in the bottom bits.
932+ */
933+ __u32 usc;
934+
935+ /**
936+ * @rsrc_spec: Resource specifier for the program. This is a packed
937+ * hardware data structure describing the required number of registers,
938+ * uniforms, bound textures, and bound samplers.
939+ */
940+ __u32 rsrc_spec;
941+};
942+
943+/**
944+ * struct drm_asahi_cmd_render - Command to submit 3D
945+ *
946+ * This command submits a single render pass. The hardware control stream may
947+ * include many draws and subpasses, but within the command, the framebuffer
948+ * dimensions and attachments are fixed.
949+ *
950+ * The hardware requires the firmware to set a large number of Control Registers
951+ * setting up state at render pass granularity before each command rendering 3D.
952+ * The firmware bundles this state into data structures. Unfortunately, we
953+ * cannot expose either any of that directly to userspace, because the
954+ * kernel-firmware ABI is not stable. Although we can guarantee the firmware
955+ * updates in tandem with the kernel, we cannot break old userspace when
956+ * upgrading the firmware and kernel. Therefore, we need to abstract well the
957+ * data structures to avoid tying our hands with future firmwares.
958+ *
959+ * The bulk of drm_asahi_cmd_render therefore consists of values of hardware
960+ * control registers, marshalled via the firmware interface.
961+ *
962+ * The framebuffer/tilebuffer dimensions are also specified here. In addition to
963+ * being passed to the firmware/hardware, the kernel requires these dimensions
964+ * to calculate various essential tiling-related data structures. It is
965+ * unfortunate that our submits are heavier than on vendors with saner
966+ * hardware-software interfaces. The upshot is all of this information is
967+ * readily available to userspace with all current APIs.
968+ *
969+ * It looks odd - but it's not overly burdensome and it ensures we can remain
970+ * compatible with old userspace.
971+ */
972+struct drm_asahi_cmd_render {
973+ /** @flags: Combination of drm_asahi_render_flags flags. */
974+ __u32 flags;
975+
976+ /**
977+ * @isp_zls_pixels: ISP_ZLS_PIXELS register value. This contains the
978+ * depth/stencil width/height, which may differ from the framebuffer
979+ * width/height.
980+ */
981+ __u32 isp_zls_pixels;
982+
983+ /**
984+ * @vdm_ctrl_stream_base: VDM_CTRL_STREAM_BASE register value. GPU
985+ * address to the beginning of the VDM control stream.
986+ */
987+ __u64 vdm_ctrl_stream_base;
988+
989+ /** @vertex_helper: Helper program used for the vertex shader */
990+ struct drm_asahi_helper_program vertex_helper;
991+
992+ /** @fragment_helper: Helper program used for the fragment shader */
993+ struct drm_asahi_helper_program fragment_helper;
994+
995+ /**
996+ * @isp_scissor_base: ISP_SCISSOR_BASE register value. GPU address of an
997+ * array of scissor descriptors indexed in the render pass.
998+ */
999+ __u64 isp_scissor_base;
1000+
1001+ /**
1002+ * @isp_dbias_base: ISP_DBIAS_BASE register value. GPU address of an
1003+ * array of depth bias values indexed in the render pass.
1004+ */
1005+ __u64 isp_dbias_base;
1006+
1007+ /**
1008+ * @isp_oclqry_base: ISP_OCLQRY_BASE register value. GPU address of an
1009+ * array of occlusion query results written by the render pass.
1010+ */
1011+ __u64 isp_oclqry_base;
1012+
1013+ /** @depth: Depth buffer */
1014+ struct drm_asahi_zls_buffer depth;
1015+
1016+ /** @stencil: Stencil buffer */
1017+ struct drm_asahi_zls_buffer stencil;
1018+
1019+ /** @zls_ctrl: ZLS_CTRL register value */
1020+ __u64 zls_ctrl;
1021+
1022+ /** @ppp_multisamplectl: PPP_MULTISAMPLECTL register value */
1023+ __u64 ppp_multisamplectl;
1024+
1025+ /**
1026+ * @sampler_heap: Base address of the sampler heap. This heap is used
1027+ * for both vertex shaders and fragment shaders. The registers are
1028+ * per-stage, but there is no known use case for separate heaps.
1029+ */
1030+ __u64 sampler_heap;
1031+
1032+ /** @ppp_ctrl: PPP_CTRL register value */
1033+ __u32 ppp_ctrl;
1034+
1035+ /** @width_px: Framebuffer width in pixels */
1036+ __u16 width_px;
1037+
1038+ /** @height_px: Framebuffer height in pixels */
1039+ __u16 height_px;
1040+
1041+ /** @layers: Number of layers in the framebuffer */
1042+ __u16 layers;
1043+
1044+ /** @sampler_count: Number of samplers in the sampler heap. */
1045+ __u16 sampler_count;
1046+
1047+ /** @utile_width_px: Width of a logical tilebuffer tile in pixels */
1048+ __u8 utile_width_px;
1049+
1050+ /** @utile_height_px: Height of a logical tilebuffer tile in pixels */
1051+ __u8 utile_height_px;
1052+
1053+ /** @samples: # of samples in the framebuffer. Must be 1, 2, or 4. */
1054+ __u8 samples;
1055+
1056+ /** @sample_size_B: # of bytes in the tilebuffer required per sample. */
1057+ __u8 sample_size_B;
1058+
1059+ /**
1060+ * @isp_merge_upper_x: 32-bit float used in the hardware triangle
1061+ * merging. Calculate as: tan(60 deg) * width.
1062+ *
1063+ * Making these values UAPI avoids requiring floating-point calculations
1064+ * in the kernel in the hot path.
1065+ */
1066+ __u32 isp_merge_upper_x;
1067+
1068+ /**
1069+ * @isp_merge_upper_y: 32-bit float. Calculate as: tan(60 deg) * height.
1070+ * See @isp_merge_upper_x.
1071+ */
1072+ __u32 isp_merge_upper_y;
1073+
1074+ /** @bg: Background program run for each tile at the start */
1075+ struct drm_asahi_bg_eot bg;
1076+
1077+ /** @eot: End-of-tile program ran for each tile at the end */
1078+ struct drm_asahi_bg_eot eot;
1079+
1080+ /**
1081+ * @partial_bg: Background program ran at the start of each tile when
1082+ * resuming the render pass during a partial render.
1083+ */
1084+ struct drm_asahi_bg_eot partial_bg;
1085+
1086+ /**
1087+ * @partial_eot: End-of-tile program ran at the end of each tile when
1088+ * pausing the render pass during a partial render.
1089+ */
1090+ struct drm_asahi_bg_eot partial_eot;
1091+
1092+ /**
1093+ * @isp_bgobjdepth: ISP_BGOBJDEPTH register value. This is the depth
1094+ * buffer clear value, encoded in the depth buffer's format: either a
1095+ * 32-bit float or a 16-bit unorm (with upper bits zeroed).
1096+ */
1097+ __u32 isp_bgobjdepth;
1098+
1099+ /**
1100+ * @isp_bgobjvals: ISP_BGOBJVALS register value. The bottom 8-bits
1101+ * contain the stencil buffer clear value.
1102+ */
1103+ __u32 isp_bgobjvals;
1104+
1105+ /** @ts_vtx: Timestamps for the vertex portion of the render */
1106+ struct drm_asahi_timestamps ts_vtx;
1107+
1108+ /** @ts_frag: Timestamps for the fragment portion of the render */
1109+ struct drm_asahi_timestamps ts_frag;
1110+};
1111+
1112+/**
1113+ * struct drm_asahi_cmd_compute - Command to submit compute
1114+ *
1115+ * This command submits a control stream consisting of compute dispatches. There
1116+ * is essentially no limit on how many compute dispatches may be included in a
1117+ * single compute command, although timestamps are at command granularity.
1118+ */
1119+struct drm_asahi_cmd_compute {
1120+ /** @flags: MBZ */
1121+ __u32 flags;
1122+
1123+ /** @sampler_count: Number of samplers in the sampler heap. */
1124+ __u32 sampler_count;
1125+
1126+ /**
1127+ * @cdm_ctrl_stream_base: CDM_CTRL_STREAM_BASE register value. GPU
1128+ * address to the beginning of the CDM control stream.
1129+ */
1130+ __u64 cdm_ctrl_stream_base;
1131+
1132+ /**
1133+ * @cdm_ctrl_stream_end: GPU base address to the end of the hardware
1134+ * control stream. Note this only considers the first contiguous segment
1135+ * of the control stream, as the stream might jump elsewhere.
1136+ */
1137+ __u64 cdm_ctrl_stream_end;
1138+
1139+ /** @sampler_heap: Base address of the sampler heap. */
1140+ __u64 sampler_heap;
1141+
1142+ /** @helper: Helper program used for this compute command */
1143+ struct drm_asahi_helper_program helper;
1144+
1145+ /** @ts: Timestamps for the compute command */
1146+ struct drm_asahi_timestamps ts;
1147+};
1148+
1149+/**
1150+ * struct drm_asahi_get_time - Arguments passed to DRM_IOCTL_ASAHI_GET_TIME
1151+ */
1152+struct drm_asahi_get_time {
1153+ /** @flags: MBZ. */
1154+ __u64 flags;
1155+
1156+ /** @gpu_timestamp: On return, the GPU timestamp in nanoseconds. */
1157+ __u64 gpu_timestamp;
1158+};
1159+
1160+/**
1161+ * DRM_IOCTL_ASAHI() - Build an Asahi IOCTL number
1162+ * @__access: Access type. Must be R, W or RW.
1163+ * @__id: One of the DRM_ASAHI_xxx id.
1164+ * @__type: Suffix of the type being passed to the IOCTL.
1165+ *
1166+ * Don't use this macro directly, use the DRM_IOCTL_ASAHI_xxx
1167+ * values instead.
1168+ *
1169+ * Return: An IOCTL number to be passed to ioctl() from userspace.
1170+ */
1171+#define DRM_IOCTL_ASAHI(__access, __id, __type) \
1172+ DRM_IO ## __access(DRM_COMMAND_BASE + DRM_ASAHI_ ## __id, \
1173+ struct drm_asahi_ ## __type)
1174+
1175+/* Note: this is an enum so that it can be resolved by Rust bindgen. */
1176+enum {
1177+ DRM_IOCTL_ASAHI_GET_PARAMS = DRM_IOCTL_ASAHI(W, GET_PARAMS, get_params),
1178+ DRM_IOCTL_ASAHI_GET_TIME = DRM_IOCTL_ASAHI(WR, GET_TIME, get_time),
1179+ DRM_IOCTL_ASAHI_VM_CREATE = DRM_IOCTL_ASAHI(WR, VM_CREATE, vm_create),
1180+ DRM_IOCTL_ASAHI_VM_DESTROY = DRM_IOCTL_ASAHI(W, VM_DESTROY, vm_destroy),
1181+ DRM_IOCTL_ASAHI_VM_BIND = DRM_IOCTL_ASAHI(W, VM_BIND, vm_bind),
1182+ DRM_IOCTL_ASAHI_GEM_CREATE = DRM_IOCTL_ASAHI(WR, GEM_CREATE, gem_create),
1183+ DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET = DRM_IOCTL_ASAHI(WR, GEM_MMAP_OFFSET, gem_mmap_offset),
1184+ DRM_IOCTL_ASAHI_GEM_BIND_OBJECT = DRM_IOCTL_ASAHI(WR, GEM_BIND_OBJECT, gem_bind_object),
1185+ DRM_IOCTL_ASAHI_QUEUE_CREATE = DRM_IOCTL_ASAHI(WR, QUEUE_CREATE, queue_create),
1186+ DRM_IOCTL_ASAHI_QUEUE_DESTROY = DRM_IOCTL_ASAHI(W, QUEUE_DESTROY, queue_destroy),
1187+ DRM_IOCTL_ASAHI_SUBMIT = DRM_IOCTL_ASAHI(W, SUBMIT, submit),
1188+};
1189+
1190+#if defined(__cplusplus)
1191+}
1192+#endif
1193+
1194+#endif /* _ASAHI_DRM_H_ */
include/uapi/drm/drm.h+4−0
@@ -905,13 +905,17 @@ struct drm_syncobj_destroy { · 904 unmodified lines
905905 };
906906
907907 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
908+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_TIMELINE (1 << 1)
908909 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
910+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_TIMELINE (1 << 1)
909911 struct drm_syncobj_handle {
910912 __u32 handle;
911913 __u32 flags;
912914
913915 __s32 fd;
914916 __u32 pad;
917+
918+ __u64 point;
915919 };
916920
917921 struct drm_syncobj_transfer {
include/uapi/drm/drm_fourcc.h+45−0
@@ -422,6 +422,7 @@ extern "C" { · 421 unmodified lines
422422 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
423423 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
424424 #define DRM_FORMAT_MOD_VENDOR_MTK 0x0b
425+#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c
425426
426427 /* add more to the end as needed */
427428
@@ -1494,6 +1495,50 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1066 unmodified lines
14941495 /* alias for the most common tiling format */
14951496 #define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)
14961497
1498+/*
1499+ * Apple GPU-tiled layouts.
1500+ *
1501+ * Apple GPUs support nonlinear tilings with optional lossless compression.
1502+ *
1503+ * GPU-tiled images are divided into 16KiB tiles:
1504+ *
1505+ * Bytes per pixel Tile size
1506+ * --------------- ---------
1507+ * 1 128x128
1508+ * 2 128x64
1509+ * 4 64x64
1510+ * 8 64x32
1511+ * 16 32x32
1512+ *
1513+ * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1514+ *
1515+ * Compressed images pad the body to 128-bytes and are immediately followed by a
1516+ * metadata section. The metadata section rounds the image dimensions to
1517+ * powers-of-two and contains 8 bytes for each 16x16 compression subtile.
1518+ * Subtiles are interleaved (Morton order).
1519+ *
1520+ * All images are 128-byte aligned.
1521+ *
1522+ * These layouts fundamentally do not have meaningful strides. No matter how we
1523+ * specify strides for these layouts, userspace unaware of Apple image layouts
1524+ * will be unable to use correctly the specified stride for any purpose.
1525+ * Userspace aware of the image layouts do not use strides. The most "correct"
1526+ * convention would be setting the image stride to 0. Unfortunately, some
1527+ * software assumes the stride is at least (width * bytes per pixel). We
1528+ * therefore require that stride equals (width * bytes per pixel). Since the
1529+ * stride is arbitrary here, we pick the simplest convention.
1530+ *
1531+ * Although containing two sections, compressed image layouts are treated in
1532+ * software as a single plane. This is modelled after AFBC, a similar
1533+ * scheme. Attempting to separate the sections to be "explicit" in DRM would
1534+ * only generate more confusion, as software does not treat the image this way.
1535+ *
1536+ * For detailed information on the hardware image layouts, see
1537+ * https://docs.mesa3d.org/drivers/asahi.html#image-layouts
1538+ */
1539+#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
1540+#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)
1541+
14971542 /*
14981543 * AMD modifiers
14991544 *
include/uapi/drm/nova_drm.h+101−0
@@ -0,0 +1,101 @@
1+/* SPDX-License-Identifier: MIT */
2+
3+#ifndef __NOVA_DRM_H__
4+#define __NOVA_DRM_H__
5+
6+#include "drm.h"
7+
8+/* DISCLAIMER: Do not use, this is not a stable uAPI.
9+ *
10+ * This uAPI serves only testing purposes as long as this driver is still in
11+ * development. It is required to implement and test infrastructure which is
12+ * upstreamed in the context of this driver. See also [1].
13+ *
14+ * [1] https://lore.kernel.org/dri-devel/Zfsj0_tb-0-tNrJy@cassiopeiae/T/#u
15+ */
16+
17+#if defined(__cplusplus)
18+extern "C" {
19+#endif
20+
21+/*
22+ * NOVA_GETPARAM_VRAM_BAR_SIZE
23+ *
24+ * Query the VRAM BAR size in bytes.
25+ */
26+#define NOVA_GETPARAM_VRAM_BAR_SIZE 0x1
27+
28+/**
29+ * struct drm_nova_getparam - query GPU and driver metadata
30+ */
31+struct drm_nova_getparam {
32+ /**
33+ * @param: The identifier of the parameter to query.
34+ */
35+ __u64 param;
36+
37+ /**
38+ * @value: The value for the specified parameter.
39+ */
40+ __u64 value;
41+};
42+
43+/**
44+ * struct drm_nova_gem_create - create a new DRM GEM object
45+ */
46+struct drm_nova_gem_create {
47+ /**
48+ * @handle: The handle of the new DRM GEM object.
49+ */
50+ __u32 handle;
51+
52+ /**
53+ * @pad: 32 bit padding, should be 0.
54+ */
55+ __u32 pad;
56+
57+ /**
58+ * @size: The size of the new DRM GEM object.
59+ */
60+ __u64 size;
61+};
62+
63+/**
64+ * struct drm_nova_gem_info - query DRM GEM object metadata
65+ */
66+struct drm_nova_gem_info {
67+ /**
68+ * @handle: The handle of the DRM GEM object to query.
69+ */
70+ __u32 handle;
71+
72+ /**
73+ * @pad: 32 bit padding, should be 0.
74+ */
75+ __u32 pad;
76+
77+ /**
78+ * @size: The size of the DRM GEM obejct.
79+ */
80+ __u64 size;
81+};
82+
83+#define DRM_NOVA_GETPARAM 0x00
84+#define DRM_NOVA_GEM_CREATE 0x01
85+#define DRM_NOVA_GEM_INFO 0x02
86+
87+/* Note: this is an enum so that it can be resolved by Rust bindgen. */
88+enum {
89+ DRM_IOCTL_NOVA_GETPARAM = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GETPARAM,
90+ struct drm_nova_getparam),
91+ DRM_IOCTL_NOVA_GEM_CREATE = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_CREATE,
92+ struct drm_nova_gem_create),
93+ DRM_IOCTL_NOVA_GEM_INFO = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_INFO,
94+ struct drm_nova_gem_info),
95+};
96+
97+#if defined(__cplusplus)
98+}
99+#endif
100+
101+#endif /* __NOVA_DRM_H__ */
include/uapi/drm/panthor_drm.h+23−0
@@ -127,6 +127,9 @@ enum drm_panthor_ioctl_id { · 126 unmodified lines
127127
128128 /** @DRM_PANTHOR_TILER_HEAP_DESTROY: Destroy a tiler heap. */
129129 DRM_PANTHOR_TILER_HEAP_DESTROY,
130+
131+ /** @DRM_PANTHOR_BO_SET_LABEL: Label a BO. */
132+ DRM_PANTHOR_BO_SET_LABEL,
130133 };
131134
132135 /**
@@ -977,6 +980,24 @@ struct drm_panthor_tiler_heap_destroy { · 844 unmodified lines
977980 __u32 pad;
978981 };
979982
983+/**
984+ * struct drm_panthor_bo_set_label - Arguments passed to DRM_IOCTL_PANTHOR_BO_SET_LABEL
985+ */
986+struct drm_panthor_bo_set_label {
987+ /** @handle: Handle of the buffer object to label. */
988+ __u32 handle;
989+
990+ /** @pad: MBZ. */
991+ __u32 pad;
992+
993+ /**
994+ * @label: User pointer to a NUL-terminated string
995+ *
996+ * Length cannot be greater than 4096
997+ */
998+ __u64 label;
999+};
1000+
9801001 /**
9811002 * DRM_IOCTL_PANTHOR() - Build a Panthor IOCTL number
9821003 * @__access: Access type. Must be R, W or RW.
@@ -1019,6 +1040,8 @@ enum { · 36 unmodified lines
10191040 DRM_IOCTL_PANTHOR(WR, TILER_HEAP_CREATE, tiler_heap_create),
10201041 DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROY =
10211042 DRM_IOCTL_PANTHOR(WR, TILER_HEAP_DESTROY, tiler_heap_destroy),
1043+ DRM_IOCTL_PANTHOR_BO_SET_LABEL =
1044+ DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label),
10221045 };
10231046
10241047 #if defined(__cplusplus)
include/uapi/drm/virtgpu_drm.h+6−0
@@ -163,6 +163,12 @@ struct drm_virtgpu_3d_wait { · 162 unmodified lines
163163 __u32 flags;
164164 };
165165
166+#define VIRTGPU_DRM_CAPSET_VIRGL 1
167+#define VIRTGPU_DRM_CAPSET_VIRGL2 2
168+#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
169+#define VIRTGPU_DRM_CAPSET_VENUS 4
170+#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
171+#define VIRTGPU_DRM_CAPSET_DRM 6
166172 struct drm_virtgpu_get_caps {
167173 __u32 cap_set_id;
168174 __u32 cap_set_ver;
include/uapi/drm/xe_drm.h+10−1
@@ -917,7 +917,11 @@ struct drm_xe_gem_mmap_offset { · 916 unmodified lines
917917 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
918918 *
919919 * The @flags can be:
920− * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE
920+ * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
921+ * space of the VM to scratch page. A vm_bind would overwrite the scratch
922+ * page mapping. This flag is mutually exclusive with the
923+ * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and
924+ * xe3 platform.
921925 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
922926 * exec submissions to its exec_queues that don't have an upper time
923927 * limit on the job execution time. But exec submissions to these
@@ -1206,6 +1210,11 @@ struct drm_xe_vm_bind { · 282 unmodified lines
12061210 * there is no need to explicitly set that. When a queue of type
12071211 * %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session
12081212 * (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running.
1213+ * The user is expected to query the PXP status via the query ioctl (see
1214+ * %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before
1215+ * attempting to create a queue with this property. When a queue is created
1216+ * before PXP is ready, the ioctl will return -EBUSY if init is still in
1217+ * progress or -EIO if init failed.
12091218 * Given that going into a power-saving state kills PXP HWDRM sessions,
12101219 * runtime PM will be blocked while queues of this type are alive.
12111220 * All PXP queues will be killed if a PXP invalidation event occurs.
include/uapi/linux/blktrace_api.h+1−1
@@ -49,7 +49,7 @@ enum blktrace_act { · 48 unmodified lines
4949 __BLK_TA_UNPLUG_TIMER, /* queue was unplugged by timer */
5050 __BLK_TA_INSERT, /* insert request */
5151 __BLK_TA_SPLIT, /* bio was split */
52− __BLK_TA_BOUNCE, /* bio was bounced */
52+ __BLK_TA_BOUNCE, /* unused, was: bio was bounced */
5353 __BLK_TA_REMAP, /* bio was remapped */
5454 __BLK_TA_ABORT, /* request aborted */
5555 __BLK_TA_DRV_DATA, /* driver-specific binary data */
include/uapi/linux/bpf.h+14−7
@@ -1506,7 +1506,7 @@ union bpf_attr { · 1505 unmodified lines
15061506 __s32 map_token_fd;
15071507 };
15081508
1509− struct { /* anonymous struct used by BPF_MAP_*_ELEM commands */
1509+ struct { /* anonymous struct used by BPF_MAP_*_ELEM and BPF_MAP_FREEZE commands */
15101510 __u32 map_fd;
15111511 __aligned_u64 key;
15121512 union {
@@ -1995,11 +1995,15 @@ union bpf_attr { · 482 unmodified lines
19951995 * long bpf_skb_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len, u64 flags)
19961996 * Description
19971997 * Store *len* bytes from address *from* into the packet
1998− * associated to *skb*, at *offset*. *flags* are a combination of
1999− * **BPF_F_RECOMPUTE_CSUM** (automatically recompute the
2000− * checksum for the packet after storing the bytes) and
2001− * **BPF_F_INVALIDATE_HASH** (set *skb*\ **->hash**, *skb*\
2002− * **->swhash** and *skb*\ **->l4hash** to 0).
1998+ * associated to *skb*, at *offset*. The *flags* are a combination
1999+ * of the following values:
2000+ *
2001+ * **BPF_F_RECOMPUTE_CSUM**
2002+ * Automatically update *skb*\ **->csum** after storing the
2003+ * bytes.
2004+ * **BPF_F_INVALIDATE_HASH**
2005+ * Set *skb*\ **->hash**, *skb*\ **->swhash** and *skb*\
2006+ * **->l4hash** to 0.
20032007 *
20042008 * A call to this helper is susceptible to change the underlying
20052009 * packet buffer. Therefore, at load time, all checks on pointers
@@ -2051,7 +2055,8 @@ union bpf_attr { · 45 unmodified lines
20512055 * untouched (unless **BPF_F_MARK_ENFORCE** is added as well), and
20522056 * for updates resulting in a null checksum the value is set to
20532057 * **CSUM_MANGLED_0** instead. Flag **BPF_F_PSEUDO_HDR** indicates
2054− * the checksum is to be computed against a pseudo-header.
2058+ * that the modified header field is part of the pseudo-header.
2059+ * Flag **BPF_F_IPV6** should be set for IPv6 packets.
20552060 *
20562061 * This helper works in combination with **bpf_csum_diff**\ (),
20572062 * which does not update the checksum in-place, but offers more
@@ -6068,6 +6073,7 @@ enum { · 4010 unmodified lines
60686073 BPF_F_PSEUDO_HDR = (1ULL << 4),
60696074 BPF_F_MARK_MANGLED_0 = (1ULL << 5),
60706075 BPF_F_MARK_ENFORCE = (1ULL << 6),
6076+ BPF_F_IPV6 = (1ULL << 7),
60716077 };
60726078
60736079 /* BPF_FUNC_skb_set_tunnel_key and BPF_FUNC_skb_get_tunnel_key flags. */
@@ -6723,6 +6729,7 @@ struct bpf_link_info { · 649 unmodified lines
67236729 __u32 name_len;
67246730 __u32 offset; /* offset from file_name */
67256731 __u64 cookie;
6732+ __u64 ref_ctr_offset;
67266733 } uprobe; /* BPF_PERF_EVENT_UPROBE, BPF_PERF_EVENT_URETPROBE */
67276734 struct {
67286735 __aligned_u64 func_name; /* in/out */
include/uapi/linux/cec-funcs.h+20−20
@@ -14,7 +14,7 @@ · 13 unmodified lines
1414 static inline void cec_msg_active_source(struct cec_msg *msg, __u16 phys_addr)
1515 {
1616 msg->len = 4;
17− msg->msg[0] |= 0xf; /* broadcast */
17+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
1818 msg->msg[1] = CEC_MSG_ACTIVE_SOURCE;
1919 msg->msg[2] = phys_addr >> 8;
2020 msg->msg[3] = phys_addr & 0xff;
@@ -59,7 +59,7 @@ static inline void cec_msg_request_active_source(struct cec_msg *msg, · 38 unmodified lines
5959 int reply)
6060 {
6161 msg->len = 2;
62− msg->msg[0] |= 0xf; /* broadcast */
62+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
6363 msg->msg[1] = CEC_MSG_REQUEST_ACTIVE_SOURCE;
6464 msg->reply = reply ? CEC_MSG_ACTIVE_SOURCE : 0;
6565 }
@@ -68,7 +68,7 @@ static inline void cec_msg_routing_information(struct cec_msg *msg, · 2 unmodified lines
6868 __u16 phys_addr)
6969 {
7070 msg->len = 4;
71− msg->msg[0] |= 0xf; /* broadcast */
71+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
7272 msg->msg[1] = CEC_MSG_ROUTING_INFORMATION;
7373 msg->msg[2] = phys_addr >> 8;
7474 msg->msg[3] = phys_addr & 0xff;
@@ -86,7 +86,7 @@ static inline void cec_msg_routing_change(struct cec_msg *msg, · 11 unmodified lines
8686 __u16 new_phys_addr)
8787 {
8888 msg->len = 6;
89− msg->msg[0] |= 0xf; /* broadcast */
89+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
9090 msg->msg[1] = CEC_MSG_ROUTING_CHANGE;
9191 msg->msg[2] = orig_phys_addr >> 8;
9292 msg->msg[3] = orig_phys_addr & 0xff;
@@ -106,7 +106,7 @@ static inline void cec_ops_routing_change(const struct cec_msg *msg, · 13 unmodified lines
106106 static inline void cec_msg_set_stream_path(struct cec_msg *msg, __u16 phys_addr)
107107 {
108108 msg->len = 4;
109− msg->msg[0] |= 0xf; /* broadcast */
109+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
110110 msg->msg[1] = CEC_MSG_SET_STREAM_PATH;
111111 msg->msg[2] = phys_addr >> 8;
112112 msg->msg[3] = phys_addr & 0xff;
@@ -791,7 +791,7 @@ static inline void cec_msg_report_physical_addr(struct cec_msg *msg, · 678 unmodified lines
791791 __u16 phys_addr, __u8 prim_devtype)
792792 {
793793 msg->len = 5;
794− msg->msg[0] |= 0xf; /* broadcast */
794+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
795795 msg->msg[1] = CEC_MSG_REPORT_PHYSICAL_ADDR;
796796 msg->msg[2] = phys_addr >> 8;
797797 msg->msg[3] = phys_addr & 0xff;
@@ -817,7 +817,7 @@ static inline void cec_msg_set_menu_language(struct cec_msg *msg, · 19 unmodified lines
817817 const char *language)
818818 {
819819 msg->len = 5;
820− msg->msg[0] |= 0xf; /* broadcast */
820+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
821821 msg->msg[1] = CEC_MSG_SET_MENU_LANGUAGE;
822822 memcpy(msg->msg + 2, language, 3);
823823 }
@@ -850,7 +850,7 @@ static inline void cec_msg_report_features(struct cec_msg *msg, · 26 unmodified lines
850850 __u8 rc_profile, __u8 dev_features)
851851 {
852852 msg->len = 6;
853− msg->msg[0] |= 0xf; /* broadcast */
853+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
854854 msg->msg[1] = CEC_MSG_REPORT_FEATURES;
855855 msg->msg[2] = cec_version;
856856 msg->msg[3] = all_device_types;
@@ -1092,7 +1092,7 @@ static inline void cec_msg_tuner_step_increment(struct cec_msg *msg) · 235 unmodified lines
10921092 static inline void cec_msg_device_vendor_id(struct cec_msg *msg, __u32 vendor_id)
10931093 {
10941094 msg->len = 5;
1095− msg->msg[0] |= 0xf; /* broadcast */
1095+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
10961096 msg->msg[1] = CEC_MSG_DEVICE_VENDOR_ID;
10971097 msg->msg[2] = vendor_id >> 16;
10981098 msg->msg[3] = (vendor_id >> 8) & 0xff;
@@ -1655,7 +1655,7 @@ static inline void cec_msg_report_current_latency(struct cec_msg *msg, · 556 unmodified lines
16551655 __u8 audio_out_delay)
16561656 {
16571657 msg->len = 6;
1658− msg->msg[0] |= 0xf; /* broadcast */
1658+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
16591659 msg->msg[1] = CEC_MSG_REPORT_CURRENT_LATENCY;
16601660 msg->msg[2] = phys_addr >> 8;
16611661 msg->msg[3] = phys_addr & 0xff;
@@ -1687,7 +1687,7 @@ static inline void cec_msg_request_current_latency(struct cec_msg *msg, · 25 unmodified lines
16871687 __u16 phys_addr)
16881688 {
16891689 msg->len = 4;
1690− msg->msg[0] |= 0xf; /* broadcast */
1690+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
16911691 msg->msg[1] = CEC_MSG_REQUEST_CURRENT_LATENCY;
16921692 msg->msg[2] = phys_addr >> 8;
16931693 msg->msg[3] = phys_addr & 0xff;
@@ -1707,7 +1707,7 @@ static inline void cec_msg_cdc_hec_inquire_state(struct cec_msg *msg, · 13 unmodified lines
17071707 __u16 phys_addr2)
17081708 {
17091709 msg->len = 9;
1710− msg->msg[0] |= 0xf; /* broadcast */
1710+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
17111711 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
17121712 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
17131713 msg->msg[4] = CEC_MSG_CDC_HEC_INQUIRE_STATE;
@@ -1737,7 +1737,7 @@ static inline void cec_msg_cdc_hec_report_state(struct cec_msg *msg, · 23 unmodified lines
17371737 __u16 hec_field)
17381738 {
17391739 msg->len = has_field ? 10 : 8;
1740− msg->msg[0] |= 0xf; /* broadcast */
1740+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
17411741 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
17421742 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
17431743 msg->msg[4] = CEC_MSG_CDC_HEC_REPORT_STATE;
@@ -1782,7 +1782,7 @@ static inline void cec_msg_cdc_hec_set_state(struct cec_msg *msg, · 38 unmodified lines
17821782 __u16 phys_addr5)
17831783 {
17841784 msg->len = 10;
1785− msg->msg[0] |= 0xf; /* broadcast */
1785+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
17861786 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
17871787 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
17881788 msg->msg[4] = CEC_MSG_CDC_HEC_INQUIRE_STATE;
@@ -1832,7 +1832,7 @@ static inline void cec_msg_cdc_hec_set_state_adjacent(struct cec_msg *msg, · 43 unmodified lines
18321832 __u8 hec_set_state)
18331833 {
18341834 msg->len = 8;
1835− msg->msg[0] |= 0xf; /* broadcast */
1835+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
18361836 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
18371837 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
18381838 msg->msg[4] = CEC_MSG_CDC_HEC_SET_STATE_ADJACENT;
@@ -1857,7 +1857,7 @@ static inline void cec_msg_cdc_hec_request_deactivation(struct cec_msg *msg, · 18 unmodified lines
18571857 __u16 phys_addr3)
18581858 {
18591859 msg->len = 11;
1860− msg->msg[0] |= 0xf; /* broadcast */
1860+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
18611861 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
18621862 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
18631863 msg->msg[4] = CEC_MSG_CDC_HEC_REQUEST_DEACTIVATION;
@@ -1884,7 +1884,7 @@ static inline void cec_ops_cdc_hec_request_deactivation(const struct cec_msg *ms · 20 unmodified lines
18841884 static inline void cec_msg_cdc_hec_notify_alive(struct cec_msg *msg)
18851885 {
18861886 msg->len = 5;
1887− msg->msg[0] |= 0xf; /* broadcast */
1887+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
18881888 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
18891889 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
18901890 msg->msg[4] = CEC_MSG_CDC_HEC_NOTIFY_ALIVE;
@@ -1899,7 +1899,7 @@ static inline void cec_ops_cdc_hec_notify_alive(const struct cec_msg *msg, · 8 unmodified lines
18991899 static inline void cec_msg_cdc_hec_discover(struct cec_msg *msg)
19001900 {
19011901 msg->len = 5;
1902− msg->msg[0] |= 0xf; /* broadcast */
1902+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
19031903 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
19041904 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
19051905 msg->msg[4] = CEC_MSG_CDC_HEC_DISCOVER;
@@ -1916,7 +1916,7 @@ static inline void cec_msg_cdc_hpd_set_state(struct cec_msg *msg, · 10 unmodified lines
19161916 __u8 hpd_state)
19171917 {
19181918 msg->len = 6;
1919− msg->msg[0] |= 0xf; /* broadcast */
1919+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
19201920 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
19211921 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
19221922 msg->msg[4] = CEC_MSG_CDC_HPD_SET_STATE;
@@ -1938,7 +1938,7 @@ static inline void cec_msg_cdc_hpd_report_state(struct cec_msg *msg, · 15 unmodified lines
19381938 __u8 hpd_error)
19391939 {
19401940 msg->len = 6;
1941− msg->msg[0] |= 0xf; /* broadcast */
1941+ msg->msg[0] |= CEC_LOG_ADDR_BROADCAST;
19421942 msg->msg[1] = CEC_MSG_CDC_MESSAGE;
19431943 /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */
19441944 msg->msg[4] = CEC_MSG_CDC_HPD_REPORT_STATE;
include/uapi/linux/devlink.h+15−0
@@ -385,6 +385,21 @@ enum devlink_linecard_state { · 384 unmodified lines
385385 DEVLINK_LINECARD_STATE_MAX = __DEVLINK_LINECARD_STATE_MAX - 1
386386 };
387387
388+/* Variable attribute type. */
389+enum devlink_var_attr_type {
390+ /* Following values relate to the internal NLA_* values */
391+ DEVLINK_VAR_ATTR_TYPE_U8 = 1,
392+ DEVLINK_VAR_ATTR_TYPE_U16,
393+ DEVLINK_VAR_ATTR_TYPE_U32,
394+ DEVLINK_VAR_ATTR_TYPE_U64,
395+ DEVLINK_VAR_ATTR_TYPE_STRING,
396+ DEVLINK_VAR_ATTR_TYPE_FLAG,
397+ DEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,
398+ DEVLINK_VAR_ATTR_TYPE_BINARY,
399+ __DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 0x80,
400+ /* Any possible custom types, unrelated to NLA_* values go below */
401+};
402+
388403 enum devlink_attr {
389404 /* don't change the order or add anything between, this is ABI! */
390405 DEVLINK_ATTR_UNSPEC,
include/uapi/linux/dm-ioctl.h+7−2
@@ -258,10 +258,12 @@ enum { · 257 unmodified lines
258258 DM_DEV_SET_GEOMETRY_CMD,
259259 DM_DEV_ARM_POLL_CMD,
260260 DM_GET_TARGET_VERSION_CMD,
261+ DM_MPATH_PROBE_PATHS_CMD,
261262 };
262263
263264 #define DM_IOCTL 0xfd
264265
266+/* Control device ioctls */
265267 #define DM_VERSION _IOWR(DM_IOCTL, DM_VERSION_CMD, struct dm_ioctl)
266268 #define DM_REMOVE_ALL _IOWR(DM_IOCTL, DM_REMOVE_ALL_CMD, struct dm_ioctl)
267269 #define DM_LIST_DEVICES _IOWR(DM_IOCTL, DM_LIST_DEVICES_CMD, struct dm_ioctl)
@@ -285,10 +287,13 @@ enum { · 17 unmodified lines
285287 #define DM_TARGET_MSG _IOWR(DM_IOCTL, DM_TARGET_MSG_CMD, struct dm_ioctl)
286288 #define DM_DEV_SET_GEOMETRY _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)
287289
290+/* Block device ioctls */
291+#define DM_MPATH_PROBE_PATHS _IO(DM_IOCTL, DM_MPATH_PROBE_PATHS_CMD)
292+
288293 #define DM_VERSION_MAJOR 4
289−#define DM_VERSION_MINOR 49
294+#define DM_VERSION_MINOR 50
290295 #define DM_VERSION_PATCHLEVEL 0
291−#define DM_VERSION_EXTRA "-ioctl (2025-01-17)"
296+#define DM_VERSION_EXTRA "-ioctl (2025-04-28)"
292297
293298 /* Status bits */
294299 #define DM_READONLY_FLAG (1 << 0) /* In/Out */
include/uapi/linux/ethtool.h+69−65
@@ -2295,71 +2295,75 @@ static inline int ethtool_validate_duplex(__u8 duplex) · 2294 unmodified lines
22952295 #define RXH_XFRM_SYM_OR_XOR (1 << 1)
22962296 #define RXH_XFRM_NO_CHANGE 0xff
22972297
2298−/* L2-L4 network traffic flow types */
2299−#define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */
2300−#define UDP_V4_FLOW 0x02 /* hash or spec (udp_ip4_spec) */
2301−#define SCTP_V4_FLOW 0x03 /* hash or spec (sctp_ip4_spec) */
2302−#define AH_ESP_V4_FLOW 0x04 /* hash only */
2303−#define TCP_V6_FLOW 0x05 /* hash or spec (tcp_ip6_spec; nfc only) */
2304−#define UDP_V6_FLOW 0x06 /* hash or spec (udp_ip6_spec; nfc only) */
2305−#define SCTP_V6_FLOW 0x07 /* hash or spec (sctp_ip6_spec; nfc only) */
2306−#define AH_ESP_V6_FLOW 0x08 /* hash only */
2307−#define AH_V4_FLOW 0x09 /* hash or spec (ah_ip4_spec) */
2308−#define ESP_V4_FLOW 0x0a /* hash or spec (esp_ip4_spec) */
2309−#define AH_V6_FLOW 0x0b /* hash or spec (ah_ip6_spec; nfc only) */
2310−#define ESP_V6_FLOW 0x0c /* hash or spec (esp_ip6_spec; nfc only) */
2311−#define IPV4_USER_FLOW 0x0d /* spec only (usr_ip4_spec) */
2312−#define IP_USER_FLOW IPV4_USER_FLOW
2313−#define IPV6_USER_FLOW 0x0e /* spec only (usr_ip6_spec; nfc only) */
2314−#define IPV4_FLOW 0x10 /* hash only */
2315−#define IPV6_FLOW 0x11 /* hash only */
2316−#define ETHER_FLOW 0x12 /* spec only (ether_spec) */
2317−
2318−/* Used for GTP-U IPv4 and IPv6.
2319− * The format of GTP packets only includes
2320− * elements such as TEID and GTP version.
2321− * It is primarily intended for data communication of the UE.
2322− */
2323−#define GTPU_V4_FLOW 0x13 /* hash only */
2324−#define GTPU_V6_FLOW 0x14 /* hash only */
2325−
2326−/* Use for GTP-C IPv4 and v6.
2327− * The format of these GTP packets does not include TEID.
2328− * Primarily expected to be used for communication
2329− * to create sessions for UE data communication,
2330− * commonly referred to as CSR (Create Session Request).
2331− */
2332−#define GTPC_V4_FLOW 0x15 /* hash only */
2333−#define GTPC_V6_FLOW 0x16 /* hash only */
2334−
2335−/* Use for GTP-C IPv4 and v6.
2336− * Unlike GTPC_V4_FLOW, the format of these GTP packets includes TEID.
2337− * After session creation, it becomes this packet.
2338− * This is mainly used for requests to realize UE handover.
2339− */
2340−#define GTPC_TEID_V4_FLOW 0x17 /* hash only */
2341−#define GTPC_TEID_V6_FLOW 0x18 /* hash only */
2342−
2343−/* Use for GTP-U and extended headers for the PSC (PDU Session Container).
2344− * The format of these GTP packets includes TEID and QFI.
2345− * In 5G communication using UPF (User Plane Function),
2346− * data communication with this extended header is performed.
2347− */
2348−#define GTPU_EH_V4_FLOW 0x19 /* hash only */
2349−#define GTPU_EH_V6_FLOW 0x1a /* hash only */
2350−
2351−/* Use for GTP-U IPv4 and v6 PSC (PDU Session Container) extended headers.
2352− * This differs from GTPU_EH_V(4|6)_FLOW in that it is distinguished by
2353− * UL/DL included in the PSC.
2354− * There are differences in the data included based on Downlink/Uplink,
2355− * and can be used to distinguish packets.
2356− * The functions described so far are useful when you want to
2357− * handle communication from the mobile network in UPF, PGW, etc.
2358− */
2359−#define GTPU_UL_V4_FLOW 0x1b /* hash only */
2360−#define GTPU_UL_V6_FLOW 0x1c /* hash only */
2361−#define GTPU_DL_V4_FLOW 0x1d /* hash only */
2362−#define GTPU_DL_V6_FLOW 0x1e /* hash only */
2298+enum {
2299+ /* L2-L4 network traffic flow types */
2300+ TCP_V4_FLOW = 0x01, /* hash or spec (tcp_ip4_spec) */
2301+ UDP_V4_FLOW = 0x02, /* hash or spec (udp_ip4_spec) */
2302+ SCTP_V4_FLOW = 0x03, /* hash or spec (sctp_ip4_spec) */
2303+ AH_ESP_V4_FLOW = 0x04, /* hash only */
2304+ TCP_V6_FLOW = 0x05, /* hash or spec (tcp_ip6_spec; nfc only) */
2305+ UDP_V6_FLOW = 0x06, /* hash or spec (udp_ip6_spec; nfc only) */
2306+ SCTP_V6_FLOW = 0x07, /* hash or spec (sctp_ip6_spec; nfc only) */
2307+ AH_ESP_V6_FLOW = 0x08, /* hash only */
2308+ AH_V4_FLOW = 0x09, /* hash or spec (ah_ip4_spec) */
2309+ ESP_V4_FLOW = 0x0a, /* hash or spec (esp_ip4_spec) */
2310+ AH_V6_FLOW = 0x0b, /* hash or spec (ah_ip6_spec; nfc only) */
2311+ ESP_V6_FLOW = 0x0c, /* hash or spec (esp_ip6_spec; nfc only) */
2312+ IPV4_USER_FLOW = 0x0d, /* spec only (usr_ip4_spec) */
2313+ IP_USER_FLOW = IPV4_USER_FLOW,
2314+ IPV6_USER_FLOW = 0x0e, /* spec only (usr_ip6_spec; nfc only) */
2315+ IPV4_FLOW = 0x10, /* hash only */
2316+ IPV6_FLOW = 0x11, /* hash only */
2317+ ETHER_FLOW = 0x12, /* spec only (ether_spec) */
2318+
2319+ /* Used for GTP-U IPv4 and IPv6.
2320+ * The format of GTP packets only includes
2321+ * elements such as TEID and GTP version.
2322+ * It is primarily intended for data communication of the UE.
2323+ */
2324+ GTPU_V4_FLOW = 0x13, /* hash only */
2325+ GTPU_V6_FLOW = 0x14, /* hash only */
2326+
2327+ /* Use for GTP-C IPv4 and v6.
2328+ * The format of these GTP packets does not include TEID.
2329+ * Primarily expected to be used for communication
2330+ * to create sessions for UE data communication,
2331+ * commonly referred to as CSR (Create Session Request).
2332+ */
2333+ GTPC_V4_FLOW = 0x15, /* hash only */
2334+ GTPC_V6_FLOW = 0x16, /* hash only */
2335+
2336+ /* Use for GTP-C IPv4 and v6.
2337+ * Unlike GTPC_V4_FLOW, the format of these GTP packets includes TEID.
2338+ * After session creation, it becomes this packet.
2339+ * This is mainly used for requests to realize UE handover.
2340+ */
2341+ GTPC_TEID_V4_FLOW = 0x17, /* hash only */
2342+ GTPC_TEID_V6_FLOW = 0x18, /* hash only */
2343+
2344+ /* Use for GTP-U and extended headers for the PSC (PDU Session Container).
2345+ * The format of these GTP packets includes TEID and QFI.
2346+ * In 5G communication using UPF (User Plane Function),
2347+ * data communication with this extended header is performed.
2348+ */
2349+ GTPU_EH_V4_FLOW = 0x19, /* hash only */
2350+ GTPU_EH_V6_FLOW = 0x1a, /* hash only */
2351+
2352+ /* Use for GTP-U IPv4 and v6 PSC (PDU Session Container) extended headers.
2353+ * This differs from GTPU_EH_V(4|6)_FLOW in that it is distinguished by
2354+ * UL/DL included in the PSC.
2355+ * There are differences in the data included based on Downlink/Uplink,
2356+ * and can be used to distinguish packets.
2357+ * The functions described so far are useful when you want to
2358+ * handle communication from the mobile network in UPF, PGW, etc.
2359+ */
2360+ GTPU_UL_V4_FLOW = 0x1b, /* hash only */
2361+ GTPU_UL_V6_FLOW = 0x1c, /* hash only */
2362+ GTPU_DL_V4_FLOW = 0x1d, /* hash only */
2363+ GTPU_DL_V6_FLOW = 0x1e, /* hash only */
2364+
2365+ __FLOW_TYPE_COUNT,
2366+};
23632367
23642368 /* Flag to enable additional fields in struct ethtool_rx_flow_spec */
23652369 #define FLOW_EXT 0x80000000
include/uapi/linux/ethtool_netlink_generated.h+14−0
@@ -37,6 +37,18 @@ enum ethtool_tcp_data_split { · 36 unmodified lines
3737 ETHTOOL_TCP_DATA_SPLIT_ENABLED,
3838 };
3939
40+/**
41+ * enum hwtstamp_source - Source of the hardware timestamp
42+ * @HWTSTAMP_SOURCE_NETDEV: Hardware timestamp comes from a MAC or a device
43+ * which has MAC and PHY integrated
44+ * @HWTSTAMP_SOURCE_PHYLIB: Hardware timestamp comes from one PHY device of the
45+ * network topology
46+ */
47+enum hwtstamp_source {
48+ HWTSTAMP_SOURCE_NETDEV = 1,
49+ HWTSTAMP_SOURCE_PHYLIB,
50+};
51+
4052 enum {
4153 ETHTOOL_A_HEADER_UNSPEC,
4254 ETHTOOL_A_HEADER_DEV_INDEX,
@@ -401,6 +413,8 @@ enum { · 358 unmodified lines
401413 ETHTOOL_A_TSINFO_PHC_INDEX,
402414 ETHTOOL_A_TSINFO_STATS,
403415 ETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER,
416+ ETHTOOL_A_TSINFO_HWTSTAMP_SOURCE,
417+ ETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX,
404418
405419 __ETHTOOL_A_TSINFO_CNT,
406420 ETHTOOL_A_TSINFO_MAX = (__ETHTOOL_A_TSINFO_CNT - 1)
include/uapi/linux/fib_rules.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __LINUX_FIB_RULES_H
3−#define __LINUX_FIB_RULES_H
2+#ifndef _UAPI__LINUX_FIB_RULES_H
3+#define _UAPI__LINUX_FIB_RULES_H
44
55 #include <linux/types.h>
66 #include <linux/rtnetlink.h>
include/uapi/linux/fs.h+1−0
@@ -361,6 +361,7 @@ typedef int __bitwise __kernel_rwf_t; · 360 unmodified lines
361361 #define PAGE_IS_PFNZERO (1 << 5)
362362 #define PAGE_IS_HUGE (1 << 6)
363363 #define PAGE_IS_SOFT_DIRTY (1 << 7)
364+#define PAGE_IS_GUARD (1 << 8)
364365
365366 /*
366367 * struct page_region - Page region with flags
include/uapi/linux/fscrypt.h+4−2
@@ -119,7 +119,7 @@ struct fscrypt_key_specifier { · 118 unmodified lines
119119 */
120120 struct fscrypt_provisioning_key_payload {
121121 __u32 type;
122− __u32 __reserved;
122+ __u32 flags;
123123 __u8 raw[];
124124 };
125125
@@ -128,7 +128,9 @@ struct fscrypt_add_key_arg { · 2 unmodified lines
128128 struct fscrypt_key_specifier key_spec;
129129 __u32 raw_size;
130130 __u32 key_id;
131− __u32 __reserved[8];
131+#define FSCRYPT_ADD_KEY_FLAG_HW_WRAPPED 0x00000001
132+ __u32 flags;
133+ __u32 __reserved[7];
132134 __u8 raw[];
133135 };
134136
include/uapi/linux/fuse.h+5−1
@@ -232,6 +232,9 @@ · 231 unmodified lines
232232 *
233233 * 7.43
234234 * - add FUSE_REQUEST_TIMEOUT
235+ *
236+ * 7.44
237+ * - add FUSE_NOTIFY_INC_EPOCH
235238 */
236239
237240 #ifndef _LINUX_FUSE_H
@@ -267,7 +270,7 @@ · 29 unmodified lines
267270 #define FUSE_KERNEL_VERSION 7
268271
269272 /** Minor version number of this interface */
270−#define FUSE_KERNEL_MINOR_VERSION 43
273+#define FUSE_KERNEL_MINOR_VERSION 44
271274
272275 /** The node ID of the root inode */
273276 #define FUSE_ROOT_ID 1
@@ -671,6 +674,7 @@ enum fuse_notify_code { · 397 unmodified lines
671674 FUSE_NOTIFY_RETRIEVE = 5,
672675 FUSE_NOTIFY_DELETE = 6,
673676 FUSE_NOTIFY_RESEND = 7,
677+ FUSE_NOTIFY_INC_EPOCH = 8,
674678 FUSE_NOTIFY_CODE_MAX,
675679 };
676680
include/uapi/linux/futex.h+8−1
@@ -63,7 +63,7 @@ · 62 unmodified lines
6363 #define FUTEX2_SIZE_U32 0x02
6464 #define FUTEX2_SIZE_U64 0x03
6565 #define FUTEX2_NUMA 0x04
66− /* 0x08 */
66+#define FUTEX2_MPOL 0x08
6767 /* 0x10 */
6868 /* 0x20 */
6969 /* 0x40 */
@@ -74,6 +74,13 @@ · 4 unmodified lines
7474 /* do not use */
7575 #define FUTEX_32 FUTEX2_SIZE_U32 /* historical accident :-( */
7676
77+/*
78+ * When FUTEX2_NUMA doubles the futex word, the second word is a node value.
79+ * The special value -1 indicates no-node. This is the same value as
80+ * NUMA_NO_NODE, except that value is not ABI, this is.
81+ */
82+#define FUTEX_NO_NODE (-1)
83+
7784 /*
7885 * Max numbers of elements in a futex_waitv array
7986 */
include/uapi/linux/if_addr.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __LINUX_IF_ADDR_H
3−#define __LINUX_IF_ADDR_H
2+#ifndef _UAPI__LINUX_IF_ADDR_H
3+#define _UAPI__LINUX_IF_ADDR_H
44
55 #include <linux/types.h>
66 #include <linux/netlink.h>
include/uapi/linux/if_addrlabel.h+2−2
@@ -8,8 +8,8 @@ · 7 unmodified lines
88 * YOSHIFUJI Hideaki @ USAGI/WIDE <yoshfuji@linux-ipv6.org>
99 */
1010
11−#ifndef __LINUX_IF_ADDRLABEL_H
12−#define __LINUX_IF_ADDRLABEL_H
11+#ifndef _UAPI__LINUX_IF_ADDRLABEL_H
12+#define _UAPI__LINUX_IF_ADDRLABEL_H
1313
1414 #include <linux/types.h>
1515
include/uapi/linux/if_alg.h+3−3
@@ -11,8 +11,8 @@ · 10 unmodified lines
1111 *
1212 */
1313
14−#ifndef _LINUX_IF_ALG_H
15−#define _LINUX_IF_ALG_H
14+#ifndef _UAPI_LINUX_IF_ALG_H
15+#define _UAPI_LINUX_IF_ALG_H
1616
1717 #include <linux/types.h>
1818
@@ -58,4 +58,4 @@ struct af_alg_iv { · 39 unmodified lines
5858 #define ALG_OP_DECRYPT 0
5959 #define ALG_OP_ENCRYPT 1
6060
61−#endif /* _LINUX_IF_ALG_H */
61+#endif /* _UAPI_LINUX_IF_ALG_H */
include/uapi/linux/if_arcnet.h+3−3
@@ -14,8 +14,8 @@ · 13 unmodified lines
1414 * 2 of the License, or (at your option) any later version.
1515 */
1616
17−#ifndef _LINUX_IF_ARCNET_H
18−#define _LINUX_IF_ARCNET_H
17+#ifndef _UAPI_LINUX_IF_ARCNET_H
18+#define _UAPI_LINUX_IF_ARCNET_H
1919
2020 #include <linux/types.h>
2121 #include <linux/if_ether.h>
@@ -127,4 +127,4 @@ struct archdr { · 105 unmodified lines
127127 } soft;
128128 };
129129
130−#endif /* _LINUX_IF_ARCNET_H */
130+#endif /* _UAPI_LINUX_IF_ARCNET_H */
include/uapi/linux/if_bonding.h+3−3
@@ -41,8 +41,8 @@ · 40 unmodified lines
4141 * - added definitions for various XOR hashing policies
4242 */
4343
44−#ifndef _LINUX_IF_BONDING_H
45−#define _LINUX_IF_BONDING_H
44+#ifndef _UAPI_LINUX_IF_BONDING_H
45+#define _UAPI_LINUX_IF_BONDING_H
4646
4747 #include <linux/if.h>
4848 #include <linux/types.h>
@@ -152,4 +152,4 @@ enum { · 103 unmodified lines
152152 };
153153 #define BOND_3AD_STAT_MAX (__BOND_3AD_STAT_MAX - 1)
154154
155−#endif /* _LINUX_IF_BONDING_H */
155+#endif /* _UAPI_LINUX_IF_BONDING_H */
include/uapi/linux/if_bridge.h+6−4
@@ -699,10 +699,11 @@ struct br_mdb_entry { · 698 unmodified lines
699699 #define MDB_TEMPORARY 0
700700 #define MDB_PERMANENT 1
701701 __u8 state;
702−#define MDB_FLAGS_OFFLOAD (1 << 0)
703−#define MDB_FLAGS_FAST_LEAVE (1 << 1)
704−#define MDB_FLAGS_STAR_EXCL (1 << 2)
705−#define MDB_FLAGS_BLOCKED (1 << 3)
702+#define MDB_FLAGS_OFFLOAD (1 << 0)
703+#define MDB_FLAGS_FAST_LEAVE (1 << 1)
704+#define MDB_FLAGS_STAR_EXCL (1 << 2)
705+#define MDB_FLAGS_BLOCKED (1 << 3)
706+#define MDB_FLAGS_OFFLOAD_FAILED (1 << 4)
706707 __u8 flags;
707708 __u16 vid;
708709 struct {
@@ -830,6 +831,7 @@ enum br_boolopt_id { · 121 unmodified lines
830831 BR_BOOLOPT_NO_LL_LEARN,
831832 BR_BOOLOPT_MCAST_VLAN_SNOOPING,
832833 BR_BOOLOPT_MST_ENABLE,
834+ BR_BOOLOPT_MDB_OFFLOAD_FAIL_NOTIFICATION,
833835 BR_BOOLOPT_MAX
834836 };
835837
include/uapi/linux/if_fc.h+3−3
@@ -18,8 +18,8 @@ · 17 unmodified lines
1818 * as published by the Free Software Foundation; either version
1919 * 2 of the License, or (at your option) any later version.
2020 */
21−#ifndef _LINUX_IF_FC_H
22−#define _LINUX_IF_FC_H
21+#ifndef _UAPI_LINUX_IF_FC_H
22+#define _UAPI_LINUX_IF_FC_H
2323
2424 #include <linux/types.h>
2525
@@ -49,4 +49,4 @@ struct fcllc { · 23 unmodified lines
4949 __be16 ethertype; /* ether type field */
5050 };
5151
52−#endif /* _LINUX_IF_FC_H */
52+#endif /* _UAPI_LINUX_IF_FC_H */
include/uapi/linux/if_hippi.h+3−3
@@ -20,8 +20,8 @@ · 19 unmodified lines
2020 * 2 of the License, or (at your option) any later version.
2121 */
2222
23−#ifndef _LINUX_IF_HIPPI_H
24−#define _LINUX_IF_HIPPI_H
23+#ifndef _UAPI_LINUX_IF_HIPPI_H
24+#define _UAPI_LINUX_IF_HIPPI_H
2525
2626 #include <linux/types.h>
2727 #include <asm/byteorder.h>
@@ -151,4 +151,4 @@ struct hippi_hdr { · 123 unmodified lines
151151 struct hippi_snap_hdr snap;
152152 } __attribute__((packed));
153153
154−#endif /* _LINUX_IF_HIPPI_H */
154+#endif /* _UAPI_LINUX_IF_HIPPI_H */
include/uapi/linux/if_link.h+15−0
@@ -1986,4 +1986,19 @@ enum { · 1985 unmodified lines
19861986
19871987 #define IFLA_DSA_MAX (__IFLA_DSA_MAX - 1)
19881988
1989+/* OVPN section */
1990+
1991+enum ovpn_mode {
1992+ OVPN_MODE_P2P,
1993+ OVPN_MODE_MP,
1994+};
1995+
1996+enum {
1997+ IFLA_OVPN_UNSPEC,
1998+ IFLA_OVPN_MODE,
1999+ __IFLA_OVPN_MAX,
2000+};
2001+
2002+#define IFLA_OVPN_MAX (__IFLA_OVPN_MAX - 1)
2003+
19892004 #endif /* _UAPI_LINUX_IF_LINK_H */
include/uapi/linux/if_packet.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __LINUX_IF_PACKET_H
3−#define __LINUX_IF_PACKET_H
2+#ifndef _UAPI__LINUX_IF_PACKET_H
3+#define _UAPI__LINUX_IF_PACKET_H
44
55 #include <asm/byteorder.h>
66 #include <linux/types.h>
include/uapi/linux/if_plip.h+2−2
@@ -9,8 +9,8 @@ · 8 unmodified lines
99 *
1010 */
1111
12−#ifndef _LINUX_IF_PLIP_H
13−#define _LINUX_IF_PLIP_H
12+#ifndef _UAPI_LINUX_IF_PLIP_H
13+#define _UAPI_LINUX_IF_PLIP_H
1414
1515 #include <linux/sockios.h>
1616
include/uapi/linux/if_slip.h+2−2
@@ -6,8 +6,8 @@ · 5 unmodified lines
66 * KISS TNC driver.
77 */
88
9−#ifndef __LINUX_SLIP_H
10−#define __LINUX_SLIP_H
9+#ifndef _UAPI__LINUX_SLIP_H
10+#define _UAPI__LINUX_SLIP_H
1111
1212 #define SL_MODE_SLIP 0
1313 #define SL_MODE_CSLIP 1
include/uapi/linux/if_x25.h+3−3
@@ -13,8 +13,8 @@ · 12 unmodified lines
1313 * GNU General Public License for more details.
1414 */
1515
16−#ifndef _IF_X25_H
17−#define _IF_X25_H
16+#ifndef _UAPI_IF_X25_H
17+#define _UAPI_IF_X25_H
1818
1919 #include <linux/types.h>
2020
@@ -24,4 +24,4 @@ · 3 unmodified lines
2424 #define X25_IFACE_DISCONNECT 0x02
2525 #define X25_IFACE_PARAMS 0x03
2626
27−#endif /* _IF_X25_H */
27+#endif /* _UAPI_IF_X25_H */
include/uapi/linux/if_xdp.h+3−3
@@ -7,8 +7,8 @@ · 6 unmodified lines
77 * Magnus Karlsson <magnus.karlsson@intel.com>
88 */
99
10−#ifndef _LINUX_IF_XDP_H
11−#define _LINUX_IF_XDP_H
10+#ifndef _UAPI_LINUX_IF_XDP_H
11+#define _UAPI_LINUX_IF_XDP_H
1212
1313 #include <linux/types.h>
1414
@@ -180,4 +180,4 @@ struct xdp_desc { · 165 unmodified lines
180180 /* TX packet carries valid metadata. */
181181 #define XDP_TX_METADATA (1 << 1)
182182
183−#endif /* _LINUX_IF_XDP_H */
183+#endif /* _UAPI_LINUX_IF_XDP_H */
include/uapi/linux/input-event-codes.h+2−1
@@ -930,7 +930,8 @@ · 929 unmodified lines
930930 #define SW_MUTE_DEVICE 0x0e /* set = device disabled */
931931 #define SW_PEN_INSERTED 0x0f /* set = pen inserted */
932932 #define SW_MACHINE_COVER 0x10 /* set = cover closed */
933−#define SW_MAX 0x10
933+#define SW_USB_INSERT 0x11 /* set = USB audio device connected */
934+#define SW_MAX 0x11
934935 #define SW_CNT (SW_MAX+1)
935936
936937 /*
include/uapi/linux/io_uring.h+11−1
@@ -73,6 +73,7 @@ struct io_uring_sqe { · 72 unmodified lines
7373 __u32 futex_flags;
7474 __u32 install_fd_flags;
7575 __u32 nop_flags;
76+ __u32 pipe_flags;
7677 };
7778 __u64 user_data; /* data to be passed back at completion time */
7879 /* pack this to avoid bogus arm OABI complaints */
@@ -93,6 +94,10 @@ struct io_uring_sqe { · 14 unmodified lines
9394 __u16 addr_len;
9495 __u16 __pad3[1];
9596 };
97+ struct {
98+ __u8 write_stream;
99+ __u8 __pad4[3];
100+ };
96101 };
97102 union {
98103 struct {
@@ -283,6 +288,7 @@ enum io_uring_op { · 184 unmodified lines
283288 IORING_OP_EPOLL_WAIT,
284289 IORING_OP_READV_FIXED,
285290 IORING_OP_WRITEV_FIXED,
291+ IORING_OP_PIPE,
286292
287293 /* this goes last, obviously */
288294 IORING_OP_LAST,
@@ -988,12 +994,16 @@ struct io_uring_zcrx_offsets { · 699 unmodified lines
988994 __u64 __resv[2];
989995 };
990996
997+enum io_uring_zcrx_area_flags {
998+ IORING_ZCRX_AREA_DMABUF = 1,
999+};
1000+
9911001 struct io_uring_zcrx_area_reg {
9921002 __u64 addr;
9931003 __u64 len;
9941004 __u64 rq_area_token;
9951005 __u32 flags;
996− __u32 __resv1;
1006+ __u32 dmabuf_fd;
9971007 __u64 __resv2[2];
9981008 };
9991009
include/uapi/linux/ip6_tunnel.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef _IP6_TUNNEL_H
3−#define _IP6_TUNNEL_H
2+#ifndef _UAPI_IP6_TUNNEL_H
3+#define _UAPI_IP6_TUNNEL_H
44
55 #include <linux/types.h>
66 #include <linux/if.h> /* For IFNAMSIZ. */
include/uapi/linux/isst_if.h+26−0
@@ -375,6 +375,30 @@ struct isst_perf_level_data_info { · 374 unmodified lines
375375 __u16 trl_freq_mhz[TRL_MAX_LEVELS][TRL_MAX_BUCKETS];
376376 };
377377
378+#define MAX_FABRIC_COUNT 8
379+
380+/**
381+ * struct isst_perf_level_fabric_info - Structure to get SST-PP fabric details
382+ * @socket_id: Socket/package id
383+ * @power_domain_id: Power Domain id
384+ * @level: SST-PP level for which caller wants to get information
385+ * @max_fabrics: Count of fabrics in resonse
386+ * @p0_fabric_freq_mhz: Fabric (Uncore) maximum frequency
387+ * @p1_fabric_freq_mhz: Fabric (Uncore) TDP frequency
388+ * @pm_fabric_freq_mhz: Fabric (Uncore) minimum frequency
389+ *
390+ * Structure used to get information on frequencies for fabrics.
391+ */
392+struct isst_perf_level_fabric_info {
393+ __u8 socket_id;
394+ __u8 power_domain_id;
395+ __u16 level;
396+ __u16 max_fabrics;
397+ __u16 p0_fabric_freq_mhz[MAX_FABRIC_COUNT];
398+ __u16 p1_fabric_freq_mhz[MAX_FABRIC_COUNT];
399+ __u16 pm_fabric_freq_mhz[MAX_FABRIC_COUNT];
400+};
401+
378402 /**
379403 * struct isst_perf_level_cpu_mask - Structure to get SST-PP level CPU mask
380404 * @socket_id: Socket/package id
@@ -471,5 +495,7 @@ struct isst_turbo_freq_info { · 90 unmodified lines
471495 #define ISST_IF_GET_BASE_FREQ_INFO _IOR(ISST_IF_MAGIC, 14, struct isst_base_freq_info *)
472496 #define ISST_IF_GET_BASE_FREQ_CPU_MASK _IOR(ISST_IF_MAGIC, 15, struct isst_perf_level_cpu_mask *)
473497 #define ISST_IF_GET_TURBO_FREQ_INFO _IOR(ISST_IF_MAGIC, 16, struct isst_turbo_freq_info *)
498+#define ISST_IF_GET_PERF_LEVEL_FABRIC_INFO _IOR(ISST_IF_MAGIC, 17,\
499+ struct isst_perf_level_fabric_info *)
474500
475501 #endif
include/uapi/linux/kfd_ioctl.h+5−0
@@ -536,6 +536,8 @@ enum kfd_smi_event { · 535 unmodified lines
536536 KFD_SMI_EVENT_QUEUE_EVICTION = 9,
537537 KFD_SMI_EVENT_QUEUE_RESTORE = 10,
538538 KFD_SMI_EVENT_UNMAP_FROM_GPU = 11,
539+ KFD_SMI_EVENT_PROCESS_START = 12,
540+ KFD_SMI_EVENT_PROCESS_END = 13,
539541
540542 /*
541543 * max event number, as a flag bit to get events from all processes,
@@ -651,6 +653,9 @@ struct kfd_ioctl_smi_events_args { · 109 unmodified lines
651653 "%lld -%d @%lx(%lx) %x %d\n", (ns), (pid), (addr), (size),\
652654 (node), (unmap_trigger)
653655
656+#define KFD_EVENT_FMT_PROCESS(pid, task_name)\
657+ "%x %s\n", (pid), (task_name)
658+
654659 /**************************************************************************************************
655660 * CRIU IOCTLs (Checkpoint Restore In Userspace)
656661 *
include/uapi/linux/kvm.h+4−0
@@ -375,6 +375,7 @@ struct kvm_run { · 374 unmodified lines
375375 #define KVM_SYSTEM_EVENT_WAKEUP 4
376376 #define KVM_SYSTEM_EVENT_SUSPEND 5
377377 #define KVM_SYSTEM_EVENT_SEV_TERM 6
378+#define KVM_SYSTEM_EVENT_TDX_FATAL 7
378379 __u32 type;
379380 __u32 ndata;
380381 union {
@@ -930,6 +931,9 @@ struct kvm_enable_cap { · 549 unmodified lines
930931 #define KVM_CAP_X86_APIC_BUS_CYCLES_NS 237
931932 #define KVM_CAP_X86_GUEST_MODE 238
932933 #define KVM_CAP_ARM_WRITABLE_IMP_ID_REGS 239
934+#define KVM_CAP_ARM_EL2 240
935+#define KVM_CAP_ARM_EL2_E2H0 241
936+#define KVM_CAP_RISCV_MP_STATE_RESET 242
933937
934938 struct kvm_irq_routing_irqchip {
935939 __u32 irqchip;
include/uapi/linux/media/amlogic/c3-isp-config.h+564−0
@@ -0,0 +1,564 @@
1+/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
2+/*
3+ * Copyright (C) 2024 Amlogic, Inc. All rights reserved
4+ */
5+
6+#ifndef _UAPI_C3_ISP_CONFIG_H_
7+#define _UAPI_C3_ISP_CONFIG_H_
8+
9+#include <linux/types.h>
10+
11+/*
12+ * Frames are split into zones of almost equal width and height - a zone is a
13+ * rectangular tile of a frame. The metering blocks within the ISP collect
14+ * aggregated statistics per zone.
15+ */
16+#define C3_ISP_AE_MAX_ZONES (17 * 15)
17+#define C3_ISP_AF_MAX_ZONES (17 * 15)
18+#define C3_ISP_AWB_MAX_ZONES (32 * 24)
19+
20+/* The maximum number of point on the diagonal of the frame for statistics */
21+#define C3_ISP_AE_MAX_PT_NUM 18
22+#define C3_ISP_AF_MAX_PT_NUM 18
23+#define C3_ISP_AWB_MAX_PT_NUM 33
24+
25+/**
26+ * struct c3_isp_awb_zone_stats - AWB statistics of a zone
27+ *
28+ * AWB zone stats is aligned with 8 bytes
29+ *
30+ * @rg: the ratio of R / G in a zone
31+ * @bg: the ratio of B / G in a zone
32+ * @pixel_sum: the total number of pixels used in a zone
33+ */
34+struct c3_isp_awb_zone_stats {
35+ __u16 rg;
36+ __u16 bg;
37+ __u32 pixel_sum;
38+};
39+
40+/**
41+ * struct c3_isp_awb_stats - Auto white balance statistics information.
42+ *
43+ * AWB statistical information of all zones.
44+ *
45+ * @stats: array of auto white balance statistics
46+ */
47+struct c3_isp_awb_stats {
48+ struct c3_isp_awb_zone_stats stats[C3_ISP_AWB_MAX_ZONES];
49+} __attribute__((aligned(16)));
50+
51+/**
52+ * struct c3_isp_ae_zone_stats - AE statistics of a zone
53+ *
54+ * AE zone stats is aligned with 8 bytes.
55+ * This is a 5-bin histogram and the total sum is normalized to 0xffff.
56+ * So hist2 = 0xffff - (hist0 + hist1 + hist3 + hist4)
57+ *
58+ * @hist0: the global normalized pixel count for bin 0
59+ * @hist1: the global normalized pixel count for bin 1
60+ * @hist3: the global normalized pixel count for bin 3
61+ * @hist4: the global normalized pixel count for bin 4
62+ */
63+struct c3_isp_ae_zone_stats {
64+ __u16 hist0;
65+ __u16 hist1;
66+ __u16 hist3;
67+ __u16 hist4;
68+};
69+
70+/**
71+ * struct c3_isp_ae_stats - Exposure statistics information
72+ *
73+ * AE statistical information consists of all blocks information and a 1024-bin
74+ * histogram.
75+ *
76+ * @stats: array of auto exposure block statistics
77+ * @reserved: undefined buffer space
78+ * @hist: a 1024-bin histogram for the entire image
79+ */
80+struct c3_isp_ae_stats {
81+ struct c3_isp_ae_zone_stats stats[C3_ISP_AE_MAX_ZONES];
82+ __u32 reserved[2];
83+ __u32 hist[1024];
84+} __attribute__((aligned(16)));
85+
86+/**
87+ * struct c3_isp_af_zone_stats - AF statistics of a zone
88+ *
89+ * AF zone stats is aligned with 8 bytes.
90+ * The zonal accumulated contrast metrics are stored in floating point format
91+ * with 16 bits mantissa and 5 or 6 bits exponent. Apart from contrast metrics
92+ * we accumulate squared image and quartic image data over the zone.
93+ *
94+ * @i2_mat: the mantissa of zonal squared image pixel sum
95+ * @i4_mat: the mantissa of zonal quartic image pixel sum
96+ * @e4_mat: the mantissa of zonal multi-directional quartic edge sum
97+ * @e4_exp: the exponent of zonal multi-directional quartic edge sum
98+ * @i2_exp: the exponent of zonal squared image pixel sum
99+ * @i4_exp: the exponent of zonal quartic image pixel sum
100+ */
101+struct c3_isp_af_zone_stats {
102+ __u16 i2_mat;
103+ __u16 i4_mat;
104+ __u16 e4_mat;
105+ __u16 e4_exp : 5;
106+ __u16 i2_exp : 5;
107+ __u16 i4_exp : 6;
108+};
109+
110+/**
111+ * struct c3_isp_af_stats - Auto Focus statistics information
112+ *
113+ * AF statistical information of each zone
114+ *
115+ * @stats: array of auto focus block statistics
116+ * @reserved: undefined buffer space
117+ */
118+struct c3_isp_af_stats {
119+ struct c3_isp_af_zone_stats stats[C3_ISP_AF_MAX_ZONES];
120+ __u32 reserved[2];
121+} __attribute__((aligned(16)));
122+
123+/**
124+ * struct c3_isp_stats_info - V4L2_META_FMT_C3ISP_STATS
125+ *
126+ * Contains ISP statistics
127+ *
128+ * @awb: auto white balance stats
129+ * @ae: auto exposure stats
130+ * @af: auto focus stats
131+ */
132+struct c3_isp_stats_info {
133+ struct c3_isp_awb_stats awb;
134+ struct c3_isp_ae_stats ae;
135+ struct c3_isp_af_stats af;
136+};
137+
138+/**
139+ * enum c3_isp_params_buffer_version - C3 ISP parameters block versioning
140+ *
141+ * @C3_ISP_PARAMS_BUFFER_V0: First version of C3 ISP parameters block
142+ */
143+enum c3_isp_params_buffer_version {
144+ C3_ISP_PARAMS_BUFFER_V0,
145+};
146+
147+/**
148+ * enum c3_isp_params_block_type - Enumeration of C3 ISP parameter blocks
149+ *
150+ * Each block configures a specific processing block of the C3 ISP.
151+ * The block type allows the driver to correctly interpret the parameters block
152+ * data.
153+ *
154+ * @C3_ISP_PARAMS_BLOCK_AWB_GAINS: White balance gains
155+ * @C3_ISP_PARAMS_BLOCK_AWB_CONFIG: AWB statistic format configuration for all
156+ * blocks that control how stats are generated
157+ * @C3_ISP_PARAMS_BLOCK_AE_CONFIG: AE statistic format configuration for all
158+ * blocks that control how stats are generated
159+ * @C3_ISP_PARAMS_BLOCK_AF_CONFIG: AF statistic format configuration for all
160+ * blocks that control how stats are generated
161+ * @C3_ISP_PARAMS_BLOCK_PST_GAMMA: post gamma parameters
162+ * @C3_ISP_PARAMS_BLOCK_CCM: Color correction matrix parameters
163+ * @C3_ISP_PARAMS_BLOCK_CSC: Color space conversion parameters
164+ * @C3_ISP_PARAMS_BLOCK_BLC: Black level correction parameters
165+ * @C3_ISP_PARAMS_BLOCK_SENTINEL: First non-valid block index
166+ */
167+enum c3_isp_params_block_type {
168+ C3_ISP_PARAMS_BLOCK_AWB_GAINS,
169+ C3_ISP_PARAMS_BLOCK_AWB_CONFIG,
170+ C3_ISP_PARAMS_BLOCK_AE_CONFIG,
171+ C3_ISP_PARAMS_BLOCK_AF_CONFIG,
172+ C3_ISP_PARAMS_BLOCK_PST_GAMMA,
173+ C3_ISP_PARAMS_BLOCK_CCM,
174+ C3_ISP_PARAMS_BLOCK_CSC,
175+ C3_ISP_PARAMS_BLOCK_BLC,
176+ C3_ISP_PARAMS_BLOCK_SENTINEL
177+};
178+
179+#define C3_ISP_PARAMS_BLOCK_FL_DISABLE (1U << 0)
180+#define C3_ISP_PARAMS_BLOCK_FL_ENABLE (1U << 1)
181+
182+/**
183+ * struct c3_isp_params_block_header - C3 ISP parameter block header
184+ *
185+ * This structure represents the common part of all the ISP configuration
186+ * blocks. Each parameters block shall embed an instance of this structure type
187+ * as its first member, followed by the block-specific configuration data. The
188+ * driver inspects this common header to discern the block type and its size and
189+ * properly handle the block content by casting it to the correct block-specific
190+ * type.
191+ *
192+ * The @type field is one of the values enumerated by
193+ * :c:type:`c3_isp_params_block_type` and specifies how the data should be
194+ * interpreted by the driver. The @size field specifies the size of the
195+ * parameters block and is used by the driver for validation purposes. The
196+ * @flags field is a bitmask of per-block flags C3_ISP_PARAMS_FL*.
197+ *
198+ * When userspace wants to disable an ISP block the
199+ * C3_ISP_PARAMS_BLOCK_FL_DISABLED bit should be set in the @flags field. In
200+ * this case userspace may optionally omit the remainder of the configuration
201+ * block, which will be ignored by the driver.
202+ *
203+ * When a new configuration of an ISP block needs to be applied userspace
204+ * shall fully populate the ISP block and omit setting the
205+ * C3_ISP_PARAMS_BLOCK_FL_DISABLED bit in the @flags field.
206+ *
207+ * Userspace is responsible for correctly populating the parameters block header
208+ * fields (@type, @flags and @size) and the block-specific parameters.
209+ *
210+ * For example:
211+ *
212+ * .. code-block:: c
213+ *
214+ * void populate_pst_gamma(struct c3_isp_params_block_header *block) {
215+ * struct c3_isp_params_pst_gamma *gamma =
216+ * (struct c3_isp_params_pst_gamma *)block;
217+ *
218+ * gamma->header.type = C3_ISP_PARAMS_BLOCK_PST_GAMMA;
219+ * gamma->header.flags = C3_ISP_PARAMS_BLOCK_FL_ENABLE;
220+ * gamma->header.size = sizeof(*gamma);
221+ *
222+ * for (unsigned int i = 0; i < 129; i++)
223+ * gamma->pst_gamma_lut[i] = i;
224+ * }
225+ *
226+ * @type: The parameters block type from :c:type:`c3_isp_params_block_type`
227+ * @flags: A bitmask of block flags
228+ * @size: Size (in bytes) of the parameters block, including this header
229+ */
230+struct c3_isp_params_block_header {
231+ __u16 type;
232+ __u16 flags;
233+ __u32 size;
234+};
235+
236+/**
237+ * struct c3_isp_params_awb_gains - Gains for auto-white balance
238+ *
239+ * This struct allows users to configure the gains for white balance.
240+ * There are four gain settings corresponding to each colour channel in
241+ * the bayer domain. All of the gains are stored in Q4.8 format.
242+ *
243+ * header.type should be set to C3_ISP_PARAMS_BLOCK_AWB_GAINS
244+ * from :c:type:`c3_isp_params_block_type`
245+ *
246+ * @header: The C3 ISP parameters block header
247+ * @gr_gain: Multiplier for Gr channel (Q4.8 format)
248+ * @r_gain: Multiplier for R channel (Q4.8 format)
249+ * @b_gain: Multiplier for B channel (Q4.8 format)
250+ * @gb_gain: Multiplier for Gb channel (Q4.8 format)
251+ */
252+struct c3_isp_params_awb_gains {
253+ struct c3_isp_params_block_header header;
254+ __u16 gr_gain;
255+ __u16 r_gain;
256+ __u16 b_gain;
257+ __u16 gb_gain;
258+} __attribute__((aligned(8)));
259+
260+/**
261+ * enum c3_isp_params_awb_tap_points - Tap points for the AWB statistics
262+ * @C3_ISP_AWB_STATS_TAP_OFE: immediately after the optical frontend block
263+ * @C3_ISP_AWB_STATS_TAP_GE: immediately after the green equal block
264+ * @C3_ISP_AWB_STATS_TAP_BEFORE_WB: immediately before the white balance block
265+ * @C3_ISP_AWB_STATS_TAP_AFTER_WB: immediately after the white balance block
266+ */
267+enum c3_isp_params_awb_tap_points {
268+ C3_ISP_AWB_STATS_TAP_OFE = 0,
269+ C3_ISP_AWB_STATS_TAP_GE,
270+ C3_ISP_AWB_STATS_TAP_BEFORE_WB,
271+ C3_ISP_AWB_STATS_TAP_AFTER_WB,
272+};
273+
274+/**
275+ * struct c3_isp_params_awb_config - Stats settings for auto-white balance
276+ *
277+ * This struct allows the configuration of the statistics generated for auto
278+ * white balance.
279+ *
280+ * header.type should be set to C3_ISP_PARAMS_BLOCK_AWB_CONFIG
281+ * from :c:type:`c3_isp_params_block_type`
282+ *
283+ * @header: the C3 ISP parameters block header
284+ * @tap_point: the tap point from enum c3_isp_params_awb_tap_point
285+ * @satur_vald: AWB statistic over saturation control
286+ * value: 0: disable, 1: enable
287+ * @horiz_zones_num: active number of hotizontal zones [0..32]
288+ * @vert_zones_num: active number of vertical zones [0..24]
289+ * @rg_min: minimum R/G ratio (Q4.8 format)
290+ * @rg_max: maximum R/G ratio (Q4.8 format)
291+ * @bg_min: minimum B/G ratio (Q4.8 format)
292+ * @bg_max: maximum B/G ratio (Q4.8 format)
293+ * @rg_low: R/G ratio trim low (Q4.8 format)
294+ * @rg_high: R/G ratio trim hight (Q4.8 format)
295+ * @bg_low: B/G ratio trim low (Q4.8 format)
296+ * @bg_high: B/G ratio trim high (Q4.8 format)
297+ * @zone_weight: array of weights for AWB statistics zones [0..15]
298+ * @horiz_coord: the horizontal coordinate of points on the diagonal [0..2888]
299+ * @vert_coord: the vertical coordinate of points on the diagonal [0..2240]
300+ */
301+struct c3_isp_params_awb_config {
302+ struct c3_isp_params_block_header header;
303+ __u8 tap_point;
304+ __u8 satur_vald;
305+ __u8 horiz_zones_num;
306+ __u8 vert_zones_num;
307+ __u16 rg_min;
308+ __u16 rg_max;
309+ __u16 bg_min;
310+ __u16 bg_max;
311+ __u16 rg_low;
312+ __u16 rg_high;
313+ __u16 bg_low;
314+ __u16 bg_high;
315+ __u8 zone_weight[C3_ISP_AWB_MAX_ZONES];
316+ __u16 horiz_coord[C3_ISP_AWB_MAX_PT_NUM];
317+ __u16 vert_coord[C3_ISP_AWB_MAX_PT_NUM];
318+} __attribute__((aligned(8)));
319+
320+/**
321+ * enum c3_isp_params_ae_tap_points - Tap points for the AE statistics
322+ * @C3_ISP_AE_STATS_TAP_GE: immediately after the green equal block
323+ * @C3_ISP_AE_STATS_TAP_MLS: immediately after the mesh lens shading block
324+ */
325+enum c3_isp_params_ae_tap_points {
326+ C3_ISP_AE_STATS_TAP_GE = 0,
327+ C3_ISP_AE_STATS_TAP_MLS,
328+};
329+
330+/**
331+ * struct c3_isp_params_ae_config - Stats settings for auto-exposure
332+ *
333+ * This struct allows the configuration of the statistics generated for
334+ * auto exposure.
335+ *
336+ * header.type should be set to C3_ISP_PARAMS_BLOCK_AE_CONFIG
337+ * from :c:type:`c3_isp_params_block_type`
338+ *
339+ * @header: the C3 ISP parameters block header
340+ * @horiz_zones_num: active number of horizontal zones [0..17]
341+ * @vert_zones_num: active number of vertical zones [0..15]
342+ * @tap_point: the tap point from enum c3_isp_params_ae_tap_point
343+ * @zone_weight: array of weights for AE statistics zones [0..15]
344+ * @horiz_coord: the horizontal coordinate of points on the diagonal [0..2888]
345+ * @vert_coord: the vertical coordinate of points on the diagonal [0..2240]
346+ * @reserved: applications must zero this array
347+ */
348+struct c3_isp_params_ae_config {
349+ struct c3_isp_params_block_header header;
350+ __u8 tap_point;
351+ __u8 horiz_zones_num;
352+ __u8 vert_zones_num;
353+ __u8 zone_weight[C3_ISP_AE_MAX_ZONES];
354+ __u16 horiz_coord[C3_ISP_AE_MAX_PT_NUM];
355+ __u16 vert_coord[C3_ISP_AE_MAX_PT_NUM];
356+ __u16 reserved[3];
357+} __attribute__((aligned(8)));
358+
359+/**
360+ * enum c3_isp_params_af_tap_points - Tap points for the AF statistics
361+ * @C3_ISP_AF_STATS_TAP_SNR: immediately after the spatial noise reduce block
362+ * @C3_ISP_AF_STATS_TAP_DMS: immediately after the demosaic block
363+ */
364+enum c3_isp_params_af_tap_points {
365+ C3_ISP_AF_STATS_TAP_SNR = 0,
366+ C3_ISP_AF_STATS_TAP_DMS,
367+};
368+
369+/**
370+ * struct c3_isp_params_af_config - Stats settings for auto-focus
371+ *
372+ * This struct allows the configuration of the statistics generated for
373+ * auto focus.
374+ *
375+ * header.type should be set to C3_ISP_PARAMS_BLOCK_AF_CONFIG
376+ * from :c:type:`c3_isp_params_block_type`
377+ *
378+ * @header: the C3 ISP parameters block header
379+ * @tap_point: the tap point from enum c3_isp_params_af_tap_point
380+ * @horiz_zones_num: active number of hotizontal zones [0..17]
381+ * @vert_zones_num: active number of vertical zones [0..15]
382+ * @reserved: applications must zero this array
383+ * @horiz_coord: the horizontal coordinate of points on the diagonal [0..2888]
384+ * @vert_coord: the vertical coordinate of points on the diagonal [0..2240]
385+ */
386+struct c3_isp_params_af_config {
387+ struct c3_isp_params_block_header header;
388+ __u8 tap_point;
389+ __u8 horiz_zones_num;
390+ __u8 vert_zones_num;
391+ __u8 reserved[5];
392+ __u16 horiz_coord[C3_ISP_AF_MAX_PT_NUM];
393+ __u16 vert_coord[C3_ISP_AF_MAX_PT_NUM];
394+} __attribute__((aligned(8)));
395+
396+/**
397+ * struct c3_isp_params_pst_gamma - Post gamma configuration
398+ *
399+ * This struct allows the configuration of the look up table for
400+ * post gamma. The gamma curve consists of 129 points, so need to
401+ * set lut[129].
402+ *
403+ * header.type should be set to C3_ISP_PARAMS_BLOCK_PST_GAMMA
404+ * from :c:type:`c3_isp_params_block_type`
405+ *
406+ * @header: the C3 ISP parameters block header
407+ * @lut: lookup table for P-Stitch gamma [0..1023]
408+ * @reserved: applications must zero this array
409+ */
410+struct c3_isp_params_pst_gamma {
411+ struct c3_isp_params_block_header header;
412+ __u16 lut[129];
413+ __u16 reserved[3];
414+} __attribute__((aligned(8)));
415+
416+/**
417+ * struct c3_isp_params_ccm - ISP CCM configuration
418+ *
419+ * This struct allows the configuration of the matrix for
420+ * color correction. The matrix consists of 3 x 3 points,
421+ * so need to set matrix[3][3].
422+ *
423+ * header.type should be set to C3_ISP_PARAMS_BLOCK_CCM
424+ * from :c:type:`c3_isp_params_block_type`
425+ *
426+ * @header: the C3 ISP parameters block header
427+ * @matrix: a 3 x 3 matrix used for color correction,
428+ * the value of matrix[x][y] is orig_value x 256. [-4096..4095]
429+ * @reserved: applications must zero this array
430+ */
431+struct c3_isp_params_ccm {
432+ struct c3_isp_params_block_header header;
433+ __s16 matrix[3][3];
434+ __u16 reserved[3];
435+} __attribute__((aligned(8)));
436+
437+/**
438+ * struct c3_isp_params_csc - ISP Color Space Conversion configuration
439+ *
440+ * This struct allows the configuration of the matrix for color space
441+ * conversion. The matrix consists of 3 x 3 points, so need to set matrix[3][3].
442+ *
443+ * header.type should be set to C3_ISP_PARAMS_BLOCK_CSC
444+ * from :c:type:`c3_isp_params_block_type`
445+ *
446+ * @header: the C3 ISP parameters block header
447+ * @matrix: a 3x3 matrix used for the color space conversion,
448+ * the value of matrix[x][y] is orig_value x 256. [-4096..4095]
449+ * @reserved: applications must zero this array
450+ */
451+struct c3_isp_params_csc {
452+ struct c3_isp_params_block_header header;
453+ __s16 matrix[3][3];
454+ __u16 reserved[3];
455+} __attribute__((aligned(8)));
456+
457+/**
458+ * struct c3_isp_params_blc - ISP Black Level Correction configuration
459+ *
460+ * This struct allows the configuration of the block level offset for each
461+ * color channel.
462+ *
463+ * header.type should be set to C3_ISP_PARAMS_BLOCK_BLC
464+ * from :c:type:`c3_isp_params_block_type`
465+ *
466+ * @header: the C3 ISP parameters block header
467+ * @gr_ofst: Gr blc offset (Q4.12 format)
468+ * @r_ofst: R blc offset (Q4.12 format)
469+ * @b_ofst: B blc offset (Q4.12 format)
470+ * @gb_ofst: Gb blc offset(Q4.12 format)
471+ */
472+struct c3_isp_params_blc {
473+ struct c3_isp_params_block_header header;
474+ __u16 gr_ofst;
475+ __u16 r_ofst;
476+ __u16 b_ofst;
477+ __u16 gb_ofst;
478+};
479+
480+/**
481+ * define C3_ISP_PARAMS_MAX_SIZE - Maximum size of all C3 ISP Parameters
482+ *
483+ * Though the parameters for the C3 ISP are passed as optional blocks, the
484+ * driver still needs to know the absolute maximum size so that it can allocate
485+ * a buffer sized appropriately to accommodate userspace attempting to set all
486+ * possible parameters in a single frame.
487+ */
488+#define C3_ISP_PARAMS_MAX_SIZE \
489+ (sizeof(struct c3_isp_params_awb_gains) + \
490+ sizeof(struct c3_isp_params_awb_config) + \
491+ sizeof(struct c3_isp_params_ae_config) + \
492+ sizeof(struct c3_isp_params_af_config) + \
493+ sizeof(struct c3_isp_params_pst_gamma) + \
494+ sizeof(struct c3_isp_params_ccm) + \
495+ sizeof(struct c3_isp_params_csc) + \
496+ sizeof(struct c3_isp_params_blc))
497+
498+/**
499+ * struct c3_isp_params_cfg - C3 ISP configuration parameters
500+ *
501+ * This struct contains the configuration parameters of the C3 ISP
502+ * algorithms, serialized by userspace into an opaque data buffer. Each
503+ * configuration parameter block is represented by a block-specific structure
504+ * which contains a :c:type:`c3_isp_param_block_header` entry as first
505+ * member. Userspace populates the @data buffer with configuration parameters
506+ * for the blocks that it intends to configure. As a consequence, the data
507+ * buffer effective size changes according to the number of ISP blocks that
508+ * userspace intends to configure.
509+ *
510+ * The parameters buffer is versioned by the @version field to allow modifying
511+ * and extending its definition. Userspace should populate the @version field to
512+ * inform the driver about the version it intends to use. The driver will parse
513+ * and handle the @data buffer according to the data layout specific to the
514+ * indicated revision and return an error if the desired revision is not
515+ * supported.
516+ *
517+ * For each ISP block that userspace wants to configure, a block-specific
518+ * structure is appended to the @data buffer, one after the other without gaps
519+ * in between nor overlaps. Userspace shall populate the @total_size field with
520+ * the effective size, in bytes, of the @data buffer.
521+ *
522+ * The expected memory layout of the parameters buffer is::
523+ *
524+ * +-------------------- struct c3_isp_params_cfg ---- ------------------+
525+ * | version = C3_ISP_PARAM_BUFFER_V0; |
526+ * | data_size = sizeof(struct c3_isp_params_awb_gains) + |
527+ * | sizeof(struct c3_isp_params_awb_config); |
528+ * | +------------------------- data ---------------------------------+ |
529+ * | | +------------ struct c3_isp_params_awb_gains) ------------------+ |
530+ * | | | +--------- struct c3_isp_params_block_header header -----+ | | |
531+ * | | | | type = C3_ISP_PARAMS_BLOCK_AWB_GAINS; | | | |
532+ * | | | | flags = C3_ISP_PARAMS_BLOCK_FL_NONE; | | | |
533+ * | | | | size = sizeof(struct c3_isp_params_awb_gains); | | | |
534+ * | | | +---------------------------------------------------------+ | | |
535+ * | | | gr_gain = ...; | | |
536+ * | | | r_gain = ...; | | |
537+ * | | | b_gain = ...; | | |
538+ * | | | gb_gain = ...; | | |
539+ * | | +------------------ struct c3_isp_params_awb_config ----------+ | |
540+ * | | | +---------- struct c3_isp_param_block_header header ------+ | | |
541+ * | | | | type = C3_ISP_PARAMS_BLOCK_AWB_CONFIG; | | | |
542+ * | | | | flags = C3_ISP_PARAMS_BLOCK_FL_NONE; | | | |
543+ * | | | | size = sizeof(struct c3_isp_params_awb_config) | | | |
544+ * | | | +---------------------------------------------------------+ | | |
545+ * | | | tap_point = ...; | | |
546+ * | | | satur_vald = ...; | | |
547+ * | | | horiz_zones_num = ...; | | |
548+ * | | | vert_zones_num = ...; | | |
549+ * | | +-------------------------------------------------------------+ | |
550+ * | +-----------------------------------------------------------------+ |
551+ * +---------------------------------------------------------------------+
552+ *
553+ * @version: The C3 ISP parameters buffer version
554+ * @data_size: The C3 ISP configuration data effective size, excluding this
555+ * header
556+ * @data: The C3 ISP configuration blocks data
557+ */
558+struct c3_isp_params_cfg {
559+ __u32 version;
560+ __u32 data_size;
561+ __u8 data[C3_ISP_PARAMS_MAX_SIZE];
562+};
563+
564+#endif
include/uapi/linux/neighbour.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __LINUX_NEIGHBOUR_H
3−#define __LINUX_NEIGHBOUR_H
2+#ifndef _UAPI__LINUX_NEIGHBOUR_H
3+#define _UAPI__LINUX_NEIGHBOUR_H
44
55 #include <linux/types.h>
66 #include <linux/netlink.h>
include/uapi/linux/net_dropmon.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __NET_DROPMON_H
3−#define __NET_DROPMON_H
2+#ifndef _UAPI__NET_DROPMON_H
3+#define _UAPI__NET_DROPMON_H
44
55 #include <linux/types.h>
66 #include <linux/netlink.h>
include/uapi/linux/net_tstamp.h+3−3
@@ -7,8 +7,8 @@ · 6 unmodified lines
77 *
88 */
99
10−#ifndef _NET_TIMESTAMPING_H
11−#define _NET_TIMESTAMPING_H
10+#ifndef _UAPI_NET_TIMESTAMPING_H
11+#define _UAPI_NET_TIMESTAMPING_H
1212
1313 #include <linux/types.h>
1414 #include <linux/socket.h> /* for SO_TIMESTAMPING */
@@ -216,4 +216,4 @@ struct sock_txtime { · 201 unmodified lines
216216 __u32 flags; /* as defined by enum txtime_flags */
217217 };
218218
219−#endif /* _NET_TIMESTAMPING_H */
219+#endif /* _UAPI_NET_TIMESTAMPING_H */
include/uapi/linux/netdev.h+1−0
@@ -219,6 +219,7 @@ enum { · 218 unmodified lines
219219 NETDEV_CMD_QSTATS_GET,
220220 NETDEV_CMD_BIND_RX,
221221 NETDEV_CMD_NAPI_SET,
222+ NETDEV_CMD_BIND_TX,
222223
223224 __NETDEV_CMD_MAX,
224225 NETDEV_CMD_MAX = (__NETDEV_CMD_MAX - 1)
include/uapi/linux/netfilter/nf_tables.h+22−0
@@ -142,6 +142,8 @@ enum nf_tables_msg_types { · 141 unmodified lines
142142 NFT_MSG_DESTROYOBJ,
143143 NFT_MSG_DESTROYFLOWTABLE,
144144 NFT_MSG_GETSETELEM_RESET,
145+ NFT_MSG_NEWDEV,
146+ NFT_MSG_DELDEV,
145147 NFT_MSG_MAX,
146148 };
147149
@@ -394,6 +396,8 @@ enum nft_set_field_attributes { · 246 unmodified lines
394396 * @NFTA_SET_HANDLE: set handle (NLA_U64)
395397 * @NFTA_SET_EXPR: set expression (NLA_NESTED: nft_expr_attributes)
396398 * @NFTA_SET_EXPRESSIONS: list of expressions (NLA_NESTED: nft_list_attributes)
399+ * @NFTA_SET_TYPE: set backend type (NLA_STRING)
400+ * @NFTA_SET_COUNT: number of set elements (NLA_U32)
397401 */
398402 enum nft_set_attributes {
399403 NFTA_SET_UNSPEC,
@@ -415,6 +419,8 @@ enum nft_set_attributes { · 15 unmodified lines
415419 NFTA_SET_HANDLE,
416420 NFTA_SET_EXPR,
417421 NFTA_SET_EXPRESSIONS,
422+ NFTA_SET_TYPE,
423+ NFTA_SET_COUNT,
418424 __NFTA_SET_MAX
419425 };
420426 #define NFTA_SET_MAX (__NFTA_SET_MAX - 1)
@@ -1780,10 +1786,18 @@ enum nft_synproxy_attributes { · 1359 unmodified lines
17801786 * enum nft_device_attributes - nf_tables device netlink attributes
17811787 *
17821788 * @NFTA_DEVICE_NAME: name of this device (NLA_STRING)
1789+ * @NFTA_DEVICE_TABLE: table containing the flowtable or chain hooking into the device (NLA_STRING)
1790+ * @NFTA_DEVICE_FLOWTABLE: flowtable hooking into the device (NLA_STRING)
1791+ * @NFTA_DEVICE_CHAIN: chain hooking into the device (NLA_STRING)
1792+ * @NFTA_DEVICE_SPEC: hook spec matching the device (NLA_STRING)
17831793 */
17841794 enum nft_devices_attributes {
17851795 NFTA_DEVICE_UNSPEC,
17861796 NFTA_DEVICE_NAME,
1797+ NFTA_DEVICE_TABLE,
1798+ NFTA_DEVICE_FLOWTABLE,
1799+ NFTA_DEVICE_CHAIN,
1800+ NFTA_DEVICE_SPEC,
17871801 __NFTA_DEVICE_MAX
17881802 };
17891803 #define NFTA_DEVICE_MAX (__NFTA_DEVICE_MAX - 1)
@@ -1837,6 +1851,10 @@ enum nft_xfrm_keys { · 47 unmodified lines
18371851 * @NFTA_TRACE_MARK: nfmark (NLA_U32)
18381852 * @NFTA_TRACE_NFPROTO: nf protocol processed (NLA_U32)
18391853 * @NFTA_TRACE_POLICY: policy that decided fate of packet (NLA_U32)
1854+ * @NFTA_TRACE_CT_ID: conntrack id (NLA_U32)
1855+ * @NFTA_TRACE_CT_DIRECTION: packets direction (NLA_U8)
1856+ * @NFTA_TRACE_CT_STATUS: conntrack status (NLA_U32)
1857+ * @NFTA_TRACE_CT_STATE: packet state (new, established, ...) (NLA_U32)
18401858 */
18411859 enum nft_trace_attributes {
18421860 NFTA_TRACE_UNSPEC,
@@ -1857,6 +1875,10 @@ enum nft_trace_attributes { · 14 unmodified lines
18571875 NFTA_TRACE_NFPROTO,
18581876 NFTA_TRACE_POLICY,
18591877 NFTA_TRACE_PAD,
1878+ NFTA_TRACE_CT_ID,
1879+ NFTA_TRACE_CT_DIRECTION,
1880+ NFTA_TRACE_CT_STATUS,
1881+ NFTA_TRACE_CT_STATE,
18601882 __NFTA_TRACE_MAX
18611883 };
18621884 #define NFTA_TRACE_MAX (__NFTA_TRACE_MAX - 1)
include/uapi/linux/netfilter/nfnetlink.h+2−0
@@ -25,6 +25,8 @@ enum nfnetlink_groups { · 24 unmodified lines
2525 #define NFNLGRP_ACCT_QUOTA NFNLGRP_ACCT_QUOTA
2626 NFNLGRP_NFTRACE,
2727 #define NFNLGRP_NFTRACE NFNLGRP_NFTRACE
28+ NFNLGRP_NFT_DEV,
29+#define NFNLGRP_NFT_DEV NFNLGRP_NFT_DEV
2830 __NFNLGRP_MAX,
2931 };
3032 #define NFNLGRP_MAX (__NFNLGRP_MAX - 1)
include/uapi/linux/netlink_diag.h+2−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __NETLINK_DIAG_H__
3−#define __NETLINK_DIAG_H__
2+#ifndef _UAPI__NETLINK_DIAG_H__
3+#define _UAPI__NETLINK_DIAG_H__
44
55 #include <linux/types.h>
66
include/uapi/linux/nl80211.h+6−0
@@ -8036,6 +8036,11 @@ enum nl80211_sar_specs_attrs { · 8035 unmodified lines
80368036 * Setting this flag is permitted only if the driver advertises EMA support
80378037 * by setting wiphy->ema_max_profile_periodicity to non-zero.
80388038 *
8039+ * @NL80211_MBSSID_CONFIG_ATTR_TX_LINK_ID: Link ID of the transmitted profile.
8040+ * This parameter is mandatory when NL80211_ATTR_MBSSID_CONFIG attributes
8041+ * are sent for a non-transmitted profile and if the transmitted profile
8042+ * is part of an MLD. For all other cases this parameter is unnecessary.
8043+ *
80398044 * @__NL80211_MBSSID_CONFIG_ATTR_LAST: Internal
80408045 * @NL80211_MBSSID_CONFIG_ATTR_MAX: highest attribute
80418046 */
@@ -8047,6 +8052,7 @@ enum nl80211_mbssid_config_attributes { · 5 unmodified lines
80478052 NL80211_MBSSID_CONFIG_ATTR_INDEX,
80488053 NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX,
80498054 NL80211_MBSSID_CONFIG_ATTR_EMA,
8055+ NL80211_MBSSID_CONFIG_ATTR_TX_LINK_ID,
80508056
80518057 /* keep last */
80528058 __NL80211_MBSSID_CONFIG_ATTR_LAST,
include/uapi/linux/ovpn.h+109−0
@@ -0,0 +1,109 @@
1+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2+/* Do not edit directly, auto-generated from: */
3+/* Documentation/netlink/specs/ovpn.yaml */
4+/* YNL-GEN uapi header */
5+
6+#ifndef _UAPI_LINUX_OVPN_H
7+#define _UAPI_LINUX_OVPN_H
8+
9+#define OVPN_FAMILY_NAME "ovpn"
10+#define OVPN_FAMILY_VERSION 1
11+
12+#define OVPN_NONCE_TAIL_SIZE 8
13+
14+enum ovpn_cipher_alg {
15+ OVPN_CIPHER_ALG_NONE,
16+ OVPN_CIPHER_ALG_AES_GCM,
17+ OVPN_CIPHER_ALG_CHACHA20_POLY1305,
18+};
19+
20+enum ovpn_del_peer_reason {
21+ OVPN_DEL_PEER_REASON_TEARDOWN,
22+ OVPN_DEL_PEER_REASON_USERSPACE,
23+ OVPN_DEL_PEER_REASON_EXPIRED,
24+ OVPN_DEL_PEER_REASON_TRANSPORT_ERROR,
25+ OVPN_DEL_PEER_REASON_TRANSPORT_DISCONNECT,
26+};
27+
28+enum ovpn_key_slot {
29+ OVPN_KEY_SLOT_PRIMARY,
30+ OVPN_KEY_SLOT_SECONDARY,
31+};
32+
33+enum {
34+ OVPN_A_PEER_ID = 1,
35+ OVPN_A_PEER_REMOTE_IPV4,
36+ OVPN_A_PEER_REMOTE_IPV6,
37+ OVPN_A_PEER_REMOTE_IPV6_SCOPE_ID,
38+ OVPN_A_PEER_REMOTE_PORT,
39+ OVPN_A_PEER_SOCKET,
40+ OVPN_A_PEER_SOCKET_NETNSID,
41+ OVPN_A_PEER_VPN_IPV4,
42+ OVPN_A_PEER_VPN_IPV6,
43+ OVPN_A_PEER_LOCAL_IPV4,
44+ OVPN_A_PEER_LOCAL_IPV6,
45+ OVPN_A_PEER_LOCAL_PORT,
46+ OVPN_A_PEER_KEEPALIVE_INTERVAL,
47+ OVPN_A_PEER_KEEPALIVE_TIMEOUT,
48+ OVPN_A_PEER_DEL_REASON,
49+ OVPN_A_PEER_VPN_RX_BYTES,
50+ OVPN_A_PEER_VPN_TX_BYTES,
51+ OVPN_A_PEER_VPN_RX_PACKETS,
52+ OVPN_A_PEER_VPN_TX_PACKETS,
53+ OVPN_A_PEER_LINK_RX_BYTES,
54+ OVPN_A_PEER_LINK_TX_BYTES,
55+ OVPN_A_PEER_LINK_RX_PACKETS,
56+ OVPN_A_PEER_LINK_TX_PACKETS,
57+
58+ __OVPN_A_PEER_MAX,
59+ OVPN_A_PEER_MAX = (__OVPN_A_PEER_MAX - 1)
60+};
61+
62+enum {
63+ OVPN_A_KEYCONF_PEER_ID = 1,
64+ OVPN_A_KEYCONF_SLOT,
65+ OVPN_A_KEYCONF_KEY_ID,
66+ OVPN_A_KEYCONF_CIPHER_ALG,
67+ OVPN_A_KEYCONF_ENCRYPT_DIR,
68+ OVPN_A_KEYCONF_DECRYPT_DIR,
69+
70+ __OVPN_A_KEYCONF_MAX,
71+ OVPN_A_KEYCONF_MAX = (__OVPN_A_KEYCONF_MAX - 1)
72+};
73+
74+enum {
75+ OVPN_A_KEYDIR_CIPHER_KEY = 1,
76+ OVPN_A_KEYDIR_NONCE_TAIL,
77+
78+ __OVPN_A_KEYDIR_MAX,
79+ OVPN_A_KEYDIR_MAX = (__OVPN_A_KEYDIR_MAX - 1)
80+};
81+
82+enum {
83+ OVPN_A_IFINDEX = 1,
84+ OVPN_A_PEER,
85+ OVPN_A_KEYCONF,
86+
87+ __OVPN_A_MAX,
88+ OVPN_A_MAX = (__OVPN_A_MAX - 1)
89+};
90+
91+enum {
92+ OVPN_CMD_PEER_NEW = 1,
93+ OVPN_CMD_PEER_SET,
94+ OVPN_CMD_PEER_GET,
95+ OVPN_CMD_PEER_DEL,
96+ OVPN_CMD_PEER_DEL_NTF,
97+ OVPN_CMD_KEY_NEW,
98+ OVPN_CMD_KEY_GET,
99+ OVPN_CMD_KEY_SWAP,
100+ OVPN_CMD_KEY_SWAP_NTF,
101+ OVPN_CMD_KEY_DEL,
102+
103+ __OVPN_CMD_MAX,
104+ OVPN_CMD_MAX = (__OVPN_CMD_MAX - 1)
105+};
106+
107+#define OVPN_MCGRP_PEERS "peers"
108+
109+#endif /* _UAPI_LINUX_OVPN_H */
include/uapi/linux/pci_regs.h+11−1
@@ -750,7 +750,8 @@ · 749 unmodified lines
750750 #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
751751 #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
752752 #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
753−#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE
753+#define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */
754+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT
754755
755756 #define PCI_EXT_CAP_DSN_SIZEOF 12
756757 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1144,12 +1145,21 @@ · 387 unmodified lines
11441145 #define PCI_DLF_CAP 0x04 /* Capabilities Register */
11451146 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
11461147
1148+/* Secondary PCIe Capability 8.0 GT/s */
1149+#define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */
1150+
11471151 /* Physical Layer 16.0 GT/s */
11481152 #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
11491153 #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F
11501154 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
11511155 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
11521156
1157+/* Physical Layer 32.0 GT/s */
1158+#define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
1159+
1160+/* Physical Layer 64.0 GT/s */
1161+#define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
1162+
11531163 /* Native PCIe Enclosure Management */
11541164 #define PCI_NPEM_CAP 0x04 /* NPEM capability register */
11551165 #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */
include/uapi/linux/perf_event.h+334−323
@@ -39,18 +39,21 @@ enum perf_type_id { · 38 unmodified lines
3939
4040 /*
4141 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
42+ *
4243 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA
4344 * AA: hardware event ID
4445 * EEEEEEEE: PMU type ID
46+ *
4547 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB
4648 * BB: hardware cache ID
4749 * CC: hardware cache op ID
4850 * DD: hardware cache op result ID
4951 * EEEEEEEE: PMU type ID
50− * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied.
52+ *
53+ * If the PMU type ID is 0, PERF_TYPE_RAW will be applied.
5154 */
52−#define PERF_PMU_TYPE_SHIFT 32
53−#define PERF_HW_EVENT_MASK 0xffffffff
55+#define PERF_PMU_TYPE_SHIFT 32
56+#define PERF_HW_EVENT_MASK 0xffffffff
5457
5558 /*
5659 * Generalized performance event event_id types, used by the
@@ -112,7 +115,7 @@ enum perf_hw_cache_op_result_id { · 55 unmodified lines
112115 /*
113116 * Special "software" events provided by the kernel, even if the hardware
114117 * does not support performance events. These events measure various
115− * physical and sw events of the kernel (and allow the profiling of them as
118+ * physical and SW events of the kernel (and allow the profiling of them as
116119 * well):
117120 */
118121 enum perf_sw_ids {
@@ -167,8 +170,9 @@ enum perf_event_sample_format { · 48 unmodified lines
167170 };
168171
169172 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT)
173+
170174 /*
171− * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
175+ * Values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set.
172176 *
173177 * If the user does not pass priv level information via branch_sample_type,
174178 * the kernel uses the event's priv level. Branch and event priv levels do
@@ -178,20 +182,20 @@ enum perf_event_sample_format { · 3 unmodified lines
178182 * of branches and therefore it supersedes all the other types.
179183 */
180184 enum perf_branch_sample_type_shift {
181− PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
182− PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
183− PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
184−
185− PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
186− PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
187− PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
188− PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
189− PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
190− PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
191− PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
185+ PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
186+ PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
187+ PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
188+
189+ PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
190+ PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
191+ PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
192+ PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
193+ PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
194+ PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
195+ PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
192196 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
193197
194− PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
198+ PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* CALL/RET stack */
195199 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
196200 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
197201
@@ -210,96 +214,95 @@ enum perf_branch_sample_type_shift { · 12 unmodified lines
210214 };
211215
212216 enum perf_branch_sample_type {
213− PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
214− PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
215− PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
217+ PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
218+ PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
219+ PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
216220
217− PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
218− PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
219− PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
220− PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
221− PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
222− PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
223− PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
224− PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
221+ PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
222+ PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
223+ PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
224+ PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
225+ PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
226+ PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
227+ PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
228+ PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
225229
226− PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
227− PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
228− PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
230+ PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
231+ PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
232+ PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
229233
230− PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
231− PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
234+ PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
235+ PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
232236
233− PERF_SAMPLE_BRANCH_TYPE_SAVE =
234− 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
237+ PERF_SAMPLE_BRANCH_TYPE_SAVE = 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
235238
236− PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT,
239+ PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT,
237240
238− PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT,
241+ PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT,
239242
240− PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT,
243+ PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT,
241244
242− PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
245+ PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
243246 };
244247
245248 /*
246− * Common flow change classification
249+ * Common control flow change classifications:
247250 */
248251 enum {
249− PERF_BR_UNKNOWN = 0, /* unknown */
250− PERF_BR_COND = 1, /* conditional */
251− PERF_BR_UNCOND = 2, /* unconditional */
252− PERF_BR_IND = 3, /* indirect */
253− PERF_BR_CALL = 4, /* function call */
254− PERF_BR_IND_CALL = 5, /* indirect function call */
255− PERF_BR_RET = 6, /* function return */
256− PERF_BR_SYSCALL = 7, /* syscall */
257− PERF_BR_SYSRET = 8, /* syscall return */
258− PERF_BR_COND_CALL = 9, /* conditional function call */
259− PERF_BR_COND_RET = 10, /* conditional function return */
260− PERF_BR_ERET = 11, /* exception return */
261− PERF_BR_IRQ = 12, /* irq */
262− PERF_BR_SERROR = 13, /* system error */
263− PERF_BR_NO_TX = 14, /* not in transaction */
264− PERF_BR_EXTEND_ABI = 15, /* extend ABI */
252+ PERF_BR_UNKNOWN = 0, /* Unknown */
253+ PERF_BR_COND = 1, /* Conditional */
254+ PERF_BR_UNCOND = 2, /* Unconditional */
255+ PERF_BR_IND = 3, /* Indirect */
256+ PERF_BR_CALL = 4, /* Function call */
257+ PERF_BR_IND_CALL = 5, /* Indirect function call */
258+ PERF_BR_RET = 6, /* Function return */
259+ PERF_BR_SYSCALL = 7, /* Syscall */
260+ PERF_BR_SYSRET = 8, /* Syscall return */
261+ PERF_BR_COND_CALL = 9, /* Conditional function call */
262+ PERF_BR_COND_RET = 10, /* Conditional function return */
263+ PERF_BR_ERET = 11, /* Exception return */
264+ PERF_BR_IRQ = 12, /* IRQ */
265+ PERF_BR_SERROR = 13, /* System error */
266+ PERF_BR_NO_TX = 14, /* Not in transaction */
267+ PERF_BR_EXTEND_ABI = 15, /* Extend ABI */
265268 PERF_BR_MAX,
266269 };
267270
268271 /*
269− * Common branch speculation outcome classification
272+ * Common branch speculation outcome classifications:
270273 */
271274 enum {
272− PERF_BR_SPEC_NA = 0, /* Not available */
273− PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */
274− PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */
275− PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */
275+ PERF_BR_SPEC_NA = 0, /* Not available */
276+ PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */
277+ PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */
278+ PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */
276279 PERF_BR_SPEC_MAX,
277280 };
278281
279282 enum {
280− PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */
281− PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */
282− PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */
283− PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */
284− PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */
285− PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */
286− PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */
287− PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */
283+ PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */
284+ PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */
285+ PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */
286+ PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */
287+ PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */
288+ PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */
289+ PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */
290+ PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */
288291 PERF_BR_NEW_MAX,
289292 };
290293
291294 enum {
292− PERF_BR_PRIV_UNKNOWN = 0,
293− PERF_BR_PRIV_USER = 1,
294− PERF_BR_PRIV_KERNEL = 2,
295− PERF_BR_PRIV_HV = 3,
295+ PERF_BR_PRIV_UNKNOWN = 0,
296+ PERF_BR_PRIV_USER = 1,
297+ PERF_BR_PRIV_KERNEL = 2,
298+ PERF_BR_PRIV_HV = 3,
296299 };
297300
298−#define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1
299−#define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2
300−#define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3
301−#define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4
302−#define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5
301+#define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1
302+#define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2
303+#define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3
304+#define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4
305+#define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5
303306
304307 #define PERF_SAMPLE_BRANCH_PLM_ALL \
305308 (PERF_SAMPLE_BRANCH_USER|\
@@ -310,9 +313,9 @@ enum { · 4 unmodified lines
310313 * Values to determine ABI of the registers dump.
311314 */
312315 enum perf_sample_regs_abi {
313− PERF_SAMPLE_REGS_ABI_NONE = 0,
314− PERF_SAMPLE_REGS_ABI_32 = 1,
315− PERF_SAMPLE_REGS_ABI_64 = 2,
316+ PERF_SAMPLE_REGS_ABI_NONE = 0,
317+ PERF_SAMPLE_REGS_ABI_32 = 1,
318+ PERF_SAMPLE_REGS_ABI_64 = 2,
316319 };
317320
318321 /*
@@ -320,21 +323,21 @@ enum perf_sample_regs_abi { · 1 unmodified line
320323 * abort events. Multiple bits can be set.
321324 */
322325 enum {
323− PERF_TXN_ELISION = (1 << 0), /* From elision */
324− PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
325− PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
326− PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
327− PERF_TXN_RETRY = (1 << 4), /* Retry possible */
328− PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
329− PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
330− PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
326+ PERF_TXN_ELISION = (1 << 0), /* From elision */
327+ PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
328+ PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
329+ PERF_TXN_ASYNC = (1 << 3), /* Instruction is not related */
330+ PERF_TXN_RETRY = (1 << 4), /* Retry possible */
331+ PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
332+ PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
333+ PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
331334
332− PERF_TXN_MAX = (1 << 8), /* non-ABI */
335+ PERF_TXN_MAX = (1 << 8), /* non-ABI */
333336
334− /* bits 32..63 are reserved for the abort code */
337+ /* Bits 32..63 are reserved for the abort code */
335338
336− PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
337− PERF_TXN_ABORT_SHIFT = 32,
339+ PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
340+ PERF_TXN_ABORT_SHIFT = 32,
338341 };
339342
340343 /*
@@ -369,24 +372,22 @@ enum perf_event_read_format { · 28 unmodified lines
369372 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */
370373 };
371374
372−#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
373−#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
374−#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
375−#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
376− /* add: sample_stack_user */
377−#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
378−#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
379−#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */
380−#define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */
381−#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */
375+#define PERF_ATTR_SIZE_VER0 64 /* Size of first published 'struct perf_event_attr' */
376+#define PERF_ATTR_SIZE_VER1 72 /* Add: config2 */
377+#define PERF_ATTR_SIZE_VER2 80 /* Add: branch_sample_type */
378+#define PERF_ATTR_SIZE_VER3 96 /* Add: sample_regs_user */
379+ /* Add: sample_stack_user */
380+#define PERF_ATTR_SIZE_VER4 104 /* Add: sample_regs_intr */
381+#define PERF_ATTR_SIZE_VER5 112 /* Add: aux_watermark */
382+#define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */
383+#define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */
384+#define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */
382385
383386 /*
384− * Hardware event_id to monitor via a performance monitoring event:
385− *
386− * @sample_max_stack: Max number of frame pointers in a callchain,
387− * should be < /proc/sys/kernel/perf_event_max_stack
388− * Max number of entries of branch stack
389− * should be < hardware limit
387+ * 'struct perf_event_attr' contains various attributes that define
388+ * a performance event - most of them hardware related configuration
389+ * details, but also a lot of behavioral switches and values implemented
390+ * by the kernel.
390391 */
391392 struct perf_event_attr {
392393
@@ -396,7 +397,7 @@ struct perf_event_attr { · 3 unmodified lines
396397 __u32 type;
397398
398399 /*
399− * Size of the attr structure, for fwd/bwd compat.
400+ * Size of the attr structure, for forward/backwards compatibility.
400401 */
401402 __u32 size;
402403
@@ -451,21 +452,21 @@ struct perf_event_attr { · 48 unmodified lines
451452 comm_exec : 1, /* flag comm events that are due to an exec */
452453 use_clockid : 1, /* use @clockid for time fields */
453454 context_switch : 1, /* context switch data */
454− write_backward : 1, /* Write ring buffer from end to beginning */
455+ write_backward : 1, /* write ring buffer from end to beginning */
455456 namespaces : 1, /* include namespaces data */
456457 ksymbol : 1, /* include ksymbol events */
457− bpf_event : 1, /* include bpf events */
458+ bpf_event : 1, /* include BPF events */
458459 aux_output : 1, /* generate AUX records instead of events */
459460 cgroup : 1, /* include cgroup events */
460461 text_poke : 1, /* include text poke events */
461− build_id : 1, /* use build id in mmap2 events */
462+ build_id : 1, /* use build ID in mmap2 events */
462463 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */
463464 remove_on_exec : 1, /* event is removed from task on exec */
464465 sigtrap : 1, /* send synchronous SIGTRAP on event */
465466 __reserved_1 : 26;
466467
467468 union {
468− __u32 wakeup_events; /* wakeup every n events */
469+ __u32 wakeup_events; /* wake up every n events */
469470 __u32 wakeup_watermark; /* bytes before wakeup */
470471 };
471472
@@ -474,13 +475,13 @@ struct perf_event_attr { · 2 unmodified lines
474475 __u64 bp_addr;
475476 __u64 kprobe_func; /* for perf_kprobe */
476477 __u64 uprobe_path; /* for perf_uprobe */
477− __u64 config1; /* extension of config */
478+ __u64 config1; /* extension of config */
478479 };
479480 union {
480481 __u64 bp_len;
481− __u64 kprobe_addr; /* when kprobe_func == NULL */
482+ __u64 kprobe_addr; /* when kprobe_func == NULL */
482483 __u64 probe_offset; /* for perf_[k,u]probe */
483− __u64 config2; /* extension of config1 */
484+ __u64 config2; /* extension of config1 */
484485 };
485486 __u64 branch_sample_type; /* enum perf_branch_sample_type */
486487
@@ -510,7 +511,16 @@ struct perf_event_attr { · 23 unmodified lines
510511 * Wakeup watermark for AUX area
511512 */
512513 __u32 aux_watermark;
514+
515+ /*
516+ * Max number of frame pointers in a callchain, should be
517+ * lower than /proc/sys/kernel/perf_event_max_stack.
518+ *
519+ * Max number of entries of branch stack should be lower
520+ * than the hardware limit.
521+ */
513522 __u16 sample_max_stack;
523+
514524 __u16 __reserved_2;
515525 __u32 aux_sample_size;
516526
@@ -537,7 +547,7 @@ struct perf_event_attr { · 20 unmodified lines
537547
538548 /*
539549 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command
540− * to query bpf programs attached to the same perf tracepoint
550+ * to query BPF programs attached to the same perf tracepoint
541551 * as the given perf event.
542552 */
543553 struct perf_event_query_bpf {
@@ -559,21 +569,21 @@ struct perf_event_query_bpf { · 15 unmodified lines
559569 /*
560570 * Ioctls that can be done on a perf event fd:
561571 */
562−#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
563−#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
564−#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
565−#define PERF_EVENT_IOC_RESET _IO ('$', 3)
566−#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
567−#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
568−#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
569−#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
570−#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
571−#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
572+#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
573+#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
574+#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
575+#define PERF_EVENT_IOC_RESET _IO ('$', 3)
576+#define PERF_EVENT_IOC_PERIOD _IOW ('$', 4, __u64)
577+#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
578+#define PERF_EVENT_IOC_SET_FILTER _IOW ('$', 6, char *)
579+#define PERF_EVENT_IOC_ID _IOR ('$', 7, __u64 *)
580+#define PERF_EVENT_IOC_SET_BPF _IOW ('$', 8, __u32)
581+#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW ('$', 9, __u32)
572582 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *)
573−#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *)
583+#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW ('$', 11, struct perf_event_attr *)
574584
575585 enum perf_event_ioc_flags {
576− PERF_IOC_FLAG_GROUP = 1U << 0,
586+ PERF_IOC_FLAG_GROUP = 1U << 0,
577587 };
578588
579589 /*
@@ -584,7 +594,7 @@ struct perf_event_mmap_page { · 4 unmodified lines
584594 __u32 compat_version; /* lowest version this is compat with */
585595
586596 /*
587− * Bits needed to read the hw events in user-space.
597+ * Bits needed to read the HW events in user-space.
588598 *
589599 * u32 seq, time_mult, time_shift, index, width;
590600 * u64 count, enabled, running;
@@ -622,7 +632,7 @@ struct perf_event_mmap_page { · 31 unmodified lines
622632 __u32 index; /* hardware event identifier */
623633 __s64 offset; /* add to hardware event value */
624634 __u64 time_enabled; /* time event active */
625− __u64 time_running; /* time event on cpu */
635+ __u64 time_running; /* time event on CPU */
626636 union {
627637 __u64 capabilities;
628638 struct {
@@ -650,7 +660,7 @@ struct perf_event_mmap_page { · 21 unmodified lines
650660
651661 /*
652662 * If cap_usr_time the below fields can be used to compute the time
653− * delta since time_enabled (in ns) using rdtsc or similar.
663+ * delta since time_enabled (in ns) using RDTSC or similar.
654664 *
655665 * u64 quot, rem;
656666 * u64 delta;
@@ -723,7 +733,7 @@ struct perf_event_mmap_page { · 66 unmodified lines
723733 * after reading this value.
724734 *
725735 * When the mapping is PROT_WRITE the @data_tail value should be
726− * written by userspace to reflect the last read data, after issueing
736+ * written by user-space to reflect the last read data, after issuing
727737 * an smp_mb() to separate the data read from the ->data_tail store.
728738 * In this case the kernel will not over-write unread data.
729739 *
@@ -739,7 +749,7 @@ struct perf_event_mmap_page { · 9 unmodified lines
739749
740750 /*
741751 * AUX area is defined by aux_{offset,size} fields that should be set
742− * by the userspace, so that
752+ * by the user-space, so that
743753 *
744754 * aux_offset >= data_offset + data_size
745755 *
@@ -813,7 +823,7 @@ struct perf_event_mmap_page { · 67 unmodified lines
813823 * Indicates that thread was preempted in TASK_RUNNING state.
814824 *
815825 * PERF_RECORD_MISC_MMAP_BUILD_ID:
816− * Indicates that mmap2 event carries build id data.
826+ * Indicates that mmap2 event carries build ID data.
817827 */
818828 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
819829 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14)
@@ -824,26 +834,26 @@ struct perf_event_mmap_page { · 4 unmodified lines
824834 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
825835
826836 struct perf_event_header {
827− __u32 type;
828− __u16 misc;
829− __u16 size;
837+ __u32 type;
838+ __u16 misc;
839+ __u16 size;
830840 };
831841
832842 struct perf_ns_link_info {
833− __u64 dev;
834− __u64 ino;
843+ __u64 dev;
844+ __u64 ino;
835845 };
836846
837847 enum {
838− NET_NS_INDEX = 0,
839− UTS_NS_INDEX = 1,
840− IPC_NS_INDEX = 2,
841− PID_NS_INDEX = 3,
842− USER_NS_INDEX = 4,
843− MNT_NS_INDEX = 5,
844− CGROUP_NS_INDEX = 6,
845−
846− NR_NAMESPACES, /* number of available namespaces */
848+ NET_NS_INDEX = 0,
849+ UTS_NS_INDEX = 1,
850+ IPC_NS_INDEX = 2,
851+ PID_NS_INDEX = 3,
852+ USER_NS_INDEX = 4,
853+ MNT_NS_INDEX = 5,
854+ CGROUP_NS_INDEX = 6,
855+
856+ NR_NAMESPACES, /* number of available namespaces */
847857 };
848858
849859 enum perf_event_type {
@@ -859,11 +869,11 @@ enum perf_event_type { · 9 unmodified lines
859869 * optional fields being ignored.
860870 *
861871 * struct sample_id {
862− * { u32 pid, tid; } && PERF_SAMPLE_TID
863− * { u64 time; } && PERF_SAMPLE_TIME
864− * { u64 id; } && PERF_SAMPLE_ID
865− * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
866− * { u32 cpu, res; } && PERF_SAMPLE_CPU
872+ * { u32 pid, tid; } && PERF_SAMPLE_TID
873+ * { u64 time; } && PERF_SAMPLE_TIME
874+ * { u64 id; } && PERF_SAMPLE_ID
875+ * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
876+ * { u32 cpu, res; } && PERF_SAMPLE_CPU
867877 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
868878 * } && perf_event_attr::sample_id_all
869879 *
@@ -874,7 +884,7 @@ enum perf_event_type { · 4 unmodified lines
874884
875885 /*
876886 * The MMAP events record the PROT_EXEC mappings so that we can
877− * correlate userspace IPs to code. They have the following structure:
887+ * correlate user-space IPs to code. They have the following structure:
878888 *
879889 * struct {
880890 * struct perf_event_header header;
@@ -884,7 +894,7 @@ enum perf_event_type { · 3 unmodified lines
884894 * u64 len;
885895 * u64 pgoff;
886896 * char filename[];
887− * struct sample_id sample_id;
897+ * struct sample_id sample_id;
888898 * };
889899 */
890900 PERF_RECORD_MMAP = 1,
@@ -894,7 +904,7 @@ enum perf_event_type { · 3 unmodified lines
894904 * struct perf_event_header header;
895905 * u64 id;
896906 * u64 lost;
897− * struct sample_id sample_id;
907+ * struct sample_id sample_id;
898908 * };
899909 */
900910 PERF_RECORD_LOST = 2,
@@ -905,7 +915,7 @@ enum perf_event_type { · 4 unmodified lines
905915 *
906916 * u32 pid, tid;
907917 * char comm[];
908− * struct sample_id sample_id;
918+ * struct sample_id sample_id;
909919 * };
910920 */
911921 PERF_RECORD_COMM = 3,
@@ -916,7 +926,7 @@ enum perf_event_type { · 4 unmodified lines
916926 * u32 pid, ppid;
917927 * u32 tid, ptid;
918928 * u64 time;
919− * struct sample_id sample_id;
929+ * struct sample_id sample_id;
920930 * };
921931 */
922932 PERF_RECORD_EXIT = 4,
@@ -927,7 +937,7 @@ enum perf_event_type { · 4 unmodified lines
927937 * u64 time;
928938 * u64 id;
929939 * u64 stream_id;
930− * struct sample_id sample_id;
940+ * struct sample_id sample_id;
931941 * };
932942 */
933943 PERF_RECORD_THROTTLE = 5,
@@ -939,7 +949,7 @@ enum perf_event_type { · 5 unmodified lines
939949 * u32 pid, ppid;
940950 * u32 tid, ptid;
941951 * u64 time;
942− * struct sample_id sample_id;
952+ * struct sample_id sample_id;
943953 * };
944954 */
945955 PERF_RECORD_FORK = 7,
@@ -950,7 +960,7 @@ enum perf_event_type { · 4 unmodified lines
950960 * u32 pid, tid;
951961 *
952962 * struct read_format values;
953− * struct sample_id sample_id;
963+ * struct sample_id sample_id;
954964 * };
955965 */
956966 PERF_RECORD_READ = 8,
@@ -1005,12 +1015,12 @@ enum perf_event_type { · 48 unmodified lines
10051015 * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS
10061016 * } && PERF_SAMPLE_BRANCH_STACK
10071017 *
1008− * { u64 abi; # enum perf_sample_regs_abi
1009− * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
1018+ * { u64 abi; # enum perf_sample_regs_abi
1019+ * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
10101020 *
1011− * { u64 size;
1012− * char data[size];
1013− * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
1021+ * { u64 size;
1022+ * char data[size];
1023+ * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
10141024 *
10151025 * { union perf_sample_weight
10161026 * {
@@ -1035,10 +1045,11 @@ enum perf_event_type { · 18 unmodified lines
10351045 * { u64 abi; # enum perf_sample_regs_abi
10361046 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
10371047 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
1038− * { u64 size;
1039− * char data[size]; } && PERF_SAMPLE_AUX
1048+ * { u64 cgroup;} && PERF_SAMPLE_CGROUP
10401049 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE
10411050 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE
1051+ * { u64 size;
1052+ * char data[size]; } && PERF_SAMPLE_AUX
10421053 * };
10431054 */
10441055 PERF_RECORD_SAMPLE = 9,
@@ -1070,7 +1081,7 @@ enum perf_event_type { · 25 unmodified lines
10701081 * };
10711082 * u32 prot, flags;
10721083 * char filename[];
1073− * struct sample_id sample_id;
1084+ * struct sample_id sample_id;
10741085 * };
10751086 */
10761087 PERF_RECORD_MMAP2 = 10,
@@ -1079,12 +1090,12 @@ enum perf_event_type { · 2 unmodified lines
10791090 * Records that new data landed in the AUX buffer part.
10801091 *
10811092 * struct {
1082− * struct perf_event_header header;
1093+ * struct perf_event_header header;
10831094 *
1084− * u64 aux_offset;
1085− * u64 aux_size;
1095+ * u64 aux_offset;
1096+ * u64 aux_size;
10861097 * u64 flags;
1087− * struct sample_id sample_id;
1098+ * struct sample_id sample_id;
10881099 * };
10891100 */
10901101 PERF_RECORD_AUX = 11,
@@ -1167,7 +1178,7 @@ enum perf_event_type { · 76 unmodified lines
11671178 PERF_RECORD_KSYMBOL = 17,
11681179
11691180 /*
1170− * Record bpf events:
1181+ * Record BPF events:
11711182 * enum perf_bpf_event_type {
11721183 * PERF_BPF_EVENT_UNKNOWN = 0,
11731184 * PERF_BPF_EVENT_PROG_LOAD = 1,
@@ -1245,181 +1256,181 @@ enum perf_record_ksymbol_type { · 71 unmodified lines
12451256 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0)
12461257
12471258 enum perf_bpf_event_type {
1248− PERF_BPF_EVENT_UNKNOWN = 0,
1249− PERF_BPF_EVENT_PROG_LOAD = 1,
1250− PERF_BPF_EVENT_PROG_UNLOAD = 2,
1251− PERF_BPF_EVENT_MAX, /* non-ABI */
1259+ PERF_BPF_EVENT_UNKNOWN = 0,
1260+ PERF_BPF_EVENT_PROG_LOAD = 1,
1261+ PERF_BPF_EVENT_PROG_UNLOAD = 2,
1262+ PERF_BPF_EVENT_MAX, /* non-ABI */
12521263 };
12531264
1254−#define PERF_MAX_STACK_DEPTH 127
1255−#define PERF_MAX_CONTEXTS_PER_STACK 8
1265+#define PERF_MAX_STACK_DEPTH 127
1266+#define PERF_MAX_CONTEXTS_PER_STACK 8
12561267
12571268 enum perf_callchain_context {
1258− PERF_CONTEXT_HV = (__u64)-32,
1259− PERF_CONTEXT_KERNEL = (__u64)-128,
1260− PERF_CONTEXT_USER = (__u64)-512,
1269+ PERF_CONTEXT_HV = (__u64)-32,
1270+ PERF_CONTEXT_KERNEL = (__u64)-128,
1271+ PERF_CONTEXT_USER = (__u64)-512,
12611272
1262− PERF_CONTEXT_GUEST = (__u64)-2048,
1263− PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
1264− PERF_CONTEXT_GUEST_USER = (__u64)-2560,
1273+ PERF_CONTEXT_GUEST = (__u64)-2048,
1274+ PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
1275+ PERF_CONTEXT_GUEST_USER = (__u64)-2560,
12651276
1266− PERF_CONTEXT_MAX = (__u64)-4095,
1277+ PERF_CONTEXT_MAX = (__u64)-4095,
12671278 };
12681279
12691280 /**
12701281 * PERF_RECORD_AUX::flags bits
12711282 */
1272−#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
1273−#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
1274−#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
1275−#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
1283+#define PERF_AUX_FLAG_TRUNCATED 0x0001 /* Record was truncated to fit */
1284+#define PERF_AUX_FLAG_OVERWRITE 0x0002 /* Snapshot from overwrite mode */
1285+#define PERF_AUX_FLAG_PARTIAL 0x0004 /* Record contains gaps */
1286+#define PERF_AUX_FLAG_COLLISION 0x0008 /* Sample collided with another */
12761287 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */
12771288
12781289 /* CoreSight PMU AUX buffer formats */
1279−#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
1280−#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */
1290+#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
1291+#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */
12811292
1282−#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
1283−#define PERF_FLAG_FD_OUTPUT (1UL << 1)
1284−#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
1285−#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
1293+#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
1294+#define PERF_FLAG_FD_OUTPUT (1UL << 1)
1295+#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup ID, per-CPU mode only */
1296+#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
12861297
12871298 #if defined(__LITTLE_ENDIAN_BITFIELD)
12881299 union perf_mem_data_src {
12891300 __u64 val;
12901301 struct {
1291− __u64 mem_op:5, /* type of opcode */
1292− mem_lvl:14, /* memory hierarchy level */
1293− mem_snoop:5, /* snoop mode */
1294− mem_lock:2, /* lock instr */
1295− mem_dtlb:7, /* tlb access */
1296− mem_lvl_num:4, /* memory hierarchy level number */
1297− mem_remote:1, /* remote */
1298− mem_snoopx:2, /* snoop mode, ext */
1299− mem_blk:3, /* access blocked */
1300− mem_hops:3, /* hop level */
1301− mem_rsvd:18;
1302+ __u64 mem_op : 5, /* Type of opcode */
1303+ mem_lvl : 14, /* Memory hierarchy level */
1304+ mem_snoop : 5, /* Snoop mode */
1305+ mem_lock : 2, /* Lock instr */
1306+ mem_dtlb : 7, /* TLB access */
1307+ mem_lvl_num : 4, /* Memory hierarchy level number */
1308+ mem_remote : 1, /* Remote */
1309+ mem_snoopx : 2, /* Snoop mode, ext */
1310+ mem_blk : 3, /* Access blocked */
1311+ mem_hops : 3, /* Hop level */
1312+ mem_rsvd : 18;
13021313 };
13031314 };
13041315 #elif defined(__BIG_ENDIAN_BITFIELD)
13051316 union perf_mem_data_src {
13061317 __u64 val;
13071318 struct {
1308− __u64 mem_rsvd:18,
1309− mem_hops:3, /* hop level */
1310− mem_blk:3, /* access blocked */
1311− mem_snoopx:2, /* snoop mode, ext */
1312− mem_remote:1, /* remote */
1313− mem_lvl_num:4, /* memory hierarchy level number */
1314− mem_dtlb:7, /* tlb access */
1315− mem_lock:2, /* lock instr */
1316− mem_snoop:5, /* snoop mode */
1317− mem_lvl:14, /* memory hierarchy level */
1318− mem_op:5; /* type of opcode */
1319+ __u64 mem_rsvd : 18,
1320+ mem_hops : 3, /* Hop level */
1321+ mem_blk : 3, /* Access blocked */
1322+ mem_snoopx : 2, /* Snoop mode, ext */
1323+ mem_remote : 1, /* Remote */
1324+ mem_lvl_num : 4, /* Memory hierarchy level number */
1325+ mem_dtlb : 7, /* TLB access */
1326+ mem_lock : 2, /* Lock instr */
1327+ mem_snoop : 5, /* Snoop mode */
1328+ mem_lvl : 14, /* Memory hierarchy level */
1329+ mem_op : 5; /* Type of opcode */
13191330 };
13201331 };
13211332 #else
1322−#error "Unknown endianness"
1333+# error "Unknown endianness"
13231334 #endif
13241335
1325−/* type of opcode (load/store/prefetch,code) */
1326−#define PERF_MEM_OP_NA 0x01 /* not available */
1327−#define PERF_MEM_OP_LOAD 0x02 /* load instruction */
1328−#define PERF_MEM_OP_STORE 0x04 /* store instruction */
1329−#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
1330−#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
1331−#define PERF_MEM_OP_SHIFT 0
1336+/* Type of memory opcode: */
1337+#define PERF_MEM_OP_NA 0x0001 /* Not available */
1338+#define PERF_MEM_OP_LOAD 0x0002 /* Load instruction */
1339+#define PERF_MEM_OP_STORE 0x0004 /* Store instruction */
1340+#define PERF_MEM_OP_PFETCH 0x0008 /* Prefetch */
1341+#define PERF_MEM_OP_EXEC 0x0010 /* Code (execution) */
1342+#define PERF_MEM_OP_SHIFT 0
13321343
13331344 /*
1334− * PERF_MEM_LVL_* namespace being depricated to some extent in the
1345+ * The PERF_MEM_LVL_* namespace is being deprecated to some extent in
13351346 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields.
1336− * Supporting this namespace inorder to not break defined ABIs.
1347+ * We support this namespace in order to not break defined ABIs.
13371348 *
1338− * memory hierarchy (memory level, hit or miss)
1349+ * Memory hierarchy (memory level, hit or miss)
13391350 */
1340−#define PERF_MEM_LVL_NA 0x01 /* not available */
1341−#define PERF_MEM_LVL_HIT 0x02 /* hit level */
1342−#define PERF_MEM_LVL_MISS 0x04 /* miss level */
1343−#define PERF_MEM_LVL_L1 0x08 /* L1 */
1344−#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
1345−#define PERF_MEM_LVL_L2 0x20 /* L2 */
1346−#define PERF_MEM_LVL_L3 0x40 /* L3 */
1347−#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
1348−#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
1349−#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
1350−#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
1351−#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
1352−#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1353−#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1354−#define PERF_MEM_LVL_SHIFT 5
1355−
1356−#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */
1357−#define PERF_MEM_REMOTE_SHIFT 37
1358−
1359−#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */
1360−#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
1361−#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1362−#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1363−#define PERF_MEM_LVLNUM_L2_MHB 0x05 /* L2 Miss Handling Buffer */
1364−#define PERF_MEM_LVLNUM_MSC 0x06 /* Memory-side Cache */
1365−/* 0x7 available */
1366−#define PERF_MEM_LVLNUM_UNC 0x08 /* Uncached */
1367−#define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */
1368−#define PERF_MEM_LVLNUM_IO 0x0a /* I/O */
1369−#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1370−#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB / L1 Miss Handling Buffer */
1371−#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
1372−#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */
1373−#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */
1374−
1375−#define PERF_MEM_LVLNUM_SHIFT 33
1376−
1377−/* snoop mode */
1378−#define PERF_MEM_SNOOP_NA 0x01 /* not available */
1379−#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
1380−#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
1381−#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
1382−#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
1383−#define PERF_MEM_SNOOP_SHIFT 19
1384−
1385−#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */
1386−#define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */
1387−#define PERF_MEM_SNOOPX_SHIFT 38
1388−
1389−/* locked instruction */
1390−#define PERF_MEM_LOCK_NA 0x01 /* not available */
1391−#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
1392−#define PERF_MEM_LOCK_SHIFT 24
1351+#define PERF_MEM_LVL_NA 0x0001 /* Not available */
1352+#define PERF_MEM_LVL_HIT 0x0002 /* Hit level */
1353+#define PERF_MEM_LVL_MISS 0x0004 /* Miss level */
1354+#define PERF_MEM_LVL_L1 0x0008 /* L1 */
1355+#define PERF_MEM_LVL_LFB 0x0010 /* Line Fill Buffer */
1356+#define PERF_MEM_LVL_L2 0x0020 /* L2 */
1357+#define PERF_MEM_LVL_L3 0x0040 /* L3 */
1358+#define PERF_MEM_LVL_LOC_RAM 0x0080 /* Local DRAM */
1359+#define PERF_MEM_LVL_REM_RAM1 0x0100 /* Remote DRAM (1 hop) */
1360+#define PERF_MEM_LVL_REM_RAM2 0x0200 /* Remote DRAM (2 hops) */
1361+#define PERF_MEM_LVL_REM_CCE1 0x0400 /* Remote Cache (1 hop) */
1362+#define PERF_MEM_LVL_REM_CCE2 0x0800 /* Remote Cache (2 hops) */
1363+#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1364+#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1365+#define PERF_MEM_LVL_SHIFT 5
1366+
1367+#define PERF_MEM_REMOTE_REMOTE 0x0001 /* Remote */
1368+#define PERF_MEM_REMOTE_SHIFT 37
1369+
1370+#define PERF_MEM_LVLNUM_L1 0x0001 /* L1 */
1371+#define PERF_MEM_LVLNUM_L2 0x0002 /* L2 */
1372+#define PERF_MEM_LVLNUM_L3 0x0003 /* L3 */
1373+#define PERF_MEM_LVLNUM_L4 0x0004 /* L4 */
1374+#define PERF_MEM_LVLNUM_L2_MHB 0x0005 /* L2 Miss Handling Buffer */
1375+#define PERF_MEM_LVLNUM_MSC 0x0006 /* Memory-side Cache */
1376+/* 0x007 available */
1377+#define PERF_MEM_LVLNUM_UNC 0x0008 /* Uncached */
1378+#define PERF_MEM_LVLNUM_CXL 0x0009 /* CXL */
1379+#define PERF_MEM_LVLNUM_IO 0x000a /* I/O */
1380+#define PERF_MEM_LVLNUM_ANY_CACHE 0x000b /* Any cache */
1381+#define PERF_MEM_LVLNUM_LFB 0x000c /* LFB / L1 Miss Handling Buffer */
1382+#define PERF_MEM_LVLNUM_RAM 0x000d /* RAM */
1383+#define PERF_MEM_LVLNUM_PMEM 0x000e /* PMEM */
1384+#define PERF_MEM_LVLNUM_NA 0x000f /* N/A */
1385+
1386+#define PERF_MEM_LVLNUM_SHIFT 33
1387+
1388+/* Snoop mode */
1389+#define PERF_MEM_SNOOP_NA 0x0001 /* Not available */
1390+#define PERF_MEM_SNOOP_NONE 0x0002 /* No snoop */
1391+#define PERF_MEM_SNOOP_HIT 0x0004 /* Snoop hit */
1392+#define PERF_MEM_SNOOP_MISS 0x0008 /* Snoop miss */
1393+#define PERF_MEM_SNOOP_HITM 0x0010 /* Snoop hit modified */
1394+#define PERF_MEM_SNOOP_SHIFT 19
1395+
1396+#define PERF_MEM_SNOOPX_FWD 0x0001 /* Forward */
1397+#define PERF_MEM_SNOOPX_PEER 0x0002 /* Transfer from peer */
1398+#define PERF_MEM_SNOOPX_SHIFT 38
1399+
1400+/* Locked instruction */
1401+#define PERF_MEM_LOCK_NA 0x0001 /* Not available */
1402+#define PERF_MEM_LOCK_LOCKED 0x0002 /* Locked transaction */
1403+#define PERF_MEM_LOCK_SHIFT 24
13931404
13941405 /* TLB access */
1395−#define PERF_MEM_TLB_NA 0x01 /* not available */
1396−#define PERF_MEM_TLB_HIT 0x02 /* hit level */
1397−#define PERF_MEM_TLB_MISS 0x04 /* miss level */
1398−#define PERF_MEM_TLB_L1 0x08 /* L1 */
1399−#define PERF_MEM_TLB_L2 0x10 /* L2 */
1400−#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
1401−#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
1402−#define PERF_MEM_TLB_SHIFT 26
1406+#define PERF_MEM_TLB_NA 0x0001 /* Not available */
1407+#define PERF_MEM_TLB_HIT 0x0002 /* Hit level */
1408+#define PERF_MEM_TLB_MISS 0x0004 /* Miss level */
1409+#define PERF_MEM_TLB_L1 0x0008 /* L1 */
1410+#define PERF_MEM_TLB_L2 0x0010 /* L2 */
1411+#define PERF_MEM_TLB_WK 0x0020 /* Hardware Walker*/
1412+#define PERF_MEM_TLB_OS 0x0040 /* OS fault handler */
1413+#define PERF_MEM_TLB_SHIFT 26
14031414
14041415 /* Access blocked */
1405−#define PERF_MEM_BLK_NA 0x01 /* not available */
1406−#define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */
1407−#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */
1408−#define PERF_MEM_BLK_SHIFT 40
1409−
1410−/* hop level */
1411−#define PERF_MEM_HOPS_0 0x01 /* remote core, same node */
1412−#define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */
1413−#define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */
1414−#define PERF_MEM_HOPS_3 0x04 /* remote board */
1416+#define PERF_MEM_BLK_NA 0x0001 /* Not available */
1417+#define PERF_MEM_BLK_DATA 0x0002 /* Data could not be forwarded */
1418+#define PERF_MEM_BLK_ADDR 0x0004 /* Address conflict */
1419+#define PERF_MEM_BLK_SHIFT 40
1420+
1421+/* Hop level */
1422+#define PERF_MEM_HOPS_0 0x0001 /* Remote core, same node */
1423+#define PERF_MEM_HOPS_1 0x0002 /* Remote node, same socket */
1424+#define PERF_MEM_HOPS_2 0x0003 /* Remote socket, same board */
1425+#define PERF_MEM_HOPS_3 0x0004 /* Remote board */
14151426 /* 5-7 available */
1416−#define PERF_MEM_HOPS_SHIFT 43
1427+#define PERF_MEM_HOPS_SHIFT 43
14171428
14181429 #define PERF_MEM_S(a, s) \
14191430 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
14201431
14211432 /*
1422− * single taken branch record layout:
1433+ * Layout of single taken branch records:
14231434 *
14241435 * from: source instruction (may not always be a branch insn)
14251436 * to: branch target
@@ -1438,37 +1449,37 @@ union perf_mem_data_src { · 12 unmodified lines
14381449 struct perf_branch_entry {
14391450 __u64 from;
14401451 __u64 to;
1441− __u64 mispred:1, /* target mispredicted */
1442− predicted:1,/* target predicted */
1443− in_tx:1, /* in transaction */
1444− abort:1, /* transaction abort */
1445− cycles:16, /* cycle count to last branch */
1446− type:4, /* branch type */
1447− spec:2, /* branch speculation info */
1448− new_type:4, /* additional branch type */
1449− priv:3, /* privilege level */
1450− reserved:31;
1452+ __u64 mispred : 1, /* target mispredicted */
1453+ predicted : 1, /* target predicted */
1454+ in_tx : 1, /* in transaction */
1455+ abort : 1, /* transaction abort */
1456+ cycles : 16, /* cycle count to last branch */
1457+ type : 4, /* branch type */
1458+ spec : 2, /* branch speculation info */
1459+ new_type : 4, /* additional branch type */
1460+ priv : 3, /* privilege level */
1461+ reserved : 31;
14511462 };
14521463
14531464 /* Size of used info bits in struct perf_branch_entry */
14541465 #define PERF_BRANCH_ENTRY_INFO_BITS_MAX 33
14551466
14561467 union perf_sample_weight {
1457− __u64 full;
1468+ __u64 full;
14581469 #if defined(__LITTLE_ENDIAN_BITFIELD)
14591470 struct {
1460− __u32 var1_dw;
1461− __u16 var2_w;
1462− __u16 var3_w;
1471+ __u32 var1_dw;
1472+ __u16 var2_w;
1473+ __u16 var3_w;
14631474 };
14641475 #elif defined(__BIG_ENDIAN_BITFIELD)
14651476 struct {
1466− __u16 var3_w;
1467− __u16 var2_w;
1468− __u32 var1_dw;
1477+ __u16 var3_w;
1478+ __u16 var2_w;
1479+ __u32 var1_dw;
14691480 };
14701481 #else
1471−#error "Unknown endianness"
1482+# error "Unknown endianness"
14721483 #endif
14731484 };
14741485
include/uapi/linux/pidfd.h+17−1
@@ -12,7 +12,7 @@ · 11 unmodified lines
1212 #define PIDFD_THREAD O_EXCL
1313 #ifdef __KERNEL__
1414 #include <linux/sched.h>
15−#define PIDFD_CLONE CLONE_PIDFD
15+#define PIDFD_STALE CLONE_PIDFD
1616 #endif
1717
1818 /* Flags for pidfd_send_signal(). */
@@ -25,9 +25,23 @@ · 6 unmodified lines
2525 #define PIDFD_INFO_CREDS (1UL << 1) /* Always returned, even if not requested */
2626 #define PIDFD_INFO_CGROUPID (1UL << 2) /* Always returned if available, even if not requested */
2727 #define PIDFD_INFO_EXIT (1UL << 3) /* Only returned if requested. */
28+#define PIDFD_INFO_COREDUMP (1UL << 4) /* Only returned if requested. */
2829
2930 #define PIDFD_INFO_SIZE_VER0 64 /* sizeof first published struct */
3031
32+/*
33+ * Values for @coredump_mask in pidfd_info.
34+ * Only valid if PIDFD_INFO_COREDUMP is set in @mask.
35+ *
36+ * Note, the @PIDFD_COREDUMP_ROOT flag indicates that the generated
37+ * coredump should be treated as sensitive and access should only be
38+ * granted to privileged users.
39+ */
40+#define PIDFD_COREDUMPED (1U << 0) /* Did crash and... */
41+#define PIDFD_COREDUMP_SKIP (1U << 1) /* coredumping generation was skipped. */
42+#define PIDFD_COREDUMP_USER (1U << 2) /* coredump was done as the user. */
43+#define PIDFD_COREDUMP_ROOT (1U << 3) /* coredump was done as root. */
44+
3145 /*
3246 * The concept of process and threads in userland and the kernel is a confusing
3347 * one - within the kernel every thread is a 'task' with its own individual PID,
@@ -92,6 +106,8 @@ struct pidfd_info { · 58 unmodified lines
92106 __u32 fsuid;
93107 __u32 fsgid;
94108 __s32 exit_code;
109+ __u32 coredump_mask;
110+ __u32 __spare1;
95111 };
96112
97113 #define PIDFS_IOCTL_MAGIC 0xFF
include/uapi/linux/pkt_cls.h+3−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __LINUX_PKT_CLS_H
3−#define __LINUX_PKT_CLS_H
2+#ifndef _UAPI__LINUX_PKT_CLS_H
3+#define _UAPI__LINUX_PKT_CLS_H
44
55 #include <linux/types.h>
66 #include <linux/pkt_sched.h>
@@ -697,6 +697,7 @@ enum { · 690 unmodified lines
697697 };
698698
699699 #define TCA_FLOWER_KEY_CFM_OPT_MAX (__TCA_FLOWER_KEY_CFM_OPT_MAX - 1)
700+#define TCA_FLOWER_KEY_CFM_MAX (__TCA_FLOWER_KEY_CFM_OPT_MAX - 1)
700701
701702 #define TCA_FLOWER_MASK_FLAGS_RANGE (1 << 0) /* Range-based match */
702703
include/uapi/linux/pkt_sched.h+3−2
@@ -1,6 +1,6 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2−#ifndef __LINUX_PKT_SCHED_H
3−#define __LINUX_PKT_SCHED_H
2+#ifndef _UAPI__LINUX_PKT_SCHED_H
3+#define _UAPI__LINUX_PKT_SCHED_H
44
55 #include <linux/const.h>
66 #include <linux/types.h>
@@ -1182,6 +1182,7 @@ enum { · 1175 unmodified lines
11821182 TCA_TAPRIO_ATTR_SCHED_SINGLE_ENTRY, /* single entry */
11831183 TCA_TAPRIO_ATTR_SCHED_CLOCKID, /* s32 */
11841184 TCA_TAPRIO_PAD,
1185+ TCA_TAPRIO_ATTR_PAD = TCA_TAPRIO_PAD,
11851186 TCA_TAPRIO_ATTR_ADMIN_SCHED, /* The admin sched, only used in dump */
11861187 TCA_TAPRIO_ATTR_SCHED_CYCLE_TIME, /* s64 */
11871188 TCA_TAPRIO_ATTR_SCHED_CYCLE_TIME_EXTENSION, /* s64 */
include/uapi/linux/prctl.h+7−0
@@ -364,4 +364,11 @@ struct prctl_mm_map { · 363 unmodified lines
364364 # define PR_TIMER_CREATE_RESTORE_IDS_ON 1
365365 # define PR_TIMER_CREATE_RESTORE_IDS_GET 2
366366
367+/* FUTEX hash management */
368+#define PR_FUTEX_HASH 78
369+# define PR_FUTEX_HASH_SET_SLOTS 1
370+# define FH_FLAG_IMMUTABLE (1ULL << 0)
371+# define PR_FUTEX_HASH_GET_SLOTS 2
372+# define PR_FUTEX_HASH_GET_IMMUTABLE 3
373+
367374 #endif /* _LINUX_PRCTL_H */
include/uapi/linux/ptrace.h+6−1
@@ -74,6 +74,7 @@ struct seccomp_metadata { · 73 unmodified lines
7474 };
7575
7676 #define PTRACE_GET_SYSCALL_INFO 0x420e
77+#define PTRACE_SET_SYSCALL_INFO 0x4212
7778 #define PTRACE_SYSCALL_INFO_NONE 0
7879 #define PTRACE_SYSCALL_INFO_ENTRY 1
7980 #define PTRACE_SYSCALL_INFO_EXIT 2
@@ -81,7 +82,8 @@ struct seccomp_metadata { · 1 unmodified line
8182
8283 struct ptrace_syscall_info {
8384 __u8 op; /* PTRACE_SYSCALL_INFO_* */
84− __u8 pad[3];
85+ __u8 reserved;
86+ __u16 flags;
8587 __u32 arch;
8688 __u64 instruction_pointer;
8789 __u64 stack_pointer;
@@ -98,6 +100,7 @@ struct ptrace_syscall_info { · 10 unmodified lines
98100 __u64 nr;
99101 __u64 args[6];
100102 __u32 ret_data;
103+ __u32 reserved2;
101104 } seccomp;
102105 };
103106 };
@@ -142,6 +145,8 @@ struct ptrace_sud_config { · 38 unmodified lines
142145 __u64 len;
143146 };
144147
148+/* 0x4212 is PTRACE_SET_SYSCALL_INFO */
149+
145150 /*
146151 * These values are stored in task->ptrace_message
147152 * by ptrace_stop to describe the current syscall-stop.
include/uapi/linux/rxrpc.h+65−12
@@ -36,26 +36,33 @@ struct sockaddr_rxrpc { · 35 unmodified lines
3636 #define RXRPC_MIN_SECURITY_LEVEL 4 /* minimum security level */
3737 #define RXRPC_UPGRADEABLE_SERVICE 5 /* Upgrade service[0] -> service[1] */
3838 #define RXRPC_SUPPORTED_CMSG 6 /* Get highest supported control message type */
39+#define RXRPC_MANAGE_RESPONSE 7 /* [clnt] Want to manage RESPONSE packets */
3940
4041 /*
4142 * RxRPC control messages
4243 * - If neither abort or accept are specified, the message is a data message.
4344 * - terminal messages mean that a user call ID tag can be recycled
45+ * - C/S/- indicate whether these are applicable to client, server or both
4446 * - s/r/- indicate whether these are applicable to sendmsg() and/or recvmsg()
4547 */
4648 enum rxrpc_cmsg_type {
47− RXRPC_USER_CALL_ID = 1, /* sr: user call ID specifier */
48− RXRPC_ABORT = 2, /* sr: abort request / notification [terminal] */
49− RXRPC_ACK = 3, /* -r: [Service] RPC op final ACK received [terminal] */
50− RXRPC_NET_ERROR = 5, /* -r: network error received [terminal] */
51− RXRPC_BUSY = 6, /* -r: server busy received [terminal] */
52− RXRPC_LOCAL_ERROR = 7, /* -r: local error generated [terminal] */
53− RXRPC_NEW_CALL = 8, /* -r: [Service] new incoming call notification */
54− RXRPC_EXCLUSIVE_CALL = 10, /* s-: Call should be on exclusive connection */
55− RXRPC_UPGRADE_SERVICE = 11, /* s-: Request service upgrade for client call */
56− RXRPC_TX_LENGTH = 12, /* s-: Total length of Tx data */
57− RXRPC_SET_CALL_TIMEOUT = 13, /* s-: Set one or more call timeouts */
58− RXRPC_CHARGE_ACCEPT = 14, /* s-: Charge the accept pool with a user call ID */
49+ RXRPC_USER_CALL_ID = 1, /* -sr: User call ID specifier */
50+ RXRPC_ABORT = 2, /* -sr: Abort request / notification [terminal] */
51+ RXRPC_ACK = 3, /* S-r: RPC op final ACK received [terminal] */
52+ RXRPC_NET_ERROR = 5, /* --r: Network error received [terminal] */
53+ RXRPC_BUSY = 6, /* C-r: Server busy received [terminal] */
54+ RXRPC_LOCAL_ERROR = 7, /* --r: Local error generated [terminal] */
55+ RXRPC_NEW_CALL = 8, /* S-r: New incoming call notification */
56+ RXRPC_EXCLUSIVE_CALL = 10, /* Cs-: Call should be on exclusive connection */
57+ RXRPC_UPGRADE_SERVICE = 11, /* Cs-: Request service upgrade for client call */
58+ RXRPC_TX_LENGTH = 12, /* -s-: Total length of Tx data */
59+ RXRPC_SET_CALL_TIMEOUT = 13, /* -s-: Set one or more call timeouts */
60+ RXRPC_CHARGE_ACCEPT = 14, /* Ss-: Charge the accept pool with a user call ID */
61+ RXRPC_OOB_ID = 15, /* -sr: OOB message ID */
62+ RXRPC_CHALLENGED = 16, /* C-r: Info on a received CHALLENGE */
63+ RXRPC_RESPOND = 17, /* Cs-: Respond to a challenge */
64+ RXRPC_RESPONDED = 18, /* S-r: Data received in RESPONSE */
65+ RXRPC_RESP_RXGK_APPDATA = 19, /* Cs-: RESPONSE: RxGK app data to include */
5966 RXRPC__SUPPORTED
6067 };
6168
@@ -73,6 +80,7 @@ enum rxrpc_cmsg_type { · 11 unmodified lines
7380 #define RXRPC_SECURITY_RXKAD 2 /* kaserver or kerberos 4 */
7481 #define RXRPC_SECURITY_RXGK 4 /* gssapi-based */
7582 #define RXRPC_SECURITY_RXK5 5 /* kerberos 5 */
83+#define RXRPC_SECURITY_YFS_RXGK 6 /* YFS gssapi-based */
7684
7785 /*
7886 * RxRPC-level abort codes
@@ -118,4 +126,49 @@ enum rxrpc_cmsg_type { · 39 unmodified lines
118126 #define RXKADDATALEN 19270411 /* user data too long */
119127 #define RXKADILLEGALLEVEL 19270412 /* caller not authorised to use encrypted conns */
120128
129+/*
130+ * RxGK GSSAPI security abort codes.
131+ */
132+#if 0 /* Original standard abort codes (used by OpenAFS) */
133+#define RXGK_INCONSISTENCY 1233242880 /* Security module structure inconsistent */
134+#define RXGK_PACKETSHORT 1233242881 /* Packet too short for security challenge */
135+#define RXGK_BADCHALLENGE 1233242882 /* Invalid security challenge */
136+#define RXGK_BADETYPE 1233242883 /* Invalid or impermissible encryption type */
137+#define RXGK_BADLEVEL 1233242884 /* Invalid or impermissible security level */
138+#define RXGK_BADKEYNO 1233242885 /* Key version number not found */
139+#define RXGK_EXPIRED 1233242886 /* Token has expired */
140+#define RXGK_NOTAUTH 1233242887 /* Caller not authorized */
141+#define RXGK_BAD_TOKEN 1233242888 /* Security object was passed a bad token */
142+#define RXGK_SEALED_INCON 1233242889 /* Sealed data inconsistent */
143+#define RXGK_DATA_LEN 1233242890 /* User data too long */
144+#define RXGK_BAD_QOP 1233242891 /* Inadequate quality of protection available */
145+#else /* Revised standard abort codes (used by YFS) */
146+#define RXGK_INCONSISTENCY 1233242880 /* Security module structure inconsistent */
147+#define RXGK_PACKETSHORT 1233242881 /* Packet too short for security challenge */
148+#define RXGK_BADCHALLENGE 1233242882 /* Security challenge/response failed */
149+#define RXGK_SEALEDINCON 1233242883 /* Sealed data is inconsistent */
150+#define RXGK_NOTAUTH 1233242884 /* Caller not authorised */
151+#define RXGK_EXPIRED 1233242885 /* Authentication expired */
152+#define RXGK_BADLEVEL 1233242886 /* Unsupported or not permitted security level */
153+#define RXGK_BADKEYNO 1233242887 /* Bad transport key number */
154+#define RXGK_NOTRXGK 1233242888 /* Security layer is not rxgk */
155+#define RXGK_UNSUPPORTED 1233242889 /* Endpoint does not support rxgk */
156+#define RXGK_GSSERROR 1233242890 /* GSSAPI mechanism error */
157+#endif
158+
159+/*
160+ * Challenge information in the RXRPC_CHALLENGED control message.
161+ */
162+struct rxrpc_challenge {
163+ __u16 service_id; /* The service ID of the connection (may be upgraded) */
164+ __u8 security_index; /* The security index of the connection */
165+ __u8 pad; /* Round out to a multiple of 4 bytes. */
166+ /* ... The security class gets to append extra information ... */
167+};
168+
169+struct rxgk_challenge {
170+ struct rxrpc_challenge base;
171+ __u32 enctype; /* Krb5 encoding type */
172+};
173+
121174 #endif /* _UAPI_LINUX_RXRPC_H */
include/uapi/linux/snmp.h+1−0
@@ -188,6 +188,7 @@ enum · 187 unmodified lines
188188 LINUX_MIB_PAWSESTABREJECTED, /* PAWSEstabRejected */
189189 LINUX_MIB_TSECRREJECTED, /* TSEcrRejected */
190190 LINUX_MIB_PAWS_OLD_ACK, /* PAWSOldAck */
191+ LINUX_MIB_PAWS_TW_REJECTED, /* PAWSTimewait */
191192 LINUX_MIB_DELAYEDACKS, /* DelayedACKs */
192193 LINUX_MIB_DELAYEDACKLOCKED, /* DelayedACKLocked */
193194 LINUX_MIB_DELAYEDACKLOST, /* DelayedACKLost */
include/uapi/linux/stat.h+6−2
@@ -182,8 +182,12 @@ struct statx { · 181 unmodified lines
182182 /* File offset alignment for direct I/O reads */
183183 __u32 stx_dio_read_offset_align;
184184
185− /* 0xb8 */
186− __u64 __spare3[9]; /* Spare space for future expansion */
185+ /* Optimised max atomic write unit in bytes */
186+ __u32 stx_atomic_write_unit_max_opt;
187+ __u32 __spare2[1];
188+
189+ /* 0xc0 */
190+ __u64 __spare3[8]; /* Spare space for future expansion */
187191
188192 /* 0x100 */
189193 };
include/uapi/linux/taskstats.h+29−18
@@ -34,7 +34,7 @@ · 33 unmodified lines
3434 */
3535
3636
37−#define TASKSTATS_VERSION 15
37+#define TASKSTATS_VERSION 16
3838 #define TS_COMM_LEN 32 /* should be >= TASK_COMM_LEN
3939 * in linux/sched.h */
4040
@@ -72,8 +72,6 @@ struct taskstats { · 31 unmodified lines
7272 */
7373 __u64 cpu_count __attribute__((aligned(8)));
7474 __u64 cpu_delay_total;
75− __u64 cpu_delay_max;
76− __u64 cpu_delay_min;
7775
7876 /* Following four fields atomically updated using task->delays->lock */
7977
@@ -82,14 +80,10 @@ struct taskstats { · 2 unmodified lines
8280 */
8381 __u64 blkio_count;
8482 __u64 blkio_delay_total;
85− __u64 blkio_delay_max;
86− __u64 blkio_delay_min;
8783
8884 /* Delay waiting for page fault I/O (swap in only) */
8985 __u64 swapin_count;
9086 __u64 swapin_delay_total;
91− __u64 swapin_delay_max;
92− __u64 swapin_delay_min;
9387
9488 /* cpu "wall-clock" running time
9589 * On some architectures, value will adjust for cpu time stolen
@@ -172,14 +166,11 @@ struct taskstats { · 76 unmodified lines
172166 /* Delay waiting for memory reclaim */
173167 __u64 freepages_count;
174168 __u64 freepages_delay_total;
175− __u64 freepages_delay_max;
176− __u64 freepages_delay_min;
169+
177170
178171 /* Delay waiting for thrashing page */
179172 __u64 thrashing_count;
180173 __u64 thrashing_delay_total;
181− __u64 thrashing_delay_max;
182− __u64 thrashing_delay_min;
183174
184175 /* v10: 64-bit btime to avoid overflow */
185176 __u64 ac_btime64; /* 64-bit begin time */
@@ -187,8 +178,6 @@ struct taskstats { · 1 unmodified line
187178 /* v11: Delay waiting for memory compact */
188179 __u64 compact_count;
189180 __u64 compact_delay_total;
190− __u64 compact_delay_max;
191− __u64 compact_delay_min;
192181
193182 /* v12 begin */
194183 __u32 ac_tgid; /* thread group ID */
@@ -210,15 +199,37 @@ struct taskstats { · 15 unmodified lines
210199 /* v13: Delay waiting for write-protect copy */
211200 __u64 wpcopy_count;
212201 __u64 wpcopy_delay_total;
213− __u64 wpcopy_delay_max;
214− __u64 wpcopy_delay_min;
215202
216203 /* v14: Delay waiting for IRQ/SOFTIRQ */
217204 __u64 irq_count;
218205 __u64 irq_delay_total;
219− __u64 irq_delay_max;
220− __u64 irq_delay_min;
221− /* v15: add Delay max */
206+
207+ /* v15: add Delay max and Delay min */
208+
209+ /* v16: move Delay max and Delay min to the end of taskstat */
210+ __u64 cpu_delay_max;
211+ __u64 cpu_delay_min;
212+
213+ __u64 blkio_delay_max;
214+ __u64 blkio_delay_min;
215+
216+ __u64 swapin_delay_max;
217+ __u64 swapin_delay_min;
218+
219+ __u64 freepages_delay_max;
220+ __u64 freepages_delay_min;
221+
222+ __u64 thrashing_delay_max;
223+ __u64 thrashing_delay_min;
224+
225+ __u64 compact_delay_max;
226+ __u64 compact_delay_min;
227+
228+ __u64 wpcopy_delay_max;
229+ __u64 wpcopy_delay_min;
230+
231+ __u64 irq_delay_max;
232+ __u64 irq_delay_min;
222233 };
223234
224235
include/uapi/linux/tcp.h+1−0
@@ -184,6 +184,7 @@ enum tcp_fastopen_client_fail { · 183 unmodified lines
184184 #define TCPI_OPT_ECN_SEEN 16 /* we received at least one packet with ECT */
185185 #define TCPI_OPT_SYN_DATA 32 /* SYN-ACK acked data in SYN sent or rcvd */
186186 #define TCPI_OPT_USEC_TS 64 /* usec timestamps */
187+#define TCPI_OPT_TFO_CHILD 128 /* child from a Fast Open option on SYN */
187188
188189 /*
189190 * Sender's congestion state indicating normal or abnormal situations
include/uapi/linux/tiocl.h+1−0
@@ -36,5 +36,6 @@ struct tiocl_selection { · 35 unmodified lines
3636 #define TIOCL_BLANKSCREEN 14 /* keep screen blank even if a key is pressed */
3737 #define TIOCL_BLANKEDSCREEN 15 /* return which vt was blanked */
3838 #define TIOCL_GETKMSGREDIRECT 17 /* get the vt the kernel messages are restricted to */
39+#define TIOCL_GETBRACKETEDPASTE 18 /* get whether paste may be bracketed */
3940
4041 #endif /* _LINUX_TIOCL_H */
include/uapi/linux/ublk_cmd.h+137−0
@@ -51,6 +51,10 @@ · 50 unmodified lines
5151 _IOR('u', 0x13, struct ublksrv_ctrl_cmd)
5252 #define UBLK_U_CMD_DEL_DEV_ASYNC \
5353 _IOR('u', 0x14, struct ublksrv_ctrl_cmd)
54+#define UBLK_U_CMD_UPDATE_SIZE \
55+ _IOWR('u', 0x15, struct ublksrv_ctrl_cmd)
56+#define UBLK_U_CMD_QUIESCE_DEV \
57+ _IOWR('u', 0x16, struct ublksrv_ctrl_cmd)
5458
5559 /*
5660 * 64bits are enough now, and it should be easy to extend in case of
@@ -211,6 +215,72 @@ · 154 unmodified lines
211215 */
212216 #define UBLK_F_USER_RECOVERY_FAIL_IO (1ULL << 9)
213217
218+/*
219+ * Resizing a block device is possible with UBLK_U_CMD_UPDATE_SIZE
220+ * New size is passed in cmd->data[0] and is in units of sectors
221+ */
222+#define UBLK_F_UPDATE_SIZE (1ULL << 10)
223+
224+/*
225+ * request buffer is registered automatically to uring_cmd's io_uring
226+ * context before delivering this io command to ublk server, meantime
227+ * it is un-registered automatically when completing this io command.
228+ *
229+ * For using this feature:
230+ *
231+ * - ublk server has to create sparse buffer table on the same `io_ring_ctx`
232+ * for issuing `UBLK_IO_FETCH_REQ` and `UBLK_IO_COMMIT_AND_FETCH_REQ`.
233+ * If uring_cmd isn't issued on same `io_ring_ctx`, it is ublk server's
234+ * responsibility to unregister the buffer by issuing `IO_UNREGISTER_IO_BUF`
235+ * manually, otherwise this ublk request won't complete.
236+ *
237+ * - ublk server passes auto buf register data via uring_cmd's sqe->addr,
238+ * `struct ublk_auto_buf_reg` is populated from sqe->addr, please see
239+ * the definition of ublk_sqe_addr_to_auto_buf_reg()
240+ *
241+ * - pass buffer index from `ublk_auto_buf_reg.index`
242+ *
243+ * - all reserved fields in `ublk_auto_buf_reg` need to be zeroed
244+ *
245+ * - pass flags from `ublk_auto_buf_reg.flags` if needed
246+ *
247+ * This way avoids extra cost from two uring_cmd, but also simplifies backend
248+ * implementation, such as, the dependency on IO_REGISTER_IO_BUF and
249+ * IO_UNREGISTER_IO_BUF becomes not necessary.
250+ *
251+ * If wrong data or flags are provided, both IO_FETCH_REQ and
252+ * IO_COMMIT_AND_FETCH_REQ are failed, for the latter, the ublk IO request
253+ * won't be completed until new IO_COMMIT_AND_FETCH_REQ command is issued
254+ * successfully
255+ */
256+#define UBLK_F_AUTO_BUF_REG (1ULL << 11)
257+
258+/*
259+ * Control command `UBLK_U_CMD_QUIESCE_DEV` is added for quiescing device,
260+ * which state can be transitioned to `UBLK_S_DEV_QUIESCED` or
261+ * `UBLK_S_DEV_FAIL_IO` finally, and it needs ublk server cooperation for
262+ * handling `UBLK_IO_RES_ABORT` correctly.
263+ *
264+ * Typical use case is for supporting to upgrade ublk server application,
265+ * meantime keep ublk block device persistent during the period.
266+ *
267+ * This feature is only available when UBLK_F_USER_RECOVERY is enabled.
268+ *
269+ * Note, this command returns -EBUSY in case that all IO commands are being
270+ * handled by ublk server and not completed in specified time period which
271+ * is passed from the control command parameter.
272+ */
273+#define UBLK_F_QUIESCE (1ULL << 12)
274+
275+/*
276+ * If this feature is set, ublk_drv supports each (qid,tag) pair having
277+ * its own independent daemon task that is responsible for handling it.
278+ * If it is not set, daemons are per-queue instead, so for two pairs
279+ * (qid1,tag1) and (qid2,tag2), if qid1 == qid2, then the same task must
280+ * be responsible for handling (qid1,tag1) and (qid2,tag2).
281+ */
282+#define UBLK_F_PER_IO_DAEMON (1ULL << 13)
283+
214284 /* device state */
215285 #define UBLK_S_DEV_DEAD 0
216286 #define UBLK_S_DEV_LIVE 1
@@ -297,6 +367,17 @@ struct ublksrv_ctrl_dev_info { · 80 unmodified lines
297367 #define UBLK_IO_F_FUA (1U << 13)
298368 #define UBLK_IO_F_NOUNMAP (1U << 15)
299369 #define UBLK_IO_F_SWAP (1U << 16)
370+/*
371+ * For UBLK_F_AUTO_BUF_REG & UBLK_AUTO_BUF_REG_FALLBACK only.
372+ *
373+ * This flag is set if auto buffer register is failed & ublk server passes
374+ * UBLK_AUTO_BUF_REG_FALLBACK, and ublk server need to register buffer
375+ * manually for handling the delivered IO command if this flag is observed
376+ *
377+ * ublk server has to check this flag if UBLK_AUTO_BUF_REG_FALLBACK is
378+ * passed in.
379+ */
380+#define UBLK_IO_F_NEED_REG_BUF (1U << 17)
300381
301382 /*
302383 * io cmd is described by this structure, and stored in share memory, indexed
@@ -331,6 +412,62 @@ static inline __u32 ublksrv_get_flags(const struct ublksrv_io_desc *iod) · 28 unmodified lines
331412 return iod->op_flags >> 8;
332413 }
333414
415+/*
416+ * If this flag is set, fallback by completing the uring_cmd and setting
417+ * `UBLK_IO_F_NEED_REG_BUF` in case of auto-buf-register failure;
418+ * otherwise the client ublk request is failed silently
419+ *
420+ * If ublk server passes this flag, it has to check if UBLK_IO_F_NEED_REG_BUF
421+ * is set in `ublksrv_io_desc.op_flags`. If UBLK_IO_F_NEED_REG_BUF is set,
422+ * ublk server needs to register io buffer manually for handling IO command.
423+ */
424+#define UBLK_AUTO_BUF_REG_FALLBACK (1 << 0)
425+#define UBLK_AUTO_BUF_REG_F_MASK UBLK_AUTO_BUF_REG_FALLBACK
426+
427+struct ublk_auto_buf_reg {
428+ /* index for registering the delivered request buffer */
429+ __u16 index;
430+ __u8 flags;
431+ __u8 reserved0;
432+
433+ /*
434+ * io_ring FD can be passed via the reserve field in future for
435+ * supporting to register io buffer to external io_uring
436+ */
437+ __u32 reserved1;
438+};
439+
440+/*
441+ * For UBLK_F_AUTO_BUF_REG, auto buffer register data is carried via
442+ * uring_cmd's sqe->addr:
443+ *
444+ * - bit0 ~ bit15: buffer index
445+ * - bit16 ~ bit23: flags
446+ * - bit24 ~ bit31: reserved0
447+ * - bit32 ~ bit63: reserved1
448+ */
449+static inline struct ublk_auto_buf_reg ublk_sqe_addr_to_auto_buf_reg(
450+ __u64 sqe_addr)
451+{
452+ struct ublk_auto_buf_reg reg = {
453+ .index = sqe_addr & 0xffff,
454+ .flags = (sqe_addr >> 16) & 0xff,
455+ .reserved0 = (sqe_addr >> 24) & 0xff,
456+ .reserved1 = sqe_addr >> 32,
457+ };
458+
459+ return reg;
460+}
461+
462+static inline __u64
463+ublk_auto_buf_reg_to_sqe_addr(const struct ublk_auto_buf_reg *buf)
464+{
465+ __u64 addr = buf->index | (__u64)buf->flags << 16 | (__u64)buf->reserved0 << 24 |
466+ (__u64)buf->reserved1 << 32;
467+
468+ return addr;
469+}
470+
334471 /* issued to ublk driver via /dev/ublkcN */
335472 struct ublksrv_io_cmd {
336473 __u16 q_id;
include/uapi/linux/udp.h+1−0
@@ -43,5 +43,6 @@ struct udphdr { · 42 unmodified lines
4343 #define UDP_ENCAP_GTP1U 5 /* 3GPP TS 29.060 */
4444 #define UDP_ENCAP_RXRPC 6
4545 #define TCP_ENCAP_ESPINTCP 7 /* Yikes, this is really xfrm encap types. */
46+#define UDP_ENCAP_OVPNINUDP 8 /* OpenVPN traffic */
4647
4748 #endif /* _UAPI_LINUX_UDP_H */
include/uapi/linux/videodev2.h+16−2
@@ -153,10 +153,18 @@ enum v4l2_buf_type { · 152 unmodified lines
153153 V4L2_BUF_TYPE_SDR_OUTPUT = 12,
154154 V4L2_BUF_TYPE_META_CAPTURE = 13,
155155 V4L2_BUF_TYPE_META_OUTPUT = 14,
156+ /*
157+ * Note: V4L2_TYPE_IS_VALID and V4L2_TYPE_IS_OUTPUT must
158+ * be updated if a new type is added.
159+ */
156160 /* Deprecated, do not use */
157161 V4L2_BUF_TYPE_PRIVATE = 0x80,
158162 };
159163
164+#define V4L2_TYPE_IS_VALID(type) \
165+ ((type) >= V4L2_BUF_TYPE_VIDEO_CAPTURE &&\
166+ (type) <= V4L2_BUF_TYPE_META_OUTPUT)
167+
160168 #define V4L2_TYPE_IS_MULTIPLANAR(type) \
161169 ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE \
162170 || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
@@ -164,14 +172,14 @@ enum v4l2_buf_type { · 1 unmodified line
164172 #define V4L2_TYPE_IS_OUTPUT(type) \
165173 ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT \
166174 || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE \
167− || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY \
168175 || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY \
169176 || (type) == V4L2_BUF_TYPE_VBI_OUTPUT \
170177 || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT \
171178 || (type) == V4L2_BUF_TYPE_SDR_OUTPUT \
172179 || (type) == V4L2_BUF_TYPE_META_OUTPUT)
173180
174−#define V4L2_TYPE_IS_CAPTURE(type) (!V4L2_TYPE_IS_OUTPUT(type))
181+#define V4L2_TYPE_IS_CAPTURE(type) \
182+ (V4L2_TYPE_IS_VALID(type) && !V4L2_TYPE_IS_OUTPUT(type))
175183
176184 enum v4l2_tuner_type {
177185 V4L2_TUNER_RADIO = 1,
@@ -643,8 +651,10 @@ struct v4l2_pix_format { · 465 unmodified lines
643651 /* two planes -- one Y, one Cr + Cb interleaved */
644652 #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
645653 #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
654+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
646655 #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
647656 #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
657+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */
648658 #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
649659 #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
650660 #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */
@@ -858,6 +868,10 @@ struct v4l2_pix_format { · 207 unmodified lines
858868 #define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A Statistics */
859869 #define V4L2_META_FMT_RK_ISP1_EXT_PARAMS v4l2_fourcc('R', 'K', '1', 'E') /* Rockchip ISP1 3a Extensible Parameters */
860870
871+/* Vendor specific - used for C3_ISP */
872+#define V4L2_META_FMT_C3ISP_PARAMS v4l2_fourcc('C', '3', 'P', 'M') /* Amlogic C3 ISP Parameters */
873+#define V4L2_META_FMT_C3ISP_STATS v4l2_fourcc('C', '3', 'S', 'T') /* Amlogic C3 ISP Statistics */
874+
861875 /* Vendor specific - used for RaspberryPi PiSP */
862876 #define V4L2_META_FMT_RPI_BE_CFG v4l2_fourcc('R', 'P', 'B', 'C') /* PiSP BE configuration */
863877 #define V4L2_META_FMT_RPI_FE_CFG v4l2_fourcc('R', 'P', 'F', 'C') /* PiSP FE configuration */
include/uapi/linux/virtio_gpu.h+2−1
@@ -309,8 +309,9 @@ struct virtio_gpu_cmd_submit { · 308 unmodified lines
309309
310310 #define VIRTIO_GPU_CAPSET_VIRGL 1
311311 #define VIRTIO_GPU_CAPSET_VIRGL2 2
312−/* 3 is reserved for gfxstream */
312+#define VIRTIO_GPU_CAPSET_GFXSTREAM_VULKAN 3
313313 #define VIRTIO_GPU_CAPSET_VENUS 4
314+#define VIRTIO_GPU_CAPSET_CROSS_DOMAIN 5
314315 #define VIRTIO_GPU_CAPSET_DRM 6
315316
316317 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
include/uapi/linux/virtio_rtc.h+237−0
@@ -0,0 +1,237 @@
1+/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) */
2+/*
3+ * Copyright (C) 2022-2024 OpenSynergy GmbH
4+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
5+ */
6+
7+#ifndef _LINUX_VIRTIO_RTC_H
8+#define _LINUX_VIRTIO_RTC_H
9+
10+#include <linux/types.h>
11+
12+/* alarm feature */
13+#define VIRTIO_RTC_F_ALARM 0
14+
15+/* read request message types */
16+
17+#define VIRTIO_RTC_REQ_READ 0x0001
18+#define VIRTIO_RTC_REQ_READ_CROSS 0x0002
19+
20+/* control request message types */
21+
22+#define VIRTIO_RTC_REQ_CFG 0x1000
23+#define VIRTIO_RTC_REQ_CLOCK_CAP 0x1001
24+#define VIRTIO_RTC_REQ_CROSS_CAP 0x1002
25+#define VIRTIO_RTC_REQ_READ_ALARM 0x1003
26+#define VIRTIO_RTC_REQ_SET_ALARM 0x1004
27+#define VIRTIO_RTC_REQ_SET_ALARM_ENABLED 0x1005
28+
29+/* alarmq message types */
30+
31+#define VIRTIO_RTC_NOTIF_ALARM 0x2000
32+
33+/* Message headers */
34+
35+/** common request header */
36+struct virtio_rtc_req_head {
37+ __le16 msg_type;
38+ __u8 reserved[6];
39+};
40+
41+/** common response header */
42+struct virtio_rtc_resp_head {
43+#define VIRTIO_RTC_S_OK 0
44+#define VIRTIO_RTC_S_EOPNOTSUPP 2
45+#define VIRTIO_RTC_S_ENODEV 3
46+#define VIRTIO_RTC_S_EINVAL 4
47+#define VIRTIO_RTC_S_EIO 5
48+ __u8 status;
49+ __u8 reserved[7];
50+};
51+
52+/** common notification header */
53+struct virtio_rtc_notif_head {
54+ __le16 msg_type;
55+ __u8 reserved[6];
56+};
57+
58+/* read requests */
59+
60+/* VIRTIO_RTC_REQ_READ message */
61+
62+struct virtio_rtc_req_read {
63+ struct virtio_rtc_req_head head;
64+ __le16 clock_id;
65+ __u8 reserved[6];
66+};
67+
68+struct virtio_rtc_resp_read {
69+ struct virtio_rtc_resp_head head;
70+ __le64 clock_reading;
71+};
72+
73+/* VIRTIO_RTC_REQ_READ_CROSS message */
74+
75+struct virtio_rtc_req_read_cross {
76+ struct virtio_rtc_req_head head;
77+ __le16 clock_id;
78+/* Arm Generic Timer Counter-timer Virtual Count Register (CNTVCT_EL0) */
79+#define VIRTIO_RTC_COUNTER_ARM_VCT 0
80+/* x86 Time-Stamp Counter */
81+#define VIRTIO_RTC_COUNTER_X86_TSC 1
82+/* Invalid */
83+#define VIRTIO_RTC_COUNTER_INVALID 0xFF
84+ __u8 hw_counter;
85+ __u8 reserved[5];
86+};
87+
88+struct virtio_rtc_resp_read_cross {
89+ struct virtio_rtc_resp_head head;
90+ __le64 clock_reading;
91+ __le64 counter_cycles;
92+};
93+
94+/* control requests */
95+
96+/* VIRTIO_RTC_REQ_CFG message */
97+
98+struct virtio_rtc_req_cfg {
99+ struct virtio_rtc_req_head head;
100+ /* no request params */
101+};
102+
103+struct virtio_rtc_resp_cfg {
104+ struct virtio_rtc_resp_head head;
105+ /** # of clocks -> clock ids < num_clocks are valid */
106+ __le16 num_clocks;
107+ __u8 reserved[6];
108+};
109+
110+/* VIRTIO_RTC_REQ_CLOCK_CAP message */
111+
112+struct virtio_rtc_req_clock_cap {
113+ struct virtio_rtc_req_head head;
114+ __le16 clock_id;
115+ __u8 reserved[6];
116+};
117+
118+struct virtio_rtc_resp_clock_cap {
119+ struct virtio_rtc_resp_head head;
120+#define VIRTIO_RTC_CLOCK_UTC 0
121+#define VIRTIO_RTC_CLOCK_TAI 1
122+#define VIRTIO_RTC_CLOCK_MONOTONIC 2
123+#define VIRTIO_RTC_CLOCK_UTC_SMEARED 3
124+#define VIRTIO_RTC_CLOCK_UTC_MAYBE_SMEARED 4
125+ __u8 type;
126+#define VIRTIO_RTC_SMEAR_UNSPECIFIED 0
127+#define VIRTIO_RTC_SMEAR_NOON_LINEAR 1
128+#define VIRTIO_RTC_SMEAR_UTC_SLS 2
129+ __u8 leap_second_smearing;
130+#define VIRTIO_RTC_FLAG_ALARM_CAP (1 << 0)
131+ __u8 flags;
132+ __u8 reserved[5];
133+};
134+
135+/* VIRTIO_RTC_REQ_CROSS_CAP message */
136+
137+struct virtio_rtc_req_cross_cap {
138+ struct virtio_rtc_req_head head;
139+ __le16 clock_id;
140+ __u8 hw_counter;
141+ __u8 reserved[5];
142+};
143+
144+struct virtio_rtc_resp_cross_cap {
145+ struct virtio_rtc_resp_head head;
146+#define VIRTIO_RTC_FLAG_CROSS_CAP (1 << 0)
147+ __u8 flags;
148+ __u8 reserved[7];
149+};
150+
151+/* VIRTIO_RTC_REQ_READ_ALARM message */
152+
153+struct virtio_rtc_req_read_alarm {
154+ struct virtio_rtc_req_head head;
155+ __le16 clock_id;
156+ __u8 reserved[6];
157+};
158+
159+struct virtio_rtc_resp_read_alarm {
160+ struct virtio_rtc_resp_head head;
161+ __le64 alarm_time;
162+#define VIRTIO_RTC_FLAG_ALARM_ENABLED (1 << 0)
163+ __u8 flags;
164+ __u8 reserved[7];
165+};
166+
167+/* VIRTIO_RTC_REQ_SET_ALARM message */
168+
169+struct virtio_rtc_req_set_alarm {
170+ struct virtio_rtc_req_head head;
171+ __le64 alarm_time;
172+ __le16 clock_id;
173+ /* flag VIRTIO_RTC_FLAG_ALARM_ENABLED */
174+ __u8 flags;
175+ __u8 reserved[5];
176+};
177+
178+struct virtio_rtc_resp_set_alarm {
179+ struct virtio_rtc_resp_head head;
180+ /* no response params */
181+};
182+
183+/* VIRTIO_RTC_REQ_SET_ALARM_ENABLED message */
184+
185+struct virtio_rtc_req_set_alarm_enabled {
186+ struct virtio_rtc_req_head head;
187+ __le16 clock_id;
188+ /* flag VIRTIO_RTC_ALARM_ENABLED */
189+ __u8 flags;
190+ __u8 reserved[5];
191+};
192+
193+struct virtio_rtc_resp_set_alarm_enabled {
194+ struct virtio_rtc_resp_head head;
195+ /* no response params */
196+};
197+
198+/** Union of request types for requestq */
199+union virtio_rtc_req_requestq {
200+ struct virtio_rtc_req_read read;
201+ struct virtio_rtc_req_read_cross read_cross;
202+ struct virtio_rtc_req_cfg cfg;
203+ struct virtio_rtc_req_clock_cap clock_cap;
204+ struct virtio_rtc_req_cross_cap cross_cap;
205+ struct virtio_rtc_req_read_alarm read_alarm;
206+ struct virtio_rtc_req_set_alarm set_alarm;
207+ struct virtio_rtc_req_set_alarm_enabled set_alarm_enabled;
208+};
209+
210+/** Union of response types for requestq */
211+union virtio_rtc_resp_requestq {
212+ struct virtio_rtc_resp_read read;
213+ struct virtio_rtc_resp_read_cross read_cross;
214+ struct virtio_rtc_resp_cfg cfg;
215+ struct virtio_rtc_resp_clock_cap clock_cap;
216+ struct virtio_rtc_resp_cross_cap cross_cap;
217+ struct virtio_rtc_resp_read_alarm read_alarm;
218+ struct virtio_rtc_resp_set_alarm set_alarm;
219+ struct virtio_rtc_resp_set_alarm_enabled set_alarm_enabled;
220+};
221+
222+/* alarmq notifications */
223+
224+/* VIRTIO_RTC_NOTIF_ALARM notification */
225+
226+struct virtio_rtc_notif_alarm {
227+ struct virtio_rtc_notif_head head;
228+ __le16 clock_id;
229+ __u8 reserved[6];
230+};
231+
232+/** Union of notification types for alarmq */
233+union virtio_rtc_notif_alarmq {
234+ struct virtio_rtc_notif_alarm alarm;
235+};
236+
237+#endif /* _LINUX_VIRTIO_RTC_H */
include/uapi/linux/vt.h+11−0
@@ -2,6 +2,8 @@ · 1 unmodified line
22 #ifndef _UAPI_LINUX_VT_H
33 #define _UAPI_LINUX_VT_H
44
5+#include <linux/ioctl.h>
6+#include <linux/types.h>
57
68 /*
79 * These constants are also useful for user-level apps (e.g., VC
@@ -84,4 +86,13 @@ struct vt_setactivate { · 76 unmodified lines
8486
8587 #define VT_SETACTIVATE 0x560F /* Activate and set the mode of a console */
8688
89+/* get console size and cursor position */
90+struct vt_consizecsrpos {
91+ __u16 con_rows; /* number of console rows */
92+ __u16 con_cols; /* number of console columns */
93+ __u16 csr_row; /* current cursor's row */
94+ __u16 csr_col; /* current cursor's column */
95+};
96+#define VT_GETCONSIZECSRPOS _IOR('V', 0x10, struct vt_consizecsrpos)
97+
8798 #endif /* _UAPI_LINUX_VT_H */
include/uapi/linux/wireguard.h+9−0
@@ -101,6 +101,10 @@ · 100 unmodified lines
101101 * WGALLOWEDIP_A_FAMILY: NLA_U16
102102 * WGALLOWEDIP_A_IPADDR: struct in_addr or struct in6_addr
103103 * WGALLOWEDIP_A_CIDR_MASK: NLA_U8
104+ * WGALLOWEDIP_A_FLAGS: NLA_U32, WGALLOWEDIP_F_REMOVE_ME if
105+ * the specified IP should be removed;
106+ * otherwise, this IP will be added if
107+ * it is not already present.
104108 * 0: NLA_NESTED
105109 * ...
106110 * 0: NLA_NESTED
@@ -184,11 +188,16 @@ enum wgpeer_attribute { · 77 unmodified lines
184188 };
185189 #define WGPEER_A_MAX (__WGPEER_A_LAST - 1)
186190
191+enum wgallowedip_flag {
192+ WGALLOWEDIP_F_REMOVE_ME = 1U << 0,
193+ __WGALLOWEDIP_F_ALL = WGALLOWEDIP_F_REMOVE_ME
194+};
187195 enum wgallowedip_attribute {
188196 WGALLOWEDIP_A_UNSPEC,
189197 WGALLOWEDIP_A_FAMILY,
190198 WGALLOWEDIP_A_IPADDR,
191199 WGALLOWEDIP_A_CIDR_MASK,
200+ WGALLOWEDIP_A_FLAGS,
192201 __WGALLOWEDIP_A_LAST
193202 };
194203 #define WGALLOWEDIP_A_MAX (__WGALLOWEDIP_A_LAST - 1)
include/uapi/misc/amd-apml.h+152−0
@@ -0,0 +1,152 @@
1+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2+/*
3+ * Copyright (C) 2021-2024 Advanced Micro Devices, Inc.
4+ */
5+#ifndef _AMD_APML_H_
6+#define _AMD_APML_H_
7+
8+#include <linux/types.h>
9+
10+/* Mailbox data size for data_in and data_out */
11+#define AMD_SBI_MB_DATA_SIZE 4
12+
13+struct apml_mbox_msg {
14+ /*
15+ * Mailbox Message ID
16+ */
17+ __u32 cmd;
18+ /*
19+ * [0]...[3] mailbox 32bit input/output data
20+ */
21+ __u32 mb_in_out;
22+ /*
23+ * Error code is returned in case of soft mailbox error
24+ */
25+ __u32 fw_ret_code;
26+};
27+
28+struct apml_cpuid_msg {
29+ /*
30+ * CPUID input
31+ * [0]...[3] cpuid func,
32+ * [4][5] cpuid: thread
33+ * [6] cpuid: ext function & read eax/ebx or ecx/edx
34+ * [7:0] -> bits [7:4] -> ext function &
35+ * bit [0] read eax/ebx or ecx/edx
36+ * CPUID output
37+ */
38+ __u64 cpu_in_out;
39+ /*
40+ * Status code for CPUID read
41+ */
42+ __u32 fw_ret_code;
43+ __u32 pad;
44+};
45+
46+struct apml_mcamsr_msg {
47+ /*
48+ * MCAMSR input
49+ * [0]...[3] mca msr func,
50+ * [4][5] thread
51+ * MCAMSR output
52+ */
53+ __u64 mcamsr_in_out;
54+ /*
55+ * Status code for MCA/MSR access
56+ */
57+ __u32 fw_ret_code;
58+ __u32 pad;
59+};
60+
61+struct apml_reg_xfer_msg {
62+ /*
63+ * RMI register address offset
64+ */
65+ __u16 reg_addr;
66+ /*
67+ * Register data for read/write
68+ */
69+ __u8 data_in_out;
70+ /*
71+ * Register read or write
72+ */
73+ __u8 rflag;
74+};
75+
76+/*
77+ * AMD sideband interface base IOCTL
78+ */
79+#define SB_BASE_IOCTL_NR 0xF9
80+
81+/**
82+ * DOC: SBRMI_IOCTL_MBOX_CMD
83+ *
84+ * @Parameters
85+ *
86+ * @struct apml_mbox_msg
87+ * Pointer to the &struct apml_mbox_msg that will contain the protocol
88+ * information
89+ *
90+ * @Description
91+ * IOCTL command for APML messages using generic _IOWR
92+ * The IOCTL provides userspace access to AMD sideband mailbox protocol
93+ * - Mailbox message read/write(0x0~0xFF)
94+ * - returning "-EFAULT" if none of the above
95+ * "-EPROTOTYPE" error is returned to provide additional error details
96+ */
97+#define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg)
98+
99+/**
100+ * DOC: SBRMI_IOCTL_CPUID_CMD
101+ *
102+ * @Parameters
103+ *
104+ * @struct apml_cpuid_msg
105+ * Pointer to the &struct apml_cpuid_msg that will contain the protocol
106+ * information
107+ *
108+ * @Description
109+ * IOCTL command for APML messages using generic _IOWR
110+ * The IOCTL provides userspace access to AMD sideband cpuid protocol
111+ * - CPUID protocol to get CPU details for Function/Ext Function
112+ * at thread level
113+ * - returning "-EFAULT" if none of the above
114+ * "-EPROTOTYPE" error is returned to provide additional error details
115+ */
116+#define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg)
117+
118+/**
119+ * DOC: SBRMI_IOCTL_MCAMSR_CMD
120+ *
121+ * @Parameters
122+ *
123+ * @struct apml_mcamsr_msg
124+ * Pointer to the &struct apml_mcamsr_msg that will contain the protocol
125+ * information
126+ *
127+ * @Description
128+ * IOCTL command for APML messages using generic _IOWR
129+ * The IOCTL provides userspace access to AMD sideband MCAMSR protocol
130+ * - MCAMSR protocol to get MCA bank details for Function at thread level
131+ * - returning "-EFAULT" if none of the above
132+ * "-EPROTOTYPE" error is returned to provide additional error details
133+ */
134+#define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg)
135+
136+/**
137+ * DOC: SBRMI_IOCTL_REG_XFER_CMD
138+ *
139+ * @Parameters
140+ *
141+ * @struct apml_reg_xfer_msg
142+ * Pointer to the &struct apml_reg_xfer_msg that will contain the protocol
143+ * information
144+ *
145+ * @Description
146+ * IOCTL command for APML messages using generic _IOWR
147+ * The IOCTL provides userspace access to AMD sideband register xfer protocol
148+ * - Register xfer protocol to get/set hardware register for given offset
149+ */
150+#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg)
151+
152+#endif /*_AMD_APML_H_*/
include/uapi/rdma/ib_user_verbs.h+16−0
@@ -233,6 +233,22 @@ struct ib_uverbs_ex_query_device { · 232 unmodified lines
233233 __u32 reserved;
234234 };
235235
236+enum ib_uverbs_odp_general_cap_bits {
237+ IB_UVERBS_ODP_SUPPORT = 1 << 0,
238+ IB_UVERBS_ODP_SUPPORT_IMPLICIT = 1 << 1,
239+};
240+
241+enum ib_uverbs_odp_transport_cap_bits {
242+ IB_UVERBS_ODP_SUPPORT_SEND = 1 << 0,
243+ IB_UVERBS_ODP_SUPPORT_RECV = 1 << 1,
244+ IB_UVERBS_ODP_SUPPORT_WRITE = 1 << 2,
245+ IB_UVERBS_ODP_SUPPORT_READ = 1 << 3,
246+ IB_UVERBS_ODP_SUPPORT_ATOMIC = 1 << 4,
247+ IB_UVERBS_ODP_SUPPORT_SRQ_RECV = 1 << 5,
248+ IB_UVERBS_ODP_SUPPORT_FLUSH = 1 << 6,
249+ IB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 1 << 7,
250+};
251+
236252 struct ib_uverbs_odp_caps {
237253 __aligned_u64 general_caps;
238254 struct {