Given a fw component index, the MCQI register allows us to query this component's information (e.g. its version and capabilities). Given a fw component index, the MCQS register allows us to query the status of a fw component, including its type and state (e.g. PRESET/IN_USE). It can be used to find the index of a component of a specific type, by sequentially increasing the component index, and querying each time the type of the returned component. If max component index is reached, 'last_index_flag' is set by the HCA. These registers' description was added to query the running and pending fw version of the HCA.
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| @@ -138,6 +138,7 @@ enum { · 137 unmodified lines | |||
| 138 | MLX5_REG_MTPPS = 0x9053, | 138 | MLX5_REG_MTPPS = 0x9053, |
| 139 | MLX5_REG_MTPPSE = 0x9054, | 139 | MLX5_REG_MTPPSE = 0x9054, |
| 140 | MLX5_REG_MPEGC = 0x9056, | 140 | MLX5_REG_MPEGC = 0x9056, |
| 141 | MLX5_REG_MCQS = 0x9060, | ||
| 141 | MLX5_REG_MCQI = 0x9061, | 142 | MLX5_REG_MCQI = 0x9061, |
| 142 | MLX5_REG_MCC = 0x9062, | 143 | MLX5_REG_MCC = 0x9062, |
| 143 | MLX5_REG_MCDA = 0x9063, | 144 | MLX5_REG_MCDA = 0x9063, |
| @@ -8542,7 +8542,7 @@ struct mlx5_ifc_mcam_access_reg_bits { · 8541 unmodified lines | |||
| 8542 | u8 mcda[0x1]; | 8542 | u8 mcda[0x1]; |
| 8543 | u8 mcc[0x1]; | 8543 | u8 mcc[0x1]; |
| 8544 | u8 mcqi[0x1]; | 8544 | u8 mcqi[0x1]; |
| 8545 | u8 reserved_at_1f[0x1]; | 8545 | u8 mcqs[0x1]; |
| 8546 | 8546 | ||
| 8547 | u8 regs_95_to_87[0x9]; | 8547 | u8 regs_95_to_87[0x9]; |
| 8548 | u8 mpegc[0x1]; | 8548 | u8 mpegc[0x1]; |
| @@ -9034,6 +9034,24 @@ struct mlx5_ifc_mtppse_reg_bits { · 485 unmodified lines | |||
| 9034 | u8 reserved_at_40[0x40]; | 9034 | u8 reserved_at_40[0x40]; |
| 9035 | }; | 9035 | }; |
| 9036 | 9036 | ||
| 9037 | struct mlx5_ifc_mcqs_reg_bits { | ||
| 9038 | u8 last_index_flag[0x1]; | ||
| 9039 | u8 reserved_at_1[0x7]; | ||
| 9040 | u8 fw_device[0x8]; | ||
| 9041 | u8 component_index[0x10]; | ||
| 9042 | |||
| 9043 | u8 reserved_at_20[0x10]; | ||
| 9044 | u8 identifier[0x10]; | ||
| 9045 | |||
| 9046 | u8 reserved_at_40[0x17]; | ||
| 9047 | u8 component_status[0x5]; | ||
| 9048 | u8 component_update_state[0x4]; | ||
| 9049 | |||
| 9050 | u8 last_update_state_changer_type[0x4]; | ||
| 9051 | u8 last_update_state_changer_host_id[0x4]; | ||
| 9052 | u8 reserved_at_68[0x18]; | ||
| 9053 | }; | ||
| 9054 | |||
| 9037 | struct mlx5_ifc_mcqi_cap_bits { | 9055 | struct mlx5_ifc_mcqi_cap_bits { |
| 9038 | u8 supported_info_bitmask[0x20]; | 9056 | u8 supported_info_bitmask[0x20]; |
| 9039 | 9057 | ||
| @@ -9054,6 +9072,43 @@ struct mlx5_ifc_mcqi_cap_bits { · 14 unmodified lines | |||
| 9054 | u8 reserved_at_86[0x1a]; | 9072 | u8 reserved_at_86[0x1a]; |
| 9055 | }; | 9073 | }; |
| 9056 | 9074 | ||
| 9075 | struct mlx5_ifc_mcqi_version_bits { | ||
| 9076 | u8 reserved_at_0[0x2]; | ||
| 9077 | u8 build_time_valid[0x1]; | ||
| 9078 | u8 user_defined_time_valid[0x1]; | ||
| 9079 | u8 reserved_at_4[0x14]; | ||
| 9080 | u8 version_string_length[0x8]; | ||
| 9081 | |||
| 9082 | u8 version[0x20]; | ||
| 9083 | |||
| 9084 | u8 build_time[0x40]; | ||
| 9085 | |||
| 9086 | u8 user_defined_time[0x40]; | ||
| 9087 | |||
| 9088 | u8 build_tool_version[0x20]; | ||
| 9089 | |||
| 9090 | u8 reserved_at_e0[0x20]; | ||
| 9091 | |||
| 9092 | u8 version_string[92][0x8]; | ||
| 9093 | }; | ||
| 9094 | |||
| 9095 | struct mlx5_ifc_mcqi_activation_method_bits { | ||
| 9096 | u8 pending_server_ac_power_cycle[0x1]; | ||
| 9097 | u8 pending_server_dc_power_cycle[0x1]; | ||
| 9098 | u8 pending_server_reboot[0x1]; | ||
| 9099 | u8 pending_fw_reset[0x1]; | ||
| 9100 | u8 auto_activate[0x1]; | ||
| 9101 | u8 all_hosts_sync[0x1]; | ||
| 9102 | u8 device_hw_reset[0x1]; | ||
| 9103 | u8 reserved_at_7[0x19]; | ||
| 9104 | }; | ||
| 9105 | |||
| 9106 | union mlx5_ifc_mcqi_reg_data_bits { | ||
| 9107 | struct mlx5_ifc_mcqi_cap_bits mcqi_caps; | ||
| 9108 | struct mlx5_ifc_mcqi_version_bits mcqi_version; | ||
| 9109 | struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; | ||
| 9110 | }; | ||
| 9111 | |||
| 9057 | struct mlx5_ifc_mcqi_reg_bits { | 9112 | struct mlx5_ifc_mcqi_reg_bits { |
| 9058 | u8 read_pending_component[0x1]; | 9113 | u8 read_pending_component[0x1]; |
| 9059 | u8 reserved_at_1[0xf]; | 9114 | u8 reserved_at_1[0xf]; |
| @@ -9071,7 +9126,7 @@ struct mlx5_ifc_mcqi_reg_bits { · 11 unmodified lines | |||
| 9071 | u8 reserved_at_a0[0x10]; | 9126 | u8 reserved_at_a0[0x10]; |
| 9072 | u8 data_size[0x10]; | 9127 | u8 data_size[0x10]; |
| 9073 | 9128 | ||
| 9074 | u8 data[0][0x20]; | 9129 | union mlx5_ifc_mcqi_reg_data_bits data[0]; |
| 9075 | }; | 9130 | }; |
| 9076 | 9131 | ||
| 9077 | struct mlx5_ifc_mcc_reg_bits { | 9132 | struct mlx5_ifc_mcc_reg_bits { |