ASoC: Updates for v5.15 Quite a quiet release this time, mostly a combination of cleanups and a good set of new drivers. - Lots of cleanups and improvements to the Intel drivers, including some new systems support. - New support for AMD Vangoh, CUI CMM-4030D-261, Mediatek Mt8195, Renesas RZ/G2L Mediatek Mt8195, RealTek RT101P, Renesas RZ/G2L,, Rockchip RK3568 S/PDIF.
Unified · Split
| @@ -33,6 +33,13 @@ Description: · 32 unmodified lines | ||
| 33 | 33 | frequency adjustment value (a positive integer) in |
| 34 | 34 | parts per billion. |
| 35 | 35 | |
| 36 | +What: /sys/class/ptp/ptpN/max_vclocks | |
| 37 | +Date: May 2021 | |
| 38 | +Contact: Yangbo Lu <yangbo.lu@nxp.com> | |
| 39 | +Description: | |
| 40 | + This file contains the maximum number of ptp vclocks. | |
| 41 | + Write integer to re-configure it. | |
| 42 | + | |
| 36 | 43 | What: /sys/class/ptp/ptpN/n_alarms |
| 37 | 44 | Date: September 2010 |
| 38 | 45 | Contact: Richard Cochran <richardcochran@gmail.com> |
| @@ -61,6 +68,19 @@ Description: · 22 unmodified lines | ||
| 61 | 68 | This file contains the number of programmable pins |
| 62 | 69 | offered by the PTP hardware clock. |
| 63 | 70 | |
| 71 | +What: /sys/class/ptp/ptpN/n_vclocks | |
| 72 | +Date: May 2021 | |
| 73 | +Contact: Yangbo Lu <yangbo.lu@nxp.com> | |
| 74 | +Description: | |
| 75 | + This file contains the number of virtual PTP clocks in | |
| 76 | + use. By default, the value is 0 meaning that only the | |
| 77 | + physical clock is in use. Setting the value creates | |
| 78 | + the corresponding number of virtual clocks and causes | |
| 79 | + the physical clock to become free running. Setting the | |
| 80 | + value back to 0 deletes the virtual clocks and | |
| 81 | + switches the physical clock back to normal, adjustable | |
| 82 | + operation. | |
| 83 | + | |
| 64 | 84 | What: /sys/class/ptp/ptpN/pins |
| 65 | 85 | Date: March 2014 |
| 66 | 86 | Contact: Richard Cochran <richardcochran@gmail.com> |
| @@ -45,14 +45,24 @@ how the user addresses are used by the kernel: · 44 unmodified lines | ||
| 45 | 45 | |
| 46 | 46 | 1. User addresses not accessed by the kernel but used for address space |
| 47 | 47 | management (e.g. ``mprotect()``, ``madvise()``). The use of valid |
| 48 | − tagged pointers in this context is allowed with the exception of | |
| 49 | − ``brk()``, ``mmap()`` and the ``new_address`` argument to | |
| 50 | − ``mremap()`` as these have the potential to alias with existing | |
| 51 | − user addresses. | |
| 52 | − | |
| 53 | − NOTE: This behaviour changed in v5.6 and so some earlier kernels may | |
| 54 | − incorrectly accept valid tagged pointers for the ``brk()``, | |
| 55 | − ``mmap()`` and ``mremap()`` system calls. | |
| 48 | + tagged pointers in this context is allowed with these exceptions: | |
| 49 | + | |
| 50 | + - ``brk()``, ``mmap()`` and the ``new_address`` argument to | |
| 51 | + ``mremap()`` as these have the potential to alias with existing | |
| 52 | + user addresses. | |
| 53 | + | |
| 54 | + NOTE: This behaviour changed in v5.6 and so some earlier kernels may | |
| 55 | + incorrectly accept valid tagged pointers for the ``brk()``, | |
| 56 | + ``mmap()`` and ``mremap()`` system calls. | |
| 57 | + | |
| 58 | + - The ``range.start``, ``start`` and ``dst`` arguments to the | |
| 59 | + ``UFFDIO_*`` ``ioctl()``s used on a file descriptor obtained from | |
| 60 | + ``userfaultfd()``, as fault addresses subsequently obtained by reading | |
| 61 | + the file descriptor will be untagged, which may otherwise confuse | |
| 62 | + tag-unaware programs. | |
| 63 | + | |
| 64 | + NOTE: This behaviour changed in v5.14 and so some earlier kernels may | |
| 65 | + incorrectly accept valid tagged pointers for this system call. | |
| 56 | 66 | |
| 57 | 67 | 2. User addresses accessed by the kernel (e.g. ``write()``). This ABI |
| 58 | 68 | relaxation is disabled by default and the application thread needs to |
| @@ -108,7 +108,7 @@ This bump in ABI version is at most once per kernel development cycle. · 107 unmodified lines | ||
| 108 | 108 | |
| 109 | 109 | For example, if current state of ``libbpf.map`` is: |
| 110 | 110 | |
| 111 | −.. code-block:: c | |
| 111 | +.. code-block:: none | |
| 112 | 112 | |
| 113 | 113 | LIBBPF_0.0.1 { |
| 114 | 114 | global: |
| @@ -121,7 +121,7 @@ For example, if current state of ``libbpf.map`` is: · 6 unmodified lines | ||
| 121 | 121 | , and a new symbol ``bpf_func_c`` is being introduced, then |
| 122 | 122 | ``libbpf.map`` should be changed like this: |
| 123 | 123 | |
| 124 | −.. code-block:: c | |
| 124 | +.. code-block:: none | |
| 125 | 125 | |
| 126 | 126 | LIBBPF_0.0.1 { |
| 127 | 127 | global: |
| @@ -86,19 +86,7 @@ Generating code coverage reports under UML · 85 unmodified lines | ||
| 86 | 86 | .. note:: |
| 87 | 87 | TODO(brendanhiggins@google.com): There are various issues with UML and |
| 88 | 88 | versions of gcc 7 and up. You're likely to run into missing ``.gcda`` |
| 89 | − files or compile errors. We know one `faulty GCC commit | |
| 90 | − <https://github.com/gcc-mirror/gcc/commit/8c9434c2f9358b8b8bad2c1990edf10a21645f9d>`_ | |
| 91 | − but not how we'd go about getting this fixed. The compile errors still | |
| 92 | − need some investigation. | |
| 93 | − | |
| 94 | −.. note:: | |
| 95 | − TODO(brendanhiggins@google.com): for recent versions of Linux | |
| 96 | − (5.10-5.12, maybe earlier), there's a bug with gcov counters not being | |
| 97 | − flushed in UML. This translates to very low (<1%) reported coverage. This is | |
| 98 | − related to the above issue and can be worked around by replacing the | |
| 99 | − one call to ``uml_abort()`` (it's in ``os_dump_core()``) with a plain | |
| 100 | − ``exit()``. | |
| 101 | − | |
| 89 | + files or compile errors. | |
| 102 | 90 | |
| 103 | 91 | This is different from the "normal" way of getting coverage information that is |
| 104 | 92 | documented in Documentation/dev-tools/gcov.rst. |
| @@ -50,7 +50,6 @@ properties: · 49 unmodified lines | ||
| 50 | 50 | |
| 51 | 51 | reg: |
| 52 | 52 | minItems: 1 |
| 53 | − maxItems: 3 | |
| 54 | 53 | items: |
| 55 | 54 | - description: base register |
| 56 | 55 | - description: power register |
| @@ -92,7 +92,6 @@ required: · 91 unmodified lines | ||
| 92 | 92 | - reg |
| 93 | 93 | - clocks |
| 94 | 94 | - interrupts |
| 95 | − - resets | |
| 96 | 95 | - ports |
| 97 | 96 | |
| 98 | 97 | allOf: |
| @@ -39,17 +39,7 @@ properties: · 38 unmodified lines | ||
| 39 | 39 | reg: |
| 40 | 40 | maxItems: 1 |
| 41 | 41 | |
| 42 | −patternProperties: | |
| 43 | − "^adi,bypass-attenuator-in[0-4]$": | |
| 44 | − description: | | |
| 45 | − Configures bypassing the individual voltage input attenuator. If | |
| 46 | − set to 1 the attenuator is bypassed if set to 0 the attenuator is | |
| 47 | − not bypassed. If the property is absent then the attenuator | |
| 48 | − retains it's configuration from the bios/bootloader. | |
| 49 | − $ref: /schemas/types.yaml#/definitions/uint32 | |
| 50 | − enum: [0, 1] | |
| 51 | − | |
| 52 | − "^adi,pwm-active-state$": | |
| 42 | + adi,pwm-active-state: | |
| 53 | 43 | description: | |
| 54 | 44 | Integer array, represents the active state of the pwm outputs If set to 0 |
| 55 | 45 | the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm |
| @@ -61,6 +51,16 @@ patternProperties: · 5 unmodified lines | ||
| 61 | 51 | enum: [0, 1] |
| 62 | 52 | default: 1 |
| 63 | 53 | |
| 54 | +patternProperties: | |
| 55 | + "^adi,bypass-attenuator-in[0-4]$": | |
| 56 | + description: | | |
| 57 | + Configures bypassing the individual voltage input attenuator. If | |
| 58 | + set to 1 the attenuator is bypassed if set to 0 the attenuator is | |
| 59 | + not bypassed. If the property is absent then the attenuator | |
| 60 | + retains it's configuration from the bios/bootloader. | |
| 61 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 62 | + enum: [0, 1] | |
| 63 | + | |
| 64 | 64 | required: |
| 65 | 65 | - compatible |
| 66 | 66 | - reg |
| @@ -152,47 +152,6 @@ allOf: · 151 unmodified lines | ||
| 152 | 152 | maxItems: 1 |
| 153 | 153 | st,drdy-int-pin: false |
| 154 | 154 | |
| 155 | − - if: | |
| 156 | − properties: | |
| 157 | − compatible: | |
| 158 | − enum: | |
| 159 | − # Two intertial interrupts i.e. accelerometer/gyro interrupts | |
| 160 | − - st,h3lis331dl-accel | |
| 161 | − - st,l3g4200d-gyro | |
| 162 | − - st,l3g4is-gyro | |
| 163 | − - st,l3gd20-gyro | |
| 164 | − - st,l3gd20h-gyro | |
| 165 | − - st,lis2de12 | |
| 166 | − - st,lis2dw12 | |
| 167 | − - st,lis2hh12 | |
| 168 | − - st,lis2dh12-accel | |
| 169 | − - st,lis331dl-accel | |
| 170 | − - st,lis331dlh-accel | |
| 171 | − - st,lis3de | |
| 172 | − - st,lis3dh-accel | |
| 173 | − - st,lis3dhh | |
| 174 | − - st,lis3mdl-magn | |
| 175 | − - st,lng2dm-accel | |
| 176 | − - st,lps331ap-press | |
| 177 | − - st,lsm303agr-accel | |
| 178 | − - st,lsm303dlh-accel | |
| 179 | − - st,lsm303dlhc-accel | |
| 180 | − - st,lsm303dlm-accel | |
| 181 | − - st,lsm330-accel | |
| 182 | − - st,lsm330-gyro | |
| 183 | − - st,lsm330d-accel | |
| 184 | − - st,lsm330d-gyro | |
| 185 | − - st,lsm330dl-accel | |
| 186 | − - st,lsm330dl-gyro | |
| 187 | − - st,lsm330dlc-accel | |
| 188 | − - st,lsm330dlc-gyro | |
| 189 | − - st,lsm9ds0-gyro | |
| 190 | − - st,lsm9ds1-magn | |
| 191 | − then: | |
| 192 | − properties: | |
| 193 | − interrupts: | |
| 194 | − maxItems: 2 | |
| 195 | − | |
| 196 | 155 | required: |
| 197 | 156 | - compatible |
| 198 | 157 | - reg |
| @@ -52,16 +52,14 @@ properties: · 51 unmodified lines | ||
| 52 | 52 | items: |
| 53 | 53 | - const: marvell,ap806-smmu-500 |
| 54 | 54 | - const: arm,mmu-500 |
| 55 | − - description: NVIDIA SoCs that program two ARM MMU-500s identically | |
| 56 | − items: | |
| 57 | 55 | - description: NVIDIA SoCs that require memory controller interaction |
| 58 | 56 | and may program multiple ARM MMU-500s identically with the memory |
| 59 | 57 | controller interleaving translations between multiple instances |
| 60 | 58 | for improved performance. |
| 61 | 59 | items: |
| 62 | 60 | - enum: |
| 63 | − - const: nvidia,tegra194-smmu | |
| 64 | − - const: nvidia,tegra186-smmu | |
| 61 | + - nvidia,tegra194-smmu | |
| 62 | + - nvidia,tegra186-smmu | |
| 65 | 63 | - const: nvidia,smmu-500 |
| 66 | 64 | - items: |
| 67 | 65 | - const: arm,mmu-500 |
| @@ -28,14 +28,12 @@ properties: · 27 unmodified lines | ||
| 28 | 28 | - description: configuration registers for MMU instance 0 |
| 29 | 29 | - description: configuration registers for MMU instance 1 |
| 30 | 30 | minItems: 1 |
| 31 | − maxItems: 2 | |
| 32 | 31 | |
| 33 | 32 | interrupts: |
| 34 | 33 | items: |
| 35 | 34 | - description: interruption for MMU instance 0 |
| 36 | 35 | - description: interruption for MMU instance 1 |
| 37 | 36 | minItems: 1 |
| 38 | − maxItems: 2 | |
| 39 | 37 | |
| 40 | 38 | clocks: |
| 41 | 39 | items: |
| @@ -57,7 +57,6 @@ properties: · 56 unmodified lines | ||
| 57 | 57 | |
| 58 | 58 | ranges: |
| 59 | 59 | minItems: 1 |
| 60 | − maxItems: 3 | |
| 61 | 60 | description: | |
| 62 | 61 | Memory bus areas for interacting with the devices. Reflects |
| 63 | 62 | the memory layout with four integer values following: |
| @@ -84,7 +84,6 @@ properties: · 83 unmodified lines | ||
| 84 | 84 | |
| 85 | 85 | interrupts: |
| 86 | 86 | minItems: 1 |
| 87 | − maxItems: 3 | |
| 88 | 87 | items: |
| 89 | 88 | - description: NAND CTLRDY interrupt |
| 90 | 89 | - description: FLASH_DMA_DONE if flash DMA is available |
| @@ -92,7 +91,6 @@ properties: · 1 unmodified line | ||
| 92 | 91 | |
| 93 | 92 | interrupt-names: |
| 94 | 93 | minItems: 1 |
| 95 | − maxItems: 3 | |
| 96 | 94 | items: |
| 97 | 95 | - const: nand_ctlrdy |
| 98 | 96 | - const: flash_dma_done |
| @@ -148,8 +146,6 @@ allOf: · 49 unmodified lines | ||
| 148 | 146 | then: |
| 149 | 147 | properties: |
| 150 | 148 | reg-names: |
| 151 | − minItems: 2 | |
| 152 | − maxItems: 2 | |
| 153 | 149 | items: |
| 154 | 150 | - const: nand |
| 155 | 151 | - const: nand-int-base |
| @@ -161,8 +157,6 @@ allOf: · 5 unmodified lines | ||
| 161 | 157 | then: |
| 162 | 158 | properties: |
| 163 | 159 | reg-names: |
| 164 | − minItems: 3 | |
| 165 | − maxItems: 3 | |
| 166 | 160 | items: |
| 167 | 161 | - const: nand |
| 168 | 162 | - const: nand-int-base |
| @@ -175,8 +169,6 @@ allOf: · 6 unmodified lines | ||
| 175 | 169 | then: |
| 176 | 170 | properties: |
| 177 | 171 | reg-names: |
| 178 | − minItems: 3 | |
| 179 | − maxItems: 3 | |
| 180 | 172 | items: |
| 181 | 173 | - const: nand |
| 182 | 174 | - const: iproc-idm |
| @@ -67,8 +67,8 @@ properties: · 66 unmodified lines | ||
| 67 | 67 | reg: |
| 68 | 68 | oneOf: |
| 69 | 69 | - enum: |
| 70 | − - 0 | |
| 71 | − - 1 | |
| 70 | + - 0 | |
| 71 | + - 1 | |
| 72 | 72 | |
| 73 | 73 | required: |
| 74 | 74 | - compatible |
| @@ -13,7 +13,7 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt · 12 unmodified lines | ||
| 13 | 13 | |
| 14 | 14 | For the properties relevant to the ethernet controller connected to the GPMC |
| 15 | 15 | refer to the binding documentation of the device. For example, the documentation |
| 16 | −for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt | |
| 16 | +for the SMSC 911x is Documentation/devicetree/bindings/net/smsc,lan9115.yaml | |
| 17 | 17 | |
| 18 | 18 | Child nodes need to specify the GPMC bus address width using the "bank-width" |
| 19 | 19 | property but is possible that an ethernet controller also has a property to |
| @@ -1,56 +0,0 @@ | ||
| 1 | −IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP. | |
| 2 | − | |
| 3 | −This file documents platform glue layer for IMX. | |
| 4 | −Please see stmmac.txt for the other unchanged properties. | |
| 5 | − | |
| 6 | −The device node has following properties. | |
| 7 | − | |
| 8 | −Required properties: | |
| 9 | −- compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer | |
| 10 | − and "snps,dwmac-5.10a" to select IP version. | |
| 11 | −- clocks: Must contain a phandle for each entry in clock-names. | |
| 12 | −- clock-names: Should be "stmmaceth" for the host clock. | |
| 13 | − Should be "pclk" for the MAC apb clock. | |
| 14 | − Should be "ptp_ref" for the MAC timer clock. | |
| 15 | − Should be "tx" for the MAC RGMII TX clock: | |
| 16 | − Should be "mem" for EQOS MEM clock. | |
| 17 | − - "mem" clock is required for imx8dxl platform. | |
| 18 | − - "mem" clock is not required for imx8mp platform. | |
| 19 | −- interrupt-names: Should contain a list of interrupt names corresponding to | |
| 20 | − the interrupts in the interrupts property, if available. | |
| 21 | − Should be "macirq" for the main MAC IRQ | |
| 22 | − Should be "eth_wake_irq" for the IT which wake up system | |
| 23 | −- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which | |
| 24 | − encompases the GPR register, and the offset of the GPR register. | |
| 25 | − - required for imx8mp platform. | |
| 26 | − - is optional for imx8dxl platform. | |
| 27 | − | |
| 28 | −Optional properties: | |
| 29 | −- intf_mode: is optional for imx8dxl platform. | |
| 30 | −- snps,rmii_refclk_ext: to select RMII reference clock from external. | |
| 31 | − | |
| 32 | −Example: | |
| 33 | − eqos: ethernet@30bf0000 { | |
| 34 | − compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; | |
| 35 | − reg = <0x30bf0000 0x10000>; | |
| 36 | − interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
| 37 | − <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
| 38 | − interrupt-names = "eth_wake_irq", "macirq"; | |
| 39 | − clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, | |
| 40 | − <&clk IMX8MP_CLK_QOS_ENET_ROOT>, | |
| 41 | − <&clk IMX8MP_CLK_ENET_QOS_TIMER>, | |
| 42 | − <&clk IMX8MP_CLK_ENET_QOS>; | |
| 43 | − clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; | |
| 44 | − assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, | |
| 45 | − <&clk IMX8MP_CLK_ENET_QOS_TIMER>, | |
| 46 | − <&clk IMX8MP_CLK_ENET_QOS>; | |
| 47 | − assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, | |
| 48 | − <&clk IMX8MP_SYS_PLL2_100M>, | |
| 49 | − <&clk IMX8MP_SYS_PLL2_125M>; | |
| 50 | − assigned-clock-rates = <0>, <100000000>, <125000000>; | |
| 51 | − nvmem-cells = <ð_mac0>; | |
| 52 | − nvmem-cell-names = "mac-address"; | |
| 53 | − nvmem_macaddr_swap; | |
| 54 | − intf_mode = <&gpr 0x4>; | |
| 55 | − status = "disabled"; | |
| 56 | − }; | |
| @@ -0,0 +1,93 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NXP i.MX8 DWMAC glue layer Device Tree Bindings | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Joakim Zhang <qiangqing.zhang@nxp.com> | |
| 11 | + | |
| 12 | +# We need a select here so we don't match all nodes with 'snps,dwmac' | |
| 13 | +select: | |
| 14 | + properties: | |
| 15 | + compatible: | |
| 16 | + contains: | |
| 17 | + enum: | |
| 18 | + - nxp,imx8mp-dwmac-eqos | |
| 19 | + - nxp,imx8dxl-dwmac-eqos | |
| 20 | + required: | |
| 21 | + - compatible | |
| 22 | + | |
| 23 | +allOf: | |
| 24 | + - $ref: "snps,dwmac.yaml#" | |
| 25 | + | |
| 26 | +properties: | |
| 27 | + compatible: | |
| 28 | + oneOf: | |
| 29 | + - items: | |
| 30 | + - enum: | |
| 31 | + - nxp,imx8mp-dwmac-eqos | |
| 32 | + - nxp,imx8dxl-dwmac-eqos | |
| 33 | + - const: snps,dwmac-5.10a | |
| 34 | + | |
| 35 | + clocks: | |
| 36 | + minItems: 3 | |
| 37 | + maxItems: 5 | |
| 38 | + items: | |
| 39 | + - description: MAC host clock | |
| 40 | + - description: MAC apb clock | |
| 41 | + - description: MAC timer clock | |
| 42 | + - description: MAC RGMII TX clock | |
| 43 | + - description: EQOS MEM clock | |
| 44 | + | |
| 45 | + clock-names: | |
| 46 | + minItems: 3 | |
| 47 | + maxItems: 5 | |
| 48 | + contains: | |
| 49 | + enum: | |
| 50 | + - stmmaceth | |
| 51 | + - pclk | |
| 52 | + - ptp_ref | |
| 53 | + - tx | |
| 54 | + - mem | |
| 55 | + | |
| 56 | + intf_mode: | |
| 57 | + $ref: /schemas/types.yaml#/definitions/phandle-array | |
| 58 | + description: | |
| 59 | + Should be phandle/offset pair. The phandle to the syscon node which | |
| 60 | + encompases the GPR register, and the offset of the GPR register. | |
| 61 | + | |
| 62 | + snps,rmii_refclk_ext: | |
| 63 | + $ref: /schemas/types.yaml#/definitions/flag | |
| 64 | + description: | |
| 65 | + To select RMII reference clock from external. | |
| 66 | + | |
| 67 | +required: | |
| 68 | + - compatible | |
| 69 | + - clocks | |
| 70 | + - clock-names | |
| 71 | + | |
| 72 | +unevaluatedProperties: false | |
| 73 | + | |
| 74 | +examples: | |
| 75 | + - | | |
| 76 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 77 | + #include <dt-bindings/interrupt-controller/irq.h> | |
| 78 | + #include <dt-bindings/clock/imx8mp-clock.h> | |
| 79 | + | |
| 80 | + eqos: ethernet@30bf0000 { | |
| 81 | + compatible = "nxp,imx8mp-dwmac-eqos","snps,dwmac-5.10a"; | |
| 82 | + reg = <0x30bf0000 0x10000>; | |
| 83 | + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 84 | + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| 85 | + interrupt-names = "macirq", "eth_wake_irq"; | |
| 86 | + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, | |
| 87 | + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, | |
| 88 | + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, | |
| 89 | + <&clk IMX8MP_CLK_ENET_QOS>; | |
| 90 | + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; | |
| 91 | + phy-mode = "rgmii"; | |
| 92 | + status = "disabled"; | |
| 93 | + }; | |
| @@ -0,0 +1,110 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/net/smsc,lan9115.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Shawn Guo <shawnguo@kernel.org> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: ethernet-controller.yaml# | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + oneOf: | |
| 18 | + - const: smsc,lan9115 | |
| 19 | + - items: | |
| 20 | + - enum: | |
| 21 | + - smsc,lan89218 | |
| 22 | + - smsc,lan9117 | |
| 23 | + - smsc,lan9118 | |
| 24 | + - smsc,lan9220 | |
| 25 | + - smsc,lan9221 | |
| 26 | + - const: smsc,lan9115 | |
| 27 | + | |
| 28 | + reg: | |
| 29 | + maxItems: 1 | |
| 30 | + | |
| 31 | + reg-shift: true | |
| 32 | + | |
| 33 | + reg-io-width: | |
| 34 | + enum: [ 2, 4 ] | |
| 35 | + default: 2 | |
| 36 | + | |
| 37 | + interrupts: | |
| 38 | + minItems: 1 | |
| 39 | + items: | |
| 40 | + - description: | |
| 41 | + LAN interrupt line | |
| 42 | + - description: | |
| 43 | + Optional PME (power management event) interrupt that is able to wake | |
| 44 | + up the host system with a 50ms pulse on network activity | |
| 45 | + | |
| 46 | + clocks: | |
| 47 | + maxItems: 1 | |
| 48 | + | |
| 49 | + phy-mode: true | |
| 50 | + | |
| 51 | + smsc,irq-active-high: | |
| 52 | + type: boolean | |
| 53 | + description: Indicates the IRQ polarity is active-high | |
| 54 | + | |
| 55 | + smsc,irq-push-pull: | |
| 56 | + type: boolean | |
| 57 | + description: Indicates the IRQ type is push-pull | |
| 58 | + | |
| 59 | + smsc,force-internal-phy: | |
| 60 | + type: boolean | |
| 61 | + description: Forces SMSC LAN controller to use internal PHY | |
| 62 | + | |
| 63 | + smsc,force-external-phy: | |
| 64 | + type: boolean | |
| 65 | + description: Forces SMSC LAN controller to use external PHY | |
| 66 | + | |
| 67 | + smsc,save-mac-address: | |
| 68 | + type: boolean | |
| 69 | + description: | |
| 70 | + Indicates that MAC address needs to be saved before resetting the | |
| 71 | + controller | |
| 72 | + | |
| 73 | + reset-gpios: | |
| 74 | + maxItems: 1 | |
| 75 | + description: | |
| 76 | + A GPIO line connected to the RESET (active low) signal of the device. | |
| 77 | + On many systems this is wired high so the device goes out of reset at | |
| 78 | + power-on, but if it is under program control, this optional GPIO can | |
| 79 | + wake up in response to it. | |
| 80 | + | |
| 81 | + vdd33a-supply: | |
| 82 | + description: 3.3V analog power supply | |
| 83 | + | |
| 84 | + vddvario-supply: | |
| 85 | + description: IO logic power supply | |
| 86 | + | |
| 87 | +required: | |
| 88 | + - compatible | |
| 89 | + - reg | |
| 90 | + - interrupts | |
| 91 | + | |
| 92 | +# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*", | |
| 93 | +# "gpmc,*", ...) to be found, that actually depend on the compatible value of | |
| 94 | +# the parent node. | |
| 95 | +additionalProperties: true | |
| 96 | + | |
| 97 | +examples: | |
| 98 | + - | | |
| 99 | + #include <dt-bindings/gpio/gpio.h> | |
| 100 | + | |
| 101 | + ethernet@f4000000 { | |
| 102 | + compatible = "smsc,lan9220", "smsc,lan9115"; | |
| 103 | + reg = <0xf4000000 0x2000000>; | |
| 104 | + phy-mode = "mii"; | |
| 105 | + interrupt-parent = <&gpio1>; | |
| 106 | + interrupts = <31>, <32>; | |
| 107 | + reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; | |
| 108 | + reg-io-width = <4>; | |
| 109 | + smsc,irq-push-pull; | |
| 110 | + }; | |
| @@ -1,43 +0,0 @@ | ||
| 1 | −* Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller | |
| 2 | − | |
| 3 | −Required properties: | |
| 4 | −- compatible : Should be "smsc,lan<model>", "smsc,lan9115" | |
| 5 | −- reg : Address and length of the io space for SMSC LAN | |
| 6 | −- interrupts : one or two interrupt specifiers | |
| 7 | − - The first interrupt is the SMSC LAN interrupt line | |
| 8 | − - The second interrupt (if present) is the PME (power | |
| 9 | − management event) interrupt that is able to wake up the host | |
| 10 | − system with a 50ms pulse on network activity | |
| 11 | −- phy-mode : See ethernet.txt file in the same directory | |
| 12 | − | |
| 13 | −Optional properties: | |
| 14 | −- reg-shift : Specify the quantity to shift the register offsets by | |
| 15 | −- reg-io-width : Specify the size (in bytes) of the IO accesses that | |
| 16 | − should be performed on the device. Valid value for SMSC LAN is | |
| 17 | − 2 or 4. If it's omitted or invalid, the size would be 2. | |
| 18 | −- smsc,irq-active-high : Indicates the IRQ polarity is active-high | |
| 19 | −- smsc,irq-push-pull : Indicates the IRQ type is push-pull | |
| 20 | −- smsc,force-internal-phy : Forces SMSC LAN controller to use | |
| 21 | − internal PHY | |
| 22 | −- smsc,force-external-phy : Forces SMSC LAN controller to use | |
| 23 | − external PHY | |
| 24 | −- smsc,save-mac-address : Indicates that mac address needs to be saved | |
| 25 | − before resetting the controller | |
| 26 | −- reset-gpios : a GPIO line connected to the RESET (active low) signal | |
| 27 | − of the device. On many systems this is wired high so the device goes | |
| 28 | − out of reset at power-on, but if it is under program control, this | |
| 29 | − optional GPIO can wake up in response to it. | |
| 30 | −- vdd33a-supply, vddvario-supply : 3.3V analog and IO logic power supplies | |
| 31 | − | |
| 32 | −Examples: | |
| 33 | − | |
| 34 | −lan9220@f4000000 { | |
| 35 | − compatible = "smsc,lan9220", "smsc,lan9115"; | |
| 36 | − reg = <0xf4000000 0x2000000>; | |
| 37 | − phy-mode = "mii"; | |
| 38 | − interrupt-parent = <&gpio1>; | |
| 39 | − interrupts = <31>, <32>; | |
| 40 | − reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; | |
| 41 | − reg-io-width = <4>; | |
| 42 | − smsc,irq-push-pull; | |
| 43 | −}; | |
| @@ -28,6 +28,7 @@ select: · 27 unmodified lines | ||
| 28 | 28 | - snps,dwmac-4.00 |
| 29 | 29 | - snps,dwmac-4.10a |
| 30 | 30 | - snps,dwmac-4.20a |
| 31 | + - snps,dwmac-5.10a | |
| 31 | 32 | - snps,dwxgmac |
| 32 | 33 | - snps,dwxgmac-2.10 |
| 33 | 34 | |
| @@ -82,6 +83,7 @@ properties: · 48 unmodified lines | ||
| 82 | 83 | - snps,dwmac-4.00 |
| 83 | 84 | - snps,dwmac-4.10a |
| 84 | 85 | - snps,dwmac-4.20a |
| 86 | + - snps,dwmac-5.10a | |
| 85 | 87 | - snps,dwxgmac |
| 86 | 88 | - snps,dwxgmac-2.10 |
| 87 | 89 | |
| @@ -375,6 +377,7 @@ allOf: · 287 unmodified lines | ||
| 375 | 377 | - snps,dwmac-4.00 |
| 376 | 378 | - snps,dwmac-4.10a |
| 377 | 379 | - snps,dwmac-4.20a |
| 380 | + - snps,dwmac-5.10a | |
| 378 | 381 | - snps,dwxgmac |
| 379 | 382 | - snps,dwxgmac-2.10 |
| 380 | 383 | - st,spear600-gmac |
| @@ -77,6 +77,34 @@ properties: · 76 unmodified lines | ||
| 77 | 77 | Type-C spec states minimum CC pin debounce of 100 ms and maximum |
| 78 | 78 | of 200 ms. However, some solutions might need more than 200 ms. |
| 79 | 79 | |
| 80 | + refclk-dig: | |
| 81 | + type: object | |
| 82 | + description: | | |
| 83 | + WIZ node should have subnode for refclk_dig to select the reference | |
| 84 | + clock source for the reference clock used in the PHY and PMA digital | |
| 85 | + logic. | |
| 86 | + properties: | |
| 87 | + clocks: | |
| 88 | + minItems: 2 | |
| 89 | + maxItems: 4 | |
| 90 | + description: Phandle to two (Torrent) or four (Sierra) clock nodes representing | |
| 91 | + the inputs to refclk_dig | |
| 92 | + | |
| 93 | + "#clock-cells": | |
| 94 | + const: 0 | |
| 95 | + | |
| 96 | + assigned-clocks: | |
| 97 | + maxItems: 1 | |
| 98 | + | |
| 99 | + assigned-clock-parents: | |
| 100 | + maxItems: 1 | |
| 101 | + | |
| 102 | + required: | |
| 103 | + - clocks | |
| 104 | + - "#clock-cells" | |
| 105 | + - assigned-clocks | |
| 106 | + - assigned-clock-parents | |
| 107 | + | |
| 80 | 108 | patternProperties: |
| 81 | 109 | "^pll[0|1]-refclk$": |
| 82 | 110 | type: object |
| @@ -121,34 +149,6 @@ patternProperties: · 38 unmodified lines | ||
| 121 | 149 | - clocks |
| 122 | 150 | - "#clock-cells" |
| 123 | 151 | |
| 124 | − "^refclk-dig$": | |
| 125 | − type: object | |
| 126 | − description: | | |
| 127 | − WIZ node should have subnode for refclk_dig to select the reference | |
| 128 | − clock source for the reference clock used in the PHY and PMA digital | |
| 129 | − logic. | |
| 130 | − properties: | |
| 131 | − clocks: | |
| 132 | − minItems: 2 | |
| 133 | − maxItems: 4 | |
| 134 | − description: Phandle to two (Torrent) or four (Sierra) clock nodes representing | |
| 135 | − the inputs to refclk_dig | |
| 136 | − | |
| 137 | − "#clock-cells": | |
| 138 | − const: 0 | |
| 139 | − | |
| 140 | − assigned-clocks: | |
| 141 | − maxItems: 1 | |
| 142 | − | |
| 143 | − assigned-clock-parents: | |
| 144 | − maxItems: 1 | |
| 145 | − | |
| 146 | − required: | |
| 147 | − - clocks | |
| 148 | − - "#clock-cells" | |
| 149 | − - assigned-clocks | |
| 150 | − - assigned-clock-parents | |
| 151 | − | |
| 152 | 152 | "^serdes@[0-9a-f]+$": |
| 153 | 153 | type: object |
| 154 | 154 | description: | |
| @@ -57,12 +57,14 @@ properties: · 56 unmodified lines | ||
| 57 | 57 | maxItems: 1 |
| 58 | 58 | |
| 59 | 59 | power-domains: |
| 60 | + deprecated: true | |
| 60 | 61 | description: |
| 61 | 62 | Power domain to use for enable control. This binding is only |
| 62 | 63 | available if the compatible is chosen to regulator-fixed-domain. |
| 63 | 64 | maxItems: 1 |
| 64 | 65 | |
| 65 | 66 | required-opps: |
| 67 | + deprecated: true | |
| 66 | 68 | description: |
| 67 | 69 | Performance state to use for enable control. This binding is only |
| 68 | 70 | available if the compatible is chosen to regulator-fixed-domain. The |
| @@ -36,12 +36,12 @@ properties: · 35 unmodified lines | ||
| 36 | 36 | switching frequency must be one of following corresponding value |
| 37 | 37 | 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz |
| 38 | 38 | |
| 39 | − patternProperties: | |
| 40 | − "^ldo[1-4]$": | |
| 39 | + ldortc: | |
| 41 | 40 | type: object |
| 42 | 41 | $ref: regulator.yaml# |
| 43 | 42 | |
| 44 | − "^ldortc$": | |
| 43 | + patternProperties: | |
| 44 | + "^ldo[1-4]$": | |
| 45 | 45 | type: object |
| 46 | 46 | $ref: regulator.yaml# |
| 47 | 47 | |
| @@ -83,7 +83,8 @@ properties: · 82 unmodified lines | ||
| 83 | 83 | |
| 84 | 84 | unevaluatedProperties: false |
| 85 | 85 | |
| 86 | − "^vsnvs$": | |
| 86 | + properties: | |
| 87 | + vsnvs: | |
| 87 | 88 | type: object |
| 88 | 89 | $ref: regulator.yaml# |
| 89 | 90 | description: |
| @@ -24,10 +24,10 @@ allOf: · 23 unmodified lines | ||
| 24 | 24 | select: |
| 25 | 25 | properties: |
| 26 | 26 | compatible: |
| 27 | − items: | |
| 28 | − - enum: | |
| 29 | − - sifive,fu540-c000-ccache | |
| 30 | − - sifive,fu740-c000-ccache | |
| 27 | + contains: | |
| 28 | + enum: | |
| 29 | + - sifive,fu540-c000-ccache | |
| 30 | + - sifive,fu740-c000-ccache | |
| 31 | 31 | |
| 32 | 32 | required: |
| 33 | 33 | - compatible |
| @@ -30,7 +30,6 @@ properties: · 29 unmodified lines | ||
| 30 | 30 | maxItems: 1 |
| 31 | 31 | |
| 32 | 32 | clocks: |
| 33 | − minItems: 2 | |
| 34 | 33 | items: |
| 35 | 34 | - description: PCLK clocks |
| 36 | 35 | - description: EXTCLK clocks. Faraday calls it CLK1HZ and says the clock |
| @@ -6,6 +6,7 @@ Required properties: · 5 unmodified lines | ||
| 6 | 6 | "ti,da830-mcasp-audio" : for both DA830 & DA850 platforms |
| 7 | 7 | "ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx) |
| 8 | 8 | "ti,dra7-mcasp-audio" : for DRA7xx platforms |
| 9 | + "ti,omap4-mcasp-audio" : for OMAP4 | |
| 9 | 10 | |
| 10 | 11 | - reg : Should contain reg specifiers for the entries in the reg-names property. |
| 11 | 12 | - reg-names : Should contain: |
| @@ -1,4 +1,4 @@ | ||
| 1 | −Invensense ICS-43432 MEMS microphone with I2S output. | |
| 1 | +Invensense ICS-43432-compatible MEMS microphone with I2S output. | |
| 2 | 2 | |
| 3 | 3 | There are no software configuration options for this device, indeed, the only |
| 4 | 4 | host connection is the I2S interface. Apart from requirements on clock |
| @@ -8,7 +8,9 @@ contain audio data. A hardware pin determines if the device outputs data · 3 unmodified lines | ||
| 8 | 8 | on the left or right channel of the I2S frame. |
| 9 | 9 | |
| 10 | 10 | Required properties: |
| 11 | − - compatible : Must be "invensense,ics43432" | |
| 11 | + - compatible: should be one of the following. | |
| 12 | + "invensense,ics43432": For the Invensense ICS43432 | |
| 13 | + "cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR | |
| 12 | 14 | |
| 13 | 15 | Example: |
| 14 | 16 | |
| @@ -0,0 +1,184 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Mediatek AFE PCM controller for mt8195 | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Trevor Wu <trevor.wu@mediatek.com> | |
| 11 | + | |
| 12 | +properties: | |
| 13 | + compatible: | |
| 14 | + const: mediatek,mt8195-audio | |
| 15 | + | |
| 16 | + reg: | |
| 17 | + maxItems: 1 | |
| 18 | + | |
| 19 | + interrupts: | |
| 20 | + maxItems: 1 | |
| 21 | + | |
| 22 | + mediatek,topckgen: | |
| 23 | + $ref: "/schemas/types.yaml#/definitions/phandle" | |
| 24 | + description: The phandle of the mediatek topckgen controller | |
| 25 | + | |
| 26 | + power-domains: | |
| 27 | + maxItems: 1 | |
| 28 | + | |
| 29 | + clocks: | |
| 30 | + items: | |
| 31 | + - description: 26M clock | |
| 32 | + - description: audio pll1 clock | |
| 33 | + - description: audio pll2 clock | |
| 34 | + - description: clock divider for i2si1_mck | |
| 35 | + - description: clock divider for i2si2_mck | |
| 36 | + - description: clock divider for i2so1_mck | |
| 37 | + - description: clock divider for i2so2_mck | |
| 38 | + - description: clock divider for dptx_mck | |
| 39 | + - description: a1sys hoping clock | |
| 40 | + - description: audio intbus clock | |
| 41 | + - description: audio hires clock | |
| 42 | + - description: audio local bus clock | |
| 43 | + - description: mux for dptx_mck | |
| 44 | + - description: mux for i2so1_mck | |
| 45 | + - description: mux for i2so2_mck | |
| 46 | + - description: mux for i2si1_mck | |
| 47 | + - description: mux for i2si2_mck | |
| 48 | + - description: audio infra 26M clock | |
| 49 | + - description: infra bus clock | |
| 50 | + | |
| 51 | + clock-names: | |
| 52 | + items: | |
| 53 | + - const: clk26m | |
| 54 | + - const: apll1_ck | |
| 55 | + - const: apll2_ck | |
| 56 | + - const: apll12_div0 | |
| 57 | + - const: apll12_div1 | |
| 58 | + - const: apll12_div2 | |
| 59 | + - const: apll12_div3 | |
| 60 | + - const: apll12_div9 | |
| 61 | + - const: a1sys_hp_sel | |
| 62 | + - const: aud_intbus_sel | |
| 63 | + - const: audio_h_sel | |
| 64 | + - const: audio_local_bus_sel | |
| 65 | + - const: dptx_m_sel | |
| 66 | + - const: i2so1_m_sel | |
| 67 | + - const: i2so2_m_sel | |
| 68 | + - const: i2si1_m_sel | |
| 69 | + - const: i2si2_m_sel | |
| 70 | + - const: infra_ao_audio_26m_b | |
| 71 | + - const: scp_adsp_audiodsp | |
| 72 | + | |
| 73 | + mediatek,etdm-in1-chn-disabled: | |
| 74 | + $ref: /schemas/types.yaml#/definitions/uint8-array | |
| 75 | + maxItems: 24 | |
| 76 | + description: Specify which input channel should be disabled. | |
| 77 | + | |
| 78 | + mediatek,etdm-in2-chn-disabled: | |
| 79 | + $ref: /schemas/types.yaml#/definitions/uint8-array | |
| 80 | + maxItems: 16 | |
| 81 | + description: Specify which input channel should be disabled. | |
| 82 | + | |
| 83 | +patternProperties: | |
| 84 | + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": | |
| 85 | + description: Specify etdm in mclk output rate for always on case. | |
| 86 | + | |
| 87 | + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$": | |
| 88 | + description: Specify etdm out mclk output rate for always on case. | |
| 89 | + | |
| 90 | + "^mediatek,etdm-in[1-2]-multi-pin-mode$": | |
| 91 | + type: boolean | |
| 92 | + description: if present, the etdm data mode is I2S. | |
| 93 | + | |
| 94 | + "^mediatek,etdm-out[1-3]-multi-pin-mode$": | |
| 95 | + type: boolean | |
| 96 | + description: if present, the etdm data mode is I2S. | |
| 97 | + | |
| 98 | + "^mediatek,etdm-in[1-2]-cowork-source$": | |
| 99 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 100 | + description: | | |
| 101 | + etdm modules can share the same external clock pin. Specify | |
| 102 | + which etdm clock source is required by this etdm in moudule. | |
| 103 | + enum: | |
| 104 | + - 0 # etdm1_in | |
| 105 | + - 1 # etdm2_in | |
| 106 | + - 2 # etdm1_out | |
| 107 | + - 3 # etdm2_out | |
| 108 | + | |
| 109 | + "^mediatek,etdm-out[1-2]-cowork-source$": | |
| 110 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 111 | + description: | | |
| 112 | + etdm modules can share the same external clock pin. Specify | |
| 113 | + which etdm clock source is required by this etdm out moudule. | |
| 114 | + enum: | |
| 115 | + - 0 # etdm1_in | |
| 116 | + - 1 # etdm2_in | |
| 117 | + - 2 # etdm1_out | |
| 118 | + - 3 # etdm2_out | |
| 119 | + | |
| 120 | +required: | |
| 121 | + - compatible | |
| 122 | + - reg | |
| 123 | + - interrupts | |
| 124 | + - mediatek,topckgen | |
| 125 | + - power-domains | |
| 126 | + - clocks | |
| 127 | + - clock-names | |
| 128 | + | |
| 129 | +additionalProperties: false | |
| 130 | + | |
| 131 | +examples: | |
| 132 | + - | | |
| 133 | + #include <dt-bindings/clock/mt8195-clk.h> | |
| 134 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 135 | + #include <dt-bindings/interrupt-controller/irq.h> | |
| 136 | + #include <dt-bindings/power/mt8195-power.h> | |
| 137 | + | |
| 138 | + afe: mt8195-afe-pcm@10890000 { | |
| 139 | + compatible = "mediatek,mt8195-audio"; | |
| 140 | + reg = <0x10890000 0x10000>; | |
| 141 | + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 142 | + mediatek,topckgen = <&topckgen>; | |
| 143 | + power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; | |
| 144 | + clocks = <&clk26m>, | |
| 145 | + <&topckgen CLK_TOP_APLL1>, | |
| 146 | + <&topckgen CLK_TOP_APLL2>, | |
| 147 | + <&topckgen CLK_TOP_APLL12_DIV0>, | |
| 148 | + <&topckgen CLK_TOP_APLL12_DIV1>, | |
| 149 | + <&topckgen CLK_TOP_APLL12_DIV2>, | |
| 150 | + <&topckgen CLK_TOP_APLL12_DIV3>, | |
| 151 | + <&topckgen CLK_TOP_APLL12_DIV9>, | |
| 152 | + <&topckgen CLK_TOP_A1SYS_HP_SEL>, | |
| 153 | + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, | |
| 154 | + <&topckgen CLK_TOP_AUDIO_H_SEL>, | |
| 155 | + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>, | |
| 156 | + <&topckgen CLK_TOP_DPTX_M_SEL>, | |
| 157 | + <&topckgen CLK_TOP_I2SO1_M_SEL>, | |
| 158 | + <&topckgen CLK_TOP_I2SO2_M_SEL>, | |
| 159 | + <&topckgen CLK_TOP_I2SI1_M_SEL>, | |
| 160 | + <&topckgen CLK_TOP_I2SI2_M_SEL>, | |
| 161 | + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, | |
| 162 | + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; | |
| 163 | + clock-names = "clk26m", | |
| 164 | + "apll1_ck", | |
| 165 | + "apll2_ck", | |
| 166 | + "apll12_div0", | |
| 167 | + "apll12_div1", | |
| 168 | + "apll12_div2", | |
| 169 | + "apll12_div3", | |
| 170 | + "apll12_div9", | |
| 171 | + "a1sys_hp_sel", | |
| 172 | + "aud_intbus_sel", | |
| 173 | + "audio_h_sel", | |
| 174 | + "audio_local_bus_sel", | |
| 175 | + "dptx_m_sel", | |
| 176 | + "i2so1_m_sel", | |
| 177 | + "i2so2_m_sel", | |
| 178 | + "i2si1_m_sel", | |
| 179 | + "i2si2_m_sel", | |
| 180 | + "infra_ao_audio_26m_b", | |
| 181 | + "scp_adsp_audiodsp"; | |
| 182 | + }; | |
| 183 | + | |
| 184 | +... | |
| @@ -0,0 +1,47 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/sound/mt8195-mt6359-rt1019-rt5682.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Mediatek MT8195 with MT6359, RT1019 and RT5682 ASoC sound card driver | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Trevor Wu <trevor.wu@mediatek.com> | |
| 11 | + | |
| 12 | +description: | |
| 13 | + This binding describes the MT8195 sound card. | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + const: mediatek,mt8195_mt6359_rt1019_rt5682 | |
| 18 | + | |
| 19 | + mediatek,platform: | |
| 20 | + $ref: "/schemas/types.yaml#/definitions/phandle" | |
| 21 | + description: The phandle of MT8195 ASoC platform. | |
| 22 | + | |
| 23 | + mediatek,dptx-codec: | |
| 24 | + $ref: "/schemas/types.yaml#/definitions/phandle" | |
| 25 | + description: The phandle of MT8195 Display Port Tx codec node. | |
| 26 | + | |
| 27 | + mediatek,hdmi-codec: | |
| 28 | + $ref: "/schemas/types.yaml#/definitions/phandle" | |
| 29 | + description: The phandle of MT8195 HDMI codec node. | |
| 30 | + | |
| 31 | +additionalProperties: false | |
| 32 | + | |
| 33 | +required: | |
| 34 | + - compatible | |
| 35 | + - mediatek,platform | |
| 36 | + | |
| 37 | +examples: | |
| 38 | + - | | |
| 39 | + | |
| 40 | + sound: mt8195-sound { | |
| 41 | + compatible = "mediatek,mt8195_mt6359_rt1019_rt5682"; | |
| 42 | + mediatek,platform = <&afe>; | |
| 43 | + pinctrl-names = "default"; | |
| 44 | + pinctrl-0 = <&aud_pins_default>; | |
| 45 | + }; | |
| 46 | + | |
| 47 | +... | |
| @@ -15,7 +15,9 @@ description: | · 14 unmodified lines | ||
| 15 | 15 | |
| 16 | 16 | properties: |
| 17 | 17 | compatible: |
| 18 | − const: realtek,rt1015p | |
| 18 | + enum: | |
| 19 | + - realtek,rt1015p | |
| 20 | + - realtek,rt1019p | |
| 19 | 21 | |
| 20 | 22 | sdb-gpios: |
| 21 | 23 | description: |
| @@ -0,0 +1,118 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Renesas RZ/G2L ASoC Sound Serial Interface (SSIF-2) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Biju Das <biju.das.jz@bp.renesas.com> | |
| 11 | + | |
| 12 | +properties: | |
| 13 | + compatible: | |
| 14 | + items: | |
| 15 | + - enum: | |
| 16 | + - renesas,r9a07g044-ssi # RZ/G2{L,LC} | |
| 17 | + - const: renesas,rz-ssi | |
| 18 | + | |
| 19 | + reg: | |
| 20 | + maxItems: 1 | |
| 21 | + | |
| 22 | + interrupts: | |
| 23 | + maxItems: 4 | |
| 24 | + | |
| 25 | + interrupt-names: | |
| 26 | + items: | |
| 27 | + - const: int_req | |
| 28 | + - const: dma_rx | |
| 29 | + - const: dma_tx | |
| 30 | + - const: dma_rt | |
| 31 | + | |
| 32 | + clocks: | |
| 33 | + maxItems: 4 | |
| 34 | + | |
| 35 | + clock-names: | |
| 36 | + items: | |
| 37 | + - const: ssi | |
| 38 | + - const: ssi_sfr | |
| 39 | + - const: audio_clk1 | |
| 40 | + - const: audio_clk2 | |
| 41 | + | |
| 42 | + power-domains: | |
| 43 | + maxItems: 1 | |
| 44 | + | |
| 45 | + resets: | |
| 46 | + maxItems: 1 | |
| 47 | + | |
| 48 | + dmas: | |
| 49 | + minItems: 1 | |
| 50 | + maxItems: 2 | |
| 51 | + description: | |
| 52 | + The first cell represents a phandle to dmac | |
| 53 | + The second cell specifies the encoded MID/RID values of the SSI port | |
| 54 | + connected to the DMA client and the slave channel configuration | |
| 55 | + parameters. | |
| 56 | + bits[0:9] - Specifies MID/RID value of a SSI channel as below | |
| 57 | + MID/RID value of SSI rx0 = 0x256 | |
| 58 | + MID/RID value of SSI tx0 = 0x255 | |
| 59 | + MID/RID value of SSI rx1 = 0x25a | |
| 60 | + MID/RID value of SSI tx1 = 0x259 | |
| 61 | + MID/RID value of SSI rt2 = 0x25f | |
| 62 | + MID/RID value of SSI rx3 = 0x262 | |
| 63 | + MID/RID value of SSI tx3 = 0x261 | |
| 64 | + bit[10] - HIEN = 1, Detects a request in response to the rising edge | |
| 65 | + of the signal | |
| 66 | + bit[11] - LVL = 0, Detects based on the edge | |
| 67 | + bits[12:14] - AM = 2, Bus cycle mode | |
| 68 | + bit[15] - TM = 0, Single transfer mode | |
| 69 | + | |
| 70 | + dma-names: | |
| 71 | + oneOf: | |
| 72 | + - items: | |
| 73 | + - const: tx | |
| 74 | + - const: rx | |
| 75 | + - items: | |
| 76 | + - const: rt | |
| 77 | + | |
| 78 | + '#sound-dai-cells': | |
| 79 | + const: 0 | |
| 80 | + | |
| 81 | +required: | |
| 82 | + - compatible | |
| 83 | + - reg | |
| 84 | + - interrupts | |
| 85 | + - interrupt-names | |
| 86 | + - clocks | |
| 87 | + - clock-names | |
| 88 | + - resets | |
| 89 | + - '#sound-dai-cells' | |
| 90 | + | |
| 91 | +additionalProperties: false | |
| 92 | + | |
| 93 | +examples: | |
| 94 | + - | | |
| 95 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 96 | + #include <dt-bindings/clock/r9a07g044-cpg.h> | |
| 97 | + | |
| 98 | + ssi0: ssi@10049c00 { | |
| 99 | + compatible = "renesas,r9a07g044-ssi", | |
| 100 | + "renesas,rz-ssi"; | |
| 101 | + reg = <0x10049c00 0x400>; | |
| 102 | + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
| 103 | + <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, | |
| 104 | + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, | |
| 105 | + <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; | |
| 106 | + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; | |
| 107 | + clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, | |
| 108 | + <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, | |
| 109 | + <&audio_clk1>, | |
| 110 | + <&audio_clk2>; | |
| 111 | + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; | |
| 112 | + power-domains = <&cpg>; | |
| 113 | + resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; | |
| 114 | + dmas = <&dmac 0x2655>, | |
| 115 | + <&dmac 0x2656>; | |
| 116 | + dma-names = "tx", "rx"; | |
| 117 | + #sound-dai-cells = <0>; | |
| 118 | + }; | |
| @@ -20,7 +20,9 @@ properties: · 19 unmodified lines | ||
| 20 | 20 | - items: |
| 21 | 21 | - enum: |
| 22 | 22 | - rockchip,px30-i2s |
| 23 | + - rockchip,rk1808-i2s | |
| 23 | 24 | - rockchip,rk3036-i2s |
| 25 | + - rockchip,rk3128-i2s | |
| 24 | 26 | - rockchip,rk3188-i2s |
| 25 | 27 | - rockchip,rk3228-i2s |
| 26 | 28 | - rockchip,rk3288-i2s |
| @@ -29,6 +31,7 @@ properties: · 2 unmodified lines | ||
| 29 | 31 | - rockchip,rk3366-i2s |
| 30 | 32 | - rockchip,rk3368-i2s |
| 31 | 33 | - rockchip,rk3399-i2s |
| 34 | + - rockchip,rv1126-i2s | |
| 32 | 35 | - const: rockchip,rk3066-i2s |
| 33 | 36 | |
| 34 | 37 | reg: |
| @@ -61,6 +64,14 @@ properties: · 26 unmodified lines | ||
| 61 | 64 | power-domains: |
| 62 | 65 | maxItems: 1 |
| 63 | 66 | |
| 67 | + reset-names: | |
| 68 | + items: | |
| 69 | + - const: reset-m | |
| 70 | + - const: reset-h | |
| 71 | + | |
| 72 | + resets: | |
| 73 | + maxItems: 2 | |
| 74 | + | |
| 64 | 75 | rockchip,capture-channels: |
| 65 | 76 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 66 | 77 | default: 2 |
| @@ -23,6 +23,7 @@ properties: · 22 unmodified lines | ||
| 23 | 23 | - const: rockchip,rk3366-spdif |
| 24 | 24 | - const: rockchip,rk3368-spdif |
| 25 | 25 | - const: rockchip,rk3399-spdif |
| 26 | + - const: rockchip,rk3568-spdif | |
| 26 | 27 | - items: |
| 27 | 28 | - enum: |
| 28 | 29 | - rockchip,rk3188-spdif |
| @@ -79,22 +79,7 @@ properties: · 78 unmodified lines | ||
| 79 | 79 | description: |
| 80 | 80 | The SPI controller acts as a slave, instead of a master. |
| 81 | 81 | |
| 82 | −allOf: | |
| 83 | − - if: | |
| 84 | − not: | |
| 85 | − required: | |
| 86 | − - spi-slave | |
| 87 | − then: | |
| 88 | − properties: | |
| 89 | − "#address-cells": | |
| 90 | − const: 1 | |
| 91 | − else: | |
| 92 | − properties: | |
| 93 | − "#address-cells": | |
| 94 | − const: 0 | |
| 95 | − | |
| 96 | −patternProperties: | |
| 97 | − "^slave$": | |
| 82 | + slave: | |
| 98 | 83 | type: object |
| 99 | 84 | |
| 100 | 85 | properties: |
| @@ -105,6 +90,7 @@ patternProperties: · 4 unmodified lines | ||
| 105 | 90 | required: |
| 106 | 91 | - compatible |
| 107 | 92 | |
| 93 | +patternProperties: | |
| 108 | 94 | "^.*@[0-9a-f]+$": |
| 109 | 95 | type: object |
| 110 | 96 | |
| @@ -180,6 +166,20 @@ patternProperties: · 69 unmodified lines | ||
| 180 | 166 | - compatible |
| 181 | 167 | - reg |
| 182 | 168 | |
| 169 | +allOf: | |
| 170 | + - if: | |
| 171 | + not: | |
| 172 | + required: | |
| 173 | + - spi-slave | |
| 174 | + then: | |
| 175 | + properties: | |
| 176 | + "#address-cells": | |
| 177 | + const: 1 | |
| 178 | + else: | |
| 179 | + properties: | |
| 180 | + "#address-cells": | |
| 181 | + const: 0 | |
| 182 | + | |
| 183 | 183 | additionalProperties: true |
| 184 | 184 | |
| 185 | 185 | examples: |
| @@ -25,14 +25,12 @@ properties: · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | interrupts: |
| 27 | 27 | minItems: 1 |
| 28 | − maxItems: 2 | |
| 29 | 28 | items: |
| 30 | 29 | - description: Host controller interrupt |
| 31 | 30 | - description: Device controller interrupt in isp1761 |
| 32 | 31 | |
| 33 | 32 | interrupt-names: |
| 34 | 33 | minItems: 1 |
| 35 | − maxItems: 2 | |
| 36 | 34 | items: |
| 37 | 35 | - const: host |
| 38 | 36 | - const: peripheral |
| @@ -271,6 +271,8 @@ patternProperties: · 270 unmodified lines | ||
| 271 | 271 | description: Shenzen Chuangsiqi Technology Co.,Ltd. |
| 272 | 272 | "^cubietech,.*": |
| 273 | 273 | description: Cubietech, Ltd. |
| 274 | + "^cui,.*": | |
| 275 | + description: CUI Devices | |
| 274 | 276 | "^cypress,.*": |
| 275 | 277 | description: Cypress Semiconductor Corporation |
| 276 | 278 | "^cznic,.*": |
| @@ -69,17 +69,17 @@ early userspace image can be built by an unprivileged user. · 68 unmodified lines | ||
| 69 | 69 | |
| 70 | 70 | As a technical note, when directories and files are specified, the |
| 71 | 71 | entire CONFIG_INITRAMFS_SOURCE is passed to |
| 72 | −usr/gen_initramfs_list.sh. This means that CONFIG_INITRAMFS_SOURCE | |
| 72 | +usr/gen_initramfs.sh. This means that CONFIG_INITRAMFS_SOURCE | |
| 73 | 73 | can really be interpreted as any legal argument to |
| 74 | −gen_initramfs_list.sh. If a directory is specified as an argument then | |
| 74 | +gen_initramfs.sh. If a directory is specified as an argument then | |
| 75 | 75 | the contents are scanned, uid/gid translation is performed, and |
| 76 | 76 | usr/gen_init_cpio file directives are output. If a directory is |
| 77 | −specified as an argument to usr/gen_initramfs_list.sh then the | |
| 77 | +specified as an argument to usr/gen_initramfs.sh then the | |
| 78 | 78 | contents of the file are simply copied to the output. All of the output |
| 79 | 79 | directives from directory scanning and file contents copying are |
| 80 | 80 | processed by usr/gen_init_cpio. |
| 81 | 81 | |
| 82 | −See also 'usr/gen_initramfs_list.sh -h'. | |
| 82 | +See also 'usr/gen_initramfs.sh -h'. | |
| 83 | 83 | |
| 84 | 84 | Where's this all leading? |
| 85 | 85 | ========================= |
| @@ -0,0 +1,32 @@ | ||
| 1 | +# | |
| 2 | +# Feature name: thread-info-in-task | |
| 3 | +# Kconfig: THREAD_INFO_IN_TASK | |
| 4 | +# description: arch makes use of the core kernel facility to embedd thread_info in task_struct | |
| 5 | +# | |
| 6 | + ----------------------- | |
| 7 | + | arch |status| | |
| 8 | + ----------------------- | |
| 9 | + | alpha: | TODO | | |
| 10 | + | arc: | TODO | | |
| 11 | + | arm: | TODO | | |
| 12 | + | arm64: | ok | | |
| 13 | + | csky: | TODO | | |
| 14 | + | h8300: | TODO | | |
| 15 | + | hexagon: | TODO | | |
| 16 | + | ia64: | TODO | | |
| 17 | + | m68k: | TODO | | |
| 18 | + | microblaze: | TODO | | |
| 19 | + | mips: | TODO | | |
| 20 | + | nds32: | ok | | |
| 21 | + | nios2: | TODO | | |
| 22 | + | openrisc: | TODO | | |
| 23 | + | parisc: | TODO | | |
| 24 | + | powerpc: | ok | | |
| 25 | + | riscv: | ok | | |
| 26 | + | s390: | ok | | |
| 27 | + | sh: | TODO | | |
| 28 | + | sparc: | TODO | | |
| 29 | + | um: | TODO | | |
| 30 | + | x86: | ok | | |
| 31 | + | xtensa: | TODO | | |
| 32 | + ----------------------- | |
| @@ -22,7 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | | openrisc: | TODO | |
| 23 | 23 | | parisc: | TODO | |
| 24 | 24 | | powerpc: | ok | |
| 25 | − | riscv: | TODO | | |
| 25 | + | riscv: | ok | | |
| 26 | 26 | | s390: | TODO | |
| 27 | 27 | | sh: | ok | |
| 28 | 28 | | sparc: | TODO | |
| @@ -170,7 +170,7 @@ Documentation/driver-api/early-userspace/early_userspace_support.rst for more de · 169 unmodified lines | ||
| 170 | 170 | The kernel does not depend on external cpio tools. If you specify a |
| 171 | 171 | directory instead of a configuration file, the kernel's build infrastructure |
| 172 | 172 | creates a configuration file from that directory (usr/Makefile calls |
| 173 | −usr/gen_initramfs_list.sh), and proceeds to package up that directory | |
| 173 | +usr/gen_initramfs.sh), and proceeds to package up that directory | |
| 174 | 174 | using the config file (by feeding it to usr/gen_init_cpio, which is created |
| 175 | 175 | from usr/gen_init_cpio.c). The kernel's build-time cpio creation code is |
| 176 | 176 | entirely self-contained, and the kernel's boot-time extractor is also |
| @@ -18,114 +18,5 @@ real, with all the uAPI bits is: · 17 unmodified lines | ||
| 18 | 18 | * Route shmem backend over to TTM SYSTEM for discrete |
| 19 | 19 | * TTM purgeable object support |
| 20 | 20 | * Move i915 buddy allocator over to TTM |
| 21 | − * MMAP ioctl mode(see `I915 MMAP`_) | |
| 22 | − * SET/GET ioctl caching(see `I915 SET/GET CACHING`_) | |
| 23 | 21 | * Send RFC(with mesa-dev on cc) for final sign off on the uAPI |
| 24 | 22 | * Add pciid for DG1 and turn on uAPI for real |
| 25 | − | |
| 26 | −New object placement and region query uAPI | |
| 27 | −========================================== | |
| 28 | −Starting from DG1 we need to give userspace the ability to allocate buffers from | |
| 29 | −device local-memory. Currently the driver supports gem_create, which can place | |
| 30 | −buffers in system memory via shmem, and the usual assortment of other | |
| 31 | −interfaces, like dumb buffers and userptr. | |
| 32 | − | |
| 33 | −To support this new capability, while also providing a uAPI which will work | |
| 34 | −beyond just DG1, we propose to offer three new bits of uAPI: | |
| 35 | − | |
| 36 | −DRM_I915_QUERY_MEMORY_REGIONS | |
| 37 | −----------------------------- | |
| 38 | −New query ID which allows userspace to discover the list of supported memory | |
| 39 | −regions(like system-memory and local-memory) for a given device. We identify | |
| 40 | −each region with a class and instance pair, which should be unique. The class | |
| 41 | −here would be DEVICE or SYSTEM, and the instance would be zero, on platforms | |
| 42 | −like DG1. | |
| 43 | − | |
| 44 | −Side note: The class/instance design is borrowed from our existing engine uAPI, | |
| 45 | −where we describe every physical engine in terms of its class, and the | |
| 46 | −particular instance, since we can have more than one per class. | |
| 47 | − | |
| 48 | −In the future we also want to expose more information which can further | |
| 49 | −describe the capabilities of a region. | |
| 50 | − | |
| 51 | −.. kernel-doc:: include/uapi/drm/i915_drm.h | |
| 52 | − :functions: drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_memory_region_info drm_i915_query_memory_regions | |
| 53 | − | |
| 54 | −GEM_CREATE_EXT | |
| 55 | −-------------- | |
| 56 | −New ioctl which is basically just gem_create but now allows userspace to provide | |
| 57 | −a chain of possible extensions. Note that if we don't provide any extensions and | |
| 58 | −set flags=0 then we get the exact same behaviour as gem_create. | |
| 59 | − | |
| 60 | −Side note: We also need to support PXP[1] in the near future, which is also | |
| 61 | −applicable to integrated platforms, and adds its own gem_create_ext extension, | |
| 62 | −which basically lets userspace mark a buffer as "protected". | |
| 63 | − | |
| 64 | −.. kernel-doc:: include/uapi/drm/i915_drm.h | |
| 65 | − :functions: drm_i915_gem_create_ext | |
| 66 | − | |
| 67 | −I915_GEM_CREATE_EXT_MEMORY_REGIONS | |
| 68 | −---------------------------------- | |
| 69 | −Implemented as an extension for gem_create_ext, we would now allow userspace to | |
| 70 | −optionally provide an immutable list of preferred placements at creation time, | |
| 71 | −in priority order, for a given buffer object. For the placements we expect | |
| 72 | −them each to use the class/instance encoding, as per the output of the regions | |
| 73 | −query. Having the list in priority order will be useful in the future when | |
| 74 | −placing an object, say during eviction. | |
| 75 | − | |
| 76 | −.. kernel-doc:: include/uapi/drm/i915_drm.h | |
| 77 | − :functions: drm_i915_gem_create_ext_memory_regions | |
| 78 | − | |
| 79 | −One fair criticism here is that this seems a little over-engineered[2]. If we | |
| 80 | −just consider DG1 then yes, a simple gem_create.flags or something is totally | |
| 81 | −all that's needed to tell the kernel to allocate the buffer in local-memory or | |
| 82 | −whatever. However looking to the future we need uAPI which can also support | |
| 83 | −upcoming Xe HP multi-tile architecture in a sane way, where there can be | |
| 84 | −multiple local-memory instances for a given device, and so using both class and | |
| 85 | −instance in our uAPI to describe regions is desirable, although specifically | |
| 86 | −for DG1 it's uninteresting, since we only have a single local-memory instance. | |
| 87 | − | |
| 88 | −Existing uAPI issues | |
| 89 | −==================== | |
| 90 | −Some potential issues we still need to resolve. | |
| 91 | − | |
| 92 | −I915 MMAP | |
| 93 | −--------- | |
| 94 | −In i915 there are multiple ways to MMAP GEM object, including mapping the same | |
| 95 | −object using different mapping types(WC vs WB), i.e multiple active mmaps per | |
| 96 | −object. TTM expects one MMAP at most for the lifetime of the object. If it | |
| 97 | −turns out that we have to backpedal here, there might be some potential | |
| 98 | −userspace fallout. | |
| 99 | − | |
| 100 | −I915 SET/GET CACHING | |
| 101 | −-------------------- | |
| 102 | −In i915 we have set/get_caching ioctl. TTM doesn't let us to change this, but | |
| 103 | −DG1 doesn't support non-snooped pcie transactions, so we can just always | |
| 104 | −allocate as WB for smem-only buffers. If/when our hw gains support for | |
| 105 | −non-snooped pcie transactions then we must fix this mode at allocation time as | |
| 106 | −a new GEM extension. | |
| 107 | − | |
| 108 | −This is related to the mmap problem, because in general (meaning, when we're | |
| 109 | −not running on intel cpus) the cpu mmap must not, ever, be inconsistent with | |
| 110 | −allocation mode. | |
| 111 | − | |
| 112 | −Possible idea is to let the kernel picks the mmap mode for userspace from the | |
| 113 | −following table: | |
| 114 | − | |
| 115 | −smem-only: WB. Userspace does not need to call clflush. | |
| 116 | − | |
| 117 | −smem+lmem: We only ever allow a single mode, so simply allocate this as uncached | |
| 118 | −memory, and always give userspace a WC mapping. GPU still does snooped access | |
| 119 | −here(assuming we can't turn it off like on DG1), which is a bit inefficient. | |
| 120 | − | |
| 121 | −lmem only: always WC | |
| 122 | − | |
| 123 | −This means on discrete you only get a single mmap mode, all others must be | |
| 124 | −rejected. That's probably going to be a new default mode or something like | |
| 125 | −that. | |
| 126 | − | |
| 127 | −Links | |
| 128 | −===== | |
| 129 | −[1] https://patchwork.freedesktop.org/series/86798/ | |
| 130 | − | |
| 131 | −[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599#note_553791 | |
| @@ -17,6 +17,7 @@ Introduction · 16 unmodified lines | ||
| 17 | 17 | busses/index |
| 18 | 18 | i2c-topology |
| 19 | 19 | muxes/i2c-mux-gpio |
| 20 | + i2c-sysfs | |
| 20 | 21 | |
| 21 | 22 | Writing device drivers |
| 22 | 23 | ====================== |
| @@ -243,8 +243,8 @@ Configuration Flags and Socket Options · 242 unmodified lines | ||
| 243 | 243 | These are the various configuration flags that can be used to control |
| 244 | 244 | and monitor the behavior of AF_XDP sockets. |
| 245 | 245 | |
| 246 | −XDP_COPY and XDP_ZERO_COPY bind flags | |
| 247 | −------------------------------------- | |
| 246 | +XDP_COPY and XDP_ZEROCOPY bind flags | |
| 247 | +------------------------------------ | |
| 248 | 248 | |
| 249 | 249 | When you bind to a socket, the kernel will first try to use zero-copy |
| 250 | 250 | copy. If zero-copy is not supported, it will fall back on using copy |
| @@ -252,7 +252,7 @@ mode, i.e. copying all packets out to user space. But if you would · 1 unmodified line | ||
| 252 | 252 | like to force a certain mode, you can use the following flags. If you |
| 253 | 253 | pass the XDP_COPY flag to the bind call, the kernel will force the |
| 254 | 254 | socket into copy mode. If it cannot use copy mode, the bind call will |
| 255 | −fail with an error. Conversely, the XDP_ZERO_COPY flag will force the | |
| 255 | +fail with an error. Conversely, the XDP_ZEROCOPY flag will force the | |
| 256 | 256 | socket into zero-copy mode or fail. |
| 257 | 257 | |
| 258 | 258 | XDP_SHARED_UMEM bind flag |
| @@ -212,6 +212,7 @@ Userspace to kernel: · 211 unmodified lines | ||
| 212 | 212 | ``ETHTOOL_MSG_FEC_SET`` set FEC settings |
| 213 | 213 | ``ETHTOOL_MSG_MODULE_EEPROM_GET`` read SFP module EEPROM |
| 214 | 214 | ``ETHTOOL_MSG_STATS_GET`` get standard statistics |
| 215 | + ``ETHTOOL_MSG_PHC_VCLOCKS_GET`` get PHC virtual clocks info | |
| 215 | 216 | ===================================== ================================ |
| 216 | 217 | |
| 217 | 218 | Kernel to userspace: |
| @@ -250,6 +251,7 @@ Kernel to userspace: · 32 unmodified lines | ||
| 250 | 251 | ``ETHTOOL_MSG_FEC_NTF`` FEC settings |
| 251 | 252 | ``ETHTOOL_MSG_MODULE_EEPROM_GET_REPLY`` read SFP module EEPROM |
| 252 | 253 | ``ETHTOOL_MSG_STATS_GET_REPLY`` standard statistics |
| 254 | + ``ETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY`` PHC virtual clocks info | |
| 253 | 255 | ======================================== ================================= |
| 254 | 256 | |
| 255 | 257 | ``GET`` requests are sent by userspace applications to retrieve device |
| @@ -1477,6 +1479,25 @@ Low and high bounds are inclusive, for example: · 1221 unmodified lines | ||
| 1477 | 1479 | etherStatsPkts512to1023Octets 512 1023 |
| 1478 | 1480 | ============================= ==== ==== |
| 1479 | 1481 | |
| 1482 | +PHC_VCLOCKS_GET | |
| 1483 | +=============== | |
| 1484 | + | |
| 1485 | +Query device PHC virtual clocks information. | |
| 1486 | + | |
| 1487 | +Request contents: | |
| 1488 | + | |
| 1489 | + ==================================== ====== ========================== | |
| 1490 | + ``ETHTOOL_A_PHC_VCLOCKS_HEADER`` nested request header | |
| 1491 | + ==================================== ====== ========================== | |
| 1492 | + | |
| 1493 | +Kernel response contents: | |
| 1494 | + | |
| 1495 | + ==================================== ====== ========================== | |
| 1496 | + ``ETHTOOL_A_PHC_VCLOCKS_HEADER`` nested reply header | |
| 1497 | + ``ETHTOOL_A_PHC_VCLOCKS_NUM`` u32 PHC virtual clocks number | |
| 1498 | + ``ETHTOOL_A_PHC_VCLOCKS_INDEX`` s32 PHC index array | |
| 1499 | + ==================================== ====== ========================== | |
| 1500 | + | |
| 1480 | 1501 | Request translation |
| 1481 | 1502 | =================== |
| 1482 | 1503 | |
| @@ -1575,4 +1596,5 @@ are netlink only. · 92 unmodified lines | ||
| 1575 | 1596 | n/a ``ETHTOOL_MSG_CABLE_TEST_ACT`` |
| 1576 | 1597 | n/a ``ETHTOOL_MSG_CABLE_TEST_TDR_ACT`` |
| 1577 | 1598 | n/a ``ETHTOOL_MSG_TUNNEL_INFO_GET`` |
| 1599 | + n/a ``ETHTOOL_MSG_PHC_VCLOCKS_GET`` | |
| 1578 | 1600 | =================================== ===================================== |
| @@ -826,7 +826,7 @@ tcp_fastopen_blackhole_timeout_sec - INTEGER · 825 unmodified lines | ||
| 826 | 826 | initial value when the blackhole issue goes away. |
| 827 | 827 | 0 to disable the blackhole detection. |
| 828 | 828 | |
| 829 | − By default, it is set to 1hr. | |
| 829 | + By default, it is set to 0 (feature is disabled). | |
| 830 | 830 | |
| 831 | 831 | tcp_fastopen_key - list of comma separated 32-digit hexadecimal INTEGERs |
| 832 | 832 | The list consists of a primary key and an optional backup key. The |
| @@ -228,6 +228,23 @@ before posting to the mailing list. The patchwork build bot instance · 227 unmodified lines | ||
| 228 | 228 | gets overloaded very easily and netdev@vger really doesn't need more |
| 229 | 229 | traffic if we can help it. |
| 230 | 230 | |
| 231 | +netdevsim is great, can I extend it for my out-of-tree tests? | |
| 232 | +------------------------------------------------------------- | |
| 233 | + | |
| 234 | +No, `netdevsim` is a test vehicle solely for upstream tests. | |
| 235 | +(Please add your tests under tools/testing/selftests/.) | |
| 236 | + | |
| 237 | +We also give no guarantees that `netdevsim` won't change in the future | |
| 238 | +in a way which would break what would normally be considered uAPI. | |
| 239 | + | |
| 240 | +Is netdevsim considered a "user" of an API? | |
| 241 | +------------------------------------------- | |
| 242 | + | |
| 243 | +Linux kernel has a long standing rule that no API should be added unless | |
| 244 | +it has a real, in-tree user. Mock-ups and tests based on `netdevsim` are | |
| 245 | +strongly encouraged when adding new APIs, but `netdevsim` in itself | |
| 246 | +is **not** considered a use case/user. | |
| 247 | + | |
| 231 | 248 | Any other tips to help ensure my net/net-next patch gets OK'd? |
| 232 | 249 | -------------------------------------------------------------- |
| 233 | 250 | Attention to detail. Re-read your own work as if you were the |
| @@ -110,6 +110,12 @@ nf_conntrack_tcp_be_liberal - BOOLEAN · 109 unmodified lines | ||
| 110 | 110 | Be conservative in what you do, be liberal in what you accept from others. |
| 111 | 111 | If it's non-zero, we mark only out of window RST segments as INVALID. |
| 112 | 112 | |
| 113 | +nf_conntrack_tcp_ignore_invalid_rst - BOOLEAN | |
| 114 | + - 0 - disabled (default) | |
| 115 | + - 1 - enabled | |
| 116 | + | |
| 117 | + If it's 1, we don't mark out of window RST segments as INVALID. | |
| 118 | + | |
| 113 | 119 | nf_conntrack_tcp_loose - BOOLEAN |
| 114 | 120 | - 0 - disabled |
| 115 | 121 | - not 0 - enabled (default) |
| @@ -185,19 +191,9 @@ nf_flowtable_tcp_timeout - INTEGER (seconds) · 69 unmodified lines | ||
| 185 | 191 | TCP connections may be offloaded from nf conntrack to nf flow table. |
| 186 | 192 | Once aged, the connection is returned to nf conntrack with tcp pickup timeout. |
| 187 | 193 | |
| 188 | −nf_flowtable_tcp_pickup - INTEGER (seconds) | |
| 189 | − default 120 | |
| 190 | − | |
| 191 | − TCP connection timeout after being aged from nf flow table offload. | |
| 192 | − | |
| 193 | 194 | nf_flowtable_udp_timeout - INTEGER (seconds) |
| 194 | 195 | default 30 |
| 195 | 196 | |
| 196 | 197 | Control offload timeout for udp connections. |
| 197 | 198 | UDP connections may be offloaded from nf conntrack to nf flow table. |
| 198 | 199 | Once aged, the connection is returned to nf conntrack with udp pickup timeout. |
| 199 | − | |
| 200 | −nf_flowtable_udp_pickup - INTEGER (seconds) | |
| 201 | − default 30 | |
| 202 | − | |
| 203 | − UDP connection timeout after being aged from nf flow table offload. | |
| @@ -73,7 +73,9 @@ IF_OPER_LOWERLAYERDOWN (3): · 72 unmodified lines | ||
| 73 | 73 | state (f.e. VLAN). |
| 74 | 74 | |
| 75 | 75 | IF_OPER_TESTING (4): |
| 76 | − Unused in current kernel. | |
| 76 | + Interface is in testing mode, for example executing driver self-tests | |
| 77 | + or media (cable) test. It can't be used for normal traffic until tests | |
| 78 | + complete. | |
| 77 | 79 | |
| 78 | 80 | IF_OPER_DORMANT (5): |
| 79 | 81 | Interface is L1 up, but waiting for an external event, f.e. for a |
| @@ -111,7 +113,7 @@ it as lower layer. · 31 unmodified lines | ||
| 111 | 113 | |
| 112 | 114 | Note that for certain kind of soft-devices, which are not managing any |
| 113 | 115 | real hardware, it is possible to set this bit from userspace. One |
| 114 | −should use TVL IFLA_CARRIER to do so. | |
| 116 | +should use TLV IFLA_CARRIER to do so. | |
| 115 | 117 | |
| 116 | 118 | netif_carrier_ok() can be used to query that bit. |
| 117 | 119 | |
| @@ -4,10 +4,125 @@ · 3 unmodified lines | ||
| 4 | 4 | Linux Kernel TIPC |
| 5 | 5 | ================= |
| 6 | 6 | |
| 7 | −TIPC (Transparent Inter Process Communication) is a protocol that is | |
| 8 | −specially designed for intra-cluster communication. | |
| 7 | +Introduction | |
| 8 | +============ | |
| 9 | 9 | |
| 10 | −For more information about TIPC, see http://tipc.sourceforge.net. | |
| 10 | +TIPC (Transparent Inter Process Communication) is a protocol that is specially | |
| 11 | +designed for intra-cluster communication. It can be configured to transmit | |
| 12 | +messages either on UDP or directly across Ethernet. Message delivery is | |
| 13 | +sequence guaranteed, loss free and flow controlled. Latency times are shorter | |
| 14 | +than with any other known protocol, while maximal throughput is comparable to | |
| 15 | +that of TCP. | |
| 16 | + | |
| 17 | +TIPC Features | |
| 18 | +------------- | |
| 19 | + | |
| 20 | +- Cluster wide IPC service | |
| 21 | + | |
| 22 | + Have you ever wished you had the convenience of Unix Domain Sockets even when | |
| 23 | + transmitting data between cluster nodes? Where you yourself determine the | |
| 24 | + addresses you want to bind to and use? Where you don't have to perform DNS | |
| 25 | + lookups and worry about IP addresses? Where you don't have to start timers | |
| 26 | + to monitor the continuous existence of peer sockets? And yet without the | |
| 27 | + downsides of that socket type, such as the risk of lingering inodes? | |
| 28 | + | |
| 29 | + Welcome to the Transparent Inter Process Communication service, TIPC in short, | |
| 30 | + which gives you all of this, and a lot more. | |
| 31 | + | |
| 32 | +- Service Addressing | |
| 33 | + | |
| 34 | + A fundamental concept in TIPC is that of Service Addressing which makes it | |
| 35 | + possible for a programmer to chose his own address, bind it to a server | |
| 36 | + socket and let client programs use only that address for sending messages. | |
| 37 | + | |
| 38 | +- Service Tracking | |
| 39 | + | |
| 40 | + A client wanting to wait for the availability of a server, uses the Service | |
| 41 | + Tracking mechanism to subscribe for binding and unbinding/close events for | |
| 42 | + sockets with the associated service address. | |
| 43 | + | |
| 44 | + The service tracking mechanism can also be used for Cluster Topology Tracking, | |
| 45 | + i.e., subscribing for availability/non-availability of cluster nodes. | |
| 46 | + | |
| 47 | + Likewise, the service tracking mechanism can be used for Cluster Connectivity | |
| 48 | + Tracking, i.e., subscribing for up/down events for individual links between | |
| 49 | + cluster nodes. | |
| 50 | + | |
| 51 | +- Transmission Modes | |
| 52 | + | |
| 53 | + Using a service address, a client can send datagram messages to a server socket. | |
| 54 | + | |
| 55 | + Using the same address type, it can establish a connection towards an accepting | |
| 56 | + server socket. | |
| 57 | + | |
| 58 | + It can also use a service address to create and join a Communication Group, | |
| 59 | + which is the TIPC manifestation of a brokerless message bus. | |
| 60 | + | |
| 61 | + Multicast with very good performance and scalability is available both in | |
| 62 | + datagram mode and in communication group mode. | |
| 63 | + | |
| 64 | +- Inter Node Links | |
| 65 | + | |
| 66 | + Communication between any two nodes in a cluster is maintained by one or two | |
| 67 | + Inter Node Links, which both guarantee data traffic integrity and monitor | |
| 68 | + the peer node's availability. | |
| 69 | + | |
| 70 | +- Cluster Scalability | |
| 71 | + | |
| 72 | + By applying the Overlapping Ring Monitoring algorithm on the inter node links | |
| 73 | + it is possible to scale TIPC clusters up to 1000 nodes with a maintained | |
| 74 | + neighbor failure discovery time of 1-2 seconds. For smaller clusters this | |
| 75 | + time can be made much shorter. | |
| 76 | + | |
| 77 | +- Neighbor Discovery | |
| 78 | + | |
| 79 | + Neighbor Node Discovery in the cluster is done by Ethernet broadcast or UDP | |
| 80 | + multicast, when any of those services are available. If not, configured peer | |
| 81 | + IP addresses can be used. | |
| 82 | + | |
| 83 | +- Configuration | |
| 84 | + | |
| 85 | + When running TIPC in single node mode no configuration whatsoever is needed. | |
| 86 | + When running in cluster mode TIPC must as a minimum be given a node address | |
| 87 | + (before Linux 4.17) and told which interface to attach to. The "tipc" | |
| 88 | + configuration tool makes is possible to add and maintain many more | |
| 89 | + configuration parameters. | |
| 90 | + | |
| 91 | +- Performance | |
| 92 | + | |
| 93 | + TIPC message transfer latency times are better than in any other known protocol. | |
| 94 | + Maximal byte throughput for inter-node connections is still somewhat lower than | |
| 95 | + for TCP, while they are superior for intra-node and inter-container throughput | |
| 96 | + on the same host. | |
| 97 | + | |
| 98 | +- Language Support | |
| 99 | + | |
| 100 | + The TIPC user API has support for C, Python, Perl, Ruby, D and Go. | |
| 101 | + | |
| 102 | +More Information | |
| 103 | +---------------- | |
| 104 | + | |
| 105 | +- How to set up TIPC: | |
| 106 | + | |
| 107 | + http://tipc.io/getting_started.html | |
| 108 | + | |
| 109 | +- How to program with TIPC: | |
| 110 | + | |
| 111 | + http://tipc.io/programming.html | |
| 112 | + | |
| 113 | +- How to contribute to TIPC: | |
| 114 | + | |
| 115 | +- http://tipc.io/contacts.html | |
| 116 | + | |
| 117 | +- More details about TIPC specification: | |
| 118 | + | |
| 119 | + http://tipc.io/protocol.html | |
| 120 | + | |
| 121 | + | |
| 122 | +Implementation | |
| 123 | +============== | |
| 124 | + | |
| 125 | +TIPC is implemented as a kernel module in net/tipc/ directory. | |
| 11 | 126 | |
| 12 | 127 | TIPC Base Types |
| 13 | 128 | --------------- |
| @@ -191,7 +191,7 @@ Documentation written by Tom Zanussi · 190 unmodified lines | ||
| 191 | 191 | with the event, in nanoseconds. May be |
| 192 | 192 | modified by .usecs to have timestamps |
| 193 | 193 | interpreted as microseconds. |
| 194 | − cpu int the cpu on which the event occurred. | |
| 194 | + common_cpu int the cpu on which the event occurred. | |
| 195 | 195 | ====================== ==== ======================================= |
| 196 | 196 | |
| 197 | 197 | Extended error information |
| @@ -47,7 +47,7 @@ · 46 unmodified lines | ||
| 47 | 47 | （顺便说一句，值得注意的是，合并窗口期间集成的更改并不是凭空产生的；它们是经 |
| 48 | 48 | 提前收集、测试和分级的。稍后将详细描述该过程的工作方式。） |
| 49 | 49 | |
| 50 | −合并窗口持续大约两周。在这段时间结束时，LinusTorvalds将声明窗口已关闭，并 | |
| 50 | +合并窗口持续大约两周。在这段时间结束时，Linus Torvalds将声明窗口已关闭，并 | |
| 51 | 51 | 释放第一个“rc”内核。例如，对于目标为5.6的内核，在合并窗口结束时发生的释放 |
| 52 | 52 | 将被称为5.6-rc1。-rc1 版本是一个信号，表示合并新特性的时间已经过去，稳定下一 |
| 53 | 53 | 个内核的时间已经到来。 |
| @@ -168,7 +168,7 @@ Greg Kroah-Hartman领导。稳定团队将使用5.x.y编号方案不定期地发 · 114 unmodified lines | ||
| 168 | 168 | 补丁如何进入内核 |
| 169 | 169 | ---------------- |
| 170 | 170 | |
| 171 | −只有一个人可以将补丁合并到主线内核存储库中：LinusTorvalds。但是，在进入 | |
| 171 | +只有一个人可以将补丁合并到主线内核存储库中：Linus Torvalds。但是，在进入 | |
| 172 | 172 | 2.6.38内核的9500多个补丁中，只有112个（大约1.3%）是由Linus自己直接选择的。 |
| 173 | 173 | 内核项目已经发展到一个没有一个开发人员可以在没有支持的情况下检查和选择每个 |
| 174 | 174 | 补丁的规模。内核开发人员处理这种增长的方式是使用围绕信任链构建的助理系统。 |
| @@ -263,7 +263,7 @@ Userspace can also add file descriptors to the notifying process via · 262 unmodified lines | ||
| 263 | 263 | ``ioctl(SECCOMP_IOCTL_NOTIF_ADDFD)``. The ``id`` member of |
| 264 | 264 | ``struct seccomp_notif_addfd`` should be the same ``id`` as in |
| 265 | 265 | ``struct seccomp_notif``. The ``newfd_flags`` flag may be used to set flags |
| 266 | −like O_EXEC on the file descriptor in the notifying process. If the supervisor | |
| 266 | +like O_CLOEXEC on the file descriptor in the notifying process. If the supervisor | |
| 267 | 267 | wants to inject the file descriptor with a specific number, the |
| 268 | 268 | ``SECCOMP_ADDFD_FLAG_SETFD`` flag can be used, and set the ``newfd`` member to |
| 269 | 269 | the specific number to use. If that file descriptor is already open in the |
| @@ -855,7 +855,7 @@ in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to · 854 unmodified lines | ||
| 855 | 855 | use PPIs designated for specific cpus. The irq field is interpreted |
| 856 | 856 | like this:: |
| 857 | 857 | |
| 858 | − bits: | 31 ... 28 | 27 ... 24 | 23 ... 16 | 15 ... 0 | | |
| 858 | + bits: | 31 ... 28 | 27 ... 24 | 23 ... 16 | 15 ... 0 | | |
| 859 | 859 | field: | vcpu2_index | irq_type | vcpu_index | irq_id | |
| 860 | 860 | |
| 861 | 861 | The irq_type field has the following values: |
| @@ -2149,10 +2149,10 @@ prior to calling the KVM_RUN ioctl. · 1287 unmodified lines | ||
| 2149 | 2149 | Errors: |
| 2150 | 2150 | |
| 2151 | 2151 | ====== ============================================================ |
| 2152 | − ENOENT no such register | |
| 2153 | − EINVAL invalid register ID, or no such register or used with VMs in | |
| 2152 | + ENOENT no such register | |
| 2153 | + EINVAL invalid register ID, or no such register or used with VMs in | |
| 2154 | 2154 | protected virtualization mode on s390 |
| 2155 | − EPERM (arm64) register access not allowed before vcpu finalization | |
| 2155 | + EPERM (arm64) register access not allowed before vcpu finalization | |
| 2156 | 2156 | ====== ============================================================ |
| 2157 | 2157 | |
| 2158 | 2158 | (These error codes are indicative only: do not rely on a specific error |
| @@ -2590,10 +2590,10 @@ following id bit patterns:: · 431 unmodified lines | ||
| 2590 | 2590 | Errors include: |
| 2591 | 2591 | |
| 2592 | 2592 | ======== ============================================================ |
| 2593 | − ENOENT no such register | |
| 2594 | − EINVAL invalid register ID, or no such register or used with VMs in | |
| 2593 | + ENOENT no such register | |
| 2594 | + EINVAL invalid register ID, or no such register or used with VMs in | |
| 2595 | 2595 | protected virtualization mode on s390 |
| 2596 | − EPERM (arm64) register access not allowed before vcpu finalization | |
| 2596 | + EPERM (arm64) register access not allowed before vcpu finalization | |
| 2597 | 2597 | ======== ============================================================ |
| 2598 | 2598 | |
| 2599 | 2599 | (These error codes are indicative only: do not rely on a specific error |
| @@ -3112,13 +3112,13 @@ current state. "addr" is ignored. · 512 unmodified lines | ||
| 3112 | 3112 | Errors: |
| 3113 | 3113 | |
| 3114 | 3114 | ====== ================================================================= |
| 3115 | − EINVAL the target is unknown, or the combination of features is invalid. | |
| 3116 | − ENOENT a features bit specified is unknown. | |
| 3115 | + EINVAL the target is unknown, or the combination of features is invalid. | |
| 3116 | + ENOENT a features bit specified is unknown. | |
| 3117 | 3117 | ====== ================================================================= |
| 3118 | 3118 | |
| 3119 | 3119 | This tells KVM what type of CPU to present to the guest, and what |
| 3120 | −optional features it should have. This will cause a reset of the cpu | |
| 3121 | −registers to their initial values. If this is not called, KVM_RUN will | |
| 3120 | +optional features it should have. This will cause a reset of the cpu | |
| 3121 | +registers to their initial values. If this is not called, KVM_RUN will | |
| 3122 | 3122 | return ENOEXEC for that vcpu. |
| 3123 | 3123 | |
| 3124 | 3124 | The initial values are defined as: |
| @@ -3239,8 +3239,8 @@ VCPU matching underlying host. · 114 unmodified lines | ||
| 3239 | 3239 | Errors: |
| 3240 | 3240 | |
| 3241 | 3241 | ===== ============================================================== |
| 3242 | − E2BIG the reg index list is too big to fit in the array specified by | |
| 3243 | − the user (the number required will be written into n). | |
| 3242 | + E2BIG the reg index list is too big to fit in the array specified by | |
| 3243 | + the user (the number required will be written into n). | |
| 3244 | 3244 | ===== ============================================================== |
| 3245 | 3245 | |
| 3246 | 3246 | :: |
| @@ -3288,7 +3288,7 @@ specific device. · 41 unmodified lines | ||
| 3288 | 3288 | ARM/arm64 divides the id field into two parts, a device id and an |
| 3289 | 3289 | address type id specific to the individual device:: |
| 3290 | 3290 | |
| 3291 | − bits: | 63 ... 32 | 31 ... 16 | 15 ... 0 | | |
| 3291 | + bits: | 63 ... 32 | 31 ... 16 | 15 ... 0 | | |
| 3292 | 3292 | field: | 0x00000000 | device id | addr type id | |
| 3293 | 3293 | |
| 3294 | 3294 | ARM/arm64 currently only require this when using the in-kernel GIC |
| @@ -7049,7 +7049,7 @@ In combination with KVM_CAP_X86_USER_SPACE_MSR, this allows user space to · 3754 unmodified lines | ||
| 7049 | 7049 | trap and emulate MSRs that are outside of the scope of KVM as well as |
| 7050 | 7050 | limit the attack surface on KVM's MSR emulation code. |
| 7051 | 7051 | |
| 7052 | −8.28 KVM_CAP_ENFORCE_PV_CPUID | |
| 7052 | +8.28 KVM_CAP_ENFORCE_PV_FEATURE_CPUID | |
| 7053 | 7053 | ----------------------------- |
| 7054 | 7054 | |
| 7055 | 7055 | Architectures: x86 |
| @@ -25,10 +25,10 @@ On x86: · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | - vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock |
| 27 | 27 | |
| 28 | −- kvm->arch.mmu_lock is an rwlock. kvm->arch.tdp_mmu_pages_lock is | |
| 29 | − taken inside kvm->arch.mmu_lock, and cannot be taken without already | |
| 30 | − holding kvm->arch.mmu_lock (typically with ``read_lock``, otherwise | |
| 31 | − there's no need to take kvm->arch.tdp_mmu_pages_lock at all). | |
| 28 | +- kvm->arch.mmu_lock is an rwlock. kvm->arch.tdp_mmu_pages_lock and | |
| 29 | + kvm->arch.mmu_unsync_pages_lock are taken inside kvm->arch.mmu_lock, and | |
| 30 | + cannot be taken without already holding kvm->arch.mmu_lock (typically with | |
| 31 | + ``read_lock`` for the TDP MMU, thus the need for additional spinlocks). | |
| 32 | 32 | |
| 33 | 33 | Everything else is a leaf: no other lock is taken inside the critical |
| 34 | 34 | sections. |
| @@ -392,7 +392,7 @@ Section 8 -- Interpretation. · 391 unmodified lines | ||
| 392 | 392 | Creative Commons is not a party to its public |
| 393 | 393 | licenses. Notwithstanding, Creative Commons may elect to apply one of |
| 394 | 394 | its public licenses to material it publishes and in those instances |
| 395 | −will be considered the “Licensor.” The text of the Creative Commons | |
| 395 | +will be considered the "Licensor." The text of the Creative Commons | |
| 396 | 396 | public licenses is dedicated to the public domain under the CC0 Public |
| 397 | 397 | Domain Dedication. Except for the limited purpose of indicating that |
| 398 | 398 | material is shared under a Creative Commons public license or as |
| @@ -445,7 +445,7 @@ F: drivers/platform/x86/wmi.c · 444 unmodified lines | ||
| 445 | 445 | F: include/uapi/linux/wmi.h |
| 446 | 446 | |
| 447 | 447 | ACRN HYPERVISOR SERVICE MODULE |
| 448 | −M: Shuo Liu <shuo.a.liu@intel.com> | |
| 448 | +M: Fei Li <fei1.li@intel.com> | |
| 449 | 449 | L: acrn-dev@lists.projectacrn.org (subscribers-only) |
| 450 | 450 | S: Supported |
| 451 | 451 | W: https://projectacrn.org |
| @@ -933,6 +933,7 @@ F: drivers/video/fbdev/geode/ · 481 unmodified lines | ||
| 933 | 933 | |
| 934 | 934 | AMD IOMMU (AMD-VI) |
| 935 | 935 | M: Joerg Roedel <joro@8bytes.org> |
| 936 | +R: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | |
| 936 | 937 | L: iommu@lists.linux-foundation.org |
| 937 | 938 | S: Maintained |
| 938 | 939 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git |
| @@ -3865,6 +3866,16 @@ L: bcm-kernel-feedback-list@broadcom.com · 2926 unmodified lines | ||
| 3865 | 3866 | S: Maintained |
| 3866 | 3867 | F: drivers/mtd/nand/raw/brcmnand/ |
| 3867 | 3868 | |
| 3869 | +BROADCOM STB PCIE DRIVER | |
| 3870 | +M: Jim Quinlan <jim2101024@gmail.com> | |
| 3871 | +M: Nicolas Saenz Julienne <nsaenz@kernel.org> | |
| 3872 | +M: Florian Fainelli <f.fainelli@gmail.com> | |
| 3873 | +M: bcm-kernel-feedback-list@broadcom.com | |
| 3874 | +L: linux-pci@vger.kernel.org | |
| 3875 | +S: Maintained | |
| 3876 | +F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | |
| 3877 | +F: drivers/pci/controller/pcie-brcmstb.c | |
| 3878 | + | |
| 3868 | 3879 | BROADCOM SYSTEMPORT ETHERNET DRIVER |
| 3869 | 3880 | M: Florian Fainelli <f.fainelli@gmail.com> |
| 3870 | 3881 | L: bcm-kernel-feedback-list@broadcom.com |
| @@ -4497,7 +4508,7 @@ L: clang-built-linux@googlegroups.com · 626 unmodified lines | ||
| 4497 | 4508 | S: Supported |
| 4498 | 4509 | W: https://clangbuiltlinux.github.io/ |
| 4499 | 4510 | B: https://github.com/ClangBuiltLinux/linux/issues |
| 4500 | −C: irc://chat.freenode.net/clangbuiltlinux | |
| 4511 | +C: irc://irc.libera.chat/clangbuiltlinux | |
| 4501 | 4512 | F: Documentation/kbuild/llvm.rst |
| 4502 | 4513 | F: include/linux/compiler-clang.h |
| 4503 | 4514 | F: scripts/clang-tools/ |
| @@ -7857,9 +7868,9 @@ S: Maintained · 3353 unmodified lines | ||
| 7857 | 7868 | F: drivers/input/touchscreen/goodix.c |
| 7858 | 7869 | |
| 7859 | 7870 | GOOGLE ETHERNET DRIVERS |
| 7860 | −M: Catherine Sullivan <csully@google.com> | |
| 7861 | −R: Sagi Shahar <sagis@google.com> | |
| 7862 | −R: Jon Olson <jonolson@google.com> | |
| 7871 | +M: Jeroen de Borst <jeroendb@google.com> | |
| 7872 | +R: Catherine Sullivan <csully@google.com> | |
| 7873 | +R: David Awogbemila <awogbemila@google.com> | |
| 7863 | 7874 | L: netdev@vger.kernel.org |
| 7864 | 7875 | S: Supported |
| 7865 | 7876 | F: Documentation/networking/device_drivers/ethernet/google/gve.rst |
| @@ -11326,6 +11337,12 @@ W: https://linuxtv.org · 3460 unmodified lines | ||
| 11326 | 11337 | T: git git://linuxtv.org/media_tree.git |
| 11327 | 11338 | F: drivers/media/radio/radio-maxiradio* |
| 11328 | 11339 | |
| 11340 | +MCBA MICROCHIP CAN BUS ANALYZER TOOL DRIVER | |
| 11341 | +R: Yasushi SHOJI <yashi@spacecubics.com> | |
| 11342 | +L: linux-can@vger.kernel.org | |
| 11343 | +S: Maintained | |
| 11344 | +F: drivers/net/can/usb/mcba_usb.c | |
| 11345 | + | |
| 11329 | 11346 | MCAN MMIO DEVICE DRIVER |
| 11330 | 11347 | M: Chandrasekar Ramakrishnan <rcsekar@samsung.com> |
| 11331 | 11348 | L: linux-can@vger.kernel.org |
| @@ -11757,6 +11774,7 @@ F: drivers/char/hw_random/mtk-rng.c · 425 unmodified lines | ||
| 11757 | 11774 | MEDIATEK SWITCH DRIVER |
| 11758 | 11775 | M: Sean Wang <sean.wang@mediatek.com> |
| 11759 | 11776 | M: Landen Chao <Landen.Chao@mediatek.com> |
| 11777 | +M: DENG Qingfang <dqfext@gmail.com> | |
| 11760 | 11778 | L: netdev@vger.kernel.org |
| 11761 | 11779 | S: Maintained |
| 11762 | 11780 | F: drivers/net/dsa/mt7530.* |
| @@ -14422,6 +14440,13 @@ S: Maintained · 2659 unmodified lines | ||
| 14422 | 14440 | F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt |
| 14423 | 14441 | F: drivers/pci/controller/dwc/pcie-histb.c |
| 14424 | 14442 | |
| 14443 | +PCIE DRIVER FOR INTEL LGM GW SOC | |
| 14444 | +M: Rahul Tanwar <rtanwar@maxlinear.com> | |
| 14445 | +L: linux-pci@vger.kernel.org | |
| 14446 | +S: Maintained | |
| 14447 | +F: Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | |
| 14448 | +F: drivers/pci/controller/dwc/pcie-intel-gw.c | |
| 14449 | + | |
| 14425 | 14450 | PCIE DRIVER FOR MEDIATEK |
| 14426 | 14451 | M: Ryder Lee <ryder.lee@mediatek.com> |
| 14427 | 14452 | M: Jianjun Wang <jianjun.wang@mediatek.com> |
| @@ -15009,6 +15034,13 @@ F: drivers/net/phy/dp83640* · 581 unmodified lines | ||
| 15009 | 15034 | F: drivers/ptp/* |
| 15010 | 15035 | F: include/linux/ptp_cl* |
| 15011 | 15036 | |
| 15037 | +PTP VIRTUAL CLOCK SUPPORT | |
| 15038 | +M: Yangbo Lu <yangbo.lu@nxp.com> | |
| 15039 | +L: netdev@vger.kernel.org | |
| 15040 | +S: Maintained | |
| 15041 | +F: drivers/ptp/ptp_vclock.c | |
| 15042 | +F: net/ethtool/phc_vclocks.c | |
| 15043 | + | |
| 15012 | 15044 | PTRACE SUPPORT |
| 15013 | 15045 | M: Oleg Nesterov <oleg@redhat.com> |
| 15014 | 15046 | S: Maintained |
| @@ -15459,6 +15491,8 @@ M: Pan, Xinhui <Xinhui.Pan@amd.com> · 444 unmodified lines | ||
| 15459 | 15491 | L: amd-gfx@lists.freedesktop.org |
| 15460 | 15492 | S: Supported |
| 15461 | 15493 | T: git https://gitlab.freedesktop.org/agd5f/linux.git |
| 15494 | +B: https://gitlab.freedesktop.org/drm/amd/-/issues | |
| 15495 | +C: irc://irc.oftc.net/radeon | |
| 15462 | 15496 | F: drivers/gpu/drm/amd/ |
| 15463 | 15497 | F: drivers/gpu/drm/radeon/ |
| 15464 | 15498 | F: include/uapi/drm/amdgpu_drm.h |
| @@ -15786,7 +15820,7 @@ F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml · 321 unmodified lines | ||
| 15786 | 15820 | F: drivers/i2c/busses/i2c-emev2.c |
| 15787 | 15821 | |
| 15788 | 15822 | RENESAS ETHERNET DRIVERS |
| 15789 | −R: Sergei Shtylyov <sergei.shtylyov@gmail.com> | |
| 15823 | +R: Sergey Shtylyov <s.shtylyov@omp.ru> | |
| 15790 | 15824 | L: netdev@vger.kernel.org |
| 15791 | 15825 | L: linux-renesas-soc@vger.kernel.org |
| 15792 | 15826 | F: Documentation/devicetree/bindings/net/renesas,*.yaml |
| @@ -17798,7 +17832,7 @@ F: include/linux/sync_file.h · 2005 unmodified lines | ||
| 17798 | 17832 | F: include/uapi/linux/sync_file.h |
| 17799 | 17833 | |
| 17800 | 17834 | SYNOPSYS ARC ARCHITECTURE |
| 17801 | −M: Vineet Gupta <vgupta@synopsys.com> | |
| 17835 | +M: Vineet Gupta <vgupta@kernel.org> | |
| 17802 | 17836 | L: linux-snps-arc@lists.infradead.org |
| 17803 | 17837 | S: Supported |
| 17804 | 17838 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git |
| @@ -19114,7 +19148,7 @@ M: Mauro Carvalho Chehab <mchehab@kernel.org> · 1309 unmodified lines | ||
| 19114 | 19148 | L: linux-usb@vger.kernel.org |
| 19115 | 19149 | S: Maintained |
| 19116 | 19150 | F: Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml |
| 19117 | −F: drivers/phy/hisilicon/phy-kirin970-usb3.c | |
| 19151 | +F: drivers/phy/hisilicon/phy-hi3670-usb3.c | |
| 19118 | 19152 | |
| 19119 | 19153 | USB ISP116X DRIVER |
| 19120 | 19154 | M: Olav Kongas <ok@artecdesign.ee> |
| @@ -19792,6 +19826,14 @@ L: netdev@vger.kernel.org · 671 unmodified lines | ||
| 19792 | 19826 | S: Supported |
| 19793 | 19827 | F: drivers/ptp/ptp_vmw.c |
| 19794 | 19828 | |
| 19829 | +VMWARE VMCI DRIVER | |
| 19830 | +M: Jorgen Hansen <jhansen@vmware.com> | |
| 19831 | +M: Vishnu Dasa <vdasa@vmware.com> | |
| 19832 | +L: linux-kernel@vger.kernel.org | |
| 19833 | +L: pv-drivers@vmware.com (private) | |
| 19834 | +S: Maintained | |
| 19835 | +F: drivers/misc/vmw_vmci/ | |
| 19836 | + | |
| 19795 | 19837 | VMWARE VMMOUSE SUBDRIVER |
| 19796 | 19838 | M: "VMware Graphics" <linux-graphics-maintainer@vmware.com> |
| 19797 | 19839 | M: "VMware, Inc." <pv-drivers@vmware.com> |
| @@ -2,7 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | VERSION = 5 |
| 3 | 3 | PATCHLEVEL = 14 |
| 4 | 4 | SUBLEVEL = 0 |
| 5 | −EXTRAVERSION = -rc1 | |
| 5 | +EXTRAVERSION = -rc7 | |
| 6 | 6 | NAME = Opossums on Parade |
| 7 | 7 | |
| 8 | 8 | # *DOCUMENTATION* |
| @@ -546,7 +546,6 @@ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \ · 537 unmodified lines | ||
| 546 | 546 | PHONY += scripts_basic |
| 547 | 547 | scripts_basic: |
| 548 | 548 | $(Q)$(MAKE) $(build)=scripts/basic |
| 549 | − $(Q)rm -f .tmp_quiet_recordmcount | |
| 550 | 549 | |
| 551 | 550 | PHONY += outputmakefile |
| 552 | 551 | ifdef building_out_of_srctree |
| @@ -728,11 +727,12 @@ $(KCONFIG_CONFIG): · 175 unmodified lines | ||
| 728 | 727 | # This exploits the 'multi-target pattern rule' trick. |
| 729 | 728 | # The syncconfig should be executed only once to make all the targets. |
| 730 | 729 | # (Note: use the grouped target '&:' when we bump to GNU Make 4.3) |
| 731 | −quiet_cmd_syncconfig = SYNC $@ | |
| 732 | − cmd_syncconfig = $(MAKE) -f $(srctree)/Makefile syncconfig | |
| 733 | − | |
| 730 | +# | |
| 731 | +# Do not use $(call cmd,...) here. That would suppress prompts from syncconfig, | |
| 732 | +# so you cannot notice that Kconfig is waiting for the user input. | |
| 734 | 733 | %/config/auto.conf %/config/auto.conf.cmd %/generated/autoconf.h: $(KCONFIG_CONFIG) |
| 735 | − +$(call cmd,syncconfig) | |
| 734 | + $(Q)$(kecho) " SYNC $@" | |
| 735 | + $(Q)$(MAKE) -f $(srctree)/Makefile syncconfig | |
| 736 | 736 | else # !may-sync-config |
| 737 | 737 | # External modules and some install targets need include/generated/autoconf.h |
| 738 | 738 | # and include/config/auto.conf but do not care if they are up-to-date. |
| @@ -802,7 +802,7 @@ else · 63 unmodified lines | ||
| 802 | 802 | # Warn about unmarked fall-throughs in switch statement. |
| 803 | 803 | # Disabled for clang while comment to attribute conversion happens and |
| 804 | 804 | # https://github.com/ClangBuiltLinux/linux/issues/636 is discussed. |
| 805 | −KBUILD_CFLAGS += $(call cc-option,-Wimplicit-fallthrough,) | |
| 805 | +KBUILD_CFLAGS += $(call cc-option,-Wimplicit-fallthrough=5,) | |
| 806 | 806 | endif |
| 807 | 807 | |
| 808 | 808 | # These warnings generated too much noise in a regular build. |
| @@ -1316,6 +1316,16 @@ PHONY += scripts_unifdef · 507 unmodified lines | ||
| 1316 | 1316 | scripts_unifdef: scripts_basic |
| 1317 | 1317 | $(Q)$(MAKE) $(build)=scripts scripts/unifdef |
| 1318 | 1318 | |
| 1319 | +# --------------------------------------------------------------------------- | |
| 1320 | +# Install | |
| 1321 | + | |
| 1322 | +# Many distributions have the custom install script, /sbin/installkernel. | |
| 1323 | +# If DKMS is installed, 'make install' will eventually recuses back | |
| 1324 | +# to the this Makefile to build and install external modules. | |
| 1325 | +# Cancel sub_make_done so that options such as M=, V=, etc. are parsed. | |
| 1326 | + | |
| 1327 | +install: sub_make_done := | |
| 1328 | + | |
| 1319 | 1329 | # --------------------------------------------------------------------------- |
| 1320 | 1330 | # Tools |
| 1321 | 1331 | |
| @@ -14,7 +14,6 @@ config ALPHA · 13 unmodified lines | ||
| 14 | 14 | select PCI_SYSCALL if PCI |
| 15 | 15 | select HAVE_AOUT |
| 16 | 16 | select HAVE_ASM_MODVERSIONS |
| 17 | − select HAVE_IDE | |
| 18 | 17 | select HAVE_PCSPKR_PLATFORM |
| 19 | 18 | select HAVE_PERF_EVENTS |
| 20 | 19 | select NEED_DMA_MAP_STATE |
| @@ -532,7 +531,7 @@ config SMP · 511 unmodified lines | ||
| 532 | 531 | will run faster if you say N here. |
| 533 | 532 | |
| 534 | 533 | See also the SMP-HOWTO available at |
| 535 | − <http://www.tldp.org/docs.html#howto>. | |
| 534 | + <https://www.tldp.org/docs.html#howto>. | |
| 536 | 535 | |
| 537 | 536 | If you don't know what to do here, say N. |
| 538 | 537 | |
| @@ -23,7 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | #include "ksize.h" |
| 24 | 24 | |
| 25 | 25 | extern unsigned long switch_to_osf_pal(unsigned long nr, |
| 26 | − struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa, | |
| 26 | + struct pcb_struct *pcb_va, struct pcb_struct *pcb_pa, | |
| 27 | 27 | unsigned long *vptb); |
| 28 | 28 | |
| 29 | 29 | extern void move_stack(unsigned long new_stack); |
| @@ -200,7 +200,7 @@ extern char _end; · 199 unmodified lines | ||
| 200 | 200 | START_ADDR KSEG address of the entry point of kernel code. |
| 201 | 201 | |
| 202 | 202 | ZERO_PGE KSEG address of page full of zeroes, but |
| 203 | − upon entry to kerne cvan be expected | |
| 203 | + upon entry to kernel, it can be expected | |
| 204 | 204 | to hold the parameter list and possible |
| 205 | 205 | INTRD information. |
| 206 | 206 | |
| @@ -30,7 +30,7 @@ extern long srm_printk(const char *, ...) · 29 unmodified lines | ||
| 30 | 30 | __attribute__ ((format (printf, 1, 2))); |
| 31 | 31 | |
| 32 | 32 | /* |
| 33 | − * gzip delarations | |
| 33 | + * gzip declarations | |
| 34 | 34 | */ |
| 35 | 35 | #define OF(args) args |
| 36 | 36 | #define STATIC static |
| @@ -70,3 +70,4 @@ CONFIG_DEBUG_INFO=y · 69 unmodified lines | ||
| 70 | 70 | CONFIG_ALPHA_LEGACY_START_ADDRESS=y |
| 71 | 71 | CONFIG_MATHEMU=y |
| 72 | 72 | CONFIG_CRYPTO_HMAC=y |
| 73 | +CONFIG_DEVTMPFS=y | |
| @@ -4,15 +4,4 @@ · 3 unmodified lines | ||
| 4 | 4 | |
| 5 | 5 | #include <uapi/asm/compiler.h> |
| 6 | 6 | |
| 7 | −/* Some idiots over in <linux/compiler.h> thought inline should imply | |
| 8 | − always_inline. This breaks stuff. We'll include this file whenever | |
| 9 | − we run into such problems. */ | |
| 10 | − | |
| 11 | −#include <linux/compiler.h> | |
| 12 | −#undef inline | |
| 13 | −#undef __inline__ | |
| 14 | −#undef __inline | |
| 15 | −#undef __always_inline | |
| 16 | −#define __always_inline inline __attribute__((always_inline)) | |
| 17 | − | |
| 18 | 7 | #endif /* __ALPHA_COMPILER_H */ |
| @@ -9,4 +9,10 @@ static inline int syscall_get_arch(struct task_struct *task) · 8 unmodified lines | ||
| 9 | 9 | return AUDIT_ARCH_ALPHA; |
| 10 | 10 | } |
| 11 | 11 | |
| 12 | +static inline long syscall_get_return_value(struct task_struct *task, | |
| 13 | + struct pt_regs *regs) | |
| 14 | +{ | |
| 15 | + return regs->r0; | |
| 16 | +} | |
| 17 | + | |
| 12 | 18 | #endif /* _ASM_ALPHA_SYSCALL_H */ |
| @@ -834,7 +834,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer, · 833 unmodified lines | ||
| 834 | 834 | return -EFAULT; |
| 835 | 835 | state = ¤t_thread_info()->ieee_state; |
| 836 | 836 | |
| 837 | − /* Update softare trap enable bits. */ | |
| 837 | + /* Update software trap enable bits. */ | |
| 838 | 838 | *state = (*state & ~IEEE_SW_MASK) | (swcr & IEEE_SW_MASK); |
| 839 | 839 | |
| 840 | 840 | /* Update the real fpcr. */ |
| @@ -854,7 +854,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer, · 13 unmodified lines | ||
| 854 | 854 | state = ¤t_thread_info()->ieee_state; |
| 855 | 855 | exc &= IEEE_STATUS_MASK; |
| 856 | 856 | |
| 857 | − /* Update softare trap enable bits. */ | |
| 857 | + /* Update software trap enable bits. */ | |
| 858 | 858 | swcr = (*state & IEEE_SW_MASK) | exc; |
| 859 | 859 | *state |= exc; |
| 860 | 860 | |
| @@ -574,7 +574,7 @@ static void alpha_pmu_start(struct perf_event *event, int flags) · 573 unmodified lines | ||
| 574 | 574 | * Check that CPU performance counters are supported. |
| 575 | 575 | * - currently support EV67 and later CPUs. |
| 576 | 576 | * - actually some later revisions of the EV6 have the same PMC model as the |
| 577 | − * EV67 but we don't do suffiently deep CPU detection to detect them. | |
| 577 | + * EV67 but we don't do sufficiently deep CPU detection to detect them. | |
| 578 | 578 | * Bad luck to the very few people who might have one, I guess. |
| 579 | 579 | */ |
| 580 | 580 | static int supported_cpu(void) |
| @@ -256,7 +256,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 255 unmodified lines | ||
| 256 | 256 | childstack->r26 = (unsigned long) ret_from_kernel_thread; |
| 257 | 257 | childstack->r9 = usp; /* function */ |
| 258 | 258 | childstack->r10 = kthread_arg; |
| 259 | − childregs->hae = alpha_mv.hae_cache, | |
| 259 | + childregs->hae = alpha_mv.hae_cache; | |
| 260 | 260 | childti->pcb.usp = 0; |
| 261 | 261 | return 0; |
| 262 | 262 | } |
| @@ -319,18 +319,19 @@ setup_memory(void *kernel_end) · 318 unmodified lines | ||
| 319 | 319 | i, cluster->usage, cluster->start_pfn, |
| 320 | 320 | cluster->start_pfn + cluster->numpages); |
| 321 | 321 | |
| 322 | − /* Bit 0 is console/PALcode reserved. Bit 1 is | |
| 323 | − non-volatile memory -- we might want to mark | |
| 324 | − this for later. */ | |
| 325 | − if (cluster->usage & 3) | |
| 326 | − continue; | |
| 327 | − | |
| 328 | 322 | end = cluster->start_pfn + cluster->numpages; |
| 329 | 323 | if (end > max_low_pfn) |
| 330 | 324 | max_low_pfn = end; |
| 331 | 325 | |
| 332 | 326 | memblock_add(PFN_PHYS(cluster->start_pfn), |
| 333 | 327 | cluster->numpages << PAGE_SHIFT); |
| 328 | + | |
| 329 | + /* Bit 0 is console/PALcode reserved. Bit 1 is | |
| 330 | + non-volatile memory -- we might want to mark | |
| 331 | + this for later. */ | |
| 332 | + if (cluster->usage & 3) | |
| 333 | + memblock_reserve(PFN_PHYS(cluster->start_pfn), | |
| 334 | + cluster->numpages << PAGE_SHIFT); | |
| 334 | 335 | } |
| 335 | 336 | |
| 336 | 337 | /* |
| @@ -582,7 +582,7 @@ void · 581 unmodified lines | ||
| 582 | 582 | smp_send_stop(void) |
| 583 | 583 | { |
| 584 | 584 | cpumask_t to_whom; |
| 585 | − cpumask_copy(&to_whom, cpu_possible_mask); | |
| 585 | + cpumask_copy(&to_whom, cpu_online_mask); | |
| 586 | 586 | cpumask_clear_cpu(smp_processor_id(), &to_whom); |
| 587 | 587 | #ifdef DEBUG_IPI_MSG |
| 588 | 588 | if (hard_smp_processor_id() != boot_cpu_id) |
| @@ -212,7 +212,7 @@ nautilus_init_pci(void) · 211 unmodified lines | ||
| 212 | 212 | |
| 213 | 213 | /* Use default IO. */ |
| 214 | 214 | pci_add_resource(&bridge->windows, &ioport_resource); |
| 215 | − /* Irongate PCI memory aperture, calculate requred size before | |
| 215 | + /* Irongate PCI memory aperture, calculate required size before | |
| 216 | 216 | setting it up. */ |
| 217 | 217 | pci_add_resource(&bridge->windows, &irongate_mem); |
| 218 | 218 | |
| @@ -730,7 +730,7 @@ do_entUnaUser(void __user * va, unsigned long opcode, · 729 unmodified lines | ||
| 730 | 730 | long error; |
| 731 | 731 | |
| 732 | 732 | /* Check the UAC bits to decide what the user wants us to do |
| 733 | − with the unaliged access. */ | |
| 733 | + with the unaligned access. */ | |
| 734 | 734 | |
| 735 | 735 | if (!(current_thread_info()->status & TS_UAC_NOPRINT)) { |
| 736 | 736 | if (__ratelimit(&ratelimit)) { |
| @@ -65,7 +65,7 @@ static long (*save_emul) (unsigned long pc); · 64 unmodified lines | ||
| 65 | 65 | long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long); |
| 66 | 66 | long do_alpha_fp_emul(unsigned long); |
| 67 | 67 | |
| 68 | −int init_module(void) | |
| 68 | +static int alpha_fp_emul_init_module(void) | |
| 69 | 69 | { |
| 70 | 70 | save_emul_imprecise = alpha_fp_emul_imprecise; |
| 71 | 71 | save_emul = alpha_fp_emul; |
| @@ -73,12 +73,14 @@ int init_module(void) · 1 unmodified line | ||
| 73 | 73 | alpha_fp_emul = do_alpha_fp_emul; |
| 74 | 74 | return 0; |
| 75 | 75 | } |
| 76 | +module_init(alpha_fp_emul_init_module); | |
| 76 | 77 | |
| 77 | −void cleanup_module(void) | |
| 78 | +static void alpha_fp_emul_cleanup_module(void) | |
| 78 | 79 | { |
| 79 | 80 | alpha_fp_emul_imprecise = save_emul_imprecise; |
| 80 | 81 | alpha_fp_emul = save_emul; |
| 81 | 82 | } |
| 83 | +module_exit(alpha_fp_emul_cleanup_module); | |
| 82 | 84 | |
| 83 | 85 | #undef alpha_fp_emul_imprecise |
| 84 | 86 | #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise |
| @@ -401,3 +403,5 @@ alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask) · 316 unmodified lines | ||
| 401 | 403 | egress: |
| 402 | 404 | return si_code; |
| 403 | 405 | } |
| 406 | + | |
| 407 | +EXPORT_SYMBOL(__udiv_qrnnd); | |
| @@ -409,7 +409,7 @@ choice · 408 unmodified lines | ||
| 409 | 409 | help |
| 410 | 410 | Depending on the configuration, CPU can contain DSP registers |
| 411 | 411 | (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). |
| 412 | − Bellow is options describing how to handle these registers in | |
| 412 | + Below are options describing how to handle these registers in | |
| 413 | 413 | interrupt entry / exit and in context switch. |
| 414 | 414 | |
| 415 | 415 | config ARC_DSP_NONE |
| @@ -24,7 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | */ |
| 25 | 25 | static inline __sum16 csum_fold(__wsum s) |
| 26 | 26 | { |
| 27 | − unsigned r = s << 16 | s >> 16; /* ror */ | |
| 27 | + unsigned int r = s << 16 | s >> 16; /* ror */ | |
| 28 | 28 | s = ~s; |
| 29 | 29 | s -= r; |
| 30 | 30 | return s >> 16; |
| @@ -123,7 +123,7 @@ static const char * const arc_pmu_ev_hw_map[] = { · 122 unmodified lines | ||
| 123 | 123 | #define C(_x) PERF_COUNT_HW_CACHE_##_x |
| 124 | 124 | #define CACHE_OP_UNSUPPORTED 0xffff |
| 125 | 125 | |
| 126 | −static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | |
| 126 | +static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | |
| 127 | 127 | [C(L1D)] = { |
| 128 | 128 | [C(OP_READ)] = { |
| 129 | 129 | [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, |
| @@ -57,23 +57,26 @@ void fpu_save_restore(struct task_struct *prev, struct task_struct *next) · 56 unmodified lines | ||
| 57 | 57 | |
| 58 | 58 | void fpu_init_task(struct pt_regs *regs) |
| 59 | 59 | { |
| 60 | + const unsigned int fwe = 0x80000000; | |
| 61 | + | |
| 60 | 62 | /* default rounding mode */ |
| 61 | 63 | write_aux_reg(ARC_REG_FPU_CTRL, 0x100); |
| 62 | 64 | |
| 63 | − /* set "Write enable" to allow explicit write to exception flags */ | |
| 64 | − write_aux_reg(ARC_REG_FPU_STATUS, 0x80000000); | |
| 65 | + /* Initialize to zero: setting requires FWE be set */ | |
| 66 | + write_aux_reg(ARC_REG_FPU_STATUS, fwe); | |
| 65 | 67 | } |
| 66 | 68 | |
| 67 | 69 | void fpu_save_restore(struct task_struct *prev, struct task_struct *next) |
| 68 | 70 | { |
| 69 | 71 | struct arc_fpu *save = &prev->thread.fpu; |
| 70 | 72 | struct arc_fpu *restore = &next->thread.fpu; |
| 73 | + const unsigned int fwe = 0x80000000; | |
| 71 | 74 | |
| 72 | 75 | save->ctrl = read_aux_reg(ARC_REG_FPU_CTRL); |
| 73 | 76 | save->status = read_aux_reg(ARC_REG_FPU_STATUS); |
| 74 | 77 | |
| 75 | 78 | write_aux_reg(ARC_REG_FPU_CTRL, restore->ctrl); |
| 76 | − write_aux_reg(ARC_REG_FPU_STATUS, restore->status); | |
| 79 | + write_aux_reg(ARC_REG_FPU_STATUS, (fwe | restore->status)); | |
| 77 | 80 | } |
| 78 | 81 | |
| 79 | 82 | #endif |
| @@ -260,7 +260,7 @@ static void init_unwind_hdr(struct unwind_table *table, · 259 unmodified lines | ||
| 260 | 260 | { |
| 261 | 261 | const u8 *ptr; |
| 262 | 262 | unsigned long tableSize = table->size, hdrSize; |
| 263 | − unsigned n; | |
| 263 | + unsigned int n; | |
| 264 | 264 | const u32 *fde; |
| 265 | 265 | struct { |
| 266 | 266 | u8 version; |
| @@ -462,7 +462,7 @@ static uleb128_t get_uleb128(const u8 **pcur, const u8 *end) · 195 unmodified lines | ||
| 462 | 462 | { |
| 463 | 463 | const u8 *cur = *pcur; |
| 464 | 464 | uleb128_t value; |
| 465 | − unsigned shift; | |
| 465 | + unsigned int shift; | |
| 466 | 466 | |
| 467 | 467 | for (shift = 0, value = 0; cur < end; shift += 7) { |
| 468 | 468 | if (shift + 7 > 8 * sizeof(value) |
| @@ -483,7 +483,7 @@ static sleb128_t get_sleb128(const u8 **pcur, const u8 *end) · 14 unmodified lines | ||
| 483 | 483 | { |
| 484 | 484 | const u8 *cur = *pcur; |
| 485 | 485 | sleb128_t value; |
| 486 | − unsigned shift; | |
| 486 | + unsigned int shift; | |
| 487 | 487 | |
| 488 | 488 | for (shift = 0, value = 0; cur < end; shift += 7) { |
| 489 | 489 | if (shift + 7 > 8 * sizeof(value) |
| @@ -609,7 +609,7 @@ static unsigned long read_pointer(const u8 **pLoc, const void *end, · 119 unmodified lines | ||
| 609 | 609 | static signed fde_pointer_type(const u32 *cie) |
| 610 | 610 | { |
| 611 | 611 | const u8 *ptr = (const u8 *)(cie + 2); |
| 612 | − unsigned version = *ptr; | |
| 612 | + unsigned int version = *ptr; | |
| 613 | 613 | |
| 614 | 614 | if (*++ptr) { |
| 615 | 615 | const char *aug; |
| @@ -904,7 +904,7 @@ int arc_unwind(struct unwind_frame_info *frame) · 288 unmodified lines | ||
| 904 | 904 | const u8 *ptr = NULL, *end = NULL; |
| 905 | 905 | unsigned long pc = UNW_PC(frame) - frame->call_frame; |
| 906 | 906 | unsigned long startLoc = 0, endLoc = 0, cfa; |
| 907 | − unsigned i; | |
| 907 | + unsigned int i; | |
| 908 | 908 | signed ptrType = -1; |
| 909 | 909 | uleb128_t retAddrReg = 0; |
| 910 | 910 | const struct unwind_table *table; |
| @@ -88,6 +88,8 @@ SECTIONS · 87 unmodified lines | ||
| 88 | 88 | CPUIDLE_TEXT |
| 89 | 89 | LOCK_TEXT |
| 90 | 90 | KPROBES_TEXT |
| 91 | + IRQENTRY_TEXT | |
| 92 | + SOFTIRQENTRY_TEXT | |
| 91 | 93 | *(.fixup) |
| 92 | 94 | *(.gnu.warning) |
| 93 | 95 | } |
| @@ -95,7 +95,6 @@ config ARM · 94 unmodified lines | ||
| 95 | 95 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
| 96 | 96 | select HAVE_GCC_PLUGINS |
| 97 | 97 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
| 98 | − select HAVE_IDE if PCI || ISA || PCMCIA | |
| 99 | 98 | select HAVE_IRQ_TIME_ACCOUNTING |
| 100 | 99 | select HAVE_KERNEL_GZIP |
| 101 | 100 | select HAVE_KERNEL_LZ4 |
| @@ -361,7 +360,6 @@ config ARCH_FOOTBRIDGE · 259 unmodified lines | ||
| 361 | 360 | bool "FootBridge" |
| 362 | 361 | select CPU_SA110 |
| 363 | 362 | select FOOTBRIDGE |
| 364 | − select HAVE_IDE | |
| 365 | 363 | select NEED_MACH_IO_H if !MMU |
| 366 | 364 | select NEED_MACH_MEMORY_H |
| 367 | 365 | help |
| @@ -395,7 +393,7 @@ config ARCH_IXP4XX · 27 unmodified lines | ||
| 395 | 393 | select IXP4XX_IRQ |
| 396 | 394 | select IXP4XX_TIMER |
| 397 | 395 | # With the new PCI driver this is not needed |
| 398 | − select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY | |
| 396 | + select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY | |
| 399 | 397 | select USB_EHCI_BIG_ENDIAN_DESC |
| 400 | 398 | select USB_EHCI_BIG_ENDIAN_MMIO |
| 401 | 399 | help |
| @@ -430,7 +428,6 @@ config ARCH_PXA · 28 unmodified lines | ||
| 430 | 428 | select GENERIC_IRQ_MULTI_HANDLER |
| 431 | 429 | select GPIO_PXA |
| 432 | 430 | select GPIOLIB |
| 433 | − select HAVE_IDE | |
| 434 | 431 | select IRQ_DOMAIN |
| 435 | 432 | select PLAT_PXA |
| 436 | 433 | select SPARSE_IRQ |
| @@ -446,7 +443,6 @@ config ARCH_RPC · 9 unmodified lines | ||
| 446 | 443 | select ARM_HAS_SG_CHAIN |
| 447 | 444 | select CPU_SA110 |
| 448 | 445 | select FIQ |
| 449 | − select HAVE_IDE | |
| 450 | 446 | select HAVE_PATA_PLATFORM |
| 451 | 447 | select ISA_DMA_API |
| 452 | 448 | select LEGACY_TIMER_TICK |
| @@ -469,7 +465,6 @@ config ARCH_SA1100 · 16 unmodified lines | ||
| 469 | 465 | select CPU_SA1100 |
| 470 | 466 | select GENERIC_IRQ_MULTI_HANDLER |
| 471 | 467 | select GPIOLIB |
| 472 | − select HAVE_IDE | |
| 473 | 468 | select IRQ_DOMAIN |
| 474 | 469 | select ISA |
| 475 | 470 | select NEED_MACH_MEMORY_H |
| @@ -505,7 +500,6 @@ config ARCH_OMAP1 · 29 unmodified lines | ||
| 505 | 500 | select GENERIC_IRQ_CHIP |
| 506 | 501 | select GENERIC_IRQ_MULTI_HANDLER |
| 507 | 502 | select GPIOLIB |
| 508 | − select HAVE_IDE | |
| 509 | 503 | select HAVE_LEGACY_CLK |
| 510 | 504 | select IRQ_DOMAIN |
| 511 | 505 | select NEED_MACH_IO_H if PCCARD |
| @@ -1595,7 +1595,7 @@ · 1594 unmodified lines | ||
| 1595 | 1595 | compatible = "ti,am4372-d_can", "ti,am3352-d_can"; |
| 1596 | 1596 | reg = <0x0 0x2000>; |
| 1597 | 1597 | clocks = <&dcan1_fck>; |
| 1598 | − clock-name = "fck"; | |
| 1598 | + clock-names = "fck"; | |
| 1599 | 1599 | syscon-raminit = <&scm_conf 0x644 1>; |
| 1600 | 1600 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 1601 | 1601 | status = "disabled"; |
| @@ -582,7 +582,7 @@ · 581 unmodified lines | ||
| 582 | 582 | status = "okay"; |
| 583 | 583 | pinctrl-names = "default"; |
| 584 | 584 | pinctrl-0 = <&i2c0_pins>; |
| 585 | − clock-frequency = <400000>; | |
| 585 | + clock-frequency = <100000>; | |
| 586 | 586 | |
| 587 | 587 | tps65218: tps65218@24 { |
| 588 | 588 | reg = <0x24>; |
| @@ -4,6 +4,7 @@ · 3 unmodified lines | ||
| 4 | 4 | #include "aspeed-g5.dtsi" |
| 5 | 5 | #include <dt-bindings/gpio/aspeed-gpio.h> |
| 6 | 6 | #include <dt-bindings/i2c/i2c.h> |
| 7 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 7 | 8 | |
| 8 | 9 | /{ |
| 9 | 10 | model = "ASRock E3C246D4I BMC"; |
| @@ -73,7 +74,8 @@ · 63 unmodified lines | ||
| 73 | 74 | |
| 74 | 75 | &vuart { |
| 75 | 76 | status = "okay"; |
| 76 | − aspeed,sirq-active-high; | |
| 77 | + aspeed,lpc-io-reg = <0x2f8>; | |
| 78 | + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; | |
| 77 | 79 | }; |
| 78 | 80 | |
| 79 | 81 | &mac0 { |
| @@ -406,14 +406,14 @@ · 405 unmodified lines | ||
| 406 | 406 | reg = <0x69>; |
| 407 | 407 | }; |
| 408 | 408 | |
| 409 | − power-supply@6a { | |
| 409 | + power-supply@6b { | |
| 410 | 410 | compatible = "ibm,cffps"; |
| 411 | − reg = <0x6a>; | |
| 411 | + reg = <0x6b>; | |
| 412 | 412 | }; |
| 413 | 413 | |
| 414 | − power-supply@6b { | |
| 414 | + power-supply@6d { | |
| 415 | 415 | compatible = "ibm,cffps"; |
| 416 | − reg = <0x6b>; | |
| 416 | + reg = <0x6d>; | |
| 417 | 417 | }; |
| 418 | 418 | }; |
| 419 | 419 | |
| @@ -2832,6 +2832,7 @@ · 2412 unmodified lines | ||
| 2832 | 2832 | |
| 2833 | 2833 | &emmc { |
| 2834 | 2834 | status = "okay"; |
| 2835 | + clk-phase-mmc-hs200 = <180>, <180>; | |
| 2835 | 2836 | }; |
| 2836 | 2837 | |
| 2837 | 2838 | &fsim0 { |
| @@ -280,10 +280,7 @@ · 279 unmodified lines | ||
| 280 | 280 | /*W0-W7*/ "","","","","","","","", |
| 281 | 281 | /*X0-X7*/ "","","","","","","","", |
| 282 | 282 | /*Y0-Y7*/ "","","","","","","","", |
| 283 | − /*Z0-Z7*/ "","","","","","","","", | |
| 284 | − /*AA0-AA7*/ "","","","","","","","", | |
| 285 | − /*AB0-AB7*/ "","","","","","","","", | |
| 286 | − /*AC0-AC7*/ "","","","","","","",""; | |
| 283 | + /*Z0-Z7*/ "","","","","","","",""; | |
| 287 | 284 | |
| 288 | 285 | pin_mclr_vpp { |
| 289 | 286 | gpio-hog; |
| @@ -136,10 +136,7 @@ · 135 unmodified lines | ||
| 136 | 136 | /*W0-W7*/ "","","","","","","","", |
| 137 | 137 | /*X0-X7*/ "","","","","","","","", |
| 138 | 138 | /*Y0-Y7*/ "","","","","","","","", |
| 139 | − /*Z0-Z7*/ "","","","","","","","", | |
| 140 | − /*AA0-AA7*/ "","","","","","","","", | |
| 141 | − /*AB0-AB7*/ "","","","","","","","", | |
| 142 | − /*AC0-AC7*/ "","","","","","","",""; | |
| 139 | + /*Z0-Z7*/ "","","","","","","",""; | |
| 143 | 140 | }; |
| 144 | 141 | |
| 145 | 142 | &fmc { |
| @@ -189,6 +186,7 @@ · 43 unmodified lines | ||
| 189 | 186 | |
| 190 | 187 | &emmc { |
| 191 | 188 | status = "okay"; |
| 189 | + clk-phase-mmc-hs200 = <36>, <270>; | |
| 192 | 190 | }; |
| 193 | 191 | |
| 194 | 192 | &fsim0 { |
| @@ -388,13 +388,13 @@ · 387 unmodified lines | ||
| 388 | 388 | |
| 389 | 389 | pinctrl_power_button: powerbutgrp { |
| 390 | 390 | fsl,pins = < |
| 391 | − MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 | |
| 391 | + MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 | |
| 392 | 392 | >; |
| 393 | 393 | }; |
| 394 | 394 | |
| 395 | 395 | pinctrl_power_out: poweroutgrp { |
| 396 | 396 | fsl,pins = < |
| 397 | − MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 | |
| 397 | + MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 | |
| 398 | 398 | >; |
| 399 | 399 | }; |
| 400 | 400 | |
| @@ -54,7 +54,13 @@ · 53 unmodified lines | ||
| 54 | 54 | pinctrl-names = "default"; |
| 55 | 55 | pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; |
| 56 | 56 | phy-mode = "rgmii-id"; |
| 57 | − phy-reset-duration = <2>; | |
| 57 | + | |
| 58 | + /* | |
| 59 | + * The PHY seems to require a long-enough reset duration to avoid | |
| 60 | + * some rare issues where the PHY gets stuck in an inconsistent and | |
| 61 | + * non-functional state at boot-up. 10ms proved to be fine . | |
| 62 | + */ | |
| 63 | + phy-reset-duration = <10>; | |
| 58 | 64 | phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
| 59 | 65 | status = "okay"; |
| 60 | 66 | |
| @@ -43,6 +43,7 @@ · 42 unmodified lines | ||
| 43 | 43 | assigned-clock-rates = <0>, <198000000>; |
| 44 | 44 | cap-power-off-card; |
| 45 | 45 | keep-power-in-suspend; |
| 46 | + max-frequency = <25000000>; | |
| 46 | 47 | mmc-pwrseq = <&wifi_pwrseq>; |
| 47 | 48 | no-1-8-v; |
| 48 | 49 | non-removable; |
| @@ -30,14 +30,6 @@ · 29 unmodified lines | ||
| 30 | 30 | regulator-max-microvolt = <5000000>; |
| 31 | 31 | }; |
| 32 | 32 | |
| 33 | − vdds_1v8_main: fixedregulator-vdds_1v8_main { | |
| 34 | − compatible = "regulator-fixed"; | |
| 35 | − regulator-name = "vdds_1v8_main"; | |
| 36 | − vin-supply = <&smps7_reg>; | |
| 37 | − regulator-min-microvolt = <1800000>; | |
| 38 | − regulator-max-microvolt = <1800000>; | |
| 39 | − }; | |
| 40 | − | |
| 41 | 33 | vmmcsd_fixed: fixedregulator-mmcsd { |
| 42 | 34 | compatible = "regulator-fixed"; |
| 43 | 35 | regulator-name = "vmmcsd_fixed"; |
| @@ -487,6 +479,7 @@ · 443 unmodified lines | ||
| 487 | 479 | regulator-boot-on; |
| 488 | 480 | }; |
| 489 | 481 | |
| 482 | + vdds_1v8_main: | |
| 490 | 483 | smps7_reg: smps7 { |
| 491 | 484 | /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ |
| 492 | 485 | regulator-name = "smps7"; |
| @@ -581,7 +581,7 @@ · 580 unmodified lines | ||
| 581 | 581 | * EBI2. This has a 25MHz chrystal next to it, so no |
| 582 | 582 | * clocking is needed. |
| 583 | 583 | */ |
| 584 | − ethernet-ebi2@2,0 { | |
| 584 | + ethernet@2,0 { | |
| 585 | 585 | compatible = "smsc,lan9221", "smsc,lan9115"; |
| 586 | 586 | reg = <2 0x0 0x100>; |
| 587 | 587 | /* |
| @@ -598,8 +598,6 @@ · 10 unmodified lines | ||
| 598 | 598 | phy-mode = "mii"; |
| 599 | 599 | reg-io-width = <2>; |
| 600 | 600 | smsc,force-external-phy; |
| 601 | − /* IRQ on edge falling = active low */ | |
| 602 | − smsc,irq-active-low; | |
| 603 | 601 | smsc,irq-push-pull; |
| 604 | 602 | |
| 605 | 603 | /* |
| @@ -755,14 +755,14 @@ · 754 unmodified lines | ||
| 755 | 755 | status = "disabled"; |
| 756 | 756 | }; |
| 757 | 757 | |
| 758 | − vica: intc@10140000 { | |
| 758 | + vica: interrupt-controller@10140000 { | |
| 759 | 759 | compatible = "arm,versatile-vic"; |
| 760 | 760 | interrupt-controller; |
| 761 | 761 | #interrupt-cells = <1>; |
| 762 | 762 | reg = <0x10140000 0x20>; |
| 763 | 763 | }; |
| 764 | 764 | |
| 765 | − vicb: intc@10140020 { | |
| 765 | + vicb: interrupt-controller@10140020 { | |
| 766 | 766 | compatible = "arm,versatile-vic"; |
| 767 | 767 | interrupt-controller; |
| 768 | 768 | #interrupt-cells = <1>; |
| @@ -37,7 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | poll-interval = <20>; |
| 38 | 38 | |
| 39 | 39 | /* |
| 40 | − * The EXTi IRQ line 3 is shared with touchscreen and ethernet, | |
| 40 | + * The EXTi IRQ line 3 is shared with ethernet, | |
| 41 | 41 | * so mark this as polled GPIO key. |
| 42 | 42 | */ |
| 43 | 43 | button-0 { |
| @@ -46,6 +46,16 @@ · 2 unmodified lines | ||
| 46 | 46 | gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; |
| 47 | 47 | }; |
| 48 | 48 | |
| 49 | + /* | |
| 50 | + * The EXTi IRQ line 6 is shared with touchscreen, | |
| 51 | + * so mark this as polled GPIO key. | |
| 52 | + */ | |
| 53 | + button-1 { | |
| 54 | + label = "TA2-GPIO-B"; | |
| 55 | + linux,code = <KEY_B>; | |
| 56 | + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; | |
| 57 | + }; | |
| 58 | + | |
| 49 | 59 | /* |
| 50 | 60 | * The EXTi IRQ line 0 is shared with PMIC, |
| 51 | 61 | * so mark this as polled GPIO key. |
| @@ -60,13 +70,6 @@ · 8 unmodified lines | ||
| 60 | 70 | gpio-keys { |
| 61 | 71 | compatible = "gpio-keys"; |
| 62 | 72 | |
| 63 | − button-1 { | |
| 64 | − label = "TA2-GPIO-B"; | |
| 65 | − linux,code = <KEY_B>; | |
| 66 | − gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; | |
| 67 | − wakeup-source; | |
| 68 | − }; | |
| 69 | − | |
| 70 | 73 | button-3 { |
| 71 | 74 | label = "TA4-GPIO-D"; |
| 72 | 75 | linux,code = <KEY_D>; |
| @@ -82,6 +85,7 @@ · 9 unmodified lines | ||
| 82 | 85 | label = "green:led5"; |
| 83 | 86 | gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; |
| 84 | 87 | default-state = "off"; |
| 88 | + status = "disabled"; | |
| 85 | 89 | }; |
| 86 | 90 | |
| 87 | 91 | led-1 { |
| @@ -185,8 +189,8 @@ · 97 unmodified lines | ||
| 185 | 189 | touchscreen@38 { |
| 186 | 190 | compatible = "edt,edt-ft5406"; |
| 187 | 191 | reg = <0x38>; |
| 188 | − interrupt-parent = <&gpiog>; | |
| 189 | − interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ | |
| 192 | + interrupt-parent = <&gpioc>; | |
| 193 | + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ | |
| 190 | 194 | }; |
| 191 | 195 | }; |
| 192 | 196 | |
| @@ -12,6 +12,8 @@ · 11 unmodified lines | ||
| 12 | 12 | aliases { |
| 13 | 13 | ethernet0 = ðernet0; |
| 14 | 14 | ethernet1 = &ksz8851; |
| 15 | + rtc0 = &hwrtc; | |
| 16 | + rtc1 = &rtc; | |
| 15 | 17 | }; |
| 16 | 18 | |
| 17 | 19 | memory@c0000000 { |
| @@ -138,6 +140,7 @@ · 120 unmodified lines | ||
| 138 | 140 | reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; |
| 139 | 141 | reset-assert-us = <500>; |
| 140 | 142 | reset-deassert-us = <500>; |
| 143 | + smsc,disable-energy-detect; | |
| 141 | 144 | interrupt-parent = <&gpioi>; |
| 142 | 145 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
| 143 | 146 | }; |
| @@ -248,7 +251,7 @@ · 104 unmodified lines | ||
| 248 | 251 | /delete-property/dmas; |
| 249 | 252 | /delete-property/dma-names; |
| 250 | 253 | |
| 251 | − rtc@32 { | |
| 254 | + hwrtc: rtc@32 { | |
| 252 | 255 | compatible = "microcrystal,rv8803"; |
| 253 | 256 | reg = <0x32>; |
| 254 | 257 | }; |
| @@ -195,16 +195,15 @@ · 194 unmodified lines | ||
| 195 | 195 | #size-cells = <1>; |
| 196 | 196 | ranges; |
| 197 | 197 | |
| 198 | − vic: intc@10140000 { | |
| 198 | + vic: interrupt-controller@10140000 { | |
| 199 | 199 | compatible = "arm,versatile-vic"; |
| 200 | 200 | interrupt-controller; |
| 201 | 201 | #interrupt-cells = <1>; |
| 202 | 202 | reg = <0x10140000 0x1000>; |
| 203 | − clear-mask = <0xffffffff>; | |
| 204 | 203 | valid-mask = <0xffffffff>; |
| 205 | 204 | }; |
| 206 | 205 | |
| 207 | − sic: intc@10003000 { | |
| 206 | + sic: interrupt-controller@10003000 { | |
| 208 | 207 | compatible = "arm,versatile-sic"; |
| 209 | 208 | interrupt-controller; |
| 210 | 209 | #interrupt-cells = <1>; |
| @@ -7,7 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | |
| 8 | 8 | amba { |
| 9 | 9 | /* The Versatile PB is using more SIC IRQ lines than the AB */ |
| 10 | − sic: intc@10003000 { | |
| 10 | + sic: interrupt-controller@10003000 { | |
| 11 | 11 | clear-mask = <0xffffffff>; |
| 12 | 12 | /* |
| 13 | 13 | * Valid interrupt lines mask according to |
| @@ -57,10 +57,7 @@ CONFIG_DRM=y · 56 unmodified lines | ||
| 57 | 57 | CONFIG_DRM_DISPLAY_CONNECTOR=y |
| 58 | 58 | CONFIG_DRM_SIMPLE_BRIDGE=y |
| 59 | 59 | CONFIG_DRM_PL111=y |
| 60 | −CONFIG_FB_MODE_HELPERS=y | |
| 61 | −CONFIG_FB_MATROX=y | |
| 62 | −CONFIG_FB_MATROX_MILLENIUM=y | |
| 63 | −CONFIG_FB_MATROX_MYSTIQUE=y | |
| 60 | +CONFIG_FB=y | |
| 64 | 61 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 65 | 62 | # CONFIG_VGA_CONSOLE is not set |
| 66 | 63 | CONFIG_LOGO=y |
| @@ -821,7 +821,7 @@ CONFIG_USB_ISP1760=y · 820 unmodified lines | ||
| 821 | 821 | CONFIG_USB_HSIC_USB3503=y |
| 822 | 822 | CONFIG_AB8500_USB=y |
| 823 | 823 | CONFIG_KEYSTONE_USB_PHY=m |
| 824 | −CONFIG_NOP_USB_XCEIV=m | |
| 824 | +CONFIG_NOP_USB_XCEIV=y | |
| 825 | 825 | CONFIG_AM335X_PHY_USB=m |
| 826 | 826 | CONFIG_TWL6030_USB=m |
| 827 | 827 | CONFIG_USB_GPIO_VBUS=y |
| @@ -15,8 +15,6 @@ CONFIG_SLAB=y · 14 unmodified lines | ||
| 15 | 15 | CONFIG_ARCH_NOMADIK=y |
| 16 | 16 | CONFIG_MACH_NOMADIK_8815NHK=y |
| 17 | 17 | CONFIG_AEABI=y |
| 18 | −CONFIG_ZBOOT_ROM_TEXT=0x0 | |
| 19 | −CONFIG_ZBOOT_ROM_BSS=0x0 | |
| 20 | 18 | CONFIG_MODULES=y |
| 21 | 19 | CONFIG_MODULE_UNLOAD=y |
| 22 | 20 | # CONFIG_BLK_DEV_BSG is not set |
| @@ -52,9 +50,9 @@ CONFIG_MTD_BLOCK=y · 29 unmodified lines | ||
| 52 | 50 | CONFIG_MTD_ONENAND=y |
| 53 | 51 | CONFIG_MTD_ONENAND_VERIFY_WRITE=y |
| 54 | 52 | CONFIG_MTD_ONENAND_GENERIC=y |
| 55 | −CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y | |
| 56 | 53 | CONFIG_MTD_RAW_NAND=y |
| 57 | 54 | CONFIG_MTD_NAND_FSMC=y |
| 55 | +CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y | |
| 58 | 56 | CONFIG_BLK_DEV_LOOP=y |
| 59 | 57 | CONFIG_BLK_DEV_CRYPTOLOOP=y |
| 60 | 58 | CONFIG_BLK_DEV_RAM=y |
| @@ -97,6 +95,7 @@ CONFIG_REGULATOR=y · 36 unmodified lines | ||
| 97 | 95 | CONFIG_DRM=y |
| 98 | 96 | CONFIG_DRM_PANEL_TPO_TPG110=y |
| 99 | 97 | CONFIG_DRM_PL111=y |
| 98 | +CONFIG_FB=y | |
| 100 | 99 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 101 | 100 | CONFIG_BACKLIGHT_PWM=y |
| 102 | 101 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| @@ -136,9 +135,8 @@ CONFIG_NLS_ISO8859_15=y · 33 unmodified lines | ||
| 136 | 135 | CONFIG_CRYPTO_MD5=y |
| 137 | 136 | CONFIG_CRYPTO_SHA1=y |
| 138 | 137 | CONFIG_CRYPTO_DES=y |
| 138 | +# CONFIG_DEBUG_BUGVERBOSE is not set | |
| 139 | 139 | CONFIG_DEBUG_INFO=y |
| 140 | −# CONFIG_ENABLE_MUST_CHECK is not set | |
| 141 | 140 | CONFIG_DEBUG_FS=y |
| 142 | 141 | # CONFIG_SCHED_DEBUG is not set |
| 143 | 142 | # CONFIG_DEBUG_PREEMPT is not set |
| 144 | −# CONFIG_DEBUG_BUGVERBOSE is not set | |
| @@ -64,11 +64,9 @@ CONFIG_DRM_PANEL_SIMPLE=y · 63 unmodified lines | ||
| 64 | 64 | CONFIG_DRM_DISPLAY_CONNECTOR=y |
| 65 | 65 | CONFIG_DRM_SIMPLE_BRIDGE=y |
| 66 | 66 | CONFIG_DRM_PL111=y |
| 67 | −CONFIG_FB_MODE_HELPERS=y | |
| 67 | +CONFIG_FB=y | |
| 68 | 68 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 69 | 69 | CONFIG_LOGO=y |
| 70 | −# CONFIG_LOGO_LINUX_MONO is not set | |
| 71 | −# CONFIG_LOGO_LINUX_VGA16 is not set | |
| 72 | 70 | CONFIG_SOUND=y |
| 73 | 71 | CONFIG_SND=y |
| 74 | 72 | # CONFIG_SND_DRIVERS is not set |
| @@ -135,6 +135,7 @@ CONFIG_DRM_SII902X=y · 134 unmodified lines | ||
| 135 | 135 | CONFIG_DRM_SIMPLE_BRIDGE=y |
| 136 | 136 | CONFIG_DRM_I2C_ADV7511=y |
| 137 | 137 | CONFIG_DRM_I2C_ADV7511_AUDIO=y |
| 138 | +CONFIG_FB=y | |
| 138 | 139 | CONFIG_FB_SH_MOBILE_LCDC=y |
| 139 | 140 | CONFIG_BACKLIGHT_PWM=y |
| 140 | 141 | CONFIG_BACKLIGHT_AS3711=y |
| @@ -61,6 +61,10 @@ CONFIG_INPUT_TOUCHSCREEN=y · 60 unmodified lines | ||
| 61 | 61 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y |
| 62 | 62 | CONFIG_TOUCHSCREEN_BU21013=y |
| 63 | 63 | CONFIG_TOUCHSCREEN_CY8CTMA140=y |
| 64 | +CONFIG_TOUCHSCREEN_CYTTSP_CORE=y | |
| 65 | +CONFIG_TOUCHSCREEN_CYTTSP_SPI=y | |
| 66 | +CONFIG_TOUCHSCREEN_MMS114=y | |
| 67 | +CONFIG_TOUCHSCREEN_ZINITIX=y | |
| 64 | 68 | CONFIG_INPUT_MISC=y |
| 65 | 69 | CONFIG_INPUT_AB8500_PONKEY=y |
| 66 | 70 | CONFIG_INPUT_GPIO_VIBRA=y |
| @@ -100,6 +104,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y · 33 unmodified lines | ||
| 100 | 104 | CONFIG_DRM_PANEL_SONY_ACX424AKP=y |
| 101 | 105 | CONFIG_DRM_LIMA=y |
| 102 | 106 | CONFIG_DRM_MCDE=y |
| 107 | +CONFIG_FB=y | |
| 103 | 108 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 104 | 109 | CONFIG_BACKLIGHT_KTD253=y |
| 105 | 110 | CONFIG_BACKLIGHT_GPIO=y |
| @@ -60,7 +60,7 @@ CONFIG_DRM_PANEL_SIMPLE=y · 59 unmodified lines | ||
| 60 | 60 | CONFIG_DRM_DISPLAY_CONNECTOR=y |
| 61 | 61 | CONFIG_DRM_SIMPLE_BRIDGE=y |
| 62 | 62 | CONFIG_DRM_PL111=y |
| 63 | −CONFIG_FB_MODE_HELPERS=y | |
| 63 | +CONFIG_FB=y | |
| 64 | 64 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 65 | 65 | CONFIG_LOGO=y |
| 66 | 66 | CONFIG_SOUND=y |
| @@ -88,8 +88,6 @@ CONFIG_NFSD=y · 21 unmodified lines | ||
| 88 | 88 | CONFIG_NFSD_V3=y |
| 89 | 89 | CONFIG_NLS_CODEPAGE_850=m |
| 90 | 90 | CONFIG_NLS_ISO8859_1=m |
| 91 | −CONFIG_FONTS=y | |
| 92 | −CONFIG_FONT_ACORN_8x8=y | |
| 93 | 91 | CONFIG_MAGIC_SYSRQ=y |
| 94 | 92 | CONFIG_DEBUG_FS=y |
| 95 | 93 | CONFIG_DEBUG_KERNEL=y |
| @@ -11,9 +11,6 @@ CONFIG_CPUSETS=y · 10 unmodified lines | ||
| 11 | 11 | # CONFIG_NET_NS is not set |
| 12 | 12 | CONFIG_BLK_DEV_INITRD=y |
| 13 | 13 | CONFIG_PROFILING=y |
| 14 | −CONFIG_MODULES=y | |
| 15 | −CONFIG_MODULE_UNLOAD=y | |
| 16 | −# CONFIG_BLK_DEV_BSG is not set | |
| 17 | 14 | CONFIG_ARCH_VEXPRESS=y |
| 18 | 15 | CONFIG_ARCH_VEXPRESS_DCSCB=y |
| 19 | 16 | CONFIG_ARCH_VEXPRESS_TC2_PM=y |
| @@ -23,14 +20,17 @@ CONFIG_MCPM=y · 3 unmodified lines | ||
| 23 | 20 | CONFIG_VMSPLIT_2G=y |
| 24 | 21 | CONFIG_NR_CPUS=8 |
| 25 | 22 | CONFIG_ARM_PSCI=y |
| 26 | −CONFIG_CMA=y | |
| 27 | 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 28 | 24 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 29 | 25 | CONFIG_CMDLINE="console=ttyAMA0" |
| 30 | 26 | CONFIG_CPU_IDLE=y |
| 31 | 27 | CONFIG_VFP=y |
| 32 | 28 | CONFIG_NEON=y |
| 29 | +CONFIG_MODULES=y | |
| 30 | +CONFIG_MODULE_UNLOAD=y | |
| 31 | +# CONFIG_BLK_DEV_BSG is not set | |
| 33 | 32 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 33 | +CONFIG_CMA=y | |
| 34 | 34 | CONFIG_NET=y |
| 35 | 35 | CONFIG_PACKET=y |
| 36 | 36 | CONFIG_UNIX=y |
| @@ -43,7 +43,6 @@ CONFIG_IP_PNP_BOOTP=y · 6 unmodified lines | ||
| 43 | 43 | CONFIG_NET_9P=y |
| 44 | 44 | CONFIG_NET_9P_VIRTIO=y |
| 45 | 45 | CONFIG_DEVTMPFS=y |
| 46 | −CONFIG_DMA_CMA=y | |
| 47 | 46 | CONFIG_MTD=y |
| 48 | 47 | CONFIG_MTD_CMDLINE_PARTS=y |
| 49 | 48 | CONFIG_MTD_BLOCK=y |
| @@ -59,7 +58,6 @@ CONFIG_VIRTIO_BLK=y · 9 unmodified lines | ||
| 59 | 58 | CONFIG_BLK_DEV_SD=y |
| 60 | 59 | CONFIG_SCSI_VIRTIO=y |
| 61 | 60 | CONFIG_ATA=y |
| 62 | −# CONFIG_SATA_PMP is not set | |
| 63 | 61 | CONFIG_NETDEVICES=y |
| 64 | 62 | CONFIG_VIRTIO_NET=y |
| 65 | 63 | CONFIG_SMC91X=y |
| @@ -81,11 +79,9 @@ CONFIG_DRM=y · 15 unmodified lines | ||
| 81 | 79 | CONFIG_DRM_PANEL_SIMPLE=y |
| 82 | 80 | CONFIG_DRM_SII902X=y |
| 83 | 81 | CONFIG_DRM_PL111=y |
| 84 | −CONFIG_FB_MODE_HELPERS=y | |
| 82 | +CONFIG_FB=y | |
| 85 | 83 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 86 | 84 | CONFIG_LOGO=y |
| 87 | −# CONFIG_LOGO_LINUX_MONO is not set | |
| 88 | −# CONFIG_LOGO_LINUX_VGA16 is not set | |
| 89 | 85 | CONFIG_SOUND=y |
| 90 | 86 | CONFIG_SND=y |
| 91 | 87 | # CONFIG_SND_DRIVERS is not set |
| @@ -136,10 +132,11 @@ CONFIG_ROOT_NFS=y · 44 unmodified lines | ||
| 136 | 132 | CONFIG_9P_FS=y |
| 137 | 133 | CONFIG_NLS_CODEPAGE_437=y |
| 138 | 134 | CONFIG_NLS_ISO8859_1=y |
| 135 | +# CONFIG_CRYPTO_HW is not set | |
| 136 | +CONFIG_DMA_CMA=y | |
| 139 | 137 | CONFIG_DEBUG_INFO=y |
| 140 | 138 | CONFIG_MAGIC_SYSRQ=y |
| 141 | 139 | CONFIG_DEBUG_KERNEL=y |
| 142 | 140 | CONFIG_DETECT_HUNG_TASK=y |
| 143 | 141 | # CONFIG_SCHED_DEBUG is not set |
| 144 | 142 | CONFIG_DEBUG_USER=y |
| 145 | −# CONFIG_CRYPTO_HW is not set | |
| @@ -9,7 +9,6 @@ menuconfig ARCH_DAVINCI · 8 unmodified lines | ||
| 9 | 9 | select PM_GENERIC_DOMAINS_OF if PM && OF |
| 10 | 10 | select REGMAP_MMIO |
| 11 | 11 | select RESET_CONTROLLER |
| 12 | − select HAVE_IDE | |
| 13 | 12 | select PINCTRL_SINGLE |
| 14 | 13 | |
| 15 | 14 | if ARCH_DAVINCI |
| @@ -68,7 +68,6 @@ void imx_set_cpu_arg(int cpu, u32 arg); · 67 unmodified lines | ||
| 68 | 68 | void v7_secondary_startup(void); |
| 69 | 69 | void imx_scu_map_io(void); |
| 70 | 70 | void imx_smp_prepare(void); |
| 71 | −void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); | |
| 72 | 71 | #else |
| 73 | 72 | static inline void imx_scu_map_io(void) {} |
| 74 | 73 | static inline void imx_smp_prepare(void) {} |
| @@ -81,6 +80,7 @@ void imx_gpc_mask_all(void); · 6 unmodified lines | ||
| 81 | 80 | void imx_gpc_restore_all(void); |
| 82 | 81 | void imx_gpc_hwirq_mask(unsigned int hwirq); |
| 83 | 82 | void imx_gpc_hwirq_unmask(unsigned int hwirq); |
| 83 | +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); | |
| 84 | 84 | void imx_anatop_init(void); |
| 85 | 85 | void imx_anatop_pre_suspend(void); |
| 86 | 86 | void imx_anatop_post_resume(void); |
| @@ -103,6 +103,7 @@ struct mmdc_pmu { · 102 unmodified lines | ||
| 103 | 103 | struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; |
| 104 | 104 | struct hlist_node node; |
| 105 | 105 | struct fsl_mmdc_devtype_data *devtype_data; |
| 106 | + struct clk *mmdc_ipg_clk; | |
| 106 | 107 | }; |
| 107 | 108 | |
| 108 | 109 | /* |
| @@ -462,11 +463,14 @@ static int imx_mmdc_remove(struct platform_device *pdev) · 353 unmodified lines | ||
| 462 | 463 | |
| 463 | 464 | cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); |
| 464 | 465 | perf_pmu_unregister(&pmu_mmdc->pmu); |
| 466 | + iounmap(pmu_mmdc->mmdc_base); | |
| 467 | + clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk); | |
| 465 | 468 | kfree(pmu_mmdc); |
| 466 | 469 | return 0; |
| 467 | 470 | } |
| 468 | 471 | |
| 469 | −static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base) | |
| 472 | +static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base, | |
| 473 | + struct clk *mmdc_ipg_clk) | |
| 470 | 474 | { |
| 471 | 475 | struct mmdc_pmu *pmu_mmdc; |
| 472 | 476 | char *name; |
| @@ -494,6 +498,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b · 21 unmodified lines | ||
| 494 | 498 | } |
| 495 | 499 | |
| 496 | 500 | mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); |
| 501 | + pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; | |
| 497 | 502 | if (mmdc_num == 0) |
| 498 | 503 | name = "mmdc"; |
| 499 | 504 | else |
| @@ -529,7 +534,7 @@ pmu_free: · 29 unmodified lines | ||
| 529 | 534 | |
| 530 | 535 | #else |
| 531 | 536 | #define imx_mmdc_remove NULL |
| 532 | −#define imx_mmdc_perf_init(pdev, mmdc_base) 0 | |
| 537 | +#define imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk) 0 | |
| 533 | 538 | #endif |
| 534 | 539 | |
| 535 | 540 | static int imx_mmdc_probe(struct platform_device *pdev) |
| @@ -567,7 +572,13 @@ static int imx_mmdc_probe(struct platform_device *pdev) · 31 unmodified lines | ||
| 567 | 572 | val &= ~(1 << BP_MMDC_MAPSR_PSD); |
| 568 | 573 | writel_relaxed(val, reg); |
| 569 | 574 | |
| 570 | − return imx_mmdc_perf_init(pdev, mmdc_base); | |
| 575 | + err = imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk); | |
| 576 | + if (err) { | |
| 577 | + iounmap(mmdc_base); | |
| 578 | + clk_disable_unprepare(mmdc_ipg_clk); | |
| 579 | + } | |
| 580 | + | |
| 581 | + return err; | |
| 571 | 582 | } |
| 572 | 583 | |
| 573 | 584 | int imx_mmdc_get_ddr_type(void) |
| @@ -91,6 +91,7 @@ config MACH_IXDP465 · 90 unmodified lines | ||
| 91 | 91 | |
| 92 | 92 | config MACH_GORAMO_MLR |
| 93 | 93 | bool "GORAMO Multi Link Router" |
| 94 | + depends on IXP4XX_PCI_LEGACY | |
| 94 | 95 | help |
| 95 | 96 | Say 'Y' here if you want your kernel to support GORAMO |
| 96 | 97 | MultiLink router. |
| @@ -218,30 +218,30 @@ · 217 unmodified lines | ||
| 218 | 218 | /* |
| 219 | 219 | * PCI Control/Status Registers |
| 220 | 220 | */ |
| 221 | −#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) | |
| 222 | − | |
| 223 | −#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) | |
| 224 | −#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) | |
| 225 | −#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) | |
| 226 | −#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) | |
| 227 | −#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) | |
| 228 | −#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) | |
| 229 | −#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) | |
| 230 | −#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET) | |
| 231 | −#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET) | |
| 232 | −#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) | |
| 233 | −#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) | |
| 234 | −#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) | |
| 235 | −#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) | |
| 236 | −#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) | |
| 237 | −#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) | |
| 238 | −#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) | |
| 239 | −#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) | |
| 240 | −#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) | |
| 241 | −#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) | |
| 242 | −#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) | |
| 243 | −#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) | |
| 244 | −#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) | |
| 221 | +#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) | |
| 222 | + | |
| 223 | +#define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) | |
| 224 | +#define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) | |
| 225 | +#define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) | |
| 226 | +#define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) | |
| 227 | +#define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) | |
| 228 | +#define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) | |
| 229 | +#define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) | |
| 230 | +#define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) | |
| 231 | +#define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET) | |
| 232 | +#define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) | |
| 233 | +#define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) | |
| 234 | +#define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) | |
| 235 | +#define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) | |
| 236 | +#define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) | |
| 237 | +#define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) | |
| 238 | +#define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) | |
| 239 | +#define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) | |
| 240 | +#define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) | |
| 241 | +#define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) | |
| 242 | +#define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) | |
| 243 | +#define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) | |
| 244 | +#define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) | |
| 245 | 245 | |
| 246 | 246 | /* |
| 247 | 247 | * PCI register values and bit definitions |
| @@ -3776,6 +3776,7 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) · 3775 unmodified lines | ||
| 3776 | 3776 | struct omap_hwmod_ocp_if *oi; |
| 3777 | 3777 | struct clockdomain *clkdm; |
| 3778 | 3778 | struct clk_hw_omap *clk; |
| 3779 | + struct clk_hw *hw; | |
| 3779 | 3780 | |
| 3780 | 3781 | if (!oh) |
| 3781 | 3782 | return NULL; |
| @@ -3792,7 +3793,14 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) · 10 unmodified lines | ||
| 3792 | 3793 | c = oi->_clk; |
| 3793 | 3794 | } |
| 3794 | 3795 | |
| 3795 | − clk = to_clk_hw_omap(__clk_get_hw(c)); | |
| 3796 | + hw = __clk_get_hw(c); | |
| 3797 | + if (!hw) | |
| 3798 | + return NULL; | |
| 3799 | + | |
| 3800 | + clk = to_clk_hw_omap(hw); | |
| 3801 | + if (!clk) | |
| 3802 | + return NULL; | |
| 3803 | + | |
| 3796 | 3804 | clkdm = clk->clkdm; |
| 3797 | 3805 | if (!clkdm) |
| 3798 | 3806 | return NULL; |
| @@ -49,6 +49,7 @@ static int __init parse_tag_acorn(const struct tag *tag) · 48 unmodified lines | ||
| 49 | 49 | fallthrough; /* ??? */ |
| 50 | 50 | case 256: |
| 51 | 51 | vram_size += PAGE_SIZE * 256; |
| 52 | + break; | |
| 52 | 53 | default: |
| 53 | 54 | break; |
| 54 | 55 | } |
| @@ -1602,6 +1602,9 @@ exit: · 1601 unmodified lines | ||
| 1602 | 1602 | rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); |
| 1603 | 1603 | emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code)); |
| 1604 | 1604 | break; |
| 1605 | + /* speculation barrier */ | |
| 1606 | + case BPF_ST | BPF_NOSPEC: | |
| 1607 | + break; | |
| 1605 | 1608 | /* ST: *(size *)(dst + off) = imm */ |
| 1606 | 1609 | case BPF_ST | BPF_MEM | BPF_W: |
| 1607 | 1610 | case BPF_ST | BPF_MEM | BPF_H: |
| @@ -1605,7 +1605,8 @@ config ARM64_BTI_KERNEL · 1604 unmodified lines | ||
| 1605 | 1605 | depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI |
| 1606 | 1606 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 |
| 1607 | 1607 | depends on !CC_IS_GCC || GCC_VERSION >= 100100 |
| 1608 | − depends on !(CC_IS_CLANG && GCOV_KERNEL) | |
| 1608 | + # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 | |
| 1609 | + depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 | |
| 1609 | 1610 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) |
| 1610 | 1611 | help |
| 1611 | 1612 | Build the kernel with Branch Target Identification annotations |
| @@ -1799,11 +1800,11 @@ config RANDOMIZE_BASE · 187 unmodified lines | ||
| 1799 | 1800 | If unsure, say N. |
| 1800 | 1801 | |
| 1801 | 1802 | config RANDOMIZE_MODULE_REGION_FULL |
| 1802 | − bool "Randomize the module region over a 4 GB range" | |
| 1803 | + bool "Randomize the module region over a 2 GB range" | |
| 1803 | 1804 | depends on RANDOMIZE_BASE |
| 1804 | 1805 | default y |
| 1805 | 1806 | help |
| 1806 | − Randomizes the location of the module region inside a 4 GB window | |
| 1807 | + Randomizes the location of the module region inside a 2 GB window | |
| 1807 | 1808 | covering the core kernel. This way, it is less likely for modules |
| 1808 | 1809 | to leak information about the location of core kernel data structures |
| 1809 | 1810 | but it does imply that function calls between modules and the core |
| @@ -1811,7 +1812,10 @@ config RANDOMIZE_MODULE_REGION_FULL · 1 unmodified line | ||
| 1811 | 1812 | |
| 1812 | 1813 | When this option is not set, the module region will be randomized over |
| 1813 | 1814 | a limited range that contains the [_stext, _etext] interval of the |
| 1814 | − core kernel, so branch relocations are always in range. | |
| 1815 | + core kernel, so branch relocations are almost always in range unless | |
| 1816 | + ARM64_MODULE_PLTS is enabled and the region is exhausted. In this | |
| 1817 | + particular case of region exhaustion, modules might be able to fall | |
| 1818 | + back to a larger 2GB area. | |
| 1815 | 1819 | |
| 1816 | 1820 | config CC_HAVE_STACKPROTECTOR_SYSREG |
| 1817 | 1821 | def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) |
| @@ -21,19 +21,11 @@ LDFLAGS_vmlinux += -shared -Bsymbolic -z notext \ · 20 unmodified lines | ||
| 21 | 21 | endif |
| 22 | 22 | |
| 23 | 23 | ifeq ($(CONFIG_ARM64_ERRATUM_843419),y) |
| 24 | − ifneq ($(CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419),y) | |
| 25 | −$(warning ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum) | |
| 26 | − else | |
| 24 | + ifeq ($(CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419),y) | |
| 27 | 25 | LDFLAGS_vmlinux += --fix-cortex-a53-843419 |
| 28 | 26 | endif |
| 29 | 27 | endif |
| 30 | 28 | |
| 31 | −ifeq ($(CONFIG_ARM64_USE_LSE_ATOMICS), y) | |
| 32 | − ifneq ($(CONFIG_ARM64_LSE_ATOMICS), y) | |
| 33 | −$(warning LSE atomics not supported by binutils) | |
| 34 | − endif | |
| 35 | −endif | |
| 36 | − | |
| 37 | 29 | cc_has_k_constraint := $(call try-run,echo \ |
| 38 | 30 | 'int main(void) { \ |
| 39 | 31 | asm volatile("and w0, w0, %w0" :: "K" (4294967295)); \ |
| @@ -176,10 +168,23 @@ vdso_install: · 136 unmodified lines | ||
| 176 | 168 | |
| 177 | 169 | archprepare: |
| 178 | 170 | $(Q)$(MAKE) $(build)=arch/arm64/tools kapi |
| 171 | +ifeq ($(CONFIG_ARM64_ERRATUM_843419),y) | |
| 172 | + ifneq ($(CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419),y) | |
| 173 | + @echo "warning: ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum" >&2 | |
| 174 | + endif | |
| 175 | +endif | |
| 176 | +ifeq ($(CONFIG_ARM64_USE_LSE_ATOMICS),y) | |
| 177 | + ifneq ($(CONFIG_ARM64_LSE_ATOMICS),y) | |
| 178 | + @echo "warning: LSE atomics not supported by binutils" >&2 | |
| 179 | + endif | |
| 180 | +endif | |
| 181 | + | |
| 179 | 182 | |
| 180 | 183 | # We use MRPROPER_FILES and CLEAN_FILES now |
| 181 | 184 | archclean: |
| 182 | 185 | $(Q)$(MAKE) $(clean)=$(boot) |
| 186 | + $(Q)$(MAKE) $(clean)=arch/arm64/kernel/vdso | |
| 187 | + $(Q)$(MAKE) $(clean)=arch/arm64/kernel/vdso32 | |
| 183 | 188 | |
| 184 | 189 | ifeq ($(KBUILD_EXTMOD),) |
| 185 | 190 | # We need to generate vdso-offsets.h before compiling certain files in kernel/. |
| @@ -54,6 +54,7 @@ · 53 unmodified lines | ||
| 54 | 54 | |
| 55 | 55 | &mscc_felix_port0 { |
| 56 | 56 | label = "swp0"; |
| 57 | + managed = "in-band-status"; | |
| 57 | 58 | phy-handle = <&phy0>; |
| 58 | 59 | phy-mode = "sgmii"; |
| 59 | 60 | status = "okay"; |
| @@ -61,6 +62,7 @@ · 1 unmodified line | ||
| 61 | 62 | |
| 62 | 63 | &mscc_felix_port1 { |
| 63 | 64 | label = "swp1"; |
| 65 | + managed = "in-band-status"; | |
| 64 | 66 | phy-handle = <&phy1>; |
| 65 | 67 | phy-mode = "sgmii"; |
| 66 | 68 | status = "okay"; |
| @@ -66,7 +66,7 @@ · 65 unmodified lines | ||
| 66 | 66 | }; |
| 67 | 67 | }; |
| 68 | 68 | |
| 69 | − sysclk: clock-sysclk { | |
| 69 | + sysclk: sysclk { | |
| 70 | 70 | compatible = "fixed-clock"; |
| 71 | 71 | #clock-cells = <0>; |
| 72 | 72 | clock-frequency = <100000000>; |
| @@ -579,7 +579,7 @@ · 578 unmodified lines | ||
| 579 | 579 | }; |
| 580 | 580 | |
| 581 | 581 | flexcan1: can@308c0000 { |
| 582 | − compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; | |
| 582 | + compatible = "fsl,imx8mp-flexcan"; | |
| 583 | 583 | reg = <0x308c0000 0x10000>; |
| 584 | 584 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| 585 | 585 | clocks = <&clk IMX8MP_CLK_IPG_ROOT>, |
| @@ -594,7 +594,7 @@ · 8 unmodified lines | ||
| 594 | 594 | }; |
| 595 | 595 | |
| 596 | 596 | flexcan2: can@308d0000 { |
| 597 | − compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; | |
| 597 | + compatible = "fsl,imx8mp-flexcan"; | |
| 598 | 598 | reg = <0x308d0000 0x10000>; |
| 599 | 599 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| 600 | 600 | clocks = <&clk IMX8MP_CLK_IPG_ROOT>, |
| @@ -821,9 +821,9 @@ · 220 unmodified lines | ||
| 821 | 821 | eqos: ethernet@30bf0000 { |
| 822 | 822 | compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; |
| 823 | 823 | reg = <0x30bf0000 0x10000>; |
| 824 | − interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
| 825 | − <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
| 826 | − interrupt-names = "eth_wake_irq", "macirq"; | |
| 824 | + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 825 | + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| 826 | + interrupt-names = "macirq", "eth_wake_irq"; | |
| 827 | 827 | clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, |
| 828 | 828 | <&clk IMX8MP_CLK_QOS_ENET_ROOT>, |
| 829 | 829 | <&clk IMX8MP_CLK_ENET_QOS_TIMER>, |
| @@ -19,6 +19,8 @@ · 18 unmodified lines | ||
| 19 | 19 | aliases { |
| 20 | 20 | spi0 = &spi0; |
| 21 | 21 | ethernet1 = ð1; |
| 22 | + mmc0 = &sdhci0; | |
| 23 | + mmc1 = &sdhci1; | |
| 22 | 24 | }; |
| 23 | 25 | |
| 24 | 26 | chosen { |
| @@ -119,6 +121,7 @@ · 94 unmodified lines | ||
| 119 | 121 | pinctrl-names = "default"; |
| 120 | 122 | pinctrl-0 = <&i2c1_pins>; |
| 121 | 123 | clock-frequency = <100000>; |
| 124 | + /delete-property/ mrvl,i2c-fast-mode; | |
| 122 | 125 | status = "okay"; |
| 123 | 126 | |
| 124 | 127 | rtc@6f { |
| @@ -948,6 +948,10 @@ · 947 unmodified lines | ||
| 948 | 948 | <&bpmp TEGRA194_CLK_XUSB_SS>, |
| 949 | 949 | <&bpmp TEGRA194_CLK_XUSB_FS>; |
| 950 | 950 | clock-names = "dev", "ss", "ss_src", "fs_src"; |
| 951 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, | |
| 952 | + <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; | |
| 953 | + interconnect-names = "dma-mem", "write"; | |
| 954 | + iommus = <&smmu TEGRA194_SID_XUSB_DEV>; | |
| 951 | 955 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, |
| 952 | 956 | <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; |
| 953 | 957 | power-domain-names = "dev", "ss"; |
| @@ -977,6 +981,10 @@ · 23 unmodified lines | ||
| 977 | 981 | "xusb_ss", "xusb_ss_src", "xusb_hs_src", |
| 978 | 982 | "xusb_fs_src", "pll_u_480m", "clk_m", |
| 979 | 983 | "pll_e"; |
| 984 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, | |
| 985 | + <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; | |
| 986 | + interconnect-names = "dma-mem", "write"; | |
| 987 | + iommus = <&smmu TEGRA194_SID_XUSB_HOST>; | |
| 980 | 988 | |
| 981 | 989 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, |
| 982 | 990 | <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; |
| @@ -1832,7 +1840,11 @@ · 849 unmodified lines | ||
| 1832 | 1840 | |
| 1833 | 1841 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, |
| 1834 | 1842 | <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; |
| 1835 | − interconnect-names = "read", "write"; | |
| 1843 | + interconnect-names = "dma-mem", "write"; | |
| 1844 | + iommus = <&smmu TEGRA194_SID_PCIE1>; | |
| 1845 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; | |
| 1846 | + iommu-map-mask = <0x0>; | |
| 1847 | + dma-coherent; | |
| 1836 | 1848 | }; |
| 1837 | 1849 | |
| 1838 | 1850 | pcie@14120000 { |
| @@ -1882,7 +1894,11 @@ · 43 unmodified lines | ||
| 1882 | 1894 | |
| 1883 | 1895 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, |
| 1884 | 1896 | <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; |
| 1885 | − interconnect-names = "read", "write"; | |
| 1897 | + interconnect-names = "dma-mem", "write"; | |
| 1898 | + iommus = <&smmu TEGRA194_SID_PCIE2>; | |
| 1899 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; | |
| 1900 | + iommu-map-mask = <0x0>; | |
| 1901 | + dma-coherent; | |
| 1886 | 1902 | }; |
| 1887 | 1903 | |
| 1888 | 1904 | pcie@14140000 { |
| @@ -1932,7 +1948,11 @@ · 43 unmodified lines | ||
| 1932 | 1948 | |
| 1933 | 1949 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, |
| 1934 | 1950 | <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; |
| 1935 | − interconnect-names = "read", "write"; | |
| 1951 | + interconnect-names = "dma-mem", "write"; | |
| 1952 | + iommus = <&smmu TEGRA194_SID_PCIE3>; | |
| 1953 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; | |
| 1954 | + iommu-map-mask = <0x0>; | |
| 1955 | + dma-coherent; | |
| 1936 | 1956 | }; |
| 1937 | 1957 | |
| 1938 | 1958 | pcie@14160000 { |
| @@ -1982,7 +2002,11 @@ · 43 unmodified lines | ||
| 1982 | 2002 | |
| 1983 | 2003 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, |
| 1984 | 2004 | <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; |
| 1985 | − interconnect-names = "read", "write"; | |
| 2005 | + interconnect-names = "dma-mem", "write"; | |
| 2006 | + iommus = <&smmu TEGRA194_SID_PCIE4>; | |
| 2007 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; | |
| 2008 | + iommu-map-mask = <0x0>; | |
| 2009 | + dma-coherent; | |
| 1986 | 2010 | }; |
| 1987 | 2011 | |
| 1988 | 2012 | pcie@14180000 { |
| @@ -2032,7 +2056,11 @@ · 43 unmodified lines | ||
| 2032 | 2056 | |
| 2033 | 2057 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, |
| 2034 | 2058 | <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; |
| 2035 | − interconnect-names = "read", "write"; | |
| 2059 | + interconnect-names = "dma-mem", "write"; | |
| 2060 | + iommus = <&smmu TEGRA194_SID_PCIE0>; | |
| 2061 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; | |
| 2062 | + iommu-map-mask = <0x0>; | |
| 2063 | + dma-coherent; | |
| 2036 | 2064 | }; |
| 2037 | 2065 | |
| 2038 | 2066 | pcie@141a0000 { |
| @@ -2086,7 +2114,11 @@ · 47 unmodified lines | ||
| 2086 | 2114 | |
| 2087 | 2115 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, |
| 2088 | 2116 | <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; |
| 2089 | − interconnect-names = "read", "write"; | |
| 2117 | + interconnect-names = "dma-mem", "write"; | |
| 2118 | + iommus = <&smmu TEGRA194_SID_PCIE5>; | |
| 2119 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; | |
| 2120 | + iommu-map-mask = <0x0>; | |
| 2121 | + dma-coherent; | |
| 2090 | 2122 | }; |
| 2091 | 2123 | |
| 2092 | 2124 | pcie_ep@14160000 { |
| @@ -2119,6 +2151,14 @@ · 26 unmodified lines | ||
| 2119 | 2151 | nvidia,aspm-cmrt-us = <60>; |
| 2120 | 2152 | nvidia,aspm-pwr-on-t-us = <20>; |
| 2121 | 2153 | nvidia,aspm-l0s-entrance-latency-us = <3>; |
| 2154 | + | |
| 2155 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, | |
| 2156 | + <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; | |
| 2157 | + interconnect-names = "dma-mem", "write"; | |
| 2158 | + iommus = <&smmu TEGRA194_SID_PCIE4>; | |
| 2159 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; | |
| 2160 | + iommu-map-mask = <0x0>; | |
| 2161 | + dma-coherent; | |
| 2122 | 2162 | }; |
| 2123 | 2163 | |
| 2124 | 2164 | pcie_ep@14180000 { |
| @@ -2151,6 +2191,14 @@ · 26 unmodified lines | ||
| 2151 | 2191 | nvidia,aspm-cmrt-us = <60>; |
| 2152 | 2192 | nvidia,aspm-pwr-on-t-us = <20>; |
| 2153 | 2193 | nvidia,aspm-l0s-entrance-latency-us = <3>; |
| 2194 | + | |
| 2195 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, | |
| 2196 | + <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; | |
| 2197 | + interconnect-names = "dma-mem", "write"; | |
| 2198 | + iommus = <&smmu TEGRA194_SID_PCIE0>; | |
| 2199 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; | |
| 2200 | + iommu-map-mask = <0x0>; | |
| 2201 | + dma-coherent; | |
| 2154 | 2202 | }; |
| 2155 | 2203 | |
| 2156 | 2204 | pcie_ep@141a0000 { |
| @@ -2186,6 +2234,14 @@ · 29 unmodified lines | ||
| 2186 | 2234 | nvidia,aspm-cmrt-us = <60>; |
| 2187 | 2235 | nvidia,aspm-pwr-on-t-us = <20>; |
| 2188 | 2236 | nvidia,aspm-l0s-entrance-latency-us = <3>; |
| 2237 | + | |
| 2238 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, | |
| 2239 | + <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; | |
| 2240 | + interconnect-names = "dma-mem", "write"; | |
| 2241 | + iommus = <&smmu TEGRA194_SID_PCIE5>; | |
| 2242 | + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; | |
| 2243 | + iommu-map-mask = <0x0>; | |
| 2244 | + dma-coherent; | |
| 2189 | 2245 | }; |
| 2190 | 2246 | |
| 2191 | 2247 | sram@40000000 { |
| @@ -2469,6 +2525,11 @@ · 277 unmodified lines | ||
| 2469 | 2525 | * for 8x and 11.025x sample rate streams. |
| 2470 | 2526 | */ |
| 2471 | 2527 | assigned-clock-rates = <258000000>; |
| 2528 | + | |
| 2529 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, | |
| 2530 | + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; | |
| 2531 | + interconnect-names = "dma-mem", "write"; | |
| 2532 | + iommus = <&smmu TEGRA194_SID_APE>; | |
| 2472 | 2533 | }; |
| 2473 | 2534 | |
| 2474 | 2535 | tcu: tcu { |
| @@ -1063,7 +1063,7 @@ · 1062 unmodified lines | ||
| 1063 | 1063 | status = "okay"; |
| 1064 | 1064 | extcon = <&usb2_id>; |
| 1065 | 1065 | |
| 1066 | − usb@7600000 { | |
| 1066 | + dwc3@7600000 { | |
| 1067 | 1067 | extcon = <&usb2_id>; |
| 1068 | 1068 | dr_mode = "otg"; |
| 1069 | 1069 | maximum-speed = "high-speed"; |
| @@ -1074,7 +1074,7 @@ · 4 unmodified lines | ||
| 1074 | 1074 | status = "okay"; |
| 1075 | 1075 | extcon = <&usb3_id>; |
| 1076 | 1076 | |
| 1077 | − usb@6a00000 { | |
| 1077 | + dwc3@6a00000 { | |
| 1078 | 1078 | extcon = <&usb3_id>; |
| 1079 | 1079 | dr_mode = "otg"; |
| 1080 | 1080 | }; |
| @@ -443,7 +443,7 @@ · 442 unmodified lines | ||
| 443 | 443 | resets = <&gcc GCC_USB0_BCR>; |
| 444 | 444 | status = "disabled"; |
| 445 | 445 | |
| 446 | − dwc_0: usb@8a00000 { | |
| 446 | + dwc_0: dwc3@8a00000 { | |
| 447 | 447 | compatible = "snps,dwc3"; |
| 448 | 448 | reg = <0x8a00000 0xcd00>; |
| 449 | 449 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -484,7 +484,7 @@ · 34 unmodified lines | ||
| 484 | 484 | resets = <&gcc GCC_USB1_BCR>; |
| 485 | 485 | status = "disabled"; |
| 486 | 486 | |
| 487 | − dwc_1: usb@8c00000 { | |
| 487 | + dwc_1: dwc3@8c00000 { | |
| 488 | 488 | compatible = "snps,dwc3"; |
| 489 | 489 | reg = <0x8c00000 0xcd00>; |
| 490 | 490 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -1,6 +1,7 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* Copyright (c) 2015, LGE Inc. All rights reserved. |
| 3 | 3 | * Copyright (c) 2016, The Linux Foundation. All rights reserved. |
| 4 | + * Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com> | |
| 4 | 5 | */ |
| 5 | 6 | |
| 6 | 7 | /dts-v1/; |
| @@ -9,6 +10,9 @@ · 2 unmodified lines | ||
| 9 | 10 | #include "pm8994.dtsi" |
| 10 | 11 | #include "pmi8994.dtsi" |
| 11 | 12 | |
| 13 | +/* cont_splash_mem has different memory mapping */ | |
| 14 | +/delete-node/ &cont_splash_mem; | |
| 15 | + | |
| 12 | 16 | / { |
| 13 | 17 | model = "LG Nexus 5X"; |
| 14 | 18 | compatible = "lg,bullhead", "qcom,msm8992"; |
| @@ -17,6 +21,9 @@ · 2 unmodified lines | ||
| 17 | 21 | qcom,board-id = <0xb64 0>; |
| 18 | 22 | qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; |
| 19 | 23 | |
| 24 | + /* Bullhead firmware doesn't support PSCI */ | |
| 25 | + /delete-node/ psci; | |
| 26 | + | |
| 20 | 27 | aliases { |
| 21 | 28 | serial0 = &blsp1_uart2; |
| 22 | 29 | }; |
| @@ -38,6 +45,11 @@ · 15 unmodified lines | ||
| 38 | 45 | ftrace-size = <0x10000>; |
| 39 | 46 | pmsg-size = <0x20000>; |
| 40 | 47 | }; |
| 48 | + | |
| 49 | + cont_splash_mem: memory@3400000 { | |
| 50 | + reg = <0 0x03400000 0 0x1200000>; | |
| 51 | + no-map; | |
| 52 | + }; | |
| 41 | 53 | }; |
| 42 | 54 | }; |
| 43 | 55 | |
| @@ -1,12 +1,16 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | 2 | /* Copyright (c) 2015, Huawei Inc. All rights reserved. |
| 3 | 3 | * Copyright (c) 2016, The Linux Foundation. All rights reserved. |
| 4 | + * Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com> | |
| 4 | 5 | */ |
| 5 | 6 | |
| 6 | 7 | /dts-v1/; |
| 7 | 8 | |
| 8 | 9 | #include "msm8994.dtsi" |
| 9 | 10 | |
| 11 | +/* Angler's firmware does not report where the memory is allocated */ | |
| 12 | +/delete-node/ &cont_splash_mem; | |
| 13 | + | |
| 10 | 14 | / { |
| 11 | 15 | model = "Huawei Nexus 6P"; |
| 12 | 16 | compatible = "huawei,angler", "qcom,msm8994"; |
| @@ -2566,7 +2566,7 @@ · 2565 unmodified lines | ||
| 2566 | 2566 | power-domains = <&gcc USB30_GDSC>; |
| 2567 | 2567 | status = "disabled"; |
| 2568 | 2568 | |
| 2569 | − usb@6a00000 { | |
| 2569 | + dwc3@6a00000 { | |
| 2570 | 2570 | compatible = "snps,dwc3"; |
| 2571 | 2571 | reg = <0x06a00000 0xcc00>; |
| 2572 | 2572 | interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -2873,7 +2873,7 @@ · 300 unmodified lines | ||
| 2873 | 2873 | qcom,select-utmi-as-pipe-clk; |
| 2874 | 2874 | status = "disabled"; |
| 2875 | 2875 | |
| 2876 | − usb@7600000 { | |
| 2876 | + dwc3@7600000 { | |
| 2877 | 2877 | compatible = "snps,dwc3"; |
| 2878 | 2878 | reg = <0x07600000 0xcc00>; |
| 2879 | 2879 | interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -1964,7 +1964,7 @@ · 1963 unmodified lines | ||
| 1964 | 1964 | |
| 1965 | 1965 | resets = <&gcc GCC_USB_30_BCR>; |
| 1966 | 1966 | |
| 1967 | − usb3_dwc3: usb@a800000 { | |
| 1967 | + usb3_dwc3: dwc3@a800000 { | |
| 1968 | 1968 | compatible = "snps,dwc3"; |
| 1969 | 1969 | reg = <0x0a800000 0xcd00>; |
| 1970 | 1970 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -337,7 +337,7 @@ · 336 unmodified lines | ||
| 337 | 337 | &usb3 { |
| 338 | 338 | status = "okay"; |
| 339 | 339 | |
| 340 | − usb@7580000 { | |
| 340 | + dwc3@7580000 { | |
| 341 | 341 | dr_mode = "host"; |
| 342 | 342 | }; |
| 343 | 343 | }; |
| @@ -544,7 +544,7 @@ · 543 unmodified lines | ||
| 544 | 544 | assigned-clock-rates = <19200000>, <200000000>; |
| 545 | 545 | status = "disabled"; |
| 546 | 546 | |
| 547 | − usb@7580000 { | |
| 547 | + dwc3@7580000 { | |
| 548 | 548 | compatible = "snps,dwc3"; |
| 549 | 549 | reg = <0x07580000 0xcd00>; |
| 550 | 550 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -573,7 +573,7 @@ · 22 unmodified lines | ||
| 573 | 573 | assigned-clock-rates = <19200000>, <133333333>; |
| 574 | 574 | status = "disabled"; |
| 575 | 575 | |
| 576 | − usb@78c0000 { | |
| 576 | + dwc3@78c0000 { | |
| 577 | 577 | compatible = "snps,dwc3"; |
| 578 | 578 | reg = <0x078c0000 0xcc00>; |
| 579 | 579 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -2756,7 +2756,7 @@ · 2755 unmodified lines | ||
| 2756 | 2756 | <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; |
| 2757 | 2757 | interconnect-names = "usb-ddr", "apps-usb"; |
| 2758 | 2758 | |
| 2759 | − usb_1_dwc3: usb@a600000 { | |
| 2759 | + usb_1_dwc3: dwc3@a600000 { | |
| 2760 | 2760 | compatible = "snps,dwc3"; |
| 2761 | 2761 | reg = <0 0x0a600000 0 0xe000>; |
| 2762 | 2762 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -200,7 +200,7 @@ · 199 unmodified lines | ||
| 200 | 200 | &BIG_CPU_SLEEP_1 |
| 201 | 201 | &CLUSTER_SLEEP_0>; |
| 202 | 202 | next-level-cache = <&L2_700>; |
| 203 | − qcom,freq-domain = <&cpufreq_hw 1>; | |
| 203 | + qcom,freq-domain = <&cpufreq_hw 2>; | |
| 204 | 204 | #cooling-cells = <2>; |
| 205 | 205 | L2_700: l2-cache { |
| 206 | 206 | compatible = "cache"; |
| @@ -69,7 +69,7 @@ · 68 unmodified lines | ||
| 69 | 69 | }; |
| 70 | 70 | rmtfs_upper_guard: memory@f5d01000 { |
| 71 | 71 | no-map; |
| 72 | − reg = <0 0xf5d01000 0 0x2000>; | |
| 72 | + reg = <0 0xf5d01000 0 0x1000>; | |
| 73 | 73 | }; |
| 74 | 74 | |
| 75 | 75 | /* |
| @@ -78,7 +78,7 @@ · 2 unmodified lines | ||
| 78 | 78 | */ |
| 79 | 79 | removed_region: memory@88f00000 { |
| 80 | 80 | no-map; |
| 81 | − reg = <0 0x88f00000 0 0x200000>; | |
| 81 | + reg = <0 0x88f00000 0 0x1c00000>; | |
| 82 | 82 | }; |
| 83 | 83 | |
| 84 | 84 | ramoops: ramoops@ac300000 { |
| @@ -3781,7 +3781,7 @@ · 3780 unmodified lines | ||
| 3781 | 3781 | <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; |
| 3782 | 3782 | interconnect-names = "usb-ddr", "apps-usb"; |
| 3783 | 3783 | |
| 3784 | − usb_1_dwc3: usb@a600000 { | |
| 3784 | + usb_1_dwc3: dwc3@a600000 { | |
| 3785 | 3785 | compatible = "snps,dwc3"; |
| 3786 | 3786 | reg = <0 0x0a600000 0 0xcd00>; |
| 3787 | 3787 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -3829,7 +3829,7 @@ · 41 unmodified lines | ||
| 3829 | 3829 | <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; |
| 3830 | 3830 | interconnect-names = "usb-ddr", "apps-usb"; |
| 3831 | 3831 | |
| 3832 | − usb_2_dwc3: usb@a800000 { | |
| 3832 | + usb_2_dwc3: dwc3@a800000 { | |
| 3833 | 3833 | compatible = "snps,dwc3"; |
| 3834 | 3834 | reg = <0 0x0a800000 0 0xcd00>; |
| 3835 | 3835 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -700,7 +700,7 @@ · 699 unmodified lines | ||
| 700 | 700 | left_spkr: wsa8810-left{ |
| 701 | 701 | compatible = "sdw10217211000"; |
| 702 | 702 | reg = <0 3>; |
| 703 | − powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; | |
| 703 | + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; | |
| 704 | 704 | #thermal-sensor-cells = <0>; |
| 705 | 705 | sound-name-prefix = "SpkrLeft"; |
| 706 | 706 | #sound-dai-cells = <0>; |
| @@ -708,7 +708,7 @@ · 1 unmodified line | ||
| 708 | 708 | |
| 709 | 709 | right_spkr: wsa8810-right{ |
| 710 | 710 | compatible = "sdw10217211000"; |
| 711 | − powerdown-gpios = <&wcdgpio 3 GPIO_ACTIVE_HIGH>; | |
| 711 | + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; | |
| 712 | 712 | reg = <0 4>; |
| 713 | 713 | #thermal-sensor-cells = <0>; |
| 714 | 714 | sound-name-prefix = "SpkrRight"; |
| @@ -2344,7 +2344,7 @@ · 2343 unmodified lines | ||
| 2344 | 2344 | |
| 2345 | 2345 | resets = <&gcc GCC_USB30_PRIM_BCR>; |
| 2346 | 2346 | |
| 2347 | − usb_1_dwc3: usb@a600000 { | |
| 2347 | + usb_1_dwc3: dwc3@a600000 { | |
| 2348 | 2348 | compatible = "snps,dwc3"; |
| 2349 | 2349 | reg = <0 0x0a600000 0 0xcd00>; |
| 2350 | 2350 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -82,10 +82,10 @@ · 81 unmodified lines | ||
| 82 | 82 | <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; |
| 83 | 83 | interrupt-names = "eri", "rxi", "txi", |
| 84 | 84 | "bri", "dri", "tei"; |
| 85 | − clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>; | |
| 85 | + clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; | |
| 86 | 86 | clock-names = "fck"; |
| 87 | 87 | power-domains = <&cpg>; |
| 88 | − resets = <&cpg R9A07G044_CLK_SCIF0>; | |
| 88 | + resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; | |
| 89 | 89 | status = "disabled"; |
| 90 | 90 | }; |
| 91 | 91 | |
| @@ -47,7 +47,7 @@ · 46 unmodified lines | ||
| 47 | 47 | * cache before the transfer is done, causing old data to be seen by |
| 48 | 48 | * the CPU. |
| 49 | 49 | */ |
| 50 | −#define ARCH_DMA_MINALIGN L1_CACHE_BYTES | |
| 50 | +#define ARCH_DMA_MINALIGN (128) | |
| 51 | 51 | |
| 52 | 52 | #ifdef CONFIG_KASAN_SW_TAGS |
| 53 | 53 | #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) |
| @@ -33,8 +33,7 @@ · 32 unmodified lines | ||
| 33 | 33 | * EL2. |
| 34 | 34 | */ |
| 35 | 35 | .macro __init_el2_timers |
| 36 | − mrs x0, cnthctl_el2 | |
| 37 | − orr x0, x0, #3 // Enable EL1 physical timers | |
| 36 | + mov x0, #3 // Enable EL1 physical timers | |
| 38 | 37 | msr cnthctl_el2, x0 |
| 39 | 38 | msr cntvoff_el2, xzr // Clear virtual offset |
| 40 | 39 | .endm |
| @@ -320,7 +320,17 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) · 319 unmodified lines | ||
| 320 | 320 | |
| 321 | 321 | static inline unsigned long regs_return_value(struct pt_regs *regs) |
| 322 | 322 | { |
| 323 | − return regs->regs[0]; | |
| 323 | + unsigned long val = regs->regs[0]; | |
| 324 | + | |
| 325 | + /* | |
| 326 | + * Audit currently uses regs_return_value() instead of | |
| 327 | + * syscall_get_return_value(). Apply the same sign-extension here until | |
| 328 | + * audit is updated to use syscall_get_return_value(). | |
| 329 | + */ | |
| 330 | + if (compat_user_mode(regs)) | |
| 331 | + val = sign_extend64(val, 31); | |
| 332 | + | |
| 333 | + return val; | |
| 324 | 334 | } |
| 325 | 335 | |
| 326 | 336 | static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | |
| 11 | 11 | #include <linux/cpumask.h> |
| 12 | 12 | |
| 13 | +#include <asm/smp.h> | |
| 13 | 14 | #include <asm/types.h> |
| 14 | 15 | |
| 15 | 16 | struct mpidr_hash { |
| @@ -35,7 +35,7 @@ struct stack_info { · 34 unmodified lines | ||
| 35 | 35 | * accounting information necessary for robust unwinding. |
| 36 | 36 | * |
| 37 | 37 | * @fp: The fp value in the frame record (or the real fp) |
| 38 | − * @pc: The fp value in the frame record (or the real lr) | |
| 38 | + * @pc: The lr value in the frame record (or the real lr) | |
| 39 | 39 | * |
| 40 | 40 | * @stacks_done: Stacks which have been entirely unwound, for which it is no |
| 41 | 41 | * longer valid to unwind to. |
| @@ -29,22 +29,23 @@ static inline void syscall_rollback(struct task_struct *task, · 28 unmodified lines | ||
| 29 | 29 | regs->regs[0] = regs->orig_x0; |
| 30 | 30 | } |
| 31 | 31 | |
| 32 | − | |
| 33 | −static inline long syscall_get_error(struct task_struct *task, | |
| 34 | − struct pt_regs *regs) | |
| 32 | +static inline long syscall_get_return_value(struct task_struct *task, | |
| 33 | + struct pt_regs *regs) | |
| 35 | 34 | { |
| 36 | − unsigned long error = regs->regs[0]; | |
| 35 | + unsigned long val = regs->regs[0]; | |
| 37 | 36 | |
| 38 | 37 | if (is_compat_thread(task_thread_info(task))) |
| 39 | − error = sign_extend64(error, 31); | |
| 38 | + val = sign_extend64(val, 31); | |
| 40 | 39 | |
| 41 | − return IS_ERR_VALUE(error) ? error : 0; | |
| 40 | + return val; | |
| 42 | 41 | } |
| 43 | 42 | |
| 44 | −static inline long syscall_get_return_value(struct task_struct *task, | |
| 45 | − struct pt_regs *regs) | |
| 43 | +static inline long syscall_get_error(struct task_struct *task, | |
| 44 | + struct pt_regs *regs) | |
| 46 | 45 | { |
| 47 | − return regs->regs[0]; | |
| 46 | + unsigned long error = syscall_get_return_value(task, regs); | |
| 47 | + | |
| 48 | + return IS_ERR_VALUE(error) ? error : 0; | |
| 48 | 49 | } |
| 49 | 50 | |
| 50 | 51 | static inline void syscall_set_return_value(struct task_struct *task, |
| @@ -17,7 +17,7 @@ CFLAGS_syscall.o += -fno-stack-protector · 16 unmodified lines | ||
| 17 | 17 | # It's not safe to invoke KCOV when portions of the kernel environment aren't |
| 18 | 18 | # available or are out-of-sync with HW state. Since `noinstr` doesn't always |
| 19 | 19 | # inhibit KCOV instrumentation, disable it for the entire compilation unit. |
| 20 | −KCOV_INSTRUMENT_entry.o := n | |
| 20 | +KCOV_INSTRUMENT_entry-common.o := n | |
| 21 | 21 | KCOV_INSTRUMENT_idle.o := n |
| 22 | 22 | |
| 23 | 23 | # Object file lists. |
| @@ -81,6 +81,7 @@ · 80 unmodified lines | ||
| 81 | 81 | #include <asm/mmu_context.h> |
| 82 | 82 | #include <asm/mte.h> |
| 83 | 83 | #include <asm/processor.h> |
| 84 | +#include <asm/smp.h> | |
| 84 | 85 | #include <asm/sysreg.h> |
| 85 | 86 | #include <asm/traps.h> |
| 86 | 87 | #include <asm/virt.h> |
| @@ -604,7 +604,7 @@ asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs) · 603 unmodified lines | ||
| 604 | 604 | __el0_fiq_handler_common(regs); |
| 605 | 605 | } |
| 606 | 606 | |
| 607 | −static void __el0_error_handler_common(struct pt_regs *regs) | |
| 607 | +static void noinstr __el0_error_handler_common(struct pt_regs *regs) | |
| 608 | 608 | { |
| 609 | 609 | unsigned long esr = read_sysreg(esr_el1); |
| 610 | 610 | |
| @@ -162,7 +162,9 @@ u64 __init kaslr_early_init(void) · 161 unmodified lines | ||
| 162 | 162 | * a PAGE_SIZE multiple in the range [_etext - MODULES_VSIZE, |
| 163 | 163 | * _stext) . This guarantees that the resulting region still |
| 164 | 164 | * covers [_stext, _etext], and that all relative branches can |
| 165 | − * be resolved without veneers. | |
| 165 | + * be resolved without veneers unless this region is exhausted | |
| 166 | + * and we fall back to a larger 2GB window in module_alloc() | |
| 167 | + * when ARM64_MODULE_PLTS is enabled. | |
| 166 | 168 | */ |
| 167 | 169 | module_range = MODULES_VSIZE - (u64)(_etext - _stext); |
| 168 | 170 | module_alloc_base = (u64)_etext + offset - MODULES_VSIZE; |
| @@ -193,18 +193,6 @@ void mte_check_tfsr_el1(void) · 192 unmodified lines | ||
| 193 | 193 | } |
| 194 | 194 | #endif |
| 195 | 195 | |
| 196 | −static void update_gcr_el1_excl(u64 excl) | |
| 197 | −{ | |
| 198 | − | |
| 199 | − /* | |
| 200 | − * Note that the mask controlled by the user via prctl() is an | |
| 201 | − * include while GCR_EL1 accepts an exclude mask. | |
| 202 | − * No need for ISB since this only affects EL0 currently, implicit | |
| 203 | − * with ERET. | |
| 204 | − */ | |
| 205 | − sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); | |
| 206 | −} | |
| 207 | − | |
| 208 | 196 | static void set_gcr_el1_excl(u64 excl) |
| 209 | 197 | { |
| 210 | 198 | current->thread.gcr_user_excl = excl; |
| @@ -265,7 +253,8 @@ void mte_suspend_exit(void) · 54 unmodified lines | ||
| 265 | 253 | if (!system_supports_mte()) |
| 266 | 254 | return; |
| 267 | 255 | |
| 268 | − update_gcr_el1_excl(gcr_kernel_excl); | |
| 256 | + sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, gcr_kernel_excl); | |
| 257 | + isb(); | |
| 269 | 258 | } |
| 270 | 259 | |
| 271 | 260 | long set_mte_ctrl(struct task_struct *task, unsigned long arg) |
| @@ -1862,7 +1862,7 @@ void syscall_trace_exit(struct pt_regs *regs) · 1861 unmodified lines | ||
| 1862 | 1862 | audit_syscall_exit(regs); |
| 1863 | 1863 | |
| 1864 | 1864 | if (flags & _TIF_SYSCALL_TRACEPOINT) |
| 1865 | − trace_sys_exit(regs, regs_return_value(regs)); | |
| 1865 | + trace_sys_exit(regs, syscall_get_return_value(current, regs)); | |
| 1866 | 1866 | |
| 1867 | 1867 | if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) |
| 1868 | 1868 | tracehook_report_syscall(regs, PTRACE_SYSCALL_EXIT); |
| @@ -29,6 +29,7 @@ · 28 unmodified lines | ||
| 29 | 29 | #include <asm/unistd.h> |
| 30 | 30 | #include <asm/fpsimd.h> |
| 31 | 31 | #include <asm/ptrace.h> |
| 32 | +#include <asm/syscall.h> | |
| 32 | 33 | #include <asm/signal32.h> |
| 33 | 34 | #include <asm/traps.h> |
| 34 | 35 | #include <asm/vdso.h> |
| @@ -890,7 +891,7 @@ static void do_signal(struct pt_regs *regs) · 855 unmodified lines | ||
| 890 | 891 | retval == -ERESTART_RESTARTBLOCK || |
| 891 | 892 | (retval == -ERESTARTSYS && |
| 892 | 893 | !(ksig.ka.sa.sa_flags & SA_RESTART)))) { |
| 893 | − regs->regs[0] = -EINTR; | |
| 894 | + syscall_set_return_value(current, regs, -EINTR, 0); | |
| 894 | 895 | regs->pc = continue_addr; |
| 895 | 896 | } |
| 896 | 897 | |
| @@ -32,20 +32,23 @@ SYM_FUNC_END(__arm_smccc_sve_check) · 31 unmodified lines | ||
| 32 | 32 | EXPORT_SYMBOL(__arm_smccc_sve_check) |
| 33 | 33 | |
| 34 | 34 | .macro SMCCC instr |
| 35 | + stp x29, x30, [sp, #-16]! | |
| 36 | + mov x29, sp | |
| 35 | 37 | alternative_if ARM64_SVE |
| 36 | 38 | bl __arm_smccc_sve_check |
| 37 | 39 | alternative_else_nop_endif |
| 38 | 40 | \instr #0 |
| 39 | − ldr x4, [sp] | |
| 41 | + ldr x4, [sp, #16] | |
| 40 | 42 | stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS] |
| 41 | 43 | stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS] |
| 42 | − ldr x4, [sp, #8] | |
| 44 | + ldr x4, [sp, #24] | |
| 43 | 45 | cbz x4, 1f /* no quirk structure */ |
| 44 | 46 | ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS] |
| 45 | 47 | cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6 |
| 46 | 48 | b.ne 1f |
| 47 | 49 | str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS] |
| 48 | −1: ret | |
| 50 | +1: ldp x29, x30, [sp], #16 | |
| 51 | + ret | |
| 49 | 52 | .endm |
| 50 | 53 | |
| 51 | 54 | /* |
| @@ -218,7 +218,7 @@ void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl) · 217 unmodified lines | ||
| 218 | 218 | |
| 219 | 219 | #ifdef CONFIG_STACKTRACE |
| 220 | 220 | |
| 221 | −noinline void arch_stack_walk(stack_trace_consume_fn consume_entry, | |
| 221 | +noinline notrace void arch_stack_walk(stack_trace_consume_fn consume_entry, | |
| 222 | 222 | void *cookie, struct task_struct *task, |
| 223 | 223 | struct pt_regs *regs) |
| 224 | 224 | { |
| @@ -54,10 +54,7 @@ static void invoke_syscall(struct pt_regs *regs, unsigned int scno, · 53 unmodified lines | ||
| 54 | 54 | ret = do_ni_syscall(regs, scno); |
| 55 | 55 | } |
| 56 | 56 | |
| 57 | − if (is_compat_task()) | |
| 58 | − ret = lower_32_bits(ret); | |
| 59 | − | |
| 60 | − regs->regs[0] = ret; | |
| 57 | + syscall_set_return_value(current, regs, 0, ret); | |
| 61 | 58 | |
| 62 | 59 | /* |
| 63 | 60 | * Ultimately, this value will get limited by KSTACK_OFFSET_MAX(), |
| @@ -115,7 +112,7 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, · 51 unmodified lines | ||
| 115 | 112 | * syscall. do_notify_resume() will send a signal to userspace |
| 116 | 113 | * before the syscall is restarted. |
| 117 | 114 | */ |
| 118 | − regs->regs[0] = -ERESTARTNOINTR; | |
| 115 | + syscall_set_return_value(current, regs, -ERESTARTNOINTR, 0); | |
| 119 | 116 | return; |
| 120 | 117 | } |
| 121 | 118 | |
| @@ -136,7 +133,7 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, · 14 unmodified lines | ||
| 136 | 133 | * anyway. |
| 137 | 134 | */ |
| 138 | 135 | if (scno == NO_SYSCALL) |
| 139 | − regs->regs[0] = -ENOSYS; | |
| 136 | + syscall_set_return_value(current, regs, -ENOSYS, 0); | |
| 140 | 137 | scno = syscall_trace_enter(regs); |
| 141 | 138 | if (scno == NO_SYSCALL) |
| 142 | 139 | goto trace_exit; |
| @@ -94,10 +94,14 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, · 93 unmodified lines | ||
| 94 | 94 | kvm->arch.return_nisv_io_abort_to_user = true; |
| 95 | 95 | break; |
| 96 | 96 | case KVM_CAP_ARM_MTE: |
| 97 | − if (!system_supports_mte() || kvm->created_vcpus) | |
| 98 | − return -EINVAL; | |
| 99 | − r = 0; | |
| 100 | − kvm->arch.mte_enabled = true; | |
| 97 | + mutex_lock(&kvm->lock); | |
| 98 | + if (!system_supports_mte() || kvm->created_vcpus) { | |
| 99 | + r = -EINVAL; | |
| 100 | + } else { | |
| 101 | + r = 0; | |
| 102 | + kvm->arch.mte_enabled = true; | |
| 103 | + } | |
| 104 | + mutex_unlock(&kvm->lock); | |
| 101 | 105 | break; |
| 102 | 106 | default: |
| 103 | 107 | r = -EINVAL; |
| @@ -193,7 +193,7 @@ static bool range_is_memory(u64 start, u64 end) · 192 unmodified lines | ||
| 193 | 193 | { |
| 194 | 194 | struct kvm_mem_range r1, r2; |
| 195 | 195 | |
| 196 | − if (!find_mem_range(start, &r1) || !find_mem_range(end, &r2)) | |
| 196 | + if (!find_mem_range(start, &r1) || !find_mem_range(end - 1, &r2)) | |
| 197 | 197 | return false; |
| 198 | 198 | if (r1.start != r2.start) |
| 199 | 199 | return false; |
| @@ -947,7 +947,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, · 946 unmodified lines | ||
| 947 | 947 | vma_shift = get_vma_page_shift(vma, hva); |
| 948 | 948 | } |
| 949 | 949 | |
| 950 | − shared = (vma->vm_flags & VM_PFNMAP); | |
| 950 | + shared = (vma->vm_flags & VM_SHARED); | |
| 951 | 951 | |
| 952 | 952 | switch (vma_shift) { |
| 953 | 953 | #ifndef __PAGETABLE_PMD_FOLDED |
| @@ -29,7 +29,7 @@ · 28 unmodified lines | ||
| 29 | 29 | .endm |
| 30 | 30 | |
| 31 | 31 | .macro ldrh1 reg, ptr, val |
| 32 | − user_ldst 9998f, ldtrh, \reg, \ptr, \val | |
| 32 | + user_ldst 9997f, ldtrh, \reg, \ptr, \val | |
| 33 | 33 | .endm |
| 34 | 34 | |
| 35 | 35 | .macro strh1 reg, ptr, val |
| @@ -37,7 +37,7 @@ · 1 unmodified line | ||
| 37 | 37 | .endm |
| 38 | 38 | |
| 39 | 39 | .macro ldr1 reg, ptr, val |
| 40 | − user_ldst 9998f, ldtr, \reg, \ptr, \val | |
| 40 | + user_ldst 9997f, ldtr, \reg, \ptr, \val | |
| 41 | 41 | .endm |
| 42 | 42 | |
| 43 | 43 | .macro str1 reg, ptr, val |
| @@ -45,7 +45,7 @@ · 1 unmodified line | ||
| 45 | 45 | .endm |
| 46 | 46 | |
| 47 | 47 | .macro ldp1 reg1, reg2, ptr, val |
| 48 | − user_ldp 9998f, \reg1, \reg2, \ptr, \val | |
| 48 | + user_ldp 9997f, \reg1, \reg2, \ptr, \val | |
| 49 | 49 | .endm |
| 50 | 50 | |
| 51 | 51 | .macro stp1 reg1, reg2, ptr, val |
| @@ -53,8 +53,10 @@ · 1 unmodified line | ||
| 53 | 53 | .endm |
| 54 | 54 | |
| 55 | 55 | end .req x5 |
| 56 | +srcin .req x15 | |
| 56 | 57 | SYM_FUNC_START(__arch_copy_from_user) |
| 57 | 58 | add end, x0, x2 |
| 59 | + mov srcin, x1 | |
| 58 | 60 | #include "copy_template.S" |
| 59 | 61 | mov x0, #0 // Nothing to copy |
| 60 | 62 | ret |
| @@ -63,6 +65,11 @@ EXPORT_SYMBOL(__arch_copy_from_user) · 2 unmodified lines | ||
| 63 | 65 | |
| 64 | 66 | .section .fixup,"ax" |
| 65 | 67 | .align 2 |
| 68 | +9997: cmp dst, dstin | |
| 69 | + b.ne 9998f | |
| 70 | + // Before being absolutely sure we couldn't copy anything, try harder | |
| 71 | +USER(9998f, ldtrb tmp1w, [srcin]) | |
| 72 | + strb tmp1w, [dst], #1 | |
| 66 | 73 | 9998: sub x0, end, dst // bytes not copied |
| 67 | 74 | ret |
| 68 | 75 | .previous |
| @@ -30,33 +30,34 @@ · 29 unmodified lines | ||
| 30 | 30 | .endm |
| 31 | 31 | |
| 32 | 32 | .macro ldrh1 reg, ptr, val |
| 33 | − user_ldst 9998f, ldtrh, \reg, \ptr, \val | |
| 33 | + user_ldst 9997f, ldtrh, \reg, \ptr, \val | |
| 34 | 34 | .endm |
| 35 | 35 | |
| 36 | 36 | .macro strh1 reg, ptr, val |
| 37 | − user_ldst 9998f, sttrh, \reg, \ptr, \val | |
| 37 | + user_ldst 9997f, sttrh, \reg, \ptr, \val | |
| 38 | 38 | .endm |
| 39 | 39 | |
| 40 | 40 | .macro ldr1 reg, ptr, val |
| 41 | − user_ldst 9998f, ldtr, \reg, \ptr, \val | |
| 41 | + user_ldst 9997f, ldtr, \reg, \ptr, \val | |
| 42 | 42 | .endm |
| 43 | 43 | |
| 44 | 44 | .macro str1 reg, ptr, val |
| 45 | − user_ldst 9998f, sttr, \reg, \ptr, \val | |
| 45 | + user_ldst 9997f, sttr, \reg, \ptr, \val | |
| 46 | 46 | .endm |
| 47 | 47 | |
| 48 | 48 | .macro ldp1 reg1, reg2, ptr, val |
| 49 | − user_ldp 9998f, \reg1, \reg2, \ptr, \val | |
| 49 | + user_ldp 9997f, \reg1, \reg2, \ptr, \val | |
| 50 | 50 | .endm |
| 51 | 51 | |
| 52 | 52 | .macro stp1 reg1, reg2, ptr, val |
| 53 | − user_stp 9998f, \reg1, \reg2, \ptr, \val | |
| 53 | + user_stp 9997f, \reg1, \reg2, \ptr, \val | |
| 54 | 54 | .endm |
| 55 | 55 | |
| 56 | 56 | end .req x5 |
| 57 | − | |
| 57 | +srcin .req x15 | |
| 58 | 58 | SYM_FUNC_START(__arch_copy_in_user) |
| 59 | 59 | add end, x0, x2 |
| 60 | + mov srcin, x1 | |
| 60 | 61 | #include "copy_template.S" |
| 61 | 62 | mov x0, #0 |
| 62 | 63 | ret |
| @@ -65,6 +66,12 @@ EXPORT_SYMBOL(__arch_copy_in_user) · 2 unmodified lines | ||
| 65 | 66 | |
| 66 | 67 | .section .fixup,"ax" |
| 67 | 68 | .align 2 |
| 69 | +9997: cmp dst, dstin | |
| 70 | + b.ne 9998f | |
| 71 | + // Before being absolutely sure we couldn't copy anything, try harder | |
| 72 | +USER(9998f, ldtrb tmp1w, [srcin]) | |
| 73 | +USER(9998f, sttrb tmp1w, [dst]) | |
| 74 | + add dst, dst, #1 | |
| 68 | 75 | 9998: sub x0, end, dst // bytes not copied |
| 69 | 76 | ret |
| 70 | 77 | .previous |
| @@ -32,7 +32,7 @@ · 31 unmodified lines | ||
| 32 | 32 | .endm |
| 33 | 33 | |
| 34 | 34 | .macro strh1 reg, ptr, val |
| 35 | − user_ldst 9998f, sttrh, \reg, \ptr, \val | |
| 35 | + user_ldst 9997f, sttrh, \reg, \ptr, \val | |
| 36 | 36 | .endm |
| 37 | 37 | |
| 38 | 38 | .macro ldr1 reg, ptr, val |
| @@ -40,7 +40,7 @@ · 1 unmodified line | ||
| 40 | 40 | .endm |
| 41 | 41 | |
| 42 | 42 | .macro str1 reg, ptr, val |
| 43 | − user_ldst 9998f, sttr, \reg, \ptr, \val | |
| 43 | + user_ldst 9997f, sttr, \reg, \ptr, \val | |
| 44 | 44 | .endm |
| 45 | 45 | |
| 46 | 46 | .macro ldp1 reg1, reg2, ptr, val |
| @@ -48,12 +48,14 @@ · 1 unmodified line | ||
| 48 | 48 | .endm |
| 49 | 49 | |
| 50 | 50 | .macro stp1 reg1, reg2, ptr, val |
| 51 | − user_stp 9998f, \reg1, \reg2, \ptr, \val | |
| 51 | + user_stp 9997f, \reg1, \reg2, \ptr, \val | |
| 52 | 52 | .endm |
| 53 | 53 | |
| 54 | 54 | end .req x5 |
| 55 | +srcin .req x15 | |
| 55 | 56 | SYM_FUNC_START(__arch_copy_to_user) |
| 56 | 57 | add end, x0, x2 |
| 58 | + mov srcin, x1 | |
| 57 | 59 | #include "copy_template.S" |
| 58 | 60 | mov x0, #0 |
| 59 | 61 | ret |
| @@ -62,6 +64,12 @@ EXPORT_SYMBOL(__arch_copy_to_user) · 2 unmodified lines | ||
| 62 | 64 | |
| 63 | 65 | .section .fixup,"ax" |
| 64 | 66 | .align 2 |
| 67 | +9997: cmp dst, dstin | |
| 68 | + b.ne 9998f | |
| 69 | + // Before being absolutely sure we couldn't copy anything, try harder | |
| 70 | + ldrb tmp1w, [srcin] | |
| 71 | +USER(9998f, sttrb tmp1w, [dst]) | |
| 72 | + add dst, dst, #1 | |
| 65 | 73 | 9998: sub x0, end, dst // bytes not copied |
| 66 | 74 | ret |
| 67 | 75 | .previous |
| @@ -8,6 +8,7 @@ · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | #include <linux/linkage.h> |
| 10 | 10 | #include <asm/assembler.h> |
| 11 | +#include <asm/mte-def.h> | |
| 11 | 12 | |
| 12 | 13 | /* Assumptions: |
| 13 | 14 | * |
| @@ -42,7 +43,16 @@ · 28 unmodified lines | ||
| 42 | 43 | #define REP8_7f 0x7f7f7f7f7f7f7f7f |
| 43 | 44 | #define REP8_80 0x8080808080808080 |
| 44 | 45 | |
| 46 | +/* | |
| 47 | + * When KASAN_HW_TAGS is in use, memory is checked at MTE_GRANULE_SIZE | |
| 48 | + * (16-byte) granularity, and we must ensure that no access straddles this | |
| 49 | + * alignment boundary. | |
| 50 | + */ | |
| 51 | +#ifdef CONFIG_KASAN_HW_TAGS | |
| 52 | +#define MIN_PAGE_SIZE MTE_GRANULE_SIZE | |
| 53 | +#else | |
| 45 | 54 | #define MIN_PAGE_SIZE 4096 |
| 55 | +#endif | |
| 46 | 56 | |
| 47 | 57 | /* Since strings are short on average, we check the first 16 bytes |
| 48 | 58 | of the string for a NUL character. In order to do an unaligned ldp |
| @@ -1339,7 +1339,6 @@ void *__init fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot) · 1338 unmodified lines | ||
| 1339 | 1339 | return dt_virt; |
| 1340 | 1340 | } |
| 1341 | 1341 | |
| 1342 | −#if CONFIG_PGTABLE_LEVELS > 3 | |
| 1343 | 1342 | int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot) |
| 1344 | 1343 | { |
| 1345 | 1344 | pud_t new_pud = pfn_pud(__phys_to_pfn(phys), mk_pud_sect_prot(prot)); |
| @@ -1354,16 +1353,6 @@ int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot) · 8 unmodified lines | ||
| 1354 | 1353 | return 1; |
| 1355 | 1354 | } |
| 1356 | 1355 | |
| 1357 | −int pud_clear_huge(pud_t *pudp) | |
| 1358 | −{ | |
| 1359 | − if (!pud_sect(READ_ONCE(*pudp))) | |
| 1360 | − return 0; | |
| 1361 | − pud_clear(pudp); | |
| 1362 | − return 1; | |
| 1363 | −} | |
| 1364 | −#endif | |
| 1365 | − | |
| 1366 | −#if CONFIG_PGTABLE_LEVELS > 2 | |
| 1367 | 1356 | int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot) |
| 1368 | 1357 | { |
| 1369 | 1358 | pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), mk_pmd_sect_prot(prot)); |
| @@ -1378,6 +1367,14 @@ int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot) · 8 unmodified lines | ||
| 1378 | 1367 | return 1; |
| 1379 | 1368 | } |
| 1380 | 1369 | |
| 1370 | +int pud_clear_huge(pud_t *pudp) | |
| 1371 | +{ | |
| 1372 | + if (!pud_sect(READ_ONCE(*pudp))) | |
| 1373 | + return 0; | |
| 1374 | + pud_clear(pudp); | |
| 1375 | + return 1; | |
| 1376 | +} | |
| 1377 | + | |
| 1381 | 1378 | int pmd_clear_huge(pmd_t *pmdp) |
| 1382 | 1379 | { |
| 1383 | 1380 | if (!pmd_sect(READ_ONCE(*pmdp))) |
| @@ -1385,7 +1382,6 @@ int pmd_clear_huge(pmd_t *pmdp) · 1 unmodified line | ||
| 1385 | 1382 | pmd_clear(pmdp); |
| 1386 | 1383 | return 1; |
| 1387 | 1384 | } |
| 1388 | −#endif | |
| 1389 | 1385 | |
| 1390 | 1386 | int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr) |
| 1391 | 1387 | { |
| @@ -823,6 +823,19 @@ emit_cond_jmp: · 822 unmodified lines | ||
| 823 | 823 | return ret; |
| 824 | 824 | break; |
| 825 | 825 | |
| 826 | + /* speculation barrier */ | |
| 827 | + case BPF_ST | BPF_NOSPEC: | |
| 828 | + /* | |
| 829 | + * Nothing required here. | |
| 830 | + * | |
| 831 | + * In case of arm64, we rely on the firmware mitigation of | |
| 832 | + * Speculative Store Bypass as controlled via the ssbd kernel | |
| 833 | + * parameter. Whenever the mitigation is enabled, it works | |
| 834 | + * for all of the kernel code with no need to provide any | |
| 835 | + * additional instructions. | |
| 836 | + */ | |
| 837 | + break; | |
| 838 | + | |
| 826 | 839 | /* ST: *(size *)(dst + off) = imm */ |
| 827 | 840 | case BPF_ST | BPF_MEM | BPF_W: |
| 828 | 841 | case BPF_ST | BPF_MEM | BPF_H: |
| @@ -44,7 +44,6 @@ config H8300_H8MAX · 43 unmodified lines | ||
| 44 | 44 | bool "H8MAX" |
| 45 | 45 | select H83069 |
| 46 | 46 | select RAMKERNEL |
| 47 | − select HAVE_IDE | |
| 48 | 47 | help |
| 49 | 48 | H8MAX Evaluation Board Support |
| 50 | 49 | More Information. (Japanese Only) |
| @@ -25,7 +25,6 @@ config IA64 · 24 unmodified lines | ||
| 25 | 25 | select HAVE_ASM_MODVERSIONS |
| 26 | 26 | select HAVE_UNSTABLE_SCHED_CLOCK |
| 27 | 27 | select HAVE_EXIT_THREAD |
| 28 | − select HAVE_IDE | |
| 29 | 28 | select HAVE_KPROBES |
| 30 | 29 | select HAVE_KRETPROBES |
| 31 | 30 | select HAVE_FTRACE_MCOUNT_RECORD |
| @@ -23,7 +23,6 @@ config M68K · 22 unmodified lines | ||
| 23 | 23 | select HAVE_DEBUG_BUGVERBOSE |
| 24 | 24 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED |
| 25 | 25 | select HAVE_FUTEX_CMPXCHG if MMU && FUTEX |
| 26 | − select HAVE_IDE | |
| 27 | 26 | select HAVE_MOD_ARCH_SPECIFIC |
| 28 | 27 | select HAVE_UID16 |
| 29 | 28 | select MMU_GATHER_NO_RANGE if MMU |
| @@ -33,6 +33,7 @@ config MAC · 32 unmodified lines | ||
| 33 | 33 | depends on MMU |
| 34 | 34 | select MMU_MOTOROLA if MMU |
| 35 | 35 | select HAVE_ARCH_NVRAM_OPS |
| 36 | + select HAVE_PATA_PLATFORM | |
| 36 | 37 | select LEGACY_TIMER_TICK |
| 37 | 38 | help |
| 38 | 39 | This option enables support for the Apple Macintosh series of |
| @@ -26,7 +26,7 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); · 25 unmodified lines | ||
| 26 | 26 | DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); |
| 27 | 27 | |
| 28 | 28 | static struct clk_lookup m525x_clk_lookup[] = { |
| 29 | − CLKDEV_INIT(NULL, "pll.0", &pll), | |
| 29 | + CLKDEV_INIT(NULL, "pll.0", &clk_pll), | |
| 30 | 30 | CLKDEV_INIT(NULL, "sys.0", &clk_sys), |
| 31 | 31 | CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), |
| 32 | 32 | CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), |
| @@ -71,7 +71,6 @@ config MIPS · 70 unmodified lines | ||
| 71 | 71 | select HAVE_FUNCTION_TRACER |
| 72 | 72 | select HAVE_GCC_PLUGINS |
| 73 | 73 | select HAVE_GENERIC_VDSO |
| 74 | − select HAVE_IDE | |
| 75 | 74 | select HAVE_IOREMAP_PROT |
| 76 | 75 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
| 77 | 76 | select HAVE_IRQ_TIME_ACCOUNTING |
| @@ -321,7 +321,7 @@ KBUILD_LDFLAGS += -m $(ld-emul) · 320 unmodified lines | ||
| 321 | 321 | |
| 322 | 322 | ifdef CONFIG_MIPS |
| 323 | 323 | CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \ |
| 324 | − egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \ | |
| 324 | + egrep -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \ | |
| 325 | 325 | sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/" -e 's/\$$/&&/g') |
| 326 | 326 | endif |
| 327 | 327 | |
| @@ -76,7 +76,7 @@ static inline int __enable_fpu(enum fpu_mode mode) · 75 unmodified lines | ||
| 76 | 76 | /* we only have a 32-bit FPU */ |
| 77 | 77 | return SIGFPE; |
| 78 | 78 | #endif |
| 79 | − fallthrough; | |
| 79 | + /* fallthrough */ | |
| 80 | 80 | case FPU_32BIT: |
| 81 | 81 | if (cpu_has_fre) { |
| 82 | 82 | /* clear FRE */ |
| @@ -58,15 +58,20 @@ do { \ · 57 unmodified lines | ||
| 58 | 58 | |
| 59 | 59 | static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) |
| 60 | 60 | { |
| 61 | − pmd_t *pmd = NULL; | |
| 61 | + pmd_t *pmd; | |
| 62 | 62 | struct page *pg; |
| 63 | 63 | |
| 64 | − pg = alloc_pages(GFP_KERNEL | __GFP_ACCOUNT, PMD_ORDER); | |
| 65 | − if (pg) { | |
| 66 | − pgtable_pmd_page_ctor(pg); | |
| 67 | − pmd = (pmd_t *)page_address(pg); | |
| 68 | − pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table); | |
| 64 | + pg = alloc_pages(GFP_KERNEL_ACCOUNT, PMD_ORDER); | |
| 65 | + if (!pg) | |
| 66 | + return NULL; | |
| 67 | + | |
| 68 | + if (!pgtable_pmd_page_ctor(pg)) { | |
| 69 | + __free_pages(pg, PMD_ORDER); | |
| 70 | + return NULL; | |
| 69 | 71 | } |
| 72 | + | |
| 73 | + pmd = (pmd_t *)page_address(pg); | |
| 74 | + pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table); | |
| 70 | 75 | return pmd; |
| 71 | 76 | } |
| 72 | 77 | |
| @@ -1383,6 +1383,7 @@ static void build_r4000_tlb_refill_handler(void) · 1382 unmodified lines | ||
| 1383 | 1383 | switch (boot_cpu_type()) { |
| 1384 | 1384 | default: |
| 1385 | 1385 | if (sizeof(long) == 4) { |
| 1386 | + fallthrough; | |
| 1386 | 1387 | case CPU_LOONGSON2EF: |
| 1387 | 1388 | /* Loongson2 ebase is different than r4k, we have more space */ |
| 1388 | 1389 | if ((p - tlb_handler) > 64) |
| @@ -2169,6 +2170,7 @@ static void build_r4000_tlb_load_handler(void) · 780 unmodified lines | ||
| 2169 | 2170 | default: |
| 2170 | 2171 | if (cpu_has_mips_r2_exec_hazard) { |
| 2171 | 2172 | uasm_i_ehb(&p); |
| 2173 | + fallthrough; | |
| 2172 | 2174 | |
| 2173 | 2175 | case CPU_CAVIUM_OCTEON: |
| 2174 | 2176 | case CPU_CAVIUM_OCTEON_PLUS: |
| @@ -48,7 +48,8 @@ static struct plat_serial8250_port uart8250_data[] = { · 47 unmodified lines | ||
| 48 | 48 | .mapbase = 0x1f000900, /* The CBUS UART */ |
| 49 | 49 | .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, |
| 50 | 50 | .uartclk = 3686400, /* Twice the usual clk! */ |
| 51 | − .iotype = UPIO_MEM32, | |
| 51 | + .iotype = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) ? | |
| 52 | + UPIO_MEM32BE : UPIO_MEM32, | |
| 52 | 53 | .flags = CBUS_UART_FLAGS, |
| 53 | 54 | .regshift = 3, |
| 54 | 55 | }, |
| @@ -1355,6 +1355,9 @@ jeq_common: · 1354 unmodified lines | ||
| 1355 | 1355 | } |
| 1356 | 1356 | break; |
| 1357 | 1357 | |
| 1358 | + case BPF_ST | BPF_NOSPEC: /* speculation barrier */ | |
| 1359 | + break; | |
| 1360 | + | |
| 1358 | 1361 | case BPF_ST | BPF_B | BPF_MEM: |
| 1359 | 1362 | case BPF_ST | BPF_H | BPF_MEM: |
| 1360 | 1363 | case BPF_ST | BPF_W | BPF_MEM: |
| @@ -59,7 +59,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, · 58 unmodified lines | ||
| 59 | 59 | |
| 60 | 60 | vma = find_vma(mm, addr); |
| 61 | 61 | if (TASK_SIZE - len >= addr && |
| 62 | − (!vma || addr + len <= vma->vm_start)) | |
| 62 | + (!vma || addr + len <= vm_start_gap(vma))) | |
| 63 | 63 | return addr; |
| 64 | 64 | } |
| 65 | 65 | |
| @@ -3,7 +3,6 @@ config PARISC · 2 unmodified lines | ||
| 3 | 3 | def_bool y |
| 4 | 4 | select ARCH_32BIT_OFF_T if !64BIT |
| 5 | 5 | select ARCH_MIGHT_HAVE_PC_PARPORT |
| 6 | − select HAVE_IDE | |
| 7 | 6 | select HAVE_FUNCTION_TRACER |
| 8 | 7 | select HAVE_FUNCTION_GRAPH_TRACER |
| 9 | 8 | select HAVE_SYSCALL_TRACEPOINTS |
| @@ -220,7 +220,6 @@ config PPC · 219 unmodified lines | ||
| 220 | 220 | select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC_BOOK3S_64 && SMP |
| 221 | 221 | select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI && !HAVE_HARDLOCKUP_DETECTOR_ARCH |
| 222 | 222 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (PPC_BOOK3S || PPC_8xx) |
| 223 | − select HAVE_IDE | |
| 224 | 223 | select HAVE_IOREMAP_PROT |
| 225 | 224 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
| 226 | 225 | select HAVE_IRQ_TIME_ACCOUNTING |
| @@ -4,6 +4,8 @@ · 3 unmodified lines | ||
| 4 | 4 | |
| 5 | 5 | #include <asm/bug.h> |
| 6 | 6 | #include <asm/book3s/32/mmu-hash.h> |
| 7 | +#include <asm/mmu.h> | |
| 8 | +#include <asm/synch.h> | |
| 7 | 9 | |
| 8 | 10 | #ifndef __ASSEMBLY__ |
| 9 | 11 | |
| @@ -28,6 +30,15 @@ static inline void kuep_lock(void) · 18 unmodified lines | ||
| 28 | 30 | return; |
| 29 | 31 | |
| 30 | 32 | update_user_segments(mfsr(0) | SR_NX); |
| 33 | + /* | |
| 34 | + * This isync() shouldn't be necessary as the kernel is not excepted to | |
| 35 | + * run any instruction in userspace soon after the update of segments, | |
| 36 | + * but hash based cores (at least G3) seem to exhibit a random | |
| 37 | + * behaviour when the 'isync' is not there. 603 cores don't have this | |
| 38 | + * behaviour so don't do the 'isync' as it saves several CPU cycles. | |
| 39 | + */ | |
| 40 | + if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) | |
| 41 | + isync(); /* Context sync required after mtsr() */ | |
| 31 | 42 | } |
| 32 | 43 | |
| 33 | 44 | static inline void kuep_unlock(void) |
| @@ -36,6 +47,15 @@ static inline void kuep_unlock(void) · 2 unmodified lines | ||
| 36 | 47 | return; |
| 37 | 48 | |
| 38 | 49 | update_user_segments(mfsr(0) & ~SR_NX); |
| 50 | + /* | |
| 51 | + * This isync() shouldn't be necessary as a 'rfi' will soon be executed | |
| 52 | + * to return to userspace, but hash based cores (at least G3) seem to | |
| 53 | + * exhibit a random behaviour when the 'isync' is not there. 603 cores | |
| 54 | + * don't have this behaviour so don't do the 'isync' as it saves several | |
| 55 | + * CPU cycles. | |
| 56 | + */ | |
| 57 | + if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) | |
| 58 | + isync(); /* Context sync required after mtsr() */ | |
| 39 | 59 | } |
| 40 | 60 | |
| 41 | 61 | #ifdef CONFIG_PPC_KUAP |
| @@ -583,6 +583,9 @@ DECLARE_INTERRUPT_HANDLER_NMI(hmi_exception_realmode); · 582 unmodified lines | ||
| 583 | 583 | |
| 584 | 584 | DECLARE_INTERRUPT_HANDLER_ASYNC(TAUException); |
| 585 | 585 | |
| 586 | +/* irq.c */ | |
| 587 | +DECLARE_INTERRUPT_HANDLER_ASYNC(do_IRQ); | |
| 588 | + | |
| 586 | 589 | void __noreturn unrecoverable_exception(struct pt_regs *regs); |
| 587 | 590 | |
| 588 | 591 | void replay_system_reset(void); |
| @@ -52,7 +52,7 @@ extern void *mcheckirq_ctx[NR_CPUS]; · 51 unmodified lines | ||
| 52 | 52 | extern void *hardirq_ctx[NR_CPUS]; |
| 53 | 53 | extern void *softirq_ctx[NR_CPUS]; |
| 54 | 54 | |
| 55 | −extern void do_IRQ(struct pt_regs *regs); | |
| 55 | +void __do_IRQ(struct pt_regs *regs); | |
| 56 | 56 | extern void __init init_IRQ(void); |
| 57 | 57 | extern void __do_irq(struct pt_regs *regs); |
| 58 | 58 | |
| @@ -70,6 +70,22 @@ struct pt_regs · 69 unmodified lines | ||
| 70 | 70 | unsigned long __pad[4]; /* Maintain 16 byte interrupt stack alignment */ |
| 71 | 71 | }; |
| 72 | 72 | #endif |
| 73 | +#if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE) | |
| 74 | + struct { /* Must be a multiple of 16 bytes */ | |
| 75 | + unsigned long mas0; | |
| 76 | + unsigned long mas1; | |
| 77 | + unsigned long mas2; | |
| 78 | + unsigned long mas3; | |
| 79 | + unsigned long mas6; | |
| 80 | + unsigned long mas7; | |
| 81 | + unsigned long srr0; | |
| 82 | + unsigned long srr1; | |
| 83 | + unsigned long csrr0; | |
| 84 | + unsigned long csrr1; | |
| 85 | + unsigned long dsrr0; | |
| 86 | + unsigned long dsrr1; | |
| 87 | + }; | |
| 88 | +#endif | |
| 73 | 89 | }; |
| 74 | 90 | #endif |
| 75 | 91 | |
| @@ -309,24 +309,21 @@ int main(void) · 308 unmodified lines | ||
| 309 | 309 | STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr); |
| 310 | 310 | #endif |
| 311 | 311 | |
| 312 | −#if defined(CONFIG_PPC32) | |
| 313 | −#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) | |
| 314 | − DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE); | |
| 315 | − DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); | |
| 312 | +#if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE) | |
| 313 | + STACK_PT_REGS_OFFSET(MAS0, mas0); | |
| 316 | 314 | /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */ |
| 317 | − DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); | |
| 318 | − DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1)); | |
| 319 | − DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2)); | |
| 320 | − DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3)); | |
| 321 | − DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6)); | |
| 322 | − DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7)); | |
| 323 | − DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0)); | |
| 324 | − DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1)); | |
| 325 | − DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0)); | |
| 326 | − DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1)); | |
| 327 | − DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0)); | |
| 328 | − DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1)); | |
| 329 | −#endif | |
| 315 | + STACK_PT_REGS_OFFSET(MMUCR, mas0); | |
| 316 | + STACK_PT_REGS_OFFSET(MAS1, mas1); | |
| 317 | + STACK_PT_REGS_OFFSET(MAS2, mas2); | |
| 318 | + STACK_PT_REGS_OFFSET(MAS3, mas3); | |
| 319 | + STACK_PT_REGS_OFFSET(MAS6, mas6); | |
| 320 | + STACK_PT_REGS_OFFSET(MAS7, mas7); | |
| 321 | + STACK_PT_REGS_OFFSET(_SRR0, srr0); | |
| 322 | + STACK_PT_REGS_OFFSET(_SRR1, srr1); | |
| 323 | + STACK_PT_REGS_OFFSET(_CSRR0, csrr0); | |
| 324 | + STACK_PT_REGS_OFFSET(_CSRR1, csrr1); | |
| 325 | + STACK_PT_REGS_OFFSET(_DSRR0, dsrr0); | |
| 326 | + STACK_PT_REGS_OFFSET(_DSRR1, dsrr1); | |
| 330 | 327 | #endif |
| 331 | 328 | |
| 332 | 329 | /* About the CPU features table */ |
| @@ -300,7 +300,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE) · 299 unmodified lines | ||
| 300 | 300 | EXCEPTION_PROLOG_1 |
| 301 | 301 | EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataAccess handle_dar_dsisr=1 |
| 302 | 302 | prepare_transfer_to_handler |
| 303 | − lwz r5, _DSISR(r11) | |
| 303 | + lwz r5, _DSISR(r1) | |
| 304 | 304 | andis. r0, r5, DSISR_DABRMATCH@h |
| 305 | 305 | bne- 1f |
| 306 | 306 | bl do_page_fault |
| @@ -168,20 +168,18 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) · 167 unmodified lines | ||
| 168 | 168 | /* only on e500mc */ |
| 169 | 169 | #define DBG_STACK_BASE dbgirq_ctx |
| 170 | 170 | |
| 171 | −#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) | |
| 172 | − | |
| 173 | 171 | #ifdef CONFIG_SMP |
| 174 | 172 | #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ |
| 175 | 173 | mfspr r8,SPRN_PIR; \ |
| 176 | 174 | slwi r8,r8,2; \ |
| 177 | 175 | addis r8,r8,level##_STACK_BASE@ha; \ |
| 178 | 176 | lwz r8,level##_STACK_BASE@l(r8); \ |
| 179 | − addi r8,r8,EXC_LVL_FRAME_OVERHEAD; | |
| 177 | + addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE; | |
| 180 | 178 | #else |
| 181 | 179 | #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ |
| 182 | 180 | lis r8,level##_STACK_BASE@ha; \ |
| 183 | 181 | lwz r8,level##_STACK_BASE@l(r8); \ |
| 184 | − addi r8,r8,EXC_LVL_FRAME_OVERHEAD; | |
| 182 | + addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE; | |
| 185 | 183 | #endif |
| 186 | 184 | |
| 187 | 185 | /* |
| @@ -208,7 +206,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) · 20 unmodified lines | ||
| 208 | 206 | mtmsr r11; \ |
| 209 | 207 | mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ |
| 210 | 208 | lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\ |
| 211 | − addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ | |
| 209 | + addi r11,r11,THREAD_SIZE - INT_FRAME_SIZE; /* allocate stack frame */\ | |
| 212 | 210 | beq 1f; \ |
| 213 | 211 | /* COMING FROM USER MODE */ \ |
| 214 | 212 | stw r9,_CCR(r11); /* save CR */\ |
| @@ -516,24 +514,5 @@ label: · 301 unmodified lines | ||
| 516 | 514 | bl kernel_fp_unavailable_exception; \ |
| 517 | 515 | b interrupt_return |
| 518 | 516 | |
| 519 | −#else /* __ASSEMBLY__ */ | |
| 520 | −struct exception_regs { | |
| 521 | − unsigned long mas0; | |
| 522 | − unsigned long mas1; | |
| 523 | − unsigned long mas2; | |
| 524 | − unsigned long mas3; | |
| 525 | − unsigned long mas6; | |
| 526 | − unsigned long mas7; | |
| 527 | − unsigned long srr0; | |
| 528 | − unsigned long srr1; | |
| 529 | − unsigned long csrr0; | |
| 530 | − unsigned long csrr1; | |
| 531 | − unsigned long dsrr0; | |
| 532 | − unsigned long dsrr1; | |
| 533 | −}; | |
| 534 | − | |
| 535 | −/* ensure this structure is always sized to a multiple of the stack alignment */ | |
| 536 | −#define STACK_EXC_LVL_FRAME_SIZE ALIGN(sizeof (struct exception_regs), 16) | |
| 537 | − | |
| 538 | 517 | #endif /* __ASSEMBLY__ */ |
| 539 | 518 | #endif /* __HEAD_BOOKE_H__ */ |
| @@ -750,7 +750,7 @@ void __do_irq(struct pt_regs *regs) · 749 unmodified lines | ||
| 750 | 750 | trace_irq_exit(regs); |
| 751 | 751 | } |
| 752 | 752 | |
| 753 | −DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ) | |
| 753 | +void __do_IRQ(struct pt_regs *regs) | |
| 754 | 754 | { |
| 755 | 755 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 756 | 756 | void *cursp, *irqsp, *sirqsp; |
| @@ -774,6 +774,11 @@ DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ) · 17 unmodified lines | ||
| 774 | 774 | set_irq_regs(old_regs); |
| 775 | 775 | } |
| 776 | 776 | |
| 777 | +DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ) | |
| 778 | +{ | |
| 779 | + __do_IRQ(regs); | |
| 780 | +} | |
| 781 | + | |
| 777 | 782 | static void *__init alloc_vm_stack(void) |
| 778 | 783 | { |
| 779 | 784 | return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP, |
| @@ -292,7 +292,8 @@ int kprobe_handler(struct pt_regs *regs) · 291 unmodified lines | ||
| 292 | 292 | if (user_mode(regs)) |
| 293 | 293 | return 0; |
| 294 | 294 | |
| 295 | − if (!(regs->msr & MSR_IR) || !(regs->msr & MSR_DR)) | |
| 295 | + if (!IS_ENABLED(CONFIG_BOOKE) && | |
| 296 | + (!(regs->msr & MSR_IR) || !(regs->msr & MSR_DR))) | |
| 296 | 297 | return 0; |
| 297 | 298 | |
| 298 | 299 | /* |
| @@ -1167,7 +1167,7 @@ static int __init topology_init(void) · 1166 unmodified lines | ||
| 1167 | 1167 | * CPU. For instance, the boot cpu might never be valid |
| 1168 | 1168 | * for hotplugging. |
| 1169 | 1169 | */ |
| 1170 | − if (smp_ops->cpu_offline_self) | |
| 1170 | + if (smp_ops && smp_ops->cpu_offline_self) | |
| 1171 | 1171 | c->hotpluggable = 1; |
| 1172 | 1172 | #endif |
| 1173 | 1173 | |
| @@ -586,7 +586,7 @@ DEFINE_INTERRUPT_HANDLER_ASYNC(timer_interrupt) · 585 unmodified lines | ||
| 586 | 586 | |
| 587 | 587 | #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_PMAC) |
| 588 | 588 | if (atomic_read(&ppc_n_lost_interrupts) != 0) |
| 589 | − do_IRQ(regs); | |
| 589 | + __do_IRQ(regs); | |
| 590 | 590 | #endif |
| 591 | 591 | |
| 592 | 592 | old_regs = set_irq_regs(regs); |
| @@ -1104,7 +1104,7 @@ DEFINE_INTERRUPT_HANDLER(RunModeException) · 1103 unmodified lines | ||
| 1104 | 1104 | _exception(SIGTRAP, regs, TRAP_UNK, 0); |
| 1105 | 1105 | } |
| 1106 | 1106 | |
| 1107 | −DEFINE_INTERRUPT_HANDLER(single_step_exception) | |
| 1107 | +static void __single_step_exception(struct pt_regs *regs) | |
| 1108 | 1108 | { |
| 1109 | 1109 | clear_single_step(regs); |
| 1110 | 1110 | clear_br_trace(regs); |
| @@ -1121,6 +1121,11 @@ DEFINE_INTERRUPT_HANDLER(single_step_exception) · 10 unmodified lines | ||
| 1121 | 1121 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |
| 1122 | 1122 | } |
| 1123 | 1123 | |
| 1124 | +DEFINE_INTERRUPT_HANDLER(single_step_exception) | |
| 1125 | +{ | |
| 1126 | + __single_step_exception(regs); | |
| 1127 | +} | |
| 1128 | + | |
| 1124 | 1129 | /* |
| 1125 | 1130 | * After we have successfully emulated an instruction, we have to |
| 1126 | 1131 | * check if the instruction was being single-stepped, and if so, |
| @@ -1130,7 +1135,7 @@ DEFINE_INTERRUPT_HANDLER(single_step_exception) · 3 unmodified lines | ||
| 1130 | 1135 | static void emulate_single_step(struct pt_regs *regs) |
| 1131 | 1136 | { |
| 1132 | 1137 | if (single_stepping(regs)) |
| 1133 | − single_step_exception(regs); | |
| 1138 | + __single_step_exception(regs); | |
| 1134 | 1139 | } |
| 1135 | 1140 | |
| 1136 | 1141 | static inline int __parse_fpscr(unsigned long fpscr) |
| @@ -27,6 +27,13 @@ KASAN_SANITIZE := n · 26 unmodified lines | ||
| 27 | 27 | |
| 28 | 28 | ccflags-y := -shared -fno-common -fno-builtin -nostdlib \ |
| 29 | 29 | -Wl,-soname=linux-vdso64.so.1 -Wl,--hash-style=both |
| 30 | + | |
| 31 | +# Go prior to 1.16.x assumes r30 is not clobbered by any VDSO code. That used to be true | |
| 32 | +# by accident when the VDSO was hand-written asm code, but may not be now that the VDSO is | |
| 33 | +# compiler generated. To avoid breaking Go tell GCC not to use r30. Impact on code | |
| 34 | +# generation is minimal, it will just use r29 instead. | |
| 35 | +ccflags-y += $(call cc-option, -ffixed-r30) | |
| 36 | + | |
| 30 | 37 | asflags-y := -D__VDSO64__ -s |
| 31 | 38 | |
| 32 | 39 | targets += vdso64.lds |
| @@ -2697,8 +2697,10 @@ static int kvmppc_core_vcpu_create_hv(struct kvm_vcpu *vcpu) · 2696 unmodified lines | ||
| 2697 | 2697 | HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP | HFSCR_PREFIX; |
| 2698 | 2698 | if (cpu_has_feature(CPU_FTR_HVMODE)) { |
| 2699 | 2699 | vcpu->arch.hfscr &= mfspr(SPRN_HFSCR); |
| 2700 | +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
| 2700 | 2701 | if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) |
| 2701 | 2702 | vcpu->arch.hfscr |= HFSCR_TM; |
| 2703 | +#endif | |
| 2702 | 2704 | } |
| 2703 | 2705 | if (cpu_has_feature(CPU_FTR_TM_COMP)) |
| 2704 | 2706 | vcpu->arch.hfscr |= HFSCR_TM; |
| @@ -302,6 +302,9 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu) · 301 unmodified lines | ||
| 302 | 302 | if (vcpu->kvm->arch.l1_ptcr == 0) |
| 303 | 303 | return H_NOT_AVAILABLE; |
| 304 | 304 | |
| 305 | + if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr)) | |
| 306 | + return H_BAD_MODE; | |
| 307 | + | |
| 305 | 308 | /* copy parameters in */ |
| 306 | 309 | hv_ptr = kvmppc_get_gpr(vcpu, 4); |
| 307 | 310 | regs_ptr = kvmppc_get_gpr(vcpu, 5); |
| @@ -322,6 +325,23 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu) · 14 unmodified lines | ||
| 322 | 325 | if (l2_hv.vcpu_token >= NR_CPUS) |
| 323 | 326 | return H_PARAMETER; |
| 324 | 327 | |
| 328 | + /* | |
| 329 | + * L1 must have set up a suspended state to enter the L2 in a | |
| 330 | + * transactional state, and only in that case. These have to be | |
| 331 | + * filtered out here to prevent causing a TM Bad Thing in the | |
| 332 | + * host HRFID. We could synthesize a TM Bad Thing back to the L1 | |
| 333 | + * here but there doesn't seem like much point. | |
| 334 | + */ | |
| 335 | + if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr)) { | |
| 336 | + if (!MSR_TM_ACTIVE(l2_regs.msr)) | |
| 337 | + return H_BAD_MODE; | |
| 338 | + } else { | |
| 339 | + if (l2_regs.msr & MSR_TS_MASK) | |
| 340 | + return H_BAD_MODE; | |
| 341 | + if (WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_TS_MASK)) | |
| 342 | + return H_BAD_MODE; | |
| 343 | + } | |
| 344 | + | |
| 325 | 345 | /* translate lpid */ |
| 326 | 346 | l2 = kvmhv_get_nested(vcpu->kvm, l2_hv.lpid, true); |
| 327 | 347 | if (!l2) |
| @@ -317,6 +317,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc · 316 unmodified lines | ||
| 317 | 317 | */ |
| 318 | 318 | mtspr(SPRN_HDEC, hdec); |
| 319 | 319 | |
| 320 | +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
| 321 | +tm_return_to_guest: | |
| 322 | +#endif | |
| 320 | 323 | mtspr(SPRN_DAR, vcpu->arch.shregs.dar); |
| 321 | 324 | mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr); |
| 322 | 325 | mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0); |
| @@ -415,11 +418,23 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc · 92 unmodified lines | ||
| 415 | 418 | * is in real suspend mode and is trying to transition to |
| 416 | 419 | * transactional mode. |
| 417 | 420 | */ |
| 418 | − if (local_paca->kvm_hstate.fake_suspend && | |
| 421 | + if (!local_paca->kvm_hstate.fake_suspend && | |
| 419 | 422 | (vcpu->arch.shregs.msr & MSR_TS_S)) { |
| 420 | 423 | if (kvmhv_p9_tm_emulation_early(vcpu)) { |
| 421 | − /* Prevent it being handled again. */ | |
| 422 | − trap = 0; | |
| 424 | + /* | |
| 425 | + * Go straight back into the guest with the | |
| 426 | + * new NIP/MSR as set by TM emulation. | |
| 427 | + */ | |
| 428 | + mtspr(SPRN_HSRR0, vcpu->arch.regs.nip); | |
| 429 | + mtspr(SPRN_HSRR1, vcpu->arch.shregs.msr); | |
| 430 | + | |
| 431 | + /* | |
| 432 | + * tm_return_to_guest re-loads SRR0/1, DAR, | |
| 433 | + * DSISR after RI is cleared, in case they had | |
| 434 | + * been clobbered by a MCE. | |
| 435 | + */ | |
| 436 | + __mtmsrd(0, 1); /* clear RI */ | |
| 437 | + goto tm_return_to_guest; | |
| 423 | 438 | } |
| 424 | 439 | } |
| 425 | 440 | #endif |
| @@ -499,6 +514,10 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc · 73 unmodified lines | ||
| 499 | 514 | * If we are in real mode, only switch MMU on after the MMU is |
| 500 | 515 | * switched to host, to avoid the P9_RADIX_PREFETCH_BUG. |
| 501 | 516 | */ |
| 517 | + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && | |
| 518 | + vcpu->arch.shregs.msr & MSR_TS_MASK) | |
| 519 | + msr |= MSR_TS_S; | |
| 520 | + | |
| 502 | 521 | __mtmsrd(msr, 0); |
| 503 | 522 | |
| 504 | 523 | end_timing(vcpu); |
| @@ -242,6 +242,17 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu) · 241 unmodified lines | ||
| 242 | 242 | * value so we can restore it on the way out. |
| 243 | 243 | */ |
| 244 | 244 | orig_rets = args.rets; |
| 245 | + if (be32_to_cpu(args.nargs) >= ARRAY_SIZE(args.args)) { | |
| 246 | + /* | |
| 247 | + * Don't overflow our args array: ensure there is room for | |
| 248 | + * at least rets[0] (even if the call specifies 0 nret). | |
| 249 | + * | |
| 250 | + * Each handler must then check for the correct nargs and nret | |
| 251 | + * values, but they may always return failure in rets[0]. | |
| 252 | + */ | |
| 253 | + rc = -EINVAL; | |
| 254 | + goto fail; | |
| 255 | + } | |
| 245 | 256 | args.rets = &args.args[be32_to_cpu(args.nargs)]; |
| 246 | 257 | |
| 247 | 258 | mutex_lock(&vcpu->kvm->arch.rtas_token_lock); |
| @@ -269,9 +280,17 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu) · 21 unmodified lines | ||
| 269 | 280 | fail: |
| 270 | 281 | /* |
| 271 | 282 | * We only get here if the guest has called RTAS with a bogus |
| 272 | − * args pointer. That means we can't get to the args, and so we | |
| 273 | − * can't fail the RTAS call. So fail right out to userspace, | |
| 274 | − * which should kill the guest. | |
| 283 | + * args pointer or nargs/nret values that would overflow the | |
| 284 | + * array. That means we can't get to the args, and so we can't | |
| 285 | + * fail the RTAS call. So fail right out to userspace, which | |
| 286 | + * should kill the guest. | |
| 287 | + * | |
| 288 | + * SLOF should actually pass the hcall return value from the | |
| 289 | + * rtas handler call in r3, so enter_rtas could be modified to | |
| 290 | + * return a failure indication in r3 and we could return such | |
| 291 | + * errors to the guest rather than failing to host userspace. | |
| 292 | + * However old guests that don't test for failure could then | |
| 293 | + * continue silently after errors, so for now we won't do this. | |
| 275 | 294 | */ |
| 276 | 295 | return rc; |
| 277 | 296 | } |
| @@ -2048,9 +2048,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, · 2047 unmodified lines | ||
| 2048 | 2048 | { |
| 2049 | 2049 | struct kvm_enable_cap cap; |
| 2050 | 2050 | r = -EFAULT; |
| 2051 | − vcpu_load(vcpu); | |
| 2052 | 2051 | if (copy_from_user(&cap, argp, sizeof(cap))) |
| 2053 | 2052 | goto out; |
| 2053 | + vcpu_load(vcpu); | |
| 2054 | 2054 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); |
| 2055 | 2055 | vcpu_put(vcpu); |
| 2056 | 2056 | break; |
| @@ -2074,9 +2074,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, · 17 unmodified lines | ||
| 2074 | 2074 | case KVM_DIRTY_TLB: { |
| 2075 | 2075 | struct kvm_dirty_tlb dirty; |
| 2076 | 2076 | r = -EFAULT; |
| 2077 | − vcpu_load(vcpu); | |
| 2078 | 2077 | if (copy_from_user(&dirty, argp, sizeof(dirty))) |
| 2079 | 2078 | goto out; |
| 2079 | + vcpu_load(vcpu); | |
| 2080 | 2080 | r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty); |
| 2081 | 2081 | vcpu_put(vcpu); |
| 2082 | 2082 | break; |
| @@ -240,3 +240,13 @@ void __init setup_kuap(bool disabled) · 239 unmodified lines | ||
| 240 | 240 | mtspr(SPRN_MD_AP, MD_APG_KUAP); |
| 241 | 241 | } |
| 242 | 242 | #endif |
| 243 | + | |
| 244 | +int pud_clear_huge(pud_t *pud) | |
| 245 | +{ | |
| 246 | + return 0; | |
| 247 | +} | |
| 248 | + | |
| 249 | +int pmd_clear_huge(pmd_t *pmd) | |
| 250 | +{ | |
| 251 | + return 0; | |
| 252 | +} | |
| @@ -18,16 +18,12 @@ · 17 unmodified lines | ||
| 18 | 18 | /* |
| 19 | 19 | * Updates the attributes of a page in three steps: |
| 20 | 20 | * |
| 21 | − * 1. invalidate the page table entry | |
| 22 | − * 2. flush the TLB | |
| 23 | − * 3. install the new entry with the updated attributes | |
| 24 | − * | |
| 25 | − * Invalidating the pte means there are situations where this will not work | |
| 26 | − * when in theory it should. | |
| 27 | − * For example: | |
| 28 | − * - removing write from page whilst it is being executed | |
| 29 | − * - setting a page read-only whilst it is being read by another CPU | |
| 21 | + * 1. take the page_table_lock | |
| 22 | + * 2. install the new entry with the updated attributes | |
| 23 | + * 3. flush the TLB | |
| 30 | 24 | * |
| 25 | + * This sequence is safe against concurrent updates, and also allows updating the | |
| 26 | + * attributes of a page currently being executed or accessed. | |
| 31 | 27 | */ |
| 32 | 28 | static int change_page_attr(pte_t *ptep, unsigned long addr, void *data) |
| 33 | 29 | { |
| @@ -36,9 +32,7 @@ static int change_page_attr(pte_t *ptep, unsigned long addr, void *data) · 2 unmodified lines | ||
| 36 | 32 | |
| 37 | 33 | spin_lock(&init_mm.page_table_lock); |
| 38 | 34 | |
| 39 | − /* invalidate the PTE so it's safe to modify */ | |
| 40 | − pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
| 41 | − flush_tlb_kernel_range(addr, addr + PAGE_SIZE); | |
| 35 | + pte = ptep_get(ptep); | |
| 42 | 36 | |
| 43 | 37 | /* modify the PTE bits as desired, then apply */ |
| 44 | 38 | switch (action) { |
| @@ -59,11 +53,14 @@ static int change_page_attr(pte_t *ptep, unsigned long addr, void *data) · 14 unmodified lines | ||
| 59 | 53 | break; |
| 60 | 54 | } |
| 61 | 55 | |
| 62 | − set_pte_at(&init_mm, addr, ptep, pte); | |
| 56 | + pte_update(&init_mm, addr, ptep, ~0UL, pte_val(pte), 0); | |
| 63 | 57 | |
| 64 | 58 | /* See ptesync comment in radix__set_pte_at() */ |
| 65 | 59 | if (radix_enabled()) |
| 66 | 60 | asm volatile("ptesync": : :"memory"); |
| 61 | + | |
| 62 | + flush_tlb_kernel_range(addr, addr + PAGE_SIZE); | |
| 63 | + | |
| 67 | 64 | spin_unlock(&init_mm.page_table_lock); |
| 68 | 65 | |
| 69 | 66 | return 0; |
| @@ -737,6 +737,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * · 736 unmodified lines | ||
| 737 | 737 | } |
| 738 | 738 | break; |
| 739 | 739 | |
| 740 | + /* | |
| 741 | + * BPF_ST NOSPEC (speculation barrier) | |
| 742 | + */ | |
| 743 | + case BPF_ST | BPF_NOSPEC: | |
| 744 | + break; | |
| 745 | + | |
| 740 | 746 | /* |
| 741 | 747 | * BPF_ST(X) |
| 742 | 748 | */ |
| @@ -627,6 +627,12 @@ emit_clear: · 626 unmodified lines | ||
| 627 | 627 | } |
| 628 | 628 | break; |
| 629 | 629 | |
| 630 | + /* | |
| 631 | + * BPF_ST NOSPEC (speculation barrier) | |
| 632 | + */ | |
| 633 | + case BPF_ST | BPF_NOSPEC: | |
| 634 | + break; | |
| 635 | + | |
| 630 | 636 | /* |
| 631 | 637 | * BPF_ST(X) |
| 632 | 638 | */ |
| @@ -42,6 +42,7 @@ static int pasemi_system_reset_exception(struct pt_regs *regs) · 41 unmodified lines | ||
| 42 | 42 | switch (regs->msr & SRR1_WAKEMASK) { |
| 43 | 43 | case SRR1_WAKEDEC: |
| 44 | 44 | set_dec(1); |
| 45 | + break; | |
| 45 | 46 | case SRR1_WAKEEE: |
| 46 | 47 | /* |
| 47 | 48 | * Handle these when interrupts get re-enabled and we take |
| @@ -146,6 +146,7 @@ static inline void psurge_clr_ipi(int cpu) · 145 unmodified lines | ||
| 146 | 146 | switch(psurge_type) { |
| 147 | 147 | case PSURGE_DUAL: |
| 148 | 148 | out_8(psurge_sec_intr, ~0); |
| 149 | + break; | |
| 149 | 150 | case PSURGE_NONE: |
| 150 | 151 | break; |
| 151 | 152 | default: |
| @@ -77,7 +77,7 @@ · 76 unmodified lines | ||
| 77 | 77 | #include "../../../../drivers/pci/pci.h" |
| 78 | 78 | |
| 79 | 79 | DEFINE_STATIC_KEY_FALSE(shared_processor); |
| 80 | −EXPORT_SYMBOL_GPL(shared_processor); | |
| 80 | +EXPORT_SYMBOL(shared_processor); | |
| 81 | 81 | |
| 82 | 82 | int CMO_PrPSP = -1; |
| 83 | 83 | int CMO_SecPSP = -1; |
| @@ -539,9 +539,10 @@ static void init_cpu_char_feature_flags(struct h_cpu_char_result *result) · 455 unmodified lines | ||
| 539 | 539 | * H_CPU_BEHAV_FAVOUR_SECURITY_H could be set only if |
| 540 | 540 | * H_CPU_BEHAV_FAVOUR_SECURITY is. |
| 541 | 541 | */ |
| 542 | − if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) | |
| 542 | + if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) { | |
| 543 | 543 | security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); |
| 544 | − else if (result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY_H) | |
| 544 | + pseries_security_flavor = 0; | |
| 545 | + } else if (result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY_H) | |
| 545 | 546 | pseries_security_flavor = 1; |
| 546 | 547 | else |
| 547 | 548 | pseries_security_flavor = 2; |
| @@ -67,6 +67,7 @@ static struct irq_domain *xive_irq_domain; · 66 unmodified lines | ||
| 67 | 67 | static struct xive_ipi_desc { |
| 68 | 68 | unsigned int irq; |
| 69 | 69 | char name[16]; |
| 70 | + atomic_t started; | |
| 70 | 71 | } *xive_ipis; |
| 71 | 72 | |
| 72 | 73 | /* |
| @@ -1120,7 +1121,7 @@ static const struct irq_domain_ops xive_ipi_irq_domain_ops = { · 1047 unmodified lines | ||
| 1120 | 1121 | .alloc = xive_ipi_irq_domain_alloc, |
| 1121 | 1122 | }; |
| 1122 | 1123 | |
| 1123 | −static int __init xive_request_ipi(void) | |
| 1124 | +static int __init xive_init_ipis(void) | |
| 1124 | 1125 | { |
| 1125 | 1126 | struct fwnode_handle *fwnode; |
| 1126 | 1127 | struct irq_domain *ipi_domain; |
| @@ -1144,10 +1145,6 @@ static int __init xive_request_ipi(void) · 17 unmodified lines | ||
| 1144 | 1145 | struct xive_ipi_desc *xid = &xive_ipis[node]; |
| 1145 | 1146 | struct xive_ipi_alloc_info info = { node }; |
| 1146 | 1147 | |
| 1147 | − /* Skip nodes without CPUs */ | |
| 1148 | − if (cpumask_empty(cpumask_of_node(node))) | |
| 1149 | − continue; | |
| 1150 | − | |
| 1151 | 1148 | /* |
| 1152 | 1149 | * Map one IPI interrupt per node for all cpus of that node. |
| 1153 | 1150 | * Since the HW interrupt number doesn't have any meaning, |
| @@ -1159,11 +1156,6 @@ static int __init xive_request_ipi(void) · 5 unmodified lines | ||
| 1159 | 1156 | xid->irq = ret; |
| 1160 | 1157 | |
| 1161 | 1158 | snprintf(xid->name, sizeof(xid->name), "IPI-%d", node); |
| 1162 | − | |
| 1163 | − ret = request_irq(xid->irq, xive_muxed_ipi_action, | |
| 1164 | − IRQF_PERCPU | IRQF_NO_THREAD, xid->name, NULL); | |
| 1165 | − | |
| 1166 | − WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret); | |
| 1167 | 1159 | } |
| 1168 | 1160 | |
| 1169 | 1161 | return ret; |
| @@ -1178,6 +1170,22 @@ out: · 8 unmodified lines | ||
| 1178 | 1170 | return ret; |
| 1179 | 1171 | } |
| 1180 | 1172 | |
| 1173 | +static int xive_request_ipi(unsigned int cpu) | |
| 1174 | +{ | |
| 1175 | + struct xive_ipi_desc *xid = &xive_ipis[early_cpu_to_node(cpu)]; | |
| 1176 | + int ret; | |
| 1177 | + | |
| 1178 | + if (atomic_inc_return(&xid->started) > 1) | |
| 1179 | + return 0; | |
| 1180 | + | |
| 1181 | + ret = request_irq(xid->irq, xive_muxed_ipi_action, | |
| 1182 | + IRQF_PERCPU | IRQF_NO_THREAD, | |
| 1183 | + xid->name, NULL); | |
| 1184 | + | |
| 1185 | + WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret); | |
| 1186 | + return ret; | |
| 1187 | +} | |
| 1188 | + | |
| 1181 | 1189 | static int xive_setup_cpu_ipi(unsigned int cpu) |
| 1182 | 1190 | { |
| 1183 | 1191 | unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu); |
| @@ -1192,6 +1200,9 @@ static int xive_setup_cpu_ipi(unsigned int cpu) · 8 unmodified lines | ||
| 1192 | 1200 | if (xc->hw_ipi != XIVE_BAD_IRQ) |
| 1193 | 1201 | return 0; |
| 1194 | 1202 | |
| 1203 | + /* Register the IPI */ | |
| 1204 | + xive_request_ipi(cpu); | |
| 1205 | + | |
| 1195 | 1206 | /* Grab an IPI from the backend, this will populate xc->hw_ipi */ |
| 1196 | 1207 | if (xive_ops->get_ipi(cpu, xc)) |
| 1197 | 1208 | return -EIO; |
| @@ -1231,6 +1242,8 @@ static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc) · 33 unmodified lines | ||
| 1231 | 1242 | if (xc->hw_ipi == XIVE_BAD_IRQ) |
| 1232 | 1243 | return; |
| 1233 | 1244 | |
| 1245 | + /* TODO: clear IPI mapping */ | |
| 1246 | + | |
| 1234 | 1247 | /* Mask the IPI */ |
| 1235 | 1248 | xive_do_source_set_mask(&xc->ipi_data, true); |
| 1236 | 1249 | |
| @@ -1253,7 +1266,7 @@ void __init xive_smp_probe(void) · 16 unmodified lines | ||
| 1253 | 1266 | smp_ops->cause_ipi = xive_cause_ipi; |
| 1254 | 1267 | |
| 1255 | 1268 | /* Register the IPI */ |
| 1256 | − xive_request_ipi(); | |
| 1269 | + xive_init_ipis(); | |
| 1257 | 1270 | |
| 1258 | 1271 | /* Allocate and setup IPI for the boot CPU */ |
| 1259 | 1272 | xive_setup_cpu_ipi(smp_processor_id()); |
| @@ -492,10 +492,16 @@ config CC_HAVE_STACKPROTECTOR_TLS · 491 unmodified lines | ||
| 492 | 492 | |
| 493 | 493 | config STACKPROTECTOR_PER_TASK |
| 494 | 494 | def_bool y |
| 495 | + depends on !GCC_PLUGIN_RANDSTRUCT | |
| 495 | 496 | depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS |
| 496 | 497 | |
| 498 | +config PHYS_RAM_BASE_FIXED | |
| 499 | + bool "Explicitly specified physical RAM address" | |
| 500 | + default n | |
| 501 | + | |
| 497 | 502 | config PHYS_RAM_BASE |
| 498 | 503 | hex "Platform Physical RAM address" |
| 504 | + depends on PHYS_RAM_BASE_FIXED | |
| 499 | 505 | default "0x80000000" |
| 500 | 506 | help |
| 501 | 507 | This is the physical address of RAM in the system. It has to be |
| @@ -508,6 +514,7 @@ config XIP_KERNEL · 6 unmodified lines | ||
| 508 | 514 | # This prevents XIP from being enabled by all{yes,mod}config, which |
| 509 | 515 | # fail to build since XIP doesn't support large kernels. |
| 510 | 516 | depends on !COMPILE_TEST |
| 517 | + select PHYS_RAM_BASE_FIXED | |
| 511 | 518 | help |
| 512 | 519 | Execute-In-Place allows the kernel to run from non-volatile storage |
| 513 | 520 | directly addressable by the CPU, such as NOR flash. This saves RAM |
| @@ -24,7 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | |
| 25 | 25 | memory@80000000 { |
| 26 | 26 | device_type = "memory"; |
| 27 | − reg = <0x0 0x80000000 0x2 0x00000000>; | |
| 27 | + reg = <0x0 0x80000000 0x4 0x00000000>; | |
| 28 | 28 | }; |
| 29 | 29 | |
| 30 | 30 | soc { |
| @@ -27,10 +27,10 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); · 26 unmodified lines | ||
| 27 | 27 | |
| 28 | 28 | #define ARCH_EFI_IRQ_FLAGS_MASK (SR_IE | SR_SPIE) |
| 29 | 29 | |
| 30 | −/* Load initrd at enough distance from DRAM start */ | |
| 30 | +/* Load initrd anywhere in system RAM */ | |
| 31 | 31 | static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr) |
| 32 | 32 | { |
| 33 | − return image_addr + SZ_256M; | |
| 33 | + return ULONG_MAX; | |
| 34 | 34 | } |
| 35 | 35 | |
| 36 | 36 | #define alloc_screen_info(x...) (&screen_info) |
| @@ -103,6 +103,7 @@ struct kernel_mapping { · 102 unmodified lines | ||
| 103 | 103 | }; |
| 104 | 104 | |
| 105 | 105 | extern struct kernel_mapping kernel_map; |
| 106 | +extern phys_addr_t phys_ram_base; | |
| 106 | 107 | |
| 107 | 108 | #ifdef CONFIG_64BIT |
| 108 | 109 | #define is_kernel_mapping(x) \ |
| @@ -113,9 +114,9 @@ extern struct kernel_mapping kernel_map; · 4 unmodified lines | ||
| 113 | 114 | #define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)) |
| 114 | 115 | #define kernel_mapping_pa_to_va(y) ({ \ |
| 115 | 116 | unsigned long _y = y; \ |
| 116 | − (_y >= CONFIG_PHYS_RAM_BASE) ? \ | |
| 117 | − (void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET) : \ | |
| 118 | − (void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset); \ | |
| 117 | + (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \ | |
| 118 | + (void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset) : \ | |
| 119 | + (void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET); \ | |
| 119 | 120 | }) |
| 120 | 121 | #define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x) |
| 121 | 122 | |
| @@ -11,7 +11,7 @@ endif · 10 unmodified lines | ||
| 11 | 11 | CFLAGS_syscall_table.o += $(call cc-option,-Wno-override-init,) |
| 12 | 12 | |
| 13 | 13 | ifdef CONFIG_KEXEC |
| 14 | −AFLAGS_kexec_relocate.o := -mcmodel=medany -mno-relax | |
| 14 | +AFLAGS_kexec_relocate.o := -mcmodel=medany $(call cc-option,-mno-relax) | |
| 15 | 15 | endif |
| 16 | 16 | |
| 17 | 17 | extra-y += head.o |
| @@ -229,8 +229,8 @@ static void __init init_resources(void) · 228 unmodified lines | ||
| 229 | 229 | } |
| 230 | 230 | |
| 231 | 231 | /* Clean-up any unused pre-allocated resources */ |
| 232 | − mem_res_sz = (num_resources - res_idx + 1) * sizeof(*mem_res); | |
| 233 | − memblock_free(__pa(mem_res), mem_res_sz); | |
| 232 | + if (res_idx >= 0) | |
| 233 | + memblock_free(__pa(mem_res), (res_idx + 1) * sizeof(*mem_res)); | |
| 234 | 234 | return; |
| 235 | 235 | |
| 236 | 236 | error: |
| @@ -27,7 +27,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, · 26 unmodified lines | ||
| 27 | 27 | fp = frame_pointer(regs); |
| 28 | 28 | sp = user_stack_pointer(regs); |
| 29 | 29 | pc = instruction_pointer(regs); |
| 30 | − } else if (task == current) { | |
| 30 | + } else if (task == NULL || task == current) { | |
| 31 | 31 | fp = (unsigned long)__builtin_frame_address(1); |
| 32 | 32 | sp = (unsigned long)__builtin_frame_address(0); |
| 33 | 33 | pc = (unsigned long)__builtin_return_address(0); |
| @@ -132,8 +132,12 @@ unsigned long get_wchan(struct task_struct *task) · 98 unmodified lines | ||
| 132 | 132 | { |
| 133 | 133 | unsigned long pc = 0; |
| 134 | 134 | |
| 135 | − if (likely(task && task != current && !task_is_running(task))) | |
| 135 | + if (likely(task && task != current && !task_is_running(task))) { | |
| 136 | + if (!try_get_task_stack(task)) | |
| 137 | + return 0; | |
| 136 | 138 | walk_stackframe(task, NULL, save_wchan, &pc); |
| 139 | + put_task_stack(task); | |
| 140 | + } | |
| 137 | 141 | return pc; |
| 138 | 142 | } |
| 139 | 143 | |
| @@ -30,23 +30,23 @@ ENTRY(__asm_copy_from_user) · 29 unmodified lines | ||
| 30 | 30 | * t0 - end of uncopied dst |
| 31 | 31 | */ |
| 32 | 32 | add t0, a0, a2 |
| 33 | − bgtu a0, t0, 5f | |
| 34 | 33 | |
| 35 | 34 | /* |
| 36 | 35 | * Use byte copy only if too small. |
| 36 | + * SZREG holds 4 for RV32 and 8 for RV64 | |
| 37 | 37 | */ |
| 38 | − li a3, 8*SZREG /* size must be larger than size in word_copy */ | |
| 38 | + li a3, 9*SZREG /* size must be larger than size in word_copy */ | |
| 39 | 39 | bltu a2, a3, .Lbyte_copy_tail |
| 40 | 40 | |
| 41 | 41 | /* |
| 42 | − * Copy first bytes until dst is align to word boundary. | |
| 42 | + * Copy first bytes until dst is aligned to word boundary. | |
| 43 | 43 | * a0 - start of dst |
| 44 | 44 | * t1 - start of aligned dst |
| 45 | 45 | */ |
| 46 | 46 | addi t1, a0, SZREG-1 |
| 47 | 47 | andi t1, t1, ~(SZREG-1) |
| 48 | 48 | /* dst is already aligned, skip */ |
| 49 | − beq a0, t1, .Lskip_first_bytes | |
| 49 | + beq a0, t1, .Lskip_align_dst | |
| 50 | 50 | 1: |
| 51 | 51 | /* a5 - one byte for copying data */ |
| 52 | 52 | fixup lb a5, 0(a1), 10f |
| @@ -55,7 +55,7 @@ ENTRY(__asm_copy_from_user) · 2 unmodified lines | ||
| 55 | 55 | addi a0, a0, 1 /* dst */ |
| 56 | 56 | bltu a0, t1, 1b /* t1 - start of aligned dst */ |
| 57 | 57 | |
| 58 | −.Lskip_first_bytes: | |
| 58 | +.Lskip_align_dst: | |
| 59 | 59 | /* |
| 60 | 60 | * Now dst is aligned. |
| 61 | 61 | * Use shift-copy if src is misaligned. |
| @@ -72,10 +72,9 @@ ENTRY(__asm_copy_from_user) · 10 unmodified lines | ||
| 72 | 72 | * |
| 73 | 73 | * a0 - start of aligned dst |
| 74 | 74 | * a1 - start of aligned src |
| 75 | − * a3 - a1 & mask:(SZREG-1) | |
| 76 | 75 | * t0 - end of aligned dst |
| 77 | 76 | */ |
| 78 | − addi t0, t0, -(8*SZREG-1) /* not to over run */ | |
| 77 | + addi t0, t0, -(8*SZREG) /* not to over run */ | |
| 79 | 78 | 2: |
| 80 | 79 | fixup REG_L a4, 0(a1), 10f |
| 81 | 80 | fixup REG_L a5, SZREG(a1), 10f |
| @@ -97,7 +96,7 @@ ENTRY(__asm_copy_from_user) · 15 unmodified lines | ||
| 97 | 96 | addi a1, a1, 8*SZREG |
| 98 | 97 | bltu a0, t0, 2b |
| 99 | 98 | |
| 100 | − addi t0, t0, 8*SZREG-1 /* revert to original value */ | |
| 99 | + addi t0, t0, 8*SZREG /* revert to original value */ | |
| 101 | 100 | j .Lbyte_copy_tail |
| 102 | 101 | |
| 103 | 102 | .Lshift_copy: |
| @@ -107,7 +106,7 @@ ENTRY(__asm_copy_from_user) · 3 unmodified lines | ||
| 107 | 106 | * For misaligned copy we still perform aligned word copy, but |
| 108 | 107 | * we need to use the value fetched from the previous iteration and |
| 109 | 108 | * do some shifts. |
| 110 | − * This is safe because reading less than a word size. | |
| 109 | + * This is safe because reading is less than a word size. | |
| 111 | 110 | * |
| 112 | 111 | * a0 - start of aligned dst |
| 113 | 112 | * a1 - start of src |
| @@ -117,7 +116,7 @@ ENTRY(__asm_copy_from_user) · 3 unmodified lines | ||
| 117 | 116 | */ |
| 118 | 117 | /* calculating aligned word boundary for dst */ |
| 119 | 118 | andi t1, t0, ~(SZREG-1) |
| 120 | − /* Converting unaligned src to aligned arc */ | |
| 119 | + /* Converting unaligned src to aligned src */ | |
| 121 | 120 | andi a1, a1, ~(SZREG-1) |
| 122 | 121 | |
| 123 | 122 | /* |
| @@ -125,11 +124,11 @@ ENTRY(__asm_copy_from_user) · 1 unmodified line | ||
| 125 | 124 | * t3 - prev shift |
| 126 | 125 | * t4 - current shift |
| 127 | 126 | */ |
| 128 | − slli t3, a3, LGREG | |
| 127 | + slli t3, a3, 3 /* converting bytes in a3 to bits */ | |
| 129 | 128 | li a5, SZREG*8 |
| 130 | 129 | sub t4, a5, t3 |
| 131 | 130 | |
| 132 | − /* Load the first word to combine with seceond word */ | |
| 131 | + /* Load the first word to combine with second word */ | |
| 133 | 132 | fixup REG_L a5, 0(a1), 10f |
| 134 | 133 | |
| 135 | 134 | 3: |
| @@ -161,7 +160,7 @@ ENTRY(__asm_copy_from_user) · 25 unmodified lines | ||
| 161 | 160 | * a1 - start of remaining src |
| 162 | 161 | * t0 - end of remaining dst |
| 163 | 162 | */ |
| 164 | − bgeu a0, t0, 5f | |
| 163 | + bgeu a0, t0, .Lout_copy_user /* check if end of copy */ | |
| 165 | 164 | 4: |
| 166 | 165 | fixup lb a5, 0(a1), 10f |
| 167 | 166 | addi a1, a1, 1 /* src */ |
| @@ -169,7 +168,7 @@ ENTRY(__asm_copy_from_user) · 1 unmodified line | ||
| 169 | 168 | addi a0, a0, 1 /* dst */ |
| 170 | 169 | bltu a0, t0, 4b /* t0 - end of dst */ |
| 171 | 170 | |
| 172 | −5: | |
| 171 | +.Lout_copy_user: | |
| 173 | 172 | /* Disable access to user memory */ |
| 174 | 173 | csrc CSR_STATUS, t6 |
| 175 | 174 | li a0, 0 |
| @@ -36,6 +36,9 @@ EXPORT_SYMBOL(kernel_map); · 35 unmodified lines | ||
| 36 | 36 | #define kernel_map (*(struct kernel_mapping *)XIP_FIXUP(&kernel_map)) |
| 37 | 37 | #endif |
| 38 | 38 | |
| 39 | +phys_addr_t phys_ram_base __ro_after_init; | |
| 40 | +EXPORT_SYMBOL(phys_ram_base); | |
| 41 | + | |
| 39 | 42 | #ifdef CONFIG_XIP_KERNEL |
| 40 | 43 | extern char _xiprom[], _exiprom[]; |
| 41 | 44 | #endif |
| @@ -127,10 +130,17 @@ void __init mem_init(void) · 85 unmodified lines | ||
| 127 | 130 | } |
| 128 | 131 | |
| 129 | 132 | /* |
| 130 | − * The default maximal physical memory size is -PAGE_OFFSET, | |
| 131 | − * limit the memory size via mem. | |
| 133 | + * The default maximal physical memory size is -PAGE_OFFSET for 32-bit kernel, | |
| 134 | + * whereas for 64-bit kernel, the end of the virtual address space is occupied | |
| 135 | + * by the modules/BPF/kernel mappings which reduces the available size of the | |
| 136 | + * linear mapping. | |
| 137 | + * Limit the memory size via mem. | |
| 132 | 138 | */ |
| 139 | +#ifdef CONFIG_64BIT | |
| 140 | +static phys_addr_t memory_limit = -PAGE_OFFSET - SZ_4G; | |
| 141 | +#else | |
| 133 | 142 | static phys_addr_t memory_limit = -PAGE_OFFSET; |
| 143 | +#endif | |
| 134 | 144 | |
| 135 | 145 | static int __init early_mem(char *p) |
| 136 | 146 | { |
| @@ -152,8 +162,8 @@ static void __init setup_bootmem(void) · 15 unmodified lines | ||
| 152 | 162 | { |
| 153 | 163 | phys_addr_t vmlinux_end = __pa_symbol(&_end); |
| 154 | 164 | phys_addr_t vmlinux_start = __pa_symbol(&_start); |
| 155 | − phys_addr_t max_mapped_addr = __pa(~(ulong)0); | |
| 156 | − phys_addr_t dram_end; | |
| 165 | + phys_addr_t __maybe_unused max_mapped_addr; | |
| 166 | + phys_addr_t phys_ram_end; | |
| 157 | 167 | |
| 158 | 168 | #ifdef CONFIG_XIP_KERNEL |
| 159 | 169 | vmlinux_start = __pa_symbol(&_sdata); |
| @@ -174,18 +184,28 @@ static void __init setup_bootmem(void) · 14 unmodified lines | ||
| 174 | 184 | #endif |
| 175 | 185 | memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start); |
| 176 | 186 | |
| 177 | − dram_end = memblock_end_of_DRAM(); | |
| 187 | + | |
| 188 | + phys_ram_end = memblock_end_of_DRAM(); | |
| 189 | +#ifndef CONFIG_64BIT | |
| 190 | +#ifndef CONFIG_XIP_KERNEL | |
| 191 | + phys_ram_base = memblock_start_of_DRAM(); | |
| 192 | +#endif | |
| 178 | 193 | /* |
| 179 | 194 | * memblock allocator is not aware of the fact that last 4K bytes of |
| 180 | 195 | * the addressable memory can not be mapped because of IS_ERR_VALUE |
| 181 | 196 | * macro. Make sure that last 4k bytes are not usable by memblock |
| 182 | − * if end of dram is equal to maximum addressable memory. | |
| 197 | + * if end of dram is equal to maximum addressable memory. For 64-bit | |
| 198 | + * kernel, this problem can't happen here as the end of the virtual | |
| 199 | + * address space is occupied by the kernel mapping then this check must | |
| 200 | + * be done as soon as the kernel mapping base address is determined. | |
| 183 | 201 | */ |
| 184 | − if (max_mapped_addr == (dram_end - 1)) | |
| 202 | + max_mapped_addr = __pa(~(ulong)0); | |
| 203 | + if (max_mapped_addr == (phys_ram_end - 1)) | |
| 185 | 204 | memblock_set_current_limit(max_mapped_addr - 4096); |
| 205 | +#endif | |
| 186 | 206 | |
| 187 | − min_low_pfn = PFN_UP(memblock_start_of_DRAM()); | |
| 188 | − max_low_pfn = max_pfn = PFN_DOWN(dram_end); | |
| 207 | + min_low_pfn = PFN_UP(phys_ram_base); | |
| 208 | + max_low_pfn = max_pfn = PFN_DOWN(phys_ram_end); | |
| 189 | 209 | |
| 190 | 210 | dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn)); |
| 191 | 211 | set_max_mapnr(max_low_pfn - ARCH_PFN_OFFSET); |
| @@ -544,6 +564,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) · 352 unmodified lines | ||
| 544 | 564 | kernel_map.xiprom = (uintptr_t)CONFIG_XIP_PHYS_ADDR; |
| 545 | 565 | kernel_map.xiprom_sz = (uintptr_t)(&_exiprom) - (uintptr_t)(&_xiprom); |
| 546 | 566 | |
| 567 | + phys_ram_base = CONFIG_PHYS_RAM_BASE; | |
| 547 | 568 | kernel_map.phys_addr = (uintptr_t)CONFIG_PHYS_RAM_BASE; |
| 548 | 569 | kernel_map.size = (uintptr_t)(&_end) - (uintptr_t)(&_sdata); |
| 549 | 570 | |
| @@ -570,6 +591,14 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) · 20 unmodified lines | ||
| 570 | 591 | BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0); |
| 571 | 592 | BUG_ON((kernel_map.phys_addr % map_size) != 0); |
| 572 | 593 | |
| 594 | +#ifdef CONFIG_64BIT | |
| 595 | + /* | |
| 596 | + * The last 4K bytes of the addressable memory can not be mapped because | |
| 597 | + * of IS_ERR_VALUE macro. | |
| 598 | + */ | |
| 599 | + BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K); | |
| 600 | +#endif | |
| 601 | + | |
| 573 | 602 | pt_ops.alloc_pte = alloc_pte_early; |
| 574 | 603 | pt_ops.get_pte_virt = get_pte_virt_early; |
| 575 | 604 | #ifndef __PAGETABLE_PMD_FOLDED |
| @@ -709,6 +738,8 @@ static void __init setup_vm_final(void) · 133 unmodified lines | ||
| 709 | 738 | if (start <= __pa(PAGE_OFFSET) && |
| 710 | 739 | __pa(PAGE_OFFSET) < end) |
| 711 | 740 | start = __pa(PAGE_OFFSET); |
| 741 | + if (end >= __pa(PAGE_OFFSET) + memory_limit) | |
| 742 | + end = __pa(PAGE_OFFSET) + memory_limit; | |
| 712 | 743 | |
| 713 | 744 | map_size = best_map_size(start, end - start); |
| 714 | 745 | for (pa = start; pa < end; pa += map_size) { |
| @@ -1251,6 +1251,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, · 1250 unmodified lines | ||
| 1251 | 1251 | return -1; |
| 1252 | 1252 | break; |
| 1253 | 1253 | |
| 1254 | + /* speculation barrier */ | |
| 1255 | + case BPF_ST | BPF_NOSPEC: | |
| 1256 | + break; | |
| 1257 | + | |
| 1254 | 1258 | case BPF_ST | BPF_MEM | BPF_B: |
| 1255 | 1259 | case BPF_ST | BPF_MEM | BPF_H: |
| 1256 | 1260 | case BPF_ST | BPF_MEM | BPF_W: |
| @@ -939,6 +939,10 @@ out_be: · 938 unmodified lines | ||
| 939 | 939 | emit_ld(rd, 0, RV_REG_T1, ctx); |
| 940 | 940 | break; |
| 941 | 941 | |
| 942 | + /* speculation barrier */ | |
| 943 | + case BPF_ST | BPF_NOSPEC: | |
| 944 | + break; | |
| 945 | + | |
| 942 | 946 | /* ST: *(size *)(dst + off) = imm */ |
| 943 | 947 | case BPF_ST | BPF_MEM | BPF_B: |
| 944 | 948 | emit_imm(RV_REG_T1, imm, ctx); |
| @@ -11,6 +11,7 @@ UBSAN_SANITIZE := n · 10 unmodified lines | ||
| 11 | 11 | KASAN_SANITIZE := n |
| 12 | 12 | |
| 13 | 13 | obj-y := $(if $(CONFIG_KERNEL_UNCOMPRESSED),,decompressor.o) info.o |
| 14 | +obj-$(CONFIG_KERNEL_ZSTD) += clz_ctz.o | |
| 14 | 15 | obj-all := $(obj-y) piggy.o syms.o |
| 15 | 16 | targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 |
| 16 | 17 | targets += vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.lz4 |
| @@ -0,0 +1,2 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0 | |
| 2 | +#include "../../../../lib/clz_ctz.c" | |
| @@ -9,16 +9,6 @@ · 8 unmodified lines | ||
| 9 | 9 | #include <asm/errno.h> |
| 10 | 10 | #include <asm/sigp.h> |
| 11 | 11 | |
| 12 | −#ifdef CC_USING_EXPOLINE | |
| 13 | − .pushsection .dma.text.__s390_indirect_jump_r14,"axG" | |
| 14 | −__dma__s390_indirect_jump_r14: | |
| 15 | − larl %r1,0f | |
| 16 | − ex 0,0(%r1) | |
| 17 | − j . | |
| 18 | −0: br %r14 | |
| 19 | − .popsection | |
| 20 | −#endif | |
| 21 | − | |
| 22 | 12 | .section .dma.text,"ax" |
| 23 | 13 | /* |
| 24 | 14 | * Simplified version of expoline thunk. The normal thunks can not be used here, |
| @@ -27,11 +17,10 @@ __dma__s390_indirect_jump_r14: · 2 unmodified lines | ||
| 27 | 17 | * affects a few functions that are not performance-relevant. |
| 28 | 18 | */ |
| 29 | 19 | .macro BR_EX_DMA_r14 |
| 30 | −#ifdef CC_USING_EXPOLINE | |
| 31 | − jg __dma__s390_indirect_jump_r14 | |
| 32 | −#else | |
| 33 | − br %r14 | |
| 34 | −#endif | |
| 20 | + larl %r1,0f | |
| 21 | + ex 0,0(%r1) | |
| 22 | + j . | |
| 23 | +0: br %r14 | |
| 35 | 24 | .endm |
| 36 | 25 | |
| 37 | 26 | /* |
| @@ -5,7 +5,12 @@ CONFIG_WATCH_QUEUE=y · 4 unmodified lines | ||
| 5 | 5 | CONFIG_AUDIT=y |
| 6 | 6 | CONFIG_NO_HZ_IDLE=y |
| 7 | 7 | CONFIG_HIGH_RES_TIMERS=y |
| 8 | +CONFIG_BPF_SYSCALL=y | |
| 9 | +CONFIG_BPF_JIT=y | |
| 10 | +CONFIG_BPF_JIT_ALWAYS_ON=y | |
| 11 | +CONFIG_BPF_LSM=y | |
| 8 | 12 | CONFIG_PREEMPT=y |
| 13 | +CONFIG_SCHED_CORE=y | |
| 9 | 14 | CONFIG_BSD_PROCESS_ACCT=y |
| 10 | 15 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 11 | 16 | CONFIG_TASKSTATS=y |
| @@ -28,14 +33,13 @@ CONFIG_CGROUP_DEVICE=y · 16 unmodified lines | ||
| 28 | 33 | CONFIG_CGROUP_CPUACCT=y |
| 29 | 34 | CONFIG_CGROUP_PERF=y |
| 30 | 35 | CONFIG_CGROUP_BPF=y |
| 36 | +CONFIG_CGROUP_MISC=y | |
| 31 | 37 | CONFIG_NAMESPACES=y |
| 32 | 38 | CONFIG_USER_NS=y |
| 33 | 39 | CONFIG_CHECKPOINT_RESTORE=y |
| 34 | 40 | CONFIG_SCHED_AUTOGROUP=y |
| 35 | 41 | CONFIG_EXPERT=y |
| 36 | 42 | # CONFIG_SYSFS_SYSCALL is not set |
| 37 | −CONFIG_BPF_LSM=y | |
| 38 | −CONFIG_BPF_SYSCALL=y | |
| 39 | 43 | CONFIG_USERFAULTFD=y |
| 40 | 44 | # CONFIG_COMPAT_BRK is not set |
| 41 | 45 | CONFIG_PROFILING=y |
| @@ -76,6 +80,7 @@ CONFIG_BLK_DEV_THROTTLING=y · 34 unmodified lines | ||
| 76 | 80 | CONFIG_BLK_WBT=y |
| 77 | 81 | CONFIG_BLK_CGROUP_IOLATENCY=y |
| 78 | 82 | CONFIG_BLK_CGROUP_IOCOST=y |
| 83 | +CONFIG_BLK_CGROUP_IOPRIO=y | |
| 79 | 84 | CONFIG_BLK_INLINE_ENCRYPTION=y |
| 80 | 85 | CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y |
| 81 | 86 | CONFIG_PARTITION_ADVANCED=y |
| @@ -95,6 +100,7 @@ CONFIG_CLEANCACHE=y · 13 unmodified lines | ||
| 95 | 100 | CONFIG_FRONTSWAP=y |
| 96 | 101 | CONFIG_CMA_DEBUG=y |
| 97 | 102 | CONFIG_CMA_DEBUGFS=y |
| 103 | +CONFIG_CMA_SYSFS=y | |
| 98 | 104 | CONFIG_CMA_AREAS=7 |
| 99 | 105 | CONFIG_MEM_SOFT_DIRTY=y |
| 100 | 106 | CONFIG_ZSWAP=y |
| @@ -158,6 +164,7 @@ CONFIG_IPV6_RPL_LWTUNNEL=y · 57 unmodified lines | ||
| 158 | 164 | CONFIG_MPTCP=y |
| 159 | 165 | CONFIG_NETFILTER=y |
| 160 | 166 | CONFIG_BRIDGE_NETFILTER=m |
| 167 | +CONFIG_NETFILTER_NETLINK_HOOK=m | |
| 161 | 168 | CONFIG_NF_CONNTRACK=m |
| 162 | 169 | CONFIG_NF_CONNTRACK_SECMARK=y |
| 163 | 170 | CONFIG_NF_CONNTRACK_EVENTS=y |
| @@ -280,6 +287,7 @@ CONFIG_IP_VS_FTP=m · 116 unmodified lines | ||
| 280 | 287 | CONFIG_IP_VS_PE_SIP=m |
| 281 | 288 | CONFIG_NFT_FIB_IPV4=m |
| 282 | 289 | CONFIG_NF_TABLES_ARP=y |
| 290 | +CONFIG_NF_LOG_IPV4=m | |
| 283 | 291 | CONFIG_IP_NF_IPTABLES=m |
| 284 | 292 | CONFIG_IP_NF_MATCH_AH=m |
| 285 | 293 | CONFIG_IP_NF_MATCH_ECN=m |
| @@ -327,7 +335,7 @@ CONFIG_L2TP_DEBUGFS=m · 41 unmodified lines | ||
| 327 | 335 | CONFIG_L2TP_V3=y |
| 328 | 336 | CONFIG_L2TP_IP=m |
| 329 | 337 | CONFIG_L2TP_ETH=m |
| 330 | −CONFIG_BRIDGE=m | |
| 338 | +CONFIG_BRIDGE=y | |
| 331 | 339 | CONFIG_BRIDGE_MRP=y |
| 332 | 340 | CONFIG_VLAN_8021Q=m |
| 333 | 341 | CONFIG_VLAN_8021Q_GVRP=y |
| @@ -384,12 +392,11 @@ CONFIG_VSOCKETS=m · 50 unmodified lines | ||
| 384 | 392 | CONFIG_VIRTIO_VSOCKETS=m |
| 385 | 393 | CONFIG_NETLINK_DIAG=m |
| 386 | 394 | CONFIG_CGROUP_NET_PRIO=y |
| 387 | −CONFIG_BPF_JIT=y | |
| 388 | 395 | CONFIG_NET_PKTGEN=m |
| 389 | 396 | CONFIG_PCI=y |
| 390 | −CONFIG_PCI_IOV=y | |
| 391 | 397 | # CONFIG_PCIEASPM is not set |
| 392 | 398 | CONFIG_PCI_DEBUG=y |
| 399 | +CONFIG_PCI_IOV=y | |
| 393 | 400 | CONFIG_HOTPLUG_PCI=y |
| 394 | 401 | CONFIG_HOTPLUG_PCI_S390=y |
| 395 | 402 | CONFIG_DEVTMPFS=y |
| @@ -436,7 +443,7 @@ CONFIG_MD_MULTIPATH=m · 40 unmodified lines | ||
| 436 | 443 | CONFIG_MD_FAULTY=m |
| 437 | 444 | CONFIG_MD_CLUSTER=m |
| 438 | 445 | CONFIG_BCACHE=m |
| 439 | −CONFIG_BLK_DEV_DM=m | |
| 446 | +CONFIG_BLK_DEV_DM=y | |
| 440 | 447 | CONFIG_DM_UNSTRIPED=m |
| 441 | 448 | CONFIG_DM_CRYPT=m |
| 442 | 449 | CONFIG_DM_SNAPSHOT=m |
| @@ -453,6 +460,7 @@ CONFIG_DM_MULTIPATH_ST=m · 10 unmodified lines | ||
| 453 | 460 | CONFIG_DM_MULTIPATH_HST=m |
| 454 | 461 | CONFIG_DM_MULTIPATH_IOA=m |
| 455 | 462 | CONFIG_DM_DELAY=m |
| 463 | +CONFIG_DM_INIT=y | |
| 456 | 464 | CONFIG_DM_UEVENT=y |
| 457 | 465 | CONFIG_DM_FLAKEY=m |
| 458 | 466 | CONFIG_DM_VERITY=m |
| @@ -495,6 +503,7 @@ CONFIG_NLMON=m · 36 unmodified lines | ||
| 495 | 503 | # CONFIG_NET_VENDOR_GOOGLE is not set |
| 496 | 504 | # CONFIG_NET_VENDOR_HUAWEI is not set |
| 497 | 505 | # CONFIG_NET_VENDOR_INTEL is not set |
| 506 | +# CONFIG_NET_VENDOR_MICROSOFT is not set | |
| 498 | 507 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 499 | 508 | CONFIG_MLX4_EN=m |
| 500 | 509 | CONFIG_MLX5_CORE=m |
| @@ -551,7 +560,6 @@ CONFIG_INPUT_EVDEV=y · 50 unmodified lines | ||
| 551 | 560 | CONFIG_LEGACY_PTY_COUNT=0 |
| 552 | 561 | CONFIG_VIRTIO_CONSOLE=m |
| 553 | 562 | CONFIG_HW_RANDOM_VIRTIO=m |
| 554 | −CONFIG_RAW_DRIVER=m | |
| 555 | 563 | CONFIG_HANGCHECK_TIMER=m |
| 556 | 564 | CONFIG_TN3270_FS=y |
| 557 | 565 | CONFIG_PPS=m |
| @@ -574,7 +582,6 @@ CONFIG_SYNC_FILE=y · 16 unmodified lines | ||
| 574 | 582 | CONFIG_VFIO=m |
| 575 | 583 | CONFIG_VFIO_PCI=m |
| 576 | 584 | CONFIG_VFIO_MDEV=m |
| 577 | −CONFIG_VFIO_MDEV_DEVICE=m | |
| 578 | 585 | CONFIG_VIRTIO_PCI=m |
| 579 | 586 | CONFIG_VIRTIO_BALLOON=m |
| 580 | 587 | CONFIG_VIRTIO_INPUT=y |
| @@ -619,6 +626,7 @@ CONFIG_FUSE_FS=y · 38 unmodified lines | ||
| 619 | 626 | CONFIG_CUSE=m |
| 620 | 627 | CONFIG_VIRTIO_FS=m |
| 621 | 628 | CONFIG_OVERLAY_FS=m |
| 629 | +CONFIG_NETFS_STATS=y | |
| 622 | 630 | CONFIG_FSCACHE=m |
| 623 | 631 | CONFIG_CACHEFILES=m |
| 624 | 632 | CONFIG_ISO9660_FS=y |
| @@ -654,7 +662,6 @@ CONFIG_NFSD_V3_ACL=y · 29 unmodified lines | ||
| 654 | 662 | CONFIG_NFSD_V4=y |
| 655 | 663 | CONFIG_NFSD_V4_SECURITY_LABEL=y |
| 656 | 664 | CONFIG_CIFS=m |
| 657 | −CONFIG_CIFS_STATS2=y | |
| 658 | 665 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 659 | 666 | CONFIG_CIFS_UPCALL=y |
| 660 | 667 | CONFIG_CIFS_XATTR=y |
| @@ -682,6 +689,7 @@ CONFIG_SECURITY_SELINUX_BOOTPARAM=y · 21 unmodified lines | ||
| 682 | 689 | CONFIG_SECURITY_SELINUX_DISABLE=y |
| 683 | 690 | CONFIG_SECURITY_LOCKDOWN_LSM=y |
| 684 | 691 | CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y |
| 692 | +CONFIG_SECURITY_LANDLOCK=y | |
| 685 | 693 | CONFIG_INTEGRITY_SIGNATURE=y |
| 686 | 694 | CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y |
| 687 | 695 | CONFIG_IMA=y |
| @@ -696,6 +704,7 @@ CONFIG_CRYPTO_CRYPTD=m · 8 unmodified lines | ||
| 696 | 704 | CONFIG_CRYPTO_TEST=m |
| 697 | 705 | CONFIG_CRYPTO_DH=m |
| 698 | 706 | CONFIG_CRYPTO_ECDH=m |
| 707 | +CONFIG_CRYPTO_ECDSA=m | |
| 699 | 708 | CONFIG_CRYPTO_ECRDSA=m |
| 700 | 709 | CONFIG_CRYPTO_SM2=m |
| 701 | 710 | CONFIG_CRYPTO_CURVE25519=m |
| @@ -843,7 +852,6 @@ CONFIG_FAULT_INJECTION_DEBUG_FS=y · 141 unmodified lines | ||
| 843 | 852 | CONFIG_FAIL_FUNCTION=y |
| 844 | 853 | CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y |
| 845 | 854 | CONFIG_LKDTM=m |
| 846 | −CONFIG_TEST_LIST_SORT=y | |
| 847 | 855 | CONFIG_TEST_MIN_HEAP=y |
| 848 | 856 | CONFIG_TEST_SORT=y |
| 849 | 857 | CONFIG_KPROBES_SANITY_TEST=y |
| @@ -853,3 +861,4 @@ CONFIG_PERCPU_TEST=m · 3 unmodified lines | ||
| 853 | 861 | CONFIG_ATOMIC64_SELFTEST=y |
| 854 | 862 | CONFIG_TEST_BITOPS=m |
| 855 | 863 | CONFIG_TEST_BPF=m |
| 864 | +CONFIG_TEST_LIVEPATCH=m | |
| @@ -4,6 +4,11 @@ CONFIG_WATCH_QUEUE=y · 3 unmodified lines | ||
| 4 | 4 | CONFIG_AUDIT=y |
| 5 | 5 | CONFIG_NO_HZ_IDLE=y |
| 6 | 6 | CONFIG_HIGH_RES_TIMERS=y |
| 7 | +CONFIG_BPF_SYSCALL=y | |
| 8 | +CONFIG_BPF_JIT=y | |
| 9 | +CONFIG_BPF_JIT_ALWAYS_ON=y | |
| 10 | +CONFIG_BPF_LSM=y | |
| 11 | +CONFIG_SCHED_CORE=y | |
| 7 | 12 | CONFIG_BSD_PROCESS_ACCT=y |
| 8 | 13 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 9 | 14 | CONFIG_TASKSTATS=y |
| @@ -26,14 +31,13 @@ CONFIG_CGROUP_DEVICE=y · 16 unmodified lines | ||
| 26 | 31 | CONFIG_CGROUP_CPUACCT=y |
| 27 | 32 | CONFIG_CGROUP_PERF=y |
| 28 | 33 | CONFIG_CGROUP_BPF=y |
| 34 | +CONFIG_CGROUP_MISC=y | |
| 29 | 35 | CONFIG_NAMESPACES=y |
| 30 | 36 | CONFIG_USER_NS=y |
| 31 | 37 | CONFIG_CHECKPOINT_RESTORE=y |
| 32 | 38 | CONFIG_SCHED_AUTOGROUP=y |
| 33 | 39 | CONFIG_EXPERT=y |
| 34 | 40 | # CONFIG_SYSFS_SYSCALL is not set |
| 35 | −CONFIG_BPF_LSM=y | |
| 36 | −CONFIG_BPF_SYSCALL=y | |
| 37 | 41 | CONFIG_USERFAULTFD=y |
| 38 | 42 | # CONFIG_COMPAT_BRK is not set |
| 39 | 43 | CONFIG_PROFILING=y |
| @@ -70,6 +74,7 @@ CONFIG_BLK_DEV_THROTTLING=y · 30 unmodified lines | ||
| 70 | 74 | CONFIG_BLK_WBT=y |
| 71 | 75 | CONFIG_BLK_CGROUP_IOLATENCY=y |
| 72 | 76 | CONFIG_BLK_CGROUP_IOCOST=y |
| 77 | +CONFIG_BLK_CGROUP_IOPRIO=y | |
| 73 | 78 | CONFIG_BLK_INLINE_ENCRYPTION=y |
| 74 | 79 | CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y |
| 75 | 80 | CONFIG_PARTITION_ADVANCED=y |
| @@ -87,6 +92,7 @@ CONFIG_KSM=y · 11 unmodified lines | ||
| 87 | 92 | CONFIG_TRANSPARENT_HUGEPAGE=y |
| 88 | 93 | CONFIG_CLEANCACHE=y |
| 89 | 94 | CONFIG_FRONTSWAP=y |
| 95 | +CONFIG_CMA_SYSFS=y | |
| 90 | 96 | CONFIG_CMA_AREAS=7 |
| 91 | 97 | CONFIG_MEM_SOFT_DIRTY=y |
| 92 | 98 | CONFIG_ZSWAP=y |
| @@ -149,6 +155,7 @@ CONFIG_IPV6_RPL_LWTUNNEL=y · 56 unmodified lines | ||
| 149 | 155 | CONFIG_MPTCP=y |
| 150 | 156 | CONFIG_NETFILTER=y |
| 151 | 157 | CONFIG_BRIDGE_NETFILTER=m |
| 158 | +CONFIG_NETFILTER_NETLINK_HOOK=m | |
| 152 | 159 | CONFIG_NF_CONNTRACK=m |
| 153 | 160 | CONFIG_NF_CONNTRACK_SECMARK=y |
| 154 | 161 | CONFIG_NF_CONNTRACK_EVENTS=y |
| @@ -271,6 +278,7 @@ CONFIG_IP_VS_FTP=m · 116 unmodified lines | ||
| 271 | 278 | CONFIG_IP_VS_PE_SIP=m |
| 272 | 279 | CONFIG_NFT_FIB_IPV4=m |
| 273 | 280 | CONFIG_NF_TABLES_ARP=y |
| 281 | +CONFIG_NF_LOG_IPV4=m | |
| 274 | 282 | CONFIG_IP_NF_IPTABLES=m |
| 275 | 283 | CONFIG_IP_NF_MATCH_AH=m |
| 276 | 284 | CONFIG_IP_NF_MATCH_ECN=m |
| @@ -317,7 +325,7 @@ CONFIG_L2TP_DEBUGFS=m · 40 unmodified lines | ||
| 317 | 325 | CONFIG_L2TP_V3=y |
| 318 | 326 | CONFIG_L2TP_IP=m |
| 319 | 327 | CONFIG_L2TP_ETH=m |
| 320 | −CONFIG_BRIDGE=m | |
| 328 | +CONFIG_BRIDGE=y | |
| 321 | 329 | CONFIG_BRIDGE_MRP=y |
| 322 | 330 | CONFIG_VLAN_8021Q=m |
| 323 | 331 | CONFIG_VLAN_8021Q_GVRP=y |
| @@ -374,11 +382,10 @@ CONFIG_VSOCKETS=m · 50 unmodified lines | ||
| 374 | 382 | CONFIG_VIRTIO_VSOCKETS=m |
| 375 | 383 | CONFIG_NETLINK_DIAG=m |
| 376 | 384 | CONFIG_CGROUP_NET_PRIO=y |
| 377 | −CONFIG_BPF_JIT=y | |
| 378 | 385 | CONFIG_NET_PKTGEN=m |
| 379 | 386 | CONFIG_PCI=y |
| 380 | −CONFIG_PCI_IOV=y | |
| 381 | 387 | # CONFIG_PCIEASPM is not set |
| 388 | +CONFIG_PCI_IOV=y | |
| 382 | 389 | CONFIG_HOTPLUG_PCI=y |
| 383 | 390 | CONFIG_HOTPLUG_PCI_S390=y |
| 384 | 391 | CONFIG_UEVENT_HELPER=y |
| @@ -427,7 +434,7 @@ CONFIG_MD_MULTIPATH=m · 42 unmodified lines | ||
| 427 | 434 | CONFIG_MD_FAULTY=m |
| 428 | 435 | CONFIG_MD_CLUSTER=m |
| 429 | 436 | CONFIG_BCACHE=m |
| 430 | −CONFIG_BLK_DEV_DM=m | |
| 437 | +CONFIG_BLK_DEV_DM=y | |
| 431 | 438 | CONFIG_DM_UNSTRIPED=m |
| 432 | 439 | CONFIG_DM_CRYPT=m |
| 433 | 440 | CONFIG_DM_SNAPSHOT=m |
| @@ -444,6 +451,7 @@ CONFIG_DM_MULTIPATH_ST=m · 10 unmodified lines | ||
| 444 | 451 | CONFIG_DM_MULTIPATH_HST=m |
| 445 | 452 | CONFIG_DM_MULTIPATH_IOA=m |
| 446 | 453 | CONFIG_DM_DELAY=m |
| 454 | +CONFIG_DM_INIT=y | |
| 447 | 455 | CONFIG_DM_UEVENT=y |
| 448 | 456 | CONFIG_DM_FLAKEY=m |
| 449 | 457 | CONFIG_DM_VERITY=m |
| @@ -487,6 +495,7 @@ CONFIG_NLMON=m · 37 unmodified lines | ||
| 487 | 495 | # CONFIG_NET_VENDOR_GOOGLE is not set |
| 488 | 496 | # CONFIG_NET_VENDOR_HUAWEI is not set |
| 489 | 497 | # CONFIG_NET_VENDOR_INTEL is not set |
| 498 | +# CONFIG_NET_VENDOR_MICROSOFT is not set | |
| 490 | 499 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 491 | 500 | CONFIG_MLX4_EN=m |
| 492 | 501 | CONFIG_MLX5_CORE=m |
| @@ -543,7 +552,6 @@ CONFIG_INPUT_EVDEV=y · 50 unmodified lines | ||
| 543 | 552 | CONFIG_LEGACY_PTY_COUNT=0 |
| 544 | 553 | CONFIG_VIRTIO_CONSOLE=m |
| 545 | 554 | CONFIG_HW_RANDOM_VIRTIO=m |
| 546 | −CONFIG_RAW_DRIVER=m | |
| 547 | 555 | CONFIG_HANGCHECK_TIMER=m |
| 548 | 556 | CONFIG_TN3270_FS=y |
| 549 | 557 | # CONFIG_PTP_1588_CLOCK is not set |
| @@ -566,7 +574,6 @@ CONFIG_SYNC_FILE=y · 16 unmodified lines | ||
| 566 | 574 | CONFIG_VFIO=m |
| 567 | 575 | CONFIG_VFIO_PCI=m |
| 568 | 576 | CONFIG_VFIO_MDEV=m |
| 569 | −CONFIG_VFIO_MDEV_DEVICE=m | |
| 570 | 577 | CONFIG_VIRTIO_PCI=m |
| 571 | 578 | CONFIG_VIRTIO_BALLOON=m |
| 572 | 579 | CONFIG_VIRTIO_INPUT=y |
| @@ -607,6 +614,7 @@ CONFIG_FUSE_FS=y · 34 unmodified lines | ||
| 607 | 614 | CONFIG_CUSE=m |
| 608 | 615 | CONFIG_VIRTIO_FS=m |
| 609 | 616 | CONFIG_OVERLAY_FS=m |
| 617 | +CONFIG_NETFS_STATS=y | |
| 610 | 618 | CONFIG_FSCACHE=m |
| 611 | 619 | CONFIG_CACHEFILES=m |
| 612 | 620 | CONFIG_ISO9660_FS=y |
| @@ -642,7 +650,6 @@ CONFIG_NFSD_V3_ACL=y · 29 unmodified lines | ||
| 642 | 650 | CONFIG_NFSD_V4=y |
| 643 | 651 | CONFIG_NFSD_V4_SECURITY_LABEL=y |
| 644 | 652 | CONFIG_CIFS=m |
| 645 | −CONFIG_CIFS_STATS2=y | |
| 646 | 653 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 647 | 654 | CONFIG_CIFS_UPCALL=y |
| 648 | 655 | CONFIG_CIFS_XATTR=y |
| @@ -669,6 +676,7 @@ CONFIG_SECURITY_SELINUX_BOOTPARAM=y · 20 unmodified lines | ||
| 669 | 676 | CONFIG_SECURITY_SELINUX_DISABLE=y |
| 670 | 677 | CONFIG_SECURITY_LOCKDOWN_LSM=y |
| 671 | 678 | CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y |
| 679 | +CONFIG_SECURITY_LANDLOCK=y | |
| 672 | 680 | CONFIG_INTEGRITY_SIGNATURE=y |
| 673 | 681 | CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y |
| 674 | 682 | CONFIG_IMA=y |
| @@ -684,6 +692,7 @@ CONFIG_CRYPTO_CRYPTD=m · 9 unmodified lines | ||
| 684 | 692 | CONFIG_CRYPTO_TEST=m |
| 685 | 693 | CONFIG_CRYPTO_DH=m |
| 686 | 694 | CONFIG_CRYPTO_ECDH=m |
| 695 | +CONFIG_CRYPTO_ECDSA=m | |
| 687 | 696 | CONFIG_CRYPTO_ECRDSA=m |
| 688 | 697 | CONFIG_CRYPTO_SM2=m |
| 689 | 698 | CONFIG_CRYPTO_CURVE25519=m |
| @@ -754,6 +763,7 @@ CONFIG_CRC8=m · 64 unmodified lines | ||
| 754 | 763 | CONFIG_DMA_CMA=y |
| 755 | 764 | CONFIG_CMA_SIZE_MBYTES=0 |
| 756 | 765 | CONFIG_PRINTK_TIME=y |
| 766 | +CONFIG_DYNAMIC_DEBUG=y | |
| 757 | 767 | CONFIG_DEBUG_INFO=y |
| 758 | 768 | CONFIG_DEBUG_INFO_DWARF4=y |
| 759 | 769 | CONFIG_GDB_SCRIPTS=y |
| @@ -781,3 +791,4 @@ CONFIG_LKDTM=m · 21 unmodified lines | ||
| 781 | 791 | CONFIG_PERCPU_TEST=m |
| 782 | 792 | CONFIG_ATOMIC64_SELFTEST=y |
| 783 | 793 | CONFIG_TEST_BPF=m |
| 794 | +CONFIG_TEST_LIVEPATCH=m | |
| @@ -29,9 +29,9 @@ CONFIG_PARTITION_ADVANCED=y · 28 unmodified lines | ||
| 29 | 29 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 30 | 30 | # CONFIG_COMPACTION is not set |
| 31 | 31 | # CONFIG_MIGRATION is not set |
| 32 | −# CONFIG_BOUNCE is not set | |
| 33 | 32 | CONFIG_NET=y |
| 34 | 33 | # CONFIG_IUCV is not set |
| 34 | +# CONFIG_PCPU_DEV_REFCNT is not set | |
| 35 | 35 | # CONFIG_ETHTOOL_NETLINK is not set |
| 36 | 36 | CONFIG_DEVTMPFS=y |
| 37 | 37 | CONFIG_BLK_DEV_RAM=y |
| @@ -51,7 +51,6 @@ CONFIG_ZFCP=y · 13 unmodified lines | ||
| 51 | 51 | # CONFIG_SERIO is not set |
| 52 | 52 | # CONFIG_HVC_IUCV is not set |
| 53 | 53 | # CONFIG_HW_RANDOM_S390 is not set |
| 54 | −CONFIG_RAW_DRIVER=y | |
| 55 | 54 | # CONFIG_HMC_DRV is not set |
| 56 | 55 | # CONFIG_S390_TAPE is not set |
| 57 | 56 | # CONFIG_VMCP is not set |
| @@ -19,6 +19,7 @@ void ftrace_caller(void); · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | extern char ftrace_graph_caller_end; |
| 21 | 21 | extern unsigned long ftrace_plt; |
| 22 | +extern void *ftrace_func; | |
| 22 | 23 | |
| 23 | 24 | struct dyn_arch_ftrace { }; |
| 24 | 25 | |
| @@ -445,15 +445,15 @@ struct kvm_vcpu_stat { · 444 unmodified lines | ||
| 445 | 445 | u64 instruction_sigp_init_cpu_reset; |
| 446 | 446 | u64 instruction_sigp_cpu_reset; |
| 447 | 447 | u64 instruction_sigp_unknown; |
| 448 | − u64 diagnose_10; | |
| 449 | − u64 diagnose_44; | |
| 450 | − u64 diagnose_9c; | |
| 451 | − u64 diagnose_9c_ignored; | |
| 452 | − u64 diagnose_9c_forward; | |
| 453 | − u64 diagnose_258; | |
| 454 | − u64 diagnose_308; | |
| 455 | − u64 diagnose_500; | |
| 456 | − u64 diagnose_other; | |
| 448 | + u64 instruction_diagnose_10; | |
| 449 | + u64 instruction_diagnose_44; | |
| 450 | + u64 instruction_diagnose_9c; | |
| 451 | + u64 diag_9c_ignored; | |
| 452 | + u64 diag_9c_forward; | |
| 453 | + u64 instruction_diagnose_258; | |
| 454 | + u64 instruction_diagnose_308; | |
| 455 | + u64 instruction_diagnose_500; | |
| 456 | + u64 instruction_diagnose_other; | |
| 457 | 457 | u64 pfault_sync; |
| 458 | 458 | }; |
| 459 | 459 | |
| @@ -40,6 +40,7 @@ · 39 unmodified lines | ||
| 40 | 40 | * trampoline (ftrace_plt), which clobbers also r1. |
| 41 | 41 | */ |
| 42 | 42 | |
| 43 | +void *ftrace_func __read_mostly = ftrace_stub; | |
| 43 | 44 | unsigned long ftrace_plt; |
| 44 | 45 | |
| 45 | 46 | int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr, |
| @@ -85,6 +86,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) · 39 unmodified lines | ||
| 85 | 86 | |
| 86 | 87 | int ftrace_update_ftrace_func(ftrace_func_t func) |
| 87 | 88 | { |
| 89 | + ftrace_func = func; | |
| 88 | 90 | return 0; |
| 89 | 91 | } |
| 90 | 92 | |
| @@ -59,13 +59,13 @@ ENTRY(ftrace_caller) · 58 unmodified lines | ||
| 59 | 59 | #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES |
| 60 | 60 | aghik %r2,%r0,-MCOUNT_INSN_SIZE |
| 61 | 61 | lgrl %r4,function_trace_op |
| 62 | − lgrl %r1,ftrace_trace_function | |
| 62 | + lgrl %r1,ftrace_func | |
| 63 | 63 | #else |
| 64 | 64 | lgr %r2,%r0 |
| 65 | 65 | aghi %r2,-MCOUNT_INSN_SIZE |
| 66 | 66 | larl %r4,function_trace_op |
| 67 | 67 | lg %r4,0(%r4) |
| 68 | − larl %r1,ftrace_trace_function | |
| 68 | + larl %r1,ftrace_func | |
| 69 | 69 | lg %r1,0(%r1) |
| 70 | 70 | #endif |
| 71 | 71 | lgr %r3,%r14 |
| @@ -745,7 +745,7 @@ static int __init cpumf_pmu_init(void) · 744 unmodified lines | ||
| 745 | 745 | if (!cf_dbg) { |
| 746 | 746 | pr_err("Registration of s390dbf(cpum_cf) failed\n"); |
| 747 | 747 | return -ENOMEM; |
| 748 | − }; | |
| 748 | + } | |
| 749 | 749 | debug_register_view(cf_dbg, &debug_sprintf_view); |
| 750 | 750 | |
| 751 | 751 | cpumf_pmu.attr_groups = cpumf_cf_event_group(); |
| @@ -126,6 +126,7 @@ int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, · 125 unmodified lines | ||
| 126 | 126 | case DIE_SSTEP: |
| 127 | 127 | if (uprobe_post_sstep_notifier(regs)) |
| 128 | 128 | return NOTIFY_STOP; |
| 129 | + break; | |
| 129 | 130 | default: |
| 130 | 131 | break; |
| 131 | 132 | } |
| @@ -29,6 +29,7 @@ $(targets:%=$(obj)/%.dbg): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32) · 28 unmodified lines | ||
| 29 | 29 | $(targets:%=$(obj)/%.dbg): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32) |
| 30 | 30 | |
| 31 | 31 | obj-y += vdso32_wrapper.o |
| 32 | +targets += vdso32.lds | |
| 32 | 33 | CPPFLAGS_vdso32.lds += -P -C -U$(ARCH) |
| 33 | 34 | |
| 34 | 35 | # Disable gcov profiling, ubsan and kasan for VDSO code |
| @@ -51,6 +51,7 @@ SECTIONS · 50 unmodified lines | ||
| 51 | 51 | |
| 52 | 52 | .rela.dyn ALIGN(8) : { *(.rela.dyn) } |
| 53 | 53 | .got ALIGN(8) : { *(.got .toc) } |
| 54 | + .got.plt ALIGN(8) : { *(.got.plt) } | |
| 54 | 55 | |
| 55 | 56 | _end = .; |
| 56 | 57 | PROVIDE(end = .); |
| @@ -51,6 +51,7 @@ SECTIONS · 50 unmodified lines | ||
| 51 | 51 | |
| 52 | 52 | .rela.dyn ALIGN(8) : { *(.rela.dyn) } |
| 53 | 53 | .got ALIGN(8) : { *(.got .toc) } |
| 54 | + .got.plt ALIGN(8) : { *(.got.plt) } | |
| 54 | 55 | |
| 55 | 56 | _end = .; |
| 56 | 57 | PROVIDE(end = .); |
| @@ -24,7 +24,7 @@ static int diag_release_pages(struct kvm_vcpu *vcpu) · 23 unmodified lines | ||
| 24 | 24 | |
| 25 | 25 | start = vcpu->run->s.regs.gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4]; |
| 26 | 26 | end = vcpu->run->s.regs.gprs[vcpu->arch.sie_block->ipa & 0xf] + PAGE_SIZE; |
| 27 | − vcpu->stat.diagnose_10++; | |
| 27 | + vcpu->stat.instruction_diagnose_10++; | |
| 28 | 28 | |
| 29 | 29 | if (start & ~PAGE_MASK || end & ~PAGE_MASK || start >= end |
| 30 | 30 | || start < 2 * PAGE_SIZE) |
| @@ -74,7 +74,7 @@ static int __diag_page_ref_service(struct kvm_vcpu *vcpu) · 43 unmodified lines | ||
| 74 | 74 | |
| 75 | 75 | VCPU_EVENT(vcpu, 3, "diag page reference parameter block at 0x%llx", |
| 76 | 76 | vcpu->run->s.regs.gprs[rx]); |
| 77 | − vcpu->stat.diagnose_258++; | |
| 77 | + vcpu->stat.instruction_diagnose_258++; | |
| 78 | 78 | if (vcpu->run->s.regs.gprs[rx] & 7) |
| 79 | 79 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
| 80 | 80 | rc = read_guest(vcpu, vcpu->run->s.regs.gprs[rx], rx, &parm, sizeof(parm)); |
| @@ -145,7 +145,7 @@ static int __diag_page_ref_service(struct kvm_vcpu *vcpu) · 64 unmodified lines | ||
| 145 | 145 | static int __diag_time_slice_end(struct kvm_vcpu *vcpu) |
| 146 | 146 | { |
| 147 | 147 | VCPU_EVENT(vcpu, 5, "%s", "diag time slice end"); |
| 148 | − vcpu->stat.diagnose_44++; | |
| 148 | + vcpu->stat.instruction_diagnose_44++; | |
| 149 | 149 | kvm_vcpu_on_spin(vcpu, true); |
| 150 | 150 | return 0; |
| 151 | 151 | } |
| @@ -169,7 +169,7 @@ static int __diag_time_slice_end_directed(struct kvm_vcpu *vcpu) · 17 unmodified lines | ||
| 169 | 169 | int tid; |
| 170 | 170 | |
| 171 | 171 | tid = vcpu->run->s.regs.gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4]; |
| 172 | − vcpu->stat.diagnose_9c++; | |
| 172 | + vcpu->stat.instruction_diagnose_9c++; | |
| 173 | 173 | |
| 174 | 174 | /* yield to self */ |
| 175 | 175 | if (tid == vcpu->vcpu_id) |
| @@ -192,7 +192,7 @@ static int __diag_time_slice_end_directed(struct kvm_vcpu *vcpu) · 16 unmodified lines | ||
| 192 | 192 | VCPU_EVENT(vcpu, 5, |
| 193 | 193 | "diag time slice end directed to %d: yield forwarded", |
| 194 | 194 | tid); |
| 195 | − vcpu->stat.diagnose_9c_forward++; | |
| 195 | + vcpu->stat.diag_9c_forward++; | |
| 196 | 196 | return 0; |
| 197 | 197 | } |
| 198 | 198 | |
| @@ -203,7 +203,7 @@ static int __diag_time_slice_end_directed(struct kvm_vcpu *vcpu) · 4 unmodified lines | ||
| 203 | 203 | return 0; |
| 204 | 204 | no_yield: |
| 205 | 205 | VCPU_EVENT(vcpu, 5, "diag time slice end directed to %d: ignored", tid); |
| 206 | − vcpu->stat.diagnose_9c_ignored++; | |
| 206 | + vcpu->stat.diag_9c_ignored++; | |
| 207 | 207 | return 0; |
| 208 | 208 | } |
| 209 | 209 | |
| @@ -213,7 +213,7 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu) · 3 unmodified lines | ||
| 213 | 213 | unsigned long subcode = vcpu->run->s.regs.gprs[reg] & 0xffff; |
| 214 | 214 | |
| 215 | 215 | VCPU_EVENT(vcpu, 3, "diag ipl functions, subcode %lx", subcode); |
| 216 | − vcpu->stat.diagnose_308++; | |
| 216 | + vcpu->stat.instruction_diagnose_308++; | |
| 217 | 217 | switch (subcode) { |
| 218 | 218 | case 3: |
| 219 | 219 | vcpu->run->s390_reset_flags = KVM_S390_RESET_CLEAR; |
| @@ -245,7 +245,7 @@ static int __diag_virtio_hypercall(struct kvm_vcpu *vcpu) · 25 unmodified lines | ||
| 245 | 245 | { |
| 246 | 246 | int ret; |
| 247 | 247 | |
| 248 | − vcpu->stat.diagnose_500++; | |
| 248 | + vcpu->stat.instruction_diagnose_500++; | |
| 249 | 249 | /* No virtio-ccw notification? Get out quickly. */ |
| 250 | 250 | if (!vcpu->kvm->arch.css_support || |
| 251 | 251 | (vcpu->run->s.regs.gprs[1] != KVM_S390_VIRTIO_CCW_NOTIFY)) |
| @@ -299,7 +299,7 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu) · 47 unmodified lines | ||
| 299 | 299 | case 0x500: |
| 300 | 300 | return __diag_virtio_hypercall(vcpu); |
| 301 | 301 | default: |
| 302 | − vcpu->stat.diagnose_other++; | |
| 302 | + vcpu->stat.instruction_diagnose_other++; | |
| 303 | 303 | return -EOPNOTSUPP; |
| 304 | 304 | } |
| 305 | 305 | } |
| @@ -163,15 +163,15 @@ const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { · 162 unmodified lines | ||
| 163 | 163 | STATS_DESC_COUNTER(VCPU, instruction_sigp_init_cpu_reset), |
| 164 | 164 | STATS_DESC_COUNTER(VCPU, instruction_sigp_cpu_reset), |
| 165 | 165 | STATS_DESC_COUNTER(VCPU, instruction_sigp_unknown), |
| 166 | − STATS_DESC_COUNTER(VCPU, diagnose_10), | |
| 167 | − STATS_DESC_COUNTER(VCPU, diagnose_44), | |
| 168 | − STATS_DESC_COUNTER(VCPU, diagnose_9c), | |
| 169 | − STATS_DESC_COUNTER(VCPU, diagnose_9c_ignored), | |
| 170 | − STATS_DESC_COUNTER(VCPU, diagnose_9c_forward), | |
| 171 | − STATS_DESC_COUNTER(VCPU, diagnose_258), | |
| 172 | − STATS_DESC_COUNTER(VCPU, diagnose_308), | |
| 173 | − STATS_DESC_COUNTER(VCPU, diagnose_500), | |
| 174 | − STATS_DESC_COUNTER(VCPU, diagnose_other), | |
| 166 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_10), | |
| 167 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_44), | |
| 168 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_9c), | |
| 169 | + STATS_DESC_COUNTER(VCPU, diag_9c_ignored), | |
| 170 | + STATS_DESC_COUNTER(VCPU, diag_9c_forward), | |
| 171 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_258), | |
| 172 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_308), | |
| 173 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_500), | |
| 174 | + STATS_DESC_COUNTER(VCPU, instruction_diagnose_other), | |
| 175 | 175 | STATS_DESC_COUNTER(VCPU, pfault_sync) |
| 176 | 176 | }; |
| 177 | 177 | static_assert(ARRAY_SIZE(kvm_vcpu_stats_desc) == |
| @@ -112,7 +112,7 @@ static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) · 111 unmodified lines | ||
| 112 | 112 | { |
| 113 | 113 | u32 r1 = reg2hex[b1]; |
| 114 | 114 | |
| 115 | − if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) | |
| 115 | + if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1]) | |
| 116 | 116 | jit->seen_reg[r1] = 1; |
| 117 | 117 | } |
| 118 | 118 | |
| @@ -1153,6 +1153,11 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, · 1034 unmodified lines | ||
| 1153 | 1153 | break; |
| 1154 | 1154 | } |
| 1155 | 1155 | break; |
| 1156 | + /* | |
| 1157 | + * BPF_NOSPEC (speculation barrier) | |
| 1158 | + */ | |
| 1159 | + case BPF_ST | BPF_NOSPEC: | |
| 1160 | + break; | |
| 1156 | 1161 | /* |
| 1157 | 1162 | * BPF_ST(X) |
| 1158 | 1163 | */ |
| @@ -560,9 +560,12 @@ static void zpci_cleanup_bus_resources(struct zpci_dev *zdev) · 559 unmodified lines | ||
| 560 | 560 | |
| 561 | 561 | int pcibios_add_device(struct pci_dev *pdev) |
| 562 | 562 | { |
| 563 | + struct zpci_dev *zdev = to_zpci(pdev); | |
| 563 | 564 | struct resource *res; |
| 564 | 565 | int i; |
| 565 | 566 | |
| 567 | + /* The pdev has a reference to the zdev via its bus */ | |
| 568 | + zpci_zdev_get(zdev); | |
| 566 | 569 | if (pdev->is_physfn) |
| 567 | 570 | pdev->no_vf_scan = 1; |
| 568 | 571 | |
| @@ -582,7 +585,10 @@ int pcibios_add_device(struct pci_dev *pdev) · 13 unmodified lines | ||
| 582 | 585 | |
| 583 | 586 | void pcibios_release_device(struct pci_dev *pdev) |
| 584 | 587 | { |
| 588 | + struct zpci_dev *zdev = to_zpci(pdev); | |
| 589 | + | |
| 585 | 590 | zpci_unmap_resources(pdev); |
| 591 | + zpci_zdev_put(zdev); | |
| 586 | 592 | } |
| 587 | 593 | |
| 588 | 594 | int pcibios_enable_device(struct pci_dev *pdev, int mask) |
| @@ -22,6 +22,11 @@ static inline void zpci_zdev_put(struct zpci_dev *zdev) · 21 unmodified lines | ||
| 22 | 22 | kref_put(&zdev->kref, zpci_release_device); |
| 23 | 23 | } |
| 24 | 24 | |
| 25 | +static inline void zpci_zdev_get(struct zpci_dev *zdev) | |
| 26 | +{ | |
| 27 | + kref_get(&zdev->kref); | |
| 28 | +} | |
| 29 | + | |
| 25 | 30 | int zpci_alloc_domain(int domain); |
| 26 | 31 | void zpci_free_domain(int domain); |
| 27 | 32 | int zpci_setup_bus_resources(struct zpci_dev *zdev, |
| @@ -39,7 +39,6 @@ config SUPERH · 38 unmodified lines | ||
| 39 | 39 | select HAVE_FUTEX_CMPXCHG if FUTEX |
| 40 | 40 | select HAVE_FTRACE_MCOUNT_RECORD |
| 41 | 41 | select HAVE_HW_BREAKPOINT |
| 42 | − select HAVE_IDE if HAS_IOPORT_MAP | |
| 43 | 42 | select HAVE_IOREMAP_PROT if MMU && !X2TLB |
| 44 | 43 | select HAVE_KERNEL_BZIP2 |
| 45 | 44 | select HAVE_KERNEL_GZIP |
| @@ -19,7 +19,6 @@ config SPARC · 18 unmodified lines | ||
| 19 | 19 | select OF |
| 20 | 20 | select OF_PROMTREE |
| 21 | 21 | select HAVE_ASM_MODVERSIONS |
| 22 | − select HAVE_IDE | |
| 23 | 22 | select HAVE_ARCH_KGDB if !SMP || SPARC64 |
| 24 | 23 | select HAVE_ARCH_TRACEHOOK |
| 25 | 24 | select HAVE_ARCH_SECCOMP if SPARC64 |
| @@ -1287,6 +1287,9 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) · 1286 unmodified lines | ||
| 1287 | 1287 | return 1; |
| 1288 | 1288 | break; |
| 1289 | 1289 | } |
| 1290 | + /* speculation barrier */ | |
| 1291 | + case BPF_ST | BPF_NOSPEC: | |
| 1292 | + break; | |
| 1290 | 1293 | /* ST: *(size *)(dst + off) = imm */ |
| 1291 | 1294 | case BPF_ST | BPF_MEM | BPF_W: |
| 1292 | 1295 | case BPF_ST | BPF_MEM | BPF_H: |
| @@ -202,7 +202,6 @@ config X86 · 201 unmodified lines | ||
| 202 | 202 | select HAVE_FUNCTION_TRACER |
| 203 | 203 | select HAVE_GCC_PLUGINS |
| 204 | 204 | select HAVE_HW_BREAKPOINT |
| 205 | − select HAVE_IDE | |
| 206 | 205 | select HAVE_IOREMAP_PROT |
| 207 | 206 | select HAVE_IRQ_EXIT_ON_IRQ_STACK if X86_64 |
| 208 | 207 | select HAVE_IRQ_TIME_ACCOUNTING |
| @@ -2489,13 +2489,15 @@ void perf_clear_dirty_counters(void) · 2488 unmodified lines | ||
| 2489 | 2489 | return; |
| 2490 | 2490 | |
| 2491 | 2491 | for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) { |
| 2492 | − /* Metrics and fake events don't have corresponding HW counters. */ | |
| 2493 | − if (is_metric_idx(i) || (i == INTEL_PMC_IDX_FIXED_VLBR)) | |
| 2494 | − continue; | |
| 2495 | − else if (i >= INTEL_PMC_IDX_FIXED) | |
| 2492 | + if (i >= INTEL_PMC_IDX_FIXED) { | |
| 2493 | + /* Metrics and fake events don't have corresponding HW counters. */ | |
| 2494 | + if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed)) | |
| 2495 | + continue; | |
| 2496 | + | |
| 2496 | 2497 | wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0); |
| 2497 | − else | |
| 2498 | + } else { | |
| 2498 | 2499 | wrmsrl(x86_pmu_event_addr(i), 0); |
| 2500 | + } | |
| 2499 | 2501 | } |
| 2500 | 2502 | |
| 2501 | 2503 | bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX); |
| @@ -2904,24 +2904,28 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) · 2903 unmodified lines | ||
| 2904 | 2904 | */ |
| 2905 | 2905 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
| 2906 | 2906 | { |
| 2907 | − struct cpu_hw_events *cpuc; | |
| 2907 | + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
| 2908 | + bool late_ack = hybrid_bit(cpuc->pmu, late_ack); | |
| 2909 | + bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); | |
| 2908 | 2910 | int loops; |
| 2909 | 2911 | u64 status; |
| 2910 | 2912 | int handled; |
| 2911 | 2913 | int pmu_enabled; |
| 2912 | 2914 | |
| 2913 | − cpuc = this_cpu_ptr(&cpu_hw_events); | |
| 2914 | − | |
| 2915 | 2915 | /* |
| 2916 | 2916 | * Save the PMU state. |
| 2917 | 2917 | * It needs to be restored when leaving the handler. |
| 2918 | 2918 | */ |
| 2919 | 2919 | pmu_enabled = cpuc->enabled; |
| 2920 | 2920 | /* |
| 2921 | − * No known reason to not always do late ACK, | |
| 2922 | − * but just in case do it opt-in. | |
| 2921 | + * In general, the early ACK is only applied for old platforms. | |
| 2922 | + * For the big core starts from Haswell, the late ACK should be | |
| 2923 | + * applied. | |
| 2924 | + * For the small core after Tremont, we have to do the ACK right | |
| 2925 | + * before re-enabling counters, which is in the middle of the | |
| 2926 | + * NMI handler. | |
| 2923 | 2927 | */ |
| 2924 | − if (!x86_pmu.late_ack) | |
| 2928 | + if (!late_ack && !mid_ack) | |
| 2925 | 2929 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 2926 | 2930 | intel_bts_disable_local(); |
| 2927 | 2931 | cpuc->enabled = 0; |
| @@ -2958,6 +2962,8 @@ again: · 30 unmodified lines | ||
| 2958 | 2962 | goto again; |
| 2959 | 2963 | |
| 2960 | 2964 | done: |
| 2965 | + if (mid_ack) | |
| 2966 | + apic_write(APIC_LVTPC, APIC_DM_NMI); | |
| 2961 | 2967 | /* Only restore PMU state when it's active. See x86_pmu_disable(). */ |
| 2962 | 2968 | cpuc->enabled = pmu_enabled; |
| 2963 | 2969 | if (pmu_enabled) |
| @@ -2969,7 +2975,7 @@ done: · 5 unmodified lines | ||
| 2969 | 2975 | * have been reset. This avoids spurious NMIs on |
| 2970 | 2976 | * Haswell CPUs. |
| 2971 | 2977 | */ |
| 2972 | − if (x86_pmu.late_ack) | |
| 2978 | + if (late_ack) | |
| 2973 | 2979 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 2974 | 2980 | return handled; |
| 2975 | 2981 | } |
| @@ -6129,7 +6135,6 @@ __init int intel_pmu_init(void) · 3153 unmodified lines | ||
| 6129 | 6135 | static_branch_enable(&perf_is_hybrid); |
| 6130 | 6136 | x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; |
| 6131 | 6137 | |
| 6132 | − x86_pmu.late_ack = true; | |
| 6133 | 6138 | x86_pmu.pebs_aliases = NULL; |
| 6134 | 6139 | x86_pmu.pebs_prec_dist = true; |
| 6135 | 6140 | x86_pmu.pebs_block = true; |
| @@ -6167,6 +6172,7 @@ __init int intel_pmu_init(void) · 31 unmodified lines | ||
| 6167 | 6172 | pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; |
| 6168 | 6173 | pmu->name = "cpu_core"; |
| 6169 | 6174 | pmu->cpu_type = hybrid_big; |
| 6175 | + pmu->late_ack = true; | |
| 6170 | 6176 | if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { |
| 6171 | 6177 | pmu->num_counters = x86_pmu.num_counters + 2; |
| 6172 | 6178 | pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; |
| @@ -6192,6 +6198,7 @@ __init int intel_pmu_init(void) · 19 unmodified lines | ||
| 6192 | 6198 | pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; |
| 6193 | 6199 | pmu->name = "cpu_atom"; |
| 6194 | 6200 | pmu->cpu_type = hybrid_small; |
| 6201 | + pmu->mid_ack = true; | |
| 6195 | 6202 | pmu->num_counters = x86_pmu.num_counters; |
| 6196 | 6203 | pmu->num_counters_fixed = x86_pmu.num_counters_fixed; |
| 6197 | 6204 | pmu->max_pebs_events = x86_pmu.max_pebs_events; |
| @@ -656,6 +656,10 @@ struct x86_hybrid_pmu { · 655 unmodified lines | ||
| 656 | 656 | struct event_constraint *event_constraints; |
| 657 | 657 | struct event_constraint *pebs_constraints; |
| 658 | 658 | struct extra_reg *extra_regs; |
| 659 | + | |
| 660 | + unsigned int late_ack :1, | |
| 661 | + mid_ack :1, | |
| 662 | + enabled_ack :1; | |
| 659 | 663 | }; |
| 660 | 664 | |
| 661 | 665 | static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) |
| @@ -686,6 +690,16 @@ extern struct static_key_false perf_is_hybrid; · 24 unmodified lines | ||
| 686 | 690 | __Fp; \ |
| 687 | 691 | })) |
| 688 | 692 | |
| 693 | +#define hybrid_bit(_pmu, _field) \ | |
| 694 | +({ \ | |
| 695 | + bool __Fp = x86_pmu._field; \ | |
| 696 | + \ | |
| 697 | + if (is_hybrid() && (_pmu)) \ | |
| 698 | + __Fp = hybrid_pmu(_pmu)->_field; \ | |
| 699 | + \ | |
| 700 | + __Fp; \ | |
| 701 | +}) | |
| 702 | + | |
| 689 | 703 | enum hybrid_pmu_type { |
| 690 | 704 | hybrid_big = 0x40, |
| 691 | 705 | hybrid_small = 0x20, |
| @@ -755,6 +769,7 @@ struct x86_pmu { · 63 unmodified lines | ||
| 755 | 769 | |
| 756 | 770 | /* PMI handler bits */ |
| 757 | 771 | unsigned int late_ack :1, |
| 772 | + mid_ack :1, | |
| 758 | 773 | enabled_ack :1; |
| 759 | 774 | /* |
| 760 | 775 | * sysfs attrs |
| @@ -1115,9 +1130,10 @@ void x86_pmu_stop(struct perf_event *event, int flags); · 354 unmodified lines | ||
| 1115 | 1130 | |
| 1116 | 1131 | static inline void x86_pmu_disable_event(struct perf_event *event) |
| 1117 | 1132 | { |
| 1133 | + u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); | |
| 1118 | 1134 | struct hw_perf_event *hwc = &event->hw; |
| 1119 | 1135 | |
| 1120 | − wrmsrl(hwc->config_base, hwc->config); | |
| 1136 | + wrmsrl(hwc->config_base, hwc->config & ~disable_mask); | |
| 1121 | 1137 | |
| 1122 | 1138 | if (is_counter_pair(hwc)) |
| 1123 | 1139 | wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); |
| @@ -1038,6 +1038,13 @@ struct kvm_arch { · 1037 unmodified lines | ||
| 1038 | 1038 | struct list_head lpage_disallowed_mmu_pages; |
| 1039 | 1039 | struct kvm_page_track_notifier_node mmu_sp_tracker; |
| 1040 | 1040 | struct kvm_page_track_notifier_head track_notifier_head; |
| 1041 | + /* | |
| 1042 | + * Protects marking pages unsync during page faults, as TDP MMU page | |
| 1043 | + * faults only take mmu_lock for read. For simplicity, the unsync | |
| 1044 | + * pages lock is always taken when marking pages unsync regardless of | |
| 1045 | + * whether mmu_lock is held for read or write. | |
| 1046 | + */ | |
| 1047 | + spinlock_t mmu_unsync_pages_lock; | |
| 1041 | 1048 | |
| 1042 | 1049 | struct list_head assigned_dev_head; |
| 1043 | 1050 | struct iommu_domain *iommu_domain; |
| @@ -184,6 +184,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area { · 183 unmodified lines | ||
| 184 | 184 | #define V_IGN_TPR_SHIFT 20 |
| 185 | 185 | #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) |
| 186 | 186 | |
| 187 | +#define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK) | |
| 188 | + | |
| 187 | 189 | #define V_INTR_MASKING_SHIFT 24 |
| 188 | 190 | #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) |
| 189 | 191 | |
| @@ -1986,7 +1986,8 @@ static struct irq_chip ioapic_chip __read_mostly = { · 1985 unmodified lines | ||
| 1986 | 1986 | .irq_set_affinity = ioapic_set_affinity, |
| 1987 | 1987 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 1988 | 1988 | .irq_get_irqchip_state = ioapic_irq_get_chip_state, |
| 1989 | − .flags = IRQCHIP_SKIP_SET_WAKE, | |
| 1989 | + .flags = IRQCHIP_SKIP_SET_WAKE | | |
| 1990 | + IRQCHIP_AFFINITY_PRE_STARTUP, | |
| 1990 | 1991 | }; |
| 1991 | 1992 | |
| 1992 | 1993 | static struct irq_chip ioapic_ir_chip __read_mostly = { |
| @@ -1999,7 +2000,8 @@ static struct irq_chip ioapic_ir_chip __read_mostly = { · 6 unmodified lines | ||
| 1999 | 2000 | .irq_set_affinity = ioapic_set_affinity, |
| 2000 | 2001 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 2001 | 2002 | .irq_get_irqchip_state = ioapic_irq_get_chip_state, |
| 2002 | − .flags = IRQCHIP_SKIP_SET_WAKE, | |
| 2003 | + .flags = IRQCHIP_SKIP_SET_WAKE | | |
| 2004 | + IRQCHIP_AFFINITY_PRE_STARTUP, | |
| 2003 | 2005 | }; |
| 2004 | 2006 | |
| 2005 | 2007 | static inline void init_IO_APIC_traps(void) |
| @@ -58,11 +58,13 @@ msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) · 57 unmodified lines | ||
| 58 | 58 | * The quirk bit is not set in this case. |
| 59 | 59 | * - The new vector is the same as the old vector |
| 60 | 60 | * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up) |
| 61 | + * - The interrupt is not yet started up | |
| 61 | 62 | * - The new destination CPU is the same as the old destination CPU |
| 62 | 63 | */ |
| 63 | 64 | if (!irqd_msi_nomask_quirk(irqd) || |
| 64 | 65 | cfg->vector == old_cfg.vector || |
| 65 | 66 | old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR || |
| 67 | + !irqd_is_started(irqd) || | |
| 66 | 68 | cfg->dest_apicid == old_cfg.dest_apicid) { |
| 67 | 69 | irq_msi_update_msg(irqd, cfg); |
| 68 | 70 | return ret; |
| @@ -150,7 +152,8 @@ static struct irq_chip pci_msi_controller = { · 81 unmodified lines | ||
| 150 | 152 | .irq_ack = irq_chip_ack_parent, |
| 151 | 153 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 152 | 154 | .irq_set_affinity = msi_set_affinity, |
| 153 | − .flags = IRQCHIP_SKIP_SET_WAKE, | |
| 155 | + .flags = IRQCHIP_SKIP_SET_WAKE | | |
| 156 | + IRQCHIP_AFFINITY_PRE_STARTUP, | |
| 154 | 157 | }; |
| 155 | 158 | |
| 156 | 159 | int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, |
| @@ -219,7 +222,8 @@ static struct irq_chip pci_msi_ir_controller = { · 62 unmodified lines | ||
| 219 | 222 | .irq_mask = pci_msi_mask_irq, |
| 220 | 223 | .irq_ack = irq_chip_ack_parent, |
| 221 | 224 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 222 | − .flags = IRQCHIP_SKIP_SET_WAKE, | |
| 225 | + .flags = IRQCHIP_SKIP_SET_WAKE | | |
| 226 | + IRQCHIP_AFFINITY_PRE_STARTUP, | |
| 223 | 227 | }; |
| 224 | 228 | |
| 225 | 229 | static struct msi_domain_info pci_msi_ir_domain_info = { |
| @@ -273,7 +277,8 @@ static struct irq_chip dmar_msi_controller = { · 47 unmodified lines | ||
| 273 | 277 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 274 | 278 | .irq_compose_msi_msg = dmar_msi_compose_msg, |
| 275 | 279 | .irq_write_msi_msg = dmar_msi_write_msg, |
| 276 | − .flags = IRQCHIP_SKIP_SET_WAKE, | |
| 280 | + .flags = IRQCHIP_SKIP_SET_WAKE | | |
| 281 | + IRQCHIP_AFFINITY_PRE_STARTUP, | |
| 277 | 282 | }; |
| 278 | 283 | |
| 279 | 284 | static int dmar_msi_init(struct irq_domain *domain, |
| @@ -237,7 +237,7 @@ static void __init hv_smp_prepare_cpus(unsigned int max_cpus) · 236 unmodified lines | ||
| 237 | 237 | for_each_present_cpu(i) { |
| 238 | 238 | if (i == 0) |
| 239 | 239 | continue; |
| 240 | − ret = hv_call_add_logical_proc(numa_cpu_node(i), i, i); | |
| 240 | + ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); | |
| 241 | 241 | BUG_ON(ret); |
| 242 | 242 | } |
| 243 | 243 | |
| @@ -285,15 +285,14 @@ static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr, unsigned int width) · 284 unmodified lines | ||
| 285 | 285 | return chunks >>= shift; |
| 286 | 286 | } |
| 287 | 287 | |
| 288 | −static int __mon_event_count(u32 rmid, struct rmid_read *rr) | |
| 288 | +static u64 __mon_event_count(u32 rmid, struct rmid_read *rr) | |
| 289 | 289 | { |
| 290 | 290 | struct mbm_state *m; |
| 291 | 291 | u64 chunks, tval; |
| 292 | 292 | |
| 293 | 293 | tval = __rmid_read(rmid, rr->evtid); |
| 294 | 294 | if (tval & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL)) { |
| 295 | − rr->val = tval; | |
| 296 | − return -EINVAL; | |
| 295 | + return tval; | |
| 297 | 296 | } |
| 298 | 297 | switch (rr->evtid) { |
| 299 | 298 | case QOS_L3_OCCUP_EVENT_ID: |
| @@ -305,12 +304,6 @@ static int __mon_event_count(u32 rmid, struct rmid_read *rr) · 5 unmodified lines | ||
| 305 | 304 | case QOS_L3_MBM_LOCAL_EVENT_ID: |
| 306 | 305 | m = &rr->d->mbm_local[rmid]; |
| 307 | 306 | break; |
| 308 | − default: | |
| 309 | − /* | |
| 310 | − * Code would never reach here because | |
| 311 | − * an invalid event id would fail the __rmid_read. | |
| 312 | − */ | |
| 313 | − return -EINVAL; | |
| 314 | 307 | } |
| 315 | 308 | |
| 316 | 309 | if (rr->first) { |
| @@ -361,23 +354,29 @@ void mon_event_count(void *info) · 44 unmodified lines | ||
| 361 | 354 | struct rdtgroup *rdtgrp, *entry; |
| 362 | 355 | struct rmid_read *rr = info; |
| 363 | 356 | struct list_head *head; |
| 357 | + u64 ret_val; | |
| 364 | 358 | |
| 365 | 359 | rdtgrp = rr->rgrp; |
| 366 | 360 | |
| 367 | − if (__mon_event_count(rdtgrp->mon.rmid, rr)) | |
| 368 | − return; | |
| 361 | + ret_val = __mon_event_count(rdtgrp->mon.rmid, rr); | |
| 369 | 362 | |
| 370 | 363 | /* |
| 371 | − * For Ctrl groups read data from child monitor groups. | |
| 364 | + * For Ctrl groups read data from child monitor groups and | |
| 365 | + * add them together. Count events which are read successfully. | |
| 366 | + * Discard the rmid_read's reporting errors. | |
| 372 | 367 | */ |
| 373 | 368 | head = &rdtgrp->mon.crdtgrp_list; |
| 374 | 369 | |
| 375 | 370 | if (rdtgrp->type == RDTCTRL_GROUP) { |
| 376 | 371 | list_for_each_entry(entry, head, mon.crdtgrp_list) { |
| 377 | − if (__mon_event_count(entry->mon.rmid, rr)) | |
| 378 | − return; | |
| 372 | + if (__mon_event_count(entry->mon.rmid, rr) == 0) | |
| 373 | + ret_val = 0; | |
| 379 | 374 | } |
| 380 | 375 | } |
| 376 | + | |
| 377 | + /* Report error if none of rmid_reads are successful */ | |
| 378 | + if (ret_val) | |
| 379 | + rr->val = ret_val; | |
| 381 | 380 | } |
| 382 | 381 | |
| 383 | 382 | /* |
| @@ -508,7 +508,7 @@ static struct irq_chip hpet_msi_controller __ro_after_init = { · 507 unmodified lines | ||
| 508 | 508 | .irq_set_affinity = msi_domain_set_affinity, |
| 509 | 509 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 510 | 510 | .irq_write_msi_msg = hpet_msi_write_msg, |
| 511 | − .flags = IRQCHIP_SKIP_SET_WAKE, | |
| 511 | + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, | |
| 512 | 512 | }; |
| 513 | 513 | |
| 514 | 514 | static int hpet_msi_init(struct irq_domain *domain, |
| @@ -79,9 +79,10 @@ __jump_label_patch(struct jump_entry *entry, enum jump_label_type type) · 78 unmodified lines | ||
| 79 | 79 | return (struct jump_label_patch){.code = code, .size = size}; |
| 80 | 80 | } |
| 81 | 81 | |
| 82 | −static inline void __jump_label_transform(struct jump_entry *entry, | |
| 83 | − enum jump_label_type type, | |
| 84 | − int init) | |
| 82 | +static __always_inline void | |
| 83 | +__jump_label_transform(struct jump_entry *entry, | |
| 84 | + enum jump_label_type type, | |
| 85 | + int init) | |
| 85 | 86 | { |
| 86 | 87 | const struct jump_label_patch jlp = __jump_label_patch(entry, type); |
| 87 | 88 | |
| @@ -208,30 +208,6 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) · 207 unmodified lines | ||
| 208 | 208 | kvm_mmu_after_set_cpuid(vcpu); |
| 209 | 209 | } |
| 210 | 210 | |
| 211 | −static int is_efer_nx(void) | |
| 212 | −{ | |
| 213 | − return host_efer & EFER_NX; | |
| 214 | −} | |
| 215 | − | |
| 216 | −static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
| 217 | −{ | |
| 218 | − int i; | |
| 219 | − struct kvm_cpuid_entry2 *e, *entry; | |
| 220 | − | |
| 221 | − entry = NULL; | |
| 222 | − for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { | |
| 223 | − e = &vcpu->arch.cpuid_entries[i]; | |
| 224 | − if (e->function == 0x80000001) { | |
| 225 | − entry = e; | |
| 226 | − break; | |
| 227 | − } | |
| 228 | − } | |
| 229 | − if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { | |
| 230 | − cpuid_entry_clear(entry, X86_FEATURE_NX); | |
| 231 | − printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
| 232 | − } | |
| 233 | −} | |
| 234 | − | |
| 235 | 211 | int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) |
| 236 | 212 | { |
| 237 | 213 | struct kvm_cpuid_entry2 *best; |
| @@ -302,7 +278,6 @@ int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, · 64 unmodified lines | ||
| 302 | 278 | vcpu->arch.cpuid_entries = e2; |
| 303 | 279 | vcpu->arch.cpuid_nent = cpuid->nent; |
| 304 | 280 | |
| 305 | − cpuid_fix_nx_cap(vcpu); | |
| 306 | 281 | kvm_update_cpuid_runtime(vcpu); |
| 307 | 282 | kvm_vcpu_after_set_cpuid(vcpu); |
| 308 | 283 | |
| @@ -401,7 +376,6 @@ static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) · 92 unmodified lines | ||
| 401 | 376 | |
| 402 | 377 | void kvm_set_cpu_caps(void) |
| 403 | 378 | { |
| 404 | − unsigned int f_nx = is_efer_nx() ? F(NX) : 0; | |
| 405 | 379 | #ifdef CONFIG_X86_64 |
| 406 | 380 | unsigned int f_gbpages = F(GBPAGES); |
| 407 | 381 | unsigned int f_lm = F(LM); |
| @@ -515,7 +489,7 @@ void kvm_set_cpu_caps(void) · 107 unmodified lines | ||
| 515 | 489 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | |
| 516 | 490 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | |
| 517 | 491 | F(PAT) | F(PSE36) | 0 /* Reserved */ | |
| 518 | − f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
| 492 | + F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
| 519 | 493 | F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | |
| 520 | 494 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) |
| 521 | 495 | ); |
| @@ -765,7 +739,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) · 243 unmodified lines | ||
| 765 | 739 | |
| 766 | 740 | edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); |
| 767 | 741 | edx.split.bit_width_fixed = cap.bit_width_fixed; |
| 768 | − edx.split.anythread_deprecated = 1; | |
| 742 | + if (cap.version) | |
| 743 | + edx.split.anythread_deprecated = 1; | |
| 769 | 744 | edx.split.reserved1 = 0; |
| 770 | 745 | edx.split.reserved2 = 0; |
| 771 | 746 | |
| @@ -940,8 +915,21 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) · 168 unmodified lines | ||
| 940 | 915 | unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); |
| 941 | 916 | unsigned phys_as = entry->eax & 0xff; |
| 942 | 917 | |
| 943 | − if (!g_phys_as) | |
| 918 | + /* | |
| 919 | + * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as | |
| 920 | + * the guest operates in the same PA space as the host, i.e. | |
| 921 | + * reductions in MAXPHYADDR for memory encryption affect shadow | |
| 922 | + * paging, too. | |
| 923 | + * | |
| 924 | + * If TDP is enabled but an explicit guest MAXPHYADDR is not | |
| 925 | + * provided, use the raw bare metal MAXPHYADDR as reductions to | |
| 926 | + * the HPAs do not affect GPAs. | |
| 927 | + */ | |
| 928 | + if (!tdp_enabled) | |
| 929 | + g_phys_as = boot_cpu_data.x86_phys_bits; | |
| 930 | + else if (!g_phys_as) | |
| 944 | 931 | g_phys_as = phys_as; |
| 932 | + | |
| 945 | 933 | entry->eax = g_phys_as | (virt_as << 8); |
| 946 | 934 | entry->edx = 0; |
| 947 | 935 | cpuid_entry_override(entry, CPUID_8000_0008_EBX); |
| @@ -964,12 +952,18 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) · 16 unmodified lines | ||
| 964 | 952 | case 0x8000001a: |
| 965 | 953 | case 0x8000001e: |
| 966 | 954 | break; |
| 967 | − /* Support memory encryption cpuid if host supports it */ | |
| 968 | 955 | case 0x8000001F: |
| 969 | − if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) | |
| 956 | + if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { | |
| 970 | 957 | entry->eax = entry->ebx = entry->ecx = entry->edx = 0; |
| 971 | − else | |
| 958 | + } else { | |
| 972 | 959 | cpuid_entry_override(entry, CPUID_8000_001F_EAX); |
| 960 | + | |
| 961 | + /* | |
| 962 | + * Enumerate '0' for "PA bits reduction", the adjusted | |
| 963 | + * MAXPHYADDR is enumerated directly (see 0x80000008). | |
| 964 | + */ | |
| 965 | + entry->ebx &= ~GENMASK(11, 6); | |
| 966 | + } | |
| 973 | 967 | break; |
| 974 | 968 | /*Add support for Centaur's CPUID instruction*/ |
| 975 | 969 | case 0xC0000000: |
| @@ -1933,7 +1933,7 @@ ret_success: · 1932 unmodified lines | ||
| 1933 | 1933 | void kvm_hv_set_cpuid(struct kvm_vcpu *vcpu) |
| 1934 | 1934 | { |
| 1935 | 1935 | struct kvm_cpuid_entry2 *entry; |
| 1936 | − struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); | |
| 1936 | + struct kvm_vcpu_hv *hv_vcpu; | |
| 1937 | 1937 | |
| 1938 | 1938 | entry = kvm_find_cpuid_entry(vcpu, HYPERV_CPUID_INTERFACE, 0); |
| 1939 | 1939 | if (entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX) { |
| @@ -2016,6 +2016,7 @@ static void kvm_hv_hypercall_set_result(struct kvm_vcpu *vcpu, u64 result) · 76 unmodified lines | ||
| 2016 | 2016 | |
| 2017 | 2017 | static int kvm_hv_hypercall_complete(struct kvm_vcpu *vcpu, u64 result) |
| 2018 | 2018 | { |
| 2019 | + trace_kvm_hv_hypercall_done(result); | |
| 2019 | 2020 | kvm_hv_hypercall_set_result(vcpu, result); |
| 2020 | 2021 | ++vcpu->stat.hypercalls; |
| 2021 | 2022 | return kvm_skip_emulated_instruction(vcpu); |
| @@ -2139,6 +2140,7 @@ static bool hv_check_hypercall_access(struct kvm_vcpu_hv *hv_vcpu, u16 code) · 117 unmodified lines | ||
| 2139 | 2140 | |
| 2140 | 2141 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
| 2141 | 2142 | { |
| 2143 | + struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); | |
| 2142 | 2144 | struct kvm_hv_hcall hc; |
| 2143 | 2145 | u64 ret = HV_STATUS_SUCCESS; |
| 2144 | 2146 | |
| @@ -2173,17 +2175,25 @@ int kvm_hv_hypercall(struct kvm_vcpu *vcpu) · 28 unmodified lines | ||
| 2173 | 2175 | hc.rep_idx = (hc.param >> HV_HYPERCALL_REP_START_OFFSET) & 0xfff; |
| 2174 | 2176 | hc.rep = !!(hc.rep_cnt || hc.rep_idx); |
| 2175 | 2177 | |
| 2176 | − if (hc.fast && is_xmm_fast_hypercall(&hc)) | |
| 2177 | − kvm_hv_hypercall_read_xmm(&hc); | |
| 2178 | − | |
| 2179 | 2178 | trace_kvm_hv_hypercall(hc.code, hc.fast, hc.rep_cnt, hc.rep_idx, |
| 2180 | 2179 | hc.ingpa, hc.outgpa); |
| 2181 | 2180 | |
| 2182 | − if (unlikely(!hv_check_hypercall_access(to_hv_vcpu(vcpu), hc.code))) { | |
| 2181 | + if (unlikely(!hv_check_hypercall_access(hv_vcpu, hc.code))) { | |
| 2183 | 2182 | ret = HV_STATUS_ACCESS_DENIED; |
| 2184 | 2183 | goto hypercall_complete; |
| 2185 | 2184 | } |
| 2186 | 2185 | |
| 2186 | + if (hc.fast && is_xmm_fast_hypercall(&hc)) { | |
| 2187 | + if (unlikely(hv_vcpu->enforce_cpuid && | |
| 2188 | + !(hv_vcpu->cpuid_cache.features_edx & | |
| 2189 | + HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE))) { | |
| 2190 | + kvm_queue_exception(vcpu, UD_VECTOR); | |
| 2191 | + return 1; | |
| 2192 | + } | |
| 2193 | + | |
| 2194 | + kvm_hv_hypercall_read_xmm(&hc); | |
| 2195 | + } | |
| 2196 | + | |
| 2187 | 2197 | switch (hc.code) { |
| 2188 | 2198 | case HVCALL_NOTIFY_LONG_SPIN_WAIT: |
| 2189 | 2199 | if (unlikely(hc.rep)) { |
| @@ -96,7 +96,7 @@ static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, · 95 unmodified lines | ||
| 96 | 96 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
| 97 | 97 | { |
| 98 | 98 | ioapic->rtc_status.pending_eoi = 0; |
| 99 | − bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID); | |
| 99 | + bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID + 1); | |
| 100 | 100 | } |
| 101 | 101 | |
| 102 | 102 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); |
| @@ -43,13 +43,13 @@ struct kvm_vcpu; · 42 unmodified lines | ||
| 43 | 43 | |
| 44 | 44 | struct dest_map { |
| 45 | 45 | /* vcpu bitmap where IRQ has been sent */ |
| 46 | − DECLARE_BITMAP(map, KVM_MAX_VCPU_ID); | |
| 46 | + DECLARE_BITMAP(map, KVM_MAX_VCPU_ID + 1); | |
| 47 | 47 | |
| 48 | 48 | /* |
| 49 | 49 | * Vector sent to a given vcpu, only valid when |
| 50 | 50 | * the vcpu's bit in map is set |
| 51 | 51 | */ |
| 52 | − u8 vectors[KVM_MAX_VCPU_ID]; | |
| 52 | + u8 vectors[KVM_MAX_VCPU_ID + 1]; | |
| 53 | 53 | }; |
| 54 | 54 | |
| 55 | 55 | |
| @@ -53,6 +53,8 @@ · 52 unmodified lines | ||
| 53 | 53 | #include <asm/kvm_page_track.h> |
| 54 | 54 | #include "trace.h" |
| 55 | 55 | |
| 56 | +#include "paging.h" | |
| 57 | + | |
| 56 | 58 | extern bool itlb_multihit_kvm_mitigation; |
| 57 | 59 | |
| 58 | 60 | int __read_mostly nx_huge_pages = -1; |
| @@ -1642,7 +1644,7 @@ static int is_empty_shadow_page(u64 *spt) · 1583 unmodified lines | ||
| 1642 | 1644 | * aggregate version in order to make the slab shrinker |
| 1643 | 1645 | * faster |
| 1644 | 1646 | */ |
| 1645 | −static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) | |
| 1647 | +static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr) | |
| 1646 | 1648 | { |
| 1647 | 1649 | kvm->arch.n_used_mmu_pages += nr; |
| 1648 | 1650 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); |
| @@ -2533,6 +2535,7 @@ static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) · 884 unmodified lines | ||
| 2533 | 2535 | int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync) |
| 2534 | 2536 | { |
| 2535 | 2537 | struct kvm_mmu_page *sp; |
| 2538 | + bool locked = false; | |
| 2536 | 2539 | |
| 2537 | 2540 | /* |
| 2538 | 2541 | * Force write-protection if the page is being tracked. Note, the page |
| @@ -2555,9 +2558,34 @@ int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync) · 16 unmodified lines | ||
| 2555 | 2558 | if (sp->unsync) |
| 2556 | 2559 | continue; |
| 2557 | 2560 | |
| 2561 | + /* | |
| 2562 | + * TDP MMU page faults require an additional spinlock as they | |
| 2563 | + * run with mmu_lock held for read, not write, and the unsync | |
| 2564 | + * logic is not thread safe. Take the spinklock regardless of | |
| 2565 | + * the MMU type to avoid extra conditionals/parameters, there's | |
| 2566 | + * no meaningful penalty if mmu_lock is held for write. | |
| 2567 | + */ | |
| 2568 | + if (!locked) { | |
| 2569 | + locked = true; | |
| 2570 | + spin_lock(&vcpu->kvm->arch.mmu_unsync_pages_lock); | |
| 2571 | + | |
| 2572 | + /* | |
| 2573 | + * Recheck after taking the spinlock, a different vCPU | |
| 2574 | + * may have since marked the page unsync. A false | |
| 2575 | + * positive on the unprotected check above is not | |
| 2576 | + * possible as clearing sp->unsync _must_ hold mmu_lock | |
| 2577 | + * for write, i.e. unsync cannot transition from 0->1 | |
| 2578 | + * while this CPU holds mmu_lock for read (or write). | |
| 2579 | + */ | |
| 2580 | + if (READ_ONCE(sp->unsync)) | |
| 2581 | + continue; | |
| 2582 | + } | |
| 2583 | + | |
| 2558 | 2584 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
| 2559 | 2585 | kvm_unsync_page(vcpu, sp); |
| 2560 | 2586 | } |
| 2587 | + if (locked) | |
| 2588 | + spin_unlock(&vcpu->kvm->arch.mmu_unsync_pages_lock); | |
| 2561 | 2589 | |
| 2562 | 2590 | /* |
| 2563 | 2591 | * We need to ensure that the marking of unsync pages is visible |
| @@ -5535,6 +5563,8 @@ void kvm_mmu_init_vm(struct kvm *kvm) · 2971 unmodified lines | ||
| 5535 | 5563 | { |
| 5536 | 5564 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
| 5537 | 5565 | |
| 5566 | + spin_lock_init(&kvm->arch.mmu_unsync_pages_lock); | |
| 5567 | + | |
| 5538 | 5568 | if (!kvm_mmu_init_tdp_mmu(kvm)) |
| 5539 | 5569 | /* |
| 5540 | 5570 | * No smp_load/store wrappers needed here as we are in |
| @@ -0,0 +1,14 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* Shadow paging constants/helpers that don't need to be #undef'd. */ | |
| 3 | +#ifndef __KVM_X86_PAGING_H | |
| 4 | +#define __KVM_X86_PAGING_H | |
| 5 | + | |
| 6 | +#define GUEST_PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) | |
| 7 | +#define PT64_LVL_ADDR_MASK(level) \ | |
| 8 | + (GUEST_PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
| 9 | + * PT64_LEVEL_BITS))) - 1)) | |
| 10 | +#define PT64_LVL_OFFSET_MASK(level) \ | |
| 11 | + (GUEST_PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
| 12 | + * PT64_LEVEL_BITS))) - 1)) | |
| 13 | +#endif /* __KVM_X86_PAGING_H */ | |
| 14 | + | |
| @@ -24,7 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | #define pt_element_t u64 |
| 25 | 25 | #define guest_walker guest_walker64 |
| 26 | 26 | #define FNAME(name) paging##64_##name |
| 27 | − #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
| 27 | + #define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK | |
| 28 | 28 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
| 29 | 29 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) |
| 30 | 30 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
| @@ -57,7 +57,7 @@ · 26 unmodified lines | ||
| 57 | 57 | #define pt_element_t u64 |
| 58 | 58 | #define guest_walker guest_walkerEPT |
| 59 | 59 | #define FNAME(name) ept_##name |
| 60 | − #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
| 60 | + #define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK | |
| 61 | 61 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
| 62 | 62 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) |
| 63 | 63 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
| @@ -38,12 +38,6 @@ static_assert(SPTE_TDP_AD_ENABLED_MASK == 0); · 37 unmodified lines | ||
| 38 | 38 | #else |
| 39 | 39 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
| 40 | 40 | #endif |
| 41 | −#define PT64_LVL_ADDR_MASK(level) \ | |
| 42 | − (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
| 43 | − * PT64_LEVEL_BITS))) - 1)) | |
| 44 | −#define PT64_LVL_OFFSET_MASK(level) \ | |
| 45 | − (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
| 46 | − * PT64_LEVEL_BITS))) - 1)) | |
| 47 | 41 | |
| 48 | 42 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
| 49 | 43 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
| @@ -43,6 +43,7 @@ void kvm_mmu_uninit_tdp_mmu(struct kvm *kvm) · 42 unmodified lines | ||
| 43 | 43 | if (!kvm->arch.tdp_mmu_enabled) |
| 44 | 44 | return; |
| 45 | 45 | |
| 46 | + WARN_ON(!list_empty(&kvm->arch.tdp_mmu_pages)); | |
| 46 | 47 | WARN_ON(!list_empty(&kvm->arch.tdp_mmu_roots)); |
| 47 | 48 | |
| 48 | 49 | /* |
| @@ -81,8 +82,6 @@ static void tdp_mmu_free_sp_rcu_callback(struct rcu_head *head) · 32 unmodified lines | ||
| 81 | 82 | void kvm_tdp_mmu_put_root(struct kvm *kvm, struct kvm_mmu_page *root, |
| 82 | 83 | bool shared) |
| 83 | 84 | { |
| 84 | − gfn_t max_gfn = 1ULL << (shadow_phys_bits - PAGE_SHIFT); | |
| 85 | − | |
| 86 | 85 | kvm_lockdep_assert_mmu_lock_held(kvm, shared); |
| 87 | 86 | |
| 88 | 87 | if (!refcount_dec_and_test(&root->tdp_mmu_root_count)) |
| @@ -94,7 +93,7 @@ void kvm_tdp_mmu_put_root(struct kvm *kvm, struct kvm_mmu_page *root, · 5 unmodified lines | ||
| 94 | 93 | list_del_rcu(&root->link); |
| 95 | 94 | spin_unlock(&kvm->arch.tdp_mmu_pages_lock); |
| 96 | 95 | |
| 97 | − zap_gfn_range(kvm, root, 0, max_gfn, false, false, shared); | |
| 96 | + zap_gfn_range(kvm, root, 0, -1ull, false, false, shared); | |
| 98 | 97 | |
| 99 | 98 | call_rcu(&root->rcu_head, tdp_mmu_free_sp_rcu_callback); |
| 100 | 99 | } |
| @@ -724,13 +723,29 @@ static bool zap_gfn_range(struct kvm *kvm, struct kvm_mmu_page *root, · 623 unmodified lines | ||
| 724 | 723 | gfn_t start, gfn_t end, bool can_yield, bool flush, |
| 725 | 724 | bool shared) |
| 726 | 725 | { |
| 726 | + gfn_t max_gfn_host = 1ULL << (shadow_phys_bits - PAGE_SHIFT); | |
| 727 | + bool zap_all = (start == 0 && end >= max_gfn_host); | |
| 727 | 728 | struct tdp_iter iter; |
| 728 | 729 | |
| 730 | + /* | |
| 731 | + * No need to try to step down in the iterator when zapping all SPTEs, | |
| 732 | + * zapping the top-level non-leaf SPTEs will recurse on their children. | |
| 733 | + */ | |
| 734 | + int min_level = zap_all ? root->role.level : PG_LEVEL_4K; | |
| 735 | + | |
| 736 | + /* | |
| 737 | + * Bound the walk at host.MAXPHYADDR, guest accesses beyond that will | |
| 738 | + * hit a #PF(RSVD) and never get to an EPT Violation/Misconfig / #NPF, | |
| 739 | + * and so KVM will never install a SPTE for such addresses. | |
| 740 | + */ | |
| 741 | + end = min(end, max_gfn_host); | |
| 742 | + | |
| 729 | 743 | kvm_lockdep_assert_mmu_lock_held(kvm, shared); |
| 730 | 744 | |
| 731 | 745 | rcu_read_lock(); |
| 732 | 746 | |
| 733 | − tdp_root_for_each_pte(iter, root, start, end) { | |
| 747 | + for_each_tdp_pte_min_level(iter, root->spt, root->role.level, | |
| 748 | + min_level, start, end) { | |
| 734 | 749 | retry: |
| 735 | 750 | if (can_yield && |
| 736 | 751 | tdp_mmu_iter_cond_resched(kvm, &iter, flush, shared)) { |
| @@ -744,9 +759,10 @@ retry: · 7 unmodified lines | ||
| 744 | 759 | /* |
| 745 | 760 | * If this is a non-last-level SPTE that covers a larger range |
| 746 | 761 | * than should be zapped, continue, and zap the mappings at a |
| 747 | − * lower level. | |
| 762 | + * lower level, except when zapping all SPTEs. | |
| 748 | 763 | */ |
| 749 | − if ((iter.gfn < start || | |
| 764 | + if (!zap_all && | |
| 765 | + (iter.gfn < start || | |
| 750 | 766 | iter.gfn + KVM_PAGES_PER_HPAGE(iter.level) > end) && |
| 751 | 767 | !is_last_spte(iter.old_spte, iter.level)) |
| 752 | 768 | continue; |
| @@ -794,12 +810,11 @@ bool __kvm_tdp_mmu_zap_gfn_range(struct kvm *kvm, int as_id, gfn_t start, · 41 unmodified lines | ||
| 794 | 810 | |
| 795 | 811 | void kvm_tdp_mmu_zap_all(struct kvm *kvm) |
| 796 | 812 | { |
| 797 | − gfn_t max_gfn = 1ULL << (shadow_phys_bits - PAGE_SHIFT); | |
| 798 | 813 | bool flush = false; |
| 799 | 814 | int i; |
| 800 | 815 | |
| 801 | 816 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) |
| 802 | − flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, 0, max_gfn, | |
| 817 | + flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, 0, -1ull, | |
| 803 | 818 | flush, false); |
| 804 | 819 | |
| 805 | 820 | if (flush) |
| @@ -838,7 +853,6 @@ static struct kvm_mmu_page *next_invalidated_root(struct kvm *kvm, · 32 unmodified lines | ||
| 838 | 853 | */ |
| 839 | 854 | void kvm_tdp_mmu_zap_invalidated_roots(struct kvm *kvm) |
| 840 | 855 | { |
| 841 | − gfn_t max_gfn = 1ULL << (shadow_phys_bits - PAGE_SHIFT); | |
| 842 | 856 | struct kvm_mmu_page *next_root; |
| 843 | 857 | struct kvm_mmu_page *root; |
| 844 | 858 | bool flush = false; |
| @@ -854,8 +868,7 @@ void kvm_tdp_mmu_zap_invalidated_roots(struct kvm *kvm) · 9 unmodified lines | ||
| 854 | 868 | |
| 855 | 869 | rcu_read_unlock(); |
| 856 | 870 | |
| 857 | − flush = zap_gfn_range(kvm, root, 0, max_gfn, true, flush, | |
| 858 | − true); | |
| 871 | + flush = zap_gfn_range(kvm, root, 0, -1ull, true, flush, true); | |
| 859 | 872 | |
| 860 | 873 | /* |
| 861 | 874 | * Put the reference acquired in |
| @@ -646,7 +646,7 @@ out: · 645 unmodified lines | ||
| 646 | 646 | void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
| 647 | 647 | { |
| 648 | 648 | struct vcpu_svm *svm = to_svm(vcpu); |
| 649 | − struct vmcb *vmcb = svm->vmcb; | |
| 649 | + struct vmcb *vmcb = svm->vmcb01.ptr; | |
| 650 | 650 | bool activated = kvm_vcpu_apicv_active(vcpu); |
| 651 | 651 | |
| 652 | 652 | if (!enable_apicv) |
| @@ -154,6 +154,13 @@ void recalc_intercepts(struct vcpu_svm *svm) · 153 unmodified lines | ||
| 154 | 154 | |
| 155 | 155 | for (i = 0; i < MAX_INTERCEPT; i++) |
| 156 | 156 | c->intercepts[i] |= g->intercepts[i]; |
| 157 | + | |
| 158 | + /* If SMI is not intercepted, ignore guest SMI intercept as well */ | |
| 159 | + if (!intercept_smi) | |
| 160 | + vmcb_clr_intercept(c, INTERCEPT_SMI); | |
| 161 | + | |
| 162 | + vmcb_set_intercept(c, INTERCEPT_VMLOAD); | |
| 163 | + vmcb_set_intercept(c, INTERCEPT_VMSAVE); | |
| 157 | 164 | } |
| 158 | 165 | |
| 159 | 166 | static void copy_vmcb_control_area(struct vmcb_control_area *dst, |
| @@ -304,8 +311,8 @@ static bool nested_vmcb_valid_sregs(struct kvm_vcpu *vcpu, · 144 unmodified lines | ||
| 304 | 311 | return true; |
| 305 | 312 | } |
| 306 | 313 | |
| 307 | −static void nested_load_control_from_vmcb12(struct vcpu_svm *svm, | |
| 308 | − struct vmcb_control_area *control) | |
| 314 | +void nested_load_control_from_vmcb12(struct vcpu_svm *svm, | |
| 315 | + struct vmcb_control_area *control) | |
| 309 | 316 | { |
| 310 | 317 | copy_vmcb_control_area(&svm->nested.ctl, control); |
| 311 | 318 | |
| @@ -499,7 +506,11 @@ static void nested_vmcb02_prepare_save(struct vcpu_svm *svm, struct vmcb *vmcb12 · 187 unmodified lines | ||
| 499 | 506 | |
| 500 | 507 | static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) |
| 501 | 508 | { |
| 502 | − const u32 mask = V_INTR_MASKING_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK; | |
| 509 | + const u32 int_ctl_vmcb01_bits = | |
| 510 | + V_INTR_MASKING_MASK | V_GIF_MASK | V_GIF_ENABLE_MASK; | |
| 511 | + | |
| 512 | + const u32 int_ctl_vmcb12_bits = V_TPR_MASK | V_IRQ_INJECTION_BITS_MASK; | |
| 513 | + | |
| 503 | 514 | struct kvm_vcpu *vcpu = &svm->vcpu; |
| 504 | 515 | |
| 505 | 516 | /* |
| @@ -511,7 +522,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) · 5 unmodified lines | ||
| 511 | 522 | * Also covers avic_vapic_bar, avic_backing_page, avic_logical_id, |
| 512 | 523 | * avic_physical_id. |
| 513 | 524 | */ |
| 514 | − WARN_ON(svm->vmcb01.ptr->control.int_ctl & AVIC_ENABLE_MASK); | |
| 525 | + WARN_ON(kvm_apicv_activated(svm->vcpu.kvm)); | |
| 515 | 526 | |
| 516 | 527 | /* Copied from vmcb01. msrpm_base can be overwritten later. */ |
| 517 | 528 | svm->vmcb->control.nested_ctl = svm->vmcb01.ptr->control.nested_ctl; |
| @@ -531,8 +542,8 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) · 13 unmodified lines | ||
| 531 | 542 | vcpu->arch.l1_tsc_offset + svm->nested.ctl.tsc_offset; |
| 532 | 543 | |
| 533 | 544 | svm->vmcb->control.int_ctl = |
| 534 | − (svm->nested.ctl.int_ctl & ~mask) | | |
| 535 | − (svm->vmcb01.ptr->control.int_ctl & mask); | |
| 545 | + (svm->nested.ctl.int_ctl & int_ctl_vmcb12_bits) | | |
| 546 | + (svm->vmcb01.ptr->control.int_ctl & int_ctl_vmcb01_bits); | |
| 536 | 547 | |
| 537 | 548 | svm->vmcb->control.virt_ext = svm->nested.ctl.virt_ext; |
| 538 | 549 | svm->vmcb->control.int_vector = svm->nested.ctl.int_vector; |
| @@ -618,6 +629,11 @@ int nested_svm_vmrun(struct kvm_vcpu *vcpu) · 79 unmodified lines | ||
| 618 | 629 | struct kvm_host_map map; |
| 619 | 630 | u64 vmcb12_gpa; |
| 620 | 631 | |
| 632 | + if (!svm->nested.hsave_msr) { | |
| 633 | + kvm_inject_gp(vcpu, 0); | |
| 634 | + return 1; | |
| 635 | + } | |
| 636 | + | |
| 621 | 637 | if (is_smm(vcpu)) { |
| 622 | 638 | kvm_queue_exception(vcpu, UD_VECTOR); |
| 623 | 639 | return 1; |
| @@ -692,7 +708,28 @@ out: · 68 unmodified lines | ||
| 692 | 708 | return ret; |
| 693 | 709 | } |
| 694 | 710 | |
| 695 | −void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) | |
| 711 | +/* Copy state save area fields which are handled by VMRUN */ | |
| 712 | +void svm_copy_vmrun_state(struct vmcb_save_area *to_save, | |
| 713 | + struct vmcb_save_area *from_save) | |
| 714 | +{ | |
| 715 | + to_save->es = from_save->es; | |
| 716 | + to_save->cs = from_save->cs; | |
| 717 | + to_save->ss = from_save->ss; | |
| 718 | + to_save->ds = from_save->ds; | |
| 719 | + to_save->gdtr = from_save->gdtr; | |
| 720 | + to_save->idtr = from_save->idtr; | |
| 721 | + to_save->rflags = from_save->rflags | X86_EFLAGS_FIXED; | |
| 722 | + to_save->efer = from_save->efer; | |
| 723 | + to_save->cr0 = from_save->cr0; | |
| 724 | + to_save->cr3 = from_save->cr3; | |
| 725 | + to_save->cr4 = from_save->cr4; | |
| 726 | + to_save->rax = from_save->rax; | |
| 727 | + to_save->rsp = from_save->rsp; | |
| 728 | + to_save->rip = from_save->rip; | |
| 729 | + to_save->cpl = 0; | |
| 730 | +} | |
| 731 | + | |
| 732 | +void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb) | |
| 696 | 733 | { |
| 697 | 734 | to_vmcb->save.fs = from_vmcb->save.fs; |
| 698 | 735 | to_vmcb->save.gs = from_vmcb->save.gs; |
| @@ -1355,28 +1392,11 @@ static int svm_set_nested_state(struct kvm_vcpu *vcpu, · 656 unmodified lines | ||
| 1355 | 1392 | |
| 1356 | 1393 | svm->nested.vmcb12_gpa = kvm_state->hdr.svm.vmcb_pa; |
| 1357 | 1394 | |
| 1358 | − svm->vmcb01.ptr->save.es = save->es; | |
| 1359 | − svm->vmcb01.ptr->save.cs = save->cs; | |
| 1360 | − svm->vmcb01.ptr->save.ss = save->ss; | |
| 1361 | − svm->vmcb01.ptr->save.ds = save->ds; | |
| 1362 | − svm->vmcb01.ptr->save.gdtr = save->gdtr; | |
| 1363 | − svm->vmcb01.ptr->save.idtr = save->idtr; | |
| 1364 | − svm->vmcb01.ptr->save.rflags = save->rflags | X86_EFLAGS_FIXED; | |
| 1365 | − svm->vmcb01.ptr->save.efer = save->efer; | |
| 1366 | − svm->vmcb01.ptr->save.cr0 = save->cr0; | |
| 1367 | − svm->vmcb01.ptr->save.cr3 = save->cr3; | |
| 1368 | − svm->vmcb01.ptr->save.cr4 = save->cr4; | |
| 1369 | − svm->vmcb01.ptr->save.rax = save->rax; | |
| 1370 | − svm->vmcb01.ptr->save.rsp = save->rsp; | |
| 1371 | − svm->vmcb01.ptr->save.rip = save->rip; | |
| 1372 | − svm->vmcb01.ptr->save.cpl = 0; | |
| 1373 | − | |
| 1395 | + svm_copy_vmrun_state(&svm->vmcb01.ptr->save, save); | |
| 1374 | 1396 | nested_load_control_from_vmcb12(svm, ctl); |
| 1375 | 1397 | |
| 1376 | 1398 | svm_switch_vmcb(svm, &svm->nested.vmcb02); |
| 1377 | − | |
| 1378 | 1399 | nested_vmcb02_prepare_control(svm); |
| 1379 | − | |
| 1380 | 1400 | kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); |
| 1381 | 1401 | ret = 0; |
| 1382 | 1402 | out_free: |
| @@ -64,6 +64,7 @@ static DEFINE_MUTEX(sev_bitmap_lock); · 63 unmodified lines | ||
| 64 | 64 | unsigned int max_sev_asid; |
| 65 | 65 | static unsigned int min_sev_asid; |
| 66 | 66 | static unsigned long sev_me_mask; |
| 67 | +static unsigned int nr_asids; | |
| 67 | 68 | static unsigned long *sev_asid_bitmap; |
| 68 | 69 | static unsigned long *sev_reclaim_asid_bitmap; |
| 69 | 70 | |
| @@ -78,11 +79,11 @@ struct enc_region { · 8 unmodified lines | ||
| 78 | 79 | /* Called with the sev_bitmap_lock held, or on shutdown */ |
| 79 | 80 | static int sev_flush_asids(int min_asid, int max_asid) |
| 80 | 81 | { |
| 81 | − int ret, pos, error = 0; | |
| 82 | + int ret, asid, error = 0; | |
| 82 | 83 | |
| 83 | 84 | /* Check if there are any ASIDs to reclaim before performing a flush */ |
| 84 | − pos = find_next_bit(sev_reclaim_asid_bitmap, max_asid, min_asid); | |
| 85 | − if (pos >= max_asid) | |
| 85 | + asid = find_next_bit(sev_reclaim_asid_bitmap, nr_asids, min_asid); | |
| 86 | + if (asid > max_asid) | |
| 86 | 87 | return -EBUSY; |
| 87 | 88 | |
| 88 | 89 | /* |
| @@ -115,15 +116,15 @@ static bool __sev_recycle_asids(int min_asid, int max_asid) · 26 unmodified lines | ||
| 115 | 116 | |
| 116 | 117 | /* The flush process will flush all reclaimable SEV and SEV-ES ASIDs */ |
| 117 | 118 | bitmap_xor(sev_asid_bitmap, sev_asid_bitmap, sev_reclaim_asid_bitmap, |
| 118 | − max_sev_asid); | |
| 119 | − bitmap_zero(sev_reclaim_asid_bitmap, max_sev_asid); | |
| 119 | + nr_asids); | |
| 120 | + bitmap_zero(sev_reclaim_asid_bitmap, nr_asids); | |
| 120 | 121 | |
| 121 | 122 | return true; |
| 122 | 123 | } |
| 123 | 124 | |
| 124 | 125 | static int sev_asid_new(struct kvm_sev_info *sev) |
| 125 | 126 | { |
| 126 | − int pos, min_asid, max_asid, ret; | |
| 127 | + int asid, min_asid, max_asid, ret; | |
| 127 | 128 | bool retry = true; |
| 128 | 129 | enum misc_res_type type; |
| 129 | 130 | |
| @@ -143,11 +144,11 @@ static int sev_asid_new(struct kvm_sev_info *sev) · 13 unmodified lines | ||
| 143 | 144 | * SEV-enabled guests must use asid from min_sev_asid to max_sev_asid. |
| 144 | 145 | * SEV-ES-enabled guest can use from 1 to min_sev_asid - 1. |
| 145 | 146 | */ |
| 146 | − min_asid = sev->es_active ? 0 : min_sev_asid - 1; | |
| 147 | + min_asid = sev->es_active ? 1 : min_sev_asid; | |
| 147 | 148 | max_asid = sev->es_active ? min_sev_asid - 1 : max_sev_asid; |
| 148 | 149 | again: |
| 149 | − pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_asid); | |
| 150 | − if (pos >= max_asid) { | |
| 150 | + asid = find_next_zero_bit(sev_asid_bitmap, max_asid + 1, min_asid); | |
| 151 | + if (asid > max_asid) { | |
| 151 | 152 | if (retry && __sev_recycle_asids(min_asid, max_asid)) { |
| 152 | 153 | retry = false; |
| 153 | 154 | goto again; |
| @@ -157,11 +158,11 @@ again: · 3 unmodified lines | ||
| 157 | 158 | goto e_uncharge; |
| 158 | 159 | } |
| 159 | 160 | |
| 160 | − __set_bit(pos, sev_asid_bitmap); | |
| 161 | + __set_bit(asid, sev_asid_bitmap); | |
| 161 | 162 | |
| 162 | 163 | mutex_unlock(&sev_bitmap_lock); |
| 163 | 164 | |
| 164 | − return pos + 1; | |
| 165 | + return asid; | |
| 165 | 166 | e_uncharge: |
| 166 | 167 | misc_cg_uncharge(type, sev->misc_cg, 1); |
| 167 | 168 | put_misc_cg(sev->misc_cg); |
| @@ -179,17 +180,16 @@ static int sev_get_asid(struct kvm *kvm) · 11 unmodified lines | ||
| 179 | 180 | static void sev_asid_free(struct kvm_sev_info *sev) |
| 180 | 181 | { |
| 181 | 182 | struct svm_cpu_data *sd; |
| 182 | − int cpu, pos; | |
| 183 | + int cpu; | |
| 183 | 184 | enum misc_res_type type; |
| 184 | 185 | |
| 185 | 186 | mutex_lock(&sev_bitmap_lock); |
| 186 | 187 | |
| 187 | − pos = sev->asid - 1; | |
| 188 | − __set_bit(pos, sev_reclaim_asid_bitmap); | |
| 188 | + __set_bit(sev->asid, sev_reclaim_asid_bitmap); | |
| 189 | 189 | |
| 190 | 190 | for_each_possible_cpu(cpu) { |
| 191 | 191 | sd = per_cpu(svm_data, cpu); |
| 192 | − sd->sev_vmcbs[pos] = NULL; | |
| 192 | + sd->sev_vmcbs[sev->asid] = NULL; | |
| 193 | 193 | } |
| 194 | 194 | |
| 195 | 195 | mutex_unlock(&sev_bitmap_lock); |
| @@ -1272,8 +1272,8 @@ static int sev_send_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) · 1076 unmodified lines | ||
| 1272 | 1272 | /* Pin guest memory */ |
| 1273 | 1273 | guest_page = sev_pin_memory(kvm, params.guest_uaddr & PAGE_MASK, |
| 1274 | 1274 | PAGE_SIZE, &n, 0); |
| 1275 | − if (!guest_page) | |
| 1276 | − return -EFAULT; | |
| 1275 | + if (IS_ERR(guest_page)) | |
| 1276 | + return PTR_ERR(guest_page); | |
| 1277 | 1277 | |
| 1278 | 1278 | /* allocate memory for header and transport buffer */ |
| 1279 | 1279 | ret = -ENOMEM; |
| @@ -1310,8 +1310,9 @@ static int sev_send_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) · 30 unmodified lines | ||
| 1310 | 1310 | } |
| 1311 | 1311 | |
| 1312 | 1312 | /* Copy packet header to userspace. */ |
| 1313 | − ret = copy_to_user((void __user *)(uintptr_t)params.hdr_uaddr, hdr, | |
| 1314 | − params.hdr_len); | |
| 1313 | + if (copy_to_user((void __user *)(uintptr_t)params.hdr_uaddr, hdr, | |
| 1314 | + params.hdr_len)) | |
| 1315 | + ret = -EFAULT; | |
| 1315 | 1316 | |
| 1316 | 1317 | e_free_trans_data: |
| 1317 | 1318 | kfree(trans_data); |
| @@ -1463,11 +1464,12 @@ static int sev_receive_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) · 145 unmodified lines | ||
| 1463 | 1464 | data.trans_len = params.trans_len; |
| 1464 | 1465 | |
| 1465 | 1466 | /* Pin guest memory */ |
| 1466 | − ret = -EFAULT; | |
| 1467 | 1467 | guest_page = sev_pin_memory(kvm, params.guest_uaddr & PAGE_MASK, |
| 1468 | 1468 | PAGE_SIZE, &n, 0); |
| 1469 | − if (!guest_page) | |
| 1469 | + if (IS_ERR(guest_page)) { | |
| 1470 | + ret = PTR_ERR(guest_page); | |
| 1470 | 1471 | goto e_free_trans; |
| 1472 | + } | |
| 1471 | 1473 | |
| 1472 | 1474 | /* The RECEIVE_UPDATE_DATA command requires C-bit to be always set. */ |
| 1473 | 1475 | data.guest_address = (page_to_pfn(guest_page[0]) << PAGE_SHIFT) + offset; |
| @@ -1855,12 +1857,17 @@ void __init sev_hardware_setup(void) · 381 unmodified lines | ||
| 1855 | 1857 | min_sev_asid = edx; |
| 1856 | 1858 | sev_me_mask = 1UL << (ebx & 0x3f); |
| 1857 | 1859 | |
| 1858 | − /* Initialize SEV ASID bitmaps */ | |
| 1859 | − sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL); | |
| 1860 | + /* | |
| 1861 | + * Initialize SEV ASID bitmaps. Allocate space for ASID 0 in the bitmap, | |
| 1862 | + * even though it's never used, so that the bitmap is indexed by the | |
| 1863 | + * actual ASID. | |
| 1864 | + */ | |
| 1865 | + nr_asids = max_sev_asid + 1; | |
| 1866 | + sev_asid_bitmap = bitmap_zalloc(nr_asids, GFP_KERNEL); | |
| 1860 | 1867 | if (!sev_asid_bitmap) |
| 1861 | 1868 | goto out; |
| 1862 | 1869 | |
| 1863 | − sev_reclaim_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL); | |
| 1870 | + sev_reclaim_asid_bitmap = bitmap_zalloc(nr_asids, GFP_KERNEL); | |
| 1864 | 1871 | if (!sev_reclaim_asid_bitmap) { |
| 1865 | 1872 | bitmap_free(sev_asid_bitmap); |
| 1866 | 1873 | sev_asid_bitmap = NULL; |
| @@ -1905,7 +1912,7 @@ void sev_hardware_teardown(void) · 38 unmodified lines | ||
| 1905 | 1912 | return; |
| 1906 | 1913 | |
| 1907 | 1914 | /* No need to take sev_bitmap_lock, all VMs have been destroyed. */ |
| 1908 | − sev_flush_asids(0, max_sev_asid); | |
| 1915 | + sev_flush_asids(1, max_sev_asid); | |
| 1909 | 1916 | |
| 1910 | 1917 | bitmap_free(sev_asid_bitmap); |
| 1911 | 1918 | bitmap_free(sev_reclaim_asid_bitmap); |
| @@ -1919,7 +1926,7 @@ int sev_cpu_init(struct svm_cpu_data *sd) · 7 unmodified lines | ||
| 1919 | 1926 | if (!sev_enabled) |
| 1920 | 1927 | return 0; |
| 1921 | 1928 | |
| 1922 | − sd->sev_vmcbs = kcalloc(max_sev_asid + 1, sizeof(void *), GFP_KERNEL); | |
| 1929 | + sd->sev_vmcbs = kcalloc(nr_asids, sizeof(void *), GFP_KERNEL); | |
| 1923 | 1930 | if (!sd->sev_vmcbs) |
| 1924 | 1931 | return -ENOMEM; |
| 1925 | 1932 | |
| @@ -198,6 +198,11 @@ module_param(avic, bool, 0444); · 197 unmodified lines | ||
| 198 | 198 | bool __read_mostly dump_invalid_vmcb; |
| 199 | 199 | module_param(dump_invalid_vmcb, bool, 0644); |
| 200 | 200 | |
| 201 | + | |
| 202 | +bool intercept_smi = true; | |
| 203 | +module_param(intercept_smi, bool, 0444); | |
| 204 | + | |
| 205 | + | |
| 201 | 206 | static bool svm_gp_erratum_intercept = true; |
| 202 | 207 | |
| 203 | 208 | static u8 rsm_ins_bytes[] = "\x0f\xaa"; |
| @@ -1185,7 +1190,10 @@ static void init_vmcb(struct kvm_vcpu *vcpu) · 981 unmodified lines | ||
| 1185 | 1190 | |
| 1186 | 1191 | svm_set_intercept(svm, INTERCEPT_INTR); |
| 1187 | 1192 | svm_set_intercept(svm, INTERCEPT_NMI); |
| 1188 | − svm_set_intercept(svm, INTERCEPT_SMI); | |
| 1193 | + | |
| 1194 | + if (intercept_smi) | |
| 1195 | + svm_set_intercept(svm, INTERCEPT_SMI); | |
| 1196 | + | |
| 1189 | 1197 | svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0); |
| 1190 | 1198 | svm_set_intercept(svm, INTERCEPT_RDPMC); |
| 1191 | 1199 | svm_set_intercept(svm, INTERCEPT_CPUID); |
| @@ -1398,8 +1406,6 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu) · 206 unmodified lines | ||
| 1398 | 1406 | goto error_free_vmsa_page; |
| 1399 | 1407 | } |
| 1400 | 1408 | |
| 1401 | − svm_vcpu_init_msrpm(vcpu, svm->msrpm); | |
| 1402 | − | |
| 1403 | 1409 | svm->vmcb01.ptr = page_address(vmcb01_page); |
| 1404 | 1410 | svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT); |
| 1405 | 1411 | |
| @@ -1411,6 +1417,8 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu) · 5 unmodified lines | ||
| 1411 | 1417 | svm_switch_vmcb(svm, &svm->vmcb01); |
| 1412 | 1418 | init_vmcb(vcpu); |
| 1413 | 1419 | |
| 1420 | + svm_vcpu_init_msrpm(vcpu, svm->msrpm); | |
| 1421 | + | |
| 1414 | 1422 | svm_init_osvw(vcpu); |
| 1415 | 1423 | vcpu->arch.microcode_version = 0x01000065; |
| 1416 | 1424 | |
| @@ -1560,8 +1568,11 @@ static void svm_set_vintr(struct vcpu_svm *svm) · 143 unmodified lines | ||
| 1560 | 1568 | { |
| 1561 | 1569 | struct vmcb_control_area *control; |
| 1562 | 1570 | |
| 1563 | − /* The following fields are ignored when AVIC is enabled */ | |
| 1564 | − WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu)); | |
| 1571 | + /* | |
| 1572 | + * The following fields are ignored when AVIC is enabled | |
| 1573 | + */ | |
| 1574 | + WARN_ON(kvm_apicv_activated(svm->vcpu.kvm)); | |
| 1575 | + | |
| 1565 | 1576 | svm_set_intercept(svm, INTERCEPT_VINTR); |
| 1566 | 1577 | |
| 1567 | 1578 | /* |
| @@ -1578,17 +1589,18 @@ static void svm_set_vintr(struct vcpu_svm *svm) · 10 unmodified lines | ||
| 1578 | 1589 | |
| 1579 | 1590 | static void svm_clear_vintr(struct vcpu_svm *svm) |
| 1580 | 1591 | { |
| 1581 | − const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK; | |
| 1582 | 1592 | svm_clr_intercept(svm, INTERCEPT_VINTR); |
| 1583 | 1593 | |
| 1584 | 1594 | /* Drop int_ctl fields related to VINTR injection. */ |
| 1585 | − svm->vmcb->control.int_ctl &= mask; | |
| 1595 | + svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK; | |
| 1586 | 1596 | if (is_guest_mode(&svm->vcpu)) { |
| 1587 | − svm->vmcb01.ptr->control.int_ctl &= mask; | |
| 1597 | + svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK; | |
| 1588 | 1598 | |
| 1589 | 1599 | WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) != |
| 1590 | 1600 | (svm->nested.ctl.int_ctl & V_TPR_MASK)); |
| 1591 | − svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask; | |
| 1601 | + | |
| 1602 | + svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & | |
| 1603 | + V_IRQ_INJECTION_BITS_MASK; | |
| 1592 | 1604 | } |
| 1593 | 1605 | |
| 1594 | 1606 | vmcb_mark_dirty(svm->vmcb, VMCB_INTR); |
| @@ -1923,7 +1935,7 @@ static int npf_interception(struct kvm_vcpu *vcpu) · 328 unmodified lines | ||
| 1923 | 1935 | { |
| 1924 | 1936 | struct vcpu_svm *svm = to_svm(vcpu); |
| 1925 | 1937 | |
| 1926 | − u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); | |
| 1938 | + u64 fault_address = svm->vmcb->control.exit_info_2; | |
| 1927 | 1939 | u64 error_code = svm->vmcb->control.exit_info_1; |
| 1928 | 1940 | |
| 1929 | 1941 | trace_kvm_page_fault(fault_address, error_code); |
| @@ -2106,6 +2118,11 @@ static int nmi_interception(struct kvm_vcpu *vcpu) · 176 unmodified lines | ||
| 2106 | 2118 | return 1; |
| 2107 | 2119 | } |
| 2108 | 2120 | |
| 2121 | +static int smi_interception(struct kvm_vcpu *vcpu) | |
| 2122 | +{ | |
| 2123 | + return 1; | |
| 2124 | +} | |
| 2125 | + | |
| 2109 | 2126 | static int intr_interception(struct kvm_vcpu *vcpu) |
| 2110 | 2127 | { |
| 2111 | 2128 | ++vcpu->stat.irq_exits; |
| @@ -2134,11 +2151,12 @@ static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload) · 22 unmodified lines | ||
| 2134 | 2151 | ret = kvm_skip_emulated_instruction(vcpu); |
| 2135 | 2152 | |
| 2136 | 2153 | if (vmload) { |
| 2137 | − nested_svm_vmloadsave(vmcb12, svm->vmcb); | |
| 2154 | + svm_copy_vmloadsave_state(svm->vmcb, vmcb12); | |
| 2138 | 2155 | svm->sysenter_eip_hi = 0; |
| 2139 | 2156 | svm->sysenter_esp_hi = 0; |
| 2140 | − } else | |
| 2141 | − nested_svm_vmloadsave(svm->vmcb, vmcb12); | |
| 2157 | + } else { | |
| 2158 | + svm_copy_vmloadsave_state(vmcb12, svm->vmcb); | |
| 2159 | + } | |
| 2142 | 2160 | |
| 2143 | 2161 | kvm_vcpu_unmap(vcpu, &map, true); |
| 2144 | 2162 | |
| @@ -2941,7 +2959,16 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) · 796 unmodified lines | ||
| 2941 | 2959 | svm_disable_lbrv(vcpu); |
| 2942 | 2960 | break; |
| 2943 | 2961 | case MSR_VM_HSAVE_PA: |
| 2944 | − svm->nested.hsave_msr = data; | |
| 2962 | + /* | |
| 2963 | + * Old kernels did not validate the value written to | |
| 2964 | + * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid | |
| 2965 | + * value to allow live migrating buggy or malicious guests | |
| 2966 | + * originating from those kernels. | |
| 2967 | + */ | |
| 2968 | + if (!msr->host_initiated && !page_address_valid(vcpu, data)) | |
| 2969 | + return 1; | |
| 2970 | + | |
| 2971 | + svm->nested.hsave_msr = data & PAGE_MASK; | |
| 2945 | 2972 | break; |
| 2946 | 2973 | case MSR_VM_CR: |
| 2947 | 2974 | return svm_set_vm_cr(vcpu, data); |
| @@ -3080,8 +3107,7 @@ static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = { · 132 unmodified lines | ||
| 3080 | 3107 | [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception, |
| 3081 | 3108 | [SVM_EXIT_INTR] = intr_interception, |
| 3082 | 3109 | [SVM_EXIT_NMI] = nmi_interception, |
| 3083 | − [SVM_EXIT_SMI] = kvm_emulate_as_nop, | |
| 3084 | − [SVM_EXIT_INIT] = kvm_emulate_as_nop, | |
| 3110 | + [SVM_EXIT_SMI] = smi_interception, | |
| 3085 | 3111 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
| 3086 | 3112 | [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc, |
| 3087 | 3113 | [SVM_EXIT_CPUID] = kvm_emulate_cpuid, |
| @@ -4288,6 +4314,7 @@ static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) · 1200 unmodified lines | ||
| 4288 | 4314 | static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
| 4289 | 4315 | { |
| 4290 | 4316 | struct vcpu_svm *svm = to_svm(vcpu); |
| 4317 | + struct kvm_host_map map_save; | |
| 4291 | 4318 | int ret; |
| 4292 | 4319 | |
| 4293 | 4320 | if (is_guest_mode(vcpu)) { |
| @@ -4303,6 +4330,29 @@ static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate) · 9 unmodified lines | ||
| 4303 | 4330 | ret = nested_svm_vmexit(svm); |
| 4304 | 4331 | if (ret) |
| 4305 | 4332 | return ret; |
| 4333 | + | |
| 4334 | + /* | |
| 4335 | + * KVM uses VMCB01 to store L1 host state while L2 runs but | |
| 4336 | + * VMCB01 is going to be used during SMM and thus the state will | |
| 4337 | + * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save | |
| 4338 | + * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the | |
| 4339 | + * format of the area is identical to guest save area offsetted | |
| 4340 | + * by 0x400 (matches the offset of 'struct vmcb_save_area' | |
| 4341 | + * within 'struct vmcb'). Note: HSAVE area may also be used by | |
| 4342 | + * L1 hypervisor to save additional host context (e.g. KVM does | |
| 4343 | + * that, see svm_prepare_guest_switch()) which must be | |
| 4344 | + * preserved. | |
| 4345 | + */ | |
| 4346 | + if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), | |
| 4347 | + &map_save) == -EINVAL) | |
| 4348 | + return 1; | |
| 4349 | + | |
| 4350 | + BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400); | |
| 4351 | + | |
| 4352 | + svm_copy_vmrun_state(map_save.hva + 0x400, | |
| 4353 | + &svm->vmcb01.ptr->save); | |
| 4354 | + | |
| 4355 | + kvm_vcpu_unmap(vcpu, &map_save, true); | |
| 4306 | 4356 | } |
| 4307 | 4357 | return 0; |
| 4308 | 4358 | } |
| @@ -4310,13 +4360,14 @@ static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate) · 1 unmodified line | ||
| 4310 | 4360 | static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) |
| 4311 | 4361 | { |
| 4312 | 4362 | struct vcpu_svm *svm = to_svm(vcpu); |
| 4313 | − struct kvm_host_map map; | |
| 4363 | + struct kvm_host_map map, map_save; | |
| 4314 | 4364 | int ret = 0; |
| 4315 | 4365 | |
| 4316 | 4366 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) { |
| 4317 | 4367 | u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0); |
| 4318 | 4368 | u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8); |
| 4319 | 4369 | u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0); |
| 4370 | + struct vmcb *vmcb12; | |
| 4320 | 4371 | |
| 4321 | 4372 | if (guest) { |
| 4322 | 4373 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
| @@ -4332,8 +4383,25 @@ static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) · 9 unmodified lines | ||
| 4332 | 4383 | if (svm_allocate_nested(svm)) |
| 4333 | 4384 | return 1; |
| 4334 | 4385 | |
| 4335 | − ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, map.hva); | |
| 4386 | + vmcb12 = map.hva; | |
| 4387 | + | |
| 4388 | + nested_load_control_from_vmcb12(svm, &vmcb12->control); | |
| 4389 | + | |
| 4390 | + ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12); | |
| 4336 | 4391 | kvm_vcpu_unmap(vcpu, &map, true); |
| 4392 | + | |
| 4393 | + /* | |
| 4394 | + * Restore L1 host state from L1 HSAVE area as VMCB01 was | |
| 4395 | + * used during SMM (see svm_enter_smm()) | |
| 4396 | + */ | |
| 4397 | + if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), | |
| 4398 | + &map_save) == -EINVAL) | |
| 4399 | + return 1; | |
| 4400 | + | |
| 4401 | + svm_copy_vmrun_state(&svm->vmcb01.ptr->save, | |
| 4402 | + map_save.hva + 0x400); | |
| 4403 | + | |
| 4404 | + kvm_vcpu_unmap(vcpu, &map_save, true); | |
| 4337 | 4405 | } |
| 4338 | 4406 | } |
| 4339 | 4407 | |
| @@ -31,6 +31,7 @@ · 30 unmodified lines | ||
| 31 | 31 | #define MSRPM_OFFSETS 16 |
| 32 | 32 | extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; |
| 33 | 33 | extern bool npt_enabled; |
| 34 | +extern bool intercept_smi; | |
| 34 | 35 | |
| 35 | 36 | /* |
| 36 | 37 | * Clean bits in VMCB. |
| @@ -463,7 +464,9 @@ void svm_leave_nested(struct vcpu_svm *svm); · 426 unmodified lines | ||
| 463 | 464 | void svm_free_nested(struct vcpu_svm *svm); |
| 464 | 465 | int svm_allocate_nested(struct vcpu_svm *svm); |
| 465 | 466 | int nested_svm_vmrun(struct kvm_vcpu *vcpu); |
| 466 | −void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); | |
| 467 | +void svm_copy_vmrun_state(struct vmcb_save_area *to_save, | |
| 468 | + struct vmcb_save_area *from_save); | |
| 469 | +void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); | |
| 467 | 470 | int nested_svm_vmexit(struct vcpu_svm *svm); |
| 468 | 471 | |
| 469 | 472 | static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) |
| @@ -479,6 +482,8 @@ int nested_svm_check_permissions(struct kvm_vcpu *vcpu); · 9 unmodified lines | ||
| 479 | 482 | int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
| 480 | 483 | bool has_error_code, u32 error_code); |
| 481 | 484 | int nested_svm_exit_special(struct vcpu_svm *svm); |
| 485 | +void nested_load_control_from_vmcb12(struct vcpu_svm *svm, | |
| 486 | + struct vmcb_control_area *control); | |
| 482 | 487 | void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); |
| 483 | 488 | void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); |
| 484 | 489 | void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); |
| @@ -89,7 +89,7 @@ static inline void svm_hv_vmcb_dirty_nested_enlightenments( · 88 unmodified lines | ||
| 89 | 89 | * as we mark it dirty unconditionally towards end of vcpu |
| 90 | 90 | * init phase. |
| 91 | 91 | */ |
| 92 | − if (vmcb && vmcb_is_clean(vmcb, VMCB_HV_NESTED_ENLIGHTENMENTS) && | |
| 92 | + if (vmcb_is_clean(vmcb, VMCB_HV_NESTED_ENLIGHTENMENTS) && | |
| 93 | 93 | hve->hv_enlightenments_control.msr_bitmap) |
| 94 | 94 | vmcb_mark_dirty(vmcb, VMCB_HV_NESTED_ENLIGHTENMENTS); |
| 95 | 95 | } |
| @@ -92,6 +92,21 @@ TRACE_EVENT(kvm_hv_hypercall, · 91 unmodified lines | ||
| 92 | 92 | __entry->outgpa) |
| 93 | 93 | ); |
| 94 | 94 | |
| 95 | +TRACE_EVENT(kvm_hv_hypercall_done, | |
| 96 | + TP_PROTO(u64 result), | |
| 97 | + TP_ARGS(result), | |
| 98 | + | |
| 99 | + TP_STRUCT__entry( | |
| 100 | + __field(__u64, result) | |
| 101 | + ), | |
| 102 | + | |
| 103 | + TP_fast_assign( | |
| 104 | + __entry->result = result; | |
| 105 | + ), | |
| 106 | + | |
| 107 | + TP_printk("result 0x%llx", __entry->result) | |
| 108 | +); | |
| 109 | + | |
| 95 | 110 | /* |
| 96 | 111 | * Tracepoint for Xen hypercall. |
| 97 | 112 | */ |
| @@ -330,6 +330,31 @@ void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu) · 329 unmodified lines | ||
| 330 | 330 | vcpu_put(vcpu); |
| 331 | 331 | } |
| 332 | 332 | |
| 333 | +#define EPTP_PA_MASK GENMASK_ULL(51, 12) | |
| 334 | + | |
| 335 | +static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp) | |
| 336 | +{ | |
| 337 | + return VALID_PAGE(root_hpa) && | |
| 338 | + ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK)); | |
| 339 | +} | |
| 340 | + | |
| 341 | +static void nested_ept_invalidate_addr(struct kvm_vcpu *vcpu, gpa_t eptp, | |
| 342 | + gpa_t addr) | |
| 343 | +{ | |
| 344 | + uint i; | |
| 345 | + struct kvm_mmu_root_info *cached_root; | |
| 346 | + | |
| 347 | + WARN_ON_ONCE(!mmu_is_nested(vcpu)); | |
| 348 | + | |
| 349 | + for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
| 350 | + cached_root = &vcpu->arch.mmu->prev_roots[i]; | |
| 351 | + | |
| 352 | + if (nested_ept_root_matches(cached_root->hpa, cached_root->pgd, | |
| 353 | + eptp)) | |
| 354 | + vcpu->arch.mmu->invlpg(vcpu, addr, cached_root->hpa); | |
| 355 | + } | |
| 356 | +} | |
| 357 | + | |
| 333 | 358 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
| 334 | 359 | struct x86_exception *fault) |
| 335 | 360 | { |
| @@ -342,10 +367,22 @@ static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, · 6 unmodified lines | ||
| 342 | 367 | vm_exit_reason = EXIT_REASON_PML_FULL; |
| 343 | 368 | vmx->nested.pml_full = false; |
| 344 | 369 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; |
| 345 | − } else if (fault->error_code & PFERR_RSVD_MASK) | |
| 346 | − vm_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
| 347 | − else | |
| 348 | − vm_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
| 370 | + } else { | |
| 371 | + if (fault->error_code & PFERR_RSVD_MASK) | |
| 372 | + vm_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
| 373 | + else | |
| 374 | + vm_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
| 375 | + | |
| 376 | + /* | |
| 377 | + * Although the caller (kvm_inject_emulated_page_fault) would | |
| 378 | + * have already synced the faulting address in the shadow EPT | |
| 379 | + * tables for the current EPTP12, we also need to sync it for | |
| 380 | + * any other cached EPTP02s based on the same EP4TA, since the | |
| 381 | + * TLB associates mappings to the EP4TA rather than the full EPTP. | |
| 382 | + */ | |
| 383 | + nested_ept_invalidate_addr(vcpu, vmcs12->ept_pointer, | |
| 384 | + fault->address); | |
| 385 | + } | |
| 349 | 386 | |
| 350 | 387 | nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification); |
| 351 | 388 | vmcs12->guest_physical_address = fault->address; |
| @@ -5325,14 +5362,6 @@ static int handle_vmptrst(struct kvm_vcpu *vcpu) · 4973 unmodified lines | ||
| 5325 | 5362 | return nested_vmx_succeed(vcpu); |
| 5326 | 5363 | } |
| 5327 | 5364 | |
| 5328 | −#define EPTP_PA_MASK GENMASK_ULL(51, 12) | |
| 5329 | − | |
| 5330 | −static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp) | |
| 5331 | −{ | |
| 5332 | − return VALID_PAGE(root_hpa) && | |
| 5333 | − ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK)); | |
| 5334 | −} | |
| 5335 | − | |
| 5336 | 5365 | /* Emulate the INVEPT instruction */ |
| 5337 | 5366 | static int handle_invept(struct kvm_vcpu *vcpu) |
| 5338 | 5367 | { |
| @@ -5826,7 +5855,8 @@ static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu, · 487 unmodified lines | ||
| 5826 | 5855 | if (is_nmi(intr_info)) |
| 5827 | 5856 | return true; |
| 5828 | 5857 | else if (is_page_fault(intr_info)) |
| 5829 | − return vcpu->arch.apf.host_apf_flags || !enable_ept; | |
| 5858 | + return vcpu->arch.apf.host_apf_flags || | |
| 5859 | + vmx_need_pf_intercept(vcpu); | |
| 5830 | 5860 | else if (is_debug(intr_info) && |
| 5831 | 5861 | vcpu->guest_debug & |
| 5832 | 5862 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) |
| @@ -14,8 +14,6 @@ · 13 unmodified lines | ||
| 14 | 14 | #include "vmx_ops.h" |
| 15 | 15 | #include "cpuid.h" |
| 16 | 16 | |
| 17 | −extern const u32 vmx_msr_index[]; | |
| 18 | − | |
| 19 | 17 | #define MSR_TYPE_R 1 |
| 20 | 18 | #define MSR_TYPE_W 2 |
| 21 | 19 | #define MSR_TYPE_RW 3 |
| @@ -524,7 +522,7 @@ static inline struct vmcs *alloc_vmcs(bool shadow) · 502 unmodified lines | ||
| 524 | 522 | |
| 525 | 523 | static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) |
| 526 | 524 | { |
| 527 | − return vmx->secondary_exec_control & | |
| 525 | + return secondary_exec_controls_get(vmx) & | |
| 528 | 526 | SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; |
| 529 | 527 | } |
| 530 | 528 | |
| @@ -3407,7 +3407,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · 3406 unmodified lines | ||
| 3407 | 3407 | return 1; |
| 3408 | 3408 | break; |
| 3409 | 3409 | case MSR_KVM_ASYNC_PF_ACK: |
| 3410 | − if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) | |
| 3410 | + if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) | |
| 3411 | 3411 | return 1; |
| 3412 | 3412 | if (data & 0x1) { |
| 3413 | 3413 | vcpu->arch.apf.pageready_pending = false; |
| @@ -3746,7 +3746,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · 332 unmodified lines | ||
| 3746 | 3746 | msr_info->data = vcpu->arch.apf.msr_int_val; |
| 3747 | 3747 | break; |
| 3748 | 3748 | case MSR_KVM_ASYNC_PF_ACK: |
| 3749 | − if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) | |
| 3749 | + if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) | |
| 3750 | 3750 | return 1; |
| 3751 | 3751 | |
| 3752 | 3752 | msr_info->data = 0; |
| @@ -4358,8 +4358,17 @@ static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) · 605 unmodified lines | ||
| 4358 | 4358 | |
| 4359 | 4359 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
| 4360 | 4360 | { |
| 4361 | − return kvm_arch_interrupt_allowed(vcpu) && | |
| 4362 | − kvm_cpu_accept_dm_intr(vcpu); | |
| 4361 | + /* | |
| 4362 | + * Do not cause an interrupt window exit if an exception | |
| 4363 | + * is pending or an event needs reinjection; userspace | |
| 4364 | + * might want to inject the interrupt manually using KVM_SET_REGS | |
| 4365 | + * or KVM_SET_SREGS. For that to work, we must be at an | |
| 4366 | + * instruction boundary and with no events half-injected. | |
| 4367 | + */ | |
| 4368 | + return (kvm_arch_interrupt_allowed(vcpu) && | |
| 4369 | + kvm_cpu_accept_dm_intr(vcpu) && | |
| 4370 | + !kvm_event_needs_reinjection(vcpu) && | |
| 4371 | + !vcpu->arch.exception.pending); | |
| 4363 | 4372 | } |
| 4364 | 4373 | |
| 4365 | 4374 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
| @@ -9601,6 +9610,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 5235 unmodified lines | ||
| 9601 | 9610 | set_debugreg(vcpu->arch.eff_db[3], 3); |
| 9602 | 9611 | set_debugreg(vcpu->arch.dr6, 6); |
| 9603 | 9612 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
| 9613 | + } else if (unlikely(hw_breakpoint_active())) { | |
| 9614 | + set_debugreg(0, 7); | |
| 9604 | 9615 | } |
| 9605 | 9616 | |
| 9606 | 9617 | for (;;) { |
| @@ -10985,9 +10996,6 @@ int kvm_arch_hardware_setup(void *opaque) · 1378 unmodified lines | ||
| 10985 | 10996 | int r; |
| 10986 | 10997 | |
| 10987 | 10998 | rdmsrl_safe(MSR_EFER, &host_efer); |
| 10988 | − if (WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_NX) && | |
| 10989 | − !(host_efer & EFER_NX))) | |
| 10990 | − return -EIO; | |
| 10991 | 10999 | |
| 10992 | 11000 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
| 10993 | 11001 | rdmsrl(MSR_IA32_XSS, host_xss); |
| @@ -682,7 +682,6 @@ int p4d_clear_huge(p4d_t *p4d) · 681 unmodified lines | ||
| 682 | 682 | } |
| 683 | 683 | #endif |
| 684 | 684 | |
| 685 | −#if CONFIG_PGTABLE_LEVELS > 3 | |
| 686 | 685 | /** |
| 687 | 686 | * pud_set_huge - setup kernel PUD mapping |
| 688 | 687 | * |
| @@ -721,23 +720,6 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) · 32 unmodified lines | ||
| 721 | 720 | return 1; |
| 722 | 721 | } |
| 723 | 722 | |
| 724 | −/** | |
| 725 | − * pud_clear_huge - clear kernel PUD mapping when it is set | |
| 726 | − * | |
| 727 | − * Returns 1 on success and 0 on failure (no PUD map is found). | |
| 728 | − */ | |
| 729 | −int pud_clear_huge(pud_t *pud) | |
| 730 | −{ | |
| 731 | − if (pud_large(*pud)) { | |
| 732 | − pud_clear(pud); | |
| 733 | − return 1; | |
| 734 | − } | |
| 735 | − | |
| 736 | − return 0; | |
| 737 | −} | |
| 738 | −#endif | |
| 739 | − | |
| 740 | −#if CONFIG_PGTABLE_LEVELS > 2 | |
| 741 | 723 | /** |
| 742 | 724 | * pmd_set_huge - setup kernel PMD mapping |
| 743 | 725 | * |
| @@ -768,6 +750,21 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) · 24 unmodified lines | ||
| 768 | 750 | return 1; |
| 769 | 751 | } |
| 770 | 752 | |
| 753 | +/** | |
| 754 | + * pud_clear_huge - clear kernel PUD mapping when it is set | |
| 755 | + * | |
| 756 | + * Returns 1 on success and 0 on failure (no PUD map is found). | |
| 757 | + */ | |
| 758 | +int pud_clear_huge(pud_t *pud) | |
| 759 | +{ | |
| 760 | + if (pud_large(*pud)) { | |
| 761 | + pud_clear(pud); | |
| 762 | + return 1; | |
| 763 | + } | |
| 764 | + | |
| 765 | + return 0; | |
| 766 | +} | |
| 767 | + | |
| 771 | 768 | /** |
| 772 | 769 | * pmd_clear_huge - clear kernel PMD mapping when it is set |
| 773 | 770 | * |
| @@ -782,7 +779,6 @@ int pmd_clear_huge(pmd_t *pmd) · 8 unmodified lines | ||
| 782 | 779 | |
| 783 | 780 | return 0; |
| 784 | 781 | } |
| 785 | −#endif | |
| 786 | 782 | |
| 787 | 783 | #ifdef CONFIG_X86_64 |
| 788 | 784 | /** |
| @@ -570,6 +570,9 @@ static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) · 569 unmodified lines | ||
| 570 | 570 | |
| 571 | 571 | for (i = 0; i < prog->aux->size_poke_tab; i++) { |
| 572 | 572 | poke = &prog->aux->poke_tab[i]; |
| 573 | + if (poke->aux && poke->aux != prog->aux) | |
| 574 | + continue; | |
| 575 | + | |
| 573 | 576 | WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); |
| 574 | 577 | |
| 575 | 578 | if (poke->reason != BPF_POKE_REASON_TAIL_CALL) |
| @@ -1216,6 +1219,13 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, · 640 unmodified lines | ||
| 1216 | 1219 | } |
| 1217 | 1220 | break; |
| 1218 | 1221 | |
| 1222 | + /* speculation barrier */ | |
| 1223 | + case BPF_ST | BPF_NOSPEC: | |
| 1224 | + if (boot_cpu_has(X86_FEATURE_XMM2)) | |
| 1225 | + /* Emit 'lfence' */ | |
| 1226 | + EMIT3(0x0F, 0xAE, 0xE8); | |
| 1227 | + break; | |
| 1228 | + | |
| 1219 | 1229 | /* ST: *(u8*)(dst_reg + off) = imm */ |
| 1220 | 1230 | case BPF_ST | BPF_MEM | BPF_B: |
| 1221 | 1231 | if (is_ereg(dst_reg)) |
| @@ -1886,6 +1886,12 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, · 1885 unmodified lines | ||
| 1886 | 1886 | i++; |
| 1887 | 1887 | break; |
| 1888 | 1888 | } |
| 1889 | + /* speculation barrier */ | |
| 1890 | + case BPF_ST | BPF_NOSPEC: | |
| 1891 | + if (boot_cpu_has(X86_FEATURE_XMM2)) | |
| 1892 | + /* Emit 'lfence' */ | |
| 1893 | + EMIT3(0x0F, 0xAE, 0xE8); | |
| 1894 | + break; | |
| 1889 | 1895 | /* ST: *(u8*)(dst_reg + off) = imm */ |
| 1890 | 1896 | case BPF_ST | BPF_MEM | BPF_H: |
| 1891 | 1897 | case BPF_ST | BPF_MEM | BPF_B: |
| @@ -10,6 +10,7 @@ BEGIN { · 9 unmodified lines | ||
| 10 | 10 | |
| 11 | 11 | /^GNU objdump/ { |
| 12 | 12 | verstr = "" |
| 13 | + gsub(/\(.*\)/, ""); | |
| 13 | 14 | for (i = 3; i <= NF; i++) |
| 14 | 15 | if (match($(i), "^[0-9]")) { |
| 15 | 16 | verstr = $(i); |
| @@ -57,12 +57,12 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = { · 56 unmodified lines | ||
| 57 | 57 | [S_REL] = |
| 58 | 58 | "^(__init_(begin|end)|" |
| 59 | 59 | "__x86_cpu_dev_(start|end)|" |
| 60 | − "(__parainstructions|__alt_instructions)(|_end)|" | |
| 61 | − "(__iommu_table|__apicdrivers|__smp_locks)(|_end)|" | |
| 60 | + "(__parainstructions|__alt_instructions)(_end)?|" | |
| 61 | + "(__iommu_table|__apicdrivers|__smp_locks)(_end)?|" | |
| 62 | 62 | "__(start|end)_pci_.*|" |
| 63 | 63 | "__(start|end)_builtin_fw|" |
| 64 | − "__(start|stop)___ksymtab(|_gpl)|" | |
| 65 | − "__(start|stop)___kcrctab(|_gpl)|" | |
| 64 | + "__(start|stop)___ksymtab(_gpl)?|" | |
| 65 | + "__(start|stop)___kcrctab(_gpl)?|" | |
| 66 | 66 | "__(start|stop)___param|" |
| 67 | 67 | "__(start|stop)___modver|" |
| 68 | 68 | "__(start|stop)___bug_table|" |
| @@ -327,7 +327,6 @@ config XTENSA_PLATFORM_ISS · 326 unmodified lines | ||
| 327 | 327 | |
| 328 | 328 | config XTENSA_PLATFORM_XT2000 |
| 329 | 329 | bool "XT2000" |
| 330 | − select HAVE_IDE | |
| 331 | 330 | help |
| 332 | 331 | XT2000 is the name of Tensilica's feature-rich emulation platform. |
| 333 | 332 | This hardware is capable of running a full Linux distribution. |
| @@ -9,12 +9,6 @@ config MQ_IOSCHED_DEADLINE · 8 unmodified lines | ||
| 9 | 9 | help |
| 10 | 10 | MQ version of the deadline IO scheduler. |
| 11 | 11 | |
| 12 | −config MQ_IOSCHED_DEADLINE_CGROUP | |
| 13 | − tristate | |
| 14 | − default y | |
| 15 | − depends on MQ_IOSCHED_DEADLINE | |
| 16 | − depends on BLK_CGROUP | |
| 17 | − | |
| 18 | 12 | config MQ_IOSCHED_KYBER |
| 19 | 13 | tristate "Kyber I/O scheduler" |
| 20 | 14 | default y |
| @@ -22,8 +22,6 @@ obj-$(CONFIG_BLK_CGROUP_IOPRIO) += blk-ioprio.o · 21 unmodified lines | ||
| 22 | 22 | obj-$(CONFIG_BLK_CGROUP_IOLATENCY) += blk-iolatency.o |
| 23 | 23 | obj-$(CONFIG_BLK_CGROUP_IOCOST) += blk-iocost.o |
| 24 | 24 | obj-$(CONFIG_MQ_IOSCHED_DEADLINE) += mq-deadline.o |
| 25 | −mq-deadline-y += mq-deadline-main.o | |
| 26 | −mq-deadline-$(CONFIG_MQ_IOSCHED_DEADLINE_CGROUP)+= mq-deadline-cgroup.o | |
| 27 | 25 | obj-$(CONFIG_MQ_IOSCHED_KYBER) += kyber-iosched.o |
| 28 | 26 | bfq-y := bfq-iosched.o bfq-wf2q.o bfq-cgroup.o |
| 29 | 27 | obj-$(CONFIG_IOSCHED_BFQ) += bfq.o |
| @@ -790,6 +790,7 @@ static void blkcg_rstat_flush(struct cgroup_subsys_state *css, int cpu) · 789 unmodified lines | ||
| 790 | 790 | struct blkcg_gq *parent = blkg->parent; |
| 791 | 791 | struct blkg_iostat_set *bisc = per_cpu_ptr(blkg->iostat_cpu, cpu); |
| 792 | 792 | struct blkg_iostat cur, delta; |
| 793 | + unsigned long flags; | |
| 793 | 794 | unsigned int seq; |
| 794 | 795 | |
| 795 | 796 | /* fetch the current per-cpu values */ |
| @@ -799,21 +800,21 @@ static void blkcg_rstat_flush(struct cgroup_subsys_state *css, int cpu) · 3 unmodified lines | ||
| 799 | 800 | } while (u64_stats_fetch_retry(&bisc->sync, seq)); |
| 800 | 801 | |
| 801 | 802 | /* propagate percpu delta to global */ |
| 802 | − u64_stats_update_begin(&blkg->iostat.sync); | |
| 803 | + flags = u64_stats_update_begin_irqsave(&blkg->iostat.sync); | |
| 803 | 804 | blkg_iostat_set(&delta, &cur); |
| 804 | 805 | blkg_iostat_sub(&delta, &bisc->last); |
| 805 | 806 | blkg_iostat_add(&blkg->iostat.cur, &delta); |
| 806 | 807 | blkg_iostat_add(&bisc->last, &delta); |
| 807 | − u64_stats_update_end(&blkg->iostat.sync); | |
| 808 | + u64_stats_update_end_irqrestore(&blkg->iostat.sync, flags); | |
| 808 | 809 | |
| 809 | 810 | /* propagate global delta to parent (unless that's root) */ |
| 810 | 811 | if (parent && parent->parent) { |
| 811 | − u64_stats_update_begin(&parent->iostat.sync); | |
| 812 | + flags = u64_stats_update_begin_irqsave(&parent->iostat.sync); | |
| 812 | 813 | blkg_iostat_set(&delta, &blkg->iostat.cur); |
| 813 | 814 | blkg_iostat_sub(&delta, &blkg->iostat.last); |
| 814 | 815 | blkg_iostat_add(&parent->iostat.cur, &delta); |
| 815 | 816 | blkg_iostat_add(&blkg->iostat.last, &delta); |
| 816 | − u64_stats_update_end(&parent->iostat.sync); | |
| 817 | + u64_stats_update_end_irqrestore(&parent->iostat.sync, flags); | |
| 817 | 818 | } |
| 818 | 819 | } |
| 819 | 820 | |
| @@ -848,6 +849,7 @@ static void blkcg_fill_root_iostats(void) · 28 unmodified lines | ||
| 848 | 849 | memset(&tmp, 0, sizeof(tmp)); |
| 849 | 850 | for_each_possible_cpu(cpu) { |
| 850 | 851 | struct disk_stats *cpu_dkstats; |
| 852 | + unsigned long flags; | |
| 851 | 853 | |
| 852 | 854 | cpu_dkstats = per_cpu_ptr(bdev->bd_stats, cpu); |
| 853 | 855 | tmp.ios[BLKG_IOSTAT_READ] += |
| @@ -864,9 +866,9 @@ static void blkcg_fill_root_iostats(void) · 10 unmodified lines | ||
| 864 | 866 | tmp.bytes[BLKG_IOSTAT_DISCARD] += |
| 865 | 867 | cpu_dkstats->sectors[STAT_DISCARD] << 9; |
| 866 | 868 | |
| 867 | − u64_stats_update_begin(&blkg->iostat.sync); | |
| 869 | + flags = u64_stats_update_begin_irqsave(&blkg->iostat.sync); | |
| 868 | 870 | blkg_iostat_set(&blkg->iostat.cur, &tmp); |
| 869 | − u64_stats_update_end(&blkg->iostat.sync); | |
| 871 | + u64_stats_update_end_irqrestore(&blkg->iostat.sync, flags); | |
| 870 | 872 | } |
| 871 | 873 | } |
| 872 | 874 | } |
| @@ -122,7 +122,6 @@ void blk_rq_init(struct request_queue *q, struct request *rq) · 121 unmodified lines | ||
| 122 | 122 | rq->internal_tag = BLK_MQ_NO_TAG; |
| 123 | 123 | rq->start_time_ns = ktime_get_ns(); |
| 124 | 124 | rq->part = NULL; |
| 125 | − refcount_set(&rq->ref, 1); | |
| 126 | 125 | blk_crypto_rq_set_defaults(rq); |
| 127 | 126 | } |
| 128 | 127 | EXPORT_SYMBOL(blk_rq_init); |
| @@ -262,6 +262,11 @@ static void flush_end_io(struct request *flush_rq, blk_status_t error) · 261 unmodified lines | ||
| 262 | 262 | spin_unlock_irqrestore(&fq->mq_flush_lock, flags); |
| 263 | 263 | } |
| 264 | 264 | |
| 265 | +bool is_flush_rq(struct request *rq) | |
| 266 | +{ | |
| 267 | + return rq->end_io == flush_end_io; | |
| 268 | +} | |
| 269 | + | |
| 265 | 270 | /** |
| 266 | 271 | * blk_kick_flush - consider issuing flush request |
| 267 | 272 | * @q: request_queue being kicked |
| @@ -329,6 +334,14 @@ static void blk_kick_flush(struct request_queue *q, struct blk_flush_queue *fq, · 61 unmodified lines | ||
| 329 | 334 | flush_rq->rq_flags |= RQF_FLUSH_SEQ; |
| 330 | 335 | flush_rq->rq_disk = first_rq->rq_disk; |
| 331 | 336 | flush_rq->end_io = flush_end_io; |
| 337 | + /* | |
| 338 | + * Order WRITE ->end_io and WRITE rq->ref, and its pair is the one | |
| 339 | + * implied in refcount_inc_not_zero() called from | |
| 340 | + * blk_mq_find_and_get_req(), which orders WRITE/READ flush_rq->ref | |
| 341 | + * and READ flush_rq->end_io | |
| 342 | + */ | |
| 343 | + smp_wmb(); | |
| 344 | + refcount_set(&flush_rq->ref, 1); | |
| 332 | 345 | |
| 333 | 346 | blk_flush_queue_rq(flush_rq, false); |
| 334 | 347 | } |
| @@ -1440,16 +1440,17 @@ static int iocg_wake_fn(struct wait_queue_entry *wq_entry, unsigned mode, · 1439 unmodified lines | ||
| 1440 | 1440 | return -1; |
| 1441 | 1441 | |
| 1442 | 1442 | iocg_commit_bio(ctx->iocg, wait->bio, wait->abs_cost, cost); |
| 1443 | + wait->committed = true; | |
| 1443 | 1444 | |
| 1444 | 1445 | /* |
| 1445 | 1446 | * autoremove_wake_function() removes the wait entry only when it |
| 1446 | − * actually changed the task state. We want the wait always | |
| 1447 | − * removed. Remove explicitly and use default_wake_function(). | |
| 1447 | + * actually changed the task state. We want the wait always removed. | |
| 1448 | + * Remove explicitly and use default_wake_function(). Note that the | |
| 1449 | + * order of operations is important as finish_wait() tests whether | |
| 1450 | + * @wq_entry is removed without grabbing the lock. | |
| 1448 | 1451 | */ |
| 1449 | − list_del_init(&wq_entry->entry); | |
| 1450 | − wait->committed = true; | |
| 1451 | − | |
| 1452 | 1452 | default_wake_function(wq_entry, mode, flags, key); |
| 1453 | + list_del_init_careful(&wq_entry->entry); | |
| 1453 | 1454 | return 0; |
| 1454 | 1455 | } |
| 1455 | 1456 | |
| @@ -3060,19 +3061,19 @@ static ssize_t ioc_weight_write(struct kernfs_open_file *of, char *buf, · 1604 unmodified lines | ||
| 3060 | 3061 | if (v < CGROUP_WEIGHT_MIN || v > CGROUP_WEIGHT_MAX) |
| 3061 | 3062 | return -EINVAL; |
| 3062 | 3063 | |
| 3063 | − spin_lock(&blkcg->lock); | |
| 3064 | + spin_lock_irq(&blkcg->lock); | |
| 3064 | 3065 | iocc->dfl_weight = v * WEIGHT_ONE; |
| 3065 | 3066 | hlist_for_each_entry(blkg, &blkcg->blkg_list, blkcg_node) { |
| 3066 | 3067 | struct ioc_gq *iocg = blkg_to_iocg(blkg); |
| 3067 | 3068 | |
| 3068 | 3069 | if (iocg) { |
| 3069 | − spin_lock_irq(&iocg->ioc->lock); | |
| 3070 | + spin_lock(&iocg->ioc->lock); | |
| 3070 | 3071 | ioc_now(iocg->ioc, &now); |
| 3071 | 3072 | weight_updated(iocg, &now); |
| 3072 | − spin_unlock_irq(&iocg->ioc->lock); | |
| 3073 | + spin_unlock(&iocg->ioc->lock); | |
| 3073 | 3074 | } |
| 3074 | 3075 | } |
| 3075 | − spin_unlock(&blkcg->lock); | |
| 3076 | + spin_unlock_irq(&blkcg->lock); | |
| 3076 | 3077 | |
| 3077 | 3078 | return nbytes; |
| 3078 | 3079 | } |
| @@ -833,7 +833,11 @@ static ssize_t iolatency_set_limit(struct kernfs_open_file *of, char *buf, · 832 unmodified lines | ||
| 833 | 833 | |
| 834 | 834 | enable = iolatency_set_min_lat_nsec(blkg, lat_val); |
| 835 | 835 | if (enable) { |
| 836 | − WARN_ON_ONCE(!blk_get_queue(blkg->q)); | |
| 836 | + if (!blk_get_queue(blkg->q)) { | |
| 837 | + ret = -ENODEV; | |
| 838 | + goto out; | |
| 839 | + } | |
| 840 | + | |
| 837 | 841 | blkg_get(blkg); |
| 838 | 842 | } |
| 839 | 843 | |
| @@ -515,17 +515,6 @@ void blk_mq_sched_insert_requests(struct blk_mq_hw_ctx *hctx, · 514 unmodified lines | ||
| 515 | 515 | percpu_ref_put(&q->q_usage_counter); |
| 516 | 516 | } |
| 517 | 517 | |
| 518 | −static void blk_mq_sched_free_tags(struct blk_mq_tag_set *set, | |
| 519 | − struct blk_mq_hw_ctx *hctx, | |
| 520 | − unsigned int hctx_idx) | |
| 521 | −{ | |
| 522 | − if (hctx->sched_tags) { | |
| 523 | − blk_mq_free_rqs(set, hctx->sched_tags, hctx_idx); | |
| 524 | − blk_mq_free_rq_map(hctx->sched_tags, set->flags); | |
| 525 | − hctx->sched_tags = NULL; | |
| 526 | − } | |
| 527 | −} | |
| 528 | − | |
| 529 | 518 | static int blk_mq_sched_alloc_tags(struct request_queue *q, |
| 530 | 519 | struct blk_mq_hw_ctx *hctx, |
| 531 | 520 | unsigned int hctx_idx) |
| @@ -539,8 +528,10 @@ static int blk_mq_sched_alloc_tags(struct request_queue *q, · 7 unmodified lines | ||
| 539 | 528 | return -ENOMEM; |
| 540 | 529 | |
| 541 | 530 | ret = blk_mq_alloc_rqs(set, hctx->sched_tags, hctx_idx, q->nr_requests); |
| 542 | − if (ret) | |
| 543 | − blk_mq_sched_free_tags(set, hctx, hctx_idx); | |
| 531 | + if (ret) { | |
| 532 | + blk_mq_free_rq_map(hctx->sched_tags, set->flags); | |
| 533 | + hctx->sched_tags = NULL; | |
| 534 | + } | |
| 544 | 535 | |
| 545 | 536 | return ret; |
| 546 | 537 | } |
| @@ -911,7 +911,7 @@ static bool blk_mq_req_expired(struct request *rq, unsigned long *next) · 910 unmodified lines | ||
| 911 | 911 | |
| 912 | 912 | void blk_mq_put_rq_ref(struct request *rq) |
| 913 | 913 | { |
| 914 | − if (is_flush_rq(rq, rq->mq_hctx)) | |
| 914 | + if (is_flush_rq(rq)) | |
| 915 | 915 | rq->end_io(rq, 0); |
| 916 | 916 | else if (refcount_dec_and_test(&rq->ref)) |
| 917 | 917 | __blk_mq_free_request(rq); |
| @@ -923,34 +923,14 @@ static bool blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, · 5 unmodified lines | ||
| 923 | 923 | unsigned long *next = priv; |
| 924 | 924 | |
| 925 | 925 | /* |
| 926 | − * Just do a quick check if it is expired before locking the request in | |
| 927 | − * so we're not unnecessarilly synchronizing across CPUs. | |
| 928 | − */ | |
| 929 | − if (!blk_mq_req_expired(rq, next)) | |
| 930 | − return true; | |
| 931 | − | |
| 932 | − /* | |
| 933 | − * We have reason to believe the request may be expired. Take a | |
| 934 | − * reference on the request to lock this request lifetime into its | |
| 935 | − * currently allocated context to prevent it from being reallocated in | |
| 936 | − * the event the completion by-passes this timeout handler. | |
| 937 | − * | |
| 938 | − * If the reference was already released, then the driver beat the | |
| 939 | − * timeout handler to posting a natural completion. | |
| 940 | − */ | |
| 941 | − if (!refcount_inc_not_zero(&rq->ref)) | |
| 942 | − return true; | |
| 943 | − | |
| 944 | − /* | |
| 945 | − * The request is now locked and cannot be reallocated underneath the | |
| 946 | − * timeout handler's processing. Re-verify this exact request is truly | |
| 947 | − * expired; if it is not expired, then the request was completed and | |
| 948 | − * reallocated as a new request. | |
| 926 | + * blk_mq_queue_tag_busy_iter() has locked the request, so it cannot | |
| 927 | + * be reallocated underneath the timeout handler's processing, then | |
| 928 | + * the expire check is reliable. If the request is not expired, then | |
| 929 | + * it was completed and reallocated as a new request after returning | |
| 930 | + * from blk_mq_check_expired(). | |
| 949 | 931 | */ |
| 950 | 932 | if (blk_mq_req_expired(rq, next)) |
| 951 | 933 | blk_mq_rq_timed_out(rq, reserved); |
| 952 | − | |
| 953 | − blk_mq_put_rq_ref(rq); | |
| 954 | 934 | return true; |
| 955 | 935 | } |
| 956 | 936 | |
| @@ -2994,10 +2974,12 @@ static void queue_set_hctx_shared(struct request_queue *q, bool shared) · 2037 unmodified lines | ||
| 2994 | 2974 | int i; |
| 2995 | 2975 | |
| 2996 | 2976 | queue_for_each_hw_ctx(q, hctx, i) { |
| 2997 | − if (shared) | |
| 2977 | + if (shared) { | |
| 2998 | 2978 | hctx->flags |= BLK_MQ_F_TAG_QUEUE_SHARED; |
| 2999 | − else | |
| 2979 | + } else { | |
| 2980 | + blk_mq_tag_idle(hctx); | |
| 3000 | 2981 | hctx->flags &= ~BLK_MQ_F_TAG_QUEUE_SHARED; |
| 2982 | + } | |
| 3001 | 2983 | } |
| 3002 | 2984 | } |
| 3003 | 2985 | |
| @@ -44,11 +44,7 @@ static inline void __blk_get_queue(struct request_queue *q) · 43 unmodified lines | ||
| 44 | 44 | kobject_get(&q->kobj); |
| 45 | 45 | } |
| 46 | 46 | |
| 47 | −static inline bool | |
| 48 | −is_flush_rq(struct request *req, struct blk_mq_hw_ctx *hctx) | |
| 49 | −{ | |
| 50 | − return hctx->fq->flush_rq == req; | |
| 51 | −} | |
| 47 | +bool is_flush_rq(struct request *req); | |
| 52 | 48 | |
| 53 | 49 | struct blk_flush_queue *blk_alloc_flush_queue(int node, int cmd_size, |
| 54 | 50 | gfp_t flags); |
| @@ -1079,10 +1079,9 @@ static void disk_release(struct device *dev) · 1078 unmodified lines | ||
| 1079 | 1079 | disk_release_events(disk); |
| 1080 | 1080 | kfree(disk->random); |
| 1081 | 1081 | xa_destroy(&disk->part_tbl); |
| 1082 | − bdput(disk->part0); | |
| 1083 | 1082 | if (test_bit(GD_QUEUE_REF, &disk->state) && disk->queue) |
| 1084 | 1083 | blk_put_queue(disk->queue); |
| 1085 | − kfree(disk); | |
| 1084 | + bdput(disk->part0); /* frees the disk */ | |
| 1086 | 1085 | } |
| 1087 | 1086 | struct class block_class = { |
| 1088 | 1087 | .name = "block", |
| @@ -596,13 +596,13 @@ static void kyber_insert_requests(struct blk_mq_hw_ctx *hctx, · 595 unmodified lines | ||
| 596 | 596 | struct list_head *head = &kcq->rq_list[sched_domain]; |
| 597 | 597 | |
| 598 | 598 | spin_lock(&kcq->lock); |
| 599 | + trace_block_rq_insert(rq); | |
| 599 | 600 | if (at_head) |
| 600 | 601 | list_move(&rq->queuelist, head); |
| 601 | 602 | else |
| 602 | 603 | list_move_tail(&rq->queuelist, head); |
| 603 | 604 | sbitmap_set_bit(&khd->kcq_map[sched_domain], |
| 604 | 605 | rq->mq_ctx->index_hw[hctx->type]); |
| 605 | − trace_block_rq_insert(rq); | |
| 606 | 606 | spin_unlock(&kcq->lock); |
| 607 | 607 | } |
| 608 | 608 | } |
| @@ -1,126 +0,0 @@ | ||
| 1 | −// SPDX-License-Identifier: GPL-2.0 | |
| 2 | − | |
| 3 | −#include <linux/blk-cgroup.h> | |
| 4 | −#include <linux/ioprio.h> | |
| 5 | − | |
| 6 | −#include "mq-deadline-cgroup.h" | |
| 7 | − | |
| 8 | −static struct blkcg_policy dd_blkcg_policy; | |
| 9 | − | |
| 10 | −static struct blkcg_policy_data *dd_cpd_alloc(gfp_t gfp) | |
| 11 | −{ | |
| 12 | − struct dd_blkcg *pd; | |
| 13 | − | |
| 14 | − pd = kzalloc(sizeof(*pd), gfp); | |
| 15 | − if (!pd) | |
| 16 | − return NULL; | |
| 17 | − pd->stats = alloc_percpu_gfp(typeof(*pd->stats), | |
| 18 | − GFP_KERNEL | __GFP_ZERO); | |
| 19 | − if (!pd->stats) { | |
| 20 | − kfree(pd); | |
| 21 | − return NULL; | |
| 22 | − } | |
| 23 | − return &pd->cpd; | |
| 24 | −} | |
| 25 | − | |
| 26 | −static void dd_cpd_free(struct blkcg_policy_data *cpd) | |
| 27 | −{ | |
| 28 | − struct dd_blkcg *dd_blkcg = container_of(cpd, typeof(*dd_blkcg), cpd); | |
| 29 | − | |
| 30 | − free_percpu(dd_blkcg->stats); | |
| 31 | − kfree(dd_blkcg); | |
| 32 | −} | |
| 33 | − | |
| 34 | −static struct dd_blkcg *dd_blkcg_from_pd(struct blkg_policy_data *pd) | |
| 35 | −{ | |
| 36 | − return container_of(blkcg_to_cpd(pd->blkg->blkcg, &dd_blkcg_policy), | |
| 37 | − struct dd_blkcg, cpd); | |
| 38 | −} | |
| 39 | − | |
| 40 | −/* | |
| 41 | − * Convert an association between a block cgroup and a request queue into a | |
| 42 | − * pointer to the mq-deadline information associated with a (blkcg, queue) pair. | |
| 43 | − */ | |
| 44 | −struct dd_blkcg *dd_blkcg_from_bio(struct bio *bio) | |
| 45 | −{ | |
| 46 | − struct blkg_policy_data *pd; | |
| 47 | − | |
| 48 | − pd = blkg_to_pd(bio->bi_blkg, &dd_blkcg_policy); | |
| 49 | − if (!pd) | |
| 50 | − return NULL; | |
| 51 | − | |
| 52 | − return dd_blkcg_from_pd(pd); | |
| 53 | −} | |
| 54 | − | |
| 55 | −static size_t dd_pd_stat(struct blkg_policy_data *pd, char *buf, size_t size) | |
| 56 | −{ | |
| 57 | − static const char *const prio_class_name[] = { | |
| 58 | − [IOPRIO_CLASS_NONE] = "NONE", | |
| 59 | − [IOPRIO_CLASS_RT] = "RT", | |
| 60 | − [IOPRIO_CLASS_BE] = "BE", | |
| 61 | − [IOPRIO_CLASS_IDLE] = "IDLE", | |
| 62 | − }; | |
| 63 | − struct dd_blkcg *blkcg = dd_blkcg_from_pd(pd); | |
| 64 | − int res = 0; | |
| 65 | − u8 prio; | |
| 66 | − | |
| 67 | − for (prio = 0; prio < ARRAY_SIZE(blkcg->stats->stats); prio++) | |
| 68 | − res += scnprintf(buf + res, size - res, | |
| 69 | − " [%s] dispatched=%u inserted=%u merged=%u", | |
| 70 | − prio_class_name[prio], | |
| 71 | − ddcg_sum(blkcg, dispatched, prio) + | |
| 72 | − ddcg_sum(blkcg, merged, prio) - | |
| 73 | − ddcg_sum(blkcg, completed, prio), | |
| 74 | − ddcg_sum(blkcg, inserted, prio) - | |
| 75 | − ddcg_sum(blkcg, completed, prio), | |
| 76 | − ddcg_sum(blkcg, merged, prio)); | |
| 77 | − | |
| 78 | − return res; | |
| 79 | −} | |
| 80 | − | |
| 81 | −static struct blkg_policy_data *dd_pd_alloc(gfp_t gfp, struct request_queue *q, | |
| 82 | − struct blkcg *blkcg) | |
| 83 | −{ | |
| 84 | − struct dd_blkg *pd; | |
| 85 | − | |
| 86 | − pd = kzalloc(sizeof(*pd), gfp); | |
| 87 | − if (!pd) | |
| 88 | − return NULL; | |
| 89 | − return &pd->pd; | |
| 90 | −} | |
| 91 | − | |
| 92 | −static void dd_pd_free(struct blkg_policy_data *pd) | |
| 93 | −{ | |
| 94 | − struct dd_blkg *dd_blkg = container_of(pd, typeof(*dd_blkg), pd); | |
| 95 | − | |
| 96 | − kfree(dd_blkg); | |
| 97 | −} | |
| 98 | − | |
| 99 | −static struct blkcg_policy dd_blkcg_policy = { | |
| 100 | − .cpd_alloc_fn = dd_cpd_alloc, | |
| 101 | − .cpd_free_fn = dd_cpd_free, | |
| 102 | − | |
| 103 | − .pd_alloc_fn = dd_pd_alloc, | |
| 104 | − .pd_free_fn = dd_pd_free, | |
| 105 | − .pd_stat_fn = dd_pd_stat, | |
| 106 | −}; | |
| 107 | − | |
| 108 | −int dd_activate_policy(struct request_queue *q) | |
| 109 | −{ | |
| 110 | − return blkcg_activate_policy(q, &dd_blkcg_policy); | |
| 111 | −} | |
| 112 | − | |
| 113 | −void dd_deactivate_policy(struct request_queue *q) | |
| 114 | −{ | |
| 115 | − blkcg_deactivate_policy(q, &dd_blkcg_policy); | |
| 116 | −} | |
| 117 | − | |
| 118 | −int __init dd_blkcg_init(void) | |
| 119 | −{ | |
| 120 | − return blkcg_policy_register(&dd_blkcg_policy); | |
| 121 | −} | |
| 122 | − | |
| 123 | −void __exit dd_blkcg_exit(void) | |
| 124 | −{ | |
| 125 | − blkcg_policy_unregister(&dd_blkcg_policy); | |
| 126 | −} | |
| @@ -1,114 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | − | |
| 3 | −#if !defined(_MQ_DEADLINE_CGROUP_H_) | |
| 4 | −#define _MQ_DEADLINE_CGROUP_H_ | |
| 5 | − | |
| 6 | −#include <linux/blk-cgroup.h> | |
| 7 | − | |
| 8 | −struct request_queue; | |
| 9 | − | |
| 10 | −/** | |
| 11 | − * struct io_stats_per_prio - I/O statistics per I/O priority class. | |
| 12 | − * @inserted: Number of inserted requests. | |
| 13 | − * @merged: Number of merged requests. | |
| 14 | − * @dispatched: Number of dispatched requests. | |
| 15 | − * @completed: Number of I/O completions. | |
| 16 | − */ | |
| 17 | −struct io_stats_per_prio { | |
| 18 | − local_t inserted; | |
| 19 | − local_t merged; | |
| 20 | − local_t dispatched; | |
| 21 | − local_t completed; | |
| 22 | −}; | |
| 23 | − | |
| 24 | −/* I/O statistics per I/O cgroup per I/O priority class (IOPRIO_CLASS_*). */ | |
| 25 | −struct blkcg_io_stats { | |
| 26 | − struct io_stats_per_prio stats[4]; | |
| 27 | −}; | |
| 28 | − | |
| 29 | −/** | |
| 30 | − * struct dd_blkcg - Per cgroup data. | |
| 31 | − * @cpd: blkcg_policy_data structure. | |
| 32 | − * @stats: I/O statistics. | |
| 33 | − */ | |
| 34 | −struct dd_blkcg { | |
| 35 | − struct blkcg_policy_data cpd; /* must be the first member */ | |
| 36 | − struct blkcg_io_stats __percpu *stats; | |
| 37 | −}; | |
| 38 | − | |
| 39 | −/* | |
| 40 | − * Count one event of type 'event_type' and with I/O priority class | |
| 41 | − * 'prio_class'. | |
| 42 | − */ | |
| 43 | −#define ddcg_count(ddcg, event_type, prio_class) do { \ | |
| 44 | −if (ddcg) { \ | |
| 45 | − struct blkcg_io_stats *io_stats = get_cpu_ptr((ddcg)->stats); \ | |
| 46 | − \ | |
| 47 | − BUILD_BUG_ON(!__same_type((ddcg), struct dd_blkcg *)); \ | |
| 48 | − BUILD_BUG_ON(!__same_type((prio_class), u8)); \ | |
| 49 | − local_inc(&io_stats->stats[(prio_class)].event_type); \ | |
| 50 | − put_cpu_ptr(io_stats); \ | |
| 51 | −} \ | |
| 52 | −} while (0) | |
| 53 | − | |
| 54 | −/* | |
| 55 | − * Returns the total number of ddcg_count(ddcg, event_type, prio_class) calls | |
| 56 | − * across all CPUs. No locking or barriers since it is fine if the returned | |
| 57 | − * sum is slightly outdated. | |
| 58 | − */ | |
| 59 | −#define ddcg_sum(ddcg, event_type, prio) ({ \ | |
| 60 | − unsigned int cpu; \ | |
| 61 | − u32 sum = 0; \ | |
| 62 | − \ | |
| 63 | − BUILD_BUG_ON(!__same_type((ddcg), struct dd_blkcg *)); \ | |
| 64 | − BUILD_BUG_ON(!__same_type((prio), u8)); \ | |
| 65 | − for_each_present_cpu(cpu) \ | |
| 66 | − sum += local_read(&per_cpu_ptr((ddcg)->stats, cpu)-> \ | |
| 67 | − stats[(prio)].event_type); \ | |
| 68 | − sum; \ | |
| 69 | −}) | |
| 70 | − | |
| 71 | −#ifdef CONFIG_BLK_CGROUP | |
| 72 | − | |
| 73 | −/** | |
| 74 | − * struct dd_blkg - Per (cgroup, request queue) data. | |
| 75 | − * @pd: blkg_policy_data structure. | |
| 76 | − */ | |
| 77 | −struct dd_blkg { | |
| 78 | − struct blkg_policy_data pd; /* must be the first member */ | |
| 79 | −}; | |
| 80 | − | |
| 81 | −struct dd_blkcg *dd_blkcg_from_bio(struct bio *bio); | |
| 82 | −int dd_activate_policy(struct request_queue *q); | |
| 83 | −void dd_deactivate_policy(struct request_queue *q); | |
| 84 | −int __init dd_blkcg_init(void); | |
| 85 | −void __exit dd_blkcg_exit(void); | |
| 86 | − | |
| 87 | −#else /* CONFIG_BLK_CGROUP */ | |
| 88 | − | |
| 89 | −static inline struct dd_blkcg *dd_blkcg_from_bio(struct bio *bio) | |
| 90 | −{ | |
| 91 | − return NULL; | |
| 92 | −} | |
| 93 | − | |
| 94 | −static inline int dd_activate_policy(struct request_queue *q) | |
| 95 | −{ | |
| 96 | − return 0; | |
| 97 | −} | |
| 98 | − | |
| 99 | −static inline void dd_deactivate_policy(struct request_queue *q) | |
| 100 | −{ | |
| 101 | −} | |
| 102 | − | |
| 103 | −static inline int dd_blkcg_init(void) | |
| 104 | −{ | |
| 105 | − return 0; | |
| 106 | −} | |
| 107 | − | |
| 108 | −static inline void dd_blkcg_exit(void) | |
| 109 | −{ | |
| 110 | −} | |
| 111 | − | |
| 112 | −#endif /* CONFIG_BLK_CGROUP */ | |
| 113 | − | |
| 114 | −#endif /* _MQ_DEADLINE_CGROUP_H_ */ | |
| @@ -25,7 +25,6 @@ · 24 unmodified lines | ||
| 25 | 25 | #include "blk-mq-debugfs.h" |
| 26 | 26 | #include "blk-mq-tag.h" |
| 27 | 27 | #include "blk-mq-sched.h" |
| 28 | −#include "mq-deadline-cgroup.h" | |
| 29 | 28 | |
| 30 | 29 | /* |
| 31 | 30 | * See Documentation/block/deadline-iosched.rst |
| @@ -57,6 +56,14 @@ enum dd_prio { · 25 unmodified lines | ||
| 57 | 56 | |
| 58 | 57 | enum { DD_PRIO_COUNT = 3 }; |
| 59 | 58 | |
| 59 | +/* I/O statistics per I/O priority. */ | |
| 60 | +struct io_stats_per_prio { | |
| 61 | + local_t inserted; | |
| 62 | + local_t merged; | |
| 63 | + local_t dispatched; | |
| 64 | + local_t completed; | |
| 65 | +}; | |
| 66 | + | |
| 60 | 67 | /* I/O statistics for all I/O priorities (enum dd_prio). */ |
| 61 | 68 | struct io_stats { |
| 62 | 69 | struct io_stats_per_prio stats[DD_PRIO_COUNT]; |
| @@ -79,9 +86,6 @@ struct deadline_data { · 16 unmodified lines | ||
| 79 | 86 | * run time data |
| 80 | 87 | */ |
| 81 | 88 | |
| 82 | − /* Request queue that owns this data structure. */ | |
| 83 | − struct request_queue *queue; | |
| 84 | − | |
| 85 | 89 | struct dd_per_prio per_prio[DD_PRIO_COUNT]; |
| 86 | 90 | |
| 87 | 91 | /* Data direction of latest dispatched request. */ |
| @@ -234,10 +238,8 @@ static void dd_merged_requests(struct request_queue *q, struct request *req, · 146 unmodified lines | ||
| 234 | 238 | struct deadline_data *dd = q->elevator->elevator_data; |
| 235 | 239 | const u8 ioprio_class = dd_rq_ioclass(next); |
| 236 | 240 | const enum dd_prio prio = ioprio_class_to_prio[ioprio_class]; |
| 237 | − struct dd_blkcg *blkcg = next->elv.priv[0]; | |
| 238 | 241 | |
| 239 | 242 | dd_count(dd, merged, prio); |
| 240 | − ddcg_count(blkcg, merged, ioprio_class); | |
| 241 | 243 | |
| 242 | 244 | /* |
| 243 | 245 | * if next expires before rq, assign its expire time to rq |
| @@ -375,7 +377,6 @@ static struct request *__dd_dispatch_request(struct deadline_data *dd, · 131 unmodified lines | ||
| 375 | 377 | { |
| 376 | 378 | struct request *rq, *next_rq; |
| 377 | 379 | enum dd_data_dir data_dir; |
| 378 | − struct dd_blkcg *blkcg; | |
| 379 | 380 | enum dd_prio prio; |
| 380 | 381 | u8 ioprio_class; |
| 381 | 382 | |
| @@ -474,8 +475,6 @@ done: · 92 unmodified lines | ||
| 474 | 475 | ioprio_class = dd_rq_ioclass(rq); |
| 475 | 476 | prio = ioprio_class_to_prio[ioprio_class]; |
| 476 | 477 | dd_count(dd, dispatched, prio); |
| 477 | − blkcg = rq->elv.priv[0]; | |
| 478 | − ddcg_count(blkcg, dispatched, ioprio_class); | |
| 479 | 478 | /* |
| 480 | 479 | * If the request needs its target zone locked, do it. |
| 481 | 480 | */ |
| @@ -569,8 +568,6 @@ static void dd_exit_sched(struct elevator_queue *e) · 87 unmodified lines | ||
| 569 | 568 | struct deadline_data *dd = e->elevator_data; |
| 570 | 569 | enum dd_prio prio; |
| 571 | 570 | |
| 572 | − dd_deactivate_policy(dd->queue); | |
| 573 | − | |
| 574 | 571 | for (prio = 0; prio <= DD_PRIO_MAX; prio++) { |
| 575 | 572 | struct dd_per_prio *per_prio = &dd->per_prio[prio]; |
| 576 | 573 | |
| @@ -584,7 +581,7 @@ static void dd_exit_sched(struct elevator_queue *e) · 7 unmodified lines | ||
| 584 | 581 | } |
| 585 | 582 | |
| 586 | 583 | /* |
| 587 | − * Initialize elevator private data (deadline_data) and associate with blkcg. | |
| 584 | + * initialize elevator private data (deadline_data). | |
| 588 | 585 | */ |
| 589 | 586 | static int dd_init_sched(struct request_queue *q, struct elevator_type *e) |
| 590 | 587 | { |
| @@ -593,12 +590,6 @@ static int dd_init_sched(struct request_queue *q, struct elevator_type *e) · 2 unmodified lines | ||
| 593 | 590 | enum dd_prio prio; |
| 594 | 591 | int ret = -ENOMEM; |
| 595 | 592 | |
| 596 | − /* | |
| 597 | − * Initialization would be very tricky if the queue is not frozen, | |
| 598 | − * hence the warning statement below. | |
| 599 | − */ | |
| 600 | − WARN_ON_ONCE(!percpu_ref_is_zero(&q->q_usage_counter)); | |
| 601 | − | |
| 602 | 593 | eq = elevator_alloc(q, e); |
| 603 | 594 | if (!eq) |
| 604 | 595 | return ret; |
| @@ -614,8 +605,6 @@ static int dd_init_sched(struct request_queue *q, struct elevator_type *e) · 9 unmodified lines | ||
| 614 | 605 | if (!dd->stats) |
| 615 | 606 | goto free_dd; |
| 616 | 607 | |
| 617 | − dd->queue = q; | |
| 618 | − | |
| 619 | 608 | for (prio = 0; prio <= DD_PRIO_MAX; prio++) { |
| 620 | 609 | struct dd_per_prio *per_prio = &dd->per_prio[prio]; |
| 621 | 610 | |
| @@ -635,17 +624,9 @@ static int dd_init_sched(struct request_queue *q, struct elevator_type *e) · 13 unmodified lines | ||
| 635 | 624 | spin_lock_init(&dd->lock); |
| 636 | 625 | spin_lock_init(&dd->zone_lock); |
| 637 | 626 | |
| 638 | − ret = dd_activate_policy(q); | |
| 639 | − if (ret) | |
| 640 | − goto free_stats; | |
| 641 | − | |
| 642 | − ret = 0; | |
| 643 | 627 | q->elevator = eq; |
| 644 | 628 | return 0; |
| 645 | 629 | |
| 646 | −free_stats: | |
| 647 | − free_percpu(dd->stats); | |
| 648 | − | |
| 649 | 630 | free_dd: |
| 650 | 631 | kfree(dd); |
| 651 | 632 | |
| @@ -718,7 +699,6 @@ static void dd_insert_request(struct blk_mq_hw_ctx *hctx, struct request *rq, · 66 unmodified lines | ||
| 718 | 699 | u8 ioprio_class = IOPRIO_PRIO_CLASS(ioprio); |
| 719 | 700 | struct dd_per_prio *per_prio; |
| 720 | 701 | enum dd_prio prio; |
| 721 | − struct dd_blkcg *blkcg; | |
| 722 | 702 | LIST_HEAD(free); |
| 723 | 703 | |
| 724 | 704 | lockdep_assert_held(&dd->lock); |
| @@ -729,18 +709,8 @@ static void dd_insert_request(struct blk_mq_hw_ctx *hctx, struct request *rq, · 4 unmodified lines | ||
| 729 | 709 | */ |
| 730 | 710 | blk_req_zone_write_unlock(rq); |
| 731 | 711 | |
| 732 | − /* | |
| 733 | − * If a block cgroup has been associated with the submitter and if an | |
| 734 | − * I/O priority has been set in the associated block cgroup, use the | |
| 735 | − * lowest of the cgroup priority and the request priority for the | |
| 736 | − * request. If no priority has been set in the request, use the cgroup | |
| 737 | − * priority. | |
| 738 | − */ | |
| 739 | 712 | prio = ioprio_class_to_prio[ioprio_class]; |
| 740 | 713 | dd_count(dd, inserted, prio); |
| 741 | − blkcg = dd_blkcg_from_bio(rq->bio); | |
| 742 | − ddcg_count(blkcg, inserted, ioprio_class); | |
| 743 | − rq->elv.priv[0] = blkcg; | |
| 744 | 714 | |
| 745 | 715 | if (blk_mq_sched_try_insert_merge(q, rq, &free)) { |
| 746 | 716 | blk_mq_free_requests(&free); |
| @@ -789,10 +759,12 @@ static void dd_insert_requests(struct blk_mq_hw_ctx *hctx, · 42 unmodified lines | ||
| 789 | 759 | spin_unlock(&dd->lock); |
| 790 | 760 | } |
| 791 | 761 | |
| 792 | −/* Callback from inside blk_mq_rq_ctx_init(). */ | |
| 762 | +/* | |
| 763 | + * Nothing to do here. This is defined only to ensure that .finish_request | |
| 764 | + * method is called upon request completion. | |
| 765 | + */ | |
| 793 | 766 | static void dd_prepare_request(struct request *rq) |
| 794 | 767 | { |
| 795 | − rq->elv.priv[0] = NULL; | |
| 796 | 768 | } |
| 797 | 769 | |
| 798 | 770 | /* |
| @@ -815,13 +787,11 @@ static void dd_finish_request(struct request *rq) · 16 unmodified lines | ||
| 815 | 787 | { |
| 816 | 788 | struct request_queue *q = rq->q; |
| 817 | 789 | struct deadline_data *dd = q->elevator->elevator_data; |
| 818 | − struct dd_blkcg *blkcg = rq->elv.priv[0]; | |
| 819 | 790 | const u8 ioprio_class = dd_rq_ioclass(rq); |
| 820 | 791 | const enum dd_prio prio = ioprio_class_to_prio[ioprio_class]; |
| 821 | 792 | struct dd_per_prio *per_prio = &dd->per_prio[prio]; |
| 822 | 793 | |
| 823 | 794 | dd_count(dd, completed, prio); |
| 824 | − ddcg_count(blkcg, completed, ioprio_class); | |
| 825 | 795 | |
| 826 | 796 | if (blk_queue_is_zoned(q)) { |
| 827 | 797 | unsigned long flags; |
| @@ -1144,26 +1114,11 @@ MODULE_ALIAS("mq-deadline-iosched"); · 316 unmodified lines | ||
| 1144 | 1114 | |
| 1145 | 1115 | static int __init deadline_init(void) |
| 1146 | 1116 | { |
| 1147 | − int ret; | |
| 1148 | − | |
| 1149 | − ret = elv_register(&mq_deadline); | |
| 1150 | − if (ret) | |
| 1151 | − goto out; | |
| 1152 | − ret = dd_blkcg_init(); | |
| 1153 | − if (ret) | |
| 1154 | − goto unreg; | |
| 1155 | − | |
| 1156 | −out: | |
| 1157 | − return ret; | |
| 1158 | − | |
| 1159 | −unreg: | |
| 1160 | − elv_unregister(&mq_deadline); | |
| 1161 | − goto out; | |
| 1117 | + return elv_register(&mq_deadline); | |
| 1162 | 1118 | } |
| 1163 | 1119 | |
| 1164 | 1120 | static void __exit deadline_exit(void) |
| 1165 | 1121 | { |
| 1166 | − dd_blkcg_exit(); | |
| 1167 | 1122 | elv_unregister(&mq_deadline); |
| 1168 | 1123 | } |
| 1169 | 1124 | |
| @@ -1,5 +1,5 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | −/** | |
| 2 | +/* | |
| 3 | 3 | * ldm - Support for Windows Logical Disk Manager (Dynamic Disks) |
| 4 | 4 | * |
| 5 | 5 | * Copyright (C) 2001,2002 Richard Russon <ldm@flatcap.org> |
| @@ -1768,7 +1768,7 @@ config CRYPTO_DRBG_HMAC · 1767 unmodified lines | ||
| 1768 | 1768 | bool |
| 1769 | 1769 | default y |
| 1770 | 1770 | select CRYPTO_HMAC |
| 1771 | − select CRYPTO_SHA256 | |
| 1771 | + select CRYPTO_SHA512 | |
| 1772 | 1772 | |
| 1773 | 1773 | config CRYPTO_DRBG_HASH |
| 1774 | 1774 | bool "Enable Hash DRBG" |
| @@ -370,7 +370,7 @@ config ACPI_TABLE_UPGRADE · 369 unmodified lines | ||
| 370 | 370 | config ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD |
| 371 | 371 | bool "Override ACPI tables from built-in initrd" |
| 372 | 372 | depends on ACPI_TABLE_UPGRADE |
| 373 | − depends on INITRAMFS_SOURCE!="" && INITRAMFS_COMPRESSION="" | |
| 373 | + depends on INITRAMFS_SOURCE!="" && INITRAMFS_COMPRESSION_NONE | |
| 374 | 374 | help |
| 375 | 375 | This option provides functionality to override arbitrary ACPI tables |
| 376 | 376 | from built-in uncompressed initrd. |
| @@ -379,13 +379,6 @@ acpi_ns_repair_CID(struct acpi_evaluate_info *info, · 378 unmodified lines | ||
| 379 | 379 | |
| 380 | 380 | (*element_ptr)->common.reference_count = |
| 381 | 381 | original_ref_count; |
| 382 | − | |
| 383 | − /* | |
| 384 | − * The original_element holds a reference from the package object | |
| 385 | − * that represents _HID. Since a new element was created by _HID, | |
| 386 | − * remove the reference from the _CID package. | |
| 387 | − */ | |
| 388 | − acpi_ut_remove_reference(original_element); | |
| 389 | 382 | } |
| 390 | 383 | |
| 391 | 384 | element_ptr++; |
| @@ -9,6 +9,42 @@ · 8 unmodified lines | ||
| 9 | 9 | #include <linux/module.h> |
| 10 | 10 | #include <linux/platform_device.h> |
| 11 | 11 | |
| 12 | +struct pch_fivr_resp { | |
| 13 | + u64 status; | |
| 14 | + u64 result; | |
| 15 | +}; | |
| 16 | + | |
| 17 | +static int pch_fivr_read(acpi_handle handle, char *method, struct pch_fivr_resp *fivr_resp) | |
| 18 | +{ | |
| 19 | + struct acpi_buffer resp = { sizeof(struct pch_fivr_resp), fivr_resp}; | |
| 20 | + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
| 21 | + struct acpi_buffer format = { sizeof("NN"), "NN" }; | |
| 22 | + union acpi_object *obj; | |
| 23 | + acpi_status status; | |
| 24 | + int ret = -EFAULT; | |
| 25 | + | |
| 26 | + status = acpi_evaluate_object(handle, method, NULL, &buffer); | |
| 27 | + if (ACPI_FAILURE(status)) | |
| 28 | + return ret; | |
| 29 | + | |
| 30 | + obj = buffer.pointer; | |
| 31 | + if (!obj || obj->type != ACPI_TYPE_PACKAGE) | |
| 32 | + goto release_buffer; | |
| 33 | + | |
| 34 | + status = acpi_extract_package(obj, &format, &resp); | |
| 35 | + if (ACPI_FAILURE(status)) | |
| 36 | + goto release_buffer; | |
| 37 | + | |
| 38 | + if (fivr_resp->status) | |
| 39 | + goto release_buffer; | |
| 40 | + | |
| 41 | + ret = 0; | |
| 42 | + | |
| 43 | +release_buffer: | |
| 44 | + kfree(buffer.pointer); | |
| 45 | + return ret; | |
| 46 | +} | |
| 47 | + | |
| 12 | 48 | /* |
| 13 | 49 | * Presentation of attributes which are defined for INT1045 |
| 14 | 50 | * They are: |
| @@ -23,15 +59,14 @@ static ssize_t name##_show(struct device *dev,\ · 8 unmodified lines | ||
| 23 | 59 | char *buf)\ |
| 24 | 60 | {\ |
| 25 | 61 | struct acpi_device *acpi_dev = dev_get_drvdata(dev);\ |
| 26 | − unsigned long long val;\ | |
| 27 | − acpi_status status;\ | |
| 62 | + struct pch_fivr_resp fivr_resp;\ | |
| 63 | + int status;\ | |
| 28 | 64 | \ |
| 29 | − status = acpi_evaluate_integer(acpi_dev->handle, #method,\ | |
| 30 | − NULL, &val);\ | |
| 31 | − if (ACPI_SUCCESS(status))\ | |
| 32 | − return sprintf(buf, "%d\n", (int)val);\ | |
| 33 | − else\ | |
| 34 | − return -EINVAL;\ | |
| 65 | + status = pch_fivr_read(acpi_dev->handle, #method, &fivr_resp);\ | |
| 66 | + if (status)\ | |
| 67 | + return status;\ | |
| 68 | +\ | |
| 69 | + return sprintf(buf, "%llu\n", fivr_resp.result);\ | |
| 35 | 70 | } |
| 36 | 71 | |
| 37 | 72 | #define PCH_FIVR_STORE(name, method) \ |
| @@ -3021,6 +3021,9 @@ static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc, · 3020 unmodified lines | ||
| 3021 | 3021 | struct acpi_nfit_memory_map *memdev = nfit_memdev->memdev; |
| 3022 | 3022 | struct nd_mapping_desc *mapping; |
| 3023 | 3023 | |
| 3024 | + /* range index 0 == unmapped in SPA or invalid-SPA */ | |
| 3025 | + if (memdev->range_index == 0 || spa->range_index == 0) | |
| 3026 | + continue; | |
| 3024 | 3027 | if (memdev->range_index != spa->range_index) |
| 3025 | 3028 | continue; |
| 3026 | 3029 | if (count >= ND_MAX_MAPPINGS) { |
| @@ -292,6 +292,12 @@ void __init init_prmt(void) · 291 unmodified lines | ||
| 292 | 292 | int mc = acpi_table_parse_entries(ACPI_SIG_PRMT, sizeof(struct acpi_table_prmt) + |
| 293 | 293 | sizeof (struct acpi_table_prmt_header), |
| 294 | 294 | 0, acpi_parse_prmt, 0); |
| 295 | + /* | |
| 296 | + * Return immediately if PRMT table is not present or no PRM module found. | |
| 297 | + */ | |
| 298 | + if (mc <= 0) | |
| 299 | + return; | |
| 300 | + | |
| 295 | 301 | pr_info("PRM: found %u modules\n", mc); |
| 296 | 302 | |
| 297 | 303 | status = acpi_install_address_space_handler(ACPI_ROOT_OBJECT, |
| @@ -423,13 +423,6 @@ static void acpi_dev_get_irqresource(struct resource *res, u32 gsi, · 422 unmodified lines | ||
| 423 | 423 | } |
| 424 | 424 | } |
| 425 | 425 | |
| 426 | −static bool irq_is_legacy(struct acpi_resource_irq *irq) | |
| 427 | −{ | |
| 428 | − return irq->triggering == ACPI_EDGE_SENSITIVE && | |
| 429 | − irq->polarity == ACPI_ACTIVE_HIGH && | |
| 430 | − irq->shareable == ACPI_EXCLUSIVE; | |
| 431 | −} | |
| 432 | − | |
| 433 | 426 | /** |
| 434 | 427 | * acpi_dev_resource_interrupt - Extract ACPI interrupt resource information. |
| 435 | 428 | * @ares: Input ACPI resource object. |
| @@ -468,7 +461,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index, · 32 unmodified lines | ||
| 468 | 461 | } |
| 469 | 462 | acpi_dev_get_irqresource(res, irq->interrupts[index], |
| 470 | 463 | irq->triggering, irq->polarity, |
| 471 | − irq->shareable, irq_is_legacy(irq)); | |
| 464 | + irq->shareable, true); | |
| 472 | 465 | break; |
| 473 | 466 | case ACPI_RESOURCE_TYPE_EXTENDED_IRQ: |
| 474 | 467 | ext_irq = &ares->data.extended_irq; |
| @@ -860,11 +860,9 @@ EXPORT_SYMBOL(acpi_dev_present); · 859 unmodified lines | ||
| 860 | 860 | * Return the next match of ACPI device if another matching device was present |
| 861 | 861 | * at the moment of invocation, or NULL otherwise. |
| 862 | 862 | * |
| 863 | − * FIXME: The function does not tolerate the sudden disappearance of @adev, e.g. | |
| 864 | − * in the case of a hotplug event. That said, the caller should ensure that | |
| 865 | − * this will never happen. | |
| 866 | − * | |
| 867 | 863 | * The caller is responsible for invoking acpi_dev_put() on the returned device. |
| 864 | + * On the other hand the function invokes acpi_dev_put() on the given @adev | |
| 865 | + * assuming that its reference counter had been increased beforehand. | |
| 868 | 866 | * |
| 869 | 867 | * See additional information in acpi_dev_present() as well. |
| 870 | 868 | */ |
| @@ -880,6 +878,7 @@ acpi_dev_get_next_match_dev(struct acpi_device *adev, const char *hid, const cha · 9 unmodified lines | ||
| 880 | 878 | match.hrv = hrv; |
| 881 | 879 | |
| 882 | 880 | dev = bus_find_device(&acpi_bus_type, start, &match, acpi_dev_match_cb); |
| 881 | + acpi_dev_put(adev); | |
| 883 | 882 | return dev ? to_acpi_device(dev) : NULL; |
| 884 | 883 | } |
| 885 | 884 | EXPORT_SYMBOL(acpi_dev_get_next_match_dev); |
| @@ -378,19 +378,25 @@ static int lps0_device_attach(struct acpi_device *adev, · 377 unmodified lines | ||
| 378 | 378 | * AMDI0006: |
| 379 | 379 | * - should use rev_id 0x0 |
| 380 | 380 | * - function mask = 0x3: Should use Microsoft method |
| 381 | + * AMDI0007: | |
| 382 | + * - Should use rev_id 0x2 | |
| 383 | + * - Should only use AMD method | |
| 381 | 384 | */ |
| 382 | 385 | const char *hid = acpi_device_hid(adev); |
| 383 | − rev_id = 0; | |
| 386 | + rev_id = strcmp(hid, "AMDI0007") ? 0 : 2; | |
| 384 | 387 | lps0_dsm_func_mask = validate_dsm(adev->handle, |
| 385 | 388 | ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid); |
| 386 | 389 | lps0_dsm_func_mask_microsoft = validate_dsm(adev->handle, |
| 387 | − ACPI_LPS0_DSM_UUID_MICROSOFT, rev_id, | |
| 390 | + ACPI_LPS0_DSM_UUID_MICROSOFT, 0, | |
| 388 | 391 | &lps0_dsm_guid_microsoft); |
| 389 | 392 | if (lps0_dsm_func_mask > 0x3 && (!strcmp(hid, "AMD0004") || |
| 390 | 393 | !strcmp(hid, "AMDI0005"))) { |
| 391 | 394 | lps0_dsm_func_mask = (lps0_dsm_func_mask << 1) | 0x1; |
| 392 | 395 | acpi_handle_debug(adev->handle, "_DSM UUID %s: Adjusted function mask: 0x%x\n", |
| 393 | 396 | ACPI_LPS0_DSM_UUID_AMD, lps0_dsm_func_mask); |
| 397 | + } else if (lps0_dsm_func_mask_microsoft > 0 && !strcmp(hid, "AMDI0007")) { | |
| 398 | + lps0_dsm_func_mask_microsoft = -EINVAL; | |
| 399 | + acpi_handle_debug(adev->handle, "_DSM Using AMD method\n"); | |
| 394 | 400 | } |
| 395 | 401 | } else { |
| 396 | 402 | rev_id = 1; |
| @@ -446,7 +452,7 @@ int acpi_s2idle_prepare_late(void) · 49 unmodified lines | ||
| 446 | 452 | if (lps0_dsm_func_mask_microsoft > 0) { |
| 447 | 453 | acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF, |
| 448 | 454 | lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); |
| 449 | − acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_EXIT, | |
| 455 | + acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_ENTRY, | |
| 450 | 456 | lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); |
| 451 | 457 | acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY, |
| 452 | 458 | lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); |
| @@ -473,7 +479,7 @@ void acpi_s2idle_restore_early(void) · 20 unmodified lines | ||
| 473 | 479 | if (lps0_dsm_func_mask_microsoft > 0) { |
| 474 | 480 | acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT, |
| 475 | 481 | lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); |
| 476 | − acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_ENTRY, | |
| 482 | + acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_EXIT, | |
| 477 | 483 | lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); |
| 478 | 484 | acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON, |
| 479 | 485 | lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); |
| @@ -637,6 +637,20 @@ unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf, · 636 unmodified lines | ||
| 637 | 637 | } |
| 638 | 638 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); |
| 639 | 639 | |
| 640 | +static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page, | |
| 641 | + unsigned int offset, size_t xfer_size) | |
| 642 | +{ | |
| 643 | + bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
| 644 | + unsigned char *buf; | |
| 645 | + | |
| 646 | + buf = kmap_atomic(page); | |
| 647 | + qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write); | |
| 648 | + kunmap_atomic(buf); | |
| 649 | + | |
| 650 | + if (!do_write && !PageSlab(page)) | |
| 651 | + flush_dcache_page(page); | |
| 652 | +} | |
| 653 | + | |
| 640 | 654 | /** |
| 641 | 655 | * ata_pio_sector - Transfer a sector of data. |
| 642 | 656 | * @qc: Command on going |
| @@ -648,11 +662,9 @@ EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); · 5 unmodified lines | ||
| 648 | 662 | */ |
| 649 | 663 | static void ata_pio_sector(struct ata_queued_cmd *qc) |
| 650 | 664 | { |
| 651 | − int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
| 652 | 665 | struct ata_port *ap = qc->ap; |
| 653 | 666 | struct page *page; |
| 654 | 667 | unsigned int offset; |
| 655 | − unsigned char *buf; | |
| 656 | 668 | |
| 657 | 669 | if (!qc->cursg) { |
| 658 | 670 | qc->curbytes = qc->nbytes; |
| @@ -670,13 +682,20 @@ static void ata_pio_sector(struct ata_queued_cmd *qc) · 11 unmodified lines | ||
| 670 | 682 | |
| 671 | 683 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); |
| 672 | 684 | |
| 673 | − /* do the actual data transfer */ | |
| 674 | − buf = kmap_atomic(page); | |
| 675 | − ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, do_write); | |
| 676 | − kunmap_atomic(buf); | |
| 685 | + /* | |
| 686 | + * Split the transfer when it splits a page boundary. Note that the | |
| 687 | + * split still has to be dword aligned like all ATA data transfers. | |
| 688 | + */ | |
| 689 | + WARN_ON_ONCE(offset % 4); | |
| 690 | + if (offset + qc->sect_size > PAGE_SIZE) { | |
| 691 | + unsigned int split_len = PAGE_SIZE - offset; | |
| 677 | 692 | |
| 678 | − if (!do_write && !PageSlab(page)) | |
| 679 | − flush_dcache_page(page); | |
| 693 | + ata_pio_xfer(qc, page, offset, split_len); | |
| 694 | + ata_pio_xfer(qc, nth_page(page, 1), 0, | |
| 695 | + qc->sect_size - split_len); | |
| 696 | + } else { | |
| 697 | + ata_pio_xfer(qc, page, offset, qc->sect_size); | |
| 698 | + } | |
| 680 | 699 | |
| 681 | 700 | qc->curbytes += qc->sect_size; |
| 682 | 701 | qc->cursg_ofs += qc->sect_size; |
| @@ -231,6 +231,8 @@ EXPORT_SYMBOL_GPL(auxiliary_find_device); · 230 unmodified lines | ||
| 231 | 231 | int __auxiliary_driver_register(struct auxiliary_driver *auxdrv, |
| 232 | 232 | struct module *owner, const char *modname) |
| 233 | 233 | { |
| 234 | + int ret; | |
| 235 | + | |
| 234 | 236 | if (WARN_ON(!auxdrv->probe) || WARN_ON(!auxdrv->id_table)) |
| 235 | 237 | return -EINVAL; |
| 236 | 238 | |
| @@ -246,7 +248,11 @@ int __auxiliary_driver_register(struct auxiliary_driver *auxdrv, · 9 unmodified lines | ||
| 246 | 248 | auxdrv->driver.bus = &auxiliary_bus_type; |
| 247 | 249 | auxdrv->driver.mod_name = modname; |
| 248 | 250 | |
| 249 | − return driver_register(&auxdrv->driver); | |
| 251 | + ret = driver_register(&auxdrv->driver); | |
| 252 | + if (ret) | |
| 253 | + kfree(auxdrv->driver.name); | |
| 254 | + | |
| 255 | + return ret; | |
| 250 | 256 | } |
| 251 | 257 | EXPORT_SYMBOL_GPL(__auxiliary_driver_register); |
| 252 | 258 | |
| @@ -574,8 +574,10 @@ static void devlink_remove_symlinks(struct device *dev, · 573 unmodified lines | ||
| 574 | 574 | return; |
| 575 | 575 | } |
| 576 | 576 | |
| 577 | − snprintf(buf, len, "supplier:%s:%s", dev_bus_name(sup), dev_name(sup)); | |
| 578 | − sysfs_remove_link(&con->kobj, buf); | |
| 577 | + if (device_is_registered(con)) { | |
| 578 | + snprintf(buf, len, "supplier:%s:%s", dev_bus_name(sup), dev_name(sup)); | |
| 579 | + sysfs_remove_link(&con->kobj, buf); | |
| 580 | + } | |
| 579 | 581 | snprintf(buf, len, "consumer:%s:%s", dev_bus_name(con), dev_name(con)); |
| 580 | 582 | sysfs_remove_link(&sup->kobj, buf); |
| 581 | 583 | kfree(buf); |
| @@ -2835,6 +2837,7 @@ void device_initialize(struct device *dev) · 2253 unmodified lines | ||
| 2835 | 2837 | device_pm_init(dev); |
| 2836 | 2838 | set_dev_node(dev, -1); |
| 2837 | 2839 | #ifdef CONFIG_GENERIC_MSI_IRQ |
| 2840 | + raw_spin_lock_init(&dev->msi_lock); | |
| 2838 | 2841 | INIT_LIST_HEAD(&dev->msi_list); |
| 2839 | 2842 | #endif |
| 2840 | 2843 | INIT_LIST_HEAD(&dev->links.consumers); |
| @@ -653,8 +653,6 @@ dev_groups_failed: · 652 unmodified lines | ||
| 653 | 653 | else if (drv->remove) |
| 654 | 654 | drv->remove(dev); |
| 655 | 655 | probe_failed: |
| 656 | − kfree(dev->dma_range_map); | |
| 657 | − dev->dma_range_map = NULL; | |
| 658 | 656 | if (dev->bus) |
| 659 | 657 | blocking_notifier_call_chain(&dev->bus->p->bus_notifier, |
| 660 | 658 | BUS_NOTIFY_DRIVER_NOT_BOUND, dev); |
| @@ -662,6 +660,8 @@ pinctrl_bind_failed: · 1 unmodified line | ||
| 662 | 660 | device_links_no_driver(dev); |
| 663 | 661 | devres_release_all(dev); |
| 664 | 662 | arch_teardown_dma_ops(dev); |
| 663 | + kfree(dev->dma_range_map); | |
| 664 | + dev->dma_range_map = NULL; | |
| 665 | 665 | driver_sysfs_remove(dev); |
| 666 | 666 | dev->driver = NULL; |
| 667 | 667 | dev_set_drvdata(dev, NULL); |
| @@ -89,12 +89,11 @@ static void __fw_load_abort(struct fw_priv *fw_priv) · 88 unmodified lines | ||
| 89 | 89 | { |
| 90 | 90 | /* |
| 91 | 91 | * There is a small window in which user can write to 'loading' |
| 92 | − * between loading done and disappearance of 'loading' | |
| 92 | + * between loading done/aborted and disappearance of 'loading' | |
| 93 | 93 | */ |
| 94 | − if (fw_sysfs_done(fw_priv)) | |
| 94 | + if (fw_state_is_aborted(fw_priv) || fw_sysfs_done(fw_priv)) | |
| 95 | 95 | return; |
| 96 | 96 | |
| 97 | − list_del_init(&fw_priv->pending_list); | |
| 98 | 97 | fw_state_aborted(fw_priv); |
| 99 | 98 | } |
| 100 | 99 | |
| @@ -280,7 +279,6 @@ static ssize_t firmware_loading_store(struct device *dev, · 179 unmodified lines | ||
| 280 | 279 | * Same logic as fw_load_abort, only the DONE bit |
| 281 | 280 | * is ignored and we set ABORT only on failure. |
| 282 | 281 | */ |
| 283 | − list_del_init(&fw_priv->pending_list); | |
| 284 | 282 | if (rc) { |
| 285 | 283 | fw_state_aborted(fw_priv); |
| 286 | 284 | written = rc; |
| @@ -513,6 +511,11 @@ static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs, long timeout) · 226 unmodified lines | ||
| 513 | 511 | } |
| 514 | 512 | |
| 515 | 513 | mutex_lock(&fw_lock); |
| 514 | + if (fw_state_is_aborted(fw_priv)) { | |
| 515 | + mutex_unlock(&fw_lock); | |
| 516 | + retval = -EINTR; | |
| 517 | + goto out; | |
| 518 | + } | |
| 516 | 519 | list_add(&fw_priv->pending_list, &pending_fw_head); |
| 517 | 520 | mutex_unlock(&fw_lock); |
| 518 | 521 | |
| @@ -535,11 +538,10 @@ static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs, long timeout) · 16 unmodified lines | ||
| 535 | 538 | if (fw_state_is_aborted(fw_priv)) { |
| 536 | 539 | if (retval == -ERESTARTSYS) |
| 537 | 540 | retval = -EINTR; |
| 538 | − else | |
| 539 | − retval = -EAGAIN; | |
| 540 | 541 | } else if (fw_priv->is_paged_buf && !fw_priv->data) |
| 541 | 542 | retval = -ENOMEM; |
| 542 | 543 | |
| 544 | +out: | |
| 543 | 545 | device_del(f_dev); |
| 544 | 546 | err_put_dev: |
| 545 | 547 | put_device(f_dev); |
| @@ -117,8 +117,16 @@ static inline void __fw_state_set(struct fw_priv *fw_priv, · 116 unmodified lines | ||
| 117 | 117 | |
| 118 | 118 | WRITE_ONCE(fw_st->status, status); |
| 119 | 119 | |
| 120 | − if (status == FW_STATUS_DONE || status == FW_STATUS_ABORTED) | |
| 120 | + if (status == FW_STATUS_DONE || status == FW_STATUS_ABORTED) { | |
| 121 | +#ifdef CONFIG_FW_LOADER_USER_HELPER | |
| 122 | + /* | |
| 123 | + * Doing this here ensures that the fw_priv is deleted from | |
| 124 | + * the pending list in all abort/done paths. | |
| 125 | + */ | |
| 126 | + list_del_init(&fw_priv->pending_list); | |
| 127 | +#endif | |
| 121 | 128 | complete_all(&fw_st->completion); |
| 129 | + } | |
| 122 | 130 | } |
| 123 | 131 | |
| 124 | 132 | static inline void fw_state_aborted(struct fw_priv *fw_priv) |
| @@ -783,8 +783,10 @@ static void fw_abort_batch_reqs(struct firmware *fw) · 782 unmodified lines | ||
| 783 | 783 | return; |
| 784 | 784 | |
| 785 | 785 | fw_priv = fw->priv; |
| 786 | + mutex_lock(&fw_lock); | |
| 786 | 787 | if (!fw_state_is_aborted(fw_priv)) |
| 787 | 788 | fw_state_aborted(fw_priv); |
| 789 | + mutex_unlock(&fw_lock); | |
| 788 | 790 | } |
| 789 | 791 | |
| 790 | 792 | /* called from request_firmware() and request_firmware_work_func() */ |
| @@ -88,6 +88,47 @@ · 87 unmodified lines | ||
| 88 | 88 | |
| 89 | 89 | static DEFINE_IDR(loop_index_idr); |
| 90 | 90 | static DEFINE_MUTEX(loop_ctl_mutex); |
| 91 | +static DEFINE_MUTEX(loop_validate_mutex); | |
| 92 | + | |
| 93 | +/** | |
| 94 | + * loop_global_lock_killable() - take locks for safe loop_validate_file() test | |
| 95 | + * | |
| 96 | + * @lo: struct loop_device | |
| 97 | + * @global: true if @lo is about to bind another "struct loop_device", false otherwise | |
| 98 | + * | |
| 99 | + * Returns 0 on success, -EINTR otherwise. | |
| 100 | + * | |
| 101 | + * Since loop_validate_file() traverses on other "struct loop_device" if | |
| 102 | + * is_loop_device() is true, we need a global lock for serializing concurrent | |
| 103 | + * loop_configure()/loop_change_fd()/__loop_clr_fd() calls. | |
| 104 | + */ | |
| 105 | +static int loop_global_lock_killable(struct loop_device *lo, bool global) | |
| 106 | +{ | |
| 107 | + int err; | |
| 108 | + | |
| 109 | + if (global) { | |
| 110 | + err = mutex_lock_killable(&loop_validate_mutex); | |
| 111 | + if (err) | |
| 112 | + return err; | |
| 113 | + } | |
| 114 | + err = mutex_lock_killable(&lo->lo_mutex); | |
| 115 | + if (err && global) | |
| 116 | + mutex_unlock(&loop_validate_mutex); | |
| 117 | + return err; | |
| 118 | +} | |
| 119 | + | |
| 120 | +/** | |
| 121 | + * loop_global_unlock() - release locks taken by loop_global_lock_killable() | |
| 122 | + * | |
| 123 | + * @lo: struct loop_device | |
| 124 | + * @global: true if @lo was about to bind another "struct loop_device", false otherwise | |
| 125 | + */ | |
| 126 | +static void loop_global_unlock(struct loop_device *lo, bool global) | |
| 127 | +{ | |
| 128 | + mutex_unlock(&lo->lo_mutex); | |
| 129 | + if (global) | |
| 130 | + mutex_unlock(&loop_validate_mutex); | |
| 131 | +} | |
| 91 | 132 | |
| 92 | 133 | static int max_part; |
| 93 | 134 | static int part_shift; |
| @@ -672,13 +713,15 @@ static int loop_validate_file(struct file *file, struct block_device *bdev) · 578 unmodified lines | ||
| 672 | 713 | while (is_loop_device(f)) { |
| 673 | 714 | struct loop_device *l; |
| 674 | 715 | |
| 716 | + lockdep_assert_held(&loop_validate_mutex); | |
| 675 | 717 | if (f->f_mapping->host->i_rdev == bdev->bd_dev) |
| 676 | 718 | return -EBADF; |
| 677 | 719 | |
| 678 | 720 | l = I_BDEV(f->f_mapping->host)->bd_disk->private_data; |
| 679 | − if (l->lo_state != Lo_bound) { | |
| 721 | + if (l->lo_state != Lo_bound) | |
| 680 | 722 | return -EINVAL; |
| 681 | − } | |
| 723 | + /* Order wrt setting lo->lo_backing_file in loop_configure(). */ | |
| 724 | + rmb(); | |
| 682 | 725 | f = l->lo_backing_file; |
| 683 | 726 | } |
| 684 | 727 | if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode)) |
| @@ -697,13 +740,18 @@ static int loop_validate_file(struct file *file, struct block_device *bdev) · 12 unmodified lines | ||
| 697 | 740 | static int loop_change_fd(struct loop_device *lo, struct block_device *bdev, |
| 698 | 741 | unsigned int arg) |
| 699 | 742 | { |
| 700 | − struct file *file = NULL, *old_file; | |
| 701 | − int error; | |
| 702 | − bool partscan; | |
| 743 | + struct file *file = fget(arg); | |
| 744 | + struct file *old_file; | |
| 745 | + int error; | |
| 746 | + bool partscan; | |
| 747 | + bool is_loop; | |
| 703 | 748 | |
| 704 | − error = mutex_lock_killable(&lo->lo_mutex); | |
| 749 | + if (!file) | |
| 750 | + return -EBADF; | |
| 751 | + is_loop = is_loop_device(file); | |
| 752 | + error = loop_global_lock_killable(lo, is_loop); | |
| 705 | 753 | if (error) |
| 706 | − return error; | |
| 754 | + goto out_putf; | |
| 707 | 755 | error = -ENXIO; |
| 708 | 756 | if (lo->lo_state != Lo_bound) |
| 709 | 757 | goto out_err; |
| @@ -713,11 +761,6 @@ static int loop_change_fd(struct loop_device *lo, struct block_device *bdev, · 3 unmodified lines | ||
| 713 | 761 | if (!(lo->lo_flags & LO_FLAGS_READ_ONLY)) |
| 714 | 762 | goto out_err; |
| 715 | 763 | |
| 716 | − error = -EBADF; | |
| 717 | − file = fget(arg); | |
| 718 | − if (!file) | |
| 719 | − goto out_err; | |
| 720 | − | |
| 721 | 764 | error = loop_validate_file(file, bdev); |
| 722 | 765 | if (error) |
| 723 | 766 | goto out_err; |
| @@ -740,7 +783,16 @@ static int loop_change_fd(struct loop_device *lo, struct block_device *bdev, · 16 unmodified lines | ||
| 740 | 783 | loop_update_dio(lo); |
| 741 | 784 | blk_mq_unfreeze_queue(lo->lo_queue); |
| 742 | 785 | partscan = lo->lo_flags & LO_FLAGS_PARTSCAN; |
| 743 | − mutex_unlock(&lo->lo_mutex); | |
| 786 | + loop_global_unlock(lo, is_loop); | |
| 787 | + | |
| 788 | + /* | |
| 789 | + * Flush loop_validate_file() before fput(), for l->lo_backing_file | |
| 790 | + * might be pointing at old_file which might be the last reference. | |
| 791 | + */ | |
| 792 | + if (!is_loop) { | |
| 793 | + mutex_lock(&loop_validate_mutex); | |
| 794 | + mutex_unlock(&loop_validate_mutex); | |
| 795 | + } | |
| 744 | 796 | /* |
| 745 | 797 | * We must drop file reference outside of lo_mutex as dropping |
| 746 | 798 | * the file ref can take open_mutex which creates circular locking |
| @@ -752,9 +804,9 @@ static int loop_change_fd(struct loop_device *lo, struct block_device *bdev, · 5 unmodified lines | ||
| 752 | 804 | return 0; |
| 753 | 805 | |
| 754 | 806 | out_err: |
| 755 | − mutex_unlock(&lo->lo_mutex); | |
| 756 | − if (file) | |
| 757 | − fput(file); | |
| 807 | + loop_global_unlock(lo, is_loop); | |
| 808 | +out_putf: | |
| 809 | + fput(file); | |
| 758 | 810 | return error; |
| 759 | 811 | } |
| 760 | 812 | |
| @@ -1136,22 +1188,22 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 375 unmodified lines | ||
| 1136 | 1188 | struct block_device *bdev, |
| 1137 | 1189 | const struct loop_config *config) |
| 1138 | 1190 | { |
| 1139 | − struct file *file; | |
| 1140 | − struct inode *inode; | |
| 1191 | + struct file *file = fget(config->fd); | |
| 1192 | + struct inode *inode; | |
| 1141 | 1193 | struct address_space *mapping; |
| 1142 | − int error; | |
| 1143 | − loff_t size; | |
| 1144 | − bool partscan; | |
| 1145 | − unsigned short bsize; | |
| 1194 | + int error; | |
| 1195 | + loff_t size; | |
| 1196 | + bool partscan; | |
| 1197 | + unsigned short bsize; | |
| 1198 | + bool is_loop; | |
| 1199 | + | |
| 1200 | + if (!file) | |
| 1201 | + return -EBADF; | |
| 1202 | + is_loop = is_loop_device(file); | |
| 1146 | 1203 | |
| 1147 | 1204 | /* This is safe, since we have a reference from open(). */ |
| 1148 | 1205 | __module_get(THIS_MODULE); |
| 1149 | 1206 | |
| 1150 | − error = -EBADF; | |
| 1151 | − file = fget(config->fd); | |
| 1152 | − if (!file) | |
| 1153 | − goto out; | |
| 1154 | − | |
| 1155 | 1207 | /* |
| 1156 | 1208 | * If we don't hold exclusive handle for the device, upgrade to it |
| 1157 | 1209 | * here to avoid changing device under exclusive owner. |
| @@ -1162,7 +1214,7 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 4 unmodified lines | ||
| 1162 | 1214 | goto out_putf; |
| 1163 | 1215 | } |
| 1164 | 1216 | |
| 1165 | − error = mutex_lock_killable(&lo->lo_mutex); | |
| 1217 | + error = loop_global_lock_killable(lo, is_loop); | |
| 1166 | 1218 | if (error) |
| 1167 | 1219 | goto out_bdev; |
| 1168 | 1220 | |
| @@ -1242,6 +1294,9 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 73 unmodified lines | ||
| 1242 | 1294 | size = get_loop_size(lo, file); |
| 1243 | 1295 | loop_set_size(lo, size); |
| 1244 | 1296 | |
| 1297 | + /* Order wrt reading lo_state in loop_validate_file(). */ | |
| 1298 | + wmb(); | |
| 1299 | + | |
| 1245 | 1300 | lo->lo_state = Lo_bound; |
| 1246 | 1301 | if (part_shift) |
| 1247 | 1302 | lo->lo_flags |= LO_FLAGS_PARTSCAN; |
| @@ -1253,7 +1308,7 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 5 unmodified lines | ||
| 1253 | 1308 | * put /dev/loopXX inode. Later in __loop_clr_fd() we bdput(bdev). |
| 1254 | 1309 | */ |
| 1255 | 1310 | bdgrab(bdev); |
| 1256 | − mutex_unlock(&lo->lo_mutex); | |
| 1311 | + loop_global_unlock(lo, is_loop); | |
| 1257 | 1312 | if (partscan) |
| 1258 | 1313 | loop_reread_partitions(lo); |
| 1259 | 1314 | if (!(mode & FMODE_EXCL)) |
| @@ -1261,13 +1316,12 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 1 unmodified line | ||
| 1261 | 1316 | return 0; |
| 1262 | 1317 | |
| 1263 | 1318 | out_unlock: |
| 1264 | − mutex_unlock(&lo->lo_mutex); | |
| 1319 | + loop_global_unlock(lo, is_loop); | |
| 1265 | 1320 | out_bdev: |
| 1266 | 1321 | if (!(mode & FMODE_EXCL)) |
| 1267 | 1322 | bd_abort_claiming(bdev, loop_configure); |
| 1268 | 1323 | out_putf: |
| 1269 | 1324 | fput(file); |
| 1270 | −out: | |
| 1271 | 1325 | /* This is safe: open() is still holding a reference. */ |
| 1272 | 1326 | module_put(THIS_MODULE); |
| 1273 | 1327 | return error; |
| @@ -1283,6 +1337,18 @@ static int __loop_clr_fd(struct loop_device *lo, bool release) · 9 unmodified lines | ||
| 1283 | 1337 | int lo_number; |
| 1284 | 1338 | struct loop_worker *pos, *worker; |
| 1285 | 1339 | |
| 1340 | + /* | |
| 1341 | + * Flush loop_configure() and loop_change_fd(). It is acceptable for | |
| 1342 | + * loop_validate_file() to succeed, for actual clear operation has not | |
| 1343 | + * started yet. | |
| 1344 | + */ | |
| 1345 | + mutex_lock(&loop_validate_mutex); | |
| 1346 | + mutex_unlock(&loop_validate_mutex); | |
| 1347 | + /* | |
| 1348 | + * loop_validate_file() now fails because l->lo_state != Lo_bound | |
| 1349 | + * became visible. | |
| 1350 | + */ | |
| 1351 | + | |
| 1286 | 1352 | mutex_lock(&lo->lo_mutex); |
| 1287 | 1353 | if (WARN_ON_ONCE(lo->lo_state != Lo_rundown)) { |
| 1288 | 1354 | err = -ENXIO; |
| @@ -74,7 +74,7 @@ static bool n64cart_do_bvec(struct device *dev, struct bio_vec *bv, u32 pos) · 73 unmodified lines | ||
| 74 | 74 | |
| 75 | 75 | n64cart_wait_dma(); |
| 76 | 76 | |
| 77 | − n64cart_write_reg(PI_DRAM_REG, dma_addr + bv->bv_offset); | |
| 77 | + n64cart_write_reg(PI_DRAM_REG, dma_addr); | |
| 78 | 78 | n64cart_write_reg(PI_CART_REG, (bstart | CART_DOMAIN) & CART_MAX); |
| 79 | 79 | n64cart_write_reg(PI_WRITE_REG, bv->bv_len - 1); |
| 80 | 80 | |
| @@ -239,8 +239,8 @@ static void nbd_dev_remove(struct nbd_device *nbd) · 238 unmodified lines | ||
| 239 | 239 | |
| 240 | 240 | if (disk) { |
| 241 | 241 | del_gendisk(disk); |
| 242 | − blk_mq_free_tag_set(&nbd->tag_set); | |
| 243 | 242 | blk_cleanup_disk(disk); |
| 243 | + blk_mq_free_tag_set(&nbd->tag_set); | |
| 244 | 244 | } |
| 245 | 245 | |
| 246 | 246 | /* |
| @@ -818,6 +818,10 @@ static bool nbd_clear_req(struct request *req, void *data, bool reserved) · 571 unmodified lines | ||
| 818 | 818 | { |
| 819 | 819 | struct nbd_cmd *cmd = blk_mq_rq_to_pdu(req); |
| 820 | 820 | |
| 821 | + /* don't abort one completed request */ | |
| 822 | + if (blk_mq_request_completed(req)) | |
| 823 | + return true; | |
| 824 | + | |
| 821 | 825 | mutex_lock(&cmd->lock); |
| 822 | 826 | cmd->status = BLK_STS_IOERR; |
| 823 | 827 | mutex_unlock(&cmd->lock); |
| @@ -2004,15 +2008,19 @@ static void nbd_disconnect_and_put(struct nbd_device *nbd) · 1180 unmodified lines | ||
| 2004 | 2008 | { |
| 2005 | 2009 | mutex_lock(&nbd->config_lock); |
| 2006 | 2010 | nbd_disconnect(nbd); |
| 2007 | − nbd_clear_sock(nbd); | |
| 2008 | − mutex_unlock(&nbd->config_lock); | |
| 2011 | + sock_shutdown(nbd); | |
| 2009 | 2012 | /* |
| 2010 | 2013 | * Make sure recv thread has finished, so it does not drop the last |
| 2011 | 2014 | * config ref and try to destroy the workqueue from inside the work |
| 2012 | − * queue. | |
| 2015 | + * queue. And this also ensure that we can safely call nbd_clear_que() | |
| 2016 | + * to cancel the inflight I/Os. | |
| 2013 | 2017 | */ |
| 2014 | 2018 | if (nbd->recv_workq) |
| 2015 | 2019 | flush_workqueue(nbd->recv_workq); |
| 2020 | + nbd_clear_que(nbd); | |
| 2021 | + nbd->task_setup = NULL; | |
| 2022 | + mutex_unlock(&nbd->config_lock); | |
| 2023 | + | |
| 2016 | 2024 | if (test_and_clear_bit(NBD_RT_HAS_CONFIG_REF, |
| 2017 | 2025 | &nbd->config->runtime_flags)) |
| 2018 | 2026 | nbd_config_put(nbd); |
| @@ -1014,8 +1014,8 @@ static void __exit pd_exit(void) · 1013 unmodified lines | ||
| 1014 | 1014 | if (p) { |
| 1015 | 1015 | disk->gd = NULL; |
| 1016 | 1016 | del_gendisk(p); |
| 1017 | − blk_mq_free_tag_set(&disk->tag_set); | |
| 1018 | 1017 | blk_cleanup_disk(p); |
| 1018 | + blk_mq_free_tag_set(&disk->tag_set); | |
| 1019 | 1019 | pi_release(disk->pi); |
| 1020 | 1020 | } |
| 1021 | 1021 | } |
| @@ -4100,8 +4100,6 @@ again: · 4099 unmodified lines | ||
| 4100 | 4100 | |
| 4101 | 4101 | static bool rbd_quiesce_lock(struct rbd_device *rbd_dev) |
| 4102 | 4102 | { |
| 4103 | − bool need_wait; | |
| 4104 | − | |
| 4105 | 4103 | dout("%s rbd_dev %p\n", __func__, rbd_dev); |
| 4106 | 4104 | lockdep_assert_held_write(&rbd_dev->lock_rwsem); |
| 4107 | 4105 | |
| @@ -4113,11 +4111,11 @@ static bool rbd_quiesce_lock(struct rbd_device *rbd_dev) · 5 unmodified lines | ||
| 4113 | 4111 | */ |
| 4114 | 4112 | rbd_dev->lock_state = RBD_LOCK_STATE_RELEASING; |
| 4115 | 4113 | rbd_assert(!completion_done(&rbd_dev->releasing_wait)); |
| 4116 | − need_wait = !list_empty(&rbd_dev->running_list); | |
| 4117 | − downgrade_write(&rbd_dev->lock_rwsem); | |
| 4118 | − if (need_wait) | |
| 4119 | − wait_for_completion(&rbd_dev->releasing_wait); | |
| 4120 | − up_read(&rbd_dev->lock_rwsem); | |
| 4114 | + if (list_empty(&rbd_dev->running_list)) | |
| 4115 | + return true; | |
| 4116 | + | |
| 4117 | + up_write(&rbd_dev->lock_rwsem); | |
| 4118 | + wait_for_completion(&rbd_dev->releasing_wait); | |
| 4121 | 4119 | |
| 4122 | 4120 | down_write(&rbd_dev->lock_rwsem); |
| 4123 | 4121 | if (rbd_dev->lock_state != RBD_LOCK_STATE_RELEASING) |
| @@ -4203,15 +4201,11 @@ static void rbd_handle_acquired_lock(struct rbd_device *rbd_dev, u8 struct_v, · 79 unmodified lines | ||
| 4203 | 4201 | if (!rbd_cid_equal(&cid, &rbd_empty_cid)) { |
| 4204 | 4202 | down_write(&rbd_dev->lock_rwsem); |
| 4205 | 4203 | if (rbd_cid_equal(&cid, &rbd_dev->owner_cid)) { |
| 4206 | − /* | |
| 4207 | − * we already know that the remote client is | |
| 4208 | − * the owner | |
| 4209 | − */ | |
| 4210 | − up_write(&rbd_dev->lock_rwsem); | |
| 4211 | − return; | |
| 4204 | + dout("%s rbd_dev %p cid %llu-%llu == owner_cid\n", | |
| 4205 | + __func__, rbd_dev, cid.gid, cid.handle); | |
| 4206 | + } else { | |
| 4207 | + rbd_set_owner_cid(rbd_dev, &cid); | |
| 4212 | 4208 | } |
| 4213 | − | |
| 4214 | − rbd_set_owner_cid(rbd_dev, &cid); | |
| 4215 | 4209 | downgrade_write(&rbd_dev->lock_rwsem); |
| 4216 | 4210 | } else { |
| 4217 | 4211 | down_read(&rbd_dev->lock_rwsem); |
| @@ -4236,14 +4230,12 @@ static void rbd_handle_released_lock(struct rbd_device *rbd_dev, u8 struct_v, · 18 unmodified lines | ||
| 4236 | 4230 | if (!rbd_cid_equal(&cid, &rbd_empty_cid)) { |
| 4237 | 4231 | down_write(&rbd_dev->lock_rwsem); |
| 4238 | 4232 | if (!rbd_cid_equal(&cid, &rbd_dev->owner_cid)) { |
| 4239 | − dout("%s rbd_dev %p unexpected owner, cid %llu-%llu != owner_cid %llu-%llu\n", | |
| 4233 | + dout("%s rbd_dev %p cid %llu-%llu != owner_cid %llu-%llu\n", | |
| 4240 | 4234 | __func__, rbd_dev, cid.gid, cid.handle, |
| 4241 | 4235 | rbd_dev->owner_cid.gid, rbd_dev->owner_cid.handle); |
| 4242 | − up_write(&rbd_dev->lock_rwsem); | |
| 4243 | − return; | |
| 4236 | + } else { | |
| 4237 | + rbd_set_owner_cid(rbd_dev, &rbd_empty_cid); | |
| 4244 | 4238 | } |
| 4245 | − | |
| 4246 | − rbd_set_owner_cid(rbd_dev, &rbd_empty_cid); | |
| 4247 | 4239 | downgrade_write(&rbd_dev->lock_rwsem); |
| 4248 | 4240 | } else { |
| 4249 | 4241 | down_read(&rbd_dev->lock_rwsem); |
| @@ -4951,6 +4943,7 @@ static int rbd_init_disk(struct rbd_device *rbd_dev) · 701 unmodified lines | ||
| 4951 | 4943 | disk->minors = RBD_MINORS_PER_MAJOR; |
| 4952 | 4944 | } |
| 4953 | 4945 | disk->fops = &rbd_bd_ops; |
| 4946 | + disk->private_data = rbd_dev; | |
| 4954 | 4947 | |
| 4955 | 4948 | blk_queue_flag_set(QUEUE_FLAG_NONROT, q); |
| 4956 | 4949 | /* QUEUE_FLAG_ADD_RANDOM is off by default for blk-mq */ |
| @@ -692,6 +692,28 @@ static const struct blk_mq_ops virtio_mq_ops = { · 691 unmodified lines | ||
| 692 | 692 | static unsigned int virtblk_queue_depth; |
| 693 | 693 | module_param_named(queue_depth, virtblk_queue_depth, uint, 0444); |
| 694 | 694 | |
| 695 | +static int virtblk_validate(struct virtio_device *vdev) | |
| 696 | +{ | |
| 697 | + u32 blk_size; | |
| 698 | + | |
| 699 | + if (!vdev->config->get) { | |
| 700 | + dev_err(&vdev->dev, "%s failure: config access disabled\n", | |
| 701 | + __func__); | |
| 702 | + return -EINVAL; | |
| 703 | + } | |
| 704 | + | |
| 705 | + if (!virtio_has_feature(vdev, VIRTIO_BLK_F_BLK_SIZE)) | |
| 706 | + return 0; | |
| 707 | + | |
| 708 | + blk_size = virtio_cread32(vdev, | |
| 709 | + offsetof(struct virtio_blk_config, blk_size)); | |
| 710 | + | |
| 711 | + if (blk_size < SECTOR_SIZE || blk_size > PAGE_SIZE) | |
| 712 | + __virtio_clear_bit(vdev, VIRTIO_BLK_F_BLK_SIZE); | |
| 713 | + | |
| 714 | + return 0; | |
| 715 | +} | |
| 716 | + | |
| 695 | 717 | static int virtblk_probe(struct virtio_device *vdev) |
| 696 | 718 | { |
| 697 | 719 | struct virtio_blk *vblk; |
| @@ -703,12 +725,6 @@ static int virtblk_probe(struct virtio_device *vdev) · 5 unmodified lines | ||
| 703 | 725 | u8 physical_block_exp, alignment_offset; |
| 704 | 726 | unsigned int queue_depth; |
| 705 | 727 | |
| 706 | − if (!vdev->config->get) { | |
| 707 | − dev_err(&vdev->dev, "%s failure: config access disabled\n", | |
| 708 | − __func__); | |
| 709 | − return -EINVAL; | |
| 710 | − } | |
| 711 | − | |
| 712 | 728 | err = ida_simple_get(&vd_index_ida, 0, minor_to_index(1 << MINORBITS), |
| 713 | 729 | GFP_KERNEL); |
| 714 | 730 | if (err < 0) |
| @@ -823,6 +839,14 @@ static int virtblk_probe(struct virtio_device *vdev) · 108 unmodified lines | ||
| 823 | 839 | else |
| 824 | 840 | blk_size = queue_logical_block_size(q); |
| 825 | 841 | |
| 842 | + if (unlikely(blk_size < SECTOR_SIZE || blk_size > PAGE_SIZE)) { | |
| 843 | + dev_err(&vdev->dev, | |
| 844 | + "block size is changed unexpectedly, now is %u\n", | |
| 845 | + blk_size); | |
| 846 | + err = -EINVAL; | |
| 847 | + goto err_cleanup_disk; | |
| 848 | + } | |
| 849 | + | |
| 826 | 850 | /* Use topology information if available */ |
| 827 | 851 | err = virtio_cread_feature(vdev, VIRTIO_BLK_F_TOPOLOGY, |
| 828 | 852 | struct virtio_blk_config, physical_block_exp, |
| @@ -881,6 +905,8 @@ static int virtblk_probe(struct virtio_device *vdev) · 52 unmodified lines | ||
| 881 | 905 | device_add_disk(&vdev->dev, vblk->disk, virtblk_attr_groups); |
| 882 | 906 | return 0; |
| 883 | 907 | |
| 908 | +err_cleanup_disk: | |
| 909 | + blk_cleanup_disk(vblk->disk); | |
| 884 | 910 | out_free_tags: |
| 885 | 911 | blk_mq_free_tag_set(&vblk->tag_set); |
| 886 | 912 | out_free_vq: |
| @@ -983,6 +1009,7 @@ static struct virtio_driver virtio_blk = { · 96 unmodified lines | ||
| 983 | 1009 | .driver.name = KBUILD_MODNAME, |
| 984 | 1010 | .driver.owner = THIS_MODULE, |
| 985 | 1011 | .id_table = id_table, |
| 1012 | + .validate = virtblk_validate, | |
| 986 | 1013 | .probe = virtblk_probe, |
| 987 | 1014 | .remove = virtblk_remove, |
| 988 | 1015 | .config_changed = virtblk_config_changed, |
| @@ -502,34 +502,21 @@ static int blkif_getgeo(struct block_device *bd, struct hd_geometry *hg) · 501 unmodified lines | ||
| 502 | 502 | static int blkif_ioctl(struct block_device *bdev, fmode_t mode, |
| 503 | 503 | unsigned command, unsigned long argument) |
| 504 | 504 | { |
| 505 | − struct blkfront_info *info = bdev->bd_disk->private_data; | |
| 506 | 505 | int i; |
| 507 | 506 | |
| 508 | − dev_dbg(&info->xbdev->dev, "command: 0x%x, argument: 0x%lx\n", | |
| 509 | − command, (long)argument); | |
| 510 | − | |
| 511 | 507 | switch (command) { |
| 512 | 508 | case CDROMMULTISESSION: |
| 513 | − dev_dbg(&info->xbdev->dev, "FIXME: support multisession CDs later\n"); | |
| 514 | 509 | for (i = 0; i < sizeof(struct cdrom_multisession); i++) |
| 515 | 510 | if (put_user(0, (char __user *)(argument + i))) |
| 516 | 511 | return -EFAULT; |
| 517 | 512 | return 0; |
| 518 | − | |
| 519 | − case CDROM_GET_CAPABILITY: { | |
| 520 | − struct gendisk *gd = info->gd; | |
| 521 | − if (gd->flags & GENHD_FL_CD) | |
| 513 | + case CDROM_GET_CAPABILITY: | |
| 514 | + if (bdev->bd_disk->flags & GENHD_FL_CD) | |
| 522 | 515 | return 0; |
| 523 | 516 | return -EINVAL; |
| 524 | − } | |
| 525 | − | |
| 526 | 517 | default: |
| 527 | − /*printk(KERN_ALERT "ioctl %08x not supported by Xen blkdev\n", | |
| 528 | − command);*/ | |
| 529 | − return -EINVAL; /* same return as native Linux */ | |
| 518 | + return -EINVAL; | |
| 530 | 519 | } |
| 531 | − | |
| 532 | − return 0; | |
| 533 | 520 | } |
| 534 | 521 | |
| 535 | 522 | static unsigned long blkif_ring_get_request(struct blkfront_ring_info *rinfo, |
| @@ -1177,36 +1164,6 @@ out_release_minors: · 641 unmodified lines | ||
| 1177 | 1164 | return err; |
| 1178 | 1165 | } |
| 1179 | 1166 | |
| 1180 | −static void xlvbd_release_gendisk(struct blkfront_info *info) | |
| 1181 | −{ | |
| 1182 | − unsigned int minor, nr_minors, i; | |
| 1183 | − struct blkfront_ring_info *rinfo; | |
| 1184 | − | |
| 1185 | − if (info->rq == NULL) | |
| 1186 | − return; | |
| 1187 | − | |
| 1188 | − /* No more blkif_request(). */ | |
| 1189 | − blk_mq_stop_hw_queues(info->rq); | |
| 1190 | − | |
| 1191 | − for_each_rinfo(info, rinfo, i) { | |
| 1192 | − /* No more gnttab callback work. */ | |
| 1193 | − gnttab_cancel_free_callback(&rinfo->callback); | |
| 1194 | − | |
| 1195 | − /* Flush gnttab callback work. Must be done with no locks held. */ | |
| 1196 | − flush_work(&rinfo->work); | |
| 1197 | − } | |
| 1198 | − | |
| 1199 | − del_gendisk(info->gd); | |
| 1200 | − | |
| 1201 | − minor = info->gd->first_minor; | |
| 1202 | − nr_minors = info->gd->minors; | |
| 1203 | − xlbd_release_minors(minor, nr_minors); | |
| 1204 | − | |
| 1205 | − blk_cleanup_disk(info->gd); | |
| 1206 | − info->gd = NULL; | |
| 1207 | − blk_mq_free_tag_set(&info->tag_set); | |
| 1208 | −} | |
| 1209 | − | |
| 1210 | 1167 | /* Already hold rinfo->ring_lock. */ |
| 1211 | 1168 | static inline void kick_pending_request_queues_locked(struct blkfront_ring_info *rinfo) |
| 1212 | 1169 | { |
| @@ -1756,12 +1713,6 @@ abort_transaction: · 543 unmodified lines | ||
| 1756 | 1713 | return err; |
| 1757 | 1714 | } |
| 1758 | 1715 | |
| 1759 | −static void free_info(struct blkfront_info *info) | |
| 1760 | −{ | |
| 1761 | − list_del(&info->info_list); | |
| 1762 | − kfree(info); | |
| 1763 | −} | |
| 1764 | − | |
| 1765 | 1716 | /* Common code used when first setting up, and when resuming. */ |
| 1766 | 1717 | static int talk_to_blkback(struct xenbus_device *dev, |
| 1767 | 1718 | struct blkfront_info *info) |
| @@ -1880,13 +1831,6 @@ again: · 112 unmodified lines | ||
| 1880 | 1831 | xenbus_dev_fatal(dev, err, "%s", message); |
| 1881 | 1832 | destroy_blkring: |
| 1882 | 1833 | blkif_free(info, 0); |
| 1883 | − | |
| 1884 | − mutex_lock(&blkfront_mutex); | |
| 1885 | − free_info(info); | |
| 1886 | − mutex_unlock(&blkfront_mutex); | |
| 1887 | − | |
| 1888 | − dev_set_drvdata(&dev->dev, NULL); | |
| 1889 | − | |
| 1890 | 1834 | return err; |
| 1891 | 1835 | } |
| 1892 | 1836 | |
| @@ -2126,38 +2070,26 @@ static int blkfront_resume(struct xenbus_device *dev) · 233 unmodified lines | ||
| 2126 | 2070 | static void blkfront_closing(struct blkfront_info *info) |
| 2127 | 2071 | { |
| 2128 | 2072 | struct xenbus_device *xbdev = info->xbdev; |
| 2129 | − struct block_device *bdev = NULL; | |
| 2130 | − | |
| 2131 | − mutex_lock(&info->mutex); | |
| 2073 | + struct blkfront_ring_info *rinfo; | |
| 2074 | + unsigned int i; | |
| 2132 | 2075 | |
| 2133 | − if (xbdev->state == XenbusStateClosing) { | |
| 2134 | − mutex_unlock(&info->mutex); | |
| 2076 | + if (xbdev->state == XenbusStateClosing) | |
| 2135 | 2077 | return; |
| 2136 | − } | |
| 2137 | 2078 | |
| 2138 | − if (info->gd) | |
| 2139 | − bdev = bdgrab(info->gd->part0); | |
| 2140 | − | |
| 2141 | − mutex_unlock(&info->mutex); | |
| 2142 | − | |
| 2143 | − if (!bdev) { | |
| 2144 | − xenbus_frontend_closed(xbdev); | |
| 2145 | − return; | |
| 2146 | − } | |
| 2079 | + /* No more blkif_request(). */ | |
| 2080 | + blk_mq_stop_hw_queues(info->rq); | |
| 2081 | + blk_set_queue_dying(info->rq); | |
| 2082 | + set_capacity(info->gd, 0); | |
| 2147 | 2083 | |
| 2148 | − mutex_lock(&bdev->bd_disk->open_mutex); | |
| 2084 | + for_each_rinfo(info, rinfo, i) { | |
| 2085 | + /* No more gnttab callback work. */ | |
| 2086 | + gnttab_cancel_free_callback(&rinfo->callback); | |
| 2149 | 2087 | |
| 2150 | − if (bdev->bd_openers) { | |
| 2151 | − xenbus_dev_error(xbdev, -EBUSY, | |
| 2152 | − "Device in use; refusing to close"); | |
| 2153 | − xenbus_switch_state(xbdev, XenbusStateClosing); | |
| 2154 | − } else { | |
| 2155 | − xlvbd_release_gendisk(info); | |
| 2156 | − xenbus_frontend_closed(xbdev); | |
| 2088 | + /* Flush gnttab callback work. Must be done with no locks held. */ | |
| 2089 | + flush_work(&rinfo->work); | |
| 2157 | 2090 | } |
| 2158 | 2091 | |
| 2159 | − mutex_unlock(&bdev->bd_disk->open_mutex); | |
| 2160 | − bdput(bdev); | |
| 2092 | + xenbus_frontend_closed(xbdev); | |
| 2161 | 2093 | } |
| 2162 | 2094 | |
| 2163 | 2095 | static void blkfront_setup_discard(struct blkfront_info *info) |
| @@ -2472,8 +2404,7 @@ static void blkback_changed(struct xenbus_device *dev, · 308 unmodified lines | ||
| 2472 | 2404 | break; |
| 2473 | 2405 | fallthrough; |
| 2474 | 2406 | case XenbusStateClosing: |
| 2475 | − if (info) | |
| 2476 | − blkfront_closing(info); | |
| 2407 | + blkfront_closing(info); | |
| 2477 | 2408 | break; |
| 2478 | 2409 | } |
| 2479 | 2410 | } |
| @@ -2481,56 +2412,21 @@ static void blkback_changed(struct xenbus_device *dev, · 1 unmodified line | ||
| 2481 | 2412 | static int blkfront_remove(struct xenbus_device *xbdev) |
| 2482 | 2413 | { |
| 2483 | 2414 | struct blkfront_info *info = dev_get_drvdata(&xbdev->dev); |
| 2484 | − struct block_device *bdev = NULL; | |
| 2485 | − struct gendisk *disk; | |
| 2486 | 2415 | |
| 2487 | 2416 | dev_dbg(&xbdev->dev, "%s removed", xbdev->nodename); |
| 2488 | 2417 | |
| 2489 | − if (!info) | |
| 2490 | − return 0; | |
| 2491 | − | |
| 2492 | − blkif_free(info, 0); | |
| 2493 | − | |
| 2494 | − mutex_lock(&info->mutex); | |
| 2495 | − | |
| 2496 | − disk = info->gd; | |
| 2497 | − if (disk) | |
| 2498 | − bdev = bdgrab(disk->part0); | |
| 2499 | − | |
| 2500 | − info->xbdev = NULL; | |
| 2501 | − mutex_unlock(&info->mutex); | |
| 2502 | − | |
| 2503 | − if (!bdev) { | |
| 2504 | − mutex_lock(&blkfront_mutex); | |
| 2505 | − free_info(info); | |
| 2506 | − mutex_unlock(&blkfront_mutex); | |
| 2507 | − return 0; | |
| 2508 | − } | |
| 2509 | − | |
| 2510 | − /* | |
| 2511 | − * The xbdev was removed before we reached the Closed | |
| 2512 | − * state. See if it's safe to remove the disk. If the bdev | |
| 2513 | − * isn't closed yet, we let release take care of it. | |
| 2514 | − */ | |
| 2515 | − | |
| 2516 | − mutex_lock(&disk->open_mutex); | |
| 2517 | − info = disk->private_data; | |
| 2518 | − | |
| 2519 | − dev_warn(disk_to_dev(disk), | |
| 2520 | − "%s was hot-unplugged, %d stale handles\n", | |
| 2521 | − xbdev->nodename, bdev->bd_openers); | |
| 2418 | + del_gendisk(info->gd); | |
| 2522 | 2419 | |
| 2523 | − if (info && !bdev->bd_openers) { | |
| 2524 | − xlvbd_release_gendisk(info); | |
| 2525 | − disk->private_data = NULL; | |
| 2526 | − mutex_lock(&blkfront_mutex); | |
| 2527 | − free_info(info); | |
| 2528 | − mutex_unlock(&blkfront_mutex); | |
| 2529 | − } | |
| 2420 | + mutex_lock(&blkfront_mutex); | |
| 2421 | + list_del(&info->info_list); | |
| 2422 | + mutex_unlock(&blkfront_mutex); | |
| 2530 | 2423 | |
| 2531 | − mutex_unlock(&disk->open_mutex); | |
| 2532 | − bdput(bdev); | |
| 2424 | + blkif_free(info, 0); | |
| 2425 | + xlbd_release_minors(info->gd->first_minor, info->gd->minors); | |
| 2426 | + blk_cleanup_disk(info->gd); | |
| 2427 | + blk_mq_free_tag_set(&info->tag_set); | |
| 2533 | 2428 | |
| 2429 | + kfree(info); | |
| 2534 | 2430 | return 0; |
| 2535 | 2431 | } |
| 2536 | 2432 | |
| @@ -2541,77 +2437,9 @@ static int blkfront_is_ready(struct xenbus_device *dev) · 4 unmodified lines | ||
| 2541 | 2437 | return info->is_ready && info->xbdev; |
| 2542 | 2438 | } |
| 2543 | 2439 | |
| 2544 | −static int blkif_open(struct block_device *bdev, fmode_t mode) | |
| 2545 | −{ | |
| 2546 | − struct gendisk *disk = bdev->bd_disk; | |
| 2547 | − struct blkfront_info *info; | |
| 2548 | − int err = 0; | |
| 2549 | − | |
| 2550 | − mutex_lock(&blkfront_mutex); | |
| 2551 | − | |
| 2552 | − info = disk->private_data; | |
| 2553 | − if (!info) { | |
| 2554 | − /* xbdev gone */ | |
| 2555 | − err = -ERESTARTSYS; | |
| 2556 | − goto out; | |
| 2557 | − } | |
| 2558 | − | |
| 2559 | − mutex_lock(&info->mutex); | |
| 2560 | − | |
| 2561 | − if (!info->gd) | |
| 2562 | − /* xbdev is closed */ | |
| 2563 | − err = -ERESTARTSYS; | |
| 2564 | − | |
| 2565 | − mutex_unlock(&info->mutex); | |
| 2566 | − | |
| 2567 | −out: | |
| 2568 | − mutex_unlock(&blkfront_mutex); | |
| 2569 | − return err; | |
| 2570 | −} | |
| 2571 | − | |
| 2572 | −static void blkif_release(struct gendisk *disk, fmode_t mode) | |
| 2573 | −{ | |
| 2574 | − struct blkfront_info *info = disk->private_data; | |
| 2575 | − struct xenbus_device *xbdev; | |
| 2576 | − | |
| 2577 | − mutex_lock(&blkfront_mutex); | |
| 2578 | − if (disk->part0->bd_openers) | |
| 2579 | − goto out_mutex; | |
| 2580 | − | |
| 2581 | − /* | |
| 2582 | − * Check if we have been instructed to close. We will have | |
| 2583 | − * deferred this request, because the bdev was still open. | |
| 2584 | − */ | |
| 2585 | − | |
| 2586 | − mutex_lock(&info->mutex); | |
| 2587 | − xbdev = info->xbdev; | |
| 2588 | − | |
| 2589 | − if (xbdev && xbdev->state == XenbusStateClosing) { | |
| 2590 | − /* pending switch to state closed */ | |
| 2591 | − dev_info(disk_to_dev(disk), "releasing disk\n"); | |
| 2592 | − xlvbd_release_gendisk(info); | |
| 2593 | − xenbus_frontend_closed(info->xbdev); | |
| 2594 | − } | |
| 2595 | − | |
| 2596 | − mutex_unlock(&info->mutex); | |
| 2597 | − | |
| 2598 | − if (!xbdev) { | |
| 2599 | − /* sudden device removal */ | |
| 2600 | − dev_info(disk_to_dev(disk), "releasing disk\n"); | |
| 2601 | − xlvbd_release_gendisk(info); | |
| 2602 | − disk->private_data = NULL; | |
| 2603 | − free_info(info); | |
| 2604 | − } | |
| 2605 | − | |
| 2606 | −out_mutex: | |
| 2607 | − mutex_unlock(&blkfront_mutex); | |
| 2608 | −} | |
| 2609 | − | |
| 2610 | 2440 | static const struct block_device_operations xlvbd_block_fops = |
| 2611 | 2441 | { |
| 2612 | 2442 | .owner = THIS_MODULE, |
| 2613 | − .open = blkif_open, | |
| 2614 | − .release = blkif_release, | |
| 2615 | 2443 | .getgeo = blkif_getgeo, |
| 2616 | 2444 | .ioctl = blkif_ioctl, |
| 2617 | 2445 | .compat_ioctl = blkdev_compat_ptr_ioctl, |
| @@ -682,7 +682,7 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, · 681 unmodified lines | ||
| 682 | 682 | struct image_info *img_info); |
| 683 | 683 | void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl); |
| 684 | 684 | int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, |
| 685 | − struct mhi_chan *mhi_chan); | |
| 685 | + struct mhi_chan *mhi_chan, unsigned int flags); | |
| 686 | 686 | int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, |
| 687 | 687 | struct mhi_chan *mhi_chan); |
| 688 | 688 | void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, |
| @@ -773,11 +773,18 @@ static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, · 772 unmodified lines | ||
| 773 | 773 | cmd_pkt = mhi_to_virtual(mhi_ring, ptr); |
| 774 | 774 | |
| 775 | 775 | chan = MHI_TRE_GET_CMD_CHID(cmd_pkt); |
| 776 | − mhi_chan = &mhi_cntrl->mhi_chan[chan]; | |
| 777 | − write_lock_bh(&mhi_chan->lock); | |
| 778 | − mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); | |
| 779 | − complete(&mhi_chan->completion); | |
| 780 | − write_unlock_bh(&mhi_chan->lock); | |
| 776 | + | |
| 777 | + if (chan < mhi_cntrl->max_chan && | |
| 778 | + mhi_cntrl->mhi_chan[chan].configured) { | |
| 779 | + mhi_chan = &mhi_cntrl->mhi_chan[chan]; | |
| 780 | + write_lock_bh(&mhi_chan->lock); | |
| 781 | + mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); | |
| 782 | + complete(&mhi_chan->completion); | |
| 783 | + write_unlock_bh(&mhi_chan->lock); | |
| 784 | + } else { | |
| 785 | + dev_err(&mhi_cntrl->mhi_dev->dev, | |
| 786 | + "Completion packet for invalid channel ID: %d\n", chan); | |
| 787 | + } | |
| 781 | 788 | |
| 782 | 789 | mhi_del_ring_element(mhi_cntrl, mhi_ring); |
| 783 | 790 | } |
| @@ -1423,7 +1430,7 @@ exit_unprepare_channel: · 639 unmodified lines | ||
| 1423 | 1430 | } |
| 1424 | 1431 | |
| 1425 | 1432 | int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, |
| 1426 | − struct mhi_chan *mhi_chan) | |
| 1433 | + struct mhi_chan *mhi_chan, unsigned int flags) | |
| 1427 | 1434 | { |
| 1428 | 1435 | int ret = 0; |
| 1429 | 1436 | struct device *dev = &mhi_chan->mhi_dev->dev; |
| @@ -1448,6 +1455,9 @@ int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, · 18 unmodified lines | ||
| 1448 | 1455 | if (ret) |
| 1449 | 1456 | goto error_pm_state; |
| 1450 | 1457 | |
| 1458 | + if (mhi_chan->dir == DMA_FROM_DEVICE) | |
| 1459 | + mhi_chan->pre_alloc = !!(flags & MHI_CH_INBOUND_ALLOC_BUFS); | |
| 1460 | + | |
| 1451 | 1461 | /* Pre-allocate buffer for xfer ring */ |
| 1452 | 1462 | if (mhi_chan->pre_alloc) { |
| 1453 | 1463 | int nr_el = get_nr_avail_ring_elements(mhi_cntrl, |
| @@ -1603,7 +1613,7 @@ void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan) · 149 unmodified lines | ||
| 1603 | 1613 | } |
| 1604 | 1614 | |
| 1605 | 1615 | /* Move channel to start state */ |
| 1606 | −int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) | |
| 1616 | +int mhi_prepare_for_transfer(struct mhi_device *mhi_dev, unsigned int flags) | |
| 1607 | 1617 | { |
| 1608 | 1618 | int ret, dir; |
| 1609 | 1619 | struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; |
| @@ -1614,7 +1624,7 @@ int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) · 4 unmodified lines | ||
| 1614 | 1624 | if (!mhi_chan) |
| 1615 | 1625 | continue; |
| 1616 | 1626 | |
| 1617 | − ret = mhi_prepare_channel(mhi_cntrl, mhi_chan); | |
| 1627 | + ret = mhi_prepare_channel(mhi_cntrl, mhi_chan, flags); | |
| 1618 | 1628 | if (ret) |
| 1619 | 1629 | goto error_open_chan; |
| 1620 | 1630 | } |
| @@ -32,6 +32,8 @@ · 31 unmodified lines | ||
| 32 | 32 | * @edl: emergency download mode firmware path (if any) |
| 33 | 33 | * @bar_num: PCI base address register to use for MHI MMIO register space |
| 34 | 34 | * @dma_data_width: DMA transfer word size (32 or 64 bits) |
| 35 | + * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead | |
| 36 | + * of inband wake support (such as sdx24) | |
| 35 | 37 | */ |
| 36 | 38 | struct mhi_pci_dev_info { |
| 37 | 39 | const struct mhi_controller_config *config; |
| @@ -40,6 +42,7 @@ struct mhi_pci_dev_info { · 2 unmodified lines | ||
| 40 | 42 | const char *edl; |
| 41 | 43 | unsigned int bar_num; |
| 42 | 44 | unsigned int dma_data_width; |
| 45 | + bool sideband_wake; | |
| 43 | 46 | }; |
| 44 | 47 | |
| 45 | 48 | #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ |
| @@ -72,6 +75,22 @@ struct mhi_pci_dev_info { · 26 unmodified lines | ||
| 72 | 75 | .doorbell_mode_switch = false, \ |
| 73 | 76 | } |
| 74 | 77 | |
| 78 | +#define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ | |
| 79 | + { \ | |
| 80 | + .num = ch_num, \ | |
| 81 | + .name = ch_name, \ | |
| 82 | + .num_elements = el_count, \ | |
| 83 | + .event_ring = ev_ring, \ | |
| 84 | + .dir = DMA_FROM_DEVICE, \ | |
| 85 | + .ee_mask = BIT(MHI_EE_AMSS), \ | |
| 86 | + .pollcfg = 0, \ | |
| 87 | + .doorbell = MHI_DB_BRST_DISABLE, \ | |
| 88 | + .lpm_notify = false, \ | |
| 89 | + .offload_channel = false, \ | |
| 90 | + .doorbell_mode_switch = false, \ | |
| 91 | + .auto_queue = true, \ | |
| 92 | + } | |
| 93 | + | |
| 75 | 94 | #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ |
| 76 | 95 | { \ |
| 77 | 96 | .num_elements = el_count, \ |
| @@ -210,7 +229,7 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { · 132 unmodified lines | ||
| 210 | 229 | MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), |
| 211 | 230 | MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), |
| 212 | 231 | MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), |
| 213 | − MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), | |
| 232 | + MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), | |
| 214 | 233 | MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), |
| 215 | 234 | MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), |
| 216 | 235 | MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), |
| @@ -242,7 +261,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { · 25 unmodified lines | ||
| 242 | 261 | .edl = "qcom/sdx65m/edl.mbn", |
| 243 | 262 | .config = &modem_qcom_v1_mhiv_config, |
| 244 | 263 | .bar_num = MHI_PCI_DEFAULT_BAR_NUM, |
| 245 | − .dma_data_width = 32 | |
| 264 | + .dma_data_width = 32, | |
| 265 | + .sideband_wake = false, | |
| 246 | 266 | }; |
| 247 | 267 | |
| 248 | 268 | static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { |
| @@ -251,7 +271,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { · 2 unmodified lines | ||
| 251 | 271 | .edl = "qcom/sdx55m/edl.mbn", |
| 252 | 272 | .config = &modem_qcom_v1_mhiv_config, |
| 253 | 273 | .bar_num = MHI_PCI_DEFAULT_BAR_NUM, |
| 254 | − .dma_data_width = 32 | |
| 274 | + .dma_data_width = 32, | |
| 275 | + .sideband_wake = false, | |
| 255 | 276 | }; |
| 256 | 277 | |
| 257 | 278 | static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { |
| @@ -259,7 +280,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { · 1 unmodified line | ||
| 259 | 280 | .edl = "qcom/prog_firehose_sdx24.mbn", |
| 260 | 281 | .config = &modem_qcom_v1_mhiv_config, |
| 261 | 282 | .bar_num = MHI_PCI_DEFAULT_BAR_NUM, |
| 262 | − .dma_data_width = 32 | |
| 283 | + .dma_data_width = 32, | |
| 284 | + .sideband_wake = true, | |
| 263 | 285 | }; |
| 264 | 286 | |
| 265 | 287 | static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { |
| @@ -301,7 +323,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { · 35 unmodified lines | ||
| 301 | 323 | .edl = "qcom/prog_firehose_sdx24.mbn", |
| 302 | 324 | .config = &modem_quectel_em1xx_config, |
| 303 | 325 | .bar_num = MHI_PCI_DEFAULT_BAR_NUM, |
| 304 | − .dma_data_width = 32 | |
| 326 | + .dma_data_width = 32, | |
| 327 | + .sideband_wake = true, | |
| 305 | 328 | }; |
| 306 | 329 | |
| 307 | 330 | static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { |
| @@ -339,7 +362,8 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { · 31 unmodified lines | ||
| 339 | 362 | .edl = "qcom/sdx55m/edl.mbn", |
| 340 | 363 | .config = &modem_foxconn_sdx55_config, |
| 341 | 364 | .bar_num = MHI_PCI_DEFAULT_BAR_NUM, |
| 342 | − .dma_data_width = 32 | |
| 365 | + .dma_data_width = 32, | |
| 366 | + .sideband_wake = false, | |
| 343 | 367 | }; |
| 344 | 368 | |
| 345 | 369 | static const struct pci_device_id mhi_pci_id_table[] = { |
| @@ -640,9 +664,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 294 unmodified lines | ||
| 640 | 664 | mhi_cntrl->status_cb = mhi_pci_status_cb; |
| 641 | 665 | mhi_cntrl->runtime_get = mhi_pci_runtime_get; |
| 642 | 666 | mhi_cntrl->runtime_put = mhi_pci_runtime_put; |
| 643 | − mhi_cntrl->wake_get = mhi_pci_wake_get_nop; | |
| 644 | − mhi_cntrl->wake_put = mhi_pci_wake_put_nop; | |
| 645 | − mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; | |
| 667 | + | |
| 668 | + if (info->sideband_wake) { | |
| 669 | + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; | |
| 670 | + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; | |
| 671 | + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; | |
| 672 | + } | |
| 646 | 673 | |
| 647 | 674 | err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); |
| 648 | 675 | if (err) |
| @@ -100,6 +100,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { · 99 unmodified lines | ||
| 100 | 100 | * @cookie: data used by legacy platform callbacks |
| 101 | 101 | * @name: name if available |
| 102 | 102 | * @revision: interconnect target module revision |
| 103 | + * @reserved: target module is reserved and already in use | |
| 103 | 104 | * @enabled: sysc runtime enabled status |
| 104 | 105 | * @needs_resume: runtime resume needed on resume from suspend |
| 105 | 106 | * @child_needs_resume: runtime resume needed for child on resume from suspend |
| @@ -130,6 +131,7 @@ struct sysc { · 24 unmodified lines | ||
| 130 | 131 | struct ti_sysc_cookie cookie; |
| 131 | 132 | const char *name; |
| 132 | 133 | u32 revision; |
| 134 | + unsigned int reserved:1; | |
| 133 | 135 | unsigned int enabled:1; |
| 134 | 136 | unsigned int needs_resume:1; |
| 135 | 137 | unsigned int child_needs_resume:1; |
| @@ -2951,6 +2953,8 @@ static int sysc_init_soc(struct sysc *ddata) · 2815 unmodified lines | ||
| 2951 | 2953 | case SOC_3430 ... SOC_3630: |
| 2952 | 2954 | sysc_add_disabled(0x48304000); /* timer12 */ |
| 2953 | 2955 | break; |
| 2956 | + case SOC_AM3: | |
| 2957 | + sysc_add_disabled(0x48310000); /* rng */ | |
| 2954 | 2958 | default: |
| 2955 | 2959 | break; |
| 2956 | 2960 | } |
| @@ -3093,7 +3097,9 @@ static int sysc_probe(struct platform_device *pdev) · 136 unmodified lines | ||
| 3093 | 3097 | return error; |
| 3094 | 3098 | |
| 3095 | 3099 | error = sysc_check_active_timer(ddata); |
| 3096 | − if (error) | |
| 3100 | + if (error == -ENXIO) | |
| 3101 | + ddata->reserved = true; | |
| 3102 | + else if (error) | |
| 3097 | 3103 | return error; |
| 3098 | 3104 | |
| 3099 | 3105 | error = sysc_get_clocks(ddata); |
| @@ -3130,11 +3136,15 @@ static int sysc_probe(struct platform_device *pdev) · 30 unmodified lines | ||
| 3130 | 3136 | sysc_show_registers(ddata); |
| 3131 | 3137 | |
| 3132 | 3138 | ddata->dev->type = &sysc_device_type; |
| 3133 | − error = of_platform_populate(ddata->dev->of_node, sysc_match_table, | |
| 3134 | − pdata ? pdata->auxdata : NULL, | |
| 3135 | − ddata->dev); | |
| 3136 | − if (error) | |
| 3137 | − goto err; | |
| 3139 | + | |
| 3140 | + if (!ddata->reserved) { | |
| 3141 | + error = of_platform_populate(ddata->dev->of_node, | |
| 3142 | + sysc_match_table, | |
| 3143 | + pdata ? pdata->auxdata : NULL, | |
| 3144 | + ddata->dev); | |
| 3145 | + if (error) | |
| 3146 | + goto err; | |
| 3147 | + } | |
| 3138 | 3148 | |
| 3139 | 3149 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
| 3140 | 3150 | |
| @@ -75,6 +75,7 @@ static int __op_panel_update_display(void) · 74 unmodified lines | ||
| 75 | 75 | rc); |
| 76 | 76 | break; |
| 77 | 77 | } |
| 78 | + break; | |
| 78 | 79 | case OPAL_SUCCESS: |
| 79 | 80 | break; |
| 80 | 81 | default: |
| @@ -254,11 +254,11 @@ static int ftpm_tee_probe(struct device *dev) · 253 unmodified lines | ||
| 254 | 254 | pvt_data->session = sess_arg.session; |
| 255 | 255 | |
| 256 | 256 | /* Allocate dynamic shared memory with fTPM TA */ |
| 257 | − pvt_data->shm = tee_shm_alloc(pvt_data->ctx, | |
| 258 | − MAX_COMMAND_SIZE + MAX_RESPONSE_SIZE, | |
| 259 | − TEE_SHM_MAPPED | TEE_SHM_DMA_BUF); | |
| 257 | + pvt_data->shm = tee_shm_alloc_kernel_buf(pvt_data->ctx, | |
| 258 | + MAX_COMMAND_SIZE + | |
| 259 | + MAX_RESPONSE_SIZE); | |
| 260 | 260 | if (IS_ERR(pvt_data->shm)) { |
| 261 | − dev_err(dev, "%s: tee_shm_alloc failed\n", __func__); | |
| 261 | + dev_err(dev, "%s: tee_shm_alloc_kernel_buf failed\n", __func__); | |
| 262 | 262 | rc = -ENOMEM; |
| 263 | 263 | goto out_shm_alloc; |
| 264 | 264 | } |
| @@ -92,13 +92,20 @@ int __must_check devm_clk_bulk_get_optional(struct device *dev, int num_clks, · 91 unmodified lines | ||
| 92 | 92 | } |
| 93 | 93 | EXPORT_SYMBOL_GPL(devm_clk_bulk_get_optional); |
| 94 | 94 | |
| 95 | +static void devm_clk_bulk_release_all(struct device *dev, void *res) | |
| 96 | +{ | |
| 97 | + struct clk_bulk_devres *devres = res; | |
| 98 | + | |
| 99 | + clk_bulk_put_all(devres->num_clks, devres->clks); | |
| 100 | +} | |
| 101 | + | |
| 95 | 102 | int __must_check devm_clk_bulk_get_all(struct device *dev, |
| 96 | 103 | struct clk_bulk_data **clks) |
| 97 | 104 | { |
| 98 | 105 | struct clk_bulk_devres *devres; |
| 99 | 106 | int ret; |
| 100 | 107 | |
| 101 | − devres = devres_alloc(devm_clk_bulk_release, | |
| 108 | + devres = devres_alloc(devm_clk_bulk_release_all, | |
| 102 | 109 | sizeof(*devres), GFP_KERNEL); |
| 103 | 110 | if (!devres) |
| 104 | 111 | return -ENOMEM; |
| @@ -526,7 +526,7 @@ struct stm32f4_pll { · 525 unmodified lines | ||
| 526 | 526 | |
| 527 | 527 | struct stm32f4_pll_post_div_data { |
| 528 | 528 | int idx; |
| 529 | − u8 pll_num; | |
| 529 | + int pll_idx; | |
| 530 | 530 | const char *name; |
| 531 | 531 | const char *parent; |
| 532 | 532 | u8 flag; |
| @@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = { · 24 unmodified lines | ||
| 557 | 557 | |
| 558 | 558 | #define MAX_POST_DIV 3 |
| 559 | 559 | static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { |
| 560 | − { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q", | |
| 560 | + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", | |
| 561 | 561 | CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, |
| 562 | 562 | |
| 563 | − { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q", | |
| 563 | + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", | |
| 564 | 564 | CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, |
| 565 | 565 | |
| 566 | − { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, | |
| 566 | + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, | |
| 567 | 567 | STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, |
| 568 | 568 | }; |
| 569 | 569 | |
| @@ -1774,7 +1774,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) · 1204 unmodified lines | ||
| 1774 | 1774 | post_div->width, |
| 1775 | 1775 | post_div->flag_div, |
| 1776 | 1776 | post_div->div_table, |
| 1777 | − clks[post_div->pll_num], | |
| 1777 | + clks[post_div->pll_idx], | |
| 1778 | 1778 | &stm32f4_clk_lock); |
| 1779 | 1779 | |
| 1780 | 1780 | if (post_div->idx != NO_IDX) |
| @@ -18,6 +18,7 @@ config COMMON_CLK_HI3519 · 17 unmodified lines | ||
| 18 | 18 | config COMMON_CLK_HI3559A |
| 19 | 19 | bool "Hi3559A Clock Driver" |
| 20 | 20 | depends on ARCH_HISI || COMPILE_TEST |
| 21 | + select RESET_HISI | |
| 21 | 22 | default ARCH_HISI |
| 22 | 23 | help |
| 23 | 24 | Build the clock driver for hi3559a. |
| @@ -974,6 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) · 973 unmodified lines | ||
| 974 | 974 | hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); |
| 975 | 975 | } |
| 976 | 976 | |
| 977 | − imx_register_uart_clocks(1); | |
| 977 | + imx_register_uart_clocks(2); | |
| 978 | 978 | } |
| 979 | 979 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); |
| @@ -467,7 +467,7 @@ DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, · 466 unmodified lines | ||
| 467 | 467 | |
| 468 | 468 | static struct clk_smd_rpm *msm8936_clks[] = { |
| 469 | 469 | [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, |
| 470 | − [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_clk, | |
| 470 | + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, | |
| 471 | 471 | [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, |
| 472 | 472 | [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, |
| 473 | 473 | [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, |
| @@ -357,27 +357,43 @@ static int gdsc_init(struct gdsc *sc) · 356 unmodified lines | ||
| 357 | 357 | if (on < 0) |
| 358 | 358 | return on; |
| 359 | 359 | |
| 360 | − /* | |
| 361 | − * Votable GDSCs can be ON due to Vote from other masters. | |
| 362 | − * If a Votable GDSC is ON, make sure we have a Vote. | |
| 363 | − */ | |
| 364 | − if ((sc->flags & VOTABLE) && on) | |
| 365 | − gdsc_enable(&sc->pd); | |
| 360 | + if (on) { | |
| 361 | + /* The regulator must be on, sync the kernel state */ | |
| 362 | + if (sc->rsupply) { | |
| 363 | + ret = regulator_enable(sc->rsupply); | |
| 364 | + if (ret < 0) | |
| 365 | + return ret; | |
| 366 | + } | |
| 366 | 367 | |
| 367 | − /* | |
| 368 | − * Make sure the retain bit is set if the GDSC is already on, otherwise | |
| 369 | − * we end up turning off the GDSC and destroying all the register | |
| 370 | − * contents that we thought we were saving. | |
| 371 | − */ | |
| 372 | − if ((sc->flags & RETAIN_FF_ENABLE) && on) | |
| 373 | − gdsc_retain_ff_on(sc); | |
| 368 | + /* | |
| 369 | + * Votable GDSCs can be ON due to Vote from other masters. | |
| 370 | + * If a Votable GDSC is ON, make sure we have a Vote. | |
| 371 | + */ | |
| 372 | + if (sc->flags & VOTABLE) { | |
| 373 | + ret = regmap_update_bits(sc->regmap, sc->gdscr, | |
| 374 | + SW_COLLAPSE_MASK, val); | |
| 375 | + if (ret) | |
| 376 | + return ret; | |
| 377 | + } | |
| 378 | + | |
| 379 | + /* Turn on HW trigger mode if supported */ | |
| 380 | + if (sc->flags & HW_CTRL) { | |
| 381 | + ret = gdsc_hwctrl(sc, true); | |
| 382 | + if (ret < 0) | |
| 383 | + return ret; | |
| 384 | + } | |
| 374 | 385 | |
| 375 | − /* If ALWAYS_ON GDSCs are not ON, turn them ON */ | |
| 376 | − if (sc->flags & ALWAYS_ON) { | |
| 377 | − if (!on) | |
| 378 | − gdsc_enable(&sc->pd); | |
| 386 | + /* | |
| 387 | + * Make sure the retain bit is set if the GDSC is already on, | |
| 388 | + * otherwise we end up turning off the GDSC and destroying all | |
| 389 | + * the register contents that we thought we were saving. | |
| 390 | + */ | |
| 391 | + if (sc->flags & RETAIN_FF_ENABLE) | |
| 392 | + gdsc_retain_ff_on(sc); | |
| 393 | + } else if (sc->flags & ALWAYS_ON) { | |
| 394 | + /* If ALWAYS_ON GDSCs are not ON, turn them ON */ | |
| 395 | + gdsc_enable(&sc->pd); | |
| 379 | 396 | on = true; |
| 380 | − sc->pd.flags |= GENPD_FLAG_ALWAYS_ON; | |
| 381 | 397 | } |
| 382 | 398 | |
| 383 | 399 | if (on || (sc->pwrsts & PWRSTS_RET)) |
| @@ -385,6 +401,8 @@ static int gdsc_init(struct gdsc *sc) · 1 unmodified line | ||
| 385 | 401 | else |
| 386 | 402 | gdsc_clear_mem_on(sc); |
| 387 | 403 | |
| 404 | + if (sc->flags & ALWAYS_ON) | |
| 405 | + sc->pd.flags |= GENPD_FLAG_ALWAYS_ON; | |
| 388 | 406 | if (!sc->pd.power_off) |
| 389 | 407 | sc->pd.power_off = gdsc_disable; |
| 390 | 408 | if (!sc->pd.power_on) |
| @@ -30,8 +30,9 @@ enum clk_ids { · 29 unmodified lines | ||
| 30 | 30 | CLK_PLL2_DIV20, |
| 31 | 31 | CLK_PLL3, |
| 32 | 32 | CLK_PLL3_DIV2, |
| 33 | + CLK_PLL3_DIV2_4, | |
| 34 | + CLK_PLL3_DIV2_4_2, | |
| 33 | 35 | CLK_PLL3_DIV4, |
| 34 | − CLK_PLL3_DIV8, | |
| 35 | 36 | CLK_PLL4, |
| 36 | 37 | CLK_PLL5, |
| 37 | 38 | CLK_PLL5_DIV2, |
| @@ -42,12 +43,13 @@ enum clk_ids { · 4 unmodified lines | ||
| 42 | 43 | }; |
| 43 | 44 | |
| 44 | 45 | /* Divider tables */ |
| 45 | −static const struct clk_div_table dtable_3b[] = { | |
| 46 | +static const struct clk_div_table dtable_1_32[] = { | |
| 46 | 47 | {0, 1}, |
| 47 | 48 | {1, 2}, |
| 48 | 49 | {2, 4}, |
| 49 | 50 | {3, 8}, |
| 50 | 51 | {4, 32}, |
| 52 | + {0, 0}, | |
| 51 | 53 | }; |
| 52 | 54 | |
| 53 | 55 | static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { |
| @@ -66,47 +68,56 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { · 12 unmodified lines | ||
| 66 | 68 | DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), |
| 67 | 69 | |
| 68 | 70 | DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), |
| 71 | + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), | |
| 72 | + DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), | |
| 69 | 73 | DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), |
| 70 | − DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8), | |
| 71 | 74 | |
| 72 | 75 | /* Core output clk */ |
| 73 | 76 | DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), |
| 74 | 77 | DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, |
| 75 | − dtable_3b, CLK_DIVIDER_HIWORD_MASK), | |
| 78 | + dtable_1_32, CLK_DIVIDER_HIWORD_MASK), | |
| 76 | 79 | DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), |
| 77 | − DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, | |
| 78 | − DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), | |
| 80 | + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, | |
| 81 | + DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), | |
| 82 | + DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, | |
| 83 | + DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), | |
| 79 | 84 | }; |
| 80 | 85 | |
| 81 | 86 | static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { |
| 82 | − DEF_MOD("gic", R9A07G044_CLK_GIC600, | |
| 83 | − R9A07G044_CLK_P1, | |
| 84 | − 0x514, BIT(0), (BIT(0) | BIT(1))), | |
| 85 | − DEF_MOD("ia55", R9A07G044_CLK_IA55, | |
| 86 | − R9A07G044_CLK_P1, | |
| 87 | − 0x518, (BIT(0) | BIT(1)), BIT(0)), | |
| 88 | − DEF_MOD("scif0", R9A07G044_CLK_SCIF0, | |
| 89 | − R9A07G044_CLK_P0, | |
| 90 | − 0x584, BIT(0), BIT(0)), | |
| 91 | − DEF_MOD("scif1", R9A07G044_CLK_SCIF1, | |
| 92 | − R9A07G044_CLK_P0, | |
| 93 | − 0x584, BIT(1), BIT(1)), | |
| 94 | − DEF_MOD("scif2", R9A07G044_CLK_SCIF2, | |
| 95 | − R9A07G044_CLK_P0, | |
| 96 | − 0x584, BIT(2), BIT(2)), | |
| 97 | − DEF_MOD("scif3", R9A07G044_CLK_SCIF3, | |
| 98 | − R9A07G044_CLK_P0, | |
| 99 | − 0x584, BIT(3), BIT(3)), | |
| 100 | − DEF_MOD("scif4", R9A07G044_CLK_SCIF4, | |
| 101 | − R9A07G044_CLK_P0, | |
| 102 | − 0x584, BIT(4), BIT(4)), | |
| 103 | − DEF_MOD("sci0", R9A07G044_CLK_SCI0, | |
| 104 | − R9A07G044_CLK_P0, | |
| 105 | − 0x588, BIT(0), BIT(0)), | |
| 87 | + DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, | |
| 88 | + 0x514, 0), | |
| 89 | + DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, | |
| 90 | + 0x518, 0), | |
| 91 | + DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, | |
| 92 | + 0x518, 1), | |
| 93 | + DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, | |
| 94 | + 0x584, 0), | |
| 95 | + DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, | |
| 96 | + 0x584, 1), | |
| 97 | + DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, | |
| 98 | + 0x584, 2), | |
| 99 | + DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, | |
| 100 | + 0x584, 3), | |
| 101 | + DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, | |
| 102 | + 0x584, 4), | |
| 103 | + DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, | |
| 104 | + 0x588, 0), | |
| 105 | +}; | |
| 106 | + | |
| 107 | +static struct rzg2l_reset r9a07g044_resets[] = { | |
| 108 | + DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), | |
| 109 | + DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), | |
| 110 | + DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), | |
| 111 | + DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), | |
| 112 | + DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), | |
| 113 | + DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), | |
| 114 | + DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), | |
| 115 | + DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), | |
| 116 | + DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), | |
| 106 | 117 | }; |
| 107 | 118 | |
| 108 | 119 | static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { |
| 109 | − MOD_CLK_BASE + R9A07G044_CLK_GIC600, | |
| 120 | + MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, | |
| 110 | 121 | }; |
| 111 | 122 | |
| 112 | 123 | const struct rzg2l_cpg_info r9a07g044_cpg_info = { |
| @@ -123,5 +134,9 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { · 10 unmodified lines | ||
| 123 | 134 | /* Module Clocks */ |
| 124 | 135 | .mod_clks = r9a07g044_mod_clks, |
| 125 | 136 | .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), |
| 126 | − .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1, | |
| 137 | + .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, | |
| 138 | + | |
| 139 | + /* Resets */ | |
| 140 | + .resets = r9a07g044_resets, | |
| 141 | + .num_resets = ARRAY_SIZE(r9a07g044_resets), | |
| 127 | 142 | }; |
| @@ -47,9 +47,9 @@ · 46 unmodified lines | ||
| 47 | 47 | #define SDIV(val) DIV_RSMASK(val, 0, 0x7) |
| 48 | 48 | |
| 49 | 49 | #define CLK_ON_R(reg) (reg) |
| 50 | −#define CLK_MON_R(reg) (0x680 - 0x500 + (reg)) | |
| 51 | −#define CLK_RST_R(reg) (0x800 - 0x500 + (reg)) | |
| 52 | −#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg)) | |
| 50 | +#define CLK_MON_R(reg) (0x180 + (reg)) | |
| 51 | +#define CLK_RST_R(reg) (reg) | |
| 52 | +#define CLK_MRST_R(reg) (0x180 + (reg)) | |
| 53 | 53 | |
| 54 | 54 | #define GET_REG_OFFSET(val) ((val >> 20) & 0xfff) |
| 55 | 55 | #define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff) |
| @@ -78,6 +78,7 @@ struct rzg2l_cpg_priv { · 22 unmodified lines | ||
| 78 | 78 | struct clk **clks; |
| 79 | 79 | unsigned int num_core_clks; |
| 80 | 80 | unsigned int num_mod_clks; |
| 81 | + unsigned int num_resets; | |
| 81 | 82 | unsigned int last_dt_core_clk; |
| 82 | 83 | |
| 83 | 84 | struct raw_notifier_head notifiers; |
| @@ -315,15 +316,13 @@ fail: · 231 unmodified lines | ||
| 315 | 316 | * |
| 316 | 317 | * @hw: handle between common and hardware-specific interfaces |
| 317 | 318 | * @off: register offset |
| 318 | − * @onoff: ON/MON bits | |
| 319 | − * @reset: reset bits | |
| 319 | + * @bit: ON/MON bit | |
| 320 | 320 | * @priv: CPG/MSTP private data |
| 321 | 321 | */ |
| 322 | 322 | struct mstp_clock { |
| 323 | 323 | struct clk_hw hw; |
| 324 | 324 | u16 off; |
| 325 | − u8 onoff; | |
| 326 | − u8 reset; | |
| 325 | + u8 bit; | |
| 327 | 326 | struct rzg2l_cpg_priv *priv; |
| 328 | 327 | }; |
| 329 | 328 | |
| @@ -337,6 +336,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) · 7 unmodified lines | ||
| 337 | 336 | struct device *dev = priv->dev; |
| 338 | 337 | unsigned long flags; |
| 339 | 338 | unsigned int i; |
| 339 | + u32 bitmask = BIT(clock->bit); | |
| 340 | 340 | u32 value; |
| 341 | 341 | |
| 342 | 342 | if (!clock->off) { |
| @@ -349,9 +349,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) · 6 unmodified lines | ||
| 349 | 349 | spin_lock_irqsave(&priv->rmw_lock, flags); |
| 350 | 350 | |
| 351 | 351 | if (enable) |
| 352 | − value = (clock->onoff << 16) | clock->onoff; | |
| 352 | + value = (bitmask << 16) | bitmask; | |
| 353 | 353 | else |
| 354 | − value = clock->onoff << 16; | |
| 354 | + value = bitmask << 16; | |
| 355 | 355 | writel(value, priv->base + CLK_ON_R(reg)); |
| 356 | 356 | |
| 357 | 357 | spin_unlock_irqrestore(&priv->rmw_lock, flags); |
| @@ -360,7 +360,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) · 2 unmodified lines | ||
| 360 | 360 | return 0; |
| 361 | 361 | |
| 362 | 362 | for (i = 1000; i > 0; --i) { |
| 363 | − if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff)) | |
| 363 | + if (((readl(priv->base + CLK_MON_R(reg))) & bitmask)) | |
| 364 | 364 | break; |
| 365 | 365 | cpu_relax(); |
| 366 | 366 | } |
| @@ -388,6 +388,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) · 21 unmodified lines | ||
| 388 | 388 | { |
| 389 | 389 | struct mstp_clock *clock = to_mod_clock(hw); |
| 390 | 390 | struct rzg2l_cpg_priv *priv = clock->priv; |
| 391 | + u32 bitmask = BIT(clock->bit); | |
| 391 | 392 | u32 value; |
| 392 | 393 | |
| 393 | 394 | if (!clock->off) { |
| @@ -397,7 +398,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) · 3 unmodified lines | ||
| 397 | 398 | |
| 398 | 399 | value = readl(priv->base + CLK_MON_R(clock->off)); |
| 399 | 400 | |
| 400 | − return !(value & clock->onoff); | |
| 401 | + return !(value & bitmask); | |
| 401 | 402 | } |
| 402 | 403 | |
| 403 | 404 | static const struct clk_ops rzg2l_mod_clock_ops = { |
| @@ -457,8 +458,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, · 53 unmodified lines | ||
| 457 | 458 | init.num_parents = 1; |
| 458 | 459 | |
| 459 | 460 | clock->off = mod->off; |
| 460 | − clock->onoff = mod->onoff; | |
| 461 | − clock->reset = mod->reset; | |
| 461 | + clock->bit = mod->bit; | |
| 462 | 462 | clock->priv = priv; |
| 463 | 463 | clock->hw.init = &init; |
| 464 | 464 | |
| @@ -483,12 +483,11 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, · 18 unmodified lines | ||
| 483 | 483 | { |
| 484 | 484 | struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); |
| 485 | 485 | const struct rzg2l_cpg_info *info = priv->info; |
| 486 | − unsigned int reg = info->mod_clks[id].off; | |
| 487 | − u32 dis = info->mod_clks[id].reset; | |
| 486 | + unsigned int reg = info->resets[id].off; | |
| 487 | + u32 dis = BIT(info->resets[id].bit); | |
| 488 | 488 | u32 we = dis << 16; |
| 489 | 489 | |
| 490 | − dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n", | |
| 491 | − info->mod_clks[id].name, id, CLK_RST_R(reg)); | |
| 490 | + dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); | |
| 492 | 491 | |
| 493 | 492 | /* Reset module */ |
| 494 | 493 | writel(we, priv->base + CLK_RST_R(reg)); |
| @@ -507,11 +506,10 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, · 12 unmodified lines | ||
| 507 | 506 | { |
| 508 | 507 | struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); |
| 509 | 508 | const struct rzg2l_cpg_info *info = priv->info; |
| 510 | − unsigned int reg = info->mod_clks[id].off; | |
| 511 | − u32 value = info->mod_clks[id].reset << 16; | |
| 509 | + unsigned int reg = info->resets[id].off; | |
| 510 | + u32 value = BIT(info->resets[id].bit) << 16; | |
| 512 | 511 | |
| 513 | − dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n", | |
| 514 | − info->mod_clks[id].name, id, CLK_RST_R(reg)); | |
| 512 | + dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); | |
| 515 | 513 | |
| 516 | 514 | writel(value, priv->base + CLK_RST_R(reg)); |
| 517 | 515 | return 0; |
| @@ -522,12 +520,12 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, · 4 unmodified lines | ||
| 522 | 520 | { |
| 523 | 521 | struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); |
| 524 | 522 | const struct rzg2l_cpg_info *info = priv->info; |
| 525 | − unsigned int reg = info->mod_clks[id].off; | |
| 526 | − u32 dis = info->mod_clks[id].reset; | |
| 523 | + unsigned int reg = info->resets[id].off; | |
| 524 | + u32 dis = BIT(info->resets[id].bit); | |
| 527 | 525 | u32 value = (dis << 16) | dis; |
| 528 | 526 | |
| 529 | − dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n", | |
| 530 | − info->mod_clks[id].name, id, CLK_RST_R(reg)); | |
| 527 | + dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, | |
| 528 | + CLK_RST_R(reg)); | |
| 531 | 529 | |
| 532 | 530 | writel(value, priv->base + CLK_RST_R(reg)); |
| 533 | 531 | return 0; |
| @@ -538,8 +536,8 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, · 4 unmodified lines | ||
| 538 | 536 | { |
| 539 | 537 | struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); |
| 540 | 538 | const struct rzg2l_cpg_info *info = priv->info; |
| 541 | − unsigned int reg = info->mod_clks[id].off; | |
| 542 | − u32 bitmask = info->mod_clks[id].reset; | |
| 539 | + unsigned int reg = info->resets[id].off; | |
| 540 | + u32 bitmask = BIT(info->resets[id].bit); | |
| 543 | 541 | |
| 544 | 542 | return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); |
| 545 | 543 | } |
| @@ -554,9 +552,11 @@ static const struct reset_control_ops rzg2l_cpg_reset_ops = { · 8 unmodified lines | ||
| 554 | 552 | static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev, |
| 555 | 553 | const struct of_phandle_args *reset_spec) |
| 556 | 554 | { |
| 555 | + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); | |
| 556 | + const struct rzg2l_cpg_info *info = priv->info; | |
| 557 | 557 | unsigned int id = reset_spec->args[0]; |
| 558 | 558 | |
| 559 | − if (id >= rcdev->nr_resets) { | |
| 559 | + if (id >= rcdev->nr_resets || !info->resets[id].off) { | |
| 560 | 560 | dev_err(rcdev->dev, "Invalid reset index %u\n", id); |
| 561 | 561 | return -EINVAL; |
| 562 | 562 | } |
| @@ -571,7 +571,7 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) · 8 unmodified lines | ||
| 571 | 571 | priv->rcdev.dev = priv->dev; |
| 572 | 572 | priv->rcdev.of_reset_n_cells = 1; |
| 573 | 573 | priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate; |
| 574 | − priv->rcdev.nr_resets = priv->num_mod_clks; | |
| 574 | + priv->rcdev.nr_resets = priv->num_resets; | |
| 575 | 575 | |
| 576 | 576 | return devm_reset_controller_register(priv->dev, &priv->rcdev); |
| 577 | 577 | } |
| @@ -594,42 +594,49 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device · 16 unmodified lines | ||
| 594 | 594 | { |
| 595 | 595 | struct device_node *np = dev->of_node; |
| 596 | 596 | struct of_phandle_args clkspec; |
| 597 | + bool once = true; | |
| 597 | 598 | struct clk *clk; |
| 598 | 599 | int error; |
| 599 | 600 | int i = 0; |
| 600 | 601 | |
| 601 | 602 | while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, |
| 602 | 603 | &clkspec)) { |
| 603 | − if (rzg2l_cpg_is_pm_clk(&clkspec)) | |
| 604 | − goto found; | |
| 605 | − | |
| 606 | − of_node_put(clkspec.np); | |
| 604 | + if (rzg2l_cpg_is_pm_clk(&clkspec)) { | |
| 605 | + if (once) { | |
| 606 | + once = false; | |
| 607 | + error = pm_clk_create(dev); | |
| 608 | + if (error) { | |
| 609 | + of_node_put(clkspec.np); | |
| 610 | + goto err; | |
| 611 | + } | |
| 612 | + } | |
| 613 | + clk = of_clk_get_from_provider(&clkspec); | |
| 614 | + of_node_put(clkspec.np); | |
| 615 | + if (IS_ERR(clk)) { | |
| 616 | + error = PTR_ERR(clk); | |
| 617 | + goto fail_destroy; | |
| 618 | + } | |
| 619 | + | |
| 620 | + error = pm_clk_add_clk(dev, clk); | |
| 621 | + if (error) { | |
| 622 | + dev_err(dev, "pm_clk_add_clk failed %d\n", | |
| 623 | + error); | |
| 624 | + goto fail_put; | |
| 625 | + } | |
| 626 | + } else { | |
| 627 | + of_node_put(clkspec.np); | |
| 628 | + } | |
| 607 | 629 | i++; |
| 608 | 630 | } |
| 609 | 631 | |
| 610 | 632 | return 0; |
| 611 | 633 | |
| 612 | −found: | |
| 613 | − clk = of_clk_get_from_provider(&clkspec); | |
| 614 | − of_node_put(clkspec.np); | |
| 615 | − | |
| 616 | − if (IS_ERR(clk)) | |
| 617 | − return PTR_ERR(clk); | |
| 618 | − | |
| 619 | − error = pm_clk_create(dev); | |
| 620 | − if (error) | |
| 621 | − goto fail_put; | |
| 622 | − | |
| 623 | − error = pm_clk_add_clk(dev, clk); | |
| 624 | − if (error) | |
| 625 | − goto fail_destroy; | |
| 626 | − | |
| 627 | − return 0; | |
| 634 | +fail_put: | |
| 635 | + clk_put(clk); | |
| 628 | 636 | |
| 629 | 637 | fail_destroy: |
| 630 | 638 | pm_clk_destroy(dev); |
| 631 | −fail_put: | |
| 632 | − clk_put(clk); | |
| 639 | +err: | |
| 633 | 640 | return error; |
| 634 | 641 | } |
| 635 | 642 | |
| @@ -692,6 +699,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) · 56 unmodified lines | ||
| 692 | 699 | priv->clks = clks; |
| 693 | 700 | priv->num_core_clks = info->num_total_core_clks; |
| 694 | 701 | priv->num_mod_clks = info->num_hw_mod_clks; |
| 702 | + priv->num_resets = info->num_resets; | |
| 695 | 703 | priv->last_dt_core_clk = info->last_dt_core_clk; |
| 696 | 704 | |
| 697 | 705 | for (i = 0; i < nclks; i++) |
| @@ -21,6 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | #define DDIV_PACK(offset, bitpos, size) \ |
| 22 | 22 | (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) |
| 23 | 23 | #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) |
| 24 | +#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) | |
| 24 | 25 | #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) |
| 25 | 26 | |
| 26 | 27 | /** |
| @@ -76,26 +77,40 @@ enum clk_types { · 49 unmodified lines | ||
| 76 | 77 | * @id: clock index in array containing all Core and Module Clocks |
| 77 | 78 | * @parent: id of parent clock |
| 78 | 79 | * @off: register offset |
| 79 | − * @onoff: ON/MON bits | |
| 80 | − * @reset: reset bits | |
| 80 | + * @bit: ON/MON bit | |
| 81 | 81 | */ |
| 82 | 82 | struct rzg2l_mod_clk { |
| 83 | 83 | const char *name; |
| 84 | 84 | unsigned int id; |
| 85 | 85 | unsigned int parent; |
| 86 | 86 | u16 off; |
| 87 | − u8 onoff; | |
| 88 | − u8 reset; | |
| 87 | + u8 bit; | |
| 89 | 88 | }; |
| 90 | 89 | |
| 91 | −#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \ | |
| 92 | − [_id] = { \ | |
| 90 | +#define DEF_MOD(_name, _id, _parent, _off, _bit) \ | |
| 91 | + { \ | |
| 93 | 92 | .name = _name, \ |
| 94 | − .id = MOD_CLK_BASE + _id, \ | |
| 93 | + .id = MOD_CLK_BASE + (_id), \ | |
| 95 | 94 | .parent = (_parent), \ |
| 96 | 95 | .off = (_off), \ |
| 97 | − .onoff = (_onoff), \ | |
| 98 | − .reset = (_reset) \ | |
| 96 | + .bit = (_bit), \ | |
| 97 | + } | |
| 98 | + | |
| 99 | +/** | |
| 100 | + * struct rzg2l_reset - Reset definitions | |
| 101 | + * | |
| 102 | + * @off: register offset | |
| 103 | + * @bit: reset bit | |
| 104 | + */ | |
| 105 | +struct rzg2l_reset { | |
| 106 | + u16 off; | |
| 107 | + u8 bit; | |
| 108 | +}; | |
| 109 | + | |
| 110 | +#define DEF_RST(_id, _off, _bit) \ | |
| 111 | + [_id] = { \ | |
| 112 | + .off = (_off), \ | |
| 113 | + .bit = (_bit) \ | |
| 99 | 114 | } |
| 100 | 115 | |
| 101 | 116 | /** |
| @@ -126,6 +141,10 @@ struct rzg2l_cpg_info { · 24 unmodified lines | ||
| 126 | 141 | unsigned int num_mod_clks; |
| 127 | 142 | unsigned int num_hw_mod_clks; |
| 128 | 143 | |
| 144 | + /* Resets */ | |
| 145 | + const struct rzg2l_reset *resets; | |
| 146 | + unsigned int num_resets; | |
| 147 | + | |
| 129 | 148 | /* Critical Module Clocks that should not be disabled */ |
| 130 | 149 | const unsigned int *crit_mod_clks; |
| 131 | 150 | unsigned int num_crit_mod_clks; |
| @@ -194,6 +194,15 @@ static void clk_sdmmc_mux_disable(struct clk_hw *hw) · 193 unmodified lines | ||
| 194 | 194 | gate_ops->disable(gate_hw); |
| 195 | 195 | } |
| 196 | 196 | |
| 197 | +static void clk_sdmmc_mux_disable_unused(struct clk_hw *hw) | |
| 198 | +{ | |
| 199 | + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); | |
| 200 | + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; | |
| 201 | + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; | |
| 202 | + | |
| 203 | + gate_ops->disable_unused(gate_hw); | |
| 204 | +} | |
| 205 | + | |
| 197 | 206 | static void clk_sdmmc_mux_restore_context(struct clk_hw *hw) |
| 198 | 207 | { |
| 199 | 208 | struct clk_hw *parent = clk_hw_get_parent(hw); |
| @@ -218,6 +227,7 @@ static const struct clk_ops tegra_clk_sdmmc_mux_ops = { · 18 unmodified lines | ||
| 218 | 227 | .is_enabled = clk_sdmmc_mux_is_enabled, |
| 219 | 228 | .enable = clk_sdmmc_mux_enable, |
| 220 | 229 | .disable = clk_sdmmc_mux_disable, |
| 230 | + .disable_unused = clk_sdmmc_mux_disable_unused, | |
| 221 | 231 | .restore_context = clk_sdmmc_mux_restore_context, |
| 222 | 232 | }; |
| 223 | 233 | |
| @@ -104,7 +104,11 @@ struct armada_37xx_dvfs { · 103 unmodified lines | ||
| 104 | 104 | }; |
| 105 | 105 | |
| 106 | 106 | static struct armada_37xx_dvfs armada_37xx_dvfs[] = { |
| 107 | − {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, | |
| 107 | + /* | |
| 108 | + * The cpufreq scaling for 1.2 GHz variant of the SOC is currently | |
| 109 | + * unstable because we do not know how to configure it properly. | |
| 110 | + */ | |
| 111 | + /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */ | |
| 108 | 112 | {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} }, |
| 109 | 113 | {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} }, |
| 110 | 114 | {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} }, |
| @@ -139,7 +139,9 @@ static const struct of_device_id blocklist[] __initconst = { · 138 unmodified lines | ||
| 139 | 139 | { .compatible = "qcom,qcs404", }, |
| 140 | 140 | { .compatible = "qcom,sc7180", }, |
| 141 | 141 | { .compatible = "qcom,sc7280", }, |
| 142 | + { .compatible = "qcom,sc8180x", }, | |
| 142 | 143 | { .compatible = "qcom,sdm845", }, |
| 144 | + { .compatible = "qcom,sm8150", }, | |
| 143 | 145 | |
| 144 | 146 | { .compatible = "st,stih407", }, |
| 145 | 147 | { .compatible = "st,stih410", }, |
| @@ -942,8 +942,6 @@ static int __init longhaul_init(void) · 941 unmodified lines | ||
| 942 | 942 | return cpufreq_register_driver(&longhaul_driver); |
| 943 | 943 | case 10: |
| 944 | 944 | pr_err("Use acpi-cpufreq driver for VIA C7\n"); |
| 945 | − default: | |
| 946 | − ; | |
| 947 | 945 | } |
| 948 | 946 | |
| 949 | 947 | return -ENODEV; |
| @@ -134,7 +134,7 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) · 133 unmodified lines | ||
| 134 | 134 | } |
| 135 | 135 | |
| 136 | 136 | if (!zalloc_cpumask_var(&opp_shared_cpus, GFP_KERNEL)) |
| 137 | − ret = -ENOMEM; | |
| 137 | + return -ENOMEM; | |
| 138 | 138 | |
| 139 | 139 | /* Obtain CPUs that share SCMI performance controls */ |
| 140 | 140 | ret = scmi_get_sharing_cpus(cpu_dev, policy->cpus); |
| @@ -382,8 +382,8 @@ static int teo_select(struct cpuidle_driver *drv, struct cpuidle_device *dev, · 381 unmodified lines | ||
| 382 | 382 | alt_intercepts = 2 * idx_intercept_sum > cpu_data->total - idx_hit_sum; |
| 383 | 383 | alt_recent = idx_recent_sum > NR_RECENT / 2; |
| 384 | 384 | if (alt_recent || alt_intercepts) { |
| 385 | − s64 last_enabled_span_ns = duration_ns; | |
| 386 | − int last_enabled_idx = idx; | |
| 385 | + s64 first_suitable_span_ns = duration_ns; | |
| 386 | + int first_suitable_idx = idx; | |
| 387 | 387 | |
| 388 | 388 | /* |
| 389 | 389 | * Look for the deepest idle state whose target residency had |
| @@ -397,37 +397,51 @@ static int teo_select(struct cpuidle_driver *drv, struct cpuidle_device *dev, · 7 unmodified lines | ||
| 397 | 397 | intercept_sum = 0; |
| 398 | 398 | recent_sum = 0; |
| 399 | 399 | |
| 400 | − for (i = idx - 1; i >= idx0; i--) { | |
| 400 | + for (i = idx - 1; i >= 0; i--) { | |
| 401 | 401 | struct teo_bin *bin = &cpu_data->state_bins[i]; |
| 402 | 402 | s64 span_ns; |
| 403 | 403 | |
| 404 | 404 | intercept_sum += bin->intercepts; |
| 405 | 405 | recent_sum += bin->recent; |
| 406 | 406 | |
| 407 | + span_ns = teo_middle_of_bin(i, drv); | |
| 408 | + | |
| 409 | + if ((!alt_recent || 2 * recent_sum > idx_recent_sum) && | |
| 410 | + (!alt_intercepts || | |
| 411 | + 2 * intercept_sum > idx_intercept_sum)) { | |
| 412 | + if (teo_time_ok(span_ns) && | |
| 413 | + !dev->states_usage[i].disable) { | |
| 414 | + idx = i; | |
| 415 | + duration_ns = span_ns; | |
| 416 | + } else { | |
| 417 | + /* | |
| 418 | + * The current state is too shallow or | |
| 419 | + * disabled, so take the first enabled | |
| 420 | + * deeper state with suitable time span. | |
| 421 | + */ | |
| 422 | + idx = first_suitable_idx; | |
| 423 | + duration_ns = first_suitable_span_ns; | |
| 424 | + } | |
| 425 | + break; | |
| 426 | + } | |
| 427 | + | |
| 407 | 428 | if (dev->states_usage[i].disable) |
| 408 | 429 | continue; |
| 409 | 430 | |
| 410 | − span_ns = teo_middle_of_bin(i, drv); | |
| 411 | 431 | if (!teo_time_ok(span_ns)) { |
| 412 | 432 | /* |
| 413 | − * The current state is too shallow, so select | |
| 414 | − * the first enabled deeper state. | |
| 433 | + * The current state is too shallow, but if an | |
| 434 | + * alternative candidate state has been found, | |
| 435 | + * it may still turn out to be a better choice. | |
| 415 | 436 | */ |
| 416 | − duration_ns = last_enabled_span_ns; | |
| 417 | − idx = last_enabled_idx; | |
| 418 | − break; | |
| 419 | − } | |
| 437 | + if (first_suitable_idx != idx) | |
| 438 | + continue; | |
| 420 | 439 | |
| 421 | − if ((!alt_recent || 2 * recent_sum > idx_recent_sum) && | |
| 422 | − (!alt_intercepts || | |
| 423 | − 2 * intercept_sum > idx_intercept_sum)) { | |
| 424 | − idx = i; | |
| 425 | − duration_ns = span_ns; | |
| 426 | 440 | break; |
| 427 | 441 | } |
| 428 | 442 | |
| 429 | − last_enabled_span_ns = span_ns; | |
| 430 | − last_enabled_idx = i; | |
| 443 | + first_suitable_span_ns = span_ns; | |
| 444 | + first_suitable_idx = i; | |
| 431 | 445 | } |
| 432 | 446 | } |
| 433 | 447 | |
| @@ -313,7 +313,7 @@ long dax_direct_access(struct dax_device *dax_dev, pgoff_t pgoff, long nr_pages, · 312 unmodified lines | ||
| 313 | 313 | return -ENXIO; |
| 314 | 314 | |
| 315 | 315 | if (nr_pages < 0) |
| 316 | − return nr_pages; | |
| 316 | + return -EINVAL; | |
| 317 | 317 | |
| 318 | 318 | avail = dax_dev->ops->direct_access(dax_dev, pgoff, nr_pages, |
| 319 | 319 | kaddr, pfn); |
| @@ -211,8 +211,8 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a, · 210 unmodified lines | ||
| 211 | 211 | struct sync_file *b) |
| 212 | 212 | { |
| 213 | 213 | struct sync_file *sync_file; |
| 214 | − struct dma_fence **fences, **nfences, **a_fences, **b_fences; | |
| 215 | − int i, i_a, i_b, num_fences, a_num_fences, b_num_fences; | |
| 214 | + struct dma_fence **fences = NULL, **nfences, **a_fences, **b_fences; | |
| 215 | + int i = 0, i_a, i_b, num_fences, a_num_fences, b_num_fences; | |
| 216 | 216 | |
| 217 | 217 | sync_file = sync_file_alloc(); |
| 218 | 218 | if (!sync_file) |
| @@ -236,7 +236,7 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a, · 17 unmodified lines | ||
| 236 | 236 | * If a sync_file can only be created with sync_file_merge |
| 237 | 237 | * and sync_file_create, this is a reasonable assumption. |
| 238 | 238 | */ |
| 239 | − for (i = i_a = i_b = 0; i_a < a_num_fences && i_b < b_num_fences; ) { | |
| 239 | + for (i_a = i_b = 0; i_a < a_num_fences && i_b < b_num_fences; ) { | |
| 240 | 240 | struct dma_fence *pt_a = a_fences[i_a]; |
| 241 | 241 | struct dma_fence *pt_b = b_fences[i_b]; |
| 242 | 242 | |
| @@ -277,15 +277,16 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a, · 34 unmodified lines | ||
| 277 | 277 | fences = nfences; |
| 278 | 278 | } |
| 279 | 279 | |
| 280 | − if (sync_file_set_fence(sync_file, fences, i) < 0) { | |
| 281 | − kfree(fences); | |
| 280 | + if (sync_file_set_fence(sync_file, fences, i) < 0) | |
| 282 | 281 | goto err; |
| 283 | − } | |
| 284 | 282 | |
| 285 | 283 | strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name)); |
| 286 | 284 | return sync_file; |
| 287 | 285 | |
| 288 | 286 | err: |
| 287 | + while (i) | |
| 288 | + dma_fence_put(fences[--i]); | |
| 289 | + kfree(fences); | |
| 289 | 290 | fput(sync_file->file); |
| 290 | 291 | return NULL; |
| 291 | 292 | |
| @@ -294,6 +294,14 @@ struct idxd_desc { · 293 unmodified lines | ||
| 294 | 294 | struct idxd_wq *wq; |
| 295 | 295 | }; |
| 296 | 296 | |
| 297 | +/* | |
| 298 | + * This is software defined error for the completion status. We overload the error code | |
| 299 | + * that will never appear in completion status and only SWERR register. | |
| 300 | + */ | |
| 301 | +enum idxd_completion_status { | |
| 302 | + IDXD_COMP_DESC_ABORT = 0xff, | |
| 303 | +}; | |
| 304 | + | |
| 297 | 305 | #define confdev_to_idxd(dev) container_of(dev, struct idxd_device, conf_dev) |
| 298 | 306 | #define confdev_to_wq(dev) container_of(dev, struct idxd_wq, conf_dev) |
| 299 | 307 | |
| @@ -482,4 +490,10 @@ static inline void perfmon_init(void) {} · 182 unmodified lines | ||
| 482 | 490 | static inline void perfmon_exit(void) {} |
| 483 | 491 | #endif |
| 484 | 492 | |
| 493 | +static inline void complete_desc(struct idxd_desc *desc, enum idxd_complete_type reason) | |
| 494 | +{ | |
| 495 | + idxd_dma_complete_txd(desc, reason); | |
| 496 | + idxd_free_desc(desc->wq, desc); | |
| 497 | +} | |
| 498 | + | |
| 485 | 499 | #endif |
| @@ -102,6 +102,8 @@ static int idxd_setup_interrupts(struct idxd_device *idxd) · 101 unmodified lines | ||
| 102 | 102 | spin_lock_init(&idxd->irq_entries[i].list_lock); |
| 103 | 103 | } |
| 104 | 104 | |
| 105 | + idxd_msix_perm_setup(idxd); | |
| 106 | + | |
| 105 | 107 | irq_entry = &idxd->irq_entries[0]; |
| 106 | 108 | rc = request_threaded_irq(irq_entry->vector, NULL, idxd_misc_thread, |
| 107 | 109 | 0, "idxd-misc", irq_entry); |
| @@ -148,7 +150,6 @@ static int idxd_setup_interrupts(struct idxd_device *idxd) · 40 unmodified lines | ||
| 148 | 150 | } |
| 149 | 151 | |
| 150 | 152 | idxd_unmask_error_interrupts(idxd); |
| 151 | − idxd_msix_perm_setup(idxd); | |
| 152 | 153 | return 0; |
| 153 | 154 | |
| 154 | 155 | err_wq_irqs: |
| @@ -162,6 +163,7 @@ static int idxd_setup_interrupts(struct idxd_device *idxd) · 7 unmodified lines | ||
| 162 | 163 | err_misc_irq: |
| 163 | 164 | /* Disable error interrupt generation */ |
| 164 | 165 | idxd_mask_error_interrupts(idxd); |
| 166 | + idxd_msix_perm_clear(idxd); | |
| 165 | 167 | err_irq_entries: |
| 166 | 168 | pci_free_irq_vectors(pdev); |
| 167 | 169 | dev_err(dev, "No usable interrupts\n"); |
| @@ -758,32 +760,40 @@ static void idxd_shutdown(struct pci_dev *pdev) · 590 unmodified lines | ||
| 758 | 760 | for (i = 0; i < msixcnt; i++) { |
| 759 | 761 | irq_entry = &idxd->irq_entries[i]; |
| 760 | 762 | synchronize_irq(irq_entry->vector); |
| 761 | − free_irq(irq_entry->vector, irq_entry); | |
| 762 | 763 | if (i == 0) |
| 763 | 764 | continue; |
| 764 | 765 | idxd_flush_pending_llist(irq_entry); |
| 765 | 766 | idxd_flush_work_list(irq_entry); |
| 766 | 767 | } |
| 767 | − | |
| 768 | − idxd_msix_perm_clear(idxd); | |
| 769 | − idxd_release_int_handles(idxd); | |
| 770 | − pci_free_irq_vectors(pdev); | |
| 771 | − pci_iounmap(pdev, idxd->reg_base); | |
| 772 | − pci_disable_device(pdev); | |
| 773 | − destroy_workqueue(idxd->wq); | |
| 768 | + flush_workqueue(idxd->wq); | |
| 774 | 769 | } |
| 775 | 770 | |
| 776 | 771 | static void idxd_remove(struct pci_dev *pdev) |
| 777 | 772 | { |
| 778 | 773 | struct idxd_device *idxd = pci_get_drvdata(pdev); |
| 774 | + struct idxd_irq_entry *irq_entry; | |
| 775 | + int msixcnt = pci_msix_vec_count(pdev); | |
| 776 | + int i; | |
| 779 | 777 | |
| 780 | 778 | dev_dbg(&pdev->dev, "%s called\n", __func__); |
| 781 | 779 | idxd_shutdown(pdev); |
| 782 | 780 | if (device_pasid_enabled(idxd)) |
| 783 | 781 | idxd_disable_system_pasid(idxd); |
| 784 | 782 | idxd_unregister_devices(idxd); |
| 785 | − perfmon_pmu_remove(idxd); | |
| 783 | + | |
| 784 | + for (i = 0; i < msixcnt; i++) { | |
| 785 | + irq_entry = &idxd->irq_entries[i]; | |
| 786 | + free_irq(irq_entry->vector, irq_entry); | |
| 787 | + } | |
| 788 | + idxd_msix_perm_clear(idxd); | |
| 789 | + idxd_release_int_handles(idxd); | |
| 790 | + pci_free_irq_vectors(pdev); | |
| 791 | + pci_iounmap(pdev, idxd->reg_base); | |
| 786 | 792 | iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); |
| 793 | + pci_disable_device(pdev); | |
| 794 | + destroy_workqueue(idxd->wq); | |
| 795 | + perfmon_pmu_remove(idxd); | |
| 796 | + device_unregister(&idxd->conf_dev); | |
| 787 | 797 | } |
| 788 | 798 | |
| 789 | 799 | static struct pci_driver idxd_pci_driver = { |
| @@ -245,12 +245,6 @@ static inline bool match_fault(struct idxd_desc *desc, u64 fault_addr) · 244 unmodified lines | ||
| 245 | 245 | return false; |
| 246 | 246 | } |
| 247 | 247 | |
| 248 | −static inline void complete_desc(struct idxd_desc *desc, enum idxd_complete_type reason) | |
| 249 | −{ | |
| 250 | − idxd_dma_complete_txd(desc, reason); | |
| 251 | − idxd_free_desc(desc->wq, desc); | |
| 252 | −} | |
| 253 | − | |
| 254 | 248 | static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry, |
| 255 | 249 | enum irq_work_type wtype, |
| 256 | 250 | int *processed, u64 data) |
| @@ -272,8 +266,16 @@ static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry, · 15 unmodified lines | ||
| 272 | 266 | reason = IDXD_COMPLETE_DEV_FAIL; |
| 273 | 267 | |
| 274 | 268 | llist_for_each_entry_safe(desc, t, head, llnode) { |
| 275 | − if (desc->completion->status) { | |
| 276 | − if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS) | |
| 269 | + u8 status = desc->completion->status & DSA_COMP_STATUS_MASK; | |
| 270 | + | |
| 271 | + if (status) { | |
| 272 | + if (unlikely(status == IDXD_COMP_DESC_ABORT)) { | |
| 273 | + complete_desc(desc, IDXD_COMPLETE_ABORT); | |
| 274 | + (*processed)++; | |
| 275 | + continue; | |
| 276 | + } | |
| 277 | + | |
| 278 | + if (unlikely(status != DSA_COMP_SUCCESS)) | |
| 277 | 279 | match_fault(desc, data); |
| 278 | 280 | complete_desc(desc, reason); |
| 279 | 281 | (*processed)++; |
| @@ -329,7 +331,14 @@ static int irq_process_work_list(struct idxd_irq_entry *irq_entry, · 49 unmodified lines | ||
| 329 | 331 | spin_unlock_irqrestore(&irq_entry->list_lock, flags); |
| 330 | 332 | |
| 331 | 333 | list_for_each_entry(desc, &flist, list) { |
| 332 | − if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS) | |
| 334 | + u8 status = desc->completion->status & DSA_COMP_STATUS_MASK; | |
| 335 | + | |
| 336 | + if (unlikely(status == IDXD_COMP_DESC_ABORT)) { | |
| 337 | + complete_desc(desc, IDXD_COMPLETE_ABORT); | |
| 338 | + continue; | |
| 339 | + } | |
| 340 | + | |
| 341 | + if (unlikely(status != DSA_COMP_SUCCESS)) | |
| 333 | 342 | match_fault(desc, data); |
| 334 | 343 | complete_desc(desc, reason); |
| 335 | 344 | } |
| @@ -25,11 +25,10 @@ static struct idxd_desc *__get_desc(struct idxd_wq *wq, int idx, int cpu) · 24 unmodified lines | ||
| 25 | 25 | * Descriptor completion vectors are 1...N for MSIX. We will round |
| 26 | 26 | * robin through the N vectors. |
| 27 | 27 | */ |
| 28 | − wq->vec_ptr = (wq->vec_ptr % idxd->num_wq_irqs) + 1; | |
| 28 | + wq->vec_ptr = desc->vector = (wq->vec_ptr % idxd->num_wq_irqs) + 1; | |
| 29 | 29 | if (!idxd->int_handles) { |
| 30 | 30 | desc->hw->int_handle = wq->vec_ptr; |
| 31 | 31 | } else { |
| 32 | − desc->vector = wq->vec_ptr; | |
| 33 | 32 | /* |
| 34 | 33 | * int_handles are only for descriptor completion. However for device |
| 35 | 34 | * MSIX enumeration, vec 0 is used for misc interrupts. Therefore even |
| @@ -88,9 +87,64 @@ void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc) · 52 unmodified lines | ||
| 88 | 87 | sbitmap_queue_clear(&wq->sbq, desc->id, cpu); |
| 89 | 88 | } |
| 90 | 89 | |
| 90 | +static struct idxd_desc *list_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie, | |
| 91 | + struct idxd_desc *desc) | |
| 92 | +{ | |
| 93 | + struct idxd_desc *d, *n; | |
| 94 | + | |
| 95 | + lockdep_assert_held(&ie->list_lock); | |
| 96 | + list_for_each_entry_safe(d, n, &ie->work_list, list) { | |
| 97 | + if (d == desc) { | |
| 98 | + list_del(&d->list); | |
| 99 | + return d; | |
| 100 | + } | |
| 101 | + } | |
| 102 | + | |
| 103 | + /* | |
| 104 | + * At this point, the desc needs to be aborted is held by the completion | |
| 105 | + * handler where it has taken it off the pending list but has not added to the | |
| 106 | + * work list. It will be cleaned up by the interrupt handler when it sees the | |
| 107 | + * IDXD_COMP_DESC_ABORT for completion status. | |
| 108 | + */ | |
| 109 | + return NULL; | |
| 110 | +} | |
| 111 | + | |
| 112 | +static void llist_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie, | |
| 113 | + struct idxd_desc *desc) | |
| 114 | +{ | |
| 115 | + struct idxd_desc *d, *t, *found = NULL; | |
| 116 | + struct llist_node *head; | |
| 117 | + unsigned long flags; | |
| 118 | + | |
| 119 | + desc->completion->status = IDXD_COMP_DESC_ABORT; | |
| 120 | + /* | |
| 121 | + * Grab the list lock so it will block the irq thread handler. This allows the | |
| 122 | + * abort code to locate the descriptor need to be aborted. | |
| 123 | + */ | |
| 124 | + spin_lock_irqsave(&ie->list_lock, flags); | |
| 125 | + head = llist_del_all(&ie->pending_llist); | |
| 126 | + if (head) { | |
| 127 | + llist_for_each_entry_safe(d, t, head, llnode) { | |
| 128 | + if (d == desc) { | |
| 129 | + found = desc; | |
| 130 | + continue; | |
| 131 | + } | |
| 132 | + list_add_tail(&desc->list, &ie->work_list); | |
| 133 | + } | |
| 134 | + } | |
| 135 | + | |
| 136 | + if (!found) | |
| 137 | + found = list_abort_desc(wq, ie, desc); | |
| 138 | + spin_unlock_irqrestore(&ie->list_lock, flags); | |
| 139 | + | |
| 140 | + if (found) | |
| 141 | + complete_desc(found, IDXD_COMPLETE_ABORT); | |
| 142 | +} | |
| 143 | + | |
| 91 | 144 | int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc) |
| 92 | 145 | { |
| 93 | 146 | struct idxd_device *idxd = wq->idxd; |
| 147 | + struct idxd_irq_entry *ie = NULL; | |
| 94 | 148 | void __iomem *portal; |
| 95 | 149 | int rc; |
| 96 | 150 | |
| @@ -108,6 +162,16 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc) · 11 unmodified lines | ||
| 108 | 162 | * even on UP because the recipient is a device. |
| 109 | 163 | */ |
| 110 | 164 | wmb(); |
| 165 | + | |
| 166 | + /* | |
| 167 | + * Pending the descriptor to the lockless list for the irq_entry | |
| 168 | + * that we designated the descriptor to. | |
| 169 | + */ | |
| 170 | + if (desc->hw->flags & IDXD_OP_FLAG_RCI) { | |
| 171 | + ie = &idxd->irq_entries[desc->vector]; | |
| 172 | + llist_add(&desc->llnode, &ie->pending_llist); | |
| 173 | + } | |
| 174 | + | |
| 111 | 175 | if (wq_dedicated(wq)) { |
| 112 | 176 | iosubmit_cmds512(portal, desc->hw, 1); |
| 113 | 177 | } else { |
| @@ -118,29 +182,13 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc) · 4 unmodified lines | ||
| 118 | 182 | * device is not accepting descriptor at all. |
| 119 | 183 | */ |
| 120 | 184 | rc = enqcmds(portal, desc->hw); |
| 121 | − if (rc < 0) | |
| 185 | + if (rc < 0) { | |
| 186 | + if (ie) | |
| 187 | + llist_abort_desc(wq, ie, desc); | |
| 122 | 188 | return rc; |
| 189 | + } | |
| 123 | 190 | } |
| 124 | 191 | |
| 125 | 192 | percpu_ref_put(&wq->wq_active); |
| 126 | − | |
| 127 | − /* | |
| 128 | − * Pending the descriptor to the lockless list for the irq_entry | |
| 129 | − * that we designated the descriptor to. | |
| 130 | − */ | |
| 131 | − if (desc->hw->flags & IDXD_OP_FLAG_RCI) { | |
| 132 | − int vec; | |
| 133 | − | |
| 134 | − /* | |
| 135 | − * If the driver is on host kernel, it would be the value | |
| 136 | − * assigned to interrupt handle, which is index for MSIX | |
| 137 | − * vector. If it's guest then can't use the int_handle since | |
| 138 | − * that is the index to IMS for the entire device. The guest | |
| 139 | − * device local index will be used. | |
| 140 | − */ | |
| 141 | − vec = !idxd->int_handles ? desc->hw->int_handle : desc->vector; | |
| 142 | − llist_add(&desc->llnode, &idxd->irq_entries[vec].pending_llist); | |
| 143 | − } | |
| 144 | − | |
| 145 | 193 | return 0; |
| 146 | 194 | } |
| @@ -1744,8 +1744,6 @@ void idxd_unregister_devices(struct idxd_device *idxd) · 1743 unmodified lines | ||
| 1744 | 1744 | |
| 1745 | 1745 | device_unregister(&group->conf_dev); |
| 1746 | 1746 | } |
| 1747 | − | |
| 1748 | − device_unregister(&idxd->conf_dev); | |
| 1749 | 1747 | } |
| 1750 | 1748 | |
| 1751 | 1749 | int idxd_register_bus_type(void) |
| @@ -812,6 +812,8 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( · 811 unmodified lines | ||
| 812 | 812 | dma_length += sg_dma_len(sg); |
| 813 | 813 | } |
| 814 | 814 | |
| 815 | + imxdma_config_write(chan, &imxdmac->config, direction); | |
| 816 | + | |
| 815 | 817 | switch (imxdmac->word_size) { |
| 816 | 818 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 817 | 819 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
| @@ -618,6 +618,7 @@ static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan) · 617 unmodified lines | ||
| 618 | 618 | case IDMAC_SDC_1: |
| 619 | 619 | case IDMAC_IC_7: |
| 620 | 620 | ipu_channel_set_priority(ipu, channel, true); |
| 621 | + break; | |
| 621 | 622 | default: |
| 622 | 623 | break; |
| 623 | 624 | } |
| @@ -978,6 +979,7 @@ static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan) · 354 unmodified lines | ||
| 978 | 979 | case IDMAC_SDC_0: |
| 979 | 980 | case IDMAC_SDC_1: |
| 980 | 981 | n_desc = 4; |
| 982 | + break; | |
| 981 | 983 | default: |
| 982 | 984 | break; |
| 983 | 985 | } |
| @@ -813,6 +813,7 @@ inline bool is_buswidth_valid(u8 buswidth, bool is_mpc8308) · 812 unmodified lines | ||
| 813 | 813 | case 16: |
| 814 | 814 | if (is_mpc8308) |
| 815 | 815 | return false; |
| 816 | + break; | |
| 816 | 817 | case 1: |
| 817 | 818 | case 2: |
| 818 | 819 | case 4: |
| @@ -67,8 +67,12 @@ static struct dma_chan *of_dma_router_xlate(struct of_phandle_args *dma_spec, · 66 unmodified lines | ||
| 67 | 67 | return NULL; |
| 68 | 68 | |
| 69 | 69 | ofdma_target = of_dma_find_controller(&dma_spec_target); |
| 70 | − if (!ofdma_target) | |
| 71 | − return NULL; | |
| 70 | + if (!ofdma_target) { | |
| 71 | + ofdma->dma_router->route_free(ofdma->dma_router->dev, | |
| 72 | + route_data); | |
| 73 | + chan = ERR_PTR(-EPROBE_DEFER); | |
| 74 | + goto err; | |
| 75 | + } | |
| 72 | 76 | |
| 73 | 77 | chan = ofdma_target->of_dma_xlate(&dma_spec_target, ofdma_target); |
| 74 | 78 | if (IS_ERR_OR_NULL(chan)) { |
| @@ -89,6 +93,7 @@ static struct dma_chan *of_dma_router_xlate(struct of_phandle_args *dma_spec, · 14 unmodified lines | ||
| 89 | 93 | } |
| 90 | 94 | } |
| 91 | 95 | |
| 96 | +err: | |
| 92 | 97 | /* |
| 93 | 98 | * Need to put the node back since the ofdma->of_dma_route_allocate |
| 94 | 99 | * has taken it for generating the new, translated dma_spec |
| @@ -855,8 +855,8 @@ static int usb_dmac_probe(struct platform_device *pdev) · 854 unmodified lines | ||
| 855 | 855 | |
| 856 | 856 | error: |
| 857 | 857 | of_dma_controller_free(pdev->dev.of_node); |
| 858 | − pm_runtime_put(&pdev->dev); | |
| 859 | 858 | error_pm: |
| 859 | + pm_runtime_put(&pdev->dev); | |
| 860 | 860 | pm_runtime_disable(&pdev->dev); |
| 861 | 861 | return ret; |
| 862 | 862 | } |
| @@ -1200,7 +1200,7 @@ static int stm32_dma_alloc_chan_resources(struct dma_chan *c) · 1199 unmodified lines | ||
| 1200 | 1200 | |
| 1201 | 1201 | chan->config_init = false; |
| 1202 | 1202 | |
| 1203 | − ret = pm_runtime_get_sync(dmadev->ddev.dev); | |
| 1203 | + ret = pm_runtime_resume_and_get(dmadev->ddev.dev); | |
| 1204 | 1204 | if (ret < 0) |
| 1205 | 1205 | return ret; |
| 1206 | 1206 | |
| @@ -1470,7 +1470,7 @@ static int stm32_dma_suspend(struct device *dev) · 263 unmodified lines | ||
| 1470 | 1470 | struct stm32_dma_device *dmadev = dev_get_drvdata(dev); |
| 1471 | 1471 | int id, ret, scr; |
| 1472 | 1472 | |
| 1473 | − ret = pm_runtime_get_sync(dev); | |
| 1473 | + ret = pm_runtime_resume_and_get(dev); | |
| 1474 | 1474 | if (ret < 0) |
| 1475 | 1475 | return ret; |
| 1476 | 1476 | |
| @@ -137,7 +137,7 @@ static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec, · 136 unmodified lines | ||
| 137 | 137 | |
| 138 | 138 | /* Set dma request */ |
| 139 | 139 | spin_lock_irqsave(&dmamux->lock, flags); |
| 140 | − ret = pm_runtime_get_sync(&pdev->dev); | |
| 140 | + ret = pm_runtime_resume_and_get(&pdev->dev); | |
| 141 | 141 | if (ret < 0) { |
| 142 | 142 | spin_unlock_irqrestore(&dmamux->lock, flags); |
| 143 | 143 | goto error; |
| @@ -336,7 +336,7 @@ static int stm32_dmamux_suspend(struct device *dev) · 192 unmodified lines | ||
| 336 | 336 | struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev); |
| 337 | 337 | int i, ret; |
| 338 | 338 | |
| 339 | − ret = pm_runtime_get_sync(dev); | |
| 339 | + ret = pm_runtime_resume_and_get(dev); | |
| 340 | 340 | if (ret < 0) |
| 341 | 341 | return ret; |
| 342 | 342 | |
| @@ -361,7 +361,7 @@ static int stm32_dmamux_resume(struct device *dev) · 18 unmodified lines | ||
| 361 | 361 | if (ret < 0) |
| 362 | 362 | return ret; |
| 363 | 363 | |
| 364 | − ret = pm_runtime_get_sync(dev); | |
| 364 | + ret = pm_runtime_resume_and_get(dev); | |
| 365 | 365 | if (ret < 0) |
| 366 | 366 | return ret; |
| 367 | 367 | |
| @@ -4948,6 +4948,7 @@ static int setup_resources(struct udma_dev *ud) · 4947 unmodified lines | ||
| 4948 | 4948 | ud->tchan_cnt), |
| 4949 | 4949 | ud->rchan_cnt - bitmap_weight(ud->rchan_map, |
| 4950 | 4950 | ud->rchan_cnt)); |
| 4951 | + break; | |
| 4951 | 4952 | default: |
| 4952 | 4953 | break; |
| 4953 | 4954 | } |
| @@ -209,8 +209,8 @@ static int uniphier_xdmac_chan_stop(struct uniphier_xdmac_chan *xc) · 208 unmodified lines | ||
| 209 | 209 | writel(0, xc->reg_ch_base + XDMAC_TSS); |
| 210 | 210 | |
| 211 | 211 | /* wait until transfer is stopped */ |
| 212 | − return readl_poll_timeout(xc->reg_ch_base + XDMAC_STAT, val, | |
| 213 | − !(val & XDMAC_STAT_TENF), 100, 1000); | |
| 212 | + return readl_poll_timeout_atomic(xc->reg_ch_base + XDMAC_STAT, val, | |
| 213 | + !(val & XDMAC_STAT_TENF), 100, 1000); | |
| 214 | 214 | } |
| 215 | 215 | |
| 216 | 216 | /* xc->vc.lock must be held by caller */ |
| @@ -394,6 +394,7 @@ struct xilinx_dma_tx_descriptor { · 393 unmodified lines | ||
| 394 | 394 | * @genlock: Support genlock mode |
| 395 | 395 | * @err: Channel has errors |
| 396 | 396 | * @idle: Check for channel idle |
| 397 | + * @terminating: Check for channel being synchronized by user | |
| 397 | 398 | * @tasklet: Cleanup work after irq |
| 398 | 399 | * @config: Device configuration info |
| 399 | 400 | * @flush_on_fsync: Flush on Frame sync |
| @@ -431,6 +432,7 @@ struct xilinx_dma_chan { · 31 unmodified lines | ||
| 431 | 432 | bool genlock; |
| 432 | 433 | bool err; |
| 433 | 434 | bool idle; |
| 435 | + bool terminating; | |
| 434 | 436 | struct tasklet_struct tasklet; |
| 435 | 437 | struct xilinx_vdma_config config; |
| 436 | 438 | bool flush_on_fsync; |
| @@ -1049,6 +1051,13 @@ static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) · 612 unmodified lines | ||
| 1049 | 1051 | /* Run any dependencies, then free the descriptor */ |
| 1050 | 1052 | dma_run_dependencies(&desc->async_tx); |
| 1051 | 1053 | xilinx_dma_free_tx_descriptor(chan, desc); |
| 1054 | + | |
| 1055 | + /* | |
| 1056 | + * While we ran a callback the user called a terminate function, | |
| 1057 | + * which takes care of cleaning up any remaining descriptors | |
| 1058 | + */ | |
| 1059 | + if (chan->terminating) | |
| 1060 | + break; | |
| 1052 | 1061 | } |
| 1053 | 1062 | |
| 1054 | 1063 | spin_unlock_irqrestore(&chan->lock, flags); |
| @@ -1965,6 +1974,8 @@ static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) · 910 unmodified lines | ||
| 1965 | 1974 | if (desc->cyclic) |
| 1966 | 1975 | chan->cyclic = true; |
| 1967 | 1976 | |
| 1977 | + chan->terminating = false; | |
| 1978 | + | |
| 1968 | 1979 | spin_unlock_irqrestore(&chan->lock, flags); |
| 1969 | 1980 | |
| 1970 | 1981 | return cookie; |
| @@ -2436,6 +2447,7 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan) · 465 unmodified lines | ||
| 2436 | 2447 | |
| 2437 | 2448 | xilinx_dma_chan_reset(chan); |
| 2438 | 2449 | /* Remove and free all of the descriptors in the lists */ |
| 2450 | + chan->terminating = true; | |
| 2439 | 2451 | xilinx_dma_free_descriptors(chan); |
| 2440 | 2452 | chan->idle = true; |
| 2441 | 2453 | |
| @@ -271,7 +271,7 @@ config EDAC_PND2 · 270 unmodified lines | ||
| 271 | 271 | config EDAC_IGEN6 |
| 272 | 272 | tristate "Intel client SoC Integrated MC" |
| 273 | 273 | depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG |
| 274 | − depends on X64_64 && X86_MCE_INTEL | |
| 274 | + depends on X86_64 && X86_MCE_INTEL | |
| 275 | 275 | help |
| 276 | 276 | Support for error detection and correction on the Intel |
| 277 | 277 | client SoC Integrated Memory Controller using In-Band ECC IP. |
| @@ -46,9 +46,6 @@ static int ffa_device_probe(struct device *dev) · 45 unmodified lines | ||
| 46 | 46 | struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver); |
| 47 | 47 | struct ffa_device *ffa_dev = to_ffa_dev(dev); |
| 48 | 48 | |
| 49 | − if (!ffa_device_match(dev, dev->driver)) | |
| 50 | − return -ENODEV; | |
| 51 | − | |
| 52 | 49 | return ffa_drv->probe(ffa_dev); |
| 53 | 50 | } |
| 54 | 51 | |
| @@ -99,6 +96,9 @@ int ffa_driver_register(struct ffa_driver *driver, struct module *owner, · 44 unmodified lines | ||
| 99 | 96 | { |
| 100 | 97 | int ret; |
| 101 | 98 | |
| 99 | + if (!driver->probe) | |
| 100 | + return -EINVAL; | |
| 101 | + | |
| 102 | 102 | driver->driver.bus = &ffa_bus_type; |
| 103 | 103 | driver->driver.name = driver->name; |
| 104 | 104 | driver->driver.owner = owner; |
| @@ -120,7 +120,7 @@ · 119 unmodified lines | ||
| 120 | 120 | #define PACK_TARGET_INFO(s, r) \ |
| 121 | 121 | (FIELD_PREP(SENDER_ID_MASK, (s)) | FIELD_PREP(RECEIVER_ID_MASK, (r))) |
| 122 | 122 | |
| 123 | −/** | |
| 123 | +/* | |
| 124 | 124 | * FF-A specification mentions explicitly about '4K pages'. This should |
| 125 | 125 | * not be confused with the kernel PAGE_SIZE, which is the translation |
| 126 | 126 | * granule kernel is configured and may be one among 4K, 16K and 64K. |
| @@ -149,8 +149,10 @@ static const int ffa_linux_errmap[] = { · 22 unmodified lines | ||
| 149 | 149 | |
| 150 | 150 | static inline int ffa_to_linux_errno(int errno) |
| 151 | 151 | { |
| 152 | − if (errno < FFA_RET_SUCCESS && errno >= -ARRAY_SIZE(ffa_linux_errmap)) | |
| 153 | − return ffa_linux_errmap[-errno]; | |
| 152 | + int err_idx = -errno; | |
| 153 | + | |
| 154 | + if (err_idx >= 0 && err_idx < ARRAY_SIZE(ffa_linux_errmap)) | |
| 155 | + return ffa_linux_errmap[err_idx]; | |
| 154 | 156 | return -EINVAL; |
| 155 | 157 | } |
| 156 | 158 | |
| @@ -104,11 +104,6 @@ static int scmi_dev_probe(struct device *dev) · 103 unmodified lines | ||
| 104 | 104 | { |
| 105 | 105 | struct scmi_driver *scmi_drv = to_scmi_driver(dev->driver); |
| 106 | 106 | struct scmi_device *scmi_dev = to_scmi_dev(dev); |
| 107 | − const struct scmi_device_id *id; | |
| 108 | − | |
| 109 | − id = scmi_dev_match_id(scmi_dev, scmi_drv); | |
| 110 | − if (!id) | |
| 111 | − return -ENODEV; | |
| 112 | 107 | |
| 113 | 108 | if (!scmi_dev->handle) |
| 114 | 109 | return -EPROBE_DEFER; |
| @@ -139,6 +134,9 @@ int scmi_driver_register(struct scmi_driver *driver, struct module *owner, · 24 unmodified lines | ||
| 139 | 134 | { |
| 140 | 135 | int retval; |
| 141 | 136 | |
| 137 | + if (!driver->probe) | |
| 138 | + return -EINVAL; | |
| 139 | + | |
| 142 | 140 | retval = scmi_protocol_device_request(driver->id_table); |
| 143 | 141 | if (retval) |
| 144 | 142 | return retval; |
| @@ -47,7 +47,6 @@ enum scmi_error_codes { · 46 unmodified lines | ||
| 47 | 47 | SCMI_ERR_GENERIC = -8, /* Generic Error */ |
| 48 | 48 | SCMI_ERR_HARDWARE = -9, /* Hardware Error */ |
| 49 | 49 | SCMI_ERR_PROTOCOL = -10,/* Protocol Error */ |
| 50 | − SCMI_ERR_MAX | |
| 51 | 50 | }; |
| 52 | 51 | |
| 53 | 52 | /* List of all SCMI devices active in system */ |
| @@ -166,8 +165,10 @@ static const int scmi_linux_errmap[] = { · 112 unmodified lines | ||
| 166 | 165 | |
| 167 | 166 | static inline int scmi_to_linux_errno(int errno) |
| 168 | 167 | { |
| 169 | − if (errno < SCMI_SUCCESS && errno > SCMI_ERR_MAX) | |
| 170 | − return scmi_linux_errmap[-errno]; | |
| 168 | + int err_idx = -errno; | |
| 169 | + | |
| 170 | + if (err_idx >= SCMI_SUCCESS && err_idx < ARRAY_SIZE(scmi_linux_errmap)) | |
| 171 | + return scmi_linux_errmap[err_idx]; | |
| 171 | 172 | return -EIO; |
| 172 | 173 | } |
| 173 | 174 | |
| @@ -1025,8 +1026,9 @@ static int __scmi_xfer_info_init(struct scmi_info *sinfo, · 851 unmodified lines | ||
| 1025 | 1026 | const struct scmi_desc *desc = sinfo->desc; |
| 1026 | 1027 | |
| 1027 | 1028 | /* Pre-allocated messages, no more than what hdr.seq can support */ |
| 1028 | − if (WARN_ON(desc->max_msg >= MSG_TOKEN_MAX)) { | |
| 1029 | − dev_err(dev, "Maximum message of %d exceeds supported %ld\n", | |
| 1029 | + if (WARN_ON(!desc->max_msg || desc->max_msg > MSG_TOKEN_MAX)) { | |
| 1030 | + dev_err(dev, | |
| 1031 | + "Invalid maximum messages %d, not in range [1 - %lu]\n", | |
| 1030 | 1032 | desc->max_msg, MSG_TOKEN_MAX); |
| 1031 | 1033 | return -EINVAL; |
| 1032 | 1034 | } |
| @@ -1137,6 +1139,8 @@ scmi_txrx_setup(struct scmi_info *info, struct device *dev, int prot_id) · 104 unmodified lines | ||
| 1137 | 1139 | * @proto_id and @name: if device was still not existent it is created as a |
| 1138 | 1140 | * child of the specified SCMI instance @info and its transport properly |
| 1139 | 1141 | * initialized as usual. |
| 1142 | + * | |
| 1143 | + * Return: A properly initialized scmi device, NULL otherwise. | |
| 1140 | 1144 | */ |
| 1141 | 1145 | static inline struct scmi_device * |
| 1142 | 1146 | scmi_get_protocol_device(struct device_node *np, struct scmi_info *info, |
| @@ -1457,6 +1457,8 @@ static void scmi_devm_release_notifier(struct device *dev, void *res) · 1456 unmodified lines | ||
| 1457 | 1457 | * |
| 1458 | 1458 | * Generic devres managed helper to register a notifier_block against a |
| 1459 | 1459 | * protocol event. |
| 1460 | + * | |
| 1461 | + * Return: 0 on Success | |
| 1460 | 1462 | */ |
| 1461 | 1463 | static int scmi_devm_notifier_register(struct scmi_device *sdev, |
| 1462 | 1464 | u8 proto_id, u8 evt_id, |
| @@ -1523,6 +1525,8 @@ static int scmi_devm_notifier_match(struct device *dev, void *res, void *data) · 60 unmodified lines | ||
| 1523 | 1525 | * Generic devres managed helper to explicitly un-register a notifier_block |
| 1524 | 1526 | * against a protocol event, which was previously registered using the above |
| 1525 | 1527 | * @scmi_devm_notifier_register. |
| 1528 | + * | |
| 1529 | + * Return: 0 on Success | |
| 1526 | 1530 | */ |
| 1527 | 1531 | static int scmi_devm_notifier_unregister(struct scmi_device *sdev, |
| 1528 | 1532 | u8 proto_id, u8 evt_id, |
| @@ -166,7 +166,8 @@ struct scmi_msg_sensor_reading_get { · 165 unmodified lines | ||
| 166 | 166 | |
| 167 | 167 | struct scmi_resp_sensor_reading_complete { |
| 168 | 168 | __le32 id; |
| 169 | − __le64 readings; | |
| 169 | + __le32 readings_low; | |
| 170 | + __le32 readings_high; | |
| 170 | 171 | }; |
| 171 | 172 | |
| 172 | 173 | struct scmi_sensor_reading_resp { |
| @@ -717,7 +718,8 @@ static int scmi_sensor_reading_get(const struct scmi_protocol_handle *ph, · 544 unmodified lines | ||
| 717 | 718 | |
| 718 | 719 | resp = t->rx.buf; |
| 719 | 720 | if (le32_to_cpu(resp->id) == sensor_id) |
| 720 | − *value = get_unaligned_le64(&resp->readings); | |
| 721 | + *value = | |
| 722 | + get_unaligned_le64(&resp->readings_low); | |
| 721 | 723 | else |
| 722 | 724 | ret = -EPROTO; |
| 723 | 725 | } |
| @@ -212,10 +212,9 @@ static int tee_bnxt_fw_probe(struct device *dev) · 211 unmodified lines | ||
| 212 | 212 | |
| 213 | 213 | pvt_data.dev = dev; |
| 214 | 214 | |
| 215 | − fw_shm_pool = tee_shm_alloc(pvt_data.ctx, MAX_SHM_MEM_SZ, | |
| 216 | − TEE_SHM_MAPPED | TEE_SHM_DMA_BUF); | |
| 215 | + fw_shm_pool = tee_shm_alloc_kernel_buf(pvt_data.ctx, MAX_SHM_MEM_SZ); | |
| 217 | 216 | if (IS_ERR(fw_shm_pool)) { |
| 218 | − dev_err(pvt_data.dev, "tee_shm_alloc failed\n"); | |
| 217 | + dev_err(pvt_data.dev, "tee_shm_alloc_kernel_buf failed\n"); | |
| 219 | 218 | err = PTR_ERR(fw_shm_pool); |
| 220 | 219 | goto out_sess; |
| 221 | 220 | } |
| @@ -242,6 +241,14 @@ static int tee_bnxt_fw_remove(struct device *dev) · 20 unmodified lines | ||
| 242 | 241 | return 0; |
| 243 | 242 | } |
| 244 | 243 | |
| 244 | +static void tee_bnxt_fw_shutdown(struct device *dev) | |
| 245 | +{ | |
| 246 | + tee_shm_free(pvt_data.fw_shm_pool); | |
| 247 | + tee_client_close_session(pvt_data.ctx, pvt_data.session_id); | |
| 248 | + tee_client_close_context(pvt_data.ctx); | |
| 249 | + pvt_data.ctx = NULL; | |
| 250 | +} | |
| 251 | + | |
| 245 | 252 | static const struct tee_client_device_id tee_bnxt_fw_id_table[] = { |
| 246 | 253 | {UUID_INIT(0x6272636D, 0x2019, 0x0716, |
| 247 | 254 | 0x42, 0x43, 0x4D, 0x5F, 0x53, 0x43, 0x48, 0x49)}, |
| @@ -257,6 +264,7 @@ static struct tee_client_driver tee_bnxt_fw_driver = { · 9 unmodified lines | ||
| 257 | 264 | .bus = &tee_bus_type, |
| 258 | 265 | .probe = tee_bnxt_fw_probe, |
| 259 | 266 | .remove = tee_bnxt_fw_remove, |
| 267 | + .shutdown = tee_bnxt_fw_shutdown, | |
| 260 | 268 | }, |
| 261 | 269 | }; |
| 262 | 270 | |
| @@ -34,7 +34,6 @@ static long __init parse_acpi_path(const struct efi_dev_path *node, · 33 unmodified lines | ||
| 34 | 34 | break; |
| 35 | 35 | if (!adev->pnp.unique_id && node->acpi.uid == 0) |
| 36 | 36 | break; |
| 37 | − acpi_dev_put(adev); | |
| 38 | 37 | } |
| 39 | 38 | if (!adev) |
| 40 | 39 | return -ENODEV; |
| @@ -896,6 +896,7 @@ static int __init efi_memreserve_map_root(void) · 895 unmodified lines | ||
| 896 | 896 | static int efi_mem_reserve_iomem(phys_addr_t addr, u64 size) |
| 897 | 897 | { |
| 898 | 898 | struct resource *res, *parent; |
| 899 | + int ret; | |
| 899 | 900 | |
| 900 | 901 | res = kzalloc(sizeof(struct resource), GFP_ATOMIC); |
| 901 | 902 | if (!res) |
| @@ -908,7 +909,17 @@ static int efi_mem_reserve_iomem(phys_addr_t addr, u64 size) · 6 unmodified lines | ||
| 908 | 909 | |
| 909 | 910 | /* we expect a conflict with a 'System RAM' region */ |
| 910 | 911 | parent = request_resource_conflict(&iomem_resource, res); |
| 911 | − return parent ? request_resource(parent, res) : 0; | |
| 912 | + ret = parent ? request_resource(parent, res) : 0; | |
| 913 | + | |
| 914 | + /* | |
| 915 | + * Given that efi_mem_reserve_iomem() can be called at any | |
| 916 | + * time, only call memblock_reserve() if the architecture | |
| 917 | + * keeps the infrastructure around. | |
| 918 | + */ | |
| 919 | + if (IS_ENABLED(CONFIG_ARCH_KEEP_MEMBLOCK) && !ret) | |
| 920 | + memblock_reserve(addr, size); | |
| 921 | + | |
| 922 | + return ret; | |
| 912 | 923 | } |
| 913 | 924 | |
| 914 | 925 | int __ref efi_mem_reserve_persistent(phys_addr_t addr, u64 size) |
| @@ -35,15 +35,48 @@ efi_status_t check_platform_features(void) · 34 unmodified lines | ||
| 35 | 35 | } |
| 36 | 36 | |
| 37 | 37 | /* |
| 38 | − * Although relocatable kernels can fix up the misalignment with respect to | |
| 39 | − * MIN_KIMG_ALIGN, the resulting virtual text addresses are subtly out of | |
| 40 | − * sync with those recorded in the vmlinux when kaslr is disabled but the | |
| 41 | − * image required relocation anyway. Therefore retain 2M alignment unless | |
| 42 | − * KASLR is in use. | |
| 38 | + * Distro versions of GRUB may ignore the BSS allocation entirely (i.e., fail | |
| 39 | + * to provide space, and fail to zero it). Check for this condition by double | |
| 40 | + * checking that the first and the last byte of the image are covered by the | |
| 41 | + * same EFI memory map entry. | |
| 43 | 42 | */ |
| 44 | −static u64 min_kimg_align(void) | |
| 43 | +static bool check_image_region(u64 base, u64 size) | |
| 45 | 44 | { |
| 46 | − return efi_nokaslr ? MIN_KIMG_ALIGN : EFI_KIMG_ALIGN; | |
| 45 | + unsigned long map_size, desc_size, buff_size; | |
| 46 | + efi_memory_desc_t *memory_map; | |
| 47 | + struct efi_boot_memmap map; | |
| 48 | + efi_status_t status; | |
| 49 | + bool ret = false; | |
| 50 | + int map_offset; | |
| 51 | + | |
| 52 | + map.map = &memory_map; | |
| 53 | + map.map_size = &map_size; | |
| 54 | + map.desc_size = &desc_size; | |
| 55 | + map.desc_ver = NULL; | |
| 56 | + map.key_ptr = NULL; | |
| 57 | + map.buff_size = &buff_size; | |
| 58 | + | |
| 59 | + status = efi_get_memory_map(&map); | |
| 60 | + if (status != EFI_SUCCESS) | |
| 61 | + return false; | |
| 62 | + | |
| 63 | + for (map_offset = 0; map_offset < map_size; map_offset += desc_size) { | |
| 64 | + efi_memory_desc_t *md = (void *)memory_map + map_offset; | |
| 65 | + u64 end = md->phys_addr + md->num_pages * EFI_PAGE_SIZE; | |
| 66 | + | |
| 67 | + /* | |
| 68 | + * Find the region that covers base, and return whether | |
| 69 | + * it covers base+size bytes. | |
| 70 | + */ | |
| 71 | + if (base >= md->phys_addr && base < end) { | |
| 72 | + ret = (base + size) <= end; | |
| 73 | + break; | |
| 74 | + } | |
| 75 | + } | |
| 76 | + | |
| 77 | + efi_bs_call(free_pool, memory_map); | |
| 78 | + | |
| 79 | + return ret; | |
| 47 | 80 | } |
| 48 | 81 | |
| 49 | 82 | efi_status_t handle_kernel_image(unsigned long *image_addr, |
| @@ -56,6 +89,16 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, · 6 unmodified lines | ||
| 56 | 89 | unsigned long kernel_size, kernel_memsize = 0; |
| 57 | 90 | u32 phys_seed = 0; |
| 58 | 91 | |
| 92 | + /* | |
| 93 | + * Although relocatable kernels can fix up the misalignment with | |
| 94 | + * respect to MIN_KIMG_ALIGN, the resulting virtual text addresses are | |
| 95 | + * subtly out of sync with those recorded in the vmlinux when kaslr is | |
| 96 | + * disabled but the image required relocation anyway. Therefore retain | |
| 97 | + * 2M alignment if KASLR was explicitly disabled, even if it was not | |
| 98 | + * going to be activated to begin with. | |
| 99 | + */ | |
| 100 | + u64 min_kimg_align = efi_nokaslr ? MIN_KIMG_ALIGN : EFI_KIMG_ALIGN; | |
| 101 | + | |
| 59 | 102 | if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { |
| 60 | 103 | if (!efi_nokaslr) { |
| 61 | 104 | status = efi_get_random_bytes(sizeof(phys_seed), |
| @@ -76,6 +119,10 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, · 14 unmodified lines | ||
| 76 | 119 | if (image->image_base != _text) |
| 77 | 120 | efi_err("FIRMWARE BUG: efi_loaded_image_t::image_base has bogus value\n"); |
| 78 | 121 | |
| 122 | + if (!IS_ALIGNED((u64)_text, EFI_KIMG_ALIGN)) | |
| 123 | + efi_err("FIRMWARE BUG: kernel image not aligned on %ldk boundary\n", | |
| 124 | + EFI_KIMG_ALIGN >> 10); | |
| 125 | + | |
| 79 | 126 | kernel_size = _edata - _text; |
| 80 | 127 | kernel_memsize = kernel_size + (_end - _edata); |
| 81 | 128 | *reserve_size = kernel_memsize; |
| @@ -85,14 +132,18 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, · 3 unmodified lines | ||
| 85 | 132 | * If KASLR is enabled, and we have some randomness available, |
| 86 | 133 | * locate the kernel at a randomized offset in physical memory. |
| 87 | 134 | */ |
| 88 | − status = efi_random_alloc(*reserve_size, min_kimg_align(), | |
| 135 | + status = efi_random_alloc(*reserve_size, min_kimg_align, | |
| 89 | 136 | reserve_addr, phys_seed); |
| 137 | + if (status != EFI_SUCCESS) | |
| 138 | + efi_warn("efi_random_alloc() failed: 0x%lx\n", status); | |
| 90 | 139 | } else { |
| 91 | 140 | status = EFI_OUT_OF_RESOURCES; |
| 92 | 141 | } |
| 93 | 142 | |
| 94 | 143 | if (status != EFI_SUCCESS) { |
| 95 | − if (IS_ALIGNED((u64)_text, min_kimg_align())) { | |
| 144 | + if (!check_image_region((u64)_text, kernel_memsize)) { | |
| 145 | + efi_err("FIRMWARE BUG: Image BSS overlaps adjacent EFI memory region\n"); | |
| 146 | + } else if (IS_ALIGNED((u64)_text, min_kimg_align)) { | |
| 96 | 147 | /* |
| 97 | 148 | * Just execute from wherever we were loaded by the |
| 98 | 149 | * UEFI PE/COFF loader if the alignment is suitable. |
| @@ -103,7 +154,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, · 4 unmodified lines | ||
| 103 | 154 | } |
| 104 | 155 | |
| 105 | 156 | status = efi_allocate_pages_aligned(*reserve_size, reserve_addr, |
| 106 | − ULONG_MAX, min_kimg_align()); | |
| 157 | + ULONG_MAX, min_kimg_align); | |
| 107 | 158 | |
| 108 | 159 | if (status != EFI_SUCCESS) { |
| 109 | 160 | efi_err("Failed to relocate kernel\n"); |
| @@ -630,8 +630,8 @@ efi_status_t efi_load_initrd_cmdline(efi_loaded_image_t *image, · 629 unmodified lines | ||
| 630 | 630 | * @image: EFI loaded image protocol |
| 631 | 631 | * @load_addr: pointer to loaded initrd |
| 632 | 632 | * @load_size: size of loaded initrd |
| 633 | − * @soft_limit: preferred size of allocated memory for loading the initrd | |
| 634 | − * @hard_limit: minimum size of allocated memory | |
| 633 | + * @soft_limit: preferred address for loading the initrd | |
| 634 | + * @hard_limit: upper limit address for loading the initrd | |
| 635 | 635 | * |
| 636 | 636 | * Return: status code |
| 637 | 637 | */ |
| @@ -30,6 +30,8 @@ static unsigned long get_entry_num_slots(efi_memory_desc_t *md, · 29 unmodified lines | ||
| 30 | 30 | |
| 31 | 31 | region_end = min(md->phys_addr + md->num_pages * EFI_PAGE_SIZE - 1, |
| 32 | 32 | (u64)ULONG_MAX); |
| 33 | + if (region_end < size) | |
| 34 | + return 0; | |
| 33 | 35 | |
| 34 | 36 | first_slot = round_up(md->phys_addr, align); |
| 35 | 37 | last_slot = round_down(region_end - size + 1, align); |
| @@ -180,7 +180,10 @@ void __init efi_mokvar_table_init(void) · 179 unmodified lines | ||
| 180 | 180 | pr_err("EFI MOKvar config table is not valid\n"); |
| 181 | 181 | return; |
| 182 | 182 | } |
| 183 | − efi_mem_reserve(efi.mokvar_table, map_size_needed); | |
| 183 | + | |
| 184 | + if (md.type == EFI_BOOT_SERVICES_DATA) | |
| 185 | + efi_mem_reserve(efi.mokvar_table, map_size_needed); | |
| 186 | + | |
| 184 | 187 | efi_mokvar_table_size = map_size_needed; |
| 185 | 188 | } |
| 186 | 189 | |
| @@ -62,9 +62,11 @@ int __init efi_tpm_eventlog_init(void) · 61 unmodified lines | ||
| 62 | 62 | tbl_size = sizeof(*log_tbl) + log_tbl->size; |
| 63 | 63 | memblock_reserve(efi.tpm_log, tbl_size); |
| 64 | 64 | |
| 65 | − if (efi.tpm_final_log == EFI_INVALID_TABLE_ADDR || | |
| 66 | − log_tbl->version != EFI_TCG2_EVENT_LOG_FORMAT_TCG_2) { | |
| 67 | − pr_warn(FW_BUG "TPM Final Events table missing or invalid\n"); | |
| 65 | + if (efi.tpm_final_log == EFI_INVALID_TABLE_ADDR) { | |
| 66 | + pr_info("TPM Final Events table not present\n"); | |
| 67 | + goto out; | |
| 68 | + } else if (log_tbl->version != EFI_TCG2_EVENT_LOG_FORMAT_TCG_2) { | |
| 69 | + pr_warn(FW_BUG "TPM Final Events table invalid\n"); | |
| 68 | 70 | goto out; |
| 69 | 71 | } |
| 70 | 72 | |
| @@ -953,6 +953,8 @@ static int fme_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) · 952 unmodified lines | ||
| 953 | 953 | return 0; |
| 954 | 954 | |
| 955 | 955 | priv->cpu = target; |
| 956 | + perf_pmu_migrate_context(&priv->pmu, cpu, target); | |
| 957 | + | |
| 956 | 958 | return 0; |
| 957 | 959 | } |
| 958 | 960 | |
| @@ -405,7 +405,7 @@ static int mpc8xxx_probe(struct platform_device *pdev) · 404 unmodified lines | ||
| 405 | 405 | |
| 406 | 406 | ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, |
| 407 | 407 | mpc8xxx_gpio_irq_cascade, |
| 408 | − IRQF_SHARED, "gpio-cascade", | |
| 408 | + IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", | |
| 409 | 409 | mpc8xxx_gc); |
| 410 | 410 | if (ret) { |
| 411 | 411 | dev_err(&pdev->dev, |
| @@ -238,8 +238,8 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) · 237 unmodified lines | ||
| 238 | 238 | struct resource *res; |
| 239 | 239 | int ret, irq; |
| 240 | 240 | |
| 241 | − irq = platform_get_irq(pdev, 0); | |
| 242 | − if (irq < 0) | |
| 241 | + irq = platform_get_irq_optional(pdev, 0); | |
| 242 | + if (irq < 0 && irq != -ENXIO) | |
| 243 | 243 | return irq; |
| 244 | 244 | |
| 245 | 245 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); |
| @@ -278,7 +278,7 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) · 32 unmodified lines | ||
| 278 | 278 | |
| 279 | 279 | pm_runtime_enable(&pdev->dev); |
| 280 | 280 | |
| 281 | − if (irq) { | |
| 281 | + if (irq > 0) { | |
| 282 | 282 | struct irq_chip *irq_chip = &gpio->irq_chip; |
| 283 | 283 | u8 irq_status; |
| 284 | 284 | |
| @@ -619,6 +619,13 @@ struct amdgpu_video_codec_info { · 618 unmodified lines | ||
| 619 | 619 | u32 max_level; |
| 620 | 620 | }; |
| 621 | 621 | |
| 622 | +#define codec_info_build(type, width, height, level) \ | |
| 623 | + .codec_type = type,\ | |
| 624 | + .max_width = width,\ | |
| 625 | + .max_height = height,\ | |
| 626 | + .max_pixels_per_frame = height * width,\ | |
| 627 | + .max_level = level, | |
| 628 | + | |
| 622 | 629 | struct amdgpu_video_codecs { |
| 623 | 630 | const u32 codec_count; |
| 624 | 631 | const struct amdgpu_video_codec_info *codec_array; |
| @@ -26,6 +26,7 @@ · 25 unmodified lines | ||
| 26 | 26 | #include <linux/slab.h> |
| 27 | 27 | #include <linux/power_supply.h> |
| 28 | 28 | #include <linux/pm_runtime.h> |
| 29 | +#include <linux/suspend.h> | |
| 29 | 30 | #include <acpi/video.h> |
| 30 | 31 | #include <acpi/actbl.h> |
| 31 | 32 | |
| @@ -1039,10 +1040,10 @@ void amdgpu_acpi_detect(void) · 1007 unmodified lines | ||
| 1039 | 1040 | */ |
| 1040 | 1041 | bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) |
| 1041 | 1042 | { |
| 1042 | −#if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE) | |
| 1043 | +#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_PM_SLEEP) | |
| 1043 | 1044 | if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) { |
| 1044 | 1045 | if (adev->flags & AMD_IS_APU) |
| 1045 | − return true; | |
| 1046 | + return pm_suspend_target_state == PM_SUSPEND_TO_IDLE; | |
| 1046 | 1047 | } |
| 1047 | 1048 | #endif |
| 1048 | 1049 | return false; |
| @@ -269,7 +269,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( · 268 unmodified lines | ||
| 269 | 269 | struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, |
| 270 | 270 | uint64_t *size); |
| 271 | 271 | int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( |
| 272 | − struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed); | |
| 272 | + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv); | |
| 273 | 273 | int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( |
| 274 | 274 | struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv); |
| 275 | 275 | int amdgpu_amdkfd_gpuvm_sync_memory( |
| @@ -1057,8 +1057,7 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem, · 1056 unmodified lines | ||
| 1057 | 1057 | |
| 1058 | 1058 | static int update_gpuvm_pte(struct kgd_mem *mem, |
| 1059 | 1059 | struct kfd_mem_attachment *entry, |
| 1060 | − struct amdgpu_sync *sync, | |
| 1061 | − bool *table_freed) | |
| 1060 | + struct amdgpu_sync *sync) | |
| 1062 | 1061 | { |
| 1063 | 1062 | struct amdgpu_bo_va *bo_va = entry->bo_va; |
| 1064 | 1063 | struct amdgpu_device *adev = entry->adev; |
| @@ -1069,7 +1068,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem, · 4 unmodified lines | ||
| 1069 | 1068 | return ret; |
| 1070 | 1069 | |
| 1071 | 1070 | /* Update the page tables */ |
| 1072 | − ret = amdgpu_vm_bo_update(adev, bo_va, false, table_freed); | |
| 1071 | + ret = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 1073 | 1072 | if (ret) { |
| 1074 | 1073 | pr_err("amdgpu_vm_bo_update failed\n"); |
| 1075 | 1074 | return ret; |
| @@ -1081,8 +1080,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem, · 5 unmodified lines | ||
| 1081 | 1080 | static int map_bo_to_gpuvm(struct kgd_mem *mem, |
| 1082 | 1081 | struct kfd_mem_attachment *entry, |
| 1083 | 1082 | struct amdgpu_sync *sync, |
| 1084 | − bool no_update_pte, | |
| 1085 | − bool *table_freed) | |
| 1083 | + bool no_update_pte) | |
| 1086 | 1084 | { |
| 1087 | 1085 | int ret; |
| 1088 | 1086 | |
| @@ -1099,7 +1097,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem, · 10 unmodified lines | ||
| 1099 | 1097 | if (no_update_pte) |
| 1100 | 1098 | return 0; |
| 1101 | 1099 | |
| 1102 | − ret = update_gpuvm_pte(mem, entry, sync, table_freed); | |
| 1100 | + ret = update_gpuvm_pte(mem, entry, sync); | |
| 1103 | 1101 | if (ret) { |
| 1104 | 1102 | pr_err("update_gpuvm_pte() failed\n"); |
| 1105 | 1103 | goto update_gpuvm_pte_failed; |
| @@ -1393,8 +1391,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 287 unmodified lines | ||
| 1393 | 1391 | domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; |
| 1394 | 1392 | alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; |
| 1395 | 1393 | alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? |
| 1396 | − AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : | |
| 1397 | − AMDGPU_GEM_CREATE_NO_CPU_ACCESS; | |
| 1394 | + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; | |
| 1398 | 1395 | } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { |
| 1399 | 1396 | domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; |
| 1400 | 1397 | alloc_flags = 0; |
| @@ -1597,8 +1594,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( · 196 unmodified lines | ||
| 1597 | 1594 | } |
| 1598 | 1595 | |
| 1599 | 1596 | int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( |
| 1600 | − struct kgd_dev *kgd, struct kgd_mem *mem, | |
| 1601 | − void *drm_priv, bool *table_freed) | |
| 1597 | + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv) | |
| 1602 | 1598 | { |
| 1603 | 1599 | struct amdgpu_device *adev = get_amdgpu_device(kgd); |
| 1604 | 1600 | struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); |
| @@ -1686,7 +1682,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( · 81 unmodified lines | ||
| 1686 | 1682 | entry->va, entry->va + bo_size, entry); |
| 1687 | 1683 | |
| 1688 | 1684 | ret = map_bo_to_gpuvm(mem, entry, ctx.sync, |
| 1689 | − is_invalid_userptr, table_freed); | |
| 1685 | + is_invalid_userptr); | |
| 1690 | 1686 | if (ret) { |
| 1691 | 1687 | pr_err("Failed to map bo to gpuvm\n"); |
| 1692 | 1688 | goto out_unreserve; |
| @@ -2136,7 +2132,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) · 443 unmodified lines | ||
| 2136 | 2132 | continue; |
| 2137 | 2133 | |
| 2138 | 2134 | kfd_mem_dmaunmap_attachment(mem, attachment); |
| 2139 | − ret = update_gpuvm_pte(mem, attachment, &sync, NULL); | |
| 2135 | + ret = update_gpuvm_pte(mem, attachment, &sync); | |
| 2140 | 2136 | if (ret) { |
| 2141 | 2137 | pr_err("%s: update PTE failed\n", __func__); |
| 2142 | 2138 | /* make sure this gets validated again */ |
| @@ -2342,7 +2338,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) · 199 unmodified lines | ||
| 2342 | 2338 | continue; |
| 2343 | 2339 | |
| 2344 | 2340 | kfd_mem_dmaunmap_attachment(mem, attachment); |
| 2345 | − ret = update_gpuvm_pte(mem, attachment, &sync_obj, NULL); | |
| 2341 | + ret = update_gpuvm_pte(mem, attachment, &sync_obj); | |
| 2346 | 2342 | if (ret) { |
| 2347 | 2343 | pr_debug("Memory eviction: update PTE failed. Try again\n"); |
| 2348 | 2344 | goto validate_map_fail; |
| @@ -468,6 +468,46 @@ bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *ade · 467 unmodified lines | ||
| 468 | 468 | return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false; |
| 469 | 469 | } |
| 470 | 470 | |
| 471 | +/* | |
| 472 | + * Helper function to query RAS EEPROM address | |
| 473 | + * | |
| 474 | + * @adev: amdgpu_device pointer | |
| 475 | + * | |
| 476 | + * Return true if vbios supports ras rom address reporting | |
| 477 | + */ | |
| 478 | +bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t* i2c_address) | |
| 479 | +{ | |
| 480 | + struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
| 481 | + int index; | |
| 482 | + u16 data_offset, size; | |
| 483 | + union firmware_info *firmware_info; | |
| 484 | + u8 frev, crev; | |
| 485 | + | |
| 486 | + if (i2c_address == NULL) | |
| 487 | + return false; | |
| 488 | + | |
| 489 | + *i2c_address = 0; | |
| 490 | + | |
| 491 | + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, | |
| 492 | + firmwareinfo); | |
| 493 | + | |
| 494 | + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, | |
| 495 | + index, &size, &frev, &crev, &data_offset)) { | |
| 496 | + /* support firmware_info 3.4 + */ | |
| 497 | + if ((frev == 3 && crev >=4) || (frev > 3)) { | |
| 498 | + firmware_info = (union firmware_info *) | |
| 499 | + (mode_info->atom_context->bios + data_offset); | |
| 500 | + *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr; | |
| 501 | + } | |
| 502 | + } | |
| 503 | + | |
| 504 | + if (*i2c_address != 0) | |
| 505 | + return true; | |
| 506 | + | |
| 507 | + return false; | |
| 508 | +} | |
| 509 | + | |
| 510 | + | |
| 471 | 511 | union smu_info { |
| 472 | 512 | struct atom_smu_info_v3_1 v31; |
| 473 | 513 | }; |
| @@ -36,6 +36,7 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev); · 35 unmodified lines | ||
| 36 | 36 | int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev); |
| 37 | 37 | bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev); |
| 38 | 38 | bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev); |
| 39 | +bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t* i2c_address); | |
| 39 | 40 | bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev); |
| 40 | 41 | bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev); |
| 41 | 42 | int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev); |
| @@ -781,7 +781,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) · 780 unmodified lines | ||
| 781 | 781 | if (r) |
| 782 | 782 | return r; |
| 783 | 783 | |
| 784 | − r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL); | |
| 784 | + r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); | |
| 785 | 785 | if (r) |
| 786 | 786 | return r; |
| 787 | 787 | |
| @@ -792,7 +792,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) · 4 unmodified lines | ||
| 792 | 792 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
| 793 | 793 | bo_va = fpriv->csa_va; |
| 794 | 794 | BUG_ON(!bo_va); |
| 795 | − r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); | |
| 795 | + r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 796 | 796 | if (r) |
| 797 | 797 | return r; |
| 798 | 798 | |
| @@ -811,7 +811,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) · 12 unmodified lines | ||
| 811 | 811 | if (bo_va == NULL) |
| 812 | 812 | continue; |
| 813 | 813 | |
| 814 | − r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); | |
| 814 | + r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 815 | 815 | if (r) |
| 816 | 816 | return r; |
| 817 | 817 | |
| @@ -3504,13 +3504,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 3503 unmodified lines | ||
| 3504 | 3504 | r = amdgpu_device_get_job_timeout_settings(adev); |
| 3505 | 3505 | if (r) { |
| 3506 | 3506 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); |
| 3507 | − goto failed_unmap; | |
| 3507 | + return r; | |
| 3508 | 3508 | } |
| 3509 | 3509 | |
| 3510 | 3510 | /* early init functions */ |
| 3511 | 3511 | r = amdgpu_device_ip_early_init(adev); |
| 3512 | 3512 | if (r) |
| 3513 | − goto failed_unmap; | |
| 3513 | + return r; | |
| 3514 | 3514 | |
| 3515 | 3515 | /* doorbell bar mapping and doorbell index init*/ |
| 3516 | 3516 | amdgpu_device_doorbell_init(adev); |
| @@ -3736,10 +3736,6 @@ release_ras_con: · 219 unmodified lines | ||
| 3736 | 3736 | failed: |
| 3737 | 3737 | amdgpu_vf_error_trans_all(adev); |
| 3738 | 3738 | |
| 3739 | −failed_unmap: | |
| 3740 | − iounmap(adev->rmmio); | |
| 3741 | − adev->rmmio = NULL; | |
| 3742 | − | |
| 3743 | 3739 | return r; |
| 3744 | 3740 | } |
| 3745 | 3741 | |
| @@ -299,6 +299,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) · 298 unmodified lines | ||
| 299 | 299 | ip->major, ip->minor, |
| 300 | 300 | ip->revision); |
| 301 | 301 | |
| 302 | + if (le16_to_cpu(ip->hw_id) == VCN_HWID) | |
| 303 | + adev->vcn.num_vcn_inst++; | |
| 304 | + | |
| 302 | 305 | for (k = 0; k < num_base_address; k++) { |
| 303 | 306 | /* |
| 304 | 307 | * convert the endianness of base addresses in place, |
| @@ -385,7 +388,7 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) · 80 unmodified lines | ||
| 385 | 388 | { |
| 386 | 389 | struct binary_header *bhdr; |
| 387 | 390 | struct harvest_table *harvest_info; |
| 388 | − int i; | |
| 391 | + int i, vcn_harvest_count = 0; | |
| 389 | 392 | |
| 390 | 393 | bhdr = (struct binary_header *)adev->mman.discovery_bin; |
| 391 | 394 | harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + |
| @@ -397,8 +400,7 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) · 5 unmodified lines | ||
| 397 | 400 | |
| 398 | 401 | switch (le32_to_cpu(harvest_info->list[i].hw_id)) { |
| 399 | 402 | case VCN_HWID: |
| 400 | − adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; | |
| 401 | − adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; | |
| 403 | + vcn_harvest_count++; | |
| 402 | 404 | break; |
| 403 | 405 | case DMU_HWID: |
| 404 | 406 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; |
| @@ -407,6 +409,10 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) · 2 unmodified lines | ||
| 407 | 409 | break; |
| 408 | 410 | } |
| 409 | 411 | } |
| 412 | + if (vcn_harvest_count == adev->vcn.num_vcn_inst) { | |
| 413 | + adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; | |
| 414 | + adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; | |
| 415 | + } | |
| 410 | 416 | } |
| 411 | 417 | |
| 412 | 418 | int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) |
| @@ -1168,6 +1168,7 @@ static const struct pci_device_id pciidlist[] = { · 1167 unmodified lines | ||
| 1168 | 1168 | {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
| 1169 | 1169 | |
| 1170 | 1170 | /* Renoir */ |
| 1171 | + {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, | |
| 1171 | 1172 | {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1172 | 1173 | {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1173 | 1174 | {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| @@ -1189,6 +1190,10 @@ static const struct pci_device_id pciidlist[] = { · 15 unmodified lines | ||
| 1189 | 1190 | /* Van Gogh */ |
| 1190 | 1191 | {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, |
| 1191 | 1192 | |
| 1193 | + /* Yellow Carp */ | |
| 1194 | + {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, | |
| 1195 | + {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, | |
| 1196 | + | |
| 1192 | 1197 | /* Navy_Flounder */ |
| 1193 | 1198 | {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1194 | 1199 | {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, |
| @@ -1208,6 +1213,13 @@ static const struct pci_device_id pciidlist[] = { · 13 unmodified lines | ||
| 1208 | 1213 | {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, |
| 1209 | 1214 | {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, |
| 1210 | 1215 | |
| 1216 | + /* BEIGE_GOBY */ | |
| 1217 | + {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, | |
| 1218 | + {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, | |
| 1219 | + {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, | |
| 1220 | + {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, | |
| 1221 | + {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, | |
| 1222 | + | |
| 1211 | 1223 | {0, 0, 0} |
| 1212 | 1224 | }; |
| 1213 | 1225 | |
| @@ -1559,6 +1571,8 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) · 345 unmodified lines | ||
| 1559 | 1571 | pci_ignore_hotplug(pdev); |
| 1560 | 1572 | pci_set_power_state(pdev, PCI_D3cold); |
| 1561 | 1573 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
| 1574 | + } else if (amdgpu_device_supports_boco(drm_dev)) { | |
| 1575 | + /* nothing to do */ | |
| 1562 | 1576 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
| 1563 | 1577 | amdgpu_device_baco_enter(drm_dev); |
| 1564 | 1578 | } |
| @@ -255,6 +255,15 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str · 254 unmodified lines | ||
| 255 | 255 | if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) |
| 256 | 256 | return -EPERM; |
| 257 | 257 | |
| 258 | + /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings | |
| 259 | + * for debugger access to invisible VRAM. Should have used MAP_SHARED | |
| 260 | + * instead. Clearing VM_MAYWRITE prevents the mapping from ever | |
| 261 | + * becoming writable and makes is_cow_mapping(vm_flags) false. | |
| 262 | + */ | |
| 263 | + if (is_cow_mapping(vma->vm_flags) && | |
| 264 | + !(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC))) | |
| 265 | + vma->vm_flags &= ~VM_MAYWRITE; | |
| 266 | + | |
| 258 | 267 | return drm_gem_ttm_mmap(obj, vma); |
| 259 | 268 | } |
| 260 | 269 | |
| @@ -612,7 +621,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, · 351 unmodified lines | ||
| 612 | 621 | |
| 613 | 622 | if (operation == AMDGPU_VA_OP_MAP || |
| 614 | 623 | operation == AMDGPU_VA_OP_REPLACE) { |
| 615 | − r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); | |
| 624 | + r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 616 | 625 | if (r) |
| 617 | 626 | goto error; |
| 618 | 627 | } |
| @@ -278,6 +278,21 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev) · 277 unmodified lines | ||
| 278 | 278 | return true; |
| 279 | 279 | } |
| 280 | 280 | |
| 281 | +static void amdgpu_restore_msix(struct amdgpu_device *adev) | |
| 282 | +{ | |
| 283 | + u16 ctrl; | |
| 284 | + | |
| 285 | + pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
| 286 | + if (!(ctrl & PCI_MSIX_FLAGS_ENABLE)) | |
| 287 | + return; | |
| 288 | + | |
| 289 | + /* VF FLR */ | |
| 290 | + ctrl &= ~PCI_MSIX_FLAGS_ENABLE; | |
| 291 | + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
| 292 | + ctrl |= PCI_MSIX_FLAGS_ENABLE; | |
| 293 | + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
| 294 | +} | |
| 295 | + | |
| 281 | 296 | /** |
| 282 | 297 | * amdgpu_irq_init - initialize interrupt handling |
| 283 | 298 | * |
| @@ -569,6 +584,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) · 285 unmodified lines | ||
| 569 | 584 | { |
| 570 | 585 | int i, j, k; |
| 571 | 586 | |
| 587 | + if (amdgpu_sriov_vf(adev)) | |
| 588 | + amdgpu_restore_msix(adev); | |
| 589 | + | |
| 572 | 590 | for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { |
| 573 | 591 | if (!adev->irq.client[i].sources) |
| 574 | 592 | continue; |
| @@ -809,7 +809,7 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, · 808 unmodified lines | ||
| 809 | 809 | |
| 810 | 810 | /* query/inject/cure begin */ |
| 811 | 811 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
| 812 | − struct ras_query_if *info) | |
| 812 | + struct ras_query_if *info) | |
| 813 | 813 | { |
| 814 | 814 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); |
| 815 | 815 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
| @@ -1043,17 +1043,32 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 227 unmodified lines | ||
| 1043 | 1043 | return ret; |
| 1044 | 1044 | } |
| 1045 | 1045 | |
| 1046 | −/* get the total error counts on all IPs */ | |
| 1047 | −void amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
| 1048 | − unsigned long *ce_count, | |
| 1049 | − unsigned long *ue_count) | |
| 1046 | +/** | |
| 1047 | + * amdgpu_ras_query_error_count -- Get error counts of all IPs | |
| 1048 | + * adev: pointer to AMD GPU device | |
| 1049 | + * ce_count: pointer to an integer to be set to the count of correctible errors. | |
| 1050 | + * ue_count: pointer to an integer to be set to the count of uncorrectible | |
| 1051 | + * errors. | |
| 1052 | + * | |
| 1053 | + * If set, @ce_count or @ue_count, count and return the corresponding | |
| 1054 | + * error counts in those integer pointers. Return 0 if the device | |
| 1055 | + * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. | |
| 1056 | + */ | |
| 1057 | +int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
| 1058 | + unsigned long *ce_count, | |
| 1059 | + unsigned long *ue_count) | |
| 1050 | 1060 | { |
| 1051 | 1061 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
| 1052 | 1062 | struct ras_manager *obj; |
| 1053 | 1063 | unsigned long ce, ue; |
| 1054 | 1064 | |
| 1055 | 1065 | if (!adev->ras_enabled || !con) |
| 1056 | − return; | |
| 1066 | + return -EOPNOTSUPP; | |
| 1067 | + | |
| 1068 | + /* Don't count since no reporting. | |
| 1069 | + */ | |
| 1070 | + if (!ce_count && !ue_count) | |
| 1071 | + return 0; | |
| 1057 | 1072 | |
| 1058 | 1073 | ce = 0; |
| 1059 | 1074 | ue = 0; |
| @@ -1061,9 +1076,11 @@ void amdgpu_ras_query_error_count(struct amdgpu_device *adev, · 1 unmodified line | ||
| 1061 | 1076 | struct ras_query_if info = { |
| 1062 | 1077 | .head = obj->head, |
| 1063 | 1078 | }; |
| 1079 | + int res; | |
| 1064 | 1080 | |
| 1065 | − if (amdgpu_ras_query_error_status(adev, &info)) | |
| 1066 | − return; | |
| 1081 | + res = amdgpu_ras_query_error_status(adev, &info); | |
| 1082 | + if (res) | |
| 1083 | + return res; | |
| 1067 | 1084 | |
| 1068 | 1085 | ce += info.ce_count; |
| 1069 | 1086 | ue += info.ue_count; |
| @@ -1074,6 +1091,8 @@ void amdgpu_ras_query_error_count(struct amdgpu_device *adev, · 4 unmodified lines | ||
| 1074 | 1091 | |
| 1075 | 1092 | if (ue_count) |
| 1076 | 1093 | *ue_count = ue; |
| 1094 | + | |
| 1095 | + return 0; | |
| 1077 | 1096 | } |
| 1078 | 1097 | /* query/inject/cure end */ |
| 1079 | 1098 | |
| @@ -2137,9 +2156,10 @@ static void amdgpu_ras_counte_dw(struct work_struct *work) · 1057 unmodified lines | ||
| 2137 | 2156 | |
| 2138 | 2157 | /* Cache new values. |
| 2139 | 2158 | */ |
| 2140 | − amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); | |
| 2141 | − atomic_set(&con->ras_ce_count, ce_count); | |
| 2142 | − atomic_set(&con->ras_ue_count, ue_count); | |
| 2159 | + if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) { | |
| 2160 | + atomic_set(&con->ras_ce_count, ce_count); | |
| 2161 | + atomic_set(&con->ras_ue_count, ue_count); | |
| 2162 | + } | |
| 2143 | 2163 | |
| 2144 | 2164 | pm_runtime_mark_last_busy(dev->dev); |
| 2145 | 2165 | Out: |
| @@ -2312,9 +2332,10 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev, · 166 unmodified lines | ||
| 2312 | 2332 | |
| 2313 | 2333 | /* Those are the cached values at init. |
| 2314 | 2334 | */ |
| 2315 | − amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); | |
| 2316 | − atomic_set(&con->ras_ce_count, ce_count); | |
| 2317 | − atomic_set(&con->ras_ue_count, ue_count); | |
| 2335 | + if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) { | |
| 2336 | + atomic_set(&con->ras_ce_count, ce_count); | |
| 2337 | + atomic_set(&con->ras_ue_count, ue_count); | |
| 2338 | + } | |
| 2318 | 2339 | |
| 2319 | 2340 | return 0; |
| 2320 | 2341 | cleanup: |
| @@ -490,9 +490,9 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, · 489 unmodified lines | ||
| 490 | 490 | void amdgpu_ras_resume(struct amdgpu_device *adev); |
| 491 | 491 | void amdgpu_ras_suspend(struct amdgpu_device *adev); |
| 492 | 492 | |
| 493 | −void amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
| 494 | − unsigned long *ce_count, | |
| 495 | − unsigned long *ue_count); | |
| 493 | +int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
| 494 | + unsigned long *ce_count, | |
| 495 | + unsigned long *ue_count); | |
| 496 | 496 | |
| 497 | 497 | /* error handling functions */ |
| 498 | 498 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, |
| @@ -26,6 +26,7 @@ · 25 unmodified lines | ||
| 26 | 26 | #include "amdgpu_ras.h" |
| 27 | 27 | #include <linux/bits.h> |
| 28 | 28 | #include "atom.h" |
| 29 | +#include "amdgpu_atomfirmware.h" | |
| 29 | 30 | |
| 30 | 31 | #define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0 |
| 31 | 32 | #define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8 |
| @@ -96,6 +97,9 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, · 64 unmodified lines | ||
| 96 | 97 | if (!i2c_addr) |
| 97 | 98 | return false; |
| 98 | 99 | |
| 100 | + if (amdgpu_atomfirmware_ras_rom_addr(adev, (uint8_t*)i2c_addr)) | |
| 101 | + return true; | |
| 102 | + | |
| 99 | 103 | switch (adev->asic_type) { |
| 100 | 104 | case CHIP_VEGA20: |
| 101 | 105 | *i2c_addr = EEPROM_I2C_TARGET_ADDR_VEGA20; |
| @@ -54,11 +54,12 @@ static inline void amdgpu_res_first(struct ttm_resource *res, · 53 unmodified lines | ||
| 54 | 54 | { |
| 55 | 55 | struct drm_mm_node *node; |
| 56 | 56 | |
| 57 | − if (!res) { | |
| 57 | + if (!res || res->mem_type == TTM_PL_SYSTEM) { | |
| 58 | 58 | cur->start = start; |
| 59 | 59 | cur->size = size; |
| 60 | 60 | cur->remaining = size; |
| 61 | 61 | cur->node = NULL; |
| 62 | + WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT); | |
| 62 | 63 | return; |
| 63 | 64 | } |
| 64 | 65 | |
| @@ -1758,7 +1758,7 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, · 1757 unmodified lines | ||
| 1758 | 1758 | r = vm->update_funcs->commit(¶ms, fence); |
| 1759 | 1759 | |
| 1760 | 1760 | if (table_freed) |
| 1761 | − *table_freed = *table_freed || params.table_freed; | |
| 1761 | + *table_freed = params.table_freed; | |
| 1762 | 1762 | |
| 1763 | 1763 | error_unlock: |
| 1764 | 1764 | amdgpu_vm_eviction_unlock(vm); |
| @@ -1816,7 +1816,6 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, · 51 unmodified lines | ||
| 1816 | 1816 | * @adev: amdgpu_device pointer |
| 1817 | 1817 | * @bo_va: requested BO and VM object |
| 1818 | 1818 | * @clear: if true clear the entries |
| 1819 | − * @table_freed: return true if page table is freed | |
| 1820 | 1819 | * |
| 1821 | 1820 | * Fill in the page table entries for @bo_va. |
| 1822 | 1821 | * |
| @@ -1824,7 +1823,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, · 1 unmodified line | ||
| 1824 | 1823 | * 0 for success, -EINVAL for failure. |
| 1825 | 1824 | */ |
| 1826 | 1825 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, |
| 1827 | − bool clear, bool *table_freed) | |
| 1826 | + bool clear) | |
| 1828 | 1827 | { |
| 1829 | 1828 | struct amdgpu_bo *bo = bo_va->base.bo; |
| 1830 | 1829 | struct amdgpu_vm *vm = bo_va->base.vm; |
| @@ -1903,7 +1902,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, · 72 unmodified lines | ||
| 1903 | 1902 | resv, mapping->start, |
| 1904 | 1903 | mapping->last, update_flags, |
| 1905 | 1904 | mapping->offset, mem, |
| 1906 | − pages_addr, last_update, table_freed); | |
| 1905 | + pages_addr, last_update, NULL); | |
| 1907 | 1906 | if (r) |
| 1908 | 1907 | return r; |
| 1909 | 1908 | } |
| @@ -2155,7 +2154,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, · 245 unmodified lines | ||
| 2155 | 2154 | |
| 2156 | 2155 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { |
| 2157 | 2156 | /* Per VM BOs never need to bo cleared in the page tables */ |
| 2158 | − r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); | |
| 2157 | + r = amdgpu_vm_bo_update(adev, bo_va, false); | |
| 2159 | 2158 | if (r) |
| 2160 | 2159 | return r; |
| 2161 | 2160 | } |
| @@ -2174,7 +2173,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, · 12 unmodified lines | ||
| 2174 | 2173 | else |
| 2175 | 2174 | clear = true; |
| 2176 | 2175 | |
| 2177 | − r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL); | |
| 2176 | + r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
| 2178 | 2177 | if (r) |
| 2179 | 2178 | return r; |
| 2180 | 2179 | |
| @@ -406,7 +406,7 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, · 405 unmodified lines | ||
| 406 | 406 | struct dma_fence **fence, bool *free_table); |
| 407 | 407 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, |
| 408 | 408 | struct amdgpu_bo_va *bo_va, |
| 409 | − bool clear, bool *table_freed); | |
| 409 | + bool clear); | |
| 410 | 410 | bool amdgpu_vm_evictable(struct amdgpu_bo *bo); |
| 411 | 411 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, |
| 412 | 412 | struct amdgpu_bo *bo, bool evicted); |
| @@ -766,7 +766,7 @@ static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = { · 765 unmodified lines | ||
| 766 | 766 | |
| 767 | 767 | static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev) |
| 768 | 768 | { |
| 769 | − adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1; | |
| 769 | + adev->crtc_irq.num_types = adev->mode_info.num_crtc; | |
| 770 | 770 | adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs; |
| 771 | 771 | } |
| 772 | 772 | |
| @@ -3300,6 +3300,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] = · 3299 unmodified lines | ||
| 3300 | 3300 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), |
| 3301 | 3301 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), |
| 3302 | 3302 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), |
| 3303 | + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), | |
| 3303 | 3304 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
| 3304 | 3305 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) |
| 3305 | 3306 | }; |
| @@ -3379,6 +3380,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = · 73 unmodified lines | ||
| 3379 | 3380 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), |
| 3380 | 3381 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), |
| 3381 | 3382 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), |
| 3383 | + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), | |
| 3382 | 3384 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
| 3383 | 3385 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), |
| 3384 | 3386 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), |
| @@ -3445,6 +3447,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = · 60 unmodified lines | ||
| 3445 | 3447 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), |
| 3446 | 3448 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), |
| 3447 | 3449 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), |
| 3450 | + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), | |
| 3448 | 3451 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), |
| 3449 | 3452 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), |
| 3450 | 3453 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) |
| @@ -1295,6 +1295,16 @@ static bool is_raven_kicker(struct amdgpu_device *adev) · 1294 unmodified lines | ||
| 1295 | 1295 | return false; |
| 1296 | 1296 | } |
| 1297 | 1297 | |
| 1298 | +static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) | |
| 1299 | +{ | |
| 1300 | + if ((adev->asic_type == CHIP_RENOIR) && | |
| 1301 | + (adev->gfx.me_fw_version >= 0x000000a5) && | |
| 1302 | + (adev->gfx.me_feature_version >= 52)) | |
| 1303 | + return true; | |
| 1304 | + else | |
| 1305 | + return false; | |
| 1306 | +} | |
| 1307 | + | |
| 1298 | 1308 | static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) |
| 1299 | 1309 | { |
| 1300 | 1310 | if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) |
| @@ -3675,7 +3685,16 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) · 2374 unmodified lines | ||
| 3675 | 3685 | if (ring->use_doorbell) { |
| 3676 | 3686 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, |
| 3677 | 3687 | (adev->doorbell_index.kiq * 2) << 2); |
| 3678 | − WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, | |
| 3688 | + /* If GC has entered CGPG, ringing doorbell > first page | |
| 3689 | + * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to | |
| 3690 | + * workaround this issue. And this change has to align with firmware | |
| 3691 | + * update. | |
| 3692 | + */ | |
| 3693 | + if (check_if_enlarge_doorbell_range(adev)) | |
| 3694 | + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, | |
| 3695 | + (adev->doorbell.size - 4)); | |
| 3696 | + else | |
| 3697 | + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, | |
| 3679 | 3698 | (adev->doorbell_index.userqueue_end * 2) << 2); |
| 3680 | 3699 | } |
| 3681 | 3700 | |
| @@ -252,7 +252,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) · 251 unmodified lines | ||
| 252 | 252 | * otherwise the mailbox msg will be ruined/reseted by |
| 253 | 253 | * the VF FLR. |
| 254 | 254 | */ |
| 255 | − if (!down_read_trylock(&adev->reset_sem)) | |
| 255 | + if (!down_write_trylock(&adev->reset_sem)) | |
| 256 | 256 | return; |
| 257 | 257 | |
| 258 | 258 | amdgpu_virt_fini_data_exchange(adev); |
| @@ -268,7 +268,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) · 9 unmodified lines | ||
| 268 | 268 | |
| 269 | 269 | flr_done: |
| 270 | 270 | atomic_set(&adev->in_gpu_reset, 0); |
| 271 | − up_read(&adev->reset_sem); | |
| 271 | + up_write(&adev->reset_sem); | |
| 272 | 272 | |
| 273 | 273 | /* Trigger recovery for world switch failure if no TDR */ |
| 274 | 274 | if (amdgpu_device_should_recover_gpu(adev) |
| @@ -273,7 +273,7 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work) · 272 unmodified lines | ||
| 273 | 273 | * otherwise the mailbox msg will be ruined/reseted by |
| 274 | 274 | * the VF FLR. |
| 275 | 275 | */ |
| 276 | − if (!down_read_trylock(&adev->reset_sem)) | |
| 276 | + if (!down_write_trylock(&adev->reset_sem)) | |
| 277 | 277 | return; |
| 278 | 278 | |
| 279 | 279 | amdgpu_virt_fini_data_exchange(adev); |
| @@ -289,7 +289,7 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work) · 9 unmodified lines | ||
| 289 | 289 | |
| 290 | 290 | flr_done: |
| 291 | 291 | atomic_set(&adev->in_gpu_reset, 0); |
| 292 | − up_read(&adev->reset_sem); | |
| 292 | + up_write(&adev->reset_sem); | |
| 293 | 293 | |
| 294 | 294 | /* Trigger recovery for world switch failure if no TDR */ |
| 295 | 295 | if (amdgpu_device_should_recover_gpu(adev) |
| @@ -64,32 +64,13 @@ · 63 unmodified lines | ||
| 64 | 64 | #include "smuio_v11_0.h" |
| 65 | 65 | #include "smuio_v11_0_6.h" |
| 66 | 66 | |
| 67 | −#define codec_info_build(type, width, height, level) \ | |
| 68 | − .codec_type = type,\ | |
| 69 | − .max_width = width,\ | |
| 70 | − .max_height = height,\ | |
| 71 | − .max_pixels_per_frame = height * width,\ | |
| 72 | − .max_level = level, | |
| 73 | − | |
| 74 | 67 | static const struct amd_ip_funcs nv_common_ip_funcs; |
| 75 | 68 | |
| 76 | 69 | /* Navi */ |
| 77 | 70 | static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = |
| 78 | 71 | { |
| 79 | − { | |
| 80 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 81 | − .max_width = 4096, | |
| 82 | − .max_height = 2304, | |
| 83 | − .max_pixels_per_frame = 4096 * 2304, | |
| 84 | − .max_level = 0, | |
| 85 | − }, | |
| 86 | − { | |
| 87 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 88 | − .max_width = 4096, | |
| 89 | − .max_height = 2304, | |
| 90 | − .max_pixels_per_frame = 4096 * 2304, | |
| 91 | − .max_level = 0, | |
| 92 | − }, | |
| 72 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, | |
| 73 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, | |
| 93 | 74 | }; |
| 94 | 75 | |
| 95 | 76 | static const struct amdgpu_video_codecs nv_video_codecs_encode = |
| @@ -101,55 +82,13 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = · 5 unmodified lines | ||
| 101 | 82 | /* Navi1x */ |
| 102 | 83 | static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = |
| 103 | 84 | { |
| 104 | − { | |
| 105 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
| 106 | − .max_width = 4096, | |
| 107 | − .max_height = 4096, | |
| 108 | − .max_pixels_per_frame = 4096 * 4096, | |
| 109 | − .max_level = 3, | |
| 110 | − }, | |
| 111 | − { | |
| 112 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
| 113 | − .max_width = 4096, | |
| 114 | − .max_height = 4096, | |
| 115 | − .max_pixels_per_frame = 4096 * 4096, | |
| 116 | − .max_level = 5, | |
| 117 | − }, | |
| 118 | − { | |
| 119 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 120 | − .max_width = 4096, | |
| 121 | − .max_height = 4096, | |
| 122 | − .max_pixels_per_frame = 4096 * 4096, | |
| 123 | − .max_level = 52, | |
| 124 | − }, | |
| 125 | − { | |
| 126 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
| 127 | − .max_width = 4096, | |
| 128 | − .max_height = 4096, | |
| 129 | − .max_pixels_per_frame = 4096 * 4096, | |
| 130 | − .max_level = 4, | |
| 131 | − }, | |
| 132 | − { | |
| 133 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 134 | − .max_width = 8192, | |
| 135 | − .max_height = 4352, | |
| 136 | − .max_pixels_per_frame = 8192 * 4352, | |
| 137 | − .max_level = 186, | |
| 138 | − }, | |
| 139 | − { | |
| 140 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
| 141 | − .max_width = 4096, | |
| 142 | − .max_height = 4096, | |
| 143 | − .max_pixels_per_frame = 4096 * 4096, | |
| 144 | − .max_level = 0, | |
| 145 | − }, | |
| 146 | − { | |
| 147 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, | |
| 148 | − .max_width = 8192, | |
| 149 | − .max_height = 4352, | |
| 150 | − .max_pixels_per_frame = 8192 * 4352, | |
| 151 | − .max_level = 0, | |
| 152 | − }, | |
| 85 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, | |
| 86 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, | |
| 87 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 88 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, | |
| 89 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, | |
| 90 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 91 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, | |
| 153 | 92 | }; |
| 154 | 93 | |
| 155 | 94 | static const struct amdgpu_video_codecs nv_video_codecs_decode = |
| @@ -161,62 +100,14 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = · 5 unmodified lines | ||
| 161 | 100 | /* Sienna Cichlid */ |
| 162 | 101 | static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = |
| 163 | 102 | { |
| 164 | − { | |
| 165 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
| 166 | − .max_width = 4096, | |
| 167 | − .max_height = 4096, | |
| 168 | − .max_pixels_per_frame = 4096 * 4096, | |
| 169 | − .max_level = 3, | |
| 170 | − }, | |
| 171 | − { | |
| 172 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
| 173 | − .max_width = 4096, | |
| 174 | − .max_height = 4096, | |
| 175 | − .max_pixels_per_frame = 4096 * 4096, | |
| 176 | − .max_level = 5, | |
| 177 | − }, | |
| 178 | − { | |
| 179 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 180 | − .max_width = 4096, | |
| 181 | − .max_height = 4096, | |
| 182 | − .max_pixels_per_frame = 4096 * 4096, | |
| 183 | − .max_level = 52, | |
| 184 | − }, | |
| 185 | − { | |
| 186 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
| 187 | − .max_width = 4096, | |
| 188 | − .max_height = 4096, | |
| 189 | − .max_pixels_per_frame = 4096 * 4096, | |
| 190 | − .max_level = 4, | |
| 191 | − }, | |
| 192 | − { | |
| 193 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 194 | − .max_width = 8192, | |
| 195 | − .max_height = 4352, | |
| 196 | − .max_pixels_per_frame = 8192 * 4352, | |
| 197 | − .max_level = 186, | |
| 198 | − }, | |
| 199 | − { | |
| 200 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
| 201 | − .max_width = 4096, | |
| 202 | − .max_height = 4096, | |
| 203 | − .max_pixels_per_frame = 4096 * 4096, | |
| 204 | − .max_level = 0, | |
| 205 | − }, | |
| 206 | − { | |
| 207 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, | |
| 208 | − .max_width = 8192, | |
| 209 | − .max_height = 4352, | |
| 210 | − .max_pixels_per_frame = 8192 * 4352, | |
| 211 | − .max_level = 0, | |
| 212 | − }, | |
| 213 | − { | |
| 214 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, | |
| 215 | − .max_width = 8192, | |
| 216 | − .max_height = 4352, | |
| 217 | − .max_pixels_per_frame = 8192 * 4352, | |
| 218 | − .max_level = 0, | |
| 219 | − }, | |
| 103 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, | |
| 104 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, | |
| 105 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 106 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, | |
| 107 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, | |
| 108 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 109 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, | |
| 110 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, | |
| 220 | 111 | }; |
| 221 | 112 | |
| 222 | 113 | static const struct amdgpu_video_codecs sc_video_codecs_decode = |
| @@ -228,80 +119,20 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode = · 5 unmodified lines | ||
| 228 | 119 | /* SRIOV Sienna Cichlid, not const since data is controlled by host */ |
| 229 | 120 | static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = |
| 230 | 121 | { |
| 231 | − { | |
| 232 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 233 | − .max_width = 4096, | |
| 234 | − .max_height = 2304, | |
| 235 | − .max_pixels_per_frame = 4096 * 2304, | |
| 236 | − .max_level = 0, | |
| 237 | − }, | |
| 238 | − { | |
| 239 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 240 | − .max_width = 4096, | |
| 241 | − .max_height = 2304, | |
| 242 | − .max_pixels_per_frame = 4096 * 2304, | |
| 243 | − .max_level = 0, | |
| 244 | − }, | |
| 122 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, | |
| 123 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, | |
| 245 | 124 | }; |
| 246 | 125 | |
| 247 | 126 | static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = |
| 248 | 127 | { |
| 249 | − { | |
| 250 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
| 251 | − .max_width = 4096, | |
| 252 | − .max_height = 4096, | |
| 253 | − .max_pixels_per_frame = 4096 * 4096, | |
| 254 | − .max_level = 3, | |
| 255 | − }, | |
| 256 | − { | |
| 257 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
| 258 | − .max_width = 4096, | |
| 259 | − .max_height = 4096, | |
| 260 | − .max_pixels_per_frame = 4096 * 4096, | |
| 261 | − .max_level = 5, | |
| 262 | − }, | |
| 263 | − { | |
| 264 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 265 | − .max_width = 4096, | |
| 266 | − .max_height = 4096, | |
| 267 | − .max_pixels_per_frame = 4096 * 4096, | |
| 268 | − .max_level = 52, | |
| 269 | − }, | |
| 270 | − { | |
| 271 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
| 272 | − .max_width = 4096, | |
| 273 | − .max_height = 4096, | |
| 274 | − .max_pixels_per_frame = 4096 * 4096, | |
| 275 | − .max_level = 4, | |
| 276 | − }, | |
| 277 | − { | |
| 278 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 279 | − .max_width = 8192, | |
| 280 | − .max_height = 4352, | |
| 281 | − .max_pixels_per_frame = 8192 * 4352, | |
| 282 | − .max_level = 186, | |
| 283 | − }, | |
| 284 | − { | |
| 285 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
| 286 | − .max_width = 4096, | |
| 287 | − .max_height = 4096, | |
| 288 | − .max_pixels_per_frame = 4096 * 4096, | |
| 289 | − .max_level = 0, | |
| 290 | − }, | |
| 291 | − { | |
| 292 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, | |
| 293 | − .max_width = 8192, | |
| 294 | − .max_height = 4352, | |
| 295 | − .max_pixels_per_frame = 8192 * 4352, | |
| 296 | − .max_level = 0, | |
| 297 | − }, | |
| 298 | − { | |
| 299 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, | |
| 300 | − .max_width = 8192, | |
| 301 | − .max_height = 4352, | |
| 302 | − .max_pixels_per_frame = 8192 * 4352, | |
| 303 | − .max_level = 0, | |
| 304 | − }, | |
| 128 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, | |
| 129 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, | |
| 130 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 131 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, | |
| 132 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, | |
| 133 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 134 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, | |
| 135 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, | |
| 305 | 136 | }; |
| 306 | 137 | |
| 307 | 138 | static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = |
| @@ -333,6 +164,19 @@ static const struct amdgpu_video_codecs bg_video_codecs_encode = { · 25 unmodified lines | ||
| 333 | 164 | .codec_array = NULL, |
| 334 | 165 | }; |
| 335 | 166 | |
| 167 | +/* Yellow Carp*/ | |
| 168 | +static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { | |
| 169 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 170 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, | |
| 171 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, | |
| 172 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 173 | +}; | |
| 174 | + | |
| 175 | +static const struct amdgpu_video_codecs yc_video_codecs_decode = { | |
| 176 | + .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), | |
| 177 | + .codec_array = yc_video_codecs_decode_array, | |
| 178 | +}; | |
| 179 | + | |
| 336 | 180 | static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, |
| 337 | 181 | const struct amdgpu_video_codecs **codecs) |
| 338 | 182 | { |
| @@ -353,12 +197,17 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, · 14 unmodified lines | ||
| 353 | 197 | case CHIP_NAVY_FLOUNDER: |
| 354 | 198 | case CHIP_DIMGREY_CAVEFISH: |
| 355 | 199 | case CHIP_VANGOGH: |
| 356 | − case CHIP_YELLOW_CARP: | |
| 357 | 200 | if (encode) |
| 358 | 201 | *codecs = &nv_video_codecs_encode; |
| 359 | 202 | else |
| 360 | 203 | *codecs = &sc_video_codecs_decode; |
| 361 | 204 | return 0; |
| 205 | + case CHIP_YELLOW_CARP: | |
| 206 | + if (encode) | |
| 207 | + *codecs = &nv_video_codecs_encode; | |
| 208 | + else | |
| 209 | + *codecs = &yc_video_codecs_decode; | |
| 210 | + return 0; | |
| 362 | 211 | case CHIP_BEIGE_GOBY: |
| 363 | 212 | if (encode) |
| 364 | 213 | *codecs = &bg_video_codecs_encode; |
| @@ -1387,7 +1236,10 @@ static int nv_common_early_init(void *handle) · 1022 unmodified lines | ||
| 1387 | 1236 | AMD_PG_SUPPORT_VCN | |
| 1388 | 1237 | AMD_PG_SUPPORT_VCN_DPG | |
| 1389 | 1238 | AMD_PG_SUPPORT_JPEG; |
| 1390 | − adev->external_rev_id = adev->rev_id + 0x01; | |
| 1239 | + if (adev->pdev->device == 0x1681) | |
| 1240 | + adev->external_rev_id = adev->rev_id + 0x19; | |
| 1241 | + else | |
| 1242 | + adev->external_rev_id = adev->rev_id + 0x01; | |
| 1391 | 1243 | break; |
| 1392 | 1244 | default: |
| 1393 | 1245 | /* FIXME: not supported yet */ |
| @@ -67,7 +67,7 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) · 66 unmodified lines | ||
| 67 | 67 | |
| 68 | 68 | err = psp_init_asd_microcode(psp, chip_name); |
| 69 | 69 | if (err) |
| 70 | − goto out; | |
| 70 | + return err; | |
| 71 | 71 | |
| 72 | 72 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); |
| 73 | 73 | err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); |
| @@ -80,7 +80,7 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) · 6 unmodified lines | ||
| 80 | 80 | } else { |
| 81 | 81 | err = amdgpu_ucode_validate(adev->psp.ta_fw); |
| 82 | 82 | if (err) |
| 83 | − goto out2; | |
| 83 | + goto out; | |
| 84 | 84 | |
| 85 | 85 | ta_hdr = (const struct ta_firmware_header_v1_0 *) |
| 86 | 86 | adev->psp.ta_fw->data; |
| @@ -105,10 +105,9 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) · 18 unmodified lines | ||
| 105 | 105 | |
| 106 | 106 | return 0; |
| 107 | 107 | |
| 108 | −out2: | |
| 108 | +out: | |
| 109 | 109 | release_firmware(adev->psp.ta_fw); |
| 110 | 110 | adev->psp.ta_fw = NULL; |
| 111 | −out: | |
| 112 | 111 | if (err) { |
| 113 | 112 | dev_err(adev->dev, |
| 114 | 113 | "psp v12.0: Failed to load firmware \"%s\"\n", |
| @@ -88,20 +88,8 @@ · 87 unmodified lines | ||
| 88 | 88 | /* Vega, Raven, Arcturus */ |
| 89 | 89 | static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = |
| 90 | 90 | { |
| 91 | − { | |
| 92 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 93 | − .max_width = 4096, | |
| 94 | − .max_height = 2304, | |
| 95 | − .max_pixels_per_frame = 4096 * 2304, | |
| 96 | − .max_level = 0, | |
| 97 | − }, | |
| 98 | − { | |
| 99 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 100 | − .max_width = 4096, | |
| 101 | − .max_height = 2304, | |
| 102 | − .max_pixels_per_frame = 4096 * 2304, | |
| 103 | − .max_level = 0, | |
| 104 | − }, | |
| 91 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, | |
| 92 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, | |
| 105 | 93 | }; |
| 106 | 94 | |
| 107 | 95 | static const struct amdgpu_video_codecs vega_video_codecs_encode = |
| @@ -113,48 +101,12 @@ static const struct amdgpu_video_codecs vega_video_codecs_encode = · 5 unmodified lines | ||
| 113 | 101 | /* Vega */ |
| 114 | 102 | static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = |
| 115 | 103 | { |
| 116 | − { | |
| 117 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
| 118 | − .max_width = 4096, | |
| 119 | − .max_height = 4096, | |
| 120 | − .max_pixels_per_frame = 4096 * 4096, | |
| 121 | − .max_level = 3, | |
| 122 | − }, | |
| 123 | − { | |
| 124 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
| 125 | − .max_width = 4096, | |
| 126 | − .max_height = 4096, | |
| 127 | − .max_pixels_per_frame = 4096 * 4096, | |
| 128 | − .max_level = 5, | |
| 129 | − }, | |
| 130 | − { | |
| 131 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 132 | − .max_width = 4096, | |
| 133 | − .max_height = 4096, | |
| 134 | − .max_pixels_per_frame = 4096 * 4096, | |
| 135 | − .max_level = 52, | |
| 136 | − }, | |
| 137 | − { | |
| 138 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
| 139 | − .max_width = 4096, | |
| 140 | − .max_height = 4096, | |
| 141 | − .max_pixels_per_frame = 4096 * 4096, | |
| 142 | − .max_level = 4, | |
| 143 | − }, | |
| 144 | − { | |
| 145 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 146 | − .max_width = 4096, | |
| 147 | − .max_height = 4096, | |
| 148 | − .max_pixels_per_frame = 4096 * 4096, | |
| 149 | − .max_level = 186, | |
| 150 | − }, | |
| 151 | − { | |
| 152 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
| 153 | − .max_width = 4096, | |
| 154 | − .max_height = 4096, | |
| 155 | − .max_pixels_per_frame = 4096 * 4096, | |
| 156 | − .max_level = 0, | |
| 157 | − }, | |
| 104 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, | |
| 105 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, | |
| 106 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 107 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, | |
| 108 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, | |
| 109 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 158 | 110 | }; |
| 159 | 111 | |
| 160 | 112 | static const struct amdgpu_video_codecs vega_video_codecs_decode = |
| @@ -166,55 +118,13 @@ static const struct amdgpu_video_codecs vega_video_codecs_decode = · 5 unmodified lines | ||
| 166 | 118 | /* Raven */ |
| 167 | 119 | static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = |
| 168 | 120 | { |
| 169 | − { | |
| 170 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
| 171 | − .max_width = 4096, | |
| 172 | − .max_height = 4096, | |
| 173 | − .max_pixels_per_frame = 4096 * 4096, | |
| 174 | − .max_level = 3, | |
| 175 | − }, | |
| 176 | − { | |
| 177 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
| 178 | − .max_width = 4096, | |
| 179 | − .max_height = 4096, | |
| 180 | − .max_pixels_per_frame = 4096 * 4096, | |
| 181 | − .max_level = 5, | |
| 182 | − }, | |
| 183 | − { | |
| 184 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 185 | − .max_width = 4096, | |
| 186 | − .max_height = 4096, | |
| 187 | − .max_pixels_per_frame = 4096 * 4096, | |
| 188 | − .max_level = 52, | |
| 189 | − }, | |
| 190 | − { | |
| 191 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
| 192 | − .max_width = 4096, | |
| 193 | − .max_height = 4096, | |
| 194 | − .max_pixels_per_frame = 4096 * 4096, | |
| 195 | − .max_level = 4, | |
| 196 | − }, | |
| 197 | − { | |
| 198 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 199 | − .max_width = 4096, | |
| 200 | − .max_height = 4096, | |
| 201 | − .max_pixels_per_frame = 4096 * 4096, | |
| 202 | − .max_level = 186, | |
| 203 | − }, | |
| 204 | − { | |
| 205 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
| 206 | − .max_width = 4096, | |
| 207 | − .max_height = 4096, | |
| 208 | − .max_pixels_per_frame = 4096 * 4096, | |
| 209 | − .max_level = 0, | |
| 210 | − }, | |
| 211 | − { | |
| 212 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, | |
| 213 | − .max_width = 4096, | |
| 214 | − .max_height = 4096, | |
| 215 | − .max_pixels_per_frame = 4096 * 4096, | |
| 216 | − .max_level = 0, | |
| 217 | − }, | |
| 121 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, | |
| 122 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, | |
| 123 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 124 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, | |
| 125 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, | |
| 126 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 127 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, | |
| 218 | 128 | }; |
| 219 | 129 | |
| 220 | 130 | static const struct amdgpu_video_codecs rv_video_codecs_decode = |
| @@ -226,55 +136,13 @@ static const struct amdgpu_video_codecs rv_video_codecs_decode = · 5 unmodified lines | ||
| 226 | 136 | /* Renoir, Arcturus */ |
| 227 | 137 | static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = |
| 228 | 138 | { |
| 229 | − { | |
| 230 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
| 231 | − .max_width = 4096, | |
| 232 | − .max_height = 4096, | |
| 233 | − .max_pixels_per_frame = 4096 * 4096, | |
| 234 | − .max_level = 3, | |
| 235 | − }, | |
| 236 | − { | |
| 237 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
| 238 | − .max_width = 4096, | |
| 239 | − .max_height = 4096, | |
| 240 | − .max_pixels_per_frame = 4096 * 4096, | |
| 241 | − .max_level = 5, | |
| 242 | − }, | |
| 243 | − { | |
| 244 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
| 245 | − .max_width = 4096, | |
| 246 | − .max_height = 4096, | |
| 247 | − .max_pixels_per_frame = 4096 * 4096, | |
| 248 | − .max_level = 52, | |
| 249 | − }, | |
| 250 | − { | |
| 251 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
| 252 | − .max_width = 4096, | |
| 253 | − .max_height = 4096, | |
| 254 | − .max_pixels_per_frame = 4096 * 4096, | |
| 255 | − .max_level = 4, | |
| 256 | − }, | |
| 257 | − { | |
| 258 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
| 259 | − .max_width = 8192, | |
| 260 | − .max_height = 4352, | |
| 261 | − .max_pixels_per_frame = 4096 * 4096, | |
| 262 | − .max_level = 186, | |
| 263 | − }, | |
| 264 | − { | |
| 265 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
| 266 | − .max_width = 4096, | |
| 267 | − .max_height = 4096, | |
| 268 | − .max_pixels_per_frame = 4096 * 4096, | |
| 269 | − .max_level = 0, | |
| 270 | − }, | |
| 271 | − { | |
| 272 | − .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, | |
| 273 | − .max_width = 8192, | |
| 274 | − .max_height = 4352, | |
| 275 | − .max_pixels_per_frame = 4096 * 4096, | |
| 276 | − .max_level = 0, | |
| 277 | − }, | |
| 139 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, | |
| 140 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, | |
| 141 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
| 142 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, | |
| 143 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, | |
| 144 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
| 145 | + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, | |
| 278 | 146 | }; |
| 279 | 147 | |
| 280 | 148 | static const struct amdgpu_video_codecs rn_video_codecs_decode = |
| @@ -1393,7 +1393,6 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 1392 unmodified lines | ||
| 1393 | 1393 | long err = 0; |
| 1394 | 1394 | int i; |
| 1395 | 1395 | uint32_t *devices_arr = NULL; |
| 1396 | − bool table_freed = false; | |
| 1397 | 1396 | |
| 1398 | 1397 | dev = kfd_device_by_id(GET_GPU_ID(args->handle)); |
| 1399 | 1398 | if (!dev) |
| @@ -1451,8 +1450,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 51 unmodified lines | ||
| 1451 | 1450 | goto get_mem_obj_from_handle_failed; |
| 1452 | 1451 | } |
| 1453 | 1452 | err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( |
| 1454 | − peer->kgd, (struct kgd_mem *)mem, | |
| 1455 | − peer_pdd->drm_priv, &table_freed); | |
| 1453 | + peer->kgd, (struct kgd_mem *)mem, peer_pdd->drm_priv); | |
| 1456 | 1454 | if (err) { |
| 1457 | 1455 | pr_err("Failed to map to gpu %d/%d\n", |
| 1458 | 1456 | i, args->n_devices); |
| @@ -1470,17 +1468,16 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 11 unmodified lines | ||
| 1470 | 1468 | } |
| 1471 | 1469 | |
| 1472 | 1470 | /* Flush TLBs after waiting for the page table updates to complete */ |
| 1473 | − if (table_freed) { | |
| 1474 | − for (i = 0; i < args->n_devices; i++) { | |
| 1475 | − peer = kfd_device_by_id(devices_arr[i]); | |
| 1476 | − if (WARN_ON_ONCE(!peer)) | |
| 1477 | − continue; | |
| 1478 | − peer_pdd = kfd_get_process_device_data(peer, p); | |
| 1479 | − if (WARN_ON_ONCE(!peer_pdd)) | |
| 1480 | − continue; | |
| 1481 | − kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); | |
| 1482 | − } | |
| 1471 | + for (i = 0; i < args->n_devices; i++) { | |
| 1472 | + peer = kfd_device_by_id(devices_arr[i]); | |
| 1473 | + if (WARN_ON_ONCE(!peer)) | |
| 1474 | + continue; | |
| 1475 | + peer_pdd = kfd_get_process_device_data(peer, p); | |
| 1476 | + if (WARN_ON_ONCE(!peer_pdd)) | |
| 1477 | + continue; | |
| 1478 | + kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); | |
| 1483 | 1479 | } |
| 1480 | + | |
| 1484 | 1481 | kfree(devices_arr); |
| 1485 | 1482 | |
| 1486 | 1483 | return err; |
| @@ -1568,27 +1565,10 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 81 unmodified lines | ||
| 1568 | 1565 | } |
| 1569 | 1566 | args->n_success = i+1; |
| 1570 | 1567 | } |
| 1571 | − mutex_unlock(&p->mutex); | |
| 1572 | − | |
| 1573 | − err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true); | |
| 1574 | − if (err) { | |
| 1575 | − pr_debug("Sync memory failed, wait interrupted by user signal\n"); | |
| 1576 | − goto sync_memory_failed; | |
| 1577 | − } | |
| 1578 | − | |
| 1579 | − /* Flush TLBs after waiting for the page table updates to complete */ | |
| 1580 | − for (i = 0; i < args->n_devices; i++) { | |
| 1581 | − peer = kfd_device_by_id(devices_arr[i]); | |
| 1582 | − if (WARN_ON_ONCE(!peer)) | |
| 1583 | − continue; | |
| 1584 | − peer_pdd = kfd_get_process_device_data(peer, p); | |
| 1585 | − if (WARN_ON_ONCE(!peer_pdd)) | |
| 1586 | − continue; | |
| 1587 | − kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); | |
| 1588 | − } | |
| 1589 | − | |
| 1590 | 1568 | kfree(devices_arr); |
| 1591 | 1569 | |
| 1570 | + mutex_unlock(&p->mutex); | |
| 1571 | + | |
| 1592 | 1572 | return 0; |
| 1593 | 1573 | |
| 1594 | 1574 | bind_process_to_device_failed: |
| @@ -1596,7 +1576,6 @@ get_mem_obj_from_handle_failed: · 1 unmodified line | ||
| 1596 | 1576 | unmap_memory_from_gpu_failed: |
| 1597 | 1577 | mutex_unlock(&p->mutex); |
| 1598 | 1578 | copy_from_user_failed: |
| 1599 | −sync_memory_failed: | |
| 1600 | 1579 | kfree(devices_arr); |
| 1601 | 1580 | return err; |
| 1602 | 1581 | } |
| @@ -714,8 +714,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, · 713 unmodified lines | ||
| 714 | 714 | if (err) |
| 715 | 715 | goto err_alloc_mem; |
| 716 | 716 | |
| 717 | − err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem, | |
| 718 | − pdd->drm_priv, NULL); | |
| 717 | + err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem, pdd->drm_priv); | |
| 719 | 718 | if (err) |
| 720 | 719 | goto err_map_mem; |
| 721 | 720 | |
| @@ -2375,21 +2375,27 @@ static bool svm_range_skip_recover(struct svm_range *prange) · 2374 unmodified lines | ||
| 2375 | 2375 | |
| 2376 | 2376 | static void |
| 2377 | 2377 | svm_range_count_fault(struct amdgpu_device *adev, struct kfd_process *p, |
| 2378 | − struct svm_range *prange, int32_t gpuidx) | |
| 2378 | + int32_t gpuidx) | |
| 2379 | 2379 | { |
| 2380 | 2380 | struct kfd_process_device *pdd; |
| 2381 | 2381 | |
| 2382 | − if (gpuidx == MAX_GPU_INSTANCE) | |
| 2383 | − /* fault is on different page of same range | |
| 2384 | − * or fault is skipped to recover later | |
| 2385 | − */ | |
| 2386 | − pdd = svm_range_get_pdd_by_adev(prange, adev); | |
| 2387 | − else | |
| 2388 | − /* fault recovered | |
| 2389 | − * or fault cannot recover because GPU no access on the range | |
| 2390 | − */ | |
| 2391 | − pdd = kfd_process_device_from_gpuidx(p, gpuidx); | |
| 2382 | + /* fault is on different page of same range | |
| 2383 | + * or fault is skipped to recover later | |
| 2384 | + * or fault is on invalid virtual address | |
| 2385 | + */ | |
| 2386 | + if (gpuidx == MAX_GPU_INSTANCE) { | |
| 2387 | + uint32_t gpuid; | |
| 2388 | + int r; | |
| 2389 | + | |
| 2390 | + r = kfd_process_gpuid_from_kgd(p, adev, &gpuid, &gpuidx); | |
| 2391 | + if (r < 0) | |
| 2392 | + return; | |
| 2393 | + } | |
| 2392 | 2394 | |
| 2395 | + /* fault is recovered | |
| 2396 | + * or fault cannot recover because GPU no access on the range | |
| 2397 | + */ | |
| 2398 | + pdd = kfd_process_device_from_gpuidx(p, gpuidx); | |
| 2393 | 2399 | if (pdd) |
| 2394 | 2400 | WRITE_ONCE(pdd->faults, pdd->faults + 1); |
| 2395 | 2401 | } |
| @@ -2525,7 +2531,7 @@ out_unlock_svms: · 129 unmodified lines | ||
| 2525 | 2531 | mutex_unlock(&svms->lock); |
| 2526 | 2532 | mmap_read_unlock(mm); |
| 2527 | 2533 | |
| 2528 | − svm_range_count_fault(adev, p, prange, gpuidx); | |
| 2534 | + svm_range_count_fault(adev, p, gpuidx); | |
| 2529 | 2535 | |
| 2530 | 2536 | mmput(mm); |
| 2531 | 2537 | out: |
| @@ -3020,6 +3026,14 @@ svm_range_get_attr(struct kfd_process *p, uint64_t start, uint64_t size, · 488 unmodified lines | ||
| 3020 | 3026 | pr_debug("svms 0x%p [0x%llx 0x%llx] nattr 0x%x\n", &p->svms, start, |
| 3021 | 3027 | start + size - 1, nattr); |
| 3022 | 3028 | |
| 3029 | + /* Flush pending deferred work to avoid racing with deferred actions from | |
| 3030 | + * previous memory map changes (e.g. munmap). Concurrent memory map changes | |
| 3031 | + * can still race with get_attr because we don't hold the mmap lock. But that | |
| 3032 | + * would be a race condition in the application anyway, and undefined | |
| 3033 | + * behaviour is acceptable in that case. | |
| 3034 | + */ | |
| 3035 | + flush_work(&p->svms.deferred_list_work); | |
| 3036 | + | |
| 3023 | 3037 | mmap_read_lock(mm); |
| 3024 | 3038 | if (!svm_range_is_valid(mm, start, size)) { |
| 3025 | 3039 | pr_debug("invalid range\n"); |
| @@ -1548,6 +1548,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) · 1547 unmodified lines | ||
| 1548 | 1548 | } |
| 1549 | 1549 | |
| 1550 | 1550 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
| 1551 | + adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 1551 | 1552 | |
| 1552 | 1553 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
| 1553 | 1554 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = |
| @@ -1561,7 +1562,6 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) · 7 unmodified lines | ||
| 1561 | 1562 | adev->dm.dmcub_fw_version); |
| 1562 | 1563 | } |
| 1563 | 1564 | |
| 1564 | − adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); | |
| 1565 | 1565 | |
| 1566 | 1566 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); |
| 1567 | 1567 | dmub_srv = adev->dm.dmub_srv; |
| @@ -2429,9 +2429,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) · 861 unmodified lines | ||
| 2429 | 2429 | max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; |
| 2430 | 2430 | min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; |
| 2431 | 2431 | |
| 2432 | − if (caps->ext_caps->bits.oled == 1 || | |
| 2432 | + if (caps->ext_caps->bits.oled == 1 /*|| | |
| 2433 | 2433 | caps->ext_caps->bits.sdr_aux_backlight_control == 1 || |
| 2434 | − caps->ext_caps->bits.hdr_aux_backlight_control == 1) | |
| 2434 | + caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) | |
| 2435 | 2435 | caps->aux_support = true; |
| 2436 | 2436 | |
| 2437 | 2437 | if (amdgpu_backlight == 0) |
| @@ -9191,7 +9191,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 6753 unmodified lines | ||
| 9191 | 9191 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ |
| 9192 | 9192 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
| 9193 | 9193 | /* restore the backlight level */ |
| 9194 | − if (dm->backlight_dev) | |
| 9194 | + if (dm->backlight_dev && (amdgpu_dm_backlight_get_level(dm) != dm->brightness[0])) | |
| 9195 | 9195 | amdgpu_dm_backlight_set_level(dm, dm->brightness[0]); |
| 9196 | 9196 | #endif |
| 9197 | 9197 | /* |
| @@ -9605,7 +9605,12 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, · 407 unmodified lines | ||
| 9605 | 9605 | } else if (amdgpu_freesync_vid_mode && aconnector && |
| 9606 | 9606 | is_freesync_video_mode(&new_crtc_state->mode, |
| 9607 | 9607 | aconnector)) { |
| 9608 | − set_freesync_fixed_config(dm_new_crtc_state); | |
| 9608 | + struct drm_display_mode *high_mode; | |
| 9609 | + | |
| 9610 | + high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
| 9611 | + if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { | |
| 9612 | + set_freesync_fixed_config(dm_new_crtc_state); | |
| 9613 | + } | |
| 9609 | 9614 | } |
| 9610 | 9615 | |
| 9611 | 9616 | ret = dm_atomic_get_state(state, &dm_state); |
| @@ -584,7 +584,7 @@ static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev, · 583 unmodified lines | ||
| 584 | 584 | handler_data = container_of(handler_list->next, struct amdgpu_dm_irq_handler_data, list); |
| 585 | 585 | |
| 586 | 586 | /*allocate a new amdgpu_dm_irq_handler_data*/ |
| 587 | − handler_data_add = kzalloc(sizeof(*handler_data), GFP_KERNEL); | |
| 587 | + handler_data_add = kzalloc(sizeof(*handler_data), GFP_ATOMIC); | |
| 588 | 588 | if (!handler_data_add) { |
| 589 | 589 | DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n"); |
| 590 | 590 | return; |
| @@ -197,7 +197,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct · 196 unmodified lines | ||
| 197 | 197 | |
| 198 | 198 | REG_UPDATE(DENTIST_DISPCLK_CNTL, |
| 199 | 199 | DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); |
| 200 | −// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); | |
| 200 | + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000); | |
| 201 | 201 | REG_UPDATE(DENTIST_DISPCLK_CNTL, |
| 202 | 202 | DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); |
| 203 | 203 | REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); |
| @@ -66,9 +66,11 @@ int rn_get_active_display_cnt_wa( · 65 unmodified lines | ||
| 66 | 66 | for (i = 0; i < context->stream_count; i++) { |
| 67 | 67 | const struct dc_stream_state *stream = context->streams[i]; |
| 68 | 68 | |
| 69 | + /* Extend the WA to DP for Linux*/ | |
| 69 | 70 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || |
| 70 | 71 | stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || |
| 71 | − stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) | |
| 72 | + stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK || | |
| 73 | + stream->signal == SIGNAL_TYPE_DISPLAY_PORT) | |
| 72 | 74 | tmds_present = true; |
| 73 | 75 | } |
| 74 | 76 | |
| @@ -190,6 +190,10 @@ void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) · 189 unmodified lines | ||
| 190 | 190 | &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, |
| 191 | 191 | &num_levels); |
| 192 | 192 | |
| 193 | + /* SOCCLK */ | |
| 194 | + dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK, | |
| 195 | + &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, | |
| 196 | + &num_levels); | |
| 193 | 197 | // DPREFCLK ??? |
| 194 | 198 | |
| 195 | 199 | /* DISPCLK */ |
| @@ -48,6 +48,21 @@ · 47 unmodified lines | ||
| 48 | 48 | |
| 49 | 49 | #include "dc_dmub_srv.h" |
| 50 | 50 | |
| 51 | +#include "yellow_carp_offset.h" | |
| 52 | + | |
| 53 | +#define regCLK1_CLK_PLL_REQ 0x0237 | |
| 54 | +#define regCLK1_CLK_PLL_REQ_BASE_IDX 0 | |
| 55 | + | |
| 56 | +#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 | |
| 57 | +#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc | |
| 58 | +#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 | |
| 59 | +#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL | |
| 60 | +#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L | |
| 61 | +#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L | |
| 62 | + | |
| 63 | +#define REG(reg_name) \ | |
| 64 | + (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) | |
| 65 | + | |
| 51 | 66 | #define TO_CLK_MGR_DCN31(clk_mgr)\ |
| 52 | 67 | container_of(clk_mgr, struct clk_mgr_dcn31, base) |
| 53 | 68 | |
| @@ -124,10 +139,10 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, · 70 unmodified lines | ||
| 124 | 139 | * also if safe to lower is false, we just go in the higher state |
| 125 | 140 | */ |
| 126 | 141 | if (safe_to_lower) { |
| 127 | − if (new_clocks->z9_support == DCN_Z9_SUPPORT_ALLOW && | |
| 128 | − new_clocks->z9_support != clk_mgr_base->clks.z9_support) { | |
| 142 | + if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW && | |
| 143 | + new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { | |
| 129 | 144 | dcn31_smu_set_Z9_support(clk_mgr, true); |
| 130 | − clk_mgr_base->clks.z9_support = new_clocks->z9_support; | |
| 145 | + clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; | |
| 131 | 146 | } |
| 132 | 147 | |
| 133 | 148 | if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { |
| @@ -148,10 +163,10 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, · 14 unmodified lines | ||
| 148 | 163 | } |
| 149 | 164 | } |
| 150 | 165 | } else { |
| 151 | − if (new_clocks->z9_support == DCN_Z9_SUPPORT_DISALLOW && | |
| 152 | − new_clocks->z9_support != clk_mgr_base->clks.z9_support) { | |
| 166 | + if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && | |
| 167 | + new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { | |
| 153 | 168 | dcn31_smu_set_Z9_support(clk_mgr, false); |
| 154 | − clk_mgr_base->clks.z9_support = new_clocks->z9_support; | |
| 169 | + clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; | |
| 155 | 170 | } |
| 156 | 171 | |
| 157 | 172 | if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { |
| @@ -229,7 +244,32 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, · 71 unmodified lines | ||
| 229 | 244 | |
| 230 | 245 | static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) |
| 231 | 246 | { |
| 232 | − return 0; | |
| 247 | + /* get FbMult value */ | |
| 248 | + struct fixed31_32 pll_req; | |
| 249 | + unsigned int fbmult_frac_val = 0; | |
| 250 | + unsigned int fbmult_int_val = 0; | |
| 251 | + | |
| 252 | + /* | |
| 253 | + * Register value of fbmult is in 8.16 format, we are converting to 31.32 | |
| 254 | + * to leverage the fix point operations available in driver | |
| 255 | + */ | |
| 256 | + | |
| 257 | + REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ | |
| 258 | + REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ | |
| 259 | + | |
| 260 | + pll_req = dc_fixpt_from_int(fbmult_int_val); | |
| 261 | + | |
| 262 | + /* | |
| 263 | + * since fractional part is only 16 bit in register definition but is 32 bit | |
| 264 | + * in our fix point definiton, need to shift left by 16 to obtain correct value | |
| 265 | + */ | |
| 266 | + pll_req.value |= fbmult_frac_val << 16; | |
| 267 | + | |
| 268 | + /* multiply by REFCLK period */ | |
| 269 | + pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); | |
| 270 | + | |
| 271 | + /* integer part is now VCO frequency in kHz */ | |
| 272 | + return dc_fixpt_floor(pll_req); | |
| 233 | 273 | } |
| 234 | 274 | |
| 235 | 275 | static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base) |
| @@ -246,7 +286,7 @@ static void dcn31_init_clocks(struct clk_mgr *clk_mgr) · 10 unmodified lines | ||
| 246 | 286 | clk_mgr->clks.p_state_change_support = true; |
| 247 | 287 | clk_mgr->clks.prev_p_state_change_support = true; |
| 248 | 288 | clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; |
| 249 | − clk_mgr->clks.z9_support = DCN_Z9_SUPPORT_UNKNOWN; | |
| 289 | + clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; | |
| 250 | 290 | } |
| 251 | 291 | |
| 252 | 292 | static bool dcn31_are_clock_states_equal(struct dc_clocks *a, |
| @@ -260,7 +300,7 @@ static bool dcn31_are_clock_states_equal(struct dc_clocks *a, · 7 unmodified lines | ||
| 260 | 300 | return false; |
| 261 | 301 | else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) |
| 262 | 302 | return false; |
| 263 | − else if (a->z9_support != b->z9_support) | |
| 303 | + else if (a->zstate_support != b->zstate_support) | |
| 264 | 304 | return false; |
| 265 | 305 | else if (a->dtbclk_en != b->dtbclk_en) |
| 266 | 306 | return false; |
| @@ -592,6 +632,7 @@ void dcn31_clk_mgr_construct( · 325 unmodified lines | ||
| 592 | 632 | clk_mgr->base.dprefclk_ss_percentage = 0; |
| 593 | 633 | clk_mgr->base.dprefclk_ss_divider = 1000; |
| 594 | 634 | clk_mgr->base.ss_on_dprefclk = false; |
| 635 | + clk_mgr->base.dfs_ref_freq_khz = 48000; | |
| 595 | 636 | |
| 596 | 637 | clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( |
| 597 | 638 | clk_mgr->base.base.ctx, |
| @@ -27,60 +27,6 @@ · 26 unmodified lines | ||
| 27 | 27 | #define __DCN31_CLK_MGR_H__ |
| 28 | 28 | #include "clk_mgr_internal.h" |
| 29 | 29 | |
| 30 | −//CLK1_CLK_PLL_REQ | |
| 31 | −#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT | |
| 32 | −#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 | |
| 33 | −#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc | |
| 34 | −#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 | |
| 35 | −#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL | |
| 36 | −#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L | |
| 37 | −#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L | |
| 38 | −//CLK1_CLK0_DFS_CNTL | |
| 39 | −#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0 | |
| 40 | −#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL | |
| 41 | −/*DPREF clock related*/ | |
| 42 | −#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 | |
| 43 | −#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL | |
| 44 | −#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 | |
| 45 | −#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL | |
| 46 | −#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 | |
| 47 | −#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL | |
| 48 | −#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 | |
| 49 | −#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL | |
| 50 | − | |
| 51 | −//CLK3_0_CLK3_CLK_PLL_REQ | |
| 52 | −#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 | |
| 53 | −#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc | |
| 54 | −#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 | |
| 55 | −#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL | |
| 56 | −#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L | |
| 57 | −#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L | |
| 58 | − | |
| 59 | −#define mmCLK0_CLK3_DFS_CNTL 0x16C60 | |
| 60 | −#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60 | |
| 61 | −#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60 | |
| 62 | −#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060 | |
| 63 | −#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260 | |
| 64 | − | |
| 65 | −#define mmCLK0_CLK_PLL_REQ 0x16C10 | |
| 66 | −#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10 | |
| 67 | −#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10 | |
| 68 | −#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010 | |
| 69 | −#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210 | |
| 70 | − | |
| 71 | −#define mmCLK1_CLK_PLL_REQ 0x1B00D | |
| 72 | −#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D | |
| 73 | −#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D | |
| 74 | −#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D | |
| 75 | −#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D | |
| 76 | − | |
| 77 | −#define mmCLK2_CLK_PLL_REQ 0x17E0D | |
| 78 | − | |
| 79 | −/*AMCLK*/ | |
| 80 | −#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F | |
| 81 | −#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D | |
| 82 | −#endif | |
| 83 | − | |
| 84 | 30 | struct dcn31_watermarks; |
| 85 | 31 | |
| 86 | 32 | struct dcn31_smu_watermark_set { |
| @@ -31,8 +31,8 @@ · 30 unmodified lines | ||
| 31 | 31 | #include "dcn31_smu.h" |
| 32 | 32 | |
| 33 | 33 | #include "yellow_carp_offset.h" |
| 34 | −#include "mp/mp_13_0_1_offset.h" | |
| 35 | −#include "mp/mp_13_0_1_sh_mask.h" | |
| 34 | +#include "mp/mp_13_0_2_offset.h" | |
| 35 | +#include "mp/mp_13_0_2_sh_mask.h" | |
| 36 | 36 | |
| 37 | 37 | #define REG(reg_name) \ |
| 38 | 38 | (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) |
| @@ -1530,6 +1530,12 @@ void dc_z10_restore(struct dc *dc) · 1529 unmodified lines | ||
| 1530 | 1530 | if (dc->hwss.z10_restore) |
| 1531 | 1531 | dc->hwss.z10_restore(dc); |
| 1532 | 1532 | } |
| 1533 | + | |
| 1534 | +void dc_z10_save_init(struct dc *dc) | |
| 1535 | +{ | |
| 1536 | + if (dc->hwss.z10_save_init) | |
| 1537 | + dc->hwss.z10_save_init(dc); | |
| 1538 | +} | |
| 1533 | 1539 | #endif |
| 1534 | 1540 | /* |
| 1535 | 1541 | * Applies given context to HW and copy it into current context. |
| @@ -1620,11 +1620,12 @@ enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_train · 1619 unmodified lines | ||
| 1620 | 1620 | { |
| 1621 | 1621 | enum dc_status status = DC_OK; |
| 1622 | 1622 | |
| 1623 | − if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) | |
| 1624 | − status = configure_lttpr_mode_non_transparent(link, lt_settings); | |
| 1625 | − else | |
| 1623 | + if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) | |
| 1626 | 1624 | status = configure_lttpr_mode_transparent(link); |
| 1627 | 1625 | |
| 1626 | + else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) | |
| 1627 | + status = configure_lttpr_mode_non_transparent(link, lt_settings); | |
| 1628 | + | |
| 1628 | 1629 | return status; |
| 1629 | 1630 | } |
| 1630 | 1631 | |
| @@ -1784,7 +1785,6 @@ bool perform_link_training_with_retries( · 153 unmodified lines | ||
| 1784 | 1785 | link_enc = stream->link_enc; |
| 1785 | 1786 | else |
| 1786 | 1787 | link_enc = link->link_enc; |
| 1787 | − ASSERT(link_enc); | |
| 1788 | 1788 | |
| 1789 | 1789 | /* We need to do this before the link training to ensure the idle pattern in SST |
| 1790 | 1790 | * mode will be sent right after the link training |
| @@ -1820,8 +1820,7 @@ bool perform_link_training_with_retries( · 29 unmodified lines | ||
| 1820 | 1820 | */ |
| 1821 | 1821 | panel_mode = DP_PANEL_MODE_DEFAULT; |
| 1822 | 1822 | } |
| 1823 | − } else | |
| 1824 | − panel_mode = DP_PANEL_MODE_DEFAULT; | |
| 1823 | + } | |
| 1825 | 1824 | } |
| 1826 | 1825 | #endif |
| 1827 | 1826 | |
| @@ -3603,29 +3602,12 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link) · 1775 unmodified lines | ||
| 3603 | 3602 | bool dp_retrieve_lttpr_cap(struct dc_link *link) |
| 3604 | 3603 | { |
| 3605 | 3604 | uint8_t lttpr_dpcd_data[6]; |
| 3606 | − bool vbios_lttpr_enable = false; | |
| 3607 | − bool vbios_lttpr_interop = false; | |
| 3608 | − struct dc_bios *bios = link->dc->ctx->dc_bios; | |
| 3605 | + bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable; | |
| 3606 | + bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware; | |
| 3609 | 3607 | enum dc_status status = DC_ERROR_UNEXPECTED; |
| 3610 | 3608 | bool is_lttpr_present = false; |
| 3611 | 3609 | |
| 3612 | 3610 | memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); |
| 3613 | − /* Query BIOS to determine if LTTPR functionality is forced on by system */ | |
| 3614 | − if (bios->funcs->get_lttpr_caps) { | |
| 3615 | − enum bp_result bp_query_result; | |
| 3616 | − uint8_t is_vbios_lttpr_enable = 0; | |
| 3617 | − | |
| 3618 | − bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable); | |
| 3619 | − vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; | |
| 3620 | − } | |
| 3621 | − | |
| 3622 | − if (bios->funcs->get_lttpr_interop) { | |
| 3623 | − enum bp_result bp_query_result; | |
| 3624 | − uint8_t is_vbios_interop_enabled = 0; | |
| 3625 | − | |
| 3626 | − bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled); | |
| 3627 | − vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; | |
| 3628 | − } | |
| 3629 | 3611 | |
| 3630 | 3612 | /* |
| 3631 | 3613 | * Logic to determine LTTPR mode |
| @@ -4650,7 +4632,10 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) · 1018 unmodified lines | ||
| 4650 | 4632 | } |
| 4651 | 4633 | } |
| 4652 | 4634 | |
| 4653 | − if (link->dpcd_caps.panel_mode_edp) { | |
| 4635 | + if (link->dpcd_caps.panel_mode_edp && | |
| 4636 | + (link->connector_signal == SIGNAL_TYPE_EDP || | |
| 4637 | + (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && | |
| 4638 | + link->is_internal_display))) { | |
| 4654 | 4639 | return DP_PANEL_MODE_EDP; |
| 4655 | 4640 | } |
| 4656 | 4641 | |
| @@ -4914,9 +4899,7 @@ bool dc_link_set_default_brightness_aux(struct dc_link *link) · 257 unmodified lines | ||
| 4914 | 4899 | { |
| 4915 | 4900 | uint32_t default_backlight; |
| 4916 | 4901 | |
| 4917 | − if (link && | |
| 4918 | − (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || | |
| 4919 | − link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { | |
| 4902 | + if (link && link->dpcd_sink_ext_caps.bits.oled == 1) { | |
| 4920 | 4903 | if (!dc_link_read_default_bl_aux(link, &default_backlight)) |
| 4921 | 4904 | default_backlight = 150000; |
| 4922 | 4905 | // if < 5 nits or > 5000, it might be wrong readback |
| @@ -1062,7 +1062,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 1061 unmodified lines | ||
| 1062 | 1062 | * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3 |
| 1063 | 1063 | * did not show such problems, so this seems to be the exception. |
| 1064 | 1064 | */ |
| 1065 | − if (plane_state->ctx->dce_version != DCE_VERSION_11_0) | |
| 1065 | + if (plane_state->ctx->dce_version > DCE_VERSION_11_0) | |
| 1066 | 1066 | pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; |
| 1067 | 1067 | else |
| 1068 | 1068 | pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; |
| @@ -47,6 +47,9 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c · 46 unmodified lines | ||
| 47 | 47 | */ |
| 48 | 48 | memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); |
| 49 | 49 | dc->vm_pa_config.valid = true; |
| 50 | +#if defined(CONFIG_DRM_AMD_DC_DCN) | |
| 51 | + dc_z10_save_init(dc); | |
| 52 | +#endif | |
| 50 | 53 | } |
| 51 | 54 | |
| 52 | 55 | return num_vmids; |
| @@ -183,6 +183,8 @@ struct dc_caps { · 182 unmodified lines | ||
| 183 | 183 | unsigned int cursor_cache_size; |
| 184 | 184 | struct dc_plane_cap planes[MAX_PLANES]; |
| 185 | 185 | struct dc_color_caps color; |
| 186 | + bool vbios_lttpr_aware; | |
| 187 | + bool vbios_lttpr_enable; | |
| 186 | 188 | }; |
| 187 | 189 | |
| 188 | 190 | struct dc_bug_wa { |
| @@ -354,10 +356,10 @@ enum dcn_pwr_state { · 165 unmodified lines | ||
| 354 | 356 | }; |
| 355 | 357 | |
| 356 | 358 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
| 357 | −enum dcn_z9_support_state { | |
| 358 | − DCN_Z9_SUPPORT_UNKNOWN, | |
| 359 | − DCN_Z9_SUPPORT_ALLOW, | |
| 360 | − DCN_Z9_SUPPORT_DISALLOW, | |
| 359 | +enum dcn_zstate_support_state { | |
| 360 | + DCN_ZSTATE_SUPPORT_UNKNOWN, | |
| 361 | + DCN_ZSTATE_SUPPORT_ALLOW, | |
| 362 | + DCN_ZSTATE_SUPPORT_DISALLOW, | |
| 361 | 363 | }; |
| 362 | 364 | #endif |
| 363 | 365 | /* |
| @@ -378,7 +380,7 @@ struct dc_clocks { · 14 unmodified lines | ||
| 378 | 380 | int dramclk_khz; |
| 379 | 381 | bool p_state_change_support; |
| 380 | 382 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
| 381 | − enum dcn_z9_support_state z9_support; | |
| 383 | + enum dcn_zstate_support_state zstate_support; | |
| 382 | 384 | bool dtbclk_en; |
| 383 | 385 | #endif |
| 384 | 386 | enum dcn_pwr_state pwr_state; |
| @@ -1336,6 +1338,7 @@ void dc_hardware_release(struct dc *dc); · 951 unmodified lines | ||
| 1336 | 1338 | bool dc_set_psr_allow_active(struct dc *dc, bool enable); |
| 1337 | 1339 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
| 1338 | 1340 | void dc_z10_restore(struct dc *dc); |
| 1341 | +void dc_z10_save_init(struct dc *dc); | |
| 1339 | 1342 | #endif |
| 1340 | 1343 | |
| 1341 | 1344 | bool dc_enable_dmub_notifications(struct dc *dc); |
| @@ -636,6 +636,7 @@ struct dce_hwseq_registers { · 635 unmodified lines | ||
| 636 | 636 | uint32_t ODM_MEM_PWR_CTRL3; |
| 637 | 637 | uint32_t DMU_MEM_PWR_CNTL; |
| 638 | 638 | uint32_t MMHUBBUB_MEM_PWR_CNTL; |
| 639 | + uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; | |
| 639 | 640 | }; |
| 640 | 641 | /* set field name */ |
| 641 | 642 | #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ |
| @@ -1110,7 +1111,8 @@ struct dce_hwseq_registers { · 468 unmodified lines | ||
| 1110 | 1111 | type DOMAIN_POWER_FORCEON;\ |
| 1111 | 1112 | type DOMAIN_POWER_GATE;\ |
| 1112 | 1113 | type DOMAIN_PGFSM_PWR_STATUS;\ |
| 1113 | − type HPO_HDMISTREAMCLK_G_GATE_DIS; | |
| 1114 | + type HPO_HDMISTREAMCLK_G_GATE_DIS;\ | |
| 1115 | + type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE; | |
| 1114 | 1116 | |
| 1115 | 1117 | struct dce_hwseq_shift { |
| 1116 | 1118 | HWSEQ_REG_FIELD_LIST(uint8_t) |
| @@ -217,6 +217,8 @@ static void dpp1_dscl_set_lb( · 216 unmodified lines | ||
| 217 | 217 | const struct line_buffer_params *lb_params, |
| 218 | 218 | enum lb_memory_config mem_size_config) |
| 219 | 219 | { |
| 220 | + uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */ | |
| 221 | + | |
| 220 | 222 | /* LB */ |
| 221 | 223 | if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { |
| 222 | 224 | /* DSCL caps: pixel data processed in fixed format */ |
| @@ -239,9 +241,12 @@ static void dpp1_dscl_set_lb( · 16 unmodified lines | ||
| 239 | 241 | LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ |
| 240 | 242 | } |
| 241 | 243 | |
| 244 | + if (dpp->base.caps->max_lb_partitions == 31) | |
| 245 | + max_partitions = 31; | |
| 246 | + | |
| 242 | 247 | REG_SET_2(LB_MEMORY_CTRL, 0, |
| 243 | 248 | MEMORY_CONFIG, mem_size_config, |
| 244 | − LB_MAX_PARTITIONS, 63); | |
| 249 | + LB_MAX_PARTITIONS, max_partitions); | |
| 245 | 250 | } |
| 246 | 251 | |
| 247 | 252 | static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) |
| @@ -464,7 +464,7 @@ void optc2_lock_doublebuffer_enable(struct timing_generator *optc) · 463 unmodified lines | ||
| 464 | 464 | |
| 465 | 465 | REG_UPDATE_2(OTG_GLOBAL_CONTROL1, |
| 466 | 466 | MASTER_UPDATE_LOCK_DB_X, |
| 467 | − h_blank_start - 200 - 1, | |
| 467 | + (h_blank_start - 200 - 1) / optc1->opp_count, | |
| 468 | 468 | MASTER_UPDATE_LOCK_DB_Y, |
| 469 | 469 | v_blank_start - 1); |
| 470 | 470 | } |
| @@ -2093,8 +2093,10 @@ int dcn20_populate_dml_pipes_from_context( · 2092 unmodified lines | ||
| 2093 | 2093 | - timing->v_border_bottom; |
| 2094 | 2094 | pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; |
| 2095 | 2095 | pipes[pipe_cnt].pipe.dest.vtotal = v_total; |
| 2096 | − pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; | |
| 2097 | − pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; | |
| 2096 | + pipes[pipe_cnt].pipe.dest.hactive = | |
| 2097 | + timing->h_addressable + timing->h_border_left + timing->h_border_right; | |
| 2098 | + pipes[pipe_cnt].pipe.dest.vactive = | |
| 2099 | + timing->v_addressable + timing->v_border_top + timing->v_border_bottom; | |
| 2098 | 2100 | pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; |
| 2099 | 2101 | pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; |
| 2100 | 2102 | if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) |
| @@ -3079,6 +3081,37 @@ static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) · 978 unmodified lines | ||
| 3079 | 3081 | return false; |
| 3080 | 3082 | } |
| 3081 | 3083 | |
| 3084 | +static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context) | |
| 3085 | +{ | |
| 3086 | + int plane_count; | |
| 3087 | + int i; | |
| 3088 | + | |
| 3089 | + plane_count = 0; | |
| 3090 | + for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
| 3091 | + if (context->res_ctx.pipe_ctx[i].plane_state) | |
| 3092 | + plane_count++; | |
| 3093 | + } | |
| 3094 | + | |
| 3095 | + /* | |
| 3096 | + * Zstate is allowed in following scenarios: | |
| 3097 | + * 1. Single eDP with PSR enabled | |
| 3098 | + * 2. 0 planes (No memory requests) | |
| 3099 | + * 3. Single eDP without PSR but > 5ms stutter period | |
| 3100 | + */ | |
| 3101 | + if (plane_count == 0) | |
| 3102 | + return DCN_ZSTATE_SUPPORT_ALLOW; | |
| 3103 | + else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { | |
| 3104 | + struct dc_link *link = context->streams[0]->sink->link; | |
| 3105 | + | |
| 3106 | + if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled) | |
| 3107 | + || context->bw_ctx.dml.vba.StutterPeriod > 5000.0) | |
| 3108 | + return DCN_ZSTATE_SUPPORT_ALLOW; | |
| 3109 | + else | |
| 3110 | + return DCN_ZSTATE_SUPPORT_DISALLOW; | |
| 3111 | + } else | |
| 3112 | + return DCN_ZSTATE_SUPPORT_DISALLOW; | |
| 3113 | +} | |
| 3114 | + | |
| 3082 | 3115 | void dcn20_calculate_dlg_params( |
| 3083 | 3116 | struct dc *dc, struct dc_state *context, |
| 3084 | 3117 | display_e2e_pipe_params_st *pipes, |
| @@ -3086,7 +3119,6 @@ void dcn20_calculate_dlg_params( · 1 unmodified line | ||
| 3086 | 3119 | int vlevel) |
| 3087 | 3120 | { |
| 3088 | 3121 | int i, pipe_idx; |
| 3089 | − int plane_count; | |
| 3090 | 3122 | |
| 3091 | 3123 | /* Writeback MCIF_WB arbitration parameters */ |
| 3092 | 3124 | dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); |
| @@ -3102,17 +3134,7 @@ void dcn20_calculate_dlg_params( · 9 unmodified lines | ||
| 3102 | 3134 | != dm_dram_clock_change_unsupported; |
| 3103 | 3135 | context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; |
| 3104 | 3136 | |
| 3105 | − context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ? | |
| 3106 | − DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW; | |
| 3107 | − | |
| 3108 | − plane_count = 0; | |
| 3109 | − for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
| 3110 | − if (context->res_ctx.pipe_ctx[i].plane_state) | |
| 3111 | − plane_count++; | |
| 3112 | − } | |
| 3113 | − | |
| 3114 | − if (plane_count == 0) | |
| 3115 | − context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW; | |
| 3137 | + context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context); | |
| 3116 | 3138 | |
| 3117 | 3139 | context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); |
| 3118 | 3140 | |
| @@ -109,6 +109,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = { · 108 unmodified lines | ||
| 109 | 109 | .max_page_table_levels = 4, |
| 110 | 110 | .pte_chunk_size_kbytes = 2, |
| 111 | 111 | .meta_chunk_size_kbytes = 2, |
| 112 | + .min_meta_chunk_size_bytes = 256, | |
| 112 | 113 | .writeback_chunk_size_kbytes = 2, |
| 113 | 114 | .line_buffer_size_bits = 789504, |
| 114 | 115 | .is_line_buffer_bpp_fixed = 0, |
| @@ -383,13 +383,6 @@ bool dpp3_get_optimal_number_of_taps( · 382 unmodified lines | ||
| 383 | 383 | int min_taps_y, min_taps_c; |
| 384 | 384 | enum lb_memory_config lb_config; |
| 385 | 385 | |
| 386 | − /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ | |
| 387 | − if (scl_data->viewport.width != scl_data->h_active && | |
| 388 | − scl_data->viewport.height != scl_data->v_active && | |
| 389 | − dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && | |
| 390 | − scl_data->format == PIXEL_FORMAT_FP16) | |
| 391 | − return false; | |
| 392 | − | |
| 393 | 386 | if (scl_data->viewport.width > scl_data->h_active && |
| 394 | 387 | dpp->ctx->dc->debug.max_downscale_src_width != 0 && |
| 395 | 388 | scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) |
| @@ -1440,15 +1433,6 @@ bool dpp3_construct( · 1044 unmodified lines | ||
| 1440 | 1433 | dpp->tf_shift = tf_shift; |
| 1441 | 1434 | dpp->tf_mask = tf_mask; |
| 1442 | 1435 | |
| 1443 | − dpp->lb_pixel_depth_supported = | |
| 1444 | − LB_PIXEL_DEPTH_18BPP | | |
| 1445 | − LB_PIXEL_DEPTH_24BPP | | |
| 1446 | − LB_PIXEL_DEPTH_30BPP | | |
| 1447 | − LB_PIXEL_DEPTH_36BPP; | |
| 1448 | − | |
| 1449 | − dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; | |
| 1450 | − dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ | |
| 1451 | − | |
| 1452 | 1436 | return true; |
| 1453 | 1437 | } |
| 1454 | 1438 | |
| @@ -154,6 +154,7 @@ · 153 unmodified lines | ||
| 154 | 154 | SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \ |
| 155 | 155 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ |
| 156 | 156 | SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\ |
| 157 | + SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \ | |
| 157 | 158 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) |
| 158 | 159 | |
| 159 | 160 | #define DPP_REG_LIST_DCN30(id)\ |
| @@ -163,8 +164,6 @@ · 3 unmodified lines | ||
| 163 | 164 | SRI(CM_SHAPER_LUT_DATA, CM, id),\ |
| 164 | 165 | SRI(CM_MEM_PWR_CTRL2, CM, id), \ |
| 165 | 166 | SRI(CM_MEM_PWR_STATUS2, CM, id), \ |
| 166 | − SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \ | |
| 167 | − SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \ | |
| 168 | 167 | SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\ |
| 169 | 168 | SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\ |
| 170 | 169 | SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\ |
| @@ -1788,7 +1788,6 @@ static bool dcn30_split_stream_for_mpc_or_odm( · 1787 unmodified lines | ||
| 1788 | 1788 | } |
| 1789 | 1789 | pri_pipe->next_odm_pipe = sec_pipe; |
| 1790 | 1790 | sec_pipe->prev_odm_pipe = pri_pipe; |
| 1791 | − ASSERT(sec_pipe->top_pipe == NULL); | |
| 1792 | 1791 | |
| 1793 | 1792 | if (!sec_pipe->top_pipe) |
| 1794 | 1793 | sec_pipe->stream_res.opp = pool->opps[pipe_idx]; |
| @@ -2617,6 +2616,26 @@ static bool dcn30_resource_construct( · 822 unmodified lines | ||
| 2617 | 2616 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; |
| 2618 | 2617 | dc->caps.color.mpc.ocsc = 1; |
| 2619 | 2618 | |
| 2619 | + /* read VBIOS LTTPR caps */ | |
| 2620 | + { | |
| 2621 | + if (ctx->dc_bios->funcs->get_lttpr_caps) { | |
| 2622 | + enum bp_result bp_query_result; | |
| 2623 | + uint8_t is_vbios_lttpr_enable = 0; | |
| 2624 | + | |
| 2625 | + bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); | |
| 2626 | + dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; | |
| 2627 | + } | |
| 2628 | + | |
| 2629 | + if (ctx->dc_bios->funcs->get_lttpr_interop) { | |
| 2630 | + enum bp_result bp_query_result; | |
| 2631 | + uint8_t is_vbios_interop_enabled = 0; | |
| 2632 | + | |
| 2633 | + bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, | |
| 2634 | + &is_vbios_interop_enabled); | |
| 2635 | + dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; | |
| 2636 | + } | |
| 2637 | + } | |
| 2638 | + | |
| 2620 | 2639 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) |
| 2621 | 2640 | dc->debug = debug_defaults_drv; |
| 2622 | 2641 | else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { |
| @@ -1622,106 +1622,12 @@ static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b · 1621 unmodified lines | ||
| 1622 | 1622 | dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); |
| 1623 | 1623 | } |
| 1624 | 1624 | |
| 1625 | −static void calculate_wm_set_for_vlevel( | |
| 1626 | − int vlevel, | |
| 1627 | − struct wm_range_table_entry *table_entry, | |
| 1628 | − struct dcn_watermarks *wm_set, | |
| 1629 | − struct display_mode_lib *dml, | |
| 1630 | − display_e2e_pipe_params_st *pipes, | |
| 1631 | − int pipe_cnt) | |
| 1632 | −{ | |
| 1633 | − double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; | |
| 1634 | − | |
| 1635 | − ASSERT(vlevel < dml->soc.num_states); | |
| 1636 | − /* only pipe 0 is read for voltage and dcf/soc clocks */ | |
| 1637 | − pipes[0].clks_cfg.voltage = vlevel; | |
| 1638 | − pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; | |
| 1639 | − pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; | |
| 1640 | − | |
| 1641 | − dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; | |
| 1642 | − dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; | |
| 1643 | − dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; | |
| 1644 | − | |
| 1645 | − wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; | |
| 1646 | − wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; | |
| 1647 | − wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; | |
| 1648 | − wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; | |
| 1649 | − wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; | |
| 1650 | − wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; | |
| 1651 | − wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; | |
| 1652 | − wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; | |
| 1653 | − dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; | |
| 1654 | − | |
| 1655 | −} | |
| 1656 | − | |
| 1657 | −static void dcn301_calculate_wm_and_dlg( | |
| 1658 | − struct dc *dc, struct dc_state *context, | |
| 1659 | − display_e2e_pipe_params_st *pipes, | |
| 1660 | − int pipe_cnt, | |
| 1661 | − int vlevel_req) | |
| 1662 | −{ | |
| 1663 | − int i, pipe_idx; | |
| 1664 | − int vlevel, vlevel_max; | |
| 1665 | − struct wm_range_table_entry *table_entry; | |
| 1666 | − struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; | |
| 1667 | − | |
| 1668 | − ASSERT(bw_params); | |
| 1669 | − | |
| 1670 | − vlevel_max = bw_params->clk_table.num_entries - 1; | |
| 1671 | − | |
| 1672 | − /* WM Set D */ | |
| 1673 | − table_entry = &bw_params->wm_table.entries[WM_D]; | |
| 1674 | − if (table_entry->wm_type == WM_TYPE_RETRAINING) | |
| 1675 | − vlevel = 0; | |
| 1676 | − else | |
| 1677 | − vlevel = vlevel_max; | |
| 1678 | − calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, | |
| 1679 | − &context->bw_ctx.dml, pipes, pipe_cnt); | |
| 1680 | − /* WM Set C */ | |
| 1681 | − table_entry = &bw_params->wm_table.entries[WM_C]; | |
| 1682 | − vlevel = min(max(vlevel_req, 2), vlevel_max); | |
| 1683 | − calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, | |
| 1684 | − &context->bw_ctx.dml, pipes, pipe_cnt); | |
| 1685 | − /* WM Set B */ | |
| 1686 | − table_entry = &bw_params->wm_table.entries[WM_B]; | |
| 1687 | − vlevel = min(max(vlevel_req, 1), vlevel_max); | |
| 1688 | − calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, | |
| 1689 | − &context->bw_ctx.dml, pipes, pipe_cnt); | |
| 1690 | − | |
| 1691 | − /* WM Set A */ | |
| 1692 | − table_entry = &bw_params->wm_table.entries[WM_A]; | |
| 1693 | − vlevel = min(vlevel_req, vlevel_max); | |
| 1694 | − calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, | |
| 1695 | − &context->bw_ctx.dml, pipes, pipe_cnt); | |
| 1696 | − | |
| 1697 | − for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |
| 1698 | − if (!context->res_ctx.pipe_ctx[i].stream) | |
| 1699 | − continue; | |
| 1700 | − | |
| 1701 | − pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); | |
| 1702 | − pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |
| 1703 | − | |
| 1704 | − if (dc->config.forced_clocks) { | |
| 1705 | − pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; | |
| 1706 | − pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; | |
| 1707 | − } | |
| 1708 | − if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) | |
| 1709 | − pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; | |
| 1710 | − if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) | |
| 1711 | − pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; | |
| 1712 | − | |
| 1713 | − pipe_idx++; | |
| 1714 | − } | |
| 1715 | − | |
| 1716 | − dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); | |
| 1717 | −} | |
| 1718 | − | |
| 1719 | 1625 | static struct resource_funcs dcn301_res_pool_funcs = { |
| 1720 | 1626 | .destroy = dcn301_destroy_resource_pool, |
| 1721 | 1627 | .link_enc_create = dcn301_link_encoder_create, |
| 1722 | 1628 | .panel_cntl_create = dcn301_panel_cntl_create, |
| 1723 | 1629 | .validate_bandwidth = dcn30_validate_bandwidth, |
| 1724 | − .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, | |
| 1630 | + .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, | |
| 1725 | 1631 | .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, |
| 1726 | 1632 | .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, |
| 1727 | 1633 | .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, |
| @@ -1398,11 +1398,18 @@ void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param · 1397 unmodified lines | ||
| 1398 | 1398 | dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; |
| 1399 | 1399 | dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; |
| 1400 | 1400 | dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; |
| 1401 | − dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz; | |
| 1401 | + /* Populate from bw_params for DTBCLK, SOCCLK */ | |
| 1402 | + if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) | |
| 1403 | + dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz; | |
| 1404 | + else | |
| 1405 | + dcn3_02_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; | |
| 1406 | + if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) | |
| 1407 | + dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz; | |
| 1408 | + else | |
| 1409 | + dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; | |
| 1402 | 1410 | /* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */ |
| 1403 | − /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ | |
| 1411 | + /* FCLK, PHYCLK_D18, DSCCLK */ | |
| 1404 | 1412 | dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; |
| 1405 | − dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz; | |
| 1406 | 1413 | dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; |
| 1407 | 1414 | } |
| 1408 | 1415 | /* re-init DML with updated bb */ |
| @@ -146,8 +146,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = { · 145 unmodified lines | ||
| 146 | 146 | |
| 147 | 147 | .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ |
| 148 | 148 | .num_states = 1, |
| 149 | − .sr_exit_time_us = 26.5, | |
| 150 | − .sr_enter_plus_exit_time_us = 31, | |
| 149 | + .sr_exit_time_us = 35.5, | |
| 150 | + .sr_enter_plus_exit_time_us = 40, | |
| 151 | 151 | .urgent_latency_us = 4.0, |
| 152 | 152 | .urgent_latency_pixel_data_only_us = 4.0, |
| 153 | 153 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, |
| @@ -1326,11 +1326,18 @@ void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param · 1172 unmodified lines | ||
| 1326 | 1326 | dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; |
| 1327 | 1327 | dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; |
| 1328 | 1328 | dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; |
| 1329 | − dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz; | |
| 1329 | + /* Populate from bw_params for DTBCLK, SOCCLK */ | |
| 1330 | + if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) | |
| 1331 | + dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz; | |
| 1332 | + else | |
| 1333 | + dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; | |
| 1334 | + if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) | |
| 1335 | + dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz; | |
| 1336 | + else | |
| 1337 | + dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; | |
| 1330 | 1338 | /* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */ |
| 1331 | − /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ | |
| 1339 | + /* FCLK, PHYCLK_D18, DSCCLK */ | |
| 1332 | 1340 | dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; |
| 1333 | − dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz; | |
| 1334 | 1341 | dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; |
| 1335 | 1342 | } |
| 1336 | 1343 | /* re-init DML with updated bb */ |
| @@ -47,6 +47,7 @@ · 46 unmodified lines | ||
| 47 | 47 | #include "dce/dmub_outbox.h" |
| 48 | 48 | #include "dc_link_dp.h" |
| 49 | 49 | #include "inc/link_dpcd.h" |
| 50 | +#include "dcn10/dcn10_hw_sequencer.h" | |
| 50 | 51 | |
| 51 | 52 | #define DC_LOGGER_INIT(logger) |
| 52 | 53 | |
| @@ -390,7 +391,7 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) · 337 unmodified lines | ||
| 390 | 391 | is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); |
| 391 | 392 | is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); |
| 392 | 393 | |
| 393 | − if (!is_hdmi_tmds) | |
| 394 | + if (!is_hdmi_tmds && !is_dp) | |
| 394 | 395 | return; |
| 395 | 396 | |
| 396 | 397 | if (is_hdmi_tmds) |
| @@ -403,6 +404,18 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) · 6 unmodified lines | ||
| 403 | 404 | &pipe_ctx->stream_res.encoder_info_frame); |
| 404 | 405 | } |
| 405 | 406 | } |
| 407 | +void dcn31_z10_save_init(struct dc *dc) | |
| 408 | +{ | |
| 409 | + union dmub_rb_cmd cmd; | |
| 410 | + | |
| 411 | + memset(&cmd, 0, sizeof(cmd)); | |
| 412 | + cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; | |
| 413 | + cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; | |
| 414 | + | |
| 415 | + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); | |
| 416 | + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); | |
| 417 | + dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); | |
| 418 | +} | |
| 406 | 419 | |
| 407 | 420 | void dcn31_z10_restore(struct dc *dc) |
| 408 | 421 | { |
| @@ -594,3 +607,20 @@ bool dcn31_is_abm_supported(struct dc *dc, · 185 unmodified lines | ||
| 594 | 607 | } |
| 595 | 608 | return false; |
| 596 | 609 | } |
| 610 | + | |
| 611 | +static void apply_riommu_invalidation_wa(struct dc *dc) | |
| 612 | +{ | |
| 613 | + struct dce_hwseq *hws = dc->hwseq; | |
| 614 | + | |
| 615 | + if (!hws->wa.early_riommu_invalidation) | |
| 616 | + return; | |
| 617 | + | |
| 618 | + REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, 0); | |
| 619 | +} | |
| 620 | + | |
| 621 | +void dcn31_init_pipes(struct dc *dc, struct dc_state *context) | |
| 622 | +{ | |
| 623 | + dcn10_init_pipes(dc, context); | |
| 624 | + apply_riommu_invalidation_wa(dc); | |
| 625 | + | |
| 626 | +} | |
| @@ -44,6 +44,7 @@ void dcn31_enable_power_gating_plane( · 43 unmodified lines | ||
| 44 | 44 | void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx); |
| 45 | 45 | |
| 46 | 46 | void dcn31_z10_restore(struct dc *dc); |
| 47 | +void dcn31_z10_save_init(struct dc *dc); | |
| 47 | 48 | |
| 48 | 49 | void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); |
| 49 | 50 | int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config); |
| @@ -52,5 +53,6 @@ void dcn31_reset_hw_ctx_wrap( · 2 unmodified lines | ||
| 52 | 53 | struct dc_state *context); |
| 53 | 54 | bool dcn31_is_abm_supported(struct dc *dc, |
| 54 | 55 | struct dc_state *context, struct dc_stream_state *stream); |
| 56 | +void dcn31_init_pipes(struct dc *dc, struct dc_state *context); | |
| 55 | 57 | |
| 56 | 58 | #endif /* __DC_HWSS_DCN31_H__ */ |
| @@ -93,18 +93,18 @@ static const struct hw_sequencer_funcs dcn31_funcs = { · 92 unmodified lines | ||
| 93 | 93 | .set_flip_control_gsl = dcn20_set_flip_control_gsl, |
| 94 | 94 | .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, |
| 95 | 95 | .calc_vupdate_position = dcn10_calc_vupdate_position, |
| 96 | − .apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations, | |
| 97 | 96 | .set_backlight_level = dcn21_set_backlight_level, |
| 98 | 97 | .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, |
| 99 | 98 | .set_pipe = dcn21_set_pipe, |
| 100 | 99 | .z10_restore = dcn31_z10_restore, |
| 100 | + .z10_save_init = dcn31_z10_save_init, | |
| 101 | 101 | .is_abm_supported = dcn31_is_abm_supported, |
| 102 | 102 | .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, |
| 103 | 103 | .update_visual_confirm_color = dcn20_update_visual_confirm_color, |
| 104 | 104 | }; |
| 105 | 105 | |
| 106 | 106 | static const struct hwseq_private_funcs dcn31_private_funcs = { |
| 107 | − .init_pipes = dcn10_init_pipes, | |
| 107 | + .init_pipes = dcn31_init_pipes, | |
| 108 | 108 | .update_plane_addr = dcn20_update_plane_addr, |
| 109 | 109 | .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, |
| 110 | 110 | .update_mpcc = dcn20_update_mpcc, |
| @@ -220,6 +220,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { · 219 unmodified lines | ||
| 220 | 220 | .sr_exit_z8_time_us = 402.0, |
| 221 | 221 | .sr_enter_plus_exit_z8_time_us = 520.0, |
| 222 | 222 | .writeback_latency_us = 12.0, |
| 223 | + .dram_channel_width_bytes = 4, | |
| 223 | 224 | .round_trip_ping_latency_dcfclk_cycles = 106, |
| 224 | 225 | .urgent_latency_pixel_data_only_us = 4.0, |
| 225 | 226 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, |
| @@ -741,6 +742,7 @@ static const struct dccg_mask dccg_mask = { · 515 unmodified lines | ||
| 741 | 742 | |
| 742 | 743 | #define HWSEQ_DCN31_REG_LIST()\ |
| 743 | 744 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
| 745 | + SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ | |
| 744 | 746 | SR(DIO_MEM_PWR_CTRL), \ |
| 745 | 747 | SR(ODM_MEM_PWR_CTRL3), \ |
| 746 | 748 | SR(DMU_MEM_PWR_CNTL), \ |
| @@ -801,6 +803,7 @@ static const struct dce_hwseq_registers hwseq_reg = { · 54 unmodified lines | ||
| 801 | 803 | #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ |
| 802 | 804 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
| 803 | 805 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
| 806 | + HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ | |
| 804 | 807 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ |
| 805 | 808 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ |
| 806 | 809 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ |
| @@ -1299,6 +1302,7 @@ static struct dce_hwseq *dcn31_hwseq_create( · 492 unmodified lines | ||
| 1299 | 1302 | hws->regs = &hwseq_reg; |
| 1300 | 1303 | hws->shifts = &hwseq_shift; |
| 1301 | 1304 | hws->masks = &hwseq_mask; |
| 1305 | + hws->wa.early_riommu_invalidation = true; | |
| 1302 | 1306 | } |
| 1303 | 1307 | return hws; |
| 1304 | 1308 | } |
| @@ -1964,6 +1968,22 @@ static bool dcn31_resource_construct( · 659 unmodified lines | ||
| 1964 | 1968 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; |
| 1965 | 1969 | dc->caps.color.mpc.ocsc = 1; |
| 1966 | 1970 | |
| 1971 | + /* read VBIOS LTTPR caps */ | |
| 1972 | + { | |
| 1973 | + if (ctx->dc_bios->funcs->get_lttpr_caps) { | |
| 1974 | + enum bp_result bp_query_result; | |
| 1975 | + uint8_t is_vbios_lttpr_enable = 0; | |
| 1976 | + | |
| 1977 | + bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); | |
| 1978 | + dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; | |
| 1979 | + } | |
| 1980 | + | |
| 1981 | + /* interop bit is implicit */ | |
| 1982 | + { | |
| 1983 | + dc->caps.vbios_lttpr_aware = true; | |
| 1984 | + } | |
| 1985 | + } | |
| 1986 | + | |
| 1967 | 1987 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) |
| 1968 | 1988 | dc->debug = debug_defaults_drv; |
| 1969 | 1989 | else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { |
| @@ -841,6 +841,9 @@ static bool CalculatePrefetchSchedule( · 840 unmodified lines | ||
| 841 | 841 | else |
| 842 | 842 | *DestinationLinesForPrefetch = dst_y_prefetch_equ; |
| 843 | 843 | |
| 844 | + // Limit to prevent overflow in DST_Y_PREFETCH register | |
| 845 | + *DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch, 63.75); | |
| 846 | + | |
| 844 | 847 | dml_print("DML: VStartup: %d\n", VStartup); |
| 845 | 848 | dml_print("DML: TCalc: %f\n", TCalc); |
| 846 | 849 | dml_print("DML: TWait: %f\n", TWait); |
| @@ -4889,7 +4892,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 4042 unmodified lines | ||
| 4889 | 4892 | } |
| 4890 | 4893 | } while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true) |
| 4891 | 4894 | && (mode_lib->vba.NextMaxVStartup != mode_lib->vba.MaxMaxVStartup[0][0] |
| 4892 | − || mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode)); | |
| 4895 | + || mode_lib->vba.NextPrefetchMode <= mode_lib->vba.MaxPrefetchMode)); | |
| 4893 | 4896 | |
| 4894 | 4897 | if (locals->PrefetchSupported[i][j] == true && locals->VRatioInPrefetchSupported[i][j] == true) { |
| 4895 | 4898 | mode_lib->vba.BandwidthAvailableForImmediateFlip = locals->ReturnBWPerState[i][0]; |
| @@ -289,6 +289,9 @@ struct dpp_caps { · 288 unmodified lines | ||
| 289 | 289 | /* DSCL processing pixel data in fixed or float format */ |
| 290 | 290 | enum dscl_data_processing_format dscl_data_proc_format; |
| 291 | 291 | |
| 292 | + /* max LB partitions */ | |
| 293 | + unsigned int max_lb_partitions; | |
| 294 | + | |
| 292 | 295 | /* Calculates the number of partitions in the line buffer. |
| 293 | 296 | * The implementation of this function is overloaded for |
| 294 | 297 | * different versions of DSCL LB. |
| @@ -237,6 +237,7 @@ struct hw_sequencer_funcs { · 236 unmodified lines | ||
| 237 | 237 | int width, int height, int offset); |
| 238 | 238 | |
| 239 | 239 | void (*z10_restore)(struct dc *dc); |
| 240 | + void (*z10_save_init)(struct dc *dc); | |
| 240 | 241 | |
| 241 | 242 | void (*update_visual_confirm_color)(struct dc *dc, |
| 242 | 243 | struct pipe_ctx *pipe_ctx, |
| @@ -41,6 +41,7 @@ struct dce_hwseq_wa { · 40 unmodified lines | ||
| 41 | 41 | bool DEGVIDCN10_254; |
| 42 | 42 | bool DEGVIDCN21; |
| 43 | 43 | bool disallow_self_refresh_during_multi_plane_transition; |
| 44 | + bool early_riommu_invalidation; | |
| 44 | 45 | }; |
| 45 | 46 | |
| 46 | 47 | struct hwseq_wa_state { |
| @@ -856,6 +856,11 @@ enum dmub_cmd_idle_opt_type { · 855 unmodified lines | ||
| 856 | 856 | * DCN hardware restore. |
| 857 | 857 | */ |
| 858 | 858 | DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, |
| 859 | + | |
| 860 | + /** | |
| 861 | + * DCN hardware save. | |
| 862 | + */ | |
| 863 | + DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 | |
| 859 | 864 | }; |
| 860 | 865 | |
| 861 | 866 | /** |
| @@ -267,11 +267,13 @@ void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) · 266 unmodified lines | ||
| 267 | 267 | |
| 268 | 268 | bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub) |
| 269 | 269 | { |
| 270 | − uint32_t is_hw_init; | |
| 270 | + union dmub_fw_boot_status status; | |
| 271 | + uint32_t is_enable; | |
| 271 | 272 | |
| 272 | − REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); | |
| 273 | + status.all = REG_READ(DMCUB_SCRATCH0); | |
| 274 | + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); | |
| 273 | 275 | |
| 274 | − return is_hw_init != 0; | |
| 276 | + return is_enable != 0 && status.bits.dal_fw; | |
| 275 | 277 | } |
| 276 | 278 | |
| 277 | 279 | bool dmub_dcn31_is_supported(struct dmub_srv *dmub) |
| @@ -1,355 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright 2020 Advanced Micro Devices, Inc. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − * | |
| 22 | − * | |
| 23 | − */ | |
| 24 | −#ifndef _mp_13_0_1_OFFSET_HEADER | |
| 25 | −#define _mp_13_0_1_OFFSET_HEADER | |
| 26 | − | |
| 27 | − | |
| 28 | − | |
| 29 | −// addressBlock: mp_SmuMp0_SmnDec | |
| 30 | −// base address: 0x0 | |
| 31 | −#define regMP0_SMN_C2PMSG_32 0x0060 | |
| 32 | −#define regMP0_SMN_C2PMSG_32_BASE_IDX 0 | |
| 33 | −#define regMP0_SMN_C2PMSG_33 0x0061 | |
| 34 | −#define regMP0_SMN_C2PMSG_33_BASE_IDX 0 | |
| 35 | −#define regMP0_SMN_C2PMSG_34 0x0062 | |
| 36 | −#define regMP0_SMN_C2PMSG_34_BASE_IDX 0 | |
| 37 | −#define regMP0_SMN_C2PMSG_35 0x0063 | |
| 38 | −#define regMP0_SMN_C2PMSG_35_BASE_IDX 0 | |
| 39 | −#define regMP0_SMN_C2PMSG_36 0x0064 | |
| 40 | −#define regMP0_SMN_C2PMSG_36_BASE_IDX 0 | |
| 41 | −#define regMP0_SMN_C2PMSG_37 0x0065 | |
| 42 | −#define regMP0_SMN_C2PMSG_37_BASE_IDX 0 | |
| 43 | −#define regMP0_SMN_C2PMSG_38 0x0066 | |
| 44 | −#define regMP0_SMN_C2PMSG_38_BASE_IDX 0 | |
| 45 | −#define regMP0_SMN_C2PMSG_39 0x0067 | |
| 46 | −#define regMP0_SMN_C2PMSG_39_BASE_IDX 0 | |
| 47 | −#define regMP0_SMN_C2PMSG_40 0x0068 | |
| 48 | −#define regMP0_SMN_C2PMSG_40_BASE_IDX 0 | |
| 49 | −#define regMP0_SMN_C2PMSG_41 0x0069 | |
| 50 | −#define regMP0_SMN_C2PMSG_41_BASE_IDX 0 | |
| 51 | −#define regMP0_SMN_C2PMSG_42 0x006a | |
| 52 | −#define regMP0_SMN_C2PMSG_42_BASE_IDX 0 | |
| 53 | −#define regMP0_SMN_C2PMSG_43 0x006b | |
| 54 | −#define regMP0_SMN_C2PMSG_43_BASE_IDX 0 | |
| 55 | −#define regMP0_SMN_C2PMSG_44 0x006c | |
| 56 | −#define regMP0_SMN_C2PMSG_44_BASE_IDX 0 | |
| 57 | −#define regMP0_SMN_C2PMSG_45 0x006d | |
| 58 | −#define regMP0_SMN_C2PMSG_45_BASE_IDX 0 | |
| 59 | −#define regMP0_SMN_C2PMSG_46 0x006e | |
| 60 | −#define regMP0_SMN_C2PMSG_46_BASE_IDX 0 | |
| 61 | −#define regMP0_SMN_C2PMSG_47 0x006f | |
| 62 | −#define regMP0_SMN_C2PMSG_47_BASE_IDX 0 | |
| 63 | −#define regMP0_SMN_C2PMSG_48 0x0070 | |
| 64 | −#define regMP0_SMN_C2PMSG_48_BASE_IDX 0 | |
| 65 | −#define regMP0_SMN_C2PMSG_49 0x0071 | |
| 66 | −#define regMP0_SMN_C2PMSG_49_BASE_IDX 0 | |
| 67 | −#define regMP0_SMN_C2PMSG_50 0x0072 | |
| 68 | −#define regMP0_SMN_C2PMSG_50_BASE_IDX 0 | |
| 69 | −#define regMP0_SMN_C2PMSG_51 0x0073 | |
| 70 | −#define regMP0_SMN_C2PMSG_51_BASE_IDX 0 | |
| 71 | −#define regMP0_SMN_C2PMSG_52 0x0074 | |
| 72 | −#define regMP0_SMN_C2PMSG_52_BASE_IDX 0 | |
| 73 | −#define regMP0_SMN_C2PMSG_53 0x0075 | |
| 74 | −#define regMP0_SMN_C2PMSG_53_BASE_IDX 0 | |
| 75 | −#define regMP0_SMN_C2PMSG_54 0x0076 | |
| 76 | −#define regMP0_SMN_C2PMSG_54_BASE_IDX 0 | |
| 77 | −#define regMP0_SMN_C2PMSG_55 0x0077 | |
| 78 | −#define regMP0_SMN_C2PMSG_55_BASE_IDX 0 | |
| 79 | −#define regMP0_SMN_C2PMSG_56 0x0078 | |
| 80 | −#define regMP0_SMN_C2PMSG_56_BASE_IDX 0 | |
| 81 | −#define regMP0_SMN_C2PMSG_57 0x0079 | |
| 82 | −#define regMP0_SMN_C2PMSG_57_BASE_IDX 0 | |
| 83 | −#define regMP0_SMN_C2PMSG_58 0x007a | |
| 84 | −#define regMP0_SMN_C2PMSG_58_BASE_IDX 0 | |
| 85 | −#define regMP0_SMN_C2PMSG_59 0x007b | |
| 86 | −#define regMP0_SMN_C2PMSG_59_BASE_IDX 0 | |
| 87 | −#define regMP0_SMN_C2PMSG_60 0x007c | |
| 88 | −#define regMP0_SMN_C2PMSG_60_BASE_IDX 0 | |
| 89 | −#define regMP0_SMN_C2PMSG_61 0x007d | |
| 90 | −#define regMP0_SMN_C2PMSG_61_BASE_IDX 0 | |
| 91 | −#define regMP0_SMN_C2PMSG_62 0x007e | |
| 92 | −#define regMP0_SMN_C2PMSG_62_BASE_IDX 0 | |
| 93 | −#define regMP0_SMN_C2PMSG_63 0x007f | |
| 94 | −#define regMP0_SMN_C2PMSG_63_BASE_IDX 0 | |
| 95 | −#define regMP0_SMN_C2PMSG_64 0x0080 | |
| 96 | −#define regMP0_SMN_C2PMSG_64_BASE_IDX 0 | |
| 97 | −#define regMP0_SMN_C2PMSG_65 0x0081 | |
| 98 | −#define regMP0_SMN_C2PMSG_65_BASE_IDX 0 | |
| 99 | −#define regMP0_SMN_C2PMSG_66 0x0082 | |
| 100 | −#define regMP0_SMN_C2PMSG_66_BASE_IDX 0 | |
| 101 | −#define regMP0_SMN_C2PMSG_67 0x0083 | |
| 102 | −#define regMP0_SMN_C2PMSG_67_BASE_IDX 0 | |
| 103 | −#define regMP0_SMN_C2PMSG_68 0x0084 | |
| 104 | −#define regMP0_SMN_C2PMSG_68_BASE_IDX 0 | |
| 105 | −#define regMP0_SMN_C2PMSG_69 0x0085 | |
| 106 | −#define regMP0_SMN_C2PMSG_69_BASE_IDX 0 | |
| 107 | −#define regMP0_SMN_C2PMSG_70 0x0086 | |
| 108 | −#define regMP0_SMN_C2PMSG_70_BASE_IDX 0 | |
| 109 | −#define regMP0_SMN_C2PMSG_71 0x0087 | |
| 110 | −#define regMP0_SMN_C2PMSG_71_BASE_IDX 0 | |
| 111 | −#define regMP0_SMN_C2PMSG_72 0x0088 | |
| 112 | −#define regMP0_SMN_C2PMSG_72_BASE_IDX 0 | |
| 113 | −#define regMP0_SMN_C2PMSG_73 0x0089 | |
| 114 | −#define regMP0_SMN_C2PMSG_73_BASE_IDX 0 | |
| 115 | −#define regMP0_SMN_C2PMSG_74 0x008a | |
| 116 | −#define regMP0_SMN_C2PMSG_74_BASE_IDX 0 | |
| 117 | −#define regMP0_SMN_C2PMSG_75 0x008b | |
| 118 | −#define regMP0_SMN_C2PMSG_75_BASE_IDX 0 | |
| 119 | −#define regMP0_SMN_C2PMSG_76 0x008c | |
| 120 | −#define regMP0_SMN_C2PMSG_76_BASE_IDX 0 | |
| 121 | −#define regMP0_SMN_C2PMSG_77 0x008d | |
| 122 | −#define regMP0_SMN_C2PMSG_77_BASE_IDX 0 | |
| 123 | −#define regMP0_SMN_C2PMSG_78 0x008e | |
| 124 | −#define regMP0_SMN_C2PMSG_78_BASE_IDX 0 | |
| 125 | −#define regMP0_SMN_C2PMSG_79 0x008f | |
| 126 | −#define regMP0_SMN_C2PMSG_79_BASE_IDX 0 | |
| 127 | −#define regMP0_SMN_C2PMSG_80 0x0090 | |
| 128 | −#define regMP0_SMN_C2PMSG_80_BASE_IDX 0 | |
| 129 | −#define regMP0_SMN_C2PMSG_81 0x0091 | |
| 130 | −#define regMP0_SMN_C2PMSG_81_BASE_IDX 0 | |
| 131 | −#define regMP0_SMN_C2PMSG_82 0x0092 | |
| 132 | −#define regMP0_SMN_C2PMSG_82_BASE_IDX 0 | |
| 133 | −#define regMP0_SMN_C2PMSG_83 0x0093 | |
| 134 | −#define regMP0_SMN_C2PMSG_83_BASE_IDX 0 | |
| 135 | −#define regMP0_SMN_C2PMSG_84 0x0094 | |
| 136 | −#define regMP0_SMN_C2PMSG_84_BASE_IDX 0 | |
| 137 | −#define regMP0_SMN_C2PMSG_85 0x0095 | |
| 138 | −#define regMP0_SMN_C2PMSG_85_BASE_IDX 0 | |
| 139 | −#define regMP0_SMN_C2PMSG_86 0x0096 | |
| 140 | −#define regMP0_SMN_C2PMSG_86_BASE_IDX 0 | |
| 141 | −#define regMP0_SMN_C2PMSG_87 0x0097 | |
| 142 | −#define regMP0_SMN_C2PMSG_87_BASE_IDX 0 | |
| 143 | −#define regMP0_SMN_C2PMSG_88 0x0098 | |
| 144 | −#define regMP0_SMN_C2PMSG_88_BASE_IDX 0 | |
| 145 | −#define regMP0_SMN_C2PMSG_89 0x0099 | |
| 146 | −#define regMP0_SMN_C2PMSG_89_BASE_IDX 0 | |
| 147 | −#define regMP0_SMN_C2PMSG_90 0x009a | |
| 148 | −#define regMP0_SMN_C2PMSG_90_BASE_IDX 0 | |
| 149 | −#define regMP0_SMN_C2PMSG_91 0x009b | |
| 150 | −#define regMP0_SMN_C2PMSG_91_BASE_IDX 0 | |
| 151 | −#define regMP0_SMN_C2PMSG_92 0x009c | |
| 152 | −#define regMP0_SMN_C2PMSG_92_BASE_IDX 0 | |
| 153 | −#define regMP0_SMN_C2PMSG_93 0x009d | |
| 154 | −#define regMP0_SMN_C2PMSG_93_BASE_IDX 0 | |
| 155 | −#define regMP0_SMN_C2PMSG_94 0x009e | |
| 156 | −#define regMP0_SMN_C2PMSG_94_BASE_IDX 0 | |
| 157 | −#define regMP0_SMN_C2PMSG_95 0x009f | |
| 158 | −#define regMP0_SMN_C2PMSG_95_BASE_IDX 0 | |
| 159 | −#define regMP0_SMN_C2PMSG_96 0x00a0 | |
| 160 | −#define regMP0_SMN_C2PMSG_96_BASE_IDX 0 | |
| 161 | −#define regMP0_SMN_C2PMSG_97 0x00a1 | |
| 162 | −#define regMP0_SMN_C2PMSG_97_BASE_IDX 0 | |
| 163 | −#define regMP0_SMN_C2PMSG_98 0x00a2 | |
| 164 | −#define regMP0_SMN_C2PMSG_98_BASE_IDX 0 | |
| 165 | −#define regMP0_SMN_C2PMSG_99 0x00a3 | |
| 166 | −#define regMP0_SMN_C2PMSG_99_BASE_IDX 0 | |
| 167 | −#define regMP0_SMN_C2PMSG_100 0x00a4 | |
| 168 | −#define regMP0_SMN_C2PMSG_100_BASE_IDX 0 | |
| 169 | −#define regMP0_SMN_C2PMSG_101 0x00a5 | |
| 170 | −#define regMP0_SMN_C2PMSG_101_BASE_IDX 0 | |
| 171 | −#define regMP0_SMN_C2PMSG_102 0x00a6 | |
| 172 | −#define regMP0_SMN_C2PMSG_102_BASE_IDX 0 | |
| 173 | −#define regMP0_SMN_C2PMSG_103 0x00a7 | |
| 174 | −#define regMP0_SMN_C2PMSG_103_BASE_IDX 0 | |
| 175 | −#define regMP0_SMN_IH_CREDIT 0x00c1 | |
| 176 | −#define regMP0_SMN_IH_CREDIT_BASE_IDX 0 | |
| 177 | −#define regMP0_SMN_IH_SW_INT 0x00c2 | |
| 178 | −#define regMP0_SMN_IH_SW_INT_BASE_IDX 0 | |
| 179 | −#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3 | |
| 180 | −#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 | |
| 181 | − | |
| 182 | − | |
| 183 | −// addressBlock: mp_SmuMp1_SmnDec | |
| 184 | −// base address: 0x0 | |
| 185 | −#define regMP1_SMN_C2PMSG_32 0x0260 | |
| 186 | −#define regMP1_SMN_C2PMSG_32_BASE_IDX 0 | |
| 187 | −#define regMP1_SMN_C2PMSG_33 0x0261 | |
| 188 | −#define regMP1_SMN_C2PMSG_33_BASE_IDX 0 | |
| 189 | −#define regMP1_SMN_C2PMSG_34 0x0262 | |
| 190 | −#define regMP1_SMN_C2PMSG_34_BASE_IDX 0 | |
| 191 | −#define regMP1_SMN_C2PMSG_35 0x0263 | |
| 192 | −#define regMP1_SMN_C2PMSG_35_BASE_IDX 0 | |
| 193 | −#define regMP1_SMN_C2PMSG_36 0x0264 | |
| 194 | −#define regMP1_SMN_C2PMSG_36_BASE_IDX 0 | |
| 195 | −#define regMP1_SMN_C2PMSG_37 0x0265 | |
| 196 | −#define regMP1_SMN_C2PMSG_37_BASE_IDX 0 | |
| 197 | −#define regMP1_SMN_C2PMSG_38 0x0266 | |
| 198 | −#define regMP1_SMN_C2PMSG_38_BASE_IDX 0 | |
| 199 | −#define regMP1_SMN_C2PMSG_39 0x0267 | |
| 200 | −#define regMP1_SMN_C2PMSG_39_BASE_IDX 0 | |
| 201 | −#define regMP1_SMN_C2PMSG_40 0x0268 | |
| 202 | −#define regMP1_SMN_C2PMSG_40_BASE_IDX 0 | |
| 203 | −#define regMP1_SMN_C2PMSG_41 0x0269 | |
| 204 | −#define regMP1_SMN_C2PMSG_41_BASE_IDX 0 | |
| 205 | −#define regMP1_SMN_C2PMSG_42 0x026a | |
| 206 | −#define regMP1_SMN_C2PMSG_42_BASE_IDX 0 | |
| 207 | −#define regMP1_SMN_C2PMSG_43 0x026b | |
| 208 | −#define regMP1_SMN_C2PMSG_43_BASE_IDX 0 | |
| 209 | −#define regMP1_SMN_C2PMSG_44 0x026c | |
| 210 | −#define regMP1_SMN_C2PMSG_44_BASE_IDX 0 | |
| 211 | −#define regMP1_SMN_C2PMSG_45 0x026d | |
| 212 | −#define regMP1_SMN_C2PMSG_45_BASE_IDX 0 | |
| 213 | −#define regMP1_SMN_C2PMSG_46 0x026e | |
| 214 | −#define regMP1_SMN_C2PMSG_46_BASE_IDX 0 | |
| 215 | −#define regMP1_SMN_C2PMSG_47 0x026f | |
| 216 | −#define regMP1_SMN_C2PMSG_47_BASE_IDX 0 | |
| 217 | −#define regMP1_SMN_C2PMSG_48 0x0270 | |
| 218 | −#define regMP1_SMN_C2PMSG_48_BASE_IDX 0 | |
| 219 | −#define regMP1_SMN_C2PMSG_49 0x0271 | |
| 220 | −#define regMP1_SMN_C2PMSG_49_BASE_IDX 0 | |
| 221 | −#define regMP1_SMN_C2PMSG_50 0x0272 | |
| 222 | −#define regMP1_SMN_C2PMSG_50_BASE_IDX 0 | |
| 223 | −#define regMP1_SMN_C2PMSG_51 0x0273 | |
| 224 | −#define regMP1_SMN_C2PMSG_51_BASE_IDX 0 | |
| 225 | −#define regMP1_SMN_C2PMSG_52 0x0274 | |
| 226 | −#define regMP1_SMN_C2PMSG_52_BASE_IDX 0 | |
| 227 | −#define regMP1_SMN_C2PMSG_53 0x0275 | |
| 228 | −#define regMP1_SMN_C2PMSG_53_BASE_IDX 0 | |
| 229 | −#define regMP1_SMN_C2PMSG_54 0x0276 | |
| 230 | −#define regMP1_SMN_C2PMSG_54_BASE_IDX 0 | |
| 231 | −#define regMP1_SMN_C2PMSG_55 0x0277 | |
| 232 | −#define regMP1_SMN_C2PMSG_55_BASE_IDX 0 | |
| 233 | −#define regMP1_SMN_C2PMSG_56 0x0278 | |
| 234 | −#define regMP1_SMN_C2PMSG_56_BASE_IDX 0 | |
| 235 | −#define regMP1_SMN_C2PMSG_57 0x0279 | |
| 236 | −#define regMP1_SMN_C2PMSG_57_BASE_IDX 0 | |
| 237 | −#define regMP1_SMN_C2PMSG_58 0x027a | |
| 238 | −#define regMP1_SMN_C2PMSG_58_BASE_IDX 0 | |
| 239 | −#define regMP1_SMN_C2PMSG_59 0x027b | |
| 240 | −#define regMP1_SMN_C2PMSG_59_BASE_IDX 0 | |
| 241 | −#define regMP1_SMN_C2PMSG_60 0x027c | |
| 242 | −#define regMP1_SMN_C2PMSG_60_BASE_IDX 0 | |
| 243 | −#define regMP1_SMN_C2PMSG_61 0x027d | |
| 244 | −#define regMP1_SMN_C2PMSG_61_BASE_IDX 0 | |
| 245 | −#define regMP1_SMN_C2PMSG_62 0x027e | |
| 246 | −#define regMP1_SMN_C2PMSG_62_BASE_IDX 0 | |
| 247 | −#define regMP1_SMN_C2PMSG_63 0x027f | |
| 248 | −#define regMP1_SMN_C2PMSG_63_BASE_IDX 0 | |
| 249 | −#define regMP1_SMN_C2PMSG_64 0x0280 | |
| 250 | −#define regMP1_SMN_C2PMSG_64_BASE_IDX 0 | |
| 251 | −#define regMP1_SMN_C2PMSG_65 0x0281 | |
| 252 | −#define regMP1_SMN_C2PMSG_65_BASE_IDX 0 | |
| 253 | −#define regMP1_SMN_C2PMSG_66 0x0282 | |
| 254 | −#define regMP1_SMN_C2PMSG_66_BASE_IDX 0 | |
| 255 | −#define regMP1_SMN_C2PMSG_67 0x0283 | |
| 256 | −#define regMP1_SMN_C2PMSG_67_BASE_IDX 0 | |
| 257 | −#define regMP1_SMN_C2PMSG_68 0x0284 | |
| 258 | −#define regMP1_SMN_C2PMSG_68_BASE_IDX 0 | |
| 259 | −#define regMP1_SMN_C2PMSG_69 0x0285 | |
| 260 | −#define regMP1_SMN_C2PMSG_69_BASE_IDX 0 | |
| 261 | −#define regMP1_SMN_C2PMSG_70 0x0286 | |
| 262 | −#define regMP1_SMN_C2PMSG_70_BASE_IDX 0 | |
| 263 | −#define regMP1_SMN_C2PMSG_71 0x0287 | |
| 264 | −#define regMP1_SMN_C2PMSG_71_BASE_IDX 0 | |
| 265 | −#define regMP1_SMN_C2PMSG_72 0x0288 | |
| 266 | −#define regMP1_SMN_C2PMSG_72_BASE_IDX 0 | |
| 267 | −#define regMP1_SMN_C2PMSG_73 0x0289 | |
| 268 | −#define regMP1_SMN_C2PMSG_73_BASE_IDX 0 | |
| 269 | −#define regMP1_SMN_C2PMSG_74 0x028a | |
| 270 | −#define regMP1_SMN_C2PMSG_74_BASE_IDX 0 | |
| 271 | −#define regMP1_SMN_C2PMSG_75 0x028b | |
| 272 | −#define regMP1_SMN_C2PMSG_75_BASE_IDX 0 | |
| 273 | −#define regMP1_SMN_C2PMSG_76 0x028c | |
| 274 | −#define regMP1_SMN_C2PMSG_76_BASE_IDX 0 | |
| 275 | −#define regMP1_SMN_C2PMSG_77 0x028d | |
| 276 | −#define regMP1_SMN_C2PMSG_77_BASE_IDX 0 | |
| 277 | −#define regMP1_SMN_C2PMSG_78 0x028e | |
| 278 | −#define regMP1_SMN_C2PMSG_78_BASE_IDX 0 | |
| 279 | −#define regMP1_SMN_C2PMSG_79 0x028f | |
| 280 | −#define regMP1_SMN_C2PMSG_79_BASE_IDX 0 | |
| 281 | −#define regMP1_SMN_C2PMSG_80 0x0290 | |
| 282 | −#define regMP1_SMN_C2PMSG_80_BASE_IDX 0 | |
| 283 | −#define regMP1_SMN_C2PMSG_81 0x0291 | |
| 284 | −#define regMP1_SMN_C2PMSG_81_BASE_IDX 0 | |
| 285 | −#define regMP1_SMN_C2PMSG_82 0x0292 | |
| 286 | −#define regMP1_SMN_C2PMSG_82_BASE_IDX 0 | |
| 287 | −#define regMP1_SMN_C2PMSG_83 0x0293 | |
| 288 | −#define regMP1_SMN_C2PMSG_83_BASE_IDX 0 | |
| 289 | −#define regMP1_SMN_C2PMSG_84 0x0294 | |
| 290 | −#define regMP1_SMN_C2PMSG_84_BASE_IDX 0 | |
| 291 | −#define regMP1_SMN_C2PMSG_85 0x0295 | |
| 292 | −#define regMP1_SMN_C2PMSG_85_BASE_IDX 0 | |
| 293 | −#define regMP1_SMN_C2PMSG_86 0x0296 | |
| 294 | −#define regMP1_SMN_C2PMSG_86_BASE_IDX 0 | |
| 295 | −#define regMP1_SMN_C2PMSG_87 0x0297 | |
| 296 | −#define regMP1_SMN_C2PMSG_87_BASE_IDX 0 | |
| 297 | −#define regMP1_SMN_C2PMSG_88 0x0298 | |
| 298 | −#define regMP1_SMN_C2PMSG_88_BASE_IDX 0 | |
| 299 | −#define regMP1_SMN_C2PMSG_89 0x0299 | |
| 300 | −#define regMP1_SMN_C2PMSG_89_BASE_IDX 0 | |
| 301 | −#define regMP1_SMN_C2PMSG_90 0x029a | |
| 302 | −#define regMP1_SMN_C2PMSG_90_BASE_IDX 0 | |
| 303 | −#define regMP1_SMN_C2PMSG_91 0x029b | |
| 304 | −#define regMP1_SMN_C2PMSG_91_BASE_IDX 0 | |
| 305 | −#define regMP1_SMN_C2PMSG_92 0x029c | |
| 306 | −#define regMP1_SMN_C2PMSG_92_BASE_IDX 0 | |
| 307 | −#define regMP1_SMN_C2PMSG_93 0x029d | |
| 308 | −#define regMP1_SMN_C2PMSG_93_BASE_IDX 0 | |
| 309 | −#define regMP1_SMN_C2PMSG_94 0x029e | |
| 310 | −#define regMP1_SMN_C2PMSG_94_BASE_IDX 0 | |
| 311 | −#define regMP1_SMN_C2PMSG_95 0x029f | |
| 312 | −#define regMP1_SMN_C2PMSG_95_BASE_IDX 0 | |
| 313 | −#define regMP1_SMN_C2PMSG_96 0x02a0 | |
| 314 | −#define regMP1_SMN_C2PMSG_96_BASE_IDX 0 | |
| 315 | −#define regMP1_SMN_C2PMSG_97 0x02a1 | |
| 316 | −#define regMP1_SMN_C2PMSG_97_BASE_IDX 0 | |
| 317 | −#define regMP1_SMN_C2PMSG_98 0x02a2 | |
| 318 | −#define regMP1_SMN_C2PMSG_98_BASE_IDX 0 | |
| 319 | −#define regMP1_SMN_C2PMSG_99 0x02a3 | |
| 320 | −#define regMP1_SMN_C2PMSG_99_BASE_IDX 0 | |
| 321 | −#define regMP1_SMN_C2PMSG_100 0x02a4 | |
| 322 | −#define regMP1_SMN_C2PMSG_100_BASE_IDX 0 | |
| 323 | −#define regMP1_SMN_C2PMSG_101 0x02a5 | |
| 324 | −#define regMP1_SMN_C2PMSG_101_BASE_IDX 0 | |
| 325 | −#define regMP1_SMN_C2PMSG_102 0x02a6 | |
| 326 | −#define regMP1_SMN_C2PMSG_102_BASE_IDX 0 | |
| 327 | −#define regMP1_SMN_C2PMSG_103 0x02a7 | |
| 328 | −#define regMP1_SMN_C2PMSG_103_BASE_IDX 0 | |
| 329 | −#define regMP1_SMN_IH_CREDIT 0x02c1 | |
| 330 | −#define regMP1_SMN_IH_CREDIT_BASE_IDX 0 | |
| 331 | −#define regMP1_SMN_IH_SW_INT 0x02c2 | |
| 332 | −#define regMP1_SMN_IH_SW_INT_BASE_IDX 0 | |
| 333 | −#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3 | |
| 334 | −#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 | |
| 335 | −#define regMP1_SMN_FPS_CNT 0x02c4 | |
| 336 | −#define regMP1_SMN_FPS_CNT_BASE_IDX 0 | |
| 337 | −#define regMP1_SMN_EXT_SCRATCH0 0x0340 | |
| 338 | −#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 | |
| 339 | −#define regMP1_SMN_EXT_SCRATCH1 0x0341 | |
| 340 | −#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 | |
| 341 | −#define regMP1_SMN_EXT_SCRATCH2 0x0342 | |
| 342 | −#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 | |
| 343 | −#define regMP1_SMN_EXT_SCRATCH3 0x0343 | |
| 344 | −#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 | |
| 345 | −#define regMP1_SMN_EXT_SCRATCH4 0x0344 | |
| 346 | −#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 | |
| 347 | −#define regMP1_SMN_EXT_SCRATCH5 0x0345 | |
| 348 | −#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 | |
| 349 | −#define regMP1_SMN_EXT_SCRATCH6 0x0346 | |
| 350 | −#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 | |
| 351 | −#define regMP1_SMN_EXT_SCRATCH7 0x0347 | |
| 352 | −#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 | |
| 353 | − | |
| 354 | − | |
| 355 | −#endif | |
| @@ -1,531 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright 2020 Advanced Micro Devices, Inc. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − * | |
| 22 | − * | |
| 23 | − */ | |
| 24 | −#ifndef _mp_13_0_1_SH_MASK_HEADER | |
| 25 | −#define _mp_13_0_1_SH_MASK_HEADER | |
| 26 | − | |
| 27 | − | |
| 28 | −// addressBlock: mp_SmuMp0_SmnDec | |
| 29 | −//MP0_SMN_C2PMSG_32 | |
| 30 | −#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 | |
| 31 | −#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL | |
| 32 | −//MP0_SMN_C2PMSG_33 | |
| 33 | −#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 | |
| 34 | −#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL | |
| 35 | −//MP0_SMN_C2PMSG_34 | |
| 36 | −#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 | |
| 37 | −#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL | |
| 38 | −//MP0_SMN_C2PMSG_35 | |
| 39 | −#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 | |
| 40 | −#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL | |
| 41 | −//MP0_SMN_C2PMSG_36 | |
| 42 | −#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 | |
| 43 | −#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL | |
| 44 | −//MP0_SMN_C2PMSG_37 | |
| 45 | −#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 | |
| 46 | −#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL | |
| 47 | −//MP0_SMN_C2PMSG_38 | |
| 48 | −#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 | |
| 49 | −#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL | |
| 50 | −//MP0_SMN_C2PMSG_39 | |
| 51 | −#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 | |
| 52 | −#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL | |
| 53 | −//MP0_SMN_C2PMSG_40 | |
| 54 | −#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 | |
| 55 | −#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL | |
| 56 | −//MP0_SMN_C2PMSG_41 | |
| 57 | −#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 | |
| 58 | −#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL | |
| 59 | −//MP0_SMN_C2PMSG_42 | |
| 60 | −#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 | |
| 61 | −#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL | |
| 62 | −//MP0_SMN_C2PMSG_43 | |
| 63 | −#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 | |
| 64 | −#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL | |
| 65 | −//MP0_SMN_C2PMSG_44 | |
| 66 | −#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 | |
| 67 | −#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL | |
| 68 | −//MP0_SMN_C2PMSG_45 | |
| 69 | −#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 | |
| 70 | −#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL | |
| 71 | −//MP0_SMN_C2PMSG_46 | |
| 72 | −#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 | |
| 73 | −#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL | |
| 74 | −//MP0_SMN_C2PMSG_47 | |
| 75 | −#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 | |
| 76 | −#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL | |
| 77 | −//MP0_SMN_C2PMSG_48 | |
| 78 | −#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 | |
| 79 | −#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL | |
| 80 | −//MP0_SMN_C2PMSG_49 | |
| 81 | −#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 | |
| 82 | −#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL | |
| 83 | −//MP0_SMN_C2PMSG_50 | |
| 84 | −#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 | |
| 85 | −#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL | |
| 86 | −//MP0_SMN_C2PMSG_51 | |
| 87 | −#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 | |
| 88 | −#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL | |
| 89 | −//MP0_SMN_C2PMSG_52 | |
| 90 | −#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 | |
| 91 | −#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL | |
| 92 | −//MP0_SMN_C2PMSG_53 | |
| 93 | −#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 | |
| 94 | −#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL | |
| 95 | −//MP0_SMN_C2PMSG_54 | |
| 96 | −#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 | |
| 97 | −#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL | |
| 98 | −//MP0_SMN_C2PMSG_55 | |
| 99 | −#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 | |
| 100 | −#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL | |
| 101 | −//MP0_SMN_C2PMSG_56 | |
| 102 | −#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 | |
| 103 | −#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL | |
| 104 | −//MP0_SMN_C2PMSG_57 | |
| 105 | −#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 | |
| 106 | −#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL | |
| 107 | −//MP0_SMN_C2PMSG_58 | |
| 108 | −#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 | |
| 109 | −#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL | |
| 110 | −//MP0_SMN_C2PMSG_59 | |
| 111 | −#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 | |
| 112 | −#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL | |
| 113 | −//MP0_SMN_C2PMSG_60 | |
| 114 | −#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 | |
| 115 | −#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL | |
| 116 | −//MP0_SMN_C2PMSG_61 | |
| 117 | −#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 | |
| 118 | −#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL | |
| 119 | −//MP0_SMN_C2PMSG_62 | |
| 120 | −#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 | |
| 121 | −#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL | |
| 122 | −//MP0_SMN_C2PMSG_63 | |
| 123 | −#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 | |
| 124 | −#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL | |
| 125 | −//MP0_SMN_C2PMSG_64 | |
| 126 | −#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 | |
| 127 | −#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL | |
| 128 | −//MP0_SMN_C2PMSG_65 | |
| 129 | −#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 | |
| 130 | −#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL | |
| 131 | −//MP0_SMN_C2PMSG_66 | |
| 132 | −#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 | |
| 133 | −#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL | |
| 134 | −//MP0_SMN_C2PMSG_67 | |
| 135 | −#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 | |
| 136 | −#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL | |
| 137 | −//MP0_SMN_C2PMSG_68 | |
| 138 | −#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 | |
| 139 | −#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL | |
| 140 | −//MP0_SMN_C2PMSG_69 | |
| 141 | −#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 | |
| 142 | −#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL | |
| 143 | −//MP0_SMN_C2PMSG_70 | |
| 144 | −#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 | |
| 145 | −#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL | |
| 146 | −//MP0_SMN_C2PMSG_71 | |
| 147 | −#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 | |
| 148 | −#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL | |
| 149 | −//MP0_SMN_C2PMSG_72 | |
| 150 | −#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 | |
| 151 | −#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL | |
| 152 | −//MP0_SMN_C2PMSG_73 | |
| 153 | −#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 | |
| 154 | −#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL | |
| 155 | −//MP0_SMN_C2PMSG_74 | |
| 156 | −#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 | |
| 157 | −#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL | |
| 158 | −//MP0_SMN_C2PMSG_75 | |
| 159 | −#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 | |
| 160 | −#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL | |
| 161 | −//MP0_SMN_C2PMSG_76 | |
| 162 | −#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 | |
| 163 | −#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL | |
| 164 | −//MP0_SMN_C2PMSG_77 | |
| 165 | −#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 | |
| 166 | −#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL | |
| 167 | −//MP0_SMN_C2PMSG_78 | |
| 168 | −#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 | |
| 169 | −#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL | |
| 170 | −//MP0_SMN_C2PMSG_79 | |
| 171 | −#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 | |
| 172 | −#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL | |
| 173 | −//MP0_SMN_C2PMSG_80 | |
| 174 | −#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 | |
| 175 | −#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL | |
| 176 | −//MP0_SMN_C2PMSG_81 | |
| 177 | −#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 | |
| 178 | −#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL | |
| 179 | −//MP0_SMN_C2PMSG_82 | |
| 180 | −#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 | |
| 181 | −#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL | |
| 182 | −//MP0_SMN_C2PMSG_83 | |
| 183 | −#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 | |
| 184 | −#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL | |
| 185 | −//MP0_SMN_C2PMSG_84 | |
| 186 | −#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 | |
| 187 | −#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL | |
| 188 | −//MP0_SMN_C2PMSG_85 | |
| 189 | −#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 | |
| 190 | −#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL | |
| 191 | −//MP0_SMN_C2PMSG_86 | |
| 192 | −#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 | |
| 193 | −#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL | |
| 194 | −//MP0_SMN_C2PMSG_87 | |
| 195 | −#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 | |
| 196 | −#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL | |
| 197 | −//MP0_SMN_C2PMSG_88 | |
| 198 | −#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 | |
| 199 | −#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL | |
| 200 | −//MP0_SMN_C2PMSG_89 | |
| 201 | −#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 | |
| 202 | −#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL | |
| 203 | −//MP0_SMN_C2PMSG_90 | |
| 204 | −#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 | |
| 205 | −#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL | |
| 206 | −//MP0_SMN_C2PMSG_91 | |
| 207 | −#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 | |
| 208 | −#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL | |
| 209 | −//MP0_SMN_C2PMSG_92 | |
| 210 | −#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 | |
| 211 | −#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL | |
| 212 | −//MP0_SMN_C2PMSG_93 | |
| 213 | −#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 | |
| 214 | −#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL | |
| 215 | −//MP0_SMN_C2PMSG_94 | |
| 216 | −#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 | |
| 217 | −#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL | |
| 218 | −//MP0_SMN_C2PMSG_95 | |
| 219 | −#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 | |
| 220 | −#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL | |
| 221 | −//MP0_SMN_C2PMSG_96 | |
| 222 | −#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 | |
| 223 | −#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL | |
| 224 | −//MP0_SMN_C2PMSG_97 | |
| 225 | −#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 | |
| 226 | −#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL | |
| 227 | −//MP0_SMN_C2PMSG_98 | |
| 228 | −#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 | |
| 229 | −#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL | |
| 230 | −//MP0_SMN_C2PMSG_99 | |
| 231 | −#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 | |
| 232 | −#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL | |
| 233 | −//MP0_SMN_C2PMSG_100 | |
| 234 | −#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 | |
| 235 | −#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL | |
| 236 | −//MP0_SMN_C2PMSG_101 | |
| 237 | −#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 | |
| 238 | −#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL | |
| 239 | −//MP0_SMN_C2PMSG_102 | |
| 240 | −#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 | |
| 241 | −#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL | |
| 242 | −//MP0_SMN_C2PMSG_103 | |
| 243 | −#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 | |
| 244 | −#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL | |
| 245 | −//MP0_SMN_IH_CREDIT | |
| 246 | −#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 | |
| 247 | −#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 | |
| 248 | −#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L | |
| 249 | −#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L | |
| 250 | −//MP0_SMN_IH_SW_INT | |
| 251 | −#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 | |
| 252 | −#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 | |
| 253 | −#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL | |
| 254 | −#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L | |
| 255 | −//MP0_SMN_IH_SW_INT_CTRL | |
| 256 | −#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 | |
| 257 | −#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 | |
| 258 | −#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L | |
| 259 | −#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L | |
| 260 | − | |
| 261 | − | |
| 262 | −// addressBlock: mp_SmuMp1Pub_CruDec | |
| 263 | −//MP1_FIRMWARE_FLAGS | |
| 264 | −#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 | |
| 265 | −#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 | |
| 266 | −#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L | |
| 267 | −#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL | |
| 268 | − | |
| 269 | − | |
| 270 | −// addressBlock: mp_SmuMp1_SmnDec | |
| 271 | −//MP1_SMN_C2PMSG_32 | |
| 272 | −#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 | |
| 273 | −#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL | |
| 274 | −//MP1_SMN_C2PMSG_33 | |
| 275 | −#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 | |
| 276 | −#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL | |
| 277 | −//MP1_SMN_C2PMSG_34 | |
| 278 | −#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 | |
| 279 | −#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL | |
| 280 | −//MP1_SMN_C2PMSG_35 | |
| 281 | −#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 | |
| 282 | −#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL | |
| 283 | −//MP1_SMN_C2PMSG_36 | |
| 284 | −#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 | |
| 285 | −#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL | |
| 286 | −//MP1_SMN_C2PMSG_37 | |
| 287 | −#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 | |
| 288 | −#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL | |
| 289 | −//MP1_SMN_C2PMSG_38 | |
| 290 | −#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 | |
| 291 | −#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL | |
| 292 | −//MP1_SMN_C2PMSG_39 | |
| 293 | −#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 | |
| 294 | −#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL | |
| 295 | −//MP1_SMN_C2PMSG_40 | |
| 296 | −#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 | |
| 297 | −#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL | |
| 298 | −//MP1_SMN_C2PMSG_41 | |
| 299 | −#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 | |
| 300 | −#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL | |
| 301 | −//MP1_SMN_C2PMSG_42 | |
| 302 | −#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 | |
| 303 | −#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL | |
| 304 | −//MP1_SMN_C2PMSG_43 | |
| 305 | −#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 | |
| 306 | −#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL | |
| 307 | −//MP1_SMN_C2PMSG_44 | |
| 308 | −#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 | |
| 309 | −#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL | |
| 310 | −//MP1_SMN_C2PMSG_45 | |
| 311 | −#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 | |
| 312 | −#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL | |
| 313 | −//MP1_SMN_C2PMSG_46 | |
| 314 | −#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 | |
| 315 | −#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL | |
| 316 | −//MP1_SMN_C2PMSG_47 | |
| 317 | −#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 | |
| 318 | −#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL | |
| 319 | −//MP1_SMN_C2PMSG_48 | |
| 320 | −#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 | |
| 321 | −#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL | |
| 322 | −//MP1_SMN_C2PMSG_49 | |
| 323 | −#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 | |
| 324 | −#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL | |
| 325 | −//MP1_SMN_C2PMSG_50 | |
| 326 | −#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 | |
| 327 | −#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL | |
| 328 | −//MP1_SMN_C2PMSG_51 | |
| 329 | −#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 | |
| 330 | −#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL | |
| 331 | −//MP1_SMN_C2PMSG_52 | |
| 332 | −#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 | |
| 333 | −#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL | |
| 334 | −//MP1_SMN_C2PMSG_53 | |
| 335 | −#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 | |
| 336 | −#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL | |
| 337 | −//MP1_SMN_C2PMSG_54 | |
| 338 | −#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 | |
| 339 | −#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL | |
| 340 | −//MP1_SMN_C2PMSG_55 | |
| 341 | −#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 | |
| 342 | −#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL | |
| 343 | −//MP1_SMN_C2PMSG_56 | |
| 344 | −#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 | |
| 345 | −#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL | |
| 346 | −//MP1_SMN_C2PMSG_57 | |
| 347 | −#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 | |
| 348 | −#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL | |
| 349 | −//MP1_SMN_C2PMSG_58 | |
| 350 | −#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 | |
| 351 | −#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL | |
| 352 | −//MP1_SMN_C2PMSG_59 | |
| 353 | −#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 | |
| 354 | −#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL | |
| 355 | −//MP1_SMN_C2PMSG_60 | |
| 356 | −#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 | |
| 357 | −#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL | |
| 358 | −//MP1_SMN_C2PMSG_61 | |
| 359 | −#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 | |
| 360 | −#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL | |
| 361 | −//MP1_SMN_C2PMSG_62 | |
| 362 | −#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 | |
| 363 | −#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL | |
| 364 | −//MP1_SMN_C2PMSG_63 | |
| 365 | −#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 | |
| 366 | −#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL | |
| 367 | −//MP1_SMN_C2PMSG_64 | |
| 368 | −#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 | |
| 369 | −#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL | |
| 370 | −//MP1_SMN_C2PMSG_65 | |
| 371 | −#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 | |
| 372 | −#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL | |
| 373 | −//MP1_SMN_C2PMSG_66 | |
| 374 | −#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 | |
| 375 | −#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL | |
| 376 | −//MP1_SMN_C2PMSG_67 | |
| 377 | −#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 | |
| 378 | −#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL | |
| 379 | −//MP1_SMN_C2PMSG_68 | |
| 380 | −#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 | |
| 381 | −#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL | |
| 382 | −//MP1_SMN_C2PMSG_69 | |
| 383 | −#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 | |
| 384 | −#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL | |
| 385 | −//MP1_SMN_C2PMSG_70 | |
| 386 | −#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 | |
| 387 | −#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL | |
| 388 | −//MP1_SMN_C2PMSG_71 | |
| 389 | −#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 | |
| 390 | −#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL | |
| 391 | −//MP1_SMN_C2PMSG_72 | |
| 392 | −#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 | |
| 393 | −#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL | |
| 394 | −//MP1_SMN_C2PMSG_73 | |
| 395 | −#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 | |
| 396 | −#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL | |
| 397 | −//MP1_SMN_C2PMSG_74 | |
| 398 | −#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 | |
| 399 | −#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL | |
| 400 | −//MP1_SMN_C2PMSG_75 | |
| 401 | −#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 | |
| 402 | −#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL | |
| 403 | −//MP1_SMN_C2PMSG_76 | |
| 404 | −#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 | |
| 405 | −#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL | |
| 406 | −//MP1_SMN_C2PMSG_77 | |
| 407 | −#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 | |
| 408 | −#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL | |
| 409 | −//MP1_SMN_C2PMSG_78 | |
| 410 | −#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 | |
| 411 | −#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL | |
| 412 | −//MP1_SMN_C2PMSG_79 | |
| 413 | −#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 | |
| 414 | −#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL | |
| 415 | −//MP1_SMN_C2PMSG_80 | |
| 416 | −#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 | |
| 417 | −#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL | |
| 418 | −//MP1_SMN_C2PMSG_81 | |
| 419 | −#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 | |
| 420 | −#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL | |
| 421 | −//MP1_SMN_C2PMSG_82 | |
| 422 | −#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 | |
| 423 | −#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL | |
| 424 | −//MP1_SMN_C2PMSG_83 | |
| 425 | −#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 | |
| 426 | −#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL | |
| 427 | −//MP1_SMN_C2PMSG_84 | |
| 428 | −#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 | |
| 429 | −#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL | |
| 430 | −//MP1_SMN_C2PMSG_85 | |
| 431 | −#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 | |
| 432 | −#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL | |
| 433 | −//MP1_SMN_C2PMSG_86 | |
| 434 | −#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 | |
| 435 | −#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL | |
| 436 | −//MP1_SMN_C2PMSG_87 | |
| 437 | −#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 | |
| 438 | −#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL | |
| 439 | −//MP1_SMN_C2PMSG_88 | |
| 440 | −#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 | |
| 441 | −#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL | |
| 442 | −//MP1_SMN_C2PMSG_89 | |
| 443 | −#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 | |
| 444 | −#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL | |
| 445 | −//MP1_SMN_C2PMSG_90 | |
| 446 | −#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 | |
| 447 | −#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL | |
| 448 | −//MP1_SMN_C2PMSG_91 | |
| 449 | −#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 | |
| 450 | −#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL | |
| 451 | −//MP1_SMN_C2PMSG_92 | |
| 452 | −#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 | |
| 453 | −#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL | |
| 454 | −//MP1_SMN_C2PMSG_93 | |
| 455 | −#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 | |
| 456 | −#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL | |
| 457 | −//MP1_SMN_C2PMSG_94 | |
| 458 | −#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 | |
| 459 | −#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL | |
| 460 | −//MP1_SMN_C2PMSG_95 | |
| 461 | −#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 | |
| 462 | −#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL | |
| 463 | −//MP1_SMN_C2PMSG_96 | |
| 464 | −#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 | |
| 465 | −#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL | |
| 466 | −//MP1_SMN_C2PMSG_97 | |
| 467 | −#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 | |
| 468 | −#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL | |
| 469 | −//MP1_SMN_C2PMSG_98 | |
| 470 | −#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 | |
| 471 | −#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL | |
| 472 | −//MP1_SMN_C2PMSG_99 | |
| 473 | −#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 | |
| 474 | −#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL | |
| 475 | −//MP1_SMN_C2PMSG_100 | |
| 476 | −#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 | |
| 477 | −#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL | |
| 478 | −//MP1_SMN_C2PMSG_101 | |
| 479 | −#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 | |
| 480 | −#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL | |
| 481 | −//MP1_SMN_C2PMSG_102 | |
| 482 | −#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 | |
| 483 | −#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL | |
| 484 | −//MP1_SMN_C2PMSG_103 | |
| 485 | −#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 | |
| 486 | −#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL | |
| 487 | −//MP1_SMN_IH_CREDIT | |
| 488 | −#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 | |
| 489 | −#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 | |
| 490 | −#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L | |
| 491 | −#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L | |
| 492 | −//MP1_SMN_IH_SW_INT | |
| 493 | −#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 | |
| 494 | −#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 | |
| 495 | −#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL | |
| 496 | −#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L | |
| 497 | −//MP1_SMN_IH_SW_INT_CTRL | |
| 498 | −#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 | |
| 499 | −#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 | |
| 500 | −#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L | |
| 501 | −#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L | |
| 502 | −//MP1_SMN_FPS_CNT | |
| 503 | −#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 | |
| 504 | −#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL | |
| 505 | −//MP1_SMN_EXT_SCRATCH0 | |
| 506 | −#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 | |
| 507 | −#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL | |
| 508 | −//MP1_SMN_EXT_SCRATCH1 | |
| 509 | −#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 | |
| 510 | −#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL | |
| 511 | −//MP1_SMN_EXT_SCRATCH2 | |
| 512 | −#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 | |
| 513 | −#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL | |
| 514 | −//MP1_SMN_EXT_SCRATCH3 | |
| 515 | −#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 | |
| 516 | −#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL | |
| 517 | −//MP1_SMN_EXT_SCRATCH4 | |
| 518 | −#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 | |
| 519 | −#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL | |
| 520 | −//MP1_SMN_EXT_SCRATCH5 | |
| 521 | −#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 | |
| 522 | −#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL | |
| 523 | −//MP1_SMN_EXT_SCRATCH6 | |
| 524 | −#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 | |
| 525 | −#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL | |
| 526 | −//MP1_SMN_EXT_SCRATCH7 | |
| 527 | −#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 | |
| 528 | −#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL | |
| 529 | − | |
| 530 | − | |
| 531 | −#endif | |
| @@ -590,7 +590,7 @@ struct atom_firmware_info_v3_4 { · 589 unmodified lines | ||
| 590 | 590 | uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def |
| 591 | 591 | uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id |
| 592 | 592 | uint8_t board_i2c_feature_slave_addr; |
| 593 | − uint8_t reserved3; | |
| 593 | + uint8_t ras_rom_i2c_slave_addr; | |
| 594 | 594 | uint16_t bootup_mvddq_mv; |
| 595 | 595 | uint16_t bootup_mvpp_mv; |
| 596 | 596 | uint32_t zfbstartaddrin16mb; |
| @@ -101,7 +101,8 @@ · 100 unmodified lines | ||
| 101 | 101 | #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41 |
| 102 | 102 | |
| 103 | 103 | #define PPSMC_MSG_GfxDriverResetRecovery 0x42 |
| 104 | −#define PPSMC_Message_Count 0x43 | |
| 104 | +#define PPSMC_MSG_BoardPowerCalibration 0x43 | |
| 105 | +#define PPSMC_Message_Count 0x44 | |
| 105 | 106 | |
| 106 | 107 | //PPSMC Reset Types |
| 107 | 108 | #define PPSMC_RESET_TYPE_WARM_RESET 0x00 |
| @@ -225,7 +225,8 @@ · 224 unmodified lines | ||
| 225 | 225 | __SMU_DUMMY_MAP(DisableDeterminism), \ |
| 226 | 226 | __SMU_DUMMY_MAP(SetUclkDpmMode), \ |
| 227 | 227 | __SMU_DUMMY_MAP(LightSBR), \ |
| 228 | − __SMU_DUMMY_MAP(GfxDriverResetRecovery), | |
| 228 | + __SMU_DUMMY_MAP(GfxDriverResetRecovery), \ | |
| 229 | + __SMU_DUMMY_MAP(BoardPowerCalibration), | |
| 229 | 230 | |
| 230 | 231 | #undef __SMU_DUMMY_MAP |
| 231 | 232 | #define __SMU_DUMMY_MAP(type) SMU_MSG_##type |
| @@ -34,7 +34,7 @@ · 33 unmodified lines | ||
| 34 | 34 | #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE |
| 35 | 35 | #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03 |
| 36 | 36 | #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF |
| 37 | −#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0x9 | |
| 37 | +#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD | |
| 38 | 38 | |
| 39 | 39 | /* MP Apertures */ |
| 40 | 40 | #define MP0_Public 0x03800000 |
| @@ -26,6 +26,7 @@ · 25 unmodified lines | ||
| 26 | 26 | #include "amdgpu_smu.h" |
| 27 | 27 | |
| 28 | 28 | #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF |
| 29 | +#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04 | |
| 29 | 30 | #define SMU13_DRIVER_IF_VERSION_ALDE 0x07 |
| 30 | 31 | |
| 31 | 32 | /* MP Apertures */ |
| @@ -1,57 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright 2020 Advanced Micro Devices, Inc. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − * | |
| 22 | − */ | |
| 23 | −#ifndef __SMU_V13_0_1_H__ | |
| 24 | −#define __SMU_V13_0_1_H__ | |
| 25 | − | |
| 26 | −#include "amdgpu_smu.h" | |
| 27 | − | |
| 28 | −#define SMU13_0_1_DRIVER_IF_VERSION_INV 0xFFFFFFFF | |
| 29 | −#define SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP 0x3 | |
| 30 | − | |
| 31 | −/* MP Apertures */ | |
| 32 | −#define MP0_Public 0x03800000 | |
| 33 | −#define MP0_SRAM 0x03900000 | |
| 34 | −#define MP1_Public 0x03b00000 | |
| 35 | −#define MP1_SRAM 0x03c00004 | |
| 36 | − | |
| 37 | −/* address block */ | |
| 38 | −#define smnMP1_FIRMWARE_FLAGS 0x3010024 | |
| 39 | − | |
| 40 | − | |
| 41 | −#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) | |
| 42 | − | |
| 43 | −int smu_v13_0_1_check_fw_status(struct smu_context *smu); | |
| 44 | − | |
| 45 | −int smu_v13_0_1_check_fw_version(struct smu_context *smu); | |
| 46 | − | |
| 47 | −int smu_v13_0_1_fini_smc_tables(struct smu_context *smu); | |
| 48 | − | |
| 49 | −int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu); | |
| 50 | − | |
| 51 | −int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu); | |
| 52 | − | |
| 53 | −int smu_v13_0_1_set_driver_table_location(struct smu_context *smu); | |
| 54 | − | |
| 55 | −int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable); | |
| 56 | −#endif | |
| 57 | −#endif | |
| @@ -111,7 +111,9 @@ typedef struct { · 110 unmodified lines | ||
| 111 | 111 | uint32_t InWhisperMode : 1; |
| 112 | 112 | uint32_t spare0 : 1; |
| 113 | 113 | uint32_t ZstateStatus : 4; |
| 114 | − uint32_t spare1 :12; | |
| 114 | + uint32_t spare1 : 4; | |
| 115 | + uint32_t DstateFun : 4; | |
| 116 | + uint32_t DstateDev : 4; | |
| 115 | 117 | // MP1_EXT_SCRATCH2 |
| 116 | 118 | uint32_t P2JobHandler :24; |
| 117 | 119 | uint32_t RsmuPmiP2FinishedCnt : 8; |
| @@ -5127,6 +5127,13 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) · 5126 unmodified lines | ||
| 5127 | 5127 | return size; |
| 5128 | 5128 | } |
| 5129 | 5129 | |
| 5130 | +static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr) | |
| 5131 | +{ | |
| 5132 | + struct amdgpu_device *adev = hwmgr->adev; | |
| 5133 | + | |
| 5134 | + return (adev->pdev->device == 0x6860); | |
| 5135 | +} | |
| 5136 | + | |
| 5130 | 5137 | static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) |
| 5131 | 5138 | { |
| 5132 | 5139 | struct vega10_hwmgr *data = hwmgr->backend; |
| @@ -5163,9 +5170,15 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui · 30 unmodified lines | ||
| 5163 | 5170 | } |
| 5164 | 5171 | |
| 5165 | 5172 | out: |
| 5166 | − smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, | |
| 5173 | + if (vega10_get_power_profile_mode_quirks(hwmgr)) | |
| 5174 | + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, | |
| 5175 | + 1 << power_profile_mode, | |
| 5176 | + NULL); | |
| 5177 | + else | |
| 5178 | + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, | |
| 5167 | 5179 | (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), |
| 5168 | 5180 | NULL); |
| 5181 | + | |
| 5169 | 5182 | hwmgr->power_profile_mode = power_profile_mode; |
| 5170 | 5183 | |
| 5171 | 5184 | return 0; |
| @@ -353,8 +353,7 @@ static void sienna_cichlid_check_bxco_support(struct smu_context *smu) · 352 unmodified lines | ||
| 353 | 353 | struct amdgpu_device *adev = smu->adev; |
| 354 | 354 | uint32_t val; |
| 355 | 355 | |
| 356 | − if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || | |
| 357 | − powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) { | |
| 356 | + if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { | |
| 358 | 357 | val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); |
| 359 | 358 | smu_baco->platform_support = |
| 360 | 359 | (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : |
| @@ -1528,6 +1528,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) · 1527 unmodified lines | ||
| 1528 | 1528 | case CHIP_SIENNA_CICHLID: |
| 1529 | 1529 | case CHIP_NAVY_FLOUNDER: |
| 1530 | 1530 | case CHIP_DIMGREY_CAVEFISH: |
| 1531 | + case CHIP_BEIGE_GOBY: | |
| 1531 | 1532 | if (amdgpu_runtime_pm == 2) |
| 1532 | 1533 | ret = smu_cmn_send_smc_msg_with_param(smu, |
| 1533 | 1534 | SMU_MSG_EnterBaco, |
| @@ -256,7 +256,7 @@ static int vangogh_tables_init(struct smu_context *smu) · 255 unmodified lines | ||
| 256 | 256 | return 0; |
| 257 | 257 | |
| 258 | 258 | err3_out: |
| 259 | − kfree(smu_table->clocks_table); | |
| 259 | + kfree(smu_table->watermarks_table); | |
| 260 | 260 | err2_out: |
| 261 | 261 | kfree(smu_table->gpu_metrics_table); |
| 262 | 262 | err1_out: |
| @@ -23,7 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | # Makefile for the 'smu manager' sub-component of powerplay. |
| 24 | 24 | # It provides the smu management services for the driver. |
| 25 | 25 | |
| 26 | −SMU13_MGR = smu_v13_0.o aldebaran_ppt.o smu_v13_0_1.o yellow_carp_ppt.o | |
| 26 | +SMU13_MGR = smu_v13_0.o aldebaran_ppt.o yellow_carp_ppt.o | |
| 27 | 27 | |
| 28 | 28 | AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR)) |
| 29 | 29 | |
| @@ -134,6 +134,7 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT · 133 unmodified lines | ||
| 134 | 134 | MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), |
| 135 | 135 | MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), |
| 136 | 136 | MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), |
| 137 | + MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), | |
| 137 | 138 | }; |
| 138 | 139 | |
| 139 | 140 | static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { |
| @@ -440,6 +441,39 @@ static int aldebaran_setup_pptable(struct smu_context *smu) · 300 unmodified lines | ||
| 440 | 441 | return ret; |
| 441 | 442 | } |
| 442 | 443 | |
| 444 | +static bool aldebaran_is_primary(struct smu_context *smu) | |
| 445 | +{ | |
| 446 | + struct amdgpu_device *adev = smu->adev; | |
| 447 | + | |
| 448 | + if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) | |
| 449 | + return adev->smuio.funcs->get_die_id(adev) == 0; | |
| 450 | + | |
| 451 | + return true; | |
| 452 | +} | |
| 453 | + | |
| 454 | +static int aldebaran_run_board_btc(struct smu_context *smu) | |
| 455 | +{ | |
| 456 | + u32 smu_version; | |
| 457 | + int ret; | |
| 458 | + | |
| 459 | + if (!aldebaran_is_primary(smu)) | |
| 460 | + return 0; | |
| 461 | + | |
| 462 | + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); | |
| 463 | + if (ret) { | |
| 464 | + dev_err(smu->adev->dev, "Failed to get smu version!\n"); | |
| 465 | + return ret; | |
| 466 | + } | |
| 467 | + if (smu_version <= 0x00441d00) | |
| 468 | + return 0; | |
| 469 | + | |
| 470 | + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); | |
| 471 | + if (ret) | |
| 472 | + dev_err(smu->adev->dev, "Board power calibration failed!\n"); | |
| 473 | + | |
| 474 | + return ret; | |
| 475 | +} | |
| 476 | + | |
| 443 | 477 | static int aldebaran_run_btc(struct smu_context *smu) |
| 444 | 478 | { |
| 445 | 479 | int ret; |
| @@ -447,6 +481,8 @@ static int aldebaran_run_btc(struct smu_context *smu) · 1 unmodified line | ||
| 447 | 481 | ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); |
| 448 | 482 | if (ret) |
| 449 | 483 | dev_err(smu->adev->dev, "RunDcBtc failed!\n"); |
| 484 | + else | |
| 485 | + ret = aldebaran_run_board_btc(smu); | |
| 450 | 486 | |
| 451 | 487 | return ret; |
| 452 | 488 | } |
| @@ -524,16 +560,6 @@ static int aldebaran_freqs_in_same_level(int32_t frequency1, · 71 unmodified lines | ||
| 524 | 560 | return (abs(frequency1 - frequency2) <= EPSILON); |
| 525 | 561 | } |
| 526 | 562 | |
| 527 | −static bool aldebaran_is_primary(struct smu_context *smu) | |
| 528 | −{ | |
| 529 | − struct amdgpu_device *adev = smu->adev; | |
| 530 | − | |
| 531 | − if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) | |
| 532 | − return adev->smuio.funcs->get_die_id(adev) == 0; | |
| 533 | − | |
| 534 | − return true; | |
| 535 | −} | |
| 536 | − | |
| 537 | 563 | static int aldebaran_get_smu_metrics_data(struct smu_context *smu, |
| 538 | 564 | MetricsMember_t member, |
| 539 | 565 | uint32_t *value) |
| @@ -210,6 +210,9 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) · 209 unmodified lines | ||
| 210 | 210 | case CHIP_ALDEBARAN: |
| 211 | 211 | smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; |
| 212 | 212 | break; |
| 213 | + case CHIP_YELLOW_CARP: | |
| 214 | + smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; | |
| 215 | + break; | |
| 213 | 216 | default: |
| 214 | 217 | dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); |
| 215 | 218 | smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; |
| @@ -694,6 +697,27 @@ failed: · 478 unmodified lines | ||
| 694 | 697 | return ret; |
| 695 | 698 | } |
| 696 | 699 | |
| 700 | +int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) | |
| 701 | +{ | |
| 702 | + int ret = 0; | |
| 703 | + struct amdgpu_device *adev = smu->adev; | |
| 704 | + | |
| 705 | + switch (adev->asic_type) { | |
| 706 | + case CHIP_YELLOW_CARP: | |
| 707 | + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) | |
| 708 | + return 0; | |
| 709 | + if (enable) | |
| 710 | + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); | |
| 711 | + else | |
| 712 | + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); | |
| 713 | + break; | |
| 714 | + default: | |
| 715 | + break; | |
| 716 | + } | |
| 717 | + | |
| 718 | + return ret; | |
| 719 | +} | |
| 720 | + | |
| 697 | 721 | int smu_v13_0_system_features_control(struct smu_context *smu, |
| 698 | 722 | bool en) |
| 699 | 723 | { |
| @@ -1,311 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright 2020 Advanced Micro Devices, Inc. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − */ | |
| 22 | − | |
| 23 | −//#include <linux/reboot.h> | |
| 24 | − | |
| 25 | −#define SWSMU_CODE_LAYER_L3 | |
| 26 | − | |
| 27 | −#include "amdgpu.h" | |
| 28 | −#include "amdgpu_smu.h" | |
| 29 | −#include "smu_v13_0_1.h" | |
| 30 | −#include "soc15_common.h" | |
| 31 | −#include "smu_cmn.h" | |
| 32 | −#include "atomfirmware.h" | |
| 33 | −#include "amdgpu_atomfirmware.h" | |
| 34 | −#include "amdgpu_atombios.h" | |
| 35 | −#include "atom.h" | |
| 36 | − | |
| 37 | −#include "asic_reg/mp/mp_13_0_1_offset.h" | |
| 38 | −#include "asic_reg/mp/mp_13_0_1_sh_mask.h" | |
| 39 | − | |
| 40 | −/* | |
| 41 | − * DO NOT use these for err/warn/info/debug messages. | |
| 42 | − * Use dev_err, dev_warn, dev_info and dev_dbg instead. | |
| 43 | − * They are more MGPU friendly. | |
| 44 | − */ | |
| 45 | −#undef pr_err | |
| 46 | −#undef pr_warn | |
| 47 | −#undef pr_info | |
| 48 | −#undef pr_debug | |
| 49 | − | |
| 50 | −int smu_v13_0_1_check_fw_status(struct smu_context *smu) | |
| 51 | −{ | |
| 52 | − struct amdgpu_device *adev = smu->adev; | |
| 53 | − uint32_t mp1_fw_flags; | |
| 54 | − | |
| 55 | − mp1_fw_flags = RREG32_PCIE(MP1_Public | | |
| 56 | − (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); | |
| 57 | − | |
| 58 | − if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> | |
| 59 | − MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) | |
| 60 | − return 0; | |
| 61 | − | |
| 62 | − return -EIO; | |
| 63 | −} | |
| 64 | − | |
| 65 | −int smu_v13_0_1_check_fw_version(struct smu_context *smu) | |
| 66 | −{ | |
| 67 | − uint32_t if_version = 0xff, smu_version = 0xff; | |
| 68 | − uint16_t smu_major; | |
| 69 | − uint8_t smu_minor, smu_debug; | |
| 70 | − int ret = 0; | |
| 71 | − | |
| 72 | − ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); | |
| 73 | − if (ret) | |
| 74 | − return ret; | |
| 75 | − | |
| 76 | − smu_major = (smu_version >> 16) & 0xffff; | |
| 77 | − smu_minor = (smu_version >> 8) & 0xff; | |
| 78 | − smu_debug = (smu_version >> 0) & 0xff; | |
| 79 | − | |
| 80 | − switch (smu->adev->asic_type) { | |
| 81 | − case CHIP_YELLOW_CARP: | |
| 82 | − smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP; | |
| 83 | − break; | |
| 84 | − | |
| 85 | − default: | |
| 86 | − dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); | |
| 87 | − smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_INV; | |
| 88 | − break; | |
| 89 | − } | |
| 90 | − | |
| 91 | − dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n", | |
| 92 | − smu_version, smu_major, smu_minor, smu_debug); | |
| 93 | − | |
| 94 | − /* | |
| 95 | − * 1. if_version mismatch is not critical as our fw is designed | |
| 96 | − * to be backward compatible. | |
| 97 | − * 2. New fw usually brings some optimizations. But that's visible | |
| 98 | − * only on the paired driver. | |
| 99 | − * Considering above, we just leave user a warning message instead | |
| 100 | − * of halt driver loading. | |
| 101 | − */ | |
| 102 | − if (if_version != smu->smc_driver_if_version) { | |
| 103 | − dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " | |
| 104 | − "smu fw version = 0x%08x (%d.%d.%d)\n", | |
| 105 | − smu->smc_driver_if_version, if_version, | |
| 106 | − smu_version, smu_major, smu_minor, smu_debug); | |
| 107 | − dev_warn(smu->adev->dev, "SMU driver if version not matched\n"); | |
| 108 | − } | |
| 109 | − | |
| 110 | − return ret; | |
| 111 | −} | |
| 112 | − | |
| 113 | −int smu_v13_0_1_fini_smc_tables(struct smu_context *smu) | |
| 114 | −{ | |
| 115 | − struct smu_table_context *smu_table = &smu->smu_table; | |
| 116 | − | |
| 117 | − kfree(smu_table->clocks_table); | |
| 118 | − smu_table->clocks_table = NULL; | |
| 119 | − | |
| 120 | − kfree(smu_table->metrics_table); | |
| 121 | − smu_table->metrics_table = NULL; | |
| 122 | − | |
| 123 | − kfree(smu_table->watermarks_table); | |
| 124 | − smu_table->watermarks_table = NULL; | |
| 125 | − | |
| 126 | − return 0; | |
| 127 | −} | |
| 128 | − | |
| 129 | −static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev, | |
| 130 | − uint8_t clk_id, | |
| 131 | − uint8_t syspll_id, | |
| 132 | − uint32_t *clk_freq) | |
| 133 | −{ | |
| 134 | − struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; | |
| 135 | − struct atom_get_smu_clock_info_output_parameters_v3_1 *output; | |
| 136 | − int ret, index; | |
| 137 | − | |
| 138 | − input.clk_id = clk_id; | |
| 139 | − input.syspll_id = syspll_id; | |
| 140 | − input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; | |
| 141 | − index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, | |
| 142 | − getsmuclockinfo); | |
| 143 | − | |
| 144 | − ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, | |
| 145 | − (uint32_t *)&input); | |
| 146 | − if (ret) | |
| 147 | − return -EINVAL; | |
| 148 | − | |
| 149 | − output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; | |
| 150 | − *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; | |
| 151 | − | |
| 152 | − return 0; | |
| 153 | −} | |
| 154 | − | |
| 155 | −int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu) | |
| 156 | −{ | |
| 157 | − int ret, index; | |
| 158 | − uint16_t size; | |
| 159 | − uint8_t frev, crev; | |
| 160 | − struct atom_common_table_header *header; | |
| 161 | − struct atom_firmware_info_v3_4 *v_3_4; | |
| 162 | − struct atom_firmware_info_v3_3 *v_3_3; | |
| 163 | − struct atom_firmware_info_v3_1 *v_3_1; | |
| 164 | − | |
| 165 | − index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, | |
| 166 | − firmwareinfo); | |
| 167 | − | |
| 168 | − ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, | |
| 169 | − (uint8_t **)&header); | |
| 170 | − if (ret) | |
| 171 | − return ret; | |
| 172 | − | |
| 173 | − if (header->format_revision != 3) { | |
| 174 | − dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); | |
| 175 | − return -EINVAL; | |
| 176 | − } | |
| 177 | − | |
| 178 | − switch (header->content_revision) { | |
| 179 | − case 0: | |
| 180 | − case 1: | |
| 181 | − case 2: | |
| 182 | − v_3_1 = (struct atom_firmware_info_v3_1 *)header; | |
| 183 | − smu->smu_table.boot_values.revision = v_3_1->firmware_revision; | |
| 184 | − smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; | |
| 185 | − smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; | |
| 186 | − smu->smu_table.boot_values.socclk = 0; | |
| 187 | − smu->smu_table.boot_values.dcefclk = 0; | |
| 188 | − smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; | |
| 189 | − smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; | |
| 190 | − smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; | |
| 191 | − smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; | |
| 192 | − smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; | |
| 193 | − break; | |
| 194 | − case 3: | |
| 195 | − v_3_3 = (struct atom_firmware_info_v3_3 *)header; | |
| 196 | − smu->smu_table.boot_values.revision = v_3_3->firmware_revision; | |
| 197 | − smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; | |
| 198 | − smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; | |
| 199 | − smu->smu_table.boot_values.socclk = 0; | |
| 200 | − smu->smu_table.boot_values.dcefclk = 0; | |
| 201 | − smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; | |
| 202 | − smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; | |
| 203 | − smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; | |
| 204 | − smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; | |
| 205 | − smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; | |
| 206 | − break; | |
| 207 | − case 4: | |
| 208 | − default: | |
| 209 | − v_3_4 = (struct atom_firmware_info_v3_4 *)header; | |
| 210 | − smu->smu_table.boot_values.revision = v_3_4->firmware_revision; | |
| 211 | − smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; | |
| 212 | − smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; | |
| 213 | − smu->smu_table.boot_values.socclk = 0; | |
| 214 | − smu->smu_table.boot_values.dcefclk = 0; | |
| 215 | − smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; | |
| 216 | − smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; | |
| 217 | − smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; | |
| 218 | − smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; | |
| 219 | − smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; | |
| 220 | − break; | |
| 221 | − } | |
| 222 | − | |
| 223 | − smu->smu_table.boot_values.format_revision = header->format_revision; | |
| 224 | − smu->smu_table.boot_values.content_revision = header->content_revision; | |
| 225 | − | |
| 226 | − smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, | |
| 227 | − (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, | |
| 228 | − (uint8_t)0, | |
| 229 | − &smu->smu_table.boot_values.socclk); | |
| 230 | − | |
| 231 | − smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, | |
| 232 | − (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, | |
| 233 | − (uint8_t)0, | |
| 234 | − &smu->smu_table.boot_values.dcefclk); | |
| 235 | − | |
| 236 | − smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, | |
| 237 | − (uint8_t)SMU11_SYSPLL0_ECLK_ID, | |
| 238 | − (uint8_t)0, | |
| 239 | − &smu->smu_table.boot_values.eclk); | |
| 240 | − | |
| 241 | − smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, | |
| 242 | − (uint8_t)SMU11_SYSPLL0_VCLK_ID, | |
| 243 | − (uint8_t)0, | |
| 244 | − &smu->smu_table.boot_values.vclk); | |
| 245 | − | |
| 246 | − smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, | |
| 247 | − (uint8_t)SMU11_SYSPLL0_DCLK_ID, | |
| 248 | − (uint8_t)0, | |
| 249 | − &smu->smu_table.boot_values.dclk); | |
| 250 | − | |
| 251 | − if ((smu->smu_table.boot_values.format_revision == 3) && | |
| 252 | − (smu->smu_table.boot_values.content_revision >= 2)) | |
| 253 | − smu_v13_0_1_atom_get_smu_clockinfo(smu->adev, | |
| 254 | − (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, | |
| 255 | − (uint8_t)SMU11_SYSPLL1_2_ID, | |
| 256 | − &smu->smu_table.boot_values.fclk); | |
| 257 | − | |
| 258 | − return 0; | |
| 259 | −} | |
| 260 | − | |
| 261 | −int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu) | |
| 262 | −{ | |
| 263 | − struct smu_table_context *smu_table = &smu->smu_table; | |
| 264 | − | |
| 265 | − return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); | |
| 266 | −} | |
| 267 | − | |
| 268 | −int smu_v13_0_1_set_driver_table_location(struct smu_context *smu) | |
| 269 | −{ | |
| 270 | − struct smu_table *driver_table = &smu->smu_table.driver_table; | |
| 271 | − int ret = 0; | |
| 272 | − | |
| 273 | − if (!driver_table->mc_address) | |
| 274 | − return 0; | |
| 275 | − | |
| 276 | − ret = smu_cmn_send_smc_msg_with_param(smu, | |
| 277 | − SMU_MSG_SetDriverDramAddrHigh, | |
| 278 | − upper_32_bits(driver_table->mc_address), | |
| 279 | − NULL); | |
| 280 | − | |
| 281 | − if (ret) | |
| 282 | − return ret; | |
| 283 | − | |
| 284 | − ret = smu_cmn_send_smc_msg_with_param(smu, | |
| 285 | − SMU_MSG_SetDriverDramAddrLow, | |
| 286 | − lower_32_bits(driver_table->mc_address), | |
| 287 | − NULL); | |
| 288 | − | |
| 289 | − return ret; | |
| 290 | −} | |
| 291 | − | |
| 292 | −int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable) | |
| 293 | −{ | |
| 294 | − int ret = 0; | |
| 295 | − struct amdgpu_device *adev = smu->adev; | |
| 296 | − | |
| 297 | − switch (adev->asic_type) { | |
| 298 | − case CHIP_YELLOW_CARP: | |
| 299 | − if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) | |
| 300 | − return 0; | |
| 301 | − if (enable) | |
| 302 | − ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); | |
| 303 | − else | |
| 304 | − ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); | |
| 305 | − break; | |
| 306 | − default: | |
| 307 | − break; | |
| 308 | − } | |
| 309 | − | |
| 310 | − return ret; | |
| 311 | −} | |
| @@ -25,7 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | #include "amdgpu.h" |
| 27 | 27 | #include "amdgpu_smu.h" |
| 28 | −#include "smu_v13_0_1.h" | |
| 28 | +#include "smu_v13_0.h" | |
| 29 | 29 | #include "smu13_driver_if_yellow_carp.h" |
| 30 | 30 | #include "yellow_carp_ppt.h" |
| 31 | 31 | #include "smu_v13_0_1_ppsmc.h" |
| @@ -186,6 +186,22 @@ err0_out: · 154 unmodified lines | ||
| 186 | 186 | return -ENOMEM; |
| 187 | 187 | } |
| 188 | 188 | |
| 189 | +static int yellow_carp_fini_smc_tables(struct smu_context *smu) | |
| 190 | +{ | |
| 191 | + struct smu_table_context *smu_table = &smu->smu_table; | |
| 192 | + | |
| 193 | + kfree(smu_table->clocks_table); | |
| 194 | + smu_table->clocks_table = NULL; | |
| 195 | + | |
| 196 | + kfree(smu_table->metrics_table); | |
| 197 | + smu_table->metrics_table = NULL; | |
| 198 | + | |
| 199 | + kfree(smu_table->watermarks_table); | |
| 200 | + smu_table->watermarks_table = NULL; | |
| 201 | + | |
| 202 | + return 0; | |
| 203 | +} | |
| 204 | + | |
| 189 | 205 | static int yellow_carp_system_features_control(struct smu_context *smu, bool en) |
| 190 | 206 | { |
| 191 | 207 | struct smu_feature *feature = &smu->smu_feature; |
| @@ -282,13 +298,9 @@ static int yellow_carp_mode_reset(struct smu_context *smu, int type) · 90 unmodified lines | ||
| 282 | 298 | if (index < 0) |
| 283 | 299 | return index == -EACCES ? 0 : index; |
| 284 | 300 | |
| 285 | − mutex_lock(&smu->message_lock); | |
| 286 | − | |
| 287 | − ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); | |
| 288 | − | |
| 289 | − mutex_unlock(&smu->message_lock); | |
| 290 | − | |
| 291 | − mdelay(10); | |
| 301 | + ret = smu_cmn_send_smc_msg_with_param(smu, (uint16_t)index, type, NULL); | |
| 302 | + if (ret) | |
| 303 | + dev_err(smu->adev->dev, "Failed to mode reset!\n"); | |
| 292 | 304 | |
| 293 | 305 | return ret; |
| 294 | 306 | } |
| @@ -659,6 +671,13 @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu, · 364 unmodified lines | ||
| 659 | 671 | return sizeof(struct gpu_metrics_v2_1); |
| 660 | 672 | } |
| 661 | 673 | |
| 674 | +static int yellow_carp_set_default_dpm_tables(struct smu_context *smu) | |
| 675 | +{ | |
| 676 | + struct smu_table_context *smu_table = &smu->smu_table; | |
| 677 | + | |
| 678 | + return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); | |
| 679 | +} | |
| 680 | + | |
| 662 | 681 | static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, |
| 663 | 682 | long input[], uint32_t size) |
| 664 | 683 | { |
| @@ -1203,17 +1222,17 @@ static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *sm · 538 unmodified lines | ||
| 1203 | 1222 | } |
| 1204 | 1223 | |
| 1205 | 1224 | static const struct pptable_funcs yellow_carp_ppt_funcs = { |
| 1206 | − .check_fw_status = smu_v13_0_1_check_fw_status, | |
| 1207 | − .check_fw_version = smu_v13_0_1_check_fw_version, | |
| 1225 | + .check_fw_status = smu_v13_0_check_fw_status, | |
| 1226 | + .check_fw_version = smu_v13_0_check_fw_version, | |
| 1208 | 1227 | .init_smc_tables = yellow_carp_init_smc_tables, |
| 1209 | − .fini_smc_tables = smu_v13_0_1_fini_smc_tables, | |
| 1210 | − .get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values, | |
| 1228 | + .fini_smc_tables = yellow_carp_fini_smc_tables, | |
| 1229 | + .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, | |
| 1211 | 1230 | .system_features_control = yellow_carp_system_features_control, |
| 1212 | 1231 | .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, |
| 1213 | 1232 | .send_smc_msg = smu_cmn_send_smc_msg, |
| 1214 | 1233 | .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable, |
| 1215 | 1234 | .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable, |
| 1216 | − .set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables, | |
| 1235 | + .set_default_dpm_table = yellow_carp_set_default_dpm_tables, | |
| 1217 | 1236 | .read_sensor = yellow_carp_read_sensor, |
| 1218 | 1237 | .is_dpm_running = yellow_carp_is_dpm_running, |
| 1219 | 1238 | .set_watermarks_table = yellow_carp_set_watermarks_table, |
| @@ -1222,8 +1241,8 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = { · 2 unmodified lines | ||
| 1222 | 1241 | .get_gpu_metrics = yellow_carp_get_gpu_metrics, |
| 1223 | 1242 | .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, |
| 1224 | 1243 | .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, |
| 1225 | − .set_driver_table_location = smu_v13_0_1_set_driver_table_location, | |
| 1226 | − .gfx_off_control = smu_v13_0_1_gfx_off_control, | |
| 1244 | + .set_driver_table_location = smu_v13_0_set_driver_table_location, | |
| 1245 | + .gfx_off_control = smu_v13_0_gfx_off_control, | |
| 1227 | 1246 | .post_init = yellow_carp_post_smu_init, |
| 1228 | 1247 | .mode2_reset = yellow_carp_mode2_reset, |
| 1229 | 1248 | .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq, |
| @@ -855,8 +855,6 @@ static int compat_drm_wait_vblank(struct file *file, unsigned int cmd, · 854 unmodified lines | ||
| 855 | 855 | req.request.sequence = req32.request.sequence; |
| 856 | 856 | req.request.signal = req32.request.signal; |
| 857 | 857 | err = drm_ioctl_kernel(file, drm_wait_vblank_ioctl, &req, DRM_UNLOCKED); |
| 858 | − if (err) | |
| 859 | − return err; | |
| 860 | 858 | |
| 861 | 859 | req32.reply.type = req.reply.type; |
| 862 | 860 | req32.reply.sequence = req.reply.sequence; |
| @@ -865,7 +863,7 @@ static int compat_drm_wait_vblank(struct file *file, unsigned int cmd, · 2 unmodified lines | ||
| 865 | 863 | if (copy_to_user(argp, &req32, sizeof(req32))) |
| 866 | 864 | return -EFAULT; |
| 867 | 865 | |
| 868 | − return 0; | |
| 866 | + return err; | |
| 869 | 867 | } |
| 870 | 868 | |
| 871 | 869 | #if defined(CONFIG_X86) |
| @@ -834,6 +834,9 @@ long drm_ioctl(struct file *filp, · 833 unmodified lines | ||
| 834 | 834 | if (drm_dev_is_unplugged(dev)) |
| 835 | 835 | return -ENODEV; |
| 836 | 836 | |
| 837 | + if (DRM_IOCTL_TYPE(cmd) != DRM_IOCTL_BASE) | |
| 838 | + return -ENOTTY; | |
| 839 | + | |
| 837 | 840 | is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END; |
| 838 | 841 | |
| 839 | 842 | if (is_driver_ioctl) { |
| @@ -2166,7 +2166,8 @@ static void · 2165 unmodified lines | ||
| 2166 | 2166 | init_vbt_missing_defaults(struct drm_i915_private *i915) |
| 2167 | 2167 | { |
| 2168 | 2168 | enum port port; |
| 2169 | − int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F; | |
| 2169 | + int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | | |
| 2170 | + BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F); | |
| 2170 | 2171 | |
| 2171 | 2172 | if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) |
| 2172 | 2173 | return; |
| @@ -2463,6 +2463,15 @@ static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, · 2462 unmodified lines | ||
| 2463 | 2463 | } |
| 2464 | 2464 | } |
| 2465 | 2465 | |
| 2466 | +/* Splitter enable for eDP MSO is limited to certain pipes. */ | |
| 2467 | +static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) | |
| 2468 | +{ | |
| 2469 | + if (IS_ALDERLAKE_P(i915)) | |
| 2470 | + return BIT(PIPE_A) | BIT(PIPE_B); | |
| 2471 | + else | |
| 2472 | + return BIT(PIPE_A); | |
| 2473 | +} | |
| 2474 | + | |
| 2466 | 2475 | static void intel_ddi_mso_get_config(struct intel_encoder *encoder, |
| 2467 | 2476 | struct intel_crtc_state *pipe_config) |
| 2468 | 2477 | { |
| @@ -2480,8 +2489,7 @@ static void intel_ddi_mso_get_config(struct intel_encoder *encoder, · 11 unmodified lines | ||
| 2480 | 2489 | if (!pipe_config->splitter.enable) |
| 2481 | 2490 | return; |
| 2482 | 2491 | |
| 2483 | − /* Splitter enable is supported for pipe A only. */ | |
| 2484 | − if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) { | |
| 2492 | + if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { | |
| 2485 | 2493 | pipe_config->splitter.enable = false; |
| 2486 | 2494 | return; |
| 2487 | 2495 | } |
| @@ -2513,10 +2521,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) · 25 unmodified lines | ||
| 2513 | 2521 | return; |
| 2514 | 2522 | |
| 2515 | 2523 | if (crtc_state->splitter.enable) { |
| 2516 | − /* Splitter enable is supported for pipe A only. */ | |
| 2517 | − if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) | |
| 2518 | − return; | |
| 2519 | − | |
| 2520 | 2524 | dss1 |= SPLITTER_ENABLE; |
| 2521 | 2525 | dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); |
| 2522 | 2526 | if (crtc_state->splitter.link_count == 2) |
| @@ -4743,12 +4747,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) · 2220 unmodified lines | ||
| 4743 | 4747 | |
| 4744 | 4748 | dig_port->hpd_pulse = intel_dp_hpd_pulse; |
| 4745 | 4749 | |
| 4746 | − /* Splitter enable for eDP MSO is limited to certain pipes. */ | |
| 4747 | − if (dig_port->dp.mso_link_count) { | |
| 4748 | − encoder->pipe_mask = BIT(PIPE_A); | |
| 4749 | − if (IS_ALDERLAKE_P(dev_priv)) | |
| 4750 | − encoder->pipe_mask |= BIT(PIPE_B); | |
| 4751 | − } | |
| 4750 | + if (dig_port->dp.mso_link_count) | |
| 4751 | + encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); | |
| 4752 | 4752 | } |
| 4753 | 4753 | |
| 4754 | 4754 | /* In theory we don't need the encoder->type check, but leave it just in |
| @@ -5746,16 +5746,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) · 5745 unmodified lines | ||
| 5746 | 5746 | |
| 5747 | 5747 | switch (crtc_state->pipe_bpp) { |
| 5748 | 5748 | case 18: |
| 5749 | − val |= PIPEMISC_DITHER_6_BPC; | |
| 5749 | + val |= PIPEMISC_6_BPC; | |
| 5750 | 5750 | break; |
| 5751 | 5751 | case 24: |
| 5752 | − val |= PIPEMISC_DITHER_8_BPC; | |
| 5752 | + val |= PIPEMISC_8_BPC; | |
| 5753 | 5753 | break; |
| 5754 | 5754 | case 30: |
| 5755 | − val |= PIPEMISC_DITHER_10_BPC; | |
| 5755 | + val |= PIPEMISC_10_BPC; | |
| 5756 | 5756 | break; |
| 5757 | 5757 | case 36: |
| 5758 | − val |= PIPEMISC_DITHER_12_BPC; | |
| 5758 | + /* Port output 12BPC defined for ADLP+ */ | |
| 5759 | + if (DISPLAY_VER(dev_priv) > 12) | |
| 5760 | + val |= PIPEMISC_12_BPC_ADLP; | |
| 5759 | 5761 | break; |
| 5760 | 5762 | default: |
| 5761 | 5763 | MISSING_CASE(crtc_state->pipe_bpp); |
| @@ -5808,15 +5810,27 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) · 46 unmodified lines | ||
| 5808 | 5810 | |
| 5809 | 5811 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); |
| 5810 | 5812 | |
| 5811 | − switch (tmp & PIPEMISC_DITHER_BPC_MASK) { | |
| 5812 | − case PIPEMISC_DITHER_6_BPC: | |
| 5813 | + switch (tmp & PIPEMISC_BPC_MASK) { | |
| 5814 | + case PIPEMISC_6_BPC: | |
| 5813 | 5815 | return 18; |
| 5814 | − case PIPEMISC_DITHER_8_BPC: | |
| 5816 | + case PIPEMISC_8_BPC: | |
| 5815 | 5817 | return 24; |
| 5816 | − case PIPEMISC_DITHER_10_BPC: | |
| 5818 | + case PIPEMISC_10_BPC: | |
| 5817 | 5819 | return 30; |
| 5818 | − case PIPEMISC_DITHER_12_BPC: | |
| 5819 | − return 36; | |
| 5820 | + /* | |
| 5821 | + * PORT OUTPUT 12 BPC defined for ADLP+. | |
| 5822 | + * | |
| 5823 | + * TODO: | |
| 5824 | + * For previous platforms with DSI interface, bits 5:7 | |
| 5825 | + * are used for storing pipe_bpp irrespective of dithering. | |
| 5826 | + * Since the value of 12 BPC is not defined for these bits | |
| 5827 | + * on older platforms, need to find a workaround for 12 BPC | |
| 5828 | + * MIPI DSI HW readout. | |
| 5829 | + */ | |
| 5830 | + case PIPEMISC_12_BPC_ADLP: | |
| 5831 | + if (DISPLAY_VER(dev_priv) > 12) | |
| 5832 | + return 36; | |
| 5833 | + fallthrough; | |
| 5820 | 5834 | default: |
| 5821 | 5835 | MISSING_CASE(tmp); |
| 5822 | 5836 | return 0; |
| @@ -11361,13 +11375,19 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) · 5538 unmodified lines | ||
| 11361 | 11375 | intel_ddi_init(dev_priv, PORT_B); |
| 11362 | 11376 | intel_ddi_init(dev_priv, PORT_C); |
| 11363 | 11377 | vlv_dsi_init(dev_priv); |
| 11364 | − } else if (DISPLAY_VER(dev_priv) >= 9) { | |
| 11378 | + } else if (DISPLAY_VER(dev_priv) == 10) { | |
| 11365 | 11379 | intel_ddi_init(dev_priv, PORT_A); |
| 11366 | 11380 | intel_ddi_init(dev_priv, PORT_B); |
| 11367 | 11381 | intel_ddi_init(dev_priv, PORT_C); |
| 11368 | 11382 | intel_ddi_init(dev_priv, PORT_D); |
| 11369 | 11383 | intel_ddi_init(dev_priv, PORT_E); |
| 11370 | 11384 | intel_ddi_init(dev_priv, PORT_F); |
| 11385 | + } else if (DISPLAY_VER(dev_priv) >= 9) { | |
| 11386 | + intel_ddi_init(dev_priv, PORT_A); | |
| 11387 | + intel_ddi_init(dev_priv, PORT_B); | |
| 11388 | + intel_ddi_init(dev_priv, PORT_C); | |
| 11389 | + intel_ddi_init(dev_priv, PORT_D); | |
| 11390 | + intel_ddi_init(dev_priv, PORT_E); | |
| 11371 | 11391 | } else if (HAS_DDI(dev_priv)) { |
| 11372 | 11392 | u32 found; |
| 11373 | 11393 | |
| @@ -6387,13 +6387,13 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) · 6386 unmodified lines | ||
| 6387 | 6387 | if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || |
| 6388 | 6388 | IS_BROXTON(i915)) { |
| 6389 | 6389 | bxt_enable_dc9(i915); |
| 6390 | − /* Tweaked Wa_14010685332:icp,jsp,mcc */ | |
| 6391 | − if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC) | |
| 6392 | − intel_de_rmw(i915, SOUTH_CHICKEN1, | |
| 6393 | − SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); | |
| 6394 | 6390 | } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { |
| 6395 | 6391 | hsw_enable_pc8(i915); |
| 6396 | 6392 | } |
| 6393 | + | |
| 6394 | + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ | |
| 6395 | + if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) | |
| 6396 | + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); | |
| 6397 | 6397 | } |
| 6398 | 6398 | |
| 6399 | 6399 | void intel_display_power_resume_early(struct drm_i915_private *i915) |
| @@ -6402,13 +6402,13 @@ void intel_display_power_resume_early(struct drm_i915_private *i915) · 2 unmodified lines | ||
| 6402 | 6402 | IS_BROXTON(i915)) { |
| 6403 | 6403 | gen9_sanitize_dc_state(i915); |
| 6404 | 6404 | bxt_disable_dc9(i915); |
| 6405 | − /* Tweaked Wa_14010685332:icp,jsp,mcc */ | |
| 6406 | − if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC) | |
| 6407 | − intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); | |
| 6408 | − | |
| 6409 | 6405 | } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { |
| 6410 | 6406 | hsw_disable_pc8(i915); |
| 6411 | 6407 | } |
| 6408 | + | |
| 6409 | + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ | |
| 6410 | + if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) | |
| 6411 | + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); | |
| 6412 | 6412 | } |
| 6413 | 6413 | |
| 6414 | 6414 | void intel_display_power_suspend(struct drm_i915_private *i915) |
| @@ -206,7 +206,6 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) · 205 unmodified lines | ||
| 206 | 206 | |
| 207 | 207 | return lttpr_count; |
| 208 | 208 | } |
| 209 | −EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps); | |
| 210 | 209 | |
| 211 | 210 | static u8 dp_voltage_max(u8 preemph) |
| 212 | 211 | { |
| @@ -25,10 +25,8 @@ · 24 unmodified lines | ||
| 25 | 25 | #include "i915_gem_clflush.h" |
| 26 | 26 | #include "i915_gem_context.h" |
| 27 | 27 | #include "i915_gem_ioctls.h" |
| 28 | −#include "i915_sw_fence_work.h" | |
| 29 | 28 | #include "i915_trace.h" |
| 30 | 29 | #include "i915_user_extensions.h" |
| 31 | −#include "i915_memcpy.h" | |
| 32 | 30 | |
| 33 | 31 | struct eb_vma { |
| 34 | 32 | struct i915_vma *vma; |
| @@ -1456,6 +1454,10 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, · 1421 unmodified lines | ||
| 1456 | 1454 | int err; |
| 1457 | 1455 | struct intel_engine_cs *engine = eb->engine; |
| 1458 | 1456 | |
| 1457 | + /* If we need to copy for the cmdparser, we will stall anyway */ | |
| 1458 | + if (eb_use_cmdparser(eb)) | |
| 1459 | + return ERR_PTR(-EWOULDBLOCK); | |
| 1460 | + | |
| 1459 | 1461 | if (!reloc_can_use_engine(engine)) { |
| 1460 | 1462 | engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; |
| 1461 | 1463 | if (!engine) |
| @@ -2372,217 +2374,6 @@ shadow_batch_pin(struct i915_execbuffer *eb, · 910 unmodified lines | ||
| 2372 | 2374 | return vma; |
| 2373 | 2375 | } |
| 2374 | 2376 | |
| 2375 | −struct eb_parse_work { | |
| 2376 | − struct dma_fence_work base; | |
| 2377 | − struct intel_engine_cs *engine; | |
| 2378 | − struct i915_vma *batch; | |
| 2379 | − struct i915_vma *shadow; | |
| 2380 | − struct i915_vma *trampoline; | |
| 2381 | − unsigned long batch_offset; | |
| 2382 | − unsigned long batch_length; | |
| 2383 | − unsigned long *jump_whitelist; | |
| 2384 | − const void *batch_map; | |
| 2385 | − void *shadow_map; | |
| 2386 | −}; | |
| 2387 | − | |
| 2388 | −static int __eb_parse(struct dma_fence_work *work) | |
| 2389 | −{ | |
| 2390 | − struct eb_parse_work *pw = container_of(work, typeof(*pw), base); | |
| 2391 | − int ret; | |
| 2392 | − bool cookie; | |
| 2393 | − | |
| 2394 | − cookie = dma_fence_begin_signalling(); | |
| 2395 | − ret = intel_engine_cmd_parser(pw->engine, | |
| 2396 | − pw->batch, | |
| 2397 | − pw->batch_offset, | |
| 2398 | − pw->batch_length, | |
| 2399 | − pw->shadow, | |
| 2400 | − pw->jump_whitelist, | |
| 2401 | − pw->shadow_map, | |
| 2402 | − pw->batch_map); | |
| 2403 | − dma_fence_end_signalling(cookie); | |
| 2404 | − | |
| 2405 | − return ret; | |
| 2406 | −} | |
| 2407 | − | |
| 2408 | −static void __eb_parse_release(struct dma_fence_work *work) | |
| 2409 | −{ | |
| 2410 | − struct eb_parse_work *pw = container_of(work, typeof(*pw), base); | |
| 2411 | − | |
| 2412 | − if (!IS_ERR_OR_NULL(pw->jump_whitelist)) | |
| 2413 | − kfree(pw->jump_whitelist); | |
| 2414 | − | |
| 2415 | − if (pw->batch_map) | |
| 2416 | − i915_gem_object_unpin_map(pw->batch->obj); | |
| 2417 | − else | |
| 2418 | − i915_gem_object_unpin_pages(pw->batch->obj); | |
| 2419 | − | |
| 2420 | − i915_gem_object_unpin_map(pw->shadow->obj); | |
| 2421 | − | |
| 2422 | − if (pw->trampoline) | |
| 2423 | − i915_active_release(&pw->trampoline->active); | |
| 2424 | − i915_active_release(&pw->shadow->active); | |
| 2425 | − i915_active_release(&pw->batch->active); | |
| 2426 | −} | |
| 2427 | − | |
| 2428 | −static const struct dma_fence_work_ops eb_parse_ops = { | |
| 2429 | − .name = "eb_parse", | |
| 2430 | − .work = __eb_parse, | |
| 2431 | − .release = __eb_parse_release, | |
| 2432 | −}; | |
| 2433 | − | |
| 2434 | −static inline int | |
| 2435 | −__parser_mark_active(struct i915_vma *vma, | |
| 2436 | − struct intel_timeline *tl, | |
| 2437 | − struct dma_fence *fence) | |
| 2438 | −{ | |
| 2439 | − struct intel_gt_buffer_pool_node *node = vma->private; | |
| 2440 | − | |
| 2441 | − return i915_active_ref(&node->active, tl->fence_context, fence); | |
| 2442 | −} | |
| 2443 | − | |
| 2444 | −static int | |
| 2445 | −parser_mark_active(struct eb_parse_work *pw, struct intel_timeline *tl) | |
| 2446 | −{ | |
| 2447 | − int err; | |
| 2448 | − | |
| 2449 | − mutex_lock(&tl->mutex); | |
| 2450 | − | |
| 2451 | − err = __parser_mark_active(pw->shadow, tl, &pw->base.dma); | |
| 2452 | − if (err) | |
| 2453 | − goto unlock; | |
| 2454 | − | |
| 2455 | − if (pw->trampoline) { | |
| 2456 | − err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma); | |
| 2457 | − if (err) | |
| 2458 | − goto unlock; | |
| 2459 | − } | |
| 2460 | − | |
| 2461 | −unlock: | |
| 2462 | − mutex_unlock(&tl->mutex); | |
| 2463 | − return err; | |
| 2464 | −} | |
| 2465 | − | |
| 2466 | −static int eb_parse_pipeline(struct i915_execbuffer *eb, | |
| 2467 | − struct i915_vma *shadow, | |
| 2468 | − struct i915_vma *trampoline) | |
| 2469 | −{ | |
| 2470 | − struct eb_parse_work *pw; | |
| 2471 | − struct drm_i915_gem_object *batch = eb->batch->vma->obj; | |
| 2472 | − bool needs_clflush; | |
| 2473 | − int err; | |
| 2474 | − | |
| 2475 | − GEM_BUG_ON(overflows_type(eb->batch_start_offset, pw->batch_offset)); | |
| 2476 | − GEM_BUG_ON(overflows_type(eb->batch_len, pw->batch_length)); | |
| 2477 | − | |
| 2478 | − pw = kzalloc(sizeof(*pw), GFP_KERNEL); | |
| 2479 | − if (!pw) | |
| 2480 | − return -ENOMEM; | |
| 2481 | − | |
| 2482 | − err = i915_active_acquire(&eb->batch->vma->active); | |
| 2483 | − if (err) | |
| 2484 | − goto err_free; | |
| 2485 | − | |
| 2486 | − err = i915_active_acquire(&shadow->active); | |
| 2487 | − if (err) | |
| 2488 | − goto err_batch; | |
| 2489 | − | |
| 2490 | − if (trampoline) { | |
| 2491 | − err = i915_active_acquire(&trampoline->active); | |
| 2492 | − if (err) | |
| 2493 | − goto err_shadow; | |
| 2494 | − } | |
| 2495 | − | |
| 2496 | − pw->shadow_map = i915_gem_object_pin_map(shadow->obj, I915_MAP_WB); | |
| 2497 | − if (IS_ERR(pw->shadow_map)) { | |
| 2498 | − err = PTR_ERR(pw->shadow_map); | |
| 2499 | − goto err_trampoline; | |
| 2500 | − } | |
| 2501 | − | |
| 2502 | − needs_clflush = | |
| 2503 | − !(batch->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ); | |
| 2504 | − | |
| 2505 | − pw->batch_map = ERR_PTR(-ENODEV); | |
| 2506 | − if (needs_clflush && i915_has_memcpy_from_wc()) | |
| 2507 | − pw->batch_map = i915_gem_object_pin_map(batch, I915_MAP_WC); | |
| 2508 | − | |
| 2509 | − if (IS_ERR(pw->batch_map)) { | |
| 2510 | − err = i915_gem_object_pin_pages(batch); | |
| 2511 | − if (err) | |
| 2512 | − goto err_unmap_shadow; | |
| 2513 | − pw->batch_map = NULL; | |
| 2514 | − } | |
| 2515 | − | |
| 2516 | − pw->jump_whitelist = | |
| 2517 | − intel_engine_cmd_parser_alloc_jump_whitelist(eb->batch_len, | |
| 2518 | − trampoline); | |
| 2519 | − if (IS_ERR(pw->jump_whitelist)) { | |
| 2520 | − err = PTR_ERR(pw->jump_whitelist); | |
| 2521 | − goto err_unmap_batch; | |
| 2522 | − } | |
| 2523 | − | |
| 2524 | − dma_fence_work_init(&pw->base, &eb_parse_ops); | |
| 2525 | − | |
| 2526 | − pw->engine = eb->engine; | |
| 2527 | − pw->batch = eb->batch->vma; | |
| 2528 | − pw->batch_offset = eb->batch_start_offset; | |
| 2529 | − pw->batch_length = eb->batch_len; | |
| 2530 | − pw->shadow = shadow; | |
| 2531 | − pw->trampoline = trampoline; | |
| 2532 | − | |
| 2533 | − /* Mark active refs early for this worker, in case we get interrupted */ | |
| 2534 | − err = parser_mark_active(pw, eb->context->timeline); | |
| 2535 | − if (err) | |
| 2536 | − goto err_commit; | |
| 2537 | − | |
| 2538 | − err = dma_resv_reserve_shared(pw->batch->resv, 1); | |
| 2539 | − if (err) | |
| 2540 | − goto err_commit; | |
| 2541 | − | |
| 2542 | − err = dma_resv_reserve_shared(shadow->resv, 1); | |
| 2543 | − if (err) | |
| 2544 | − goto err_commit; | |
| 2545 | − | |
| 2546 | − /* Wait for all writes (and relocs) into the batch to complete */ | |
| 2547 | − err = i915_sw_fence_await_reservation(&pw->base.chain, | |
| 2548 | − pw->batch->resv, NULL, false, | |
| 2549 | − 0, I915_FENCE_GFP); | |
| 2550 | − if (err < 0) | |
| 2551 | − goto err_commit; | |
| 2552 | − | |
| 2553 | − /* Keep the batch alive and unwritten as we parse */ | |
| 2554 | − dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma); | |
| 2555 | − | |
| 2556 | − /* Force execution to wait for completion of the parser */ | |
| 2557 | − dma_resv_add_excl_fence(shadow->resv, &pw->base.dma); | |
| 2558 | − | |
| 2559 | − dma_fence_work_commit_imm(&pw->base); | |
| 2560 | − return 0; | |
| 2561 | − | |
| 2562 | −err_commit: | |
| 2563 | − i915_sw_fence_set_error_once(&pw->base.chain, err); | |
| 2564 | − dma_fence_work_commit_imm(&pw->base); | |
| 2565 | − return err; | |
| 2566 | − | |
| 2567 | −err_unmap_batch: | |
| 2568 | − if (pw->batch_map) | |
| 2569 | − i915_gem_object_unpin_map(batch); | |
| 2570 | − else | |
| 2571 | − i915_gem_object_unpin_pages(batch); | |
| 2572 | −err_unmap_shadow: | |
| 2573 | − i915_gem_object_unpin_map(shadow->obj); | |
| 2574 | −err_trampoline: | |
| 2575 | − if (trampoline) | |
| 2576 | − i915_active_release(&trampoline->active); | |
| 2577 | −err_shadow: | |
| 2578 | − i915_active_release(&shadow->active); | |
| 2579 | −err_batch: | |
| 2580 | − i915_active_release(&eb->batch->vma->active); | |
| 2581 | −err_free: | |
| 2582 | − kfree(pw); | |
| 2583 | − return err; | |
| 2584 | −} | |
| 2585 | − | |
| 2586 | 2377 | static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma) |
| 2587 | 2378 | { |
| 2588 | 2379 | /* |
| @@ -2672,7 +2463,15 @@ static int eb_parse(struct i915_execbuffer *eb) · 83 unmodified lines | ||
| 2672 | 2463 | goto err_trampoline; |
| 2673 | 2464 | } |
| 2674 | 2465 | |
| 2675 | − err = eb_parse_pipeline(eb, shadow, trampoline); | |
| 2466 | + err = dma_resv_reserve_shared(shadow->resv, 1); | |
| 2467 | + if (err) | |
| 2468 | + goto err_trampoline; | |
| 2469 | + | |
| 2470 | + err = intel_engine_cmd_parser(eb->engine, | |
| 2471 | + eb->batch->vma, | |
| 2472 | + eb->batch_start_offset, | |
| 2473 | + eb->batch_len, | |
| 2474 | + shadow, trampoline); | |
| 2676 | 2475 | if (err) |
| 2677 | 2476 | goto err_unpin_batch; |
| 2678 | 2477 | |
| @@ -62,6 +62,7 @@ static void try_to_writeback(struct drm_i915_gem_object *obj, · 61 unmodified lines | ||
| 62 | 62 | switch (obj->mm.madv) { |
| 63 | 63 | case I915_MADV_DONTNEED: |
| 64 | 64 | i915_gem_object_truncate(obj); |
| 65 | + return; | |
| 65 | 66 | case __I915_MADV_PURGED: |
| 66 | 67 | return; |
| 67 | 68 | } |
| @@ -125,6 +125,10 @@ static int igt_gpu_reloc(void *arg) · 124 unmodified lines | ||
| 125 | 125 | intel_gt_pm_get(&eb.i915->gt); |
| 126 | 126 | |
| 127 | 127 | for_each_uabi_engine(eb.engine, eb.i915) { |
| 128 | + if (intel_engine_requires_cmd_parser(eb.engine) || | |
| 129 | + intel_engine_using_cmd_parser(eb.engine)) | |
| 130 | + continue; | |
| 131 | + | |
| 128 | 132 | reloc_cache_init(&eb.reloc_cache, eb.i915); |
| 129 | 133 | memset(map, POISON_INUSE, 4096); |
| 130 | 134 | |
| @@ -303,10 +303,7 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, · 302 unmodified lines | ||
| 303 | 303 | __i915_gem_object_pin_pages(pt->base); |
| 304 | 304 | i915_gem_object_make_unshrinkable(pt->base); |
| 305 | 305 | |
| 306 | − if (lvl || | |
| 307 | − gen8_pt_count(*start, end) < I915_PDES || | |
| 308 | − intel_vgpu_active(vm->i915)) | |
| 309 | − fill_px(pt, vm->scratch[lvl]->encode); | |
| 306 | + fill_px(pt, vm->scratch[lvl]->encode); | |
| 310 | 307 | |
| 311 | 308 | spin_lock(&pd->lock); |
| 312 | 309 | if (likely(!pd->entry[idx])) { |
| @@ -348,7 +348,7 @@ static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt) · 347 unmodified lines | ||
| 348 | 348 | if (intel_has_pending_fb_unpin(ggtt->vm.i915)) |
| 349 | 349 | return ERR_PTR(-EAGAIN); |
| 350 | 350 | |
| 351 | − return ERR_PTR(-EDEADLK); | |
| 351 | + return ERR_PTR(-ENOBUFS); | |
| 352 | 352 | } |
| 353 | 353 | |
| 354 | 354 | int __i915_vma_pin_fence(struct i915_vma *vma) |
| @@ -1977,6 +1977,21 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, · 1976 unmodified lines | ||
| 1977 | 1977 | if (drm_WARN_ON(&i915->drm, !engine)) |
| 1978 | 1978 | return -EINVAL; |
| 1979 | 1979 | |
| 1980 | + /* | |
| 1981 | + * Due to d3_entered is used to indicate skipping PPGTT invalidation on | |
| 1982 | + * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after | |
| 1983 | + * vGPU reset if in resuming. | |
| 1984 | + * In S0ix exit, the device power state also transite from D3 to D0 as | |
| 1985 | + * S3 resume, but no vGPU reset (triggered by QEMU devic model). After | |
| 1986 | + * S0ix exit, all engines continue to work. However the d3_entered | |
| 1987 | + * remains set which will break next vGPU reset logic (miss the expected | |
| 1988 | + * PPGTT invalidation). | |
| 1989 | + * Engines can only work in D0. Thus the 1st elsp write gives GVT a | |
| 1990 | + * chance to clear d3_entered. | |
| 1991 | + */ | |
| 1992 | + if (vgpu->d3_entered) | |
| 1993 | + vgpu->d3_entered = false; | |
| 1994 | + | |
| 1980 | 1995 | execlist = &vgpu->submission.execlist[engine->id]; |
| 1981 | 1996 | |
| 1982 | 1997 | execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; |
| @@ -3134,6 +3149,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt) · 1151 unmodified lines | ||
| 3134 | 3149 | MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); |
| 3135 | 3150 | MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); |
| 3136 | 3151 | MMIO_D(_MMIO(0xb110), D_BDW); |
| 3152 | + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS); | |
| 3137 | 3153 | |
| 3138 | 3154 | MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, |
| 3139 | 3155 | D_BDW_PLUS, NULL, force_nonpriv_write); |
| @@ -105,6 +105,8 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { · 104 unmodified lines | ||
| 105 | 105 | {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ |
| 106 | 106 | {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ |
| 107 | 107 | {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ |
| 108 | + {RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */ | |
| 109 | + {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */ | |
| 108 | 110 | {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ |
| 109 | 111 | {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ |
| 110 | 112 | {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ |
| @@ -1145,19 +1145,41 @@ find_reg(const struct intel_engine_cs *engine, u32 addr) · 1144 unmodified lines | ||
| 1145 | 1145 | static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, |
| 1146 | 1146 | struct drm_i915_gem_object *src_obj, |
| 1147 | 1147 | unsigned long offset, unsigned long length, |
| 1148 | − void *dst, const void *src) | |
| 1148 | + bool *needs_clflush_after) | |
| 1149 | 1149 | { |
| 1150 | − bool needs_clflush = | |
| 1151 | − !(src_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ); | |
| 1152 | − | |
| 1153 | − if (src) { | |
| 1154 | − GEM_BUG_ON(!needs_clflush); | |
| 1155 | − i915_unaligned_memcpy_from_wc(dst, src + offset, length); | |
| 1156 | − } else { | |
| 1157 | − struct scatterlist *sg; | |
| 1150 | + unsigned int src_needs_clflush; | |
| 1151 | + unsigned int dst_needs_clflush; | |
| 1152 | + void *dst, *src; | |
| 1153 | + int ret; | |
| 1154 | + | |
| 1155 | + ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush); | |
| 1156 | + if (ret) | |
| 1157 | + return ERR_PTR(ret); | |
| 1158 | + | |
| 1159 | + dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB); | |
| 1160 | + i915_gem_object_finish_access(dst_obj); | |
| 1161 | + if (IS_ERR(dst)) | |
| 1162 | + return dst; | |
| 1163 | + | |
| 1164 | + ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush); | |
| 1165 | + if (ret) { | |
| 1166 | + i915_gem_object_unpin_map(dst_obj); | |
| 1167 | + return ERR_PTR(ret); | |
| 1168 | + } | |
| 1169 | + | |
| 1170 | + src = ERR_PTR(-ENODEV); | |
| 1171 | + if (src_needs_clflush && i915_has_memcpy_from_wc()) { | |
| 1172 | + src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); | |
| 1173 | + if (!IS_ERR(src)) { | |
| 1174 | + i915_unaligned_memcpy_from_wc(dst, | |
| 1175 | + src + offset, | |
| 1176 | + length); | |
| 1177 | + i915_gem_object_unpin_map(src_obj); | |
| 1178 | + } | |
| 1179 | + } | |
| 1180 | + if (IS_ERR(src)) { | |
| 1181 | + unsigned long x, n, remain; | |
| 1158 | 1182 | void *ptr; |
| 1159 | − unsigned int x, sg_ofs; | |
| 1160 | − unsigned long remain; | |
| 1161 | 1183 | |
| 1162 | 1184 | /* |
| 1163 | 1185 | * We can avoid clflushing partial cachelines before the write |
| @@ -1168,40 +1190,34 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, · 4 unmodified lines | ||
| 1168 | 1190 | * validate up to the end of the batch. |
| 1169 | 1191 | */ |
| 1170 | 1192 | remain = length; |
| 1171 | − if (!(dst_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) | |
| 1193 | + if (dst_needs_clflush & CLFLUSH_BEFORE) | |
| 1172 | 1194 | remain = round_up(remain, |
| 1173 | 1195 | boot_cpu_data.x86_clflush_size); |
| 1174 | 1196 | |
| 1175 | 1197 | ptr = dst; |
| 1176 | 1198 | x = offset_in_page(offset); |
| 1177 | − sg = i915_gem_object_get_sg(src_obj, offset >> PAGE_SHIFT, &sg_ofs, false); | |
| 1178 | − | |
| 1179 | − while (remain) { | |
| 1180 | − unsigned long sg_max = sg->length >> PAGE_SHIFT; | |
| 1181 | − | |
| 1182 | − for (; remain && sg_ofs < sg_max; sg_ofs++) { | |
| 1183 | − unsigned long len = min(remain, PAGE_SIZE - x); | |
| 1184 | − void *map; | |
| 1185 | − | |
| 1186 | − map = kmap_atomic(nth_page(sg_page(sg), sg_ofs)); | |
| 1187 | − if (needs_clflush) | |
| 1188 | − drm_clflush_virt_range(map + x, len); | |
| 1189 | − memcpy(ptr, map + x, len); | |
| 1190 | − kunmap_atomic(map); | |
| 1191 | − | |
| 1192 | − ptr += len; | |
| 1193 | − remain -= len; | |
| 1194 | − x = 0; | |
| 1195 | − } | |
| 1196 | − | |
| 1197 | − sg_ofs = 0; | |
| 1198 | − sg = sg_next(sg); | |
| 1199 | + for (n = offset >> PAGE_SHIFT; remain; n++) { | |
| 1200 | + int len = min(remain, PAGE_SIZE - x); | |
| 1201 | + | |
| 1202 | + src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); | |
| 1203 | + if (src_needs_clflush) | |
| 1204 | + drm_clflush_virt_range(src + x, len); | |
| 1205 | + memcpy(ptr, src + x, len); | |
| 1206 | + kunmap_atomic(src); | |
| 1207 | + | |
| 1208 | + ptr += len; | |
| 1209 | + remain -= len; | |
| 1210 | + x = 0; | |
| 1199 | 1211 | } |
| 1200 | 1212 | } |
| 1201 | 1213 | |
| 1214 | + i915_gem_object_finish_access(src_obj); | |
| 1215 | + | |
| 1202 | 1216 | memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32)); |
| 1203 | 1217 | |
| 1204 | 1218 | /* dst_obj is returned with vmap pinned */ |
| 1219 | + *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER; | |
| 1220 | + | |
| 1205 | 1221 | return dst; |
| 1206 | 1222 | } |
| 1207 | 1223 | |
| @@ -1360,6 +1376,9 @@ static int check_bbstart(u32 *cmd, u32 offset, u32 length, · 152 unmodified lines | ||
| 1360 | 1376 | if (target_cmd_index == offset) |
| 1361 | 1377 | return 0; |
| 1362 | 1378 | |
| 1379 | + if (IS_ERR(jump_whitelist)) | |
| 1380 | + return PTR_ERR(jump_whitelist); | |
| 1381 | + | |
| 1363 | 1382 | if (!test_bit(target_cmd_index, jump_whitelist)) { |
| 1364 | 1383 | DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n", |
| 1365 | 1384 | jump_target); |
| @@ -1369,28 +1388,10 @@ static int check_bbstart(u32 *cmd, u32 offset, u32 length, · 3 unmodified lines | ||
| 1369 | 1388 | return 0; |
| 1370 | 1389 | } |
| 1371 | 1390 | |
| 1372 | −/** | |
| 1373 | − * intel_engine_cmd_parser_alloc_jump_whitelist() - preallocate jump whitelist for intel_engine_cmd_parser() | |
| 1374 | − * @batch_length: length of the commands in batch_obj | |
| 1375 | − * @trampoline: Whether jump trampolines are used. | |
| 1376 | − * | |
| 1377 | − * Preallocates a jump whitelist for parsing the cmd buffer in intel_engine_cmd_parser(). | |
| 1378 | − * This has to be preallocated, because the command parser runs in signaling context, | |
| 1379 | − * and may not allocate any memory. | |
| 1380 | − * | |
| 1381 | − * Return: NULL or pointer to a jump whitelist, or ERR_PTR() on failure. Use | |
| 1382 | − * IS_ERR() to check for errors. Must bre freed() with kfree(). | |
| 1383 | − * | |
| 1384 | − * NULL is a valid value, meaning no allocation was required. | |
| 1385 | − */ | |
| 1386 | −unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, | |
| 1387 | − bool trampoline) | |
| 1391 | +static unsigned long *alloc_whitelist(u32 batch_length) | |
| 1388 | 1392 | { |
| 1389 | 1393 | unsigned long *jmp; |
| 1390 | 1394 | |
| 1391 | − if (trampoline) | |
| 1392 | − return NULL; | |
| 1393 | − | |
| 1394 | 1395 | /* |
| 1395 | 1396 | * We expect batch_length to be less than 256KiB for known users, |
| 1396 | 1397 | * i.e. we need at most an 8KiB bitmap allocation which should be |
| @@ -1415,9 +1416,7 @@ unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, · 18 unmodified lines | ||
| 1415 | 1416 | * @batch_offset: byte offset in the batch at which execution starts |
| 1416 | 1417 | * @batch_length: length of the commands in batch_obj |
| 1417 | 1418 | * @shadow: validated copy of the batch buffer in question |
| 1418 | − * @jump_whitelist: buffer preallocated with intel_engine_cmd_parser_alloc_jump_whitelist() | |
| 1419 | − * @shadow_map: mapping to @shadow vma | |
| 1420 | − * @batch_map: mapping to @batch vma | |
| 1419 | + * @trampoline: true if we need to trampoline into privileged execution | |
| 1421 | 1420 | * |
| 1422 | 1421 | * Parses the specified batch buffer looking for privilege violations as |
| 1423 | 1422 | * described in the overview. |
| @@ -1425,21 +1424,21 @@ unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, · 1 unmodified line | ||
| 1425 | 1424 | * Return: non-zero if the parser finds violations or otherwise fails; -EACCES |
| 1426 | 1425 | * if the batch appears legal but should use hardware parsing |
| 1427 | 1426 | */ |
| 1427 | + | |
| 1428 | 1428 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
| 1429 | 1429 | struct i915_vma *batch, |
| 1430 | 1430 | unsigned long batch_offset, |
| 1431 | 1431 | unsigned long batch_length, |
| 1432 | 1432 | struct i915_vma *shadow, |
| 1433 | − unsigned long *jump_whitelist, | |
| 1434 | − void *shadow_map, | |
| 1435 | − const void *batch_map) | |
| 1433 | + bool trampoline) | |
| 1436 | 1434 | { |
| 1437 | 1435 | u32 *cmd, *batch_end, offset = 0; |
| 1438 | 1436 | struct drm_i915_cmd_descriptor default_desc = noop_desc; |
| 1439 | 1437 | const struct drm_i915_cmd_descriptor *desc = &default_desc; |
| 1438 | + bool needs_clflush_after = false; | |
| 1439 | + unsigned long *jump_whitelist; | |
| 1440 | 1440 | u64 batch_addr, shadow_addr; |
| 1441 | 1441 | int ret = 0; |
| 1442 | − bool trampoline = !jump_whitelist; | |
| 1443 | 1442 | |
| 1444 | 1443 | GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd))); |
| 1445 | 1444 | GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd))); |
| @@ -1447,8 +1446,18 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, · 1 unmodified line | ||
| 1447 | 1446 | batch->size)); |
| 1448 | 1447 | GEM_BUG_ON(!batch_length); |
| 1449 | 1448 | |
| 1450 | − cmd = copy_batch(shadow->obj, batch->obj, batch_offset, batch_length, | |
| 1451 | − shadow_map, batch_map); | |
| 1449 | + cmd = copy_batch(shadow->obj, batch->obj, | |
| 1450 | + batch_offset, batch_length, | |
| 1451 | + &needs_clflush_after); | |
| 1452 | + if (IS_ERR(cmd)) { | |
| 1453 | + DRM_DEBUG("CMD: Failed to copy batch\n"); | |
| 1454 | + return PTR_ERR(cmd); | |
| 1455 | + } | |
| 1456 | + | |
| 1457 | + jump_whitelist = NULL; | |
| 1458 | + if (!trampoline) | |
| 1459 | + /* Defer failure until attempted use */ | |
| 1460 | + jump_whitelist = alloc_whitelist(batch_length); | |
| 1452 | 1461 | |
| 1453 | 1462 | shadow_addr = gen8_canonical_addr(shadow->node.start); |
| 1454 | 1463 | batch_addr = gen8_canonical_addr(batch->node.start + batch_offset); |
| @@ -1549,6 +1558,9 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, · 94 unmodified lines | ||
| 1549 | 1558 | |
| 1550 | 1559 | i915_gem_object_flush_map(shadow->obj); |
| 1551 | 1560 | |
| 1561 | + if (!IS_ERR_OR_NULL(jump_whitelist)) | |
| 1562 | + kfree(jump_whitelist); | |
| 1563 | + i915_gem_object_unpin_map(shadow->obj); | |
| 1552 | 1564 | return ret; |
| 1553 | 1565 | } |
| 1554 | 1566 | |
| @@ -1906,17 +1906,12 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type); · 1905 unmodified lines | ||
| 1906 | 1906 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
| 1907 | 1907 | int intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
| 1908 | 1908 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
| 1909 | −unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, | |
| 1910 | − bool trampoline); | |
| 1911 | − | |
| 1912 | 1909 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
| 1913 | 1910 | struct i915_vma *batch, |
| 1914 | 1911 | unsigned long batch_offset, |
| 1915 | 1912 | unsigned long batch_length, |
| 1916 | 1913 | struct i915_vma *shadow, |
| 1917 | − unsigned long *jump_whitelist, | |
| 1918 | − void *shadow_map, | |
| 1919 | − const void *batch_map); | |
| 1914 | + bool trampoline); | |
| 1920 | 1915 | #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 |
| 1921 | 1916 | |
| 1922 | 1917 | /* intel_device_info.c */ |
| @@ -138,7 +138,7 @@ void i915_globals_unpark(void) · 137 unmodified lines | ||
| 138 | 138 | atomic_inc(&active); |
| 139 | 139 | } |
| 140 | 140 | |
| 141 | −static void __exit __i915_globals_flush(void) | |
| 141 | +static void __i915_globals_flush(void) | |
| 142 | 142 | { |
| 143 | 143 | atomic_inc(&active); /* skip shrinking */ |
| 144 | 144 | |
| @@ -148,7 +148,7 @@ static void __exit __i915_globals_flush(void) · 3 unmodified lines | ||
| 148 | 148 | atomic_dec(&active); |
| 149 | 149 | } |
| 150 | 150 | |
| 151 | −void __exit i915_globals_exit(void) | |
| 151 | +void i915_globals_exit(void) | |
| 152 | 152 | { |
| 153 | 153 | GEM_BUG_ON(atomic_read(&active)); |
| 154 | 154 | |
| @@ -727,9 +727,18 @@ static void err_print_gt(struct drm_i915_error_state_buf *m, · 726 unmodified lines | ||
| 727 | 727 | if (GRAPHICS_VER(m->i915) >= 12) { |
| 728 | 728 | int i; |
| 729 | 729 | |
| 730 | − for (i = 0; i < GEN12_SFC_DONE_MAX; i++) | |
| 730 | + for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { | |
| 731 | + /* | |
| 732 | + * SFC_DONE resides in the VD forcewake domain, so it | |
| 733 | + * only exists if the corresponding VCS engine is | |
| 734 | + * present. | |
| 735 | + */ | |
| 736 | + if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) | |
| 737 | + continue; | |
| 738 | + | |
| 731 | 739 | err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, |
| 732 | 740 | gt->sfc_done[i]); |
| 741 | + } | |
| 733 | 742 | |
| 734 | 743 | err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); |
| 735 | 744 | } |
| @@ -1581,6 +1590,14 @@ static void gt_record_regs(struct intel_gt_coredump *gt) · 845 unmodified lines | ||
| 1581 | 1590 | |
| 1582 | 1591 | if (GRAPHICS_VER(i915) >= 12) { |
| 1583 | 1592 | for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { |
| 1593 | + /* | |
| 1594 | + * SFC_DONE resides in the VD forcewake domain, so it | |
| 1595 | + * only exists if the corresponding VCS engine is | |
| 1596 | + * present. | |
| 1597 | + */ | |
| 1598 | + if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) | |
| 1599 | + continue; | |
| 1600 | + | |
| 1584 | 1601 | gt->sfc_done[i] = |
| 1585 | 1602 | intel_uncore_read(uncore, GEN12_SFC_DONE(i)); |
| 1586 | 1603 | } |
| @@ -3064,24 +3064,6 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv) · 3063 unmodified lines | ||
| 3064 | 3064 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3065 | 3065 | } |
| 3066 | 3066 | |
| 3067 | −static void cnp_display_clock_wa(struct drm_i915_private *dev_priv) | |
| 3068 | −{ | |
| 3069 | − struct intel_uncore *uncore = &dev_priv->uncore; | |
| 3070 | − | |
| 3071 | − /* | |
| 3072 | − * Wa_14010685332:cnp/cmp,tgp,adp | |
| 3073 | − * TODO: Clarify which platforms this applies to | |
| 3074 | − * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as | |
| 3075 | − * on earlier platforms and whether the workaround is also needed for runtime suspend/resume | |
| 3076 | − */ | |
| 3077 | − if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP || | |
| 3078 | − (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) { | |
| 3079 | − intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, | |
| 3080 | − SBCLK_RUN_REFCLK_DIS); | |
| 3081 | − intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); | |
| 3082 | − } | |
| 3083 | −} | |
| 3084 | − | |
| 3085 | 3067 | static void gen8_display_irq_reset(struct drm_i915_private *dev_priv) |
| 3086 | 3068 | { |
| 3087 | 3069 | struct intel_uncore *uncore = &dev_priv->uncore; |
| @@ -3115,7 +3097,6 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv) · 27 unmodified lines | ||
| 3115 | 3097 | if (HAS_PCH_SPLIT(dev_priv)) |
| 3116 | 3098 | ibx_irq_reset(dev_priv); |
| 3117 | 3099 | |
| 3118 | − cnp_display_clock_wa(dev_priv); | |
| 3119 | 3100 | } |
| 3120 | 3101 | |
| 3121 | 3102 | static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) |
| @@ -3159,8 +3140,6 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) · 37 unmodified lines | ||
| 3159 | 3140 | |
| 3160 | 3141 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
| 3161 | 3142 | GEN3_IRQ_RESET(uncore, SDE); |
| 3162 | − | |
| 3163 | − cnp_display_clock_wa(dev_priv); | |
| 3164 | 3143 | } |
| 3165 | 3144 | |
| 3166 | 3145 | static void gen11_irq_reset(struct drm_i915_private *dev_priv) |
| @@ -1195,6 +1195,7 @@ static int __init i915_init(void) · 1194 unmodified lines | ||
| 1195 | 1195 | err = pci_register_driver(&i915_pci_driver); |
| 1196 | 1196 | if (err) { |
| 1197 | 1197 | i915_pmu_exit(); |
| 1198 | + i915_globals_exit(); | |
| 1198 | 1199 | return err; |
| 1199 | 1200 | } |
| 1200 | 1201 | |
| @@ -422,7 +422,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 421 unmodified lines | ||
| 422 | 422 | #define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1) |
| 423 | 423 | #define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0) |
| 424 | 424 | |
| 425 | −#define GEN12_SFC_DONE(n) _MMIO(0x1cc00 + (n) * 0x100) | |
| 425 | +#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) | |
| 426 | 426 | #define GEN12_SFC_DONE_MAX 4 |
| 427 | 427 | |
| 428 | 428 | #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) |
| @@ -6163,11 +6163,17 @@ enum { · 5734 unmodified lines | ||
| 6163 | 6163 | #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ |
| 6164 | 6164 | #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) |
| 6165 | 6165 | #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ |
| 6166 | −#define PIPEMISC_DITHER_BPC_MASK (7 << 5) | |
| 6167 | −#define PIPEMISC_DITHER_8_BPC (0 << 5) | |
| 6168 | −#define PIPEMISC_DITHER_10_BPC (1 << 5) | |
| 6169 | −#define PIPEMISC_DITHER_6_BPC (2 << 5) | |
| 6170 | −#define PIPEMISC_DITHER_12_BPC (3 << 5) | |
| 6166 | +/* | |
| 6167 | + * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with | |
| 6168 | + * valid values of: 6, 8, 10 BPC. | |
| 6169 | + * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: | |
| 6170 | + * 6, 8, 10, 12 BPC. | |
| 6171 | + */ | |
| 6172 | +#define PIPEMISC_BPC_MASK (7 << 5) | |
| 6173 | +#define PIPEMISC_8_BPC (0 << 5) | |
| 6174 | +#define PIPEMISC_10_BPC (1 << 5) | |
| 6175 | +#define PIPEMISC_6_BPC (2 << 5) | |
| 6176 | +#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */ | |
| 6171 | 6177 | #define PIPEMISC_DITHER_ENABLE (1 << 4) |
| 6172 | 6178 | #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) |
| 6173 | 6179 | #define PIPEMISC_DITHER_TYPE_SP (0 << 2) |
| @@ -1426,10 +1426,8 @@ i915_request_await_execution(struct i915_request *rq, · 1425 unmodified lines | ||
| 1426 | 1426 | |
| 1427 | 1427 | do { |
| 1428 | 1428 | fence = *child++; |
| 1429 | − if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { | |
| 1430 | − i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
| 1429 | + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
| 1431 | 1430 | continue; |
| 1432 | − } | |
| 1433 | 1431 | |
| 1434 | 1432 | if (fence->context == rq->fence.context) |
| 1435 | 1433 | continue; |
| @@ -1527,10 +1525,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) · 91 unmodified lines | ||
| 1527 | 1525 | |
| 1528 | 1526 | do { |
| 1529 | 1527 | fence = *child++; |
| 1530 | − if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { | |
| 1531 | − i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
| 1528 | + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
| 1532 | 1529 | continue; |
| 1533 | − } | |
| 1534 | 1530 | |
| 1535 | 1531 | /* |
| 1536 | 1532 | * Requests on the same timeline are explicitly ordered, along |
| @@ -325,7 +325,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 324 unmodified lines | ||
| 325 | 325 | info->pipe_mask &= ~BIT(PIPE_C); |
| 326 | 326 | info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); |
| 327 | 327 | } |
| 328 | − } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) { | |
| 328 | + } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { | |
| 329 | 329 | u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); |
| 330 | 330 | |
| 331 | 331 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { |
| @@ -340,7 +340,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 8 unmodified lines | ||
| 340 | 340 | info->pipe_mask &= ~BIT(PIPE_C); |
| 341 | 341 | info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); |
| 342 | 342 | } |
| 343 | − if (GRAPHICS_VER(dev_priv) >= 12 && | |
| 343 | + | |
| 344 | + if (DISPLAY_VER(dev_priv) >= 12 && | |
| 344 | 345 | (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { |
| 345 | 346 | info->pipe_mask &= ~BIT(PIPE_D); |
| 346 | 347 | info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); |
| @@ -352,10 +353,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 5 unmodified lines | ||
| 352 | 353 | if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) |
| 353 | 354 | info->display.has_fbc = 0; |
| 354 | 355 | |
| 355 | − if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) | |
| 356 | + if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) | |
| 356 | 357 | info->display.has_dmc = 0; |
| 357 | 358 | |
| 358 | − if (GRAPHICS_VER(dev_priv) >= 10 && | |
| 359 | + if (DISPLAY_VER(dev_priv) >= 10 && | |
| 359 | 360 | (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) |
| 360 | 361 | info->display.has_dsc = 0; |
| 361 | 362 | } |
| @@ -203,6 +203,7 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) · 202 unmodified lines | ||
| 203 | 203 | unsigned long status, val, val1; |
| 204 | 204 | int plane_id, dma0_state, dma1_state; |
| 205 | 205 | struct kmb_drm_private *kmb = to_kmb(dev); |
| 206 | + u32 ctrl = 0; | |
| 206 | 207 | |
| 207 | 208 | status = kmb_read_lcd(kmb, LCD_INT_STATUS); |
| 208 | 209 | |
| @@ -227,6 +228,19 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) · 18 unmodified lines | ||
| 227 | 228 | kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, |
| 228 | 229 | kmb->plane_status[plane_id].ctrl); |
| 229 | 230 | |
| 231 | + ctrl = kmb_read_lcd(kmb, LCD_CONTROL); | |
| 232 | + if (!(ctrl & (LCD_CTRL_VL1_ENABLE | | |
| 233 | + LCD_CTRL_VL2_ENABLE | | |
| 234 | + LCD_CTRL_GL1_ENABLE | | |
| 235 | + LCD_CTRL_GL2_ENABLE))) { | |
| 236 | + /* If no LCD layers are using DMA, | |
| 237 | + * then disable DMA pipelined AXI read | |
| 238 | + * transactions. | |
| 239 | + */ | |
| 240 | + kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, | |
| 241 | + LCD_CTRL_PIPELINE_DMA); | |
| 242 | + } | |
| 243 | + | |
| 230 | 244 | kmb->plane_status[plane_id].disable = false; |
| 231 | 245 | } |
| 232 | 246 | } |
| @@ -411,10 +425,10 @@ static const struct drm_driver kmb_driver = { · 178 unmodified lines | ||
| 411 | 425 | .fops = &fops, |
| 412 | 426 | DRM_GEM_CMA_DRIVER_OPS_VMAP, |
| 413 | 427 | .name = "kmb-drm", |
| 414 | − .desc = "KEEMBAY DISPLAY DRIVER ", | |
| 415 | − .date = "20201008", | |
| 416 | − .major = 1, | |
| 417 | − .minor = 0, | |
| 428 | + .desc = "KEEMBAY DISPLAY DRIVER", | |
| 429 | + .date = DRIVER_DATE, | |
| 430 | + .major = DRIVER_MAJOR, | |
| 431 | + .minor = DRIVER_MINOR, | |
| 418 | 432 | }; |
| 419 | 433 | |
| 420 | 434 | static int kmb_remove(struct platform_device *pdev) |
| @@ -15,6 +15,11 @@ · 14 unmodified lines | ||
| 15 | 15 | #define KMB_MAX_HEIGHT 1080 /*Max height in pixels */ |
| 16 | 16 | #define KMB_MIN_WIDTH 1920 /*Max width in pixels */ |
| 17 | 17 | #define KMB_MIN_HEIGHT 1080 /*Max height in pixels */ |
| 18 | + | |
| 19 | +#define DRIVER_DATE "20210223" | |
| 20 | +#define DRIVER_MAJOR 1 | |
| 21 | +#define DRIVER_MINOR 1 | |
| 22 | + | |
| 18 | 23 | #define KMB_LCD_DEFAULT_CLK 200000000 |
| 19 | 24 | #define KMB_SYS_CLK_MHZ 500 |
| 20 | 25 | |
| @@ -427,8 +427,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, · 426 unmodified lines | ||
| 427 | 427 | |
| 428 | 428 | kmb_set_bitmask_lcd(kmb, LCD_CONTROL, ctrl); |
| 429 | 429 | |
| 430 | − /* FIXME no doc on how to set output format,these values are | |
| 431 | − * taken from the Myriadx tests | |
| 430 | + /* Enable pipeline AXI read transactions for the DMA | |
| 431 | + * after setting graphics layers. This must be done | |
| 432 | + * in a separate write cycle. | |
| 433 | + */ | |
| 434 | + kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA); | |
| 435 | + | |
| 436 | + /* FIXME no doc on how to set output format, these values are taken | |
| 437 | + * from the Myriadx tests | |
| 432 | 438 | */ |
| 433 | 439 | out_format |= LCD_OUTF_FORMAT_RGB888; |
| 434 | 440 | |
| @@ -526,6 +532,11 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) · 91 unmodified lines | ||
| 526 | 532 | plane->id = i; |
| 527 | 533 | } |
| 528 | 534 | |
| 535 | + /* Disable pipeline AXI read transactions for the DMA | |
| 536 | + * prior to setting graphics layers | |
| 537 | + */ | |
| 538 | + kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA); | |
| 539 | + | |
| 529 | 540 | return primary; |
| 530 | 541 | cleanup: |
| 531 | 542 | drmm_kfree(drm, plane); |
| @@ -133,6 +133,8 @@ static int mtk_disp_color_probe(struct platform_device *pdev) · 132 unmodified lines | ||
| 133 | 133 | |
| 134 | 134 | static int mtk_disp_color_remove(struct platform_device *pdev) |
| 135 | 135 | { |
| 136 | + component_del(&pdev->dev, &mtk_disp_color_component_ops); | |
| 137 | + | |
| 136 | 138 | return 0; |
| 137 | 139 | } |
| 138 | 140 | |
| @@ -423,6 +423,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) · 422 unmodified lines | ||
| 423 | 423 | |
| 424 | 424 | static int mtk_disp_ovl_remove(struct platform_device *pdev) |
| 425 | 425 | { |
| 426 | + component_del(&pdev->dev, &mtk_disp_ovl_component_ops); | |
| 427 | + | |
| 426 | 428 | return 0; |
| 427 | 429 | } |
| 428 | 430 | |
| @@ -605,11 +605,15 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, · 604 unmodified lines | ||
| 605 | 605 | struct drm_crtc_state *crtc_state, |
| 606 | 606 | struct drm_connector_state *conn_state) |
| 607 | 607 | { |
| 608 | − struct mtk_dpi *dpi = bridge->driver_private; | |
| 608 | + struct mtk_dpi *dpi = bridge_to_dpi(bridge); | |
| 609 | 609 | unsigned int out_bus_format; |
| 610 | 610 | |
| 611 | 611 | out_bus_format = bridge_state->output_bus_cfg.format; |
| 612 | 612 | |
| 613 | + if (out_bus_format == MEDIA_BUS_FMT_FIXED) | |
| 614 | + if (dpi->conf->num_output_fmts) | |
| 615 | + out_bus_format = dpi->conf->output_fmts[0]; | |
| 616 | + | |
| 613 | 617 | dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", |
| 614 | 618 | bridge_state->input_bus_cfg.format, |
| 615 | 619 | bridge_state->output_bus_cfg.format); |
| @@ -532,13 +532,10 @@ void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, · 531 unmodified lines | ||
| 532 | 532 | struct drm_atomic_state *state) |
| 533 | 533 | { |
| 534 | 534 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); |
| 535 | − const struct drm_plane_helper_funcs *plane_helper_funcs = | |
| 536 | − plane->helper_private; | |
| 537 | 535 | |
| 538 | 536 | if (!mtk_crtc->enabled) |
| 539 | 537 | return; |
| 540 | 538 | |
| 541 | − plane_helper_funcs->atomic_update(plane, state); | |
| 542 | 539 | mtk_drm_crtc_update_config(mtk_crtc, false); |
| 543 | 540 | } |
| 544 | 541 | |
| @@ -34,6 +34,7 @@ · 33 unmodified lines | ||
| 34 | 34 | |
| 35 | 35 | #define DISP_AAL_EN 0x0000 |
| 36 | 36 | #define DISP_AAL_SIZE 0x0030 |
| 37 | +#define DISP_AAL_OUTPUT_SIZE 0x04d8 | |
| 37 | 38 | |
| 38 | 39 | #define DISP_DITHER_EN 0x0000 |
| 39 | 40 | #define DITHER_EN BIT(0) |
| @@ -197,6 +198,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w, · 157 unmodified lines | ||
| 197 | 198 | struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); |
| 198 | 199 | |
| 199 | 200 | mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); |
| 201 | + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_OUTPUT_SIZE); | |
| 200 | 202 | } |
| 201 | 203 | |
| 202 | 204 | static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) |
| @@ -110,6 +110,35 @@ static int mtk_plane_atomic_async_check(struct drm_plane *plane, · 109 unmodified lines | ||
| 110 | 110 | true, true); |
| 111 | 111 | } |
| 112 | 112 | |
| 113 | +static void mtk_plane_update_new_state(struct drm_plane_state *new_state, | |
| 114 | + struct mtk_plane_state *mtk_plane_state) | |
| 115 | +{ | |
| 116 | + struct drm_framebuffer *fb = new_state->fb; | |
| 117 | + struct drm_gem_object *gem; | |
| 118 | + struct mtk_drm_gem_obj *mtk_gem; | |
| 119 | + unsigned int pitch, format; | |
| 120 | + dma_addr_t addr; | |
| 121 | + | |
| 122 | + gem = fb->obj[0]; | |
| 123 | + mtk_gem = to_mtk_gem_obj(gem); | |
| 124 | + addr = mtk_gem->dma_addr; | |
| 125 | + pitch = fb->pitches[0]; | |
| 126 | + format = fb->format->format; | |
| 127 | + | |
| 128 | + addr += (new_state->src.x1 >> 16) * fb->format->cpp[0]; | |
| 129 | + addr += (new_state->src.y1 >> 16) * pitch; | |
| 130 | + | |
| 131 | + mtk_plane_state->pending.enable = true; | |
| 132 | + mtk_plane_state->pending.pitch = pitch; | |
| 133 | + mtk_plane_state->pending.format = format; | |
| 134 | + mtk_plane_state->pending.addr = addr; | |
| 135 | + mtk_plane_state->pending.x = new_state->dst.x1; | |
| 136 | + mtk_plane_state->pending.y = new_state->dst.y1; | |
| 137 | + mtk_plane_state->pending.width = drm_rect_width(&new_state->dst); | |
| 138 | + mtk_plane_state->pending.height = drm_rect_height(&new_state->dst); | |
| 139 | + mtk_plane_state->pending.rotation = new_state->rotation; | |
| 140 | +} | |
| 141 | + | |
| 113 | 142 | static void mtk_plane_atomic_async_update(struct drm_plane *plane, |
| 114 | 143 | struct drm_atomic_state *state) |
| 115 | 144 | { |
| @@ -126,8 +155,10 @@ static void mtk_plane_atomic_async_update(struct drm_plane *plane, · 10 unmodified lines | ||
| 126 | 155 | plane->state->src_h = new_state->src_h; |
| 127 | 156 | plane->state->src_w = new_state->src_w; |
| 128 | 157 | swap(plane->state->fb, new_state->fb); |
| 129 | − new_plane_state->pending.async_dirty = true; | |
| 130 | 158 | |
| 159 | + mtk_plane_update_new_state(new_state, new_plane_state); | |
| 160 | + wmb(); /* Make sure the above parameters are set before update */ | |
| 161 | + new_plane_state->pending.async_dirty = true; | |
| 131 | 162 | mtk_drm_crtc_async_update(new_state->crtc, plane, state); |
| 132 | 163 | } |
| 133 | 164 | |
| @@ -189,14 +220,8 @@ static void mtk_plane_atomic_update(struct drm_plane *plane, · 55 unmodified lines | ||
| 189 | 220 | struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, |
| 190 | 221 | plane); |
| 191 | 222 | struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(new_state); |
| 192 | − struct drm_crtc *crtc = new_state->crtc; | |
| 193 | − struct drm_framebuffer *fb = new_state->fb; | |
| 194 | − struct drm_gem_object *gem; | |
| 195 | − struct mtk_drm_gem_obj *mtk_gem; | |
| 196 | − unsigned int pitch, format; | |
| 197 | − dma_addr_t addr; | |
| 198 | 223 | |
| 199 | − if (!crtc || WARN_ON(!fb)) | |
| 224 | + if (!new_state->crtc || WARN_ON(!new_state->fb)) | |
| 200 | 225 | return; |
| 201 | 226 | |
| 202 | 227 | if (!new_state->visible) { |
| @@ -204,24 +229,7 @@ static void mtk_plane_atomic_update(struct drm_plane *plane, · 1 unmodified line | ||
| 204 | 229 | return; |
| 205 | 230 | } |
| 206 | 231 | |
| 207 | − gem = fb->obj[0]; | |
| 208 | − mtk_gem = to_mtk_gem_obj(gem); | |
| 209 | − addr = mtk_gem->dma_addr; | |
| 210 | − pitch = fb->pitches[0]; | |
| 211 | − format = fb->format->format; | |
| 212 | − | |
| 213 | − addr += (new_state->src.x1 >> 16) * fb->format->cpp[0]; | |
| 214 | − addr += (new_state->src.y1 >> 16) * pitch; | |
| 215 | − | |
| 216 | − mtk_plane_state->pending.enable = true; | |
| 217 | − mtk_plane_state->pending.pitch = pitch; | |
| 218 | − mtk_plane_state->pending.format = format; | |
| 219 | − mtk_plane_state->pending.addr = addr; | |
| 220 | − mtk_plane_state->pending.x = new_state->dst.x1; | |
| 221 | − mtk_plane_state->pending.y = new_state->dst.y1; | |
| 222 | − mtk_plane_state->pending.width = drm_rect_width(&new_state->dst); | |
| 223 | − mtk_plane_state->pending.height = drm_rect_height(&new_state->dst); | |
| 224 | − mtk_plane_state->pending.rotation = new_state->rotation; | |
| 232 | + mtk_plane_update_new_state(new_state, mtk_plane_state); | |
| 225 | 233 | wmb(); /* Make sure the above parameters are set before update */ |
| 226 | 234 | mtk_plane_state->pending.dirty = true; |
| 227 | 235 | } |
| @@ -634,6 +634,11 @@ · 633 unmodified lines | ||
| 634 | 634 | #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc |
| 635 | 635 | #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd |
| 636 | 636 | |
| 637 | +/* osd1 HDR */ | |
| 638 | +#define OSD1_HDR2_CTRL 0x38a0 | |
| 639 | +#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN BIT(13) | |
| 640 | +#define OSD1_HDR2_CTRL_REG_ONLY_MAT BIT(16) | |
| 641 | + | |
| 637 | 642 | /* osd2 scaler */ |
| 638 | 643 | #define OSD2_VSC_PHASE_STEP 0x3d00 |
| 639 | 644 | #define OSD2_VSC_INI_PHASE 0x3d01 |
| @@ -425,9 +425,14 @@ void meson_viu_init(struct meson_drm *priv) · 424 unmodified lines | ||
| 425 | 425 | if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || |
| 426 | 426 | meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) |
| 427 | 427 | meson_viu_load_matrix(priv); |
| 428 | − else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) | |
| 428 | + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { | |
| 429 | 429 | meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff, |
| 430 | 430 | true); |
| 431 | + /* fix green/pink color distortion from vendor u-boot */ | |
| 432 | + writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT | | |
| 433 | + OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0, | |
| 434 | + priv->io_base + _REG(OSD1_HDR2_CTRL)); | |
| 435 | + } | |
| 431 | 436 | |
| 432 | 437 | /* Initialize OSD1 fifo control register */ |
| 433 | 438 | reg = VIU_OSD_DDR_PRIORITY_URGENT | |
| @@ -296,7 +296,7 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = { · 295 unmodified lines | ||
| 296 | 296 | static const struct dpu_mdp_cfg sm8250_mdp[] = { |
| 297 | 297 | { |
| 298 | 298 | .name = "top_0", .id = MDP_TOP, |
| 299 | − .base = 0x0, .len = 0x45C, | |
| 299 | + .base = 0x0, .len = 0x494, | |
| 300 | 300 | .features = 0, |
| 301 | 301 | .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ |
| 302 | 302 | .clk_ctrls[DPU_CLK_CTRL_VIG0] = { |
| @@ -771,6 +771,7 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) · 770 unmodified lines | ||
| 771 | 771 | dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, |
| 772 | 772 | dp_catalog->width_blanking); |
| 773 | 773 | dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active); |
| 774 | + dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0); | |
| 774 | 775 | return 0; |
| 775 | 776 | } |
| 776 | 777 | |
| @@ -1526,7 +1526,7 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) · 1525 unmodified lines | ||
| 1526 | 1526 | * running. Add the global reset just before disabling the |
| 1527 | 1527 | * link clocks and core clocks. |
| 1528 | 1528 | */ |
| 1529 | − ret = dp_ctrl_off(&ctrl->dp_ctrl); | |
| 1529 | + ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl); | |
| 1530 | 1530 | if (ret) { |
| 1531 | 1531 | DRM_ERROR("failed to disable DP controller\n"); |
| 1532 | 1532 | return ret; |
| @@ -219,6 +219,7 @@ static int dp_display_bind(struct device *dev, struct device *master, · 218 unmodified lines | ||
| 219 | 219 | goto end; |
| 220 | 220 | } |
| 221 | 221 | |
| 222 | + dp->aux->drm_dev = drm; | |
| 222 | 223 | rc = dp_aux_register(dp->aux); |
| 223 | 224 | if (rc) { |
| 224 | 225 | DRM_ERROR("DRM DP AUX register failed\n"); |
| @@ -1311,6 +1312,10 @@ static int dp_pm_resume(struct device *dev) · 1086 unmodified lines | ||
| 1311 | 1312 | else |
| 1312 | 1313 | dp->dp_display.is_connected = false; |
| 1313 | 1314 | |
| 1315 | + dp_display_handle_plugged_change(g_dp_display, | |
| 1316 | + dp->dp_display.is_connected); | |
| 1317 | + | |
| 1318 | + | |
| 1314 | 1319 | mutex_unlock(&dp->event_mutex); |
| 1315 | 1320 | |
| 1316 | 1321 | return 0; |
| @@ -1169,7 +1169,7 @@ static int msm_gem_new_impl(struct drm_device *dev, · 1168 unmodified lines | ||
| 1169 | 1169 | case MSM_BO_CACHED_COHERENT: |
| 1170 | 1170 | if (priv->has_cached_coherent) |
| 1171 | 1171 | break; |
| 1172 | − /* fallthrough */ | |
| 1172 | + fallthrough; | |
| 1173 | 1173 | default: |
| 1174 | 1174 | DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n", |
| 1175 | 1175 | (flags & MSM_BO_CACHE_MASK)); |
| @@ -142,6 +142,9 @@ static const struct iommu_flush_ops null_tlb_ops = { · 141 unmodified lines | ||
| 142 | 142 | .tlb_add_page = msm_iommu_tlb_add_page, |
| 143 | 143 | }; |
| 144 | 144 | |
| 145 | +static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, | |
| 146 | + unsigned long iova, int flags, void *arg); | |
| 147 | + | |
| 145 | 148 | struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) |
| 146 | 149 | { |
| 147 | 150 | struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); |
| @@ -157,6 +160,13 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) · 9 unmodified lines | ||
| 157 | 160 | if (!ttbr1_cfg) |
| 158 | 161 | return ERR_PTR(-ENODEV); |
| 159 | 162 | |
| 163 | + /* | |
| 164 | + * Defer setting the fault handler until we have a valid adreno_smmu | |
| 165 | + * to avoid accidentially installing a GPU specific fault handler for | |
| 166 | + * the display's iommu | |
| 167 | + */ | |
| 168 | + iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); | |
| 169 | + | |
| 160 | 170 | pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); |
| 161 | 171 | if (!pagetable) |
| 162 | 172 | return ERR_PTR(-ENOMEM); |
| @@ -300,7 +310,6 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) · 137 unmodified lines | ||
| 300 | 310 | |
| 301 | 311 | iommu->domain = domain; |
| 302 | 312 | msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); |
| 303 | − iommu_set_fault_handler(domain, msm_fault_handler, iommu); | |
| 304 | 313 | |
| 305 | 314 | atomic_set(&iommu->pagetables, 0); |
| 306 | 315 | |
| @@ -2237,6 +2237,33 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) · 2236 unmodified lines | ||
| 2237 | 2237 | interlock[NV50_DISP_INTERLOCK_CORE] = 0; |
| 2238 | 2238 | } |
| 2239 | 2239 | |
| 2240 | + /* Finish updating head(s)... | |
| 2241 | + * | |
| 2242 | + * NVD is rather picky about both where window assignments can change, | |
| 2243 | + * *and* about certain core and window channel states matching. | |
| 2244 | + * | |
| 2245 | + * The EFI GOP driver on newer GPUs configures window channels with a | |
| 2246 | + * different output format to what we do, and the core channel update | |
| 2247 | + * in the assign_windows case above would result in a state mismatch. | |
| 2248 | + * | |
| 2249 | + * Delay some of the head update until after that point to workaround | |
| 2250 | + * the issue. This only affects the initial modeset. | |
| 2251 | + * | |
| 2252 | + * TODO: handle this better when adding flexible window mapping | |
| 2253 | + */ | |
| 2254 | + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
| 2255 | + struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); | |
| 2256 | + struct nv50_head *head = nv50_head(crtc); | |
| 2257 | + | |
| 2258 | + NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, | |
| 2259 | + asyh->set.mask, asyh->clr.mask); | |
| 2260 | + | |
| 2261 | + if (asyh->set.mask) { | |
| 2262 | + nv50_head_flush_set_wndw(head, asyh); | |
| 2263 | + interlock[NV50_DISP_INTERLOCK_CORE] = 1; | |
| 2264 | + } | |
| 2265 | + } | |
| 2266 | + | |
| 2240 | 2267 | /* Update plane(s). */ |
| 2241 | 2268 | for_each_new_plane_in_state(state, plane, new_plane_state, i) { |
| 2242 | 2269 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); |
| @@ -50,11 +50,8 @@ nv50_head_flush_clr(struct nv50_head *head, · 49 unmodified lines | ||
| 50 | 50 | } |
| 51 | 51 | |
| 52 | 52 | void |
| 53 | −nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
| 53 | +nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh) | |
| 54 | 54 | { |
| 55 | − if (asyh->set.view ) head->func->view (head, asyh); | |
| 56 | − if (asyh->set.mode ) head->func->mode (head, asyh); | |
| 57 | − if (asyh->set.core ) head->func->core_set(head, asyh); | |
| 58 | 55 | if (asyh->set.olut ) { |
| 59 | 56 | asyh->olut.offset = nv50_lut_load(&head->olut, |
| 60 | 57 | asyh->olut.buffer, |
| @@ -62,6 +59,14 @@ nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) · 1 unmodified line | ||
| 62 | 59 | asyh->olut.load); |
| 63 | 60 | head->func->olut_set(head, asyh); |
| 64 | 61 | } |
| 62 | +} | |
| 63 | + | |
| 64 | +void | |
| 65 | +nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
| 66 | +{ | |
| 67 | + if (asyh->set.view ) head->func->view (head, asyh); | |
| 68 | + if (asyh->set.mode ) head->func->mode (head, asyh); | |
| 69 | + if (asyh->set.core ) head->func->core_set(head, asyh); | |
| 65 | 70 | if (asyh->set.curs ) head->func->curs_set(head, asyh); |
| 66 | 71 | if (asyh->set.base ) head->func->base (head, asyh); |
| 67 | 72 | if (asyh->set.ovly ) head->func->ovly (head, asyh); |
| @@ -21,6 +21,7 @@ struct nv50_head { · 20 unmodified lines | ||
| 21 | 21 | |
| 22 | 22 | struct nv50_head *nv50_head_create(struct drm_device *, int index); |
| 23 | 23 | void nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh); |
| 24 | +void nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh); | |
| 24 | 25 | void nv50_head_flush_clr(struct nv50_head *head, |
| 25 | 26 | struct nv50_head_atom *asyh, bool flush); |
| 26 | 27 | |
| @@ -4,7 +4,8 @@ · 3 unmodified lines | ||
| 4 | 4 | |
| 5 | 5 | struct nv_device_v0 { |
| 6 | 6 | __u8 version; |
| 7 | − __u8 pad01[7]; | |
| 7 | + __u8 priv; | |
| 8 | + __u8 pad02[6]; | |
| 8 | 9 | __u64 device; /* device identifier, ~0 for client default */ |
| 9 | 10 | }; |
| 10 | 11 | |
| @@ -61,8 +61,6 @@ · 60 unmodified lines | ||
| 61 | 61 | #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e |
| 62 | 62 | #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e |
| 63 | 63 | #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e |
| 64 | −#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e | |
| 65 | −#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e | |
| 66 | 64 | |
| 67 | 65 | #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f |
| 68 | 66 | #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f |
| @@ -9,7 +9,6 @@ struct nvif_client { · 8 unmodified lines | ||
| 9 | 9 | const struct nvif_driver *driver; |
| 10 | 10 | u64 version; |
| 11 | 11 | u8 route; |
| 12 | − bool super; | |
| 13 | 12 | }; |
| 14 | 13 | |
| 15 | 14 | int nvif_client_ctor(struct nvif_client *parent, const char *name, u64 device, |
| @@ -11,7 +11,7 @@ struct nvif_driver { · 10 unmodified lines | ||
| 11 | 11 | void (*fini)(void *priv); |
| 12 | 12 | int (*suspend)(void *priv); |
| 13 | 13 | int (*resume)(void *priv); |
| 14 | − int (*ioctl)(void *priv, bool super, void *data, u32 size, void **hack); | |
| 14 | + int (*ioctl)(void *priv, void *data, u32 size, void **hack); | |
| 15 | 15 | void __iomem *(*map)(void *priv, u64 handle, u32 size); |
| 16 | 16 | void (*unmap)(void *priv, void __iomem *ptr, u32 size); |
| 17 | 17 | bool keep; |
| @@ -13,7 +13,6 @@ struct nvkm_client { · 12 unmodified lines | ||
| 13 | 13 | struct nvkm_client_notify *notify[32]; |
| 14 | 14 | struct rb_root objroot; |
| 15 | 15 | |
| 16 | − bool super; | |
| 17 | 16 | void *data; |
| 18 | 17 | int (*ntfy)(const void *, u32, const void *, u32); |
| 19 | 18 | |
| @@ -4,5 +4,5 @@ · 3 unmodified lines | ||
| 4 | 4 | #include <core/os.h> |
| 5 | 5 | struct nvkm_client; |
| 6 | 6 | |
| 7 | −int nvkm_ioctl(struct nvkm_client *, bool, void *, u32, void **); | |
| 7 | +int nvkm_ioctl(struct nvkm_client *, void *, u32, void **); | |
| 8 | 8 | #endif |
| @@ -15,7 +15,6 @@ struct nvkm_vma { · 14 unmodified lines | ||
| 15 | 15 | u8 refd:3; /* Current page type (index, or NONE for unreferenced). */ |
| 16 | 16 | bool used:1; /* Region allocated. */ |
| 17 | 17 | bool part:1; /* Region was split from an allocated region by map(). */ |
| 18 | − bool user:1; /* Region user-allocated. */ | |
| 19 | 18 | bool busy:1; /* Region busy (for temporarily preventing user access). */ |
| 20 | 19 | bool mapped:1; /* Region contains valid pages. */ |
| 21 | 20 | struct nvkm_memory *memory; /* Memory currently mapped into VMA. */ |
| @@ -570,11 +570,9 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) · 569 unmodified lines | ||
| 570 | 570 | } |
| 571 | 571 | |
| 572 | 572 | client->route = NVDRM_OBJECT_ABI16; |
| 573 | − client->super = true; | |
| 574 | 573 | ret = nvif_object_ctor(&chan->chan->user, "abi16Ntfy", info->handle, |
| 575 | 574 | NV_DMA_IN_MEMORY, &args, sizeof(args), |
| 576 | 575 | &ntfy->object); |
| 577 | − client->super = false; | |
| 578 | 576 | client->route = NVDRM_OBJECT_NVIF; |
| 579 | 577 | if (ret) |
| 580 | 578 | goto done; |
| @@ -149,6 +149,8 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo) · 148 unmodified lines | ||
| 149 | 149 | */ |
| 150 | 150 | if (bo->base.dev) |
| 151 | 151 | drm_gem_object_release(&bo->base); |
| 152 | + else | |
| 153 | + dma_resv_fini(&bo->base._resv); | |
| 152 | 154 | |
| 153 | 155 | kfree(nvbo); |
| 154 | 156 | } |
| @@ -330,6 +332,10 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, · 175 unmodified lines | ||
| 330 | 332 | if (IS_ERR(nvbo)) |
| 331 | 333 | return PTR_ERR(nvbo); |
| 332 | 334 | |
| 335 | + nvbo->bo.base.size = size; | |
| 336 | + dma_resv_init(&nvbo->bo.base._resv); | |
| 337 | + drm_vma_node_reset(&nvbo->bo.base.vma_node); | |
| 338 | + | |
| 333 | 339 | ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj); |
| 334 | 340 | if (ret) |
| 335 | 341 | return ret; |
| @@ -86,12 +86,6 @@ nouveau_channel_del(struct nouveau_channel **pchan) · 85 unmodified lines | ||
| 86 | 86 | struct nouveau_channel *chan = *pchan; |
| 87 | 87 | if (chan) { |
| 88 | 88 | struct nouveau_cli *cli = (void *)chan->user.client; |
| 89 | − bool super; | |
| 90 | − | |
| 91 | − if (cli) { | |
| 92 | − super = cli->base.super; | |
| 93 | − cli->base.super = true; | |
| 94 | − } | |
| 95 | 89 | |
| 96 | 90 | if (chan->fence) |
| 97 | 91 | nouveau_fence(chan->drm)->context_del(chan); |
| @@ -111,9 +105,6 @@ nouveau_channel_del(struct nouveau_channel **pchan) · 13 unmodified lines | ||
| 111 | 105 | nouveau_bo_unpin(chan->push.buffer); |
| 112 | 106 | nouveau_bo_ref(NULL, &chan->push.buffer); |
| 113 | 107 | kfree(chan); |
| 114 | − | |
| 115 | − if (cli) | |
| 116 | − cli->base.super = super; | |
| 117 | 108 | } |
| 118 | 109 | *pchan = NULL; |
| 119 | 110 | } |
| @@ -512,20 +503,16 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, · 392 unmodified lines | ||
| 512 | 503 | struct nouveau_channel **pchan) |
| 513 | 504 | { |
| 514 | 505 | struct nouveau_cli *cli = (void *)device->object.client; |
| 515 | − bool super; | |
| 516 | 506 | int ret; |
| 517 | 507 | |
| 518 | 508 | /* hack until fencenv50 is fixed, and agp access relaxed */ |
| 519 | − super = cli->base.super; | |
| 520 | − cli->base.super = true; | |
| 521 | − | |
| 522 | 509 | ret = nouveau_channel_ind(drm, device, arg0, priv, pchan); |
| 523 | 510 | if (ret) { |
| 524 | 511 | NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); |
| 525 | 512 | ret = nouveau_channel_dma(drm, device, pchan); |
| 526 | 513 | if (ret) { |
| 527 | 514 | NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); |
| 528 | − goto done; | |
| 515 | + return ret; | |
| 529 | 516 | } |
| 530 | 517 | } |
| 531 | 518 | |
| @@ -533,15 +520,13 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, · 1 unmodified line | ||
| 533 | 520 | if (ret) { |
| 534 | 521 | NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); |
| 535 | 522 | nouveau_channel_del(pchan); |
| 536 | − goto done; | |
| 523 | + return ret; | |
| 537 | 524 | } |
| 538 | 525 | |
| 539 | 526 | ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst); |
| 540 | 527 | if (ret) |
| 541 | 528 | nouveau_channel_del(pchan); |
| 542 | 529 | |
| 543 | −done: | |
| 544 | − cli->base.super = super; | |
| 545 | 530 | return ret; |
| 546 | 531 | } |
| 547 | 532 | |
| @@ -244,6 +244,7 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname, · 243 unmodified lines | ||
| 244 | 244 | ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE, |
| 245 | 245 | &(struct nv_device_v0) { |
| 246 | 246 | .device = ~0, |
| 247 | + .priv = true, | |
| 247 | 248 | }, sizeof(struct nv_device_v0), |
| 248 | 249 | &cli->device); |
| 249 | 250 | if (ret) { |
| @@ -1086,8 +1087,6 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) · 836 unmodified lines | ||
| 1086 | 1087 | if (ret) |
| 1087 | 1088 | goto done; |
| 1088 | 1089 | |
| 1089 | − cli->base.super = false; | |
| 1090 | − | |
| 1091 | 1090 | fpriv->driver_priv = cli; |
| 1092 | 1091 | |
| 1093 | 1092 | mutex_lock(&drm->client.mutex); |
| @@ -41,8 +41,6 @@ nouveau_mem_map(struct nouveau_mem *mem, · 40 unmodified lines | ||
| 41 | 41 | struct gf100_vmm_map_v0 gf100; |
| 42 | 42 | } args; |
| 43 | 43 | u32 argc = 0; |
| 44 | − bool super; | |
| 45 | − int ret; | |
| 46 | 44 | |
| 47 | 45 | switch (vmm->object.oclass) { |
| 48 | 46 | case NVIF_CLASS_VMM_NV04: |
| @@ -73,12 +71,7 @@ nouveau_mem_map(struct nouveau_mem *mem, · 24 unmodified lines | ||
| 73 | 71 | return -ENOSYS; |
| 74 | 72 | } |
| 75 | 73 | |
| 76 | − super = vmm->object.client->super; | |
| 77 | − vmm->object.client->super = true; | |
| 78 | − ret = nvif_vmm_map(vmm, vma->addr, mem->mem.size, &args, argc, | |
| 79 | − &mem->mem, 0); | |
| 80 | − vmm->object.client->super = super; | |
| 81 | − return ret; | |
| 74 | + return nvif_vmm_map(vmm, vma->addr, mem->mem.size, &args, argc, &mem->mem, 0); | |
| 82 | 75 | } |
| 83 | 76 | |
| 84 | 77 | void |
| @@ -99,7 +92,6 @@ nouveau_mem_host(struct ttm_resource *reg, struct ttm_tt *tt) · 14 unmodified lines | ||
| 99 | 92 | struct nouveau_drm *drm = cli->drm; |
| 100 | 93 | struct nvif_mmu *mmu = &cli->mmu; |
| 101 | 94 | struct nvif_mem_ram_v0 args = {}; |
| 102 | − bool super = cli->base.super; | |
| 103 | 95 | u8 type; |
| 104 | 96 | int ret; |
| 105 | 97 | |
| @@ -122,11 +114,9 @@ nouveau_mem_host(struct ttm_resource *reg, struct ttm_tt *tt) · 16 unmodified lines | ||
| 122 | 114 | args.dma = tt->dma_address; |
| 123 | 115 | |
| 124 | 116 | mutex_lock(&drm->master.lock); |
| 125 | − cli->base.super = true; | |
| 126 | 117 | ret = nvif_mem_ctor_type(mmu, "ttmHostMem", cli->mem->oclass, type, PAGE_SHIFT, |
| 127 | 118 | reg->num_pages << PAGE_SHIFT, |
| 128 | 119 | &args, sizeof(args), &mem->mem); |
| 129 | − cli->base.super = super; | |
| 130 | 120 | mutex_unlock(&drm->master.lock); |
| 131 | 121 | return ret; |
| 132 | 122 | } |
| @@ -138,12 +128,10 @@ nouveau_mem_vram(struct ttm_resource *reg, bool contig, u8 page) · 5 unmodified lines | ||
| 138 | 128 | struct nouveau_cli *cli = mem->cli; |
| 139 | 129 | struct nouveau_drm *drm = cli->drm; |
| 140 | 130 | struct nvif_mmu *mmu = &cli->mmu; |
| 141 | − bool super = cli->base.super; | |
| 142 | 131 | u64 size = ALIGN(reg->num_pages << PAGE_SHIFT, 1 << page); |
| 143 | 132 | int ret; |
| 144 | 133 | |
| 145 | 134 | mutex_lock(&drm->master.lock); |
| 146 | − cli->base.super = true; | |
| 147 | 135 | switch (cli->mem->oclass) { |
| 148 | 136 | case NVIF_CLASS_MEM_GF100: |
| 149 | 137 | ret = nvif_mem_ctor_type(mmu, "ttmVram", cli->mem->oclass, |
| @@ -167,7 +155,6 @@ nouveau_mem_vram(struct ttm_resource *reg, bool contig, u8 page) · 17 unmodified lines | ||
| 167 | 155 | WARN_ON(1); |
| 168 | 156 | break; |
| 169 | 157 | } |
| 170 | − cli->base.super = super; | |
| 171 | 158 | mutex_unlock(&drm->master.lock); |
| 172 | 159 | |
| 173 | 160 | reg->start = mem->mem.addr >> PAGE_SHIFT; |
| @@ -52,9 +52,9 @@ nvkm_client_map(void *priv, u64 handle, u32 size) · 51 unmodified lines | ||
| 52 | 52 | } |
| 53 | 53 | |
| 54 | 54 | static int |
| 55 | −nvkm_client_ioctl(void *priv, bool super, void *data, u32 size, void **hack) | |
| 55 | +nvkm_client_ioctl(void *priv, void *data, u32 size, void **hack) | |
| 56 | 56 | { |
| 57 | − return nvkm_ioctl(priv, super, data, size, hack); | |
| 57 | + return nvkm_ioctl(priv, data, size, hack); | |
| 58 | 58 | } |
| 59 | 59 | |
| 60 | 60 | static int |
| @@ -237,14 +237,11 @@ void · 236 unmodified lines | ||
| 237 | 237 | nouveau_svmm_invalidate(struct nouveau_svmm *svmm, u64 start, u64 limit) |
| 238 | 238 | { |
| 239 | 239 | if (limit > start) { |
| 240 | − bool super = svmm->vmm->vmm.object.client->super; | |
| 241 | − svmm->vmm->vmm.object.client->super = true; | |
| 242 | 240 | nvif_object_mthd(&svmm->vmm->vmm.object, NVIF_VMM_V0_PFNCLR, |
| 243 | 241 | &(struct nvif_vmm_pfnclr_v0) { |
| 244 | 242 | .addr = start, |
| 245 | 243 | .size = limit - start, |
| 246 | 244 | }, sizeof(struct nvif_vmm_pfnclr_v0)); |
| 247 | − svmm->vmm->vmm.object.client->super = super; | |
| 248 | 245 | } |
| 249 | 246 | } |
| 250 | 247 | |
| @@ -634,9 +631,7 @@ static int nouveau_atomic_range_fault(struct nouveau_svmm *svmm, · 383 unmodified lines | ||
| 634 | 631 | NVIF_VMM_PFNMAP_V0_A | |
| 635 | 632 | NVIF_VMM_PFNMAP_V0_HOST; |
| 636 | 633 | |
| 637 | − svmm->vmm->vmm.object.client->super = true; | |
| 638 | 634 | ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, size, NULL); |
| 639 | − svmm->vmm->vmm.object.client->super = false; | |
| 640 | 635 | mutex_unlock(&svmm->mutex); |
| 641 | 636 | |
| 642 | 637 | unlock_page(page); |
| @@ -702,9 +697,7 @@ static int nouveau_range_fault(struct nouveau_svmm *svmm, · 59 unmodified lines | ||
| 702 | 697 | |
| 703 | 698 | nouveau_hmm_convert_pfn(drm, &range, args); |
| 704 | 699 | |
| 705 | − svmm->vmm->vmm.object.client->super = true; | |
| 706 | 700 | ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, size, NULL); |
| 707 | − svmm->vmm->vmm.object.client->super = false; | |
| 708 | 701 | mutex_unlock(&svmm->mutex); |
| 709 | 702 | |
| 710 | 703 | out: |
| @@ -928,10 +921,8 @@ nouveau_pfns_map(struct nouveau_svmm *svmm, struct mm_struct *mm, · 217 unmodified lines | ||
| 928 | 921 | |
| 929 | 922 | mutex_lock(&svmm->mutex); |
| 930 | 923 | |
| 931 | − svmm->vmm->vmm.object.client->super = true; | |
| 932 | 924 | ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, sizeof(*args) + |
| 933 | 925 | npages * sizeof(args->p.phys[0]), NULL); |
| 934 | − svmm->vmm->vmm.object.client->super = false; | |
| 935 | 926 | |
| 936 | 927 | mutex_unlock(&svmm->mutex); |
| 937 | 928 | } |
| @@ -32,6 +32,9 @@ · 31 unmodified lines | ||
| 32 | 32 | #include <nvif/event.h> |
| 33 | 33 | #include <nvif/ioctl.h> |
| 34 | 34 | |
| 35 | +#include <nvif/class.h> | |
| 36 | +#include <nvif/cl0080.h> | |
| 37 | + | |
| 35 | 38 | struct usif_notify_p { |
| 36 | 39 | struct drm_pending_event base; |
| 37 | 40 | struct { |
| @@ -261,7 +264,7 @@ usif_object_dtor(struct usif_object *object) · 223 unmodified lines | ||
| 261 | 264 | } |
| 262 | 265 | |
| 263 | 266 | static int |
| 264 | −usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) | |
| 267 | +usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc, bool parent_abi16) | |
| 265 | 268 | { |
| 266 | 269 | struct nouveau_cli *cli = nouveau_cli(f); |
| 267 | 270 | struct nvif_client *client = &cli->base; |
| @@ -271,23 +274,48 @@ usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) · 3 unmodified lines | ||
| 271 | 274 | struct usif_object *object; |
| 272 | 275 | int ret = -ENOSYS; |
| 273 | 276 | |
| 277 | + if ((ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) | |
| 278 | + return ret; | |
| 279 | + | |
| 280 | + switch (args->v0.oclass) { | |
| 281 | + case NV_DMA_FROM_MEMORY: | |
| 282 | + case NV_DMA_TO_MEMORY: | |
| 283 | + case NV_DMA_IN_MEMORY: | |
| 284 | + return -EINVAL; | |
| 285 | + case NV_DEVICE: { | |
| 286 | + union { | |
| 287 | + struct nv_device_v0 v0; | |
| 288 | + } *args = data; | |
| 289 | + | |
| 290 | + if ((ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) | |
| 291 | + return ret; | |
| 292 | + | |
| 293 | + args->v0.priv = false; | |
| 294 | + break; | |
| 295 | + } | |
| 296 | + default: | |
| 297 | + if (!parent_abi16) | |
| 298 | + return -EINVAL; | |
| 299 | + break; | |
| 300 | + } | |
| 301 | + | |
| 274 | 302 | if (!(object = kmalloc(sizeof(*object), GFP_KERNEL))) |
| 275 | 303 | return -ENOMEM; |
| 276 | 304 | list_add(&object->head, &cli->objects); |
| 277 | 305 | |
| 278 | − if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { | |
| 279 | − object->route = args->v0.route; | |
| 280 | − object->token = args->v0.token; | |
| 281 | − args->v0.route = NVDRM_OBJECT_USIF; | |
| 282 | − args->v0.token = (unsigned long)(void *)object; | |
| 283 | − ret = nvif_client_ioctl(client, argv, argc); | |
| 284 | − args->v0.token = object->token; | |
| 285 | − args->v0.route = object->route; | |
| 306 | + object->route = args->v0.route; | |
| 307 | + object->token = args->v0.token; | |
| 308 | + args->v0.route = NVDRM_OBJECT_USIF; | |
| 309 | + args->v0.token = (unsigned long)(void *)object; | |
| 310 | + ret = nvif_client_ioctl(client, argv, argc); | |
| 311 | + if (ret) { | |
| 312 | + usif_object_dtor(object); | |
| 313 | + return ret; | |
| 286 | 314 | } |
| 287 | 315 | |
| 288 | − if (ret) | |
| 289 | − usif_object_dtor(object); | |
| 290 | − return ret; | |
| 316 | + args->v0.token = object->token; | |
| 317 | + args->v0.route = object->route; | |
| 318 | + return 0; | |
| 291 | 319 | } |
| 292 | 320 | |
| 293 | 321 | int |
| @@ -301,6 +329,7 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc) · 7 unmodified lines | ||
| 301 | 329 | struct nvif_ioctl_v0 v0; |
| 302 | 330 | } *argv = data; |
| 303 | 331 | struct usif_object *object; |
| 332 | + bool abi16 = false; | |
| 304 | 333 | u8 owner; |
| 305 | 334 | int ret; |
| 306 | 335 | |
| @@ -331,11 +360,13 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc) · 24 unmodified lines | ||
| 331 | 360 | mutex_unlock(&cli->mutex); |
| 332 | 361 | goto done; |
| 333 | 362 | } |
| 363 | + | |
| 364 | + abi16 = true; | |
| 334 | 365 | } |
| 335 | 366 | |
| 336 | 367 | switch (argv->v0.type) { |
| 337 | 368 | case NVIF_IOCTL_V0_NEW: |
| 338 | − ret = usif_object_new(filp, data, size, argv, argc); | |
| 369 | + ret = usif_object_new(filp, data, size, argv, argc, abi16); | |
| 339 | 370 | break; |
| 340 | 371 | case NVIF_IOCTL_V0_NTFY_NEW: |
| 341 | 372 | ret = usif_notify_new(filp, data, size, argv, argc); |
| @@ -32,7 +32,7 @@ · 31 unmodified lines | ||
| 32 | 32 | int |
| 33 | 33 | nvif_client_ioctl(struct nvif_client *client, void *data, u32 size) |
| 34 | 34 | { |
| 35 | − return client->driver->ioctl(client->object.priv, client->super, data, size, NULL); | |
| 35 | + return client->driver->ioctl(client->object.priv, data, size, NULL); | |
| 36 | 36 | } |
| 37 | 37 | |
| 38 | 38 | int |
| @@ -80,7 +80,6 @@ nvif_client_ctor(struct nvif_client *parent, const char *name, u64 device, · 41 unmodified lines | ||
| 80 | 80 | client->object.client = client; |
| 81 | 81 | client->object.handle = ~0; |
| 82 | 82 | client->route = NVIF_IOCTL_V0_ROUTE_NVIF; |
| 83 | − client->super = true; | |
| 84 | 83 | client->driver = parent->driver; |
| 85 | 84 | |
| 86 | 85 | if (ret == 0) { |
| @@ -44,8 +44,7 @@ nvif_object_ioctl(struct nvif_object *object, void *data, u32 size, void **hack) · 43 unmodified lines | ||
| 44 | 44 | } else |
| 45 | 45 | return -ENOSYS; |
| 46 | 46 | |
| 47 | − return client->driver->ioctl(client->object.priv, client->super, | |
| 48 | − data, size, hack); | |
| 47 | + return client->driver->ioctl(client->object.priv, data, size, hack); | |
| 49 | 48 | } |
| 50 | 49 | |
| 51 | 50 | void |
| @@ -426,8 +426,7 @@ nvkm_ioctl_path(struct nvkm_client *client, u64 handle, u32 type, · 425 unmodified lines | ||
| 426 | 426 | } |
| 427 | 427 | |
| 428 | 428 | int |
| 429 | −nvkm_ioctl(struct nvkm_client *client, bool supervisor, | |
| 430 | − void *data, u32 size, void **hack) | |
| 429 | +nvkm_ioctl(struct nvkm_client *client, void *data, u32 size, void **hack) | |
| 431 | 430 | { |
| 432 | 431 | struct nvkm_object *object = &client->object; |
| 433 | 432 | union { |
| @@ -435,7 +434,6 @@ nvkm_ioctl(struct nvkm_client *client, bool supervisor, · 1 unmodified line | ||
| 435 | 434 | } *args = data; |
| 436 | 435 | int ret = -ENOSYS; |
| 437 | 436 | |
| 438 | − client->super = supervisor; | |
| 439 | 437 | nvif_ioctl(object, "size %d\n", size); |
| 440 | 438 | |
| 441 | 439 | if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { |
| @@ -2624,6 +2624,26 @@ nv174_chipset = { · 2623 unmodified lines | ||
| 2624 | 2624 | .dma = { 0x00000001, gv100_dma_new }, |
| 2625 | 2625 | }; |
| 2626 | 2626 | |
| 2627 | +static const struct nvkm_device_chip | |
| 2628 | +nv177_chipset = { | |
| 2629 | + .name = "GA107", | |
| 2630 | + .bar = { 0x00000001, tu102_bar_new }, | |
| 2631 | + .bios = { 0x00000001, nvkm_bios_new }, | |
| 2632 | + .devinit = { 0x00000001, ga100_devinit_new }, | |
| 2633 | + .fb = { 0x00000001, ga102_fb_new }, | |
| 2634 | + .gpio = { 0x00000001, ga102_gpio_new }, | |
| 2635 | + .i2c = { 0x00000001, gm200_i2c_new }, | |
| 2636 | + .imem = { 0x00000001, nv50_instmem_new }, | |
| 2637 | + .mc = { 0x00000001, ga100_mc_new }, | |
| 2638 | + .mmu = { 0x00000001, tu102_mmu_new }, | |
| 2639 | + .pci = { 0x00000001, gp100_pci_new }, | |
| 2640 | + .privring = { 0x00000001, gm200_privring_new }, | |
| 2641 | + .timer = { 0x00000001, gk20a_timer_new }, | |
| 2642 | + .top = { 0x00000001, ga100_top_new }, | |
| 2643 | + .disp = { 0x00000001, ga102_disp_new }, | |
| 2644 | + .dma = { 0x00000001, gv100_dma_new }, | |
| 2645 | +}; | |
| 2646 | + | |
| 2627 | 2647 | static int |
| 2628 | 2648 | nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, |
| 2629 | 2649 | struct nvkm_notify *notify) |
| @@ -3049,6 +3069,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, · 419 unmodified lines | ||
| 3049 | 3069 | case 0x168: device->chip = &nv168_chipset; break; |
| 3050 | 3070 | case 0x172: device->chip = &nv172_chipset; break; |
| 3051 | 3071 | case 0x174: device->chip = &nv174_chipset; break; |
| 3072 | + case 0x177: device->chip = &nv177_chipset; break; | |
| 3052 | 3073 | default: |
| 3053 | 3074 | if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) { |
| 3054 | 3075 | switch (device->chipset) { |
| @@ -397,7 +397,7 @@ nvkm_udevice_new(const struct nvkm_oclass *oclass, void *data, u32 size, · 396 unmodified lines | ||
| 397 | 397 | return ret; |
| 398 | 398 | |
| 399 | 399 | /* give priviledged clients register access */ |
| 400 | − if (client->super) | |
| 400 | + if (args->v0.priv) | |
| 401 | 401 | func = &nvkm_udevice_super; |
| 402 | 402 | else |
| 403 | 403 | func = &nvkm_udevice; |
| @@ -440,7 +440,7 @@ nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps) · 439 unmodified lines | ||
| 440 | 440 | return ret; |
| 441 | 441 | } |
| 442 | 442 | |
| 443 | −static void | |
| 443 | +void | |
| 444 | 444 | nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior) |
| 445 | 445 | { |
| 446 | 446 | struct nvkm_dp *dp = nvkm_dp(outp); |
| @@ -32,6 +32,7 @@ struct nvkm_dp { · 31 unmodified lines | ||
| 32 | 32 | |
| 33 | 33 | int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, |
| 34 | 34 | struct nvkm_outp **); |
| 35 | +void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); | |
| 35 | 36 | |
| 36 | 37 | /* DPCD Receiver Capabilities */ |
| 37 | 38 | #define DPCD_RC00_DPCD_REV 0x00000 |
| @@ -22,6 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | * Authors: Ben Skeggs |
| 23 | 23 | */ |
| 24 | 24 | #include "outp.h" |
| 25 | +#include "dp.h" | |
| 25 | 26 | #include "ior.h" |
| 26 | 27 | |
| 27 | 28 | #include <subdev/bios.h> |
| @@ -257,6 +258,14 @@ nvkm_outp_init_route(struct nvkm_outp *outp) · 229 unmodified lines | ||
| 257 | 258 | if (!ior->arm.head || ior->arm.proto != proto) { |
| 258 | 259 | OUTP_DBG(outp, "no heads (%x %d %d)", ior->arm.head, |
| 259 | 260 | ior->arm.proto, proto); |
| 261 | + | |
| 262 | + /* The EFI GOP driver on Ampere can leave unused DP links routed, | |
| 263 | + * which we don't expect. The DisableLT IED script *should* get | |
| 264 | + * us back to where we need to be. | |
| 265 | + */ | |
| 266 | + if (ior->func->route.get && !ior->arm.head && outp->info.type == DCB_OUTPUT_DP) | |
| 267 | + nvkm_dp_disable(outp, ior); | |
| 268 | + | |
| 260 | 269 | return; |
| 261 | 270 | } |
| 262 | 271 | |
| @@ -26,7 +26,6 @@ · 25 unmodified lines | ||
| 26 | 26 | #include <core/client.h> |
| 27 | 27 | #include <core/gpuobj.h> |
| 28 | 28 | #include <subdev/fb.h> |
| 29 | −#include <subdev/instmem.h> | |
| 30 | 29 | |
| 31 | 30 | #include <nvif/cl0002.h> |
| 32 | 31 | #include <nvif/unpack.h> |
| @@ -72,11 +71,7 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, · 39 unmodified lines | ||
| 72 | 71 | union { |
| 73 | 72 | struct nv_dma_v0 v0; |
| 74 | 73 | } *args = *pdata; |
| 75 | − struct nvkm_device *device = dma->engine.subdev.device; | |
| 76 | − struct nvkm_client *client = oclass->client; | |
| 77 | 74 | struct nvkm_object *parent = oclass->parent; |
| 78 | − struct nvkm_instmem *instmem = device->imem; | |
| 79 | − struct nvkm_fb *fb = device->fb; | |
| 80 | 75 | void *data = *pdata; |
| 81 | 76 | u32 size = *psize; |
| 82 | 77 | int ret = -ENOSYS; |
| @@ -109,23 +104,13 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, · 26 unmodified lines | ||
| 109 | 104 | dmaobj->target = NV_MEM_TARGET_VM; |
| 110 | 105 | break; |
| 111 | 106 | case NV_DMA_V0_TARGET_VRAM: |
| 112 | − if (!client->super) { | |
| 113 | − if (dmaobj->limit >= fb->ram->size - instmem->reserved) | |
| 114 | − return -EACCES; | |
| 115 | − if (device->card_type >= NV_50) | |
| 116 | − return -EACCES; | |
| 117 | − } | |
| 118 | 107 | dmaobj->target = NV_MEM_TARGET_VRAM; |
| 119 | 108 | break; |
| 120 | 109 | case NV_DMA_V0_TARGET_PCI: |
| 121 | − if (!client->super) | |
| 122 | − return -EACCES; | |
| 123 | 110 | dmaobj->target = NV_MEM_TARGET_PCI; |
| 124 | 111 | break; |
| 125 | 112 | case NV_DMA_V0_TARGET_PCI_US: |
| 126 | 113 | case NV_DMA_V0_TARGET_AGP: |
| 127 | − if (!client->super) | |
| 128 | − return -EACCES; | |
| 129 | 114 | dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP; |
| 130 | 115 | break; |
| 131 | 116 | default: |
| @@ -27,8 +27,6 @@ nvkm-y += nvkm/engine/fifo/dmanv04.o · 26 unmodified lines | ||
| 27 | 27 | nvkm-y += nvkm/engine/fifo/dmanv10.o |
| 28 | 28 | nvkm-y += nvkm/engine/fifo/dmanv17.o |
| 29 | 29 | nvkm-y += nvkm/engine/fifo/dmanv40.o |
| 30 | −nvkm-y += nvkm/engine/fifo/dmanv50.o | |
| 31 | −nvkm-y += nvkm/engine/fifo/dmag84.o | |
| 32 | 30 | |
| 33 | 31 | nvkm-y += nvkm/engine/fifo/gpfifonv50.o |
| 34 | 32 | nvkm-y += nvkm/engine/fifo/gpfifog84.o |
| @@ -48,8 +48,6 @@ void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); · 47 unmodified lines | ||
| 48 | 48 | int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push, |
| 49 | 49 | const struct nvkm_oclass *, struct nv50_fifo_chan *); |
| 50 | 50 | |
| 51 | −extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass; | |
| 52 | 51 | extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass; |
| 53 | −extern const struct nvkm_fifo_chan_oclass g84_fifo_dma_oclass; | |
| 54 | 52 | extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass; |
| 55 | 53 | #endif |
| @@ -1,94 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright 2012 Red Hat Inc. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − * | |
| 22 | − * Authors: Ben Skeggs | |
| 23 | − */ | |
| 24 | −#include "channv50.h" | |
| 25 | − | |
| 26 | −#include <core/client.h> | |
| 27 | −#include <core/ramht.h> | |
| 28 | − | |
| 29 | −#include <nvif/class.h> | |
| 30 | −#include <nvif/cl826e.h> | |
| 31 | −#include <nvif/unpack.h> | |
| 32 | − | |
| 33 | −static int | |
| 34 | −g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, | |
| 35 | − void *data, u32 size, struct nvkm_object **pobject) | |
| 36 | −{ | |
| 37 | − struct nvkm_object *parent = oclass->parent; | |
| 38 | − union { | |
| 39 | − struct g82_channel_dma_v0 v0; | |
| 40 | − } *args = data; | |
| 41 | − struct nv50_fifo *fifo = nv50_fifo(base); | |
| 42 | − struct nv50_fifo_chan *chan; | |
| 43 | − int ret = -ENOSYS; | |
| 44 | − | |
| 45 | − nvif_ioctl(parent, "create channel dma size %d\n", size); | |
| 46 | − if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { | |
| 47 | − nvif_ioctl(parent, "create channel dma vers %d vmm %llx " | |
| 48 | − "pushbuf %llx offset %016llx\n", | |
| 49 | − args->v0.version, args->v0.vmm, args->v0.pushbuf, | |
| 50 | − args->v0.offset); | |
| 51 | − if (!args->v0.pushbuf) | |
| 52 | − return -EINVAL; | |
| 53 | − } else | |
| 54 | − return ret; | |
| 55 | − | |
| 56 | − if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) | |
| 57 | − return -ENOMEM; | |
| 58 | − *pobject = &chan->base.object; | |
| 59 | − | |
| 60 | − ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf, | |
| 61 | − oclass, chan); | |
| 62 | − if (ret) | |
| 63 | − return ret; | |
| 64 | − | |
| 65 | − args->v0.chid = chan->base.chid; | |
| 66 | − | |
| 67 | − nvkm_kmap(chan->ramfc); | |
| 68 | − nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); | |
| 69 | − nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); | |
| 70 | − nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); | |
| 71 | − nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); | |
| 72 | − nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); | |
| 73 | − nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); | |
| 74 | − nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); | |
| 75 | − nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); | |
| 76 | − nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); | |
| 77 | − nvkm_wo32(chan->ramfc, 0x78, 0x00000000); | |
| 78 | − nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); | |
| 79 | − nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | | |
| 80 | − (4 << 24) /* SEARCH_FULL */ | | |
| 81 | − (chan->ramht->gpuobj->node->offset >> 4)); | |
| 82 | − nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); | |
| 83 | − nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); | |
| 84 | − nvkm_done(chan->ramfc); | |
| 85 | − return 0; | |
| 86 | −} | |
| 87 | − | |
| 88 | −const struct nvkm_fifo_chan_oclass | |
| 89 | −g84_fifo_dma_oclass = { | |
| 90 | − .base.oclass = G82_CHANNEL_DMA, | |
| 91 | − .base.minver = 0, | |
| 92 | − .base.maxver = 0, | |
| 93 | − .ctor = g84_fifo_dma_new, | |
| 94 | −}; | |
| @@ -1,92 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright 2012 Red Hat Inc. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − * | |
| 22 | − * Authors: Ben Skeggs | |
| 23 | − */ | |
| 24 | −#include "channv50.h" | |
| 25 | − | |
| 26 | −#include <core/client.h> | |
| 27 | −#include <core/ramht.h> | |
| 28 | − | |
| 29 | −#include <nvif/class.h> | |
| 30 | −#include <nvif/cl506e.h> | |
| 31 | −#include <nvif/unpack.h> | |
| 32 | − | |
| 33 | −static int | |
| 34 | −nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, | |
| 35 | − void *data, u32 size, struct nvkm_object **pobject) | |
| 36 | −{ | |
| 37 | − struct nvkm_object *parent = oclass->parent; | |
| 38 | − union { | |
| 39 | − struct nv50_channel_dma_v0 v0; | |
| 40 | − } *args = data; | |
| 41 | − struct nv50_fifo *fifo = nv50_fifo(base); | |
| 42 | − struct nv50_fifo_chan *chan; | |
| 43 | − int ret = -ENOSYS; | |
| 44 | − | |
| 45 | − nvif_ioctl(parent, "create channel dma size %d\n", size); | |
| 46 | − if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { | |
| 47 | − nvif_ioctl(parent, "create channel dma vers %d vmm %llx " | |
| 48 | − "pushbuf %llx offset %016llx\n", | |
| 49 | − args->v0.version, args->v0.vmm, args->v0.pushbuf, | |
| 50 | − args->v0.offset); | |
| 51 | − if (!args->v0.pushbuf) | |
| 52 | − return -EINVAL; | |
| 53 | − } else | |
| 54 | − return ret; | |
| 55 | − | |
| 56 | − if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) | |
| 57 | − return -ENOMEM; | |
| 58 | − *pobject = &chan->base.object; | |
| 59 | − | |
| 60 | − ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf, | |
| 61 | − oclass, chan); | |
| 62 | − if (ret) | |
| 63 | − return ret; | |
| 64 | − | |
| 65 | − args->v0.chid = chan->base.chid; | |
| 66 | − | |
| 67 | − nvkm_kmap(chan->ramfc); | |
| 68 | − nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); | |
| 69 | − nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); | |
| 70 | − nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); | |
| 71 | − nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); | |
| 72 | − nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); | |
| 73 | − nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); | |
| 74 | − nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); | |
| 75 | − nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); | |
| 76 | − nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); | |
| 77 | − nvkm_wo32(chan->ramfc, 0x78, 0x00000000); | |
| 78 | − nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); | |
| 79 | − nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | | |
| 80 | − (4 << 24) /* SEARCH_FULL */ | | |
| 81 | − (chan->ramht->gpuobj->node->offset >> 4)); | |
| 82 | − nvkm_done(chan->ramfc); | |
| 83 | − return 0; | |
| 84 | −} | |
| 85 | − | |
| 86 | −const struct nvkm_fifo_chan_oclass | |
| 87 | −nv50_fifo_dma_oclass = { | |
| 88 | − .base.oclass = NV50_CHANNEL_DMA, | |
| 89 | − .base.minver = 0, | |
| 90 | − .base.maxver = 0, | |
| 91 | − .ctor = nv50_fifo_dma_new, | |
| 92 | −}; | |
| @@ -119,7 +119,6 @@ g84_fifo = { · 118 unmodified lines | ||
| 119 | 119 | .uevent_init = g84_fifo_uevent_init, |
| 120 | 120 | .uevent_fini = g84_fifo_uevent_fini, |
| 121 | 121 | .chan = { |
| 122 | − &g84_fifo_dma_oclass, | |
| 123 | 122 | &g84_fifo_gpfifo_oclass, |
| 124 | 123 | NULL |
| 125 | 124 | }, |
| @@ -341,8 +341,6 @@ gk104_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, · 340 unmodified lines | ||
| 341 | 341 | "runlist %016llx priv %d\n", |
| 342 | 342 | args->v0.version, args->v0.vmm, args->v0.ioffset, |
| 343 | 343 | args->v0.ilength, args->v0.runlist, args->v0.priv); |
| 344 | − if (args->v0.priv && !oclass->client->super) | |
| 345 | − return -EINVAL; | |
| 346 | 344 | return gk104_fifo_gpfifo_new_(fifo, |
| 347 | 345 | &args->v0.runlist, |
| 348 | 346 | &args->v0.chid, |
| @@ -226,8 +226,6 @@ gv100_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, · 225 unmodified lines | ||
| 226 | 226 | "runlist %016llx priv %d\n", |
| 227 | 227 | args->v0.version, args->v0.vmm, args->v0.ioffset, |
| 228 | 228 | args->v0.ilength, args->v0.runlist, args->v0.priv); |
| 229 | − if (args->v0.priv && !oclass->client->super) | |
| 230 | − return -EINVAL; | |
| 231 | 229 | return gv100_fifo_gpfifo_new_(&gv100_fifo_gpfifo, fifo, |
| 232 | 230 | &args->v0.runlist, |
| 233 | 231 | &args->v0.chid, |
| @@ -65,8 +65,6 @@ tu102_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, · 64 unmodified lines | ||
| 65 | 65 | "runlist %016llx priv %d\n", |
| 66 | 66 | args->v0.version, args->v0.vmm, args->v0.ioffset, |
| 67 | 67 | args->v0.ilength, args->v0.runlist, args->v0.priv); |
| 68 | − if (args->v0.priv && !oclass->client->super) | |
| 69 | − return -EINVAL; | |
| 70 | 68 | return gv100_fifo_gpfifo_new_(&tu102_fifo_gpfifo, fifo, |
| 71 | 69 | &args->v0.runlist, |
| 72 | 70 | &args->v0.chid, |
| @@ -136,7 +136,6 @@ nv50_fifo = { · 135 unmodified lines | ||
| 136 | 136 | .pause = nv04_fifo_pause, |
| 137 | 137 | .start = nv04_fifo_start, |
| 138 | 138 | .chan = { |
| 139 | − &nv50_fifo_dma_oclass, | |
| 140 | 139 | &nv50_fifo_gpfifo_oclass, |
| 141 | 140 | NULL |
| 142 | 141 | }, |
| @@ -41,7 +41,7 @@ nvkm_umem_search(struct nvkm_client *client, u64 handle) · 40 unmodified lines | ||
| 41 | 41 | |
| 42 | 42 | object = nvkm_object_search(client, handle, &nvkm_umem); |
| 43 | 43 | if (IS_ERR(object)) { |
| 44 | − if (client->super && client != master) { | |
| 44 | + if (client != master) { | |
| 45 | 45 | spin_lock(&master->lock); |
| 46 | 46 | list_for_each_entry(umem, &master->umem, head) { |
| 47 | 47 | if (umem->object.object == handle) { |
| @@ -53,8 +53,7 @@ nvkm_umem_search(struct nvkm_client *client, u64 handle) · 5 unmodified lines | ||
| 53 | 53 | } |
| 54 | 54 | } else { |
| 55 | 55 | umem = nvkm_umem(object); |
| 56 | − if (!umem->priv || client->super) | |
| 57 | − memory = nvkm_memory_ref(umem->memory); | |
| 56 | + memory = nvkm_memory_ref(umem->memory); | |
| 58 | 57 | } |
| 59 | 58 | |
| 60 | 59 | return memory ? memory : ERR_PTR(-ENOENT); |
| @@ -167,7 +166,6 @@ nvkm_umem_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, · 106 unmodified lines | ||
| 167 | 166 | nvkm_object_ctor(&nvkm_umem, oclass, &umem->object); |
| 168 | 167 | umem->mmu = mmu; |
| 169 | 168 | umem->type = mmu->type[type].type; |
| 170 | − umem->priv = oclass->client->super; | |
| 171 | 169 | INIT_LIST_HEAD(&umem->head); |
| 172 | 170 | *pobject = &umem->object; |
| 173 | 171 | |
| @@ -8,7 +8,6 @@ struct nvkm_umem { · 7 unmodified lines | ||
| 8 | 8 | struct nvkm_object object; |
| 9 | 9 | struct nvkm_mmu *mmu; |
| 10 | 10 | u8 type:8; |
| 11 | − bool priv:1; | |
| 12 | 11 | bool mappable:1; |
| 13 | 12 | bool io:1; |
| 14 | 13 | |
| @@ -34,7 +34,7 @@ nvkm_ummu_sclass(struct nvkm_object *object, int index, · 33 unmodified lines | ||
| 34 | 34 | { |
| 35 | 35 | struct nvkm_mmu *mmu = nvkm_ummu(object)->mmu; |
| 36 | 36 | |
| 37 | − if (mmu->func->mem.user.oclass && oclass->client->super) { | |
| 37 | + if (mmu->func->mem.user.oclass) { | |
| 38 | 38 | if (index-- == 0) { |
| 39 | 39 | oclass->base = mmu->func->mem.user; |
| 40 | 40 | oclass->ctor = nvkm_umem_new; |
| @@ -45,7 +45,6 @@ nvkm_uvmm_search(struct nvkm_client *client, u64 handle) · 44 unmodified lines | ||
| 45 | 45 | static int |
| 46 | 46 | nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc) |
| 47 | 47 | { |
| 48 | − struct nvkm_client *client = uvmm->object.client; | |
| 49 | 48 | union { |
| 50 | 49 | struct nvif_vmm_pfnclr_v0 v0; |
| 51 | 50 | } *args = argv; |
| @@ -59,9 +58,6 @@ nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 7 unmodified lines | ||
| 59 | 58 | } else |
| 60 | 59 | return ret; |
| 61 | 60 | |
| 62 | − if (!client->super) | |
| 63 | − return -ENOENT; | |
| 64 | − | |
| 65 | 61 | if (size) { |
| 66 | 62 | mutex_lock(&vmm->mutex); |
| 67 | 63 | ret = nvkm_vmm_pfn_unmap(vmm, addr, size); |
| @@ -74,7 +70,6 @@ nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 6 unmodified lines | ||
| 74 | 70 | static int |
| 75 | 71 | nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) |
| 76 | 72 | { |
| 77 | − struct nvkm_client *client = uvmm->object.client; | |
| 78 | 73 | union { |
| 79 | 74 | struct nvif_vmm_pfnmap_v0 v0; |
| 80 | 75 | } *args = argv; |
| @@ -93,9 +88,6 @@ nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 12 unmodified lines | ||
| 93 | 88 | } else |
| 94 | 89 | return ret; |
| 95 | 90 | |
| 96 | − if (!client->super) | |
| 97 | − return -ENOENT; | |
| 98 | − | |
| 99 | 91 | if (size) { |
| 100 | 92 | mutex_lock(&vmm->mutex); |
| 101 | 93 | ret = nvkm_vmm_pfn_map(vmm, page, addr, size, phys); |
| @@ -108,7 +100,6 @@ nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 6 unmodified lines | ||
| 108 | 100 | static int |
| 109 | 101 | nvkm_uvmm_mthd_unmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) |
| 110 | 102 | { |
| 111 | − struct nvkm_client *client = uvmm->object.client; | |
| 112 | 103 | union { |
| 113 | 104 | struct nvif_vmm_unmap_v0 v0; |
| 114 | 105 | } *args = argv; |
| @@ -130,9 +121,8 @@ nvkm_uvmm_mthd_unmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 15 unmodified lines | ||
| 130 | 121 | goto done; |
| 131 | 122 | } |
| 132 | 123 | |
| 133 | − if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) { | |
| 134 | − VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr, | |
| 135 | − vma->user, !client->super, vma->busy); | |
| 124 | + if (ret = -ENOENT, vma->busy) { | |
| 125 | + VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy); | |
| 136 | 126 | goto done; |
| 137 | 127 | } |
| 138 | 128 | |
| @@ -181,9 +171,8 @@ nvkm_uvmm_mthd_map(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 42 unmodified lines | ||
| 181 | 171 | goto fail; |
| 182 | 172 | } |
| 183 | 173 | |
| 184 | − if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) { | |
| 185 | − VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr, | |
| 186 | − vma->user, !client->super, vma->busy); | |
| 174 | + if (ret = -ENOENT, vma->busy) { | |
| 175 | + VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy); | |
| 187 | 176 | goto fail; |
| 188 | 177 | } |
| 189 | 178 | |
| @@ -230,7 +219,6 @@ fail: · 40 unmodified lines | ||
| 230 | 219 | static int |
| 231 | 220 | nvkm_uvmm_mthd_put(struct nvkm_uvmm *uvmm, void *argv, u32 argc) |
| 232 | 221 | { |
| 233 | − struct nvkm_client *client = uvmm->object.client; | |
| 234 | 222 | union { |
| 235 | 223 | struct nvif_vmm_put_v0 v0; |
| 236 | 224 | } *args = argv; |
| @@ -252,9 +240,8 @@ nvkm_uvmm_mthd_put(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 15 unmodified lines | ||
| 252 | 240 | goto done; |
| 253 | 241 | } |
| 254 | 242 | |
| 255 | − if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) { | |
| 256 | − VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr, | |
| 257 | − vma->user, !client->super, vma->busy); | |
| 243 | + if (ret = -ENOENT, vma->busy) { | |
| 244 | + VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy); | |
| 258 | 245 | goto done; |
| 259 | 246 | } |
| 260 | 247 | |
| @@ -268,7 +255,6 @@ done: · 7 unmodified lines | ||
| 268 | 255 | static int |
| 269 | 256 | nvkm_uvmm_mthd_get(struct nvkm_uvmm *uvmm, void *argv, u32 argc) |
| 270 | 257 | { |
| 271 | − struct nvkm_client *client = uvmm->object.client; | |
| 272 | 258 | union { |
| 273 | 259 | struct nvif_vmm_get_v0 v0; |
| 274 | 260 | } *args = argv; |
| @@ -297,7 +283,6 @@ nvkm_uvmm_mthd_get(struct nvkm_uvmm *uvmm, void *argv, u32 argc) · 22 unmodified lines | ||
| 297 | 283 | return ret; |
| 298 | 284 | |
| 299 | 285 | args->v0.addr = vma->addr; |
| 300 | − vma->user = !client->super; | |
| 301 | 286 | return ret; |
| 302 | 287 | } |
| 303 | 288 | |
| @@ -774,7 +774,6 @@ nvkm_vma_tail(struct nvkm_vma *vma, u64 tail) · 773 unmodified lines | ||
| 774 | 774 | new->refd = vma->refd; |
| 775 | 775 | new->used = vma->used; |
| 776 | 776 | new->part = vma->part; |
| 777 | − new->user = vma->user; | |
| 778 | 777 | new->busy = vma->busy; |
| 779 | 778 | new->mapped = vma->mapped; |
| 780 | 779 | list_add(&new->head, &vma->head); |
| @@ -951,7 +950,7 @@ nvkm_vmm_node_split(struct nvkm_vmm *vmm, · 170 unmodified lines | ||
| 951 | 950 | static void |
| 952 | 951 | nvkm_vma_dump(struct nvkm_vma *vma) |
| 953 | 952 | { |
| 954 | − printk(KERN_ERR "%016llx %016llx %c%c%c%c%c%c%c%c%c %p\n", | |
| 953 | + printk(KERN_ERR "%016llx %016llx %c%c%c%c%c%c%c%c %p\n", | |
| 955 | 954 | vma->addr, (u64)vma->size, |
| 956 | 955 | vma->used ? '-' : 'F', |
| 957 | 956 | vma->mapref ? 'R' : '-', |
| @@ -959,7 +958,6 @@ nvkm_vma_dump(struct nvkm_vma *vma) · 1 unmodified line | ||
| 959 | 958 | vma->page != NVKM_VMA_PAGE_NONE ? '0' + vma->page : '-', |
| 960 | 959 | vma->refd != NVKM_VMA_PAGE_NONE ? '0' + vma->refd : '-', |
| 961 | 960 | vma->part ? 'P' : '-', |
| 962 | − vma->user ? 'U' : '-', | |
| 963 | 961 | vma->busy ? 'B' : '-', |
| 964 | 962 | vma->mapped ? 'M' : '-', |
| 965 | 963 | vma->memory); |
| @@ -1024,7 +1022,6 @@ nvkm_vmm_ctor_managed(struct nvkm_vmm *vmm, u64 addr, u64 size) · 58 unmodified lines | ||
| 1024 | 1022 | vma->mapref = true; |
| 1025 | 1023 | vma->sparse = false; |
| 1026 | 1024 | vma->used = true; |
| 1027 | − vma->user = true; | |
| 1028 | 1025 | nvkm_vmm_node_insert(vmm, vma); |
| 1029 | 1026 | list_add_tail(&vma->head, &vmm->list); |
| 1030 | 1027 | return 0; |
| @@ -1615,7 +1612,6 @@ nvkm_vmm_put_locked(struct nvkm_vmm *vmm, struct nvkm_vma *vma) · 584 unmodified lines | ||
| 1615 | 1612 | vma->page = NVKM_VMA_PAGE_NONE; |
| 1616 | 1613 | vma->refd = NVKM_VMA_PAGE_NONE; |
| 1617 | 1614 | vma->used = false; |
| 1618 | − vma->user = false; | |
| 1619 | 1615 | nvkm_vmm_put_region(vmm, vma); |
| 1620 | 1616 | } |
| 1621 | 1617 | |
| @@ -534,15 +534,13 @@ int · 533 unmodified lines | ||
| 534 | 534 | gp100_vmm_mthd(struct nvkm_vmm *vmm, |
| 535 | 535 | struct nvkm_client *client, u32 mthd, void *argv, u32 argc) |
| 536 | 536 | { |
| 537 | − if (client->super) { | |
| 538 | − switch (mthd) { | |
| 539 | − case GP100_VMM_VN_FAULT_REPLAY: | |
| 540 | − return gp100_vmm_fault_replay(vmm, argv, argc); | |
| 541 | − case GP100_VMM_VN_FAULT_CANCEL: | |
| 542 | − return gp100_vmm_fault_cancel(vmm, argv, argc); | |
| 543 | − default: | |
| 544 | − break; | |
| 545 | − } | |
| 537 | + switch (mthd) { | |
| 538 | + case GP100_VMM_VN_FAULT_REPLAY: | |
| 539 | + return gp100_vmm_fault_replay(vmm, argv, argc); | |
| 540 | + case GP100_VMM_VN_FAULT_CANCEL: | |
| 541 | + return gp100_vmm_fault_cancel(vmm, argv, argc); | |
| 542 | + default: | |
| 543 | + break; | |
| 546 | 544 | } |
| 547 | 545 | return -EINVAL; |
| 548 | 546 | } |
| @@ -706,9 +706,7 @@ static int nt35510_power_on(struct nt35510 *nt) · 705 unmodified lines | ||
| 706 | 706 | if (ret) |
| 707 | 707 | return ret; |
| 708 | 708 | |
| 709 | − ret = nt35510_read_id(nt); | |
| 710 | − if (ret) | |
| 711 | − return ret; | |
| 709 | + nt35510_read_id(nt); | |
| 712 | 710 | |
| 713 | 711 | /* Set up stuff in manufacturer control, page 1 */ |
| 714 | 712 | ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, |
| @@ -447,7 +447,6 @@ static int rpi_touchscreen_remove(struct i2c_client *i2c) · 446 unmodified lines | ||
| 447 | 447 | drm_panel_remove(&ts->base); |
| 448 | 448 | |
| 449 | 449 | mipi_dsi_device_unregister(ts->dsi); |
| 450 | − kfree(ts->dsi); | |
| 451 | 450 | |
| 452 | 451 | return 0; |
| 453 | 452 | } |
| @@ -4166,7 +4166,7 @@ static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode · 4165 unmodified lines | ||
| 4166 | 4166 | static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { |
| 4167 | 4167 | .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, |
| 4168 | 4168 | .num_modes = 1, |
| 4169 | − .bpc = 6, | |
| 4169 | + .bpc = 8, | |
| 4170 | 4170 | .size = { |
| 4171 | 4171 | .width = 154, |
| 4172 | 4172 | .height = 90, |
| @@ -127,7 +127,7 @@ static void qxl_bo_move_notify(struct ttm_buffer_object *bo, · 126 unmodified lines | ||
| 127 | 127 | struct qxl_bo *qbo; |
| 128 | 128 | struct qxl_device *qdev; |
| 129 | 129 | |
| 130 | − if (!qxl_ttm_bo_is_qxl_bo(bo)) | |
| 130 | + if (!qxl_ttm_bo_is_qxl_bo(bo) || !bo->resource) | |
| 131 | 131 | return; |
| 132 | 132 | qbo = to_qxl_bo(bo); |
| 133 | 133 | qdev = to_qxl(qbo->tbo.base.dev); |
| @@ -102,6 +102,9 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo, · 101 unmodified lines | ||
| 102 | 102 | return; |
| 103 | 103 | } |
| 104 | 104 | |
| 105 | + if (!mem) | |
| 106 | + return; | |
| 107 | + | |
| 105 | 108 | man = ttm_manager_type(bdev, mem->mem_type); |
| 106 | 109 | list_move_tail(&bo->lru, &man->lru[bo->priority]); |
| 107 | 110 | |
| @@ -63,6 +63,9 @@ int ttm_mem_io_reserve(struct ttm_device *bdev, · 62 unmodified lines | ||
| 63 | 63 | void ttm_mem_io_free(struct ttm_device *bdev, |
| 64 | 64 | struct ttm_resource *mem) |
| 65 | 65 | { |
| 66 | + if (!mem) | |
| 67 | + return; | |
| 68 | + | |
| 66 | 69 | if (!mem->bus.offset && !mem->bus.addr) |
| 67 | 70 | return; |
| 68 | 71 | |
| @@ -44,6 +44,8 @@ static unsigned ttm_glob_use_count; · 43 unmodified lines | ||
| 44 | 44 | struct ttm_global ttm_glob; |
| 45 | 45 | EXPORT_SYMBOL(ttm_glob); |
| 46 | 46 | |
| 47 | +struct dentry *ttm_debugfs_root; | |
| 48 | + | |
| 47 | 49 | static void ttm_global_release(void) |
| 48 | 50 | { |
| 49 | 51 | struct ttm_global *glob = &ttm_glob; |
| @@ -53,6 +55,7 @@ static void ttm_global_release(void) · 3 unmodified lines | ||
| 53 | 55 | goto out; |
| 54 | 56 | |
| 55 | 57 | ttm_pool_mgr_fini(); |
| 58 | + debugfs_remove(ttm_debugfs_root); | |
| 56 | 59 | |
| 57 | 60 | __free_page(glob->dummy_read_page); |
| 58 | 61 | memset(glob, 0, sizeof(*glob)); |
| @@ -73,6 +76,11 @@ static int ttm_global_init(void) · 14 unmodified lines | ||
| 73 | 76 | |
| 74 | 77 | si_meminfo(&si); |
| 75 | 78 | |
| 79 | + ttm_debugfs_root = debugfs_create_dir("ttm", NULL); | |
| 80 | + if (IS_ERR(ttm_debugfs_root)) { | |
| 81 | + ttm_debugfs_root = NULL; | |
| 82 | + } | |
| 83 | + | |
| 76 | 84 | /* Limit the number of pages in the pool to about 50% of the total |
| 77 | 85 | * system memory. |
| 78 | 86 | */ |
| @@ -100,6 +108,10 @@ static int ttm_global_init(void) · 21 unmodified lines | ||
| 100 | 108 | debugfs_create_atomic_t("buffer_objects", 0444, ttm_debugfs_root, |
| 101 | 109 | &glob->bo_count); |
| 102 | 110 | out: |
| 111 | + if (ret && ttm_debugfs_root) | |
| 112 | + debugfs_remove(ttm_debugfs_root); | |
| 113 | + if (ret) | |
| 114 | + --ttm_glob_use_count; | |
| 103 | 115 | mutex_unlock(&ttm_global_mutex); |
| 104 | 116 | return ret; |
| 105 | 117 | } |
| @@ -72,22 +72,6 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) · 71 unmodified lines | ||
| 72 | 72 | return tmp; |
| 73 | 73 | } |
| 74 | 74 | |
| 75 | −struct dentry *ttm_debugfs_root; | |
| 76 | − | |
| 77 | −static int __init ttm_init(void) | |
| 78 | −{ | |
| 79 | − ttm_debugfs_root = debugfs_create_dir("ttm", NULL); | |
| 80 | − return 0; | |
| 81 | −} | |
| 82 | − | |
| 83 | −static void __exit ttm_exit(void) | |
| 84 | −{ | |
| 85 | − debugfs_remove(ttm_debugfs_root); | |
| 86 | −} | |
| 87 | − | |
| 88 | −module_init(ttm_init); | |
| 89 | −module_exit(ttm_exit); | |
| 90 | − | |
| 91 | 75 | MODULE_AUTHOR("Thomas Hellstrom, Jerome Glisse"); |
| 92 | 76 | MODULE_DESCRIPTION("TTM memory manager subsystem (for DRM device)"); |
| 93 | 77 | MODULE_LICENSE("GPL and additional rights"); |
| @@ -181,6 +181,9 @@ int ttm_range_man_fini(struct ttm_device *bdev, · 180 unmodified lines | ||
| 181 | 181 | struct drm_mm *mm = &rman->mm; |
| 182 | 182 | int ret; |
| 183 | 183 | |
| 184 | + if (!man) | |
| 185 | + return 0; | |
| 186 | + | |
| 184 | 187 | ttm_resource_manager_set_used(man, false); |
| 185 | 188 | |
| 186 | 189 | ret = ttm_resource_manager_evict_all(bdev, man); |
| @@ -1857,38 +1857,46 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) · 1856 unmodified lines | ||
| 1857 | 1857 | vc4_hdmi_cec_update_clk_div(vc4_hdmi); |
| 1858 | 1858 | |
| 1859 | 1859 | if (vc4_hdmi->variant->external_irq_controller) { |
| 1860 | − ret = devm_request_threaded_irq(&pdev->dev, | |
| 1861 | − platform_get_irq_byname(pdev, "cec-rx"), | |
| 1862 | − vc4_cec_irq_handler_rx_bare, | |
| 1863 | − vc4_cec_irq_handler_rx_thread, 0, | |
| 1864 | − "vc4 hdmi cec rx", vc4_hdmi); | |
| 1860 | + ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), | |
| 1861 | + vc4_cec_irq_handler_rx_bare, | |
| 1862 | + vc4_cec_irq_handler_rx_thread, 0, | |
| 1863 | + "vc4 hdmi cec rx", vc4_hdmi); | |
| 1865 | 1864 | if (ret) |
| 1866 | 1865 | goto err_delete_cec_adap; |
| 1867 | 1866 | |
| 1868 | − ret = devm_request_threaded_irq(&pdev->dev, | |
| 1869 | − platform_get_irq_byname(pdev, "cec-tx"), | |
| 1870 | − vc4_cec_irq_handler_tx_bare, | |
| 1871 | − vc4_cec_irq_handler_tx_thread, 0, | |
| 1872 | − "vc4 hdmi cec tx", vc4_hdmi); | |
| 1867 | + ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), | |
| 1868 | + vc4_cec_irq_handler_tx_bare, | |
| 1869 | + vc4_cec_irq_handler_tx_thread, 0, | |
| 1870 | + "vc4 hdmi cec tx", vc4_hdmi); | |
| 1873 | 1871 | if (ret) |
| 1874 | − goto err_delete_cec_adap; | |
| 1872 | + goto err_remove_cec_rx_handler; | |
| 1875 | 1873 | } else { |
| 1876 | 1874 | HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); |
| 1877 | 1875 | |
| 1878 | − ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), | |
| 1879 | − vc4_cec_irq_handler, | |
| 1880 | − vc4_cec_irq_handler_thread, 0, | |
| 1881 | − "vc4 hdmi cec", vc4_hdmi); | |
| 1876 | + ret = request_threaded_irq(platform_get_irq(pdev, 0), | |
| 1877 | + vc4_cec_irq_handler, | |
| 1878 | + vc4_cec_irq_handler_thread, 0, | |
| 1879 | + "vc4 hdmi cec", vc4_hdmi); | |
| 1882 | 1880 | if (ret) |
| 1883 | 1881 | goto err_delete_cec_adap; |
| 1884 | 1882 | } |
| 1885 | 1883 | |
| 1886 | 1884 | ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); |
| 1887 | 1885 | if (ret < 0) |
| 1888 | − goto err_delete_cec_adap; | |
| 1886 | + goto err_remove_handlers; | |
| 1889 | 1887 | |
| 1890 | 1888 | return 0; |
| 1891 | 1889 | |
| 1890 | +err_remove_handlers: | |
| 1891 | + if (vc4_hdmi->variant->external_irq_controller) | |
| 1892 | + free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); | |
| 1893 | + else | |
| 1894 | + free_irq(platform_get_irq(pdev, 0), vc4_hdmi); | |
| 1895 | + | |
| 1896 | +err_remove_cec_rx_handler: | |
| 1897 | + if (vc4_hdmi->variant->external_irq_controller) | |
| 1898 | + free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); | |
| 1899 | + | |
| 1892 | 1900 | err_delete_cec_adap: |
| 1893 | 1901 | cec_delete_adapter(vc4_hdmi->cec_adap); |
| 1894 | 1902 | |
| @@ -1897,6 +1905,15 @@ err_delete_cec_adap: · 2 unmodified lines | ||
| 1897 | 1905 | |
| 1898 | 1906 | static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) |
| 1899 | 1907 | { |
| 1908 | + struct platform_device *pdev = vc4_hdmi->pdev; | |
| 1909 | + | |
| 1910 | + if (vc4_hdmi->variant->external_irq_controller) { | |
| 1911 | + free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); | |
| 1912 | + free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); | |
| 1913 | + } else { | |
| 1914 | + free_irq(platform_get_irq(pdev, 0), vc4_hdmi); | |
| 1915 | + } | |
| 1916 | + | |
| 1900 | 1917 | cec_unregister_adapter(vc4_hdmi->cec_adap); |
| 1901 | 1918 | } |
| 1902 | 1919 | #else |
| @@ -36,6 +36,7 @@ · 35 unmodified lines | ||
| 36 | 36 | #include <drm/drm_ioctl.h> |
| 37 | 37 | #include <drm/drm_sysfs.h> |
| 38 | 38 | #include <drm/ttm/ttm_bo_driver.h> |
| 39 | +#include <drm/ttm/ttm_range_manager.h> | |
| 39 | 40 | #include <drm/ttm/ttm_placement.h> |
| 40 | 41 | #include <generated/utsrelease.h> |
| 41 | 42 | |
| @@ -492,7 +492,7 @@ struct vmw_private { · 491 unmodified lines | ||
| 492 | 492 | resource_size_t vram_start; |
| 493 | 493 | resource_size_t vram_size; |
| 494 | 494 | resource_size_t prim_bb_mem; |
| 495 | − void __iomem *rmmio; | |
| 495 | + u32 __iomem *rmmio; | |
| 496 | 496 | u32 *fifo_mem; |
| 497 | 497 | resource_size_t fifo_mem_size; |
| 498 | 498 | uint32_t fb_max_width; |
| @@ -354,7 +354,6 @@ static void vmw_otable_batch_takedown(struct vmw_private *dev_priv, · 353 unmodified lines | ||
| 354 | 354 | ttm_bo_unpin(bo); |
| 355 | 355 | ttm_bo_unreserve(bo); |
| 356 | 356 | |
| 357 | − ttm_bo_unpin(batch->otable_bo); | |
| 358 | 357 | ttm_bo_put(batch->otable_bo); |
| 359 | 358 | batch->otable_bo = NULL; |
| 360 | 359 | } |
| @@ -576,7 +576,7 @@ config HID_LOGITECH_HIDPP · 575 unmodified lines | ||
| 576 | 576 | depends on HID_LOGITECH |
| 577 | 577 | select POWER_SUPPLY |
| 578 | 578 | help |
| 579 | − Support for Logitech devices relyingon the HID++ Logitech specification | |
| 579 | + Support for Logitech devices relying on the HID++ Logitech specification | |
| 580 | 580 | |
| 581 | 581 | Say Y if you want support for Logitech devices relying on the HID++ |
| 582 | 582 | specification. Such devices are the various Logitech Touchpads (T650, |
| @@ -58,7 +58,7 @@ static void amd_stop_sensor_v2(struct amd_mp2_dev *privdata, u16 sensor_idx) · 57 unmodified lines | ||
| 58 | 58 | cmd_base.cmd_v2.sensor_id = sensor_idx; |
| 59 | 59 | cmd_base.cmd_v2.length = 16; |
| 60 | 60 | |
| 61 | − writeq(0x0, privdata->mmio + AMD_C2P_MSG2); | |
| 61 | + writeq(0x0, privdata->mmio + AMD_C2P_MSG1); | |
| 62 | 62 | writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); |
| 63 | 63 | } |
| 64 | 64 | |
| @@ -501,6 +501,8 @@ static const struct hid_device_id apple_devices[] = { · 500 unmodified lines | ||
| 501 | 501 | APPLE_RDESC_JIS }, |
| 502 | 502 | { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ANSI), |
| 503 | 503 | .driver_data = APPLE_HAS_FN }, |
| 504 | + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ANSI), | |
| 505 | + .driver_data = APPLE_HAS_FN }, | |
| 504 | 506 | { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ISO), |
| 505 | 507 | .driver_data = APPLE_HAS_FN }, |
| 506 | 508 | { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ISO), |
| @@ -485,9 +485,6 @@ static void asus_kbd_backlight_set(struct led_classdev *led_cdev, · 484 unmodified lines | ||
| 485 | 485 | { |
| 486 | 486 | struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds, |
| 487 | 487 | cdev); |
| 488 | − if (led->brightness == brightness) | |
| 489 | − return; | |
| 490 | − | |
| 491 | 488 | led->brightness = brightness; |
| 492 | 489 | schedule_work(&led->work); |
| 493 | 490 | } |
| @@ -742,7 +742,7 @@ static int ft260_is_interface_enabled(struct hid_device *hdev) · 741 unmodified lines | ||
| 742 | 742 | int ret; |
| 743 | 743 | |
| 744 | 744 | ret = ft260_get_system_config(hdev, &cfg); |
| 745 | − if (ret) | |
| 745 | + if (ret < 0) | |
| 746 | 746 | return ret; |
| 747 | 747 | |
| 748 | 748 | ft260_dbg("interface: 0x%02x\n", interface); |
| @@ -754,23 +754,16 @@ static int ft260_is_interface_enabled(struct hid_device *hdev) · 5 unmodified lines | ||
| 754 | 754 | switch (cfg.chip_mode) { |
| 755 | 755 | case FT260_MODE_ALL: |
| 756 | 756 | case FT260_MODE_BOTH: |
| 757 | − if (interface == 1) { | |
| 757 | + if (interface == 1) | |
| 758 | 758 | hid_info(hdev, "uart interface is not supported\n"); |
| 759 | − return 0; | |
| 760 | − } | |
| 761 | − ret = 1; | |
| 759 | + else | |
| 760 | + ret = 1; | |
| 762 | 761 | break; |
| 763 | 762 | case FT260_MODE_UART: |
| 764 | − if (interface == 0) { | |
| 765 | − hid_info(hdev, "uart is unsupported on interface 0\n"); | |
| 766 | − ret = 0; | |
| 767 | − } | |
| 763 | + hid_info(hdev, "uart interface is not supported\n"); | |
| 768 | 764 | break; |
| 769 | 765 | case FT260_MODE_I2C: |
| 770 | − if (interface == 1) { | |
| 771 | − hid_info(hdev, "i2c is unsupported on interface 1\n"); | |
| 772 | − ret = 0; | |
| 773 | − } | |
| 766 | + ret = 1; | |
| 774 | 767 | break; |
| 775 | 768 | } |
| 776 | 769 | return ret; |
| @@ -785,7 +778,7 @@ static int ft260_byte_show(struct hid_device *hdev, int id, u8 *cfg, int len, · 8 unmodified lines | ||
| 785 | 778 | if (ret < 0) |
| 786 | 779 | return ret; |
| 787 | 780 | |
| 788 | − return scnprintf(buf, PAGE_SIZE, "%hi\n", *field); | |
| 781 | + return scnprintf(buf, PAGE_SIZE, "%d\n", *field); | |
| 789 | 782 | } |
| 790 | 783 | |
| 791 | 784 | static int ft260_word_show(struct hid_device *hdev, int id, u8 *cfg, int len, |
| @@ -797,7 +790,7 @@ static int ft260_word_show(struct hid_device *hdev, int id, u8 *cfg, int len, · 5 unmodified lines | ||
| 797 | 790 | if (ret < 0) |
| 798 | 791 | return ret; |
| 799 | 792 | |
| 800 | − return scnprintf(buf, PAGE_SIZE, "%hi\n", le16_to_cpu(*field)); | |
| 793 | + return scnprintf(buf, PAGE_SIZE, "%d\n", le16_to_cpu(*field)); | |
| 801 | 794 | } |
| 802 | 795 | |
| 803 | 796 | #define FT260_ATTR_SHOW(name, reptype, id, type, func) \ |
| @@ -1004,11 +997,9 @@ err_hid_stop: · 200 unmodified lines | ||
| 1004 | 997 | |
| 1005 | 998 | static void ft260_remove(struct hid_device *hdev) |
| 1006 | 999 | { |
| 1007 | − int ret; | |
| 1008 | 1000 | struct ft260_device *dev = hid_get_drvdata(hdev); |
| 1009 | 1001 | |
| 1010 | − ret = ft260_is_interface_enabled(hdev); | |
| 1011 | − if (ret <= 0) | |
| 1002 | + if (!dev) | |
| 1012 | 1003 | return; |
| 1013 | 1004 | |
| 1014 | 1005 | sysfs_remove_group(&hdev->dev.kobj, &ft260_attr_group); |
| @@ -784,6 +784,17 @@ static void hid_ishtp_cl_reset_handler(struct work_struct *work) · 783 unmodified lines | ||
| 784 | 784 | } |
| 785 | 785 | } |
| 786 | 786 | |
| 787 | +static void hid_ishtp_cl_resume_handler(struct work_struct *work) | |
| 788 | +{ | |
| 789 | + struct ishtp_cl_data *client_data = container_of(work, struct ishtp_cl_data, resume_work); | |
| 790 | + struct ishtp_cl *hid_ishtp_cl = client_data->hid_ishtp_cl; | |
| 791 | + | |
| 792 | + if (ishtp_wait_resume(ishtp_get_ishtp_device(hid_ishtp_cl))) { | |
| 793 | + client_data->suspended = false; | |
| 794 | + wake_up_interruptible(&client_data->ishtp_resume_wait); | |
| 795 | + } | |
| 796 | +} | |
| 797 | + | |
| 787 | 798 | ishtp_print_log ishtp_hid_print_trace; |
| 788 | 799 | |
| 789 | 800 | /** |
| @@ -822,6 +833,8 @@ static int hid_ishtp_cl_probe(struct ishtp_cl_device *cl_device) · 32 unmodified lines | ||
| 822 | 833 | init_waitqueue_head(&client_data->ishtp_resume_wait); |
| 823 | 834 | |
| 824 | 835 | INIT_WORK(&client_data->work, hid_ishtp_cl_reset_handler); |
| 836 | + INIT_WORK(&client_data->resume_work, hid_ishtp_cl_resume_handler); | |
| 837 | + | |
| 825 | 838 | |
| 826 | 839 | ishtp_hid_print_trace = ishtp_trace_callback(cl_device); |
| 827 | 840 | |
| @@ -921,7 +934,7 @@ static int hid_ishtp_cl_resume(struct device *device) · 93 unmodified lines | ||
| 921 | 934 | |
| 922 | 935 | hid_ishtp_trace(client_data, "%s hid_ishtp_cl %p\n", __func__, |
| 923 | 936 | hid_ishtp_cl); |
| 924 | − client_data->suspended = false; | |
| 937 | + schedule_work(&client_data->resume_work); | |
| 925 | 938 | return 0; |
| 926 | 939 | } |
| 927 | 940 | |
| @@ -135,6 +135,7 @@ struct ishtp_cl_data { · 134 unmodified lines | ||
| 135 | 135 | int multi_packet_cnt; |
| 136 | 136 | |
| 137 | 137 | struct work_struct work; |
| 138 | + struct work_struct resume_work; | |
| 138 | 139 | struct ishtp_cl_device *cl_device; |
| 139 | 140 | }; |
| 140 | 141 | |
| @@ -314,13 +314,6 @@ static int ishtp_cl_device_resume(struct device *dev) · 313 unmodified lines | ||
| 314 | 314 | if (!device) |
| 315 | 315 | return 0; |
| 316 | 316 | |
| 317 | − /* | |
| 318 | − * When ISH needs hard reset, it is done asynchrnously, hence bus | |
| 319 | − * resume will be called before full ISH resume | |
| 320 | − */ | |
| 321 | − if (device->ishtp_dev->resume_flag) | |
| 322 | − return 0; | |
| 323 | − | |
| 324 | 317 | driver = to_ishtp_cl_driver(dev->driver); |
| 325 | 318 | if (driver && driver->driver.pm) { |
| 326 | 319 | if (driver->driver.pm->resume) |
| @@ -849,6 +842,28 @@ struct device *ishtp_device(struct ishtp_cl_device *device) · 522 unmodified lines | ||
| 849 | 842 | } |
| 850 | 843 | EXPORT_SYMBOL(ishtp_device); |
| 851 | 844 | |
| 845 | +/** | |
| 846 | + * ishtp_wait_resume() - Wait for IPC resume | |
| 847 | + * | |
| 848 | + * Wait for IPC resume | |
| 849 | + * | |
| 850 | + * Return: resume complete or not | |
| 851 | + */ | |
| 852 | +bool ishtp_wait_resume(struct ishtp_device *dev) | |
| 853 | +{ | |
| 854 | + /* 50ms to get resume response */ | |
| 855 | + #define WAIT_FOR_RESUME_ACK_MS 50 | |
| 856 | + | |
| 857 | + /* Waiting to get resume response */ | |
| 858 | + if (dev->resume_flag) | |
| 859 | + wait_event_interruptible_timeout(dev->resume_wait, | |
| 860 | + !dev->resume_flag, | |
| 861 | + msecs_to_jiffies(WAIT_FOR_RESUME_ACK_MS)); | |
| 862 | + | |
| 863 | + return (!dev->resume_flag); | |
| 864 | +} | |
| 865 | +EXPORT_SYMBOL_GPL(ishtp_wait_resume); | |
| 866 | + | |
| 852 | 867 | /** |
| 853 | 868 | * ishtp_get_pci_device() - Return PCI device dev pointer |
| 854 | 869 | * This interface is used to return PCI device pointer |
| @@ -38,7 +38,7 @@ config USB_HIDDEV · 37 unmodified lines | ||
| 38 | 38 | help |
| 39 | 39 | Say Y here if you want to support HID devices (from the USB |
| 40 | 40 | specification standpoint) that aren't strictly user interface |
| 41 | − devices, like monitor controls and Uninterruptable Power Supplies. | |
| 41 | + devices, like monitor controls and Uninterruptible Power Supplies. | |
| 42 | 42 | |
| 43 | 43 | This module supports these devices separately using a separate |
| 44 | 44 | event interface on /dev/usb/hiddevX (char 180:96 to 180:111). |
| @@ -2548,6 +2548,9 @@ static void wacom_wac_finger_slot(struct wacom_wac *wacom_wac, · 2547 unmodified lines | ||
| 2548 | 2548 | int slot; |
| 2549 | 2549 | |
| 2550 | 2550 | slot = input_mt_get_slot_by_key(input, hid_data->id); |
| 2551 | + if (slot < 0) | |
| 2552 | + return; | |
| 2553 | + | |
| 2551 | 2554 | input_mt_slot(input, slot); |
| 2552 | 2555 | input_mt_report_slot_state(input, MT_TOOL_FINGER, prox); |
| 2553 | 2556 | } |
| @@ -3831,7 +3834,7 @@ int wacom_setup_touch_input_capabilities(struct input_dev *input_dev, · 1277 unmodified lines | ||
| 3831 | 3834 | wacom_wac->shared->touch->product == 0xF6) { |
| 3832 | 3835 | input_dev->evbit[0] |= BIT_MASK(EV_SW); |
| 3833 | 3836 | __set_bit(SW_MUTE_DEVICE, input_dev->swbit); |
| 3834 | − wacom_wac->shared->has_mute_touch_switch = true; | |
| 3837 | + wacom_wac->has_mute_touch_switch = true; | |
| 3835 | 3838 | } |
| 3836 | 3839 | fallthrough; |
| 3837 | 3840 | |
| @@ -605,6 +605,17 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) · 604 unmodified lines | ||
| 605 | 605 | */ |
| 606 | 606 | mutex_lock(&vmbus_connection.channel_mutex); |
| 607 | 607 | |
| 608 | + list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) { | |
| 609 | + if (guid_equal(&channel->offermsg.offer.if_type, | |
| 610 | + &newchannel->offermsg.offer.if_type) && | |
| 611 | + guid_equal(&channel->offermsg.offer.if_instance, | |
| 612 | + &newchannel->offermsg.offer.if_instance)) { | |
| 613 | + fnew = false; | |
| 614 | + newchannel->primary_channel = channel; | |
| 615 | + break; | |
| 616 | + } | |
| 617 | + } | |
| 618 | + | |
| 608 | 619 | init_vp_index(newchannel); |
| 609 | 620 | |
| 610 | 621 | /* Remember the channels that should be cleaned up upon suspend. */ |
| @@ -617,16 +628,6 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) · 6 unmodified lines | ||
| 617 | 628 | */ |
| 618 | 629 | atomic_dec(&vmbus_connection.offer_in_progress); |
| 619 | 630 | |
| 620 | − list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) { | |
| 621 | − if (guid_equal(&channel->offermsg.offer.if_type, | |
| 622 | − &newchannel->offermsg.offer.if_type) && | |
| 623 | − guid_equal(&channel->offermsg.offer.if_instance, | |
| 624 | − &newchannel->offermsg.offer.if_instance)) { | |
| 625 | − fnew = false; | |
| 626 | − break; | |
| 627 | − } | |
| 628 | − } | |
| 629 | − | |
| 630 | 631 | if (fnew) { |
| 631 | 632 | list_add_tail(&newchannel->listentry, |
| 632 | 633 | &vmbus_connection.chn_list); |
| @@ -647,7 +648,6 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) · 14 unmodified lines | ||
| 647 | 648 | /* |
| 648 | 649 | * Process the sub-channel. |
| 649 | 650 | */ |
| 650 | − newchannel->primary_channel = channel; | |
| 651 | 651 | list_add_tail(&newchannel->sc_list, &channel->sc_list); |
| 652 | 652 | } |
| 653 | 653 | |
| @@ -683,6 +683,30 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) · 29 unmodified lines | ||
| 683 | 683 | queue_work(wq, &newchannel->add_channel_work); |
| 684 | 684 | } |
| 685 | 685 | |
| 686 | +/* | |
| 687 | + * Check if CPUs used by other channels of the same device. | |
| 688 | + * It should only be called by init_vp_index(). | |
| 689 | + */ | |
| 690 | +static bool hv_cpuself_used(u32 cpu, struct vmbus_channel *chn) | |
| 691 | +{ | |
| 692 | + struct vmbus_channel *primary = chn->primary_channel; | |
| 693 | + struct vmbus_channel *sc; | |
| 694 | + | |
| 695 | + lockdep_assert_held(&vmbus_connection.channel_mutex); | |
| 696 | + | |
| 697 | + if (!primary) | |
| 698 | + return false; | |
| 699 | + | |
| 700 | + if (primary->target_cpu == cpu) | |
| 701 | + return true; | |
| 702 | + | |
| 703 | + list_for_each_entry(sc, &primary->sc_list, sc_list) | |
| 704 | + if (sc != chn && sc->target_cpu == cpu) | |
| 705 | + return true; | |
| 706 | + | |
| 707 | + return false; | |
| 708 | +} | |
| 709 | + | |
| 686 | 710 | /* |
| 687 | 711 | * We use this state to statically distribute the channel interrupt load. |
| 688 | 712 | */ |
| @@ -702,6 +726,7 @@ static int next_numa_node_id; · 13 unmodified lines | ||
| 702 | 726 | static void init_vp_index(struct vmbus_channel *channel) |
| 703 | 727 | { |
| 704 | 728 | bool perf_chn = hv_is_perf_channel(channel); |
| 729 | + u32 i, ncpu = num_online_cpus(); | |
| 705 | 730 | cpumask_var_t available_mask; |
| 706 | 731 | struct cpumask *alloced_mask; |
| 707 | 732 | u32 target_cpu; |
| @@ -724,31 +749,38 @@ static void init_vp_index(struct vmbus_channel *channel) · 16 unmodified lines | ||
| 724 | 749 | return; |
| 725 | 750 | } |
| 726 | 751 | |
| 727 | − while (true) { | |
| 728 | − numa_node = next_numa_node_id++; | |
| 729 | − if (numa_node == nr_node_ids) { | |
| 730 | − next_numa_node_id = 0; | |
| 731 | − continue; | |
| 752 | + for (i = 1; i <= ncpu + 1; i++) { | |
| 753 | + while (true) { | |
| 754 | + numa_node = next_numa_node_id++; | |
| 755 | + if (numa_node == nr_node_ids) { | |
| 756 | + next_numa_node_id = 0; | |
| 757 | + continue; | |
| 758 | + } | |
| 759 | + if (cpumask_empty(cpumask_of_node(numa_node))) | |
| 760 | + continue; | |
| 761 | + break; | |
| 762 | + } | |
| 763 | + alloced_mask = &hv_context.hv_numa_map[numa_node]; | |
| 764 | + | |
| 765 | + if (cpumask_weight(alloced_mask) == | |
| 766 | + cpumask_weight(cpumask_of_node(numa_node))) { | |
| 767 | + /* | |
| 768 | + * We have cycled through all the CPUs in the node; | |
| 769 | + * reset the alloced map. | |
| 770 | + */ | |
| 771 | + cpumask_clear(alloced_mask); | |
| 732 | 772 | } |
| 733 | − if (cpumask_empty(cpumask_of_node(numa_node))) | |
| 734 | − continue; | |
| 735 | − break; | |
| 736 | − } | |
| 737 | − alloced_mask = &hv_context.hv_numa_map[numa_node]; | |
| 738 | 773 | |
| 739 | − if (cpumask_weight(alloced_mask) == | |
| 740 | − cpumask_weight(cpumask_of_node(numa_node))) { | |
| 741 | − /* | |
| 742 | − * We have cycled through all the CPUs in the node; | |
| 743 | − * reset the alloced map. | |
| 744 | − */ | |
| 745 | − cpumask_clear(alloced_mask); | |
| 746 | − } | |
| 774 | + cpumask_xor(available_mask, alloced_mask, | |
| 775 | + cpumask_of_node(numa_node)); | |
| 747 | 776 | |
| 748 | − cpumask_xor(available_mask, alloced_mask, cpumask_of_node(numa_node)); | |
| 777 | + target_cpu = cpumask_first(available_mask); | |
| 778 | + cpumask_set_cpu(target_cpu, alloced_mask); | |
| 749 | 779 | |
| 750 | − target_cpu = cpumask_first(available_mask); | |
| 751 | − cpumask_set_cpu(target_cpu, alloced_mask); | |
| 780 | + if (channel->offermsg.offer.sub_channel_index >= ncpu || | |
| 781 | + i > ncpu || !hv_cpuself_used(target_cpu, channel)) | |
| 782 | + break; | |
| 783 | + } | |
| 752 | 784 | |
| 753 | 785 | channel->target_cpu = target_cpu; |
| 754 | 786 | |
| @@ -1224,14 +1224,14 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) · 1223 unmodified lines | ||
| 1224 | 1224 | |
| 1225 | 1225 | disable_irq(iproc_i2c->irq); |
| 1226 | 1226 | |
| 1227 | + tasklet_kill(&iproc_i2c->slave_rx_tasklet); | |
| 1228 | + | |
| 1227 | 1229 | /* disable all slave interrupts */ |
| 1228 | 1230 | tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
| 1229 | 1231 | tmp &= ~(IE_S_ALL_INTERRUPT_MASK << |
| 1230 | 1232 | IE_S_ALL_INTERRUPT_SHIFT); |
| 1231 | 1233 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp); |
| 1232 | 1234 | |
| 1233 | − tasklet_kill(&iproc_i2c->slave_rx_tasklet); | |
| 1234 | − | |
| 1235 | 1235 | /* Erase the slave address programmed */ |
| 1236 | 1236 | tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); |
| 1237 | 1237 | tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); |
| @@ -635,8 +635,8 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) · 634 unmodified lines | ||
| 635 | 635 | |
| 636 | 636 | status = readb(i2c->base + MPC_I2C_SR); |
| 637 | 637 | if (status & CSR_MIF) { |
| 638 | − /* Read again to allow register to stabilise */ | |
| 639 | − status = readb(i2c->base + MPC_I2C_SR); | |
| 638 | + /* Wait up to 100us for transfer to properly complete */ | |
| 639 | + readb_poll_timeout(i2c->base + MPC_I2C_SR, status, !(status & CSR_MCF), 0, 100); | |
| 640 | 640 | writeb(0, i2c->base + MPC_I2C_SR); |
| 641 | 641 | mpc_i2c_do_intr(i2c, status); |
| 642 | 642 | return IRQ_HANDLED; |
| @@ -141,7 +141,7 @@ static ssize_t i2cdev_read(struct file *file, char __user *buf, size_t count, · 140 unmodified lines | ||
| 141 | 141 | if (count > 8192) |
| 142 | 142 | count = 8192; |
| 143 | 143 | |
| 144 | − tmp = kmalloc(count, GFP_KERNEL); | |
| 144 | + tmp = kzalloc(count, GFP_KERNEL); | |
| 145 | 145 | if (tmp == NULL) |
| 146 | 146 | return -ENOMEM; |
| 147 | 147 | |
| @@ -150,7 +150,8 @@ static ssize_t i2cdev_read(struct file *file, char __user *buf, size_t count, · 2 unmodified lines | ||
| 150 | 150 | |
| 151 | 151 | ret = i2c_master_recv(client, tmp, count); |
| 152 | 152 | if (ret >= 0) |
| 153 | − ret = copy_to_user(buf, tmp, count) ? -EFAULT : ret; | |
| 153 | + if (copy_to_user(buf, tmp, ret)) | |
| 154 | + ret = -EFAULT; | |
| 154 | 155 | kfree(tmp); |
| 155 | 156 | return ret; |
| 156 | 157 | } |
| @@ -231,6 +231,7 @@ config DMARD10 · 230 unmodified lines | ||
| 231 | 231 | |
| 232 | 232 | config FXLS8962AF |
| 233 | 233 | tristate |
| 234 | + depends on I2C || !I2C # cannot be built-in for modular I2C | |
| 234 | 235 | |
| 235 | 236 | config FXLS8962AF_I2C |
| 236 | 237 | tristate "NXP FXLS8962AF/FXLS8964AF Accelerometer I2C Driver" |
| @@ -247,6 +248,7 @@ config FXLS8962AF_I2C · 10 unmodified lines | ||
| 247 | 248 | config FXLS8962AF_SPI |
| 248 | 249 | tristate "NXP FXLS8962AF/FXLS8964AF Accelerometer SPI Driver" |
| 249 | 250 | depends on SPI |
| 251 | + depends on I2C || !I2C | |
| 250 | 252 | select FXLS8962AF |
| 251 | 253 | select REGMAP_SPI |
| 252 | 254 | help |
| @@ -637,7 +637,7 @@ static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, · 636 unmodified lines | ||
| 637 | 637 | return ret; |
| 638 | 638 | } |
| 639 | 639 | |
| 640 | − return ret; | |
| 640 | + return 0; | |
| 641 | 641 | } |
| 642 | 642 | |
| 643 | 643 | static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, |
| @@ -664,8 +664,8 @@ static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc) · 663 unmodified lines | ||
| 664 | 664 | |
| 665 | 665 | adc_period = adc->auto_conversion_period; |
| 666 | 666 | for (i = 0; i < 16; ++i) { |
| 667 | − if (((1000 * (1 << i)) / 32) < adc_period) | |
| 668 | − continue; | |
| 667 | + if (((1000 * (1 << i)) / 32) >= adc_period) | |
| 668 | + break; | |
| 669 | 669 | } |
| 670 | 670 | if (i > 0) |
| 671 | 671 | i--; |
| @@ -568,7 +568,6 @@ static int ti_ads7950_probe(struct spi_device *spi) · 567 unmodified lines | ||
| 568 | 568 | st->ring_xfer.tx_buf = &st->tx_buf[0]; |
| 569 | 569 | st->ring_xfer.rx_buf = &st->rx_buf[0]; |
| 570 | 570 | /* len will be set later */ |
| 571 | − st->ring_xfer.cs_change = true; | |
| 572 | 571 | |
| 573 | 572 | spi_message_add_tail(&st->ring_xfer, &st->ring_msg); |
| 574 | 573 | |
| @@ -25,6 +25,8 @@ · 24 unmodified lines | ||
| 25 | 25 | #include <linux/iio/trigger_consumer.h> |
| 26 | 26 | #include <linux/iio/triggered_buffer.h> |
| 27 | 27 | |
| 28 | +#include <linux/time.h> | |
| 29 | + | |
| 28 | 30 | #define HDC100X_REG_TEMP 0x00 |
| 29 | 31 | #define HDC100X_REG_HUMIDITY 0x01 |
| 30 | 32 | |
| @@ -166,7 +168,7 @@ static int hdc100x_get_measurement(struct hdc100x_data *data, · 135 unmodified lines | ||
| 166 | 168 | struct iio_chan_spec const *chan) |
| 167 | 169 | { |
| 168 | 170 | struct i2c_client *client = data->client; |
| 169 | − int delay = data->adc_int_us[chan->address]; | |
| 171 | + int delay = data->adc_int_us[chan->address] + 1*USEC_PER_MSEC; | |
| 170 | 172 | int ret; |
| 171 | 173 | __be16 val; |
| 172 | 174 | |
| @@ -316,7 +318,7 @@ static irqreturn_t hdc100x_trigger_handler(int irq, void *p) · 143 unmodified lines | ||
| 316 | 318 | struct iio_dev *indio_dev = pf->indio_dev; |
| 317 | 319 | struct hdc100x_data *data = iio_priv(indio_dev); |
| 318 | 320 | struct i2c_client *client = data->client; |
| 319 | − int delay = data->adc_int_us[0] + data->adc_int_us[1]; | |
| 321 | + int delay = data->adc_int_us[0] + data->adc_int_us[1] + 2*USEC_PER_MSEC; | |
| 320 | 322 | int ret; |
| 321 | 323 | |
| 322 | 324 | /* dual read starts at temp register */ |
| @@ -411,12 +411,11 @@ int __adis_initial_startup(struct adis *adis) · 410 unmodified lines | ||
| 411 | 411 | int ret; |
| 412 | 412 | |
| 413 | 413 | /* check if the device has rst pin low */ |
| 414 | − gpio = devm_gpiod_get_optional(&adis->spi->dev, "reset", GPIOD_ASIS); | |
| 414 | + gpio = devm_gpiod_get_optional(&adis->spi->dev, "reset", GPIOD_OUT_HIGH); | |
| 415 | 415 | if (IS_ERR(gpio)) |
| 416 | 416 | return PTR_ERR(gpio); |
| 417 | 417 | |
| 418 | 418 | if (gpio) { |
| 419 | − gpiod_set_value_cansleep(gpio, 1); | |
| 420 | 419 | msleep(10); |
| 421 | 420 | /* bring device out of reset */ |
| 422 | 421 | gpiod_set_value_cansleep(gpio, 0); |
| @@ -926,12 +926,25 @@ static int cma_init_ud_qp(struct rdma_id_private *id_priv, struct ib_qp *qp) · 925 unmodified lines | ||
| 926 | 926 | return ret; |
| 927 | 927 | } |
| 928 | 928 | |
| 929 | +static int cma_init_conn_qp(struct rdma_id_private *id_priv, struct ib_qp *qp) | |
| 930 | +{ | |
| 931 | + struct ib_qp_attr qp_attr; | |
| 932 | + int qp_attr_mask, ret; | |
| 933 | + | |
| 934 | + qp_attr.qp_state = IB_QPS_INIT; | |
| 935 | + ret = rdma_init_qp_attr(&id_priv->id, &qp_attr, &qp_attr_mask); | |
| 936 | + if (ret) | |
| 937 | + return ret; | |
| 938 | + | |
| 939 | + return ib_modify_qp(qp, &qp_attr, qp_attr_mask); | |
| 940 | +} | |
| 941 | + | |
| 929 | 942 | int rdma_create_qp(struct rdma_cm_id *id, struct ib_pd *pd, |
| 930 | 943 | struct ib_qp_init_attr *qp_init_attr) |
| 931 | 944 | { |
| 932 | 945 | struct rdma_id_private *id_priv; |
| 933 | 946 | struct ib_qp *qp; |
| 934 | − int ret = 0; | |
| 947 | + int ret; | |
| 935 | 948 | |
| 936 | 949 | id_priv = container_of(id, struct rdma_id_private, id); |
| 937 | 950 | if (id->device != pd->device) { |
| @@ -948,6 +961,8 @@ int rdma_create_qp(struct rdma_cm_id *id, struct ib_pd *pd, · 10 unmodified lines | ||
| 948 | 961 | |
| 949 | 962 | if (id->qp_type == IB_QPT_UD) |
| 950 | 963 | ret = cma_init_ud_qp(id_priv, qp); |
| 964 | + else | |
| 965 | + ret = cma_init_conn_qp(id_priv, qp); | |
| 951 | 966 | if (ret) |
| 952 | 967 | goto out_destroy; |
| 953 | 968 | |
| @@ -120,6 +120,7 @@ static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) · 119 unmodified lines | ||
| 120 | 120 | if (!chip_ctx) |
| 121 | 121 | return -ENOMEM; |
| 122 | 122 | chip_ctx->chip_num = bp->chip_num; |
| 123 | + chip_ctx->hw_stats_size = bp->hw_ring_stats_size; | |
| 123 | 124 | |
| 124 | 125 | rdev->chip_ctx = chip_ctx; |
| 125 | 126 | /* rest members to follow eventually */ |
| @@ -550,6 +551,7 @@ static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, · 424 unmodified lines | ||
| 550 | 551 | dma_addr_t dma_map, |
| 551 | 552 | u32 *fw_stats_ctx_id) |
| 552 | 553 | { |
| 554 | + struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; | |
| 553 | 555 | struct hwrm_stat_ctx_alloc_output resp = {0}; |
| 554 | 556 | struct hwrm_stat_ctx_alloc_input req = {0}; |
| 555 | 557 | struct bnxt_en_dev *en_dev = rdev->en_dev; |
| @@ -566,7 +568,7 @@ static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, · 10 unmodified lines | ||
| 566 | 568 | bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_STAT_CTX_ALLOC, -1, -1); |
| 567 | 569 | req.update_period_ms = cpu_to_le32(1000); |
| 568 | 570 | req.stats_dma_addr = cpu_to_le64(dma_map); |
| 569 | − req.stats_dma_length = cpu_to_le16(sizeof(struct ctx_hw_stats_ext)); | |
| 571 | + req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); | |
| 570 | 572 | req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; |
| 571 | 573 | bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, |
| 572 | 574 | sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); |
| @@ -56,6 +56,7 @@ · 55 unmodified lines | ||
| 56 | 56 | static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev, |
| 57 | 57 | struct bnxt_qplib_stats *stats); |
| 58 | 58 | static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev, |
| 59 | + struct bnxt_qplib_chip_ctx *cctx, | |
| 59 | 60 | struct bnxt_qplib_stats *stats); |
| 60 | 61 | |
| 61 | 62 | /* PBL */ |
| @@ -559,7 +560,7 @@ int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, · 497 unmodified lines | ||
| 559 | 560 | goto fail; |
| 560 | 561 | stats_alloc: |
| 561 | 562 | /* Stats */ |
| 562 | − rc = bnxt_qplib_alloc_stats_ctx(res->pdev, &ctx->stats); | |
| 563 | + rc = bnxt_qplib_alloc_stats_ctx(res->pdev, res->cctx, &ctx->stats); | |
| 563 | 564 | if (rc) |
| 564 | 565 | goto fail; |
| 565 | 566 | |
| @@ -889,15 +890,12 @@ static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev, · 323 unmodified lines | ||
| 889 | 890 | } |
| 890 | 891 | |
| 891 | 892 | static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev, |
| 893 | + struct bnxt_qplib_chip_ctx *cctx, | |
| 892 | 894 | struct bnxt_qplib_stats *stats) |
| 893 | 895 | { |
| 894 | 896 | memset(stats, 0, sizeof(*stats)); |
| 895 | 897 | stats->fw_id = -1; |
| 896 | − /* 128 byte aligned context memory is required only for 57500. | |
| 897 | − * However making this unconditional, it does not harm previous | |
| 898 | − * generation. | |
| 899 | − */ | |
| 900 | − stats->size = ALIGN(sizeof(struct ctx_hw_stats), 128); | |
| 898 | + stats->size = cctx->hw_stats_size; | |
| 901 | 899 | stats->dma = dma_alloc_coherent(&pdev->dev, stats->size, |
| 902 | 900 | &stats->dma_map, GFP_KERNEL); |
| 903 | 901 | if (!stats->dma) { |
| @@ -54,6 +54,7 @@ struct bnxt_qplib_chip_ctx { · 53 unmodified lines | ||
| 54 | 54 | u16 chip_num; |
| 55 | 55 | u8 chip_rev; |
| 56 | 56 | u8 chip_metal; |
| 57 | + u16 hw_stats_size; | |
| 57 | 58 | struct bnxt_qplib_drv_modes modes; |
| 58 | 59 | }; |
| 59 | 60 | |
| @@ -967,6 +967,12 @@ int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) · 966 unmodified lines | ||
| 967 | 967 | return !err || err == -ENODATA ? npolled : err; |
| 968 | 968 | } |
| 969 | 969 | |
| 970 | +void c4iw_cq_rem_ref(struct c4iw_cq *chp) | |
| 971 | +{ | |
| 972 | + if (refcount_dec_and_test(&chp->refcnt)) | |
| 973 | + complete(&chp->cq_rel_comp); | |
| 974 | +} | |
| 975 | + | |
| 970 | 976 | int c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) |
| 971 | 977 | { |
| 972 | 978 | struct c4iw_cq *chp; |
| @@ -976,8 +982,8 @@ int c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) · 3 unmodified lines | ||
| 976 | 982 | chp = to_c4iw_cq(ib_cq); |
| 977 | 983 | |
| 978 | 984 | xa_erase_irq(&chp->rhp->cqs, chp->cq.cqid); |
| 979 | − refcount_dec(&chp->refcnt); | |
| 980 | − wait_event(chp->wait, !refcount_read(&chp->refcnt)); | |
| 985 | + c4iw_cq_rem_ref(chp); | |
| 986 | + wait_for_completion(&chp->cq_rel_comp); | |
| 981 | 987 | |
| 982 | 988 | ucontext = rdma_udata_to_drv_context(udata, struct c4iw_ucontext, |
| 983 | 989 | ibucontext); |
| @@ -1081,7 +1087,7 @@ int c4iw_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, · 97 unmodified lines | ||
| 1081 | 1087 | spin_lock_init(&chp->lock); |
| 1082 | 1088 | spin_lock_init(&chp->comp_handler_lock); |
| 1083 | 1089 | refcount_set(&chp->refcnt, 1); |
| 1084 | − init_waitqueue_head(&chp->wait); | |
| 1090 | + init_completion(&chp->cq_rel_comp); | |
| 1085 | 1091 | ret = xa_insert_irq(&rhp->cqs, chp->cq.cqid, chp, GFP_KERNEL); |
| 1086 | 1092 | if (ret) |
| 1087 | 1093 | goto err_destroy_cq; |
| @@ -213,8 +213,7 @@ void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe) · 212 unmodified lines | ||
| 213 | 213 | break; |
| 214 | 214 | } |
| 215 | 215 | done: |
| 216 | − if (refcount_dec_and_test(&chp->refcnt)) | |
| 217 | − wake_up(&chp->wait); | |
| 216 | + c4iw_cq_rem_ref(chp); | |
| 218 | 217 | c4iw_qp_rem_ref(&qhp->ibqp); |
| 219 | 218 | out: |
| 220 | 219 | return; |
| @@ -234,8 +233,7 @@ int c4iw_ev_handler(struct c4iw_dev *dev, u32 qid) · 13 unmodified lines | ||
| 234 | 233 | spin_lock_irqsave(&chp->comp_handler_lock, flag); |
| 235 | 234 | (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context); |
| 236 | 235 | spin_unlock_irqrestore(&chp->comp_handler_lock, flag); |
| 237 | − if (refcount_dec_and_test(&chp->refcnt)) | |
| 238 | − wake_up(&chp->wait); | |
| 236 | + c4iw_cq_rem_ref(chp); | |
| 239 | 237 | } else { |
| 240 | 238 | pr_debug("unknown cqid 0x%x\n", qid); |
| 241 | 239 | xa_unlock_irqrestore(&dev->cqs, flag); |
| @@ -428,7 +428,7 @@ struct c4iw_cq { · 427 unmodified lines | ||
| 428 | 428 | spinlock_t lock; |
| 429 | 429 | spinlock_t comp_handler_lock; |
| 430 | 430 | refcount_t refcnt; |
| 431 | − wait_queue_head_t wait; | |
| 431 | + struct completion cq_rel_comp; | |
| 432 | 432 | struct c4iw_wr_wait *wr_waitp; |
| 433 | 433 | }; |
| 434 | 434 | |
| @@ -979,6 +979,7 @@ struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, · 544 unmodified lines | ||
| 979 | 979 | struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); |
| 980 | 980 | int c4iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata); |
| 981 | 981 | int c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); |
| 982 | +void c4iw_cq_rem_ref(struct c4iw_cq *chp); | |
| 982 | 983 | int c4iw_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, |
| 983 | 984 | struct ib_udata *udata); |
| 984 | 985 | int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); |
| @@ -213,8 +213,10 @@ int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev) · 212 unmodified lines | ||
| 213 | 213 | |
| 214 | 214 | hr_cmd->context = |
| 215 | 215 | kcalloc(hr_cmd->max_cmds, sizeof(*hr_cmd->context), GFP_KERNEL); |
| 216 | − if (!hr_cmd->context) | |
| 216 | + if (!hr_cmd->context) { | |
| 217 | + hr_dev->cmd_mod = 0; | |
| 217 | 218 | return -ENOMEM; |
| 219 | + } | |
| 218 | 220 | |
| 219 | 221 | for (i = 0; i < hr_cmd->max_cmds; ++i) { |
| 220 | 222 | hr_cmd->context[i].token = i; |
| @@ -228,7 +230,6 @@ int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev) · 7 unmodified lines | ||
| 228 | 230 | spin_lock_init(&hr_cmd->context_lock); |
| 229 | 231 | |
| 230 | 232 | hr_cmd->use_events = 1; |
| 231 | − down(&hr_cmd->poll_sem); | |
| 232 | 233 | |
| 233 | 234 | return 0; |
| 234 | 235 | } |
| @@ -239,8 +240,6 @@ void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev) · 4 unmodified lines | ||
| 239 | 240 | |
| 240 | 241 | kfree(hr_cmd->context); |
| 241 | 242 | hr_cmd->use_events = 0; |
| 242 | − | |
| 243 | − up(&hr_cmd->poll_sem); | |
| 244 | 243 | } |
| 245 | 244 | |
| 246 | 245 | struct hns_roce_cmd_mailbox * |
| @@ -873,11 +873,9 @@ int hns_roce_init(struct hns_roce_dev *hr_dev) · 872 unmodified lines | ||
| 873 | 873 | |
| 874 | 874 | if (hr_dev->cmd_mod) { |
| 875 | 875 | ret = hns_roce_cmd_use_events(hr_dev); |
| 876 | − if (ret) { | |
| 876 | + if (ret) | |
| 877 | 877 | dev_warn(dev, |
| 878 | 878 | "Cmd event mode failed, set back to poll!\n"); |
| 879 | − hns_roce_cmd_use_polling(hr_dev); | |
| 880 | − } | |
| 881 | 879 | } |
| 882 | 880 | |
| 883 | 881 | ret = hns_roce_init_hem(hr_dev); |
| @@ -2845,7 +2845,7 @@ static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf, · 2844 unmodified lines | ||
| 2845 | 2845 | * parses fpm commit info and copy base value |
| 2846 | 2846 | * of hmc objects in hmc_info |
| 2847 | 2847 | */ |
| 2848 | −static enum irdma_status_code | |
| 2848 | +static void | |
| 2849 | 2849 | irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, |
| 2850 | 2850 | struct irdma_hmc_obj_info *info, u32 *sd) |
| 2851 | 2851 | { |
| @@ -2915,7 +2915,6 @@ irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, · 63 unmodified lines | ||
| 2915 | 2915 | else |
| 2916 | 2916 | *sd = (u32)(size >> 21); |
| 2917 | 2917 | |
| 2918 | − return 0; | |
| 2919 | 2918 | } |
| 2920 | 2919 | |
| 2921 | 2920 | /** |
| @@ -4187,11 +4186,9 @@ enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, · 1265 unmodified lines | ||
| 4187 | 4186 | * @dev: sc device struct |
| 4188 | 4187 | * @count: allocate count |
| 4189 | 4188 | */ |
| 4190 | −enum irdma_status_code irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) | |
| 4189 | +void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) | |
| 4191 | 4190 | { |
| 4192 | 4191 | writel(count, dev->hw_regs[IRDMA_AEQALLOC]); |
| 4193 | − | |
| 4194 | − return 0; | |
| 4195 | 4192 | } |
| 4196 | 4193 | |
| 4197 | 4194 | /** |
| @@ -4434,9 +4431,9 @@ static enum irdma_status_code irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, · 236 unmodified lines | ||
| 4434 | 4431 | ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, |
| 4435 | 4432 | &commit_fpm_mem, true, wait_type); |
| 4436 | 4433 | if (!ret_code) |
| 4437 | − ret_code = irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, | |
| 4438 | − hmc_info->hmc_obj, | |
| 4439 | − &hmc_info->sd_table.sd_cnt); | |
| 4434 | + irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, | |
| 4435 | + hmc_info->hmc_obj, | |
| 4436 | + &hmc_info->sd_table.sd_cnt); | |
| 4440 | 4437 | print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, |
| 4441 | 4438 | 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, |
| 4442 | 4439 | false); |
| @@ -1920,7 +1920,7 @@ enum irdma_status_code irdma_ctrl_init_hw(struct irdma_pci_f *rf) · 1919 unmodified lines | ||
| 1920 | 1920 | * irdma_set_hw_rsrc - set hw memory resources. |
| 1921 | 1921 | * @rf: RDMA PCI function |
| 1922 | 1922 | */ |
| 1923 | −static u32 irdma_set_hw_rsrc(struct irdma_pci_f *rf) | |
| 1923 | +static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) | |
| 1924 | 1924 | { |
| 1925 | 1925 | rf->allocated_qps = (void *)(rf->mem_rsrc + |
| 1926 | 1926 | (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); |
| @@ -1937,8 +1937,6 @@ static u32 irdma_set_hw_rsrc(struct irdma_pci_f *rf) · 10 unmodified lines | ||
| 1937 | 1937 | spin_lock_init(&rf->arp_lock); |
| 1938 | 1938 | spin_lock_init(&rf->qptable_lock); |
| 1939 | 1939 | spin_lock_init(&rf->qh_list_lock); |
| 1940 | − | |
| 1941 | − return 0; | |
| 1942 | 1940 | } |
| 1943 | 1941 | |
| 1944 | 1942 | /** |
| @@ -2000,9 +1998,7 @@ u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) · 55 unmodified lines | ||
| 2000 | 1998 | |
| 2001 | 1999 | rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; |
| 2002 | 2000 | |
| 2003 | − ret = irdma_set_hw_rsrc(rf); | |
| 2004 | − if (ret) | |
| 2005 | − goto set_hw_rsrc_fail; | |
| 2001 | + irdma_set_hw_rsrc(rf); | |
| 2006 | 2002 | |
| 2007 | 2003 | set_bit(0, rf->allocated_mrs); |
| 2008 | 2004 | set_bit(0, rf->allocated_qps); |
| @@ -2025,9 +2021,6 @@ u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) · 16 unmodified lines | ||
| 2025 | 2021 | |
| 2026 | 2022 | return 0; |
| 2027 | 2023 | |
| 2028 | −set_hw_rsrc_fail: | |
| 2029 | − kfree(rf->mem_rsrc); | |
| 2030 | − rf->mem_rsrc = NULL; | |
| 2031 | 2024 | mem_rsrc_kzalloc_fail: |
| 2032 | 2025 | kfree(rf->allocated_ws_nodes); |
| 2033 | 2026 | rf->allocated_ws_nodes = NULL; |
| @@ -215,10 +215,10 @@ static void irdma_remove(struct auxiliary_device *aux_dev) · 214 unmodified lines | ||
| 215 | 215 | pr_debug("INIT: Gen2 PF[%d] device remove success\n", PCI_FUNC(pf->pdev->devfn)); |
| 216 | 216 | } |
| 217 | 217 | |
| 218 | −static void irdma_fill_device_info(struct irdma_device *iwdev, struct ice_pf *pf) | |
| 218 | +static void irdma_fill_device_info(struct irdma_device *iwdev, struct ice_pf *pf, | |
| 219 | + struct ice_vsi *vsi) | |
| 219 | 220 | { |
| 220 | 221 | struct irdma_pci_f *rf = iwdev->rf; |
| 221 | − struct ice_vsi *vsi = ice_get_main_vsi(pf); | |
| 222 | 222 | |
| 223 | 223 | rf->cdev = pf; |
| 224 | 224 | rf->gen_ops.register_qset = irdma_lan_register_qset; |
| @@ -253,12 +253,15 @@ static int irdma_probe(struct auxiliary_device *aux_dev, const struct auxiliary_ · 28 unmodified lines | ||
| 253 | 253 | struct iidc_auxiliary_dev, |
| 254 | 254 | adev); |
| 255 | 255 | struct ice_pf *pf = iidc_adev->pf; |
| 256 | + struct ice_vsi *vsi = ice_get_main_vsi(pf); | |
| 256 | 257 | struct iidc_qos_params qos_info = {}; |
| 257 | 258 | struct irdma_device *iwdev; |
| 258 | 259 | struct irdma_pci_f *rf; |
| 259 | 260 | struct irdma_l2params l2params = {}; |
| 260 | 261 | int err; |
| 261 | 262 | |
| 263 | + if (!vsi) | |
| 264 | + return -EIO; | |
| 262 | 265 | iwdev = ib_alloc_device(irdma_device, ibdev); |
| 263 | 266 | if (!iwdev) |
| 264 | 267 | return -ENOMEM; |
| @@ -268,7 +271,7 @@ static int irdma_probe(struct auxiliary_device *aux_dev, const struct auxiliary_ · 3 unmodified lines | ||
| 268 | 271 | return -ENOMEM; |
| 269 | 272 | } |
| 270 | 273 | |
| 271 | − irdma_fill_device_info(iwdev, pf); | |
| 274 | + irdma_fill_device_info(iwdev, pf, vsi); | |
| 272 | 275 | rf = iwdev->rf; |
| 273 | 276 | |
| 274 | 277 | if (irdma_ctrl_init_hw(rf)) { |
| @@ -1222,8 +1222,7 @@ enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, · 1221 unmodified lines | ||
| 1222 | 1222 | struct irdma_aeq_init_info *info); |
| 1223 | 1223 | enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, |
| 1224 | 1224 | struct irdma_aeqe_info *info); |
| 1225 | −enum irdma_status_code irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, | |
| 1226 | − u32 count); | |
| 1225 | +void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count); | |
| 1227 | 1226 | |
| 1228 | 1227 | void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, |
| 1229 | 1228 | int abi_ver); |
| @@ -931,7 +931,7 @@ enum irdma_status_code irdma_uk_mw_bind(struct irdma_qp_uk *qp, · 930 unmodified lines | ||
| 931 | 931 | enum irdma_status_code irdma_uk_post_receive(struct irdma_qp_uk *qp, |
| 932 | 932 | struct irdma_post_rq_info *info) |
| 933 | 933 | { |
| 934 | − u32 total_size = 0, wqe_idx, i, byte_off; | |
| 934 | + u32 wqe_idx, i, byte_off; | |
| 935 | 935 | u32 addl_frag_cnt; |
| 936 | 936 | __le64 *wqe; |
| 937 | 937 | u64 hdr; |
| @@ -939,9 +939,6 @@ enum irdma_status_code irdma_uk_post_receive(struct irdma_qp_uk *qp, · 1 unmodified line | ||
| 939 | 939 | if (qp->max_rq_frag_cnt < info->num_sges) |
| 940 | 940 | return IRDMA_ERR_INVALID_FRAG_COUNT; |
| 941 | 941 | |
| 942 | − for (i = 0; i < info->num_sges; i++) | |
| 943 | − total_size += info->sg_list[i].len; | |
| 944 | − | |
| 945 | 942 | wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx); |
| 946 | 943 | if (!wqe) |
| 947 | 944 | return IRDMA_ERR_QP_TOOMANY_WRS_POSTED; |
| @@ -557,7 +557,7 @@ static int irdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) · 556 unmodified lines | ||
| 557 | 557 | * @iwqp: qp ptr |
| 558 | 558 | * @init_info: initialize info to return |
| 559 | 559 | */ |
| 560 | −static int irdma_setup_virt_qp(struct irdma_device *iwdev, | |
| 560 | +static void irdma_setup_virt_qp(struct irdma_device *iwdev, | |
| 561 | 561 | struct irdma_qp *iwqp, |
| 562 | 562 | struct irdma_qp_init_info *init_info) |
| 563 | 563 | { |
| @@ -574,8 +574,6 @@ static int irdma_setup_virt_qp(struct irdma_device *iwdev, · 10 unmodified lines | ||
| 574 | 574 | init_info->sq_pa = qpmr->sq_pbl.addr; |
| 575 | 575 | init_info->rq_pa = qpmr->rq_pbl.addr; |
| 576 | 576 | } |
| 577 | − | |
| 578 | − return 0; | |
| 579 | 577 | } |
| 580 | 578 | |
| 581 | 579 | /** |
| @@ -914,7 +912,7 @@ static struct ib_qp *irdma_create_qp(struct ib_pd *ibpd, · 332 unmodified lines | ||
| 914 | 912 | } |
| 915 | 913 | } |
| 916 | 914 | init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver; |
| 917 | − err_code = irdma_setup_virt_qp(iwdev, iwqp, &init_info); | |
| 915 | + irdma_setup_virt_qp(iwdev, iwqp, &init_info); | |
| 918 | 916 | } else { |
| 919 | 917 | init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER; |
| 920 | 918 | err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr); |
| @@ -945,7 +945,6 @@ int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, · 944 unmodified lines | ||
| 945 | 945 | u32 *cqb = NULL; |
| 946 | 946 | void *cqc; |
| 947 | 947 | int cqe_size; |
| 948 | − unsigned int irqn; | |
| 949 | 948 | int eqn; |
| 950 | 949 | int err; |
| 951 | 950 | |
| @@ -984,7 +983,7 @@ int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, · 32 unmodified lines | ||
| 984 | 983 | INIT_WORK(&cq->notify_work, notify_soft_wc_handler); |
| 985 | 984 | } |
| 986 | 985 | |
| 987 | − err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn); | |
| 986 | + err = mlx5_vector2eqn(dev->mdev, vector, &eqn); | |
| 988 | 987 | if (err) |
| 989 | 988 | goto err_cqb; |
| 990 | 989 | |
| @@ -1007,7 +1006,6 @@ int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, · 16 unmodified lines | ||
| 1007 | 1006 | goto err_cqb; |
| 1008 | 1007 | |
| 1009 | 1008 | mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); |
| 1010 | − cq->mcq.irqn = irqn; | |
| 1011 | 1009 | if (udata) |
| 1012 | 1010 | cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp; |
| 1013 | 1011 | else |
| @@ -975,7 +975,6 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)( · 974 unmodified lines | ||
| 975 | 975 | struct mlx5_ib_dev *dev; |
| 976 | 976 | int user_vector; |
| 977 | 977 | int dev_eqn; |
| 978 | − unsigned int irqn; | |
| 979 | 978 | int err; |
| 980 | 979 | |
| 981 | 980 | if (uverbs_copy_from(&user_vector, attrs, |
| @@ -987,7 +986,7 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)( · 5 unmodified lines | ||
| 987 | 986 | return PTR_ERR(c); |
| 988 | 987 | dev = to_mdev(c->ibucontext.device); |
| 989 | 988 | |
| 990 | − err = mlx5_vector2eqn(dev->mdev, user_vector, &dev_eqn, &irqn); | |
| 989 | + err = mlx5_vector2eqn(dev->mdev, user_vector, &dev_eqn); | |
| 991 | 990 | if (err < 0) |
| 992 | 991 | return err; |
| 993 | 992 | |
| @@ -531,8 +531,8 @@ static void __cache_work_func(struct mlx5_cache_ent *ent) · 530 unmodified lines | ||
| 531 | 531 | */ |
| 532 | 532 | spin_unlock_irq(&ent->lock); |
| 533 | 533 | need_delay = need_resched() || someone_adding(cache) || |
| 534 | − time_after(jiffies, | |
| 535 | − READ_ONCE(cache->last_add) + 300 * HZ); | |
| 534 | + !time_after(jiffies, | |
| 535 | + READ_ONCE(cache->last_add) + 300 * HZ); | |
| 536 | 536 | spin_lock_irq(&ent->lock); |
| 537 | 537 | if (ent->disabled) |
| 538 | 538 | goto out; |
| @@ -113,13 +113,14 @@ int rxe_mr_init_user(struct rxe_pd *pd, u64 start, u64 length, u64 iova, · 112 unmodified lines | ||
| 113 | 113 | int num_buf; |
| 114 | 114 | void *vaddr; |
| 115 | 115 | int err; |
| 116 | + int i; | |
| 116 | 117 | |
| 117 | 118 | umem = ib_umem_get(pd->ibpd.device, start, length, access); |
| 118 | 119 | if (IS_ERR(umem)) { |
| 119 | − pr_warn("err %d from rxe_umem_get\n", | |
| 120 | − (int)PTR_ERR(umem)); | |
| 120 | + pr_warn("%s: Unable to pin memory region err = %d\n", | |
| 121 | + __func__, (int)PTR_ERR(umem)); | |
| 121 | 122 | err = PTR_ERR(umem); |
| 122 | − goto err1; | |
| 123 | + goto err_out; | |
| 123 | 124 | } |
| 124 | 125 | |
| 125 | 126 | mr->umem = umem; |
| @@ -129,9 +130,9 @@ int rxe_mr_init_user(struct rxe_pd *pd, u64 start, u64 length, u64 iova, · 3 unmodified lines | ||
| 129 | 130 | |
| 130 | 131 | err = rxe_mr_alloc(mr, num_buf); |
| 131 | 132 | if (err) { |
| 132 | − pr_warn("err %d from rxe_mr_alloc\n", err); | |
| 133 | − ib_umem_release(umem); | |
| 134 | − goto err1; | |
| 133 | + pr_warn("%s: Unable to allocate memory for map\n", | |
| 134 | + __func__); | |
| 135 | + goto err_release_umem; | |
| 135 | 136 | } |
| 136 | 137 | |
| 137 | 138 | mr->page_shift = PAGE_SHIFT; |
| @@ -151,10 +152,10 @@ int rxe_mr_init_user(struct rxe_pd *pd, u64 start, u64 length, u64 iova, · 13 unmodified lines | ||
| 151 | 152 | |
| 152 | 153 | vaddr = page_address(sg_page_iter_page(&sg_iter)); |
| 153 | 154 | if (!vaddr) { |
| 154 | − pr_warn("null vaddr\n"); | |
| 155 | − ib_umem_release(umem); | |
| 155 | + pr_warn("%s: Unable to get virtual address\n", | |
| 156 | + __func__); | |
| 156 | 157 | err = -ENOMEM; |
| 157 | − goto err1; | |
| 158 | + goto err_cleanup_map; | |
| 158 | 159 | } |
| 159 | 160 | |
| 160 | 161 | buf->addr = (uintptr_t)vaddr; |
| @@ -177,7 +178,13 @@ int rxe_mr_init_user(struct rxe_pd *pd, u64 start, u64 length, u64 iova, · 16 unmodified lines | ||
| 177 | 178 | |
| 178 | 179 | return 0; |
| 179 | 180 | |
| 180 | −err1: | |
| 181 | +err_cleanup_map: | |
| 182 | + for (i = 0; i < mr->num_map; i++) | |
| 183 | + kfree(mr->map[i]); | |
| 184 | + kfree(mr->map); | |
| 185 | +err_release_umem: | |
| 186 | + ib_umem_release(umem); | |
| 187 | +err_out: | |
| 181 | 188 | return err; |
| 182 | 189 | } |
| 183 | 190 | |
| @@ -259,6 +259,7 @@ static void prepare_ipv4_hdr(struct dst_entry *dst, struct sk_buff *skb, · 258 unmodified lines | ||
| 259 | 259 | |
| 260 | 260 | iph->version = IPVERSION; |
| 261 | 261 | iph->ihl = sizeof(struct iphdr) >> 2; |
| 262 | + iph->tot_len = htons(skb->len); | |
| 262 | 263 | iph->frag_off = df; |
| 263 | 264 | iph->protocol = proto; |
| 264 | 265 | iph->tos = tos; |
| @@ -318,7 +318,7 @@ static enum resp_states get_srq_wqe(struct rxe_qp *qp) · 317 unmodified lines | ||
| 318 | 318 | pr_warn("%s: invalid num_sge in SRQ entry\n", __func__); |
| 319 | 319 | return RESPST_ERR_MALFORMED_WQE; |
| 320 | 320 | } |
| 321 | − size = sizeof(wqe) + wqe->dma.num_sge*sizeof(struct rxe_sge); | |
| 321 | + size = sizeof(*wqe) + wqe->dma.num_sge*sizeof(struct rxe_sge); | |
| 322 | 322 | memcpy(&qp->resp.srq_wqe, wqe, size); |
| 323 | 323 | |
| 324 | 324 | qp->resp.wqe = &qp->resp.srq_wqe.wqe; |
| @@ -403,7 +403,7 @@ struct icc_path *devm_of_icc_get(struct device *dev, const char *name) · 402 unmodified lines | ||
| 403 | 403 | { |
| 404 | 404 | struct icc_path **ptr, *path; |
| 405 | 405 | |
| 406 | − ptr = devres_alloc(devm_icc_release, sizeof(**ptr), GFP_KERNEL); | |
| 406 | + ptr = devres_alloc(devm_icc_release, sizeof(*ptr), GFP_KERNEL); | |
| 407 | 407 | if (!ptr) |
| 408 | 408 | return ERR_PTR(-ENOMEM); |
| 409 | 409 | |
| @@ -973,9 +973,14 @@ void icc_node_add(struct icc_node *node, struct icc_provider *provider) · 563 unmodified lines | ||
| 973 | 973 | } |
| 974 | 974 | node->avg_bw = node->init_avg; |
| 975 | 975 | node->peak_bw = node->init_peak; |
| 976 | + | |
| 977 | + if (provider->pre_aggregate) | |
| 978 | + provider->pre_aggregate(node); | |
| 979 | + | |
| 976 | 980 | if (provider->aggregate) |
| 977 | 981 | provider->aggregate(node, 0, node->init_avg, node->init_peak, |
| 978 | 982 | &node->avg_bw, &node->peak_bw); |
| 983 | + | |
| 979 | 984 | provider->set(node, node); |
| 980 | 985 | node->avg_bw = 0; |
| 981 | 986 | node->peak_bw = 0; |
| @@ -1106,6 +1111,8 @@ void icc_sync_state(struct device *dev) · 124 unmodified lines | ||
| 1106 | 1111 | dev_dbg(p->dev, "interconnect provider is in synced state\n"); |
| 1107 | 1112 | list_for_each_entry(n, &p->nodes, node_list) { |
| 1108 | 1113 | if (n->init_avg || n->init_peak) { |
| 1114 | + n->init_avg = 0; | |
| 1115 | + n->init_peak = 0; | |
| 1109 | 1116 | aggregate_requests(n); |
| 1110 | 1117 | p->set(n, n); |
| 1111 | 1118 | } |
| @@ -57,6 +57,11 @@ int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, · 56 unmodified lines | ||
| 57 | 57 | qn->sum_avg[i] += avg_bw; |
| 58 | 58 | qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw); |
| 59 | 59 | } |
| 60 | + | |
| 61 | + if (node->init_avg || node->init_peak) { | |
| 62 | + qn->sum_avg[i] = max_t(u64, qn->sum_avg[i], node->init_avg); | |
| 63 | + qn->max_peak[i] = max_t(u64, qn->max_peak[i], node->init_peak); | |
| 64 | + } | |
| 60 | 65 | } |
| 61 | 66 | |
| 62 | 67 | *agg_avg += avg_bw; |
| @@ -79,7 +84,6 @@ EXPORT_SYMBOL_GPL(qcom_icc_aggregate); · 16 unmodified lines | ||
| 79 | 84 | int qcom_icc_set(struct icc_node *src, struct icc_node *dst) |
| 80 | 85 | { |
| 81 | 86 | struct qcom_icc_provider *qp; |
| 82 | − struct qcom_icc_node *qn; | |
| 83 | 87 | struct icc_node *node; |
| 84 | 88 | |
| 85 | 89 | if (!src) |
| @@ -88,12 +92,6 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst) · 2 unmodified lines | ||
| 88 | 92 | node = src; |
| 89 | 93 | |
| 90 | 94 | qp = to_qcom_provider(node->provider); |
| 91 | − qn = node->data; | |
| 92 | − | |
| 93 | − qn->sum_avg[QCOM_ICC_BUCKET_AMC] = max_t(u64, qn->sum_avg[QCOM_ICC_BUCKET_AMC], | |
| 94 | − node->avg_bw); | |
| 95 | − qn->max_peak[QCOM_ICC_BUCKET_AMC] = max_t(u64, qn->max_peak[QCOM_ICC_BUCKET_AMC], | |
| 96 | − node->peak_bw); | |
| 97 | 95 | |
| 98 | 96 | qcom_icc_bcm_voter_commit(qp->voter); |
| 99 | 97 | |
| @@ -379,6 +379,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) · 378 unmodified lines | ||
| 379 | 379 | switch (idx) { |
| 380 | 380 | case CMDQ_ERR_CERROR_ABT_IDX: |
| 381 | 381 | dev_err(smmu->dev, "retrying command fetch\n"); |
| 382 | + return; | |
| 382 | 383 | case CMDQ_ERR_CERROR_NONE_IDX: |
| 383 | 384 | return; |
| 384 | 385 | case CMDQ_ERR_CERROR_ATC_INV_IDX: |
| @@ -849,12 +849,10 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) · 848 unmodified lines | ||
| 849 | 849 | ret = iommu_device_register(&qcom_iommu->iommu, &qcom_iommu_ops, dev); |
| 850 | 850 | if (ret) { |
| 851 | 851 | dev_err(dev, "Failed to register iommu\n"); |
| 852 | − goto err_sysfs_remove; | |
| 852 | + return ret; | |
| 853 | 853 | } |
| 854 | 854 | |
| 855 | − ret = bus_set_iommu(&platform_bus_type, &qcom_iommu_ops); | |
| 856 | − if (ret) | |
| 857 | − goto err_unregister_device; | |
| 855 | + bus_set_iommu(&platform_bus_type, &qcom_iommu_ops); | |
| 858 | 856 | |
| 859 | 857 | if (qcom_iommu->local_base) { |
| 860 | 858 | pm_runtime_get_sync(dev); |
| @@ -863,13 +861,6 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) · 2 unmodified lines | ||
| 863 | 861 | } |
| 864 | 862 | |
| 865 | 863 | return 0; |
| 866 | − | |
| 867 | −err_unregister_device: | |
| 868 | − iommu_device_unregister(&qcom_iommu->iommu); | |
| 869 | − | |
| 870 | −err_sysfs_remove: | |
| 871 | − iommu_device_sysfs_remove(&qcom_iommu->iommu); | |
| 872 | − return ret; | |
| 873 | 864 | } |
| 874 | 865 | |
| 875 | 866 | static int qcom_iommu_device_remove(struct platform_device *pdev) |
| @@ -768,6 +768,7 @@ static void iommu_dma_free_noncontiguous(struct device *dev, size_t size, · 767 unmodified lines | ||
| 768 | 768 | __iommu_dma_unmap(dev, sgt->sgl->dma_address, size); |
| 769 | 769 | __iommu_dma_free_pages(sh->pages, PAGE_ALIGN(size) >> PAGE_SHIFT); |
| 770 | 770 | sg_free_table(&sh->sgt); |
| 771 | + kfree(sh); | |
| 771 | 772 | } |
| 772 | 773 | #endif /* CONFIG_DMA_REMAP */ |
| 773 | 774 | |
| @@ -2429,10 +2429,11 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, · 2428 unmodified lines | ||
| 2429 | 2429 | return 0; |
| 2430 | 2430 | } |
| 2431 | 2431 | |
| 2432 | −static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
| 2432 | +static void domain_context_clear_one(struct device_domain_info *info, u8 bus, u8 devfn) | |
| 2433 | 2433 | { |
| 2434 | − unsigned long flags; | |
| 2434 | + struct intel_iommu *iommu = info->iommu; | |
| 2435 | 2435 | struct context_entry *context; |
| 2436 | + unsigned long flags; | |
| 2436 | 2437 | u16 did_old; |
| 2437 | 2438 | |
| 2438 | 2439 | if (!iommu) |
| @@ -2444,7 +2445,16 @@ static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn · 5 unmodified lines | ||
| 2444 | 2445 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 2445 | 2446 | return; |
| 2446 | 2447 | } |
| 2447 | − did_old = context_domain_id(context); | |
| 2448 | + | |
| 2449 | + if (sm_supported(iommu)) { | |
| 2450 | + if (hw_pass_through && domain_type_is_si(info->domain)) | |
| 2451 | + did_old = FLPT_DEFAULT_DID; | |
| 2452 | + else | |
| 2453 | + did_old = info->domain->iommu_did[iommu->seq_id]; | |
| 2454 | + } else { | |
| 2455 | + did_old = context_domain_id(context); | |
| 2456 | + } | |
| 2457 | + | |
| 2448 | 2458 | context_clear_entry(context); |
| 2449 | 2459 | __iommu_flush_cache(iommu, context, sizeof(*context)); |
| 2450 | 2460 | spin_unlock_irqrestore(&iommu->lock, flags); |
| @@ -2462,6 +2472,8 @@ static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn · 11 unmodified lines | ||
| 2462 | 2472 | 0, |
| 2463 | 2473 | 0, |
| 2464 | 2474 | DMA_TLB_DSI_FLUSH); |
| 2475 | + | |
| 2476 | + __iommu_flush_dev_iotlb(info, 0, MAX_AGAW_PFN_WIDTH); | |
| 2465 | 2477 | } |
| 2466 | 2478 | |
| 2467 | 2479 | static inline void unlink_domain_info(struct device_domain_info *info) |
| @@ -4425,9 +4437,9 @@ out_free_dmar: · 1957 unmodified lines | ||
| 4425 | 4437 | |
| 4426 | 4438 | static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque) |
| 4427 | 4439 | { |
| 4428 | − struct intel_iommu *iommu = opaque; | |
| 4440 | + struct device_domain_info *info = opaque; | |
| 4429 | 4441 | |
| 4430 | − domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); | |
| 4442 | + domain_context_clear_one(info, PCI_BUS_NUM(alias), alias & 0xff); | |
| 4431 | 4443 | return 0; |
| 4432 | 4444 | } |
| 4433 | 4445 | |
| @@ -4437,12 +4449,13 @@ static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *op · 3 unmodified lines | ||
| 4437 | 4449 | * devices, unbinding the driver from any one of them will possibly leave |
| 4438 | 4450 | * the others unable to operate. |
| 4439 | 4451 | */ |
| 4440 | −static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) | |
| 4452 | +static void domain_context_clear(struct device_domain_info *info) | |
| 4441 | 4453 | { |
| 4442 | − if (!iommu || !dev || !dev_is_pci(dev)) | |
| 4454 | + if (!info->iommu || !info->dev || !dev_is_pci(info->dev)) | |
| 4443 | 4455 | return; |
| 4444 | 4456 | |
| 4445 | − pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); | |
| 4457 | + pci_for_each_dma_alias(to_pci_dev(info->dev), | |
| 4458 | + &domain_context_clear_one_cb, info); | |
| 4446 | 4459 | } |
| 4447 | 4460 | |
| 4448 | 4461 | static void __dmar_remove_one_dev_info(struct device_domain_info *info) |
| @@ -4459,14 +4472,13 @@ static void __dmar_remove_one_dev_info(struct device_domain_info *info) · 10 unmodified lines | ||
| 4459 | 4472 | iommu = info->iommu; |
| 4460 | 4473 | domain = info->domain; |
| 4461 | 4474 | |
| 4462 | − if (info->dev) { | |
| 4475 | + if (info->dev && !dev_is_real_dma_subdevice(info->dev)) { | |
| 4463 | 4476 | if (dev_is_pci(info->dev) && sm_supported(iommu)) |
| 4464 | 4477 | intel_pasid_tear_down_entry(iommu, info->dev, |
| 4465 | 4478 | PASID_RID2PASID, false); |
| 4466 | 4479 | |
| 4467 | 4480 | iommu_disable_dev_iotlb(info); |
| 4468 | − if (!dev_is_real_dma_subdevice(info->dev)) | |
| 4469 | − domain_context_clear(iommu, info->dev); | |
| 4481 | + domain_context_clear(info); | |
| 4470 | 4482 | intel_pasid_free_table(info->dev); |
| 4471 | 4483 | } |
| 4472 | 4484 | |
| @@ -511,7 +511,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, · 510 unmodified lines | ||
| 511 | 511 | u32 pasid, bool fault_ignore) |
| 512 | 512 | { |
| 513 | 513 | struct pasid_entry *pte; |
| 514 | − u16 did; | |
| 514 | + u16 did, pgtt; | |
| 515 | 515 | |
| 516 | 516 | pte = intel_pasid_get_entry(dev, pasid); |
| 517 | 517 | if (WARN_ON(!pte)) |
| @@ -521,13 +521,19 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, · 3 unmodified lines | ||
| 521 | 521 | return; |
| 522 | 522 | |
| 523 | 523 | did = pasid_get_domain_id(pte); |
| 524 | + pgtt = pasid_pte_get_pgtt(pte); | |
| 525 | + | |
| 524 | 526 | intel_pasid_clear_entry(dev, pasid, fault_ignore); |
| 525 | 527 | |
| 526 | 528 | if (!ecap_coherent(iommu->ecap)) |
| 527 | 529 | clflush_cache_range(pte, sizeof(*pte)); |
| 528 | 530 | |
| 529 | 531 | pasid_cache_invalidation_with_pasid(iommu, did, pasid); |
| 530 | − qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); | |
| 532 | + | |
| 533 | + if (pgtt == PASID_ENTRY_PGTT_PT || pgtt == PASID_ENTRY_PGTT_FL_ONLY) | |
| 534 | + qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); | |
| 535 | + else | |
| 536 | + iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); | |
| 531 | 537 | |
| 532 | 538 | /* Device IOTLB doesn't need to be flushed in caching mode. */ |
| 533 | 539 | if (!cap_caching_mode(iommu->cap)) |
| @@ -99,6 +99,12 @@ static inline bool pasid_pte_is_present(struct pasid_entry *pte) · 98 unmodified lines | ||
| 99 | 99 | return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT; |
| 100 | 100 | } |
| 101 | 101 | |
| 102 | +/* Get PGTT field of a PASID table entry */ | |
| 103 | +static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte) | |
| 104 | +{ | |
| 105 | + return (u16)((READ_ONCE(pte->val[0]) >> 6) & 0x7); | |
| 106 | +} | |
| 107 | + | |
| 102 | 108 | extern unsigned int intel_pasid_max_id; |
| 103 | 109 | int intel_pasid_alloc_table(struct device *dev); |
| 104 | 110 | void intel_pasid_free_table(struct device *dev); |
| @@ -675,7 +675,6 @@ static int intel_svm_unbind_mm(struct device *dev, u32 pasid) · 674 unmodified lines | ||
| 675 | 675 | kfree_rcu(sdev, rcu); |
| 676 | 676 | |
| 677 | 677 | if (list_empty(&svm->devs)) { |
| 678 | − intel_svm_free_pasid(mm); | |
| 679 | 678 | if (svm->notifier.ops) { |
| 680 | 679 | mmu_notifier_unregister(&svm->notifier, mm); |
| 681 | 680 | /* Clear mm's pasid. */ |
| @@ -690,6 +689,8 @@ static int intel_svm_unbind_mm(struct device *dev, u32 pasid) · 8 unmodified lines | ||
| 690 | 689 | kfree(svm); |
| 691 | 690 | } |
| 692 | 691 | } |
| 692 | + /* Drop a PASID reference and free it if no reference. */ | |
| 693 | + intel_svm_free_pasid(mm); | |
| 693 | 694 | } |
| 694 | 695 | out: |
| 695 | 696 | return ret; |
| @@ -924,6 +924,9 @@ void iommu_group_remove_device(struct device *dev) · 923 unmodified lines | ||
| 924 | 924 | struct iommu_group *group = dev->iommu_group; |
| 925 | 925 | struct group_device *tmp_device, *device = NULL; |
| 926 | 926 | |
| 927 | + if (!group) | |
| 928 | + return; | |
| 929 | + | |
| 927 | 930 | dev_info(dev, "Removing from iommu group %d\n", group->id); |
| 928 | 931 | |
| 929 | 932 | /* Pre-notify listeners that a device is being removed. */ |
| @@ -544,12 +544,14 @@ static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma) · 543 unmodified lines | ||
| 544 | 544 | } |
| 545 | 545 | |
| 546 | 546 | #define DT_HI_MASK GENMASK_ULL(39, 32) |
| 547 | +#define DTE_BASE_HI_MASK GENMASK(11, 4) | |
| 547 | 548 | #define DT_SHIFT 28 |
| 548 | 549 | |
| 549 | 550 | static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr) |
| 550 | 551 | { |
| 551 | − return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) | | |
| 552 | − ((addr & DT_HI_MASK) << DT_SHIFT); | |
| 552 | + u64 addr64 = addr; | |
| 553 | + return (phys_addr_t)(addr64 & RK_DTE_PT_ADDRESS_MASK) | | |
| 554 | + ((addr64 & DTE_BASE_HI_MASK) << DT_SHIFT); | |
| 553 | 555 | } |
| 554 | 556 | |
| 555 | 557 | static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma) |
| @@ -89,16 +89,13 @@ static void tpci200_unregister(struct tpci200_board *tpci200) · 88 unmodified lines | ||
| 89 | 89 | free_irq(tpci200->info->pdev->irq, (void *) tpci200); |
| 90 | 90 | |
| 91 | 91 | pci_iounmap(tpci200->info->pdev, tpci200->info->interface_regs); |
| 92 | − pci_iounmap(tpci200->info->pdev, tpci200->info->cfg_regs); | |
| 93 | 92 | |
| 94 | 93 | pci_release_region(tpci200->info->pdev, TPCI200_IP_INTERFACE_BAR); |
| 95 | 94 | pci_release_region(tpci200->info->pdev, TPCI200_IO_ID_INT_SPACES_BAR); |
| 96 | 95 | pci_release_region(tpci200->info->pdev, TPCI200_MEM16_SPACE_BAR); |
| 97 | 96 | pci_release_region(tpci200->info->pdev, TPCI200_MEM8_SPACE_BAR); |
| 98 | − pci_release_region(tpci200->info->pdev, TPCI200_CFG_MEM_BAR); | |
| 99 | 97 | |
| 100 | 98 | pci_disable_device(tpci200->info->pdev); |
| 101 | − pci_dev_put(tpci200->info->pdev); | |
| 102 | 99 | } |
| 103 | 100 | |
| 104 | 101 | static void tpci200_enable_irq(struct tpci200_board *tpci200, |
| @@ -257,7 +254,7 @@ static int tpci200_register(struct tpci200_board *tpci200) · 152 unmodified lines | ||
| 257 | 254 | "(bn 0x%X, sn 0x%X) failed to allocate PCI resource for BAR 2 !", |
| 258 | 255 | tpci200->info->pdev->bus->number, |
| 259 | 256 | tpci200->info->pdev->devfn); |
| 260 | − goto out_disable_pci; | |
| 257 | + goto err_disable_device; | |
| 261 | 258 | } |
| 262 | 259 | |
| 263 | 260 | /* Request IO ID INT space (Bar 3) */ |
| @@ -269,7 +266,7 @@ static int tpci200_register(struct tpci200_board *tpci200) · 5 unmodified lines | ||
| 269 | 266 | "(bn 0x%X, sn 0x%X) failed to allocate PCI resource for BAR 3 !", |
| 270 | 267 | tpci200->info->pdev->bus->number, |
| 271 | 268 | tpci200->info->pdev->devfn); |
| 272 | − goto out_release_ip_space; | |
| 269 | + goto err_ip_interface_bar; | |
| 273 | 270 | } |
| 274 | 271 | |
| 275 | 272 | /* Request MEM8 space (Bar 5) */ |
| @@ -280,7 +277,7 @@ static int tpci200_register(struct tpci200_board *tpci200) · 4 unmodified lines | ||
| 280 | 277 | "(bn 0x%X, sn 0x%X) failed to allocate PCI resource for BAR 5!", |
| 281 | 278 | tpci200->info->pdev->bus->number, |
| 282 | 279 | tpci200->info->pdev->devfn); |
| 283 | − goto out_release_ioid_int_space; | |
| 280 | + goto err_io_id_int_spaces_bar; | |
| 284 | 281 | } |
| 285 | 282 | |
| 286 | 283 | /* Request MEM16 space (Bar 4) */ |
| @@ -291,7 +288,7 @@ static int tpci200_register(struct tpci200_board *tpci200) · 4 unmodified lines | ||
| 291 | 288 | "(bn 0x%X, sn 0x%X) failed to allocate PCI resource for BAR 4!", |
| 292 | 289 | tpci200->info->pdev->bus->number, |
| 293 | 290 | tpci200->info->pdev->devfn); |
| 294 | − goto out_release_mem8_space; | |
| 291 | + goto err_mem8_space_bar; | |
| 295 | 292 | } |
| 296 | 293 | |
| 297 | 294 | /* Map internal tpci200 driver user space */ |
| @@ -305,7 +302,7 @@ static int tpci200_register(struct tpci200_board *tpci200) · 7 unmodified lines | ||
| 305 | 302 | tpci200->info->pdev->bus->number, |
| 306 | 303 | tpci200->info->pdev->devfn); |
| 307 | 304 | res = -ENOMEM; |
| 308 | − goto out_release_mem8_space; | |
| 305 | + goto err_mem16_space_bar; | |
| 309 | 306 | } |
| 310 | 307 | |
| 311 | 308 | /* Initialize lock that protects interface_regs */ |
| @@ -344,18 +341,22 @@ static int tpci200_register(struct tpci200_board *tpci200) · 32 unmodified lines | ||
| 344 | 341 | "(bn 0x%X, sn 0x%X) unable to register IRQ !", |
| 345 | 342 | tpci200->info->pdev->bus->number, |
| 346 | 343 | tpci200->info->pdev->devfn); |
| 347 | − goto out_release_ioid_int_space; | |
| 344 | + goto err_interface_regs; | |
| 348 | 345 | } |
| 349 | 346 | |
| 350 | 347 | return 0; |
| 351 | 348 | |
| 352 | −out_release_mem8_space: | |
| 349 | +err_interface_regs: | |
| 350 | + pci_iounmap(tpci200->info->pdev, tpci200->info->interface_regs); | |
| 351 | +err_mem16_space_bar: | |
| 352 | + pci_release_region(tpci200->info->pdev, TPCI200_MEM16_SPACE_BAR); | |
| 353 | +err_mem8_space_bar: | |
| 353 | 354 | pci_release_region(tpci200->info->pdev, TPCI200_MEM8_SPACE_BAR); |
| 354 | −out_release_ioid_int_space: | |
| 355 | +err_io_id_int_spaces_bar: | |
| 355 | 356 | pci_release_region(tpci200->info->pdev, TPCI200_IO_ID_INT_SPACES_BAR); |
| 356 | −out_release_ip_space: | |
| 357 | +err_ip_interface_bar: | |
| 357 | 358 | pci_release_region(tpci200->info->pdev, TPCI200_IP_INTERFACE_BAR); |
| 358 | −out_disable_pci: | |
| 359 | +err_disable_device: | |
| 359 | 360 | pci_disable_device(tpci200->info->pdev); |
| 360 | 361 | return res; |
| 361 | 362 | } |
| @@ -527,7 +528,7 @@ static int tpci200_pci_probe(struct pci_dev *pdev, · 165 unmodified lines | ||
| 527 | 528 | tpci200->info = kzalloc(sizeof(struct tpci200_infos), GFP_KERNEL); |
| 528 | 529 | if (!tpci200->info) { |
| 529 | 530 | ret = -ENOMEM; |
| 530 | − goto out_err_info; | |
| 531 | + goto err_tpci200; | |
| 531 | 532 | } |
| 532 | 533 | |
| 533 | 534 | pci_dev_get(pdev); |
| @@ -538,7 +539,7 @@ static int tpci200_pci_probe(struct pci_dev *pdev, · 4 unmodified lines | ||
| 538 | 539 | if (ret) { |
| 539 | 540 | dev_err(&pdev->dev, "Failed to allocate PCI Configuration Memory"); |
| 540 | 541 | ret = -EBUSY; |
| 541 | − goto out_err_pci_request; | |
| 542 | + goto err_tpci200_info; | |
| 542 | 543 | } |
| 543 | 544 | tpci200->info->cfg_regs = ioremap( |
| 544 | 545 | pci_resource_start(pdev, TPCI200_CFG_MEM_BAR), |
| @@ -546,7 +547,7 @@ static int tpci200_pci_probe(struct pci_dev *pdev, · 1 unmodified line | ||
| 546 | 547 | if (!tpci200->info->cfg_regs) { |
| 547 | 548 | dev_err(&pdev->dev, "Failed to map PCI Configuration Memory"); |
| 548 | 549 | ret = -EFAULT; |
| 549 | − goto out_err_ioremap; | |
| 550 | + goto err_request_region; | |
| 550 | 551 | } |
| 551 | 552 | |
| 552 | 553 | /* Disable byte swapping for 16 bit IP module access. This will ensure |
| @@ -569,7 +570,7 @@ static int tpci200_pci_probe(struct pci_dev *pdev, · 16 unmodified lines | ||
| 569 | 570 | if (ret) { |
| 570 | 571 | dev_err(&pdev->dev, "error during tpci200 install\n"); |
| 571 | 572 | ret = -ENODEV; |
| 572 | − goto out_err_install; | |
| 573 | + goto err_cfg_regs; | |
| 573 | 574 | } |
| 574 | 575 | |
| 575 | 576 | /* Register the carrier in the industry pack bus driver */ |
| @@ -581,7 +582,7 @@ static int tpci200_pci_probe(struct pci_dev *pdev, · 5 unmodified lines | ||
| 581 | 582 | dev_err(&pdev->dev, |
| 582 | 583 | "error registering the carrier on ipack driver\n"); |
| 583 | 584 | ret = -EFAULT; |
| 584 | − goto out_err_bus_register; | |
| 585 | + goto err_tpci200_install; | |
| 585 | 586 | } |
| 586 | 587 | |
| 587 | 588 | /* save the bus number given by ipack to logging purpose */ |
| @@ -592,19 +593,16 @@ static int tpci200_pci_probe(struct pci_dev *pdev, · 4 unmodified lines | ||
| 592 | 593 | tpci200_create_device(tpci200, i); |
| 593 | 594 | return 0; |
| 594 | 595 | |
| 595 | −out_err_bus_register: | |
| 596 | +err_tpci200_install: | |
| 596 | 597 | tpci200_uninstall(tpci200); |
| 597 | − /* tpci200->info->cfg_regs is unmapped in tpci200_uninstall */ | |
| 598 | − tpci200->info->cfg_regs = NULL; | |
| 599 | −out_err_install: | |
| 600 | − if (tpci200->info->cfg_regs) | |
| 601 | − iounmap(tpci200->info->cfg_regs); | |
| 602 | −out_err_ioremap: | |
| 598 | +err_cfg_regs: | |
| 599 | + pci_iounmap(tpci200->info->pdev, tpci200->info->cfg_regs); | |
| 600 | +err_request_region: | |
| 603 | 601 | pci_release_region(pdev, TPCI200_CFG_MEM_BAR); |
| 604 | −out_err_pci_request: | |
| 605 | − pci_dev_put(pdev); | |
| 602 | +err_tpci200_info: | |
| 606 | 603 | kfree(tpci200->info); |
| 607 | −out_err_info: | |
| 604 | + pci_dev_put(pdev); | |
| 605 | +err_tpci200: | |
| 608 | 606 | kfree(tpci200); |
| 609 | 607 | return ret; |
| 610 | 608 | } |
| @@ -614,6 +612,12 @@ static void __tpci200_pci_remove(struct tpci200_board *tpci200) · 3 unmodified lines | ||
| 614 | 612 | ipack_bus_unregister(tpci200->info->ipack_bus); |
| 615 | 613 | tpci200_uninstall(tpci200); |
| 616 | 614 | |
| 615 | + pci_iounmap(tpci200->info->pdev, tpci200->info->cfg_regs); | |
| 616 | + | |
| 617 | + pci_release_region(tpci200->info->pdev, TPCI200_CFG_MEM_BAR); | |
| 618 | + | |
| 619 | + pci_dev_put(tpci200->info->pdev); | |
| 620 | + | |
| 617 | 621 | kfree(tpci200->info); |
| 618 | 622 | kfree(tpci200); |
| 619 | 623 | } |
| @@ -474,8 +474,6 @@ static void raid1_end_write_request(struct bio *bio) · 473 unmodified lines | ||
| 474 | 474 | /* |
| 475 | 475 | * When the device is faulty, it is not necessary to |
| 476 | 476 | * handle write error. |
| 477 | − * For failfast, this is the only remaining device, | |
| 478 | − * We need to retry the write without FailFast. | |
| 479 | 477 | */ |
| 480 | 478 | if (!test_bit(Faulty, &rdev->flags)) |
| 481 | 479 | set_bit(R1BIO_WriteError, &r1_bio->state); |
| @@ -471,12 +471,12 @@ static void raid10_end_write_request(struct bio *bio) · 470 unmodified lines | ||
| 471 | 471 | /* |
| 472 | 472 | * When the device is faulty, it is not necessary to |
| 473 | 473 | * handle write error. |
| 474 | − * For failfast, this is the only remaining device, | |
| 475 | − * We need to retry the write without FailFast. | |
| 476 | 474 | */ |
| 477 | 475 | if (!test_bit(Faulty, &rdev->flags)) |
| 478 | 476 | set_bit(R10BIO_WriteError, &r10_bio->state); |
| 479 | 477 | else { |
| 478 | + /* Fail the request */ | |
| 479 | + set_bit(R10BIO_Degraded, &r10_bio->state); | |
| 480 | 480 | r10_bio->devs[slot].bio = NULL; |
| 481 | 481 | to_put = bio; |
| 482 | 482 | dec_rdev = 1; |
| @@ -1573,6 +1573,7 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb, · 1572 unmodified lines | ||
| 1573 | 1573 | struct media_request *req) |
| 1574 | 1574 | { |
| 1575 | 1575 | struct vb2_buffer *vb; |
| 1576 | + enum vb2_buffer_state orig_state; | |
| 1576 | 1577 | int ret; |
| 1577 | 1578 | |
| 1578 | 1579 | if (q->error) { |
| @@ -1673,6 +1674,7 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb, · 94 unmodified lines | ||
| 1673 | 1674 | * Add to the queued buffers list, a buffer will stay on it until |
| 1674 | 1675 | * dequeued in dqbuf. |
| 1675 | 1676 | */ |
| 1677 | + orig_state = vb->state; | |
| 1676 | 1678 | list_add_tail(&vb->queued_entry, &q->queued_list); |
| 1677 | 1679 | q->queued_count++; |
| 1678 | 1680 | q->waiting_for_buffers = false; |
| @@ -1703,8 +1705,17 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb, · 24 unmodified lines | ||
| 1703 | 1705 | if (q->streaming && !q->start_streaming_called && |
| 1704 | 1706 | q->queued_count >= q->min_buffers_needed) { |
| 1705 | 1707 | ret = vb2_start_streaming(q); |
| 1706 | − if (ret) | |
| 1708 | + if (ret) { | |
| 1709 | + /* | |
| 1710 | + * Since vb2_core_qbuf will return with an error, | |
| 1711 | + * we should return it to state DEQUEUED since | |
| 1712 | + * the error indicates that the buffer wasn't queued. | |
| 1713 | + */ | |
| 1714 | + list_del(&vb->queued_entry); | |
| 1715 | + q->queued_count--; | |
| 1716 | + vb->state = orig_state; | |
| 1707 | 1717 | return ret; |
| 1718 | + } | |
| 1708 | 1719 | } |
| 1709 | 1720 | |
| 1710 | 1721 | dprintk(q, 2, "qbuf of buffer %d succeeded\n", vb->index); |
| @@ -173,10 +173,8 @@ static int cio2_bridge_connect_sensor(const struct cio2_sensor_config *cfg, · 172 unmodified lines | ||
| 173 | 173 | int ret; |
| 174 | 174 | |
| 175 | 175 | for_each_acpi_dev_match(adev, cfg->hid, NULL, -1) { |
| 176 | − if (!adev->status.enabled) { | |
| 177 | − acpi_dev_put(adev); | |
| 176 | + if (!adev->status.enabled) | |
| 178 | 177 | continue; |
| 179 | − } | |
| 180 | 178 | |
| 181 | 179 | if (bridge->n_sensors >= CIO2_NUM_PORTS) { |
| 182 | 180 | acpi_dev_put(adev); |
| @@ -185,7 +183,6 @@ static int cio2_bridge_connect_sensor(const struct cio2_sensor_config *cfg, · 2 unmodified lines | ||
| 185 | 183 | } |
| 186 | 184 | |
| 187 | 185 | sensor = &bridge->sensors[bridge->n_sensors]; |
| 188 | − sensor->adev = adev; | |
| 189 | 186 | strscpy(sensor->name, cfg->hid, sizeof(sensor->name)); |
| 190 | 187 | |
| 191 | 188 | ret = cio2_bridge_read_acpi_buffer(adev, "SSDB", |
| @@ -215,6 +212,7 @@ static int cio2_bridge_connect_sensor(const struct cio2_sensor_config *cfg, · 23 unmodified lines | ||
| 215 | 212 | goto err_free_swnodes; |
| 216 | 213 | } |
| 217 | 214 | |
| 215 | + sensor->adev = acpi_dev_get(adev); | |
| 218 | 216 | adev->fwnode.secondary = fwnode; |
| 219 | 217 | |
| 220 | 218 | dev_info(&cio2->dev, "Found supported sensor %s\n", |
| @@ -385,7 +385,7 @@ static int ngene_command_config_free_buf(struct ngene *dev, u8 *config) · 384 unmodified lines | ||
| 385 | 385 | |
| 386 | 386 | com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; |
| 387 | 387 | com.cmd.hdr.Length = 6; |
| 388 | − memcpy(&com.cmd.ConfigureBuffers.config, config, 6); | |
| 388 | + memcpy(&com.cmd.ConfigureFreeBuffers.config, config, 6); | |
| 389 | 389 | com.in_len = 6; |
| 390 | 390 | com.out_len = 0; |
| 391 | 391 | |
| @@ -407,12 +407,14 @@ enum _BUFFER_CONFIGS { · 406 unmodified lines | ||
| 407 | 407 | |
| 408 | 408 | struct FW_CONFIGURE_FREE_BUFFERS { |
| 409 | 409 | struct FW_HEADER hdr; |
| 410 | − u8 UVI1_BufferLength; | |
| 411 | − u8 UVI2_BufferLength; | |
| 412 | − u8 TVO_BufferLength; | |
| 413 | − u8 AUD1_BufferLength; | |
| 414 | − u8 AUD2_BufferLength; | |
| 415 | − u8 TVA_BufferLength; | |
| 410 | + struct { | |
| 411 | + u8 UVI1_BufferLength; | |
| 412 | + u8 UVI2_BufferLength; | |
| 413 | + u8 TVO_BufferLength; | |
| 414 | + u8 AUD1_BufferLength; | |
| 415 | + u8 AUD2_BufferLength; | |
| 416 | + u8 TVA_BufferLength; | |
| 417 | + } __packed config; | |
| 416 | 418 | } __attribute__ ((__packed__)); |
| 417 | 419 | |
| 418 | 420 | struct FW_CONFIGURE_UART { |
| @@ -8,6 +8,7 @@ config VIDEO_ATMEL_ISC · 7 unmodified lines | ||
| 8 | 8 | select VIDEOBUF2_DMA_CONTIG |
| 9 | 9 | select REGMAP_MMIO |
| 10 | 10 | select V4L2_FWNODE |
| 11 | + select VIDEO_ATMEL_ISC_BASE | |
| 11 | 12 | help |
| 12 | 13 | This module makes the ATMEL Image Sensor Controller available |
| 13 | 14 | as a v4l2 device. |
| @@ -19,10 +20,17 @@ config VIDEO_ATMEL_XISC · 5 unmodified lines | ||
| 19 | 20 | select VIDEOBUF2_DMA_CONTIG |
| 20 | 21 | select REGMAP_MMIO |
| 21 | 22 | select V4L2_FWNODE |
| 23 | + select VIDEO_ATMEL_ISC_BASE | |
| 22 | 24 | help |
| 23 | 25 | This module makes the ATMEL eXtended Image Sensor Controller |
| 24 | 26 | available as a v4l2 device. |
| 25 | 27 | |
| 28 | +config VIDEO_ATMEL_ISC_BASE | |
| 29 | + tristate | |
| 30 | + default n | |
| 31 | + help | |
| 32 | + ATMEL ISC and XISC common code base. | |
| 33 | + | |
| 26 | 34 | config VIDEO_ATMEL_ISI |
| 27 | 35 | tristate "ATMEL Image Sensor Interface (ISI) support" |
| 28 | 36 | depends on VIDEO_V4L2 && OF |
| @@ -1,7 +1,8 @@ | ||
| 1 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | −atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o | |
| 3 | −atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o | |
| 2 | +atmel-isc-objs = atmel-sama5d2-isc.o | |
| 3 | +atmel-xisc-objs = atmel-sama7g5-isc.o | |
| 4 | 4 | |
| 5 | 5 | obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o |
| 6 | +obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o | |
| 6 | 7 | obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o |
| 7 | 8 | obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o |
| @@ -378,6 +378,7 @@ int isc_clk_init(struct isc_device *isc) · 377 unmodified lines | ||
| 378 | 378 | |
| 379 | 379 | return 0; |
| 380 | 380 | } |
| 381 | +EXPORT_SYMBOL_GPL(isc_clk_init); | |
| 381 | 382 | |
| 382 | 383 | void isc_clk_cleanup(struct isc_device *isc) |
| 383 | 384 | { |
| @@ -392,6 +393,7 @@ void isc_clk_cleanup(struct isc_device *isc) · 8 unmodified lines | ||
| 392 | 393 | clk_unregister(isc_clk->clk); |
| 393 | 394 | } |
| 394 | 395 | } |
| 396 | +EXPORT_SYMBOL_GPL(isc_clk_cleanup); | |
| 395 | 397 | |
| 396 | 398 | static int isc_queue_setup(struct vb2_queue *vq, |
| 397 | 399 | unsigned int *nbuffers, unsigned int *nplanes, |
| @@ -1578,6 +1580,7 @@ irqreturn_t isc_interrupt(int irq, void *dev_id) · 1180 unmodified lines | ||
| 1578 | 1580 | |
| 1579 | 1581 | return ret; |
| 1580 | 1582 | } |
| 1583 | +EXPORT_SYMBOL_GPL(isc_interrupt); | |
| 1581 | 1584 | |
| 1582 | 1585 | static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) |
| 1583 | 1586 | { |
| @@ -2212,6 +2215,7 @@ const struct v4l2_async_notifier_operations isc_async_ops = { · 628 unmodified lines | ||
| 2212 | 2215 | .unbind = isc_async_unbind, |
| 2213 | 2216 | .complete = isc_async_complete, |
| 2214 | 2217 | }; |
| 2218 | +EXPORT_SYMBOL_GPL(isc_async_ops); | |
| 2215 | 2219 | |
| 2216 | 2220 | void isc_subdev_cleanup(struct isc_device *isc) |
| 2217 | 2221 | { |
| @@ -2224,6 +2228,7 @@ void isc_subdev_cleanup(struct isc_device *isc) · 6 unmodified lines | ||
| 2224 | 2228 | |
| 2225 | 2229 | INIT_LIST_HEAD(&isc->subdev_entities); |
| 2226 | 2230 | } |
| 2231 | +EXPORT_SYMBOL_GPL(isc_subdev_cleanup); | |
| 2227 | 2232 | |
| 2228 | 2233 | int isc_pipeline_init(struct isc_device *isc) |
| 2229 | 2234 | { |
| @@ -2264,6 +2269,7 @@ int isc_pipeline_init(struct isc_device *isc) · 34 unmodified lines | ||
| 2264 | 2269 | |
| 2265 | 2270 | return 0; |
| 2266 | 2271 | } |
| 2272 | +EXPORT_SYMBOL_GPL(isc_pipeline_init); | |
| 2267 | 2273 | |
| 2268 | 2274 | /* regmap configuration */ |
| 2269 | 2275 | #define ATMEL_ISC_REG_MAX 0xd5c |
| @@ -2273,4 +2279,9 @@ const struct regmap_config isc_regmap_config = { · 3 unmodified lines | ||
| 2273 | 2279 | .val_bits = 32, |
| 2274 | 2280 | .max_register = ATMEL_ISC_REG_MAX, |
| 2275 | 2281 | }; |
| 2282 | +EXPORT_SYMBOL_GPL(isc_regmap_config); | |
| 2276 | 2283 | |
| 2284 | +MODULE_AUTHOR("Songjun Wu"); | |
| 2285 | +MODULE_AUTHOR("Eugen Hristev"); | |
| 2286 | +MODULE_DESCRIPTION("Atmel ISC common code base"); | |
| 2287 | +MODULE_LICENSE("GPL v2"); | |
| @@ -37,7 +37,16 @@ static int rtl28xxu_ctrl_msg(struct dvb_usb_device *d, struct rtl28xxu_req *req) · 36 unmodified lines | ||
| 37 | 37 | } else { |
| 38 | 38 | /* read */ |
| 39 | 39 | requesttype = (USB_TYPE_VENDOR | USB_DIR_IN); |
| 40 | − pipe = usb_rcvctrlpipe(d->udev, 0); | |
| 40 | + | |
| 41 | + /* | |
| 42 | + * Zero-length transfers must use usb_sndctrlpipe() and | |
| 43 | + * rtl28xxu_identify_state() uses a zero-length i2c read | |
| 44 | + * command to determine the chip type. | |
| 45 | + */ | |
| 46 | + if (req->size) | |
| 47 | + pipe = usb_rcvctrlpipe(d->udev, 0); | |
| 48 | + else | |
| 49 | + pipe = usb_sndctrlpipe(d->udev, 0); | |
| 41 | 50 | } |
| 42 | 51 | |
| 43 | 52 | ret = usb_control_msg(d->udev, pipe, 0, requesttype, req->value, |
| @@ -612,9 +621,8 @@ static int rtl28xxu_read_config(struct dvb_usb_device *d) · 568 unmodified lines | ||
| 612 | 621 | static int rtl28xxu_identify_state(struct dvb_usb_device *d, const char **name) |
| 613 | 622 | { |
| 614 | 623 | struct rtl28xxu_dev *dev = d_to_priv(d); |
| 615 | − u8 buf[1]; | |
| 616 | 624 | int ret; |
| 617 | − struct rtl28xxu_req req_demod_i2c = {0x0020, CMD_I2C_DA_RD, 1, buf}; | |
| 625 | + struct rtl28xxu_req req_demod_i2c = {0x0020, CMD_I2C_DA_RD, 0, NULL}; | |
| 618 | 626 | |
| 619 | 627 | dev_dbg(&d->intf->dev, "\n"); |
| 620 | 628 | |
| @@ -714,23 +714,20 @@ static int at24_probe(struct i2c_client *client) · 713 unmodified lines | ||
| 714 | 714 | } |
| 715 | 715 | |
| 716 | 716 | /* |
| 717 | − * If the 'label' property is not present for the AT24 EEPROM, | |
| 718 | − * then nvmem_config.id is initialised to NVMEM_DEVID_AUTO, | |
| 719 | − * and this will append the 'devid' to the name of the NVMEM | |
| 720 | − * device. This is purely legacy and the AT24 driver has always | |
| 721 | − * defaulted to this. However, if the 'label' property is | |
| 722 | − * present then this means that the name is specified by the | |
| 723 | − * firmware and this name should be used verbatim and so it is | |
| 724 | − * not necessary to append the 'devid'. | |
| 717 | + * We initialize nvmem_config.id to NVMEM_DEVID_AUTO even if the | |
| 718 | + * label property is set as some platform can have multiple eeproms | |
| 719 | + * with same label and we can not register each of those with same | |
| 720 | + * label. Failing to register those eeproms trigger cascade failure | |
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