Merge tag 'mmc-v3.17-1' of git://git.linaro.org/people/ulf.hansson/mmc

Pull MMC updates from Ulf Hansson: "Me and Chris Ball decided to try out using my MMC tree as the primary one, to simplify handling of patches. This pull does thus contains all the MMC patches for 3.17 rc1, no pull from Chris this time. Details: MMC core: - forward compatibility for eMMC - fix some blacklisted cards with broken secure discard MMC host: - mmci: Add support for Qualcomm variant - mmci: Fix regression for arm_variant - sdhci: Various fixes and cleanups - sdhci: Improve external VDD regulator support - sdhci: Support for DDR50 1.8V mode for BayTrail - sdhci-st: Add driver for ST SDHCI controller - sh-mmcif: DMA fixes - omap_hsmmc: Add support for SDIO interrupts - sdhci-pci: Add support for Intel Quark X1000 - dw_mmc: Update the reset sequence - s3cmci: port DMA code to dmaengine API" * tag 'mmc-v3.17-1' of git://git.linaro.org/people/ulf.hansson/mmc: (67 commits) mmc: dw_mmc: modify the dt-binding for removing slot-node and supports-highspeed mmc: dw_mmc: Slot quirk "disable-wp" is deprecated. mmc: mmci: Reverse IRQ handling for the arm_variant mmc: mmci: Move all CMD irq handling to mmci_cmd_irq() mmc: mmci: Remove redundant check of status for DATA irq mmc: dw_mmc: change to use recommended reset procedure mmc: sdhci-pxav3: Use devm_* managed helpers mmc: tmio: Configure DMA slave bus width mmc: sh_mmcif: Configure DMA slave bus width mmc: sh_mmcif: Fix DMA slave address configuration mmc: sh_mmcif: Document DT bindings mmc: sdhci-pci: remove PCI PM functions in suspend/resume callback mmc: Do not advertise secure discard if it is blacklisted mmc: sdhci-msm: Get COMPILE_TEST support mmc: sdhci-msm: Remove unnecessary header file inclusion mmc: sdhci-msm: Fix the binding example mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC Controller mmc: sdhci: Preset value not supported in Baytrail eMMC mmc: MMC_USDHI6ROL0 should depend on HAS_DMA mmc: MMC_SH_MMCIF should depend on HAS_DMA ...

Linus Torvalds committed 12 years ago

Commit a8e4def2 parents d429a36 c83c87340 files · +1050 −471Browse files

Unified · Split

40 files

Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +5 −12
Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt +5 −7
Documentation/devicetree/bindings/mmc/mmc.txt +2 −2
Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +32 −0
Documentation/devicetree/bindings/mmc/sdhci-msm.txt +4 −4
Documentation/devicetree/bindings/mmc/sdhci-st.txt +33 −0
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +5 −7
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +54 −0
Documentation/devicetree/bindings/mmc/tmio_mmc.txt +1 −0
drivers/mmc/card/block.c +3 −3
drivers/mmc/core/bus.c +1 −9
drivers/mmc/core/core.c +2 −1
drivers/mmc/core/mmc.c +5 −6
drivers/mmc/core/quirks.c +1 −1
drivers/mmc/core/sd_ops.c +3 −0
drivers/mmc/host/Kconfig +17 −11
drivers/mmc/host/Makefile +1 −0
drivers/mmc/host/dw_mmc.c +73 −25
drivers/mmc/host/dw_mmc.h +5 −0
drivers/mmc/host/mmci.c +140 −28
drivers/mmc/host/mmci.h +20 −0
drivers/mmc/host/moxart-mmc.c +0 −1
drivers/mmc/host/mxs-mmc.c +2 −1
drivers/mmc/host/omap_hsmmc.c +262 −21
drivers/mmc/host/s3cmci.c +53 −133
drivers/mmc/host/s3cmci.h +1 −3
drivers/mmc/host/sdhci-acpi.c +3 −1
drivers/mmc/host/sdhci-msm.c +0 −1
drivers/mmc/host/sdhci-pci.c +20 −18
drivers/mmc/host/sdhci-pci.h +1 −0
drivers/mmc/host/sdhci-pxav3.c +3 −10
drivers/mmc/host/sdhci-st.c +176 −0
drivers/mmc/host/sdhci-tegra.c +0 −2
drivers/mmc/host/sdhci.c +58 −86
drivers/mmc/host/sh_mmcif.c +38 −58
drivers/mmc/host/tmio_mmc_dma.c +2 −0
drivers/mmc/host/wmt-sdmmc.c +16 −17
include/linux/mmc/dw_mmc.h +2 −0
include/linux/mmc/sdhci.h +0 −3
include/linux/platform_data/mmc-omap.h +1 −0

Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt+5−12

@@ -46,13 +46,14 @@ Required Properties: · 45 unmodified lines
46	46	- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
47	47	phase shift clocks should be 0.
48	48
49		−Required properties for a slot:
	49	+Required properties for a slot (Deprecated - Recommend to use one slot per host):
50	50
51	51	* gpios: specifies a list of gpios used for command, clock and data bus. The
52	52	first gpio is the command line and the second gpio is the clock line. The
53	53	rest of the gpios (depending on the bus-width property) are the data lines in
54	54	no particular order. The format of the gpio specifier depends on the gpio
55	55	controller.
	56	+(Deprecated - Refer to Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
56	57
57	58	Example:
58	59
@@ -69,21 +70,13 @@ Example: · 10 unmodified lines
69	70
70	71	dwmmc0@12200000 {
71	72	num-slots = <1>;
72		− supports-highspeed;
	73	+ cap-mmc-highspeed;
	74	+ cap-sd-highspeed;
73	75	broken-cd;
74	76	fifo-depth = <0x80>;
75	77	card-detect-delay = <200>;
76	78	samsung,dw-mshc-ciu-div = <3>;
77	79	samsung,dw-mshc-sdr-timing = <2 3>;
78	80	samsung,dw-mshc-ddr-timing = <1 2>;
79		−
80		− slot@0 {
81		− reg = <0>;
82		− bus-width = <8>;
83		− gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
84		− <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
85		− <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
86		− <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
87		− <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
88		− };
	81	+ bus-width = <8>;
89	82	};

Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt+5−7

@@ -34,13 +34,11 @@ Example: · 33 unmodified lines
34	34	num-slots = <1>;
35	35	vmmc-supply = <&ldo12>;
36	36	fifo-depth = <0x100>;
37		− supports-highspeed;
38	37	pinctrl-names = "default";
39	38	pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
40		− slot@0 {
41		− reg = <0>;
42		− bus-width = <4>;
43		− disable-wp;
44		− cd-gpios = <&gpio10 3 0>;
45		− };
	39	+ bus-width = <4>;
	40	+ disable-wp;
	41	+ cd-gpios = <&gpio10 3 0>;
	42	+ cap-mmc-highspeed;
	43	+ cap-sd-highspeed;
46	44	};

Documentation/devicetree/bindings/mmc/mmc.txt+2−2

@@ -34,8 +34,8 @@ Optional properties: · 33 unmodified lines
34	34	- cap-power-off-card: powering off the card is safe
35	35	- cap-sdio-irq: enable SDIO IRQ signalling on this interface
36	36	- full-pwr-cycle: full power cycle of the card is supported
37		−- mmc-highspeed-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
38		−- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
	37	+- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
	38	+- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
39	39	- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
40	40	- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
41	41	- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported

Documentation/devicetree/bindings/mmc/renesas,mmcif.txt+32−0

@@ -0,0 +1,32 @@
	1	+* Renesas Multi Media Card Interface (MMCIF) Controller
	2	+
	3	+This file documents differences between the core properties in mmc.txt
	4	+and the properties used by the MMCIF device.
	5	+
	6	+
	7	+Required properties:
	8	+
	9	+- compatible: must contain one of the following
	10	+ - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
	11	+ - "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
	12	+ - "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
	13	+ - "renesas,sh-mmcif" for the generic MMCIF
	14	+
	15	+- clocks: reference to the functional clock
	16	+
	17	+- dmas: reference to the DMA channels, one per channel name listed in the
	18	+ dma-names property.
	19	+- dma-names: must contain "tx" for the transmit DMA channel and "rx" for the
	20	+ receive DMA channel.
	21	+
	22	+
	23	+Example: R8A7790 (R-Car H2) MMCIF0
	24	+
	25	+ mmcif0: mmc@ee200000 {
	26	+ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
	27	+ reg = <0 0xee200000 0 0x80>;
	28	+ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
	29	+ clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
	30	+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
	31	+ dma-names = "tx", "rx";
	32	+ };

Documentation/devicetree/bindings/mmc/sdhci-msm.txt+4−4

@@ -27,8 +27,8 @@ Example: · 26 unmodified lines
27	27	bus-width = <8>;
28	28	non-removable;
29	29
30		− vmmc = <&pm8941_l20>;
31		− vqmmc = <&pm8941_s3>;
	30	+ vmmc-supply = <&pm8941_l20>;
	31	+ vqmmc-supply = <&pm8941_s3>;
32	32
33	33	pinctrl-names = "default";
34	34	pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
@@ -44,8 +44,8 @@ Example: · 9 unmodified lines
44	44	bus-width = <4>;
45	45	cd-gpios = <&msmgpio 62 0x1>;
46	46
47		− vmmc = <&pm8941_l21>;
48		− vqmmc = <&pm8941_l13>;
	47	+ vmmc-supply = <&pm8941_l21>;
	48	+ vqmmc-supply = <&pm8941_l13>;
49	49
50	50	pinctrl-names = "default";
51	51	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;

Documentation/devicetree/bindings/mmc/sdhci-st.txt+33−0

@@ -0,0 +1,33 @@
	1	+* STMicroelectronics sdhci-st MMC/SD controller
	2	+
	3	+This file documents the differences between the core properties in
	4	+Documentation/devicetree/bindings/mmc/mmc.txt and the properties
	5	+used by the sdhci-st driver.
	6	+
	7	+Required properties:
	8	+- compatible : Must be "st,sdhci"
	9	+- clock-names : Should be "mmc"
	10	+ See: Documentation/devicetree/bindings/resource-names.txt
	11	+- clocks : Phandle of the clock used by the sdhci controler
	12	+ See: Documentation/devicetree/bindings/clock/clock-bindings.txt
	13	+
	14	+Optional properties:
	15	+- non-removable: non-removable slot
	16	+ See: Documentation/devicetree/bindings/mmc/mmc.txt
	17	+- bus-width: Number of data lines
	18	+ See: Documentation/devicetree/bindings/mmc/mmc.txt
	19	+
	20	+Example:
	21	+
	22	+mmc0: sdhci@fe81e000 {
	23	+ compatible = "st,sdhci";
	24	+ status = "disabled";
	25	+ reg = <0xfe81e000 0x1000>;
	26	+ interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
	27	+ interrupt-names = "mmcirq";
	28	+ pinctrl-names = "default";
	29	+ pinctrl-0 = <&pinctrl_mmc0>;
	30	+ clock-names = "mmc";
	31	+ clocks = <&clk_s_a1_ls 1>;
	32	+ bus-width = <8>
	33	+};

Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt+5−7

@@ -67,7 +67,8 @@ Optional properties: · 66 unmodified lines
67	67	* card-detect-delay: Delay in milli-seconds before detecting card after card
68	68	insert event. The default value is 0.
69	69
70		−* supports-highspeed: Enables support for high speed cards (up to 50MHz)
	70	+* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 50MHz)
	71	+ (use "cap-mmc-highspeed" or "cap-sd-highspeed" instead)
71	72
72	73	* broken-cd: as documented in mmc core bindings.
73	74
@@ -98,14 +99,11 @@ board specific portions as listed below. · 24 unmodified lines
98	99	clock-frequency = <400000000>;
99	100	clock-freq-min-max = <400000 200000000>;
100	101	num-slots = <1>;
101		− supports-highspeed;
102	102	broken-cd;
103	103	fifo-depth = <0x80>;
104	104	card-detect-delay = <200>;
105	105	vmmc-supply = <&buck8>;
106		−
107		− slot@0 {
108		− reg = <0>;
109		− bus-width = <8>;
110		− };
	106	+ bus-width = <8>;
	107	+ cap-mmc-highspeed;
	108	+ cap-sd-highspeed;
111	109	};

Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt+54−0

@@ -12,6 +12,7 @@ Required properties: · 11 unmodified lines
12	12	Should be "ti,omap3-hsmmc", for OMAP3 controllers
13	13	Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
14	14	Should be "ti,omap4-hsmmc", for OMAP4 controllers
	15	+ Should be "ti,am33xx-hsmmc", for AM335x controllers
15	16	- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
16	17
17	18	Optional properties:
@@ -56,3 +57,56 @@ Examples: · 38 unmodified lines
56	57	&edma 25>;
57	58	dma-names = "tx", "rx";
58	59	};
	60	+
	61	+[workaround for missing swakeup on am33xx]
	62	+
	63	+This SOC is missing the swakeup line, it will not detect SDIO irq
	64	+while in suspend.
	65	+
	66	+ ------
	67	+ \| PRCM \|
	68	+ ------
	69	+ ^ \|
	70	+ swakeup \| \| fclk
	71	+ \| v
	72	+ ------ ------- -----
	73	+ \| card \| -- CIRQ --> \| hsmmc \| -- IRQ --> \| CPU \|
	74	+ ------ ------- -----
	75	+
	76	+In suspend the fclk is off and the module is disfunctional. Even register reads
	77	+will fail. A small logic in the host will request fclk restore, when an
	78	+external event is detected. Once the clock is restored, the host detects the
	79	+event normally. Since am33xx doesn't have this line it never wakes from
	80	+suspend.
	81	+
	82	+The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make
	83	+this work, we need to set the named pinctrl states "default" and "idle".
	84	+Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio
	85	+dat1. The MMC driver will then toggle between idle and default state during
	86	+runtime.
	87	+
	88	+In summary:
	89	+1. select matching 'compatible' section, see example below.
	90	+2. specify pinctrl states "default" and "idle", "sleep" is optional.
	91	+3. specify the gpio irq used for detecting sdio irq in suspend
	92	+
	93	+If configuration is incomplete, a warning message is emitted "falling back to
	94	+polling". Also check the "sdio irq mode" in /sys/kernel/debug/mmc0/regs. Mind
	95	+not every application needs SDIO irq, e.g. MMC cards.
	96	+
	97	+ mmc1: mmc@48060100 {
	98	+ compatible = "ti,am33xx-hsmmc";
	99	+ ...
	100	+ pinctrl-names = "default", "idle", "sleep"
	101	+ pinctrl-0 = <&mmc1_pins>;
	102	+ pinctrl-1 = <&mmc1_idle>;
	103	+ pinctrl-2 = <&mmc1_sleep>;
	104	+ ...
	105	+ interrupts-extended = <&intc 64 &gpio2 28 0>;
	106	+ };
	107	+
	108	+ mmc1_idle : pinmux_cirq_pin {
	109	+ pinctrl-single,pins = <
	110	+ 0x0f8 0x3f /* GPIO2_28 */
	111	+ >;
	112	+ };

Documentation/devicetree/bindings/mmc/tmio_mmc.txt+1−0

@@ -18,6 +18,7 @@ Required properties: · 17 unmodified lines
18	18	"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
19	19	"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
20	20	"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
	21	+ "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
21	22
22	23	Optional properties:
23	24	- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable

drivers/mmc/card/block.c+3−3

@@ -2028,8 +2028,7 @@ static int mmc_blk_issue_rq(struct mmc_queue mq, struct request req) · 2027 unmodified lines
2028	2028	/* complete ongoing async transfer before issuing discard */
2029	2029	if (card->host->areq)
2030	2030	mmc_blk_issue_rw_rq(mq, NULL);
2031		− if (req->cmd_flags & REQ_SECURE &&
2032		− !(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN))
	2031	+ if (req->cmd_flags & REQ_SECURE)
2033	2032	ret = mmc_blk_issue_secdiscard_rq(mq, req);
2034	2033	else
2035	2034	ret = mmc_blk_issue_discard_rq(mq, req);
@@ -2432,6 +2431,8 @@ static int mmc_blk_probe(struct mmc_card *card) · 396 unmodified lines
2432	2431	if (!(card->csd.cmdclass & CCC_BLOCK_READ))
2433	2432	return -ENODEV;
2434	2433
	2434	+ mmc_fixup_device(card, blk_fixups);
	2435	+
2435	2436	md = mmc_blk_alloc(card);
2436	2437	if (IS_ERR(md))
2437	2438	return PTR_ERR(md);
@@ -2446,7 +2447,6 @@ static int mmc_blk_probe(struct mmc_card *card) · 8 unmodified lines
2446	2447	goto out;
2447	2448
2448	2449	mmc_set_drvdata(card, md);
2449		− mmc_fixup_device(card, blk_fixups);
2450	2450
2451	2451	if (mmc_add_disk(md))
2452	2452	goto out;

drivers/mmc/core/bus.c+1−9

@@ -180,7 +180,6 @@ static int mmc_bus_resume(struct device *dev) · 179 unmodified lines
180	180	#endif
181	181
182	182	#ifdef CONFIG_PM_RUNTIME
183		−
184	183	static int mmc_runtime_suspend(struct device *dev)
185	184	{
186	185	struct mmc_card *card = mmc_dev_to_card(dev);
@@ -196,17 +195,10 @@ static int mmc_runtime_resume(struct device *dev) · 9 unmodified lines
196	195
197	196	return host->bus_ops->runtime_resume(host);
198	197	}
199		−
200		−static int mmc_runtime_idle(struct device *dev)
201		−{
202		− return 0;
203		−}
204		−
205	198	#endif /* !CONFIG_PM_RUNTIME */
206	199
207	200	static const struct dev_pm_ops mmc_bus_pm_ops = {
208		− SET_RUNTIME_PM_OPS(mmc_runtime_suspend, mmc_runtime_resume,
209		− mmc_runtime_idle)
	201	+ SET_RUNTIME_PM_OPS(mmc_runtime_suspend, mmc_runtime_resume, NULL)
210	202	SET_SYSTEM_SLEEP_PM_OPS(mmc_bus_suspend, mmc_bus_resume)
211	203	};
212	204

drivers/mmc/core/core.c+2−1

@@ -2102,7 +2102,8 @@ EXPORT_SYMBOL(mmc_can_sanitize); · 2101 unmodified lines
2102	2102
2103	2103	int mmc_can_secure_erase_trim(struct mmc_card *card)
2104	2104	{
2105		− if (card->ext_csd.sec_feature_support & EXT_CSD_SEC_ER_EN)
	2105	+ if ((card->ext_csd.sec_feature_support & EXT_CSD_SEC_ER_EN) &&
	2106	+ !(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN))
2106	2107	return 1;
2107	2108	return 0;
2108	2109	}

drivers/mmc/core/mmc.c+5−6

@@ -324,13 +324,12 @@ static int mmc_read_ext_csd(struct mmc_card card, u8 ext_csd) · 323 unmodified lines
324	324	}
325	325	}
326	326
	327	+ /*
	328	+ * The EXT_CSD format is meant to be forward compatible. As long
	329	+ * as CSD_STRUCTURE does not change, all values for EXT_CSD_REV
	330	+ * are authorized, see JEDEC JESD84-B50 section B.8.
	331	+ */
327	332	card->ext_csd.rev = ext_csd[EXT_CSD_REV];
328		− if (card->ext_csd.rev > 7) {
329		− pr_err("%s: unrecognised EXT_CSD revision %d\n",
330		− mmc_hostname(card->host), card->ext_csd.rev);
331		− err = -EINVAL;
332		− goto out;
333		− }
334	333
335	334	card->ext_csd.raw_sectors[0] = ext_csd[EXT_CSD_SEC_CNT + 0];
336	335	card->ext_csd.raw_sectors[1] = ext_csd[EXT_CSD_SEC_CNT + 1];

drivers/mmc/core/quirks.c+1−1

@@ -91,7 +91,7 @@ void mmc_fixup_device(struct mmc_card card, const struct mmc_fixup table) · 90 unmodified lines
91	91	(f->cis_device == card->cis.device \|\|
92	92	f->cis_device == (u16) SDIO_ANY_ID) &&
93	93	rev >= f->rev_start && rev <= f->rev_end) {
94		− dev_dbg(&card->dev, "calling %pF\n", f->vendor_fixup);
	94	+ dev_dbg(&card->dev, "calling %pf\n", f->vendor_fixup);
95	95	f->vendor_fixup(card, f->data);
96	96	}
97	97	}

drivers/mmc/core/sd_ops.c+3−0

@@ -184,6 +184,9 @@ int mmc_send_app_op_cond(struct mmc_host host, u32 ocr, u32 rocr) · 183 unmodified lines
184	184	mmc_delay(10);
185	185	}
186	186
	187	+ if (!i)
	188	+ pr_err("%s: card never left busy state\n", mmc_hostname(host));
	189	+
187	190	if (rocr && !mmc_host_is_spi(host))
188	191	*rocr = cmd.resp[0];
189	192

drivers/mmc/host/Kconfig+17−11

@@ -290,6 +290,18 @@ config MMC_MOXART · 289 unmodified lines
290	290	be found on some embedded hardware such as UC-7112-LX.
291	291	If you have a controller with this interface, say Y here.
292	292
	293	+config MMC_SDHCI_ST
	294	+ tristate "SDHCI support on STMicroelectronics SoC"
	295	+ depends on ARCH_STI
	296	+ depends on MMC_SDHCI_PLTFM
	297	+ select MMC_SDHCI_IO_ACCESSORS
	298	+ help
	299	+ This selects the Secure Digital Host Controller Interface in
	300	+ STMicroelectronics SoCs.
	301	+
	302	+ If you have a controller with this interface, say Y or M here.
	303	+ If unsure, say N.
	304	+
293	305	config MMC_OMAP
294	306	tristate "TI OMAP Multimedia Card Interface support"
295	307	depends on ARCH_OMAP
@@ -303,6 +315,7 @@ config MMC_OMAP · 7 unmodified lines
303	315
304	316	config MMC_OMAP_HS
305	317	tristate "TI OMAP High Speed Multimedia Card Interface support"
	318	+ depends on HAS_DMA
306	319	depends on ARCH_OMAP2PLUS \|\| COMPILE_TEST
307	320	help
308	321	This selects the TI OMAP High Speed Multimedia card Interface.
@@ -343,7 +356,7 @@ config MMC_ATMELMCI · 34 unmodified lines
343	356
344	357	config MMC_SDHCI_MSM
345	358	tristate "Qualcomm SDHCI Controller Support"
346		− depends on ARCH_QCOM
	359	+ depends on ARCH_QCOM \|\| (ARM && COMPILE_TEST)
347	360	depends on MMC_SDHCI_PLTFM
348	361	help
349	362	This selects the Secure Digital Host Controller Interface (SDHCI)
@@ -440,6 +453,7 @@ config MMC_SPI · 90 unmodified lines
440	453	config MMC_S3C
441	454	tristate "Samsung S3C SD/MMC Card Interface support"
442	455	depends on ARCH_S3C24XX
	456	+ depends on S3C24XX_DMAC
443	457	help
444	458	This selects a driver for the MCI interface found in
445	459	Samsung's S3C2410, S3C2412, S3C2440, S3C2442 CPUs.
@@ -477,15 +491,6 @@ config MMC_S3C_DMA · 31 unmodified lines
477	491	working properly and needs to be debugged before this
478	492	option is useful.
479	493
480		−config MMC_S3C_PIODMA
481		− bool "Support for both PIO and DMA"
482		− help
483		− Compile both the PIO and DMA transfer routines into the
484		− driver and let the platform select at run-time which one
485		− is best.
486		−
487		− See notes for the DMA option.
488		−
489	494	endchoice
490	495
491	496	config MMC_SDRICOH_CS
@@ -623,7 +628,7 @@ config MMC_DW_PCI · 131 unmodified lines
623	628
624	629	config MMC_SH_MMCIF
625	630	tristate "SuperH Internal MMCIF support"
626		− depends on MMC_BLOCK
	631	+ depends on MMC_BLOCK && HAS_DMA
627	632	depends on SUPERH \|\| ARCH_SHMOBILE \|\| COMPILE_TEST
628	633	help
629	634	This selects the MMC Host Interface controller (MMCIF).
@@ -697,6 +702,7 @@ config MMC_WMT · 67 unmodified lines
697	702
698	703	config MMC_USDHI6ROL0
699	704	tristate "Renesas USDHI6ROL0 SD/SDIO Host Controller support"
	705	+ depends on HAS_DMA
700	706	help
701	707	This selects support for the Renesas USDHI6ROL0 SD/SDIO
702	708	Host Controller

drivers/mmc/host/Makefile+1−0

@@ -68,6 +68,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o · 67 unmodified lines
68	68	obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
69	69	obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
70	70	obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
	71	+obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
71	72
72	73	ifeq ($(CONFIG_CB710_DEBUG),y)
73	74	CFLAGS-cb710-mmc += -DDEBUG

drivers/mmc/host/dw_mmc.c+73−25

@@ -111,8 +111,7 @@ static const u8 tuning_blk_pattern_8bit[] = { · 110 unmodified lines
111	111	0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
112	112	};
113	113
114		−static inline bool dw_mci_fifo_reset(struct dw_mci *host);
115		−static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
	114	+static bool dw_mci_reset(struct dw_mci *host);
116	115
117	116	#if defined(CONFIG_DEBUG_FS)
118	117	static int dw_mci_req_show(struct seq_file s, void v)
@@ -997,7 +996,8 @@ static int dw_mci_get_ro(struct mmc_host *mmc) · 878 unmodified lines
997	996	int gpio_ro = mmc_gpio_get_ro(mmc);
998	997
999	998	/* Use platform get_ro function, else try on board write protect */
1000		− if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
	999	+ if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) \|\|
	1000	+ (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1001	1001	read_only = 0;
1002	1002	else if (!IS_ERR_VALUE(gpio_ro))
1003	1003	read_only = gpio_ro;
@@ -1235,7 +1235,7 @@ static int dw_mci_data_complete(struct dw_mci host, struct mmc_data data) · 231 unmodified lines
1235	1235	* After an error, there may be data lingering
1236	1236	* in the FIFO
1237	1237	*/
1238		− dw_mci_fifo_reset(host);
	1238	+ dw_mci_reset(host);
1239	1239	} else {
1240	1240	data->bytes_xfered = data->blocks * data->blksz;
1241	1241	data->error = 0;
@@ -1352,7 +1352,7 @@ static void dw_mci_tasklet_func(unsigned long priv) · 110 unmodified lines
1352	1352
1353	1353	/* CMD error in data command */
1354	1354	if (mrq->cmd->error && mrq->data)
1355		− dw_mci_fifo_reset(host);
	1355	+ dw_mci_reset(host);
1356	1356
1357	1357	host->cmd = NULL;
1358	1358	host->data = NULL;
@@ -1963,14 +1963,8 @@ static void dw_mci_work_routine_card(struct work_struct *work) · 604 unmodified lines
1963	1963	}
1964	1964
1965	1965	/* Power down slot */
1966		− if (present == 0) {
1967		− /* Clear down the FIFO */
1968		− dw_mci_fifo_reset(host);
1969		−#ifdef CONFIG_MMC_DW_IDMAC
1970		− dw_mci_idmac_reset(host);
1971		−#endif
1972		−
1973		− }
	1966	+ if (present == 0)
	1967	+ dw_mci_reset(host);
1974	1968
1975	1969	spin_unlock_bh(&host->lock);
1976	1970
@@ -2021,8 +2015,11 @@ static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) · 44 unmodified lines
2021	2015
2022	2016	/* get quirks */
2023	2017	for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2024		− if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
	2018	+ if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
	2019	+ dev_warn(dev, "Slot quirk %s is deprecated\n",
	2020	+ of_slot_quirks[idx].quirk);
2025	2021	quirks \|= of_slot_quirks[idx].id;
	2022	+ }
2026	2023
2027	2024	return quirks;
2028	2025	}
@@ -2208,8 +2205,11 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) · 179 unmodified lines
2208	2205	return false;
2209	2206	}
2210	2207
2211		−static inline bool dw_mci_fifo_reset(struct dw_mci *host)
	2208	+static bool dw_mci_reset(struct dw_mci *host)
2212	2209	{
	2210	+ u32 flags = SDMMC_CTRL_RESET \| SDMMC_CTRL_FIFO_RESET;
	2211	+ bool ret = false;
	2212	+
2213	2213	/*
2214	2214	* Reseting generates a block interrupt, hence setting
2215	2215	* the scatter-gather pointer to NULL.
@@ -2219,15 +2219,60 @@ static inline bool dw_mci_fifo_reset(struct dw_mci *host) · 3 unmodified lines
2219	2219	host->sg = NULL;
2220	2220	}
2221	2221
2222		− return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
2223		−}
	2222	+ if (host->use_dma)
	2223	+ flags \|= SDMMC_CTRL_DMA_RESET;
2224	2224
2225		−static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
2226		−{
2227		− return dw_mci_ctrl_reset(host,
2228		− SDMMC_CTRL_FIFO_RESET \|
2229		− SDMMC_CTRL_RESET \|
2230		− SDMMC_CTRL_DMA_RESET);
	2225	+ if (dw_mci_ctrl_reset(host, flags)) {
	2226	+ /*
	2227	+ * In all cases we clear the RAWINTS register to clear any
	2228	+ * interrupts.
	2229	+ */
	2230	+ mci_writel(host, RINTSTS, 0xFFFFFFFF);
	2231	+
	2232	+ /* if using dma we wait for dma_req to clear */
	2233	+ if (host->use_dma) {
	2234	+ unsigned long timeout = jiffies + msecs_to_jiffies(500);
	2235	+ u32 status;
	2236	+ do {
	2237	+ status = mci_readl(host, STATUS);
	2238	+ if (!(status & SDMMC_STATUS_DMA_REQ))
	2239	+ break;
	2240	+ cpu_relax();
	2241	+ } while (time_before(jiffies, timeout));
	2242	+
	2243	+ if (status & SDMMC_STATUS_DMA_REQ) {
	2244	+ dev_err(host->dev,
	2245	+ "%s: Timeout waiting for dma_req to "
	2246	+ "clear during reset\n", __func__);
	2247	+ goto ciu_out;
	2248	+ }
	2249	+
	2250	+ /* when using DMA next we reset the fifo again */
	2251	+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
	2252	+ goto ciu_out;
	2253	+ }
	2254	+ } else {
	2255	+ /* if the controller reset bit did clear, then set clock regs */
	2256	+ if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
	2257	+ dev_err(host->dev, "%s: fifo/dma reset bits didn't "
	2258	+ "clear but ciu was reset, doing clock update\n",
	2259	+ __func__);
	2260	+ goto ciu_out;
	2261	+ }
	2262	+ }
	2263	+
	2264	+#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
	2265	+ /* It is also recommended that we reset and reprogram idmac */
	2266	+ dw_mci_idmac_reset(host);
	2267	+#endif
	2268	+
	2269	+ ret = true;
	2270	+
	2271	+ciu_out:
	2272	+ /* After a CTRL reset we need to have CIU set clock registers */
	2273	+ mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
	2274	+
	2275	+ return ret;
2231	2276	}
2232	2277
2233	2278	#ifdef CONFIG_OF
@@ -2238,6 +2283,9 @@ static struct dw_mci_of_quirks { · 4 unmodified lines
2238	2283	{
2239	2284	.quirk = "broken-cd",
2240	2285	.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
	2286	+ }, {
	2287	+ .quirk = "disable-wp",
	2288	+ .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2241	2289	},
2242	2290	};
2243	2291
@@ -2425,7 +2473,7 @@ int dw_mci_probe(struct dw_mci *host) · 181 unmodified lines
2425	2473	}
2426	2474
2427	2475	/* Reset all blocks */
2428		− if (!dw_mci_ctrl_all_reset(host))
	2476	+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2429	2477	return -ENODEV;
2430	2478
2431	2479	host->dma_ops = host->pdata->dma_ops;
@@ -2612,7 +2660,7 @@ int dw_mci_resume(struct dw_mci *host) · 180 unmodified lines
2612	2660	}
2613	2661	}
2614	2662
2615		− if (!dw_mci_ctrl_all_reset(host)) {
	2663	+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2616	2664	ret = -ENODEV;
2617	2665	return ret;
2618	2666	}

drivers/mmc/host/dw_mmc.h+5−0

@@ -129,6 +129,7 @@ · 128 unmodified lines
129	129	#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
130	130	/* Status register defines */
131	131	#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
	132	+#define SDMMC_STATUS_DMA_REQ BIT(31)
132	133	/* FIFOTH register defines */
133	134	#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 \| \
134	135	((r) & 0xFFF) << 16 \| \
@@ -150,6 +151,10 @@ · 15 unmodified lines
150	151	/* Card read threshold */
151	152	#define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 \| (x))
152	153
	154	+/* All ctrl reset bits */
	155	+#define SDMMC_CTRL_ALL_RESET_FLAGS \
	156	+ (SDMMC_CTRL_RESET \| SDMMC_CTRL_FIFO_RESET \| SDMMC_CTRL_DMA_RESET)
	157	+
153	158	/* Register access macros */
154	159	#define mci_readl(dev, reg) \
155	160	__raw_readl((dev)->regs + SDMMC_##reg)

drivers/mmc/host/mmci.c+140−28

@@ -52,34 +52,53 @@ static unsigned int fmax = 515633; · 51 unmodified lines
52	52	* struct variant_data - MMCI variant-specific quirks
53	53	* @clkreg: default value for MCICLOCK register
54	54	* @clkreg_enable: enable value for MMCICLOCK register
	55	+ * @clkreg_8bit_bus_enable: enable value for 8 bit bus
	56	+ * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
55	57	* @datalength_bits: number of bits in the MMCIDATALENGTH register
56	58	* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
57	59	* is asserted (likewise for RX)
58	60	* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
59	61	* is asserted (likewise for RX)
	62	+ * @data_cmd_enable: enable value for data commands.
60	63	* @sdio: variant supports SDIO
61	64	* @st_clkdiv: true if using a ST-specific clock divider algorithm
	65	+ * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
62	66	* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
	67	+ * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
	68	+ * register
63	69	* @pwrreg_powerup: power up value for MMCIPOWER register
	70	+ * @f_max: maximum clk frequency supported by the controller.
64	71	* @signal_direction: input/out direction of bus signals can be indicated
65	72	* @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
66	73	* @busy_detect: true if busy detection on dat0 is supported
67	74	* @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
	75	+ * @explicit_mclk_control: enable explicit mclk control in driver.
	76	+ * @qcom_fifo: enables qcom specific fifo pio read logic.
	77	+ * @reversed_irq_handling: handle data irq before cmd irq.
68	78	*/
69	79	struct variant_data {
70	80	unsigned int clkreg;
71	81	unsigned int clkreg_enable;
	82	+ unsigned int clkreg_8bit_bus_enable;
	83	+ unsigned int clkreg_neg_edge_enable;
72	84	unsigned int datalength_bits;
73	85	unsigned int fifosize;
74	86	unsigned int fifohalfsize;
	87	+ unsigned int data_cmd_enable;
	88	+ unsigned int datactrl_mask_ddrmode;
75	89	bool sdio;
76	90	bool st_clkdiv;
77	91	bool blksz_datactrl16;
	92	+ bool blksz_datactrl4;
78	93	u32 pwrreg_powerup;
	94	+ u32 f_max;
79	95	bool signal_direction;
80	96	bool pwrreg_clkgate;
81	97	bool busy_detect;
82	98	bool pwrreg_nopower;
	99	+ bool explicit_mclk_control;
	100	+ bool qcom_fifo;
	101	+ bool reversed_irq_handling;
83	102	};
84	103
85	104	static struct variant_data variant_arm = {
@@ -87,6 +106,8 @@ static struct variant_data variant_arm = { · 1 unmodified line
87	106	.fifohalfsize = 8 * 4,
88	107	.datalength_bits = 16,
89	108	.pwrreg_powerup = MCI_PWR_UP,
	109	+ .f_max = 100000000,
	110	+ .reversed_irq_handling = true,
90	111	};
91	112
92	113	static struct variant_data variant_arm_extended_fifo = {
@@ -94,6 +115,7 @@ static struct variant_data variant_arm_extended_fifo = { · 1 unmodified line
94	115	.fifohalfsize = 64 * 4,
95	116	.datalength_bits = 16,
96	117	.pwrreg_powerup = MCI_PWR_UP,
	118	+ .f_max = 100000000,
97	119	};
98	120
99	121	static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -102,15 +124,18 @@ static struct variant_data variant_arm_extended_fifo_hwfc = { · 2 unmodified lines
102	124	.clkreg_enable = MCI_ARM_HWFCEN,
103	125	.datalength_bits = 16,
104	126	.pwrreg_powerup = MCI_PWR_UP,
	127	+ .f_max = 100000000,
105	128	};
106	129
107	130	static struct variant_data variant_u300 = {
108	131	.fifosize = 16 * 4,
109	132	.fifohalfsize = 8 * 4,
110	133	.clkreg_enable = MCI_ST_U300_HWFCEN,
	134	+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
111	135	.datalength_bits = 16,
112	136	.sdio = true,
113	137	.pwrreg_powerup = MCI_PWR_ON,
	138	+ .f_max = 100000000,
114	139	.signal_direction = true,
115	140	.pwrreg_clkgate = true,
116	141	.pwrreg_nopower = true,
@@ -124,6 +149,7 @@ static struct variant_data variant_nomadik = { · 7 unmodified lines
124	149	.sdio = true,
125	150	.st_clkdiv = true,
126	151	.pwrreg_powerup = MCI_PWR_ON,
	152	+ .f_max = 100000000,
127	153	.signal_direction = true,
128	154	.pwrreg_clkgate = true,
129	155	.pwrreg_nopower = true,
@@ -134,10 +160,13 @@ static struct variant_data variant_ux500 = { · 4 unmodified lines
134	160	.fifohalfsize = 8 * 4,
135	161	.clkreg = MCI_CLK_ENABLE,
136	162	.clkreg_enable = MCI_ST_UX500_HWFCEN,
	163	+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
	164	+ .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
137	165	.datalength_bits = 24,
138	166	.sdio = true,
139	167	.st_clkdiv = true,
140	168	.pwrreg_powerup = MCI_PWR_ON,
	169	+ .f_max = 100000000,
141	170	.signal_direction = true,
142	171	.pwrreg_clkgate = true,
143	172	.busy_detect = true,
@@ -149,17 +178,38 @@ static struct variant_data variant_ux500v2 = { · 5 unmodified lines
149	178	.fifohalfsize = 8 * 4,
150	179	.clkreg = MCI_CLK_ENABLE,
151	180	.clkreg_enable = MCI_ST_UX500_HWFCEN,
	181	+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
	182	+ .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
	183	+ .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
152	184	.datalength_bits = 24,
153	185	.sdio = true,
154	186	.st_clkdiv = true,
155	187	.blksz_datactrl16 = true,
156	188	.pwrreg_powerup = MCI_PWR_ON,
	189	+ .f_max = 100000000,
157	190	.signal_direction = true,
158	191	.pwrreg_clkgate = true,
159	192	.busy_detect = true,
160	193	.pwrreg_nopower = true,
161	194	};
162	195
	196	+static struct variant_data variant_qcom = {
	197	+ .fifosize = 16 * 4,
	198	+ .fifohalfsize = 8 * 4,
	199	+ .clkreg = MCI_CLK_ENABLE,
	200	+ .clkreg_enable = MCI_QCOM_CLK_FLOWENA \|
	201	+ MCI_QCOM_CLK_SELECT_IN_FBCLK,
	202	+ .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
	203	+ .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
	204	+ .data_cmd_enable = MCI_QCOM_CSPM_DATCMD,
	205	+ .blksz_datactrl4 = true,
	206	+ .datalength_bits = 24,
	207	+ .pwrreg_powerup = MCI_PWR_UP,
	208	+ .f_max = 208000000,
	209	+ .explicit_mclk_control = true,
	210	+ .qcom_fifo = true,
	211	+};
	212	+
163	213	static int mmci_card_busy(struct mmc_host *mmc)
164	214	{
165	215	struct mmci_host *host = mmc_priv(mmc);
@@ -260,7 +310,9 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) · 94 unmodified lines
260	310	host->cclk = 0;
261	311
262	312	if (desired) {
263		− if (desired >= host->mclk) {
	313	+ if (variant->explicit_mclk_control) {
	314	+ host->cclk = host->mclk;
	315	+ } else if (desired >= host->mclk) {
264	316	clk = MCI_CLK_BYPASS;
265	317	if (variant->st_clkdiv)
266	318	clk \|= MCI_ST_UX500_NEG_EDGE;
@@ -299,11 +351,11 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) · 32 unmodified lines
299	351	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
300	352	clk \|= MCI_4BIT_BUS;
301	353	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
302		− clk \|= MCI_ST_8BIT_BUS;
	354	+ clk \|= variant->clkreg_8bit_bus_enable;
303	355
304	356	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 \|\|
305	357	host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
306		− clk \|= MCI_ST_UX500_NEG_EDGE;
	358	+ clk \|= variant->clkreg_neg_edge_enable;
307	359
308	360	mmci_write_clkreg(host, clk);
309	361	}
@@ -719,7 +771,7 @@ static void mmci_start_data(struct mmci_host host, struct mmc_data data) · 409 unmodified lines
719	771	data->bytes_xfered = 0;
720	772
721	773	clks = (unsigned long long)data->timeout_ns * host->cclk;
722		− do_div(clks, 1000000000UL);
	774	+ do_div(clks, NSEC_PER_SEC);
723	775
724	776	timeout = data->timeout_clks + (unsigned int)clks;
725	777
@@ -732,6 +784,8 @@ static void mmci_start_data(struct mmci_host host, struct mmc_data data) · 6 unmodified lines
732	784
733	785	if (variant->blksz_datactrl16)
734	786	datactrl = MCI_DPSM_ENABLE \| (data->blksz << 16);
	787	+ else if (variant->blksz_datactrl4)
	788	+ datactrl = MCI_DPSM_ENABLE \| (data->blksz << 4);
735	789	else
736	790	datactrl = MCI_DPSM_ENABLE \| blksz_bits << 4;
737	791
@@ -767,7 +821,7 @@ static void mmci_start_data(struct mmci_host host, struct mmc_data data) · 29 unmodified lines
767	821
768	822	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 \|\|
769	823	host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
770		− datactrl \|= MCI_ST_DPSM_DDRMODE;
	824	+ datactrl \|= variant->datactrl_mask_ddrmode;
771	825
772	826	/*
773	827	* Attempt to use DMA operation mode, if this
@@ -812,7 +866,7 @@ mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c) · 38 unmodified lines
812	866
813	867	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
814	868	writel(0, base + MMCICOMMAND);
815		− udelay(1);
	869	+ mmci_reg_delay(host);
816	870	}
817	871
818	872	c \|= cmd->opcode \| MCI_CPSM_ENABLE;
@@ -824,6 +878,9 @@ mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c) · 5 unmodified lines
824	878	if (/interrupt/0)
825	879	c \|= MCI_CPSM_INTERRUPT;
826	880
	881	+ if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
	882	+ c \|= host->variant->data_cmd_enable;
	883	+
827	884	host->cmd = cmd;
828	885
829	886	writel(cmd->arg, base + MMCIARGUMENT);
@@ -834,6 +891,10 @@ static void · 4 unmodified lines
834	891	mmci_data_irq(struct mmci_host host, struct mmc_data data,
835	892	unsigned int status)
836	893	{
	894	+ /* Make sure we have data to handle */
	895	+ if (!data)
	896	+ return;
	897	+
837	898	/* First check for errors */
838	899	if (status & (MCI_DATACRCFAIL\|MCI_DATATIMEOUT\|MCI_STARTBITERR\|
839	900	MCI_TXUNDERRUN\|MCI_RXOVERRUN)) {
@@ -902,9 +963,17 @@ mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd, · 62 unmodified lines
902	963	unsigned int status)
903	964	{
904	965	void __iomem *base = host->base;
905		− bool sbc = (cmd == host->mrq->sbc);
906		− bool busy_resp = host->variant->busy_detect &&
907		− (cmd->flags & MMC_RSP_BUSY);
	966	+ bool sbc, busy_resp;
	967	+
	968	+ if (!cmd)
	969	+ return;
	970	+
	971	+ sbc = (cmd == host->mrq->sbc);
	972	+ busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY);
	973	+
	974	+ if (!((status\|host->busy_status) & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|
	975	+ MCI_CMDSENT\|MCI_CMDRESPEND)))
	976	+ return;
908	977
909	978	/* Check if we need to wait for busy completion. */
910	979	if (host->busy_status && (status & MCI_ST_CARDBUSY))
@@ -957,15 +1026,34 @@ mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd, · 46 unmodified lines
957	1026	}
958	1027	}
959	1028
	1029	+static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
	1030	+{
	1031	+ return remain - (readl(host->base + MMCIFIFOCNT) << 2);
	1032	+}
	1033	+
	1034	+static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
	1035	+{
	1036	+ /*
	1037	+ * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
	1038	+ * from the fifo range should be used
	1039	+ */
	1040	+ if (status & MCI_RXFIFOHALFFULL)
	1041	+ return host->variant->fifohalfsize;
	1042	+ else if (status & MCI_RXDATAAVLBL)
	1043	+ return 4;
	1044	+
	1045	+ return 0;
	1046	+}
	1047	+
960	1048	static int mmci_pio_read(struct mmci_host host, char buffer, unsigned int remain)
961	1049	{
962	1050	void __iomem *base = host->base;
963	1051	char *ptr = buffer;
964		− u32 status;
	1052	+ u32 status = readl(host->base + MMCISTATUS);
965	1053	int host_remain = host->size;
966	1054
967	1055	do {
968		− int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
	1056	+ int count = host->get_rx_fifocnt(host, status, host_remain);
969	1057
970	1058	if (count > remain)
971	1059	count = remain;
@@ -1132,9 +1220,6 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) · 160 unmodified lines
1132	1220	spin_lock(&host->lock);
1133	1221
1134	1222	do {
1135		− struct mmc_command *cmd;
1136		− struct mmc_data *data;
1137		−
1138	1223	status = readl(host->base + MMCISTATUS);
1139	1224
1140	1225	if (host->singleirq) {
@@ -1154,16 +1239,13 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) · 13 unmodified lines
1154	1239
1155	1240	dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1156	1241
1157		− cmd = host->cmd;
1158		− if ((status\|host->busy_status) & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|
1159		− MCI_CMDSENT\|MCI_CMDRESPEND) && cmd)
1160		− mmci_cmd_irq(host, cmd, status);
1161		−
1162		− data = host->data;
1163		− if (status & (MCI_DATACRCFAIL\|MCI_DATATIMEOUT\|MCI_STARTBITERR\|
1164		− MCI_TXUNDERRUN\|MCI_RXOVERRUN\|MCI_DATAEND\|
1165		− MCI_DATABLOCKEND) && data)
1166		− mmci_data_irq(host, data, status);
	1242	+ if (host->variant->reversed_irq_handling) {
	1243	+ mmci_data_irq(host, host->data, status);
	1244	+ mmci_cmd_irq(host, host->cmd, status);
	1245	+ } else {
	1246	+ mmci_cmd_irq(host, host->cmd, status);
	1247	+ mmci_data_irq(host, host->data, status);
	1248	+ }
1167	1249
1168	1250	/* Don't poll for busy completion in irq context. */
1169	1251	if (host->busy_status)
@@ -1296,6 +1378,17 @@ static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios) · 126 unmodified lines
1296	1378	if (!ios->clock && variant->pwrreg_clkgate)
1297	1379	pwr &= ~MCI_PWR_ON;
1298	1380
	1381	+ if (host->variant->explicit_mclk_control &&
	1382	+ ios->clock != host->clock_cache) {
	1383	+ ret = clk_set_rate(host->clk, ios->clock);
	1384	+ if (ret < 0)
	1385	+ dev_err(mmc_dev(host->mmc),
	1386	+ "Error setting clock rate (%d)\n", ret);
	1387	+ else
	1388	+ host->mclk = clk_get_rate(host->clk);
	1389	+ }
	1390	+ host->clock_cache = ios->clock;
	1391	+
1299	1392	spin_lock_irqsave(&host->lock, flags);
1300	1393
1301	1394	mmci_set_clkreg(host, ios->clock);
@@ -1443,6 +1536,11 @@ static int mmci_probe(struct amba_device *dev, · 141 unmodified lines
1443	1536	if (ret)
1444	1537	goto host_free;
1445	1538
	1539	+ if (variant->qcom_fifo)
	1540	+ host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
	1541	+ else
	1542	+ host->get_rx_fifocnt = mmci_get_rx_fifocnt;
	1543	+
1446	1544	host->plat = plat;
1447	1545	host->variant = variant;
1448	1546	host->mclk = clk_get_rate(host->clk);
@@ -1451,8 +1549,8 @@ static int mmci_probe(struct amba_device *dev, · 2 unmodified lines
1451	1549	* so we try to adjust the clock down to this,
1452	1550	* (if possible).
1453	1551	*/
1454		− if (host->mclk > 100000000) {
1455		− ret = clk_set_rate(host->clk, 100000000);
	1552	+ if (host->mclk > variant->f_max) {
	1553	+ ret = clk_set_rate(host->clk, variant->f_max);
1456	1554	if (ret < 0)
1457	1555	goto clk_disable;
1458	1556	host->mclk = clk_get_rate(host->clk);
@@ -1471,9 +1569,12 @@ static int mmci_probe(struct amba_device *dev, · 12 unmodified lines
1471	1569	* The ARM and ST versions of the block have slightly different
1472	1570	* clock divider equations which means that the minimum divider
1473	1571	* differs too.
	1572	+ * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1474	1573	*/
1475	1574	if (variant->st_clkdiv)
1476	1575	mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
	1576	+ else if (variant->explicit_mclk_control)
	1577	+ mmc->f_min = clk_round_rate(host->clk, 100000);
1477	1578	else
1478	1579	mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1479	1580	/*
@@ -1483,9 +1584,14 @@ static int mmci_probe(struct amba_device *dev, · 3 unmodified lines
1483	1584	* the block, of course.
1484	1585	*/
1485	1586	if (mmc->f_max)
1486		− mmc->f_max = min(host->mclk, mmc->f_max);
	1587	+ mmc->f_max = variant->explicit_mclk_control ?
	1588	+ min(variant->f_max, mmc->f_max) :
	1589	+ min(host->mclk, mmc->f_max);
1487	1590	else
1488		− mmc->f_max = min(host->mclk, fmax);
	1591	+ mmc->f_max = variant->explicit_mclk_control ?
	1592	+ fmax : min(host->mclk, fmax);
	1593	+
	1594	+
1489	1595	dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1490	1596
1491	1597	/* Get regulators and the supported OCR mask */
@@ -1752,6 +1858,12 @@ static struct amba_id mmci_ids[] = { · 260 unmodified lines
1752	1858	.mask = 0xf0ffffff,
1753	1859	.data = &variant_ux500v2,
1754	1860	},
	1861	+ /* Qualcomm variants */
	1862	+ {
	1863	+ .id = 0x00051180,
	1864	+ .mask = 0x000fffff,
	1865	+ .data = &variant_qcom,
	1866	+ },
1755	1867	{ 0, 0 },
1756	1868	};
1757	1869

drivers/mmc/host/mmci.h+20−0

@@ -41,6 +41,15 @@ · 40 unmodified lines
41	41	/* Modified PL180 on Versatile Express platform */
42	42	#define MCI_ARM_HWFCEN (1 << 12)
43	43
	44	+/* Modified on Qualcomm Integrations */
	45	+#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) \| BIT(11))
	46	+#define MCI_QCOM_CLK_FLOWENA BIT(12)
	47	+#define MCI_QCOM_CLK_INVERTOUT BIT(13)
	48	+
	49	+/* select in latch data and command in */
	50	+#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
	51	+#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) \| BIT(15))
	52	+
44	53	#define MMCIARGUMENT 0x008
45	54	#define MMCICOMMAND 0x00c
46	55	#define MCI_CPSM_RESPONSE (1 << 6)
@@ -54,6 +63,14 @@ · 7 unmodified lines
54	63	#define MCI_ST_NIEN (1 << 13)
55	64	#define MCI_ST_CE_ATACMD (1 << 14)
56	65
	66	+/* Modified on Qualcomm Integrations */
	67	+#define MCI_QCOM_CSPM_DATCMD BIT(12)
	68	+#define MCI_QCOM_CSPM_MCIABORT BIT(13)
	69	+#define MCI_QCOM_CSPM_CCSENABLE BIT(14)
	70	+#define MCI_QCOM_CSPM_CCSDISABLE BIT(15)
	71	+#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16)
	72	+#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21)
	73	+
57	74	#define MMCIRESPCMD 0x010
58	75	#define MMCIRESPONSE0 0x014
59	76	#define MMCIRESPONSE1 0x018
@@ -191,6 +208,8 @@ struct mmci_host { · 131 unmodified lines
191	208	spinlock_t lock;
192	209
193	210	unsigned int mclk;
	211	+ /* cached value of requested clk in set_ios */
	212	+ unsigned int clock_cache;
194	213	unsigned int cclk;
195	214	u32 pwr_reg;
196	215	u32 pwr_reg_add;
@@ -210,6 +229,7 @@ struct mmci_host { · 13 unmodified lines
210	229	/* pio stuff */
211	230	struct sg_mapping_iter sg_miter;
212	231	unsigned int size;
	232	+ int (get_rx_fifocnt)(struct mmci_host h, u32 status, int remain);
213	233
214	234	#ifdef CONFIG_DMA_ENGINE
215	235	/* DMA stuff */

drivers/mmc/host/moxart-mmc.c+0−1

@@ -13,7 +13,6 @@ · 12 unmodified lines
13	13	* warranty of any kind, whether express or implied.
14	14	*/
15	15
16		−#include <linux/version.h>
17	16	#include <linux/module.h>
18	17	#include <linux/init.h>
19	18	#include <linux/platform_device.h>

drivers/mmc/host/mxs-mmc.c+2−1

@@ -86,7 +86,8 @@ static int mxs_mmc_get_cd(struct mmc_host *mmc) · 85 unmodified lines
86	86	if (ret >= 0)
87	87	return ret;
88	88
89		− present = !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
	89	+ present = mmc->caps & MMC_CAP_NEEDS_POLL \|\|
	90	+ !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
90	91	BM_SSP_STATUS_CARD_DETECT);
91	92
92	93	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)

drivers/mmc/host/omap_hsmmc.c+262−21

@@ -29,6 +29,7 @@ · 28 unmodified lines
29	29	#include <linux/timer.h>
30	30	#include <linux/clk.h>
31	31	#include <linux/of.h>
	32	+#include <linux/of_irq.h>
32	33	#include <linux/of_gpio.h>
33	34	#include <linux/of_device.h>
34	35	#include <linux/omap-dmaengine.h>
@@ -36,6 +37,7 @@ · 1 unmodified line
36	37	#include <linux/mmc/core.h>
37	38	#include <linux/mmc/mmc.h>
38	39	#include <linux/io.h>
	40	+#include <linux/irq.h>
39	41	#include <linux/gpio.h>
40	42	#include <linux/regulator/consumer.h>
41	43	#include <linux/pinctrl/consumer.h>
@@ -54,6 +56,7 @@ · 12 unmodified lines
54	56	#define OMAP_HSMMC_RSP54 0x0118
55	57	#define OMAP_HSMMC_RSP76 0x011C
56	58	#define OMAP_HSMMC_DATA 0x0120
	59	+#define OMAP_HSMMC_PSTATE 0x0124
57	60	#define OMAP_HSMMC_HCTL 0x0128
58	61	#define OMAP_HSMMC_SYSCTL 0x012C
59	62	#define OMAP_HSMMC_STAT 0x0130
@@ -91,7 +94,10 @@ · 31 unmodified lines
91	94	#define BCE (1 << 1)
92	95	#define FOUR_BIT (1 << 1)
93	96	#define HSPE (1 << 2)
	97	+#define IWE (1 << 24)
94	98	#define DDR (1 << 19)
	99	+#define CLKEXTFREE (1 << 16)
	100	+#define CTPL (1 << 11)
95	101	#define DW8 (1 << 5)
96	102	#define OD 0x1
97	103	#define STAT_CLEAR 0xFFFFFFFF
@@ -101,11 +107,15 @@ · 3 unmodified lines
101	107	#define SRD (1 << 26)
102	108	#define SOFTRESET (1 << 1)
103	109
	110	+/* PSTATE */
	111	+#define DLEV_DAT(x) (1 << (20 + (x)))
	112	+
104	113	/* Interrupt masks for IE and ISE register */
105	114	#define CC_EN (1 << 0)
106	115	#define TC_EN (1 << 1)
107	116	#define BWR_EN (1 << 4)
108	117	#define BRR_EN (1 << 5)
	118	+#define CIRQ_EN (1 << 8)
109	119	#define ERR_EN (1 << 15)
110	120	#define CTO_EN (1 << 16)
111	121	#define CCRC_EN (1 << 17)
@@ -140,7 +150,6 @@ · 28 unmodified lines
140	150	#define VDD_3V0 3000000 /* 300000 uV */
141	151	#define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
142	152
143		−#define AUTO_CMD23 (1 << 1) /* Auto CMD23 support */
144	153	/*
145	154	* One controller can have multiple slots, like on some omap boards using
146	155	* omap.c controller driver. Luckily this is not currently done on any known
@@ -194,6 +203,7 @@ struct omap_hsmmc_host { · 47 unmodified lines
194	203	u32 sysctl;
195	204	u32 capa;
196	205	int irq;
	206	+ int wake_irq;
197	207	int use_dma, dma_ch;
198	208	struct dma_chan *tx_chan;
199	209	struct dma_chan *rx_chan;
@@ -206,6 +216,9 @@ struct omap_hsmmc_host { · 6 unmodified lines
206	216	int req_in_progress;
207	217	unsigned long clk_rate;
208	218	unsigned int flags;
	219	+#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
	220	+#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
	221	+#define HSMMC_WAKE_IRQ_ENABLED (1 << 2)
209	222	struct omap_hsmmc_next next_data;
210	223	struct omap_mmc_platform_data *pdata;
211	224	};
@@ -510,27 +523,40 @@ static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) · 298 unmodified lines
510	523	static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
511	524	struct mmc_command *cmd)
512	525	{
513		− unsigned int irq_mask;
	526	+ u32 irq_mask = INT_EN_MASK;
	527	+ unsigned long flags;
514	528
515	529	if (host->use_dma)
516		− irq_mask = INT_EN_MASK & ~(BRR_EN \| BWR_EN);
517		− else
518		− irq_mask = INT_EN_MASK;
	530	+ irq_mask &= ~(BRR_EN \| BWR_EN);
519	531
520	532	/* Disable timeout for erases */
521	533	if (cmd->opcode == MMC_ERASE)
522	534	irq_mask &= ~DTO_EN;
523	535
	536	+ spin_lock_irqsave(&host->irq_lock, flags);
524	537	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
525	538	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
	539	+
	540	+ /* latch pending CIRQ, but don't signal MMC core */
	541	+ if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
	542	+ irq_mask \|= CIRQ_EN;
526	543	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
	544	+ spin_unlock_irqrestore(&host->irq_lock, flags);
527	545	}
528	546
529	547	static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
530	548	{
531		− OMAP_HSMMC_WRITE(host->base, ISE, 0);
532		− OMAP_HSMMC_WRITE(host->base, IE, 0);
	549	+ u32 irq_mask = 0;
	550	+ unsigned long flags;
	551	+
	552	+ spin_lock_irqsave(&host->irq_lock, flags);
	553	+ /* no transfer running but need to keep cirq if enabled */
	554	+ if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
	555	+ irq_mask \|= CIRQ_EN;
	556	+ OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
	557	+ OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
533	558	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	559	+ spin_unlock_irqrestore(&host->irq_lock, flags);
534	560	}
535	561
536	562	/* Calculate divisor for the given clock frequency */
@@ -667,6 +693,9 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) · 130 unmodified lines
667	693	capa = VS18;
668	694	}
669	695
	696	+ if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
	697	+ hctl \|= IWE;
	698	+
670	699	OMAP_HSMMC_WRITE(host->base, HCTL,
671	700	OMAP_HSMMC_READ(host->base, HCTL) \| hctl);
672	701
@@ -681,7 +710,9 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) · 8 unmodified lines
681	710	&& time_before(jiffies, timeout))
682	711	;
683	712
684		− omap_hsmmc_disable_irq(host);
	713	+ OMAP_HSMMC_WRITE(host->base, ISE, 0);
	714	+ OMAP_HSMMC_WRITE(host->base, IE, 0);
	715	+ OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
685	716
686	717	/* Do not initialize card-specific things if the power is off */
687	718	if (host->power_mode == MMC_POWER_OFF)
@@ -1118,8 +1149,12 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) · 430 unmodified lines
1118	1149	int status;
1119	1150
1120	1151	status = OMAP_HSMMC_READ(host->base, STAT);
1121		− while (status & INT_EN_MASK && host->req_in_progress) {
1122		− omap_hsmmc_do_irq(host, status);
	1152	+ while (status & (INT_EN_MASK \| CIRQ_EN)) {
	1153	+ if (host->req_in_progress)
	1154	+ omap_hsmmc_do_irq(host, status);
	1155	+
	1156	+ if (status & CIRQ_EN)
	1157	+ mmc_signal_sdio_irq(host->mmc);
1123	1158
1124	1159	/* Flush posted write */
1125	1160	status = OMAP_HSMMC_READ(host->base, STAT);
@@ -1128,6 +1163,22 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) · 2 unmodified lines
1128	1163	return IRQ_HANDLED;
1129	1164	}
1130	1165
	1166	+static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
	1167	+{
	1168	+ struct omap_hsmmc_host *host = dev_id;
	1169	+
	1170	+ /* cirq is level triggered, disable to avoid infinite loop */
	1171	+ spin_lock(&host->irq_lock);
	1172	+ if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
	1173	+ disable_irq_nosync(host->wake_irq);
	1174	+ host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
	1175	+ }
	1176	+ spin_unlock(&host->irq_lock);
	1177	+ pm_request_resume(host->dev); /* no use counter */
	1178	+
	1179	+ return IRQ_HANDLED;
	1180	+}
	1181	+
1131	1182	static void set_sd_bus_power(struct omap_hsmmc_host *host)
1132	1183	{
1133	1184	unsigned long i;
@@ -1639,6 +1690,103 @@ static void omap_hsmmc_init_card(struct mmc_host mmc, struct mmc_card card) · 505 unmodified lines
1639	1690	mmc_slot(host).init_card(card);
1640	1691	}
1641	1692
	1693	+static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
	1694	+{
	1695	+ struct omap_hsmmc_host *host = mmc_priv(mmc);
	1696	+ u32 irq_mask, con;
	1697	+ unsigned long flags;
	1698	+
	1699	+ spin_lock_irqsave(&host->irq_lock, flags);
	1700	+
	1701	+ con = OMAP_HSMMC_READ(host->base, CON);
	1702	+ irq_mask = OMAP_HSMMC_READ(host->base, ISE);
	1703	+ if (enable) {
	1704	+ host->flags \|= HSMMC_SDIO_IRQ_ENABLED;
	1705	+ irq_mask \|= CIRQ_EN;
	1706	+ con \|= CTPL \| CLKEXTFREE;
	1707	+ } else {
	1708	+ host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
	1709	+ irq_mask &= ~CIRQ_EN;
	1710	+ con &= ~(CTPL \| CLKEXTFREE);
	1711	+ }
	1712	+ OMAP_HSMMC_WRITE(host->base, CON, con);
	1713	+ OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
	1714	+
	1715	+ /*
	1716	+ * if enable, piggy back detection on current request
	1717	+ * but always disable immediately
	1718	+ */
	1719	+ if (!host->req_in_progress \|\| !enable)
	1720	+ OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
	1721	+
	1722	+ /* flush posted write */
	1723	+ OMAP_HSMMC_READ(host->base, IE);
	1724	+
	1725	+ spin_unlock_irqrestore(&host->irq_lock, flags);
	1726	+}
	1727	+
	1728	+static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
	1729	+{
	1730	+ struct mmc_host *mmc = host->mmc;
	1731	+ int ret;
	1732	+
	1733	+ /*
	1734	+ * For omaps with wake-up path, wakeirq will be irq from pinctrl and
	1735	+ * for other omaps, wakeirq will be from GPIO (dat line remuxed to
	1736	+ * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
	1737	+ * with functional clock disabled.
	1738	+ */
	1739	+ if (!host->dev->of_node \|\| !host->wake_irq)
	1740	+ return -ENODEV;
	1741	+
	1742	+ /* Prevent auto-enabling of IRQ */
	1743	+ irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
	1744	+ ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
	1745	+ IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	1746	+ mmc_hostname(mmc), host);
	1747	+ if (ret) {
	1748	+ dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
	1749	+ goto err;
	1750	+ }
	1751	+
	1752	+ /*
	1753	+ * Some omaps don't have wake-up path from deeper idle states
	1754	+ * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
	1755	+ */
	1756	+ if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
	1757	+ struct pinctrl *p = devm_pinctrl_get(host->dev);
	1758	+ if (!p) {
	1759	+ ret = -ENODEV;
	1760	+ goto err_free_irq;
	1761	+ }
	1762	+ if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
	1763	+ dev_info(host->dev, "missing default pinctrl state\n");
	1764	+ devm_pinctrl_put(p);
	1765	+ ret = -EINVAL;
	1766	+ goto err_free_irq;
	1767	+ }
	1768	+
	1769	+ if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
	1770	+ dev_info(host->dev, "missing idle pinctrl state\n");
	1771	+ devm_pinctrl_put(p);
	1772	+ ret = -EINVAL;
	1773	+ goto err_free_irq;
	1774	+ }
	1775	+ devm_pinctrl_put(p);
	1776	+ }
	1777	+
	1778	+ OMAP_HSMMC_WRITE(host->base, HCTL,
	1779	+ OMAP_HSMMC_READ(host->base, HCTL) \| IWE);
	1780	+ return 0;
	1781	+
	1782	+err_free_irq:
	1783	+ devm_free_irq(host->dev, host->wake_irq, host);
	1784	+err:
	1785	+ dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
	1786	+ host->wake_irq = 0;
	1787	+ return ret;
	1788	+}
	1789	+
1642	1790	static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1643	1791	{
1644	1792	u32 hctl, capa, value;
@@ -1691,7 +1839,7 @@ static const struct mmc_host_ops omap_hsmmc_ops = { · 46 unmodified lines
1691	1839	.get_cd = omap_hsmmc_get_cd,
1692	1840	.get_ro = omap_hsmmc_get_ro,
1693	1841	.init_card = omap_hsmmc_init_card,
1694		− /* NYET -- enable_sdio_irq */
	1842	+ .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1695	1843	};
1696	1844
1697	1845	#ifdef CONFIG_DEBUG_FS
@@ -1701,13 +1849,23 @@ static int omap_hsmmc_regs_show(struct seq_file s, void data) · 3 unmodified lines
1701	1849	struct mmc_host *mmc = s->private;
1702	1850	struct omap_hsmmc_host *host = mmc_priv(mmc);
1703	1851
1704		− seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
1705		− mmc->index, host->context_loss);
	1852	+ seq_printf(s, "mmc%d:\n", mmc->index);
	1853	+ seq_printf(s, "sdio irq mode\t%s\n",
	1854	+ (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1706	1855
1707		− pm_runtime_get_sync(host->dev);
	1856	+ if (mmc->caps & MMC_CAP_SDIO_IRQ) {
	1857	+ seq_printf(s, "sdio irq \t%s\n",
	1858	+ (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
	1859	+ : "disabled");
	1860	+ }
	1861	+ seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1708	1862
	1863	+ pm_runtime_get_sync(host->dev);
	1864	+ seq_puts(s, "\nregs:\n");
1709	1865	seq_printf(s, "CON:\t\t0x%08x\n",
1710	1866	OMAP_HSMMC_READ(host->base, CON));
	1867	+ seq_printf(s, "PSTATE:\t\t0x%08x\n",
	1868	+ OMAP_HSMMC_READ(host->base, PSTATE));
1711	1869	seq_printf(s, "HCTL:\t\t0x%08x\n",
1712	1870	OMAP_HSMMC_READ(host->base, HCTL));
1713	1871	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
@@ -1761,6 +1919,10 @@ static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { · 47 unmodified lines
1761	1919	static const struct omap_mmc_of_data omap4_mmc_of_data = {
1762	1920	.reg_offset = 0x100,
1763	1921	};
	1922	+static const struct omap_mmc_of_data am33xx_mmc_of_data = {
	1923	+ .reg_offset = 0x100,
	1924	+ .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
	1925	+};
1764	1926
1765	1927	static const struct of_device_id omap_mmc_of_match[] = {
1766	1928	{
@@ -1777,6 +1939,10 @@ static const struct of_device_id omap_mmc_of_match[] = { · 10 unmodified lines
1777	1939	.compatible = "ti,omap4-hsmmc",
1778	1940	.data = &omap4_mmc_of_data,
1779	1941	},
	1942	+ {
	1943	+ .compatible = "ti,am33xx-hsmmc",
	1944	+ .data = &am33xx_mmc_of_data,
	1945	+ },
1780	1946	{},
1781	1947	};
1782	1948	MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
@@ -1850,7 +2016,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev) · 67 unmodified lines
1850	2016	const struct of_device_id *match;
1851	2017	dma_cap_mask_t mask;
1852	2018	unsigned tx_req, rx_req;
1853		− struct pinctrl *pinctrl;
1854	2019	const struct omap_mmc_of_data *data;
1855	2020	void __iomem *base;
1856	2021
@@ -1913,6 +2078,9 @@ static int omap_hsmmc_probe(struct platform_device *pdev) · 56 unmodified lines
1913	2078
1914	2079	platform_set_drvdata(pdev, host);
1915	2080
	2081	+ if (pdev->dev.of_node)
	2082	+ host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
	2083	+
1916	2084	mmc->ops = &omap_hsmmc_ops;
1917	2085
1918	2086	mmc->f_min = OMAP_MMC_MIN_CLOCK;
@@ -2061,10 +2229,17 @@ static int omap_hsmmc_probe(struct platform_device *pdev) · 142 unmodified lines
2061	2229
2062	2230	omap_hsmmc_disable_irq(host);
2063	2231
2064		− pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2065		− if (IS_ERR(pinctrl))
2066		− dev_warn(&pdev->dev,
2067		− "pins are not configured from the driver\n");
	2232	+ /*
	2233	+ * For now, only support SDIO interrupt if we have a separate
	2234	+ * wake-up interrupt configured from device tree. This is because
	2235	+ * the wake-up interrupt is needed for idle state and some
	2236	+ * platforms need special quirks. And we don't want to add new
	2237	+ * legacy mux platform init code callbacks any longer as we
	2238	+ * are moving to DT based booting anyways.
	2239	+ */
	2240	+ ret = omap_hsmmc_configure_wake_irq(host);
	2241	+ if (!ret)
	2242	+ mmc->caps \|= MMC_CAP_SDIO_IRQ;
2068	2243
2069	2244	omap_hsmmc_protect_card(host);
2070	2245
@@ -2170,11 +2345,18 @@ static int omap_hsmmc_suspend(struct device *dev) · 99 unmodified lines
2170	2345	pm_runtime_get_sync(host->dev);
2171	2346
2172	2347	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2173		− omap_hsmmc_disable_irq(host);
	2348	+ OMAP_HSMMC_WRITE(host->base, ISE, 0);
	2349	+ OMAP_HSMMC_WRITE(host->base, IE, 0);
	2350	+ OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2174	2351	OMAP_HSMMC_WRITE(host->base, HCTL,
2175	2352	OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2176	2353	}
2177	2354
	2355	+ /* do not wake up due to sdio irq */
	2356	+ if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	2357	+ !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
	2358	+ disable_irq(host->wake_irq);
	2359	+
2178	2360	if (host->dbclk)
2179	2361	clk_disable_unprepare(host->dbclk);
2180	2362
@@ -2200,6 +2382,10 @@ static int omap_hsmmc_resume(struct device *dev) · 19 unmodified lines
2200	2382
2201	2383	omap_hsmmc_protect_card(host);
2202	2384
	2385	+ if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	2386	+ !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
	2387	+ enable_irq(host->wake_irq);
	2388	+
2203	2389	pm_runtime_mark_last_busy(host->dev);
2204	2390	pm_runtime_put_autosuspend(host->dev);
2205	2391	return 0;
@@ -2215,22 +2401,77 @@ static int omap_hsmmc_resume(struct device *dev) · 9 unmodified lines
2215	2401	static int omap_hsmmc_runtime_suspend(struct device *dev)
2216	2402	{
2217	2403	struct omap_hsmmc_host *host;
	2404	+ unsigned long flags;
	2405	+ int ret = 0;
2218	2406
2219	2407	host = platform_get_drvdata(to_platform_device(dev));
2220	2408	omap_hsmmc_context_save(host);
2221	2409	dev_dbg(dev, "disabled\n");
2222	2410
2223		− return 0;
	2411	+ spin_lock_irqsave(&host->irq_lock, flags);
	2412	+ if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	2413	+ (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
	2414	+ /* disable sdio irq handling to prevent race */
	2415	+ OMAP_HSMMC_WRITE(host->base, ISE, 0);
	2416	+ OMAP_HSMMC_WRITE(host->base, IE, 0);
	2417	+
	2418	+ if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
	2419	+ /*
	2420	+ * dat1 line low, pending sdio irq
	2421	+ * race condition: possible irq handler running on
	2422	+ * multi-core, abort
	2423	+ */
	2424	+ dev_dbg(dev, "pending sdio irq, abort suspend\n");
	2425	+ OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	2426	+ OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
	2427	+ OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
	2428	+ pm_runtime_mark_last_busy(dev);
	2429	+ ret = -EBUSY;
	2430	+ goto abort;
	2431	+ }
	2432	+
	2433	+ pinctrl_pm_select_idle_state(dev);
	2434	+
	2435	+ WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
	2436	+ enable_irq(host->wake_irq);
	2437	+ host->flags \|= HSMMC_WAKE_IRQ_ENABLED;
	2438	+ } else {
	2439	+ pinctrl_pm_select_idle_state(dev);
	2440	+ }
	2441	+
	2442	+abort:
	2443	+ spin_unlock_irqrestore(&host->irq_lock, flags);
	2444	+ return ret;
2224	2445	}
2225	2446
2226	2447	static int omap_hsmmc_runtime_resume(struct device *dev)
2227	2448	{
2228	2449	struct omap_hsmmc_host *host;
	2450	+ unsigned long flags;
2229	2451
2230	2452	host = platform_get_drvdata(to_platform_device(dev));
2231	2453	omap_hsmmc_context_restore(host);
2232	2454	dev_dbg(dev, "enabled\n");
2233	2455
	2456	+ spin_lock_irqsave(&host->irq_lock, flags);
	2457	+ if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	2458	+ (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
	2459	+ /* sdio irq flag can't change while in runtime suspend */
	2460	+ if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
	2461	+ disable_irq_nosync(host->wake_irq);
	2462	+ host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
	2463	+ }
	2464	+
	2465	+ pinctrl_pm_select_default_state(host->dev);
	2466	+
	2467	+ /* irq lost, if pinmux incorrect */
	2468	+ OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	2469	+ OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
	2470	+ OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
	2471	+ } else {
	2472	+ pinctrl_pm_select_default_state(host->dev);
	2473	+ }
	2474	+ spin_unlock_irqrestore(&host->irq_lock, flags);
2234	2475	return 0;
2235	2476	}
2236	2477

drivers/mmc/host/s3cmci.c+53−133

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	12	*/
13	13
14	14	#include <linux/module.h>
	15	+#include <linux/dmaengine.h>
15	16	#include <linux/dma-mapping.h>
16	17	#include <linux/clk.h>
17	18	#include <linux/mmc/host.h>
@@ -27,6 +28,7 @@ · 9 unmodified lines
27	28	#include <mach/dma.h>
28	29	#include <mach/gpio-samsung.h>
29	30
	31	+#include <linux/platform_data/dma-s3c24xx.h>
30	32	#include <linux/platform_data/mmc-s3cmci.h>
31	33
32	34	#include "s3cmci.h"
@@ -140,10 +142,6 @@ static const int dbgmap_debug = dbg_err \| dbg_debug; · 107 unmodified lines
140	142	dev_dbg(&host->pdev->dev, args); \
141	143	} while (0)
142	144
143		−static struct s3c2410_dma_client s3cmci_dma_client = {
144		− .name = "s3c-mci",
145		−};
146		−
147	145	static void finalize_request(struct s3cmci_host *host);
148	146	static void s3cmci_send_request(struct mmc_host *mmc);
149	147	static void s3cmci_reset(struct s3cmci_host *host);
@@ -256,25 +254,8 @@ static inline bool s3cmci_host_usedma(struct s3cmci_host *host) · 106 unmodified lines
256	254	{
257	255	#ifdef CONFIG_MMC_S3C_PIO
258	256	return false;
259		−#elif defined(CONFIG_MMC_S3C_DMA)
	257	+#else /* CONFIG_MMC_S3C_DMA */
260	258	return true;
261		−#else
262		− return host->dodma;
263		−#endif
264		−}
265		−
266		−/**
267		− * s3cmci_host_canpio - return true if host has pio code available
268		− *
269		− * Return true if the driver has been compiled with the PIO support code
270		− * available.
271		− */
272		−static inline bool s3cmci_host_canpio(void)
273		−{
274		−#ifdef CONFIG_MMC_S3C_PIO
275		− return true;
276		−#else
277		− return false;
278	259	#endif
279	260	}
280	261
@@ -841,60 +822,24 @@ static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id) · 560 unmodified lines
841	822	return IRQ_HANDLED;
842	823	}
843	824
844		−static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
845		− void *buf_id, int size,
846		− enum s3c2410_dma_buffresult result)
	825	+static void s3cmci_dma_done_callback(void *arg)
847	826	{
848		− struct s3cmci_host *host = buf_id;
	827	+ struct s3cmci_host *host = arg;
849	828	unsigned long iflags;
850		− u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
851		−
852		− mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
853		− mci_dsta = readl(host->base + S3C2410_SDIDSTA);
854		− mci_fsta = readl(host->base + S3C2410_SDIFSTA);
855		− mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
856	829
857	830	BUG_ON(!host->mrq);
858	831	BUG_ON(!host->mrq->data);
859		− BUG_ON(!host->dmatogo);
860	832
861	833	spin_lock_irqsave(&host->complete_lock, iflags);
862	834
863		− if (result != S3C2410_RES_OK) {
864		− dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
865		− "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
866		− mci_csta, mci_dsta, mci_fsta,
867		− mci_dcnt, result, host->dmatogo);
868		−
869		− goto fail_request;
870		− }
871		−
872		− host->dmatogo--;
873		− if (host->dmatogo) {
874		− dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
875		− "DCNT:[%08x] toGo:%u\n",
876		− size, mci_dsta, mci_dcnt, host->dmatogo);
877		−
878		− goto out;
879		− }
880		−
881		− dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
882		− size, mci_dsta, mci_dcnt);
	835	+ dbg(host, dbg_dma, "DMA FINISHED\n");
883	836
884	837	host->dma_complete = 1;
885	838	host->complete_what = COMPLETION_FINALIZE;
886	839
887		−out:
888	840	tasklet_schedule(&host->pio_tasklet);
889	841	spin_unlock_irqrestore(&host->complete_lock, iflags);
890		− return;
891	842
892		−fail_request:
893		− host->mrq->data->error = -EINVAL;
894		− host->complete_what = COMPLETION_FINALIZE;
895		− clear_imask(host);
896		−
897		− goto out;
898	843	}
899	844
900	845	static void finalize_request(struct s3cmci_host *host)
@@ -966,7 +911,7 @@ static void finalize_request(struct s3cmci_host *host) · 65 unmodified lines
966	911	* DMA channel and the fifo to clear out any garbage. */
967	912	if (mrq->data->error != 0) {
968	913	if (s3cmci_host_usedma(host))
969		− s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
	914	+ dmaengine_terminate_all(host->dma);
970	915
971	916	if (host->is2440) {
972	917	/* Clear failure register and reset fifo. */
@@ -992,29 +937,6 @@ request_done: · 19 unmodified lines
992	937	mmc_request_done(host->mmc, mrq);
993	938	}
994	939
995		−static void s3cmci_dma_setup(struct s3cmci_host *host,
996		− enum dma_data_direction source)
997		−{
998		− static enum dma_data_direction last_source = -1;
999		− static int setup_ok;
1000		−
1001		− if (last_source == source)
1002		− return;
1003		−
1004		− last_source = source;
1005		−
1006		− s3c2410_dma_devconfig(host->dma, source,
1007		− host->mem->start + host->sdidata);
1008		−
1009		− if (!setup_ok) {
1010		− s3c2410_dma_config(host->dma, 4);
1011		− s3c2410_dma_set_buffdone_fn(host->dma,
1012		− s3cmci_dma_done_callback);
1013		− s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
1014		− setup_ok = 1;
1015		− }
1016		−}
1017		−
1018	940	static void s3cmci_send_command(struct s3cmci_host *host,
1019	941	struct mmc_command *cmd)
1020	942	{
@@ -1162,43 +1084,45 @@ static int s3cmci_prepare_pio(struct s3cmci_host host, struct mmc_data data) · 141 unmodified lines
1162	1084
1163	1085	static int s3cmci_prepare_dma(struct s3cmci_host host, struct mmc_data data)
1164	1086	{
1165		− int dma_len, i;
1166	1087	int rw = data->flags & MMC_DATA_WRITE;
	1088	+ struct dma_async_tx_descriptor *desc;
	1089	+ struct dma_slave_config conf = {
	1090	+ .src_addr = host->mem->start + host->sdidata,
	1091	+ .dst_addr = host->mem->start + host->sdidata,
	1092	+ .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
	1093	+ .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
	1094	+ };
1167	1095
1168	1096	BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1169	1097
1170		− s3cmci_dma_setup(host, rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1171		− s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1172		−
1173		− dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1174		− rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1175		−
1176		− if (dma_len == 0)
1177		− return -ENOMEM;
1178		−
1179		− host->dma_complete = 0;
1180		− host->dmatogo = dma_len;
1181		−
1182		− for (i = 0; i < dma_len; i++) {
1183		− int res;
1184		−
1185		− dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1186		− sg_dma_address(&data->sg[i]),
1187		− sg_dma_len(&data->sg[i]));
	1098	+ /* Restore prescaler value */
	1099	+ writel(host->prescaler, host->base + S3C2410_SDIPRE);
1188	1100
1189		− res = s3c2410_dma_enqueue(host->dma, host,
1190		− sg_dma_address(&data->sg[i]),
1191		− sg_dma_len(&data->sg[i]));
	1101	+ if (!rw)
	1102	+ conf.direction = DMA_DEV_TO_MEM;
	1103	+ else
	1104	+ conf.direction = DMA_MEM_TO_DEV;
1192	1105
1193		− if (res) {
1194		− s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1195		− return -EBUSY;
1196		− }
1197		− }
	1106	+ dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
	1107	+ rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1198	1108
1199		− s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
	1109	+ dmaengine_slave_config(host->dma, &conf);
	1110	+ desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
	1111	+ conf.direction,
	1112	+ DMA_CTRL_ACK \| DMA_PREP_INTERRUPT);
	1113	+ if (!desc)
	1114	+ goto unmap_exit;
	1115	+ desc->callback = s3cmci_dma_done_callback;
	1116	+ desc->callback_param = host;
	1117	+ dmaengine_submit(desc);
	1118	+ dma_async_issue_pending(host->dma);
1200	1119
1201	1120	return 0;
	1121	+
	1122	+unmap_exit:
	1123	+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
	1124	+ rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	1125	+ return -ENOMEM;
1202	1126	}
1203	1127
1204	1128	static void s3cmci_send_request(struct mmc_host *mmc)
@@ -1676,10 +1600,6 @@ static int s3cmci_probe(struct platform_device *pdev) · 471 unmodified lines
1676	1600	host->complete_what = COMPLETION_NONE;
1677	1601	host->pio_active = XFER_NONE;
1678	1602
1679		−#ifdef CONFIG_MMC_S3C_PIODMA
1680		− host->dodma = host->pdata->use_dma;
1681		−#endif
1682		−
1683	1603	host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1684	1604	if (!host->mem) {
1685	1605	dev_err(&pdev->dev,
@@ -1765,17 +1685,17 @@ static int s3cmci_probe(struct platform_device *pdev) · 79 unmodified lines
1765	1685	/* depending on the dma state, get a dma channel to use. */
1766	1686
1767	1687	if (s3cmci_host_usedma(host)) {
1768		− host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1769		− host);
1770		− if (host->dma < 0) {
	1688	+ dma_cap_mask_t mask;
	1689	+
	1690	+ dma_cap_zero(mask);
	1691	+ dma_cap_set(DMA_SLAVE, mask);
	1692	+
	1693	+ host->dma = dma_request_slave_channel_compat(mask,
	1694	+ s3c24xx_dma_filter, (void *)DMACH_SDI, &pdev->dev, "rx-tx");
	1695	+ if (!host->dma) {
1771	1696	dev_err(&pdev->dev, "cannot get DMA channel.\n");
1772		− if (!s3cmci_host_canpio()) {
1773		− ret = -EBUSY;
1774		− goto probe_free_gpio_wp;
1775		− } else {
1776		− dev_warn(&pdev->dev, "falling back to PIO.\n");
1777		− host->dodma = 0;
1778		− }
	1697	+ ret = -EBUSY;
	1698	+ goto probe_free_gpio_wp;
1779	1699	}
1780	1700	}
1781	1701
@@ -1787,7 +1707,7 @@ static int s3cmci_probe(struct platform_device *pdev) · 5 unmodified lines
1787	1707	goto probe_free_dma;
1788	1708	}
1789	1709
1790		− ret = clk_enable(host->clk);
	1710	+ ret = clk_prepare_enable(host->clk);
1791	1711	if (ret) {
1792	1712	dev_err(&pdev->dev, "failed to enable clock source.\n");
1793	1713	goto clk_free;
@@ -1816,7 +1736,7 @@ static int s3cmci_probe(struct platform_device *pdev) · 22 unmodified lines
1816	1736	mmc->max_segs = 128;
1817	1737
1818	1738	dbg(host, dbg_debug,
1819		− "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
	1739	+ "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1820	1740	(host->is2440?"2440":""),
1821	1741	host->base, host->irq, host->irq_cd, host->dma);
1822	1742
@@ -1845,14 +1765,14 @@ static int s3cmci_probe(struct platform_device *pdev) · 22 unmodified lines
1845	1765	s3cmci_cpufreq_deregister(host);
1846	1766
1847	1767	free_dmabuf:
1848		− clk_disable(host->clk);
	1768	+ clk_disable_unprepare(host->clk);
1849	1769
1850	1770	clk_free:
1851	1771	clk_put(host->clk);
1852	1772
1853	1773	probe_free_dma:
1854	1774	if (s3cmci_host_usedma(host))
1855		− s3c2410_dma_free(host->dma, &s3cmci_dma_client);
	1775	+ dma_release_channel(host->dma);
1856	1776
1857	1777	probe_free_gpio_wp:
1858	1778	if (!host->pdata->no_wprotect)
@@ -1897,7 +1817,7 @@ static void s3cmci_shutdown(struct platform_device *pdev) · 38 unmodified lines
1897	1817	s3cmci_debugfs_remove(host);
1898	1818	s3cmci_cpufreq_deregister(host);
1899	1819	mmc_remove_host(mmc);
1900		− clk_disable(host->clk);
	1820	+ clk_disable_unprepare(host->clk);
1901	1821	}
1902	1822
1903	1823	static int s3cmci_remove(struct platform_device *pdev)
@@ -1914,7 +1834,7 @@ static int s3cmci_remove(struct platform_device *pdev) · 10 unmodified lines
1914	1834	tasklet_disable(&host->pio_tasklet);
1915	1835
1916	1836	if (s3cmci_host_usedma(host))
1917		− s3c2410_dma_free(host->dma, &s3cmci_dma_client);
	1837	+ dma_release_channel(host->dma);
1918	1838
1919	1839	free_irq(host->irq, host);
1920	1840

drivers/mmc/host/s3cmci.h+1−3

@@ -26,7 +26,7 @@ struct s3cmci_host { · 25 unmodified lines
26	26	void __iomem *base;
27	27	int irq;
28	28	int irq_cd;
29		− int dma;
	29	+ struct dma_chan *dma;
30	30
31	31	unsigned long clk_rate;
32	32	unsigned long clk_div;
@@ -36,8 +36,6 @@ struct s3cmci_host { · 3 unmodified lines
36	36	int is2440;
37	37	unsigned sdiimsk;
38	38	unsigned sdidata;
39		− int dodma;
40		− int dmatogo;
41	39
42	40	bool irq_disabled;
43	41	bool irq_enabled;

drivers/mmc/host/sdhci-acpi.c+3−1

@@ -124,9 +124,11 @@ static const struct sdhci_acpi_chip sdhci_acpi_chip_int = { · 123 unmodified lines
124	124
125	125	static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
126	126	.chip = &sdhci_acpi_chip_int,
127		− .caps = MMC_CAP_8_BIT_DATA \| MMC_CAP_NONREMOVABLE \| MMC_CAP_HW_RESET,
	127	+ .caps = MMC_CAP_8_BIT_DATA \| MMC_CAP_NONREMOVABLE \|
	128	+ MMC_CAP_HW_RESET \| MMC_CAP_1_8V_DDR,
128	129	.caps2 = MMC_CAP2_HC_ERASE_SZ,
129	130	.flags = SDHCI_ACPI_RUNTIME_PM,
	131	+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
130	132	};
131	133
132	134	static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {

drivers/mmc/host/sdhci-msm.c+0−1

@@ -16,7 +16,6 @@ · 15 unmodified lines
16	16
17	17	#include <linux/module.h>
18	18	#include <linux/of_device.h>
19		−#include <linux/regulator/consumer.h>
20	19	#include <linux/delay.h>
21	20	#include <linux/mmc/mmc.h>
22	21	#include <linux/slab.h>

drivers/mmc/host/sdhci-pci.c+20−18

@@ -103,6 +103,10 @@ static const struct sdhci_pci_fixes sdhci_cafe = { · 102 unmodified lines
103	103	SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
104	104	};
105	105
	106	+static const struct sdhci_pci_fixes sdhci_intel_qrk = {
	107	+ .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
	108	+};
	109	+
106	110	static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
107	111	{
108	112	slot->host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
@@ -264,7 +268,7 @@ static void sdhci_pci_int_hw_reset(struct sdhci_host *host) · 155 unmodified lines
264	268	static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
265	269	{
266	270	slot->host->mmc->caps \|= MMC_CAP_8_BIT_DATA \| MMC_CAP_NONREMOVABLE \|
267		− MMC_CAP_HW_RESET;
	271	+ MMC_CAP_HW_RESET \| MMC_CAP_1_8V_DDR;
268	272	slot->host->mmc->caps2 \|= MMC_CAP2_HC_ERASE_SZ;
269	273	slot->hw_reset = sdhci_pci_int_hw_reset;
270	274	return 0;
@@ -279,6 +283,7 @@ static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) · 8 unmodified lines
279	283	static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
280	284	.allow_runtime_pm = true,
281	285	.probe_slot = byt_emmc_probe_slot,
	286	+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
282	287	};
283	288
284	289	static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
@@ -751,6 +756,14 @@ static const struct pci_device_id pci_ids[] = { · 466 unmodified lines
751	756	.driver_data = (kernel_ulong_t)&sdhci_rtsx,
752	757	},
753	758
	759	+ {
	760	+ .vendor = PCI_VENDOR_ID_INTEL,
	761	+ .device = PCI_DEVICE_ID_INTEL_QRK_SD,
	762	+ .subvendor = PCI_ANY_ID,
	763	+ .subdevice = PCI_ANY_ID,
	764	+ .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
	765	+ },
	766	+
754	767	{
755	768	.vendor = PCI_VENDOR_ID_INTEL,
756	769	.device = PCI_DEVICE_ID_INTEL_MRST_SD0,
@@ -1130,18 +1143,13 @@ static int sdhci_pci_suspend(struct device *dev) · 373 unmodified lines
1130	1143	goto err_pci_suspend;
1131	1144	}
1132	1145
1133		− pci_save_state(pdev);
1134	1146	if (pm_flags & MMC_PM_KEEP_POWER) {
1135		− if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1136		− pci_pme_active(pdev, true);
1137		− pci_enable_wake(pdev, PCI_D3hot, 1);
1138		− }
1139		− pci_set_power_state(pdev, PCI_D3hot);
1140		− } else {
1141		− pci_enable_wake(pdev, PCI_D3hot, 0);
1142		− pci_disable_device(pdev);
1143		− pci_set_power_state(pdev, PCI_D3hot);
1144		− }
	1147	+ if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
	1148	+ device_init_wakeup(dev, true);
	1149	+ else
	1150	+ device_init_wakeup(dev, false);
	1151	+ } else
	1152	+ device_init_wakeup(dev, false);
1145	1153
1146	1154	return 0;
1147	1155
@@ -1162,12 +1170,6 @@ static int sdhci_pci_resume(struct device *dev) · 14 unmodified lines
1162	1170	if (!chip)
1163	1171	return 0;
1164	1172
1165		− pci_set_power_state(pdev, PCI_D0);
1166		− pci_restore_state(pdev);
1167		− ret = pci_enable_device(pdev);
1168		− if (ret)
1169		− return ret;
1170		−
1171	1173	if (chip->fixes && chip->fixes->resume) {
1172	1174	ret = chip->fixes->resume(chip);
1173	1175	if (ret)

drivers/mmc/host/sdhci-pci.h+1−0

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	17	#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
18	18	#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
19	19	#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
	20	+#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
20	21
21	22	/*
22	23	* PCI registers

drivers/mmc/host/sdhci-pxav3.c+3−10

@@ -288,15 +288,13 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) · 287 unmodified lines
288	288	int ret;
289	289	struct clk *clk;
290	290
291		− pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	291	+ pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
292	292	if (!pxa)
293	293	return -ENOMEM;
294	294
295	295	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
296		− if (IS_ERR(host)) {
297		− kfree(pxa);
	296	+ if (IS_ERR(host))
298	297	return PTR_ERR(host);
299		− }
300	298
301	299	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
302	300	ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
@@ -308,7 +306,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) · 5 unmodified lines
308	306	pltfm_host = sdhci_priv(host);
309	307	pltfm_host->priv = pxa;
310	308
311		− clk = clk_get(dev, NULL);
	309	+ clk = devm_clk_get(dev, NULL);
312	310	if (IS_ERR(clk)) {
313	311	dev_err(dev, "failed to get io clock\n");
314	312	ret = PTR_ERR(clk);
@@ -389,11 +387,9 @@ err_add_host: · 74 unmodified lines
389	387	pm_runtime_put_sync(&pdev->dev);
390	388	pm_runtime_disable(&pdev->dev);
391	389	clk_disable_unprepare(clk);
392		− clk_put(clk);
393	390	err_clk_get:
394	391	err_mbus_win:
395	392	sdhci_pltfm_free(pdev);
396		− kfree(pxa);
397	393	return ret;
398	394	}
399	395
@@ -401,17 +397,14 @@ static int sdhci_pxav3_remove(struct platform_device *pdev) · 1 unmodified line
401	397	{
402	398	struct sdhci_host *host = platform_get_drvdata(pdev);
403	399	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
404		− struct sdhci_pxa *pxa = pltfm_host->priv;
405	400
406	401	pm_runtime_get_sync(&pdev->dev);
407	402	sdhci_remove_host(host, 1);
408	403	pm_runtime_disable(&pdev->dev);
409	404
410	405	clk_disable_unprepare(pltfm_host->clk);
411		− clk_put(pltfm_host->clk);
412	406
413	407	sdhci_pltfm_free(pdev);
414		− kfree(pxa);
415	408
416	409	return 0;
417	410	}

drivers/mmc/host/sdhci-st.c+176−0

@@ -0,0 +1,176 @@
	1	+/*
	2	+ * Support for SDHCI on STMicroelectronics SoCs
	3	+ *
	4	+ * Copyright (C) 2014 STMicroelectronics Ltd
	5	+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	6	+ * Contributors: Peter Griffin <peter.griffin@linaro.org>
	7	+ *
	8	+ * Based on sdhci-cns3xxx.c
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or modify
	11	+ * it under the terms of the GNU General Public License version 2 as
	12	+ * published by the Free Software Foundation.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ */
	20	+
	21	+#include <linux/io.h>
	22	+#include <linux/of.h>
	23	+#include <linux/module.h>
	24	+#include <linux/err.h>
	25	+#include <linux/mmc/host.h>
	26	+
	27	+#include "sdhci-pltfm.h"
	28	+
	29	+static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
	30	+{
	31	+ u32 ret;
	32	+
	33	+ switch (reg) {
	34	+ case SDHCI_CAPABILITIES:
	35	+ ret = readl_relaxed(host->ioaddr + reg);
	36	+ /* Support 3.3V and 1.8V */
	37	+ ret &= ~SDHCI_CAN_VDD_300;
	38	+ break;
	39	+ default:
	40	+ ret = readl_relaxed(host->ioaddr + reg);
	41	+ }
	42	+ return ret;
	43	+}
	44	+
	45	+static const struct sdhci_ops sdhci_st_ops = {
	46	+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
	47	+ .set_clock = sdhci_set_clock,
	48	+ .set_bus_width = sdhci_set_bus_width,
	49	+ .read_l = sdhci_st_readl,
	50	+ .reset = sdhci_reset,
	51	+};
	52	+
	53	+static const struct sdhci_pltfm_data sdhci_st_pdata = {
	54	+ .ops = &sdhci_st_ops,
	55	+ .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC \|
	56	+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	57	+};
	58	+
	59	+
	60	+static int sdhci_st_probe(struct platform_device *pdev)
	61	+{
	62	+ struct sdhci_host *host;
	63	+ struct sdhci_pltfm_host *pltfm_host;
	64	+ struct clk *clk;
	65	+ int ret = 0;
	66	+ u16 host_version;
	67	+
	68	+ clk = devm_clk_get(&pdev->dev, "mmc");
	69	+ if (IS_ERR(clk)) {
	70	+ dev_err(&pdev->dev, "Peripheral clk not found\n");
	71	+ return PTR_ERR(clk);
	72	+ }
	73	+
	74	+ host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
	75	+ if (IS_ERR(host)) {
	76	+ dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
	77	+ return PTR_ERR(host);
	78	+ }
	79	+
	80	+ ret = mmc_of_parse(host->mmc);
	81	+
	82	+ if (ret) {
	83	+ dev_err(&pdev->dev, "Failed mmc_of_parse\n");
	84	+ return ret;
	85	+ }
	86	+
	87	+ clk_prepare_enable(clk);
	88	+
	89	+ pltfm_host = sdhci_priv(host);
	90	+ pltfm_host->clk = clk;
	91	+
	92	+ ret = sdhci_add_host(host);
	93	+ if (ret) {
	94	+ dev_err(&pdev->dev, "Failed sdhci_add_host\n");
	95	+ goto err_out;
	96	+ }
	97	+
	98	+ platform_set_drvdata(pdev, host);
	99	+
	100	+ host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
	101	+
	102	+ dev_info(&pdev->dev, "SDHCI ST Initialised: Host Version: 0x%x Vendor Version 0x%x\n",
	103	+ ((host_version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT),
	104	+ ((host_version & SDHCI_VENDOR_VER_MASK) >>
	105	+ SDHCI_VENDOR_VER_SHIFT));
	106	+
	107	+ return 0;
	108	+
	109	+err_out:
	110	+ clk_disable_unprepare(clk);
	111	+ sdhci_pltfm_free(pdev);
	112	+
	113	+ return ret;
	114	+}
	115	+
	116	+static int sdhci_st_remove(struct platform_device *pdev)
	117	+{
	118	+ struct sdhci_host *host = platform_get_drvdata(pdev);
	119	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	120	+
	121	+ clk_disable_unprepare(pltfm_host->clk);
	122	+
	123	+ return sdhci_pltfm_unregister(pdev);
	124	+}
	125	+
	126	+#ifdef CONFIG_PM_SLEEP
	127	+static int sdhci_st_suspend(struct device *dev)
	128	+{
	129	+ struct sdhci_host *host = dev_get_drvdata(dev);
	130	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	131	+ int ret = sdhci_suspend_host(host);
	132	+
	133	+ if (ret)
	134	+ goto out;
	135	+
	136	+ clk_disable_unprepare(pltfm_host->clk);
	137	+out:
	138	+ return ret;
	139	+}
	140	+
	141	+static int sdhci_st_resume(struct device *dev)
	142	+{
	143	+ struct sdhci_host *host = dev_get_drvdata(dev);
	144	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	145	+
	146	+ clk_prepare_enable(pltfm_host->clk);
	147	+
	148	+ return sdhci_resume_host(host);
	149	+}
	150	+#endif
	151	+
	152	+static SIMPLE_DEV_PM_OPS(sdhci_st_pmops, sdhci_st_suspend, sdhci_st_resume);
	153	+
	154	+static const struct of_device_id st_sdhci_match[] = {
	155	+ { .compatible = "st,sdhci" },
	156	+ {},
	157	+};
	158	+
	159	+MODULE_DEVICE_TABLE(of, st_sdhci_match);
	160	+
	161	+static struct platform_driver sdhci_st_driver = {
	162	+ .probe = sdhci_st_probe,
	163	+ .remove = sdhci_st_remove,
	164	+ .driver = {
	165	+ .name = "sdhci-st",
	166	+ .pm = &sdhci_st_pmops,
	167	+ .of_match_table = of_match_ptr(st_sdhci_match),
	168	+ },
	169	+};
	170	+
	171	+module_platform_driver(sdhci_st_driver);
	172	+
	173	+MODULE_DESCRIPTION("SDHCI driver for STMicroelectronics SoCs");
	174	+MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
	175	+MODULE_LICENSE("GPL v2");
	176	+MODULE_ALIAS("platform:st-sdhci");

drivers/mmc/host/sdhci-tegra.c+0−2

@@ -26,8 +26,6 @@ · 25 unmodified lines
26	26	#include <linux/mmc/host.h>
27	27	#include <linux/mmc/slot-gpio.h>
28	28
29		−#include <asm/gpio.h>
30		−
31	29	#include "sdhci-pltfm.h"
32	30
33	31	/* Tegra SDHOST controller vendor register definitions */

drivers/mmc/host/sdhci.c+58−86

@@ -1223,8 +1223,16 @@ EXPORT_SYMBOL_GPL(sdhci_set_clock); · 1222 unmodified lines
1223	1223	static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1224	1224	unsigned short vdd)
1225	1225	{
	1226	+ struct mmc_host *mmc = host->mmc;
1226	1227	u8 pwr = 0;
1227	1228
	1229	+ if (!IS_ERR(mmc->supply.vmmc)) {
	1230	+ spin_unlock_irq(&host->lock);
	1231	+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
	1232	+ spin_lock_irq(&host->lock);
	1233	+ return;
	1234	+ }
	1235	+
1228	1236	if (mode != MMC_POWER_OFF) {
1229	1237	switch (1 << vdd) {
1230	1238	case MMC_VDD_165_195:
@@ -1283,12 +1291,6 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, · 52 unmodified lines
1283	1291	if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1284	1292	mdelay(10);
1285	1293	}
1286		−
1287		− if (host->vmmc) {
1288		− spin_unlock_irq(&host->lock);
1289		− mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd);
1290		− spin_lock_irq(&host->lock);
1291		− }
1292	1294	}
1293	1295
1294	1296	/*****************************************************************************\
@@ -1440,13 +1442,15 @@ static void sdhci_do_set_ios(struct sdhci_host host, struct mmc_ios ios) · 145 unmodified lines
1440	1442	{
1441	1443	unsigned long flags;
1442	1444	u8 ctrl;
	1445	+ struct mmc_host *mmc = host->mmc;
1443	1446
1444	1447	spin_lock_irqsave(&host->lock, flags);
1445	1448
1446	1449	if (host->flags & SDHCI_DEVICE_DEAD) {
1447	1450	spin_unlock_irqrestore(&host->lock, flags);
1448		− if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1449		− mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
	1451	+ if (!IS_ERR(mmc->supply.vmmc) &&
	1452	+ ios->power_mode == MMC_POWER_OFF)
	1453	+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1450	1454	return;
1451	1455	}
1452	1456
@@ -1530,7 +1534,6 @@ static void sdhci_do_set_ios(struct sdhci_host host, struct mmc_ios ios) · 77 unmodified lines
1530	1534	host->ops->set_clock(host, host->clock);
1531	1535	}
1532	1536
1533		−
1534	1537	/* Reset SD Clock Enable */
1535	1538	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1536	1539	clk &= ~SDHCI_CLOCK_CARD_EN;
@@ -1707,6 +1710,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) · 170 unmodified lines
1707	1710	static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1708	1711	struct mmc_ios *ios)
1709	1712	{
	1713	+ struct mmc_host *mmc = host->mmc;
1710	1714	u16 ctrl;
1711	1715	int ret;
1712	1716
@@ -1725,11 +1729,12 @@ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, · 12 unmodified lines
1725	1729	ctrl &= ~SDHCI_CTRL_VDD_180;
1726	1730	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1727	1731
1728		− if (host->vqmmc) {
1729		− ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
	1732	+ if (!IS_ERR(mmc->supply.vqmmc)) {
	1733	+ ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
	1734	+ 3600000);
1730	1735	if (ret) {
1731	1736	pr_warning("%s: Switching to 3.3V signalling voltage "
1732		− " failed\n", mmc_hostname(host->mmc));
	1737	+ " failed\n", mmc_hostname(mmc));
1733	1738	return -EIO;
1734	1739	}
1735	1740	}
@@ -1742,16 +1747,16 @@ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, · 6 unmodified lines
1742	1747	return 0;
1743	1748
1744	1749	pr_warning("%s: 3.3V regulator output did not became stable\n",
1745		− mmc_hostname(host->mmc));
	1750	+ mmc_hostname(mmc));
1746	1751
1747	1752	return -EAGAIN;
1748	1753	case MMC_SIGNAL_VOLTAGE_180:
1749		− if (host->vqmmc) {
1750		− ret = regulator_set_voltage(host->vqmmc,
	1754	+ if (!IS_ERR(mmc->supply.vqmmc)) {
	1755	+ ret = regulator_set_voltage(mmc->supply.vqmmc,
1751	1756	1700000, 1950000);
1752	1757	if (ret) {
1753	1758	pr_warning("%s: Switching to 1.8V signalling voltage "
1754		− " failed\n", mmc_hostname(host->mmc));
	1759	+ " failed\n", mmc_hostname(mmc));
1755	1760	return -EIO;
1756	1761	}
1757	1762	}
@@ -1763,24 +1768,22 @@ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, · 5 unmodified lines
1763	1768	ctrl \|= SDHCI_CTRL_VDD_180;
1764	1769	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1765	1770
1766		− /* Wait for 5ms */
1767		− usleep_range(5000, 5500);
1768		−
1769	1771	/* 1.8V regulator output should be stable within 5 ms */
1770	1772	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1771	1773	if (ctrl & SDHCI_CTRL_VDD_180)
1772	1774	return 0;
1773	1775
1774	1776	pr_warning("%s: 1.8V regulator output did not became stable\n",
1775		− mmc_hostname(host->mmc));
	1777	+ mmc_hostname(mmc));
1776	1778
1777	1779	return -EAGAIN;
1778	1780	case MMC_SIGNAL_VOLTAGE_120:
1779		− if (host->vqmmc) {
1780		− ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
	1781	+ if (!IS_ERR(mmc->supply.vqmmc)) {
	1782	+ ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
	1783	+ 1300000);
1781	1784	if (ret) {
1782	1785	pr_warning("%s: Switching to 1.2V signalling voltage "
1783		− " failed\n", mmc_hostname(host->mmc));
	1786	+ " failed\n", mmc_hostname(mmc));
1784	1787	return -EIO;
1785	1788	}
1786	1789	}
@@ -2643,7 +2646,6 @@ static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) · 856 unmodified lines
2643	2646	int sdhci_runtime_suspend_host(struct sdhci_host *host)
2644	2647	{
2645	2648	unsigned long flags;
2646		− int ret = 0;
2647	2649
2648	2650	/* Disable tuning since we are suspending */
2649	2651	if (host->flags & SDHCI_USING_RETUNING_TIMER) {
@@ -2663,14 +2665,14 @@ int sdhci_runtime_suspend_host(struct sdhci_host *host) · 13 unmodified lines
2663	2665	host->runtime_suspended = true;
2664	2666	spin_unlock_irqrestore(&host->lock, flags);
2665	2667
2666		− return ret;
	2668	+ return 0;
2667	2669	}
2668	2670	EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2669	2671
2670	2672	int sdhci_runtime_resume_host(struct sdhci_host *host)
2671	2673	{
2672	2674	unsigned long flags;
2673		− int ret = 0, host_flags = host->flags;
	2675	+ int host_flags = host->flags;
2674	2676
2675	2677	if (host_flags & (SDHCI_USE_SDMA \| SDHCI_USE_ADMA)) {
2676	2678	if (host->ops->enable_dma)
@@ -2709,7 +2711,7 @@ int sdhci_runtime_resume_host(struct sdhci_host *host) · 32 unmodified lines
2709	2711
2710	2712	spin_unlock_irqrestore(&host->lock, flags);
2711	2713
2712		− return ret;
	2714	+ return 0;
2713	2715	}
2714	2716	EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2715	2717
@@ -2820,12 +2822,12 @@ int sdhci_add_host(struct sdhci_host *host) · 104 unmodified lines
2820	2822	* (128) and potentially one alignment transfer for
2821	2823	* each of those entries.
2822	2824	*/
2823		− host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
	2825	+ host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2824	2826	ADMA_SIZE, &host->adma_addr,
2825	2827	GFP_KERNEL);
2826	2828	host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2827	2829	if (!host->adma_desc \|\| !host->align_buffer) {
2828		− dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
	2830	+ dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2829	2831	host->adma_desc, host->adma_addr);
2830	2832	kfree(host->align_buffer);
2831	2833	pr_warning("%s: Unable to allocate ADMA "
@@ -2838,7 +2840,7 @@ int sdhci_add_host(struct sdhci_host *host) · 6 unmodified lines
2838	2840	pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2839	2841	mmc_hostname(mmc));
2840	2842	host->flags &= ~SDHCI_USE_ADMA;
2841		− dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
	2843	+ dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2842	2844	host->adma_desc, host->adma_addr);
2843	2845	kfree(host->align_buffer);
2844	2846	host->adma_desc = NULL;
@@ -2853,7 +2855,7 @@ int sdhci_add_host(struct sdhci_host *host) · 8 unmodified lines
2853	2855	*/
2854	2856	if (!(host->flags & (SDHCI_USE_SDMA \| SDHCI_USE_ADMA))) {
2855	2857	host->dma_mask = DMA_BIT_MASK(64);
2856		− mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
	2858	+ mmc_dev(mmc)->dma_mask = &host->dma_mask;
2857	2859	}
2858	2860
2859	2861	if (host->version >= SDHCI_SPEC_300)
@@ -2959,28 +2961,25 @@ int sdhci_add_host(struct sdhci_host *host) · 99 unmodified lines
2959	2961	mmc->caps \|= MMC_CAP_SD_HIGHSPEED \| MMC_CAP_MMC_HIGHSPEED;
2960	2962
2961	2963	if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2962		− !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
	2964	+ !(mmc->caps & MMC_CAP_NONREMOVABLE))
2963	2965	mmc->caps \|= MMC_CAP_NEEDS_POLL;
2964	2966
	2967	+ /* If there are external regulators, get them */
	2968	+ if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
	2969	+ return -EPROBE_DEFER;
	2970	+
2965	2971	/* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2966		− host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2967		− if (IS_ERR_OR_NULL(host->vqmmc)) {
2968		− if (PTR_ERR(host->vqmmc) < 0) {
2969		− pr_info("%s: no vqmmc regulator found\n",
2970		− mmc_hostname(mmc));
2971		− host->vqmmc = NULL;
2972		− }
2973		− } else {
2974		− ret = regulator_enable(host->vqmmc);
2975		− if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2976		− 1950000))
	2972	+ if (!IS_ERR(mmc->supply.vqmmc)) {
	2973	+ ret = regulator_enable(mmc->supply.vqmmc);
	2974	+ if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
	2975	+ 1950000))
2977	2976	caps[1] &= ~(SDHCI_SUPPORT_SDR104 \|
2978	2977	SDHCI_SUPPORT_SDR50 \|
2979	2978	SDHCI_SUPPORT_DDR50);
2980	2979	if (ret) {
2981	2980	pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2982	2981	mmc_hostname(mmc), ret);
2983		− host->vqmmc = NULL;
	2982	+ mmc->supply.vqmmc = NULL;
2984	2983	}
2985	2984	}
2986	2985
@@ -3041,34 +3040,6 @@ int sdhci_add_host(struct sdhci_host *host) · 54 unmodified lines
3041	3040
3042	3041	ocr_avail = 0;
3043	3042
3044		− host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3045		− if (IS_ERR_OR_NULL(host->vmmc)) {
3046		− if (PTR_ERR(host->vmmc) < 0) {
3047		− pr_info("%s: no vmmc regulator found\n",
3048		− mmc_hostname(mmc));
3049		− host->vmmc = NULL;
3050		− }
3051		− }
3052		−
3053		−#ifdef CONFIG_REGULATOR
3054		− /*
3055		− * Voltage range check makes sense only if regulator reports
3056		− * any voltage value.
3057		− */
3058		− if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3059		− ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3060		− 3600000);
3061		− if ((ret <= 0) \|\| (!(caps[0] & SDHCI_CAN_VDD_330)))
3062		− caps[0] &= ~SDHCI_CAN_VDD_330;
3063		− if ((ret <= 0) \|\| (!(caps[0] & SDHCI_CAN_VDD_300)))
3064		− caps[0] &= ~SDHCI_CAN_VDD_300;
3065		− ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3066		− 1950000);
3067		− if ((ret <= 0) \|\| (!(caps[0] & SDHCI_CAN_VDD_180)))
3068		− caps[0] &= ~SDHCI_CAN_VDD_180;
3069		− }
3070		−#endif /* CONFIG_REGULATOR */
3071		−
3072	3043	/*
3073	3044	* According to SD Host Controller spec v3.00, if the Host System
3074	3045	* can afford more than 150mA, Host Driver should set XPC to 1. Also
@@ -3077,8 +3048,8 @@ int sdhci_add_host(struct sdhci_host *host) · 2 unmodified lines
3077	3048	* value.
3078	3049	*/
3079	3050	max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3080		− if (!max_current_caps && host->vmmc) {
3081		− u32 curr = regulator_get_current_limit(host->vmmc);
	3051	+ if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
	3052	+ u32 curr = regulator_get_current_limit(mmc->supply.vmmc);
3082	3053	if (curr > 0) {
3083	3054
3084	3055	/* convert to SDHCI_MAX_CURRENT format */
@@ -3118,8 +3089,12 @@ int sdhci_add_host(struct sdhci_host *host) · 33 unmodified lines
3118	3089	SDHCI_MAX_CURRENT_MULTIPLIER;
3119	3090	}
3120	3091
	3092	+ /* If OCR set by external regulators, use it instead */
	3093	+ if (mmc->ocr_avail)
	3094	+ ocr_avail = mmc->ocr_avail;
	3095	+
3121	3096	if (host->ocr_mask)
3122		− ocr_avail = host->ocr_mask;
	3097	+ ocr_avail &= host->ocr_mask;
3123	3098
3124	3099	mmc->ocr_avail = ocr_avail;
3125	3100	mmc->ocr_avail_sdio = ocr_avail;
@@ -3273,6 +3248,7 @@ EXPORT_SYMBOL_GPL(sdhci_add_host); · 147 unmodified lines
3273	3248
3274	3249	void sdhci_remove_host(struct sdhci_host *host, int dead)
3275	3250	{
	3251	+ struct mmc_host *mmc = host->mmc;
3276	3252	unsigned long flags;
3277	3253
3278	3254	if (dead) {
@@ -3282,7 +3258,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) · 3 unmodified lines
3282	3258
3283	3259	if (host->mrq) {
3284	3260	pr_err("%s: Controller removed during "
3285		− " transfer!\n", mmc_hostname(host->mmc));
	3261	+ " transfer!\n", mmc_hostname(mmc));
3286	3262
3287	3263	host->mrq->cmd->error = -ENOMEDIUM;
3288	3264	tasklet_schedule(&host->finish_tasklet);
@@ -3293,7 +3269,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) · 4 unmodified lines
3293	3269
3294	3270	sdhci_disable_card_detection(host);
3295	3271
3296		− mmc_remove_host(host->mmc);
	3272	+ mmc_remove_host(mmc);
3297	3273
3298	3274	#ifdef SDHCI_USE_LEDS_CLASS
3299	3275	led_classdev_unregister(&host->led);
@@ -3310,18 +3286,14 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) · 10 unmodified lines
3310	3286
3311	3287	tasklet_kill(&host->finish_tasklet);
3312	3288
3313		− if (host->vmmc) {
3314		− regulator_disable(host->vmmc);
3315		− regulator_put(host->vmmc);
3316		− }
	3289	+ if (!IS_ERR(mmc->supply.vmmc))
	3290	+ regulator_disable(mmc->supply.vmmc);
3317	3291
3318		− if (host->vqmmc) {
3319		− regulator_disable(host->vqmmc);
3320		− regulator_put(host->vqmmc);
3321		− }
	3292	+ if (!IS_ERR(mmc->supply.vqmmc))
	3293	+ regulator_disable(mmc->supply.vqmmc);
3322	3294
3323	3295	if (host->adma_desc)
3324		− dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
	3296	+ dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3325	3297	host->adma_desc, host->adma_addr);
3326	3298	kfree(host->align_buffer);
3327	3299

drivers/mmc/host/sh_mmcif.c+38−58

@@ -386,7 +386,7 @@ sh_mmcif_request_dma_one(struct sh_mmcif_host *host, · 385 unmodified lines
386	386	struct sh_mmcif_plat_data *pdata,
387	387	enum dma_transfer_direction direction)
388	388	{
389		− struct dma_slave_config cfg;
	389	+ struct dma_slave_config cfg = { 0, };
390	390	struct dma_chan *chan;
391	391	unsigned int slave_id;
392	392	struct resource *res;
@@ -417,8 +417,15 @@ sh_mmcif_request_dma_one(struct sh_mmcif_host *host, · 24 unmodified lines
417	417	/* In the OF case the driver will get the slave ID from the DT */
418	418	cfg.slave_id = slave_id;
419	419	cfg.direction = direction;
420		− cfg.dst_addr = res->start + MMCIF_CE_DATA;
421		− cfg.src_addr = 0;
	420	+
	421	+ if (direction == DMA_DEV_TO_MEM) {
	422	+ cfg.src_addr = res->start + MMCIF_CE_DATA;
	423	+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	424	+ } else {
	425	+ cfg.dst_addr = res->start + MMCIF_CE_DATA;
	426	+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	427	+ }
	428	+
422	429	ret = dmaengine_slave_config(chan, &cfg);
423	430	if (ret < 0) {
424	431	dma_release_channel(chan);
@@ -1378,26 +1385,19 @@ static int sh_mmcif_probe(struct platform_device *pdev) · 953 unmodified lines
1378	1385	dev_err(&pdev->dev, "Get irq error\n");
1379	1386	return -ENXIO;
1380	1387	}
	1388	+
1381	1389	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382		− if (!res) {
1383		− dev_err(&pdev->dev, "platform_get_resource error.\n");
1384		− return -ENXIO;
1385		− }
1386		− reg = ioremap(res->start, resource_size(res));
1387		− if (!reg) {
1388		− dev_err(&pdev->dev, "ioremap error.\n");
1389		− return -ENOMEM;
1390		− }
	1390	+ reg = devm_ioremap_resource(&pdev->dev, res);
	1391	+ if (IS_ERR(reg))
	1392	+ return PTR_ERR(reg);
1391	1393
1392	1394	mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1393		− if (!mmc) {
1394		− ret = -ENOMEM;
1395		− goto ealloch;
1396		− }
	1395	+ if (!mmc)
	1396	+ return -ENOMEM;
1397	1397
1398	1398	ret = mmc_of_parse(mmc);
1399	1399	if (ret < 0)
1400		− goto eofparse;
	1400	+ goto err_host;
1401	1401
1402	1402	host = mmc_priv(mmc);
1403	1403	host->mmc = mmc;
@@ -1427,19 +1427,19 @@ static int sh_mmcif_probe(struct platform_device *pdev) · 23 unmodified lines
1427	1427	pm_runtime_enable(&pdev->dev);
1428	1428	host->power = false;
1429	1429
1430		− host->hclk = clk_get(&pdev->dev, NULL);
	1430	+ host->hclk = devm_clk_get(&pdev->dev, NULL);
1431	1431	if (IS_ERR(host->hclk)) {
1432	1432	ret = PTR_ERR(host->hclk);
1433	1433	dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
1434		− goto eclkget;
	1434	+ goto err_pm;
1435	1435	}
1436	1436	ret = sh_mmcif_clk_update(host);
1437	1437	if (ret < 0)
1438		− goto eclkupdate;
	1438	+ goto err_pm;
1439	1439
1440	1440	ret = pm_runtime_resume(&pdev->dev);
1441	1441	if (ret < 0)
1442		− goto eresume;
	1442	+ goto err_clk;
1443	1443
1444	1444	INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1445	1445
@@ -1447,65 +1447,55 @@ static int sh_mmcif_probe(struct platform_device *pdev) · 1 unmodified line
1447	1447	sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1448	1448
1449	1449	name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1450		− ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host);
	1450	+ ret = devm_request_threaded_irq(&pdev->dev, irq[0], sh_mmcif_intr,
	1451	+ sh_mmcif_irqt, 0, name, host);
1451	1452	if (ret) {
1452	1453	dev_err(&pdev->dev, "request_irq error (%s)\n", name);
1453		− goto ereqirq0;
	1454	+ goto err_clk;
1454	1455	}
1455	1456	if (irq[1] >= 0) {
1456		− ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt,
1457		− 0, "sh_mmc:int", host);
	1457	+ ret = devm_request_threaded_irq(&pdev->dev, irq[1],
	1458	+ sh_mmcif_intr, sh_mmcif_irqt,
	1459	+ 0, "sh_mmc:int", host);
1458	1460	if (ret) {
1459	1461	dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1460		− goto ereqirq1;
	1462	+ goto err_clk;
1461	1463	}
1462	1464	}
1463	1465
1464	1466	if (pd && pd->use_cd_gpio) {
1465	1467	ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1466	1468	if (ret < 0)
1467		− goto erqcd;
	1469	+ goto err_clk;
1468	1470	}
1469	1471
1470	1472	mutex_init(&host->thread_lock);
1471	1473
1472		− clk_disable_unprepare(host->hclk);
1473	1474	ret = mmc_add_host(mmc);
1474	1475	if (ret < 0)
1475		− goto emmcaddh;
	1476	+ goto err_clk;
1476	1477
1477	1478	dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1478	1479
1479		− dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1480		− dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1481		− sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
	1480	+ dev_info(&pdev->dev, "Chip version 0x%04x, clock rate %luMHz\n",
	1481	+ sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
	1482	+ clk_get_rate(host->hclk) / 1000000UL);
	1483	+
	1484	+ clk_disable_unprepare(host->hclk);
1482	1485	return ret;
1483	1486
1484		−emmcaddh:
1485		−erqcd:
1486		− if (irq[1] >= 0)
1487		− free_irq(irq[1], host);
1488		−ereqirq1:
1489		− free_irq(irq[0], host);
1490		−ereqirq0:
1491		− pm_runtime_suspend(&pdev->dev);
1492		−eresume:
	1487	+err_clk:
1493	1488	clk_disable_unprepare(host->hclk);
1494		−eclkupdate:
1495		− clk_put(host->hclk);
1496		−eclkget:
	1489	+err_pm:
1497	1490	pm_runtime_disable(&pdev->dev);
1498		−eofparse:
	1491	+err_host:
1499	1492	mmc_free_host(mmc);
1500		−ealloch:
1501		− iounmap(reg);
1502	1493	return ret;
1503	1494	}
1504	1495
1505	1496	static int sh_mmcif_remove(struct platform_device *pdev)
1506	1497	{
1507	1498	struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1508		− int irq[2];
1509	1499
1510	1500	host->dying = true;
1511	1501	clk_prepare_enable(host->hclk);
@@ -1523,16 +1513,6 @@ static int sh_mmcif_remove(struct platform_device *pdev) · 11 unmodified lines
1523	1513	*/
1524	1514	cancel_delayed_work_sync(&host->timeout_work);
1525	1515
1526		− if (host->addr)
1527		− iounmap(host->addr);
1528		−
1529		− irq[0] = platform_get_irq(pdev, 0);
1530		− irq[1] = platform_get_irq(pdev, 1);
1531		−
1532		− free_irq(irq[0], host);
1533		− if (irq[1] >= 0)
1534		− free_irq(irq[1], host);
1535		−
1536	1516	clk_disable_unprepare(host->hclk);
1537	1517	mmc_free_host(host->mmc);
1538	1518	pm_runtime_put_sync(&pdev->dev);

drivers/mmc/host/tmio_mmc_dma.c+2−0

@@ -294,6 +294,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host host, struct tmio_mmc_data pdat · 293 unmodified lines
294	294	cfg.slave_id = pdata->dma->slave_id_tx;
295	295	cfg.direction = DMA_MEM_TO_DEV;
296	296	cfg.dst_addr = res->start + (CTL_SD_DATA_PORT << host->pdata->bus_shift);
	297	+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
297	298	cfg.src_addr = 0;
298	299	ret = dmaengine_slave_config(host->chan_tx, &cfg);
299	300	if (ret < 0)
@@ -312,6 +313,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host host, struct tmio_mmc_data pdat · 12 unmodified lines
312	313	cfg.slave_id = pdata->dma->slave_id_rx;
313	314	cfg.direction = DMA_DEV_TO_MEM;
314	315	cfg.src_addr = cfg.dst_addr;
	316	+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
315	317	cfg.dst_addr = 0;
316	318	ret = dmaengine_slave_config(host->chan_rx, &cfg);
317	319	if (ret < 0)

drivers/mmc/host/wmt-sdmmc.c+16−17

@@ -72,7 +72,6 @@ · 71 unmodified lines
72	72	#define BM_SPI_CS 0x20
73	73	#define BM_SD_POWER 0x40
74	74	#define BM_SOFT_RESET 0x80
75		−#define BM_ONEBIT_MASK 0xFD
76	75
77	76	/* SDMMC_BLKLEN bit fields */
78	77	#define BLKL_CRCERR_ABORT 0x0800
@@ -120,6 +119,8 @@ · 41 unmodified lines
120	119	#define STS2_DATARSP_BUSY 0x20
121	120	#define STS2_DIS_FORCECLK 0x80
122	121
	122	+/* SDMMC_EXTCTRL bit fields */
	123	+#define EXT_EIGHTBIT 0x04
123	124
124	125	/* MMC/SD DMA Controller Registers */
125	126	#define SDDMA_GCR 0x100
@@ -672,7 +673,7 @@ static void wmt_mci_request(struct mmc_host mmc, struct mmc_request req) · 546 unmodified lines
672	673	static void wmt_mci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
673	674	{
674	675	struct wmt_mci_priv *priv;
675		− u32 reg_tmp;
	676	+ u32 busmode, extctrl;
676	677
677	678	priv = mmc_priv(mmc);
678	679
@@ -687,28 +688,26 @@ static void wmt_mci_set_ios(struct mmc_host mmc, struct mmc_ios ios) · 8 unmodified lines
687	688	if (ios->clock != 0)
688	689	clk_set_rate(priv->clk_sdmmc, ios->clock);
689	690
	691	+ busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);
	692	+ extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
	693	+
	694	+ busmode &= ~(BM_EIGHTBIT_MODE \| BM_FOURBIT_MODE);
	695	+ extctrl &= ~EXT_EIGHTBIT;
	696	+
690	697	switch (ios->bus_width) {
691	698	case MMC_BUS_WIDTH_8:
692		− reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
693		− writeb(reg_tmp \| 0x04, priv->sdmmc_base + SDMMC_EXTCTRL);
	699	+ busmode \|= BM_EIGHTBIT_MODE;
	700	+ extctrl \|= EXT_EIGHTBIT;
694	701	break;
695	702	case MMC_BUS_WIDTH_4:
696		− reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
697		− writeb(reg_tmp \| BM_FOURBIT_MODE, priv->sdmmc_base +
698		− SDMMC_BUSMODE);
699		−
700		− reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
701		− writeb(reg_tmp & 0xFB, priv->sdmmc_base + SDMMC_EXTCTRL);
	703	+ busmode \|= BM_FOURBIT_MODE;
702	704	break;
703	705	case MMC_BUS_WIDTH_1:
704		− reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
705		− writeb(reg_tmp & BM_ONEBIT_MASK, priv->sdmmc_base +
706		− SDMMC_BUSMODE);
707		−
708		− reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
709		− writeb(reg_tmp & 0xFB, priv->sdmmc_base + SDMMC_EXTCTRL);
710	706	break;
711	707	}
	708	+
	709	+ writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE);
	710	+ writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL);
712	711	}
713	712
714	713	static int wmt_mci_get_ro(struct mmc_host *mmc)
@@ -830,7 +829,7 @@ static int wmt_mci_probe(struct platform_device *pdev) · 115 unmodified lines
830	829	goto fail3;
831	830	}
832	831
833		− ret = request_irq(dma_irq, wmt_mci_dma_isr, 32, "sdmmc", priv);
	832	+ ret = request_irq(dma_irq, wmt_mci_dma_isr, 0, "sdmmc", priv);
834	833	if (ret) {
835	834	dev_err(&pdev->dev, "Register DMA IRQ fail\n");
836	835	goto fail4;

include/linux/mmc/dw_mmc.h+2−0

@@ -213,6 +213,8 @@ struct dw_mci_dma_ops { · 212 unmodified lines
213	213	#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
214	214	/* Unreliable card detection */
215	215	#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
	216	+/* No write protect */
	217	+#define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4)
216	218
217	219	/* Slot level quirks */
218	220	/* This slot has no write protect */

include/linux/mmc/sdhci.h+0−3

@@ -104,9 +104,6 @@ struct sdhci_host { · 103 unmodified lines
104	104
105	105	const struct sdhci_ops ops; / Low level hw interface */
106	106
107		− struct regulator vmmc; / Power regulator (vmmc) */
108		− struct regulator vqmmc; / Signaling regulator (vccq) */
109		−
110	107	/* Internal data */
111	108	struct mmc_host mmc; / MMC structure */
112	109	u64 dma_mask; /* custom DMA mask */

include/linux/platform_data/mmc-omap.h+1−0

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	28	*/
29	29	#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
30	30	#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)
	31	+#define OMAP_HSMMC_SWAKEUP_MISSING BIT(2)
31	32
32	33	struct mmc_card;
33	34