The values of bclk and fsync are inverted WRT the codec. But the existing solution already works for Broadwell, see the alsa-lib config: `alsa-lib/src/conf/topology/broadwell/broadwell.conf` This commit provides the backwards-compatible solution to fix this misuse.
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| @@ -160,6 +160,18 @@ · 159 unmodified lines | |||
| 160 | #define SND_SOC_TPLG_LNK_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2) | 160 | #define SND_SOC_TPLG_LNK_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2) |
| 161 | #define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3) | 161 | #define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3) |
| 162 | 162 | ||
| 163 | /* DAI topology BCLK parameter | ||
| 164 | * For the backwards capability, by default codec is bclk master | ||
| 165 | */ | ||
| 166 | #define SND_SOC_TPLG_BCLK_CM 0 /* codec is bclk master */ | ||
| 167 | #define SND_SOC_TPLG_BCLK_CS 1 /* codec is bclk slave */ | ||
| 168 | |||
| 169 | /* DAI topology FSYNC parameter | ||
| 170 | * For the backwards capability, by default codec is fsync master | ||
| 171 | */ | ||
| 172 | #define SND_SOC_TPLG_FSYNC_CM 0 /* codec is fsync master */ | ||
| 173 | #define SND_SOC_TPLG_FSYNC_CS 1 /* codec is fsync slave */ | ||
| 174 | |||
| 163 | /* | 175 | /* |
| 164 | * Block Header. | 176 | * Block Header. |
| 165 | * This header precedes all object and object arrays below. | 177 | * This header precedes all object and object arrays below. |
| @@ -315,8 +327,8 @@ struct snd_soc_tplg_hw_config { · 149 unmodified lines | |||
| 315 | __u8 clock_gated; /* 1 if clock can be gated to save power */ | 327 | __u8 clock_gated; /* 1 if clock can be gated to save power */ |
| 316 | __u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */ | 328 | __u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */ |
| 317 | __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ | 329 | __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ |
| 318 | __u8 bclk_master; /* 1 for master of BCLK, 0 for slave */ | 330 | __u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */ |
| 319 | __u8 fsync_master; /* 1 for master of FSYNC, 0 for slave */ | 331 | __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */ |
| 320 | __u8 mclk_direction; /* 0 for input, 1 for output */ | 332 | __u8 mclk_direction; /* 0 for input, 1 for output */ |
| 321 | __le16 reserved; /* for 32bit alignment */ | 333 | __le16 reserved; /* for 32bit alignment */ |
| 322 | __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */ | 334 | __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */ |