bunch of i915 fixes. * tag 'drm-intel-fixes-2015-06-05' of git://anongit.freedesktop.org/drm-intel: drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code drm/i915: Include G4X/VLV/CHV in self refresh status drm/i915: Initialize HWS page address after GPU reset drm/i915: Don't skip request retirement if the active list is empty drm/i915/hsw: Fix workaround for server AUX channel clock divisor
Unified · Split
| @@ -1667,12 +1667,15 @@ static int i915_sr_status(struct seq_file *m, void *unused) · 1666 unmodified lines | |||
| 1667 | 1667 | ||
| 1668 | if (HAS_PCH_SPLIT(dev)) | 1668 | if (HAS_PCH_SPLIT(dev)) |
| 1669 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; | 1669 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
| 1670 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) | 1670 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
| 1671 | IS_I945G(dev) || IS_I945GM(dev)) | ||
| 1671 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; | 1672 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1672 | else if (IS_I915GM(dev)) | 1673 | else if (IS_I915GM(dev)) |
| 1673 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | 1674 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1674 | else if (IS_PINEVIEW(dev)) | 1675 | else if (IS_PINEVIEW(dev)) |
| 1675 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | 1676 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1677 | else if (IS_VALLEYVIEW(dev)) | ||
| 1678 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; | ||
| 1676 | 1679 | ||
| 1677 | intel_runtime_pm_put(dev_priv); | 1680 | intel_runtime_pm_put(dev_priv); |
| 1678 | 1681 | ||
| @@ -2656,9 +2656,6 @@ void i915_gem_reset(struct drm_device *dev) · 2655 unmodified lines | |||
| 2656 | void | 2656 | void |
| 2657 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) | 2657 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
| 2658 | { | 2658 | { |
| 2659 | if (list_empty(&ring->request_list)) | ||
| 2660 | return; | ||
| 2661 | |||
| 2662 | WARN_ON(i915_verify_lists(ring->dev)); | 2659 | WARN_ON(i915_verify_lists(ring->dev)); |
| 2663 | 2660 | ||
| 2664 | /* Retire requests first as we use it above for the early return. | 2661 | /* Retire requests first as we use it above for the early return. |
| @@ -880,10 +880,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, · 879 unmodified lines | |||
| 880 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | 880 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
| 881 | continue; | 881 | continue; |
| 882 | if (status & DP_AUX_CH_CTL_DONE) | 882 | if (status & DP_AUX_CH_CTL_DONE) |
| 883 | break; | 883 | goto done; |
| 884 | } | 884 | } |
| 885 | if (status & DP_AUX_CH_CTL_DONE) | ||
| 886 | break; | ||
| 887 | } | 885 | } |
| 888 | 886 | ||
| 889 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { | 887 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
| @@ -892,6 +890,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, · 2 unmodified lines | |||
| 892 | goto out; | 890 | goto out; |
| 893 | } | 891 | } |
| 894 | 892 | ||
| 893 | done: | ||
| 895 | /* Check for timeout or receive error. | 894 | /* Check for timeout or receive error. |
| 896 | * Timeouts occur when the sink is not connected | 895 | * Timeouts occur when the sink is not connected |
| 897 | */ | 896 | */ |
| @@ -1134,6 +1134,12 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) · 1133 unmodified lines | |||
| 1134 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | 1134 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
| 1135 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | 1135 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); |
| 1136 | 1136 | ||
| 1137 | if (ring->status_page.obj) { | ||
| 1138 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | ||
| 1139 | (u32)ring->status_page.gfx_addr); | ||
| 1140 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | ||
| 1141 | } | ||
| 1142 | |||
| 1137 | I915_WRITE(RING_MODE_GEN7(ring), | 1143 | I915_WRITE(RING_MODE_GEN7(ring), |
| 1138 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | 1144 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
| 1139 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | 1145 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
| @@ -901,13 +901,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) · 900 unmodified lines | |||
| 901 | GEN6_WIZ_HASHING_MASK, | 901 | GEN6_WIZ_HASHING_MASK, |
| 902 | GEN6_WIZ_HASHING_16x4); | 902 | GEN6_WIZ_HASHING_16x4); |
| 903 | 903 | ||
| 904 | if (INTEL_REVID(dev) == SKL_REVID_C0 || | ||
| 905 | INTEL_REVID(dev) == SKL_REVID_D0) | ||
| 906 | /* WaBarrierPerformanceFixDisable:skl */ | ||
| 907 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | ||
| 908 | HDC_FENCE_DEST_SLM_DISABLE | | ||
| 909 | HDC_BARRIER_PERFORMANCE_DISABLE); | ||
| 910 | |||
| 911 | return 0; | 904 | return 0; |
| 912 | } | 905 | } |
| 913 | 906 | ||
| @@ -1024,6 +1017,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) · 110 unmodified lines | |||
| 1024 | WA_SET_BIT_MASKED(HIZ_CHICKEN, | 1017 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
| 1025 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | 1018 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); |
| 1026 | 1019 | ||
| 1020 | if (INTEL_REVID(dev) == SKL_REVID_C0 || | ||
| 1021 | INTEL_REVID(dev) == SKL_REVID_D0) | ||
| 1022 | /* WaBarrierPerformanceFixDisable:skl */ | ||
| 1023 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | ||
| 1024 | HDC_FENCE_DEST_SLM_DISABLE | | ||
| 1025 | HDC_BARRIER_PERFORMANCE_DISABLE); | ||
| 1026 | |||
| 1027 | return skl_tune_iz_hashing(ring); | 1027 | return skl_tune_iz_hashing(ring); |
| 1028 | } | 1028 | } |
| 1029 | 1029 | ||