History

Merge branch 'for-4.4/drivers' of git://git.kernel.dk/linux-block

Pull block driver updates from Jens Axboe: "Here are the block driver changes for 4.4. This pull request contains: - NVMe: - Refactor and moving of code to prepare for proper target support. From Christoph and Jay. - 32-bit nvme warning fix from Arnd. - Error initialization fix from me. - Proper namespace removal and reference counting support from Keith. - Device resume fix on IO failure, also from Keith. - Dependency fix from Keith, now that nvme isn't under the umbrella of the block anymore. - Target location and maintainers update from Jay. - From Ming Lei, the long awaited DIO/AIO support for loop. - Enable BD-RE writeable opens, from Georgios" * 'for-4.4/drivers' of git://git.kernel.dk/linux-block: (24 commits) Update target repo for nvme patch contributions NVMe: initialize error to '0' nvme: use an integer value to Linux errno values nvme: fix 32-bit build warning NVMe: Add explicit block config dependency nvme: include <linux/types.ĥ> in <linux/nvme.h> nvme: move to a new drivers/nvme/host directory nvme.h: add missing nvme_id_ctrl endianess annotations nvme: move hardware structures out of the uapi version of nvme.h nvme: add a local nvme.h header nvme: properly handle partially initialized queues in nvme_create_io_queues nvme: merge nvme_dev_start, nvme_dev_resume and nvme_async_probe nvme: factor reset code into a common helper nvme: merge nvme_dev_reset into nvme_reset_failed_dev nvme: delete dev from dev_list in nvme_reset NVMe: Simplify device resume on io queue failure NVMe: Namespace removal simplifications NVMe: Reference count open namespaces cdrom: Random writing support for BD-RE media block: loop: support DIO & AIO ...

Linus Torvalds committed 11 years ago

Commit a9aa31c2 parents d9734e0 b3975e919 files · +1056 −899Browse files

Showing the changes to include/uapi (3 of 19 files). Show all

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3 files
  1. include/uapi/linux/loop.h +2 −0
  2. include/uapi/linux/nvme.h +0 −589
  3. include/uapi/linux/nvme_ioctl.h +65 −0
include/uapi/linux/loop.h+2−0
@@ -21,6 +21,7 @@ enum { · 20 unmodified lines
2121 LO_FLAGS_READ_ONLY = 1,
2222 LO_FLAGS_AUTOCLEAR = 4,
2323 LO_FLAGS_PARTSCAN = 8,
24+ LO_FLAGS_DIRECT_IO = 16,
2425 };
2526
2627 #include <asm/posix_types.h> /* for __kernel_old_dev_t */
@@ -86,6 +87,7 @@ struct loop_info64 { · 59 unmodified lines
8687 #define LOOP_GET_STATUS64 0x4C05
8788 #define LOOP_CHANGE_FD 0x4C06
8889 #define LOOP_SET_CAPACITY 0x4C07
90+#define LOOP_SET_DIRECT_IO 0x4C08
8991
9092 /* /dev/loop-control interface */
9193 #define LOOP_CTL_ADD 0x4C80
include/uapi/linux/nvme.h+0−589
@@ -1,589 +0,0 @@
1−/*
2− * Definitions for the NVM Express interface
3− * Copyright (c) 2011-2014, Intel Corporation.
4− *
5− * This program is free software; you can redistribute it and/or modify it
6− * under the terms and conditions of the GNU General Public License,
7− * version 2, as published by the Free Software Foundation.
8− *
9− * This program is distributed in the hope it will be useful, but WITHOUT
10− * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11− * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12− * more details.
13− */
14−
15−#ifndef _UAPI_LINUX_NVME_H
16−#define _UAPI_LINUX_NVME_H
17−
18−#include <linux/types.h>
19−
20−struct nvme_id_power_state {
21− __le16 max_power; /* centiwatts */
22− __u8 rsvd2;
23− __u8 flags;
24− __le32 entry_lat; /* microseconds */
25− __le32 exit_lat; /* microseconds */
26− __u8 read_tput;
27− __u8 read_lat;
28− __u8 write_tput;
29− __u8 write_lat;
30− __le16 idle_power;
31− __u8 idle_scale;
32− __u8 rsvd19;
33− __le16 active_power;
34− __u8 active_work_scale;
35− __u8 rsvd23[9];
36−};
37−
38−enum {
39− NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
40− NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
41−};
42−
43−struct nvme_id_ctrl {
44− __le16 vid;
45− __le16 ssvid;
46− char sn[20];
47− char mn[40];
48− char fr[8];
49− __u8 rab;
50− __u8 ieee[3];
51− __u8 mic;
52− __u8 mdts;
53− __u16 cntlid;
54− __u32 ver;
55− __u8 rsvd84[172];
56− __le16 oacs;
57− __u8 acl;
58− __u8 aerl;
59− __u8 frmw;
60− __u8 lpa;
61− __u8 elpe;
62− __u8 npss;
63− __u8 avscc;
64− __u8 apsta;
65− __le16 wctemp;
66− __le16 cctemp;
67− __u8 rsvd270[242];
68− __u8 sqes;
69− __u8 cqes;
70− __u8 rsvd514[2];
71− __le32 nn;
72− __le16 oncs;
73− __le16 fuses;
74− __u8 fna;
75− __u8 vwc;
76− __le16 awun;
77− __le16 awupf;
78− __u8 nvscc;
79− __u8 rsvd531;
80− __le16 acwu;
81− __u8 rsvd534[2];
82− __le32 sgls;
83− __u8 rsvd540[1508];
84− struct nvme_id_power_state psd[32];
85− __u8 vs[1024];
86−};
87−
88−enum {
89− NVME_CTRL_ONCS_COMPARE = 1 << 0,
90− NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
91− NVME_CTRL_ONCS_DSM = 1 << 2,
92− NVME_CTRL_VWC_PRESENT = 1 << 0,
93−};
94−
95−struct nvme_lbaf {
96− __le16 ms;
97− __u8 ds;
98− __u8 rp;
99−};
100−
101−struct nvme_id_ns {
102− __le64 nsze;
103− __le64 ncap;
104− __le64 nuse;
105− __u8 nsfeat;
106− __u8 nlbaf;
107− __u8 flbas;
108− __u8 mc;
109− __u8 dpc;
110− __u8 dps;
111− __u8 nmic;
112− __u8 rescap;
113− __u8 fpi;
114− __u8 rsvd33;
115− __le16 nawun;
116− __le16 nawupf;
117− __le16 nacwu;
118− __le16 nabsn;
119− __le16 nabo;
120− __le16 nabspf;
121− __u16 rsvd46;
122− __le64 nvmcap[2];
123− __u8 rsvd64[40];
124− __u8 nguid[16];
125− __u8 eui64[8];
126− struct nvme_lbaf lbaf[16];
127− __u8 rsvd192[192];
128− __u8 vs[3712];
129−};
130−
131−enum {
132− NVME_NS_FEAT_THIN = 1 << 0,
133− NVME_NS_FLBAS_LBA_MASK = 0xf,
134− NVME_NS_FLBAS_META_EXT = 0x10,
135− NVME_LBAF_RP_BEST = 0,
136− NVME_LBAF_RP_BETTER = 1,
137− NVME_LBAF_RP_GOOD = 2,
138− NVME_LBAF_RP_DEGRADED = 3,
139− NVME_NS_DPC_PI_LAST = 1 << 4,
140− NVME_NS_DPC_PI_FIRST = 1 << 3,
141− NVME_NS_DPC_PI_TYPE3 = 1 << 2,
142− NVME_NS_DPC_PI_TYPE2 = 1 << 1,
143− NVME_NS_DPC_PI_TYPE1 = 1 << 0,
144− NVME_NS_DPS_PI_FIRST = 1 << 3,
145− NVME_NS_DPS_PI_MASK = 0x7,
146− NVME_NS_DPS_PI_TYPE1 = 1,
147− NVME_NS_DPS_PI_TYPE2 = 2,
148− NVME_NS_DPS_PI_TYPE3 = 3,
149−};
150−
151−struct nvme_smart_log {
152− __u8 critical_warning;
153− __u8 temperature[2];
154− __u8 avail_spare;
155− __u8 spare_thresh;
156− __u8 percent_used;
157− __u8 rsvd6[26];
158− __u8 data_units_read[16];
159− __u8 data_units_written[16];
160− __u8 host_reads[16];
161− __u8 host_writes[16];
162− __u8 ctrl_busy_time[16];
163− __u8 power_cycles[16];
164− __u8 power_on_hours[16];
165− __u8 unsafe_shutdowns[16];
166− __u8 media_errors[16];
167− __u8 num_err_log_entries[16];
168− __le32 warning_temp_time;
169− __le32 critical_comp_time;
170− __le16 temp_sensor[8];
171− __u8 rsvd216[296];
172−};
173−
174−enum {
175− NVME_SMART_CRIT_SPARE = 1 << 0,
176− NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
177− NVME_SMART_CRIT_RELIABILITY = 1 << 2,
178− NVME_SMART_CRIT_MEDIA = 1 << 3,
179− NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
180−};
181−
182−enum {
183− NVME_AER_NOTICE_NS_CHANGED = 0x0002,
184−};
185−
186−struct nvme_lba_range_type {
187− __u8 type;
188− __u8 attributes;
189− __u8 rsvd2[14];
190− __u64 slba;
191− __u64 nlb;
192− __u8 guid[16];
193− __u8 rsvd48[16];
194−};
195−
196−enum {
197− NVME_LBART_TYPE_FS = 0x01,
198− NVME_LBART_TYPE_RAID = 0x02,
199− NVME_LBART_TYPE_CACHE = 0x03,
200− NVME_LBART_TYPE_SWAP = 0x04,
201−
202− NVME_LBART_ATTRIB_TEMP = 1 << 0,
203− NVME_LBART_ATTRIB_HIDE = 1 << 1,
204−};
205−
206−struct nvme_reservation_status {
207− __le32 gen;
208− __u8 rtype;
209− __u8 regctl[2];
210− __u8 resv5[2];
211− __u8 ptpls;
212− __u8 resv10[13];
213− struct {
214− __le16 cntlid;
215− __u8 rcsts;
216− __u8 resv3[5];
217− __le64 hostid;
218− __le64 rkey;
219− } regctl_ds[];
220−};
221−
222−/* I/O commands */
223−
224−enum nvme_opcode {
225− nvme_cmd_flush = 0x00,
226− nvme_cmd_write = 0x01,
227− nvme_cmd_read = 0x02,
228− nvme_cmd_write_uncor = 0x04,
229− nvme_cmd_compare = 0x05,
230− nvme_cmd_write_zeroes = 0x08,
231− nvme_cmd_dsm = 0x09,
232− nvme_cmd_resv_register = 0x0d,
233− nvme_cmd_resv_report = 0x0e,
234− nvme_cmd_resv_acquire = 0x11,
235− nvme_cmd_resv_release = 0x15,
236−};
237−
238−struct nvme_common_command {
239− __u8 opcode;
240− __u8 flags;
241− __u16 command_id;
242− __le32 nsid;
243− __le32 cdw2[2];
244− __le64 metadata;
245− __le64 prp1;
246− __le64 prp2;
247− __le32 cdw10[6];
248−};
249−
250−struct nvme_rw_command {
251− __u8 opcode;
252− __u8 flags;
253− __u16 command_id;
254− __le32 nsid;
255− __u64 rsvd2;
256− __le64 metadata;
257− __le64 prp1;
258− __le64 prp2;
259− __le64 slba;
260− __le16 length;
261− __le16 control;
262− __le32 dsmgmt;
263− __le32 reftag;
264− __le16 apptag;
265− __le16 appmask;
266−};
267−
268−enum {
269− NVME_RW_LR = 1 << 15,
270− NVME_RW_FUA = 1 << 14,
271− NVME_RW_DSM_FREQ_UNSPEC = 0,
272− NVME_RW_DSM_FREQ_TYPICAL = 1,
273− NVME_RW_DSM_FREQ_RARE = 2,
274− NVME_RW_DSM_FREQ_READS = 3,
275− NVME_RW_DSM_FREQ_WRITES = 4,
276− NVME_RW_DSM_FREQ_RW = 5,
277− NVME_RW_DSM_FREQ_ONCE = 6,
278− NVME_RW_DSM_FREQ_PREFETCH = 7,
279− NVME_RW_DSM_FREQ_TEMP = 8,
280− NVME_RW_DSM_LATENCY_NONE = 0 << 4,
281− NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
282− NVME_RW_DSM_LATENCY_NORM = 2 << 4,
283− NVME_RW_DSM_LATENCY_LOW = 3 << 4,
284− NVME_RW_DSM_SEQ_REQ = 1 << 6,
285− NVME_RW_DSM_COMPRESSED = 1 << 7,
286− NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
287− NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
288− NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
289− NVME_RW_PRINFO_PRACT = 1 << 13,
290−};
291−
292−struct nvme_dsm_cmd {
293− __u8 opcode;
294− __u8 flags;
295− __u16 command_id;
296− __le32 nsid;
297− __u64 rsvd2[2];
298− __le64 prp1;
299− __le64 prp2;
300− __le32 nr;
301− __le32 attributes;
302− __u32 rsvd12[4];
303−};
304−
305−enum {
306− NVME_DSMGMT_IDR = 1 << 0,
307− NVME_DSMGMT_IDW = 1 << 1,
308− NVME_DSMGMT_AD = 1 << 2,
309−};
310−
311−struct nvme_dsm_range {
312− __le32 cattr;
313− __le32 nlb;
314− __le64 slba;
315−};
316−
317−/* Admin commands */
318−
319−enum nvme_admin_opcode {
320− nvme_admin_delete_sq = 0x00,
321− nvme_admin_create_sq = 0x01,
322− nvme_admin_get_log_page = 0x02,
323− nvme_admin_delete_cq = 0x04,
324− nvme_admin_create_cq = 0x05,
325− nvme_admin_identify = 0x06,
326− nvme_admin_abort_cmd = 0x08,
327− nvme_admin_set_features = 0x09,
328− nvme_admin_get_features = 0x0a,
329− nvme_admin_async_event = 0x0c,
330− nvme_admin_activate_fw = 0x10,
331− nvme_admin_download_fw = 0x11,
332− nvme_admin_format_nvm = 0x80,
333− nvme_admin_security_send = 0x81,
334− nvme_admin_security_recv = 0x82,
335−};
336−
337−enum {
338− NVME_QUEUE_PHYS_CONTIG = (1 << 0),
339− NVME_CQ_IRQ_ENABLED = (1 << 1),
340− NVME_SQ_PRIO_URGENT = (0 << 1),
341− NVME_SQ_PRIO_HIGH = (1 << 1),
342− NVME_SQ_PRIO_MEDIUM = (2 << 1),
343− NVME_SQ_PRIO_LOW = (3 << 1),
344− NVME_FEAT_ARBITRATION = 0x01,
345− NVME_FEAT_POWER_MGMT = 0x02,
346− NVME_FEAT_LBA_RANGE = 0x03,
347− NVME_FEAT_TEMP_THRESH = 0x04,
348− NVME_FEAT_ERR_RECOVERY = 0x05,
349− NVME_FEAT_VOLATILE_WC = 0x06,
350− NVME_FEAT_NUM_QUEUES = 0x07,
351− NVME_FEAT_IRQ_COALESCE = 0x08,
352− NVME_FEAT_IRQ_CONFIG = 0x09,
353− NVME_FEAT_WRITE_ATOMIC = 0x0a,
354− NVME_FEAT_ASYNC_EVENT = 0x0b,
355− NVME_FEAT_AUTO_PST = 0x0c,
356− NVME_FEAT_SW_PROGRESS = 0x80,
357− NVME_FEAT_HOST_ID = 0x81,
358− NVME_FEAT_RESV_MASK = 0x82,
359− NVME_FEAT_RESV_PERSIST = 0x83,
360− NVME_LOG_ERROR = 0x01,
361− NVME_LOG_SMART = 0x02,
362− NVME_LOG_FW_SLOT = 0x03,
363− NVME_LOG_RESERVATION = 0x80,
364− NVME_FWACT_REPL = (0 << 3),
365− NVME_FWACT_REPL_ACTV = (1 << 3),
366− NVME_FWACT_ACTV = (2 << 3),
367−};
368−
369−struct nvme_identify {
370− __u8 opcode;
371− __u8 flags;
372− __u16 command_id;
373− __le32 nsid;
374− __u64 rsvd2[2];
375− __le64 prp1;
376− __le64 prp2;
377− __le32 cns;
378− __u32 rsvd11[5];
379−};
380−
381−struct nvme_features {
382− __u8 opcode;
383− __u8 flags;
384− __u16 command_id;
385− __le32 nsid;
386− __u64 rsvd2[2];
387− __le64 prp1;
388− __le64 prp2;
389− __le32 fid;
390− __le32 dword11;
391− __u32 rsvd12[4];
392−};
393−
394−struct nvme_create_cq {
395− __u8 opcode;
396− __u8 flags;
397− __u16 command_id;
398− __u32 rsvd1[5];
399− __le64 prp1;
400− __u64 rsvd8;
401− __le16 cqid;
402− __le16 qsize;
403− __le16 cq_flags;
404− __le16 irq_vector;
405− __u32 rsvd12[4];
406−};
407−
408−struct nvme_create_sq {
409− __u8 opcode;
410− __u8 flags;
411− __u16 command_id;
412− __u32 rsvd1[5];
413− __le64 prp1;
414− __u64 rsvd8;
415− __le16 sqid;
416− __le16 qsize;
417− __le16 sq_flags;
418− __le16 cqid;
419− __u32 rsvd12[4];
420−};
421−
422−struct nvme_delete_queue {
423− __u8 opcode;
424− __u8 flags;
425− __u16 command_id;
426− __u32 rsvd1[9];
427− __le16 qid;
428− __u16 rsvd10;
429− __u32 rsvd11[5];
430−};
431−
432−struct nvme_abort_cmd {
433− __u8 opcode;
434− __u8 flags;
435− __u16 command_id;
436− __u32 rsvd1[9];
437− __le16 sqid;
438− __u16 cid;
439− __u32 rsvd11[5];
440−};
441−
442−struct nvme_download_firmware {
443− __u8 opcode;
444− __u8 flags;
445− __u16 command_id;
446− __u32 rsvd1[5];
447− __le64 prp1;
448− __le64 prp2;
449− __le32 numd;
450− __le32 offset;
451− __u32 rsvd12[4];
452−};
453−
454−struct nvme_format_cmd {
455− __u8 opcode;
456− __u8 flags;
457− __u16 command_id;
458− __le32 nsid;
459− __u64 rsvd2[4];
460− __le32 cdw10;
461− __u32 rsvd11[5];
462−};
463−
464−struct nvme_command {
465− union {
466− struct nvme_common_command common;
467− struct nvme_rw_command rw;
468− struct nvme_identify identify;
469− struct nvme_features features;
470− struct nvme_create_cq create_cq;
471− struct nvme_create_sq create_sq;
472− struct nvme_delete_queue delete_queue;
473− struct nvme_download_firmware dlfw;
474− struct nvme_format_cmd format;
475− struct nvme_dsm_cmd dsm;
476− struct nvme_abort_cmd abort;
477− };
478−};
479−
480−enum {
481− NVME_SC_SUCCESS = 0x0,
482− NVME_SC_INVALID_OPCODE = 0x1,
483− NVME_SC_INVALID_FIELD = 0x2,
484− NVME_SC_CMDID_CONFLICT = 0x3,
485− NVME_SC_DATA_XFER_ERROR = 0x4,
486− NVME_SC_POWER_LOSS = 0x5,
487− NVME_SC_INTERNAL = 0x6,
488− NVME_SC_ABORT_REQ = 0x7,
489− NVME_SC_ABORT_QUEUE = 0x8,
490− NVME_SC_FUSED_FAIL = 0x9,
491− NVME_SC_FUSED_MISSING = 0xa,
492− NVME_SC_INVALID_NS = 0xb,
493− NVME_SC_CMD_SEQ_ERROR = 0xc,
494− NVME_SC_SGL_INVALID_LAST = 0xd,
495− NVME_SC_SGL_INVALID_COUNT = 0xe,
496− NVME_SC_SGL_INVALID_DATA = 0xf,
497− NVME_SC_SGL_INVALID_METADATA = 0x10,
498− NVME_SC_SGL_INVALID_TYPE = 0x11,
499− NVME_SC_LBA_RANGE = 0x80,
500− NVME_SC_CAP_EXCEEDED = 0x81,
501− NVME_SC_NS_NOT_READY = 0x82,
502− NVME_SC_RESERVATION_CONFLICT = 0x83,
503− NVME_SC_CQ_INVALID = 0x100,
504− NVME_SC_QID_INVALID = 0x101,
505− NVME_SC_QUEUE_SIZE = 0x102,
506− NVME_SC_ABORT_LIMIT = 0x103,
507− NVME_SC_ABORT_MISSING = 0x104,
508− NVME_SC_ASYNC_LIMIT = 0x105,
509− NVME_SC_FIRMWARE_SLOT = 0x106,
510− NVME_SC_FIRMWARE_IMAGE = 0x107,
511− NVME_SC_INVALID_VECTOR = 0x108,
512− NVME_SC_INVALID_LOG_PAGE = 0x109,
513− NVME_SC_INVALID_FORMAT = 0x10a,
514− NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
515− NVME_SC_INVALID_QUEUE = 0x10c,
516− NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
517− NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
518− NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
519− NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
520− NVME_SC_BAD_ATTRIBUTES = 0x180,
521− NVME_SC_INVALID_PI = 0x181,
522− NVME_SC_READ_ONLY = 0x182,
523− NVME_SC_WRITE_FAULT = 0x280,
524− NVME_SC_READ_ERROR = 0x281,
525− NVME_SC_GUARD_CHECK = 0x282,
526− NVME_SC_APPTAG_CHECK = 0x283,
527− NVME_SC_REFTAG_CHECK = 0x284,
528− NVME_SC_COMPARE_FAILED = 0x285,
529− NVME_SC_ACCESS_DENIED = 0x286,
530− NVME_SC_DNR = 0x4000,
531−};
532−
533−struct nvme_completion {
534− __le32 result; /* Used by admin commands to return data */
535− __u32 rsvd;
536− __le16 sq_head; /* how much of this queue may be reclaimed */
537− __le16 sq_id; /* submission queue that generated this entry */
538− __u16 command_id; /* of the command which completed */
539− __le16 status; /* did the command fail, and if so, why? */
540−};
541−
542−struct nvme_user_io {
543− __u8 opcode;
544− __u8 flags;
545− __u16 control;
546− __u16 nblocks;
547− __u16 rsvd;
548− __u64 metadata;
549− __u64 addr;
550− __u64 slba;
551− __u32 dsmgmt;
552− __u32 reftag;
553− __u16 apptag;
554− __u16 appmask;
555−};
556−
557−struct nvme_passthru_cmd {
558− __u8 opcode;
559− __u8 flags;
560− __u16 rsvd1;
561− __u32 nsid;
562− __u32 cdw2;
563− __u32 cdw3;
564− __u64 metadata;
565− __u64 addr;
566− __u32 metadata_len;
567− __u32 data_len;
568− __u32 cdw10;
569− __u32 cdw11;
570− __u32 cdw12;
571− __u32 cdw13;
572− __u32 cdw14;
573− __u32 cdw15;
574− __u32 timeout_ms;
575− __u32 result;
576−};
577−
578−#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
579−
580−#define nvme_admin_cmd nvme_passthru_cmd
581−
582−#define NVME_IOCTL_ID _IO('N', 0x40)
583−#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
584−#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
585−#define NVME_IOCTL_IO_CMD _IOWR('N', 0x43, struct nvme_passthru_cmd)
586−#define NVME_IOCTL_RESET _IO('N', 0x44)
587−#define NVME_IOCTL_SUBSYS_RESET _IO('N', 0x45)
588−
589−#endif /* _UAPI_LINUX_NVME_H */
include/uapi/linux/nvme_ioctl.h+65−0
@@ -0,0 +1,65 @@
1+/*
2+ * Definitions for the NVM Express ioctl interface
3+ * Copyright (c) 2011-2014, Intel Corporation.
4+ *
5+ * This program is free software; you can redistribute it and/or modify it
6+ * under the terms and conditions of the GNU General Public License,
7+ * version 2, as published by the Free Software Foundation.
8+ *
9+ * This program is distributed in the hope it will be useful, but WITHOUT
10+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12+ * more details.
13+ */
14+
15+#ifndef _UAPI_LINUX_NVME_IOCTL_H
16+#define _UAPI_LINUX_NVME_IOCTL_H
17+
18+#include <linux/types.h>
19+
20+struct nvme_user_io {
21+ __u8 opcode;
22+ __u8 flags;
23+ __u16 control;
24+ __u16 nblocks;
25+ __u16 rsvd;
26+ __u64 metadata;
27+ __u64 addr;
28+ __u64 slba;
29+ __u32 dsmgmt;
30+ __u32 reftag;
31+ __u16 apptag;
32+ __u16 appmask;
33+};
34+
35+struct nvme_passthru_cmd {
36+ __u8 opcode;
37+ __u8 flags;
38+ __u16 rsvd1;
39+ __u32 nsid;
40+ __u32 cdw2;
41+ __u32 cdw3;
42+ __u64 metadata;
43+ __u64 addr;
44+ __u32 metadata_len;
45+ __u32 data_len;
46+ __u32 cdw10;
47+ __u32 cdw11;
48+ __u32 cdw12;
49+ __u32 cdw13;
50+ __u32 cdw14;
51+ __u32 cdw15;
52+ __u32 timeout_ms;
53+ __u32 result;
54+};
55+
56+#define nvme_admin_cmd nvme_passthru_cmd
57+
58+#define NVME_IOCTL_ID _IO('N', 0x40)
59+#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
60+#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
61+#define NVME_IOCTL_IO_CMD _IOWR('N', 0x43, struct nvme_passthru_cmd)
62+#define NVME_IOCTL_RESET _IO('N', 0x44)
63+#define NVME_IOCTL_SUBSYS_RESET _IO('N', 0x45)
64+
65+#endif /* _UAPI_LINUX_NVME_IOCTL_H */