History

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon: "The diffstat is a bit spread out thanks to an invasive CPU erratum workaround which missed the merge window and also a bunch of fixes to the recently added MTE selftests. - Fixes to MTE kselftests - Fix return code from KVM Spectre-v2 hypercall - Build fixes for ld.lld and Clang's infamous integrated assembler - Ensure RCU is up and running before we use printk() - Workaround for Cortex-A77 erratum 1508412 - Fix linker warnings from unexpected ELF sections - Ensure PE/COFF sections are 64k aligned" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Change .weak to SYM_FUNC_START_WEAK_PI for arch/arm64/lib/mem*.S arm64/smp: Move rcu_cpu_starting() earlier arm64: Add workaround for Arm Cortex-A77 erratum 1508412 arm64: Add part number for Arm Cortex-A77 arm64: mte: Document that user PSTATE.TCO is ignored by kernel uaccess module: use hidden visibility for weak symbol references arm64: efi: increase EFI PE/COFF header padding to 64 KB arm64: vmlinux.lds: account for spurious empty .igot.plt sections kselftest/arm64: Fix check_user_mem test kselftest/arm64: Fix check_ksm_options test kselftest/arm64: Fix check_mmap_options test kselftest/arm64: Fix check_child_memory test kselftest/arm64: Fix check_tags_inclusion test kselftest/arm64: Fix check_buffer_fill test arm64: avoid -Woverride-init warning KVM: arm64: ARM_SMCCC_ARCH_WORKAROUND_1 doesn't return SMCCC_RET_NOT_REQUIRED arm64: vdso32: Allow ld.lld to properly link the VDSO

Linus Torvalds committed 6 years ago

Commit aab6bf52 parents 11ad2a7 ec9d78034 files · +119 −42Browse files

Unified · Split

34 files
  1. Documentation/arm64/memory-tagging-extension.rst +3 −1
  2. Documentation/arm64/silicon-errata.rst +2 −0
  3. arch/arm64/Kconfig +20 −0
  4. arch/arm64/include/asm/cache.h +1 −0
  5. arch/arm64/include/asm/cpucaps.h +2 −1
  6. arch/arm64/include/asm/cputype.h +2 −0
  7. arch/arm64/include/asm/sysreg.h +9 −0
  8. arch/arm64/kernel/cpu_errata.c +10 −0
  9. arch/arm64/kernel/cpuinfo.c +4 −3
  10. arch/arm64/kernel/efi-header.S +1 −1
  11. arch/arm64/kernel/entry.S +3 −0
  12. arch/arm64/kernel/proton-pack.c +0 −2
  13. arch/arm64/kernel/smp.c +1 −0
  14. arch/arm64/kernel/vdso32/Makefile +12 −11
  15. arch/arm64/kernel/vmlinux.lds.S +1 −1
  16. arch/arm64/kvm/arm.c +2 −1
  17. arch/arm64/kvm/hyp/include/hyp/switch.h +13 −8
  18. arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +1 −1
  19. arch/arm64/kvm/hyp/nvhe/switch.c +1 −1
  20. arch/arm64/kvm/hyp/vhe/switch.c +1 −1
  21. arch/arm64/kvm/hypercalls.c +1 −1
  22. arch/arm64/kvm/sys_regs.c +1 −1
  23. arch/arm64/lib/memcpy.S +1 −2
  24. arch/arm64/lib/memmove.S +1 −2
  25. arch/arm64/lib/memset.S +1 −2
  26. arch/arm64/mm/fault.c +1 −1
  27. include/linux/arm-smccc.h +2 −0
  28. include/linux/module.h +1 −1
  29. tools/testing/selftests/arm64/mte/check_buffer_fill.c +3 −0
  30. tools/testing/selftests/arm64/mte/check_child_memory.c +3 −0
  31. tools/testing/selftests/arm64/mte/check_ksm_options.c +4 −0
  32. tools/testing/selftests/arm64/mte/check_mmap_options.c +4 −0
  33. tools/testing/selftests/arm64/mte/check_tags_inclusion.c +3 −0
  34. tools/testing/selftests/arm64/mte/check_user_mem.c +4 −0
Documentation/arm64/memory-tagging-extension.rst+3−1
@@ -102,7 +102,9 @@ applications. · 101 unmodified lines
102102 system call) are not checked if the user thread tag checking mode is
103103 ``PR_MTE_TCF_NONE`` or ``PR_MTE_TCF_ASYNC``. If the tag checking mode is
104104 ``PR_MTE_TCF_SYNC``, the kernel makes a best effort to check its user
105−address accesses, however it cannot always guarantee it.
105+address accesses, however it cannot always guarantee it. Kernel accesses
106+to user addresses are always performed with an effective ``PSTATE.TCO``
107+value of zero, regardless of the user configuration.
106108
107109 Excluding Tags in the ``IRG``, ``ADDG`` and ``SUBG`` instructions
108110 -----------------------------------------------------------------
Documentation/arm64/silicon-errata.rst+2−0
@@ -90,6 +90,8 @@ stable kernels. · 89 unmodified lines
9090 +----------------+-----------------+-----------------+-----------------------------+
9191 | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
9292 +----------------+-----------------+-----------------+-----------------------------+
93+| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
94++----------------+-----------------+-----------------+-----------------------------+
9395 | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
9496 +----------------+-----------------+-----------------+-----------------------------+
9597 | ARM | Neoverse-N1 | #1349291 | N/A |
arch/arm64/Kconfig+20−0
@@ -636,6 +636,26 @@ config ARM64_ERRATUM_1542419 · 635 unmodified lines
636636
637637 If unsure, say Y.
638638
639+config ARM64_ERRATUM_1508412
640+ bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
641+ default y
642+ help
643+ This option adds a workaround for Arm Cortex-A77 erratum 1508412.
644+
645+ Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
646+ of a store-exclusive or read of PAR_EL1 and a load with device or
647+ non-cacheable memory attributes. The workaround depends on a firmware
648+ counterpart.
649+
650+ KVM guests must also have the workaround implemented or they can
651+ deadlock the system.
652+
653+ Work around the issue by inserting DMB SY barriers around PAR_EL1
654+ register reads and warning KVM users. The DMB barrier is sufficient
655+ to prevent a speculative PAR_EL1 read.
656+
657+ If unsure, say Y.
658+
639659 config CAVIUM_ERRATUM_22375
640660 bool "Cavium erratum 22375, 24313"
641661 default y
arch/arm64/include/asm/cache.h+1−0
@@ -24,6 +24,7 @@ · 23 unmodified lines
2424 #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
2525
2626 #define ICACHE_POLICY_VPIPT 0
27+#define ICACHE_POLICY_RESERVED 1
2728 #define ICACHE_POLICY_VIPT 2
2829 #define ICACHE_POLICY_PIPT 3
2930
arch/arm64/include/asm/cpucaps.h+2−1
@@ -65,7 +65,8 @@ · 64 unmodified lines
6565 #define ARM64_HAS_ARMv8_4_TTL 55
6666 #define ARM64_HAS_TLB_RANGE 56
6767 #define ARM64_MTE 57
68+#define ARM64_WORKAROUND_1508412 58
6869
69−#define ARM64_NCAPS 58
70+#define ARM64_NCAPS 59
7071
7172 #endif /* __ASM_CPUCAPS_H */
arch/arm64/include/asm/cputype.h+2−0
@@ -71,6 +71,7 @@ · 70 unmodified lines
7171 #define ARM_CPU_PART_CORTEX_A55 0xD05
7272 #define ARM_CPU_PART_CORTEX_A76 0xD0B
7373 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C
74+#define ARM_CPU_PART_CORTEX_A77 0xD0D
7475
7576 #define APM_CPU_PART_POTENZA 0x000
7677
@@ -105,6 +106,7 @@ · 28 unmodified lines
105106 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
106107 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
107108 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
109+#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
108110 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
109111 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
110112 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
arch/arm64/include/asm/sysreg.h+9−0
@@ -1007,6 +1007,7 @@ · 1006 unmodified lines
10071007
10081008 #include <linux/build_bug.h>
10091009 #include <linux/types.h>
1010+#include <asm/alternative.h>
10101011
10111012 #define __DEFINE_MRS_MSR_S_REGNUM \
10121013 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
@@ -1095,6 +1096,14 @@ · 82 unmodified lines
10951096 write_sysreg_s(__scs_new, sysreg); \
10961097 } while (0)
10971098
1099+#define read_sysreg_par() ({ \
1100+ u64 par; \
1101+ asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1102+ par = read_sysreg(par_el1); \
1103+ asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1104+ par; \
1105+})
1106+
10981107 #endif
10991108
11001109 #endif /* __ASM_SYSREG_H */
arch/arm64/kernel/cpu_errata.c+10−0
@@ -522,6 +522,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 521 unmodified lines
522522 .matches = has_neoverse_n1_erratum_1542419,
523523 .cpu_enable = cpu_enable_trap_ctr_access,
524524 },
525+#endif
526+#ifdef CONFIG_ARM64_ERRATUM_1508412
527+ {
528+ /* we depend on the firmware portion for correctness */
529+ .desc = "ARM erratum 1508412 (kernel portion)",
530+ .capability = ARM64_WORKAROUND_1508412,
531+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
532+ 0, 0,
533+ 1, 0),
534+ },
525535 #endif
526536 {
527537 }
arch/arm64/kernel/cpuinfo.c+4−3
@@ -34,10 +34,10 @@ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); · 33 unmodified lines
3434 static struct cpuinfo_arm64 boot_cpu_data;
3535
3636 static const char *icache_policy_str[] = {
37− [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
37+ [ICACHE_POLICY_VPIPT] = "VPIPT",
38+ [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
3839 [ICACHE_POLICY_VIPT] = "VIPT",
3940 [ICACHE_POLICY_PIPT] = "PIPT",
40− [ICACHE_POLICY_VPIPT] = "VPIPT",
4141 };
4242
4343 unsigned long __icache_flags;
@@ -334,10 +334,11 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) · 290 unmodified lines
334334 case ICACHE_POLICY_VPIPT:
335335 set_bit(ICACHEF_VPIPT, &__icache_flags);
336336 break;
337− default:
337+ case ICACHE_POLICY_RESERVED:
338338 case ICACHE_POLICY_VIPT:
339339 /* Assume aliasing */
340340 set_bit(ICACHEF_ALIASING, &__icache_flags);
341+ break;
341342 }
342343
343344 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
arch/arm64/kernel/efi-header.S+1−1
@@ -147,6 +147,6 @@ efi_debug_entry: · 146 unmodified lines
147147 * correctly at this alignment, we must ensure that .text is
148148 * placed at a 4k boundary in the Image to begin with.
149149 */
150− .align 12
150+ .balign SEGMENT_ALIGN
151151 efi_header_end:
152152 .endm
arch/arm64/kernel/entry.S+3−0
@@ -365,6 +365,9 @@ alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 · 364 unmodified lines
365365 br x30
366366 #endif
367367 .else
368+ /* Ensure any device/NC reads complete */
369+ alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
370+
368371 eret
369372 .endif
370373 sb
arch/arm64/kernel/proton-pack.c+0−2
@@ -135,8 +135,6 @@ static enum mitigation_state spectre_v2_get_cpu_hw_mitigation_state(void) · 134 unmodified lines
135135 return SPECTRE_VULNERABLE;
136136 }
137137
138−#define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED (1)
139−
140138 static enum mitigation_state spectre_v2_get_cpu_fw_mitigation_state(void)
141139 {
142140 int ret;
arch/arm64/kernel/smp.c+1−0
@@ -222,6 +222,7 @@ asmlinkage notrace void secondary_start_kernel(void) · 221 unmodified lines
222222 if (system_uses_irq_prio_masking())
223223 init_gic_priority_masking();
224224
225+ rcu_cpu_starting(cpu);
225226 preempt_disable();
226227 trace_hardirqs_off();
227228
arch/arm64/kernel/vdso32/Makefile+12−11
@@ -22,16 +22,21 @@ endif · 21 unmodified lines
2222
2323 CC_COMPAT ?= $(CC)
2424 CC_COMPAT += $(CC_COMPAT_CLANG_FLAGS)
25+
26+ifneq ($(LLVM),)
27+LD_COMPAT ?= $(LD)
28+else
29+LD_COMPAT ?= $(CROSS_COMPILE_COMPAT)ld
30+endif
2531 else
2632 CC_COMPAT ?= $(CROSS_COMPILE_COMPAT)gcc
33+LD_COMPAT ?= $(CROSS_COMPILE_COMPAT)ld
2734 endif
2835
2936 cc32-option = $(call try-run,\
3037 $(CC_COMPAT) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2))
3138 cc32-disable-warning = $(call try-run,\
3239 $(CC_COMPAT) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
33−cc32-ldoption = $(call try-run,\
34− $(CC_COMPAT) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
3540 cc32-as-instr = $(call try-run,\
3641 printf "%b\n" "$(1)" | $(CC_COMPAT) $(VDSO_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3))
3742
@@ -122,14 +127,10 @@ dmbinstr := $(call cc32-as-instr,dmb ishld,-DCONFIG_AS_DMB_ISHLD=1) · 84 unmodified lines
122127 VDSO_CFLAGS += $(dmbinstr)
123128 VDSO_AFLAGS += $(dmbinstr)
124129
125−VDSO_LDFLAGS := $(VDSO_CPPFLAGS)
126130 # From arm vDSO Makefile
127−VDSO_LDFLAGS += -Wl,-Bsymbolic -Wl,--no-undefined -Wl,-soname=linux-vdso.so.1
128−VDSO_LDFLAGS += -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096
129−VDSO_LDFLAGS += -nostdlib -shared -mfloat-abi=soft
130−VDSO_LDFLAGS += -Wl,--hash-style=sysv
131−VDSO_LDFLAGS += -Wl,--build-id=sha1
132−VDSO_LDFLAGS += $(call cc32-ldoption,-fuse-ld=bfd)
131+VDSO_LDFLAGS += -Bsymbolic --no-undefined -soname=linux-vdso.so.1
132+VDSO_LDFLAGS += -z max-page-size=4096 -z common-page-size=4096
133+VDSO_LDFLAGS += -nostdlib -shared --hash-style=sysv --build-id=sha1
133134
134135
135136 # Borrow vdsomunge.c from the arm vDSO
@@ -189,8 +190,8 @@ quiet_cmd_vdsold_and_vdso_check = LD32 $@ · 53 unmodified lines
189190 cmd_vdsold_and_vdso_check = $(cmd_vdsold); $(cmd_vdso_check)
190191
191192 quiet_cmd_vdsold = LD32 $@
192− cmd_vdsold = $(CC_COMPAT) -Wp,-MD,$(depfile) $(VDSO_LDFLAGS) \
193− -Wl,-T $(filter %.lds,$^) $(filter %.o,$^) -o $@
193+ cmd_vdsold = $(LD_COMPAT) $(VDSO_LDFLAGS) \
194+ -T $(filter %.lds,$^) $(filter %.o,$^) -o $@
194195 quiet_cmd_vdsocc = CC32 $@
195196 cmd_vdsocc = $(CC_COMPAT) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) -c -o $@ $<
196197 quiet_cmd_vdsocc_gettimeofday = CC32 $@
arch/arm64/kernel/vmlinux.lds.S+1−1
@@ -278,7 +278,7 @@ SECTIONS · 277 unmodified lines
278278 * explicitly check instead of blindly discarding.
279279 */
280280 .plt : {
281− *(.plt) *(.plt.*) *(.iplt) *(.igot)
281+ *(.plt) *(.plt.*) *(.iplt) *(.igot .igot.plt)
282282 }
283283 ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!")
284284
arch/arm64/kvm/arm.c+2−1
@@ -1719,7 +1719,8 @@ int kvm_arch_init(void *opaque) · 1718 unmodified lines
17191719 return -ENODEV;
17201720 }
17211721
1722− if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE))
1722+ if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) ||
1723+ cpus_have_final_cap(ARM64_WORKAROUND_1508412))
17231724 kvm_info("Guests without required CPU erratum workarounds can deadlock system!\n" \
17241725 "Only trusted guests should be used on this system.\n");
17251726
arch/arm64/kvm/hyp/include/hyp/switch.h+13−8
@@ -140,9 +140,9 @@ static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar) · 139 unmodified lines
140140 * We do need to save/restore PAR_EL1 though, as we haven't
141141 * saved the guest context yet, and we may return early...
142142 */
143− par = read_sysreg(par_el1);
143+ par = read_sysreg_par();
144144 if (!__kvm_at("s1e1r", far))
145− tmp = read_sysreg(par_el1);
145+ tmp = read_sysreg_par();
146146 else
147147 tmp = SYS_PAR_EL1_F; /* back to the guest */
148148 write_sysreg(par, par_el1);
@@ -421,7 +421,7 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 272 unmodified lines
421421 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
422422 kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 &&
423423 handle_tx2_tvm(vcpu))
424− return true;
424+ goto guest;
425425
426426 /*
427427 * We trap the first access to the FP/SIMD to save the host context
@@ -431,13 +431,13 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 3 unmodified lines
431431 * Similarly for trapped SVE accesses.
432432 */
433433 if (__hyp_handle_fpsimd(vcpu))
434− return true;
434+ goto guest;
435435
436436 if (__hyp_handle_ptrauth(vcpu))
437− return true;
437+ goto guest;
438438
439439 if (!__populate_fault_info(vcpu))
440− return true;
440+ goto guest;
441441
442442 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
443443 bool valid;
@@ -452,7 +452,7 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 8 unmodified lines
452452 int ret = __vgic_v2_perform_cpuif_access(vcpu);
453453
454454 if (ret == 1)
455− return true;
455+ goto guest;
456456
457457 /* Promote an illegal access to an SError.*/
458458 if (ret == -1)
@@ -468,12 +468,17 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 9 unmodified lines
468468 int ret = __vgic_v3_perform_cpuif_access(vcpu);
469469
470470 if (ret == 1)
471− return true;
471+ goto guest;
472472 }
473473
474474 exit:
475475 /* Return to the host kernel and handle the exit */
476476 return false;
477+
478+guest:
479+ /* Re-enter the guest */
480+ asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
481+ return true;
477482 }
478483
479484 static inline void __kvm_unexpected_el2_exception(void)
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h+1−1
@@ -43,7 +43,7 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) · 42 unmodified lines
4343 ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
4444 ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
4545 ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
46− ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg(par_el1);
46+ ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
4747 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
4848
4949 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
arch/arm64/kvm/hyp/nvhe/switch.c+1−1
@@ -250,7 +250,7 @@ void __noreturn hyp_panic(void) · 249 unmodified lines
250250 {
251251 u64 spsr = read_sysreg_el2(SYS_SPSR);
252252 u64 elr = read_sysreg_el2(SYS_ELR);
253− u64 par = read_sysreg(par_el1);
253+ u64 par = read_sysreg_par();
254254 bool restore_host = true;
255255 struct kvm_cpu_context *host_ctxt;
256256 struct kvm_vcpu *vcpu;
arch/arm64/kvm/hyp/vhe/switch.c+1−1
@@ -215,7 +215,7 @@ void __noreturn hyp_panic(void) · 214 unmodified lines
215215 {
216216 u64 spsr = read_sysreg_el2(SYS_SPSR);
217217 u64 elr = read_sysreg_el2(SYS_ELR);
218− u64 par = read_sysreg(par_el1);
218+ u64 par = read_sysreg_par();
219219
220220 __hyp_call_panic(spsr, elr, par);
221221 unreachable();
arch/arm64/kvm/hypercalls.c+1−1
@@ -31,7 +31,7 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) · 30 unmodified lines
3131 val = SMCCC_RET_SUCCESS;
3232 break;
3333 case SPECTRE_UNAFFECTED:
34− val = SMCCC_RET_NOT_REQUIRED;
34+ val = SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED;
3535 break;
3636 }
3737 break;
arch/arm64/kvm/sys_regs.c+1−1
@@ -95,7 +95,7 @@ static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) · 94 unmodified lines
9595 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
9696 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
9797 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
98− case PAR_EL1: *val = read_sysreg_s(SYS_PAR_EL1); break;
98+ case PAR_EL1: *val = read_sysreg_par(); break;
9999 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
100100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
101101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
arch/arm64/lib/memcpy.S+1−2
@@ -56,9 +56,8 @@ · 55 unmodified lines
5656 stp \reg1, \reg2, [\ptr], \val
5757 .endm
5858
59− .weak memcpy
6059 SYM_FUNC_START_ALIAS(__memcpy)
61−SYM_FUNC_START_PI(memcpy)
60+SYM_FUNC_START_WEAK_PI(memcpy)
6261 #include "copy_template.S"
6362 ret
6463 SYM_FUNC_END_PI(memcpy)
arch/arm64/lib/memmove.S+1−2
@@ -45,9 +45,8 @@ C_h .req x12 · 44 unmodified lines
4545 D_l .req x13
4646 D_h .req x14
4747
48− .weak memmove
4948 SYM_FUNC_START_ALIAS(__memmove)
50−SYM_FUNC_START_PI(memmove)
49+SYM_FUNC_START_WEAK_PI(memmove)
5150 cmp dstin, src
5251 b.lo __memcpy
5352 add tmp1, src, count
arch/arm64/lib/memset.S+1−2
@@ -42,9 +42,8 @@ dst .req x8 · 41 unmodified lines
4242 tmp3w .req w9
4343 tmp3 .req x9
4444
45− .weak memset
4645 SYM_FUNC_START_ALIAS(__memset)
47−SYM_FUNC_START_PI(memset)
46+SYM_FUNC_START_WEAK_PI(memset)
4847 mov dst, dstin /* Preserve return value. */
4948 and A_lw, val, #255
5049 orr A_lw, A_lw, A_lw, lsl #8
arch/arm64/mm/fault.c+1−1
@@ -262,7 +262,7 @@ static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, · 261 unmodified lines
262262 local_irq_save(flags);
263263 asm volatile("at s1e1r, %0" :: "r" (addr));
264264 isb();
265− par = read_sysreg(par_el1);
265+ par = read_sysreg_par();
266266 local_irq_restore(flags);
267267
268268 /*
include/linux/arm-smccc.h+2−0
@@ -87,6 +87,8 @@ · 86 unmodified lines
8787 ARM_SMCCC_SMC_32, \
8888 0, 0x7fff)
8989
90+#define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED 1
91+
9092 /* Paravirtualised time calls (defined by ARM DEN0057A) */
9193 #define ARM_SMCCC_HV_PV_TIME_FEATURES \
9294 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
include/linux/module.h+1−1
@@ -740,7 +740,7 @@ static inline bool within_module(unsigned long addr, const struct module *mod) · 739 unmodified lines
740740 }
741741
742742 /* Get/put a kernel symbol (calls should be symmetric) */
743−#define symbol_get(x) ({ extern typeof(x) x __attribute__((weak)); &(x); })
743+#define symbol_get(x) ({ extern typeof(x) x __attribute__((weak,visibility("hidden"))); &(x); })
744744 #define symbol_put(x) do { } while (0)
745745 #define symbol_put_addr(x) do { } while (0)
746746
tools/testing/selftests/arm64/mte/check_buffer_fill.c+3−0
@@ -417,6 +417,9 @@ int main(int argc, char *argv[]) · 416 unmodified lines
417417 /* Register SIGSEGV handler */
418418 mte_register_signal(SIGSEGV, mte_default_handler);
419419
420+ /* Set test plan */
421+ ksft_set_plan(20);
422+
420423 /* Buffer by byte tests */
421424 evaluate_test(check_buffer_by_byte(USE_MMAP, MTE_SYNC_ERR),
422425 "Check buffer correctness by byte with sync err mode and mmap memory\n");
tools/testing/selftests/arm64/mte/check_child_memory.c+3−0
@@ -163,6 +163,9 @@ int main(int argc, char *argv[]) · 162 unmodified lines
163163 mte_register_signal(SIGSEGV, mte_default_handler);
164164 mte_register_signal(SIGBUS, mte_default_handler);
165165
166+ /* Set test plan */
167+ ksft_set_plan(12);
168+
166169 evaluate_test(check_child_memory_mapping(USE_MMAP, MTE_SYNC_ERR, MAP_PRIVATE),
167170 "Check child anonymous memory with private mapping, precise mode and mmap memory\n");
168171 evaluate_test(check_child_memory_mapping(USE_MMAP, MTE_SYNC_ERR, MAP_SHARED),
tools/testing/selftests/arm64/mte/check_ksm_options.c+4−0
@@ -140,6 +140,10 @@ int main(int argc, char *argv[]) · 139 unmodified lines
140140 /* Register signal handlers */
141141 mte_register_signal(SIGBUS, mte_default_handler);
142142 mte_register_signal(SIGSEGV, mte_default_handler);
143+
144+ /* Set test plan */
145+ ksft_set_plan(4);
146+
143147 /* Enable KSM */
144148 mte_ksm_setup();
145149
tools/testing/selftests/arm64/mte/check_mmap_options.c+4−0
@@ -205,7 +205,11 @@ int main(int argc, char *argv[]) · 204 unmodified lines
205205 mte_register_signal(SIGBUS, mte_default_handler);
206206 mte_register_signal(SIGSEGV, mte_default_handler);
207207
208+ /* Set test plan */
209+ ksft_set_plan(22);
210+
208211 mte_enable_pstate_tco();
212+
209213 evaluate_test(check_anonymous_memory_mapping(USE_MMAP, MTE_SYNC_ERR, MAP_PRIVATE, TAG_CHECK_OFF),
210214 "Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off\n");
211215 evaluate_test(check_file_memory_mapping(USE_MPROTECT, MTE_SYNC_ERR, MAP_PRIVATE, TAG_CHECK_OFF),
tools/testing/selftests/arm64/mte/check_tags_inclusion.c+3−0
@@ -170,6 +170,9 @@ int main(int argc, char *argv[]) · 169 unmodified lines
170170 /* Register SIGSEGV handler */
171171 mte_register_signal(SIGSEGV, mte_default_handler);
172172
173+ /* Set test plan */
174+ ksft_set_plan(4);
175+
173176 evaluate_test(check_single_included_tags(USE_MMAP, MTE_SYNC_ERR),
174177 "Check an included tag value with sync mode\n");
175178 evaluate_test(check_multiple_included_tags(USE_MMAP, MTE_SYNC_ERR),
tools/testing/selftests/arm64/mte/check_user_mem.c+4−0
@@ -92,9 +92,13 @@ int main(int argc, char *argv[]) · 91 unmodified lines
9292 err = mte_default_setup();
9393 if (err)
9494 return err;
95+
9596 /* Register signal handlers */
9697 mte_register_signal(SIGSEGV, mte_default_handler);
9798
99+ /* Set test plan */
100+ ksft_set_plan(4);
101+
98102 evaluate_test(check_usermem_access_fault(USE_MMAP, MTE_SYNC_ERR, MAP_PRIVATE),
99103 "Check memory access from kernel in sync mode, private mapping and mmap memory\n");
100104 evaluate_test(check_usermem_access_fault(USE_MMAP, MTE_SYNC_ERR, MAP_SHARED),

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