Pull rdma updates from Jason Gunthorpe: "Usual size of updates, a new driver, and most of the bulk focusing on rxe: - Usual typos, style, and language updates - Driver updates for mlx5, irdma, siw, rts, srp, hfi1, hns, erdma, mlx4, srp - Lots of RXE updates: * Improve reply error handling for bad MR operations * Code tidying * Debug printing uses common loggers * Remove half implemented RD related stuff * Support IBA's recently defined Atomic Write and Flush operations - erdma support for atomic operations - New driver 'mana' for Ethernet HW available in Azure VMs. This driver only supports DPDK" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (122 commits) IB/IPoIB: Fix queue count inconsistency for PKEY child interfaces RDMA: Add missed netdev_put() for the netdevice_tracker RDMA/rxe: Enable RDMA FLUSH capability for rxe device RDMA/cm: Make QP FLUSHABLE for supported device RDMA/rxe: Implement flush completion RDMA/rxe: Implement flush execution in responder side RDMA/rxe: Implement RC RDMA FLUSH service in requester side RDMA/rxe: Extend rxe packet format to support flush RDMA/rxe: Allow registering persistent flag for pmem MR only RDMA/rxe: Extend rxe user ABI to support flush RDMA: Extend RDMA kernel verbs ABI to support flush RDMA: Extend RDMA user ABI to support flush RDMA/rxe: Fix incorrect responder length checking RDMA/rxe: Fix oops with zero length reads RDMA/mlx5: Remove not-used IB_FLOW_SPEC_IB define RDMA/hns: Fix XRC caps on HIP08 RDMA/hns: Fix error code of CMD RDMA/hns: Fix page size cap from firmware RDMA/hns: Fix PBL page MTR find RDMA/hns: Fix AH attr queried by query_qp ...
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| @@ -85,11 +85,26 @@ struct hns_roce_ib_create_qp_resp { · 84 unmodified lines | |||
| 85 | __aligned_u64 dwqe_mmap_key; | 85 | __aligned_u64 dwqe_mmap_key; |
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | enum { | ||
| 89 | HNS_ROCE_EXSGE_FLAGS = 1 << 0, | ||
| 90 | }; | ||
| 91 | |||
| 92 | enum { | ||
| 93 | HNS_ROCE_RSP_EXSGE_FLAGS = 1 << 0, | ||
| 94 | }; | ||
| 95 | |||
| 88 | struct hns_roce_ib_alloc_ucontext_resp { | 96 | struct hns_roce_ib_alloc_ucontext_resp { |
| 89 | __u32 qp_tab_size; | 97 | __u32 qp_tab_size; |
| 90 | __u32 cqe_size; | 98 | __u32 cqe_size; |
| 91 | __u32 srq_tab_size; | 99 | __u32 srq_tab_size; |
| 92 | __u32 reserved; | 100 | __u32 reserved; |
| 101 | __u32 config; | ||
| 102 | __u32 max_inline_data; | ||
| 103 | }; | ||
| 104 | |||
| 105 | struct hns_roce_ib_alloc_ucontext { | ||
| 106 | __u32 config; | ||
| 107 | __u32 reserved; | ||
| 93 | }; | 108 | }; |
| 94 | 109 | ||
| 95 | struct hns_roce_ib_alloc_pd_resp { | 110 | struct hns_roce_ib_alloc_pd_resp { |
| @@ -57,6 +57,8 @@ enum ib_uverbs_access_flags { · 56 unmodified lines | |||
| 57 | IB_UVERBS_ACCESS_ZERO_BASED = 1 << 5, | 57 | IB_UVERBS_ACCESS_ZERO_BASED = 1 << 5, |
| 58 | IB_UVERBS_ACCESS_ON_DEMAND = 1 << 6, | 58 | IB_UVERBS_ACCESS_ON_DEMAND = 1 << 6, |
| 59 | IB_UVERBS_ACCESS_HUGETLB = 1 << 7, | 59 | IB_UVERBS_ACCESS_HUGETLB = 1 << 7, |
| 60 | IB_UVERBS_ACCESS_FLUSH_GLOBAL = 1 << 8, | ||
| 61 | IB_UVERBS_ACCESS_FLUSH_PERSISTENT = 1 << 9, | ||
| 60 | 62 | ||
| 61 | IB_UVERBS_ACCESS_RELAXED_ORDERING = IB_UVERBS_ACCESS_OPTIONAL_FIRST, | 63 | IB_UVERBS_ACCESS_RELAXED_ORDERING = IB_UVERBS_ACCESS_OPTIONAL_FIRST, |
| 62 | IB_UVERBS_ACCESS_OPTIONAL_RANGE = | 64 | IB_UVERBS_ACCESS_OPTIONAL_RANGE = |
| @@ -251,6 +253,7 @@ enum rdma_driver_id { · 188 unmodified lines | |||
| 251 | RDMA_DRIVER_EFA, | 253 | RDMA_DRIVER_EFA, |
| 252 | RDMA_DRIVER_SIW, | 254 | RDMA_DRIVER_SIW, |
| 253 | RDMA_DRIVER_ERDMA, | 255 | RDMA_DRIVER_ERDMA, |
| 256 | RDMA_DRIVER_MANA, | ||
| 254 | }; | 257 | }; |
| 255 | 258 | ||
| 256 | enum ib_uverbs_gid_type { | 259 | enum ib_uverbs_gid_type { |
| @@ -105,6 +105,18 @@ enum { · 104 unmodified lines | |||
| 105 | IB_USER_VERBS_EX_CMD_MODIFY_CQ | 105 | IB_USER_VERBS_EX_CMD_MODIFY_CQ |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | /* see IBA A19.4.1.1 Placement Types */ | ||
| 109 | enum ib_placement_type { | ||
| 110 | IB_FLUSH_GLOBAL = 1U << 0, | ||
| 111 | IB_FLUSH_PERSISTENT = 1U << 1, | ||
| 112 | }; | ||
| 113 | |||
| 114 | /* see IBA A19.4.1.2 Selectivity Level */ | ||
| 115 | enum ib_selectivity_level { | ||
| 116 | IB_FLUSH_RANGE = 0, | ||
| 117 | IB_FLUSH_MR, | ||
| 118 | }; | ||
| 119 | |||
| 108 | /* | 120 | /* |
| 109 | * Make sure that all structs defined in this file remain laid out so | 121 | * Make sure that all structs defined in this file remain laid out so |
| 110 | * that they pack the same way on 32-bit and 64-bit architectures (to | 122 | * that they pack the same way on 32-bit and 64-bit architectures (to |
| @@ -466,6 +478,8 @@ enum ib_uverbs_wc_opcode { · 355 unmodified lines | |||
| 466 | IB_UVERBS_WC_BIND_MW = 5, | 478 | IB_UVERBS_WC_BIND_MW = 5, |
| 467 | IB_UVERBS_WC_LOCAL_INV = 6, | 479 | IB_UVERBS_WC_LOCAL_INV = 6, |
| 468 | IB_UVERBS_WC_TSO = 7, | 480 | IB_UVERBS_WC_TSO = 7, |
| 481 | IB_UVERBS_WC_FLUSH = 8, | ||
| 482 | IB_UVERBS_WC_ATOMIC_WRITE = 9, | ||
| 469 | }; | 483 | }; |
| 470 | 484 | ||
| 471 | struct ib_uverbs_wc { | 485 | struct ib_uverbs_wc { |
| @@ -784,6 +798,8 @@ enum ib_uverbs_wr_opcode { · 312 unmodified lines | |||
| 784 | IB_UVERBS_WR_RDMA_READ_WITH_INV = 11, | 798 | IB_UVERBS_WR_RDMA_READ_WITH_INV = 11, |
| 785 | IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12, | 799 | IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12, |
| 786 | IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13, | 800 | IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13, |
| 801 | IB_UVERBS_WR_FLUSH = 14, | ||
| 802 | IB_UVERBS_WR_ATOMIC_WRITE = 15, | ||
| 787 | /* Review enum ib_wr_opcode before modifying this */ | 803 | /* Review enum ib_wr_opcode before modifying this */ |
| 788 | }; | 804 | }; |
| 789 | 805 | ||
| @@ -1331,6 +1347,11 @@ enum ib_uverbs_device_cap_flags { · 541 unmodified lines | |||
| 1331 | /* Deprecated. Please use IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS. */ | 1347 | /* Deprecated. Please use IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS. */ |
| 1332 | IB_UVERBS_DEVICE_RAW_SCATTER_FCS = 1ULL << 34, | 1348 | IB_UVERBS_DEVICE_RAW_SCATTER_FCS = 1ULL << 34, |
| 1333 | IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 1ULL << 36, | 1349 | IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 1ULL << 36, |
| 1350 | /* Flush placement types */ | ||
| 1351 | IB_UVERBS_DEVICE_FLUSH_GLOBAL = 1ULL << 38, | ||
| 1352 | IB_UVERBS_DEVICE_FLUSH_PERSISTENT = 1ULL << 39, | ||
| 1353 | /* Atomic write attributes */ | ||
| 1354 | IB_UVERBS_DEVICE_ATOMIC_WRITE = 1ULL << 40, | ||
| 1334 | }; | 1355 | }; |
| 1335 | 1356 | ||
| 1336 | enum ib_uverbs_raw_packet_caps { | 1357 | enum ib_uverbs_raw_packet_caps { |
| @@ -0,0 +1,66 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) */ | ||
| 2 | /* | ||
| 3 | * Copyright (c) 2022, Microsoft Corporation. All rights reserved. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef MANA_ABI_USER_H | ||
| 7 | #define MANA_ABI_USER_H | ||
| 8 | |||
| 9 | #include <linux/types.h> | ||
| 10 | #include <rdma/ib_user_ioctl_verbs.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Increment this value if any changes that break userspace ABI | ||
| 14 | * compatibility are made. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #define MANA_IB_UVERBS_ABI_VERSION 1 | ||
| 18 | |||
| 19 | struct mana_ib_create_cq { | ||
| 20 | __aligned_u64 buf_addr; | ||
| 21 | }; | ||
| 22 | |||
| 23 | struct mana_ib_create_qp { | ||
| 24 | __aligned_u64 sq_buf_addr; | ||
| 25 | __u32 sq_buf_size; | ||
| 26 | __u32 port; | ||
| 27 | }; | ||
| 28 | |||
| 29 | struct mana_ib_create_qp_resp { | ||
| 30 | __u32 sqid; | ||
| 31 | __u32 cqid; | ||
| 32 | __u32 tx_vp_offset; | ||
| 33 | __u32 reserved; | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct mana_ib_create_wq { | ||
| 37 | __aligned_u64 wq_buf_addr; | ||
| 38 | __u32 wq_buf_size; | ||
| 39 | __u32 reserved; | ||
| 40 | }; | ||
| 41 | |||
| 42 | /* RX Hash function flags */ | ||
| 43 | enum mana_ib_rx_hash_function_flags { | ||
| 44 | MANA_IB_RX_HASH_FUNC_TOEPLITZ = 1 << 0, | ||
| 45 | }; | ||
| 46 | |||
| 47 | struct mana_ib_create_qp_rss { | ||
| 48 | __aligned_u64 rx_hash_fields_mask; | ||
| 49 | __u8 rx_hash_function; | ||
| 50 | __u8 reserved[7]; | ||
| 51 | __u32 rx_hash_key_len; | ||
| 52 | __u8 rx_hash_key[40]; | ||
| 53 | __u32 port; | ||
| 54 | }; | ||
| 55 | |||
| 56 | struct rss_resp_entry { | ||
| 57 | __u32 cqid; | ||
| 58 | __u32 wqid; | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct mana_ib_create_qp_rss_resp { | ||
| 62 | __aligned_u64 num_entries; | ||
| 63 | struct rss_resp_entry entries[64]; | ||
| 64 | }; | ||
| 65 | |||
| 66 | #endif | ||
| @@ -82,6 +82,13 @@ struct rxe_send_wr { · 81 unmodified lines | |||
| 82 | __u32 invalidate_rkey; | 82 | __u32 invalidate_rkey; |
| 83 | } ex; | 83 | } ex; |
| 84 | union { | 84 | union { |
| 85 | struct { | ||
| 86 | __aligned_u64 remote_addr; | ||
| 87 | __u32 length; | ||
| 88 | __u32 rkey; | ||
| 89 | __u8 type; | ||
| 90 | __u8 level; | ||
| 91 | } flush; | ||
| 85 | struct { | 92 | struct { |
| 86 | __aligned_u64 remote_addr; | 93 | __aligned_u64 remote_addr; |
| 87 | __u32 rkey; | 94 | __u32 rkey; |
| @@ -146,6 +153,7 @@ struct rxe_dma_info { · 58 unmodified lines | |||
| 146 | __u32 reserved; | 153 | __u32 reserved; |
| 147 | union { | 154 | union { |
| 148 | __DECLARE_FLEX_ARRAY(__u8, inline_data); | 155 | __DECLARE_FLEX_ARRAY(__u8, inline_data); |
| 156 | __DECLARE_FLEX_ARRAY(__u8, atomic_wr); | ||
| 149 | __DECLARE_FLEX_ARRAY(struct rxe_sge, sge); | 157 | __DECLARE_FLEX_ARRAY(struct rxe_sge, sge); |
| 150 | }; | 158 | }; |
| 151 | }; | 159 | }; |