History

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie: "This contains fixes for exynos, amdgpu, radeon, i915 and qxl. It also contains some fixes to the core drm edid parser. qxl: - fix for a cursor hotspot issue radeon: - some MST fixes that I've been running locally and make my monitor a bit happier exynos: - fix some regressions and build fixes amdgpu: - a couple of small fixes i915: - two DP MST fixes and a couple of other regression fixes Nothing too out of the ordinary or surprising at this point" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/exynos: Use VIDEO_SAMSUNG_S5P_G2D=n as G2D Kconfig dependency drm/exynos: fix a warning message drm/exynos: mic: fix an error code drm/exynos: fimd: fix broken dp_clock control drm/exynos: build fbdev code conditionally drm/exynos: fix adjusted_mode pointer in exynos_plane_mode_set drm/exynos: fix error handling in exynos_drm_subdrv_open drm/amd/amdgpu: fix irq domain remove for tonga ih drm/i915: fix deadlock on lid open drm/radeon: use helper for mst connector dpms. drm/radeon/mst: port some MST setup code from DAL. drm/amdgpu: add invisible pin size statistic drm/edid: Fix DMT 1024x768@43Hz (interlaced) timings drm/i915: Exit cherryview_irq_handler() after one pass drm/i915: Call intel_dp_mst_resume() before resuming displays drm/i915: Fix race condition in intel_dp_destroy_mst_connector() drm/edid: Fix parsing of EDID 1.4 Established Timings III descriptor drm/edid: Fix EDID Established Timings I and II drm/qxl: fix cursor position with non-zero hotspot

Linus Torvalds committed 10 years ago

Commit ab5f9eb2 parents 60ea7bb ff3e84e22 files · +104 −62Browse files

Unified · Split

22 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu.h +1 −0
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +1 −1
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +8 −4
  4. drivers/gpu/drm/amd/amdgpu/tonga_ih.c +1 −1
  5. drivers/gpu/drm/drm_edid.c +5 −5
  6. drivers/gpu/drm/exynos/Kconfig +1 −1
  7. drivers/gpu/drm/exynos/Makefile +3 −3
  8. drivers/gpu/drm/exynos/exynos_drm_core.c +1 −1
  9. drivers/gpu/drm/exynos/exynos_drm_fb.c +0 −11
  10. drivers/gpu/drm/exynos/exynos_drm_fbdev.c +11 −0
  11. drivers/gpu/drm/exynos/exynos_drm_fbdev.h +22 −1
  12. drivers/gpu/drm/exynos/exynos_drm_fimd.c +1 −1
  13. drivers/gpu/drm/exynos/exynos_drm_mic.c +2 −1
  14. drivers/gpu/drm/exynos/exynos_drm_plane.c +7 −5
  15. drivers/gpu/drm/i915/i915_drv.c +2 −2
  16. drivers/gpu/drm/i915/i915_irq.c +2 −2
  17. drivers/gpu/drm/i915/intel_dp_mst.c +2 −4
  18. drivers/gpu/drm/i915/intel_lvds.c +1 −4
  19. drivers/gpu/drm/qxl/qxl_display.c +9 −4
  20. drivers/gpu/drm/qxl/qxl_drv.h +2 −0
  21. drivers/gpu/drm/radeon/ni_reg.h +2 −0
  22. drivers/gpu/drm/radeon/radeon_dp_mst.c +20 −11
drivers/gpu/drm/amd/amdgpu/amdgpu.h+1−0
@@ -2034,6 +2034,7 @@ struct amdgpu_device { · 2033 unmodified lines
20342034
20352035 /* tracking pinned memory */
20362036 u64 vram_pin_size;
2037+ u64 invisible_pin_size;
20372038 u64 gart_pin_size;
20382039
20392040 /* amdkfd interface */
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+1−1
@@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 383 unmodified lines
384384 vram_gtt.vram_size = adev->mc.real_vram_size;
385385 vram_gtt.vram_size -= adev->vram_pin_size;
386386 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
387− vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
387+ vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
388388 vram_gtt.gtt_size = adev->mc.gtt_size;
389389 vram_gtt.gtt_size -= adev->gart_pin_size;
390390 return copy_to_user(out, &vram_gtt,
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+8−4
@@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, · 423 unmodified lines
424424 bo->pin_count = 1;
425425 if (gpu_addr != NULL)
426426 *gpu_addr = amdgpu_bo_gpu_offset(bo);
427− if (domain == AMDGPU_GEM_DOMAIN_VRAM)
427+ if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
428428 bo->adev->vram_pin_size += amdgpu_bo_size(bo);
429− else
429+ if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
430+ bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
431+ } else
430432 bo->adev->gart_pin_size += amdgpu_bo_size(bo);
431433 } else {
432434 dev_err(bo->adev->dev, "%p pin failed\n", bo);
@@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) · 23 unmodified lines
456458 }
457459 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
458460 if (likely(r == 0)) {
459− if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
461+ if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
460462 bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
461− else
463+ if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
464+ bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
465+ } else
462466 bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
463467 } else {
464468 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
drivers/gpu/drm/amd/amdgpu/tonga_ih.c+1−1
@@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle) · 306 unmodified lines
307307
308308 amdgpu_irq_fini(adev);
309309 amdgpu_ih_ring_fini(adev);
310− amdgpu_irq_add_domain(adev);
310+ amdgpu_irq_remove_domain(adev);
311311
312312 return 0;
313313 }
drivers/gpu/drm/drm_edid.c+5−5
@@ -205,7 +205,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { · 204 unmodified lines
205205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
206206 /* 0x0f - 1024x768@43Hz, interlace */
207207 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
208− 1208, 1264, 0, 768, 768, 772, 817, 0,
208+ 1208, 1264, 0, 768, 768, 776, 817, 0,
209209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
210210 DRM_MODE_FLAG_INTERLACE) },
211211 /* 0x10 - 1024x768@60Hz */
@@ -522,12 +522,12 @@ static const struct drm_display_mode edid_est_modes[] = { · 310 unmodified lines
522522 720, 840, 0, 480, 481, 484, 500, 0,
523523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
524524 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
525− 704, 832, 0, 480, 489, 491, 520, 0,
525+ 704, 832, 0, 480, 489, 492, 520, 0,
526526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
527527 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
528528 768, 864, 0, 480, 483, 486, 525, 0,
529529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
530− { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
530+ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
531531 752, 800, 0, 480, 490, 492, 525, 0,
532532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
533533 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
@@ -539,7 +539,7 @@ static const struct drm_display_mode edid_est_modes[] = { · 5 unmodified lines
539539 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
540540 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
541541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
542− { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
542+ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
543543 1136, 1312, 0, 768, 769, 772, 800, 0,
544544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
545545 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
@@ -2241,7 +2241,7 @@ drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) · 1695 unmodified lines
22412241 {
22422242 int i, j, m, modes = 0;
22432243 struct drm_display_mode *mode;
2244− u8 *est = ((u8 *)timing) + 5;
2244+ u8 *est = ((u8 *)timing) + 6;
22452245
22462246 for (i = 0; i < 6; i++) {
22472247 for (j = 7; j >= 0; j--) {
drivers/gpu/drm/exynos/Kconfig+1−1
@@ -94,7 +94,7 @@ comment "Sub-drivers" · 93 unmodified lines
9494
9595 config DRM_EXYNOS_G2D
9696 bool "G2D"
97− depends on !VIDEO_SAMSUNG_S5P_G2D
97+ depends on VIDEO_SAMSUNG_S5P_G2D=n
9898 select FRAME_VECTOR
9999 help
100100 Choose this option if you want to use Exynos G2D for DRM.
drivers/gpu/drm/exynos/Makefile+3−3
@@ -2,10 +2,10 @@ · 1 unmodified line
22 # Makefile for the drm device driver. This driver provides support for the
33 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
44
5−exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fbdev.o \
6− exynos_drm_fb.o exynos_drm_gem.o exynos_drm_core.o \
7− exynos_drm_plane.o
5+exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fb.o \
6+ exynos_drm_gem.o exynos_drm_core.o exynos_drm_plane.o
87
8+exynosdrm-$(CONFIG_DRM_FBDEV_EMULATION) += exynos_drm_fbdev.o
99 exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
1010 exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
1111 exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o
drivers/gpu/drm/exynos/exynos_drm_core.c+1−1
@@ -101,7 +101,7 @@ int exynos_drm_subdrv_open(struct drm_device *dev, struct drm_file *file) · 100 unmodified lines
101101 return 0;
102102
103103 err:
104− list_for_each_entry_reverse(subdrv, &subdrv->list, list) {
104+ list_for_each_entry_continue_reverse(subdrv, &exynos_drm_subdrv_list, list) {
105105 if (subdrv->close)
106106 subdrv->close(dev, subdrv->dev, file);
107107 }
drivers/gpu/drm/exynos/exynos_drm_fb.c+0−11
@@ -199,17 +199,6 @@ dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index) · 198 unmodified lines
199199 return exynos_fb->dma_addr[index];
200200 }
201201
202−static void exynos_drm_output_poll_changed(struct drm_device *dev)
203−{
204− struct exynos_drm_private *private = dev->dev_private;
205− struct drm_fb_helper *fb_helper = private->fb_helper;
206−
207− if (fb_helper)
208− drm_fb_helper_hotplug_event(fb_helper);
209− else
210− exynos_drm_fbdev_init(dev);
211−}
212−
213202 static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
214203 .fb_create = exynos_user_fb_create,
215204 .output_poll_changed = exynos_drm_output_poll_changed,
drivers/gpu/drm/exynos/exynos_drm_fbdev.c+11−0
@@ -317,3 +317,14 @@ void exynos_drm_fbdev_restore_mode(struct drm_device *dev) · 316 unmodified lines
317317
318318 drm_fb_helper_restore_fbdev_mode_unlocked(private->fb_helper);
319319 }
320+
321+void exynos_drm_output_poll_changed(struct drm_device *dev)
322+{
323+ struct exynos_drm_private *private = dev->dev_private;
324+ struct drm_fb_helper *fb_helper = private->fb_helper;
325+
326+ if (fb_helper)
327+ drm_fb_helper_hotplug_event(fb_helper);
328+ else
329+ exynos_drm_fbdev_init(dev);
330+}
drivers/gpu/drm/exynos/exynos_drm_fbdev.h+22−1
@@ -15,9 +15,30 @@ · 14 unmodified lines
1515 #ifndef _EXYNOS_DRM_FBDEV_H_
1616 #define _EXYNOS_DRM_FBDEV_H_
1717
18+#ifdef CONFIG_DRM_FBDEV_EMULATION
19+
1820 int exynos_drm_fbdev_init(struct drm_device *dev);
19−int exynos_drm_fbdev_reinit(struct drm_device *dev);
2021 void exynos_drm_fbdev_fini(struct drm_device *dev);
2122 void exynos_drm_fbdev_restore_mode(struct drm_device *dev);
23+void exynos_drm_output_poll_changed(struct drm_device *dev);
24+
25+#else
26+
27+static inline int exynos_drm_fbdev_init(struct drm_device *dev)
28+{
29+ return 0;
30+}
31+
32+static inline void exynos_drm_fbdev_fini(struct drm_device *dev)
33+{
34+}
35+
36+static inline void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
37+{
38+}
39+
40+#define exynos_drm_output_poll_changed (NULL)
41+
42+#endif
2243
2344 #endif
drivers/gpu/drm/exynos/exynos_drm_fimd.c+1−1
@@ -888,7 +888,7 @@ static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) · 887 unmodified lines
888888 * clock. On these SoCs the bootloader may enable it but any
889889 * power domain off/on will reset it to disable state.
890890 */
891− if (ctx->driver_data != &exynos5_fimd_driver_data ||
891+ if (ctx->driver_data != &exynos5_fimd_driver_data &&
892892 ctx->driver_data != &exynos5420_fimd_driver_data)
893893 return;
894894
drivers/gpu/drm/exynos/exynos_drm_mic.c+2−1
@@ -129,7 +129,7 @@ static void mic_set_path(struct exynos_mic *mic, bool enable) · 128 unmodified lines
129129 } else
130130 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
131131
132− regmap_write(mic->sysreg, DSD_CFG_MUX, val);
132+ ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
133133 if (ret)
134134 DRM_ERROR("mic: Failed to read system register\n");
135135 }
@@ -457,6 +457,7 @@ static int exynos_mic_probe(struct platform_device *pdev) · 321 unmodified lines
457457 "samsung,disp-syscon");
458458 if (IS_ERR(mic->sysreg)) {
459459 DRM_ERROR("mic: Failed to get system register.\n");
460+ ret = PTR_ERR(mic->sysreg);
460461 goto err;
461462 }
462463
drivers/gpu/drm/exynos/exynos_drm_plane.c+7−5
@@ -11,9 +11,10 @@ · 10 unmodified lines
1111
1212 #include <drm/drmP.h>
1313
14−#include <drm/exynos_drm.h>
15−#include <drm/drm_plane_helper.h>
14+#include <drm/drm_atomic.h>
1615 #include <drm/drm_atomic_helper.h>
16+#include <drm/drm_plane_helper.h>
17+#include <drm/exynos_drm.h>
1718 #include "exynos_drm_drv.h"
1819 #include "exynos_drm_crtc.h"
1920 #include "exynos_drm_fb.h"
@@ -57,11 +58,12 @@ static int exynos_plane_get_size(int start, unsigned length, unsigned last) · 37 unmodified lines
5758 }
5859
5960 static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state)
60−
6161 {
6262 struct drm_plane_state *state = &exynos_state->base;
63− struct drm_crtc *crtc = exynos_state->base.crtc;
64− struct drm_display_mode *mode = &crtc->state->adjusted_mode;
63+ struct drm_crtc *crtc = state->crtc;
64+ struct drm_crtc_state *crtc_state =
65+ drm_atomic_get_existing_crtc_state(state->state, crtc);
66+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
6567 int crtc_x, crtc_y;
6668 unsigned int crtc_w, crtc_h;
6769 unsigned int src_x, src_y;
drivers/gpu/drm/i915/i915_drv.c+2−2
@@ -758,10 +758,10 @@ static int i915_drm_resume(struct drm_device *dev) · 757 unmodified lines
758758 dev_priv->display.hpd_irq_setup(dev);
759759 spin_unlock_irq(&dev_priv->irq_lock);
760760
761− intel_display_resume(dev);
762−
763761 intel_dp_mst_resume(dev);
764762
763+ intel_display_resume(dev);
764+
765765 /*
766766 * ... but also need to make sure that hotplug processing
767767 * doesn't cause havoc. Like in the driver load code we don't
drivers/gpu/drm/i915/i915_irq.c+2−2
@@ -1829,7 +1829,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) · 1828 unmodified lines
18291829 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
18301830 disable_rpm_wakeref_asserts(dev_priv);
18311831
1832− for (;;) {
1832+ do {
18331833 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
18341834 iir = I915_READ(VLV_IIR);
18351835
@@ -1857,7 +1857,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) · 21 unmodified lines
18571857
18581858 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
18591859 POSTING_READ(GEN8_MASTER_IRQ);
1860− }
1860+ } while (0);
18611861
18621862 enable_rpm_wakeref_asserts(dev_priv);
18631863
drivers/gpu/drm/i915/intel_dp_mst.c+2−4
@@ -506,6 +506,8 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, · 505 unmodified lines
506506 struct intel_connector *intel_connector = to_intel_connector(connector);
507507 struct drm_device *dev = connector->dev;
508508
509+ intel_connector->unregister(intel_connector);
510+
509511 /* need to nuke the connector */
510512 drm_modeset_lock_all(dev);
511513 if (connector->state->crtc) {
@@ -519,11 +521,7 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, · 7 unmodified lines
519521
520522 WARN(ret, "Disabling mst crtc failed with %i\n", ret);
521523 }
522− drm_modeset_unlock_all(dev);
523524
524− intel_connector->unregister(intel_connector);
525−
526− drm_modeset_lock_all(dev);
527525 intel_connector_remove_from_fbdev(intel_connector);
528526 drm_connector_cleanup(connector);
529527 drm_modeset_unlock_all(dev);
drivers/gpu/drm/i915/intel_lvds.c+1−4
@@ -478,11 +478,8 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val, · 477 unmodified lines
478478 * and as part of the cleanup in the hw state restore we also redisable
479479 * the vga plane.
480480 */
481− if (!HAS_PCH_SPLIT(dev)) {
482− drm_modeset_lock_all(dev);
481+ if (!HAS_PCH_SPLIT(dev))
483482 intel_display_resume(dev);
484− drm_modeset_unlock_all(dev);
485− }
486483
487484 dev_priv->modeset_restore = MODESET_DONE;
488485
drivers/gpu/drm/qxl/qxl_display.c+9−4
@@ -375,10 +375,15 @@ static int qxl_crtc_cursor_set2(struct drm_crtc *crtc, · 374 unmodified lines
375375
376376 qxl_bo_kunmap(user_bo);
377377
378+ qcrtc->cur_x += qcrtc->hot_spot_x - hot_x;
379+ qcrtc->cur_y += qcrtc->hot_spot_y - hot_y;
380+ qcrtc->hot_spot_x = hot_x;
381+ qcrtc->hot_spot_y = hot_y;
382+
378383 cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release);
379384 cmd->type = QXL_CURSOR_SET;
380− cmd->u.set.position.x = qcrtc->cur_x;
381− cmd->u.set.position.y = qcrtc->cur_y;
385+ cmd->u.set.position.x = qcrtc->cur_x + qcrtc->hot_spot_x;
386+ cmd->u.set.position.y = qcrtc->cur_y + qcrtc->hot_spot_y;
382387
383388 cmd->u.set.shape = qxl_bo_physical_address(qdev, cursor_bo, 0);
384389
@@ -441,8 +446,8 @@ static int qxl_crtc_cursor_move(struct drm_crtc *crtc, · 56 unmodified lines
441446
442447 cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release);
443448 cmd->type = QXL_CURSOR_MOVE;
444− cmd->u.position.x = qcrtc->cur_x;
445− cmd->u.position.y = qcrtc->cur_y;
449+ cmd->u.position.x = qcrtc->cur_x + qcrtc->hot_spot_x;
450+ cmd->u.position.y = qcrtc->cur_y + qcrtc->hot_spot_y;
446451 qxl_release_unmap(qdev, release, &cmd->release_info);
447452
448453 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
drivers/gpu/drm/qxl/qxl_drv.h+2−0
@@ -135,6 +135,8 @@ struct qxl_crtc { · 134 unmodified lines
135135 int index;
136136 int cur_x;
137137 int cur_y;
138+ int hot_spot_x;
139+ int hot_spot_y;
138140 };
139141
140142 struct qxl_output {
drivers/gpu/drm/radeon/ni_reg.h+2−0
@@ -109,6 +109,8 @@ · 108 unmodified lines
109109 #define NI_DP_MSE_SAT2 0x7398
110110
111111 #define NI_DP_MSE_SAT_UPDATE 0x739c
112+# define NI_DP_MSE_SAT_UPDATE_MASK 0x3
113+# define NI_DP_MSE_16_MTP_KEEPOUT 0x100
112114
113115 #define NI_DIG_BE_CNTL 0x7140
114116 # define NI_DIG_FE_SOURCE_SELECT(x) (((x) & 0x7f) << 8)
drivers/gpu/drm/radeon/radeon_dp_mst.c+20−11
@@ -89,8 +89,16 @@ static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary, · 88 unmodified lines
8989 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
9090
9191 do {
92+ unsigned value1, value2;
93+ udelay(10);
9294 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
93− } while ((temp & 0x1) && retries++ < 10000);
95+
96+ value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
97+ value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
98+
99+ if (!value1 && !value2)
100+ break;
101+ } while (retries++ < 50);
94102
95103 if (retries == 10000)
96104 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
@@ -150,7 +158,7 @@ static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn · 53 unmodified lines
150158 return 0;
151159 }
152160
153−static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
161+static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
154162 {
155163 struct drm_device *dev = mst->base.dev;
156164 struct radeon_device *rdev = dev->dev_private;
@@ -158,6 +166,8 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui · 1 unmodified line
158166 uint32_t val, temp;
159167 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
160168 int retries = 0;
169+ uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
170+ uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
161171
162172 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
163173
@@ -165,6 +175,7 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui · 1 unmodified line
165175
166176 do {
167177 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
178+ udelay(10);
168179 } while ((temp & 0x1) && (retries++ < 10000));
169180
170181 if (retries >= 10000)
@@ -246,14 +257,8 @@ radeon_dp_mst_connector_destroy(struct drm_connector *connector) · 75 unmodified lines
246257 kfree(radeon_connector);
247258 }
248259
249−static int radeon_connector_dpms(struct drm_connector *connector, int mode)
250−{
251− DRM_DEBUG_KMS("\n");
252− return 0;
253−}
254−
255260 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
256− .dpms = radeon_connector_dpms,
261+ .dpms = drm_helper_connector_dpms,
257262 .detect = radeon_dp_mst_detect,
258263 .fill_modes = drm_helper_probe_single_connector_modes,
259264 .destroy = radeon_dp_mst_connector_destroy,
@@ -394,7 +399,7 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) · 134 unmodified lines
394399 struct drm_crtc *crtc;
395400 struct radeon_crtc *radeon_crtc;
396401 int ret, slots;
397−
402+ s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
398403 if (!ASIC_IS_DCE5(rdev)) {
399404 DRM_ERROR("got mst dpms on non-DCE5\n");
400405 return;
@@ -456,7 +461,11 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) · 55 unmodified lines
456461
457462 mst_enc->enc_active = true;
458463 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
459− radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
464+
465+ fixed_pbn = drm_int2fixp(mst_enc->pbn);
466+ fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
467+ avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
468+ radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
460469
461470 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
462471 mst_enc->fe);