Per PCIe r3.1, sec 6.2.10 and sec 7.13.4, on Root Ports that support "RP Extensions for DPC", When the DPC Trigger Status bit is Set and the DPC RP Busy bit is Set, software must leave the Root Port in DPC until the DPC RP Busy bit reads 0b. Wait up to 1 second for the Root Port to become non-busy. [bhelgaas: changelog, spec references] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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| @@ -973,6 +973,7 @@ · 972 unmodified lines | |||
| 973 | #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ | 973 | #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ |
| 974 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */ | 974 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */ |
| 975 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */ | 975 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */ |
| 976 | #define PCI_EXP_DPC_RP_BUSY 0x10 /* Root Port Busy */ | ||
| 976 | 977 | ||
| 977 | #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ | 978 | #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ |
| 978 | 979 | ||