Merge tag 'i2c-for-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c updates from Wolfram Sang: "Core: - list-based mechanisms for handling auto-detected and userspace created clients are replaced with a flag-based approach. The resulting code is much simpler as well as the locking. - i2c clients now get a default debugfs dir managed by the I2C core. Drivers don't have to maintain their own directory anymore. Driver updates: - xiic: atomic_transfer support - imx-lpi2c: DMA and target mode support - riic cleanups - npcm: better timeout handling and more precise frequency setups - davinci: remove unused platform_data - at24: add new compatibles for variants from Giantec and Puya Semiconductor (together with a new vendor prefix)" * tag 'i2c-for-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (52 commits) i2c: add kdoc for the new debugfs entry of clients i2c: designware: Actually make use of the I2C_DW_COMMON and I2C_DW symbol namespaces i2c: add core-managed per-client directory in debugfs i2c: Force ELAN06FA touchpad I2C bus freq to 100KHz i2c: riic: Add `riic_bus_barrier()` to check bus availability i2c: riic: Use predefined macro and simplify clock tick calculation i2c: riic: Mark riic_irqs array as const i2c: riic: Make use of devres helper to request deasserted reset line i2c: riic: Use GENMASK() macro for bitmask definitions i2c: riic: Use BIT macro consistently i2c: riic: Use local `dev` pointer in `dev_err_probe()` i2c: riic: Use dev_err_probe in probe and riic_init_hw functions i2c: riic: Introduce a separate variable for IRQ i2c: amd756: Remove superfluous TODO Revert "i2c: amd756: Fix endianness handling for word data" i2c: i801: Add lis3lv02d for Dell Precision M6800 i2c: i801: Remove unnecessary PCI function call i2c: core: Allocate temp client on the stack in i2c_detect i2c: slave-eeprom: Constify 'struct bin_attribute' i2c: imx-lpi2c: make controller available until the system enters suspend_noirq() and from resume_noirq(). ...

Linus Torvalds committed 1 year ago

Commit abdebb22 parents d12f68b 27c3f0e27 files · +1714 −507Browse files

Unified · Split

27 files

Documentation/devicetree/bindings/eeprom/at24.yaml +5 −0
Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +1 −0
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +2 −0
Documentation/devicetree/bindings/i2c/renesas,riic.yaml +4 −1
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 −0
drivers/i2c/busses/Kconfig +2 −2
drivers/i2c/busses/i2c-amd756.c +2 −2
drivers/i2c/busses/i2c-davinci.c +33 −79
drivers/i2c/busses/i2c-designware-common.c +3 −2
drivers/i2c/busses/i2c-designware-master.c +3 −2
drivers/i2c/busses/i2c-designware-slave.c +3 −2
drivers/i2c/busses/i2c-exynos5.c +31 −4
drivers/i2c/busses/i2c-i801.c +6 −2
drivers/i2c/busses/i2c-imx-lpi2c.c +799 −12
drivers/i2c/busses/i2c-imx.c +82 −17
drivers/i2c/busses/i2c-isch.c +3 −3
drivers/i2c/busses/i2c-keba.c +2 −6
drivers/i2c/busses/i2c-npcm7xx.c +326 −101
drivers/i2c/busses/i2c-qcom-geni.c +27 −29
drivers/i2c/busses/i2c-riic.c +72 −62
drivers/i2c/busses/i2c-xiic.c +227 −54
drivers/i2c/i2c-core-acpi.c +22 −0
drivers/i2c/i2c-core-base.c +47 −83
drivers/i2c/i2c-slave-eeprom.c +4 −4
include/linux/i2c.h +5 −8
include/linux/platform_data/i2c-davinci.h +0 −26
sound/ppc/keywest.c +1 −6

Documentation/devicetree/bindings/eeprom/at24.yaml+5−0

@@ -134,9 +134,14 @@ properties: · 133 unmodified lines
134	134	- const: atmel,24c64
135	135	- items:
136	136	- enum:
	137	+ - giantec,gt24p128f
137	138	- renesas,r1ex24128
138	139	- samsung,s524ad0xd1
139	140	- const: atmel,24c128
	141	+ - items:
	142	+ - enum:
	143	+ - puya,p24c256c
	144	+ - const: atmel,24c256
140	145	- items:
141	146	- const: microchip,24aa025e48
142	147	- items:

Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml+1−0

@@ -25,6 +25,7 @@ properties: · 24 unmodified lines
25	25	- samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
26	26	- samsung,exynos5260-hsi2c # Exynos5260
27	27	- samsung,exynos7-hsi2c # Exynos7
	28	+ - samsung,exynos8895-hsi2c
28	29	- samsung,exynosautov9-hsi2c
29	30	- items:
30	31	- enum:

Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml+2−0

@@ -34,6 +34,7 @@ properties: · 33 unmodified lines
34	34	- qcom,sm8450-cci
35	35	- qcom,sm8550-cci
36	36	- qcom,sm8650-cci
	37	+ - qcom,x1e80100-cci
37	38	- const: qcom,msm8996-cci # CCI v2
38	39
39	40	"#address-cells":
@@ -224,6 +225,7 @@ allOf: · 184 unmodified lines
224	225	enum:
225	226	- qcom,sm8550-cci
226	227	- qcom,sm8650-cci
	228	+ - qcom,x1e80100-cci
227	229	then:
228	230	properties:
229	231	clocks:

Documentation/devicetree/bindings/i2c/renesas,riic.yaml+4−1

@@ -26,7 +26,9 @@ properties: · 25 unmodified lines
26	26	- const: renesas,riic-rz # RZ/A or RZ/G2L
27	27
28	28	- items:
29		− - const: renesas,riic-r9a08g045 # RZ/G3S
	29	+ - enum:
	30	+ - renesas,riic-r9a08g045 # RZ/G3S
	31	+ - renesas,riic-r9a09g047 # RZ/G3E
30	32	- const: renesas,riic-r9a09g057 # RZ/V2H(P)
31	33
32	34	- const: renesas,riic-r9a09g057 # RZ/V2H(P)
@@ -89,6 +91,7 @@ if: · 56 unmodified lines
89	91	- renesas,riic-r9a07g043
90	92	- renesas,riic-r9a07g044
91	93	- renesas,riic-r9a07g054
	94	+ - renesas,riic-r9a09g057
92	95	then:
93	96	required:
94	97	- resets

Documentation/devicetree/bindings/vendor-prefixes.yaml+2−0

@@ -1204,6 +1204,8 @@ patternProperties: · 1203 unmodified lines
1204	1204	description: PulsedLight, Inc
1205	1205	"^purism,.*":
1206	1206	description: Purism, SPC
	1207	+ "^puya,.*":
	1208	+ description: Puya Semiconductor (Shanghai) Co., Ltd.
1207	1209	"^qca,.*":
1208	1210	description: Qualcomm Atheros, Inc.
1209	1211	"^qcom,.*":

drivers/i2c/busses/Kconfig+2−2

@@ -503,7 +503,7 @@ config I2C_BRCMSTB · 502 unmodified lines
503	503	tristate "BRCM Settop/DSL I2C controller"
504	504	depends on ARCH_BCM2835 \|\| ARCH_BCMBCA \|\| ARCH_BRCMSTB \|\| \
505	505	BMIPS_GENERIC \|\| COMPILE_TEST
506		− default y
	506	+ default ARCH_BCM2835 \|\| ARCH_BCMBCA \|\| ARCH_BRCMSTB \|\| BMIPS_GENERIC
507	507	help
508	508	If you say yes to this option, support will be included for the
509	509	I2C interface on the Broadcom Settop/DSL SoCs.
@@ -910,7 +910,7 @@ config I2C_MXS · 400 unmodified lines
910	910
911	911	config I2C_NOMADIK
912	912	tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
913		− depends on ARM_AMBA
	913	+ depends on ARM_AMBA \|\| COMPILE_TEST
914	914	help
915	915	If you say yes to this option, support will be included for the
916	916	I2C interface from ST-Ericsson's Nomadik and Ux500 architectures,

drivers/i2c/busses/i2c-amd756.c+2−2

@@ -211,7 +211,7 @@ static s32 amd756_access(struct i2c_adapter * adap, u16 addr, · 210 unmodified lines
211	211	SMB_HOST_ADDRESS);
212	212	outb_p(command, SMB_HOST_COMMAND);
213	213	if (read_write == I2C_SMBUS_WRITE)
214		− outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */
	214	+ outw_p(data->word, SMB_HOST_DATA);
215	215	size = AMD756_WORD_DATA;
216	216	break;
217	217	case I2C_SMBUS_BLOCK_DATA:
@@ -256,7 +256,7 @@ static s32 amd756_access(struct i2c_adapter * adap, u16 addr, · 38 unmodified lines
256	256	data->byte = inw_p(SMB_HOST_DATA);
257	257	break;
258	258	case AMD756_WORD_DATA:
259		− data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */
	259	+ data->word = inw_p(SMB_HOST_DATA);
260	260	break;
261	261	case AMD756_BLOCK_DATA:
262	262	data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;

drivers/i2c/busses/i2c-davinci.c+33−79

@@ -11,23 +11,23 @@ · 10 unmodified lines
11	11	*
12	12	* ----------------------------------------------------------------------------
13	13	*/
14		−#include <linux/kernel.h>
15		−#include <linux/module.h>
16		−#include <linux/delay.h>
17		−#include <linux/i2c.h>
	14	+
18	15	#include <linux/clk.h>
19		−#include <linux/errno.h>
20		−#include <linux/sched.h>
	16	+#include <linux/cpufreq.h>
	17	+#include <linux/delay.h>
21	18	#include <linux/err.h>
	19	+#include <linux/errno.h>
	20	+#include <linux/gpio/consumer.h>
	21	+#include <linux/i2c.h>
22	22	#include <linux/interrupt.h>
23		−#include <linux/platform_device.h>
24	23	#include <linux/io.h>
25		−#include <linux/slab.h>
26		−#include <linux/cpufreq.h>
27		−#include <linux/gpio/consumer.h>
28		−#include <linux/of.h>
29		−#include <linux/platform_data/i2c-davinci.h>
	24	+#include <linux/kernel.h>
	25	+#include <linux/module.h>
	26	+#include <linux/platform_device.h>
30	27	#include <linux/pm_runtime.h>
	28	+#include <linux/property.h>
	29	+#include <linux/sched.h>
	30	+#include <linux/slab.h>
31	31
32	32	/* ----- global defines ----------------------------------------------- */
33	33
@@ -117,6 +117,8 @@ · 83 unmodified lines
117	117	/* timeout for pm runtime autosuspend */
118	118	#define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */
119	119
	120	+#define DAVINCI_I2C_DEFAULT_BUS_FREQ 100
	121	+
120	122	struct davinci_i2c_dev {
121	123	struct device *dev;
122	124	void __iomem *base;
@@ -132,13 +134,10 @@ struct davinci_i2c_dev { · 9 unmodified lines
132	134	#ifdef CONFIG_CPU_FREQ
133	135	struct notifier_block freq_transition;
134	136	#endif
135		− struct davinci_i2c_platform_data *pdata;
136		−};
137		−
138		−/* default platform data to use if not supplied in the platform_device */
139		−static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
140		− .bus_freq = 100,
141		− .bus_delay = 0,
	137	+ /* standard bus frequency (kHz) */
	138	+ unsigned int bus_freq;
	139	+ /* Chip has a ICPFUNC register */
	140	+ bool has_pfunc;
142	141	};
143	142
144	143	static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
@@ -168,14 +167,12 @@ static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, · 23 unmodified lines
168	167
169	168	static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
170	169	{
171		− struct davinci_i2c_platform_data *pdata = dev->pdata;
172	170	u16 psc;
173	171	u32 clk;
174	172	u32 d;
175	173	u32 clkh;
176	174	u32 clkl;
177	175	u32 input_clock = clk_get_rate(dev->clk);
178		− struct device_node *of_node = dev->dev->of_node;
179	176
180	177	/* NOTE: I2C Clock divider programming info
181	178	* As per I2C specs the following formulas provide prescaler
@@ -209,19 +206,19 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) · 27 unmodified lines
209	206	psc++; /* better to run under spec than over */
210	207	d = (psc >= 2) ? 5 : 7 - psc;
211	208
212		− if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
	209	+ if (device_is_compatible(dev->dev, "ti,keystone-i2c"))
213	210	d = 6;
214	211
215		− clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
	212	+ clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000));
216	213	/* Avoid driving the bus too fast because of rounding errors above */
217		− if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
	214	+ if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000)
218	215	clk++;
219	216	/*
220	217	* According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
221	218	* least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
222	219	* to LOW ratio as 1 to 2 is more safe.
223	220	*/
224		− if (pdata->bus_freq > 100)
	221	+ if (dev->bus_freq > 100)
225	222	clkl = (clk << 1) / 3;
226	223	else
227	224	clkl = (clk >> 1);
@@ -255,8 +252,6 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) · 27 unmodified lines
255	252	*/
256	253	static int i2c_davinci_init(struct davinci_i2c_dev *dev)
257	254	{
258		− struct davinci_i2c_platform_data *pdata = dev->pdata;
259		−
260	255	/* put I2C into reset */
261	256	davinci_i2c_reset_ctrl(dev, 0);
262	257
@@ -274,8 +269,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) · 11 unmodified lines
274	269	davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
275	270	dev_dbg(dev->dev, "CLKH = %d\n",
276	271	davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
277		− dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
278		− pdata->bus_freq, pdata->bus_delay);
	272	+ dev_dbg(dev->dev, "bus_freq = %dkHz\n", dev->bus_freq);
279	273
280	274
281	275	/* Take the I2C module out of reset: */
@@ -309,12 +303,6 @@ static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap) · 27 unmodified lines
309	303	i2c_davinci_init(dev);
310	304	}
311	305
312		−static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
313		− .recover_bus = i2c_generic_scl_recovery,
314		− .prepare_recovery = davinci_i2c_prepare_recovery,
315		− .unprepare_recovery = davinci_i2c_unprepare_recovery,
316		−};
317		−
318	306	static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
319	307	{
320	308	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
@@ -414,7 +402,6 @@ static int · 93 unmodified lines
414	402	i2c_davinci_xfer_msg(struct i2c_adapter adap, struct i2c_msg msg, int stop)
415	403	{
416	404	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
417		− struct davinci_i2c_platform_data *pdata = dev->pdata;
418	405	u32 flag;
419	406	u16 w;
420	407	unsigned long time_left;
@@ -424,10 +411,6 @@ i2c_davinci_xfer_msg(struct i2c_adapter adap, struct i2c_msg msg, int stop) · 3 unmodified lines
424	411	return -EADDRNOTAVAIL;
425	412	}
426	413
427		− /* Introduce a delay, required for some boards (e.g Davinci EVM) */
428		− if (pdata->bus_delay)
429		− udelay(pdata->bus_delay);
430		−
431	414	/* set the target address */
432	415	davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
433	416
@@ -758,8 +741,8 @@ static int davinci_i2c_probe(struct platform_device *pdev) · 324 unmodified lines
758	741	{
759	742	struct davinci_i2c_dev *dev;
760	743	struct i2c_adapter *adap;
761		− struct i2c_bus_recovery_info *rinfo;
762	744	int r, irq;
	745	+ u32 prop;
763	746
764	747	irq = platform_get_irq(pdev, 0);
765	748	if (irq < 0)
@@ -773,29 +756,15 @@ static int davinci_i2c_probe(struct platform_device *pdev) · 7 unmodified lines
773	756
774	757	dev->dev = &pdev->dev;
775	758	dev->irq = irq;
776		− dev->pdata = dev_get_platdata(&pdev->dev);
777	759	platform_set_drvdata(pdev, dev);
778	760
779		− if (!dev->pdata && pdev->dev.of_node) {
780		− u32 prop;
781		−
782		− dev->pdata = devm_kzalloc(&pdev->dev,
783		− sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
784		− if (!dev->pdata)
785		− return -ENOMEM;
786		−
787		− memcpy(dev->pdata, &davinci_i2c_platform_data_default,
788		− sizeof(struct davinci_i2c_platform_data));
789		− if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
790		− &prop))
791		− dev->pdata->bus_freq = prop / 1000;
792		−
793		− dev->pdata->has_pfunc =
794		− of_property_read_bool(pdev->dev.of_node,
795		− "ti,has-pfunc");
796		− } else if (!dev->pdata) {
797		− dev->pdata = &davinci_i2c_platform_data_default;
798		− }
	761	+ r = device_property_read_u32(&pdev->dev, "clock-frequency", &prop);
	762	+ if (r)
	763	+ prop = DAVINCI_I2C_DEFAULT_BUS_FREQ;
	764	+
	765	+ dev->bus_freq = prop / 1000;
	766	+
	767	+ dev->has_pfunc = device_property_present(&pdev->dev, "ti,has-pfunc");
799	768
800	769	dev->clk = devm_clk_get(&pdev->dev, NULL);
801	770	if (IS_ERR(dev->clk))
@@ -841,25 +810,10 @@ static int davinci_i2c_probe(struct platform_device *pdev) · 39 unmodified lines
841	810	adap->algo = &i2c_davinci_algo;
842	811	adap->dev.parent = &pdev->dev;
843	812	adap->timeout = DAVINCI_I2C_TIMEOUT;
844		− adap->dev.of_node = pdev->dev.of_node;
	813	+ adap->dev.of_node = dev_of_node(&pdev->dev);
845	814
846		− if (dev->pdata->has_pfunc)
	815	+ if (dev->has_pfunc)
847	816	adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
848		− else if (dev->pdata->gpio_recovery) {
849		− rinfo = &davinci_i2c_gpio_recovery_info;
850		− adap->bus_recovery_info = rinfo;
851		− rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl",
852		− GPIOD_OUT_HIGH_OPEN_DRAIN);
853		− if (IS_ERR(rinfo->scl_gpiod)) {
854		− r = PTR_ERR(rinfo->scl_gpiod);
855		− goto err_unuse_clocks;
856		− }
857		− rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
858		− if (IS_ERR(rinfo->sda_gpiod)) {
859		− r = PTR_ERR(rinfo->sda_gpiod);
860		− goto err_unuse_clocks;
861		− }
862		− }
863	817
864	818	adap->nr = pdev->id;
865	819	r = i2c_add_numbered_adapter(adap);

drivers/i2c/busses/i2c-designware-common.c+3−2

@@ -8,6 +8,9 @@ · 7 unmodified lines
8	8	* Copyright (C) 2007 MontaVista Software Inc.
9	9	* Copyright (C) 2009 Provigent Ltd.
10	10	*/
	11	+
	12	+#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON"
	13	+
11	14	#include <linux/acpi.h>
12	15	#include <linux/clk.h>
13	16	#include <linux/delay.h>
@@ -29,8 +32,6 @@ · 15 unmodified lines
29	32	#include <linux/types.h>
30	33	#include <linux/units.h>
31	34
32		−#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON"
33		−
34	35	#include "i2c-designware-core.h"
35	36
36	37	static const char *const abort_sources[] = {

drivers/i2c/busses/i2c-designware-master.c+3−2

@@ -8,6 +8,9 @@ · 7 unmodified lines
8	8	* Copyright (C) 2007 MontaVista Software Inc.
9	9	* Copyright (C) 2009 Provigent Ltd.
10	10	*/
	11	+
	12	+#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW"
	13	+
11	14	#include <linux/delay.h>
12	15	#include <linux/err.h>
13	16	#include <linux/errno.h>
@@ -22,8 +25,6 @@ · 8 unmodified lines
22	25	#include <linux/regmap.h>
23	26	#include <linux/reset.h>
24	27
25		−#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW"
26		−
27	28	#include "i2c-designware-core.h"
28	29
29	30	#define AMD_TIMEOUT_MIN_US 25

drivers/i2c/busses/i2c-designware-slave.c+3−2

@@ -6,6 +6,9 @@ · 5 unmodified lines
6	6	*
7	7	* Copyright (C) 2016 Synopsys Inc.
8	8	*/
	9	+
	10	+#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW"
	11	+
9	12	#include <linux/delay.h>
10	13	#include <linux/err.h>
11	14	#include <linux/errno.h>
@@ -16,8 +19,6 @@ · 4 unmodified lines
16	19	#include <linux/pm_runtime.h>
17	20	#include <linux/regmap.h>
18	21
19		−#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW"
20		−
21	22	#include "i2c-designware-core.h"
22	23
23	24	static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)

drivers/i2c/busses/i2c-exynos5.c+31−4

@@ -168,6 +168,7 @@ enum i2c_type_exynos { · 167 unmodified lines
168	168	I2C_TYPE_EXYNOS5,
169	169	I2C_TYPE_EXYNOS7,
170	170	I2C_TYPE_EXYNOSAUTOV9,
	171	+ I2C_TYPE_EXYNOS8895,
171	172	};
172	173
173	174	struct exynos5_i2c {
@@ -240,6 +241,11 @@ static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = { · 66 unmodified lines
240	241	.hw = I2C_TYPE_EXYNOSAUTOV9,
241	242	};
242	243
	244	+static const struct exynos_hsi2c_variant exynos8895_hsi2c_data = {
	245	+ .fifo_depth = 64,
	246	+ .hw = I2C_TYPE_EXYNOS8895,
	247	+};
	248	+
243	249	static const struct of_device_id exynos5_i2c_match[] = {
244	250	{
245	251	.compatible = "samsung,exynos5-hsi2c",
@@ -256,6 +262,9 @@ static const struct of_device_id exynos5_i2c_match[] = { · 10 unmodified lines
256	262	}, {
257	263	.compatible = "samsung,exynosautov9-hsi2c",
258	264	.data = &exynosautov9_hsi2c_data
	265	+ }, {
	266	+ .compatible = "samsung,exynos8895-hsi2c",
	267	+ .data = &exynos8895_hsi2c_data
259	268	}, {},
260	269	};
261	270	MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
@@ -331,6 +340,14 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) · 69 unmodified lines
331	340	* clk_cycle := TSCLK_L + TSCLK_H
332	341	* temp := (CLK_DIV + 1) * (clk_cycle + 2)
333	342	*
	343	+ * In case of HSI2C controllers in Exynos8895
	344	+ * FPCLK / FI2C =
	345	+ * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) +
	346	+ * 2 * ((FLT_CYCLE + 3) - (FLT_CYCLE + 3) % (CLK_DIV + 1))
	347	+ *
	348	+ * clk_cycle := TSCLK_L + TSCLK_H
	349	+ * temp := (FPCLK / FI2C) - (FLT_CYCLE + 3) * 2
	350	+ *
334	351	* Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
335	352	*
336	353	* To split SCL clock into low, high periods appropriately, one
@@ -352,11 +369,19 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) · 15 unmodified lines
352	369	*
353	370	*/
354	371	t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
355		− temp = clkin / op_clk - 8 - t_ftl_cycle;
356		− if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
357		− temp -= t_ftl_cycle;
	372	+ if (i2c->variant->hw == I2C_TYPE_EXYNOS8895)
	373	+ temp = clkin / op_clk - (t_ftl_cycle + 3) * 2;
	374	+ else if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
	375	+ temp = clkin / op_clk - 8 - t_ftl_cycle;
	376	+ else
	377	+ temp = clkin / op_clk - 8 - (t_ftl_cycle * 2);
358	378	div = temp / 512;
359		− clk_cycle = temp / (div + 1) - 2;
	379	+
	380	+ if (i2c->variant->hw == I2C_TYPE_EXYNOS8895)
	381	+ clk_cycle = (temp + ((t_ftl_cycle + 3) % (div + 1)) * 2) /
	382	+ (div + 1) - 2;
	383	+ else
	384	+ clk_cycle = temp / (div + 1) - 2;
360	385	if (temp < 4 \|\| div >= 256 \|\| clk_cycle < 2) {
361	386	dev_err(i2c->dev, "%s clock set-up failed\n",
362	387	hs_timings ? "HS" : "FS");
@@ -491,6 +516,8 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) · 128 unmodified lines
491	516	switch (i2c->variant->hw) {
492	517	case I2C_TYPE_EXYNOSAUTOV9:
493	518	fallthrough;
	519	+ case I2C_TYPE_EXYNOS8895:
	520	+ fallthrough;
494	521	case I2C_TYPE_EXYNOS7:
495	522	if (int_status & HSI2C_INT_TRANS_DONE) {
496	523	i2c->trans_done = 1;

drivers/i2c/busses/i2c-i801.c+6−2

@@ -1252,6 +1252,7 @@ static const struct { · 1251 unmodified lines
1252	1252	*/
1253	1253	{ "Latitude 5480", 0x29 },
1254	1254	{ "Precision 3540", 0x29 },
	1255	+ { "Precision M6800", 0x29 },
1255	1256	{ "Vostro V131", 0x1d },
1256	1257	{ "Vostro 5568", 0x29 },
1257	1258	{ "XPS 15 7590", 0x29 },
@@ -1682,13 +1683,16 @@ static int i801_probe(struct pci_dev dev, const struct pci_device_id id) · 424 unmodified lines
1682	1683	if (!(priv->features & FEATURE_BLOCK_BUFFER))
1683	1684	priv->features &= ~FEATURE_BLOCK_PROC;
1684	1685
1685		− err = pcim_enable_device(dev);
	1686	+ /*
	1687	+ * Do not call pcim_enable_device(), because the device has to remain
	1688	+ * enabled on driver detach. See i801_remove() for the reasoning.
	1689	+ */
	1690	+ err = pci_enable_device(dev);
1686	1691	if (err) {
1687	1692	dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1688	1693	err);
1689	1694	return err;
1690	1695	}
1691		− pcim_pin_device(dev);
1692	1696
1693	1697	/* Determine the address of the SMBus area */
1694	1698	priv->smba = pci_resource_start(dev, SMBBAR);

drivers/i2c/busses/i2c-imx-lpi2c.c+799−12

@@ -8,6 +8,8 @@ · 7 unmodified lines
8	8	#include <linux/clk.h>
9	9	#include <linux/completion.h>
10	10	#include <linux/delay.h>
	11	+#include <linux/dma-mapping.h>
	12	+#include <linux/dmaengine.h>
11	13	#include <linux/err.h>
12	14	#include <linux/errno.h>
13	15	#include <linux/i2c.h>
@@ -29,6 +31,7 @@ · 15 unmodified lines
29	31	#define LPI2C_MCR 0x10 /* i2c contrl register */
30	32	#define LPI2C_MSR 0x14 /* i2c status register */
31	33	#define LPI2C_MIER 0x18 /* i2c interrupt enable */
	34	+#define LPI2C_MDER 0x1C /* i2c DMA enable */
32	35	#define LPI2C_MCFGR0 0x20 /* i2c master configuration */
33	36	#define LPI2C_MCFGR1 0x24 /* i2c master configuration */
34	37	#define LPI2C_MCFGR2 0x28 /* i2c master configuration */
@@ -40,6 +43,20 @@ · 5 unmodified lines
40	43	#define LPI2C_MTDR 0x60 /* i2c master TX data register */
41	44	#define LPI2C_MRDR 0x70 /* i2c master RX data register */
42	45
	46	+#define LPI2C_SCR 0x110 /* i2c target control register */
	47	+#define LPI2C_SSR 0x114 /* i2c target status register */
	48	+#define LPI2C_SIER 0x118 /* i2c target interrupt enable */
	49	+#define LPI2C_SDER 0x11C /* i2c target DMA enable */
	50	+#define LPI2C_SCFGR0 0x120 /* i2c target configuration */
	51	+#define LPI2C_SCFGR1 0x124 /* i2c target configuration */
	52	+#define LPI2C_SCFGR2 0x128 /* i2c target configuration */
	53	+#define LPI2C_SAMR 0x140 /* i2c target address match */
	54	+#define LPI2C_SASR 0x150 /* i2c target address status */
	55	+#define LPI2C_STAR 0x154 /* i2c target transmit ACK */
	56	+#define LPI2C_STDR 0x160 /* i2c target transmit data */
	57	+#define LPI2C_SRDR 0x170 /* i2c target receive data */
	58	+#define LPI2C_SRDROR 0x178 /* i2c target receive data read only */
	59	+
43	60	/* i2c command */
44	61	#define TRAN_DATA 0X00
45	62	#define RECV_DATA 0X01
@@ -70,11 +87,50 @@ · 24 unmodified lines
70	87	#define MCFGR1_AUTOSTOP BIT(8)
71	88	#define MCFGR1_IGNACK BIT(9)
72	89	#define MRDR_RXEMPTY BIT(14)
	90	+#define MDER_TDDE BIT(0)
	91	+#define MDER_RDDE BIT(1)
	92	+
	93	+#define SCR_SEN BIT(0)
	94	+#define SCR_RST BIT(1)
	95	+#define SCR_FILTEN BIT(4)
	96	+#define SCR_RTF BIT(8)
	97	+#define SCR_RRF BIT(9)
	98	+#define SSR_TDF BIT(0)
	99	+#define SSR_RDF BIT(1)
	100	+#define SSR_AVF BIT(2)
	101	+#define SSR_TAF BIT(3)
	102	+#define SSR_RSF BIT(8)
	103	+#define SSR_SDF BIT(9)
	104	+#define SSR_BEF BIT(10)
	105	+#define SSR_FEF BIT(11)
	106	+#define SSR_SBF BIT(24)
	107	+#define SSR_BBF BIT(25)
	108	+#define SSR_CLEAR_BITS (SSR_RSF \| SSR_SDF \| SSR_BEF \| SSR_FEF)
	109	+#define SIER_TDIE BIT(0)
	110	+#define SIER_RDIE BIT(1)
	111	+#define SIER_AVIE BIT(2)
	112	+#define SIER_TAIE BIT(3)
	113	+#define SIER_RSIE BIT(8)
	114	+#define SIER_SDIE BIT(9)
	115	+#define SIER_BEIE BIT(10)
	116	+#define SIER_FEIE BIT(11)
	117	+#define SIER_AM0F BIT(12)
	118	+#define SCFGR1_RXSTALL BIT(1)
	119	+#define SCFGR1_TXDSTALL BIT(2)
	120	+#define SCFGR2_FILTSDA_SHIFT 24
	121	+#define SCFGR2_FILTSCL_SHIFT 16
	122	+#define SCFGR2_CLKHOLD(x) (x)
	123	+#define SCFGR2_FILTSDA(x) ((x) << SCFGR2_FILTSDA_SHIFT)
	124	+#define SCFGR2_FILTSCL(x) ((x) << SCFGR2_FILTSCL_SHIFT)
	125	+#define SASR_READ_REQ 0x1
	126	+#define SLAVE_INT_FLAG (SIER_TDIE \| SIER_RDIE \| SIER_AVIE \| \
	127	+ SIER_SDIE \| SIER_BEIE)
73	128
74	129	#define I2C_CLK_RATIO 2
75	130	#define CHUNK_DATA 256
76	131
77	132	#define I2C_PM_TIMEOUT 10 /* ms */
	133	+#define I2C_DMA_THRESHOLD 8 /* bytes */
78	134
79	135	enum lpi2c_imx_mode {
80	136	STANDARD, /* 100+Kbps */
@@ -91,6 +147,24 @@ enum lpi2c_imx_pincfg { · 10 unmodified lines
91	147	FOUR_PIN_PP,
92	148	};
93	149
	150	+struct lpi2c_imx_dma {
	151	+ bool using_pio_mode;
	152	+ u8 rx_cmd_buf_len;
	153	+ u8 *dma_buf;
	154	+ u16 *rx_cmd_buf;
	155	+ unsigned int dma_len;
	156	+ unsigned int tx_burst_num;
	157	+ unsigned int rx_burst_num;
	158	+ unsigned long dma_msg_flag;
	159	+ resource_size_t phy_addr;
	160	+ dma_addr_t dma_tx_addr;
	161	+ dma_addr_t dma_addr;
	162	+ enum dma_data_direction dma_data_dir;
	163	+ enum dma_transfer_direction dma_transfer_dir;
	164	+ struct dma_chan *chan_tx;
	165	+ struct dma_chan *chan_rx;
	166	+};
	167	+
94	168	struct lpi2c_imx_struct {
95	169	struct i2c_adapter adapter;
96	170	int num_clks;
@@ -108,6 +182,9 @@ struct lpi2c_imx_struct { · 11 unmodified lines
108	182	unsigned int rxfifosize;
109	183	enum lpi2c_imx_mode mode;
110	184	struct i2c_bus_recovery_info rinfo;
	185	+ bool can_use_dma;
	186	+ struct lpi2c_imx_dma *dma;
	187	+ struct i2c_client *target;
111	188	};
112	189
113	190	static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
@@ -305,7 +382,7 @@ static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx) · 191 unmodified lines
305	382	return 0;
306	383	}
307	384
308		−static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
	385	+static int lpi2c_imx_pio_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
309	386	{
310	387	unsigned long time_left;
311	388
@@ -451,6 +528,425 @@ static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx, · 139 unmodified lines
451	528	lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE \| MIER_NDIE);
452	529	}
453	530
	531	+static bool is_use_dma(struct lpi2c_imx_struct lpi2c_imx, struct i2c_msg msg)
	532	+{
	533	+ if (!lpi2c_imx->can_use_dma)
	534	+ return false;
	535	+
	536	+ /*
	537	+ * When the length of data is less than I2C_DMA_THRESHOLD,
	538	+ * cpu mode is used directly to avoid low performance.
	539	+ */
	540	+ return !(msg->len < I2C_DMA_THRESHOLD);
	541	+}
	542	+
	543	+static int lpi2c_imx_pio_xfer(struct lpi2c_imx_struct *lpi2c_imx,
	544	+ struct i2c_msg *msg)
	545	+{
	546	+ reinit_completion(&lpi2c_imx->complete);
	547	+
	548	+ if (msg->flags & I2C_M_RD)
	549	+ lpi2c_imx_read(lpi2c_imx, msg);
	550	+ else
	551	+ lpi2c_imx_write(lpi2c_imx, msg);
	552	+
	553	+ return lpi2c_imx_pio_msg_complete(lpi2c_imx);
	554	+}
	555	+
	556	+static int lpi2c_imx_dma_timeout_calculate(struct lpi2c_imx_struct *lpi2c_imx)
	557	+{
	558	+ unsigned long time = 0;
	559	+
	560	+ time = 8 * lpi2c_imx->dma->dma_len * 1000 / lpi2c_imx->bitrate;
	561	+
	562	+ /* Add extra second for scheduler related activities */
	563	+ time += 1;
	564	+
	565	+ /* Double calculated time */
	566	+ return msecs_to_jiffies(time * MSEC_PER_SEC);
	567	+}
	568	+
	569	+static int lpi2c_imx_alloc_rx_cmd_buf(struct lpi2c_imx_struct *lpi2c_imx)
	570	+{
	571	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	572	+ u16 rx_remain = dma->dma_len;
	573	+ int cmd_num;
	574	+ u16 temp;
	575	+
	576	+ /*
	577	+ * Calculate the number of rx command words via the DMA TX channel
	578	+ * writing into command register based on the i2c msg len, and build
	579	+ * the rx command words buffer.
	580	+ */
	581	+ cmd_num = DIV_ROUND_UP(rx_remain, CHUNK_DATA);
	582	+ dma->rx_cmd_buf = kcalloc(cmd_num, sizeof(u16), GFP_KERNEL);
	583	+ dma->rx_cmd_buf_len = cmd_num * sizeof(u16);
	584	+
	585	+ if (!dma->rx_cmd_buf) {
	586	+ dev_err(&lpi2c_imx->adapter.dev, "Alloc RX cmd buffer failed\n");
	587	+ return -ENOMEM;
	588	+ }
	589	+
	590	+ for (int i = 0; i < cmd_num ; i++) {
	591	+ temp = rx_remain > CHUNK_DATA ? CHUNK_DATA - 1 : rx_remain - 1;
	592	+ temp \|= (RECV_DATA << 8);
	593	+ rx_remain -= CHUNK_DATA;
	594	+ dma->rx_cmd_buf[i] = temp;
	595	+ }
	596	+
	597	+ return 0;
	598	+}
	599	+
	600	+static int lpi2c_imx_dma_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
	601	+{
	602	+ unsigned long time_left, time;
	603	+
	604	+ time = lpi2c_imx_dma_timeout_calculate(lpi2c_imx);
	605	+ time_left = wait_for_completion_timeout(&lpi2c_imx->complete, time);
	606	+ if (time_left == 0) {
	607	+ dev_err(&lpi2c_imx->adapter.dev, "I/O Error in DMA Data Transfer\n");
	608	+ return -ETIMEDOUT;
	609	+ }
	610	+
	611	+ return 0;
	612	+}
	613	+
	614	+static void lpi2c_dma_unmap(struct lpi2c_imx_dma *dma)
	615	+{
	616	+ struct dma_chan *chan = dma->dma_data_dir == DMA_FROM_DEVICE
	617	+ ? dma->chan_rx : dma->chan_tx;
	618	+
	619	+ dma_unmap_single(chan->device->dev, dma->dma_addr,
	620	+ dma->dma_len, dma->dma_data_dir);
	621	+
	622	+ dma->dma_data_dir = DMA_NONE;
	623	+}
	624	+
	625	+static void lpi2c_cleanup_rx_cmd_dma(struct lpi2c_imx_dma *dma)
	626	+{
	627	+ dmaengine_terminate_sync(dma->chan_tx);
	628	+ dma_unmap_single(dma->chan_tx->device->dev, dma->dma_tx_addr,
	629	+ dma->rx_cmd_buf_len, DMA_TO_DEVICE);
	630	+}
	631	+
	632	+static void lpi2c_cleanup_dma(struct lpi2c_imx_dma *dma)
	633	+{
	634	+ if (dma->dma_data_dir == DMA_FROM_DEVICE)
	635	+ dmaengine_terminate_sync(dma->chan_rx);
	636	+ else if (dma->dma_data_dir == DMA_TO_DEVICE)
	637	+ dmaengine_terminate_sync(dma->chan_tx);
	638	+
	639	+ lpi2c_dma_unmap(dma);
	640	+}
	641	+
	642	+static void lpi2c_dma_callback(void *data)
	643	+{
	644	+ struct lpi2c_imx_struct lpi2c_imx = (struct lpi2c_imx_struct )data;
	645	+
	646	+ complete(&lpi2c_imx->complete);
	647	+}
	648	+
	649	+static int lpi2c_dma_rx_cmd_submit(struct lpi2c_imx_struct *lpi2c_imx)
	650	+{
	651	+ struct dma_async_tx_descriptor *rx_cmd_desc;
	652	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	653	+ struct dma_chan *txchan = dma->chan_tx;
	654	+ dma_cookie_t cookie;
	655	+
	656	+ dma->dma_tx_addr = dma_map_single(txchan->device->dev,
	657	+ dma->rx_cmd_buf, dma->rx_cmd_buf_len,
	658	+ DMA_TO_DEVICE);
	659	+ if (dma_mapping_error(txchan->device->dev, dma->dma_tx_addr)) {
	660	+ dev_err(&lpi2c_imx->adapter.dev, "DMA map failed, use pio\n");
	661	+ return -EINVAL;
	662	+ }
	663	+
	664	+ rx_cmd_desc = dmaengine_prep_slave_single(txchan, dma->dma_tx_addr,
	665	+ dma->rx_cmd_buf_len, DMA_MEM_TO_DEV,
	666	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	667	+ if (!rx_cmd_desc) {
	668	+ dev_err(&lpi2c_imx->adapter.dev, "DMA prep slave sg failed, use pio\n");
	669	+ goto desc_prepare_err_exit;
	670	+ }
	671	+
	672	+ cookie = dmaengine_submit(rx_cmd_desc);
	673	+ if (dma_submit_error(cookie)) {
	674	+ dev_err(&lpi2c_imx->adapter.dev, "submitting DMA failed, use pio\n");
	675	+ goto submit_err_exit;
	676	+ }
	677	+
	678	+ dma_async_issue_pending(txchan);
	679	+
	680	+ return 0;
	681	+
	682	+desc_prepare_err_exit:
	683	+ dma_unmap_single(txchan->device->dev, dma->dma_tx_addr,
	684	+ dma->rx_cmd_buf_len, DMA_TO_DEVICE);
	685	+ return -EINVAL;
	686	+
	687	+submit_err_exit:
	688	+ dma_unmap_single(txchan->device->dev, dma->dma_tx_addr,
	689	+ dma->rx_cmd_buf_len, DMA_TO_DEVICE);
	690	+ dmaengine_desc_free(rx_cmd_desc);
	691	+ return -EINVAL;
	692	+}
	693	+
	694	+static int lpi2c_dma_submit(struct lpi2c_imx_struct *lpi2c_imx)
	695	+{
	696	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	697	+ struct dma_async_tx_descriptor *desc;
	698	+ struct dma_chan *chan;
	699	+ dma_cookie_t cookie;
	700	+
	701	+ if (dma->dma_msg_flag & I2C_M_RD) {
	702	+ chan = dma->chan_rx;
	703	+ dma->dma_data_dir = DMA_FROM_DEVICE;
	704	+ dma->dma_transfer_dir = DMA_DEV_TO_MEM;
	705	+ } else {
	706	+ chan = dma->chan_tx;
	707	+ dma->dma_data_dir = DMA_TO_DEVICE;
	708	+ dma->dma_transfer_dir = DMA_MEM_TO_DEV;
	709	+ }
	710	+
	711	+ dma->dma_addr = dma_map_single(chan->device->dev,
	712	+ dma->dma_buf, dma->dma_len, dma->dma_data_dir);
	713	+ if (dma_mapping_error(chan->device->dev, dma->dma_addr)) {
	714	+ dev_err(&lpi2c_imx->adapter.dev, "DMA map failed, use pio\n");
	715	+ return -EINVAL;
	716	+ }
	717	+
	718	+ desc = dmaengine_prep_slave_single(chan, dma->dma_addr,
	719	+ dma->dma_len, dma->dma_transfer_dir,
	720	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	721	+ if (!desc) {
	722	+ dev_err(&lpi2c_imx->adapter.dev, "DMA prep slave sg failed, use pio\n");
	723	+ goto desc_prepare_err_exit;
	724	+ }
	725	+
	726	+ reinit_completion(&lpi2c_imx->complete);
	727	+ desc->callback = lpi2c_dma_callback;
	728	+ desc->callback_param = lpi2c_imx;
	729	+
	730	+ cookie = dmaengine_submit(desc);
	731	+ if (dma_submit_error(cookie)) {
	732	+ dev_err(&lpi2c_imx->adapter.dev, "submitting DMA failed, use pio\n");
	733	+ goto submit_err_exit;
	734	+ }
	735	+
	736	+ /* Can't switch to PIO mode when DMA have started transfer */
	737	+ dma->using_pio_mode = false;
	738	+
	739	+ dma_async_issue_pending(chan);
	740	+
	741	+ return 0;
	742	+
	743	+desc_prepare_err_exit:
	744	+ lpi2c_dma_unmap(dma);
	745	+ return -EINVAL;
	746	+
	747	+submit_err_exit:
	748	+ lpi2c_dma_unmap(dma);
	749	+ dmaengine_desc_free(desc);
	750	+ return -EINVAL;
	751	+}
	752	+
	753	+static int lpi2c_imx_find_max_burst_num(unsigned int fifosize, unsigned int len)
	754	+{
	755	+ unsigned int i;
	756	+
	757	+ for (i = fifosize / 2; i > 0; i--)
	758	+ if (!(len % i))
	759	+ break;
	760	+
	761	+ return i;
	762	+}
	763	+
	764	+/*
	765	+ * For a highest DMA efficiency, tx/rx burst number should be calculated according
	766	+ * to the FIFO depth.
	767	+ */
	768	+static void lpi2c_imx_dma_burst_num_calculate(struct lpi2c_imx_struct *lpi2c_imx)
	769	+{
	770	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	771	+ unsigned int cmd_num;
	772	+
	773	+ if (dma->dma_msg_flag & I2C_M_RD) {
	774	+ /*
	775	+ * One RX cmd word can trigger DMA receive no more than 256 bytes.
	776	+ * The number of RX cmd words should be calculated based on the data
	777	+ * length.
	778	+ */
	779	+ cmd_num = DIV_ROUND_UP(dma->dma_len, CHUNK_DATA);
	780	+ dma->tx_burst_num = lpi2c_imx_find_max_burst_num(lpi2c_imx->txfifosize,
	781	+ cmd_num);
	782	+ dma->rx_burst_num = lpi2c_imx_find_max_burst_num(lpi2c_imx->rxfifosize,
	783	+ dma->dma_len);
	784	+ } else {
	785	+ dma->tx_burst_num = lpi2c_imx_find_max_burst_num(lpi2c_imx->txfifosize,
	786	+ dma->dma_len);
	787	+ }
	788	+}
	789	+
	790	+static int lpi2c_dma_config(struct lpi2c_imx_struct *lpi2c_imx)
	791	+{
	792	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	793	+ struct dma_slave_config rx = {}, tx = {};
	794	+ int ret;
	795	+
	796	+ lpi2c_imx_dma_burst_num_calculate(lpi2c_imx);
	797	+
	798	+ if (dma->dma_msg_flag & I2C_M_RD) {
	799	+ tx.dst_addr = dma->phy_addr + LPI2C_MTDR;
	800	+ tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	801	+ tx.dst_maxburst = dma->tx_burst_num;
	802	+ tx.direction = DMA_MEM_TO_DEV;
	803	+ ret = dmaengine_slave_config(dma->chan_tx, &tx);
	804	+ if (ret < 0)
	805	+ return ret;
	806	+
	807	+ rx.src_addr = dma->phy_addr + LPI2C_MRDR;
	808	+ rx.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	809	+ rx.src_maxburst = dma->rx_burst_num;
	810	+ rx.direction = DMA_DEV_TO_MEM;
	811	+ ret = dmaengine_slave_config(dma->chan_rx, &rx);
	812	+ if (ret < 0)
	813	+ return ret;
	814	+ } else {
	815	+ tx.dst_addr = dma->phy_addr + LPI2C_MTDR;
	816	+ tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	817	+ tx.dst_maxburst = dma->tx_burst_num;
	818	+ tx.direction = DMA_MEM_TO_DEV;
	819	+ ret = dmaengine_slave_config(dma->chan_tx, &tx);
	820	+ if (ret < 0)
	821	+ return ret;
	822	+ }
	823	+
	824	+ return 0;
	825	+}
	826	+
	827	+static void lpi2c_dma_enable(struct lpi2c_imx_struct *lpi2c_imx)
	828	+{
	829	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	830	+ /*
	831	+ * TX interrupt will be triggered when the number of words in
	832	+ * the transmit FIFO is equal or less than TX watermark.
	833	+ * RX interrupt will be triggered when the number of words in
	834	+ * the receive FIFO is greater than RX watermark.
	835	+ * In order to trigger the DMA interrupt, TX watermark should be
	836	+ * set equal to the DMA TX burst number but RX watermark should
	837	+ * be set less than the DMA RX burst number.
	838	+ */
	839	+ if (dma->dma_msg_flag & I2C_M_RD) {
	840	+ /* Set I2C TX/RX watermark */
	841	+ writel(dma->tx_burst_num \| (dma->rx_burst_num - 1) << 16,
	842	+ lpi2c_imx->base + LPI2C_MFCR);
	843	+ /* Enable I2C DMA TX/RX function */
	844	+ writel(MDER_TDDE \| MDER_RDDE, lpi2c_imx->base + LPI2C_MDER);
	845	+ } else {
	846	+ /* Set I2C TX watermark */
	847	+ writel(dma->tx_burst_num, lpi2c_imx->base + LPI2C_MFCR);
	848	+ /* Enable I2C DMA TX function */
	849	+ writel(MDER_TDDE, lpi2c_imx->base + LPI2C_MDER);
	850	+ }
	851	+
	852	+ /* Enable NACK detected */
	853	+ lpi2c_imx_intctrl(lpi2c_imx, MIER_NDIE);
	854	+};
	855	+
	856	+/*
	857	+ * When lpi2c is in TX DMA mode we can use one DMA TX channel to write
	858	+ * data word into TXFIFO, but in RX DMA mode it is different.
	859	+ *
	860	+ * The LPI2C MTDR register is a command data and transmit data register.
	861	+ * Bits 8-10 are the command data field and Bits 0-7 are the transmit
	862	+ * data field. When the LPI2C master needs to read data, the number of
	863	+ * bytes to read should be set in the command field and RECV_DATA should
	864	+ * be set into the command data field to receive (DATA[7:0] + 1) bytes.
	865	+ * The recv data command word is made of RECV_DATA in the command data
	866	+ * field and the number of bytes to read in transmit data field. When the
	867	+ * length of data to be read exceeds 256 bytes, recv data command word
	868	+ * needs to be written to TXFIFO multiple times.
	869	+ *
	870	+ * So when in RX DMA mode, the TX channel also must to be configured to
	871	+ * send RX command words and the RX command word must be set in advance
	872	+ * before transmitting.
	873	+ */
	874	+static int lpi2c_imx_dma_xfer(struct lpi2c_imx_struct *lpi2c_imx,
	875	+ struct i2c_msg *msg)
	876	+{
	877	+ struct lpi2c_imx_dma *dma = lpi2c_imx->dma;
	878	+ int ret;
	879	+
	880	+ /* When DMA mode fails before transferring, CPU mode can be used. */
	881	+ dma->using_pio_mode = true;
	882	+
	883	+ dma->dma_len = msg->len;
	884	+ dma->dma_msg_flag = msg->flags;
	885	+ dma->dma_buf = i2c_get_dma_safe_msg_buf(msg, I2C_DMA_THRESHOLD);
	886	+ if (!dma->dma_buf)
	887	+ return -ENOMEM;
	888	+
	889	+ ret = lpi2c_dma_config(lpi2c_imx);
	890	+ if (ret) {
	891	+ dev_err(&lpi2c_imx->adapter.dev, "Failed to configure DMA (%d)\n", ret);
	892	+ goto disable_dma;
	893	+ }
	894	+
	895	+ lpi2c_dma_enable(lpi2c_imx);
	896	+
	897	+ ret = lpi2c_dma_submit(lpi2c_imx);
	898	+ if (ret) {
	899	+ dev_err(&lpi2c_imx->adapter.dev, "DMA submission failed (%d)\n", ret);
	900	+ goto disable_dma;
	901	+ }
	902	+
	903	+ if (dma->dma_msg_flag & I2C_M_RD) {
	904	+ ret = lpi2c_imx_alloc_rx_cmd_buf(lpi2c_imx);
	905	+ if (ret)
	906	+ goto disable_cleanup_data_dma;
	907	+
	908	+ ret = lpi2c_dma_rx_cmd_submit(lpi2c_imx);
	909	+ if (ret)
	910	+ goto disable_cleanup_data_dma;
	911	+ }
	912	+
	913	+ ret = lpi2c_imx_dma_msg_complete(lpi2c_imx);
	914	+ if (ret)
	915	+ goto disable_cleanup_all_dma;
	916	+
	917	+ /* When encountering NACK in transfer, clean up all DMA transfers */
	918	+ if ((readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) && !ret) {
	919	+ ret = -EIO;
	920	+ goto disable_cleanup_all_dma;
	921	+ }
	922	+
	923	+ if (dma->dma_msg_flag & I2C_M_RD)
	924	+ dma_unmap_single(dma->chan_tx->device->dev, dma->dma_tx_addr,
	925	+ dma->rx_cmd_buf_len, DMA_TO_DEVICE);
	926	+ lpi2c_dma_unmap(dma);
	927	+
	928	+ goto disable_dma;
	929	+
	930	+disable_cleanup_all_dma:
	931	+ if (dma->dma_msg_flag & I2C_M_RD)
	932	+ lpi2c_cleanup_rx_cmd_dma(dma);
	933	+disable_cleanup_data_dma:
	934	+ lpi2c_cleanup_dma(dma);
	935	+disable_dma:
	936	+ /* Disable I2C DMA function */
	937	+ writel(0, lpi2c_imx->base + LPI2C_MDER);
	938	+
	939	+ if (dma->dma_msg_flag & I2C_M_RD)
	940	+ kfree(dma->rx_cmd_buf);
	941	+
	942	+ if (ret)
	943	+ i2c_put_dma_safe_msg_buf(dma->dma_buf, msg, false);
	944	+ else
	945	+ i2c_put_dma_safe_msg_buf(dma->dma_buf, msg, true);
	946	+
	947	+ return ret;
	948	+}
	949	+
454	950	static int lpi2c_imx_xfer(struct i2c_adapter *adapter,
455	951	struct i2c_msg *msgs, int num)
456	952	{
@@ -477,12 +973,14 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, · 20 unmodified lines
477	973	lpi2c_imx->msglen = msgs[i].len;
478	974	init_completion(&lpi2c_imx->complete);
479	975
480		− if (msgs[i].flags & I2C_M_RD)
481		− lpi2c_imx_read(lpi2c_imx, &msgs[i]);
482		− else
483		− lpi2c_imx_write(lpi2c_imx, &msgs[i]);
	976	+ if (is_use_dma(lpi2c_imx, &msgs[i])) {
	977	+ result = lpi2c_imx_dma_xfer(lpi2c_imx, &msgs[i]);
	978	+ if (result && lpi2c_imx->dma->using_pio_mode)
	979	+ result = lpi2c_imx_pio_xfer(lpi2c_imx, &msgs[i]);
	980	+ } else {
	981	+ result = lpi2c_imx_pio_xfer(lpi2c_imx, &msgs[i]);
	982	+ }
484	983
485		− result = lpi2c_imx_msg_complete(lpi2c_imx);
486	984	if (result)
487	985	goto stop;
488	986
@@ -510,9 +1008,56 @@ disable: · 21 unmodified lines
510	1008	return (result < 0) ? result : num;
511	1009	}
512	1010
513		−static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
	1011	+static irqreturn_t lpi2c_imx_target_isr(struct lpi2c_imx_struct *lpi2c_imx,
	1012	+ u32 ssr, u32 sier_filter)
	1013	+{
	1014	+ u8 value;
	1015	+ u32 sasr;
	1016	+
	1017	+ /* Arbitration lost */
	1018	+ if (sier_filter & SSR_BEF) {
	1019	+ writel(0, lpi2c_imx->base + LPI2C_SIER);
	1020	+ return IRQ_HANDLED;
	1021	+ }
	1022	+
	1023	+ /* Address detected */
	1024	+ if (sier_filter & SSR_AVF) {
	1025	+ sasr = readl(lpi2c_imx->base + LPI2C_SASR);
	1026	+ if (SASR_READ_REQ & sasr) {
	1027	+ /* Read request */
	1028	+ i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_READ_REQUESTED, &value);
	1029	+ writel(value, lpi2c_imx->base + LPI2C_STDR);
	1030	+ goto ret;
	1031	+ } else {
	1032	+ /* Write request */
	1033	+ i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_WRITE_REQUESTED, &value);
	1034	+ }
	1035	+ }
	1036	+
	1037	+ if (sier_filter & SSR_SDF)
	1038	+ /* STOP */
	1039	+ i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_STOP, &value);
	1040	+
	1041	+ if (sier_filter & SSR_TDF) {
	1042	+ /* Target send data */
	1043	+ i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_READ_PROCESSED, &value);
	1044	+ writel(value, lpi2c_imx->base + LPI2C_STDR);
	1045	+ }
	1046	+
	1047	+ if (sier_filter & SSR_RDF) {
	1048	+ /* Target receive data */
	1049	+ value = readl(lpi2c_imx->base + LPI2C_SRDR);
	1050	+ i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_WRITE_RECEIVED, &value);
	1051	+ }
	1052	+
	1053	+ret:
	1054	+ /* Clear SSR */
	1055	+ writel(ssr & SSR_CLEAR_BITS, lpi2c_imx->base + LPI2C_SSR);
	1056	+ return IRQ_HANDLED;
	1057	+}
	1058	+
	1059	+static irqreturn_t lpi2c_imx_master_isr(struct lpi2c_imx_struct *lpi2c_imx)
514	1060	{
515		− struct lpi2c_imx_struct *lpi2c_imx = dev_id;
516	1061	unsigned int enabled;
517	1062	unsigned int temp;
518	1063
@@ -532,6 +1077,124 @@ static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) · 13 unmodified lines
532	1077	return IRQ_HANDLED;
533	1078	}
534	1079
	1080	+static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
	1081	+{
	1082	+ struct lpi2c_imx_struct *lpi2c_imx = dev_id;
	1083	+
	1084	+ if (lpi2c_imx->target) {
	1085	+ u32 scr = readl(lpi2c_imx->base + LPI2C_SCR);
	1086	+ u32 ssr = readl(lpi2c_imx->base + LPI2C_SSR);
	1087	+ u32 sier_filter = ssr & readl(lpi2c_imx->base + LPI2C_SIER);
	1088	+
	1089	+ /*
	1090	+ * The target is enabled and an interrupt has been triggered.
	1091	+ * Enter the target's irq handler.
	1092	+ */
	1093	+ if ((scr & SCR_SEN) && sier_filter)
	1094	+ return lpi2c_imx_target_isr(lpi2c_imx, ssr, sier_filter);
	1095	+ }
	1096	+
	1097	+ /*
	1098	+ * Otherwise the interrupt has been triggered by the master.
	1099	+ * Enter the master's irq handler.
	1100	+ */
	1101	+ return lpi2c_imx_master_isr(lpi2c_imx);
	1102	+}
	1103	+
	1104	+static void lpi2c_imx_target_init(struct lpi2c_imx_struct *lpi2c_imx)
	1105	+{
	1106	+ u32 temp;
	1107	+
	1108	+ /* reset target module */
	1109	+ writel(SCR_RST, lpi2c_imx->base + LPI2C_SCR);
	1110	+ writel(0, lpi2c_imx->base + LPI2C_SCR);
	1111	+
	1112	+ /* Set target address */
	1113	+ writel((lpi2c_imx->target->addr << 1), lpi2c_imx->base + LPI2C_SAMR);
	1114	+
	1115	+ writel(SCFGR1_RXSTALL \| SCFGR1_TXDSTALL, lpi2c_imx->base + LPI2C_SCFGR1);
	1116	+
	1117	+ /*
	1118	+ * set SCFGR2: FILTSDA, FILTSCL and CLKHOLD
	1119	+ *
	1120	+ * FILTSCL/FILTSDA can eliminate signal skew. It should generally be
	1121	+ * set to the same value and should be set >= 50ns.
	1122	+ *
	1123	+ * CLKHOLD is only used when clock stretching is enabled, but it will
	1124	+ * extend the clock stretching to ensure there is an additional delay
	1125	+ * between the target driving SDA and the target releasing the SCL pin.
	1126	+ *
	1127	+ * CLKHOLD setting is crucial for lpi2c target. When master read data
	1128	+ * from target, if there is a delay caused by cpu idle, excessive load,
	1129	+ * or other delays between two bytes in one message transmission, it
	1130	+ * will cause a short interval time between the driving SDA signal and
	1131	+ * releasing SCL signal. The lpi2c master will mistakenly think it is a stop
	1132	+ * signal resulting in an arbitration failure. This issue can be avoided
	1133	+ * by setting CLKHOLD.
	1134	+ *
	1135	+ * In order to ensure lpi2c function normally when the lpi2c speed is as
	1136	+ * low as 100kHz, CLKHOLD should be set to 3 and it is also compatible with
	1137	+ * higher clock frequency like 400kHz and 1MHz.
	1138	+ */
	1139	+ temp = SCFGR2_FILTSDA(2) \| SCFGR2_FILTSCL(2) \| SCFGR2_CLKHOLD(3);
	1140	+ writel(temp, lpi2c_imx->base + LPI2C_SCFGR2);
	1141	+
	1142	+ /*
	1143	+ * Enable module:
	1144	+ * SCR_FILTEN can enable digital filter and output delay counter for LPI2C
	1145	+ * target mode. So SCR_FILTEN need be asserted when enable SDA/SCL FILTER
	1146	+ * and CLKHOLD.
	1147	+ */
	1148	+ writel(SCR_SEN \| SCR_FILTEN, lpi2c_imx->base + LPI2C_SCR);
	1149	+
	1150	+ /* Enable interrupt from i2c module */
	1151	+ writel(SLAVE_INT_FLAG, lpi2c_imx->base + LPI2C_SIER);
	1152	+}
	1153	+
	1154	+static int lpi2c_imx_register_target(struct i2c_client *client)
	1155	+{
	1156	+ struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(client->adapter);
	1157	+ int ret;
	1158	+
	1159	+ if (lpi2c_imx->target)
	1160	+ return -EBUSY;
	1161	+
	1162	+ lpi2c_imx->target = client;
	1163	+
	1164	+ ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent);
	1165	+ if (ret < 0) {
	1166	+ dev_err(&lpi2c_imx->adapter.dev, "failed to resume i2c controller");
	1167	+ return ret;
	1168	+ }
	1169	+
	1170	+ lpi2c_imx_target_init(lpi2c_imx);
	1171	+
	1172	+ return 0;
	1173	+}
	1174	+
	1175	+static int lpi2c_imx_unregister_target(struct i2c_client *client)
	1176	+{
	1177	+ struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(client->adapter);
	1178	+ int ret;
	1179	+
	1180	+ if (!lpi2c_imx->target)
	1181	+ return -EINVAL;
	1182	+
	1183	+ /* Reset target address. */
	1184	+ writel(0, lpi2c_imx->base + LPI2C_SAMR);
	1185	+
	1186	+ writel(SCR_RST, lpi2c_imx->base + LPI2C_SCR);
	1187	+ writel(0, lpi2c_imx->base + LPI2C_SCR);
	1188	+
	1189	+ lpi2c_imx->target = NULL;
	1190	+
	1191	+ ret = pm_runtime_put_sync(lpi2c_imx->adapter.dev.parent);
	1192	+ if (ret < 0)
	1193	+ dev_err(&lpi2c_imx->adapter.dev, "failed to suspend i2c controller");
	1194	+
	1195	+ return ret;
	1196	+}
	1197	+
535	1198	static int lpi2c_imx_init_recovery_info(struct lpi2c_imx_struct *lpi2c_imx,
536	1199	struct platform_device *pdev)
537	1200	{
@@ -546,6 +1209,58 @@ static int lpi2c_imx_init_recovery_info(struct lpi2c_imx_struct *lpi2c_imx, · 8 unmodified lines
546	1209	return 0;
547	1210	}
548	1211
	1212	+static void dma_exit(struct device dev, struct lpi2c_imx_dma dma)
	1213	+{
	1214	+ if (dma->chan_rx)
	1215	+ dma_release_channel(dma->chan_rx);
	1216	+
	1217	+ if (dma->chan_tx)
	1218	+ dma_release_channel(dma->chan_tx);
	1219	+
	1220	+ devm_kfree(dev, dma);
	1221	+}
	1222	+
	1223	+static int lpi2c_dma_init(struct device *dev, dma_addr_t phy_addr)
	1224	+{
	1225	+ struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
	1226	+ struct lpi2c_imx_dma *dma;
	1227	+ int ret;
	1228	+
	1229	+ dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
	1230	+ if (!dma)
	1231	+ return -ENOMEM;
	1232	+
	1233	+ dma->phy_addr = phy_addr;
	1234	+
	1235	+ /* Prepare for TX DMA: */
	1236	+ dma->chan_tx = dma_request_chan(dev, "tx");
	1237	+ if (IS_ERR(dma->chan_tx)) {
	1238	+ ret = PTR_ERR(dma->chan_tx);
	1239	+ if (ret != -ENODEV && ret != -EPROBE_DEFER)
	1240	+ dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
	1241	+ dma->chan_tx = NULL;
	1242	+ goto dma_exit;
	1243	+ }
	1244	+
	1245	+ /* Prepare for RX DMA: */
	1246	+ dma->chan_rx = dma_request_chan(dev, "rx");
	1247	+ if (IS_ERR(dma->chan_rx)) {
	1248	+ ret = PTR_ERR(dma->chan_rx);
	1249	+ if (ret != -ENODEV && ret != -EPROBE_DEFER)
	1250	+ dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
	1251	+ dma->chan_rx = NULL;
	1252	+ goto dma_exit;
	1253	+ }
	1254	+
	1255	+ lpi2c_imx->can_use_dma = true;
	1256	+ lpi2c_imx->dma = dma;
	1257	+ return 0;
	1258	+
	1259	+dma_exit:
	1260	+ dma_exit(dev, dma);
	1261	+ return ret;
	1262	+}
	1263	+
549	1264	static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
550	1265	{
551	1266	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
@@ -555,6 +1270,8 @@ static u32 lpi2c_imx_func(struct i2c_adapter *adapter) · 3 unmodified lines
555	1270	static const struct i2c_algorithm lpi2c_imx_algo = {
556	1271	.master_xfer = lpi2c_imx_xfer,
557	1272	.functionality = lpi2c_imx_func,
	1273	+ .reg_target = lpi2c_imx_register_target,
	1274	+ .unreg_target = lpi2c_imx_unregister_target,
558	1275	};
559	1276
560	1277	static const struct of_device_id lpi2c_imx_of_match[] = {
@@ -566,6 +1283,8 @@ MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); · 5 unmodified lines
566	1283	static int lpi2c_imx_probe(struct platform_device *pdev)
567	1284	{
568	1285	struct lpi2c_imx_struct *lpi2c_imx;
	1286	+ struct resource *res;
	1287	+ dma_addr_t phy_addr;
569	1288	unsigned int temp;
570	1289	int irq, ret;
571	1290
@@ -573,7 +1292,7 @@ static int lpi2c_imx_probe(struct platform_device *pdev) · 1 unmodified line
573	1292	if (!lpi2c_imx)
574	1293	return -ENOMEM;
575	1294
576		− lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0);
	1295	+ lpi2c_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
577	1296	if (IS_ERR(lpi2c_imx->base))
578	1297	return PTR_ERR(lpi2c_imx->base);
579	1298
@@ -587,6 +1306,7 @@ static int lpi2c_imx_probe(struct platform_device *pdev) · 7 unmodified lines
587	1306	lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node;
588	1307	strscpy(lpi2c_imx->adapter.name, pdev->name,
589	1308	sizeof(lpi2c_imx->adapter.name));
	1309	+ phy_addr = (dma_addr_t)res->start;
590	1310
591	1311	ret = devm_clk_bulk_get_all(&pdev->dev, &lpi2c_imx->clks);
592	1312	if (ret < 0)
@@ -598,7 +1318,7 @@ static int lpi2c_imx_probe(struct platform_device *pdev) · 5 unmodified lines
598	1318	if (ret)
599	1319	lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
600	1320
601		− ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0,
	1321	+ ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, IRQF_NO_SUSPEND,
602	1322	pdev->name, lpi2c_imx);
603	1323	if (ret)
604	1324	return dev_err_probe(&pdev->dev, ret, "can't claim irq %d\n", irq);
@@ -640,6 +1360,14 @@ static int lpi2c_imx_probe(struct platform_device *pdev) · 35 unmodified lines
640	1360	if (ret == -EPROBE_DEFER)
641	1361	goto rpm_disable;
642	1362
	1363	+ /* Init DMA */
	1364	+ ret = lpi2c_dma_init(&pdev->dev, phy_addr);
	1365	+ if (ret) {
	1366	+ if (ret == -EPROBE_DEFER)
	1367	+ goto rpm_disable;
	1368	+ dev_info(&pdev->dev, "use pio mode\n");
	1369	+ }
	1370	+
643	1371	ret = i2c_add_adapter(&lpi2c_imx->adapter);
644	1372	if (ret)
645	1373	goto rpm_disable;
@@ -694,9 +1422,68 @@ static int __maybe_unused lpi2c_runtime_resume(struct device *dev) · 48 unmodified lines
694	1422	return 0;
695	1423	}
696	1424
	1425	+static int __maybe_unused lpi2c_suspend_noirq(struct device *dev)
	1426	+{
	1427	+ return pm_runtime_force_suspend(dev);
	1428	+}
	1429	+
	1430	+static int __maybe_unused lpi2c_resume_noirq(struct device *dev)
	1431	+{
	1432	+ struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
	1433	+ int ret;
	1434	+
	1435	+ ret = pm_runtime_force_resume(dev);
	1436	+ if (ret)
	1437	+ return ret;
	1438	+
	1439	+ /*
	1440	+ * If the I2C module powers down during system suspend,
	1441	+ * the register values will be lost. Therefore, reinitialize
	1442	+ * the target when the system resumes.
	1443	+ */
	1444	+ if (lpi2c_imx->target)
	1445	+ lpi2c_imx_target_init(lpi2c_imx);
	1446	+
	1447	+ return 0;
	1448	+}
	1449	+
	1450	+static int lpi2c_suspend(struct device *dev)
	1451	+{
	1452	+ /*
	1453	+ * Some I2C devices may need the I2C controller to remain active
	1454	+ * during resume_noirq() or suspend_noirq(). If the controller is
	1455	+ * autosuspended, there is no way to wake it up once runtime PM is
	1456	+ * disabled (in suspend_late()).
	1457	+ *
	1458	+ * During system resume, the I2C controller will be available only
	1459	+ * after runtime PM is re-enabled (in resume_early()). However, this
	1460	+ * may be too late for some devices.
	1461	+ *
	1462	+ * Wake up the controller in the suspend() callback while runtime PM
	1463	+ * is still enabled. The I2C controller will remain available until
	1464	+ * the suspend_noirq() callback (pm_runtime_force_suspend()) is
	1465	+ * called. During resume, the I2C controller can be restored by the
	1466	+ * resume_noirq() callback (pm_runtime_force_resume()).
	1467	+ *
	1468	+ * Finally, the resume() callback re-enables autosuspend, ensuring
	1469	+ * the I2C controller remains available until the system enters
	1470	+ * suspend_noirq() and from resume_noirq().
	1471	+ */
	1472	+ return pm_runtime_resume_and_get(dev);
	1473	+}
	1474	+
	1475	+static int lpi2c_resume(struct device *dev)
	1476	+{
	1477	+ pm_runtime_mark_last_busy(dev);
	1478	+ pm_runtime_put_autosuspend(dev);
	1479	+
	1480	+ return 0;
	1481	+}
	1482	+
697	1483	static const struct dev_pm_ops lpi2c_pm_ops = {
698		− SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
699		− pm_runtime_force_resume)
	1484	+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(lpi2c_suspend_noirq,
	1485	+ lpi2c_resume_noirq)
	1486	+ SYSTEM_SLEEP_PM_OPS(lpi2c_suspend, lpi2c_resume)
700	1487	SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
701	1488	lpi2c_runtime_resume, NULL)
702	1489	};

drivers/i2c/busses/i2c-imx.c+82−17

@@ -397,17 +397,16 @@ static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) · 396 unmodified lines
397	397	}
398	398
399	399	/* Functions for DMA support */
400		−static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
401		− dma_addr_t phy_addr)
	400	+static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr)
402	401	{
403	402	struct imx_i2c_dma *dma;
404	403	struct dma_slave_config dma_sconfig;
405		− struct device *dev = &i2c_imx->adapter.dev;
	404	+ struct device *dev = i2c_imx->adapter.dev.parent;
406	405	int ret;
407	406
408	407	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
409	408	if (!dma)
410		− return;
	409	+ return -ENOMEM;
411	410
412	411	dma->chan_tx = dma_request_chan(dev, "tx");
413	412	if (IS_ERR(dma->chan_tx)) {
@@ -452,7 +451,7 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, · 38 unmodified lines
452	451	dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
453	452	dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
454	453
455		− return;
	454	+ return 0;
456	455
457	456	fail_rx:
458	457	dma_release_channel(dma->chan_rx);
@@ -460,6 +459,8 @@ fail_tx: · 1 unmodified line
460	459	dma_release_channel(dma->chan_tx);
461	460	fail_al:
462	461	devm_kfree(dev, dma);
	462	+
	463	+ return ret;
463	464	}
464	465
465	466	static void i2c_imx_dma_callback(void *arg)
@@ -621,8 +622,8 @@ static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) · 155 unmodified lines
621	622	return 0;
622	623	}
623	624
624		−static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
625		− unsigned int i2c_clk_rate)
	625	+static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
	626	+ unsigned int i2c_clk_rate)
626	627	{
627	628	struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
628	629	unsigned int div;
@@ -637,7 +638,11 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, · 8 unmodified lines
637	638
638	639	/* Divider value calculation */
639	640	if (i2c_imx->cur_clk == i2c_clk_rate)
640		− return;
	641	+ return 0;
	642	+
	643	+ /* Keep the denominator of the following program always NOT equal to 0. */
	644	+ if (!(i2c_clk_rate / 2))
	645	+ return -EINVAL;
641	646
642	647	i2c_imx->cur_clk = i2c_clk_rate;
643	648
@@ -668,6 +673,8 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, · 24 unmodified lines
668	673	dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
669	674	i2c_clk_div[i].val, i2c_clk_div[i].div);
670	675	#endif
	676	+
	677	+ return 0;
671	678	}
672	679
673	680	static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
@@ -677,11 +684,12 @@ static int i2c_imx_clk_notifier_call(struct notifier_block *nb, · 3 unmodified lines
677	684	struct imx_i2c_struct *i2c_imx = container_of(nb,
678	685	struct imx_i2c_struct,
679	686	clk_change_nb);
	687	+ int ret = 0;
680	688
681	689	if (action & POST_RATE_CHANGE)
682		− i2c_imx_set_clk(i2c_imx, ndata->new_rate);
	690	+ ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate);
683	691
684		− return NOTIFY_OK;
	692	+ return notifier_from_errno(ret);
685	693	}
686	694
687	695	static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
@@ -1760,7 +1768,8 @@ static int i2c_imx_probe(struct platform_device *pdev) · 1072 unmodified lines
1760	1768	goto rpm_disable;
1761	1769
1762	1770	/* Request IRQ */
1763		− ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx);
	1771	+ ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED \| IRQF_NO_SUSPEND,
	1772	+ pdev->name, i2c_imx);
1764	1773	if (ret) {
1765	1774	dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1766	1775	goto rpm_disable;
@@ -1780,7 +1789,11 @@ static int i2c_imx_probe(struct platform_device *pdev) · 13 unmodified lines
1780	1789	i2c_imx->bitrate = pdata->bitrate;
1781	1790	i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1782	1791	clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1783		− i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
	1792	+ ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
	1793	+ if (ret < 0) {
	1794	+ dev_err(&pdev->dev, "can't get I2C clock\n");
	1795	+ goto clk_notifier_unregister;
	1796	+ }
1784	1797
1785	1798	i2c_imx_reset_regs(i2c_imx);
1786	1799
@@ -1790,6 +1803,22 @@ static int i2c_imx_probe(struct platform_device *pdev) · 3 unmodified lines
1790	1803	if (ret == -EPROBE_DEFER)
1791	1804	goto clk_notifier_unregister;
1792	1805
	1806	+ /*
	1807	+ * DMA mode should be optional for I2C, when encountering DMA errors,
	1808	+ * no need to exit I2C probe. Only print warning to show DMA error and
	1809	+ * use PIO mode directly to ensure I2C bus available as much as possible.
	1810	+ */
	1811	+ ret = i2c_imx_dma_request(i2c_imx, phy_addr);
	1812	+ if (ret) {
	1813	+ if (ret == -EPROBE_DEFER)
	1814	+ goto clk_notifier_unregister;
	1815	+ else if (ret == -ENODEV)
	1816	+ dev_dbg(&pdev->dev, "Only use PIO mode\n");
	1817	+ else
	1818	+ dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n",
	1819	+ ERR_PTR(ret));
	1820	+ }
	1821	+
1793	1822	/* Add I2C adapter */
1794	1823	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1795	1824	if (ret < 0)
@@ -1804,9 +1833,6 @@ static int i2c_imx_probe(struct platform_device *pdev) · 8 unmodified lines
1804	1833	i2c_imx->adapter.name);
1805	1834	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1806	1835
1807		− /* Init DMA config if supported */
1808		− i2c_imx_dma_request(i2c_imx, phy_addr);
1809		−
1810	1836	return 0; /* Return OK */
1811	1837
1812	1838	clk_notifier_unregister:
@@ -1858,8 +1884,7 @@ static int i2c_imx_runtime_suspend(struct device *dev) · 45 unmodified lines
1858	1884	struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1859	1885
1860	1886	clk_disable(i2c_imx->clk);
1861		−
1862		− return 0;
	1887	+ return pinctrl_pm_select_sleep_state(dev);
1863	1888	}
1864	1889
1865	1890	static int i2c_imx_runtime_resume(struct device *dev)
@@ -1867,6 +1892,10 @@ static int i2c_imx_runtime_resume(struct device *dev) · 1 unmodified line
1867	1892	struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1868	1893	int ret;
1869	1894
	1895	+ ret = pinctrl_pm_select_default_state(dev);
	1896	+ if (ret)
	1897	+ return ret;
	1898	+
1870	1899	ret = clk_enable(i2c_imx->clk);
1871	1900	if (ret)
1872	1901	dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
@@ -1874,7 +1903,43 @@ static int i2c_imx_runtime_resume(struct device *dev) · 1 unmodified line
1874	1903	return ret;
1875	1904	}
1876	1905
	1906	+static int i2c_imx_suspend(struct device *dev)
	1907	+{
	1908	+ /*
	1909	+ * Some I2C devices may need the I2C controller to remain active
	1910	+ * during resume_noirq() or suspend_noirq(). If the controller is
	1911	+ * autosuspended, there is no way to wake it up once runtime PM is
	1912	+ * disabled (in suspend_late()).
	1913	+ *
	1914	+ * During system resume, the I2C controller will be available only
	1915	+ * after runtime PM is re-enabled (in resume_early()). However, this
	1916	+ * may be too late for some devices.
	1917	+ *
	1918	+ * Wake up the controller in the suspend() callback while runtime PM
	1919	+ * is still enabled. The I2C controller will remain available until
	1920	+ * the suspend_noirq() callback (pm_runtime_force_suspend()) is
	1921	+ * called. During resume, the I2C controller can be restored by the
	1922	+ * resume_noirq() callback (pm_runtime_force_resume()).
	1923	+ *
	1924	+ * Finally, the resume() callback re-enables autosuspend, ensuring
	1925	+ * the I2C controller remains available until the system enters
	1926	+ * suspend_noirq() and from resume_noirq().
	1927	+ */
	1928	+ return pm_runtime_resume_and_get(dev);
	1929	+}
	1930	+
	1931	+static int i2c_imx_resume(struct device *dev)
	1932	+{
	1933	+ pm_runtime_mark_last_busy(dev);
	1934	+ pm_runtime_put_autosuspend(dev);
	1935	+
	1936	+ return 0;
	1937	+}
	1938	+
1877	1939	static const struct dev_pm_ops i2c_imx_pm_ops = {
	1940	+ NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	1941	+ pm_runtime_force_resume)
	1942	+ SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume)
1878	1943	RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL)
1879	1944	};
1880	1945

drivers/i2c/busses/i2c-isch.c+3−3

@@ -291,9 +291,9 @@ static int smbus_sch_probe(struct platform_device *pdev) · 290 unmodified lines
291	291
292	292	/* Set up the sysfs linkage to our parent device */
293	293	priv->adapter.dev.parent = dev;
294		− priv->adapter.owner = THIS_MODULE,
295		− priv->adapter.class = I2C_CLASS_HWMON,
296		− priv->adapter.algo = &smbus_algorithm,
	294	+ priv->adapter.owner = THIS_MODULE;
	295	+ priv->adapter.class = I2C_CLASS_HWMON;
	296	+ priv->adapter.algo = &smbus_algorithm;
297	297
298	298	snprintf(priv->adapter.name, sizeof(priv->adapter.name),
299	299	"SMBus SCH adapter at %04x", (unsigned short)res->start);

drivers/i2c/busses/i2c-keba.c+2−6

@@ -464,12 +464,8 @@ static void ki2c_unregister_devices(struct ki2c *ki2c) · 463 unmodified lines
464	464	{
465	465	int i;
466	466
467		− for (i = 0; i < ki2c->client_size; i++) {
468		− struct i2c_client *client = ki2c->client[i];
469		−
470		− if (client)
471		− i2c_unregister_device(client);
472		− }
	467	+ for (i = 0; i < ki2c->client_size; i++)
	468	+ i2c_unregister_device(ki2c->client[i]);
473	469	}
474	470
475	471	static int ki2c_register_devices(struct ki2c *ki2c)

drivers/i2c/busses/i2c-npcm7xx.c+326−101

@@ -263,6 +263,265 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { · 262 unmodified lines
263	263	#define I2C_FREQ_MIN_HZ 10000
264	264	#define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
265	265
	266	+struct smb_timing_t {
	267	+ u32 core_clk;
	268	+ u8 hldt;
	269	+ u8 dbcnt;
	270	+ u16 sclfrq;
	271	+ u8 scllt;
	272	+ u8 sclht;
	273	+ bool fast_mode;
	274	+};
	275	+
	276	+static struct smb_timing_t smb_timing_100khz[] = {
	277	+ {
	278	+ .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x4,
	279	+ .sclfrq = 0xFB, .scllt = 0x0, .sclht = 0x0,
	280	+ .fast_mode = false,
	281	+ },
	282	+ {
	283	+ .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x1,
	284	+ .sclfrq = 0x9D, .scllt = 0x0, .sclht = 0x0,
	285	+ .fast_mode = false,
	286	+ },
	287	+ {
	288	+ .core_clk = 50000000, .hldt = 0x2A, .dbcnt = 0x1,
	289	+ .sclfrq = 0x7E, .scllt = 0x0, .sclht = 0x0,
	290	+ .fast_mode = false,
	291	+ },
	292	+ {
	293	+ .core_clk = 48000000, .hldt = 0x2A, .dbcnt = 0x1,
	294	+ .sclfrq = 0x79, .scllt = 0x0, .sclht = 0x0,
	295	+ .fast_mode = false,
	296	+ },
	297	+ {
	298	+ .core_clk = 40000000, .hldt = 0x2A, .dbcnt = 0x1,
	299	+ .sclfrq = 0x65, .scllt = 0x0, .sclht = 0x0,
	300	+ .fast_mode = false,
	301	+ },
	302	+ {
	303	+ .core_clk = 30000000, .hldt = 0x2A, .dbcnt = 0x1,
	304	+ .sclfrq = 0x4C, .scllt = 0x0, .sclht = 0x0,
	305	+ .fast_mode = false,
	306	+ },
	307	+ {
	308	+ .core_clk = 29000000, .hldt = 0x2A, .dbcnt = 0x1,
	309	+ .sclfrq = 0x49, .scllt = 0x0, .sclht = 0x0,
	310	+ .fast_mode = false,
	311	+ },
	312	+ {
	313	+ .core_clk = 26000000, .hldt = 0x2A, .dbcnt = 0x1,
	314	+ .sclfrq = 0x42, .scllt = 0x0, .sclht = 0x0,
	315	+ .fast_mode = false,
	316	+ },
	317	+ {
	318	+ .core_clk = 25000000, .hldt = 0x2A, .dbcnt = 0x1,
	319	+ .sclfrq = 0x3F, .scllt = 0x0, .sclht = 0x0,
	320	+ .fast_mode = false,
	321	+ },
	322	+ {
	323	+ .core_clk = 24000000, .hldt = 0x2A, .dbcnt = 0x1,
	324	+ .sclfrq = 0x3D, .scllt = 0x0, .sclht = 0x0,
	325	+ .fast_mode = false,
	326	+ },
	327	+ {
	328	+ .core_clk = 20000000, .hldt = 0x2A, .dbcnt = 0x1,
	329	+ .sclfrq = 0x33, .scllt = 0x0, .sclht = 0x0,
	330	+ .fast_mode = false,
	331	+ },
	332	+ {
	333	+ .core_clk = 16180000, .hldt = 0x2A, .dbcnt = 0x1,
	334	+ .sclfrq = 0x29, .scllt = 0x0, .sclht = 0x0,
	335	+ .fast_mode = false,
	336	+ },
	337	+ {
	338	+ .core_clk = 15000000, .hldt = 0x23, .dbcnt = 0x1,
	339	+ .sclfrq = 0x26, .scllt = 0x0, .sclht = 0x0,
	340	+ .fast_mode = false,
	341	+ },
	342	+ {
	343	+ .core_clk = 13000000, .hldt = 0x1D, .dbcnt = 0x1,
	344	+ .sclfrq = 0x21, .scllt = 0x0, .sclht = 0x0,
	345	+ .fast_mode = false,
	346	+ },
	347	+ {
	348	+ .core_clk = 12000000, .hldt = 0x1B, .dbcnt = 0x1,
	349	+ .sclfrq = 0x1F, .scllt = 0x0, .sclht = 0x0,
	350	+ .fast_mode = false,
	351	+ },
	352	+ {
	353	+ .core_clk = 10000000, .hldt = 0x18, .dbcnt = 0x1,
	354	+ .sclfrq = 0x1A, .scllt = 0x0, .sclht = 0x0,
	355	+ .fast_mode = false,
	356	+ },
	357	+ {
	358	+ .core_clk = 9000000, .hldt = 0x16, .dbcnt = 0x1,
	359	+ .sclfrq = 0x17, .scllt = 0x0, .sclht = 0x0,
	360	+ .fast_mode = false,
	361	+ },
	362	+ {
	363	+ .core_clk = 8090000, .hldt = 0x14, .dbcnt = 0x1,
	364	+ .sclfrq = 0x15, .scllt = 0x0, .sclht = 0x0,
	365	+ .fast_mode = false,
	366	+ },
	367	+ {
	368	+ .core_clk = 7500000, .hldt = 0x7, .dbcnt = 0x1,
	369	+ .sclfrq = 0x13, .scllt = 0x0, .sclht = 0x0,
	370	+ .fast_mode = false,
	371	+ },
	372	+ {
	373	+ .core_clk = 6500000, .hldt = 0xE, .dbcnt = 0x1,
	374	+ .sclfrq = 0x11, .scllt = 0x0, .sclht = 0x0,
	375	+ .fast_mode = false,
	376	+ },
	377	+ {
	378	+ .core_clk = 4000000, .hldt = 0x9, .dbcnt = 0x1,
	379	+ .sclfrq = 0xB, .scllt = 0x0, .sclht = 0x0,
	380	+ .fast_mode = false,
	381	+ },
	382	+};
	383	+
	384	+static struct smb_timing_t smb_timing_400khz[] = {
	385	+ {
	386	+ .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x3,
	387	+ .sclfrq = 0x0, .scllt = 0x47, .sclht = 0x35,
	388	+ .fast_mode = true,
	389	+ },
	390	+ {
	391	+ .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x2,
	392	+ .sclfrq = 0x0, .scllt = 0x2C, .sclht = 0x22,
	393	+ .fast_mode = true,
	394	+ },
	395	+ {
	396	+ .core_clk = 50000000, .hldt = 0x21, .dbcnt = 0x1,
	397	+ .sclfrq = 0x0, .scllt = 0x24, .sclht = 0x1B,
	398	+ .fast_mode = true,
	399	+ },
	400	+ {
	401	+ .core_clk = 48000000, .hldt = 0x1E, .dbcnt = 0x1,
	402	+ .sclfrq = 0x0, .scllt = 0x24, .sclht = 0x19,
	403	+ .fast_mode = true,
	404	+ },
	405	+ {
	406	+ .core_clk = 40000000, .hldt = 0x1B, .dbcnt = 0x1,
	407	+ .sclfrq = 0x0, .scllt = 0x1E, .sclht = 0x14,
	408	+ .fast_mode = true,
	409	+ },
	410	+ {
	411	+ .core_clk = 33000000, .hldt = 0x15, .dbcnt = 0x1,
	412	+ .sclfrq = 0x0, .scllt = 0x19, .sclht = 0x11,
	413	+ .fast_mode = true,
	414	+ },
	415	+ {
	416	+ .core_clk = 30000000, .hldt = 0x15, .dbcnt = 0x1,
	417	+ .sclfrq = 0x0, .scllt = 0x19, .sclht = 0xD,
	418	+ .fast_mode = true,
	419	+ },
	420	+ {
	421	+ .core_clk = 29000000, .hldt = 0x11, .dbcnt = 0x1,
	422	+ .sclfrq = 0x0, .scllt = 0x15, .sclht = 0x10,
	423	+ .fast_mode = true,
	424	+ },
	425	+ {
	426	+ .core_clk = 26000000, .hldt = 0x10, .dbcnt = 0x1,
	427	+ .sclfrq = 0x0, .scllt = 0x13, .sclht = 0xE,
	428	+ .fast_mode = true,
	429	+ },
	430	+ {
	431	+ .core_clk = 25000000, .hldt = 0xF, .dbcnt = 0x1,
	432	+ .sclfrq = 0x0, .scllt = 0x13, .sclht = 0xD,
	433	+ .fast_mode = true,
	434	+ },
	435	+ {
	436	+ .core_clk = 24000000, .hldt = 0xD, .dbcnt = 0x1,
	437	+ .sclfrq = 0x0, .scllt = 0x12, .sclht = 0xD,
	438	+ .fast_mode = true,
	439	+ },
	440	+ {
	441	+ .core_clk = 20000000, .hldt = 0xB, .dbcnt = 0x1,
	442	+ .sclfrq = 0x0, .scllt = 0xF, .sclht = 0xA,
	443	+ .fast_mode = true,
	444	+ },
	445	+ {
	446	+ .core_clk = 16180000, .hldt = 0xA, .dbcnt = 0x1,
	447	+ .sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9,
	448	+ .fast_mode = true,
	449	+ },
	450	+ {
	451	+ .core_clk = 15000000, .hldt = 0x9, .dbcnt = 0x1,
	452	+ .sclfrq = 0x0, .scllt = 0xB, .sclht = 0x8,
	453	+ .fast_mode = true,
	454	+ },
	455	+ {
	456	+ .core_clk = 13000000, .hldt = 0x7, .dbcnt = 0x1,
	457	+ .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7,
	458	+ .fast_mode = true,
	459	+ },
	460	+ {
	461	+ .core_clk = 12000000, .hldt = 0x7, .dbcnt = 0x1,
	462	+ .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x6,
	463	+ .fast_mode = true,
	464	+ },
	465	+ {
	466	+ .core_clk = 10000000, .hldt = 0x6, .dbcnt = 0x1,
	467	+ .sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5,
	468	+ .fast_mode = true,
	469	+ },
	470	+};
	471	+
	472	+static struct smb_timing_t smb_timing_1000khz[] = {
	473	+ {
	474	+ .core_clk = 100000000, .hldt = 0x15, .dbcnt = 0x4,
	475	+ .sclfrq = 0x0, .scllt = 0x1C, .sclht = 0x15,
	476	+ .fast_mode = true,
	477	+ },
	478	+ {
	479	+ .core_clk = 62500000, .hldt = 0xF, .dbcnt = 0x3,
	480	+ .sclfrq = 0x0, .scllt = 0x11, .sclht = 0xE,
	481	+ .fast_mode = true,
	482	+ },
	483	+ {
	484	+ .core_clk = 50000000, .hldt = 0xA, .dbcnt = 0x2,
	485	+ .sclfrq = 0x0, .scllt = 0xE, .sclht = 0xB,
	486	+ .fast_mode = true,
	487	+ },
	488	+ {
	489	+ .core_clk = 48000000, .hldt = 0x9, .dbcnt = 0x2,
	490	+ .sclfrq = 0x0, .scllt = 0xD, .sclht = 0xB,
	491	+ .fast_mode = true,
	492	+ },
	493	+ {
	494	+ .core_clk = 41000000, .hldt = 0x9, .dbcnt = 0x2,
	495	+ .sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9,
	496	+ .fast_mode = true,
	497	+ },
	498	+ {
	499	+ .core_clk = 40000000, .hldt = 0x8, .dbcnt = 0x2,
	500	+ .sclfrq = 0x0, .scllt = 0xB, .sclht = 0x9,
	501	+ .fast_mode = true,
	502	+ },
	503	+ {
	504	+ .core_clk = 33000000, .hldt = 0x7, .dbcnt = 0x1,
	505	+ .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7,
	506	+ .fast_mode = true,
	507	+ },
	508	+ {
	509	+ .core_clk = 25000000, .hldt = 0x4, .dbcnt = 0x1,
	510	+ .sclfrq = 0x0, .scllt = 0x7, .sclht = 0x6,
	511	+ .fast_mode = true,
	512	+ },
	513	+ {
	514	+ .core_clk = 24000000, .hldt = 0x7, .dbcnt = 0x1,
	515	+ .sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5,
	516	+ .fast_mode = true,
	517	+ },
	518	+ {
	519	+ .core_clk = 20000000, .hldt = 0x4, .dbcnt = 0x1,
	520	+ .sclfrq = 0x0, .scllt = 0x6, .sclht = 0x4,
	521	+ .fast_mode = true,
	522	+ },
	523	+};
	524	+
266	525	struct npcm_i2c_data {
267	526	u8 fifo_size;
268	527	u32 segctl_init_val;
@@ -1666,6 +1925,12 @@ static int npcm_i2c_int_master_handler(struct npcm_i2c *bus) · 1397 unmodified lines
1666	1925	(FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1667	1926	ioread8(bus->reg + NPCM_I2CCST3)))) {
1668	1927	npcm_i2c_irq_handle_eob(bus);
	1928	+#if IS_ENABLED(CONFIG_I2C_SLAVE)
	1929	+ /* reenable slave if it was enabled */
	1930	+ if (bus->slave)
	1931	+ iowrite8(bus->slave->addr \| NPCM_I2CADDR_SAEN,
	1932	+ bus->reg + NPCM_I2CADDR1);
	1933	+#endif
1669	1934	return 0;
1670	1935	}
1671	1936
@@ -1805,102 +2070,45 @@ static void npcm_i2c_recovery_init(struct i2c_adapter *_adap) · 133 unmodified lines
1805	2070	*/
1806	2071	static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1807	2072	{
1808		− u32 k1 = 0;
1809		− u32 k2 = 0;
1810		− u8 dbnct = 0;
1811		− u32 sclfrq = 0;
1812		− u8 hldt = 7;
	2073	+ struct smb_timing_t *smb_timing;
	2074	+ u8 scl_table_cnt = 0, table_size = 0;
1813	2075	u8 fast_mode = 0;
1814		− u32 src_clk_khz;
1815		− u32 bus_freq_khz;
1816	2076
1817		− src_clk_khz = bus->apb_clk / 1000;
1818		− bus_freq_khz = bus_freq_hz / 1000;
1819	2077	bus->bus_freq = bus_freq_hz;
1820	2078
1821		− /* 100KHz and below: */
1822		− if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1823		− sclfrq = src_clk_khz / (bus_freq_khz * 4);
1824		−
1825		− if (sclfrq < SCLFRQ_MIN \|\| sclfrq > SCLFRQ_MAX)
1826		− return -EDOM;
1827		−
1828		− if (src_clk_khz >= 40000)
1829		− hldt = 17;
1830		− else if (src_clk_khz >= 12500)
1831		− hldt = 15;
1832		− else
1833		− hldt = 7;
1834		− }
1835		−
1836		− /* 400KHz: */
1837		− else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1838		− sclfrq = 0;
	2079	+ switch (bus_freq_hz) {
	2080	+ case I2C_MAX_STANDARD_MODE_FREQ:
	2081	+ smb_timing = smb_timing_100khz;
	2082	+ table_size = ARRAY_SIZE(smb_timing_100khz);
	2083	+ break;
	2084	+ case I2C_MAX_FAST_MODE_FREQ:
	2085	+ smb_timing = smb_timing_400khz;
	2086	+ table_size = ARRAY_SIZE(smb_timing_400khz);
1839	2087	fast_mode = I2CCTL3_400K_MODE;
1840		−
1841		− if (src_clk_khz < 7500)
1842		− /* 400KHZ cannot be supported for core clock < 7.5MHz */
1843		− return -EDOM;
1844		−
1845		− else if (src_clk_khz >= 50000) {
1846		− k1 = 80;
1847		− k2 = 48;
1848		− hldt = 12;
1849		− dbnct = 7;
1850		− }
1851		−
1852		− /* Master or Slave with frequency > 25MHz */
1853		− else if (src_clk_khz > 25000) {
1854		− hldt = clk_coef(src_clk_khz, 300) + 7;
1855		− k1 = clk_coef(src_clk_khz, 1600);
1856		− k2 = clk_coef(src_clk_khz, 900);
1857		− }
1858		− }
1859		−
1860		− /* 1MHz: */
1861		− else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1862		− sclfrq = 0;
	2088	+ break;
	2089	+ case I2C_MAX_FAST_MODE_PLUS_FREQ:
	2090	+ smb_timing = smb_timing_1000khz;
	2091	+ table_size = ARRAY_SIZE(smb_timing_1000khz);
1863	2092	fast_mode = I2CCTL3_400K_MODE;
1864		−
1865		− /* 1MHZ cannot be supported for core clock < 24 MHz */
1866		− if (src_clk_khz < 24000)
1867		− return -EDOM;
1868		−
1869		− k1 = clk_coef(src_clk_khz, 620);
1870		− k2 = clk_coef(src_clk_khz, 380);
1871		−
1872		− /* Core clk > 40 MHz */
1873		− if (src_clk_khz > 40000) {
1874		− /*
1875		− * Set HLDT:
1876		− * SDA hold time: (HLDT-7) * T(CLK) >= 120
1877		− * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1878		− */
1879		− hldt = clk_coef(src_clk_khz, 120) + 7;
1880		− } else {
1881		− hldt = 7;
1882		− dbnct = 2;
1883		− }
	2093	+ break;
	2094	+ default:
	2095	+ return -EINVAL;
1884	2096	}
1885	2097
1886		− /* Frequency larger than 1 MHz is not supported */
1887		− else
1888		− return -EINVAL;
	2098	+ for (scl_table_cnt = 0; scl_table_cnt < table_size; scl_table_cnt++)
	2099	+ if (bus->apb_clk >= smb_timing[scl_table_cnt].core_clk)
	2100	+ break;
1889	2101
1890		− if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1891		− k1 = round_up(k1, 2);
1892		− k2 = round_up(k2 + 1, 2);
1893		− if (k1 < SCLFRQ_MIN \|\| k1 > SCLFRQ_MAX \|\|
1894		− k2 < SCLFRQ_MIN \|\| k2 > SCLFRQ_MAX)
1895		− return -EDOM;
1896		− }
	2102	+ if (scl_table_cnt == table_size)
	2103	+ return -EINVAL;
1897	2104
1898	2105	/* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1899		− iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
	2106	+ iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq & 0x7F),
1900	2107	bus->reg + NPCM_I2CCTL2);
1901	2108
1902	2109	/* bits [8:7] are in I2CCTL3 reg */
1903		− iowrite8(fast_mode \| FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
	2110	+ iowrite8(FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_cnt].sclfrq >> 7) & 0x3) \|
	2111	+ fast_mode,
1904	2112	bus->reg + NPCM_I2CCTL3);
1905	2113
1906	2114	/* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
@@ -1912,13 +2120,13 @@ static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) · 5 unmodified lines
1912	2120	* k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2
1913	2121	* k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1914	2122	*/
1915		− iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1916		− iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
	2123	+ iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT);
	2124	+ iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT);
1917	2125
1918		− iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
	2126	+ iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5);
1919	2127	}
1920	2128
1921		− iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
	2129	+ iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4);
1922	2130
1923	2131	/* Return to Bank 1, and stay there by default: */
1924	2132	npcm_i2c_select_bank(bus, I2C_BANK_1);
@@ -2035,7 +2243,7 @@ static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) · 110 unmodified lines
2035	2243	}
2036	2244
2037	2245	static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2038		− u8 slave_addr, u16 nwrite, u16 nread,
	2246	+ u16 nwrite, u16 nread,
2039	2247	u8 write_data, u8 read_data,
2040	2248	bool use_PEC, bool use_read_block)
2041	2249	{
@@ -2043,7 +2251,6 @@ static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus, · 1 unmodified line
2043	2251	bus->cmd_err = -EBUSY;
2044	2252	return false;
2045	2253	}
2046		− bus->dest_addr = slave_addr << 1;
2047	2254	bus->wr_buf = write_data;
2048	2255	bus->wr_size = nwrite;
2049	2256	bus->wr_ind = 0;
@@ -2086,7 +2293,6 @@ static int npcm_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs, · 36 unmodified lines
2086	2293	unsigned long time_left, flags;
2087	2294	u16 nwrite, nread;
2088	2295	u8 write_data, read_data;
2089		− u8 slave_addr;
2090	2296	unsigned long timeout;
2091	2297	bool read_block = false;
2092	2298	bool read_PEC = false;
@@ -2099,7 +2305,6 @@ static int npcm_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs, · 6 unmodified lines
2099	2305	}
2100	2306
2101	2307	msg0 = &msgs[0];
2102		− slave_addr = msg0->addr;
2103	2308	if (msg0->flags & I2C_M_RD) { /* read */
2104	2309	nwrite = 0;
2105	2310	write_data = NULL;
@@ -2132,19 +2337,12 @@ static int npcm_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs, · 26 unmodified lines
2132	2337	}
2133	2338	}
2134	2339
2135		− /*
2136		− * Adaptive TimeOut: estimated time in usec + 100% margin:
2137		− * 2: double the timeout for clock stretching case
2138		− * 9: bits per transaction (including the ack/nack)
2139		− */
2140		− timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2141		− timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2142	2340	if (nwrite >= 32 * 1024 \|\| nread >= 32 * 1024) {
2143	2341	dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2144	2342	return -EINVAL;
2145	2343	}
2146	2344
2147		− time_left = jiffies + timeout + 1;
	2345	+ time_left = jiffies + bus->adap.timeout / bus->adap.retries + 1;
2148	2346	do {
2149	2347	/*
2150	2348	* we must clear slave address immediately when the bus is not
@@ -2162,6 +2360,21 @@ static int npcm_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs, · 11 unmodified lines
2162	2360
2163	2361	} while (time_is_after_jiffies(time_left) && bus_busy);
2164	2362
	2363	+ /*
	2364	+ * Store the address early in a global position to ensure it is
	2365	+ * accessible for a potential call to i2c_recover_bus().
	2366	+ *
	2367	+ * Since the transfer might be a read operation, remove the I2C_M_RD flag
	2368	+ * from the bus->dest_addr for the i2c_recover_bus() call later.
	2369	+ *
	2370	+ * The i2c_recover_bus() uses the address in a write direction to recover
	2371	+ * the i2c bus if some error condition occurs.
	2372	+ *
	2373	+ * Remove the I2C_M_RD flag from the address since npcm_i2c_master_start_xmit()
	2374	+ * handles the read/write operation internally.
	2375	+ */
	2376	+ bus->dest_addr = i2c_8bit_addr_from_msg(msg0) & ~I2C_M_RD;
	2377	+
2165	2378	/*
2166	2379	* Check the BER (bus error) state, when ber_state is true, it means that the module
2167	2380	* detects the bus error which is caused by some factor like that the electricity
@@ -2179,7 +2392,6 @@ static int npcm_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs, · 11 unmodified lines
2179	2392	}
2180	2393
2181	2394	npcm_i2c_init_params(bus);
2182		− bus->dest_addr = slave_addr;
2183	2395	bus->msgs = msgs;
2184	2396	bus->msgs_num = num;
2185	2397	bus->cmd_err = 0;
@@ -2189,9 +2401,17 @@ static int npcm_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs, · 3 unmodified lines
2189	2401
2190	2402	npcm_i2c_int_enable(bus, true);
2191	2403
2192		− if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
	2404	+ if (npcm_i2c_master_start_xmit(bus, nwrite, nread,
2193	2405	write_data, read_data, read_PEC,
2194	2406	read_block)) {
	2407	+ /*
	2408	+ * Adaptive TimeOut: estimated time in usec + 100% margin:
	2409	+ * 2: double the timeout for clock stretching case
	2410	+ * 9: bits per transaction (including the ack/nack)
	2411	+ */
	2412	+ timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
	2413	+ timeout = max_t(unsigned long, bus->adap.timeout / bus->adap.retries,
	2414	+ usecs_to_jiffies(timeout_usec));
2195	2415	time_left = wait_for_completion_timeout(&bus->cmd_complete,
2196	2416	timeout);
2197	2417
@@ -2317,7 +2537,12 @@ static int npcm_i2c_probe_bus(struct platform_device *pdev) · 119 unmodified lines
2317	2537	adap = &bus->adap;
2318	2538	adap->owner = THIS_MODULE;
2319	2539	adap->retries = 3;
2320		− adap->timeout = msecs_to_jiffies(35);
	2540	+ /*
	2541	+ * The users want to connect a lot of masters on the same bus.
	2542	+ * This timeout is used to determine the time it takes to take bus ownership.
	2543	+ * The transactions are very long, so waiting 35ms is not enough.
	2544	+ */
	2545	+ adap->timeout = 2 * HZ;
2321	2546	adap->algo = &npcm_i2c_algo;
2322	2547	adap->quirks = &npcm_i2c_quirks;
2323	2548	adap->algo_data = bus;

drivers/i2c/busses/i2c-qcom-geni.c+27−29

@@ -823,11 +823,9 @@ static int geni_i2c_probe(struct platform_device *pdev) · 822 unmodified lines
823	823	return gi2c->irq;
824	824
825	825	ret = geni_i2c_clk_map_idx(gi2c);
826		− if (ret) {
827		− dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
828		− gi2c->clk_freq_out, ret);
829		− return ret;
830		− }
	826	+ if (ret)
	827	+ return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n",
	828	+ gi2c->clk_freq_out);
831	829
832	830	gi2c->adap.algo = &geni_i2c_algo;
833	831	init_completion(&gi2c->done);
@@ -837,11 +835,10 @@ static int geni_i2c_probe(struct platform_device *pdev) · 3 unmodified lines
837	835	/* Keep interrupts disabled initially to allow for low-power modes */
838	836	ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
839	837	dev_name(dev), gi2c);
840		− if (ret) {
841		− dev_err(dev, "Request_irq failed:%d: err:%d\n",
842		− gi2c->irq, ret);
843		− return ret;
844		− }
	838	+ if (ret)
	839	+ return dev_err_probe(dev, ret,
	840	+ "Request_irq failed: %d\n", gi2c->irq);
	841	+
845	842	i2c_set_adapdata(&gi2c->adap, gi2c);
846	843	gi2c->adap.dev.parent = dev;
847	844	gi2c->adap.dev.of_node = dev->of_node;
@@ -870,16 +867,13 @@ static int geni_i2c_probe(struct platform_device *pdev) · 22 unmodified lines
870	867
871	868	ret = geni_se_resources_on(&gi2c->se);
872	869	if (ret) {
873		− dev_err(dev, "Error turning on resources %d\n", ret);
874		− clk_disable_unprepare(gi2c->core_clk);
875		− return ret;
	870	+ dev_err_probe(dev, ret, "Error turning on resources\n");
	871	+ goto err_clk;
876	872	}
877	873	proto = geni_se_read_proto(&gi2c->se);
878	874	if (proto != GENI_SE_I2C) {
879		− dev_err(dev, "Invalid proto %d\n", proto);
880		− geni_se_resources_off(&gi2c->se);
881		− clk_disable_unprepare(gi2c->core_clk);
882		− return -ENXIO;
	875	+ ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto);
	876	+ goto err_resources;
883	877	}
884	878
885	879	if (desc && desc->no_dma_support)
@@ -891,11 +885,8 @@ static int geni_i2c_probe(struct platform_device *pdev) · 5 unmodified lines
891	885	/* FIFO is disabled, so we can only use GPI DMA */
892	886	gi2c->gpi_mode = true;
893	887	ret = setup_gpi_dma(gi2c);
894		− if (ret) {
895		− geni_se_resources_off(&gi2c->se);
896		− clk_disable_unprepare(gi2c->core_clk);
897		− return dev_err_probe(dev, ret, "Failed to setup GPI DMA mode\n");
898		− }
	888	+ if (ret)
	889	+ goto err_resources;
899	890
900	891	dev_dbg(dev, "Using GPI DMA mode for I2C\n");
901	892	} else {
@@ -907,10 +898,9 @@ static int geni_i2c_probe(struct platform_device *pdev) · 5 unmodified lines
907	898	tx_depth = desc->tx_fifo_depth;
908	899
909	900	if (!tx_depth) {
910		− dev_err(dev, "Invalid TX FIFO depth\n");
911		− geni_se_resources_off(&gi2c->se);
912		− clk_disable_unprepare(gi2c->core_clk);
913		− return -EINVAL;
	901	+ ret = dev_err_probe(dev, -EINVAL,
	902	+ "Invalid TX FIFO depth\n");
	903	+ goto err_resources;
914	904	}
915	905
916	906	gi2c->tx_wm = tx_depth - 1;
@@ -924,7 +914,7 @@ static int geni_i2c_probe(struct platform_device *pdev) · 7 unmodified lines
924	914	clk_disable_unprepare(gi2c->core_clk);
925	915	ret = geni_se_resources_off(&gi2c->se);
926	916	if (ret) {
927		− dev_err(dev, "Error turning off resources %d\n", ret);
	917	+ dev_err_probe(dev, ret, "Error turning off resources\n");
928	918	goto err_dma;
929	919	}
930	920
@@ -940,17 +930,25 @@ static int geni_i2c_probe(struct platform_device *pdev) · 9 unmodified lines
940	930
941	931	ret = i2c_add_adapter(&gi2c->adap);
942	932	if (ret) {
943		− dev_err(dev, "Error adding i2c adapter %d\n", ret);
	933	+ dev_err_probe(dev, ret, "Error adding i2c adapter\n");
944	934	pm_runtime_disable(gi2c->se.dev);
945	935	goto err_dma;
946	936	}
947	937
948	938	dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
949	939
950		− return 0;
	940	+ return ret;
	941	+
	942	+err_resources:
	943	+ geni_se_resources_off(&gi2c->se);
	944	+err_clk:
	945	+ clk_disable_unprepare(gi2c->core_clk);
	946	+
	947	+ return ret;
951	948
952	949	err_dma:
953	950	release_gpi_dma(gi2c);
	951	+
954	952	return ret;
955	953	}
956	954

drivers/i2c/busses/i2c-riic.c+72−62

@@ -34,46 +34,51 @@ · 33 unmodified lines
34	34	* Also check the comments in the interrupt routines for some gory details.
35	35	*/
36	36
	37	+#include <linux/bits.h>
37	38	#include <linux/clk.h>
38	39	#include <linux/completion.h>
39	40	#include <linux/err.h>
40	41	#include <linux/i2c.h>
41	42	#include <linux/interrupt.h>
42	43	#include <linux/io.h>
	44	+#include <linux/iopoll.h>
43	45	#include <linux/module.h>
44	46	#include <linux/of.h>
45	47	#include <linux/platform_device.h>
46	48	#include <linux/pm_runtime.h>
47	49	#include <linux/reset.h>
	50	+#include <linux/time.h>
48	51
49		−#define ICCR1_ICE 0x80
50		−#define ICCR1_IICRST 0x40
51		−#define ICCR1_SOWP 0x10
	52	+#define ICCR1_ICE BIT(7)
	53	+#define ICCR1_IICRST BIT(6)
	54	+#define ICCR1_SOWP BIT(4)
	55	+#define ICCR1_SCLI BIT(1)
	56	+#define ICCR1_SDAI BIT(0)
52	57
53		−#define ICCR2_BBSY 0x80
54		−#define ICCR2_SP 0x08
55		−#define ICCR2_RS 0x04
56		−#define ICCR2_ST 0x02
	58	+#define ICCR2_BBSY BIT(7)
	59	+#define ICCR2_SP BIT(3)
	60	+#define ICCR2_RS BIT(2)
	61	+#define ICCR2_ST BIT(1)
57	62
58		−#define ICMR1_CKS_MASK 0x70
59		−#define ICMR1_BCWP 0x08
	63	+#define ICMR1_CKS_MASK GENMASK(6, 4)
	64	+#define ICMR1_BCWP BIT(3)
60	65	#define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) \| ICMR1_BCWP)
61	66
62		−#define ICMR3_RDRFS 0x20
63		−#define ICMR3_ACKWP 0x10
64		−#define ICMR3_ACKBT 0x08
	67	+#define ICMR3_RDRFS BIT(5)
	68	+#define ICMR3_ACKWP BIT(4)
	69	+#define ICMR3_ACKBT BIT(3)
65	70
66		−#define ICFER_FMPE 0x80
	71	+#define ICFER_FMPE BIT(7)
67	72
68		−#define ICIER_TIE 0x80
69		−#define ICIER_TEIE 0x40
70		−#define ICIER_RIE 0x20
71		−#define ICIER_NAKIE 0x10
72		−#define ICIER_SPIE 0x08
	73	+#define ICIER_TIE BIT(7)
	74	+#define ICIER_TEIE BIT(6)
	75	+#define ICIER_RIE BIT(5)
	76	+#define ICIER_NAKIE BIT(4)
	77	+#define ICIER_SPIE BIT(3)
73	78
74		−#define ICSR2_NACKF 0x10
	79	+#define ICSR2_NACKF BIT(4)
75	80
76		−#define ICBR_RESERVED 0xe0 /* Should be 1 on writes */
	81	+#define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */
77	82
78	83	#define RIIC_INIT_MSG -1
79	84
@@ -134,6 +139,27 @@ static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u · 54 unmodified lines
134	139	riic_writeb(riic, (riic_readb(riic, reg) & ~clear) \| set, reg);
135	140	}
136	141
	142	+static int riic_bus_barrier(struct riic_dev *riic)
	143	+{
	144	+ int ret;
	145	+ u8 val;
	146	+
	147	+ /*
	148	+ * The SDA line can still be low even when BBSY = 0. Therefore, after checking
	149	+ * the BBSY flag, also verify that the SDA and SCL lines are not being held low.
	150	+ */
	151	+ ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val,
	152	+ !(val & ICCR2_BBSY), 10, riic->adapter.timeout);
	153	+ if (ret)
	154	+ return ret;
	155	+
	156	+ if ((riic_readb(riic, RIIC_ICCR1) & (ICCR1_SDAI \| ICCR1_SCLI)) !=
	157	+ (ICCR1_SDAI \| ICCR1_SCLI))
	158	+ return -EBUSY;
	159	+
	160	+ return 0;
	161	+}
	162	+
137	163	static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
138	164	{
139	165	struct riic_dev *riic = i2c_get_adapdata(adap);
@@ -146,13 +172,11 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) · 6 unmodified lines
146	172	if (ret)
147	173	return ret;
148	174
149		− if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {
150		− riic->err = -EBUSY;
	175	+ riic->err = riic_bus_barrier(riic);
	176	+ if (riic->err)
151	177	goto out;
152		− }
153	178
154	179	reinit_completion(&riic->msg_done);
155		− riic->err = 0;
156	180
157	181	riic_writeb(riic, 0, RIIC_ICSR2);
158	182
@@ -312,6 +336,7 @@ static int riic_init_hw(struct riic_dev *riic) · 153 unmodified lines
312	336	{
313	337	int ret;
314	338	unsigned long rate;
	339	+ unsigned long ns_per_tick;
315	340	int total_ticks, cks, brl, brh;
316	341	struct i2c_timings *t = &riic->i2c_t;
317	342	struct device *dev = riic->adapter.dev.parent;
@@ -320,7 +345,7 @@ static int riic_init_hw(struct riic_dev *riic) · 2 unmodified lines
320	345	: I2C_MAX_FAST_MODE_FREQ;
321	346
322	347	if (t->bus_freq_hz > max_freq)
323		− return dev_err_probe(&riic->adapter.dev, -EINVAL,
	348	+ return dev_err_probe(dev, -EINVAL,
324	349	"unsupported bus speed %uHz (%u max)\n",
325	350	t->bus_freq_hz, max_freq);
326	351
@@ -356,11 +381,9 @@ static int riic_init_hw(struct riic_dev *riic) · 29 unmodified lines
356	381	rate /= 2;
357	382	}
358	383
359		− if (brl > (0x1F + 3)) {
360		− dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
361		− (unsigned long)t->bus_freq_hz);
362		− return -EINVAL;
363		− }
	384	+ if (brl > (0x1F + 3))
	385	+ return dev_err_probe(dev, -EINVAL, "invalid speed (%uHz). Too slow.\n",
	386	+ t->bus_freq_hz);
364	387
365	388	brh = total_ticks - brl;
366	389
@@ -377,8 +400,9 @@ static int riic_init_hw(struct riic_dev *riic) · 10 unmodified lines
377	400	* Remove clock ticks for rise and fall times. Convert ns to clock
378	401	* ticks.
379	402	*/
380		− brl -= t->scl_fall_ns / (1000000000 / rate);
381		− brh -= t->scl_rise_ns / (1000000000 / rate);
	403	+ ns_per_tick = NSEC_PER_SEC / rate;
	404	+ brl -= t->scl_fall_ns / ns_per_tick;
	405	+ brh -= t->scl_rise_ns / ns_per_tick;
382	406
383	407	/* Adjust for min register values for when SCLE=1 and NFE=1 */
384	408	if (brl < 1)
@@ -388,8 +412,7 @@ static int riic_init_hw(struct riic_dev *riic) · 3 unmodified lines
388	412
389	413	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
390	414	rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
391		− t->scl_fall_ns / (1000000000 / rate),
392		− t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
	415	+ t->scl_fall_ns / ns_per_tick, t->scl_rise_ns / ns_per_tick, cks, brl, brh);
393	416
394	417	ret = pm_runtime_resume_and_get(dev);
395	418	if (ret)
@@ -416,7 +439,7 @@ static int riic_init_hw(struct riic_dev *riic) · 20 unmodified lines
416	439	return 0;
417	440	}
418	441
419		−static struct riic_irq_desc riic_irqs[] = {
	442	+static const struct riic_irq_desc riic_irqs[] = {
420	443	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
421	444	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
422	445	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
@@ -424,11 +447,6 @@ static struct riic_irq_desc riic_irqs[] = { · 1 unmodified line
424	447	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
425	448	};
426	449
427		−static void riic_reset_control_assert(void *data)
428		−{
429		− reset_control_assert(data);
430		−}
431		−
432	450	static int riic_i2c_probe(struct platform_device *pdev)
433	451	{
434	452	struct device *dev = &pdev->dev;
@@ -445,35 +463,27 @@ static int riic_i2c_probe(struct platform_device *pdev) · 10 unmodified lines
445	463	return PTR_ERR(riic->base);
446	464
447	465	riic->clk = devm_clk_get(dev, NULL);
448		− if (IS_ERR(riic->clk)) {
449		− dev_err(dev, "missing controller clock");
450		− return PTR_ERR(riic->clk);
451		− }
	466	+ if (IS_ERR(riic->clk))
	467	+ return dev_err_probe(dev, PTR_ERR(riic->clk),
	468	+ "missing controller clock");
452	469
453		− riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
	470	+ riic->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
454	471	if (IS_ERR(riic->rstc))
455	472	return dev_err_probe(dev, PTR_ERR(riic->rstc),
456		− "Error: missing reset ctrl\n");
457		−
458		− ret = reset_control_deassert(riic->rstc);
459		− if (ret)
460		− return ret;
461		−
462		− ret = devm_add_action_or_reset(dev, riic_reset_control_assert, riic->rstc);
463		− if (ret)
464		− return ret;
	473	+ "failed to acquire deasserted reset\n");
465	474
466	475	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
467		− ret = platform_get_irq(pdev, riic_irqs[i].res_num);
468		− if (ret < 0)
469		− return ret;
	476	+ int irq;
	477	+
	478	+ irq = platform_get_irq(pdev, riic_irqs[i].res_num);
	479	+ if (irq < 0)
	480	+ return irq;
470	481
471		− ret = devm_request_irq(dev, ret, riic_irqs[i].isr,
	482	+ ret = devm_request_irq(dev, irq, riic_irqs[i].isr,
472	483	0, riic_irqs[i].name, riic);
473		− if (ret) {
474		− dev_err(dev, "failed to request irq %s\n", riic_irqs[i].name);
475		− return ret;
476		− }
	484	+ if (ret)
	485	+ return dev_err_probe(dev, ret, "failed to request irq %s\n",
	486	+ riic_irqs[i].name);
477	487	}
478	488
479	489	riic->info = of_device_get_match_data(dev);

drivers/i2c/busses/i2c-xiic.c+227−54

@@ -30,6 +30,8 @@ · 29 unmodified lines
30	30	#include <linux/of.h>
31	31	#include <linux/clk.h>
32	32	#include <linux/pm_runtime.h>
	33	+#include <linux/iopoll.h>
	34	+#include <linux/spinlock.h>
33	35
34	36	#define DRIVER_NAME "xiic-i2c"
35	37	#define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
@@ -74,6 +76,9 @@ enum i2c_scl_freq { · 38 unmodified lines
74	76	* @smbus_block_read: Flag to handle block read
75	77	* @input_clk: Input clock to I2C controller
76	78	* @i2c_clk: I2C SCL frequency
	79	+ * @atomic: Mode of transfer
	80	+ * @atomic_lock: Lock for atomic transfer mode
	81	+ * @atomic_xfer_state: See STATE_
77	82	*/
78	83	struct xiic_i2c {
79	84	struct device *dev;
@@ -96,6 +101,9 @@ struct xiic_i2c { · 16 unmodified lines
96	101	bool smbus_block_read;
97	102	unsigned long input_clk;
98	103	unsigned int i2c_clk;
	104	+ bool atomic;
	105	+ spinlock_t atomic_lock; /* Lock for atomic transfer mode */
	106	+ enum xilinx_i2c_state atomic_xfer_state;
99	107	};
100	108
101	109	struct xiic_version_data {
@@ -224,6 +232,8 @@ static const struct timing_regs timing_reg_values[] = { · 122 unmodified lines
224	232	#define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
225	233	/* timeout waiting for the controller finish transfers */
226	234	#define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000))
	235	+/* timeout waiting for the controller finish transfers in micro seconds */
	236	+#define XIIC_XFER_TIMEOUT_US 10000000
227	237
228	238	/*
229	239	* The following constant is used for the device global interrupt enable
@@ -238,6 +248,29 @@ static const struct timing_regs timing_reg_values[] = { · 8 unmodified lines
238	248	static int xiic_start_xfer(struct xiic_i2c i2c, struct i2c_msg msgs, int num);
239	249	static void __xiic_start_xfer(struct xiic_i2c *i2c);
240	250
	251	+static int xiic_i2c_runtime_suspend(struct device *dev)
	252	+{
	253	+ struct xiic_i2c *i2c = dev_get_drvdata(dev);
	254	+
	255	+ clk_disable(i2c->clk);
	256	+
	257	+ return 0;
	258	+}
	259	+
	260	+static int xiic_i2c_runtime_resume(struct device *dev)
	261	+{
	262	+ struct xiic_i2c *i2c = dev_get_drvdata(dev);
	263	+ int ret;
	264	+
	265	+ ret = clk_enable(i2c->clk);
	266	+ if (ret) {
	267	+ dev_err(dev, "Cannot enable clock.\n");
	268	+ return ret;
	269	+ }
	270	+
	271	+ return 0;
	272	+}
	273	+
241	274	/*
242	275	* For the register read and write functions, a little-endian and big-endian
243	276	* version are necessary. Endianness is detected during the probe function.
@@ -374,9 +407,10 @@ static int xiic_setclk(struct xiic_i2c *i2c) · 130 unmodified lines
374	407	unsigned int index = 0;
375	408	u32 reg_val;
376	409
377		− dev_dbg(i2c->adap.dev.parent,
378		− "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
379		− __func__, i2c->input_clk, i2c->i2c_clk);
	410	+ if (!i2c->atomic)
	411	+ dev_dbg(i2c->adap.dev.parent,
	412	+ "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
	413	+ __func__, i2c->input_clk, i2c->i2c_clk);
380	414
381	415	/* If not specified in DT, do not configure in SW. Rely only on Vivado design */
382	416	if (!i2c->i2c_clk \|\| !i2c->input_clk)
@@ -467,7 +501,8 @@ static int xiic_reinit(struct xiic_i2c *i2c) · 84 unmodified lines
467	501	return ret;
468	502
469	503	/* Enable interrupts */
470		− xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
	504	+ if (!i2c->atomic)
	505	+ xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
471	506
472	507	xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
473	508
@@ -549,11 +584,12 @@ static void xiic_read_rx(struct xiic_i2c *i2c) · 75 unmodified lines
549	584
550	585	bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
551	586
552		− dev_dbg(i2c->adap.dev.parent,
553		− "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n",
554		− __func__, bytes_in_fifo, xiic_rx_space(i2c),
555		− xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
556		− xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
	587	+ if (!i2c->atomic)
	588	+ dev_dbg(i2c->adap.dev.parent,
	589	+ "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n",
	590	+ __func__, bytes_in_fifo, xiic_rx_space(i2c),
	591	+ xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
	592	+ xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
557	593
558	594	if (bytes_in_fifo > xiic_rx_space(i2c))
559	595	bytes_in_fifo = xiic_rx_space(i2c);
@@ -612,6 +648,26 @@ static void xiic_read_rx(struct xiic_i2c *i2c) · 52 unmodified lines
612	648	}
613	649	}
614	650
	651	+static bool xiic_error_check(struct xiic_i2c *i2c)
	652	+{
	653	+ bool status = false;
	654	+ u32 pend, isr, ier;
	655	+
	656	+ isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
	657	+ ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
	658	+ pend = isr & ier;
	659	+
	660	+ if ((pend & XIIC_INTR_ARB_LOST_MASK) \|\|
	661	+ ((pend & XIIC_INTR_TX_ERROR_MASK) &&
	662	+ !(pend & XIIC_INTR_RX_FULL_MASK))) {
	663	+ xiic_reinit(i2c);
	664	+ status = true;
	665	+ if (i2c->tx_msg \|\| i2c->rx_msg)
	666	+ i2c->atomic_xfer_state = STATE_ERROR;
	667	+ }
	668	+ return status;
	669	+}
	670	+
615	671	static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
616	672	{
617	673	/* return the actual space left in the FIFO */
@@ -625,8 +681,9 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) · 7 unmodified lines
625	681
626	682	len = (len > fifo_space) ? fifo_space : len;
627	683
628		− dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
629		− __func__, len, fifo_space);
	684	+ if (!i2c->atomic)
	685	+ dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
	686	+ __func__, len, fifo_space);
630	687
631	688	while (len--) {
632	689	u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
@@ -649,9 +706,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) · 16 unmodified lines
649	706	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
650	707	~XIIC_CR_MSMS_MASK);
651	708	}
652		− dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
	709	+ if (!i2c->atomic)
	710	+ dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
653	711	}
654	712	xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
	713	+
	714	+ if (i2c->atomic && xiic_error_check(i2c))
	715	+ return;
655	716	}
656	717	}
657	718
@@ -854,22 +915,51 @@ static int xiic_wait_not_busy(struct xiic_i2c *i2c) · 196 unmodified lines
854	915	*/
855	916	err = xiic_bus_busy(i2c);
856	917	while (err && tries--) {
857		− msleep(1);
	918	+ if (i2c->atomic)
	919	+ udelay(1000);
	920	+ else
	921	+ usleep_range(1000, 1100);
858	922	err = xiic_bus_busy(i2c);
859	923	}
860	924
861	925	return err;
862	926	}
863	927
	928	+static void xiic_recv_atomic(struct xiic_i2c *i2c)
	929	+{
	930	+ while (xiic_rx_space(i2c)) {
	931	+ if (xiic_getreg32(i2c, XIIC_IISR_OFFSET) & XIIC_INTR_RX_FULL_MASK) {
	932	+ xiic_read_rx(i2c);
	933	+
	934	+ /* Clear Rx full and Tx error interrupts. */
	935	+ xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK \|
	936	+ XIIC_INTR_TX_ERROR_MASK);
	937	+ }
	938	+ if (xiic_error_check(i2c))
	939	+ return;
	940	+ }
	941	+
	942	+ i2c->rx_msg = NULL;
	943	+ xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK);
	944	+
	945	+ /* send next message if this wasn't the last. */
	946	+ if (i2c->nmsgs > 1) {
	947	+ i2c->nmsgs--;
	948	+ i2c->tx_msg++;
	949	+ __xiic_start_xfer(i2c);
	950	+ }
	951	+}
	952	+
864	953	static void xiic_start_recv(struct xiic_i2c *i2c)
865	954	{
866	955	u16 rx_watermark;
867	956	u8 cr = 0, rfd_set = 0;
868	957	struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
869	958
870		− dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
871		− __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
872		− xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
	959	+ if (!i2c->atomic)
	960	+ dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
	961	+ __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
	962	+ xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
873	963
874	964	/* Disable Tx interrupts */
875	965	xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK \| XIIC_INTR_TX_EMPTY_MASK);
@@ -967,9 +1057,10 @@ static void xiic_start_recv(struct xiic_i2c *i2c) · 91 unmodified lines
967	1057	XIIC_CR_MSMS_MASK)
968	1058	& ~(XIIC_CR_DIR_IS_TX_MASK));
969	1059	}
970		− dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
971		− __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
972		− xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
	1060	+ if (!i2c->atomic)
	1061	+ dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
	1062	+ __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
	1063	+ xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
973	1064	}
974	1065
975	1066	if (i2c->nmsgs == 1)
@@ -979,10 +1070,55 @@ static void xiic_start_recv(struct xiic_i2c *i2c) · 3 unmodified lines
979	1070	/* the message is tx:ed */
980	1071	i2c->tx_pos = msg->len;
981	1072
	1073	+ i2c->prev_msg_tx = false;
	1074	+
982	1075	/* Enable interrupts */
983		− xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
	1076	+ if (!i2c->atomic)
	1077	+ xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
	1078	+ else
	1079	+ xiic_recv_atomic(i2c);
	1080	+}
984	1081
985		− i2c->prev_msg_tx = false;
	1082	+static void xiic_send_rem_atomic(struct xiic_i2c *i2c)
	1083	+{
	1084	+ while (xiic_tx_space(i2c)) {
	1085	+ if (xiic_tx_fifo_space(i2c)) {
	1086	+ u16 data;
	1087	+
	1088	+ data = i2c->tx_msg->buf[i2c->tx_pos];
	1089	+ i2c->tx_pos++;
	1090	+ if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
	1091	+ /* last message in transfer -> STOP */
	1092	+ if (i2c->dynamic) {
	1093	+ data \|= XIIC_TX_DYN_STOP_MASK;
	1094	+ } else {
	1095	+ u8 cr;
	1096	+ int status;
	1097	+
	1098	+ /* Wait till FIFO is empty so STOP is sent last */
	1099	+ status = xiic_wait_tx_empty(i2c);
	1100	+ if (status)
	1101	+ return;
	1102	+
	1103	+ /* Write to CR to stop */
	1104	+ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
	1105	+ xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
	1106	+ ~XIIC_CR_MSMS_MASK);
	1107	+ }
	1108	+ }
	1109	+ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
	1110	+ }
	1111	+ if (xiic_error_check(i2c))
	1112	+ return;
	1113	+ }
	1114	+
	1115	+ if (i2c->nmsgs > 1) {
	1116	+ i2c->nmsgs--;
	1117	+ i2c->tx_msg++;
	1118	+ __xiic_start_xfer(i2c);
	1119	+ } else {
	1120	+ xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
	1121	+ }
986	1122	}
987	1123
988	1124	static void xiic_start_send(struct xiic_i2c *i2c)
@@ -991,11 +1127,13 @@ static void xiic_start_send(struct xiic_i2c *i2c) · 2 unmodified lines
991	1127	u16 data;
992	1128	struct i2c_msg *msg = i2c->tx_msg;
993	1129
994		− dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
995		− __func__, msg, msg->len);
996		− dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
997		− __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
998		− xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
	1130	+ if (!i2c->atomic) {
	1131	+ dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
	1132	+ __func__, msg, msg->len);
	1133	+ dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
	1134	+ __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
	1135	+ xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
	1136	+ }
999	1137
1000	1138	if (i2c->dynamic) {
1001	1139	/* write the address */
@@ -1060,19 +1198,27 @@ static void xiic_start_send(struct xiic_i2c *i2c) · 58 unmodified lines
1060	1198	XIIC_INTR_TX_ERROR_MASK \|
1061	1199	XIIC_INTR_BNB_MASK);
1062	1200	}
	1201	+
1063	1202	i2c->prev_msg_tx = true;
	1203	+
	1204	+ if (i2c->atomic && !i2c->atomic_xfer_state)
	1205	+ xiic_send_rem_atomic(i2c);
1064	1206	}
1065	1207
1066	1208	static void __xiic_start_xfer(struct xiic_i2c *i2c)
1067	1209	{
1068	1210	int fifo_space = xiic_tx_fifo_space(i2c);
1069	1211
1070		− dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1071		− __func__, i2c->tx_msg, fifo_space);
	1212	+ if (!i2c->atomic)
	1213	+ dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
	1214	+ __func__, i2c->tx_msg, fifo_space);
1072	1215
1073	1216	if (!i2c->tx_msg)
1074	1217	return;
1075	1218
	1219	+ if (i2c->atomic && xiic_error_check(i2c))
	1220	+ return;
	1221	+
1076	1222	i2c->rx_pos = 0;
1077	1223	i2c->tx_pos = 0;
1078	1224	i2c->state = STATE_START;
@@ -1089,7 +1235,10 @@ static int xiic_start_xfer(struct xiic_i2c i2c, struct i2c_msg msgs, int num) · 10 unmodified lines
1089	1235	bool broken_read, max_read_len, smbus_blk_read;
1090	1236	int ret, count;
1091	1237
1092		− mutex_lock(&i2c->lock);
	1238	+ if (i2c->atomic)
	1239	+ spin_lock(&i2c->atomic_lock);
	1240	+ else
	1241	+ mutex_lock(&i2c->lock);
1093	1242
1094	1243	if (i2c->tx_msg \|\| i2c->rx_msg) {
1095	1244	dev_err(i2c->adap.dev.parent,
@@ -1098,6 +1247,8 @@ static int xiic_start_xfer(struct xiic_i2c i2c, struct i2c_msg msgs, int num) · 2 unmodified lines
1098	1247	goto out;
1099	1248	}
1100	1249
	1250	+ i2c->atomic_xfer_state = STATE_DONE;
	1251	+
1101	1252	/* In single master mode bus can only be busy, when in use by this
1102	1253	* driver. If the register indicates bus being busy for some reason we
1103	1254	* should ignore it, since bus will never be released and i2c will be
@@ -1124,7 +1275,9 @@ static int xiic_start_xfer(struct xiic_i2c i2c, struct i2c_msg msgs, int num) · 20 unmodified lines
1124	1275	i2c->tx_msg = msgs;
1125	1276	i2c->rx_msg = NULL;
1126	1277	i2c->nmsgs = num;
1127		− init_completion(&i2c->completion);
	1278	+
	1279	+ if (!i2c->atomic)
	1280	+ init_completion(&i2c->completion);
1128	1281
1129	1282	/* Decide standard mode or Dynamic mode */
1130	1283	i2c->dynamic = true;
@@ -1159,7 +1312,10 @@ static int xiic_start_xfer(struct xiic_i2c i2c, struct i2c_msg msgs, int num) · 28 unmodified lines
1159	1312	__xiic_start_xfer(i2c);
1160	1313
1161	1314	out:
1162		− mutex_unlock(&i2c->lock);
	1315	+ if (i2c->atomic)
	1316	+ spin_unlock(&i2c->atomic_lock);
	1317	+ else
	1318	+ mutex_unlock(&i2c->lock);
1163	1319
1164	1320	return ret;
1165	1321	}
@@ -1198,6 +1354,44 @@ out: · 32 unmodified lines
1198	1354	return err;
1199	1355	}
1200	1356
	1357	+static int xiic_xfer_atomic(struct i2c_adapter adap, struct i2c_msg msgs, int num)
	1358	+{
	1359	+ struct xiic_i2c *i2c = i2c_get_adapdata(adap);
	1360	+ u32 status_reg;
	1361	+ int err;
	1362	+
	1363	+ err = xiic_i2c_runtime_resume(i2c->dev);
	1364	+ if (err)
	1365	+ return err;
	1366	+
	1367	+ i2c->atomic = true;
	1368	+ err = xiic_start_xfer(i2c, msgs, num);
	1369	+ if (err < 0)
	1370	+ return err;
	1371	+
	1372	+ err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET,
	1373	+ status_reg, !(status_reg & XIIC_SR_BUS_BUSY_MASK),
	1374	+ 1, XIIC_XFER_TIMEOUT_US);
	1375	+
	1376	+ if (err) /* Timeout */
	1377	+ err = -ETIMEDOUT;
	1378	+
	1379	+ spin_lock(&i2c->atomic_lock);
	1380	+ if (err \|\| i2c->state) {
	1381	+ i2c->tx_msg = NULL;
	1382	+ i2c->rx_msg = NULL;
	1383	+ i2c->nmsgs = 0;
	1384	+ }
	1385	+
	1386	+ err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO;
	1387	+ spin_unlock(&i2c->atomic_lock);
	1388	+
	1389	+ i2c->atomic = false;
	1390	+ xiic_i2c_runtime_suspend(i2c->dev);
	1391	+
	1392	+ return err;
	1393	+}
	1394	+
1201	1395	static u32 xiic_func(struct i2c_adapter *adap)
1202	1396	{
1203	1397	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \| I2C_FUNC_SMBUS_BLOCK_DATA;
@@ -1205,6 +1399,7 @@ static u32 xiic_func(struct i2c_adapter *adap) · 1 unmodified line
1205	1399
1206	1400	static const struct i2c_algorithm xiic_algorithm = {
1207	1401	.master_xfer = xiic_xfer,
	1402	+ .master_xfer_atomic = xiic_xfer_atomic,
1208	1403	.functionality = xiic_func,
1209	1404	};
1210	1405
@@ -1268,6 +1463,7 @@ static int xiic_i2c_probe(struct platform_device *pdev) · 57 unmodified lines
1268	1463	DRIVER_NAME " %s", pdev->name);
1269	1464
1270	1465	mutex_init(&i2c->lock);
	1466	+ spin_lock_init(&i2c->atomic_lock);
1271	1467
1272	1468	i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1273	1469	if (IS_ERR(i2c->clk))
@@ -1365,29 +1561,6 @@ static void xiic_i2c_remove(struct platform_device *pdev) · 91 unmodified lines
1365	1561	pm_runtime_dont_use_autosuspend(&pdev->dev);
1366	1562	}
1367	1563
1368		−static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
1369		−{
1370		− struct xiic_i2c *i2c = dev_get_drvdata(dev);
1371		−
1372		− clk_disable(i2c->clk);
1373		−
1374		− return 0;
1375		−}
1376		−
1377		−static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
1378		−{
1379		− struct xiic_i2c *i2c = dev_get_drvdata(dev);
1380		− int ret;
1381		−
1382		− ret = clk_enable(i2c->clk);
1383		− if (ret) {
1384		− dev_err(dev, "Cannot enable clock.\n");
1385		− return ret;
1386		− }
1387		−
1388		− return 0;
1389		−}
1390		−
1391	1564	static const struct dev_pm_ops xiic_dev_pm_ops = {
1392	1565	SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
1393	1566	xiic_i2c_runtime_resume, NULL)

drivers/i2c/i2c-core-acpi.c+22−0

@@ -355,6 +355,25 @@ static const struct acpi_device_id i2c_acpi_force_400khz_device_ids[] = { · 354 unmodified lines
355	355	{}
356	356	};
357	357
	358	+static const struct acpi_device_id i2c_acpi_force_100khz_device_ids[] = {
	359	+ /*
	360	+ * When a 400KHz freq is used on this model of ELAN touchpad in Linux,
	361	+ * excessive smoothing (similar to when the touchpad's firmware detects
	362	+ * a noisy signal) is sometimes applied. As some devices' (e.g, Lenovo
	363	+ * V15 G4) ACPI tables specify a 400KHz frequency for this device and
	364	+ * some I2C busses (e.g, Designware I2C) default to a 400KHz freq,
	365	+ * force the speed to 100KHz as a workaround.
	366	+ *
	367	+ * For future investigation: This problem may be related to the default
	368	+ * HCNT/LCNT values given by some busses' drivers, because they are not
	369	+ * specified in the aforementioned devices' ACPI tables, and because
	370	+ * the device works without issues on Windows at what is expected to be
	371	+ * a 400KHz frequency. The root cause of the issue is not known.
	372	+ */
	373	+ { "ELAN06FA", 0 },
	374	+ {}
	375	+};
	376	+
358	377	static acpi_status i2c_acpi_lookup_speed(acpi_handle handle, u32 level,
359	378	void data, void *return_value)
360	379	{
@@ -373,6 +392,9 @@ static acpi_status i2c_acpi_lookup_speed(acpi_handle handle, u32 level, · 12 unmodified lines
373	392	if (acpi_match_device_ids(adev, i2c_acpi_force_400khz_device_ids) == 0)
374	393	lookup->force_speed = I2C_MAX_FAST_MODE_FREQ;
375	394
	395	+ if (acpi_match_device_ids(adev, i2c_acpi_force_100khz_device_ids) == 0)
	396	+ lookup->force_speed = I2C_MAX_STANDARD_MODE_FREQ;
	397	+
376	398	return AE_OK;
377	399	}
378	400

drivers/i2c/i2c-core-base.c+47−83

@@ -1015,6 +1015,8 @@ i2c_new_client_device(struct i2c_adapter adap, struct i2c_board_info const inf · 1014 unmodified lines
1015	1015	if (status)
1016	1016	goto out_remove_swnode;
1017	1017
	1018	+ client->debugfs = debugfs_create_dir(dev_name(&client->dev), adap->debugfs);
	1019	+
1018	1020	dev_dbg(&adap->dev, "client [%s] registered with bus id %s\n",
1019	1021	client->name, dev_name(&client->dev));
1020	1022
@@ -1058,6 +1060,8 @@ void i2c_unregister_device(struct i2c_client *client) · 37 unmodified lines
1058	1060
1059	1061	if (ACPI_COMPANION(&client->dev))
1060	1062	acpi_device_clear_enumerated(ACPI_COMPANION(&client->dev));
	1063	+
	1064	+ debugfs_remove_recursive(client->debugfs);
1061	1065	device_remove_software_node(&client->dev);
1062	1066	device_unregister(&client->dev);
1063	1067	}
@@ -1293,14 +1297,12 @@ new_device_store(struct device dev, struct device_attribute attr, · 229 unmodified lines
1293	1297	info.flags \|= I2C_CLIENT_SLAVE;
1294	1298	}
1295	1299
	1300	+ info.flags \|= I2C_CLIENT_USER;
	1301	+
1296	1302	client = i2c_new_client_device(adap, &info);
1297	1303	if (IS_ERR(client))
1298	1304	return PTR_ERR(client);
1299	1305
1300		− /* Keep track of the added device */
1301		− mutex_lock(&adap->userspace_clients_lock);
1302		− list_add_tail(&client->detected, &adap->userspace_clients);
1303		− mutex_unlock(&adap->userspace_clients_lock);
1304	1306	dev_info(dev, "%s: Instantiated device %s at 0x%02hx\n", "new_device",
1305	1307	info.type, info.addr);
1306	1308
@@ -1308,6 +1310,15 @@ new_device_store(struct device dev, struct device_attribute attr, · 1 unmodified line
1308	1310	}
1309	1311	static DEVICE_ATTR_WO(new_device);
1310	1312
	1313	+static int __i2c_find_user_addr(struct device dev, void addrp)
	1314	+{
	1315	+ struct i2c_client *client = i2c_verify_client(dev);
	1316	+ unsigned short addr = (unsigned short )addrp;
	1317	+
	1318	+ return client && client->flags & I2C_CLIENT_USER &&
	1319	+ i2c_encode_flags_to_addr(client) == addr;
	1320	+}
	1321	+
1311	1322	/*
1312	1323	* And of course let the users delete the devices they instantiated, if
1313	1324	* they got it wrong. This interface can only be used to delete devices
@@ -1322,7 +1333,7 @@ delete_device_store(struct device dev, struct device_attribute attr, · 8 unmodified lines
1322	1333	const char *buf, size_t count)
1323	1334	{
1324	1335	struct i2c_adapter *adap = to_i2c_adapter(dev);
1325		− struct i2c_client client, next;
	1336	+ struct device *child_dev;
1326	1337	unsigned short addr;
1327	1338	char end;
1328	1339	int res;
@@ -1338,28 +1349,19 @@ delete_device_store(struct device dev, struct device_attribute attr, · 9 unmodified lines
1338	1349	return -EINVAL;
1339	1350	}
1340	1351
	1352	+ mutex_lock(&core_lock);
1341	1353	/* Make sure the device was added through sysfs */
1342		− res = -ENOENT;
1343		− mutex_lock_nested(&adap->userspace_clients_lock,
1344		− i2c_adapter_depth(adap));
1345		− list_for_each_entry_safe(client, next, &adap->userspace_clients,
1346		− detected) {
1347		− if (i2c_encode_flags_to_addr(client) == addr) {
1348		− dev_info(dev, "%s: Deleting device %s at 0x%02hx\n",
1349		− "delete_device", client->name, client->addr);
1350		−
1351		− list_del(&client->detected);
1352		− i2c_unregister_device(client);
1353		− res = count;
1354		− break;
1355		− }
	1354	+ child_dev = device_find_child(&adap->dev, &addr, __i2c_find_user_addr);
	1355	+ if (child_dev) {
	1356	+ i2c_unregister_device(i2c_verify_client(child_dev));
	1357	+ put_device(child_dev);
	1358	+ } else {
	1359	+ dev_err(dev, "Can't find userspace-created device at %#x\n", addr);
	1360	+ count = -ENOENT;
1356	1361	}
1357		− mutex_unlock(&adap->userspace_clients_lock);
	1362	+ mutex_unlock(&core_lock);
1358	1363
1359		− if (res < 0)
1360		− dev_err(dev, "%s: Can't find device in list\n",
1361		− "delete_device");
1362		− return res;
	1364	+ return count;
1363	1365	}
1364	1366	static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, S_IWUSR, NULL,
1365	1367	delete_device_store);
@@ -1530,8 +1532,6 @@ static int i2c_register_adapter(struct i2c_adapter *adap) · 164 unmodified lines
1530	1532	adap->locked_flags = 0;
1531	1533	rt_mutex_init(&adap->bus_lock);
1532	1534	rt_mutex_init(&adap->mux_lock);
1533		− mutex_init(&adap->userspace_clients_lock);
1534		− INIT_LIST_HEAD(&adap->userspace_clients);
1535	1535
1536	1536	/* Set default timeout to 1 second if not already set */
1537	1537	if (adap->timeout == 0)
@@ -1697,23 +1697,6 @@ int i2c_add_numbered_adapter(struct i2c_adapter *adap) · 159 unmodified lines
1697	1697	}
1698	1698	EXPORT_SYMBOL_GPL(i2c_add_numbered_adapter);
1699	1699
1700		−static void i2c_do_del_adapter(struct i2c_driver *driver,
1701		− struct i2c_adapter *adapter)
1702		−{
1703		− struct i2c_client client, _n;
1704		−
1705		− /* Remove the devices we created ourselves as the result of hardware
1706		− * probing (using a driver's detect method) */
1707		− list_for_each_entry_safe(client, _n, &driver->clients, detected) {
1708		− if (client->adapter == adapter) {
1709		− dev_dbg(&adapter->dev, "Removing %s at 0x%x\n",
1710		− client->name, client->addr);
1711		− list_del(&client->detected);
1712		− i2c_unregister_device(client);
1713		− }
1714		− }
1715		−}
1716		−
1717	1700	static int __unregister_client(struct device dev, void dummy)
1718	1701	{
1719	1702	struct i2c_client *client = i2c_verify_client(dev);
@@ -1729,12 +1712,6 @@ static int __unregister_dummy(struct device dev, void dummy) · 9 unmodified lines
1729	1712	return 0;
1730	1713	}
1731	1714
1732		−static int __process_removed_adapter(struct device_driver d, void data)
1733		−{
1734		− i2c_do_del_adapter(to_i2c_driver(d), data);
1735		− return 0;
1736		−}
1737		−
1738	1715	/**
1739	1716	* i2c_del_adapter - unregister I2C adapter
1740	1717	* @adap: the adapter being unregistered
@@ -1746,7 +1723,6 @@ static int __process_removed_adapter(struct device_driver d, void data) · 5 unmodified lines
1746	1723	void i2c_del_adapter(struct i2c_adapter *adap)
1747	1724	{
1748	1725	struct i2c_adapter *found;
1749		− struct i2c_client client, next;
1750	1726
1751	1727	/* First make sure that this adapter was ever added */
1752	1728	mutex_lock(&core_lock);
@@ -1758,31 +1734,16 @@ void i2c_del_adapter(struct i2c_adapter *adap) · 5 unmodified lines
1758	1734	}
1759	1735
1760	1736	i2c_acpi_remove_space_handler(adap);
1761		− /* Tell drivers about this removal */
1762		− mutex_lock(&core_lock);
1763		− bus_for_each_drv(&i2c_bus_type, NULL, adap,
1764		− __process_removed_adapter);
1765		− mutex_unlock(&core_lock);
1766		−
1767		− /* Remove devices instantiated from sysfs */
1768		− mutex_lock_nested(&adap->userspace_clients_lock,
1769		− i2c_adapter_depth(adap));
1770		− list_for_each_entry_safe(client, next, &adap->userspace_clients,
1771		− detected) {
1772		− dev_dbg(&adap->dev, "Removing %s at 0x%x\n", client->name,
1773		− client->addr);
1774		− list_del(&client->detected);
1775		− i2c_unregister_device(client);
1776		− }
1777		− mutex_unlock(&adap->userspace_clients_lock);
1778	1737
1779	1738	/* Detach any active clients. This can't fail, thus we do not
1780	1739	* check the returned value. This is a two-pass process, because
1781	1740	* we can't remove the dummy devices during the first pass: they
1782	1741	* could have been instantiated by real devices wishing to clean
1783	1742	* them up properly, so we give them a chance to do that first. */
	1743	+ mutex_lock(&core_lock);
1784	1744	device_for_each_child(&adap->dev, NULL, __unregister_client);
1785	1745	device_for_each_child(&adap->dev, NULL, __unregister_dummy);
	1746	+ mutex_unlock(&core_lock);
1786	1747
1787	1748	/* device name is gone after device_unregister */
1788	1749	dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name);
@@ -2002,7 +1963,6 @@ int i2c_register_driver(struct module owner, struct i2c_driver driver) · 213 unmodified lines
2002	1963	/* add the driver to the list of i2c drivers in the driver core */
2003	1964	driver->driver.owner = owner;
2004	1965	driver->driver.bus = &i2c_bus_type;
2005		− INIT_LIST_HEAD(&driver->clients);
2006	1966
2007	1967	/* When registration returns, the driver core
2008	1968	* will have called probe() for all matching-but-unbound devices.
@@ -2020,10 +1980,13 @@ int i2c_register_driver(struct module owner, struct i2c_driver driver) · 11 unmodified lines
2020	1980	}
2021	1981	EXPORT_SYMBOL(i2c_register_driver);
2022	1982
2023		−static int __process_removed_driver(struct device dev, void data)
	1983	+static int __i2c_unregister_detected_client(struct device dev, void argp)
2024	1984	{
2025		− if (dev->type == &i2c_adapter_type)
2026		− i2c_do_del_adapter(data, to_i2c_adapter(dev));
	1985	+ struct i2c_client *client = i2c_verify_client(dev);
	1986	+
	1987	+ if (client && client->flags & I2C_CLIENT_AUTO)
	1988	+ i2c_unregister_device(client);
	1989	+
2027	1990	return 0;
2028	1991	}
2029	1992
@@ -2034,7 +1997,12 @@ static int __process_removed_driver(struct device dev, void data) · 4 unmodified lines
2034	1997	*/
2035	1998	void i2c_del_driver(struct i2c_driver *driver)
2036	1999	{
2037		− i2c_for_each_dev(driver, __process_removed_driver);
	2000	+ mutex_lock(&core_lock);
	2001	+ /* Satisfy __must_check, function can't fail */
	2002	+ if (driver_for_each_device(&driver->driver, NULL, NULL,
	2003	+ __i2c_unregister_detected_client)) {
	2004	+ }
	2005	+ mutex_unlock(&core_lock);
2038	2006
2039	2007	driver_unregister(&driver->driver);
2040	2008	pr_debug("driver [%s] unregistered\n", driver->driver.name);
@@ -2461,6 +2429,7 @@ static int i2c_detect_address(struct i2c_client *temp_client, · 420 unmodified lines
2461	2429	/* Finally call the custom detection function */
2462	2430	memset(&info, 0, sizeof(struct i2c_board_info));
2463	2431	info.addr = addr;
	2432	+ info.flags = I2C_CLIENT_AUTO;
2464	2433	err = driver->detect(temp_client, &info);
2465	2434	if (err) {
2466	2435	/* -ENODEV is returned if the detection fails. We catch it
@@ -2487,9 +2456,7 @@ static int i2c_detect_address(struct i2c_client *temp_client, · 20 unmodified lines
2487	2456	dev_dbg(&adapter->dev, "Creating %s at 0x%02x\n",
2488	2457	info.type, info.addr);
2489	2458	client = i2c_new_client_device(adapter, &info);
2490		− if (!IS_ERR(client))
2491		− list_add_tail(&client->detected, &driver->clients);
2492		− else
	2459	+ if (IS_ERR(client))
2493	2460	dev_err(&adapter->dev, "Failed creating %s at 0x%02x\n",
2494	2461	info.type, info.addr);
2495	2462	}
@@ -2499,7 +2466,7 @@ static int i2c_detect_address(struct i2c_client *temp_client, · 3 unmodified lines
2499	2466	static int i2c_detect(struct i2c_adapter adapter, struct i2c_driver driver)
2500	2467	{
2501	2468	const unsigned short *address_list;
2502		− struct i2c_client *temp_client;
	2469	+ struct i2c_client temp_client;
2503	2470	int i, err = 0;
2504	2471
2505	2472	address_list = driver->address_list;
@@ -2520,22 +2487,19 @@ static int i2c_detect(struct i2c_adapter adapter, struct i2c_driver driver) · 14 unmodified lines
2520	2487	return 0;
2521	2488
2522	2489	/* Set up a temporary client to help detect callback */
2523		− temp_client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
2524		− if (!temp_client)
2525		− return -ENOMEM;
2526		− temp_client->adapter = adapter;
	2490	+ memset(&temp_client, 0, sizeof(temp_client));
	2491	+ temp_client.adapter = adapter;
2527	2492
2528	2493	for (i = 0; address_list[i] != I2C_CLIENT_END; i += 1) {
2529	2494	dev_dbg(&adapter->dev,
2530	2495	"found normal entry for adapter %d, addr 0x%02x\n",
2531	2496	i2c_adapter_id(adapter), address_list[i]);
2532		− temp_client->addr = address_list[i];
2533		− err = i2c_detect_address(temp_client, driver);
	2497	+ temp_client.addr = address_list[i];
	2498	+ err = i2c_detect_address(&temp_client, driver);
2534	2499	if (unlikely(err))
2535	2500	break;
2536	2501	}
2537	2502
2538		− kfree(temp_client);
2539	2503	return err;
2540	2504	}
2541	2505

drivers/i2c/i2c-slave-eeprom.c+4−4

@@ -91,7 +91,7 @@ static int i2c_slave_eeprom_slave_cb(struct i2c_client *client, · 90 unmodified lines
91	91	}
92	92
93	93	static ssize_t i2c_slave_eeprom_bin_read(struct file filp, struct kobject kobj,
94		− struct bin_attribute attr, char buf, loff_t off, size_t count)
	94	+ const struct bin_attribute attr, char buf, loff_t off, size_t count)
95	95	{
96	96	struct eeprom_data *eeprom;
97	97	unsigned long flags;
@@ -106,7 +106,7 @@ static ssize_t i2c_slave_eeprom_bin_read(struct file filp, struct kobject kobj · 8 unmodified lines
106	106	}
107	107
108	108	static ssize_t i2c_slave_eeprom_bin_write(struct file filp, struct kobject kobj,
109		− struct bin_attribute attr, char buf, loff_t off, size_t count)
	109	+ const struct bin_attribute attr, char buf, loff_t off, size_t count)
110	110	{
111	111	struct eeprom_data *eeprom;
112	112	unsigned long flags;
@@ -165,8 +165,8 @@ static int i2c_slave_eeprom_probe(struct i2c_client *client) · 52 unmodified lines
165	165	sysfs_bin_attr_init(&eeprom->bin);
166	166	eeprom->bin.attr.name = "slave-eeprom";
167	167	eeprom->bin.attr.mode = S_IRUSR \| S_IWUSR;
168		− eeprom->bin.read = i2c_slave_eeprom_bin_read;
169		− eeprom->bin.write = i2c_slave_eeprom_bin_write;
	168	+ eeprom->bin.read_new = i2c_slave_eeprom_bin_read;
	169	+ eeprom->bin.write_new = i2c_slave_eeprom_bin_write;
170	170	eeprom->bin.size = size;
171	171
172	172	ret = sysfs_create_bin_file(&client->dev.kobj, &eeprom->bin);

include/linux/i2c.h+5−8

@@ -244,7 +244,6 @@ enum i2c_driver_flags { · 243 unmodified lines
244	244	* @id_table: List of I2C devices supported by this driver
245	245	* @detect: Callback for device detection
246	246	* @address_list: The I2C addresses to probe (for detect)
247		− * @clients: List of detected clients we created (for i2c-core use only)
248	247	* @flags: A bitmask of flags defined in &enum i2c_driver_flags
249	248	*
250	249	* The driver.owner field should be set to the module owner of this driver.
@@ -299,7 +298,6 @@ struct i2c_driver { · 48 unmodified lines
299	298	/* Device detection callback for automatic device creation */
300	299	int (detect)(struct i2c_client client, struct i2c_board_info *info);
301	300	const unsigned short *address_list;
302		− struct list_head clients;
303	301
304	302	u32 flags;
305	303	};
@@ -315,12 +313,12 @@ struct i2c_driver { · 9 unmodified lines
315	313	* @dev: Driver model device node for the slave.
316	314	* @init_irq: IRQ that was set at initialization
317	315	* @irq: indicates the IRQ generated by this device (if any)
318		− * @detected: member of an i2c_driver.clients list or i2c-core's
319		− * userspace_devices list
320	316	* @slave_cb: Callback when I2C slave mode of an adapter is used. The adapter
321	317	* calls it to pass on slave events to the slave driver.
322	318	* @devres_group_id: id of the devres group that will be created for resources
323	319	* acquired when probing this device.
	320	+ * @debugfs: pointer to the debugfs subdirectory which the I2C core created
	321	+ * for this client.
324	322	*
325	323	* An i2c_client identifies a single device (i.e. chip) connected to an
326	324	* i2c bus. The behaviour exposed to Linux is defined by the driver
@@ -334,6 +332,8 @@ struct i2c_client { · 7 unmodified lines
334	332	#define I2C_CLIENT_SLAVE 0x20 /* we are the slave */
335	333	#define I2C_CLIENT_HOST_NOTIFY 0x40 /* We want to use I2C host notify */
336	334	#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */
	335	+#define I2C_CLIENT_AUTO 0x100 /* client was auto-detected */
	336	+#define I2C_CLIENT_USER 0x200 /* client was userspace-created */
337	337	#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */
338	338	/* Must match I2C_M_STOP\|IGNORE_NAK */
339	339
@@ -345,11 +345,11 @@ struct i2c_client { · 5 unmodified lines
345	345	struct device dev; /* the device structure */
346	346	int init_irq; /* irq set at initialization */
347	347	int irq; /* irq issued by device */
348		− struct list_head detected;
349	348	#if IS_ENABLED(CONFIG_I2C_SLAVE)
350	349	i2c_slave_cb_t slave_cb; /* callback for slave mode */
351	350	#endif
352	351	void devres_group_id; / ID of probe devres group */
	352	+ struct dentry debugfs; / per-client debugfs dir */
353	353	};
354	354	#define to_i2c_client(d) container_of(d, struct i2c_client, dev)
355	355
@@ -751,9 +751,6 @@ struct i2c_adapter { · 395 unmodified lines
751	751	char name[48];
752	752	struct completion dev_released;
753	753
754		− struct mutex userspace_clients_lock;
755		− struct list_head userspace_clients;
756		−
757	754	struct i2c_bus_recovery_info *bus_recovery_info;
758	755	const struct i2c_adapter_quirks *quirks;
759	756

include/linux/platform_data/i2c-davinci.h+0−26

@@ -1,26 +0,0 @@
1		−/*
2		− * DaVinci I2C controller platform_device info
3		− *
4		− * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5		− *
6		− * 2007 (c) MontaVista Software, Inc. This file is licensed under
7		− * the terms of the GNU General Public License version 2. This program
8		− * is licensed "as is" without any warranty of any kind, whether express
9		− * or implied.
10		−*/
11		−
12		−#ifndef __ASM_ARCH_I2C_H
13		−#define __ASM_ARCH_I2C_H
14		−
15		−/* All frequencies are expressed in kHz */
16		−struct davinci_i2c_platform_data {
17		− unsigned int bus_freq; /* standard bus frequency (kHz) */
18		− unsigned int bus_delay; /* post-transaction delay (usec) */
19		− bool gpio_recovery; /* Use GPIO recovery method */
20		− bool has_pfunc; /* Chip has a ICPFUNC register */
21		−};
22		−
23		−/* for board setup code */
24		−void davinci_init_i2c(struct davinci_i2c_platform_data *);
25		−
26		−#endif /* __ASM_ARCH_I2C_H */

sound/ppc/keywest.c+1−6

@@ -61,12 +61,6 @@ static int keywest_attach_adapter(struct i2c_adapter *adapter) · 60 unmodified lines
61	61	return -ENODEV;
62	62	}
63	63
64		− /*
65		− * Let i2c-core delete that device on driver removal.
66		− * This is safe because i2c-core holds the core_lock mutex for us.
67		− */
68		− list_add_tail(&keywest_ctx->client->detected,
69		− &to_i2c_driver(keywest_ctx->client->dev.driver)->clients);
70	64	return 0;
71	65	}
72	66
@@ -99,6 +93,7 @@ static struct i2c_driver keywest_driver = { · 26 unmodified lines
99	93	void snd_pmac_keywest_cleanup(struct pmac_keywest *i2c)
100	94	{
101	95	if (keywest_ctx && keywest_ctx == i2c) {
	96	+ i2c_unregister_device(keywest_ctx->client);
102	97	i2c_del_driver(&keywest_driver);
103	98	keywest_ctx = NULL;
104	99	}