Pull ARM SoC devicetree updates from Arnd Bergmann: "As usual, this is the bulk of the updates for the SoC tree, adding more devices to existing files, addressing issues from ever improving automated checking, and fixing minor issues. The most interesting bits as usual are the new platforms. All the newly supported SoCs belong into existing families this time: - Qualcomm gets support for two newly announced platforms, both of which can now work in production environments: the SDX65 5G modem that can run a minimal Linux on its Cortex-A7 core, and the Snapdragon 8 Gen 1, their latest high-end phone SoC. - Renesas adds support for R-Car S4-8, the most recent automotive Server/Communication SoC. - TI adds support for J721s2, a new automotive SoC in the K3 family. - Mediatek MT7986a/b is a SoC used in Wifi routers, the latest generation following their popular MT76xx series. Only basic support is added for now. - NXP i.MX8 ULP8 is a new low-power variant of the widespread i.MX8 series. - TI SPEAr320s is a minor variant of the old SPEAr320 SoC that we have supported for a long time. New boards with the existing SoCs include - Aspeed AST2500/AST2600 BMCs in TYAN, Facebook and Yadro servers - AT91/SAMA5 based evaluation board - NXP gains twenty new development and industrial boards for their i.MX and Layerscape SoCs - Intel IXP4xx now supports the final two machines in device tree that were previously only supported in old style board files. - Mediatek MT6589 is used in the Fairphone FP1 phone from 2013, while MT8183 is used in the Acer Chromebook 314. - Qualcomm gains support for the reference machines using the two new SoCs, plus a number of Chromebook variants and phones based on the Snapdragon 7c, 845 and 888 SoCs, including various Sony Xperia devices and the Microsoft Surface Duo 2. - ST STM32 now supports the Engicam i.Core STM32MP1 carrier board. - Tegra now boots various older Android devices based on 32-bit chips out of the box, including a number of ASUS Transformer tablets. There is also a new Jetson AGX Orin developer kit. - Apple support adds the missing device trees for all the remaining M1 Macbook and iMac variants, though not yet the M1 Pro/Max versions. - Allwinner now supports another version of the Tanix TX6 set-top box based on the H6 SoC. - Broadcom gains support for the Netgear RAXE500 Wireless router based on BCM4908" * tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (574 commits) Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX arm64: dts: qcom: sm8450-qrd: Enable USB nodes arm64: dts: qcom: sm8450: Add usb nodes ARM: dts: aspeed: add LCLK setting into LPC KCS nodes dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property ARM: dts: aspeed: add LCLK setting into LPC IBT node ARM: dts: aspeed: p10: Add TPM device ARM: dts: aspeed: p10: Enable USB host ports ARM: dts: aspeed: Add TYAN S8036 BMC machine ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config ARM: dts: aspeed: Adding Facebook Bletchley BMC ARM: dts: aspeed: g220a: Enable secondary flash ARM: dts: Add openbmc-flash-layout-64-alt.dtsi ARM: dts: aspeed: Add secure boot controller node dt-bindings: aspeed: Add Secure Boot Controller bindings ARM: dts: Remove "spidev" nodes dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 dt-bindings: arm: samsung: Document E850-96 board binding dt-bindings: Add vendor prefix for WinLink ...
Unified · Split
| @@ -12,12 +12,19 @@ maintainers: · 11 unmodified lines | ||
| 12 | 12 | description: | |
| 13 | 13 | ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon". |
| 14 | 14 | |
| 15 | − This currently includes devices based on the "M1" SoC, starting with the | |
| 16 | − three Mac models released in late 2020: | |
| 15 | + This currently includes devices based on the "M1" SoC: | |
| 17 | 16 | |
| 18 | 17 | - Mac mini (M1, 2020) |
| 19 | 18 | - MacBook Pro (13-inch, M1, 2020) |
| 20 | 19 | - MacBook Air (M1, 2020) |
| 20 | + - iMac (24-inch, M1, 2021) | |
| 21 | + | |
| 22 | + And devices based on the "M1 Pro" and "M1 Max" SoCs: | |
| 23 | + | |
| 24 | + - MacBook Pro (14-inch, M1 Pro, 2021) | |
| 25 | + - MacBook Pro (14-inch, M1 Max, 2021) | |
| 26 | + - MacBook Pro (16-inch, M1 Pro, 2021) | |
| 27 | + - MacBook Pro (16-inch, M1 Max, 2021) | |
| 21 | 28 | |
| 22 | 29 | The compatible property should follow this format: |
| 23 | 30 | |
| @@ -56,8 +63,24 @@ properties: · 32 unmodified lines | ||
| 56 | 63 | - apple,j274 # Mac mini (M1, 2020) |
| 57 | 64 | - apple,j293 # MacBook Pro (13-inch, M1, 2020) |
| 58 | 65 | - apple,j313 # MacBook Air (M1, 2020) |
| 66 | + - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021) | |
| 67 | + - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) | |
| 59 | 68 | - const: apple,t8103 |
| 60 | 69 | - const: apple,arm-platform |
| 70 | + - description: Apple M1 Pro SoC based platforms | |
| 71 | + items: | |
| 72 | + - enum: | |
| 73 | + - apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021) | |
| 74 | + - apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021) | |
| 75 | + - const: apple,t6000 | |
| 76 | + - const: apple,arm-platform | |
| 77 | + - description: Apple M1 Max SoC based platforms | |
| 78 | + items: | |
| 79 | + - enum: | |
| 80 | + - apple,j314c # MacBook Pro (14-inch, M1 Max, 2021) | |
| 81 | + - apple,j316c # MacBook Pro (16-inch, M1 Max, 2021) | |
| 82 | + - const: apple,t6001 | |
| 83 | + - const: apple,arm-platform | |
| 61 | 84 | |
| 62 | 85 | additionalProperties: true |
| 63 | 86 | |
| @@ -0,0 +1,134 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Apple SoC Power Manager (PMGR) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Hector Martin <marcan@marcan.st> | |
| 11 | + | |
| 12 | +description: | | |
| 13 | + Apple SoCs include PMGR blocks responsible for power management, | |
| 14 | + which can control various clocks, resets, power states, and | |
| 15 | + performance features. This node represents the PMGR as a syscon, | |
| 16 | + with sub-nodes representing individual features. | |
| 17 | + | |
| 18 | +properties: | |
| 19 | + $nodename: | |
| 20 | + pattern: "^power-management@[0-9a-f]+$" | |
| 21 | + | |
| 22 | + compatible: | |
| 23 | + items: | |
| 24 | + - enum: | |
| 25 | + - apple,t8103-pmgr | |
| 26 | + - apple,t6000-pmgr | |
| 27 | + - const: apple,pmgr | |
| 28 | + - const: syscon | |
| 29 | + - const: simple-mfd | |
| 30 | + | |
| 31 | + reg: | |
| 32 | + maxItems: 1 | |
| 33 | + | |
| 34 | + "#address-cells": | |
| 35 | + const: 1 | |
| 36 | + | |
| 37 | + "#size-cells": | |
| 38 | + const: 1 | |
| 39 | + | |
| 40 | +patternProperties: | |
| 41 | + "power-controller@[0-9a-f]+$": | |
| 42 | + description: | |
| 43 | + The individual power management domains within this controller | |
| 44 | + type: object | |
| 45 | + $ref: /power/apple,pmgr-pwrstate.yaml# | |
| 46 | + | |
| 47 | +required: | |
| 48 | + - compatible | |
| 49 | + - reg | |
| 50 | + | |
| 51 | +additionalProperties: false | |
| 52 | + | |
| 53 | +examples: | |
| 54 | + - | | |
| 55 | + soc { | |
| 56 | + #address-cells = <2>; | |
| 57 | + #size-cells = <2>; | |
| 58 | + | |
| 59 | + power-management@23b700000 { | |
| 60 | + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; | |
| 61 | + #address-cells = <1>; | |
| 62 | + #size-cells = <1>; | |
| 63 | + reg = <0x2 0x3b700000 0x0 0x14000>; | |
| 64 | + | |
| 65 | + ps_sio: power-controller@1c0 { | |
| 66 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 67 | + reg = <0x1c0 8>; | |
| 68 | + #power-domain-cells = <0>; | |
| 69 | + #reset-cells = <0>; | |
| 70 | + label = "sio"; | |
| 71 | + apple,always-on; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + ps_uart_p: power-controller@220 { | |
| 75 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 76 | + reg = <0x220 8>; | |
| 77 | + #power-domain-cells = <0>; | |
| 78 | + #reset-cells = <0>; | |
| 79 | + label = "uart_p"; | |
| 80 | + power-domains = <&ps_sio>; | |
| 81 | + }; | |
| 82 | + | |
| 83 | + ps_uart0: power-controller@270 { | |
| 84 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 85 | + reg = <0x270 8>; | |
| 86 | + #power-domain-cells = <0>; | |
| 87 | + #reset-cells = <0>; | |
| 88 | + label = "uart0"; | |
| 89 | + power-domains = <&ps_uart_p>; | |
| 90 | + }; | |
| 91 | + }; | |
| 92 | + | |
| 93 | + power-management@23d280000 { | |
| 94 | + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; | |
| 95 | + #address-cells = <1>; | |
| 96 | + #size-cells = <1>; | |
| 97 | + reg = <0x2 0x3d280000 0x0 0xc000>; | |
| 98 | + | |
| 99 | + ps_aop_filter: power-controller@4000 { | |
| 100 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 101 | + reg = <0x4000 8>; | |
| 102 | + #power-domain-cells = <0>; | |
| 103 | + #reset-cells = <0>; | |
| 104 | + label = "aop_filter"; | |
| 105 | + }; | |
| 106 | + | |
| 107 | + ps_aop_base: power-controller@4010 { | |
| 108 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 109 | + reg = <0x4010 8>; | |
| 110 | + #power-domain-cells = <0>; | |
| 111 | + #reset-cells = <0>; | |
| 112 | + label = "aop_base"; | |
| 113 | + power-domains = <&ps_aop_filter>; | |
| 114 | + }; | |
| 115 | + | |
| 116 | + ps_aop_shim: power-controller@4038 { | |
| 117 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 118 | + reg = <0x4038 8>; | |
| 119 | + #power-domain-cells = <0>; | |
| 120 | + #reset-cells = <0>; | |
| 121 | + label = "aop_shim"; | |
| 122 | + power-domains = <&ps_aop_base>; | |
| 123 | + }; | |
| 124 | + | |
| 125 | + ps_aop_uart0: power-controller@4048 { | |
| 126 | + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; | |
| 127 | + reg = <0x4048 8>; | |
| 128 | + #power-domain-cells = <0>; | |
| 129 | + #reset-cells = <0>; | |
| 130 | + label = "aop_uart0"; | |
| 131 | + power-domains = <&ps_aop_shim>; | |
| 132 | + }; | |
| 133 | + }; | |
| 134 | + }; | |
| @@ -0,0 +1,37 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) | |
| 2 | +# Copyright 2021 Joel Stanley, IBM Corp. | |
| 3 | +%YAML 1.2 | |
| 4 | +--- | |
| 5 | +$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#" | |
| 6 | +$schema: "http://devicetree.org/meta-schemas/core.yaml#" | |
| 7 | + | |
| 8 | +title: ASPEED Secure Boot Controller | |
| 9 | + | |
| 10 | +maintainers: | |
| 11 | + - Joel Stanley <joel@jms.id.au> | |
| 12 | + - Andrew Jeffery <andrew@aj.id.au> | |
| 13 | + | |
| 14 | +description: | | |
| 15 | + The ASPEED SoCs have a register bank for interacting with the secure boot | |
| 16 | + controller. | |
| 17 | + | |
| 18 | +properties: | |
| 19 | + compatible: | |
| 20 | + items: | |
| 21 | + - const: aspeed,ast2600-sbc | |
| 22 | + | |
| 23 | + reg: | |
| 24 | + maxItems: 1 | |
| 25 | + | |
| 26 | +required: | |
| 27 | + - compatible | |
| 28 | + - reg | |
| 29 | + | |
| 30 | +additionalProperties: false | |
| 31 | + | |
| 32 | +examples: | |
| 33 | + - | | |
| 34 | + sbc: secure-boot-controller@1e6f2000 { | |
| 35 | + compatible = "aspeed,ast2600-sbc"; | |
| 36 | + reg = <0x1e6f2000 0x1000>; | |
| 37 | + }; | |
| @@ -29,6 +29,7 @@ properties: · 28 unmodified lines | ||
| 29 | 29 | items: |
| 30 | 30 | - enum: |
| 31 | 31 | - asus,gt-ac5300 |
| 32 | + - netgear,raxe500 | |
| 32 | 33 | - const: brcm,bcm4908 |
| 33 | 34 | |
| 34 | 35 | - description: BCM49408 based boards |
| @@ -240,6 +240,7 @@ properties: · 239 unmodified lines | ||
| 240 | 240 | - uniwest,imx6q-evi # Uniwest Evi |
| 241 | 241 | - variscite,dt6customboard |
| 242 | 242 | - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board |
| 243 | + - ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board | |
| 243 | 244 | - zealz,imx6q-gk802 # Zealz GK802 |
| 244 | 245 | - zii,imx6q-zii-rdu2 # ZII RDU2 Board |
| 245 | 246 | - const: fsl,imx6q |
| @@ -323,6 +324,20 @@ properties: · 77 unmodified lines | ||
| 323 | 324 | - const: toradex,apalis_imx6q |
| 324 | 325 | - const: fsl,imx6q |
| 325 | 326 | |
| 327 | + - description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x | |
| 328 | + items: | |
| 329 | + - const: tq,imx6q-mba6x-a | |
| 330 | + - const: tq,mba6a # Expected by bootloader, to be removed in the future | |
| 331 | + - const: tq,imx6q-tqma6q-a | |
| 332 | + - const: fsl,imx6q | |
| 333 | + | |
| 334 | + - description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x | |
| 335 | + items: | |
| 336 | + - const: tq,imx6q-mba6x-b | |
| 337 | + - const: tq,mba6b # Expected by bootloader, to be removed in the future | |
| 338 | + - const: tq,imx6q-tqma6q-b | |
| 339 | + - const: fsl,imx6q | |
| 340 | + | |
| 326 | 341 | - description: i.MX6QP based Boards |
| 327 | 342 | items: |
| 328 | 343 | - enum: |
| @@ -334,6 +349,7 @@ properties: · 5 unmodified lines | ||
| 334 | 349 | - kvg,vicutp # Kverneland UT1P board |
| 335 | 350 | - prt,prtwd3 # Protonic WD3 board |
| 336 | 351 | - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board |
| 352 | + - ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board | |
| 337 | 353 | - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board |
| 338 | 354 | - const: fsl,imx6qp |
| 339 | 355 | |
| @@ -344,6 +360,13 @@ properties: · 4 unmodified lines | ||
| 344 | 360 | - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 |
| 345 | 361 | - const: fsl,imx6qp |
| 346 | 362 | |
| 363 | + - description: TQ-Systems TQMa6QP SoM on MBa6x | |
| 364 | + items: | |
| 365 | + - const: tq,imx6qp-mba6x-b | |
| 366 | + - const: tq,mba6b # Expected by bootloader, to be removed in the future | |
| 367 | + - const: tq,imx6qp-tqma6qp-b | |
| 368 | + - const: fsl,imx6qp | |
| 369 | + | |
| 347 | 370 | - description: i.MX6DL based Boards |
| 348 | 371 | items: |
| 349 | 372 | - enum: |
| @@ -482,6 +505,20 @@ properties: · 132 unmodified lines | ||
| 482 | 505 | - const: dh,imx6s-dhcom-som |
| 483 | 506 | - const: fsl,imx6dl |
| 484 | 507 | |
| 508 | + - description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x | |
| 509 | + items: | |
| 510 | + - const: tq,imx6dl-mba6x-a | |
| 511 | + - const: tq,mba6a # Expected by bootloader, to be removed in the future | |
| 512 | + - const: tq,imx6dl-tqma6dl-a | |
| 513 | + - const: fsl,imx6dl | |
| 514 | + | |
| 515 | + - description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x | |
| 516 | + items: | |
| 517 | + - const: tq,imx6dl-mba6x-b | |
| 518 | + - const: tq,mba6b # Expected by bootloader, to be removed in the future | |
| 519 | + - const: tq,imx6dl-tqma6dl-b | |
| 520 | + - const: fsl,imx6dl | |
| 521 | + | |
| 485 | 522 | - description: i.MX6SL based Boards |
| 486 | 523 | items: |
| 487 | 524 | - enum: |
| @@ -580,6 +617,7 @@ properties: · 92 unmodified lines | ||
| 580 | 617 | items: |
| 581 | 618 | - enum: |
| 582 | 619 | - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board |
| 620 | + - joz,jozacp # JOZ Access Point | |
| 583 | 621 | - kontron,imx6ull-n6411-som # Kontron N6411 SOM |
| 584 | 622 | - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board |
| 585 | 623 | - toradex,colibri-imx6ull # Colibri iMX6ULL Modules |
| @@ -632,6 +670,7 @@ properties: · 46 unmodified lines | ||
| 632 | 670 | - description: i.MX6ULZ based Boards |
| 633 | 671 | items: |
| 634 | 672 | - enum: |
| 673 | + - bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster | |
| 635 | 674 | - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board |
| 636 | 675 | - const: fsl,imx6ull # This seems odd. Should be last? |
| 637 | 676 | - const: fsl,imx6ulz |
| @@ -754,10 +793,23 @@ properties: · 116 unmodified lines | ||
| 754 | 793 | - const: variscite,var-som-mx8mm |
| 755 | 794 | - const: fsl,imx8mm |
| 756 | 795 | |
| 796 | + - description: | |
| 797 | + TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip | |
| 798 | + variants. It is designed to be soldered on different carrier boards. | |
| 799 | + All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only | |
| 800 | + one compatible is needed. | |
| 801 | + items: | |
| 802 | + - enum: | |
| 803 | + - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx | |
| 804 | + - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM | |
| 805 | + - const: fsl,imx8mm | |
| 806 | + | |
| 757 | 807 | - description: i.MX8MN based Boards |
| 758 | 808 | items: |
| 759 | 809 | - enum: |
| 760 | 810 | - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit |
| 811 | + - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 | |
| 812 | + - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO | |
| 761 | 813 | - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board |
| 762 | 814 | - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board |
| 763 | 815 | - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board |
| @@ -769,6 +821,17 @@ properties: · 5 unmodified lines | ||
| 769 | 821 | - const: variscite,var-som-mx8mn |
| 770 | 822 | - const: fsl,imx8mn |
| 771 | 823 | |
| 824 | + - description: | |
| 825 | + TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip | |
| 826 | + variants. It is designed to be soldered on different carrier boards. | |
| 827 | + All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only | |
| 828 | + one compatible is needed. | |
| 829 | + items: | |
| 830 | + - enum: | |
| 831 | + - tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx | |
| 832 | + - const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM | |
| 833 | + - const: fsl,imx8mn | |
| 834 | + | |
| 772 | 835 | - description: i.MX8MP based Boards |
| 773 | 836 | items: |
| 774 | 837 | - enum: |
| @@ -805,6 +868,15 @@ properties: · 30 unmodified lines | ||
| 805 | 868 | - const: purism,librem5 |
| 806 | 869 | - const: fsl,imx8mq |
| 807 | 870 | |
| 871 | + - description: | |
| 872 | + TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip | |
| 873 | + variants. It is designed to be clicked on different carrier boards. | |
| 874 | + items: | |
| 875 | + - enum: | |
| 876 | + - tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx | |
| 877 | + - const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM | |
| 878 | + - const: fsl,imx8mq | |
| 879 | + | |
| 808 | 880 | - description: Zodiac Inflight Innovations Ultra Boards |
| 809 | 881 | items: |
| 810 | 882 | - enum: |
| @@ -834,6 +906,12 @@ properties: · 23 unmodified lines | ||
| 834 | 906 | - const: toradex,colibri-imx8x |
| 835 | 907 | - const: fsl,imx8qxp |
| 836 | 908 | |
| 909 | + - description: i.MX8ULP based Boards | |
| 910 | + items: | |
| 911 | + - enum: | |
| 912 | + - fsl,imx8ulp-evk # i.MX8ULP EVK Board | |
| 913 | + - const: fsl,imx8ulp | |
| 914 | + | |
| 837 | 915 | - description: |
| 838 | 916 | Freescale Vybrid Platform Device Tree Bindings |
| 839 | 917 | |
| @@ -77,6 +77,14 @@ properties: · 76 unmodified lines | ||
| 77 | 77 | - enum: |
| 78 | 78 | - mediatek,mt7629-rfb |
| 79 | 79 | - const: mediatek,mt7629 |
| 80 | + - items: | |
| 81 | + - enum: | |
| 82 | + - mediatek,mt7986a-rfb | |
| 83 | + - const: mediatek,mt7986a | |
| 84 | + - items: | |
| 85 | + - enum: | |
| 86 | + - mediatek,mt7986b-rfb | |
| 87 | + - const: mediatek,mt7986b | |
| 80 | 88 | - items: |
| 81 | 89 | - enum: |
| 82 | 90 | - mediatek,mt8127-moose |
| @@ -134,6 +142,10 @@ properties: · 51 unmodified lines | ||
| 134 | 142 | - google,krane-sku176 |
| 135 | 143 | - const: google,krane |
| 136 | 144 | - const: mediatek,mt8183 |
| 145 | + - description: Google Cozmo (Acer Chromebook 314) | |
| 146 | + items: | |
| 147 | + - const: google,cozmo | |
| 148 | + - const: mediatek,mt8183 | |
| 137 | 149 | - description: Google Damu (ASUS Chromebook Flip CM3) |
| 138 | 150 | items: |
| 139 | 151 | - const: google,damu |
| @@ -143,7 +155,9 @@ properties: · 3 unmodified lines | ||
| 143 | 155 | - enum: |
| 144 | 156 | - google,fennel-sku0 |
| 145 | 157 | - google,fennel-sku1 |
| 158 | + - google,fennel-sku2 | |
| 146 | 159 | - google,fennel-sku6 |
| 160 | + - google,fennel-sku7 | |
| 147 | 161 | - const: google,fennel |
| 148 | 162 | - const: mediatek,mt8183 |
| 149 | 163 | - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) |
| @@ -159,6 +173,12 @@ properties: · 9 unmodified lines | ||
| 159 | 173 | - const: google,kakadu-rev2 |
| 160 | 174 | - const: google,kakadu |
| 161 | 175 | - const: mediatek,mt8183 |
| 176 | + - description: Google Kakadu (ASUS Chromebook Detachable CM3) | |
| 177 | + items: | |
| 178 | + - const: google,kakadu-rev3-sku22 | |
| 179 | + - const: google,kakadu-rev2-sku22 | |
| 180 | + - const: google,kakadu | |
| 181 | + - const: mediatek,mt8183 | |
| 162 | 182 | - description: Google Kappa (HP Chromebook 11a) |
| 163 | 183 | items: |
| 164 | 184 | - const: google,kappa |
| @@ -48,6 +48,7 @@ description: | · 47 unmodified lines | ||
| 48 | 48 | sdx65 |
| 49 | 49 | sm7225 |
| 50 | 50 | sm8150 |
| 51 | + sdx65 | |
| 51 | 52 | sm8250 |
| 52 | 53 | sm8350 |
| 53 | 54 | sm8450 |
| @@ -202,8 +203,10 @@ properties: · 148 unmodified lines | ||
| 202 | 203 | |
| 203 | 204 | - items: |
| 204 | 205 | - enum: |
| 206 | + - qcom,sc7280-crd | |
| 205 | 207 | - qcom,sc7280-idp |
| 206 | 208 | - qcom,sc7280-idp2 |
| 209 | + - google,hoglin | |
| 207 | 210 | - google,piglin |
| 208 | 211 | - google,senor |
| 209 | 212 | - const: qcom,sc7280 |
| @@ -225,6 +228,11 @@ properties: · 15 unmodified lines | ||
| 225 | 228 | - qcom,sdx65-mtp |
| 226 | 229 | - const: qcom,sdx65 |
| 227 | 230 | |
| 231 | + - items: | |
| 232 | + - enum: | |
| 233 | + - qcom,sdx65-mtp | |
| 234 | + - const: qcom,sdx65 | |
| 235 | + | |
| 228 | 236 | - items: |
| 229 | 237 | - enum: |
| 230 | 238 | - qcom,ipq6018-cp01 |
| @@ -315,6 +315,18 @@ properties: · 314 unmodified lines | ||
| 315 | 315 | - const: renesas,falcon-cpu |
| 316 | 316 | - const: renesas,r8a779a0 |
| 317 | 317 | |
| 318 | + - description: R-Car S4-8 (R8A779F0) | |
| 319 | + items: | |
| 320 | + - enum: | |
| 321 | + - renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S) | |
| 322 | + - const: renesas,r8a779f0 | |
| 323 | + | |
| 324 | + - items: | |
| 325 | + - enum: | |
| 326 | + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) | |
| 327 | + - const: renesas,spider-cpu | |
| 328 | + - const: renesas,r8a779f0 | |
| 329 | + | |
| 318 | 330 | - description: R-Car H3e (R8A779M0) |
| 319 | 331 | items: |
| 320 | 332 | - enum: |
| @@ -199,6 +199,18 @@ properties: · 198 unmodified lines | ||
| 199 | 199 | - samsung,exynos7-espresso # Samsung Exynos7 Espresso |
| 200 | 200 | - const: samsung,exynos7 |
| 201 | 201 | |
| 202 | + - description: Exynos7885 based boards | |
| 203 | + items: | |
| 204 | + - enum: | |
| 205 | + - samsung,jackpotlte # Samsung Galaxy A8 (2018) | |
| 206 | + - const: samsung,exynos7885 | |
| 207 | + | |
| 208 | + - description: Exynos850 based boards | |
| 209 | + items: | |
| 210 | + - enum: | |
| 211 | + - winlink,e850-96 # WinLink E850-96 | |
| 212 | + - const: samsung,exynos850 | |
| 213 | + | |
| 202 | 214 | - description: Exynos Auto v9 based boards |
| 203 | 215 | items: |
| 204 | 216 | - enum: |
| @@ -77,6 +77,7 @@ properties: · 76 unmodified lines | ||
| 77 | 77 | items: |
| 78 | 78 | - enum: |
| 79 | 79 | - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 |
| 80 | + - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF | |
| 80 | 81 | - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit |
| 81 | 82 | - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM |
| 82 | 83 | - const: st,stm32mp157 |
| @@ -808,6 +808,11 @@ properties: · 807 unmodified lines | ||
| 808 | 808 | - const: oranth,tanix-tx6 |
| 809 | 809 | - const: allwinner,sun50i-h6 |
| 810 | 810 | |
| 811 | + - description: Tanix TX6 mini | |
| 812 | + items: | |
| 813 | + - const: oranth,tanix-tx6-mini | |
| 814 | + - const: allwinner,sun50i-h6 | |
| 815 | + | |
| 811 | 816 | - description: TBS A711 Tablet |
| 812 | 817 | items: |
| 813 | 818 | - const: tbs-biometrics,a711 |
| @@ -32,12 +32,38 @@ properties: · 31 unmodified lines | ||
| 32 | 32 | - allwinner,sun8i-h3-mbus |
| 33 | 33 | - allwinner,sun8i-r40-mbus |
| 34 | 34 | - allwinner,sun50i-a64-mbus |
| 35 | + - allwinner,sun50i-h5-mbus | |
| 35 | 36 | |
| 36 | 37 | reg: |
| 37 | − maxItems: 1 | |
| 38 | + minItems: 1 | |
| 39 | + items: | |
| 40 | + - description: MBUS interconnect/bandwidth limit/PMU registers | |
| 41 | + - description: DRAM controller/PHY registers | |
| 42 | + | |
| 43 | + reg-names: | |
| 44 | + minItems: 1 | |
| 45 | + items: | |
| 46 | + - const: mbus | |
| 47 | + - const: dram | |
| 38 | 48 | |
| 39 | 49 | clocks: |
| 50 | + minItems: 1 | |
| 51 | + items: | |
| 52 | + - description: MBUS interconnect module clock | |
| 53 | + - description: DRAM controller/PHY module clock | |
| 54 | + - description: Register bus clock, shared by MBUS and DRAM | |
| 55 | + | |
| 56 | + clock-names: | |
| 57 | + minItems: 1 | |
| 58 | + items: | |
| 59 | + - const: mbus | |
| 60 | + - const: dram | |
| 61 | + - const: bus | |
| 62 | + | |
| 63 | + interrupts: | |
| 40 | 64 | maxItems: 1 |
| 65 | + description: | |
| 66 | + MBUS PMU activity interrupt. | |
| 41 | 67 | |
| 42 | 68 | dma-ranges: |
| 43 | 69 | description: |
| @@ -54,13 +80,55 @@ required: · 10 unmodified lines | ||
| 54 | 80 | - clocks |
| 55 | 81 | - dma-ranges |
| 56 | 82 | |
| 83 | +if: | |
| 84 | + properties: | |
| 85 | + compatible: | |
| 86 | + contains: | |
| 87 | + enum: | |
| 88 | + - allwinner,sun8i-h3-mbus | |
| 89 | + - allwinner,sun50i-a64-mbus | |
| 90 | + - allwinner,sun50i-h5-mbus | |
| 91 | + | |
| 92 | +then: | |
| 93 | + properties: | |
| 94 | + reg: | |
| 95 | + minItems: 2 | |
| 96 | + | |
| 97 | + reg-names: | |
| 98 | + minItems: 2 | |
| 99 | + | |
| 100 | + clocks: | |
| 101 | + minItems: 3 | |
| 102 | + | |
| 103 | + clock-names: | |
| 104 | + minItems: 3 | |
| 105 | + | |
| 106 | + required: | |
| 107 | + - reg-names | |
| 108 | + - clock-names | |
| 109 | + | |
| 110 | +else: | |
| 111 | + properties: | |
| 112 | + reg: | |
| 113 | + maxItems: 1 | |
| 114 | + | |
| 115 | + reg-names: | |
| 116 | + maxItems: 1 | |
| 117 | + | |
| 118 | + clocks: | |
| 119 | + maxItems: 1 | |
| 120 | + | |
| 121 | + clock-names: | |
| 122 | + maxItems: 1 | |
| 123 | + | |
| 57 | 124 | additionalProperties: false |
| 58 | 125 | |
| 59 | 126 | examples: |
| 60 | 127 | - | |
| 61 | − #include <dt-bindings/clock/sun5i-ccu.h> | |
| 128 | + #include <dt-bindings/clock/sun50i-a64-ccu.h> | |
| 129 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 62 | 130 | |
| 63 | − mbus: dram-controller@1c01000 { | |
| 131 | + dram-controller@1c01000 { | |
| 64 | 132 | compatible = "allwinner,sun5i-a13-mbus"; |
| 65 | 133 | reg = <0x01c01000 0x1000>; |
| 66 | 134 | clocks = <&ccu CLK_MBUS>; |
| @@ -70,4 +138,21 @@ examples: · 3 unmodified lines | ||
| 70 | 138 | #interconnect-cells = <1>; |
| 71 | 139 | }; |
| 72 | 140 | |
| 141 | + - | | |
| 142 | + dram-controller@1c62000 { | |
| 143 | + compatible = "allwinner,sun50i-a64-mbus"; | |
| 144 | + reg = <0x01c62000 0x1000>, | |
| 145 | + <0x01c63000 0x1000>; | |
| 146 | + reg-names = "mbus", "dram"; | |
| 147 | + clocks = <&ccu CLK_MBUS>, | |
| 148 | + <&ccu CLK_DRAM>, | |
| 149 | + <&ccu CLK_BUS_DRAM>; | |
| 150 | + clock-names = "mbus", "dram", "bus"; | |
| 151 | + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 152 | + #address-cells = <1>; | |
| 153 | + #size-cells = <1>; | |
| 154 | + dma-ranges = <0x00000000 0x40000000 0xc0000000>; | |
| 155 | + #interconnect-cells = <1>; | |
| 156 | + }; | |
| 157 | + | |
| 73 | 158 | ... |
| @@ -36,6 +36,9 @@ properties: · 35 unmodified lines | ||
| 36 | 36 | - toradex,colibri_t20-iris |
| 37 | 37 | - const: toradex,colibri_t20 |
| 38 | 38 | - const: nvidia,tegra20 |
| 39 | + - items: | |
| 40 | + - const: asus,tf101 | |
| 41 | + - const: nvidia,tegra20 | |
| 39 | 42 | - items: |
| 40 | 43 | - const: acer,picasso |
| 41 | 44 | - const: nvidia,tegra20 |
| @@ -49,6 +52,18 @@ properties: · 7 unmodified lines | ||
| 49 | 52 | - nvidia,cardhu-a04 |
| 50 | 53 | - const: nvidia,cardhu |
| 51 | 54 | - const: nvidia,tegra30 |
| 55 | + - items: | |
| 56 | + - const: asus,tf201 | |
| 57 | + - const: nvidia,tegra30 | |
| 58 | + - items: | |
| 59 | + - const: asus,tf300t | |
| 60 | + - const: nvidia,tegra30 | |
| 61 | + - items: | |
| 62 | + - const: asus,tf300tg | |
| 63 | + - const: nvidia,tegra30 | |
| 64 | + - items: | |
| 65 | + - const: asus,tf700t | |
| 66 | + - const: nvidia,tegra30 | |
| 52 | 67 | - items: |
| 53 | 68 | - const: toradex,apalis_t30-eval |
| 54 | 69 | - const: toradex,apalis_t30 |
| @@ -74,8 +89,12 @@ properties: · 19 unmodified lines | ||
| 74 | 89 | - items: |
| 75 | 90 | - const: ouya,ouya |
| 76 | 91 | - const: nvidia,tegra30 |
| 92 | + - items: | |
| 93 | + - const: pegatron,chagall | |
| 94 | + - const: nvidia,tegra30 | |
| 77 | 95 | - items: |
| 78 | 96 | - enum: |
| 97 | + - asus,tf701t | |
| 79 | 98 | - nvidia,dalmore |
| 80 | 99 | - nvidia,roth |
| 81 | 100 | - nvidia,tn7 |
| @@ -108,14 +127,17 @@ properties: · 26 unmodified lines | ||
| 108 | 127 | - nvidia,p2571 |
| 109 | 128 | - nvidia,p2894-0050-a08 |
| 110 | 129 | - const: nvidia,tegra210 |
| 111 | − - items: | |
| 112 | − - enum: | |
| 113 | − - nvidia,p2771-0000 | |
| 114 | − - nvidia,p3509-0000+p3636-0001 | |
| 130 | + - description: Jetson TX2 Developer Kit | |
| 131 | + items: | |
| 132 | + - const: nvidia,p2771-0000 | |
| 115 | 133 | - const: nvidia,tegra186 |
| 116 | − - items: | |
| 117 | − - enum: | |
| 118 | − - nvidia,p2972-0000 | |
| 134 | + - description: Jetson TX2 NX Developer Kit | |
| 135 | + items: | |
| 136 | + - const: nvidia,p3509-0000+p3636-0001 | |
| 137 | + - const: nvidia,tegra186 | |
| 138 | + - description: Jetson AGX Xavier Developer Kit | |
| 139 | + items: | |
| 140 | + - const: nvidia,p2972-0000 | |
| 119 | 141 | - const: nvidia,tegra194 |
| 120 | 142 | - description: Jetson Xavier NX |
| 121 | 143 | items: |
| @@ -134,8 +156,16 @@ properties: · 12 unmodified lines | ||
| 134 | 156 | - const: nvidia,p3509-0000+p3668-0001 |
| 135 | 157 | - const: nvidia,tegra194 |
| 136 | 158 | - items: |
| 137 | − - enum: | |
| 138 | − - nvidia,tegra234-vdk | |
| 159 | + - const: nvidia,tegra234-vdk | |
| 160 | + - const: nvidia,tegra234 | |
| 161 | + - description: Jetson AGX Orin | |
| 162 | + items: | |
| 163 | + - const: nvidia,p3701-0000 | |
| 164 | + - const: nvidia,tegra234 | |
| 165 | + - description: Jetson AGX Orin Developer Kit | |
| 166 | + items: | |
| 167 | + - const: nvidia,p3737-0000+p3701-0000 | |
| 168 | + - const: nvidia,p3701-0000 | |
| 139 | 169 | - const: nvidia,tegra234 |
| 140 | 170 | |
| 141 | 171 | additionalProperties: true |
| @@ -1,133 +0,0 @@ | ||
| 1 | −NVIDIA Tegra Power Management Controller (PMC) | |
| 2 | − | |
| 3 | −Required properties: | |
| 4 | −- compatible: Should contain one of the following: | |
| 5 | − - "nvidia,tegra186-pmc": for Tegra186 | |
| 6 | − - "nvidia,tegra194-pmc": for Tegra194 | |
| 7 | − - "nvidia,tegra234-pmc": for Tegra234 | |
| 8 | −- reg: Must contain an (offset, length) pair of the register set for each | |
| 9 | − entry in reg-names. | |
| 10 | −- reg-names: Must include the following entries: | |
| 11 | − - "pmc" | |
| 12 | − - "wake" | |
| 13 | − - "aotag" | |
| 14 | − - "scratch" | |
| 15 | − - "misc" (Only for Tegra194 and later) | |
| 16 | − | |
| 17 | −Optional properties: | |
| 18 | −- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. | |
| 19 | −- interrupt-controller: Identifies the node as an interrupt controller. | |
| 20 | −- #interrupt-cells: Specifies the number of cells needed to encode an | |
| 21 | − interrupt source. The value must be 2. | |
| 22 | − | |
| 23 | −Example: | |
| 24 | − | |
| 25 | −SoC DTSI: | |
| 26 | − | |
| 27 | − pmc@c3600000 { | |
| 28 | − compatible = "nvidia,tegra186-pmc"; | |
| 29 | − reg = <0 0x0c360000 0 0x10000>, | |
| 30 | − <0 0x0c370000 0 0x10000>, | |
| 31 | − <0 0x0c380000 0 0x10000>, | |
| 32 | − <0 0x0c390000 0 0x10000>; | |
| 33 | − reg-names = "pmc", "wake", "aotag", "scratch"; | |
| 34 | − }; | |
| 35 | − | |
| 36 | −Board DTS: | |
| 37 | − | |
| 38 | − pmc@c360000 { | |
| 39 | − nvidia,invert-interrupt; | |
| 40 | − }; | |
| 41 | − | |
| 42 | −== Pad Control == | |
| 43 | − | |
| 44 | −On Tegra SoCs a pad is a set of pins which are configured as a group. | |
| 45 | −The pin grouping is a fixed attribute of the hardware. The PMC can be | |
| 46 | −used to set pad power state and signaling voltage. A pad can be either | |
| 47 | −in active or power down mode. The support for power state and signaling | |
| 48 | −voltage configuration varies depending on the pad in question. 3.3 V and | |
| 49 | −1.8 V signaling voltages are supported on pins where software | |
| 50 | −controllable signaling voltage switching is available. | |
| 51 | − | |
| 52 | −Pad configurations are described with pin configuration nodes which | |
| 53 | −are placed under the pmc node and they are referred to by the pinctrl | |
| 54 | −client properties. For more information see | |
| 55 | −Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. | |
| 56 | − | |
| 57 | −The following pads are present on Tegra186: | |
| 58 | −csia csib dsi mipi-bias | |
| 59 | −pex-clk-bias pex-clk3 pex-clk2 pex-clk1 | |
| 60 | −usb0 usb1 usb2 usb-bias | |
| 61 | −uart audio hsic dbg | |
| 62 | −hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv | |
| 63 | −sdmmc4 cam dsib dsic | |
| 64 | −dsid csic csid csie | |
| 65 | −dsif spi ufs dmic-hv | |
| 66 | −edp sdmmc1-hv sdmmc3-hv conn | |
| 67 | −audio-hv ao-hv | |
| 68 | − | |
| 69 | −Required pin configuration properties: | |
| 70 | − - pins: A list of strings, each of which contains the name of a pad | |
| 71 | − to be configured. | |
| 72 | − | |
| 73 | −Optional pin configuration properties: | |
| 74 | − - low-power-enable: Configure the pad into power down mode | |
| 75 | − - low-power-disable: Configure the pad into active mode | |
| 76 | − - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or | |
| 77 | − TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. | |
| 78 | − The values are defined in | |
| 79 | − include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. | |
| 80 | − | |
| 81 | −Note: The power state can be configured on all of the above pads except | |
| 82 | − for ao-hv. Following pads have software configurable signaling | |
| 83 | − voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, | |
| 84 | − ao-hv. | |
| 85 | − | |
| 86 | −Pad configuration state example: | |
| 87 | − pmc: pmc@7000e400 { | |
| 88 | − compatible = "nvidia,tegra186-pmc"; | |
| 89 | − reg = <0 0x0c360000 0 0x10000>, | |
| 90 | − <0 0x0c370000 0 0x10000>, | |
| 91 | − <0 0x0c380000 0 0x10000>, | |
| 92 | − <0 0x0c390000 0 0x10000>; | |
| 93 | − reg-names = "pmc", "wake", "aotag", "scratch"; | |
| 94 | − | |
| 95 | − ... | |
| 96 | − | |
| 97 | − sdmmc1_3v3: sdmmc1-3v3 { | |
| 98 | − pins = "sdmmc1-hv"; | |
| 99 | − power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; | |
| 100 | − }; | |
| 101 | − | |
| 102 | − sdmmc1_1v8: sdmmc1-1v8 { | |
| 103 | − pins = "sdmmc1-hv"; | |
| 104 | − power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; | |
| 105 | − }; | |
| 106 | − | |
| 107 | − hdmi_off: hdmi-off { | |
| 108 | − pins = "hdmi"; | |
| 109 | − low-power-enable; | |
| 110 | − } | |
| 111 | − | |
| 112 | − hdmi_on: hdmi-on { | |
| 113 | − pins = "hdmi"; | |
| 114 | − low-power-disable; | |
| 115 | − } | |
| 116 | − }; | |
| 117 | − | |
| 118 | −Pinctrl client example: | |
| 119 | − sdmmc1: sdhci@3400000 { | |
| 120 | − ... | |
| 121 | − pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; | |
| 122 | − pinctrl-0 = <&sdmmc1_3v3>; | |
| 123 | − pinctrl-1 = <&sdmmc1_1v8>; | |
| 124 | − }; | |
| 125 | − | |
| 126 | − ... | |
| 127 | − | |
| 128 | − sor0: sor@15540000 { | |
| 129 | − ... | |
| 130 | − pinctrl-0 = <&hdmi_off>; | |
| 131 | − pinctrl-1 = <&hdmi_on>; | |
| 132 | − pinctrl-names = "hdmi-on", "hdmi-off"; | |
| 133 | − }; | |
| @@ -0,0 +1,198 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra Power Management Controller (PMC) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +properties: | |
| 14 | + compatible: | |
| 15 | + enum: | |
| 16 | + - nvidia,tegra186-pmc | |
| 17 | + - nvidia,tegra194-pmc | |
| 18 | + - nvidia,tegra234-pmc | |
| 19 | + | |
| 20 | + reg: | |
| 21 | + minItems: 4 | |
| 22 | + maxItems: 5 | |
| 23 | + | |
| 24 | + reg-names: | |
| 25 | + minItems: 4 | |
| 26 | + items: | |
| 27 | + - const: pmc | |
| 28 | + - const: wake | |
| 29 | + - const: aotag | |
| 30 | + - const: scratch | |
| 31 | + - const: misc | |
| 32 | + | |
| 33 | + interrupt-controller: true | |
| 34 | + | |
| 35 | + "#interrupt-cells": | |
| 36 | + description: Specifies the number of cells needed to encode an | |
| 37 | + interrupt source. The value must be 2. | |
| 38 | + const: 2 | |
| 39 | + | |
| 40 | + nvidia,invert-interrupt: | |
| 41 | + description: If present, inverts the PMU interrupt signal. | |
| 42 | + $ref: /schemas/types.yaml#/definitions/flag | |
| 43 | + | |
| 44 | +if: | |
| 45 | + properties: | |
| 46 | + compatible: | |
| 47 | + contains: | |
| 48 | + const: nvidia,tegra186-pmc | |
| 49 | +then: | |
| 50 | + properties: | |
| 51 | + reg: | |
| 52 | + maxItems: 4 | |
| 53 | + | |
| 54 | + reg-names: | |
| 55 | + maxItems: 4 | |
| 56 | +else: | |
| 57 | + properties: | |
| 58 | + reg: | |
| 59 | + minItems: 5 | |
| 60 | + | |
| 61 | + reg-names: | |
| 62 | + minItems: 5 | |
| 63 | + | |
| 64 | +patternProperties: | |
| 65 | + "^[a-z0-9]+-[a-z0-9]+$": | |
| 66 | + if: | |
| 67 | + type: object | |
| 68 | + then: | |
| 69 | + description: | | |
| 70 | + These are pad configuration nodes. On Tegra SoCs a pad is a set of | |
| 71 | + pins which are configured as a group. The pin grouping is a fixed | |
| 72 | + attribute of the hardware. The PMC can be used to set pad power | |
| 73 | + state and signaling voltage. A pad can be either in active or | |
| 74 | + power down mode. The support for power state and signaling voltage | |
| 75 | + configuration varies depending on the pad in question. 3.3 V and | |
| 76 | + 1.8 V signaling voltages are supported on pins where software | |
| 77 | + controllable signaling voltage switching is available. | |
| 78 | + | |
| 79 | + Pad configurations are described with pin configuration nodes | |
| 80 | + which are placed under the pmc node and they are referred to by | |
| 81 | + the pinctrl client properties. For more information see | |
| 82 | + | |
| 83 | + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | |
| 84 | + | |
| 85 | + The following pads are present on Tegra186: | |
| 86 | + | |
| 87 | + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, | |
| 88 | + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, | |
| 89 | + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, | |
| 90 | + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, | |
| 91 | + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv | |
| 92 | + | |
| 93 | + The following pads are present on Tegra194: | |
| 94 | + | |
| 95 | + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, | |
| 96 | + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, | |
| 97 | + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, | |
| 98 | + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, | |
| 99 | + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, | |
| 100 | + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, | |
| 101 | + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, | |
| 102 | + audio-hv, ao-hv | |
| 103 | + | |
| 104 | + properties: | |
| 105 | + pins: | |
| 106 | + $ref: /schemas/types.yaml#/definitions/string | |
| 107 | + description: Must contain the name of the pad(s) to be | |
| 108 | + configured. | |
| 109 | + | |
| 110 | + low-power-enable: | |
| 111 | + description: Configure the pad into power down mode. | |
| 112 | + $ref: /schemas/types.yaml#/definitions/flag | |
| 113 | + | |
| 114 | + low-power-disable: | |
| 115 | + description: Configure the pad into active mode. | |
| 116 | + $ref: /schemas/types.yaml#/definitions/flag | |
| 117 | + | |
| 118 | + power-source: | |
| 119 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 120 | + description: | | |
| 121 | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or | |
| 122 | + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling | |
| 123 | + voltages. | |
| 124 | + | |
| 125 | + The values are defined in | |
| 126 | + | |
| 127 | + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | |
| 128 | + | |
| 129 | + The power state can be configured on all of the above pads | |
| 130 | + except for ao-hv. Following pads have software configurable | |
| 131 | + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, | |
| 132 | + audio-hv, ao-hv. | |
| 133 | + | |
| 134 | + phandle: true | |
| 135 | + | |
| 136 | + required: | |
| 137 | + - pins | |
| 138 | + | |
| 139 | + additionalProperties: false | |
| 140 | + | |
| 141 | +required: | |
| 142 | + - compatible | |
| 143 | + - reg | |
| 144 | + - reg-names | |
| 145 | + | |
| 146 | +additionalProperties: false | |
| 147 | + | |
| 148 | +dependencies: | |
| 149 | + interrupt-controller: ['#interrupt-cells'] | |
| 150 | + "#interrupt-cells": | |
| 151 | + required: | |
| 152 | + - interrupt-controller | |
| 153 | + | |
| 154 | +examples: | |
| 155 | + - | | |
| 156 | + #include <dt-bindings/clock/tegra186-clock.h> | |
| 157 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 158 | + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> | |
| 159 | + #include <dt-bindings/memory/tegra186-mc.h> | |
| 160 | + #include <dt-bindings/reset/tegra186-reset.h> | |
| 161 | + | |
| 162 | + pmc@c3600000 { | |
| 163 | + compatible = "nvidia,tegra186-pmc"; | |
| 164 | + reg = <0x0c360000 0x10000>, | |
| 165 | + <0x0c370000 0x10000>, | |
| 166 | + <0x0c380000 0x10000>, | |
| 167 | + <0x0c390000 0x10000>; | |
| 168 | + reg-names = "pmc", "wake", "aotag", "scratch"; | |
| 169 | + nvidia,invert-interrupt; | |
| 170 | + | |
| 171 | + sdmmc1_3v3: sdmmc1-3v3 { | |
| 172 | + pins = "sdmmc1-hv"; | |
| 173 | + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; | |
| 174 | + }; | |
| 175 | + | |
| 176 | + sdmmc1_1v8: sdmmc1-1v8 { | |
| 177 | + pins = "sdmmc1-hv"; | |
| 178 | + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; | |
| 179 | + }; | |
| 180 | + }; | |
| 181 | + | |
| 182 | + sdmmc1: mmc@3400000 { | |
| 183 | + compatible = "nvidia,tegra186-sdhci"; | |
| 184 | + reg = <0x03400000 0x10000>; | |
| 185 | + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 186 | + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, | |
| 187 | + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; | |
| 188 | + clock-names = "sdhci", "tmclk"; | |
| 189 | + resets = <&bpmp TEGRA186_RESET_SDMMC1>; | |
| 190 | + reset-names = "sdhci"; | |
| 191 | + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, | |
| 192 | + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; | |
| 193 | + interconnect-names = "dma-mem", "write"; | |
| 194 | + iommus = <&smmu TEGRA186_SID_SDMMC1>; | |
| 195 | + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; | |
| 196 | + pinctrl-0 = <&sdmmc1_3v3>; | |
| 197 | + pinctrl-1 = <&sdmmc1_1v8>; | |
| 198 | + }; | |
| @@ -53,6 +53,12 @@ properties: · 52 unmodified lines | ||
| 53 | 53 | - ti,am642-sk |
| 54 | 54 | - const: ti,am642 |
| 55 | 55 | |
| 56 | + - description: K3 J721s2 SoC | |
| 57 | + items: | |
| 58 | + - enum: | |
| 59 | + - ti,j721s2-evm | |
| 60 | + - const: ti,j721s2 | |
| 61 | + | |
| 56 | 62 | additionalProperties: true |
| 57 | 63 | |
| 58 | 64 | ... |
| @@ -0,0 +1,68 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Shared Peripherals Bus Interface | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Shawn Guo <shawnguo@kernel.org> | |
| 11 | + | |
| 12 | +description: | | |
| 13 | + A simple bus enabling access to shared peripherals. | |
| 14 | + | |
| 15 | + The "spba-bus" follows the "simple-bus" set of properties, as | |
| 16 | + specified in the Devicetree Specification. It is an extension of | |
| 17 | + "simple-bus" because the SDMA controller uses this compatible flag to | |
| 18 | + determine which peripherals are available to it and the range over which | |
| 19 | + the SDMA can access. There are no special clocks for the bus, because | |
| 20 | + the SDMA controller itself has its interrupt and clock assignments. | |
| 21 | + | |
| 22 | +select: | |
| 23 | + properties: | |
| 24 | + compatible: | |
| 25 | + contains: | |
| 26 | + const: fsl,spba-bus | |
| 27 | + required: | |
| 28 | + - compatible | |
| 29 | + | |
| 30 | +properties: | |
| 31 | + $nodename: | |
| 32 | + pattern: "^spba-bus(@[0-9a-f]+)?$" | |
| 33 | + | |
| 34 | + compatible: | |
| 35 | + items: | |
| 36 | + - const: fsl,spba-bus | |
| 37 | + - const: simple-bus | |
| 38 | + | |
| 39 | + '#address-cells': | |
| 40 | + enum: [ 1, 2 ] | |
| 41 | + | |
| 42 | + '#size-cells': | |
| 43 | + enum: [ 1, 2 ] | |
| 44 | + | |
| 45 | + reg: | |
| 46 | + maxItems: 1 | |
| 47 | + | |
| 48 | + ranges: true | |
| 49 | + | |
| 50 | +required: | |
| 51 | + - compatible | |
| 52 | + - '#address-cells' | |
| 53 | + - '#size-cells' | |
| 54 | + - reg | |
| 55 | + - ranges | |
| 56 | + | |
| 57 | +additionalProperties: | |
| 58 | + type: object | |
| 59 | + | |
| 60 | +examples: | |
| 61 | + - | | |
| 62 | + spba-bus@30000000 { | |
| 63 | + compatible = "fsl,spba-bus", "simple-bus"; | |
| 64 | + #address-cells = <1>; | |
| 65 | + #size-cells = <1>; | |
| 66 | + reg = <0x30000000 0x100000>; | |
| 67 | + ranges; | |
| 68 | + }; | |
| @@ -48,6 +48,11 @@ Optional properties: · 47 unmodified lines | ||
| 48 | 48 | devices, the presence of this property indicates that |
| 49 | 49 | the weim bus should operate in Burst Clock Mode. |
| 50 | 50 | |
| 51 | + - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. | |
| 52 | + Without this option Burst Clock will output clock | |
| 53 | + only when necessary. This takes effect only if | |
| 54 | + "fsl,burst-clk-enable" is set. | |
| 55 | + | |
| 51 | 56 | Timing property for child nodes. It is mandatory, not optional. |
| 52 | 57 | |
| 53 | 58 | - fsl,weim-cs-timing: The timing array, contains timing values for the |
| @@ -42,6 +42,36 @@ properties: · 41 unmodified lines | ||
| 42 | 42 | "#reset-cells": |
| 43 | 43 | const: 1 |
| 44 | 44 | |
| 45 | +patternProperties: | |
| 46 | + "^(sclk)|(pll-[cem])$": | |
| 47 | + type: object | |
| 48 | + properties: | |
| 49 | + compatible: | |
| 50 | + enum: | |
| 51 | + - nvidia,tegra20-sclk | |
| 52 | + - nvidia,tegra30-sclk | |
| 53 | + - nvidia,tegra30-pllc | |
| 54 | + - nvidia,tegra30-plle | |
| 55 | + - nvidia,tegra30-pllm | |
| 56 | + | |
| 57 | + operating-points-v2: true | |
| 58 | + | |
| 59 | + clocks: | |
| 60 | + items: | |
| 61 | + - description: node's clock | |
| 62 | + | |
| 63 | + power-domains: | |
| 64 | + maxItems: 1 | |
| 65 | + description: phandle to the core SoC power domain | |
| 66 | + | |
| 67 | + required: | |
| 68 | + - compatible | |
| 69 | + - operating-points-v2 | |
| 70 | + - clocks | |
| 71 | + - power-domains | |
| 72 | + | |
| 73 | + additionalProperties: false | |
| 74 | + | |
| 45 | 75 | required: |
| 46 | 76 | - compatible |
| 47 | 77 | - reg |
| @@ -59,6 +89,13 @@ examples: · 11 unmodified lines | ||
| 59 | 89 | reg = <0x60006000 0x1000>; |
| 60 | 90 | #clock-cells = <1>; |
| 61 | 91 | #reset-cells = <1>; |
| 92 | + | |
| 93 | + sclk { | |
| 94 | + compatible = "nvidia,tegra20-sclk"; | |
| 95 | + operating-points-v2 = <&opp_table>; | |
| 96 | + clocks = <&tegra_car TEGRA20_CLK_SCLK>; | |
| 97 | + power-domains = <&domain>; | |
| 98 | + }; | |
| 62 | 99 | }; |
| 63 | 100 | |
| 64 | 101 | usb-controller@c5004000 { |
| @@ -0,0 +1,80 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Qualcomm Global Clock & Reset Controller Binding for SDX65 | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Vamsi krishna Lanka <quic_vamslank@quicinc.com> | |
| 11 | + | |
| 12 | +description: | | |
| 13 | + Qualcomm global clock control module which supports the clocks, resets and | |
| 14 | + power domains on SDX65 | |
| 15 | + | |
| 16 | + See also: | |
| 17 | + - dt-bindings/clock/qcom,gcc-sdx65.h | |
| 18 | + | |
| 19 | +properties: | |
| 20 | + compatible: | |
| 21 | + const: qcom,gcc-sdx65 | |
| 22 | + | |
| 23 | + reg: | |
| 24 | + maxItems: 1 | |
| 25 | + | |
| 26 | + clocks: | |
| 27 | + items: | |
| 28 | + - description: Board XO source | |
| 29 | + - description: Board active XO source | |
| 30 | + - description: Sleep clock source | |
| 31 | + - description: PCIE Pipe clock source | |
| 32 | + - description: USB3 phy wrapper pipe clock source | |
| 33 | + - description: PLL test clock source (Optional clock) | |
| 34 | + minItems: 5 | |
| 35 | + | |
| 36 | + clock-names: | |
| 37 | + items: | |
| 38 | + - const: bi_tcxo | |
| 39 | + - const: bi_tcxo_ao | |
| 40 | + - const: sleep_clk | |
| 41 | + - const: pcie_pipe_clk | |
| 42 | + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk | |
| 43 | + - const: core_bi_pll_test_se # Optional clock | |
| 44 | + minItems: 5 | |
| 45 | + | |
| 46 | + '#clock-cells': | |
| 47 | + const: 1 | |
| 48 | + | |
| 49 | + '#reset-cells': | |
| 50 | + const: 1 | |
| 51 | + | |
| 52 | + '#power-domain-cells': | |
| 53 | + const: 1 | |
| 54 | + | |
| 55 | +required: | |
| 56 | + - compatible | |
| 57 | + - reg | |
| 58 | + - clocks | |
| 59 | + - clock-names | |
| 60 | + - '#clock-cells' | |
| 61 | + - '#reset-cells' | |
| 62 | + - '#power-domain-cells' | |
| 63 | + | |
| 64 | +additionalProperties: false | |
| 65 | + | |
| 66 | +examples: | |
| 67 | + - | | |
| 68 | + #include <dt-bindings/clock/qcom,rpmh.h> | |
| 69 | + clock-controller@100000 { | |
| 70 | + compatible = "qcom,gcc-sdx65"; | |
| 71 | + reg = <0x100000 0x1f7400>; | |
| 72 | + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, | |
| 73 | + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; | |
| 74 | + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", | |
| 75 | + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; | |
| 76 | + #clock-cells = <1>; | |
| 77 | + #reset-cells = <1>; | |
| 78 | + #power-domain-cells = <1>; | |
| 79 | + }; | |
| 80 | +... | |
| @@ -0,0 +1,85 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Qualcomm Global Clock & Reset Controller Binding for SM8450 | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Vinod Koul <vkoul@kernel.org> | |
| 11 | + | |
| 12 | +description: | | |
| 13 | + Qualcomm global clock control module which supports the clocks, resets and | |
| 14 | + power domains on SM8450 | |
| 15 | + | |
| 16 | + See also: | |
| 17 | + - dt-bindings/clock/qcom,gcc-sm8450.h | |
| 18 | + | |
| 19 | +properties: | |
| 20 | + compatible: | |
| 21 | + const: qcom,gcc-sm8450 | |
| 22 | + | |
| 23 | + clocks: | |
| 24 | + items: | |
| 25 | + - description: Board XO source | |
| 26 | + - description: Sleep clock source | |
| 27 | + - description: PCIE 0 Pipe clock source (Optional clock) | |
| 28 | + - description: PCIE 1 Pipe clock source (Optional clock) | |
| 29 | + - description: PCIE 1 Phy Auxillary clock source (Optional clock) | |
| 30 | + - description: UFS Phy Rx symbol 0 clock source (Optional clock) | |
| 31 | + - description: UFS Phy Rx symbol 1 clock source (Optional clock) | |
| 32 | + - description: UFS Phy Tx symbol 0 clock source (Optional clock) | |
| 33 | + - description: USB3 Phy wrapper pipe clock source (Optional clock) | |
| 34 | + minItems: 2 | |
| 35 | + | |
| 36 | + clock-names: | |
| 37 | + items: | |
| 38 | + - const: bi_tcxo | |
| 39 | + - const: sleep_clk | |
| 40 | + - const: pcie_0_pipe_clk # Optional clock | |
| 41 | + - const: pcie_1_pipe_clk # Optional clock | |
| 42 | + - const: pcie_1_phy_aux_clk # Optional clock | |
| 43 | + - const: ufs_phy_rx_symbol_0_clk # Optional clock | |
| 44 | + - const: ufs_phy_rx_symbol_1_clk # Optional clock | |
| 45 | + - const: ufs_phy_tx_symbol_0_clk # Optional clock | |
| 46 | + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock | |
| 47 | + minItems: 2 | |
| 48 | + | |
| 49 | + '#clock-cells': | |
| 50 | + const: 1 | |
| 51 | + | |
| 52 | + '#reset-cells': | |
| 53 | + const: 1 | |
| 54 | + | |
| 55 | + '#power-domain-cells': | |
| 56 | + const: 1 | |
| 57 | + | |
| 58 | + reg: | |
| 59 | + maxItems: 1 | |
| 60 | + | |
| 61 | +required: | |
| 62 | + - compatible | |
| 63 | + - reg | |
| 64 | + - clocks | |
| 65 | + - clock-names | |
| 66 | + - '#clock-cells' | |
| 67 | + - '#reset-cells' | |
| 68 | + - '#power-domain-cells' | |
| 69 | + | |
| 70 | +additionalProperties: false | |
| 71 | + | |
| 72 | +examples: | |
| 73 | + - | | |
| 74 | + #include <dt-bindings/clock/qcom,rpmh.h> | |
| 75 | + clock-controller@100000 { | |
| 76 | + compatible = "qcom,gcc-sm8450"; | |
| 77 | + reg = <0x00100000 0x001f4200>; | |
| 78 | + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; | |
| 79 | + clock-names = "bi_tcxo", "sleep_clk"; | |
| 80 | + #clock-cells = <1>; | |
| 81 | + #reset-cells = <1>; | |
| 82 | + #power-domain-cells = <1>; | |
| 83 | + }; | |
| 84 | + | |
| 85 | +... | |
| @@ -44,6 +44,16 @@ properties: · 43 unmodified lines | ||
| 44 | 44 | - const: ahb |
| 45 | 45 | - const: mod |
| 46 | 46 | |
| 47 | + dmas: | |
| 48 | + items: | |
| 49 | + - description: RX DMA Channel | |
| 50 | + - description: TX DMA Channel | |
| 51 | + | |
| 52 | + dma-names: | |
| 53 | + items: | |
| 54 | + - const: rx | |
| 55 | + - const: tx | |
| 56 | + | |
| 47 | 57 | resets: |
| 48 | 58 | maxItems: 1 |
| 49 | 59 | |
| @@ -19,6 +19,19 @@ Required properties: · 18 unmodified lines | ||
| 19 | 19 | See ../reset/reset.txt for details. |
| 20 | 20 | - reset-names: Must include the following entries: |
| 21 | 21 | - host1x |
| 22 | + - mc | |
| 23 | + | |
| 24 | +Optional properties: | |
| 25 | +- operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 26 | + - power-domains: Phandle to HEG or core power domain. | |
| 27 | + | |
| 28 | +For each opp entry in 'operating-points-v2' table of host1x and its modules: | |
| 29 | +- opp-supported-hw: One bitfield indicating: | |
| 30 | + On Tegra20: SoC process ID mask | |
| 31 | + On Tegra30+: SoC speedo ID mask | |
| 32 | + | |
| 33 | + A bitwise AND is performed against the value and if any bit | |
| 34 | + matches, the OPP gets enabled. | |
| 22 | 35 | |
| 23 | 36 | Each host1x client module having to perform DMA through the Memory Controller |
| 24 | 37 | should have the interconnect endpoints set to the Memory Client and External |
| @@ -45,6 +58,8 @@ of the following host1x client modules: · 20 unmodified lines | ||
| 45 | 58 | - interconnect-names: Must include name of the interconnect path for each |
| 46 | 59 | interconnect entry. Consult TRM documentation for information about |
| 47 | 60 | available memory clients, see MEMORY CONTROLLER section. |
| 61 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 62 | + - power-domains: Phandle to MPE power domain. | |
| 48 | 63 | |
| 49 | 64 | - vi: video input |
| 50 | 65 | |
| @@ -128,6 +143,8 @@ of the following host1x client modules: · 77 unmodified lines | ||
| 128 | 143 | - interconnect-names: Must include name of the interconnect path for each |
| 129 | 144 | interconnect entry. Consult TRM documentation for information about |
| 130 | 145 | available memory clients, see MEMORY CONTROLLER section. |
| 146 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 147 | + - power-domains: Phandle to VENC power domain. | |
| 131 | 148 | |
| 132 | 149 | - epp: encoder pre-processor |
| 133 | 150 | |
| @@ -147,6 +164,8 @@ of the following host1x client modules: · 13 unmodified lines | ||
| 147 | 164 | - interconnect-names: Must include name of the interconnect path for each |
| 148 | 165 | interconnect entry. Consult TRM documentation for information about |
| 149 | 166 | available memory clients, see MEMORY CONTROLLER section. |
| 167 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 168 | + - power-domains: Phandle to HEG or core power domain. | |
| 150 | 169 | |
| 151 | 170 | - isp: image signal processor |
| 152 | 171 | |
| @@ -166,6 +185,7 @@ of the following host1x client modules: · 13 unmodified lines | ||
| 166 | 185 | - interconnect-names: Must include name of the interconnect path for each |
| 167 | 186 | interconnect entry. Consult TRM documentation for information about |
| 168 | 187 | available memory clients, see MEMORY CONTROLLER section. |
| 188 | + - power-domains: Phandle to VENC or core power domain. | |
| 169 | 189 | |
| 170 | 190 | - gr2d: 2D graphics engine |
| 171 | 191 | |
| @@ -179,12 +199,15 @@ of the following host1x client modules: · 7 unmodified lines | ||
| 179 | 199 | See ../reset/reset.txt for details. |
| 180 | 200 | - reset-names: Must include the following entries: |
| 181 | 201 | - 2d |
| 202 | + - mc | |
| 182 | 203 | |
| 183 | 204 | Optional properties: |
| 184 | 205 | - interconnects: Must contain entry for the GR2D memory clients. |
| 185 | 206 | - interconnect-names: Must include name of the interconnect path for each |
| 186 | 207 | interconnect entry. Consult TRM documentation for information about |
| 187 | 208 | available memory clients, see MEMORY CONTROLLER section. |
| 209 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 210 | + - power-domains: Phandle to HEG or core power domain. | |
| 188 | 211 | |
| 189 | 212 | - gr3d: 3D graphics engine |
| 190 | 213 | |
| @@ -203,12 +226,16 @@ of the following host1x client modules: · 12 unmodified lines | ||
| 203 | 226 | - reset-names: Must include the following entries: |
| 204 | 227 | - 3d |
| 205 | 228 | - 3d2 (Only required on SoCs with two 3D clocks) |
| 229 | + - mc | |
| 230 | + - mc2 (Only required on SoCs with two 3D clocks) | |
| 206 | 231 | |
| 207 | 232 | Optional properties: |
| 208 | 233 | - interconnects: Must contain entry for the GR3D memory clients. |
| 209 | 234 | - interconnect-names: Must include name of the interconnect path for each |
| 210 | 235 | interconnect entry. Consult TRM documentation for information about |
| 211 | 236 | available memory clients, see MEMORY CONTROLLER section. |
| 237 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 238 | + - power-domains: Phandles to 3D or core power domain. | |
| 212 | 239 | |
| 213 | 240 | - dc: display controller |
| 214 | 241 | |
| @@ -241,6 +268,8 @@ of the following host1x client modules: · 26 unmodified lines | ||
| 241 | 268 | - interconnect-names: Must include name of the interconnect path for each |
| 242 | 269 | interconnect entry. Consult TRM documentation for information about |
| 243 | 270 | available memory clients, see MEMORY CONTROLLER section. |
| 271 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 272 | + - power-domains: Phandle to core power domain. | |
| 244 | 273 | |
| 245 | 274 | - hdmi: High Definition Multimedia Interface |
| 246 | 275 | |
| @@ -267,6 +296,7 @@ of the following host1x client modules: · 20 unmodified lines | ||
| 267 | 296 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
| 268 | 297 | - nvidia,edid: supplies a binary EDID blob |
| 269 | 298 | - nvidia,panel: phandle of a display panel |
| 299 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 270 | 300 | |
| 271 | 301 | - tvo: TV encoder output |
| 272 | 302 | |
| @@ -277,6 +307,10 @@ of the following host1x client modules: · 4 unmodified lines | ||
| 277 | 307 | - clocks: Must contain one entry, for the module clock. |
| 278 | 308 | See ../clocks/clock-bindings.txt for details. |
| 279 | 309 | |
| 310 | + Optional properties: | |
| 311 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 312 | + - power-domains: Phandle to core power domain. | |
| 313 | + | |
| 280 | 314 | - dsi: display serial interface |
| 281 | 315 | |
| 282 | 316 | Required properties: |
| @@ -305,6 +339,7 @@ of the following host1x client modules: · 22 unmodified lines | ||
| 305 | 339 | - nvidia,panel: phandle of a display panel |
| 306 | 340 | - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang |
| 307 | 341 | up with in order to support up to 8 data lanes |
| 342 | + - operating-points-v2: See ../bindings/opp/opp.txt for details. | |
| 308 | 343 | |
| 309 | 344 | - sor: serial output resource |
| 310 | 345 | |
| @@ -408,6 +443,8 @@ Example: · 97 unmodified lines | ||
| 408 | 443 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
| 409 | 444 | resets = <&tegra_car 28>; |
| 410 | 445 | reset-names = "host1x"; |
| 446 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 447 | + power-domains = <&domain>; | |
| 411 | 448 | |
| 412 | 449 | #address-cells = <1>; |
| 413 | 450 | #size-cells = <1>; |
| @@ -421,6 +458,8 @@ Example: · 7 unmodified lines | ||
| 421 | 458 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
| 422 | 459 | resets = <&tegra_car 60>; |
| 423 | 460 | reset-names = "mpe"; |
| 461 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 462 | + power-domains = <&domain>; | |
| 424 | 463 | }; |
| 425 | 464 | |
| 426 | 465 | vi@54080000 { |
| @@ -429,6 +468,7 @@ Example: · 2 unmodified lines | ||
| 429 | 468 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 430 | 469 | assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; |
| 431 | 470 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; |
| 471 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 432 | 472 | |
| 433 | 473 | clocks = <&tegra_car TEGRA210_CLK_VI>; |
| 434 | 474 | power-domains = <&pd_venc>; |
| @@ -510,6 +550,8 @@ Example: · 75 unmodified lines | ||
| 510 | 550 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
| 511 | 551 | resets = <&tegra_car 19>; |
| 512 | 552 | reset-names = "epp"; |
| 553 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 554 | + power-domains = <&domain>; | |
| 513 | 555 | }; |
| 514 | 556 | |
| 515 | 557 | isp { |
| @@ -528,6 +570,8 @@ Example: · 12 unmodified lines | ||
| 528 | 570 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
| 529 | 571 | resets = <&tegra_car 21>; |
| 530 | 572 | reset-names = "2d"; |
| 573 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 574 | + power-domains = <&domain>; | |
| 531 | 575 | }; |
| 532 | 576 | |
| 533 | 577 | gr3d { |
| @@ -536,6 +580,8 @@ Example: · 2 unmodified lines | ||
| 536 | 580 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
| 537 | 581 | resets = <&tegra_car 24>; |
| 538 | 582 | reset-names = "3d"; |
| 583 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 584 | + power-domains = <&domain>; | |
| 539 | 585 | }; |
| 540 | 586 | |
| 541 | 587 | dc@54200000 { |
| @@ -547,6 +593,8 @@ Example: · 5 unmodified lines | ||
| 547 | 593 | clock-names = "dc", "parent"; |
| 548 | 594 | resets = <&tegra_car 27>; |
| 549 | 595 | reset-names = "dc"; |
| 596 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 597 | + power-domains = <&domain>; | |
| 550 | 598 | |
| 551 | 599 | interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, |
| 552 | 600 | <&mc TEGRA20_MC_DISPLAY0B &emc>, |
| @@ -571,6 +619,8 @@ Example: · 18 unmodified lines | ||
| 571 | 619 | clock-names = "dc", "parent"; |
| 572 | 620 | resets = <&tegra_car 26>; |
| 573 | 621 | reset-names = "dc"; |
| 622 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 623 | + power-domains = <&domain>; | |
| 574 | 624 | |
| 575 | 625 | interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, |
| 576 | 626 | <&mc TEGRA20_MC_DISPLAY0BB &emc>, |
| @@ -596,6 +646,7 @@ Example: · 19 unmodified lines | ||
| 596 | 646 | resets = <&tegra_car 51>; |
| 597 | 647 | reset-names = "hdmi"; |
| 598 | 648 | status = "disabled"; |
| 649 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 599 | 650 | }; |
| 600 | 651 | |
| 601 | 652 | tvo { |
| @@ -604,6 +655,7 @@ Example: · 2 unmodified lines | ||
| 604 | 655 | interrupts = <0 76 0x04>; |
| 605 | 656 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
| 606 | 657 | status = "disabled"; |
| 658 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 607 | 659 | }; |
| 608 | 660 | |
| 609 | 661 | dsi { |
| @@ -615,6 +667,7 @@ Example: · 5 unmodified lines | ||
| 615 | 667 | resets = <&tegra_car 48>; |
| 616 | 668 | reset-names = "dsi"; |
| 617 | 669 | status = "disabled"; |
| 670 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 618 | 671 | }; |
| 619 | 672 | }; |
| 620 | 673 | |
| @@ -1,107 +0,0 @@ | ||
| 1 | −NVIDIA Tegra Boot and Power Management Processor (BPMP) | |
| 2 | − | |
| 3 | −The BPMP is a specific processor in Tegra chip, which is designed for | |
| 4 | −booting process handling and offloading the power management, clock | |
| 5 | −management, and reset control tasks from the CPU. The binding document | |
| 6 | −defines the resources that would be used by the BPMP firmware driver, | |
| 7 | −which can create the interprocessor communication (IPC) between the CPU | |
| 8 | −and BPMP. | |
| 9 | − | |
| 10 | −Required properties: | |
| 11 | −- compatible | |
| 12 | − Array of strings | |
| 13 | − One of: | |
| 14 | − - "nvidia,tegra186-bpmp" | |
| 15 | −- mboxes : The phandle of mailbox controller and the mailbox specifier. | |
| 16 | −- shmem : List of the phandle of the TX and RX shared memory area that | |
| 17 | − the IPC between CPU and BPMP is based on. | |
| 18 | −- #clock-cells : Should be 1. | |
| 19 | −- #power-domain-cells : Should be 1. | |
| 20 | −- #reset-cells : Should be 1. | |
| 21 | − | |
| 22 | −This node is a mailbox consumer. See the following files for details of | |
| 23 | −the mailbox subsystem, and the specifiers implemented by the relevant | |
| 24 | −provider(s): | |
| 25 | − | |
| 26 | −- .../mailbox/mailbox.txt | |
| 27 | −- .../mailbox/nvidia,tegra186-hsp.txt | |
| 28 | − | |
| 29 | −This node is a clock, power domain, and reset provider. See the following | |
| 30 | −files for general documentation of those features, and the specifiers | |
| 31 | −implemented by this node: | |
| 32 | − | |
| 33 | −- .../clock/clock-bindings.txt | |
| 34 | −- <dt-bindings/clock/tegra186-clock.h> | |
| 35 | −- ../power/power-domain.yaml | |
| 36 | −- <dt-bindings/power/tegra186-powergate.h> | |
| 37 | −- .../reset/reset.txt | |
| 38 | −- <dt-bindings/reset/tegra186-reset.h> | |
| 39 | − | |
| 40 | −The BPMP implements some services which must be represented by separate nodes. | |
| 41 | −For example, it can provide access to certain I2C controllers, and the I2C | |
| 42 | −bindings represent each I2C controller as a device tree node. Such nodes should | |
| 43 | −be nested directly inside the main BPMP node. | |
| 44 | − | |
| 45 | −Software can determine whether a child node of the BPMP node represents a device | |
| 46 | −by checking for a compatible property. Any node with a compatible property | |
| 47 | −represents a device that can be instantiated. Nodes without a compatible | |
| 48 | −property may be used to provide configuration information regarding the BPMP | |
| 49 | −itself, although no such configuration nodes are currently defined by this | |
| 50 | −binding. | |
| 51 | − | |
| 52 | −The BPMP firmware defines no single global name-/numbering-space for such | |
| 53 | −services. Put another way, the numbering scheme for I2C buses is distinct from | |
| 54 | −the numbering scheme for any other service the BPMP may provide (e.g. a future | |
| 55 | −hypothetical SPI bus service). As such, child device nodes will have no reg | |
| 56 | −property, and the BPMP node will have no #address-cells or #size-cells property. | |
| 57 | − | |
| 58 | −The shared memory bindings for BPMP | |
| 59 | −----------------------------------- | |
| 60 | − | |
| 61 | −The shared memory area for the IPC TX and RX between CPU and BPMP are | |
| 62 | −predefined and work on top of sysram, which is an SRAM inside the chip. | |
| 63 | − | |
| 64 | −See ".../sram/sram.txt" for the bindings. | |
| 65 | − | |
| 66 | −Example: | |
| 67 | − | |
| 68 | −hsp_top0: hsp@3c00000 { | |
| 69 | − ... | |
| 70 | − #mbox-cells = <2>; | |
| 71 | −}; | |
| 72 | − | |
| 73 | −sysram@30000000 { | |
| 74 | − compatible = "nvidia,tegra186-sysram", "mmio-sram"; | |
| 75 | − reg = <0x0 0x30000000 0x0 0x50000>; | |
| 76 | − #address-cells = <2>; | |
| 77 | − #size-cells = <2>; | |
| 78 | − ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; | |
| 79 | − | |
| 80 | − cpu_bpmp_tx: shmem@4e000 { | |
| 81 | − compatible = "nvidia,tegra186-bpmp-shmem"; | |
| 82 | − reg = <0x0 0x4e000 0x0 0x1000>; | |
| 83 | − label = "cpu-bpmp-tx"; | |
| 84 | − pool; | |
| 85 | − }; | |
| 86 | − | |
| 87 | − cpu_bpmp_rx: shmem@4f000 { | |
| 88 | − compatible = "nvidia,tegra186-bpmp-shmem"; | |
| 89 | − reg = <0x0 0x4f000 0x0 0x1000>; | |
| 90 | − label = "cpu-bpmp-rx"; | |
| 91 | − pool; | |
| 92 | − }; | |
| 93 | −}; | |
| 94 | − | |
| 95 | −bpmp { | |
| 96 | − compatible = "nvidia,tegra186-bpmp"; | |
| 97 | − mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; | |
| 98 | − shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; | |
| 99 | − #clock-cells = <1>; | |
| 100 | − #power-domain-cells = <1>; | |
| 101 | − #reset-cells = <1>; | |
| 102 | − | |
| 103 | − i2c { | |
| 104 | − compatible = "..."; | |
| 105 | − ... | |
| 106 | − }; | |
| 107 | −}; | |
| @@ -0,0 +1,186 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra Boot and Power Management Processor (BPMP) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: | | |
| 14 | + The BPMP is a specific processor in Tegra chip, which is designed for | |
| 15 | + booting process handling and offloading the power management, clock | |
| 16 | + management, and reset control tasks from the CPU. The binding document | |
| 17 | + defines the resources that would be used by the BPMP firmware driver, | |
| 18 | + which can create the interprocessor communication (IPC) between the | |
| 19 | + CPU and BPMP. | |
| 20 | + | |
| 21 | + This node is a mailbox consumer. See the following files for details | |
| 22 | + of the mailbox subsystem, and the specifiers implemented by the | |
| 23 | + relevant provider(s): | |
| 24 | + | |
| 25 | + - .../mailbox/mailbox.txt | |
| 26 | + - .../mailbox/nvidia,tegra186-hsp.yaml | |
| 27 | + | |
| 28 | + This node is a clock, power domain, and reset provider. See the | |
| 29 | + following files for general documentation of those features, and the | |
| 30 | + specifiers implemented by this node: | |
| 31 | + | |
| 32 | + - .../clock/clock-bindings.txt | |
| 33 | + - <dt-bindings/clock/tegra186-clock.h> | |
| 34 | + - ../power/power-domain.yaml | |
| 35 | + - <dt-bindings/power/tegra186-powergate.h> | |
| 36 | + - .../reset/reset.txt | |
| 37 | + - <dt-bindings/reset/tegra186-reset.h> | |
| 38 | + | |
| 39 | + The BPMP implements some services which must be represented by | |
| 40 | + separate nodes. For example, it can provide access to certain I2C | |
| 41 | + controllers, and the I2C bindings represent each I2C controller as a | |
| 42 | + device tree node. Such nodes should be nested directly inside the main | |
| 43 | + BPMP node. | |
| 44 | + | |
| 45 | + Software can determine whether a child node of the BPMP node | |
| 46 | + represents a device by checking for a compatible property. Any node | |
| 47 | + with a compatible property represents a device that can be | |
| 48 | + instantiated. Nodes without a compatible property may be used to | |
| 49 | + provide configuration information regarding the BPMP itself, although | |
| 50 | + no such configuration nodes are currently defined by this binding. | |
| 51 | + | |
| 52 | + The BPMP firmware defines no single global name-/numbering-space for | |
| 53 | + such services. Put another way, the numbering scheme for I2C buses is | |
| 54 | + distinct from the numbering scheme for any other service the BPMP may | |
| 55 | + provide (e.g. a future hypothetical SPI bus service). As such, child | |
| 56 | + device nodes will have no reg property, and the BPMP node will have no | |
| 57 | + "#address-cells" or "#size-cells" property. | |
| 58 | + | |
| 59 | + The shared memory area for the IPC TX and RX between CPU and BPMP are | |
| 60 | + predefined and work on top of sysram, which is an SRAM inside the | |
| 61 | + chip. See ".../sram/sram.yaml" for the bindings. | |
| 62 | + | |
| 63 | +properties: | |
| 64 | + compatible: | |
| 65 | + oneOf: | |
| 66 | + - items: | |
| 67 | + - enum: | |
| 68 | + - nvidia,tegra194-bpmp | |
| 69 | + - nvidia,tegra234-bpmp | |
| 70 | + - const: nvidia,tegra186-bpmp | |
| 71 | + - const: nvidia,tegra186-bpmp | |
| 72 | + | |
| 73 | + mboxes: | |
| 74 | + description: A phandle and channel specifier for the mailbox used to | |
| 75 | + communicate with the BPMP. | |
| 76 | + maxItems: 1 | |
| 77 | + | |
| 78 | + shmem: | |
| 79 | + description: List of the phandle to the TX and RX shared memory area | |
| 80 | + that the IPC between CPU and BPMP is based on. | |
| 81 | + minItems: 2 | |
| 82 | + maxItems: 2 | |
| 83 | + | |
| 84 | + "#clock-cells": | |
| 85 | + const: 1 | |
| 86 | + | |
| 87 | + "#power-domain-cells": | |
| 88 | + const: 1 | |
| 89 | + | |
| 90 | + "#reset-cells": | |
| 91 | + const: 1 | |
| 92 | + | |
| 93 | + interconnects: | |
| 94 | + items: | |
| 95 | + - description: memory read client | |
| 96 | + - description: memory write client | |
| 97 | + - description: DMA read client | |
| 98 | + - description: DMA write client | |
| 99 | + | |
| 100 | + interconnect-names: | |
| 101 | + items: | |
| 102 | + - const: read | |
| 103 | + - const: write | |
| 104 | + - const: dma-mem # dma-read | |
| 105 | + - const: dma-write | |
| 106 | + | |
| 107 | + iommus: | |
| 108 | + maxItems: 1 | |
| 109 | + | |
| 110 | + i2c: | |
| 111 | + type: object | |
| 112 | + | |
| 113 | + thermal: | |
| 114 | + type: object | |
| 115 | + | |
| 116 | +additionalProperties: false | |
| 117 | + | |
| 118 | +required: | |
| 119 | + - compatible | |
| 120 | + - mboxes | |
| 121 | + - shmem | |
| 122 | + - "#clock-cells" | |
| 123 | + - "#power-domain-cells" | |
| 124 | + - "#reset-cells" | |
| 125 | + | |
| 126 | +examples: | |
| 127 | + - | | |
| 128 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 129 | + #include <dt-bindings/mailbox/tegra186-hsp.h> | |
| 130 | + #include <dt-bindings/memory/tegra186-mc.h> | |
| 131 | + | |
| 132 | + hsp_top0: hsp@3c00000 { | |
| 133 | + compatible = "nvidia,tegra186-hsp"; | |
| 134 | + reg = <0x03c00000 0xa0000>; | |
| 135 | + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; | |
| 136 | + interrupt-names = "doorbell"; | |
| 137 | + #mbox-cells = <2>; | |
| 138 | + }; | |
| 139 | + | |
| 140 | + sram@30000000 { | |
| 141 | + compatible = "nvidia,tegra186-sysram", "mmio-sram"; | |
| 142 | + reg = <0x30000000 0x50000>; | |
| 143 | + #address-cells = <1>; | |
| 144 | + #size-cells = <1>; | |
| 145 | + ranges = <0x0 0x30000000 0x50000>; | |
| 146 | + | |
| 147 | + cpu_bpmp_tx: sram@4e000 { | |
| 148 | + reg = <0x4e000 0x1000>; | |
| 149 | + label = "cpu-bpmp-tx"; | |
| 150 | + pool; | |
| 151 | + }; | |
| 152 | + | |
| 153 | + cpu_bpmp_rx: sram@4f000 { | |
| 154 | + reg = <0x4f000 0x1000>; | |
| 155 | + label = "cpu-bpmp-rx"; | |
| 156 | + pool; | |
| 157 | + }; | |
| 158 | + }; | |
| 159 | + | |
| 160 | + bpmp { | |
| 161 | + compatible = "nvidia,tegra186-bpmp"; | |
| 162 | + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, | |
| 163 | + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, | |
| 164 | + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, | |
| 165 | + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; | |
| 166 | + interconnect-names = "read", "write", "dma-mem", "dma-write"; | |
| 167 | + iommus = <&smmu TEGRA186_SID_BPMP>; | |
| 168 | + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB | |
| 169 | + TEGRA_HSP_DB_MASTER_BPMP>; | |
| 170 | + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; | |
| 171 | + #clock-cells = <1>; | |
| 172 | + #power-domain-cells = <1>; | |
| 173 | + #reset-cells = <1>; | |
| 174 | + | |
| 175 | + i2c { | |
| 176 | + compatible = "nvidia,tegra186-bpmp-i2c"; | |
| 177 | + nvidia,bpmp-bus-id = <5>; | |
| 178 | + #address-cells = <1>; | |
| 179 | + #size-cells = <0>; | |
| 180 | + }; | |
| 181 | + | |
| 182 | + thermal { | |
| 183 | + compatible = "nvidia,tegra186-bpmp-thermal"; | |
| 184 | + #thermal-sensor-cells = <1>; | |
| 185 | + }; | |
| 186 | + }; | |
| @@ -1,42 +0,0 @@ | ||
| 1 | −NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. | |
| 2 | − | |
| 3 | −Required properties: | |
| 4 | −- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, | |
| 5 | − must contain "nvidia,tegra30-efuse". For Tegra114, must contain | |
| 6 | − "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". | |
| 7 | − For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". | |
| 8 | − For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain | |
| 9 | − "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". | |
| 10 | − For Tegra234 must contain "nvidia,tegra234-efuse". | |
| 11 | − Details: | |
| 12 | − nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data | |
| 13 | − due to a hardware bug. Tegra20 also lacks certain information which is | |
| 14 | − available in later generations such as fab code, lot code, wafer id,.. | |
| 15 | − nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: | |
| 16 | − The differences between these SoCs are the size of the efuse array, | |
| 17 | − the location of the spare (OEM programmable) bits and the location of | |
| 18 | − the speedo data. | |
| 19 | −- reg: Should contain 1 entry: the entry gives the physical address and length | |
| 20 | − of the fuse registers. | |
| 21 | −- clocks: Must contain an entry for each entry in clock-names. | |
| 22 | − See ../clocks/clock-bindings.txt for details. | |
| 23 | −- clock-names: Must include the following entries: | |
| 24 | − - fuse | |
| 25 | −- resets: Must contain an entry for each entry in reset-names. | |
| 26 | − See ../reset/reset.txt for details. | |
| 27 | −- reset-names: Must include the following entries: | |
| 28 | − - fuse | |
| 29 | − | |
| 30 | −Example: | |
| 31 | − | |
| 32 | − fuse@7000f800 { | |
| 33 | − compatible = "nvidia,tegra20-efuse"; | |
| 34 | − reg = <0x7000f800 0x400>, | |
| 35 | − <0x70000000 0x400>; | |
| 36 | − clocks = <&tegra_car TEGRA20_CLK_FUSE>; | |
| 37 | − clock-names = "fuse"; | |
| 38 | − resets = <&tegra_car 39>; | |
| 39 | − reset-names = "fuse"; | |
| 40 | − }; | |
| 41 | − | |
| 42 | − | |
| @@ -0,0 +1,89 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra FUSE block | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +properties: | |
| 14 | + compatible: | |
| 15 | + oneOf: | |
| 16 | + - enum: | |
| 17 | + - nvidia,tegra20-efuse | |
| 18 | + - nvidia,tegra30-efuse | |
| 19 | + - nvidia,tegra114-efuse | |
| 20 | + - nvidia,tegra124-efuse | |
| 21 | + - nvidia,tegra210-efuse | |
| 22 | + - nvidia,tegra186-efuse | |
| 23 | + - nvidia,tegra194-efuse | |
| 24 | + - nvidia,tegra234-efuse | |
| 25 | + | |
| 26 | + - items: | |
| 27 | + - const: nvidia,tegra132-efuse | |
| 28 | + - const: nvidia,tegra124-efuse | |
| 29 | + | |
| 30 | + reg: | |
| 31 | + maxItems: 1 | |
| 32 | + | |
| 33 | + clocks: | |
| 34 | + maxItems: 1 | |
| 35 | + | |
| 36 | + clock-names: | |
| 37 | + items: | |
| 38 | + - const: fuse | |
| 39 | + | |
| 40 | + resets: | |
| 41 | + maxItems: 1 | |
| 42 | + | |
| 43 | + reset-names: | |
| 44 | + items: | |
| 45 | + - const: fuse | |
| 46 | + | |
| 47 | + operating-points-v2: | |
| 48 | + $ref: "/schemas/types.yaml#/definitions/phandle" | |
| 49 | + | |
| 50 | + power-domains: | |
| 51 | + items: | |
| 52 | + - description: phandle to the core power domain | |
| 53 | + | |
| 54 | +additionalProperties: false | |
| 55 | + | |
| 56 | +required: | |
| 57 | + - compatible | |
| 58 | + - reg | |
| 59 | + - clocks | |
| 60 | + - clock-names | |
| 61 | + | |
| 62 | +if: | |
| 63 | + properties: | |
| 64 | + compatible: | |
| 65 | + contains: | |
| 66 | + enum: | |
| 67 | + - nvidia,tegra20-efuse | |
| 68 | + - nvidia,tegra30-efuse | |
| 69 | + - nvidia,tegra114-efuse | |
| 70 | + - nvidia,tegra124-efuse | |
| 71 | + - nvidia,tegra132-efuse | |
| 72 | + - nvidia,tegra210-efuse | |
| 73 | +then: | |
| 74 | + required: | |
| 75 | + - resets | |
| 76 | + - reset-names | |
| 77 | + | |
| 78 | +examples: | |
| 79 | + - | | |
| 80 | + #include <dt-bindings/clock/tegra20-car.h> | |
| 81 | + | |
| 82 | + fuse@7000f800 { | |
| 83 | + compatible = "nvidia,tegra20-efuse"; | |
| 84 | + reg = <0x7000f800 0x400>; | |
| 85 | + clocks = <&tegra_car TEGRA20_CLK_FUSE>; | |
| 86 | + clock-names = "fuse"; | |
| 87 | + resets = <&tegra_car 39>; | |
| 88 | + reset-names = "fuse"; | |
| 89 | + }; | |
| @@ -0,0 +1,135 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" | |
| 5 | +$schema: "http://devicetree.org/meta-schemas/core.yaml#" | |
| 6 | + | |
| 7 | +title: Device tree binding for NVIDIA Tegra NVENC | |
| 8 | + | |
| 9 | +description: | | |
| 10 | + NVENC is the hardware video encoder present on NVIDIA Tegra210 | |
| 11 | + and newer chips. It is located on the Host1x bus and typically | |
| 12 | + programmed through Host1x channels. | |
| 13 | + | |
| 14 | +maintainers: | |
| 15 | + - Thierry Reding <treding@gmail.com> | |
| 16 | + - Mikko Perttunen <mperttunen@nvidia.com> | |
| 17 | + | |
| 18 | +properties: | |
| 19 | + $nodename: | |
| 20 | + pattern: "^nvenc@[0-9a-f]*$" | |
| 21 | + | |
| 22 | + compatible: | |
| 23 | + enum: | |
| 24 | + - nvidia,tegra210-nvenc | |
| 25 | + - nvidia,tegra186-nvenc | |
| 26 | + - nvidia,tegra194-nvenc | |
| 27 | + | |
| 28 | + reg: | |
| 29 | + maxItems: 1 | |
| 30 | + | |
| 31 | + clocks: | |
| 32 | + maxItems: 1 | |
| 33 | + | |
| 34 | + clock-names: | |
| 35 | + items: | |
| 36 | + - const: nvenc | |
| 37 | + | |
| 38 | + resets: | |
| 39 | + maxItems: 1 | |
| 40 | + | |
| 41 | + reset-names: | |
| 42 | + items: | |
| 43 | + - const: nvenc | |
| 44 | + | |
| 45 | + power-domains: | |
| 46 | + maxItems: 1 | |
| 47 | + | |
| 48 | + iommus: | |
| 49 | + maxItems: 1 | |
| 50 | + | |
| 51 | + dma-coherent: true | |
| 52 | + | |
| 53 | + interconnects: | |
| 54 | + minItems: 2 | |
| 55 | + maxItems: 3 | |
| 56 | + | |
| 57 | + interconnect-names: | |
| 58 | + minItems: 2 | |
| 59 | + maxItems: 3 | |
| 60 | + | |
| 61 | + nvidia,host1x-class: | |
| 62 | + description: | | |
| 63 | + Host1x class of the engine, used to specify the targeted engine | |
| 64 | + when programming the engine through Host1x channels or when | |
| 65 | + configuring engine-specific behavior in Host1x. | |
| 66 | + default: 0x21 | |
| 67 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 68 | + | |
| 69 | +required: | |
| 70 | + - compatible | |
| 71 | + - reg | |
| 72 | + - clocks | |
| 73 | + - clock-names | |
| 74 | + - resets | |
| 75 | + - reset-names | |
| 76 | + - power-domains | |
| 77 | + | |
| 78 | +allOf: | |
| 79 | + - if: | |
| 80 | + properties: | |
| 81 | + compatible: | |
| 82 | + enum: | |
| 83 | + - nvidia,tegra210-nvenc | |
| 84 | + - nvidia,tegra186-nvenc | |
| 85 | + then: | |
| 86 | + properties: | |
| 87 | + interconnects: | |
| 88 | + items: | |
| 89 | + - description: DMA read memory client | |
| 90 | + - description: DMA write memory client | |
| 91 | + interconnect-names: | |
| 92 | + items: | |
| 93 | + - const: dma-mem | |
| 94 | + - const: write | |
| 95 | + - if: | |
| 96 | + properties: | |
| 97 | + compatible: | |
| 98 | + enum: | |
| 99 | + - nvidia,tegra194-nvenc | |
| 100 | + then: | |
| 101 | + properties: | |
| 102 | + interconnects: | |
| 103 | + items: | |
| 104 | + - description: DMA read memory client | |
| 105 | + - description: DMA read 2 memory client | |
| 106 | + - description: DMA write memory client | |
| 107 | + interconnect-names: | |
| 108 | + items: | |
| 109 | + - const: dma-mem | |
| 110 | + - const: read-1 | |
| 111 | + - const: write | |
| 112 | + | |
| 113 | +additionalProperties: false | |
| 114 | + | |
| 115 | +examples: | |
| 116 | + - | | |
| 117 | + #include <dt-bindings/clock/tegra186-clock.h> | |
| 118 | + #include <dt-bindings/memory/tegra186-mc.h> | |
| 119 | + #include <dt-bindings/power/tegra186-powergate.h> | |
| 120 | + #include <dt-bindings/reset/tegra186-reset.h> | |
| 121 | + | |
| 122 | + nvenc@154c0000 { | |
| 123 | + compatible = "nvidia,tegra186-nvenc"; | |
| 124 | + reg = <0x154c0000 0x40000>; | |
| 125 | + clocks = <&bpmp TEGRA186_CLK_NVENC>; | |
| 126 | + clock-names = "nvenc"; | |
| 127 | + resets = <&bpmp TEGRA186_RESET_NVENC>; | |
| 128 | + reset-names = "nvenc"; | |
| 129 | + | |
| 130 | + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; | |
| 131 | + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, | |
| 132 | + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; | |
| 133 | + interconnect-names = "dma-mem", "write"; | |
| 134 | + iommus = <&smmu TEGRA186_SID_NVENC>; | |
| 135 | + }; | |
| @@ -0,0 +1,94 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" | |
| 5 | +$schema: "http://devicetree.org/meta-schemas/core.yaml#" | |
| 6 | + | |
| 7 | +title: Device tree binding for NVIDIA Tegra NVJPG | |
| 8 | + | |
| 9 | +description: | | |
| 10 | + NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210 | |
| 11 | + and newer chips. It is located on the Host1x bus and typically programmed | |
| 12 | + through Host1x channels. | |
| 13 | + | |
| 14 | +maintainers: | |
| 15 | + - Thierry Reding <treding@gmail.com> | |
| 16 | + - Mikko Perttunen <mperttunen@nvidia.com> | |
| 17 | + | |
| 18 | +properties: | |
| 19 | + $nodename: | |
| 20 | + pattern: "^nvjpg@[0-9a-f]*$" | |
| 21 | + | |
| 22 | + compatible: | |
| 23 | + enum: | |
| 24 | + - nvidia,tegra210-nvjpg | |
| 25 | + - nvidia,tegra186-nvjpg | |
| 26 | + - nvidia,tegra194-nvjpg | |
| 27 | + | |
| 28 | + reg: | |
| 29 | + maxItems: 1 | |
| 30 | + | |
| 31 | + clocks: | |
| 32 | + maxItems: 1 | |
| 33 | + | |
| 34 | + clock-names: | |
| 35 | + items: | |
| 36 | + - const: nvjpg | |
| 37 | + | |
| 38 | + resets: | |
| 39 | + maxItems: 1 | |
| 40 | + | |
| 41 | + reset-names: | |
| 42 | + items: | |
| 43 | + - const: nvjpg | |
| 44 | + | |
| 45 | + power-domains: | |
| 46 | + maxItems: 1 | |
| 47 | + | |
| 48 | + iommus: | |
| 49 | + maxItems: 1 | |
| 50 | + | |
| 51 | + dma-coherent: true | |
| 52 | + | |
| 53 | + interconnects: | |
| 54 | + items: | |
| 55 | + - description: DMA read memory client | |
| 56 | + - description: DMA write memory client | |
| 57 | + | |
| 58 | + interconnect-names: | |
| 59 | + items: | |
| 60 | + - const: dma-mem | |
| 61 | + - const: write | |
| 62 | + | |
| 63 | +required: | |
| 64 | + - compatible | |
| 65 | + - reg | |
| 66 | + - clocks | |
| 67 | + - clock-names | |
| 68 | + - resets | |
| 69 | + - reset-names | |
| 70 | + - power-domains | |
| 71 | + | |
| 72 | +additionalProperties: false | |
| 73 | + | |
| 74 | +examples: | |
| 75 | + - | | |
| 76 | + #include <dt-bindings/clock/tegra186-clock.h> | |
| 77 | + #include <dt-bindings/memory/tegra186-mc.h> | |
| 78 | + #include <dt-bindings/power/tegra186-powergate.h> | |
| 79 | + #include <dt-bindings/reset/tegra186-reset.h> | |
| 80 | + | |
| 81 | + nvjpg@15380000 { | |
| 82 | + compatible = "nvidia,tegra186-nvjpg"; | |
| 83 | + reg = <0x15380000 0x40000>; | |
| 84 | + clocks = <&bpmp TEGRA186_CLK_NVJPG>; | |
| 85 | + clock-names = "nvjpg"; | |
| 86 | + resets = <&bpmp TEGRA186_RESET_NVJPG>; | |
| 87 | + reset-names = "nvjpg"; | |
| 88 | + | |
| 89 | + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; | |
| 90 | + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, | |
| 91 | + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; | |
| 92 | + interconnect-names = "dma-mem", "write"; | |
| 93 | + iommus = <&smmu TEGRA186_SID_NVJPG>; | |
| 94 | + }; | |
| @@ -21,7 +21,9 @@ allOf: · 20 unmodified lines | ||
| 21 | 21 | properties: |
| 22 | 22 | compatible: |
| 23 | 23 | items: |
| 24 | − - const: apple,t8103-i2c | |
| 24 | + - enum: | |
| 25 | + - apple,t8103-i2c | |
| 26 | + - apple,t6000-i2c | |
| 25 | 27 | - const: apple,i2c |
| 26 | 28 | |
| 27 | 29 | reg: |
| @@ -40,6 +42,9 @@ properties: · 12 unmodified lines | ||
| 40 | 42 | used. This frequency is generated by dividing the reference clock. |
| 41 | 43 | Allowed values are between ref_clk/(16*4) and ref_clk/(16*255). |
| 42 | 44 | |
| 45 | + power-domains: | |
| 46 | + maxItems: 1 | |
| 47 | + | |
| 43 | 48 | required: |
| 44 | 49 | - compatible |
| 45 | 50 | - reg |
| @@ -65,6 +65,9 @@ properties: · 64 unmodified lines | ||
| 65 | 65 | Specifies base physical address and size of the AIC registers. |
| 66 | 66 | maxItems: 1 |
| 67 | 67 | |
| 68 | + power-domains: | |
| 69 | + maxItems: 1 | |
| 70 | + | |
| 68 | 71 | required: |
| 69 | 72 | - compatible |
| 70 | 73 | - '#interrupt-cells' |
| @@ -41,6 +41,9 @@ properties: · 40 unmodified lines | ||
| 41 | 41 | Has to be one. The single cell describes the stream id emitted by |
| 42 | 42 | a master to the IOMMU. |
| 43 | 43 | |
| 44 | + power-domains: | |
| 45 | + maxItems: 1 | |
| 46 | + | |
| 44 | 47 | required: |
| 45 | 48 | - compatible |
| 46 | 49 | - reg |
| @@ -11,6 +11,7 @@ Required properties: · 10 unmodified lines | ||
| 11 | 11 | "aspeed,ast2500-ibt-bmc" |
| 12 | 12 | "aspeed,ast2600-ibt-bmc" |
| 13 | 13 | - reg: physical address and size of the registers |
| 14 | +- clocks: clock for the device | |
| 14 | 15 | |
| 15 | 16 | Optional properties: |
| 16 | 17 | |
| @@ -23,4 +24,5 @@ Example: · 6 unmodified lines | ||
| 23 | 24 | compatible = "aspeed,ast2400-ibt-bmc"; |
| 24 | 25 | reg = <0x1e789140 0x18>; |
| 25 | 26 | interrupts = <8>; |
| 27 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 26 | 28 | }; |
| @@ -56,6 +56,9 @@ properties: · 55 unmodified lines | ||
| 56 | 56 | "#mbox-cells": |
| 57 | 57 | const: 0 |
| 58 | 58 | |
| 59 | + power-domains: | |
| 60 | + maxItems: 1 | |
| 61 | + | |
| 59 | 62 | required: |
| 60 | 63 | - compatible |
| 61 | 64 | - reg |
| @@ -1,72 +0,0 @@ | ||
| 1 | −NVIDIA Tegra Hardware Synchronization Primitives (HSP) | |
| 2 | − | |
| 3 | −The HSP modules are used for the processors to share resources and communicate | |
| 4 | −together. It provides a set of hardware synchronization primitives for | |
| 5 | −interprocessor communication. So the interprocessor communication (IPC) | |
| 6 | −protocols can use hardware synchronization primitives, when operating between | |
| 7 | −two processors not in an SMP relationship. | |
| 8 | − | |
| 9 | −The features that HSP supported are shared mailboxes, shared semaphores, | |
| 10 | −arbitrated semaphores and doorbells. | |
| 11 | − | |
| 12 | −Required properties: | |
| 13 | −- name : Should be hsp | |
| 14 | −- compatible | |
| 15 | − Array of strings. | |
| 16 | − one of: | |
| 17 | − - "nvidia,tegra186-hsp" | |
| 18 | − - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" | |
| 19 | −- reg : Offset and length of the register set for the device. | |
| 20 | −- interrupt-names | |
| 21 | − Array of strings. | |
| 22 | − Contains a list of names for the interrupts described by the interrupt | |
| 23 | − property. May contain the following entries, in any order: | |
| 24 | − - "doorbell" | |
| 25 | − - "sharedN", where 'N' is a number from zero up to the number of | |
| 26 | − external interrupts supported by the HSP instance minus one. | |
| 27 | − Users of this binding MUST look up entries in the interrupt property | |
| 28 | − by name, using this interrupt-names property to do so. | |
| 29 | −- interrupts | |
| 30 | − Array of interrupt specifiers. | |
| 31 | − Must contain one entry per entry in the interrupt-names property, | |
| 32 | − in a matching order. | |
| 33 | −- #mbox-cells : Should be 2. | |
| 34 | − | |
| 35 | −The mbox specifier of the "mboxes" property in the client node should contain | |
| 36 | −two cells. The first cell determines the HSP type and the second cell is used | |
| 37 | −to identify the mailbox that the client is going to use. | |
| 38 | − | |
| 39 | −For doorbells, the second cell specifies the index of the doorbell to use. | |
| 40 | − | |
| 41 | −For shared mailboxes, the second cell is composed of two fields: | |
| 42 | −- bits 31..24: | |
| 43 | − A bit mask of flags that further specify how the shared mailbox will be | |
| 44 | − used. Valid flags are: | |
| 45 | − - bit 31: | |
| 46 | − Defines the direction of the mailbox. If set, the mailbox will be used | |
| 47 | − as a producer (i.e. used to send data). If cleared, the mailbox is the | |
| 48 | − consumer of data sent by a producer. | |
| 49 | − | |
| 50 | −- bits 23.. 0: | |
| 51 | − The index of the shared mailbox to use. The number of available mailboxes | |
| 52 | − may vary by instance of the HSP block and SoC generation. | |
| 53 | − | |
| 54 | −The following file contains definitions that can be used to construct mailbox | |
| 55 | −specifiers: | |
| 56 | − | |
| 57 | − <dt-bindings/mailbox/tegra186-hsp.h> | |
| 58 | − | |
| 59 | −Example: | |
| 60 | − | |
| 61 | −hsp_top0: hsp@3c00000 { | |
| 62 | − compatible = "nvidia,tegra186-hsp"; | |
| 63 | − reg = <0x0 0x03c00000 0x0 0xa0000>; | |
| 64 | − interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; | |
| 65 | − interrupt-names = "doorbell"; | |
| 66 | − #mbox-cells = <2>; | |
| 67 | −}; | |
| 68 | − | |
| 69 | −client { | |
| 70 | − ... | |
| 71 | − mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; | |
| 72 | −}; | |
| @@ -0,0 +1,114 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra Hardware Synchronization Primitives (HSP) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: | | |
| 14 | + The HSP modules are used for the processors to share resources and | |
| 15 | + communicate together. It provides a set of hardware synchronization | |
| 16 | + primitives for interprocessor communication. So the interprocessor | |
| 17 | + communication (IPC) protocols can use hardware synchronization | |
| 18 | + primitives, when operating between two processors not in an SMP | |
| 19 | + relationship. | |
| 20 | + | |
| 21 | + The features that HSP supported are shared mailboxes, shared | |
| 22 | + semaphores, arbitrated semaphores and doorbells. | |
| 23 | + | |
| 24 | + The mbox specifier of the "mboxes" property in the client node should | |
| 25 | + contain two cells. The first cell determines the HSP type and the | |
| 26 | + second cell is used to identify the mailbox that the client is going | |
| 27 | + to use. | |
| 28 | + | |
| 29 | + For doorbells, the second cell specifies the index of the doorbell to | |
| 30 | + use. | |
| 31 | + | |
| 32 | + For shared mailboxes, the second cell is composed of two fields: | |
| 33 | + - bits 31..24: | |
| 34 | + A bit mask of flags that further specify how the shared mailbox | |
| 35 | + will be used. Valid flags are: | |
| 36 | + - bit 31: | |
| 37 | + Defines the direction of the mailbox. If set, the mailbox | |
| 38 | + will be used as a producer (i.e. used to send data). If | |
| 39 | + cleared, the mailbox is the consumer of data sent by a | |
| 40 | + producer. | |
| 41 | + | |
| 42 | + - bits 23..0: | |
| 43 | + The index of the shared mailbox to use. The number of available | |
| 44 | + mailboxes may vary by instance of the HSP block and SoC | |
| 45 | + generation. | |
| 46 | + | |
| 47 | + The following file contains definitions that can be used to | |
| 48 | + construct mailbox specifiers: | |
| 49 | + | |
| 50 | + <dt-bindings/mailbox/tegra186-hsp.h> | |
| 51 | + | |
| 52 | +properties: | |
| 53 | + $nodename: | |
| 54 | + pattern: "^hsp@[0-9a-f]+$" | |
| 55 | + | |
| 56 | + compatible: | |
| 57 | + oneOf: | |
| 58 | + - const: nvidia,tegra186-hsp | |
| 59 | + - const: nvidia,tegra194-hsp | |
| 60 | + - items: | |
| 61 | + - const: nvidia,tegra234-hsp | |
| 62 | + - const: nvidia,tegra194-hsp | |
| 63 | + | |
| 64 | + reg: | |
| 65 | + maxItems: 1 | |
| 66 | + | |
| 67 | + interrupts: | |
| 68 | + minItems: 1 | |
| 69 | + maxItems: 9 | |
| 70 | + | |
| 71 | + interrupt-names: | |
| 72 | + oneOf: | |
| 73 | + # shared interrupts are optional | |
| 74 | + - items: | |
| 75 | + - const: doorbell | |
| 76 | + | |
| 77 | + - items: | |
| 78 | + - const: doorbell | |
| 79 | + - pattern: "^shared[0-7]$" | |
| 80 | + - pattern: "^shared[0-7]$" | |
| 81 | + - pattern: "^shared[0-7]$" | |
| 82 | + - pattern: "^shared[0-7]$" | |
| 83 | + - pattern: "^shared[0-7]$" | |
| 84 | + - pattern: "^shared[0-7]$" | |
| 85 | + - pattern: "^shared[0-7]$" | |
| 86 | + - pattern: "^shared[0-7]$" | |
| 87 | + | |
| 88 | + - items: | |
| 89 | + - pattern: "^shared[0-7]$" | |
| 90 | + - pattern: "^shared[0-7]$" | |
| 91 | + - pattern: "^shared[0-7]$" | |
| 92 | + - pattern: "^shared[0-7]$" | |
| 93 | + | |
| 94 | + "#mbox-cells": | |
| 95 | + const: 2 | |
| 96 | + | |
| 97 | +additionalProperties: false | |
| 98 | + | |
| 99 | +examples: | |
| 100 | + - | | |
| 101 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 102 | + #include <dt-bindings/mailbox/tegra186-hsp.h> | |
| 103 | + | |
| 104 | + hsp_top0: hsp@3c00000 { | |
| 105 | + compatible = "nvidia,tegra186-hsp"; | |
| 106 | + reg = <0x03c00000 0xa0000>; | |
| 107 | + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; | |
| 108 | + interrupt-names = "doorbell"; | |
| 109 | + #mbox-cells = <2>; | |
| 110 | + }; | |
| 111 | + | |
| 112 | + client { | |
| 113 | + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>; | |
| 114 | + }; | |
| @@ -1,64 +0,0 @@ | ||
| 1 | −NVIDIA Tegra Video Decoder Engine | |
| 2 | − | |
| 3 | −Required properties: | |
| 4 | −- compatible : Must contain one of the following values: | |
| 5 | − - "nvidia,tegra20-vde" | |
| 6 | − - "nvidia,tegra30-vde" | |
| 7 | − - "nvidia,tegra114-vde" | |
| 8 | − - "nvidia,tegra124-vde" | |
| 9 | − - "nvidia,tegra132-vde" | |
| 10 | −- reg : Must contain an entry for each entry in reg-names. | |
| 11 | −- reg-names : Must include the following entries: | |
| 12 | − - sxe | |
| 13 | − - bsev | |
| 14 | − - mbe | |
| 15 | − - ppe | |
| 16 | − - mce | |
| 17 | − - tfe | |
| 18 | − - ppb | |
| 19 | − - vdma | |
| 20 | − - frameid | |
| 21 | −- iram : Must contain phandle to the mmio-sram device node that represents | |
| 22 | − IRAM region used by VDE. | |
| 23 | −- interrupts : Must contain an entry for each entry in interrupt-names. | |
| 24 | −- interrupt-names : Must include the following entries: | |
| 25 | − - sync-token | |
| 26 | − - bsev | |
| 27 | − - sxe | |
| 28 | −- clocks : Must include the following entries: | |
| 29 | − - vde | |
| 30 | −- resets : Must contain an entry for each entry in reset-names. | |
| 31 | −- reset-names : Should include the following entries: | |
| 32 | − - vde | |
| 33 | − | |
| 34 | −Optional properties: | |
| 35 | −- resets : Must contain an entry for each entry in reset-names. | |
| 36 | −- reset-names : Must include the following entries: | |
| 37 | − - mc | |
| 38 | −- iommus: Must contain phandle to the IOMMU device node. | |
| 39 | − | |
| 40 | −Example: | |
| 41 | − | |
| 42 | −video-codec@6001a000 { | |
| 43 | − compatible = "nvidia,tegra20-vde"; | |
| 44 | − reg = <0x6001a000 0x1000 /* Syntax Engine */ | |
| 45 | − 0x6001b000 0x1000 /* Video Bitstream Engine */ | |
| 46 | − 0x6001c000 0x100 /* Macroblock Engine */ | |
| 47 | − 0x6001c200 0x100 /* Post-processing Engine */ | |
| 48 | − 0x6001c400 0x100 /* Motion Compensation Engine */ | |
| 49 | − 0x6001c600 0x100 /* Transform Engine */ | |
| 50 | − 0x6001c800 0x100 /* Pixel prediction block */ | |
| 51 | − 0x6001ca00 0x100 /* Video DMA */ | |
| 52 | − 0x6001d800 0x300 /* Video frame controls */>; | |
| 53 | − reg-names = "sxe", "bsev", "mbe", "ppe", "mce", | |
| 54 | − "tfe", "ppb", "vdma", "frameid"; | |
| 55 | − iram = <&vde_pool>; /* IRAM region */ | |
| 56 | − interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ | |
| 57 | − <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ | |
| 58 | − <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ | |
| 59 | − interrupt-names = "sync-token", "bsev", "sxe"; | |
| 60 | − clocks = <&tegra_car TEGRA20_CLK_VDE>; | |
| 61 | − reset-names = "vde", "mc"; | |
| 62 | − resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; | |
| 63 | − iommus = <&mc TEGRA_SWGROUP_VDE>; | |
| 64 | −}; | |
| @@ -0,0 +1,119 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra Video Decoder Engine | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Dmitry Osipenko <digetx@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 13 | + | |
| 14 | +properties: | |
| 15 | + compatible: | |
| 16 | + oneOf: | |
| 17 | + - items: | |
| 18 | + - enum: | |
| 19 | + - nvidia,tegra132-vde | |
| 20 | + - nvidia,tegra124-vde | |
| 21 | + - nvidia,tegra114-vde | |
| 22 | + - items: | |
| 23 | + - const: nvidia,tegra30-vde | |
| 24 | + - const: nvidia,tegra20-vde | |
| 25 | + - items: | |
| 26 | + - const: nvidia,tegra20-vde | |
| 27 | + | |
| 28 | + reg: | |
| 29 | + maxItems: 9 | |
| 30 | + | |
| 31 | + reg-names: | |
| 32 | + items: | |
| 33 | + - const: sxe | |
| 34 | + - const: bsev | |
| 35 | + - const: mbe | |
| 36 | + - const: ppe | |
| 37 | + - const: mce | |
| 38 | + - const: tfe | |
| 39 | + - const: ppb | |
| 40 | + - const: vdma | |
| 41 | + - const: frameid | |
| 42 | + | |
| 43 | + clocks: | |
| 44 | + maxItems: 1 | |
| 45 | + | |
| 46 | + resets: | |
| 47 | + maxItems: 2 | |
| 48 | + | |
| 49 | + reset-names: | |
| 50 | + items: | |
| 51 | + - const: vde | |
| 52 | + - const: mc | |
| 53 | + | |
| 54 | + interrupts: | |
| 55 | + maxItems: 3 | |
| 56 | + | |
| 57 | + interrupt-names: | |
| 58 | + items: | |
| 59 | + - const: sync-token | |
| 60 | + - const: bsev | |
| 61 | + - const: sxe | |
| 62 | + | |
| 63 | + iommus: | |
| 64 | + maxItems: 1 | |
| 65 | + | |
| 66 | + iram: | |
| 67 | + $ref: /schemas/types.yaml#/definitions/phandle | |
| 68 | + description: | |
| 69 | + Phandle of the SRAM MMIO node. | |
| 70 | + | |
| 71 | + operating-points-v2: | |
| 72 | + description: | |
| 73 | + Should contain freqs and voltages and opp-supported-hw property, | |
| 74 | + which is a bitfield indicating SoC speedo or process ID mask. | |
| 75 | + | |
| 76 | + power-domains: | |
| 77 | + maxItems: 1 | |
| 78 | + description: | |
| 79 | + Phandle to the SoC core power domain. | |
| 80 | + | |
| 81 | +required: | |
| 82 | + - compatible | |
| 83 | + - reg | |
| 84 | + - reg-names | |
| 85 | + - clocks | |
| 86 | + - resets | |
| 87 | + - reset-names | |
| 88 | + - interrupts | |
| 89 | + - interrupt-names | |
| 90 | + | |
| 91 | +additionalProperties: false | |
| 92 | + | |
| 93 | +examples: | |
| 94 | + - | | |
| 95 | + video-codec@6001a000 { | |
| 96 | + compatible = "nvidia,tegra20-vde"; | |
| 97 | + reg = <0x6001a000 0x1000>, /* Syntax Engine */ | |
| 98 | + <0x6001b000 0x1000>, /* Video Bitstream Engine */ | |
| 99 | + <0x6001c000 0x100>, /* Macroblock Engine */ | |
| 100 | + <0x6001c200 0x100>, /* Post-processing Engine */ | |
| 101 | + <0x6001c400 0x100>, /* Motion Compensation Engine */ | |
| 102 | + <0x6001c600 0x100>, /* Transform Engine */ | |
| 103 | + <0x6001c800 0x100>, /* Pixel prediction block */ | |
| 104 | + <0x6001ca00 0x100>, /* Video DMA */ | |
| 105 | + <0x6001d800 0x300>; /* Video frame controls */ | |
| 106 | + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", | |
| 107 | + "tfe", "ppb", "vdma", "frameid"; | |
| 108 | + iram = <&iram>; /* IRAM MMIO region */ | |
| 109 | + interrupts = <0 9 4>, /* Sync token */ | |
| 110 | + <0 10 4>, /* BSE-V */ | |
| 111 | + <0 12 4>; /* SXE */ | |
| 112 | + interrupt-names = "sync-token", "bsev", "sxe"; | |
| 113 | + clocks = <&clk 61>; | |
| 114 | + reset-names = "vde", "mc"; | |
| 115 | + resets = <&rst 61>, <&mem 13>; | |
| 116 | + iommus = <&mem 15>; | |
| 117 | + operating-points-v2 = <&dvfs_opp_table>; | |
| 118 | + power-domains = <&domain>; | |
| 119 | + }; | |
| @@ -31,12 +31,15 @@ properties: · 30 unmodified lines | ||
| 31 | 31 | - enum: |
| 32 | 32 | - nvidia,tegra186-mc |
| 33 | 33 | - nvidia,tegra194-mc |
| 34 | + - nvidia,tegra234-mc | |
| 34 | 35 | |
| 35 | 36 | reg: |
| 36 | − maxItems: 1 | |
| 37 | + minItems: 1 | |
| 38 | + maxItems: 3 | |
| 37 | 39 | |
| 38 | 40 | interrupts: |
| 39 | − maxItems: 1 | |
| 41 | + items: | |
| 42 | + - description: MC general interrupt | |
| 40 | 43 | |
| 41 | 44 | "#address-cells": |
| 42 | 45 | const: 2 |
| @@ -48,6 +51,9 @@ properties: · 5 unmodified lines | ||
| 48 | 51 | |
| 49 | 52 | dma-ranges: true |
| 50 | 53 | |
| 54 | + "#interconnect-cells": | |
| 55 | + const: 1 | |
| 56 | + | |
| 51 | 57 | patternProperties: |
| 52 | 58 | "^external-memory-controller@[0-9a-f]+$": |
| 53 | 59 | description: |
| @@ -63,12 +69,15 @@ patternProperties: · 9 unmodified lines | ||
| 63 | 69 | - enum: |
| 64 | 70 | - nvidia,tegra186-emc |
| 65 | 71 | - nvidia,tegra194-emc |
| 72 | + - nvidia,tegra234-emc | |
| 66 | 73 | |
| 67 | 74 | reg: |
| 68 | − maxItems: 1 | |
| 75 | + minItems: 1 | |
| 76 | + maxItems: 2 | |
| 69 | 77 | |
| 70 | 78 | interrupts: |
| 71 | − maxItems: 1 | |
| 79 | + items: | |
| 80 | + - description: EMC general interrupt | |
| 72 | 81 | |
| 73 | 82 | clocks: |
| 74 | 83 | items: |
| @@ -78,11 +87,83 @@ patternProperties: · 3 unmodified lines | ||
| 78 | 87 | items: |
| 79 | 88 | - const: emc |
| 80 | 89 | |
| 90 | + "#interconnect-cells": | |
| 91 | + const: 0 | |
| 92 | + | |
| 81 | 93 | nvidia,bpmp: |
| 82 | 94 | $ref: /schemas/types.yaml#/definitions/phandle |
| 83 | 95 | description: |
| 84 | 96 | phandle of the node representing the BPMP |
| 85 | 97 | |
| 98 | + allOf: | |
| 99 | + - if: | |
| 100 | + properties: | |
| 101 | + compatible: | |
| 102 | + const: nvidia,tegra186-emc | |
| 103 | + then: | |
| 104 | + properties: | |
| 105 | + reg: | |
| 106 | + maxItems: 1 | |
| 107 | + | |
| 108 | + - if: | |
| 109 | + properties: | |
| 110 | + compatible: | |
| 111 | + const: nvidia,tegra194-emc | |
| 112 | + then: | |
| 113 | + properties: | |
| 114 | + reg: | |
| 115 | + minItems: 2 | |
| 116 | + | |
| 117 | + - if: | |
| 118 | + properties: | |
| 119 | + compatible: | |
| 120 | + const: nvidia,tegra234-emc | |
| 121 | + then: | |
| 122 | + properties: | |
| 123 | + reg: | |
| 124 | + minItems: 2 | |
| 125 | + | |
| 126 | + additionalProperties: false | |
| 127 | + | |
| 128 | + required: | |
| 129 | + - compatible | |
| 130 | + - reg | |
| 131 | + - interrupts | |
| 132 | + - clocks | |
| 133 | + - clock-names | |
| 134 | + - "#interconnect-cells" | |
| 135 | + - nvidia,bpmp | |
| 136 | + | |
| 137 | +allOf: | |
| 138 | + - if: | |
| 139 | + properties: | |
| 140 | + compatible: | |
| 141 | + const: nvidia,tegra186-mc | |
| 142 | + then: | |
| 143 | + properties: | |
| 144 | + reg: | |
| 145 | + maxItems: 1 | |
| 146 | + | |
| 147 | + - if: | |
| 148 | + properties: | |
| 149 | + compatible: | |
| 150 | + const: nvidia,tegra194-mc | |
| 151 | + then: | |
| 152 | + properties: | |
| 153 | + reg: | |
| 154 | + minItems: 3 | |
| 155 | + | |
| 156 | + - if: | |
| 157 | + properties: | |
| 158 | + compatible: | |
| 159 | + const: nvidia,tegra234-mc | |
| 160 | + then: | |
| 161 | + properties: | |
| 162 | + reg: | |
| 163 | + minItems: 3 | |
| 164 | + | |
| 165 | +additionalProperties: false | |
| 166 | + | |
| 86 | 167 | required: |
| 87 | 168 | - compatible |
| 88 | 169 | - reg |
| @@ -90,8 +171,6 @@ required: · 1 unmodified line | ||
| 90 | 171 | - "#address-cells" |
| 91 | 172 | - "#size-cells" |
| 92 | 173 | |
| 93 | −additionalProperties: false | |
| 94 | − | |
| 95 | 174 | examples: |
| 96 | 175 | - | |
| 97 | 176 | #include <dt-bindings/clock/tegra186-clock.h> |
| @@ -124,12 +203,9 @@ examples: · 26 unmodified lines | ||
| 124 | 203 | clocks = <&bpmp TEGRA186_CLK_EMC>; |
| 125 | 204 | clock-names = "emc"; |
| 126 | 205 | |
| 206 | + #interconnect-cells = <0>; | |
| 207 | + | |
| 127 | 208 | nvidia,bpmp = <&bpmp>; |
| 128 | 209 | }; |
| 129 | 210 | }; |
| 130 | 211 | }; |
| 131 | − | |
| 132 | − bpmp: bpmp { | |
| 133 | − compatible = "nvidia,tegra186-bpmp"; | |
| 134 | − #clock-cells = <1>; | |
| 135 | − }; | |
| @@ -1,14 +0,0 @@ | ||
| 1 | −NVIDIA Tegra186 (and later) MISC register block | |
| 2 | − | |
| 3 | −The MISC register block found on Tegra186 and later SoCs contains registers | |
| 4 | −that can be used to identify a given chip and various strapping options. | |
| 5 | − | |
| 6 | −Required properties: | |
| 7 | −- compatible: Must be: | |
| 8 | − - Tegra186: "nvidia,tegra186-misc" | |
| 9 | − - Tegra194: "nvidia,tegra194-misc" | |
| 10 | − - Tegra234: "nvidia,tegra234-misc" | |
| 11 | −- reg: Should contain 2 entries: The first entry gives the physical address | |
| 12 | − and length of the register region which contains revision and debug | |
| 13 | − features. The second entry specifies the physical address and length | |
| 14 | − of the register region indicating the strapping options. | |
| @@ -0,0 +1,43 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra186 (and later) MISC register block | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: The MISC register block found on Tegra186 and later SoCs contains | |
| 14 | + registers that can be used to identify a given chip and various strapping | |
| 15 | + options. | |
| 16 | + | |
| 17 | +properties: | |
| 18 | + compatible: | |
| 19 | + enum: | |
| 20 | + - nvidia,tegra186-misc | |
| 21 | + - nvidia,tegra194-misc | |
| 22 | + - nvidia,tegra234-misc | |
| 23 | + | |
| 24 | + reg: | |
| 25 | + items: | |
| 26 | + - description: physical address and length of the registers which | |
| 27 | + contain revision and debug features | |
| 28 | + - description: physical address and length of the registers which | |
| 29 | + indicate strapping options | |
| 30 | + | |
| 31 | +additionalProperties: false | |
| 32 | + | |
| 33 | +required: | |
| 34 | + - compatible | |
| 35 | + - reg | |
| 36 | + | |
| 37 | +examples: | |
| 38 | + - | | |
| 39 | + misc@100000 { | |
| 40 | + compatible = "nvidia,tegra186-misc"; | |
| 41 | + reg = <0x00100000 0xf000>, | |
| 42 | + <0x0010f000 0x1000>; | |
| 43 | + }; | |
| @@ -1,17 +0,0 @@ | ||
| 1 | −NVIDIA Tegra APBMISC block | |
| 2 | − | |
| 3 | −Required properties: | |
| 4 | −- compatible: Must be: | |
| 5 | − - Tegra20: "nvidia,tegra20-apbmisc" | |
| 6 | − - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" | |
| 7 | − - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" | |
| 8 | − - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" | |
| 9 | − - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" | |
| 10 | − - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" | |
| 11 | −- reg: Should contain 2 entries: the first entry gives the physical address | |
| 12 | − and length of the registers which contain revision and debug features. | |
| 13 | − The second entry gives the physical address and length of the | |
| 14 | − registers indicating the strapping options. | |
| 15 | − | |
| 16 | −Optional properties: | |
| 17 | −- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). | |
| @@ -0,0 +1,51 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra APBMISC block | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +properties: | |
| 14 | + compatible: | |
| 15 | + oneOf: | |
| 16 | + - items: | |
| 17 | + - enum: | |
| 18 | + - nvidia,tegra210-apbmisc | |
| 19 | + - nvidia,tegra124-apbmisc | |
| 20 | + - nvidia,tegra114-apbmisc | |
| 21 | + - nvidia,tegra30-apbmisc | |
| 22 | + - const: nvidia,tegra20-apbmisc | |
| 23 | + | |
| 24 | + - items: | |
| 25 | + - const: nvidia,tegra20-apbmisc | |
| 26 | + | |
| 27 | + reg: | |
| 28 | + items: | |
| 29 | + - description: physical address and length of the registers which | |
| 30 | + contain revision and debug features | |
| 31 | + - description: physical address and length of the registers which | |
| 32 | + indicate strapping options | |
| 33 | + | |
| 34 | + nvidia,long-ram-code: | |
| 35 | + description: If present, the RAM code is long (4 bit). If not, short | |
| 36 | + (2 bit). | |
| 37 | + type: boolean | |
| 38 | + | |
| 39 | +additionalProperties: false | |
| 40 | + | |
| 41 | +required: | |
| 42 | + - compatible | |
| 43 | + - reg | |
| 44 | + | |
| 45 | +examples: | |
| 46 | + - | | |
| 47 | + apbmisc@70000800 { | |
| 48 | + compatible = "nvidia,tegra20-apbmisc"; | |
| 49 | + reg = <0x70000800 0x64>, /* Chip revision */ | |
| 50 | + <0x70000008 0x04>; /* Strapping options */ | |
| 51 | + }; | |
| @@ -1,143 +0,0 @@ | ||
| 1 | −* NVIDIA Tegra Secure Digital Host Controller | |
| 2 | − | |
| 3 | −This controller on Tegra family SoCs provides an interface for MMC, SD, | |
| 4 | −and SDIO types of memory cards. | |
| 5 | − | |
| 6 | −This file documents differences between the core properties described | |
| 7 | −by mmc.txt and the properties used by the sdhci-tegra driver. | |
| 8 | − | |
| 9 | −Required properties: | |
| 10 | −- compatible : should be one of: | |
| 11 | − - "nvidia,tegra20-sdhci": for Tegra20 | |
| 12 | − - "nvidia,tegra30-sdhci": for Tegra30 | |
| 13 | − - "nvidia,tegra114-sdhci": for Tegra114 | |
| 14 | − - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 | |
| 15 | − - "nvidia,tegra210-sdhci": for Tegra210 | |
| 16 | − - "nvidia,tegra186-sdhci": for Tegra186 | |
| 17 | − - "nvidia,tegra194-sdhci": for Tegra194 | |
| 18 | −- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries. | |
| 19 | − One for the module clock and one for the timeout clock. | |
| 20 | − For all other Tegra devices, must contain a single entry for | |
| 21 | − the module clock. See ../clocks/clock-bindings.txt for details. | |
| 22 | −- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the | |
| 23 | − strings 'sdhci' and 'tmclk' to represent the module and | |
| 24 | − the timeout clocks, respectively. | |
| 25 | − For all other Tegra devices must contain the string 'sdhci' | |
| 26 | − to represent the module clock. | |
| 27 | −- resets : Must contain an entry for each entry in reset-names. | |
| 28 | − See ../reset/reset.txt for details. | |
| 29 | −- reset-names : Must include the following entries: | |
| 30 | − - sdhci | |
| 31 | − | |
| 32 | −Optional properties: | |
| 33 | −- power-gpios : Specify GPIOs for power control | |
| 34 | − | |
| 35 | −Example: | |
| 36 | − | |
| 37 | −sdhci@c8000200 { | |
| 38 | − compatible = "nvidia,tegra20-sdhci"; | |
| 39 | − reg = <0xc8000200 0x200>; | |
| 40 | − interrupts = <47>; | |
| 41 | − clocks = <&tegra_car 14>; | |
| 42 | − resets = <&tegra_car 14>; | |
| 43 | − reset-names = "sdhci"; | |
| 44 | − cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | |
| 45 | − wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | |
| 46 | − power-gpios = <&gpio 155 0>; /* gpio PT3 */ | |
| 47 | − bus-width = <8>; | |
| 48 | −}; | |
| 49 | − | |
| 50 | −Optional properties for Tegra210, Tegra186 and Tegra194: | |
| 51 | −- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage | |
| 52 | − configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" | |
| 53 | − for controllers supporting multiple voltage levels. The order of names | |
| 54 | − should correspond to the pin configuration states in pinctrl-0 and | |
| 55 | − pinctrl-1. | |
| 56 | −- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for | |
| 57 | − Tegra210 where pad config registers are in the pinmux register domain | |
| 58 | − for pull-up-strength and pull-down-strength values configuration when | |
| 59 | − using pads at 3V3 and 1V8 levels. | |
| 60 | −- nvidia,only-1-8-v : The presence of this property indicates that the | |
| 61 | − controller operates at a 1.8 V fixed I/O voltage. | |
| 62 | −- nvidia,pad-autocal-pull-up-offset-3v3, | |
| 63 | − nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength | |
| 64 | − calibration offsets for 3.3 V signaling modes. | |
| 65 | −- nvidia,pad-autocal-pull-up-offset-1v8, | |
| 66 | − nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength | |
| 67 | − calibration offsets for 1.8 V signaling modes. | |
| 68 | −- nvidia,pad-autocal-pull-up-offset-3v3-timeout, | |
| 69 | − nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive | |
| 70 | − strength used as a fallback in case the automatic calibration times | |
| 71 | − out on a 3.3 V signaling mode. | |
| 72 | −- nvidia,pad-autocal-pull-up-offset-1v8-timeout, | |
| 73 | − nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive | |
| 74 | − strength used as a fallback in case the automatic calibration times | |
| 75 | − out on a 1.8 V signaling mode. | |
| 76 | −- nvidia,pad-autocal-pull-up-offset-sdr104, | |
| 77 | − nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength | |
| 78 | − calibration offsets for SDR104 mode. | |
| 79 | −- nvidia,pad-autocal-pull-up-offset-hs400, | |
| 80 | − nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength | |
| 81 | − calibration offsets for HS400 mode. | |
| 82 | −- nvidia,default-tap : Specify the default inbound sampling clock | |
| 83 | − trimmer value for non-tunable modes. | |
| 84 | −- nvidia,default-trim : Specify the default outbound clock trimmer | |
| 85 | − value. | |
| 86 | −- nvidia,dqs-trim : Specify DQS trim value for HS400 timing | |
| 87 | − | |
| 88 | − Notes on the pad calibration pull up and pulldown offset values: | |
| 89 | − - The property values are drive codes which are programmed into the | |
| 90 | − PD_OFFSET and PU_OFFSET sections of the | |
| 91 | − SDHCI_TEGRA_AUTO_CAL_CONFIG register. | |
| 92 | − - A higher value corresponds to higher drive strength. Please refer | |
| 93 | − to the reference manual of the SoC for correct values. | |
| 94 | − - The SDR104 and HS400 timing specific values are used in | |
| 95 | − corresponding modes if specified. | |
| 96 | − | |
| 97 | − Notes on tap and trim values: | |
| 98 | − - The values are used for compensating trace length differences | |
| 99 | − by adjusting the sampling point. | |
| 100 | − - The values are programmed to the Vendor Clock Control Register. | |
| 101 | − Please refer to the reference manual of the SoC for correct | |
| 102 | − values. | |
| 103 | − - The DQS trim values are only used on controllers which support | |
| 104 | − HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports | |
| 105 | − HS400. | |
| 106 | − | |
| 107 | −Example: | |
| 108 | −sdhci@700b0000 { | |
| 109 | − compatible = "nvidia,tegra124-sdhci"; | |
| 110 | − reg = <0x0 0x700b0000 0x0 0x200>; | |
| 111 | − interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 112 | − clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; | |
| 113 | − clock-names = "sdhci"; | |
| 114 | − resets = <&tegra_car 14>; | |
| 115 | − reset-names = "sdhci"; | |
| 116 | − pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; | |
| 117 | − pinctrl-0 = <&sdmmc1_3v3>; | |
| 118 | − pinctrl-1 = <&sdmmc1_1v8>; | |
| 119 | − nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; | |
| 120 | − nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; | |
| 121 | − nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; | |
| 122 | − nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; | |
| 123 | − status = "disabled"; | |
| 124 | −}; | |
| 125 | − | |
| 126 | −sdhci@700b0000 { | |
| 127 | − compatible = "nvidia,tegra210-sdhci"; | |
| 128 | − reg = <0x0 0x700b0000 0x0 0x200>; | |
| 129 | − interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 130 | − clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, | |
| 131 | − <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; | |
| 132 | − clock-names = "sdhci", "tmclk"; | |
| 133 | − resets = <&tegra_car 14>; | |
| 134 | − reset-names = "sdhci"; | |
| 135 | − pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; | |
| 136 | − pinctrl-0 = <&sdmmc1_3v3>; | |
| 137 | − pinctrl-1 = <&sdmmc1_1v8>; | |
| 138 | − nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; | |
| 139 | − nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; | |
| 140 | − nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; | |
| 141 | − nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; | |
| 142 | − status = "disabled"; | |
| 143 | −}; | |
| @@ -0,0 +1,317 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra Secure Digital Host Controller | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: | | |
| 14 | + This controller on Tegra family SoCs provides an interface for MMC, SD, and | |
| 15 | + SDIO types of memory cards. | |
| 16 | + | |
| 17 | + This file documents differences between the core properties described by | |
| 18 | + mmc-controller.yaml and the properties for the Tegra SDHCI controller. | |
| 19 | + | |
| 20 | +properties: | |
| 21 | + compatible: | |
| 22 | + oneOf: | |
| 23 | + - enum: | |
| 24 | + - nvidia,tegra20-sdhci | |
| 25 | + - nvidia,tegra30-sdhci | |
| 26 | + - nvidia,tegra114-sdhci | |
| 27 | + - nvidia,tegra124-sdhci | |
| 28 | + - nvidia,tegra210-sdhci | |
| 29 | + - nvidia,tegra186-sdhci | |
| 30 | + - nvidia,tegra194-sdhci | |
| 31 | + | |
| 32 | + - items: | |
| 33 | + - const: nvidia,tegra132-sdhci | |
| 34 | + - const: nvidia,tegra124-sdhci | |
| 35 | + | |
| 36 | + - items: | |
| 37 | + - enum: | |
| 38 | + - nvidia,tegra194-sdhci | |
| 39 | + - nvidia,tegra234-sdhci | |
| 40 | + - const: nvidia,tegra186-sdhci | |
| 41 | + | |
| 42 | + reg: | |
| 43 | + maxItems: 1 | |
| 44 | + | |
| 45 | + interrupts: | |
| 46 | + maxItems: 1 | |
| 47 | + | |
| 48 | + assigned-clocks: true | |
| 49 | + assigned-clock-parents: true | |
| 50 | + assigned-clock-rates: true | |
| 51 | + | |
| 52 | + clocks: | |
| 53 | + minItems: 1 | |
| 54 | + maxItems: 2 | |
| 55 | + | |
| 56 | + clock-names: | |
| 57 | + minItems: 1 | |
| 58 | + maxItems: 2 | |
| 59 | + | |
| 60 | + resets: | |
| 61 | + items: | |
| 62 | + - description: module reset | |
| 63 | + | |
| 64 | + reset-names: | |
| 65 | + items: | |
| 66 | + - const: sdhci | |
| 67 | + | |
| 68 | + power-gpios: | |
| 69 | + description: specify GPIOs for power control | |
| 70 | + maxItems: 1 | |
| 71 | + | |
| 72 | + interconnects: | |
| 73 | + items: | |
| 74 | + - description: memory read client | |
| 75 | + - description: memory write client | |
| 76 | + | |
| 77 | + interconnect-names: | |
| 78 | + items: | |
| 79 | + - const: dma-mem # read | |
| 80 | + - const: write | |
| 81 | + | |
| 82 | + iommus: | |
| 83 | + maxItems: 1 | |
| 84 | + | |
| 85 | + operating-points-v2: | |
| 86 | + $ref: "/schemas/types.yaml#/definitions/phandle" | |
| 87 | + | |
| 88 | + power-domains: | |
| 89 | + items: | |
| 90 | + - description: phandle to the core power domain | |
| 91 | + | |
| 92 | + nvidia,default-tap: | |
| 93 | + description: Specify the default inbound sampling clock trimmer value for | |
| 94 | + non-tunable modes. | |
| 95 | + | |
| 96 | + The values are used for compensating trace length differences by | |
| 97 | + adjusting the sampling point. The values are programmed to the Vendor | |
| 98 | + Clock Control Register. Please refer to the reference manual of the SoC | |
| 99 | + for correct values. | |
| 100 | + | |
| 101 | + The DQS trim values are only used on controllers which support HS400 | |
| 102 | + timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. | |
| 103 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 104 | + | |
| 105 | + nvidia,default-trim: | |
| 106 | + description: Specify the default outbound clock trimmer value. | |
| 107 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 108 | + | |
| 109 | + nvidia,dqs-trim: | |
| 110 | + description: Specify DQS trim value for HS400 timing. | |
| 111 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 112 | + | |
| 113 | + nvidia,pad-autocal-pull-down-offset-1v8: | |
| 114 | + description: Specify drive strength calibration offsets for 1.8 V | |
| 115 | + signaling modes. | |
| 116 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 117 | + | |
| 118 | + nvidia,pad-autocal-pull-down-offset-1v8-timeout: | |
| 119 | + description: Specify drive strength used as a fallback in case the | |
| 120 | + automatic calibration times out on a 1.8 V signaling mode. | |
| 121 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 122 | + | |
| 123 | + nvidia,pad-autocal-pull-down-offset-3v3: | |
| 124 | + description: Specify drive strength calibration offsets for 3.3 V | |
| 125 | + signaling modes. | |
| 126 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 127 | + | |
| 128 | + nvidia,pad-autocal-pull-down-offset-3v3-timeout: | |
| 129 | + description: Specify drive strength used as a fallback in case the | |
| 130 | + automatic calibration times out on a 3.3 V signaling mode. | |
| 131 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 132 | + | |
| 133 | + nvidia,pad-autocal-pull-down-offset-sdr104: | |
| 134 | + description: Specify drive strength calibration offsets for SDR104 mode. | |
| 135 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 136 | + | |
| 137 | + nvidia,pad-autocal-pull-down-offset-hs400: | |
| 138 | + description: Specify drive strength calibration offsets for HS400 mode. | |
| 139 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 140 | + | |
| 141 | + nvidia,pad-autocal-pull-up-offset-1v8: | |
| 142 | + description: Specify drive strength calibration offsets for 1.8 V | |
| 143 | + signaling modes. | |
| 144 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 145 | + | |
| 146 | + nvidia,pad-autocal-pull-up-offset-1v8-timeout: | |
| 147 | + description: Specify drive strength used as a fallback in case the | |
| 148 | + automatic calibration times out on a 1.8 V signaling mode. | |
| 149 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 150 | + | |
| 151 | + nvidia,pad-autocal-pull-up-offset-3v3: | |
| 152 | + description: Specify drive strength calibration offsets for 3.3 V | |
| 153 | + signaling modes. | |
| 154 | + | |
| 155 | + The property values are drive codes which are programmed into the | |
| 156 | + PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG | |
| 157 | + register. A higher value corresponds to higher drive strength. Please | |
| 158 | + refer to the reference manual of the SoC for correct values. The SDR104 | |
| 159 | + and HS400 timing specific values are used in corresponding modes if | |
| 160 | + specified. | |
| 161 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 162 | + | |
| 163 | + nvidia,pad-autocal-pull-up-offset-3v3-timeout: | |
| 164 | + description: Specify drive strength used as a fallback in case the | |
| 165 | + automatic calibration times out on a 3.3 V signaling mode. | |
| 166 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 167 | + | |
| 168 | + nvidia,pad-autocal-pull-up-offset-sdr104: | |
| 169 | + description: Specify drive strength calibration offsets for SDR104 mode. | |
| 170 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 171 | + | |
| 172 | + nvidia,pad-autocal-pull-up-offset-hs400: | |
| 173 | + description: Specify drive strength calibration offsets for HS400 mode. | |
| 174 | + $ref: "/schemas/types.yaml#/definitions/uint32" | |
| 175 | + | |
| 176 | + nvidia,only-1-8v: | |
| 177 | + description: The presence of this property indicates that the controller | |
| 178 | + operates at a 1.8 V fixed I/O voltage. | |
| 179 | + $ref: "/schemas/types.yaml#/definitions/flag" | |
| 180 | + | |
| 181 | +required: | |
| 182 | + - compatible | |
| 183 | + - reg | |
| 184 | + - interrupts | |
| 185 | + - clocks | |
| 186 | + - resets | |
| 187 | + - reset-names | |
| 188 | + | |
| 189 | +allOf: | |
| 190 | + - $ref: "mmc-controller.yaml" | |
| 191 | + - if: | |
| 192 | + properties: | |
| 193 | + compatible: | |
| 194 | + contains: | |
| 195 | + enum: | |
| 196 | + - nvidia,tegra20-sdhci | |
| 197 | + - nvidia,tegra30-sdhci | |
| 198 | + - nvidia,tegra114-sdhci | |
| 199 | + - nvidia,tegra124-sdhci | |
| 200 | + clocks: | |
| 201 | + items: | |
| 202 | + - description: module clock | |
| 203 | + minItems: 1 | |
| 204 | + maxItems: 1 | |
| 205 | + else: | |
| 206 | + properties: | |
| 207 | + clocks: | |
| 208 | + items: | |
| 209 | + - description: module clock | |
| 210 | + - description: timeout clock | |
| 211 | + minItems: 2 | |
| 212 | + maxItems: 2 | |
| 213 | + clock-names: | |
| 214 | + items: | |
| 215 | + - const: sdhci | |
| 216 | + - const: tmclk | |
| 217 | + minItems: 2 | |
| 218 | + maxItems: 2 | |
| 219 | + required: | |
| 220 | + - clock-names | |
| 221 | + | |
| 222 | + - if: | |
| 223 | + properties: | |
| 224 | + compatible: | |
| 225 | + contains: | |
| 226 | + const: nvidia,tegra210-sdhci | |
| 227 | + then: | |
| 228 | + properties: | |
| 229 | + pinctrl-names: | |
| 230 | + oneOf: | |
| 231 | + - items: | |
| 232 | + - const: sdmmc-3v3 | |
| 233 | + description: pad configuration for 3.3 V | |
| 234 | + - const: sdmmc-1v8 | |
| 235 | + description: pad configuration for 1.8 V | |
| 236 | + - const: sdmmc-3v3-drv | |
| 237 | + description: pull-up/down configuration for 3.3 V | |
| 238 | + - const: sdmmc-1v8-drv | |
| 239 | + description: pull-up/down configuration for 1.8 V | |
| 240 | + - items: | |
| 241 | + - const: sdmmc-3v3-drv | |
| 242 | + description: pull-up/down configuration for 3.3 V | |
| 243 | + - const: sdmmc-1v8-drv | |
| 244 | + description: pull-up/down configuration for 1.8 V | |
| 245 | + - items: | |
| 246 | + - const: sdmmc-1v8-drv | |
| 247 | + description: pull-up/down configuration for 1.8 V | |
| 248 | + required: | |
| 249 | + - clock-names | |
| 250 | + - if: | |
| 251 | + properties: | |
| 252 | + compatible: | |
| 253 | + contains: | |
| 254 | + enum: | |
| 255 | + - nvidia,tegra186-sdhci | |
| 256 | + - nvidia,tegra194-sdhci | |
| 257 | + then: | |
| 258 | + properties: | |
| 259 | + pinctrl-names: | |
| 260 | + items: | |
| 261 | + - const: sdmmc-3v3 | |
| 262 | + description: pad configuration for 3.3 V | |
| 263 | + - const: sdmmc-1v8 | |
| 264 | + description: pad configuration for 1.8 V | |
| 265 | + required: | |
| 266 | + - clock-names | |
| 267 | + | |
| 268 | +unevaluatedProperties: false | |
| 269 | + | |
| 270 | +examples: | |
| 271 | + - | | |
| 272 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 273 | + | |
| 274 | + mmc@c8000200 { | |
| 275 | + compatible = "nvidia,tegra20-sdhci"; | |
| 276 | + reg = <0xc8000200 0x200>; | |
| 277 | + interrupts = <47>; | |
| 278 | + clocks = <&tegra_car 14>; | |
| 279 | + resets = <&tegra_car 14>; | |
| 280 | + reset-names = "sdhci"; | |
| 281 | + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | |
| 282 | + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | |
| 283 | + power-gpios = <&gpio 155 0>; /* gpio PT3 */ | |
| 284 | + bus-width = <8>; | |
| 285 | + }; | |
| 286 | + | |
| 287 | + - | | |
| 288 | + #include <dt-bindings/clock/tegra210-car.h> | |
| 289 | + #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 290 | + | |
| 291 | + mmc@700b0000 { | |
| 292 | + compatible = "nvidia,tegra210-sdhci"; | |
| 293 | + reg = <0x700b0000 0x200>; | |
| 294 | + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 295 | + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, | |
| 296 | + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; | |
| 297 | + clock-names = "sdhci", "tmclk"; | |
| 298 | + resets = <&tegra_car 14>; | |
| 299 | + reset-names = "sdhci"; | |
| 300 | + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", | |
| 301 | + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; | |
| 302 | + pinctrl-0 = <&sdmmc1_3v3>; | |
| 303 | + pinctrl-1 = <&sdmmc1_1v8>; | |
| 304 | + pinctrl-2 = <&sdmmc1_3v3_drv>; | |
| 305 | + pinctrl-3 = <&sdmmc1_1v8_drv>; | |
| 306 | + nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; | |
| 307 | + nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; | |
| 308 | + nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; | |
| 309 | + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; | |
| 310 | + nvidia,default-tap = <0x2>; | |
| 311 | + nvidia,default-trim = <0x4>; | |
| 312 | + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, | |
| 313 | + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, | |
| 314 | + <&tegra_car TEGRA210_CLK_PLL_C4>; | |
| 315 | + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; | |
| 316 | + assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; | |
| 317 | + }; | |
| @@ -113,31 +113,51 @@ allOf: · 112 unmodified lines | ||
| 113 | 113 | clocks: |
| 114 | 114 | items: |
| 115 | 115 | - description: IMCLK, SDHI channel main clock1. |
| 116 | + - description: CLK_HS, SDHI channel High speed clock which operates | |
| 117 | + 4 times that of SDHI channel main clock1. | |
| 116 | 118 | - description: IMCLK2, SDHI channel main clock2. When this clock is |
| 117 | 119 | turned off, external SD card detection cannot be |
| 118 | 120 | detected. |
| 119 | − - description: CLK_HS, SDHI channel High speed clock which operates | |
| 120 | − 4 times that of SDHI channel main clock1. | |
| 121 | 121 | - description: ACLK, SDHI channel bus clock. |
| 122 | 122 | clock-names: |
| 123 | 123 | items: |
| 124 | − - const: imclk | |
| 125 | − - const: imclk2 | |
| 126 | − - const: clk_hs | |
| 124 | + - const: core | |
| 125 | + - const: clkh | |
| 126 | + - const: cd | |
| 127 | 127 | - const: aclk |
| 128 | 128 | required: |
| 129 | 129 | - clock-names |
| 130 | 130 | - resets |
| 131 | 131 | else: |
| 132 | − properties: | |
| 133 | − clocks: | |
| 134 | − minItems: 1 | |
| 135 | − maxItems: 2 | |
| 136 | − clock-names: | |
| 137 | − minItems: 1 | |
| 138 | − items: | |
| 139 | − - const: core | |
| 140 | − - const: cd | |
| 132 | + if: | |
| 133 | + properties: | |
| 134 | + compatible: | |
| 135 | + contains: | |
| 136 | + enum: | |
| 137 | + - renesas,rcar-gen2-sdhi | |
| 138 | + - renesas,rcar-gen3-sdhi | |
| 139 | + then: | |
| 140 | + properties: | |
| 141 | + clocks: | |
| 142 | + minItems: 1 | |
| 143 | + maxItems: 3 | |
| 144 | + clock-names: | |
| 145 | + minItems: 1 | |
| 146 | + uniqueItems: true | |
| 147 | + items: | |
| 148 | + - const: core | |
| 149 | + - enum: [ clkh, cd ] | |
| 150 | + - const: cd | |
| 151 | + else: | |
| 152 | + properties: | |
| 153 | + clocks: | |
| 154 | + minItems: 1 | |
| 155 | + maxItems: 2 | |
| 156 | + clock-names: | |
| 157 | + minItems: 1 | |
| 158 | + items: | |
| 159 | + - const: core | |
| 160 | + - const: cd | |
| 141 | 161 | |
| 142 | 162 | - if: |
| 143 | 163 | properties: |
| @@ -28,19 +28,17 @@ description: | · 27 unmodified lines | ||
| 28 | 28 | distributed over the root ports as the OS sees fit by programming |
| 29 | 29 | the PCIe controller's port registers. |
| 30 | 30 | |
| 31 | −allOf: | |
| 32 | − - $ref: /schemas/pci/pci-bus.yaml# | |
| 33 | − - $ref: /schemas/interrupt-controller/msi-controller.yaml# | |
| 34 | − | |
| 35 | 31 | properties: |
| 36 | 32 | compatible: |
| 37 | 33 | items: |
| 38 | − - const: apple,t8103-pcie | |
| 34 | + - enum: | |
| 35 | + - apple,t8103-pcie | |
| 36 | + - apple,t6000-pcie | |
| 39 | 37 | - const: apple,pcie |
| 40 | 38 | |
| 41 | 39 | reg: |
| 42 | 40 | minItems: 3 |
| 43 | − maxItems: 5 | |
| 41 | + maxItems: 6 | |
| 44 | 42 | |
| 45 | 43 | reg-names: |
| 46 | 44 | minItems: 3 |
| @@ -50,6 +48,7 @@ properties: · 3 unmodified lines | ||
| 50 | 48 | - const: port0 |
| 51 | 49 | - const: port1 |
| 52 | 50 | - const: port2 |
| 51 | + - const: port3 | |
| 53 | 52 | |
| 54 | 53 | ranges: |
| 55 | 54 | minItems: 2 |
| @@ -59,7 +58,7 @@ properties: · 3 unmodified lines | ||
| 59 | 58 | description: |
| 60 | 59 | Interrupt specifiers, one for each root port. |
| 61 | 60 | minItems: 1 |
| 62 | − maxItems: 3 | |
| 61 | + maxItems: 4 | |
| 63 | 62 | |
| 64 | 63 | msi-parent: true |
| 65 | 64 | |
| @@ -81,6 +80,21 @@ required: · 15 unmodified lines | ||
| 81 | 80 | |
| 82 | 81 | unevaluatedProperties: false |
| 83 | 82 | |
| 83 | +allOf: | |
| 84 | + - $ref: /schemas/pci/pci-bus.yaml# | |
| 85 | + - $ref: /schemas/interrupt-controller/msi-controller.yaml# | |
| 86 | + - if: | |
| 87 | + properties: | |
| 88 | + compatible: | |
| 89 | + contains: | |
| 90 | + const: apple,t8103-pcie | |
| 91 | + then: | |
| 92 | + properties: | |
| 93 | + reg: | |
| 94 | + maxItems: 5 | |
| 95 | + interrupts: | |
| 96 | + maxItems: 3 | |
| 97 | + | |
| 84 | 98 | examples: |
| 85 | 99 | - | |
| 86 | 100 | #include <dt-bindings/interrupt-controller/apple-aic.h> |
| @@ -17,7 +17,9 @@ description: | · 16 unmodified lines | ||
| 17 | 17 | properties: |
| 18 | 18 | compatible: |
| 19 | 19 | items: |
| 20 | − - const: apple,t8103-pinctrl | |
| 20 | + - enum: | |
| 21 | + - apple,t8103-pinctrl | |
| 22 | + - apple,t6000-pinctrl | |
| 21 | 23 | - const: apple,pinctrl |
| 22 | 24 | |
| 23 | 25 | reg: |
| @@ -50,6 +52,9 @@ properties: · 26 unmodified lines | ||
| 50 | 52 | '#interrupt-cells': |
| 51 | 53 | const: 2 |
| 52 | 54 | |
| 55 | + power-domains: | |
| 56 | + maxItems: 1 | |
| 57 | + | |
| 53 | 58 | patternProperties: |
| 54 | 59 | '-pins$': |
| 55 | 60 | type: object |
| @@ -0,0 +1,79 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Apple SoC PMGR Power States | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Hector Martin <marcan@marcan.st> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: "power-domain.yaml#" | |
| 14 | + | |
| 15 | +description: | | |
| 16 | + Apple SoCs include PMGR blocks responsible for power management, | |
| 17 | + which can control various clocks, resets, power states, and | |
| 18 | + performance features. This binding describes the device power | |
| 19 | + state registers, which control power states and resets. | |
| 20 | + | |
| 21 | + Each instance of a power controller within the PMGR syscon node | |
| 22 | + represents a generic power domain provider, as documented in | |
| 23 | + Documentation/devicetree/bindings/power/power-domain.yaml. | |
| 24 | + The provider controls a single SoC block. The power hierarchy is | |
| 25 | + represented via power-domains relationships between these nodes. | |
| 26 | + | |
| 27 | + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml | |
| 28 | + for the top-level PMGR node documentation. | |
| 29 | + | |
| 30 | +properties: | |
| 31 | + compatible: | |
| 32 | + items: | |
| 33 | + - enum: | |
| 34 | + - apple,t8103-pmgr-pwrstate | |
| 35 | + - apple,t6000-pmgr-pwrstate | |
| 36 | + - const: apple,pmgr-pwrstate | |
| 37 | + | |
| 38 | + reg: | |
| 39 | + maxItems: 1 | |
| 40 | + | |
| 41 | + "#power-domain-cells": | |
| 42 | + const: 0 | |
| 43 | + | |
| 44 | + "#reset-cells": | |
| 45 | + const: 0 | |
| 46 | + | |
| 47 | + power-domains: | |
| 48 | + description: | |
| 49 | + Reference to parent power domains. A domain may have multiple parents, | |
| 50 | + and all will be powered up when it is powered. | |
| 51 | + minItems: 1 | |
| 52 | + maxItems: 8 # Arbitrary, should be enough | |
| 53 | + | |
| 54 | + label: | |
| 55 | + description: | |
| 56 | + Specifies the name of the SoC domain being controlled. This is used to | |
| 57 | + name the power/reset domains. | |
| 58 | + | |
| 59 | + apple,always-on: | |
| 60 | + description: | |
| 61 | + Forces this power domain to always be powered up. | |
| 62 | + type: boolean | |
| 63 | + | |
| 64 | + apple,min-state: | |
| 65 | + description: | |
| 66 | + Specifies the minimum power state for auto-PM. | |
| 67 | + 0 = power gated, 4 = clock gated, 15 = on. | |
| 68 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 69 | + minimum: 0 | |
| 70 | + maximum: 15 | |
| 71 | + | |
| 72 | +required: | |
| 73 | + - compatible | |
| 74 | + - reg | |
| 75 | + - "#power-domain-cells" | |
| 76 | + - "#reset-cells" | |
| 77 | + - label | |
| 78 | + | |
| 79 | +additionalProperties: false | |
| @@ -41,6 +41,7 @@ properties: · 40 unmodified lines | ||
| 41 | 41 | - renesas,r8a77990-sysc # R-Car E3 |
| 42 | 42 | - renesas,r8a77995-sysc # R-Car D3 |
| 43 | 43 | - renesas,r8a779a0-sysc # R-Car V3U |
| 44 | + - renesas,r8a779f0-sysc # R-Car S4-8 | |
| 44 | 45 | |
| 45 | 46 | reg: |
| 46 | 47 | maxItems: 1 |
| @@ -48,6 +48,7 @@ properties: · 47 unmodified lines | ||
| 48 | 48 | - renesas,r8a77990-rst # R-Car E3 |
| 49 | 49 | - renesas,r8a77995-rst # R-Car D3 |
| 50 | 50 | - renesas,r8a779a0-rst # R-Car V3U |
| 51 | + - renesas,r8a779f0-rst # R-Car S4-8 | |
| 51 | 52 | |
| 52 | 53 | reg: |
| 53 | 54 | maxItems: 1 |
| @@ -1,24 +0,0 @@ | ||
| 1 | −NVIDIA Tegra20 real-time clock | |
| 2 | − | |
| 3 | −The Tegra RTC maintains seconds and milliseconds counters, and five alarm | |
| 4 | −registers. The alarms and other interrupts may wake the system from low-power | |
| 5 | −state. | |
| 6 | − | |
| 7 | −Required properties: | |
| 8 | − | |
| 9 | −- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, | |
| 10 | − must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip> | |
| 11 | − can be tegra30, tegra114, tegra124, or tegra132. | |
| 12 | −- reg : Specifies base physical address and size of the registers. | |
| 13 | −- interrupts : A single interrupt specifier. | |
| 14 | −- clocks : Must contain one entry, for the module clock. | |
| 15 | − See ../clocks/clock-bindings.txt for details. | |
| 16 | − | |
| 17 | −Example: | |
| 18 | − | |
| 19 | −timer { | |
| 20 | − compatible = "nvidia,tegra20-rtc"; | |
| 21 | − reg = <0x7000e000 0x100>; | |
| 22 | − interrupts = <0 2 0x04>; | |
| 23 | − clocks = <&tegra_car 4>; | |
| 24 | −}; | |
| @@ -0,0 +1,61 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra real-time clock | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: | | |
| 14 | + The Tegra RTC maintains seconds and milliseconds counters, and five | |
| 15 | + alarm registers. The alarms and other interrupts may wake the system | |
| 16 | + from low-power state. | |
| 17 | + | |
| 18 | +properties: | |
| 19 | + compatible: | |
| 20 | + oneOf: | |
| 21 | + - const: nvidia,tegra20-rtc | |
| 22 | + - items: | |
| 23 | + - enum: | |
| 24 | + - nvidia,tegra30-rtc | |
| 25 | + - nvidia,tegra114-rtc | |
| 26 | + - nvidia,tegra124-rtc | |
| 27 | + - nvidia,tegra210-rtc | |
| 28 | + - nvidia,tegra186-rtc | |
| 29 | + - nvidia,tegra194-rtc | |
| 30 | + - nvidia,tegra234-rtc | |
| 31 | + - const: nvidia,tegra20-rtc | |
| 32 | + | |
| 33 | + reg: | |
| 34 | + maxItems: 1 | |
| 35 | + | |
| 36 | + interrupts: | |
| 37 | + maxItems: 1 | |
| 38 | + | |
| 39 | + clocks: | |
| 40 | + maxItems: 1 | |
| 41 | + | |
| 42 | + clock-names: | |
| 43 | + items: | |
| 44 | + - const: rtc | |
| 45 | + | |
| 46 | +additionalProperties: false | |
| 47 | + | |
| 48 | +required: | |
| 49 | + - compatible | |
| 50 | + - reg | |
| 51 | + - interrupts | |
| 52 | + - clocks | |
| 53 | + | |
| 54 | +examples: | |
| 55 | + - | | |
| 56 | + timer@7000e000 { | |
| 57 | + compatible = "nvidia,tegra20-rtc"; | |
| 58 | + reg = <0x7000e000 0x100>; | |
| 59 | + interrupts = <0 2 0x04>; | |
| 60 | + clocks = <&tegra_car 4>; | |
| 61 | + }; | |
| @@ -113,9 +113,10 @@ properties: · 112 unmodified lines | ||
| 113 | 113 | - nvidia,tegra30-uart |
| 114 | 114 | - nvidia,tegra114-uart |
| 115 | 115 | - nvidia,tegra124-uart |
| 116 | + - nvidia,tegra210-uart | |
| 116 | 117 | - nvidia,tegra186-uart |
| 117 | 118 | - nvidia,tegra194-uart |
| 118 | − - nvidia,tegra210-uart | |
| 119 | + - nvidia,tegra234-uart | |
| 119 | 120 | - const: nvidia,tegra20-uart |
| 120 | 121 | |
| 121 | 122 | reg: |
| @@ -1,35 +0,0 @@ | ||
| 1 | −NVIDIA Tegra Combined UART (TCU) | |
| 2 | − | |
| 3 | −The TCU is a system for sharing a hardware UART instance among multiple | |
| 4 | −systems within the Tegra SoC. It is implemented through a mailbox- | |
| 5 | −based protocol where each "virtual UART" has a pair of mailboxes, one | |
| 6 | −for transmitting and one for receiving, that is used to communicate | |
| 7 | −with the hardware implementing the TCU. | |
| 8 | − | |
| 9 | −Required properties: | |
| 10 | −- name : Should be tcu | |
| 11 | −- compatible | |
| 12 | − Array of strings | |
| 13 | − One of: | |
| 14 | − - "nvidia,tegra194-tcu" | |
| 15 | −- mbox-names: | |
| 16 | − "rx" - Mailbox for receiving data from hardware UART | |
| 17 | − "tx" - Mailbox for transmitting data to hardware UART | |
| 18 | −- mboxes: Mailboxes corresponding to the mbox-names. | |
| 19 | − | |
| 20 | −This node is a mailbox consumer. See the following files for details of | |
| 21 | −the mailbox subsystem, and the specifiers implemented by the relevant | |
| 22 | −provider(s): | |
| 23 | − | |
| 24 | −- .../mailbox/mailbox.txt | |
| 25 | −- .../mailbox/nvidia,tegra186-hsp.txt | |
| 26 | − | |
| 27 | −Example bindings: | |
| 28 | −----------------- | |
| 29 | − | |
| 30 | −tcu: tcu { | |
| 31 | − compatible = "nvidia,tegra194-tcu"; | |
| 32 | − mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, | |
| 33 | − <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; | |
| 34 | − mbox-names = "rx", "tx"; | |
| 35 | −}; | |
| @@ -0,0 +1,61 @@ | ||
| 1 | +# SPDX-License-Identifier: GPL-2.0 | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra Combined UART (TCU) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jonathan Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: | |
| 14 | + The TCU is a system for sharing a hardware UART instance among multiple | |
| 15 | + systems within the Tegra SoC. It is implemented through a mailbox- | |
| 16 | + based protocol where each "virtual UART" has a pair of mailboxes, one | |
| 17 | + for transmitting and one for receiving, that is used to communicate | |
| 18 | + with the hardware implementing the TCU. | |
| 19 | + | |
| 20 | +properties: | |
| 21 | + $nodename: | |
| 22 | + pattern: "^serial(@.*)?$" | |
| 23 | + | |
| 24 | + compatible: | |
| 25 | + oneOf: | |
| 26 | + - const: nvidia,tegra194-tcu | |
| 27 | + - items: | |
| 28 | + - enum: | |
| 29 | + - nvidia,tegra234-tcu | |
| 30 | + - const: nvidia,tegra194-tcu | |
| 31 | + | |
| 32 | + mbox-names: | |
| 33 | + items: | |
| 34 | + - const: rx | |
| 35 | + - const: tx | |
| 36 | + | |
| 37 | + mboxes: | |
| 38 | + description: | | |
| 39 | + List of phandles to mailbox channels used for receiving and | |
| 40 | + transmitting data from and to the hardware UART. | |
| 41 | + items: | |
| 42 | + - description: mailbox for receiving data from hardware UART | |
| 43 | + - description: mailbox for transmitting data to hardware UART | |
| 44 | + | |
| 45 | +required: | |
| 46 | + - compatible | |
| 47 | + - mbox-names | |
| 48 | + - mboxes | |
| 49 | + | |
| 50 | +additionalProperties: false | |
| 51 | + | |
| 52 | +examples: | |
| 53 | + - | | |
| 54 | + #include <dt-bindings/mailbox/tegra186-hsp.h> | |
| 55 | + | |
| 56 | + tcu: serial { | |
| 57 | + compatible = "nvidia,tegra194-tcu"; | |
| 58 | + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, | |
| 59 | + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; | |
| 60 | + mbox-names = "rx", "tx"; | |
| 61 | + }; | |
| @@ -1,17 +0,0 @@ | ||
| 1 | −Broadcom VCHIQ firmware services | |
| 2 | − | |
| 3 | −Required properties: | |
| 4 | − | |
| 5 | −- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise | |
| 6 | − "brcm,bcm2836-vchiq". | |
| 7 | −- reg: Physical base address and length of the doorbell register pair | |
| 8 | −- interrupts: The interrupt number | |
| 9 | − See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt | |
| 10 | − | |
| 11 | −Example: | |
| 12 | − | |
| 13 | −mailbox@7e00b840 { | |
| 14 | − compatible = "brcm,bcm2835-vchiq"; | |
| 15 | − reg = <0x7e00b840 0xf>; | |
| 16 | − interrupts = <0 2>; | |
| 17 | −}; | |
| @@ -0,0 +1,53 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-vchiq.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Broadcom VCHIQ firmware services | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Nicolas Saenz Julienne <nsaenz@kernel.org> | |
| 11 | + | |
| 12 | +description: | |
| 13 | + The VCHIQ communication channel can be provided by BCM283x and Capri SoCs, | |
| 14 | + to communicate with the VPU-side OS services. | |
| 15 | + | |
| 16 | +properties: | |
| 17 | + compatible: | |
| 18 | + oneOf: | |
| 19 | + - description: BCM2835 based boards | |
| 20 | + items: | |
| 21 | + - enum: | |
| 22 | + - brcm,bcm2835-vchiq | |
| 23 | + | |
| 24 | + - description: BCM2836/BCM2837 based boards | |
| 25 | + items: | |
| 26 | + - enum: | |
| 27 | + - brcm,bcm2836-vchiq | |
| 28 | + - const: brcm,bcm2835-vchiq | |
| 29 | + | |
| 30 | + reg: | |
| 31 | + description: Physical base address and length of the doorbell register pair | |
| 32 | + minItems: 1 | |
| 33 | + | |
| 34 | + interrupts: | |
| 35 | + description: Interrupt number of the doorbell interrupt | |
| 36 | + minItems: 1 | |
| 37 | + | |
| 38 | +required: | |
| 39 | + - compatible | |
| 40 | + - reg | |
| 41 | + - interrupts | |
| 42 | + | |
| 43 | +additionalProperties: false | |
| 44 | + | |
| 45 | +examples: | |
| 46 | + - | | |
| 47 | + mailbox@7e00b840 { | |
| 48 | + compatible = "brcm,bcm2835-vchiq"; | |
| 49 | + reg = <0x7e00b840 0xf>; | |
| 50 | + interrupts = <0 2>; | |
| 51 | + }; | |
| 52 | + | |
| 53 | +... | |
| @@ -0,0 +1,97 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NXP i.MX8MN DISP blk-ctrl | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Lucas Stach <l.stach@pengutronix.de> | |
| 11 | + | |
| 12 | +description: | |
| 13 | + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to | |
| 14 | + the NoC and ensuring proper power sequencing of the display and MIPI CSI | |
| 15 | + peripherals located in the DISP domain of the SoC. | |
| 16 | + | |
| 17 | +properties: | |
| 18 | + compatible: | |
| 19 | + items: | |
| 20 | + - const: fsl,imx8mn-disp-blk-ctrl | |
| 21 | + - const: syscon | |
| 22 | + | |
| 23 | + reg: | |
| 24 | + maxItems: 1 | |
| 25 | + | |
| 26 | + '#power-domain-cells': | |
| 27 | + const: 1 | |
| 28 | + | |
| 29 | + power-domains: | |
| 30 | + minItems: 5 | |
| 31 | + maxItems: 5 | |
| 32 | + | |
| 33 | + power-domain-names: | |
| 34 | + items: | |
| 35 | + - const: bus | |
| 36 | + - const: isi | |
| 37 | + - const: lcdif | |
| 38 | + - const: mipi-dsi | |
| 39 | + - const: mipi-csi | |
| 40 | + | |
| 41 | + clocks: | |
| 42 | + minItems: 11 | |
| 43 | + maxItems: 11 | |
| 44 | + | |
| 45 | + clock-names: | |
| 46 | + items: | |
| 47 | + - const: disp_axi | |
| 48 | + - const: disp_apb | |
| 49 | + - const: disp_axi_root | |
| 50 | + - const: disp_apb_root | |
| 51 | + - const: lcdif-axi | |
| 52 | + - const: lcdif-apb | |
| 53 | + - const: lcdif-pix | |
| 54 | + - const: dsi-pclk | |
| 55 | + - const: dsi-ref | |
| 56 | + - const: csi-aclk | |
| 57 | + - const: csi-pclk | |
| 58 | + | |
| 59 | +required: | |
| 60 | + - compatible | |
| 61 | + - reg | |
| 62 | + - power-domains | |
| 63 | + - power-domain-names | |
| 64 | + - clocks | |
| 65 | + - clock-names | |
| 66 | + | |
| 67 | +additionalProperties: false | |
| 68 | + | |
| 69 | +examples: | |
| 70 | + - | | |
| 71 | + #include <dt-bindings/clock/imx8mn-clock.h> | |
| 72 | + #include <dt-bindings/power/imx8mn-power.h> | |
| 73 | + | |
| 74 | + disp_blk_ctl: blk_ctrl@32e28000 { | |
| 75 | + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; | |
| 76 | + reg = <0x32e28000 0x100>; | |
| 77 | + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, | |
| 78 | + <&pgc_dispmix>, <&pgc_mipi>, | |
| 79 | + <&pgc_mipi>; | |
| 80 | + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi", | |
| 81 | + "mipi-csi"; | |
| 82 | + clocks = <&clk IMX8MN_CLK_DISP_AXI>, | |
| 83 | + <&clk IMX8MN_CLK_DISP_APB>, | |
| 84 | + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, | |
| 85 | + <&clk IMX8MN_CLK_DISP_APB_ROOT>, | |
| 86 | + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, | |
| 87 | + <&clk IMX8MN_CLK_DISP_APB_ROOT>, | |
| 88 | + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, | |
| 89 | + <&clk IMX8MN_CLK_DSI_CORE>, | |
| 90 | + <&clk IMX8MN_CLK_DSI_PHY_REF>, | |
| 91 | + <&clk IMX8MN_CLK_CSI1_PHY_REF>, | |
| 92 | + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; | |
| 93 | + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root", | |
| 94 | + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", | |
| 95 | + "dsi-ref", "csi-aclk", "csi-pclk"; | |
| 96 | + #power-domain-cells = <1>; | |
| 97 | + }; | |
| @@ -152,8 +152,8 @@ examples: · 151 unmodified lines | ||
| 152 | 152 | interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| 153 | 153 | #address-cells = <1>; |
| 154 | 154 | #size-cells = <0>; |
| 155 | − clocks = <&cmu_peri 32>, <&cmu_peri 31>; | |
| 156 | − clock-names = "hsi2c_pclk", "hsi2c"; | |
| 155 | + clocks = <&cmu_peri 31>, <&cmu_peri 32>; | |
| 156 | + clock-names = "hsi2c", "hsi2c_pclk"; | |
| 157 | 157 | status = "disabled"; |
| 158 | 158 | }; |
| 159 | 159 | }; |
| @@ -31,6 +31,9 @@ properties: · 30 unmodified lines | ||
| 31 | 31 | - amlogic,meson-gxbb-sram |
| 32 | 32 | - arm,juno-sram-ns |
| 33 | 33 | - atmel,sama5d2-securam |
| 34 | + - nvidia,tegra186-sysram | |
| 35 | + - nvidia,tegra194-sysram | |
| 36 | + - nvidia,tegra234-sysram | |
| 34 | 37 | - qcom,rpm-msg-ram |
| 35 | 38 | - rockchip,rk3288-pmu-sram |
| 36 | 39 | |
| @@ -1,33 +0,0 @@ | ||
| 1 | −NVIDIA Tegra186 BPMP thermal sensor | |
| 2 | − | |
| 3 | −In Tegra186, the BPMP (Boot and Power Management Processor) implements an | |
| 4 | −interface that is used to read system temperatures, including CPU cluster | |
| 5 | −and GPU temperatures. This binding describes the thermal sensor that is | |
| 6 | −exposed by BPMP. | |
| 7 | − | |
| 8 | −The BPMP thermal node must be located directly inside the main BPMP node. See | |
| 9 | −../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. | |
| 10 | − | |
| 11 | −This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the | |
| 12 | −core thermal binding. | |
| 13 | − | |
| 14 | −Required properties: | |
| 15 | −- compatible: | |
| 16 | − Array of strings. | |
| 17 | − One of: | |
| 18 | − - "nvidia,tegra186-bpmp-thermal" | |
| 19 | − - "nvidia,tegra194-bpmp-thermal" | |
| 20 | −- #thermal-sensor-cells: Cell for sensor index. | |
| 21 | − Single-cell integer. | |
| 22 | − Must be <1>. | |
| 23 | − | |
| 24 | −Example: | |
| 25 | − | |
| 26 | −bpmp { | |
| 27 | − ... | |
| 28 | − | |
| 29 | − bpmp_thermal: thermal { | |
| 30 | − compatible = "nvidia,tegra186-bpmp-thermal"; | |
| 31 | − #thermal-sensor-cells = <1>; | |
| 32 | − }; | |
| 33 | −}; | |
| @@ -0,0 +1,42 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: NVIDIA Tegra186 (and later) BPMP thermal sensor | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Thierry Reding <thierry.reding@gmail.com> | |
| 11 | + - Jon Hunter <jonathanh@nvidia.com> | |
| 12 | + | |
| 13 | +description: | | |
| 14 | + In Tegra186, the BPMP (Boot and Power Management Processor) implements | |
| 15 | + an interface that is used to read system temperatures, including CPU | |
| 16 | + cluster and GPU temperatures. This binding describes the thermal | |
| 17 | + sensor that is exposed by BPMP. | |
| 18 | + | |
| 19 | + The BPMP thermal node must be located directly inside the main BPMP | |
| 20 | + node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the | |
| 21 | + BPMP binding. | |
| 22 | + | |
| 23 | + This node represents a thermal sensor. See | |
| 24 | + | |
| 25 | + Documentation/devicetree/bindings/thermal/thermal-sensor.yaml | |
| 26 | + | |
| 27 | + for details of the core thermal binding. | |
| 28 | + | |
| 29 | +properties: | |
| 30 | + compatible: | |
| 31 | + enum: | |
| 32 | + - nvidia,tegra186-bpmp-thermal | |
| 33 | + - nvidia,tegra194-bpmp-thermal | |
| 34 | + | |
| 35 | + '#thermal-sensor-cells': | |
| 36 | + $ref: /schemas/types.yaml#/definitions/uint32 | |
| 37 | + description: Number of cells needed in the phandle specifier to | |
| 38 | + identify a given sensor. Must be 1 and the single cell specifies | |
| 39 | + the sensor index. | |
| 40 | + const: 1 | |
| 41 | + | |
| 42 | +additionalProperties: false | |
| @@ -59,6 +59,19 @@ properties: · 58 unmodified lines | ||
| 59 | 59 | - const: fs_src |
| 60 | 60 | - const: hs_src |
| 61 | 61 | |
| 62 | + interconnects: | |
| 63 | + items: | |
| 64 | + - description: memory read client | |
| 65 | + - description: memory write client | |
| 66 | + | |
| 67 | + interconnect-names: | |
| 68 | + items: | |
| 69 | + - const: dma-mem # read | |
| 70 | + - const: write | |
| 71 | + | |
| 72 | + iommus: | |
| 73 | + maxItems: 1 | |
| 74 | + | |
| 62 | 75 | power-domains: |
| 63 | 76 | items: |
| 64 | 77 | - description: XUSBB(device) power-domain |
| @@ -187,6 +187,8 @@ patternProperties: · 186 unmodified lines | ||
| 187 | 187 | description: Shanghai Broadmobi Communication Technology Co.,Ltd. |
| 188 | 188 | "^brcm,.*": |
| 189 | 189 | description: Broadcom Corporation |
| 190 | + "^bsh,.*": | |
| 191 | + description: BSH Hausgeraete GmbH | |
| 190 | 192 | "^buffalo,.*": |
| 191 | 193 | description: Buffalo, Inc. |
| 192 | 194 | "^bur,.*": |
| @@ -593,6 +595,8 @@ patternProperties: · 400 unmodified lines | ||
| 593 | 595 | description: JetHome (IP Sokolov P.A.) |
| 594 | 596 | "^jianda,.*": |
| 595 | 597 | description: Jiandangjing Technology Co., Ltd. |
| 598 | + "^joz,.*": | |
| 599 | + description: JOZ BV | |
| 596 | 600 | "^kam,.*": |
| 597 | 601 | description: Kamstrup A/S |
| 598 | 602 | "^karo,.*": |
| @@ -1318,6 +1322,8 @@ patternProperties: · 719 unmodified lines | ||
| 1318 | 1322 | description: Wiligear, Ltd. |
| 1319 | 1323 | "^winbond,.*": |
| 1320 | 1324 | description: Winbond Electronics corp. |
| 1325 | + "^winlink,.*": | |
| 1326 | + description: WinLink Co., Ltd | |
| 1321 | 1327 | "^winstar,.*": |
| 1322 | 1328 | description: Winstar Display Corp. |
| 1323 | 1329 | "^wits,.*": |
| @@ -1350,6 +1356,8 @@ patternProperties: · 26 unmodified lines | ||
| 1350 | 1356 | description: Shenzhen Xunlong Software CO.,Limited |
| 1351 | 1357 | "^xylon,.*": |
| 1352 | 1358 | description: Xylon |
| 1359 | + "^yadro,.*": | |
| 1360 | + description: YADRO | |
| 1353 | 1361 | "^yamaha,.*": |
| 1354 | 1362 | description: Yamaha Corporation |
| 1355 | 1363 | "^yes-optoelectronics,.*": |
| @@ -0,0 +1,52 @@ | ||
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Apple SoC Watchdog | |
| 8 | + | |
| 9 | +allOf: | |
| 10 | + - $ref: "watchdog.yaml#" | |
| 11 | + | |
| 12 | +maintainers: | |
| 13 | + - Sven Peter <sven@svenpeter.dev> | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + items: | |
| 18 | + - enum: | |
| 19 | + - apple,t8103-wdt | |
| 20 | + - apple,t6000-wdt | |
| 21 | + - const: apple,wdt | |
| 22 | + | |
| 23 | + reg: | |
| 24 | + maxItems: 1 | |
| 25 | + | |
| 26 | + clocks: | |
| 27 | + maxItems: 1 | |
| 28 | + | |
| 29 | + interrupts: | |
| 30 | + maxItems: 1 | |
| 31 | + | |
| 32 | +required: | |
| 33 | + - compatible | |
| 34 | + - reg | |
| 35 | + - clocks | |
| 36 | + - interrupts | |
| 37 | + | |
| 38 | +unevaluatedProperties: false | |
| 39 | + | |
| 40 | +examples: | |
| 41 | + - | | |
| 42 | + #include <dt-bindings/interrupt-controller/apple-aic.h> | |
| 43 | + #include <dt-bindings/interrupt-controller/irq.h> | |
| 44 | + | |
| 45 | + wdt: watchdog@50000000 { | |
| 46 | + compatible = "apple,t8103-wdt", "apple,wdt"; | |
| 47 | + reg = <0x50000000 0x4000>; | |
| 48 | + clocks = <&clk>; | |
| 49 | + interrupts = <AIC_IRQ 123 IRQ_TYPE_LEVEL_HIGH>; | |
| 50 | + }; | |
| 51 | + | |
| 52 | +... | |
| @@ -1745,17 +1745,21 @@ B: https://github.com/AsahiLinux/linux/issues · 1744 unmodified lines | ||
| 1745 | 1745 | C: irc://irc.oftc.net/asahi-dev |
| 1746 | 1746 | T: git https://github.com/AsahiLinux/linux.git |
| 1747 | 1747 | F: Documentation/devicetree/bindings/arm/apple.yaml |
| 1748 | +F: Documentation/devicetree/bindings/arm/apple/* | |
| 1748 | 1749 | F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml |
| 1749 | 1750 | F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml |
| 1750 | 1751 | F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml |
| 1751 | 1752 | F: Documentation/devicetree/bindings/pci/apple,pcie.yaml |
| 1752 | 1753 | F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml |
| 1754 | +F: Documentation/devicetree/bindings/power/apple* | |
| 1755 | +F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml | |
| 1753 | 1756 | F: arch/arm64/boot/dts/apple/ |
| 1754 | 1757 | F: drivers/i2c/busses/i2c-pasemi-core.c |
| 1755 | 1758 | F: drivers/i2c/busses/i2c-pasemi-platform.c |
| 1756 | 1759 | F: drivers/irqchip/irq-apple-aic.c |
| 1757 | 1760 | F: drivers/mailbox/apple-mailbox.c |
| 1758 | 1761 | F: drivers/pinctrl/pinctrl-apple-gpio.c |
| 1762 | +F: drivers/soc/apple/* | |
| 1759 | 1763 | F: include/dt-bindings/interrupt-controller/apple-aic.h |
| 1760 | 1764 | F: include/dt-bindings/pinctrl/apple.h |
| 1761 | 1765 | F: include/linux/apple-mailbox.h |
| @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ · 60 unmodified lines | ||
| 61 | 61 | at91-sama5d2_icp.dtb \ |
| 62 | 62 | at91-sama5d2_ptc_ek.dtb \ |
| 63 | 63 | at91-sama5d2_xplained.dtb \ |
| 64 | + at91-sama5d3_ksz9477_evb.dtb \ | |
| 64 | 65 | at91-sama5d3_xplained.dtb \ |
| 65 | 66 | at91-dvk_som60.dtb \ |
| 66 | 67 | at91-gatwick.dtb \ |
| @@ -263,12 +264,14 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ · 196 unmodified lines | ||
| 263 | 264 | intel-ixp46x-ixdp465.dtb \ |
| 264 | 265 | intel-ixp42x-adi-coyote.dtb \ |
| 265 | 266 | intel-ixp42x-ixdpg425.dtb \ |
| 267 | + intel-ixp42x-goramo-multilink.dtb \ | |
| 266 | 268 | intel-ixp42x-iomega-nas100d.dtb \ |
| 267 | 269 | intel-ixp42x-dlink-dsm-g600.dtb \ |
| 268 | 270 | intel-ixp42x-gateworks-gw2348.dtb \ |
| 269 | 271 | intel-ixp43x-gateworks-gw2358.dtb \ |
| 270 | 272 | intel-ixp42x-netgear-wg302v2.dtb \ |
| 271 | − intel-ixp42x-arcom-vulcan.dtb | |
| 273 | + intel-ixp42x-arcom-vulcan.dtb \ | |
| 274 | + intel-ixp42x-gateway-7001.dtb | |
| 272 | 275 | dtb-$(CONFIG_ARCH_KEYSTONE) += \ |
| 273 | 276 | keystone-k2hk-evm.dtb \ |
| 274 | 277 | keystone-k2l-evm.dtb \ |
| @@ -483,6 +486,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ · 208 unmodified lines | ||
| 483 | 486 | imx6dl-icore-rqs.dtb \ |
| 484 | 487 | imx6dl-lanmcu.dtb \ |
| 485 | 488 | imx6dl-mamoj.dtb \ |
| 489 | + imx6dl-mba6a.dtb \ | |
| 490 | + imx6dl-mba6b.dtb \ | |
| 486 | 491 | imx6dl-nit6xlite.dtb \ |
| 487 | 492 | imx6dl-nitrogen6x.dtb \ |
| 488 | 493 | imx6dl-phytec-mira-rdk-nand.dtb \ |
| @@ -584,6 +589,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ · 95 unmodified lines | ||
| 584 | 589 | imx6q-kp-tpc.dtb \ |
| 585 | 590 | imx6q-logicpd.dtb \ |
| 586 | 591 | imx6q-marsboard.dtb \ |
| 592 | + imx6q-mba6a.dtb \ | |
| 593 | + imx6q-mba6b.dtb \ | |
| 587 | 594 | imx6q-mccmon6.dtb \ |
| 588 | 595 | imx6q-nitrogen6x.dtb \ |
| 589 | 596 | imx6q-nitrogen6_max.dtb \ |
| @@ -628,7 +635,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ · 38 unmodified lines | ||
| 628 | 635 | imx6q-wandboard.dtb \ |
| 629 | 636 | imx6q-wandboard-revb1.dtb \ |
| 630 | 637 | imx6q-wandboard-revd1.dtb \ |
| 638 | + imx6q-yapp4-crux.dtb \ | |
| 631 | 639 | imx6q-zii-rdu2.dtb \ |
| 640 | + imx6qp-mba6b.dtb \ | |
| 632 | 641 | imx6qp-nitrogen6_max.dtb \ |
| 633 | 642 | imx6qp-nitrogen6_som2.dtb \ |
| 634 | 643 | imx6qp-phytec-mira-rdk-nand.dtb \ |
| @@ -641,6 +650,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ · 6 unmodified lines | ||
| 641 | 650 | imx6qp-tx6qp-8137-mb7.dtb \ |
| 642 | 651 | imx6qp-vicutp.dtb \ |
| 643 | 652 | imx6qp-wandboard-revd1.dtb \ |
| 653 | + imx6qp-yapp4-crux-plus.dtb \ | |
| 644 | 654 | imx6qp-zii-rdu2.dtb \ |
| 645 | 655 | imx6s-dhcom-drc02.dtb |
| 646 | 656 | dtb-$(CONFIG_SOC_IMX6SL) += \ |
| @@ -688,12 +698,14 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ · 41 unmodified lines | ||
| 688 | 698 | imx6ull-colibri-emmc-eval-v3.dtb \ |
| 689 | 699 | imx6ull-colibri-eval-v3.dtb \ |
| 690 | 700 | imx6ull-colibri-wifi-eval-v3.dtb \ |
| 701 | + imx6ull-jozacp.dtb \ | |
| 691 | 702 | imx6ull-myir-mys-6ulx-eval.dtb \ |
| 692 | 703 | imx6ull-opos6uldev.dtb \ |
| 693 | 704 | imx6ull-phytec-segin-ff-rdk-nand.dtb \ |
| 694 | 705 | imx6ull-phytec-segin-ff-rdk-emmc.dtb \ |
| 695 | 706 | imx6ull-phytec-segin-lc-rdk-nand.dtb \ |
| 696 | − imx6ulz-14x14-evk.dtb | |
| 707 | + imx6ulz-14x14-evk.dtb \ | |
| 708 | + imx6ulz-bsh-smm-m2.dtb | |
| 697 | 709 | dtb-$(CONFIG_SOC_IMX7D) += \ |
| 698 | 710 | imx7d-cl-som-imx7.dtb \ |
| 699 | 711 | imx7d-colibri-aster.dtb \ |
| @@ -954,6 +966,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ · 254 unmodified lines | ||
| 954 | 966 | ox810se-wd-mbwe.dtb \ |
| 955 | 967 | ox820-cloudengines-pogoplug-series-3.dtb |
| 956 | 968 | dtb-$(CONFIG_ARCH_QCOM) += \ |
| 969 | + qcom-apq8016-sbc.dtb \ | |
| 957 | 970 | qcom-apq8026-lg-lenok.dtb \ |
| 958 | 971 | qcom-apq8060-dragonboard.dtb \ |
| 959 | 972 | qcom-apq8064-cm-qs600.dtb \ |
| @@ -986,7 +999,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ · 26 unmodified lines | ||
| 986 | 999 | qcom-mdm9615-wp8548-mangoh-green.dtb \ |
| 987 | 1000 | qcom-sdx55-mtp.dtb \ |
| 988 | 1001 | qcom-sdx55-t55.dtb \ |
| 989 | − qcom-sdx55-telit-fn980-tlb.dtb | |
| 1002 | + qcom-sdx55-telit-fn980-tlb.dtb \ | |
| 1003 | + qcom-sdx65-mtp.dtb | |
| 990 | 1004 | dtb-$(CONFIG_ARCH_RDA) += \ |
| 991 | 1005 | rda8810pl-orangepi-2g-iot.dtb \ |
| 992 | 1006 | rda8810pl-orangepi-i96.dtb |
| @@ -1140,6 +1154,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ · 147 unmodified lines | ||
| 1140 | 1154 | stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ |
| 1141 | 1155 | stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ |
| 1142 | 1156 | stm32mp157a-icore-stm32mp1-ctouch2.dtb \ |
| 1157 | + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ | |
| 1143 | 1158 | stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ |
| 1144 | 1159 | stm32mp157a-stinger96.dtb \ |
| 1145 | 1160 | stm32mp157c-dhcom-pdk2.dtb \ |
| @@ -1304,6 +1319,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \ · 158 unmodified lines | ||
| 1304 | 1319 | suniv-f1c100s-licheepi-nano.dtb |
| 1305 | 1320 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ |
| 1306 | 1321 | tegra20-acer-a500-picasso.dtb \ |
| 1322 | + tegra20-asus-tf101.dtb \ | |
| 1307 | 1323 | tegra20-harmony.dtb \ |
| 1308 | 1324 | tegra20-colibri-eval-v3.dtb \ |
| 1309 | 1325 | tegra20-colibri-iris.dtb \ |
| @@ -1320,12 +1336,18 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ · 10 unmodified lines | ||
| 1320 | 1336 | tegra30-asus-nexus7-grouper-PM269.dtb \ |
| 1321 | 1337 | tegra30-asus-nexus7-grouper-E1565.dtb \ |
| 1322 | 1338 | tegra30-asus-nexus7-tilapia-E1565.dtb \ |
| 1339 | + tegra30-asus-tf201.dtb \ | |
| 1340 | + tegra30-asus-tf300t.dtb \ | |
| 1341 | + tegra30-asus-tf300tg.dtb \ | |
| 1342 | + tegra30-asus-tf700t.dtb \ | |
| 1323 | 1343 | tegra30-beaver.dtb \ |
| 1324 | 1344 | tegra30-cardhu-a02.dtb \ |
| 1325 | 1345 | tegra30-cardhu-a04.dtb \ |
| 1326 | 1346 | tegra30-colibri-eval-v3.dtb \ |
| 1327 | − tegra30-ouya.dtb | |
| 1347 | + tegra30-ouya.dtb \ | |
| 1348 | + tegra30-pegatron-chagall.dtb | |
| 1328 | 1349 | dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ |
| 1350 | + tegra114-asus-tf701t.dtb \ | |
| 1329 | 1351 | tegra114-dalmore.dtb \ |
| 1330 | 1352 | tegra114-roth.dtb \ |
| 1331 | 1353 | tegra114-tn7.dtb |
| @@ -1334,6 +1356,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ · 2 unmodified lines | ||
| 1334 | 1356 | tegra124-apalis-v1.2-eval.dtb \ |
| 1335 | 1357 | tegra124-jetson-tk1.dtb \ |
| 1336 | 1358 | tegra124-nyan-big.dtb \ |
| 1359 | + tegra124-nyan-big-fhd.dtb \ | |
| 1337 | 1360 | tegra124-nyan-blaze.dtb \ |
| 1338 | 1361 | tegra124-venice2.dtb |
| 1339 | 1362 | dtb-$(CONFIG_ARCH_U8500) += \ |
| @@ -1457,6 +1480,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ · 117 unmodified lines | ||
| 1457 | 1480 | mt2701-evb.dtb \ |
| 1458 | 1481 | mt6580-evbp1.dtb \ |
| 1459 | 1482 | mt6589-aquaris5.dtb \ |
| 1483 | + mt6589-fairphone-fp1.dtb \ | |
| 1460 | 1484 | mt6592-evb.dtb \ |
| 1461 | 1485 | mt7623a-rfb-emmc.dtb \ |
| 1462 | 1486 | mt7623a-rfb-nand.dtb \ |
| @@ -1482,6 +1506,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ · 19 unmodified lines | ||
| 1482 | 1506 | aspeed-bmc-arm-stardragon4800-rep2.dtb \ |
| 1483 | 1507 | aspeed-bmc-asrock-e3c246d4i.dtb \ |
| 1484 | 1508 | aspeed-bmc-bytedance-g220a.dtb \ |
| 1509 | + aspeed-bmc-facebook-bletchley.dtb \ | |
| 1485 | 1510 | aspeed-bmc-facebook-cloudripper.dtb \ |
| 1486 | 1511 | aspeed-bmc-facebook-cmm.dtb \ |
| 1487 | 1512 | aspeed-bmc-facebook-elbert.dtb \ |
| @@ -1519,4 +1544,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ · 31 unmodified lines | ||
| 1519 | 1544 | aspeed-bmc-quanta-q71l.dtb \ |
| 1520 | 1545 | aspeed-bmc-supermicro-x11spi.dtb \ |
| 1521 | 1546 | aspeed-bmc-inventec-transformers.dtb \ |
| 1522 | − aspeed-bmc-tyan-s7106.dtb | |
| 1547 | + aspeed-bmc-tyan-s7106.dtb \ | |
| 1548 | + aspeed-bmc-tyan-s8036.dtb \ | |
| 1549 | + aspeed-bmc-vegman-n110.dtb \ | |
| 1550 | + aspeed-bmc-vegman-rx20.dtb \ | |
| 1551 | + aspeed-bmc-vegman-sx20.dtb | |
| @@ -399,6 +399,7 @@ · 398 unmodified lines | ||
| 399 | 399 | &rtc { |
| 400 | 400 | clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; |
| 401 | 401 | clock-names = "ext-clk", "int-clk"; |
| 402 | + system-power-controller; | |
| 402 | 403 | }; |
| 403 | 404 | |
| 404 | 405 | &pruss_tm { |
| @@ -22,10 +22,6 @@ · 21 unmodified lines | ||
| 22 | 22 | non-removable; |
| 23 | 23 | }; |
| 24 | 24 | |
| 25 | −&rtc { | |
| 26 | − system-power-controller; | |
| 27 | −}; | |
| 28 | − | |
| 29 | 25 | / { |
| 30 | 26 | memory@80000000 { |
| 31 | 27 | device_type = "memory"; |
| @@ -341,7 +341,7 @@ · 340 unmodified lines | ||
| 341 | 341 | #address-cells = <1>; |
| 342 | 342 | #size-cells = <0>; |
| 343 | 343 | ax8975@c { |
| 344 | − compatible = "ak,ak8975"; | |
| 344 | + compatible = "asahi-kasei,ak8975"; | |
| 345 | 345 | reg = <0x0c>; |
| 346 | 346 | }; |
| 347 | 347 | }; |
| @@ -512,3 +512,7 @@ · 511 unmodified lines | ||
| 512 | 512 | &pruss_tm { |
| 513 | 513 | status = "okay"; |
| 514 | 514 | }; |
| 515 | + | |
| 516 | +&rtc { | |
| 517 | + system-power-controller; | |
| 518 | +}; | |
| @@ -84,7 +84,7 @@ · 83 unmodified lines | ||
| 84 | 84 | #address-cells = <1>; |
| 85 | 85 | #size-cells = <0>; |
| 86 | 86 | ax8975@c { |
| 87 | − compatible = "ak,ak8975"; | |
| 87 | + compatible = "asahi-kasei,ak8975"; | |
| 88 | 88 | reg = <0x0c>; |
| 89 | 89 | }; |
| 90 | 90 | }; |
| @@ -399,7 +399,7 @@ · 398 unmodified lines | ||
| 399 | 399 | tsc { |
| 400 | 400 | ti,wires = <4>; |
| 401 | 401 | ti,x-plate-resistance = <200>; |
| 402 | − ti,coordiante-readouts = <5>; | |
| 402 | + ti,coordinate-readouts = <5>; | |
| 403 | 403 | ti,wire-config = <0x00 0x11 0x22 0x33>; |
| 404 | 404 | }; |
| 405 | 405 | |
| @@ -775,6 +775,14 @@ · 774 unmodified lines | ||
| 775 | 775 | }; |
| 776 | 776 | }; |
| 777 | 777 | |
| 778 | +&magadc { | |
| 779 | + status = "okay"; | |
| 780 | + | |
| 781 | + adc { | |
| 782 | + ti,adc-channels = <0 1 2 3 4 5 6 7>; | |
| 783 | + }; | |
| 784 | +}; | |
| 785 | + | |
| 778 | 786 | &ecap0 { |
| 779 | 787 | status = "okay"; |
| 780 | 788 | pinctrl-names = "default"; |
| @@ -2378,11 +2378,38 @@ · 2377 unmodified lines | ||
| 2378 | 2378 | }; |
| 2379 | 2379 | |
| 2380 | 2380 | target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ |
| 2381 | − compatible = "ti,sysc"; | |
| 2382 | − status = "disabled"; | |
| 2381 | + compatible = "ti,sysc-omap4", "ti,sysc"; | |
| 2382 | + reg = <0x4c000 0x4>, | |
| 2383 | + <0x4c010 0x4>; | |
| 2384 | + reg-names = "rev", "sysc"; | |
| 2385 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
| 2386 | + <SYSC_IDLE_NO>, | |
| 2387 | + <SYSC_IDLE_SMART>; | |
| 2388 | + clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; | |
| 2389 | + clock-names = "fck"; | |
| 2383 | 2390 | #address-cells = <1>; |
| 2384 | 2391 | #size-cells = <1>; |
| 2385 | 2392 | ranges = <0x0 0x4c000 0x2000>; |
| 2393 | + | |
| 2394 | + magadc: magadc@0 { | |
| 2395 | + compatible = "ti,am4372-magadc"; | |
| 2396 | + reg = <0x0 0x2000>; | |
| 2397 | + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
| 2398 | + clocks = <&adc_mag_fck>; | |
| 2399 | + clock-names = "fck"; | |
| 2400 | + dmas = <&edma 54 0>, <&edma 55 0>; | |
| 2401 | + dma-names = "fifo0", "fifo1"; | |
| 2402 | + status = "disabled"; | |
| 2403 | + | |
| 2404 | + mag { | |
| 2405 | + compatible = "ti,am4372-mag"; | |
| 2406 | + }; | |
| 2407 | + | |
| 2408 | + adc { | |
| 2409 | + #io-channel-cells = <1>; | |
| 2410 | + compatible ="ti,am4372-adc"; | |
| 2411 | + }; | |
| 2412 | + }; | |
| 2386 | 2413 | }; |
| 2387 | 2414 | |
| 2388 | 2415 | target-module@80000 { /* 0x48380000, ap 123 42.0 */ |
| @@ -444,6 +444,13 @@ · 443 unmodified lines | ||
| 444 | 444 | reg = <0x422c>; |
| 445 | 445 | }; |
| 446 | 446 | |
| 447 | + adc_mag_fck: adc_mag_fck@424c { | |
| 448 | + #clock-cells = <0>; | |
| 449 | + compatible = "ti,mux-clock"; | |
| 450 | + clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; | |
| 451 | + reg = <0x424c>; | |
| 452 | + }; | |
| 453 | + | |
| 447 | 454 | l3_gclk: l3_gclk { |
| 448 | 455 | #clock-cells = <0>; |
| 449 | 456 | compatible = "fixed-factor-clock"; |
| @@ -168,7 +168,7 @@ · 167 unmodified lines | ||
| 168 | 168 | }; |
| 169 | 169 | |
| 170 | 170 | uart0: serial@12000 { |
| 171 | − compatible = "marvell,armada-38x-uart"; | |
| 171 | + compatible = "marvell,armada-38x-uart", "ns16550a"; | |
| 172 | 172 | reg = <0x12000 0x100>; |
| 173 | 173 | reg-shift = <2>; |
| 174 | 174 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -178,7 +178,7 @@ · 3 unmodified lines | ||
| 178 | 178 | }; |
| 179 | 179 | |
| 180 | 180 | uart1: serial@12100 { |
| 181 | − compatible = "marvell,armada-38x-uart"; | |
| 181 | + compatible = "marvell,armada-38x-uart", "ns16550a"; | |
| 182 | 182 | reg = <0x12100 0x100>; |
| 183 | 183 | reg-shift = <2>; |
| 184 | 184 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -7,6 +7,50 @@ · 6 unmodified lines | ||
| 7 | 7 | model = "Ampere Mt. Jade BMC"; |
| 8 | 8 | compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; |
| 9 | 9 | |
| 10 | + aliases { | |
| 11 | + /* | |
| 12 | + * i2c bus 50-57 assigned to NVMe slot 0-7 | |
| 13 | + */ | |
| 14 | + i2c50 = &nvmeslot_0; | |
| 15 | + i2c51 = &nvmeslot_1; | |
| 16 | + i2c52 = &nvmeslot_2; | |
| 17 | + i2c53 = &nvmeslot_3; | |
| 18 | + i2c54 = &nvmeslot_4; | |
| 19 | + i2c55 = &nvmeslot_5; | |
| 20 | + i2c56 = &nvmeslot_6; | |
| 21 | + i2c57 = &nvmeslot_7; | |
| 22 | + | |
| 23 | + /* | |
| 24 | + * i2c bus 60-67 assigned to NVMe slot 8-15 | |
| 25 | + */ | |
| 26 | + i2c60 = &nvmeslot_8; | |
| 27 | + i2c61 = &nvmeslot_9; | |
| 28 | + i2c62 = &nvmeslot_10; | |
| 29 | + i2c63 = &nvmeslot_11; | |
| 30 | + i2c64 = &nvmeslot_12; | |
| 31 | + i2c65 = &nvmeslot_13; | |
| 32 | + i2c66 = &nvmeslot_14; | |
| 33 | + i2c67 = &nvmeslot_15; | |
| 34 | + | |
| 35 | + /* | |
| 36 | + * i2c bus 70-77 assigned to NVMe slot 16-23 | |
| 37 | + */ | |
| 38 | + i2c70 = &nvmeslot_16; | |
| 39 | + i2c71 = &nvmeslot_17; | |
| 40 | + i2c72 = &nvmeslot_18; | |
| 41 | + i2c73 = &nvmeslot_19; | |
| 42 | + i2c74 = &nvmeslot_20; | |
| 43 | + i2c75 = &nvmeslot_21; | |
| 44 | + i2c76 = &nvmeslot_22; | |
| 45 | + i2c77 = &nvmeslot_23; | |
| 46 | + | |
| 47 | + /* | |
| 48 | + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 | |
| 49 | + */ | |
| 50 | + i2c80 = &nvme_m2_0; | |
| 51 | + i2c81 = &nvme_m2_1; | |
| 52 | + }; | |
| 53 | + | |
| 10 | 54 | chosen { |
| 11 | 55 | stdout-path = &uart5; |
| 12 | 56 | bootargs = "console=ttyS4,115200 earlycon"; |
| @@ -330,6 +374,15 @@ · 317 unmodified lines | ||
| 330 | 374 | m25p,fast-read; |
| 331 | 375 | label = "pnor"; |
| 332 | 376 | /* spi-max-frequency = <100000000>; */ |
| 377 | + partitions { | |
| 378 | + compatible = "fixed-partitions"; | |
| 379 | + #address-cells = <1>; | |
| 380 | + #size-cells = <1>; | |
| 381 | + uefi@400000 { | |
| 382 | + reg = <0x400000 0x1C00000>; | |
| 383 | + label = "pnor-uefi"; | |
| 384 | + }; | |
| 385 | + }; | |
| 333 | 386 | }; |
| 334 | 387 | }; |
| 335 | 388 | |
| @@ -445,6 +498,220 @@ · 109 unmodified lines | ||
| 445 | 498 | |
| 446 | 499 | &i2c5 { |
| 447 | 500 | status = "okay"; |
| 501 | + i2c-mux@70 { | |
| 502 | + compatible = "nxp,pca9548"; | |
| 503 | + #address-cells = <1>; | |
| 504 | + #size-cells = <0>; | |
| 505 | + reg = <0x70>; | |
| 506 | + i2c-mux-idle-disconnect; | |
| 507 | + | |
| 508 | + nvmeslot_0_7: i2c@3 { | |
| 509 | + #address-cells = <1>; | |
| 510 | + #size-cells = <0>; | |
| 511 | + reg = <0x3>; | |
| 512 | + }; | |
| 513 | + }; | |
| 514 | + | |
| 515 | + i2c-mux@71 { | |
| 516 | + compatible = "nxp,pca9548"; | |
| 517 | + #address-cells = <1>; | |
| 518 | + #size-cells = <0>; | |
| 519 | + reg = <0x71>; | |
| 520 | + i2c-mux-idle-disconnect; | |
| 521 | + | |
| 522 | + nvmeslot_8_15: i2c@4 { | |
| 523 | + #address-cells = <1>; | |
| 524 | + #size-cells = <0>; | |
| 525 | + reg = <0x4>; | |
| 526 | + }; | |
| 527 | + | |
| 528 | + nvmeslot_16_23: i2c@3 { | |
| 529 | + #address-cells = <1>; | |
| 530 | + #size-cells = <0>; | |
| 531 | + reg = <0x3>; | |
| 532 | + }; | |
| 533 | + | |
| 534 | + }; | |
| 535 | + | |
| 536 | + i2c-mux@72 { | |
| 537 | + compatible = "nxp,pca9545"; | |
| 538 | + #address-cells = <1>; | |
| 539 | + #size-cells = <0>; | |
| 540 | + reg = <0x72>; | |
| 541 | + i2c-mux-idle-disconnect; | |
| 542 | + | |
| 543 | + nvme_m2_0: i2c@0 { | |
| 544 | + #address-cells = <1>; | |
| 545 | + #size-cells = <0>; | |
| 546 | + reg = <0x0>; | |
| 547 | + }; | |
| 548 | + | |
| 549 | + nvme_m2_1: i2c@1 { | |
| 550 | + #address-cells = <1>; | |
| 551 | + #size-cells = <0>; | |
| 552 | + reg = <0x1>; | |
| 553 | + }; | |
| 554 | + }; | |
| 555 | +}; | |
| 556 | + | |
| 557 | +&nvmeslot_0_7 { | |
| 558 | + status = "okay"; | |
| 559 | + | |
| 560 | + i2c-mux@75 { | |
| 561 | + compatible = "nxp,pca9548"; | |
| 562 | + #address-cells = <1>; | |
| 563 | + #size-cells = <0>; | |
| 564 | + reg = <0x75>; | |
| 565 | + i2c-mux-idle-disconnect; | |
| 566 | + | |
| 567 | + nvmeslot_0: i2c@0 { | |
| 568 | + #address-cells = <1>; | |
| 569 | + #size-cells = <0>; | |
| 570 | + reg = <0x0>; | |
| 571 | + }; | |
| 572 | + nvmeslot_1: i2c@1 { | |
| 573 | + #address-cells = <1>; | |
| 574 | + #size-cells = <0>; | |
| 575 | + reg = <0x1>; | |
| 576 | + }; | |
| 577 | + nvmeslot_2: i2c@2 { | |
| 578 | + #address-cells = <1>; | |
| 579 | + #size-cells = <0>; | |
| 580 | + reg = <0x2>; | |
| 581 | + }; | |
| 582 | + nvmeslot_3: i2c@3 { | |
| 583 | + #address-cells = <1>; | |
| 584 | + #size-cells = <0>; | |
| 585 | + reg = <0x3>; | |
| 586 | + }; | |
| 587 | + nvmeslot_4: i2c@4 { | |
| 588 | + #address-cells = <1>; | |
| 589 | + #size-cells = <0>; | |
| 590 | + reg = <0x4>; | |
| 591 | + }; | |
| 592 | + nvmeslot_5: i2c@5 { | |
| 593 | + #address-cells = <1>; | |
| 594 | + #size-cells = <0>; | |
| 595 | + reg = <0x5>; | |
| 596 | + }; | |
| 597 | + nvmeslot_6: i2c@6 { | |
| 598 | + #address-cells = <1>; | |
| 599 | + #size-cells = <0>; | |
| 600 | + reg = <0x6>; | |
| 601 | + }; | |
| 602 | + nvmeslot_7: i2c@7 { | |
| 603 | + #address-cells = <1>; | |
| 604 | + #size-cells = <0>; | |
| 605 | + reg = <0x7>; | |
| 606 | + }; | |
| 607 | + | |
| 608 | + }; | |
| 609 | +}; | |
| 610 | + | |
| 611 | +&nvmeslot_8_15 { | |
| 612 | + status = "okay"; | |
| 613 | + | |
| 614 | + i2c-mux@75 { | |
| 615 | + compatible = "nxp,pca9548"; | |
| 616 | + #address-cells = <1>; | |
| 617 | + #size-cells = <0>; | |
| 618 | + reg = <0x75>; | |
| 619 | + i2c-mux-idle-disconnect; | |
| 620 | + | |
| 621 | + nvmeslot_8: i2c@0 { | |
| 622 | + #address-cells = <1>; | |
| 623 | + #size-cells = <0>; | |
| 624 | + reg = <0x0>; | |
| 625 | + }; | |
| 626 | + nvmeslot_9: i2c@1 { | |
| 627 | + #address-cells = <1>; | |
| 628 | + #size-cells = <0>; | |
| 629 | + reg = <0x1>; | |
| 630 | + }; | |
| 631 | + nvmeslot_10: i2c@2 { | |
| 632 | + #address-cells = <1>; | |
| 633 | + #size-cells = <0>; | |
| 634 | + reg = <0x2>; | |
| 635 | + }; | |
| 636 | + nvmeslot_11: i2c@3 { | |
| 637 | + #address-cells = <1>; | |
| 638 | + #size-cells = <0>; | |
| 639 | + reg = <0x3>; | |
| 640 | + }; | |
| 641 | + nvmeslot_12: i2c@4 { | |
| 642 | + #address-cells = <1>; | |
| 643 | + #size-cells = <0>; | |
| 644 | + reg = <0x4>; | |
| 645 | + }; | |
| 646 | + nvmeslot_13: i2c@5 { | |
| 647 | + #address-cells = <1>; | |
| 648 | + #size-cells = <0>; | |
| 649 | + reg = <0x5>; | |
| 650 | + }; | |
| 651 | + nvmeslot_14: i2c@6 { | |
| 652 | + #address-cells = <1>; | |
| 653 | + #size-cells = <0>; | |
| 654 | + reg = <0x6>; | |
| 655 | + }; | |
| 656 | + nvmeslot_15: i2c@7 { | |
| 657 | + #address-cells = <1>; | |
| 658 | + #size-cells = <0>; | |
| 659 | + reg = <0x7>; | |
| 660 | + }; | |
| 661 | + }; | |
| 662 | +}; | |
| 663 | + | |
| 664 | +&nvmeslot_16_23 { | |
| 665 | + status = "okay"; | |
| 666 | + | |
| 667 | + i2c-mux@75 { | |
| 668 | + compatible = "nxp,pca9548"; | |
| 669 | + #address-cells = <1>; | |
| 670 | + #size-cells = <0>; | |
| 671 | + reg = <0x75>; | |
| 672 | + i2c-mux-idle-disconnect; | |
| 673 | + | |
| 674 | + nvmeslot_16: i2c@0 { | |
| 675 | + #address-cells = <1>; | |
| 676 | + #size-cells = <0>; | |
| 677 | + reg = <0x0>; | |
| 678 | + }; | |
| 679 | + nvmeslot_17: i2c@1 { | |
| 680 | + #address-cells = <1>; | |
| 681 | + #size-cells = <0>; | |
| 682 | + reg = <0x1>; | |
| 683 | + }; | |
| 684 | + nvmeslot_18: i2c@2 { | |
| 685 | + #address-cells = <1>; | |
| 686 | + #size-cells = <0>; | |
| 687 | + reg = <0x2>; | |
| 688 | + }; | |
| 689 | + nvmeslot_19: i2c@3 { | |
| 690 | + #address-cells = <1>; | |
| 691 | + #size-cells = <0>; | |
| 692 | + reg = <0x3>; | |
| 693 | + }; | |
| 694 | + nvmeslot_20: i2c@4 { | |
| 695 | + #address-cells = <1>; | |
| 696 | + #size-cells = <0>; | |
| 697 | + reg = <0x4>; | |
| 698 | + }; | |
| 699 | + nvmeslot_21: i2c@5 { | |
| 700 | + #address-cells = <1>; | |
| 701 | + #size-cells = <0>; | |
| 702 | + reg = <0x5>; | |
| 703 | + }; | |
| 704 | + nvmeslot_22: i2c@6 { | |
| 705 | + #address-cells = <1>; | |
| 706 | + #size-cells = <0>; | |
| 707 | + reg = <0x6>; | |
| 708 | + }; | |
| 709 | + nvmeslot_23: i2c@7 { | |
| 710 | + #address-cells = <1>; | |
| 711 | + #size-cells = <0>; | |
| 712 | + reg = <0x7>; | |
| 713 | + }; | |
| 714 | + }; | |
| 448 | 715 | }; |
| 449 | 716 | |
| 450 | 717 | &i2c6 { |
| @@ -260,6 +260,13 @@ · 259 unmodified lines | ||
| 260 | 260 | spi-max-frequency = <50000000>; |
| 261 | 261 | #include "openbmc-flash-layout-64.dtsi" |
| 262 | 262 | }; |
| 263 | + flash@1 { | |
| 264 | + status = "okay"; | |
| 265 | + label = "alt-bmc"; | |
| 266 | + m25p,fast-read; | |
| 267 | + spi-max-frequency = <50000000>; | |
| 268 | +#include "openbmc-flash-layout-64-alt.dtsi" | |
| 269 | + }; | |
| 263 | 270 | }; |
| 264 | 271 | |
| 265 | 272 | &spi1 { |
| @@ -278,6 +285,11 @@ · 12 unmodified lines | ||
| 278 | 285 | status = "okay"; |
| 279 | 286 | }; |
| 280 | 287 | |
| 288 | +&wdt2 { | |
| 289 | + status = "okay"; | |
| 290 | + aspeed,alt-boot; | |
| 291 | +}; | |
| 292 | + | |
| 281 | 293 | &gpio { |
| 282 | 294 | status = "okay"; |
| 283 | 295 | gpio-line-names = |
| @@ -0,0 +1,756 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +// Copyright (c) 2021 Facebook Inc. | |
| 3 | +/dts-v1/; | |
| 4 | + | |
| 5 | +#include "aspeed-g6.dtsi" | |
| 6 | +#include <dt-bindings/gpio/aspeed-gpio.h> | |
| 7 | +#include <dt-bindings/usb/pd.h> | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + model = "Facebook Bletchley BMC"; | |
| 11 | + compatible = "facebook,bletchley-bmc", "aspeed,ast2600"; | |
| 12 | + | |
| 13 | + aliases { | |
| 14 | + serial4 = &uart5; | |
| 15 | + }; | |
| 16 | + | |
| 17 | + chosen { | |
| 18 | + bootargs = "console=ttyS4,57600n8"; | |
| 19 | + }; | |
| 20 | + | |
| 21 | + memory@80000000 { | |
| 22 | + device_type = "memory"; | |
| 23 | + reg = <0x80000000 0x80000000>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + iio-hwmon { | |
| 27 | + compatible = "iio-hwmon"; | |
| 28 | + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, | |
| 29 | + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, | |
| 30 | + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, | |
| 31 | + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + spi_gpio: spi-gpio { | |
| 35 | + compatible = "spi-gpio"; | |
| 36 | + #address-cells = <1>; | |
| 37 | + #size-cells = <0>; | |
| 38 | + | |
| 39 | + gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; | |
| 40 | + gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; | |
| 41 | + gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; | |
| 42 | + num-chipselects = <1>; | |
| 43 | + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; | |
| 44 | + | |
| 45 | + tpmdev@0 { | |
| 46 | + compatible = "tcg,tpm_tis-spi"; | |
| 47 | + spi-max-frequency = <33000000>; | |
| 48 | + reg = <0>; | |
| 49 | + }; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + switchphy: ethernet-phy@0 { | |
| 53 | + // Fixed link | |
| 54 | + }; | |
| 55 | + | |
| 56 | + leds { | |
| 57 | + compatible = "gpio-leds"; | |
| 58 | + | |
| 59 | + sys_log_id { | |
| 60 | + retain-state-shutdown; | |
| 61 | + default-state = "keep"; | |
| 62 | + gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; | |
| 63 | + }; | |
| 64 | + fan0_blue { | |
| 65 | + retain-state-shutdown; | |
| 66 | + default-state = "on"; | |
| 67 | + gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>; | |
| 68 | + }; | |
| 69 | + fan1_blue { | |
| 70 | + retain-state-shutdown; | |
| 71 | + default-state = "on"; | |
| 72 | + gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>; | |
| 73 | + }; | |
| 74 | + fan2_blue { | |
| 75 | + retain-state-shutdown; | |
| 76 | + default-state = "on"; | |
| 77 | + gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>; | |
| 78 | + }; | |
| 79 | + fan3_blue { | |
| 80 | + retain-state-shutdown; | |
| 81 | + default-state = "on"; | |
| 82 | + gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>; | |
| 83 | + }; | |
| 84 | + fan0_amber { | |
| 85 | + retain-state-shutdown; | |
| 86 | + default-state = "off"; | |
| 87 | + gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>; | |
| 88 | + }; | |
| 89 | + fan1_amber { | |
| 90 | + retain-state-shutdown; | |
| 91 | + default-state = "off"; | |
| 92 | + gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>; | |
| 93 | + }; | |
| 94 | + fan2_amber { | |
| 95 | + retain-state-shutdown; | |
| 96 | + default-state = "off"; | |
| 97 | + gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>; | |
| 98 | + }; | |
| 99 | + fan3_amber { | |
| 100 | + retain-state-shutdown; | |
| 101 | + default-state = "off"; | |
| 102 | + gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>; | |
| 103 | + }; | |
| 104 | + sled0_amber { | |
| 105 | + retain-state-shutdown; | |
| 106 | + default-state = "off"; | |
| 107 | + gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>; | |
| 108 | + }; | |
| 109 | + sled0_blue { | |
| 110 | + retain-state-shutdown; | |
| 111 | + default-state = "off"; | |
| 112 | + gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>; | |
| 113 | + }; | |
| 114 | + sled1_amber { | |
| 115 | + retain-state-shutdown; | |
| 116 | + default-state = "off"; | |
| 117 | + gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; | |
| 118 | + }; | |
| 119 | + sled1_blue { | |
| 120 | + retain-state-shutdown; | |
| 121 | + default-state = "off"; | |
| 122 | + gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; | |
| 123 | + }; | |
| 124 | + sled2_amber { | |
| 125 | + retain-state-shutdown; | |
| 126 | + default-state = "off"; | |
| 127 | + gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; | |
| 128 | + }; | |
| 129 | + sled2_blue { | |
| 130 | + retain-state-shutdown; | |
| 131 | + default-state = "off"; | |
| 132 | + gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; | |
| 133 | + }; | |
| 134 | + sled3_amber { | |
| 135 | + retain-state-shutdown; | |
| 136 | + default-state = "off"; | |
| 137 | + gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; | |
| 138 | + }; | |
| 139 | + sled3_blue { | |
| 140 | + retain-state-shutdown; | |
| 141 | + default-state = "off"; | |
| 142 | + gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; | |
| 143 | + }; | |
| 144 | + sled4_amber { | |
| 145 | + retain-state-shutdown; | |
| 146 | + default-state = "off"; | |
| 147 | + gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; | |
| 148 | + }; | |
| 149 | + sled4_blue { | |
| 150 | + retain-state-shutdown; | |
| 151 | + default-state = "off"; | |
| 152 | + gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; | |
| 153 | + }; | |
| 154 | + sled5_amber { | |
| 155 | + retain-state-shutdown; | |
| 156 | + default-state = "off"; | |
| 157 | + gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; | |
| 158 | + }; | |
| 159 | + sled5_blue { | |
| 160 | + retain-state-shutdown; | |
| 161 | + default-state = "off"; | |
| 162 | + gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; | |
| 163 | + }; | |
| 164 | + }; | |
| 165 | +}; | |
| 166 | + | |
| 167 | +&mac2 { | |
| 168 | + status = "okay"; | |
| 169 | + phy-mode = "rgmii"; | |
| 170 | + phy-handle = <&switchphy>; | |
| 171 | + pinctrl-names = "default"; | |
| 172 | + pinctrl-0 = <&pinctrl_rgmii3_default>; | |
| 173 | + | |
| 174 | + fixed-link { | |
| 175 | + speed = <1000>; | |
| 176 | + full-duplex; | |
| 177 | + }; | |
| 178 | +}; | |
| 179 | + | |
| 180 | +&rtc { | |
| 181 | + status = "okay"; | |
| 182 | +}; | |
| 183 | + | |
| 184 | +&fmc { | |
| 185 | + status = "okay"; | |
| 186 | + flash@0 { | |
| 187 | + status = "okay"; | |
| 188 | + m25p,fast-read; | |
| 189 | + label = "bmc"; | |
| 190 | + spi-max-frequency = <50000000>; | |
| 191 | +#include "openbmc-flash-layout-128.dtsi" | |
| 192 | + }; | |
| 193 | +}; | |
| 194 | + | |
| 195 | +&spi2 { | |
| 196 | + status = "okay"; | |
| 197 | + pinctrl-names = "default"; | |
| 198 | + pinctrl-0 = <&pinctrl_spi2_default>; | |
| 199 | + | |
| 200 | + flash@0 { | |
| 201 | + status = "okay"; | |
| 202 | + m25p,fast-read; | |
| 203 | + label = "pnor"; | |
| 204 | + spi-max-frequency = <100000000>; | |
| 205 | + }; | |
| 206 | +}; | |
| 207 | + | |
| 208 | +&i2c0 { | |
| 209 | + status = "okay"; | |
| 210 | + /* TODO: Add ADC INA230 */ | |
| 211 | + | |
| 212 | + mp5023@40 { | |
| 213 | + compatible = "mps,mp5023"; | |
| 214 | + reg = <0x40>; | |
| 215 | + }; | |
| 216 | + | |
| 217 | + tmp421@4f { | |
| 218 | + compatible = "ti,tmp421"; | |
| 219 | + reg = <0x4f>; | |
| 220 | + }; | |
| 221 | + | |
| 222 | + sled0_ioexp: pca9539@76 { | |
| 223 | + compatible = "nxp,pca9539"; | |
| 224 | + reg = <0x76>; | |
| 225 | + #address-cells = <1>; | |
| 226 | + #size-cells = <0>; | |
| 227 | + gpio-controller; | |
| 228 | + #gpio-cells = <2>; | |
| 229 | + | |
| 230 | + gpio-line-names = | |
| 231 | + "SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT", | |
| 232 | + "SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT", | |
| 233 | + "SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY", | |
| 234 | + "SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0"; | |
| 235 | + }; | |
| 236 | + | |
| 237 | + sled0_leds: pca9552@67 { | |
| 238 | + compatible = "nxp,pca9552"; | |
| 239 | + reg = <0x67>; | |
| 240 | + #address-cells = <1>; | |
| 241 | + #size-cells = <0>; | |
| 242 | + gpio-controller; | |
| 243 | + #gpio-cells = <2>; | |
| 244 | + | |
| 245 | + gpio-line-names = | |
| 246 | + "led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","", | |
| 247 | + "","","","", | |
| 248 | + "","","","", | |
| 249 | + "","","",""; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + sled0_fusb302: typec-portc@22 { | |
| 253 | + compatible = "fcs,fusb302"; | |
| 254 | + reg = <0x22>; | |
| 255 | + | |
| 256 | + connector { | |
| 257 | + compatible = "usb-c-connector"; | |
| 258 | + label = "USB-C"; | |
| 259 | + power-role = "dual"; | |
| 260 | + try-power-role = "sink"; | |
| 261 | + data-role = "dual"; | |
| 262 | + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; | |
| 263 | + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) | |
| 264 | + PDO_VAR(3000, 12000, 3000) | |
| 265 | + PDO_PPS_APDO(3000, 11000, 3000)>; | |
| 266 | + op-sink-microwatt = <10000000>; | |
| 267 | + }; | |
| 268 | + }; | |
| 269 | +}; | |
| 270 | + | |
| 271 | +&i2c1 { | |
| 272 | + status = "okay"; | |
| 273 | + /* TODO: Add ADC INA230 */ | |
| 274 | + | |
| 275 | + mp5023@40 { | |
| 276 | + compatible = "mps,mp5023"; | |
| 277 | + reg = <0x40>; | |
| 278 | + }; | |
| 279 | + | |
| 280 | + tmp421@4f { | |
| 281 | + compatible = "ti,tmp421"; | |
| 282 | + reg = <0x4f>; | |
| 283 | + }; | |
| 284 | + | |
| 285 | + sled1_ioexp: pca9539@76 { | |
| 286 | + compatible = "nxp,pca9539"; | |
| 287 | + reg = <0x76>; | |
| 288 | + #address-cells = <1>; | |
| 289 | + #size-cells = <0>; | |
| 290 | + gpio-controller; | |
| 291 | + #gpio-cells = <2>; | |
| 292 | + | |
| 293 | + gpio-line-names = | |
| 294 | + "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", | |
| 295 | + "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", | |
| 296 | + "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", | |
| 297 | + "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; | |
| 298 | + }; | |
| 299 | + | |
| 300 | + sled1_leds: pca9552@67 { | |
| 301 | + compatible = "nxp,pca9552"; | |
| 302 | + reg = <0x67>; | |
| 303 | + #address-cells = <1>; | |
| 304 | + #size-cells = <0>; | |
| 305 | + gpio-controller; | |
| 306 | + #gpio-cells = <2>; | |
| 307 | + | |
| 308 | + gpio-line-names = | |
| 309 | + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","", | |
| 310 | + "","","","", | |
| 311 | + "","","","", | |
| 312 | + "","","",""; | |
| 313 | + }; | |
| 314 | + | |
| 315 | + sled1_fusb302: typec-portc@22 { | |
| 316 | + compatible = "fcs,fusb302"; | |
| 317 | + reg = <0x22>; | |
| 318 | + | |
| 319 | + connector { | |
| 320 | + compatible = "usb-c-connector"; | |
| 321 | + label = "USB-C"; | |
| 322 | + power-role = "dual"; | |
| 323 | + try-power-role = "sink"; | |
| 324 | + data-role = "dual"; | |
| 325 | + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; | |
| 326 | + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) | |
| 327 | + PDO_VAR(3000, 12000, 3000) | |
| 328 | + PDO_PPS_APDO(3000, 11000, 3000)>; | |
| 329 | + op-sink-microwatt = <10000000>; | |
| 330 | + }; | |
| 331 | + }; | |
| 332 | +}; | |
| 333 | + | |
| 334 | +&i2c1 { | |
| 335 | + status = "okay"; | |
| 336 | +}; | |
| 337 | + | |
| 338 | +&i2c2 { | |
| 339 | + status = "okay"; | |
| 340 | + /* TODO: Add ADC INA230 */ | |
| 341 | + | |
| 342 | + mp5023@40 { | |
| 343 | + compatible = "mps,mp5023"; | |
| 344 | + reg = <0x40>; | |
| 345 | + }; | |
| 346 | + | |
| 347 | + tmp421@4f { | |
| 348 | + compatible = "ti,tmp421"; | |
| 349 | + reg = <0x4f>; | |
| 350 | + }; | |
| 351 | + | |
| 352 | + sled2_ioexp: pca9539@76 { | |
| 353 | + compatible = "nxp,pca9539"; | |
| 354 | + reg = <0x76>; | |
| 355 | + #address-cells = <1>; | |
| 356 | + #size-cells = <0>; | |
| 357 | + gpio-controller; | |
| 358 | + #gpio-cells = <2>; | |
| 359 | + | |
| 360 | + gpio-line-names = | |
| 361 | + "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", | |
| 362 | + "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", | |
| 363 | + "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", | |
| 364 | + "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; | |
| 365 | + }; | |
| 366 | + | |
| 367 | + sled2_leds: pca9552@67 { | |
| 368 | + compatible = "nxp,pca9552"; | |
| 369 | + reg = <0x67>; | |
| 370 | + #address-cells = <1>; | |
| 371 | + #size-cells = <0>; | |
| 372 | + gpio-controller; | |
| 373 | + #gpio-cells = <2>; | |
| 374 | + | |
| 375 | + gpio-line-names = | |
| 376 | + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","", | |
| 377 | + "","","","", | |
| 378 | + "","","","", | |
| 379 | + "","","",""; | |
| 380 | + }; | |
| 381 | + | |
| 382 | + sled2_fusb302: typec-portc@22 { | |
| 383 | + compatible = "fcs,fusb302"; | |
| 384 | + reg = <0x22>; | |
| 385 | + | |
| 386 | + connector { | |
| 387 | + compatible = "usb-c-connector"; | |
| 388 | + label = "USB-C"; | |
| 389 | + power-role = "dual"; | |
| 390 | + try-power-role = "sink"; | |
| 391 | + data-role = "dual"; | |
| 392 | + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; | |
| 393 | + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) | |
| 394 | + PDO_VAR(3000, 12000, 3000) | |
| 395 | + PDO_PPS_APDO(3000, 11000, 3000)>; | |
| 396 | + op-sink-microwatt = <10000000>; | |
| 397 | + }; | |
| 398 | + }; | |
| 399 | +}; | |
| 400 | + | |
| 401 | +&i2c3 { | |
| 402 | + status = "okay"; | |
| 403 | + /* TODO: Add ADC INA230 */ | |
| 404 | + | |
| 405 | + mp5023@40 { | |
| 406 | + compatible = "mps,mp5023"; | |
| 407 | + reg = <0x40>; | |
| 408 | + }; | |
| 409 | + | |
| 410 | + tmp421@4f { | |
| 411 | + compatible = "ti,tmp421"; | |
| 412 | + reg = <0x4f>; | |
| 413 | + }; | |
| 414 | + | |
| 415 | + sled3_ioexp: pca9539@76 { | |
| 416 | + compatible = "nxp,pca9539"; | |
| 417 | + reg = <0x76>; | |
| 418 | + #address-cells = <1>; | |
| 419 | + #size-cells = <0>; | |
| 420 | + gpio-controller; | |
| 421 | + #gpio-cells = <2>; | |
| 422 | + | |
| 423 | + gpio-line-names = | |
| 424 | + "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", | |
| 425 | + "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", | |
| 426 | + "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", | |
| 427 | + "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; | |
| 428 | + }; | |
| 429 | + | |
| 430 | + sled3_leds: pca9552@67 { | |
| 431 | + compatible = "nxp,pca9552"; | |
| 432 | + reg = <0x67>; | |
| 433 | + #address-cells = <1>; | |
| 434 | + #size-cells = <0>; | |
| 435 | + gpio-controller; | |
| 436 | + #gpio-cells = <2>; | |
| 437 | + | |
| 438 | + gpio-line-names = | |
| 439 | + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","", | |
| 440 | + "","","","", | |
| 441 | + "","","","", | |
| 442 | + "","","",""; | |
| 443 | + }; | |
| 444 | + | |
| 445 | + sled3_fusb302: typec-portc@22 { | |
| 446 | + compatible = "fcs,fusb302"; | |
| 447 | + reg = <0x22>; | |
| 448 | + | |
| 449 | + connector { | |
| 450 | + compatible = "usb-c-connector"; | |
| 451 | + label = "USB-C"; | |
| 452 | + power-role = "dual"; | |
| 453 | + try-power-role = "sink"; | |
| 454 | + data-role = "dual"; | |
| 455 | + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; | |
| 456 | + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) | |
| 457 | + PDO_VAR(3000, 12000, 3000) | |
| 458 | + PDO_PPS_APDO(3000, 11000, 3000)>; | |
| 459 | + op-sink-microwatt = <10000000>; | |
| 460 | + }; | |
| 461 | + }; | |
| 462 | +}; | |
| 463 | + | |
| 464 | +&i2c4 { | |
| 465 | + status = "okay"; | |
| 466 | + /* TODO: Add ADC INA230 */ | |
| 467 | + | |
| 468 | + mp5023@40 { | |
| 469 | + compatible = "mps,mp5023"; | |
| 470 | + reg = <0x40>; | |
| 471 | + }; | |
| 472 | + | |
| 473 | + tmp421@4f { | |
| 474 | + compatible = "ti,tmp421"; | |
| 475 | + reg = <0x4f>; | |
| 476 | + }; | |
| 477 | + | |
| 478 | + sled4_ioexp: pca9539@76 { | |
| 479 | + compatible = "nxp,pca9539"; | |
| 480 | + reg = <0x76>; | |
| 481 | + #address-cells = <1>; | |
| 482 | + #size-cells = <0>; | |
| 483 | + gpio-controller; | |
| 484 | + #gpio-cells = <2>; | |
| 485 | + | |
| 486 | + gpio-line-names = | |
| 487 | + "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", | |
| 488 | + "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", | |
| 489 | + "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", | |
| 490 | + "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; | |
| 491 | + }; | |
| 492 | + | |
| 493 | + sled4_leds: pca9552@67 { | |
| 494 | + compatible = "nxp,pca9552"; | |
| 495 | + reg = <0x67>; | |
| 496 | + #address-cells = <1>; | |
| 497 | + #size-cells = <0>; | |
| 498 | + gpio-controller; | |
| 499 | + #gpio-cells = <2>; | |
| 500 | + | |
| 501 | + gpio-line-names = | |
| 502 | + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","", | |
| 503 | + "","","","", | |
| 504 | + "","","","", | |
| 505 | + "","","",""; | |
| 506 | + }; | |
| 507 | + | |
| 508 | + sled4_fusb302: typec-portc@22 { | |
| 509 | + compatible = "fcs,fusb302"; | |
| 510 | + reg = <0x22>; | |
| 511 | + | |
| 512 | + connector { | |
| 513 | + compatible = "usb-c-connector"; | |
| 514 | + label = "USB-C"; | |
| 515 | + power-role = "dual"; | |
| 516 | + try-power-role = "sink"; | |
| 517 | + data-role = "dual"; | |
| 518 | + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; | |
| 519 | + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) | |
| 520 | + PDO_VAR(3000, 12000, 3000) | |
| 521 | + PDO_PPS_APDO(3000, 11000, 3000)>; | |
| 522 | + op-sink-microwatt = <10000000>; | |
| 523 | + }; | |
| 524 | + }; | |
| 525 | +}; | |
| 526 | + | |
| 527 | +&i2c5 { | |
| 528 | + status = "okay"; | |
| 529 | + /* TODO: Add ADC INA230 */ | |
| 530 | + | |
| 531 | + mp5023@40 { | |
| 532 | + compatible = "mps,mp5023"; | |
| 533 | + reg = <0x40>; | |
| 534 | + }; | |
| 535 | + | |
| 536 | + tmp421@4f { | |
| 537 | + compatible = "ti,tmp421"; | |
| 538 | + reg = <0x4f>; | |
| 539 | + }; | |
| 540 | + | |
| 541 | + sled5_ioexp: pca9539@76 { | |
| 542 | + compatible = "nxp,pca9539"; | |
| 543 | + reg = <0x76>; | |
| 544 | + #address-cells = <1>; | |
| 545 | + #size-cells = <0>; | |
| 546 | + gpio-controller; | |
| 547 | + #gpio-cells = <2>; | |
| 548 | + | |
| 549 | + gpio-line-names = | |
| 550 | + "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", | |
| 551 | + "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", | |
| 552 | + "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", | |
| 553 | + "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; | |
| 554 | + }; | |
| 555 | + | |
| 556 | + sled5_leds: pca9552@67 { | |
| 557 | + compatible = "nxp,pca9552"; | |
| 558 | + reg = <0x67>; | |
| 559 | + #address-cells = <1>; | |
| 560 | + #size-cells = <0>; | |
| 561 | + gpio-controller; | |
| 562 | + #gpio-cells = <2>; | |
| 563 | + | |
| 564 | + gpio-line-names = | |
| 565 | + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","", | |
| 566 | + "","","","", | |
| 567 | + "","","","", | |
| 568 | + "","","",""; | |
| 569 | + }; | |
| 570 | + | |
| 571 | + sled5_fusb302: typec-portc@22 { | |
| 572 | + compatible = "fcs,fusb302"; | |
| 573 | + reg = <0x22>; | |
| 574 | + | |
| 575 | + connector { | |
| 576 | + compatible = "usb-c-connector"; | |
| 577 | + label = "USB-C"; | |
| 578 | + power-role = "dual"; | |
| 579 | + try-power-role = "sink"; | |
| 580 | + data-role = "dual"; | |
| 581 | + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; | |
| 582 | + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) | |
| 583 | + PDO_VAR(3000, 12000, 3000) | |
| 584 | + PDO_PPS_APDO(3000, 11000, 3000)>; | |
| 585 | + op-sink-microwatt = <10000000>; | |
| 586 | + }; | |
| 587 | + }; | |
| 588 | +}; | |
| 589 | + | |
| 590 | +&i2c6 { | |
| 591 | + status = "okay"; | |
| 592 | + | |
| 593 | + eeprom@56 { | |
| 594 | + compatible = "atmel,24c64"; | |
| 595 | + reg = <0x56>; | |
| 596 | + }; | |
| 597 | + | |
| 598 | + rtc@51 { | |
| 599 | + compatible = "nxp,pcf85263"; | |
| 600 | + reg = <0x51>; | |
| 601 | + }; | |
| 602 | +}; | |
| 603 | + | |
| 604 | +&i2c7 { | |
| 605 | + status = "okay"; | |
| 606 | + | |
| 607 | + eeprom@54 { | |
| 608 | + compatible = "atmel,24c64"; | |
| 609 | + reg = <0x54>; | |
| 610 | + }; | |
| 611 | +}; | |
| 612 | + | |
| 613 | +&i2c9 { | |
| 614 | + status = "okay"; | |
| 615 | + | |
| 616 | + tmp421@4f { | |
| 617 | + compatible = "ti,tmp421"; | |
| 618 | + reg = <0x4f>; | |
| 619 | + }; | |
| 620 | +}; | |
| 621 | + | |
| 622 | +&i2c10 { | |
| 623 | + status = "okay"; | |
| 624 | + | |
| 625 | + tmp421@4f { | |
| 626 | + compatible = "ti,tmp421"; | |
| 627 | + reg = <0x4f>; | |
| 628 | + }; | |
| 629 | + | |
| 630 | + hdc1080@40 { | |
| 631 | + compatible = "ti,hdc1080"; | |
| 632 | + reg = <0x40>; | |
| 633 | + }; | |
| 634 | + | |
| 635 | + front_leds: pca9552@67 { | |
| 636 | + compatible = "nxp,pca9552"; | |
| 637 | + reg = <0x67>; | |
| 638 | + #address-cells = <1>; | |
| 639 | + #size-cells = <0>; | |
| 640 | + gpio-controller; | |
| 641 | + #gpio-cells = <2>; | |
| 642 | + | |
| 643 | + gpio-line-names = | |
| 644 | + "led-fault-identify","power-p5v-stby-good", | |
| 645 | + "power-p1v0-dvdd-good","power-p1v0-avdd-good", | |
| 646 | + "","","","", | |
| 647 | + "","","","", | |
| 648 | + "","","",""; | |
| 649 | + }; | |
| 650 | +}; | |
| 651 | + | |
| 652 | +&i2c12 { | |
| 653 | + status = "okay"; | |
| 654 | + | |
| 655 | + adm1278@11 { | |
| 656 | + compatible = "adi,adm1278"; | |
| 657 | + reg = <0x11>; | |
| 658 | + }; | |
| 659 | + | |
| 660 | + tmp421@4c { | |
| 661 | + compatible = "ti,tmp421"; | |
| 662 | + reg = <0x4c>; | |
| 663 | + }; | |
| 664 | + | |
| 665 | + tmp421@4d { | |
| 666 | + compatible = "ti,tmp421"; | |
| 667 | + reg = <0x4d>; | |
| 668 | + }; | |
| 669 | + | |
| 670 | + fan_ioexp: pca9552@67 { | |
| 671 | + compatible = "nxp,pca9552"; | |
| 672 | + reg = <0x67>; | |
| 673 | + #address-cells = <1>; | |
| 674 | + #size-cells = <0>; | |
| 675 | + gpio-controller; | |
| 676 | + #gpio-cells = <2>; | |
| 677 | + | |
| 678 | + gpio-line-names = | |
| 679 | + "presence-fan0","presence-fan1", | |
| 680 | + "presence-fan2","presence-fan3", | |
| 681 | + "power-fan0-good","power-fan1-good", | |
| 682 | + "power-fan2-good","power-fan3-good", | |
| 683 | + "","","","", | |
| 684 | + "","","",""; | |
| 685 | + }; | |
| 686 | +}; | |
| 687 | + | |
| 688 | +&i2c13 { | |
| 689 | + multi-master; | |
| 690 | + aspeed,hw-timeout-ms = <1000>; | |
| 691 | + status = "okay"; | |
| 692 | +}; | |
| 693 | + | |
| 694 | +&gpio0 { | |
| 695 | + gpio-line-names = | |
| 696 | + /*A0-A7*/ "","","","","","","","", | |
| 697 | + /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1", | |
| 698 | + "SPI2_MUX2","SPI2_MUX3","","", | |
| 699 | + /*C0-C7*/ "","","","","","","","", | |
| 700 | + /*D0-D7*/ "","","","","","","","", | |
| 701 | + /*E0-E7*/ "","","","","","","","", | |
| 702 | + /*F0-F7*/ "","","","","","","","", | |
| 703 | + /*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","", | |
| 704 | + /*H0-H7*/ "presence-riser1","presence-riser2", | |
| 705 | + "presence-sled0","presence-sled1", | |
| 706 | + "presence-sled2","presence-sled3", | |
| 707 | + "presence-sled4","presence-sled5", | |
| 708 | + /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", | |
| 709 | + "","","","", | |
| 710 | + /*J0-J7*/ "","","","","","","","", | |
| 711 | + /*K0-K7*/ "","","","","","","","", | |
| 712 | + /*L0-L7*/ "","","","","","","","", | |
| 713 | + /*M0-M7*/ "ALERT_SLED0","ALERT_SLED1", | |
| 714 | + "ALERT_SLED2","ALERT_SLED3", | |
| 715 | + "ALERT_SLED4","ALERT_SLED5", | |
| 716 | + "P12V_AUX_ALERT1","", | |
| 717 | + /*N0-N7*/ "","","","","","","","", | |
| 718 | + /*O0-O7*/ "","","","", | |
| 719 | + "","BOARD_ID0","BOARD_ID1","BOARD_ID2", | |
| 720 | + /*P0-P7*/ "","","","","","","","", | |
| 721 | + /*Q0-Q7*/ "","","","","","","","", | |
| 722 | + /*R0-R7*/ "","","","","","","","", | |
| 723 | + /*S0-S7*/ "","","","BAT_DETECT", | |
| 724 | + "BMC_BT_WP0","BMC_BT_WP1","","", | |
| 725 | + /*T0-T7*/ "","","","","","","","", | |
| 726 | + /*U0-U7*/ "","","","","","","","", | |
| 727 | + /*V0-V7*/ "","RST_BMC_MVL","","", | |
| 728 | + "USB2_SEL0_A","USB2_SEL1_A", | |
| 729 | + "USB2_SEL0_B","USB2_SEL1_B", | |
| 730 | + /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", | |
| 731 | + /*X0-X7*/ "","","","","","","","", | |
| 732 | + /*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","", | |
| 733 | + /*Z0-Z7*/ "","","","","","","",""; | |
| 734 | +}; | |
| 735 | + | |
| 736 | +&adc0 { | |
| 737 | + vref = <1800>; | |
| 738 | + status = "okay"; | |
| 739 | + | |
| 740 | + pinctrl-names = "default"; | |
| 741 | + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default | |
| 742 | + &pinctrl_adc2_default &pinctrl_adc3_default | |
| 743 | + &pinctrl_adc4_default &pinctrl_adc5_default | |
| 744 | + &pinctrl_adc6_default &pinctrl_adc7_default>; | |
| 745 | +}; | |
| 746 | + | |
| 747 | +&adc1 { | |
| 748 | + vref = <2500>; | |
| 749 | + status = "okay"; | |
| 750 | + | |
| 751 | + pinctrl-names = "default"; | |
| 752 | + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default | |
| 753 | + &pinctrl_adc10_default &pinctrl_adc11_default | |
| 754 | + &pinctrl_adc12_default &pinctrl_adc13_default | |
| 755 | + &pinctrl_adc14_default &pinctrl_adc15_default>; | |
| 756 | +}; | |
| @@ -280,7 +280,7 @@ · 279 unmodified lines | ||
| 280 | 280 | /*L0-L7*/ "","","","","","","","", |
| 281 | 281 | /*M0-M7*/ "","","","","","","","", |
| 282 | 282 | /*N0-N7*/ "","","","","","","","", |
| 283 | − /*O0-O7*/ "","","","","","","","", | |
| 283 | + /*O0-O7*/ "","","","usb-power","","","","", | |
| 284 | 284 | /*P0-P7*/ "","","","","led-pcieslot-power","","","", |
| 285 | 285 | /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", |
| 286 | 286 | /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", |
| @@ -292,6 +292,12 @@ · 5 unmodified lines | ||
| 292 | 292 | /*X0-X7*/ "","","","","","","","", |
| 293 | 293 | /*Y0-Y7*/ "","","","","","","","", |
| 294 | 294 | /*Z0-Z7*/ "","","","","","","",""; |
| 295 | + | |
| 296 | + usb_power { | |
| 297 | + gpio-hog; | |
| 298 | + gpios = <ASPEED_GPIO(O, 3) GPIO_ACTIVE_LOW>; | |
| 299 | + output-high; | |
| 300 | + }; | |
| 295 | 301 | }; |
| 296 | 302 | |
| 297 | 303 | &i2c0 { |
| @@ -1881,6 +1887,11 @@ · 1583 unmodified lines | ||
| 1881 | 1887 | |
| 1882 | 1888 | &i2c12 { |
| 1883 | 1889 | status = "okay"; |
| 1890 | + | |
| 1891 | + tpm@2e { | |
| 1892 | + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; | |
| 1893 | + reg = <0x2e>; | |
| 1894 | + }; | |
| 1884 | 1895 | }; |
| 1885 | 1896 | |
| 1886 | 1897 | &i2c13 { |
| @@ -2375,6 +2386,10 @@ · 488 unmodified lines | ||
| 2375 | 2386 | }; |
| 2376 | 2387 | }; |
| 2377 | 2388 | |
| 2389 | +&ehci0 { | |
| 2390 | + status = "okay"; | |
| 2391 | +}; | |
| 2392 | + | |
| 2378 | 2393 | &ehci1 { |
| 2379 | 2394 | status = "okay"; |
| 2380 | 2395 | }; |
| @@ -275,6 +275,12 @@ · 274 unmodified lines | ||
| 275 | 275 | output-high; |
| 276 | 276 | line-name = "I2C3_MUX_OE_N"; |
| 277 | 277 | }; |
| 278 | + | |
| 279 | + usb_power { | |
| 280 | + gpio-hog; | |
| 281 | + gpios = <ASPEED_GPIO(O, 3) GPIO_ACTIVE_LOW>; | |
| 282 | + output-high; | |
| 283 | + }; | |
| 278 | 284 | }; |
| 279 | 285 | |
| 280 | 286 | &emmc_controller { |
| @@ -2061,6 +2067,11 @@ · 1780 unmodified lines | ||
| 2061 | 2067 | &i2c12 { |
| 2062 | 2068 | status = "okay"; |
| 2063 | 2069 | |
| 2070 | + tpm@2e { | |
| 2071 | + compatible = "nuvoton,npct75x"; | |
| 2072 | + reg = <0x2e>; | |
| 2073 | + }; | |
| 2074 | + | |
| 2064 | 2075 | eeprom@50 { |
| 2065 | 2076 | compatible = "atmel,24c64"; |
| 2066 | 2077 | reg = <0x50>; |
| @@ -3,6 +3,7 @@ · 2 unmodified lines | ||
| 3 | 3 | |
| 4 | 4 | #include "aspeed-g5.dtsi" |
| 5 | 5 | #include <dt-bindings/gpio/aspeed-gpio.h> |
| 6 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 6 | 7 | |
| 7 | 8 | / { |
| 8 | 9 | model = "Tyan S7106 BMC"; |
| @@ -127,8 +128,23 @@ · 118 unmodified lines | ||
| 127 | 128 | status = "okay"; |
| 128 | 129 | }; |
| 129 | 130 | |
| 131 | +&uart_routing { | |
| 132 | + status = "okay"; | |
| 133 | +}; | |
| 134 | + | |
| 130 | 135 | &vuart { |
| 131 | 136 | status = "okay"; |
| 137 | + | |
| 138 | + /* We enable the VUART here, but leave it in a state that does | |
| 139 | + * not interfere with the SuperIO. The goal is to have both the | |
| 140 | + * VUART and the SuperIO available and decide at runtime whether | |
| 141 | + * the VUART should actually be used. For that reason, configure | |
| 142 | + * an "invalid" IO address and an IRQ that is not used by the | |
| 143 | + * BMC. | |
| 144 | + */ | |
| 145 | + | |
| 146 | + aspeed,lpc-io-reg = <0xffff>; | |
| 147 | + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; | |
| 132 | 148 | }; |
| 133 | 149 | |
| 134 | 150 | &lpc_ctrl { |
| @@ -213,6 +229,30 @@ · 78 unmodified lines | ||
| 213 | 229 | nct7802@28 { |
| 214 | 230 | compatible = "nuvoton,nct7802"; |
| 215 | 231 | reg = <0x28>; |
| 232 | + | |
| 233 | + #address-cells = <1>; | |
| 234 | + #size-cells = <0>; | |
| 235 | + | |
| 236 | + channel@0 { /* LTD */ | |
| 237 | + reg = <0>; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + channel@1 { /* RTD1 */ | |
| 241 | + reg = <1>; | |
| 242 | + sensor-type = "temperature"; | |
| 243 | + temperature-mode = "thermistor"; | |
| 244 | + }; | |
| 245 | + | |
| 246 | + channel@2 { /* RTD2 */ | |
| 247 | + reg = <2>; | |
| 248 | + sensor-type = "temperature"; | |
| 249 | + temperature-mode = "thermistor"; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + channel@3 { /* RTD3 */ | |
| 253 | + reg = <3>; | |
| 254 | + sensor-type = "temperature"; | |
| 255 | + }; | |
| 216 | 256 | }; |
| 217 | 257 | |
| 218 | 258 | /* Also connected to: |
| @@ -0,0 +1,470 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +/dts-v1/; | |
| 3 | + | |
| 4 | +#include "aspeed-g5.dtsi" | |
| 5 | +#include <dt-bindings/gpio/aspeed-gpio.h> | |
| 6 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 7 | + | |
| 8 | +/ { | |
| 9 | + model = "Tyan S8036 BMC"; | |
| 10 | + compatible = "tyan,s8036-bmc", "aspeed,ast2500"; | |
| 11 | + | |
| 12 | + chosen { | |
| 13 | + stdout-path = &uart5; | |
| 14 | + bootargs = "console=ttyS4,115200 earlycon"; | |
| 15 | + }; | |
| 16 | + | |
| 17 | + memory@80000000 { | |
| 18 | + device_type = "memory"; | |
| 19 | + reg = <0x80000000 0x20000000>; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + reserved-memory { | |
| 23 | + #address-cells = <1>; | |
| 24 | + #size-cells = <1>; | |
| 25 | + ranges; | |
| 26 | + | |
| 27 | + p2a_memory: region@987f0000 { | |
| 28 | + no-map; | |
| 29 | + reg = <0x987f0000 0x00010000>; /* 64KB */ | |
| 30 | + }; | |
| 31 | + | |
| 32 | + vga_memory: framebuffer@9f000000 { | |
| 33 | + no-map; | |
| 34 | + reg = <0x9f000000 0x01000000>; /* 16M */ | |
| 35 | + }; | |
| 36 | + | |
| 37 | + gfx_memory: framebuffer { | |
| 38 | + size = <0x01000000>; /* 16M */ | |
| 39 | + alignment = <0x01000000>; | |
| 40 | + compatible = "shared-dma-pool"; | |
| 41 | + reusable; | |
| 42 | + }; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + leds { | |
| 46 | + compatible = "gpio-leds"; | |
| 47 | + | |
| 48 | + identify { | |
| 49 | + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + heartbeat { | |
| 53 | + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; | |
| 54 | + }; | |
| 55 | + }; | |
| 56 | + | |
| 57 | + iio-hwmon { | |
| 58 | + compatible = "iio-hwmon"; | |
| 59 | + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, | |
| 60 | + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, | |
| 61 | + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, | |
| 62 | + <&adc 12>, <&adc 13>, <&adc 14>; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + iio-hwmon-battery { | |
| 66 | + compatible = "iio-hwmon"; | |
| 67 | + io-channels = <&adc 15>; | |
| 68 | + }; | |
| 69 | +}; | |
| 70 | + | |
| 71 | +&fmc { | |
| 72 | + status = "okay"; | |
| 73 | + flash@0 { | |
| 74 | + label = "bmc"; | |
| 75 | + status = "okay"; | |
| 76 | + m25p,fast-read; | |
| 77 | +#include "openbmc-flash-layout.dtsi" | |
| 78 | + }; | |
| 79 | +}; | |
| 80 | + | |
| 81 | +&spi1 { | |
| 82 | + status = "okay"; | |
| 83 | + pinctrl-names = "default"; | |
| 84 | + pinctrl-0 = <&pinctrl_spi1_default>; | |
| 85 | + | |
| 86 | + flash@0 { | |
| 87 | + status = "okay"; | |
| 88 | + label = "pnor"; | |
| 89 | + m25p,fast-read; | |
| 90 | + }; | |
| 91 | +}; | |
| 92 | + | |
| 93 | +&uart1 { | |
| 94 | + /* Rear RS-232 connector */ | |
| 95 | + status = "okay"; | |
| 96 | + pinctrl-names = "default"; | |
| 97 | + pinctrl-0 = <&pinctrl_txd1_default | |
| 98 | + &pinctrl_rxd1_default>; | |
| 99 | +}; | |
| 100 | + | |
| 101 | +&uart2 { | |
| 102 | + /* RS-232 connector on header */ | |
| 103 | + status = "okay"; | |
| 104 | + pinctrl-names = "default"; | |
| 105 | + pinctrl-0 = <&pinctrl_txd2_default | |
| 106 | + &pinctrl_rxd2_default>; | |
| 107 | +}; | |
| 108 | + | |
| 109 | +&uart3 { | |
| 110 | + /* Alternative to vuart to internally connect (route) to uart1 | |
| 111 | + * when vuart cannot be used due to BIOS limitations. | |
| 112 | + */ | |
| 113 | + status = "okay"; | |
| 114 | +}; | |
| 115 | + | |
| 116 | +&uart4 { | |
| 117 | + /* Alternative to vuart to internally connect (route) to the | |
| 118 | + * external port usually used by uart1 when vuart cannot be | |
| 119 | + * used due to BIOS limitations. | |
| 120 | + */ | |
| 121 | + status = "okay"; | |
| 122 | +}; | |
| 123 | + | |
| 124 | +&uart5 { | |
| 125 | + /* BMC "debug" (console) UART; connected to RS-232 connector | |
| 126 | + * on header; selectable via jumpers as alternative to uart2 | |
| 127 | + */ | |
| 128 | + status = "okay"; | |
| 129 | +}; | |
| 130 | + | |
| 131 | +&uart_routing { | |
| 132 | + status = "okay"; | |
| 133 | +}; | |
| 134 | + | |
| 135 | +&vuart { | |
| 136 | + status = "okay"; | |
| 137 | + | |
| 138 | + /* We enable the VUART here, but leave it in a state that does | |
| 139 | + * not interfere with the SuperIO. The goal is to have both the | |
| 140 | + * VUART and the SuperIO available and decide at runtime whether | |
| 141 | + * the VUART should actually be used. For that reason, configure | |
| 142 | + * an "invalid" IO address and an IRQ that is not used by the | |
| 143 | + * BMC. | |
| 144 | + */ | |
| 145 | + aspeed,lpc-io-reg = <0xffff>; | |
| 146 | + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; | |
| 147 | +}; | |
| 148 | + | |
| 149 | +&lpc_ctrl { | |
| 150 | + status = "okay"; | |
| 151 | +}; | |
| 152 | + | |
| 153 | +&p2a { | |
| 154 | + status = "okay"; | |
| 155 | + memory-region = <&p2a_memory>; | |
| 156 | +}; | |
| 157 | + | |
| 158 | +&lpc_snoop { | |
| 159 | + status = "okay"; | |
| 160 | + snoop-ports = <0x80>; | |
| 161 | +}; | |
| 162 | + | |
| 163 | +&adc { | |
| 164 | + status = "okay"; | |
| 165 | +}; | |
| 166 | + | |
| 167 | +&vhub { | |
| 168 | + status = "okay"; | |
| 169 | +}; | |
| 170 | + | |
| 171 | +&pwm_tacho { | |
| 172 | + status = "okay"; | |
| 173 | + pinctrl-names = "default"; | |
| 174 | + pinctrl-0 = <&pinctrl_pwm0_default | |
| 175 | + &pinctrl_pwm1_default | |
| 176 | + &pinctrl_pwm3_default | |
| 177 | + &pinctrl_pwm4_default>; | |
| 178 | + | |
| 179 | + /* CPU fan */ | |
| 180 | + fan@0 { | |
| 181 | + reg = <0x00>; | |
| 182 | + aspeed,fan-tach-ch = /bits/ 8 <0x00>; | |
| 183 | + }; | |
| 184 | + | |
| 185 | + /* PWM group for chassis fans #1, #2, #3 and #4 */ | |
| 186 | + fan@2 { | |
| 187 | + reg = <0x03>; | |
| 188 | + aspeed,fan-tach-ch = /bits/ 8 <0x02>; | |
| 189 | + }; | |
| 190 | + | |
| 191 | + fan@3 { | |
| 192 | + reg = <0x03>; | |
| 193 | + aspeed,fan-tach-ch = /bits/ 8 <0x03>; | |
| 194 | + }; | |
| 195 | + | |
| 196 | + fan@4 { | |
| 197 | + reg = <0x03>; | |
| 198 | + aspeed,fan-tach-ch = /bits/ 8 <0x04>; | |
| 199 | + }; | |
| 200 | + | |
| 201 | + fan@5 { | |
| 202 | + reg = <0x03>; | |
| 203 | + aspeed,fan-tach-ch = /bits/ 8 <0x05>; | |
| 204 | + }; | |
| 205 | + | |
| 206 | + /* PWM group for chassis fans #5 and #6 */ | |
| 207 | + fan@6 { | |
| 208 | + reg = <0x04>; | |
| 209 | + aspeed,fan-tach-ch = /bits/ 8 <0x06>; | |
| 210 | + }; | |
| 211 | + | |
| 212 | + fan@7 { | |
| 213 | + reg = <0x04>; | |
| 214 | + aspeed,fan-tach-ch = /bits/ 8 <0x07>; | |
| 215 | + }; | |
| 216 | +}; | |
| 217 | + | |
| 218 | +&i2c0 { | |
| 219 | + /* Directly connected to Sideband-Temperature Sensor Interface (APML) */ | |
| 220 | + status = "okay"; | |
| 221 | +}; | |
| 222 | + | |
| 223 | +&i2c1 { | |
| 224 | + /* Directly connected to IPMB HDR. */ | |
| 225 | + status = "okay"; | |
| 226 | +}; | |
| 227 | + | |
| 228 | +&i2c2 { | |
| 229 | + status = "okay"; | |
| 230 | + | |
| 231 | + /* BMC EEPROM, incl. mainboard FRU */ | |
| 232 | + eeprom@50 { | |
| 233 | + compatible = "atmel,24c256"; | |
| 234 | + reg = <0x50>; | |
| 235 | + }; | |
| 236 | + /* Also connected to: | |
| 237 | + * - BCM5720 | |
| 238 | + * - FPGA | |
| 239 | + * - FAN HDR | |
| 240 | + * - FPIO HDR | |
| 241 | + */ | |
| 242 | +}; | |
| 243 | + | |
| 244 | +&i2c3 { | |
| 245 | + status = "okay"; | |
| 246 | + | |
| 247 | + /* PSU1 FRU @ 0xA0 */ | |
| 248 | + eeprom@50 { | |
| 249 | + compatible = "atmel,24c02"; | |
| 250 | + reg = <0x50>; | |
| 251 | + }; | |
| 252 | + | |
| 253 | + /* PSU2 FRU @ 0xA2 */ | |
| 254 | + eeprom@51 { | |
| 255 | + compatible = "atmel,24c02"; | |
| 256 | + reg = <0x51>; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + /* PSU1 @ 0xB0 */ | |
| 260 | + power-supply@58 { | |
| 261 | + compatible = "pmbus"; | |
| 262 | + reg = <0x58>; | |
| 263 | + }; | |
| 264 | + | |
| 265 | + /* PSU2 @ 0xB2 */ | |
| 266 | + power-supply@59 { | |
| 267 | + compatible = "pmbus"; | |
| 268 | + reg = <0x59>; | |
| 269 | + }; | |
| 270 | + | |
| 271 | +}; | |
| 272 | + | |
| 273 | +&i2c4 { | |
| 274 | + status = "okay"; | |
| 275 | +}; | |
| 276 | + | |
| 277 | +&i2c5 { | |
| 278 | + status = "okay"; | |
| 279 | + /* Hardware monitor with temperature sensors */ | |
| 280 | + nct7802@28 { | |
| 281 | + compatible = "nuvoton,nct7802"; | |
| 282 | + reg = <0x28>; | |
| 283 | + #address-cells = <1>; | |
| 284 | + #size-cells = <0>; | |
| 285 | + | |
| 286 | + channel@0 { /* LTD */ | |
| 287 | + reg = <0>; | |
| 288 | + status = "okay"; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + channel@1 { /* RTD1 */ | |
| 292 | + reg = <1>; | |
| 293 | + status = "okay"; | |
| 294 | + sensor-type = "temperature"; | |
| 295 | + temperature-mode = "thermistor"; | |
| 296 | + }; | |
| 297 | + | |
| 298 | + channel@2 { /* RTD2 */ | |
| 299 | + reg = <2>; | |
| 300 | + status = "okay"; | |
| 301 | + sensor-type = "temperature"; | |
| 302 | + temperature-mode = "thermistor"; | |
| 303 | + }; | |
| 304 | + | |
| 305 | + channel@3 { /* RTD3 */ | |
| 306 | + reg = <3>; | |
| 307 | + status = "okay"; | |
| 308 | + sensor-type = "temperature"; | |
| 309 | + }; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + /* Also connected to: | |
| 313 | + * - PCA9544 | |
| 314 | + * - CLK BUFF | |
| 315 | + * - OCP FRU | |
| 316 | + */ | |
| 317 | +}; | |
| 318 | + | |
| 319 | +&i2c6 { | |
| 320 | + status = "okay"; | |
| 321 | + /* Connected to: | |
| 322 | + * - PCA9548 @0xE0 | |
| 323 | + * - PCA9548 @0xE2 | |
| 324 | + * - PCA9544 @0xE4 | |
| 325 | + */ | |
| 326 | +}; | |
| 327 | + | |
| 328 | +&i2c7 { | |
| 329 | + status = "okay"; | |
| 330 | + | |
| 331 | + /* Connected to: | |
| 332 | + * - PCH SMBUS #4 | |
| 333 | + */ | |
| 334 | +}; | |
| 335 | + | |
| 336 | +&i2c8 { | |
| 337 | + status = "okay"; | |
| 338 | + | |
| 339 | + /* Not connected */ | |
| 340 | +}; | |
| 341 | + | |
| 342 | +&mac0 { | |
| 343 | + status = "okay"; | |
| 344 | + use-ncsi; | |
| 345 | + pinctrl-names = "default"; | |
| 346 | + pinctrl-0 = <&pinctrl_rmii1_default>; | |
| 347 | +}; | |
| 348 | + | |
| 349 | +&mac1 { | |
| 350 | + status = "okay"; | |
| 351 | + pinctrl-names = "default"; | |
| 352 | + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; | |
| 353 | +}; | |
| 354 | + | |
| 355 | +&ibt { | |
| 356 | + status = "okay"; | |
| 357 | +}; | |
| 358 | + | |
| 359 | +&kcs1 { | |
| 360 | + status = "okay"; | |
| 361 | + aspeed,lpc-io-reg = <0xca8>; | |
| 362 | +}; | |
| 363 | + | |
| 364 | +&kcs3 { | |
| 365 | + status = "okay"; | |
| 366 | + aspeed,lpc-io-reg = <0xca2>; | |
| 367 | +}; | |
| 368 | + | |
| 369 | +/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ | |
| 370 | +&gfx { | |
| 371 | + status = "okay"; | |
| 372 | + memory-region = <&gfx_memory>; | |
| 373 | +}; | |
| 374 | + | |
| 375 | +/* We're following the GPIO naming as defined at | |
| 376 | + * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. | |
| 377 | + * | |
| 378 | + * Notes on led-identify and id-button: | |
| 379 | + * - A physical button is connected to id-button which | |
| 380 | + * triggers the clock on a D flip-flop. The /Q output of the | |
| 381 | + * flip-flop drives its D input. | |
| 382 | + * - The flip-flop's Q output drives led-identify which is | |
| 383 | + * connected to LEDs. | |
| 384 | + * - With that, every button press toggles the LED between on and off. | |
| 385 | + * | |
| 386 | + * Notes on power-, reset- and nmi- button and control: | |
| 387 | + * - The -button signals can be used to monitor physical buttons. | |
| 388 | + * - The -control signals can be used to actuate the specific | |
| 389 | + * operation. | |
| 390 | + * - In hardware, the -button signals are connected to the -control | |
| 391 | + * signals through drivers with the -control signals being | |
| 392 | + * protected through diodes. | |
| 393 | + */ | |
| 394 | +&gpio { | |
| 395 | + status = "okay"; | |
| 396 | + gpio-line-names = | |
| 397 | + /*A0*/ "", | |
| 398 | + /*A1*/ "", | |
| 399 | + /*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */ | |
| 400 | + /*A3*/ "", | |
| 401 | + /*A4*/ "", | |
| 402 | + /*A5*/ "", | |
| 403 | + /*A6*/ "", | |
| 404 | + /*A7*/ "", | |
| 405 | + /*B0-B7*/ "","","","","","","","", | |
| 406 | + /*C0-C7*/ "","","","","","","","", | |
| 407 | + /*D0*/ "", | |
| 408 | + /*D1*/ "", | |
| 409 | + /*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/ | |
| 410 | + /*D3*/ "platform-reset", /* in: RESET_LED_L */ | |
| 411 | + /*D4*/ "", | |
| 412 | + /*D5*/ "", | |
| 413 | + /*D6*/ "", | |
| 414 | + /*D7*/ "", | |
| 415 | + /*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */ | |
| 416 | + /*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */ | |
| 417 | + /*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/ | |
| 418 | + /*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */ | |
| 419 | + /*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */ | |
| 420 | + /*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */ | |
| 421 | + /*E6*/ "TSI_RESERT", | |
| 422 | + /*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */ | |
| 423 | + /*F0*/ "", | |
| 424 | + /*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */ | |
| 425 | + /*F2*/ "", | |
| 426 | + /*F3*/ "", | |
| 427 | + /*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */ | |
| 428 | + /*F5*/ "BMC_SYS_FAULT_LED_L", | |
| 429 | + /*F6*/ "BMC_ASSERT_BIOS_WP_L", | |
| 430 | + /*F7*/ "", | |
| 431 | + /*G0-G7*/ "","","","","","","","", | |
| 432 | + /*H0-H7*/ "","","","","","","","", | |
| 433 | + /*I0-I7*/ "","","","","","","","", | |
| 434 | + /*J0-J7*/ "","","","","","","","", | |
| 435 | + /*K0-K7*/ "","","","","","","","", | |
| 436 | + /*L0-L7*/ "","","","","","","","", | |
| 437 | + /*M0-M7*/ "","","","","","","","", | |
| 438 | + /*N0-N7*/ "","","","","","","","", | |
| 439 | + /*O0-O7*/ "","","","","","","","", | |
| 440 | + /*P0-P7*/ "","","","","","","","", | |
| 441 | + /*Q0*/ "", | |
| 442 | + /*Q1*/ "", | |
| 443 | + /*Q2*/ "", | |
| 444 | + /*Q3*/ "", | |
| 445 | + /*Q4*/ "", | |
| 446 | + /*Q5*/ "", | |
| 447 | + /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */ | |
| 448 | + /*Q7*/ "", | |
| 449 | + /*R0-R7*/ "","","","","","","","", | |
| 450 | + /*S0-S7*/ "","","","","","","","", | |
| 451 | + /*T0-T7*/ "","","","","","","","", | |
| 452 | + /*U0-U7*/ "","","","","","","","", | |
| 453 | + /*V0-V7*/ "","","","","","","","", | |
| 454 | + /*W0-W7*/ "","","","","","","","", | |
| 455 | + /*X0-X7*/ "","","","","","","","", | |
| 456 | + /*Y0-Y7*/ "","","","","","","","", | |
| 457 | + /*Z0-Z2*/ "","","", | |
| 458 | + /*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */ | |
| 459 | + /*Z4-Z7*/ "","","","", | |
| 460 | + /*AA0*/ "", | |
| 461 | + /*AA1*/ "", | |
| 462 | + /*AA2*/ "", | |
| 463 | + /*AA3*/ "", | |
| 464 | + /*AA4*/ "", | |
| 465 | + /*AA5*/ "", | |
| 466 | + /*AA6*/ "", | |
| 467 | + /*AA7*/ "BMC_ASSERT_BMC_READY", | |
| 468 | + /*AB0*/ "BMC_SPD_SEL", | |
| 469 | + /*AB1-AB7*/ "","","","","","",""; | |
| 470 | +}; | |
| @@ -0,0 +1,149 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +// Copyright (C) 2021 YADRO | |
| 3 | +/dts-v1/; | |
| 4 | + | |
| 5 | +#include "aspeed-bmc-vegman.dtsi" | |
| 6 | + | |
| 7 | +/ { | |
| 8 | + model = "YADRO VEGMAN N110 BMC"; | |
| 9 | + compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; | |
| 10 | +}; | |
| 11 | + | |
| 12 | +&gpio { | |
| 13 | + status = "okay"; | |
| 14 | + gpio-line-names = | |
| 15 | + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", | |
| 16 | + /*B0-B7*/ "","","","","","","","", | |
| 17 | + /*C0-C7*/ "","","","","","","","", | |
| 18 | + /*D0-D7*/ "","","","","","","","", | |
| 19 | + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", | |
| 20 | + /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", | |
| 21 | + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", | |
| 22 | + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", | |
| 23 | + /*I0-I7*/ "","","","","","","","", | |
| 24 | + /*J0-J7*/ "","","","","","","","", | |
| 25 | + /*K0-K7*/ "","","","","","","","", | |
| 26 | + /*L0-L7*/ "","","","","","","","", | |
| 27 | + /*M0-M7*/ "","","","","","","","", | |
| 28 | + /*N0-N7*/ "","","","","","","","", | |
| 29 | + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", | |
| 30 | + /*P0-P7*/ "","","","","","","","", | |
| 31 | + /*Q0-Q7*/ "","","","","","","","", | |
| 32 | + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", | |
| 33 | + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", | |
| 34 | + /*T0-T7*/ "","","","","","","","", | |
| 35 | + /*U0-U7*/ "","","","","","","","", | |
| 36 | + /*V0-V7*/ "","","","","","","","", | |
| 37 | + /*W0-W7*/ "","","","","","","","", | |
| 38 | + /*X0-X7*/ "","","","","","","","", | |
| 39 | + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", | |
| 40 | + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", | |
| 41 | + /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", | |
| 42 | + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", | |
| 43 | + /*AC0-AC7*/ "","","","","","","",""; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&sgpio { | |
| 47 | + ngpios = <80>; | |
| 48 | + bus-frequency = <2000000>; | |
| 49 | + status = "okay"; | |
| 50 | + /* SGPIO lines. even: input, odd: output */ | |
| 51 | + gpio-line-names = | |
| 52 | + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", | |
| 53 | + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", | |
| 54 | + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", | |
| 55 | + /*D0-D7*/ "","","","","","","","","","","","","","","","", | |
| 56 | + /*E0-E7*/ "","","","","","","","","","","","","","","","", | |
| 57 | + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", | |
| 58 | + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", | |
| 59 | + /*H0-H7*/ "","","","","","","","","","","","","","","","", | |
| 60 | + /*I0-I7*/ "","","","","","","","","","","","","","","","", | |
| 61 | + /*J0-J7*/ "","","","","","","","","","","","","","","",""; | |
| 62 | +}; | |
| 63 | + | |
| 64 | +&i2c11 { | |
| 65 | + /* SMB_BMC_MGMT_LVC3 */ | |
| 66 | + gpio@21 { | |
| 67 | + compatible = "nxp,pcal9535"; | |
| 68 | + reg = <0x21>; | |
| 69 | + gpio-controller; | |
| 70 | + #gpio-cells = <2>; | |
| 71 | + gpio-line-names = | |
| 72 | + /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", | |
| 73 | + /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; | |
| 74 | + }; | |
| 75 | + gpio@27 { | |
| 76 | + compatible = "nxp,pca9698"; | |
| 77 | + reg = <0x27>; | |
| 78 | + gpio-controller; | |
| 79 | + #gpio-cells = <2>; | |
| 80 | + gpio-line-names = | |
| 81 | + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", | |
| 82 | + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", | |
| 83 | + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", | |
| 84 | + /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", | |
| 85 | + /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; | |
| 86 | + }; | |
| 87 | +}; | |
| 88 | + | |
| 89 | +&i2c13 { | |
| 90 | + /* SMB_PCIE2_STBY_LVC3 */ | |
| 91 | + mux-expa@73 { | |
| 92 | + compatible = "nxp,pca9545"; | |
| 93 | + reg = <0x73>; | |
| 94 | + #address-cells = <1>; | |
| 95 | + #size-cells = <0>; | |
| 96 | + i2c-mux-idle-disconnect; | |
| 97 | + }; | |
| 98 | + mux-sata@71 { | |
| 99 | + compatible = "nxp,pca9543"; | |
| 100 | + reg = <0x71>; | |
| 101 | + #address-cells = <1>; | |
| 102 | + #size-cells = <0>; | |
| 103 | + i2c-mux-idle-disconnect; | |
| 104 | + }; | |
| 105 | +}; | |
| 106 | + | |
| 107 | +&i2c2 { | |
| 108 | + /* SMB_PCIE_STBY_LVC3 */ | |
| 109 | + mux-expb@71 { | |
| 110 | + compatible = "nxp,pca9545"; | |
| 111 | + reg = <0x71>; | |
| 112 | + #address-cells = <1>; | |
| 113 | + #size-cells = <0>; | |
| 114 | + i2c-mux-idle-disconnect; | |
| 115 | + }; | |
| 116 | +}; | |
| 117 | + | |
| 118 | +&pwm_tacho { | |
| 119 | + status = "okay"; | |
| 120 | + pinctrl-names = "default"; | |
| 121 | + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default | |
| 122 | + &pinctrl_pwm2_default &pinctrl_pwm3_default | |
| 123 | + &pinctrl_pwm4_default &pinctrl_pwm5_default>; | |
| 124 | + | |
| 125 | + fan@0 { | |
| 126 | + reg = <0x00>; | |
| 127 | + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; | |
| 128 | + }; | |
| 129 | + fan@1 { | |
| 130 | + reg = <0x01>; | |
| 131 | + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; | |
| 132 | + }; | |
| 133 | + fan@2 { | |
| 134 | + reg = <0x02>; | |
| 135 | + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; | |
| 136 | + }; | |
| 137 | + fan@3 { | |
| 138 | + reg = <0x03>; | |
| 139 | + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; | |
| 140 | + }; | |
| 141 | + fan@4 { | |
| 142 | + reg = <0x04>; | |
| 143 | + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; | |
| 144 | + }; | |
| 145 | + fan@5 { | |
| 146 | + reg = <0x05>; | |
| 147 | + aspeed,fan-tach-ch = /bits/ 8 <0x05>; | |
| 148 | + }; | |
| 149 | +}; | |
| @@ -0,0 +1,255 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +// Copyright (C) 2021 YADRO | |
| 3 | +/dts-v1/; | |
| 4 | + | |
| 5 | +#include "aspeed-bmc-vegman.dtsi" | |
| 6 | + | |
| 7 | +/ { | |
| 8 | + model = "YADRO VEGMAN Rx20 BMC"; | |
| 9 | + compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500"; | |
| 10 | + | |
| 11 | + leds { | |
| 12 | + compatible = "gpio-leds"; | |
| 13 | + | |
| 14 | + temp_alarm { | |
| 15 | + label = "temp:red:status"; | |
| 16 | + default-state = "off"; | |
| 17 | + gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>; | |
| 18 | + }; | |
| 19 | + | |
| 20 | + temp_ok { | |
| 21 | + label = "temp:green:status"; | |
| 22 | + default-state = "off"; | |
| 23 | + gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + psu_fault { | |
| 27 | + label = "psu:red:status"; | |
| 28 | + default-state = "off"; | |
| 29 | + gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + psu_ok { | |
| 33 | + label = "psu:green:status"; | |
| 34 | + default-state = "off"; | |
| 35 | + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; | |
| 36 | + }; | |
| 37 | + }; | |
| 38 | +}; | |
| 39 | + | |
| 40 | +&gpio { | |
| 41 | + status = "okay"; | |
| 42 | + gpio-line-names = | |
| 43 | + /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", | |
| 44 | + /*B0-B7*/ "","","","","","","","", | |
| 45 | + /*C0-C7*/ "","","","","","","","", | |
| 46 | + /*D0-D7*/ "","","","","","","","", | |
| 47 | + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G", | |
| 48 | + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","", | |
| 49 | + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","", | |
| 50 | + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", | |
| 51 | + /*I0-I7*/ "","","","","","","","", | |
| 52 | + /*J0-J7*/ "","","","","","","","", | |
| 53 | + /*K0-K7*/ "","","","","","","","", | |
| 54 | + /*L0-L7*/ "","","","","","","","", | |
| 55 | + /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","", | |
| 56 | + /*N0-N7*/ "","","","","","","","", | |
| 57 | + /*O0-O7*/ "","","","","","","","", | |
| 58 | + /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS", | |
| 59 | + /*Q0-Q7*/ "","","","","","","","", | |
| 60 | + /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","", | |
| 61 | + /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", | |
| 62 | + /*T0-T7*/ "","","","","","","","", | |
| 63 | + /*U0-U7*/ "","","","","","","","", | |
| 64 | + /*V0-V7*/ "","","","","","","","", | |
| 65 | + /*W0-W7*/ "","","","","","","","", | |
| 66 | + /*X0-X7*/ "","","","","","","","", | |
| 67 | + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", | |
| 68 | + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", | |
| 69 | + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", | |
| 70 | + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","", | |
| 71 | + /*AC0-AC7*/ "","","","","","","",""; | |
| 72 | +}; | |
| 73 | + | |
| 74 | +&sgpio { | |
| 75 | + ngpios = <80>; | |
| 76 | + bus-frequency = <2000000>; | |
| 77 | + status = "okay"; | |
| 78 | + /* SGPIO lines. even: input, odd: output */ | |
| 79 | + gpio-line-names = | |
| 80 | + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", | |
| 81 | + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", | |
| 82 | + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", | |
| 83 | + /*D0-D7*/ "","","","","","","","","","","","","","","","", | |
| 84 | + /*E0-E7*/ "","","","","","","","","","","","","","","","", | |
| 85 | + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", | |
| 86 | + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", | |
| 87 | + /*H0-H7*/ "","","","","","","","","","","","","","","","", | |
| 88 | + /*I0-I7*/ "","","","","","","","","","","","","","","","", | |
| 89 | + /*J0-J7*/ "","","","","","","","","","","","","","","",""; | |
| 90 | +}; | |
| 91 | + | |
| 92 | +&i2c11 { | |
| 93 | + /* SMB_BMC_MGMT_LVC3 */ | |
| 94 | + gpio@21 { | |
| 95 | + compatible = "nxp,pcal9535"; | |
| 96 | + reg = <0x21>; | |
| 97 | + gpio-controller; | |
| 98 | + #gpio-cells = <2>; | |
| 99 | + gpio-line-names = | |
| 100 | + /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N", | |
| 101 | + /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", ""; | |
| 102 | + }; | |
| 103 | + gpio@23 { | |
| 104 | + compatible = "nxp,pcal9535"; | |
| 105 | + reg = <0x23>; | |
| 106 | + gpio-controller; | |
| 107 | + #gpio-cells = <2>; | |
| 108 | + gpio-line-names = | |
| 109 | + /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "", | |
| 110 | + /*IO1.0-1.7*/ "", "", "", "", "", "", "", ""; | |
| 111 | + }; | |
| 112 | + gpio@27 { | |
| 113 | + compatible = "nxp,pca9698"; | |
| 114 | + reg = <0x27>; | |
| 115 | + gpio-controller; | |
| 116 | + #gpio-cells = <2>; | |
| 117 | + gpio-line-names = | |
| 118 | + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", | |
| 119 | + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", | |
| 120 | + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", | |
| 121 | + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", | |
| 122 | + /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1"; | |
| 123 | + }; | |
| 124 | + gpio@39 { | |
| 125 | + compatible = "nxp,pca9554"; | |
| 126 | + reg = <0x39>; | |
| 127 | + gpio-controller; | |
| 128 | + #gpio-cells = <2>; | |
| 129 | + gpio-line-names = | |
| 130 | + /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", ""; | |
| 131 | + }; | |
| 132 | +}; | |
| 133 | + | |
| 134 | +&i2c13 { | |
| 135 | + /* SMB_PCIE2_STBY_LVC3 */ | |
| 136 | + mux-expa@70 { | |
| 137 | + compatible = "nxp,pca9548"; | |
| 138 | + reg = <0x70>; | |
| 139 | + #address-cells = <1>; | |
| 140 | + #size-cells = <0>; | |
| 141 | + i2c-mux-idle-disconnect; | |
| 142 | + | |
| 143 | + i2c@2 { | |
| 144 | + #address-cells = <1>; | |
| 145 | + #size-cells = <0>; | |
| 146 | + reg = <2>; | |
| 147 | + rsra-mux@72 { | |
| 148 | + compatible = "nxp,pca9548"; | |
| 149 | + reg = <0x72>; | |
| 150 | + #address-cells = <1>; | |
| 151 | + #size-cells = <0>; | |
| 152 | + | |
| 153 | + i2c@7 { | |
| 154 | + #address-cells = <1>; | |
| 155 | + #size-cells = <0>; | |
| 156 | + reg = <7>; | |
| 157 | + at24@50 { | |
| 158 | + compatible = "atmel,24c64"; | |
| 159 | + reg = <0x50>; | |
| 160 | + pagesize = <32>; | |
| 161 | + size = <8192>; | |
| 162 | + address-width = <16>; | |
| 163 | + }; | |
| 164 | + }; | |
| 165 | + }; | |
| 166 | + }; | |
| 167 | + }; | |
| 168 | + mux-sata@71 { | |
| 169 | + compatible = "nxp,pca9543"; | |
| 170 | + reg = <0x71>; | |
| 171 | + #address-cells = <1>; | |
| 172 | + #size-cells = <0>; | |
| 173 | + i2c-mux-idle-disconnect; | |
| 174 | + }; | |
| 175 | +}; | |
| 176 | + | |
| 177 | +&i2c2 { | |
| 178 | + /* SMB_PCIE_STBY_LVC3 */ | |
| 179 | + mux-expb@71 { | |
| 180 | + compatible = "nxp,pca9548"; | |
| 181 | + reg = <0x71>; | |
| 182 | + #address-cells = <1>; | |
| 183 | + #size-cells = <0>; | |
| 184 | + i2c-mux-idle-disconnect; | |
| 185 | + | |
| 186 | + i2c@0 { | |
| 187 | + #address-cells = <1>; | |
| 188 | + #size-cells = <0>; | |
| 189 | + reg = <0>; | |
| 190 | + rsrb-mux@72 { | |
| 191 | + compatible = "nxp,pca9548"; | |
| 192 | + reg = <0x72>; | |
| 193 | + #address-cells = <1>; | |
| 194 | + #size-cells = <0>; | |
| 195 | + i2c@7 { | |
| 196 | + #address-cells = <1>; | |
| 197 | + #size-cells = <0>; | |
| 198 | + reg = <7>; | |
| 199 | + at24@50 { | |
| 200 | + compatible = "atmel,24c64"; | |
| 201 | + reg = <0x50>; | |
| 202 | + pagesize = <32>; | |
| 203 | + size = <8192>; | |
| 204 | + address-width = <16>; | |
| 205 | + }; | |
| 206 | + }; | |
| 207 | + }; | |
| 208 | + at24@50 { | |
| 209 | + compatible = "atmel,24c64"; | |
| 210 | + reg = <0x50>; | |
| 211 | + pagesize = <32>; | |
| 212 | + size = <8192>; | |
| 213 | + address-width = <16>; | |
| 214 | + }; | |
| 215 | + }; | |
| 216 | + }; | |
| 217 | +}; | |
| 218 | + | |
| 219 | +&pwm_tacho { | |
| 220 | + status = "okay"; | |
| 221 | + pinctrl-names = "default"; | |
| 222 | + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default | |
| 223 | + &pinctrl_pwm2_default &pinctrl_pwm3_default | |
| 224 | + &pinctrl_pwm4_default &pinctrl_pwm5_default | |
| 225 | + &pinctrl_pwm6_default>; | |
| 226 | + | |
| 227 | + fan@0 { | |
| 228 | + reg = <0x00>; | |
| 229 | + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>; | |
| 230 | + }; | |
| 231 | + fan@1 { | |
| 232 | + reg = <0x01>; | |
| 233 | + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; | |
| 234 | + }; | |
| 235 | + fan@2 { | |
| 236 | + reg = <0x02>; | |
| 237 | + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; | |
| 238 | + }; | |
| 239 | + fan@3 { | |
| 240 | + reg = <0x03>; | |
| 241 | + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; | |
| 242 | + }; | |
| 243 | + fan@4 { | |
| 244 | + reg = <0x04>; | |
| 245 | + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; | |
| 246 | + }; | |
| 247 | + fan@5 { | |
| 248 | + reg = <0x05>; | |
| 249 | + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>; | |
| 250 | + }; | |
| 251 | + fan@6 { | |
| 252 | + reg = <0x06>; | |
| 253 | + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>; | |
| 254 | + }; | |
| 255 | +}; | |
| @@ -0,0 +1,154 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +// Copyright (C) 2021 YADRO | |
| 3 | +/dts-v1/; | |
| 4 | + | |
| 5 | +#include "aspeed-bmc-vegman.dtsi" | |
| 6 | + | |
| 7 | +/ { | |
| 8 | + model = "YADRO VEGMAN Sx20 BMC"; | |
| 9 | + compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; | |
| 10 | +}; | |
| 11 | + | |
| 12 | +&gpio { | |
| 13 | + status = "okay"; | |
| 14 | + gpio-line-names = | |
| 15 | + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", | |
| 16 | + /*B0-B7*/ "","","","","","","","", | |
| 17 | + /*C0-C7*/ "","","","","","","","", | |
| 18 | + /*D0-D7*/ "","","","","","","","", | |
| 19 | + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", | |
| 20 | + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", | |
| 21 | + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", | |
| 22 | + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", | |
| 23 | + /*I0-I7*/ "","","","","","","","", | |
| 24 | + /*J0-J7*/ "","","","","","","","", | |
| 25 | + /*K0-K7*/ "","","","","","","","", | |
| 26 | + /*L0-L7*/ "","","","","","","","", | |
| 27 | + /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", | |
| 28 | + /*N0-N7*/ "","","","","","","","", | |
| 29 | + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", | |
| 30 | + /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", | |
| 31 | + /*Q0-Q7*/ "","","","","","","","", | |
| 32 | + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", | |
| 33 | + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", | |
| 34 | + /*T0-T7*/ "","","","","","","","", | |
| 35 | + /*U0-U7*/ "","","","","","","","", | |
| 36 | + /*V0-V7*/ "","","","","","","","", | |
| 37 | + /*W0-W7*/ "","","","","","","","", | |
| 38 | + /*X0-X7*/ "","","","","","","","", | |
| 39 | + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", | |
| 40 | + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", | |
| 41 | + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", | |
| 42 | + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", | |
| 43 | + /*AC0-AC7*/ "","","","","","","",""; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&sgpio { | |
| 47 | + ngpios = <80>; | |
| 48 | + bus-frequency = <2000000>; | |
| 49 | + status = "okay"; | |
| 50 | + /* SGPIO lines. even: input, odd: output */ | |
| 51 | + gpio-line-names = | |
| 52 | + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", | |
| 53 | + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", | |
| 54 | + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", | |
| 55 | + /*D0-D7*/ "","","","","","","","","","","","","","","","", | |
| 56 | + /*E0-E7*/ "","","","","","","","","","","","","","","","", | |
| 57 | + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", | |
| 58 | + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", | |
| 59 | + /*H0-H7*/ "","","","","","","","","","","","","","","","", | |
| 60 | + /*I0-I7*/ "","","","","","","","","","","","","","","","", | |
| 61 | + /*J0-J7*/ "","","","","","","","","","","","","","","",""; | |
| 62 | +}; | |
| 63 | + | |
| 64 | +&i2c11 { | |
| 65 | + /* SMB_BMC_MGMT_LVC3 */ | |
| 66 | + gpio@21 { | |
| 67 | + compatible = "nxp,pcal9535"; | |
| 68 | + reg = <0x21>; | |
| 69 | + gpio-controller; | |
| 70 | + #gpio-cells = <2>; | |
| 71 | + gpio-line-names = | |
| 72 | + /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", | |
| 73 | + /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; | |
| 74 | + }; | |
| 75 | + gpio@27 { | |
| 76 | + compatible = "nxp,pca9698"; | |
| 77 | + reg = <0x27>; | |
| 78 | + gpio-controller; | |
| 79 | + #gpio-cells = <2>; | |
| 80 | + gpio-line-names = | |
| 81 | + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", | |
| 82 | + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", | |
| 83 | + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", | |
| 84 | + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", | |
| 85 | + /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; | |
| 86 | + }; | |
| 87 | +}; | |
| 88 | + | |
| 89 | +&i2c13 { | |
| 90 | + /* SMB_PCIE2_STBY_LVC3 */ | |
| 91 | + mux-expa@73 { | |
| 92 | + compatible = "nxp,pca9545"; | |
| 93 | + reg = <0x73>; | |
| 94 | + #address-cells = <1>; | |
| 95 | + #size-cells = <0>; | |
| 96 | + i2c-mux-idle-disconnect; | |
| 97 | + }; | |
| 98 | + mux-sata@71 { | |
| 99 | + compatible = "nxp,pca9543"; | |
| 100 | + reg = <0x71>; | |
| 101 | + #address-cells = <1>; | |
| 102 | + #size-cells = <0>; | |
| 103 | + i2c-mux-idle-disconnect; | |
| 104 | + }; | |
| 105 | +}; | |
| 106 | + | |
| 107 | +&i2c2 { | |
| 108 | + /* SMB_PCIE_STBY_LVC3 */ | |
| 109 | + mux-expb@71 { | |
| 110 | + compatible = "nxp,pca9545"; | |
| 111 | + reg = <0x71>; | |
| 112 | + #address-cells = <1>; | |
| 113 | + #size-cells = <0>; | |
| 114 | + i2c-mux-idle-disconnect; | |
| 115 | + }; | |
| 116 | +}; | |
| 117 | + | |
| 118 | +&pwm_tacho { | |
| 119 | + status = "okay"; | |
| 120 | + pinctrl-names = "default"; | |
| 121 | + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default | |
| 122 | + &pinctrl_pwm2_default &pinctrl_pwm3_default | |
| 123 | + &pinctrl_pwm4_default &pinctrl_pwm5_default | |
| 124 | + &pinctrl_pwm6_default>; | |
| 125 | + | |
| 126 | + fan@0 { | |
| 127 | + reg = <0x00>; | |
| 128 | + aspeed,fan-tach-ch = /bits/ 8 <0x00>; | |
| 129 | + }; | |
| 130 | + fan@1 { | |
| 131 | + reg = <0x01>; | |
| 132 | + aspeed,fan-tach-ch = /bits/ 8 <0x01>; | |
| 133 | + }; | |
| 134 | + fan@2 { | |
| 135 | + reg = <0x02>; | |
| 136 | + aspeed,fan-tach-ch = /bits/ 8 <0x02>; | |
| 137 | + }; | |
| 138 | + fan@3 { | |
| 139 | + reg = <0x03>; | |
| 140 | + aspeed,fan-tach-ch = /bits/ 8 <0x03>; | |
| 141 | + }; | |
| 142 | + fan@4 { | |
| 143 | + reg = <0x04>; | |
| 144 | + aspeed,fan-tach-ch = /bits/ 8 <0x04>; | |
| 145 | + }; | |
| 146 | + fan@5 { | |
| 147 | + reg = <0x05>; | |
| 148 | + aspeed,fan-tach-ch = /bits/ 8 <0x05>; | |
| 149 | + }; | |
| 150 | + fan@6 { | |
| 151 | + reg = <0x06>; | |
| 152 | + aspeed,fan-tach-ch = /bits/ 8 <0x06>; | |
| 153 | + }; | |
| 154 | +}; | |
| @@ -0,0 +1,311 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +// Copyright (C) 2021 YADRO | |
| 3 | + | |
| 4 | +#include "aspeed-g5.dtsi" | |
| 5 | +#include <dt-bindings/gpio/aspeed-gpio.h> | |
| 6 | + | |
| 7 | +/ { | |
| 8 | + aliases { | |
| 9 | + serial4 = &uart5; | |
| 10 | + }; | |
| 11 | + | |
| 12 | + chosen { | |
| 13 | + stdout-path = &uart5; | |
| 14 | + bootargs = "console=ttyS4,115200 earlyprintk"; | |
| 15 | + }; | |
| 16 | + | |
| 17 | + memory@80000000 { | |
| 18 | + reg = <0x80000000 0x20000000>; | |
| 19 | + }; | |
| 20 | + | |
| 21 | + reserved-memory { | |
| 22 | + #address-cells = <1>; | |
| 23 | + #size-cells = <1>; | |
| 24 | + ranges; | |
| 25 | + | |
| 26 | + video_engine_memory: jpegbuffer { | |
| 27 | + size = <0x02000000>; /* 32M */ | |
| 28 | + alignment = <0x01000000>; | |
| 29 | + compatible = "shared-dma-pool"; | |
| 30 | + reusable; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + ramoops@9eff0000{ | |
| 34 | + compatible = "ramoops"; | |
| 35 | + reg = <0x9eff0000 0x10000>; | |
| 36 | + record-size = <0x2000>; | |
| 37 | + console-size = <0x2000>; | |
| 38 | + }; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + iio-hwmon { | |
| 42 | + compatible = "iio-hwmon"; | |
| 43 | + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, | |
| 44 | + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, | |
| 45 | + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, | |
| 46 | + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; | |
| 47 | + }; | |
| 48 | + | |
| 49 | + leds { | |
| 50 | + compatible = "gpio-leds"; | |
| 51 | + | |
| 52 | + identify { | |
| 53 | + label = "platform:blue:indicator"; | |
| 54 | + linux,default-trigger = "heartbeat"; | |
| 55 | + gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; | |
| 56 | + }; | |
| 57 | + | |
| 58 | + status_amber { | |
| 59 | + label = "platform:red:status"; | |
| 60 | + default-state = "off"; | |
| 61 | + gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; | |
| 62 | + }; | |
| 63 | + | |
| 64 | + status_green { | |
| 65 | + label = "platform:green:status"; | |
| 66 | + default-state = "off"; | |
| 67 | + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + power_fault { | |
| 71 | + label = "platform:red:power"; | |
| 72 | + default-state = "off"; | |
| 73 | + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; | |
| 74 | + }; | |
| 75 | + | |
| 76 | + power_ok { | |
| 77 | + label = "platform:green:power"; | |
| 78 | + default-state = "off"; | |
| 79 | + gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>; | |
| 80 | + }; | |
| 81 | + }; | |
| 82 | + | |
| 83 | + beeper { | |
| 84 | + compatible = "pwm-beeper"; | |
| 85 | + pwms = <&timer 5 1000000 0>; | |
| 86 | + }; | |
| 87 | +}; | |
| 88 | + | |
| 89 | +&fmc { | |
| 90 | + status = "okay"; | |
| 91 | + flash@0 { | |
| 92 | + status = "okay"; | |
| 93 | + label = "bmc"; | |
| 94 | + m25p,fast-read; | |
| 95 | +#include "openbmc-flash-layout-64.dtsi" | |
| 96 | + }; | |
| 97 | +}; | |
| 98 | + | |
| 99 | +&spi2 { | |
| 100 | + status = "okay"; | |
| 101 | + pinctrl-names = "default"; | |
| 102 | + pinctrl-0 = <&pinctrl_spi2ck_default | |
| 103 | + &pinctrl_spi2miso_default | |
| 104 | + &pinctrl_spi2mosi_default | |
| 105 | + &pinctrl_spi2cs0_default>; | |
| 106 | + flash@0 { | |
| 107 | + status = "okay"; | |
| 108 | + label = "bios"; | |
| 109 | + m25p,fast-read; | |
| 110 | + }; | |
| 111 | +}; | |
| 112 | + | |
| 113 | +&mac0 { | |
| 114 | + status = "okay"; | |
| 115 | + use-ncsi; | |
| 116 | + | |
| 117 | + pinctrl-names = "default"; | |
| 118 | + pinctrl-0 = <&pinctrl_rmii1_default>; | |
| 119 | +}; | |
| 120 | + | |
| 121 | +&mac1 { | |
| 122 | + status = "okay"; | |
| 123 | + | |
| 124 | + pinctrl-names = "default"; | |
| 125 | + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; | |
| 126 | + | |
| 127 | + phy-mode = "rgmii"; | |
| 128 | + phy-handle = <&phy>; | |
| 129 | + mdio { | |
| 130 | + #address-cells = <1>; | |
| 131 | + #size-cells = <0>; | |
| 132 | + | |
| 133 | + phy: ethernet-phy@1 { | |
| 134 | + /* KSZ9131 */ | |
| 135 | + compatible = "ethernet-phy-id0022.1640"; | |
| 136 | + reg = <1>; | |
| 137 | + | |
| 138 | + micrel,led-mode = <0>; | |
| 139 | + }; | |
| 140 | + }; | |
| 141 | +}; | |
| 142 | + | |
| 143 | +&vhub { | |
| 144 | + status = "okay"; | |
| 145 | +}; | |
| 146 | + | |
| 147 | +&adc { | |
| 148 | + status = "okay"; | |
| 149 | +}; | |
| 150 | + | |
| 151 | +&video { | |
| 152 | + status = "okay"; | |
| 153 | + memory-region = <&video_engine_memory>; | |
| 154 | +}; | |
| 155 | + | |
| 156 | +&sdmmc { | |
| 157 | + status = "okay"; | |
| 158 | +}; | |
| 159 | + | |
| 160 | +&sdhci1 { | |
| 161 | + status = "okay"; | |
| 162 | + | |
| 163 | + pinctrl-names = "default"; | |
| 164 | + pinctrl-0 = <&pinctrl_sd2_default>; | |
| 165 | + disable-wp; | |
| 166 | +}; | |
| 167 | + | |
| 168 | +&timer { | |
| 169 | + fttmr010,pwm-outputs = <5>; | |
| 170 | + pinctrl-names = "default"; | |
| 171 | + pinctrl-0 = <&pinctrl_timer5_default>; | |
| 172 | + #pwm-cells = <3>; | |
| 173 | + status = "okay"; | |
| 174 | +}; | |
| 175 | + | |
| 176 | +&uart1 { | |
| 177 | + status = "okay"; | |
| 178 | + pinctrl-names = "default"; | |
| 179 | + pinctrl-0 = <&pinctrl_txd1_default | |
| 180 | + &pinctrl_rxd1_default | |
| 181 | + &pinctrl_nrts1_default | |
| 182 | + &pinctrl_ndtr1_default | |
| 183 | + &pinctrl_ndsr1_default | |
| 184 | + &pinctrl_ncts1_default | |
| 185 | + &pinctrl_ndcd1_default | |
| 186 | + &pinctrl_nri1_default>; | |
| 187 | +}; | |
| 188 | + | |
| 189 | +&uart5 { | |
| 190 | + status = "okay"; | |
| 191 | +}; | |
| 192 | + | |
| 193 | +&vuart { | |
| 194 | + status = "okay"; | |
| 195 | +}; | |
| 196 | + | |
| 197 | +&kcs3 { | |
| 198 | + aspeed,lpc-io-reg = <0xCA2>; | |
| 199 | + status = "okay"; | |
| 200 | +}; | |
| 201 | + | |
| 202 | +&kcs4 { | |
| 203 | + aspeed,lpc-io-reg = <0xCA4>; | |
| 204 | + status = "okay"; | |
| 205 | +}; | |
| 206 | + | |
| 207 | +&lpc_snoop { | |
| 208 | + snoop-ports = <0x80>; | |
| 209 | + status = "okay"; | |
| 210 | +}; | |
| 211 | + | |
| 212 | +&uart_routing { | |
| 213 | + status = "okay"; | |
| 214 | +}; | |
| 215 | + | |
| 216 | +&uart2 { | |
| 217 | + status = "okay"; | |
| 218 | + pinctrl-names = "default"; | |
| 219 | + pinctrl-0 = <>; | |
| 220 | +}; | |
| 221 | + | |
| 222 | +&uart3 { | |
| 223 | + status = "okay"; | |
| 224 | + pinctrl-names = "default"; | |
| 225 | + pinctrl-0 = <>; | |
| 226 | +}; | |
| 227 | + | |
| 228 | +&uart4 { | |
| 229 | + status = "okay"; | |
| 230 | + pinctrl-names = "default"; | |
| 231 | + pinctrl-0 = <>; | |
| 232 | +}; | |
| 233 | + | |
| 234 | +&i2c0 { | |
| 235 | + /* SMB_IPMB_STBY_LVC3 */ | |
| 236 | + multi-master; | |
| 237 | + status = "okay"; | |
| 238 | +}; | |
| 239 | + | |
| 240 | +&i2c1 { | |
| 241 | + /* SMB_CHASSENSOR_STBY_LVC3 */ | |
| 242 | + status = "okay"; | |
| 243 | +}; | |
| 244 | + | |
| 245 | +&i2c2 { | |
| 246 | + /* SMB_PCIE_STBY_LVC3 */ | |
| 247 | + status = "okay"; | |
| 248 | +}; | |
| 249 | + | |
| 250 | +&i2c3 { | |
| 251 | + /* SMB_HOST_STBY_LVC3 */ | |
| 252 | + multi-master; | |
| 253 | + status = "okay"; | |
| 254 | +}; | |
| 255 | + | |
| 256 | +&i2c4 { | |
| 257 | + /* BMC_PMBUS2_STBY */ | |
| 258 | + status = "okay"; | |
| 259 | +}; | |
| 260 | + | |
| 261 | +&i2c5 { | |
| 262 | + /* SMB_SMLINK0_STBY_LVC3 */ | |
| 263 | + bus-frequency = <1000000>; | |
| 264 | + multi-master; | |
| 265 | + status = "okay"; | |
| 266 | +}; | |
| 267 | + | |
| 268 | +&i2c6 { | |
| 269 | + /* SMB_TEMPSENSOR_STBY_LVC3 */ | |
| 270 | + multi-master; | |
| 271 | + status = "okay"; | |
| 272 | +}; | |
| 273 | + | |
| 274 | +&i2c7 { | |
| 275 | + /* SMB_SM_PMB1_SML1_STBY_LVC3 */ | |
| 276 | + multi-master; | |
| 277 | + status = "okay"; | |
| 278 | +}; | |
| 279 | + | |
| 280 | +&i2c9 { | |
| 281 | + /* SMB_BMC_ETH3_LVC3 */ | |
| 282 | + status = "okay"; | |
| 283 | +}; | |
| 284 | + | |
| 285 | +&i2c10 { | |
| 286 | + /* SMB_BMC_ETH2_LVC3 */ | |
| 287 | + status = "okay"; | |
| 288 | +}; | |
| 289 | + | |
| 290 | +&i2c11 { | |
| 291 | + /* SMB_BMC_MGMT_LVC3 */ | |
| 292 | + status = "okay"; | |
| 293 | + | |
| 294 | + at24@50 { | |
| 295 | + compatible = "atmel,24c64"; | |
| 296 | + reg = <0x50>; | |
| 297 | + pagesize = <32>; | |
| 298 | + size = <8192>; | |
| 299 | + address-width = <16>; | |
| 300 | + }; | |
| 301 | +}; | |
| 302 | + | |
| 303 | +&i2c12 { | |
| 304 | + /* SMB_BMC_FAULT_EXP_LVC3 */ | |
| 305 | + status = "okay"; | |
| 306 | +}; | |
| 307 | + | |
| 308 | +&i2c13 { | |
| 309 | + /* SMB_PCIE2_STBY_LVC3 */ | |
| 310 | + status = "okay"; | |
| 311 | +}; | |
| @@ -381,6 +381,7 @@ · 380 unmodified lines | ||
| 381 | 381 | compatible = "aspeed,ast2400-ibt-bmc"; |
| 382 | 382 | reg = <0x140 0x18>; |
| 383 | 383 | interrupts = <8>; |
| 384 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 384 | 385 | status = "disabled"; |
| 385 | 386 | }; |
| 386 | 387 | |
| @@ -446,6 +446,7 @@ · 445 unmodified lines | ||
| 446 | 446 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 447 | 447 | reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; |
| 448 | 448 | interrupts = <8>; |
| 449 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 449 | 450 | status = "disabled"; |
| 450 | 451 | }; |
| 451 | 452 | |
| @@ -453,6 +454,7 @@ · 1 unmodified line | ||
| 453 | 454 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 454 | 455 | reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; |
| 455 | 456 | interrupts = <8>; |
| 457 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 456 | 458 | status = "disabled"; |
| 457 | 459 | }; |
| 458 | 460 | |
| @@ -460,6 +462,7 @@ · 1 unmodified line | ||
| 460 | 462 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 461 | 463 | reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; |
| 462 | 464 | interrupts = <8>; |
| 465 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 463 | 466 | status = "disabled"; |
| 464 | 467 | }; |
| 465 | 468 | |
| @@ -467,6 +470,7 @@ · 1 unmodified line | ||
| 467 | 470 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 468 | 471 | reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; |
| 469 | 472 | interrupts = <8>; |
| 473 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 470 | 474 | status = "disabled"; |
| 471 | 475 | }; |
| 472 | 476 | |
| @@ -507,6 +511,7 @@ · 34 unmodified lines | ||
| 507 | 511 | compatible = "aspeed,ast2500-ibt-bmc"; |
| 508 | 512 | reg = <0x140 0x18>; |
| 509 | 513 | interrupts = <8>; |
| 514 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 510 | 515 | status = "disabled"; |
| 511 | 516 | }; |
| 512 | 517 | }; |
| @@ -384,6 +384,11 @@ · 383 unmodified lines | ||
| 384 | 384 | status = "disabled"; |
| 385 | 385 | }; |
| 386 | 386 | |
| 387 | + sbc: secure-boot-controller@1e6f2000 { | |
| 388 | + compatible = "aspeed,ast2600-sbc"; | |
| 389 | + reg = <0x1e6f2000 0x1000>; | |
| 390 | + }; | |
| 391 | + | |
| 387 | 392 | gpio0: gpio@1e780000 { |
| 388 | 393 | #gpio-cells = <2>; |
| 389 | 394 | gpio-controller; |
| @@ -520,6 +525,7 @@ · 130 unmodified lines | ||
| 520 | 525 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 521 | 526 | reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; |
| 522 | 527 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| 528 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 523 | 529 | kcs_chan = <1>; |
| 524 | 530 | status = "disabled"; |
| 525 | 531 | }; |
| @@ -528,6 +534,7 @@ · 2 unmodified lines | ||
| 528 | 534 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 529 | 535 | reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; |
| 530 | 536 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| 537 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 531 | 538 | status = "disabled"; |
| 532 | 539 | }; |
| 533 | 540 | |
| @@ -535,6 +542,7 @@ · 1 unmodified line | ||
| 535 | 542 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 536 | 543 | reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; |
| 537 | 544 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| 545 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 538 | 546 | status = "disabled"; |
| 539 | 547 | }; |
| 540 | 548 | |
| @@ -542,6 +550,7 @@ · 1 unmodified line | ||
| 542 | 550 | compatible = "aspeed,ast2500-kcs-bmc-v2"; |
| 543 | 551 | reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; |
| 544 | 552 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| 553 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 545 | 554 | status = "disabled"; |
| 546 | 555 | }; |
| 547 | 556 | |
| @@ -581,6 +590,7 @@ · 33 unmodified lines | ||
| 581 | 590 | compatible = "aspeed,ast2600-ibt-bmc"; |
| 582 | 591 | reg = <0x140 0x18>; |
| 583 | 592 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 593 | + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| 584 | 594 | status = "disabled"; |
| 585 | 595 | }; |
| 586 | 596 | }; |
| @@ -147,12 +147,6 @@ · 146 unmodified lines | ||
| 147 | 147 | reg = <0x8000 0x3E000>; |
| 148 | 148 | }; |
| 149 | 149 | }; |
| 150 | − | |
| 151 | − spidev@1 { | |
| 152 | − compatible = "spidev"; | |
| 153 | − spi-max-frequency = <2000000>; | |
| 154 | − reg = <1>; | |
| 155 | − }; | |
| 156 | 150 | }; |
| 157 | 151 | |
| 158 | 152 | &spi1 { |
| @@ -160,18 +154,6 @@ · 1 unmodified line | ||
| 160 | 154 | pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>; |
| 161 | 155 | cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>; |
| 162 | 156 | status = "okay"; |
| 163 | − | |
| 164 | − spidev@0 { | |
| 165 | − compatible = "spidev"; | |
| 166 | − spi-max-frequency = <2000000>; | |
| 167 | − reg = <0>; | |
| 168 | − }; | |
| 169 | − | |
| 170 | − spidev@1 { | |
| 171 | − compatible = "spidev"; | |
| 172 | − spi-max-frequency = <2000000>; | |
| 173 | − reg = <1>; | |
| 174 | − }; | |
| 175 | 157 | }; |
| 176 | 158 | |
| 177 | 159 | &usart0 { |
| @@ -66,7 +66,7 @@ · 65 unmodified lines | ||
| 66 | 66 | pinctrl-names = "default"; |
| 67 | 67 | pinctrl-0 = <&pinctrl_sdmmc0_default>; |
| 68 | 68 | non-removable; |
| 69 | − mmc-ddr-1_8v; | |
| 69 | + mmc-ddr-3_3v; | |
| 70 | 70 | status = "okay"; |
| 71 | 71 | }; |
| 72 | 72 | |
| @@ -619,10 +619,9 @@ · 546 unmodified lines | ||
| 619 | 619 | bias-disable; |
| 620 | 620 | }; |
| 621 | 621 | |
| 622 | − ck_cd_rstn_vddsel { | |
| 622 | + ck_cd_rstn { | |
| 623 | 623 | pinmux = <PIN_PA0__SDMMC0_CK>, |
| 624 | 624 | <PIN_PA10__SDMMC0_RSTN>, |
| 625 | − <PIN_PA11__SDMMC0_VDDSEL>, | |
| 626 | 625 | <PIN_PA13__SDMMC0_CD>; |
| 627 | 626 | bias-disable; |
| 628 | 627 | }; |
| @@ -0,0 +1,209 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT | |
| 2 | +/* | |
| 3 | + * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix | |
| 4 | + */ | |
| 5 | +/dts-v1/; | |
| 6 | +#include "sama5d36.dtsi" | |
| 7 | + | |
| 8 | +/ { | |
| 9 | + model = "EVB-KSZ9477"; | |
| 10 | + compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", | |
| 11 | + "atmel,sama5d3", "atmel,sama5"; | |
| 12 | + | |
| 13 | + chosen { | |
| 14 | + stdout-path = &dbgu; | |
| 15 | + }; | |
| 16 | + | |
| 17 | + reg_3v3: regulator-3v3 { | |
| 18 | + compatible = "regulator-fixed"; | |
| 19 | + regulator-name = "3v3"; | |
| 20 | + regulator-min-microvolt = <3300000>; | |
| 21 | + regulator-max-microvolt = <3300000>; | |
| 22 | + }; | |
| 23 | + | |
| 24 | + reg_vcc_mmc0: regulator-mmc0 { | |
| 25 | + compatible = "regulator-fixed"; | |
| 26 | + pinctrl-names = "default"; | |
| 27 | + pinctrl-0 = <&pinctrl_mcc0_vcc>; | |
| 28 | + regulator-name = "mmc0-vcc"; | |
| 29 | + regulator-max-microvolt = <3300000>; | |
| 30 | + regulator-min-microvolt = <3300000>; | |
| 31 | + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; | |
| 32 | + }; | |
| 33 | +}; | |
| 34 | + | |
| 35 | +&dbgu { | |
| 36 | + status = "okay"; | |
| 37 | +}; | |
| 38 | + | |
| 39 | +&ebi { | |
| 40 | + pinctrl-0 = <&pinctrl_ebi_nand_addr>; | |
| 41 | + pinctrl-names = "default"; | |
| 42 | + status = "okay"; | |
| 43 | +}; | |
| 44 | + | |
| 45 | +&i2c0 { | |
| 46 | + pinctrl-0 = <&pinctrl_i2c0_pu>; | |
| 47 | + status = "okay"; | |
| 48 | +}; | |
| 49 | + | |
| 50 | +&macb0 { | |
| 51 | + phy-mode = "rgmii"; | |
| 52 | + status = "okay"; | |
| 53 | + | |
| 54 | + fixed-link { | |
| 55 | + speed = <1000>; | |
| 56 | + full-duplex; | |
| 57 | + }; | |
| 58 | +}; | |
| 59 | + | |
| 60 | +&main_xtal { | |
| 61 | + clock-frequency = <12000000>; | |
| 62 | +}; | |
| 63 | + | |
| 64 | +&mmc0 { | |
| 65 | + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 | |
| 66 | + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; | |
| 67 | + status = "okay"; | |
| 68 | + | |
| 69 | + slot@0 { | |
| 70 | + reg = <0>; | |
| 71 | + bus-width = <8>; | |
| 72 | + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; | |
| 73 | + disable-wp; | |
| 74 | + vmmc-supply = <®_vcc_mmc0>; | |
| 75 | + vqmmc-supply = <®_3v3>; | |
| 76 | + }; | |
| 77 | +}; | |
| 78 | + | |
| 79 | +&nand_controller { | |
| 80 | + status = "okay"; | |
| 81 | + | |
| 82 | + nand@3 { | |
| 83 | + reg = <0x3 0x0 0x2>; | |
| 84 | + atmel,rb = <0>; | |
| 85 | + nand-bus-width = <8>; | |
| 86 | + nand-ecc-mode = "hw"; | |
| 87 | + nand-ecc-strength = <4>; | |
| 88 | + nand-ecc-step-size = <512>; | |
| 89 | + nand-on-flash-bbt; | |
| 90 | + label = "atmel_nand"; | |
| 91 | + }; | |
| 92 | +}; | |
| 93 | + | |
| 94 | +&slow_xtal { | |
| 95 | + clock-frequency = <32768>; | |
| 96 | +}; | |
| 97 | + | |
| 98 | +&spi0 { | |
| 99 | + cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, | |
| 100 | + <&pioD 16 GPIO_ACTIVE_LOW>; | |
| 101 | + status = "okay"; | |
| 102 | +}; | |
| 103 | + | |
| 104 | +&spi1 { | |
| 105 | + pinctrl-0 = <&pinctrl_spi_ksz>; | |
| 106 | + cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; | |
| 107 | + status = "okay"; | |
| 108 | + | |
| 109 | + switch@0 { | |
| 110 | + compatible = "microchip,ksz9477"; | |
| 111 | + reg = <0>; | |
| 112 | + spi-max-frequency = <1000000>; | |
| 113 | + spi-cpha; | |
| 114 | + spi-cpol; | |
| 115 | + | |
| 116 | + ports { | |
| 117 | + #address-cells = <1>; | |
| 118 | + #size-cells = <0>; | |
| 119 | + | |
| 120 | + port@0 { | |
| 121 | + reg = <0>; | |
| 122 | + label = "lan1"; | |
| 123 | + }; | |
| 124 | + | |
| 125 | + port@1 { | |
| 126 | + reg = <1>; | |
| 127 | + label = "lan2"; | |
| 128 | + }; | |
| 129 | + | |
| 130 | + port@2 { | |
| 131 | + reg = <2>; | |
| 132 | + label = "lan3"; | |
| 133 | + }; | |
| 134 | + | |
| 135 | + port@3 { | |
| 136 | + reg = <3>; | |
| 137 | + label = "lan4"; | |
| 138 | + }; | |
| 139 | + | |
| 140 | + port@4 { | |
| 141 | + reg = <4>; | |
| 142 | + label = "lan5"; | |
| 143 | + }; | |
| 144 | + | |
| 145 | + port@5 { | |
| 146 | + reg = <5>; | |
| 147 | + label = "cpu"; | |
| 148 | + ethernet = <&macb0>; | |
| 149 | + phy-mode = "rgmii-txid"; | |
| 150 | + | |
| 151 | + fixed-link { | |
| 152 | + speed = <1000>; | |
| 153 | + full-duplex; | |
| 154 | + }; | |
| 155 | + }; | |
| 156 | + }; | |
| 157 | + }; | |
| 158 | +}; | |
| 159 | + | |
| 160 | +&usb0 { | |
| 161 | + pinctrl-names = "default"; | |
| 162 | + pinctrl-0 = <&pinctrl_usba_vbus>; | |
| 163 | + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; | |
| 164 | + status = "okay"; | |
| 165 | +}; | |
| 166 | + | |
| 167 | +&pinctrl { | |
| 168 | + board { | |
| 169 | + pinctrl_i2c0_pu: i2c0-pu { | |
| 170 | + atmel,pins = | |
| 171 | + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, | |
| 172 | + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + pinctrl_mmc0_cd: mmc0-cd { | |
| 176 | + atmel,pins = <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + pinctrl_mcc0_vcc: mmc0-vcc { | |
| 180 | + atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; | |
| 181 | + }; | |
| 182 | + | |
| 183 | + pinctrl_spi_ksz: spi-ksz { | |
| 184 | + atmel,pins = | |
| 185 | + < | |
| 186 | + /* SPI1_MISO */ | |
| 187 | + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP | |
| 188 | + /* SPI1_MOSI */ | |
| 189 | + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE | |
| 190 | + /* SPI1_SPCK */ | |
| 191 | + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE | |
| 192 | + | |
| 193 | + /* SPI CS */ | |
| 194 | + AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE | |
| 195 | + /* switch IRQ */ | |
| 196 | + AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH | |
| 197 | + /* switch PME_N, SoC IN */ | |
| 198 | + AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP | |
| 199 | + /* switch RST */ | |
| 200 | + AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH | |
| 201 | + >; | |
| 202 | + }; | |
| 203 | + | |
| 204 | + pinctrl_usba_vbus: usba-vbus { | |
| 205 | + atmel,pins = | |
| 206 | + <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; | |
| 207 | + }; | |
| 208 | + }; | |
| 209 | +}; | |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | #include "sama7g5.dtsi" |
| 14 | 14 | #include <dt-bindings/mfd/atmel-flexcom.h> |
| 15 | 15 | #include <dt-bindings/input/input.h> |
| 16 | +#include <dt-bindings/pinctrl/at91.h> | |
| 16 | 17 | |
| 17 | 18 | / { |
| 18 | 19 | model = "Microchip SAMA7G5-EK"; |
| @@ -134,6 +135,59 @@ · 115 unmodified lines | ||
| 134 | 135 | cpu-supply = <&vddcpu>; |
| 135 | 136 | }; |
| 136 | 137 | |
| 138 | +&qspi0 { | |
| 139 | + pinctrl-names = "default"; | |
| 140 | + pinctrl-0 = <&pinctrl_qspi>; | |
| 141 | + status = "okay"; | |
| 142 | + | |
| 143 | + flash@0 { | |
| 144 | + #address-cells = <1>; | |
| 145 | + #size-cells = <1>; | |
| 146 | + compatible = "jedec,spi-nor"; | |
| 147 | + reg = <0>; | |
| 148 | + spi-max-frequency = <133000000>; | |
| 149 | + spi-tx-bus-width = <8>; | |
| 150 | + spi-rx-bus-width = <8>; | |
| 151 | + m25p,fast-read; | |
| 152 | + | |
| 153 | + at91bootstrap@0 { | |
| 154 | + label = "ospi: at91bootstrap"; | |
| 155 | + reg = <0x0 0x40000>; | |
| 156 | + }; | |
| 157 | + | |
| 158 | + bootloader@40000 { | |
| 159 | + label = "ospi: bootloader"; | |
| 160 | + reg = <0x40000 0xc0000>; | |
| 161 | + }; | |
| 162 | + | |
| 163 | + bootloaderenvred@100000 { | |
| 164 | + label = "ospi: bootloader env redundant"; | |
| 165 | + reg = <0x100000 0x40000>; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + bootloaderenv@140000 { | |
| 169 | + label = "ospi: bootloader env"; | |
| 170 | + reg = <0x140000 0x40000>; | |
| 171 | + }; | |
| 172 | + | |
| 173 | + dtb@180000 { | |
| 174 | + label = "ospi: device tree"; | |
| 175 | + reg = <0x180000 0x80000>; | |
| 176 | + }; | |
| 177 | + | |
| 178 | + kernel@200000 { | |
| 179 | + label = "ospi: kernel"; | |
| 180 | + reg = <0x200000 0x600000>; | |
| 181 | + }; | |
| 182 | + | |
| 183 | + rootfs@800000 { | |
| 184 | + label = "ospi: rootfs"; | |
| 185 | + reg = <0x800000 0x7800000>; | |
| 186 | + }; | |
| 187 | + | |
| 188 | + }; | |
| 189 | +}; | |
| 190 | + | |
| 137 | 191 | &dma0 { |
| 138 | 192 | status = "okay"; |
| 139 | 193 | }; |
| @@ -555,6 +609,25 @@ · 415 unmodified lines | ||
| 555 | 609 | bias-disable; |
| 556 | 610 | }; |
| 557 | 611 | |
| 612 | + pinctrl_qspi: qspi { | |
| 613 | + pinmux = <PIN_PB12__QSPI0_IO0>, | |
| 614 | + <PIN_PB11__QSPI0_IO1>, | |
| 615 | + <PIN_PB10__QSPI0_IO2>, | |
| 616 | + <PIN_PB9__QSPI0_IO3>, | |
| 617 | + <PIN_PB16__QSPI0_IO4>, | |
| 618 | + <PIN_PB17__QSPI0_IO5>, | |
| 619 | + <PIN_PB18__QSPI0_IO6>, | |
| 620 | + <PIN_PB19__QSPI0_IO7>, | |
| 621 | + <PIN_PB13__QSPI0_CS>, | |
| 622 | + <PIN_PB14__QSPI0_SCK>, | |
| 623 | + <PIN_PB15__QSPI0_SCKN>, | |
| 624 | + <PIN_PB20__QSPI0_DQS>, | |
| 625 | + <PIN_PB21__QSPI0_INT>; | |
| 626 | + bias-disable; | |
| 627 | + slew-rate = <0>; | |
| 628 | + atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>; | |
| 629 | + }; | |
| 630 | + | |
| 558 | 631 | pinctrl_sdmmc0_default: sdmmc0_default { |
| 559 | 632 | cmd_data { |
| 560 | 633 | pinmux = <PIN_PA1__SDMMC0_CMD>, |
| @@ -90,12 +90,6 @@ · 89 unmodified lines | ||
| 90 | 90 | |
| 91 | 91 | &spi1 { |
| 92 | 92 | status = "okay"; |
| 93 | − | |
| 94 | − spidev@0 { | |
| 95 | − compatible = "spidev"; | |
| 96 | − reg = <0>; | |
| 97 | − spi-max-frequency = <8000000>; | |
| 98 | − }; | |
| 99 | 93 | }; |
| 100 | 94 | |
| 101 | 95 | &usb0 { |
| @@ -112,18 +112,18 @@ · 111 unmodified lines | ||
| 112 | 112 | status = "disabled"; |
| 113 | 113 | }; |
| 114 | 114 | |
| 115 | − pcie_phy: phy@301d0a0 { | |
| 115 | + pcie_phy: pcie_phy@301d0a0 { | |
| 116 | 116 | compatible = "brcm,cygnus-pcie-phy"; |
| 117 | 117 | reg = <0x0301d0a0 0x14>; |
| 118 | 118 | #address-cells = <1>; |
| 119 | 119 | #size-cells = <0>; |
| 120 | 120 | |
| 121 | − pcie0_phy: phy@0 { | |
| 121 | + pcie0_phy: pcie-phy@0 { | |
| 122 | 122 | reg = <0>; |
| 123 | 123 | #phy-cells = <0>; |
| 124 | 124 | }; |
| 125 | 125 | |
| 126 | − pcie1_phy: phy@1 { | |
| 126 | + pcie1_phy: pcie-phy@1 { | |
| 127 | 127 | reg = <1>; |
| 128 | 128 | #phy-cells = <0>; |
| 129 | 129 | }; |
| @@ -274,8 +274,8 @@ · 144 unmodified lines | ||
| 274 | 274 | #address-cells = <3>; |
| 275 | 275 | #size-cells = <2>; |
| 276 | 276 | device_type = "pci"; |
| 277 | − ranges = <0x81000000 0 0 0x28000000 0 0x00010000 | |
| 278 | − 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; | |
| 277 | + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, | |
| 278 | + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; | |
| 279 | 279 | |
| 280 | 280 | phys = <&pcie0_phy>; |
| 281 | 281 | phy-names = "pcie-phy"; |
| @@ -283,7 +283,7 @@ · 1 unmodified line | ||
| 283 | 283 | status = "disabled"; |
| 284 | 284 | |
| 285 | 285 | msi-parent = <&msi0>; |
| 286 | − msi0: msi-controller { | |
| 286 | + msi0: msi { | |
| 287 | 287 | compatible = "brcm,iproc-msi"; |
| 288 | 288 | msi-controller; |
| 289 | 289 | interrupt-parent = <&gic>; |
| @@ -309,8 +309,8 @@ · 19 unmodified lines | ||
| 309 | 309 | #address-cells = <3>; |
| 310 | 310 | #size-cells = <2>; |
| 311 | 311 | device_type = "pci"; |
| 312 | − ranges = <0x81000000 0 0 0x48000000 0 0x00010000 | |
| 313 | − 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; | |
| 312 | + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, | |
| 313 | + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; | |
| 314 | 314 | |
| 315 | 315 | phys = <&pcie1_phy>; |
| 316 | 316 | phy-names = "pcie-phy"; |
| @@ -318,7 +318,7 @@ · 1 unmodified line | ||
| 318 | 318 | status = "disabled"; |
| 319 | 319 | |
| 320 | 320 | msi-parent = <&msi1>; |
| 321 | − msi1: msi-controller { | |
| 321 | + msi1: msi { | |
| 322 | 322 | compatible = "brcm,iproc-msi"; |
| 323 | 323 | msi-controller; |
| 324 | 324 | interrupt-parent = <&gic>; |
| @@ -318,7 +318,7 @@ · 317 unmodified lines | ||
| 318 | 318 | status = "disabled"; |
| 319 | 319 | |
| 320 | 320 | msi-parent = <&msi0>; |
| 321 | − msi0: msi-controller { | |
| 321 | + msi0: msi { | |
| 322 | 322 | compatible = "brcm,iproc-msi"; |
| 323 | 323 | msi-controller; |
| 324 | 324 | interrupt-parent = <&gic>; |
| @@ -354,7 +354,7 @@ · 29 unmodified lines | ||
| 354 | 354 | status = "disabled"; |
| 355 | 355 | |
| 356 | 356 | msi-parent = <&msi1>; |
| 357 | − msi1: msi-controller { | |
| 357 | + msi1: msi { | |
| 358 | 358 | compatible = "brcm,iproc-msi"; |
| 359 | 359 | msi-controller; |
| 360 | 360 | interrupt-parent = <&gic>; |
| @@ -534,7 +534,7 @@ · 533 unmodified lines | ||
| 534 | 534 | }; |
| 535 | 535 | }; |
| 536 | 536 | |
| 537 | − sata: ahci@41000 { | |
| 537 | + sata: sata@41000 { | |
| 538 | 538 | compatible = "brcm,bcm-nsp-ahci"; |
| 539 | 539 | reg-names = "ahci", "top-ctrl"; |
| 540 | 540 | reg = <0x41000 0x1000>, <0x40020 0x1c>; |
| @@ -587,7 +587,7 @@ · 46 unmodified lines | ||
| 587 | 587 | status = "disabled"; |
| 588 | 588 | |
| 589 | 589 | msi-parent = <&msi0>; |
| 590 | − msi0: msi-controller { | |
| 590 | + msi0: msi { | |
| 591 | 591 | compatible = "brcm,iproc-msi"; |
| 592 | 592 | msi-controller; |
| 593 | 593 | interrupt-parent = <&gic>; |
| @@ -624,7 +624,7 @@ · 30 unmodified lines | ||
| 624 | 624 | status = "disabled"; |
| 625 | 625 | |
| 626 | 626 | msi-parent = <&msi1>; |
| 627 | − msi1: msi-controller { | |
| 627 | + msi1: msi { | |
| 628 | 628 | compatible = "brcm,iproc-msi"; |
| 629 | 629 | msi-controller; |
| 630 | 630 | interrupt-parent = <&gic>; |
| @@ -661,7 +661,7 @@ · 30 unmodified lines | ||
| 661 | 661 | status = "disabled"; |
| 662 | 662 | |
| 663 | 663 | msi-parent = <&msi2>; |
| 664 | − msi2: msi-controller { | |
| 664 | + msi2: msi { | |
| 665 | 665 | compatible = "brcm,iproc-msi"; |
| 666 | 666 | msi-controller; |
| 667 | 667 | interrupt-parent = <&gic>; |
| @@ -65,12 +65,12 @@ · 64 unmodified lines | ||
| 65 | 65 | }; |
| 66 | 66 | |
| 67 | 67 | &expgpio { |
| 68 | − gpio-line-names = "BT_ON", | |
| 68 | + gpio-line-names = "BT_ON", /* 0 */ | |
| 69 | 69 | "WL_ON", |
| 70 | 70 | "PWR_LED_OFF", |
| 71 | 71 | "GLOBAL_RESET", |
| 72 | 72 | "VDD_SD_IO_SEL", |
| 73 | − "CAM_GPIO", | |
| 73 | + "CAM_GPIO", /* 5 */ | |
| 74 | 74 | "SD_PWR_ON", |
| 75 | 75 | ""; |
| 76 | 76 | }; |
| @@ -84,66 +84,66 @@ · 7 unmodified lines | ||
| 84 | 84 | * "FOO" = GPIO line named "FOO" on the schematic |
| 85 | 85 | * "FOO_N" = GPIO line named "FOO" on schematic, active low |
| 86 | 86 | */ |
| 87 | − gpio-line-names = "ID_SDA", | |
| 87 | + gpio-line-names = "ID_SDA", /* 0 */ | |
| 88 | 88 | "ID_SCL", |
| 89 | 89 | "SDA1", |
| 90 | 90 | "SCL1", |
| 91 | 91 | "GPIO_GCLK", |
| 92 | − "GPIO5", | |
| 92 | + "GPIO5", /* 5 */ | |
| 93 | 93 | "GPIO6", |
| 94 | 94 | "SPI_CE1_N", |
| 95 | 95 | "SPI_CE0_N", |
| 96 | 96 | "SPI_MISO", |
| 97 | − "SPI_MOSI", | |
| 97 | + "SPI_MOSI", /* 10 */ | |
| 98 | 98 | "SPI_SCLK", |
| 99 | 99 | "GPIO12", |
| 100 | 100 | "GPIO13", |
| 101 | 101 | /* Serial port */ |
| 102 | 102 | "TXD1", |
| 103 | − "RXD1", | |
| 103 | + "RXD1", /* 15 */ | |
| 104 | 104 | "GPIO16", |
| 105 | 105 | "GPIO17", |
| 106 | 106 | "GPIO18", |
| 107 | 107 | "GPIO19", |
| 108 | − "GPIO20", | |
| 108 | + "GPIO20", /* 20 */ | |
| 109 | 109 | "GPIO21", |
| 110 | 110 | "GPIO22", |
| 111 | 111 | "GPIO23", |
| 112 | 112 | "GPIO24", |
| 113 | − "GPIO25", | |
| 113 | + "GPIO25", /* 25 */ | |
| 114 | 114 | "GPIO26", |
| 115 | 115 | "GPIO27", |
| 116 | 116 | "RGMII_MDIO", |
| 117 | 117 | "RGMIO_MDC", |
| 118 | 118 | /* Used by BT module */ |
| 119 | − "CTS0", | |
| 119 | + "CTS0", /* 30 */ | |
| 120 | 120 | "RTS0", |
| 121 | 121 | "TXD0", |
| 122 | 122 | "RXD0", |
| 123 | 123 | /* Used by Wifi */ |
| 124 | 124 | "SD1_CLK", |
| 125 | − "SD1_CMD", | |
| 125 | + "SD1_CMD", /* 35 */ | |
| 126 | 126 | "SD1_DATA0", |
| 127 | 127 | "SD1_DATA1", |
| 128 | 128 | "SD1_DATA2", |
| 129 | 129 | "SD1_DATA3", |
| 130 | 130 | /* Shared with SPI flash */ |
| 131 | − "PWM0_MISO", | |
| 131 | + "PWM0_MISO", /* 40 */ | |
| 132 | 132 | "PWM1_MOSI", |
| 133 | 133 | "STATUS_LED_G_CLK", |
| 134 | 134 | "SPIFLASH_CE_N", |
| 135 | 135 | "SDA0", |
| 136 | − "SCL0", | |
| 136 | + "SCL0", /* 45 */ | |
| 137 | 137 | "RGMII_RXCLK", |
| 138 | 138 | "RGMII_RXCTL", |
| 139 | 139 | "RGMII_RXD0", |
| 140 | 140 | "RGMII_RXD1", |
| 141 | − "RGMII_RXD2", | |
| 141 | + "RGMII_RXD2", /* 50 */ | |
| 142 | 142 | "RGMII_RXD3", |
| 143 | 143 | "RGMII_TXCLK", |
| 144 | 144 | "RGMII_TXCTL", |
| 145 | 145 | "RGMII_TXD0", |
| 146 | − "RGMII_TXD1", | |
| 146 | + "RGMII_TXD1", /* 55 */ | |
| 147 | 147 | "RGMII_TXD2", |
| 148 | 148 | "RGMII_TXD3"; |
| 149 | 149 | }; |
| @@ -68,8 +68,6 @@ · 67 unmodified lines | ||
| 68 | 68 | |
| 69 | 69 | gpio-keys { |
| 70 | 70 | compatible = "gpio-keys"; |
| 71 | − #address-cells = <1>; | |
| 72 | − #size-cells = <0>; | |
| 73 | 71 | |
| 74 | 72 | wps { |
| 75 | 73 | label = "WPS"; |
| @@ -138,6 +136,7 @@ · 62 unmodified lines | ||
| 138 | 136 | fixed-link { |
| 139 | 137 | speed = <1000>; |
| 140 | 138 | full-duplex; |
| 139 | + pause; | |
| 141 | 140 | }; |
| 142 | 141 | }; |
| 143 | 142 | |
| @@ -84,40 +84,6 @@ · 83 unmodified lines | ||
| 84 | 84 | max-brightness = <255>; |
| 85 | 85 | }; |
| 86 | 86 | }; |
| 87 | − | |
| 88 | − i2c { | |
| 89 | − /* | |
| 90 | − * The platform provided I2C does not budge. | |
| 91 | − * This is a replacement until I can figure | |
| 92 | − * out what are the missing bits... | |
| 93 | − */ | |
| 94 | − | |
| 95 | − compatible = "i2c-gpio"; | |
| 96 | − sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; | |
| 97 | − scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; | |
| 98 | − i2c-gpio,delay-us = <10>; /* close to 100 kHz */ | |
| 99 | − #address-cells = <1>; | |
| 100 | − #size-cells = <0>; | |
| 101 | − | |
| 102 | − current_sense: ina219@45 { | |
| 103 | − compatible = "ti,ina219"; | |
| 104 | − reg = <0x45>; | |
| 105 | − shunt-resistor = <60000>; /* = 60 mOhms */ | |
| 106 | − }; | |
| 107 | − | |
| 108 | − eeprom: eeprom@50 { | |
| 109 | − compatible = "atmel,24c64"; | |
| 110 | − reg = <0x50>; | |
| 111 | − pagesize = <32>; | |
| 112 | − read-only; | |
| 113 | − #address-cells = <1>; | |
| 114 | − #size-cells = <1>; | |
| 115 | − | |
| 116 | − mac_address: mac-address@66 { | |
| 117 | − reg = <0x66 0x6>; | |
| 118 | − }; | |
| 119 | − }; | |
| 120 | − }; | |
| 121 | 87 | }; |
| 122 | 88 | |
| 123 | 89 | &uart0 { |
| @@ -228,3 +194,31 @@ · 104 unmodified lines | ||
| 228 | 194 | }; |
| 229 | 195 | }; |
| 230 | 196 | }; |
| 197 | + | |
| 198 | +&i2c0 { | |
| 199 | + status = "okay"; | |
| 200 | + | |
| 201 | + pinctrl-names = "default"; | |
| 202 | + pinctrl-0 = <&pinmux_i2c>; | |
| 203 | + | |
| 204 | + clock-frequency = <100000>; | |
| 205 | + | |
| 206 | + current_sense: ina219@45 { | |
| 207 | + compatible = "ti,ina219"; | |
| 208 | + reg = <0x45>; | |
| 209 | + shunt-resistor = <60000>; /* = 60 mOhms */ | |
| 210 | + }; | |
| 211 | + | |
| 212 | + eeprom: eeprom@50 { | |
| 213 | + compatible = "atmel,24c64"; | |
| 214 | + reg = <0x50>; | |
| 215 | + pagesize = <32>; | |
| 216 | + read-only; | |
| 217 | + #address-cells = <1>; | |
| 218 | + #size-cells = <1>; | |
| 219 | + | |
| 220 | + mac_address: mac-address@66 { | |
| 221 | + reg = <0x66 0x6>; | |
| 222 | + }; | |
| 223 | + }; | |
| 224 | +}; | |
| @@ -148,15 +148,6 @@ · 147 unmodified lines | ||
| 148 | 148 | }; |
| 149 | 149 | }; |
| 150 | 150 | |
| 151 | − usb2_phy: usb2-phy@1800c000 { | |
| 152 | − compatible = "brcm,ns-usb2-phy"; | |
| 153 | − reg = <0x1800c000 0x1000>; | |
| 154 | − reg-names = "dmu"; | |
| 155 | − #phy-cells = <0>; | |
| 156 | − clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; | |
| 157 | − clock-names = "phy-ref-clk"; | |
| 158 | − }; | |
| 159 | − | |
| 160 | 151 | axi@18000000 { |
| 161 | 152 | compatible = "brcm,bus-axi"; |
| 162 | 153 | reg = <0x18000000 0x1000>; |
| @@ -423,14 +414,14 @@ · 260 unmodified lines | ||
| 423 | 414 | #address-cells = <1>; |
| 424 | 415 | #size-cells = <1>; |
| 425 | 416 | |
| 426 | − cru@100 { | |
| 427 | − compatible = "simple-bus"; | |
| 417 | + cru-bus@100 { | |
| 418 | + compatible = "brcm,ns-cru", "simple-mfd"; | |
| 428 | 419 | reg = <0x100 0x1a4>; |
| 429 | 420 | ranges; |
| 430 | 421 | #address-cells = <1>; |
| 431 | 422 | #size-cells = <1>; |
| 432 | 423 | |
| 433 | − lcpll0: lcpll0@100 { | |
| 424 | + lcpll0: clock-controller@100 { | |
| 434 | 425 | #clock-cells = <1>; |
| 435 | 426 | compatible = "brcm,nsp-lcpll0"; |
| 436 | 427 | reg = <0x100 0x14>; |
| @@ -439,7 +430,7 @@ · 2 unmodified lines | ||
| 439 | 430 | "sdio", "ddr_phy"; |
| 440 | 431 | }; |
| 441 | 432 | |
| 442 | − genpll: genpll@140 { | |
| 433 | + genpll: clock-controller@140 { | |
| 443 | 434 | #clock-cells = <1>; |
| 444 | 435 | compatible = "brcm,nsp-genpll"; |
| 445 | 436 | reg = <0x140 0x24>; |
| @@ -450,6 +441,20 @@ · 4 unmodified lines | ||
| 450 | 441 | "sata1", "sata2"; |
| 451 | 442 | }; |
| 452 | 443 | |
| 444 | + usb2_phy: phy@164 { | |
| 445 | + compatible = "brcm,ns-usb2-phy"; | |
| 446 | + reg = <0x164 0x4>; | |
| 447 | + brcm,syscon-clkset = <&cru_clkset>; | |
| 448 | + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; | |
| 449 | + clock-names = "phy-ref-clk"; | |
| 450 | + #phy-cells = <0>; | |
| 451 | + }; | |
| 452 | + | |
| 453 | + cru_clkset: syscon@180 { | |
| 454 | + compatible = "brcm,cru-clkset", "syscon"; | |
| 455 | + reg = <0x180 0x4>; | |
| 456 | + }; | |
| 457 | + | |
| 453 | 458 | pinctrl: pin-controller@1c0 { |
| 454 | 459 | compatible = "brcm,bcm4708-pinmux"; |
| 455 | 460 | reg = <0x1c0 0x24>; |
| @@ -118,6 +118,8 @@ · 117 unmodified lines | ||
| 118 | 118 | reg = <0>; |
| 119 | 119 | ethernet = <&sgmii1>; |
| 120 | 120 | phy-mode = "sgmii"; |
| 121 | + qca,sgmii-enable-pll; | |
| 122 | + qca,sgmii-txclk-falling-edge; | |
| 121 | 123 | fixed-link { |
| 122 | 124 | speed = <1000>; |
| 123 | 125 | full-duplex; |
| @@ -194,6 +196,8 @@ · 70 unmodified lines | ||
| 194 | 196 | reg = <0>; |
| 195 | 197 | ethernet = <&sgmii0>; |
| 196 | 198 | phy-mode = "sgmii"; |
| 199 | + qca,sgmii-enable-pll; | |
| 200 | + qca,sgmii-txclk-falling-edge; | |
| 197 | 201 | fixed-link { |
| 198 | 202 | speed = <1000>; |
| 199 | 203 | full-duplex; |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | |
| 6 | 6 | / { |
| 7 | 7 | elpida_ECB240ABACN: lpddr2 { |
| 8 | − compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; | |
| 8 | + compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4"; | |
| 9 | 9 | density = <2048>; |
| 10 | 10 | io-width = <32>; |
| 11 | 11 | |
| @@ -828,9 +828,12 @@ · 827 unmodified lines | ||
| 828 | 828 | compatible = "brcm,bcm4330-bt"; |
| 829 | 829 | |
| 830 | 830 | shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; |
| 831 | − reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; | |
| 831 | + reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; | |
| 832 | 832 | device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; |
| 833 | − host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; | |
| 833 | + | |
| 834 | + interrupt-parent = <&gpx2>; | |
| 835 | + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; | |
| 836 | + interrupt-names = "host-wakeup"; | |
| 834 | 837 | }; |
| 835 | 838 | }; |
| 836 | 839 | |
| @@ -368,7 +368,7 @@ · 367 unmodified lines | ||
| 368 | 368 | status = "disabled"; |
| 369 | 369 | }; |
| 370 | 370 | |
| 371 | − hsi2c_0: hsi2c@12da0000 { | |
| 371 | + hsi2c_0: i2c@12da0000 { | |
| 372 | 372 | compatible = "samsung,exynos5260-hsi2c"; |
| 373 | 373 | reg = <0x12DA0000 0x1000>; |
| 374 | 374 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -381,7 +381,7 @@ · 6 unmodified lines | ||
| 381 | 381 | status = "disabled"; |
| 382 | 382 | }; |
| 383 | 383 | |
| 384 | − hsi2c_1: hsi2c@12db0000 { | |
| 384 | + hsi2c_1: i2c@12db0000 { | |
| 385 | 385 | compatible = "samsung,exynos5260-hsi2c"; |
| 386 | 386 | reg = <0x12DB0000 0x1000>; |
| 387 | 387 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -394,7 +394,7 @@ · 6 unmodified lines | ||
| 394 | 394 | status = "disabled"; |
| 395 | 395 | }; |
| 396 | 396 | |
| 397 | − hsi2c_2: hsi2c@12dc0000 { | |
| 397 | + hsi2c_2: i2c@12dc0000 { | |
| 398 | 398 | compatible = "samsung,exynos5260-hsi2c"; |
| 399 | 399 | reg = <0x12DC0000 0x1000>; |
| 400 | 400 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -407,7 +407,7 @@ · 6 unmodified lines | ||
| 407 | 407 | status = "disabled"; |
| 408 | 408 | }; |
| 409 | 409 | |
| 410 | − hsi2c_3: hsi2c@12dd0000 { | |
| 410 | + hsi2c_3: i2c@12dd0000 { | |
| 411 | 411 | compatible = "samsung,exynos5260-hsi2c"; |
| 412 | 412 | reg = <0x12DD0000 0x1000>; |
| 413 | 413 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -84,7 +84,7 @@ · 83 unmodified lines | ||
| 84 | 84 | partitions { |
| 85 | 85 | compatible = "redboot-fis"; |
| 86 | 86 | /* Eraseblock at 0xfe0000 */ |
| 87 | − fis-index-block = <0x1fc>; | |
| 87 | + fis-index-block = <0x7f>; | |
| 88 | 88 | }; |
| 89 | 89 | }; |
| 90 | 90 | |
| @@ -26,9 +26,9 @@ · 25 unmodified lines | ||
| 26 | 26 | * 2 - 0 |
| 27 | 27 | * 3 - 1 |
| 28 | 28 | * |
| 29 | − * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable | |
| 30 | − * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin | |
| 31 | − * number on the specific port (between 0 and 31). | |
| 29 | + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 | |
| 30 | + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is | |
| 31 | + * the pin number on the specific port (between 0 and 31). | |
| 32 | 32 | */ |
| 33 | 33 | |
| 34 | 34 | #define MX1_PAD_A24__A24 0x00 0x004 |
| @@ -55,7 +55,7 @@ · 54 unmodified lines | ||
| 55 | 55 | |
| 56 | 56 | clocks { |
| 57 | 57 | clk32 { |
| 58 | − compatible = "fsl,imx-clk32", "fixed-clock"; | |
| 58 | + compatible = "fixed-clock"; | |
| 59 | 59 | #clock-cells = <0>; |
| 60 | 60 | clock-frequency = <32000>; |
| 61 | 61 | }; |
| @@ -62,7 +62,7 @@ · 61 unmodified lines | ||
| 62 | 62 | |
| 63 | 63 | clocks { |
| 64 | 64 | osc { |
| 65 | − compatible = "fsl,imx-osc", "fixed-clock"; | |
| 65 | + compatible = "fixed-clock"; | |
| 66 | 66 | #clock-cells = <0>; |
| 67 | 67 | clock-frequency = <24000000>; |
| 68 | 68 | }; |
| @@ -200,7 +200,7 @@ · 131 unmodified lines | ||
| 200 | 200 | }; |
| 201 | 201 | }; |
| 202 | 202 | |
| 203 | − spba@50000000 { | |
| 203 | + spba-bus@50000000 { | |
| 204 | 204 | compatible = "fsl,spba-bus", "simple-bus"; |
| 205 | 205 | #address-cells = <1>; |
| 206 | 206 | #size-cells = <1>; |
| @@ -26,9 +26,9 @@ · 25 unmodified lines | ||
| 26 | 26 | * 2 - 0 |
| 27 | 27 | * 3 - 1 |
| 28 | 28 | * |
| 29 | − * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable | |
| 30 | − * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin | |
| 31 | − * number on the specific port (between 0 and 31). | |
| 29 | + * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 | |
| 30 | + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is | |
| 31 | + * the pin number on the specific port (between 0 and 31). | |
| 32 | 32 | */ |
| 33 | 33 | |
| 34 | 34 | #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 |
| @@ -239,24 +239,6 @@ · 238 unmodified lines | ||
| 239 | 239 | >; |
| 240 | 240 | /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ |
| 241 | 241 | status = "disabled"; |
| 242 | − | |
| 243 | − spi@0 { | |
| 244 | − compatible = "spidev"; | |
| 245 | − reg = <0>; | |
| 246 | − spi-max-frequency = <57600000>; | |
| 247 | − }; | |
| 248 | − | |
| 249 | − spi@1 { | |
| 250 | − compatible = "spidev"; | |
| 251 | − reg = <1>; | |
| 252 | − spi-max-frequency = <57600000>; | |
| 253 | − }; | |
| 254 | − | |
| 255 | − spi@2 { | |
| 256 | − compatible = "spidev"; | |
| 257 | − reg = <2>; | |
| 258 | − spi-max-frequency = <57600000>; | |
| 259 | − }; | |
| 260 | 242 | }; |
| 261 | 243 | }; |
| 262 | 244 | |
| @@ -700,24 +682,6 @@ · 437 unmodified lines | ||
| 700 | 682 | pinctrl-0 = <&spi3_pins_a>; |
| 701 | 683 | clock-frequency = <57600000>; |
| 702 | 684 | status = "okay"; |
| 703 | − | |
| 704 | − spi@0 { | |
| 705 | − compatible = "spidev"; | |
| 706 | − reg = <0>; | |
| 707 | − spi-max-frequency = <57600000>; | |
| 708 | − }; | |
| 709 | − | |
| 710 | − spi@1 { | |
| 711 | − compatible = "spidev"; | |
| 712 | − reg = <1>; | |
| 713 | − spi-max-frequency = <57600000>; | |
| 714 | − }; | |
| 715 | − | |
| 716 | − spi@2 { | |
| 717 | − compatible = "spidev"; | |
| 718 | − reg = <2>; | |
| 719 | − spi-max-frequency = <57600000>; | |
| 720 | − }; | |
| 721 | 685 | }; |
| 722 | 686 | |
| 723 | 687 | &usb0 { |
| @@ -166,7 +166,7 @@ · 165 unmodified lines | ||
| 166 | 166 | }; |
| 167 | 167 | }; |
| 168 | 168 | |
| 169 | − spba@50000000 { | |
| 169 | + spba-bus@50000000 { | |
| 170 | 170 | compatible = "fsl,spba-bus", "simple-bus"; |
| 171 | 171 | #address-cells = <1>; |
| 172 | 172 | #size-cells = <1>; |
| @@ -62,25 +62,25 @@ · 61 unmodified lines | ||
| 62 | 62 | |
| 63 | 63 | clocks { |
| 64 | 64 | ckil { |
| 65 | − compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 65 | + compatible = "fixed-clock"; | |
| 66 | 66 | #clock-cells = <0>; |
| 67 | 67 | clock-frequency = <32768>; |
| 68 | 68 | }; |
| 69 | 69 | |
| 70 | 70 | ckih1 { |
| 71 | − compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 71 | + compatible = "fixed-clock"; | |
| 72 | 72 | #clock-cells = <0>; |
| 73 | 73 | clock-frequency = <22579200>; |
| 74 | 74 | }; |
| 75 | 75 | |
| 76 | 76 | ckih2 { |
| 77 | − compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 77 | + compatible = "fixed-clock"; | |
| 78 | 78 | #clock-cells = <0>; |
| 79 | 79 | clock-frequency = <0>; |
| 80 | 80 | }; |
| 81 | 81 | |
| 82 | 82 | osc { |
| 83 | − compatible = "fsl,imx-osc", "fixed-clock"; | |
| 83 | + compatible = "fixed-clock"; | |
| 84 | 84 | #clock-cells = <0>; |
| 85 | 85 | clock-frequency = <24000000>; |
| 86 | 86 | }; |
| @@ -108,7 +108,7 @@ · 21 unmodified lines | ||
| 108 | 108 | reg = <0x50000000 0x10000000>; |
| 109 | 109 | ranges; |
| 110 | 110 | |
| 111 | − spba@50000000 { | |
| 111 | + spba-bus@50000000 { | |
| 112 | 112 | compatible = "fsl,spba-bus", "simple-bus"; |
| 113 | 113 | #address-cells = <1>; |
| 114 | 114 | #size-cells = <1>; |
| @@ -48,25 +48,25 @@ · 47 unmodified lines | ||
| 48 | 48 | |
| 49 | 49 | clocks { |
| 50 | 50 | ckil { |
| 51 | − compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 51 | + compatible = "fixed-clock"; | |
| 52 | 52 | #clock-cells = <0>; |
| 53 | 53 | clock-frequency = <32768>; |
| 54 | 54 | }; |
| 55 | 55 | |
| 56 | 56 | ckih1 { |
| 57 | − compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 57 | + compatible = "fixed-clock"; | |
| 58 | 58 | #clock-cells = <0>; |
| 59 | 59 | clock-frequency = <0>; |
| 60 | 60 | }; |
| 61 | 61 | |
| 62 | 62 | ckih2 { |
| 63 | − compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 63 | + compatible = "fixed-clock"; | |
| 64 | 64 | #clock-cells = <0>; |
| 65 | 65 | clock-frequency = <0>; |
| 66 | 66 | }; |
| 67 | 67 | |
| 68 | 68 | osc { |
| 69 | − compatible = "fsl,imx-osc", "fixed-clock"; | |
| 69 | + compatible = "fixed-clock"; | |
| 70 | 70 | #clock-cells = <0>; |
| 71 | 71 | clock-frequency = <24000000>; |
| 72 | 72 | }; |
| @@ -178,7 +178,7 @@ · 105 unmodified lines | ||
| 178 | 178 | reg = <0x70000000 0x10000000>; |
| 179 | 179 | ranges; |
| 180 | 180 | |
| 181 | − spba@70000000 { | |
| 181 | + spba-bus@70000000 { | |
| 182 | 182 | compatible = "fsl,spba-bus", "simple-bus"; |
| 183 | 183 | #address-cells = <1>; |
| 184 | 184 | #size-cells = <1>; |
| @@ -192,17 +192,6 @@ · 191 unmodified lines | ||
| 192 | 192 | &gpio3 19 GPIO_ACTIVE_HIGH |
| 193 | 193 | >; |
| 194 | 194 | |
| 195 | − spidev0: spi@0 { | |
| 196 | − compatible = "spidev"; | |
| 197 | − reg = <0>; | |
| 198 | − spi-max-frequency = <54000000>; | |
| 199 | − }; | |
| 200 | − | |
| 201 | − spidev1: spi@1 { | |
| 202 | − compatible = "spidev"; | |
| 203 | − reg = <1>; | |
| 204 | − spi-max-frequency = <54000000>; | |
| 205 | − }; | |
| 206 | 195 | }; |
| 207 | 196 | |
| 208 | 197 | &esdhc1 { |
| @@ -86,25 +86,25 @@ · 85 unmodified lines | ||
| 86 | 86 | |
| 87 | 87 | clocks { |
| 88 | 88 | ckil { |
| 89 | − compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 89 | + compatible = "fixed-clock"; | |
| 90 | 90 | #clock-cells = <0>; |
| 91 | 91 | clock-frequency = <32768>; |
| 92 | 92 | }; |
| 93 | 93 | |
| 94 | 94 | ckih1 { |
| 95 | − compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 95 | + compatible = "fixed-clock"; | |
| 96 | 96 | #clock-cells = <0>; |
| 97 | 97 | clock-frequency = <22579200>; |
| 98 | 98 | }; |
| 99 | 99 | |
| 100 | 100 | ckih2 { |
| 101 | − compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 101 | + compatible = "fixed-clock"; | |
| 102 | 102 | #clock-cells = <0>; |
| 103 | 103 | clock-frequency = <0>; |
| 104 | 104 | }; |
| 105 | 105 | |
| 106 | 106 | osc { |
| 107 | − compatible = "fsl,imx-osc", "fixed-clock"; | |
| 107 | + compatible = "fixed-clock"; | |
| 108 | 108 | #clock-cells = <0>; |
| 109 | 109 | clock-frequency = <24000000>; |
| 110 | 110 | }; |
| @@ -229,7 +229,7 @@ · 118 unmodified lines | ||
| 229 | 229 | reg = <0x50000000 0x10000000>; |
| 230 | 230 | ranges; |
| 231 | 231 | |
| 232 | − spba@50000000 { | |
| 232 | + spba-bus@50000000 { | |
| 233 | 233 | compatible = "fsl,spba-bus", "simple-bus"; |
| 234 | 234 | #address-cells = <1>; |
| 235 | 235 | #size-cells = <1>; |
| @@ -0,0 +1,22 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +ðphy { | |
| 10 | + rxdv-skew-ps = <180>; | |
| 11 | + txen-skew-ps = <0>; | |
| 12 | + rxd3-skew-ps = <180>; | |
| 13 | + rxd2-skew-ps = <180>; | |
| 14 | + rxd1-skew-ps = <180>; | |
| 15 | + rxd0-skew-ps = <180>; | |
| 16 | + txd3-skew-ps = <120>; | |
| 17 | + txd2-skew-ps = <0>; | |
| 18 | + txd1-skew-ps = <300>; | |
| 19 | + txd0-skew-ps = <120>; | |
| 20 | + txc-skew-ps = <1860>; | |
| 21 | + rxc-skew-ps = <1860>; | |
| 22 | +}; | |
| @@ -0,0 +1,21 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/dts-v1/; | |
| 10 | + | |
| 11 | +#include <dt-bindings/gpio/gpio.h> | |
| 12 | +#include "imx6dl-tqma6a.dtsi" | |
| 13 | +#include "imx6qdl-mba6.dtsi" | |
| 14 | +#include "imx6qdl-mba6a.dtsi" | |
| 15 | +#include "imx6dl-mba6.dtsi" | |
| 16 | + | |
| 17 | +/ { | |
| 18 | + model = "TQ TQMa6S/DL on MBa6x"; | |
| 19 | + compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", | |
| 20 | + "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; | |
| 21 | +}; | |
| @@ -0,0 +1,21 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/dts-v1/; | |
| 10 | + | |
| 11 | +#include <dt-bindings/gpio/gpio.h> | |
| 12 | +#include "imx6dl-tqma6b.dtsi" | |
| 13 | +#include "imx6qdl-mba6.dtsi" | |
| 14 | +#include "imx6qdl-mba6b.dtsi" | |
| 15 | +#include "imx6dl-mba6.dtsi" | |
| 16 | + | |
| 17 | +/ { | |
| 18 | + model = "TQ TQMa6S/DL on MBa6x"; | |
| 19 | + compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", | |
| 20 | + "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; | |
| 21 | +}; | |
| @@ -8,6 +8,9 @@ · 7 unmodified lines | ||
| 8 | 8 | #include "imx6dl.dtsi" |
| 9 | 9 | #include "imx6qdl-phytec-phycore-som.dtsi" |
| 10 | 10 | #include "imx6qdl-phytec-mira.dtsi" |
| 11 | +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" | |
| 12 | +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" | |
| 13 | +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" | |
| 11 | 14 | |
| 12 | 15 | / { |
| 13 | 16 | model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; |
| @@ -0,0 +1,44 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +&ecspi5 { | |
| 10 | + pinctrl-names = "default"; | |
| 11 | + pinctrl-0 = <&pinctrl_ecspi5_mba6x>; | |
| 12 | + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; | |
| 13 | +}; | |
| 14 | + | |
| 15 | +ðphy { | |
| 16 | + rxdv-skew-ps = <180>; | |
| 17 | + txen-skew-ps = <120>; | |
| 18 | + rxd3-skew-ps = <180>; | |
| 19 | + rxd2-skew-ps = <180>; | |
| 20 | + rxd1-skew-ps = <180>; | |
| 21 | + rxd0-skew-ps = <180>; | |
| 22 | + txd3-skew-ps = <120>; | |
| 23 | + txd2-skew-ps = <0>; | |
| 24 | + txd1-skew-ps = <180>; | |
| 25 | + txd0-skew-ps = <360>; | |
| 26 | + txc-skew-ps = <1860>; | |
| 27 | + rxc-skew-ps = <1860>; | |
| 28 | +}; | |
| 29 | + | |
| 30 | +&sata { | |
| 31 | + status = "okay"; | |
| 32 | +}; | |
| 33 | + | |
| 34 | +&iomuxc { | |
| 35 | + pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { | |
| 36 | + fsl,pins = < | |
| 37 | + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ | |
| 38 | + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 | |
| 39 | + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 | |
| 40 | + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 | |
| 41 | + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ | |
| 42 | + >; | |
| 43 | + }; | |
| 44 | +}; | |
| @@ -0,0 +1,20 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/dts-v1/; | |
| 10 | + | |
| 11 | +#include "imx6q-tqma6a.dtsi" | |
| 12 | +#include "imx6qdl-mba6.dtsi" | |
| 13 | +#include "imx6qdl-mba6a.dtsi" | |
| 14 | +#include "imx6q-mba6.dtsi" | |
| 15 | + | |
| 16 | +/ { | |
| 17 | + model = "TQ TQMa6Q on MBa6x"; | |
| 18 | + compatible = "tq,imx6q-mba6x-a", "tq,mba6a", | |
| 19 | + "tq,imx6q-tqma6q-a", "fsl,imx6q"; | |
| 20 | +}; | |
| @@ -0,0 +1,20 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/dts-v1/; | |
| 10 | + | |
| 11 | +#include "imx6q-tqma6b.dtsi" | |
| 12 | +#include "imx6qdl-mba6.dtsi" | |
| 13 | +#include "imx6qdl-mba6b.dtsi" | |
| 14 | +#include "imx6q-mba6.dtsi" | |
| 15 | + | |
| 16 | +/ { | |
| 17 | + model = "TQ TQMa6Q on MBa6x"; | |
| 18 | + compatible = "tq,imx6q-mba6x-b", "tq,mba6b", | |
| 19 | + "tq,imx6q-tqma6q-b", "fsl,imx6q"; | |
| 20 | +}; | |
| @@ -8,6 +8,9 @@ · 7 unmodified lines | ||
| 8 | 8 | #include "imx6q.dtsi" |
| 9 | 9 | #include "imx6qdl-phytec-phycore-som.dtsi" |
| 10 | 10 | #include "imx6qdl-phytec-mira.dtsi" |
| 11 | +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" | |
| 12 | +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" | |
| 13 | +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" | |
| 11 | 14 | |
| 12 | 15 | / { |
| 13 | 16 | model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; |
| @@ -8,6 +8,9 @@ · 7 unmodified lines | ||
| 8 | 8 | #include "imx6q.dtsi" |
| 9 | 9 | #include "imx6qdl-phytec-phycore-som.dtsi" |
| 10 | 10 | #include "imx6qdl-phytec-mira.dtsi" |
| 11 | +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" | |
| 12 | +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" | |
| 13 | +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" | |
| 11 | 14 | |
| 12 | 15 | / { |
| 13 | 16 | model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; |
| @@ -0,0 +1,54 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0 | |
| 2 | +// | |
| 3 | +// Copyright (C) 2021 Y Soft Corporation, a.s. | |
| 4 | + | |
| 5 | +/dts-v1/; | |
| 6 | + | |
| 7 | +#include "imx6q.dtsi" | |
| 8 | +#include "imx6dl-yapp4-common.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + model = "Y Soft IOTA Crux i.MX6Quad board"; | |
| 12 | + compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q"; | |
| 13 | + | |
| 14 | + memory@10000000 { | |
| 15 | + device_type = "memory"; | |
| 16 | + reg = <0x10000000 0xf0000000>; | |
| 17 | + }; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +&gpio_oled { | |
| 21 | + status = "okay"; | |
| 22 | +}; | |
| 23 | + | |
| 24 | +&leds { | |
| 25 | + status = "okay"; | |
| 26 | +}; | |
| 27 | + | |
| 28 | +&oled_1305 { | |
| 29 | + status = "okay"; | |
| 30 | +}; | |
| 31 | + | |
| 32 | +&oled_1309 { | |
| 33 | + status = "okay"; | |
| 34 | +}; | |
| 35 | + | |
| 36 | +®_usb_h1_vbus { | |
| 37 | + status = "okay"; | |
| 38 | +}; | |
| 39 | + | |
| 40 | +&touchkeys { | |
| 41 | + status = "okay"; | |
| 42 | +}; | |
| 43 | + | |
| 44 | +&uart2 { | |
| 45 | + status = "disabled"; | |
| 46 | +}; | |
| 47 | + | |
| 48 | +&usbh1 { | |
| 49 | + status = "okay"; | |
| 50 | +}; | |
| 51 | + | |
| 52 | +&usbphy2 { | |
| 53 | + status = "okay"; | |
| 54 | +}; | |
| @@ -95,6 +95,10 @@ · 94 unmodified lines | ||
| 95 | 95 | rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ |
| 96 | 96 | }; |
| 97 | 97 | |
| 98 | +&usbh1 { | |
| 99 | + disable-over-current; | |
| 100 | +}; | |
| 101 | + | |
| 98 | 102 | &usdhc2 { /* SD card */ |
| 99 | 103 | status = "okay"; |
| 100 | 104 | }; |
| @@ -260,6 +260,10 @@ · 259 unmodified lines | ||
| 260 | 260 | status = "okay"; |
| 261 | 261 | }; |
| 262 | 262 | |
| 263 | +&usbh1 { | |
| 264 | + disable-over-current; | |
| 265 | +}; | |
| 266 | + | |
| 263 | 267 | &usdhc2 { /* SD card */ |
| 264 | 268 | status = "okay"; |
| 265 | 269 | }; |
| @@ -132,14 +132,15 @@ · 131 unmodified lines | ||
| 132 | 132 | #size-cells = <0>; |
| 133 | 133 | |
| 134 | 134 | ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ |
| 135 | − compatible = "ethernet-phy-ieee802.3-c22"; | |
| 135 | + compatible = "ethernet-phy-id0007.c0f0", | |
| 136 | + "ethernet-phy-ieee802.3-c22"; | |
| 136 | 137 | interrupt-parent = <&gpio4>; |
| 137 | 138 | interrupts = <15 IRQ_TYPE_LEVEL_LOW>; |
| 138 | 139 | pinctrl-0 = <&pinctrl_ethphy0>; |
| 139 | 140 | pinctrl-names = "default"; |
| 140 | 141 | reg = <0>; |
| 141 | − reset-assert-us = <1000>; | |
| 142 | − reset-deassert-us = <1000>; | |
| 142 | + reset-assert-us = <500>; | |
| 143 | + reset-deassert-us = <500>; | |
| 143 | 144 | reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
| 144 | 145 | smsc,disable-energy-detect; /* Make plugin detection reliable */ |
| 145 | 146 | }; |
| @@ -728,6 +729,7 @@ · 582 unmodified lines | ||
| 728 | 729 | pinctrl_usbh1: usbh1-grp { |
| 729 | 730 | fsl,pins = < |
| 730 | 731 | MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 |
| 732 | + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 | |
| 731 | 733 | >; |
| 732 | 734 | }; |
| 733 | 735 | |
| @@ -0,0 +1,526 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#include <dt-bindings/clock/imx6qdl-clock.h> | |
| 10 | +#include <dt-bindings/gpio/gpio.h> | |
| 11 | +#include <dt-bindings/input/input.h> | |
| 12 | +#include <dt-bindings/sound/fsl-imx-audmux.h> | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + aliases { | |
| 16 | + mmc0 = &usdhc3; | |
| 17 | + mmc1 = &usdhc2; | |
| 18 | + /delete-property/ mmc2; | |
| 19 | + /delete-property/ mmc3; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + chosen { | |
| 23 | + stdout-path = &uart2; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + beeper: gpio-beeper { | |
| 27 | + compatible = "gpio-beeper"; | |
| 28 | + pinctrl-names = "default"; | |
| 29 | + pinctrl-0 = <&pinctrl_gpiobeeper>; | |
| 30 | + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + gpio_buttons: gpio-buttons { | |
| 34 | + compatible = "gpio-keys"; | |
| 35 | + pinctrl-names = "default"; | |
| 36 | + pinctrl-0 = <&pinctrl_gpiobuttons>; | |
| 37 | + | |
| 38 | + button1 { | |
| 39 | + label = "s6"; | |
| 40 | + linux,code = <KEY_F6>; | |
| 41 | + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + button2 { | |
| 45 | + label = "s7"; | |
| 46 | + linux,code = <KEY_F7>; | |
| 47 | + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + button3 { | |
| 51 | + label = "s8"; | |
| 52 | + linux,code = <KEY_F8>; | |
| 53 | + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; | |
| 54 | + }; | |
| 55 | + }; | |
| 56 | + | |
| 57 | + gpio-leds { | |
| 58 | + compatible = "gpio-leds"; | |
| 59 | + pinctrl-names = "default"; | |
| 60 | + pinctrl-0 = <&pinctrl_gpioled>; | |
| 61 | + | |
| 62 | + led1 { | |
| 63 | + label = "led1"; | |
| 64 | + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; | |
| 65 | + linux,default-trigger = "default-on"; | |
| 66 | + }; | |
| 67 | + | |
| 68 | + led2 { | |
| 69 | + label = "led2"; | |
| 70 | + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; | |
| 71 | + linux,default-trigger = "heartbeat"; | |
| 72 | + }; | |
| 73 | + }; | |
| 74 | + | |
| 75 | + reg_mba6_3p3v: regulator-mba6-3p3v { | |
| 76 | + compatible = "regulator-fixed"; | |
| 77 | + regulator-name = "supply-mba6-3p3v"; | |
| 78 | + regulator-min-microvolt = <3300000>; | |
| 79 | + regulator-max-microvolt = <3300000>; | |
| 80 | + regulator-always-on; | |
| 81 | + }; | |
| 82 | + | |
| 83 | + reg_pcie: regulator-pcie { | |
| 84 | + compatible = "regulator-fixed"; | |
| 85 | + regulator-name = "supply-pcie"; | |
| 86 | + regulator-min-microvolt = <3300000>; | |
| 87 | + regulator-max-microvolt = <3300000>; | |
| 88 | + /* PCIE.PWR_EN */ | |
| 89 | + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; | |
| 90 | + enable-active-high; | |
| 91 | + regulator-always-on; | |
| 92 | + vin-supply = <®_mba6_3p3v>; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + reg_vcc3v3_audio: regulator-vcc3v3-audio { | |
| 96 | + compatible = "regulator-fixed"; | |
| 97 | + regulator-name = "vcc3v3-audio"; | |
| 98 | + regulator-min-microvolt = <3300000>; | |
| 99 | + regulator-max-microvolt = <3300000>; | |
| 100 | + vin-supply = <®_mba6_3p3v>; | |
| 101 | + }; | |
| 102 | + | |
| 103 | + sound { | |
| 104 | + compatible = "fsl,imx-audio-tlv320aic32x4"; | |
| 105 | + pinctrl-names = "default"; | |
| 106 | + pinctrl-0 = <&pinctrl_audmux>; | |
| 107 | + model = "imx-audio-tlv320aic32x4"; | |
| 108 | + ssi-controller = <&ssi1>; | |
| 109 | + audio-codec = <&tlv320aic32x4>; | |
| 110 | + audio-asrc = <&asrc>; | |
| 111 | + audio-routing = | |
| 112 | + "IN3_L", "Mic Jack", | |
| 113 | + "Mic Jack", "Mic Bias", | |
| 114 | + "IN1_L", "Line In Jack", | |
| 115 | + "IN1_R", "Line In Jack", | |
| 116 | + "Line Out Jack", "LOL", | |
| 117 | + "Line Out Jack", "LOR"; | |
| 118 | + mux-int-port = <1>; | |
| 119 | + mux-ext-port = <3>; | |
| 120 | + }; | |
| 121 | +}; | |
| 122 | + | |
| 123 | +&audmux { | |
| 124 | + status = "okay"; | |
| 125 | + | |
| 126 | + ssi0 { | |
| 127 | + fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>; | |
| 128 | + fsl,port-config = < | |
| 129 | + (IMX_AUDMUX_V2_PTCR_SYN | | |
| 130 | + IMX_AUDMUX_V2_PTCR_TFSDIR | | |
| 131 | + IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | | |
| 132 | + IMX_AUDMUX_V2_PTCR_TCLKDIR | | |
| 133 | + IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) | |
| 134 | + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | |
| 135 | + >; | |
| 136 | + }; | |
| 137 | + | |
| 138 | + aud3 { | |
| 139 | + fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>; | |
| 140 | + fsl,port-config = < | |
| 141 | + IMX_AUDMUX_V2_PTCR_SYN | |
| 142 | + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) | |
| 143 | + >; | |
| 144 | + }; | |
| 145 | +}; | |
| 146 | + | |
| 147 | +&can1 { | |
| 148 | + pinctrl-names = "default"; | |
| 149 | + pinctrl-0 = <&pinctrl_can1>; | |
| 150 | + status = "okay"; | |
| 151 | +}; | |
| 152 | + | |
| 153 | +&can2 { | |
| 154 | + pinctrl-names = "default"; | |
| 155 | + pinctrl-0 = <&pinctrl_can2>; | |
| 156 | + status = "okay"; | |
| 157 | +}; | |
| 158 | + | |
| 159 | +&ecspi1 { | |
| 160 | + pinctrl-names = "default"; | |
| 161 | + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; | |
| 162 | + cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; | |
| 163 | +}; | |
| 164 | + | |
| 165 | +&fec { | |
| 166 | + phy-mode = "rgmii-id"; | |
| 167 | + phy-handle = <ðphy>; | |
| 168 | + mac-address = [00 00 00 00 00 00]; | |
| 169 | + status = "okay"; | |
| 170 | + | |
| 171 | + mdio { | |
| 172 | + #address-cells = <1>; | |
| 173 | + #size-cells = <0>; | |
| 174 | + | |
| 175 | + ethphy: ethernet-phy@3 { | |
| 176 | + compatible = "ethernet-phy-ieee802.3-c22"; | |
| 177 | + reg = <3>; | |
| 178 | + interrupt-parent = <&gpio1>; | |
| 179 | + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; | |
| 180 | + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; | |
| 181 | + reset-assert-us = <1000>; | |
| 182 | + reset-deassert-us = <100000>; | |
| 183 | + micrel,force-master; | |
| 184 | + max-speed = <1000>; | |
| 185 | + }; | |
| 186 | + }; | |
| 187 | +}; | |
| 188 | + | |
| 189 | +&i2c1 { | |
| 190 | + tlv320aic32x4: audio-codec@18 { | |
| 191 | + compatible = "ti,tlv320aic32x4"; | |
| 192 | + reg = <0x18>; | |
| 193 | + clocks = <&clks IMX6QDL_CLK_CKO>; | |
| 194 | + clock-names = "mclk"; | |
| 195 | + pinctrl-names = "default"; | |
| 196 | + pinctrl-0 = <&pinctrl_codec>; | |
| 197 | + ldoin-supply = <®_vcc3v3_audio>; | |
| 198 | + iov-supply = <®_mba6_3p3v>; | |
| 199 | + }; | |
| 200 | +}; | |
| 201 | + | |
| 202 | +&pcie { | |
| 203 | + pinctrl-names = "default"; | |
| 204 | + pinctrl-0 = <&pinctrl_pcie>; | |
| 205 | + reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; | |
| 206 | + status = "okay"; | |
| 207 | +}; | |
| 208 | + | |
| 209 | +&pwm1 { | |
| 210 | + pinctrl-names = "default"; | |
| 211 | + pinctrl-0 = <&pinctrl_pwm1>; | |
| 212 | + status = "okay"; | |
| 213 | +}; | |
| 214 | + | |
| 215 | +&pwm3 { | |
| 216 | + pinctrl-names = "default"; | |
| 217 | + pinctrl-0 = <&pinctrl_pwm3>; | |
| 218 | + status = "okay"; | |
| 219 | +}; | |
| 220 | + | |
| 221 | +&pwm4 { | |
| 222 | + pinctrl-names = "default"; | |
| 223 | + pinctrl-0 = <&pinctrl_pwm4>; | |
| 224 | + status = "okay"; | |
| 225 | +}; | |
| 226 | + | |
| 227 | +&snvs_poweroff { | |
| 228 | + status = "okay"; | |
| 229 | +}; | |
| 230 | + | |
| 231 | +&ssi1 { | |
| 232 | + status = "okay"; | |
| 233 | +}; | |
| 234 | + | |
| 235 | +&uart2 { | |
| 236 | + pinctrl-names = "default"; | |
| 237 | + pinctrl-0 = <&pinctrl_uart2>; | |
| 238 | + status = "okay"; | |
| 239 | +}; | |
| 240 | + | |
| 241 | + | |
| 242 | +&uart3 { | |
| 243 | + pinctrl-names = "default"; | |
| 244 | + pinctrl-0 = <&pinctrl_uart3>; | |
| 245 | + uart-has-rtscts; | |
| 246 | + status = "okay"; | |
| 247 | +}; | |
| 248 | + | |
| 249 | +&uart4 { | |
| 250 | + pinctrl-names = "default"; | |
| 251 | + pinctrl-0 = <&pinctrl_uart4>; | |
| 252 | + uart-has-rtscts; | |
| 253 | + linux,rs485-enabled-at-boot-time; | |
| 254 | + rs485-rts-active-low; | |
| 255 | + rs485-rx-during-tx; | |
| 256 | + status = "okay"; | |
| 257 | +}; | |
| 258 | + | |
| 259 | +&uart5 { | |
| 260 | + pinctrl-names = "default"; | |
| 261 | + pinctrl-0 = <&pinctrl_uart5>; | |
| 262 | + uart-has-rtscts; | |
| 263 | + status = "okay"; | |
| 264 | +}; | |
| 265 | + | |
| 266 | +&usbh1 { | |
| 267 | + disable-over-current; | |
| 268 | + status = "okay"; | |
| 269 | +}; | |
| 270 | + | |
| 271 | +&usbotg { | |
| 272 | + pinctrl-names = "default"; | |
| 273 | + pinctrl-0 = <&pinctrl_usbotg>; | |
| 274 | + power-active-high; | |
| 275 | + over-current-active-low; | |
| 276 | + srp-disable; | |
| 277 | + hnp-disable; | |
| 278 | + adp-disable; | |
| 279 | + dr_mode = "otg"; | |
| 280 | + status = "okay"; | |
| 281 | +}; | |
| 282 | + | |
| 283 | +/* SD card slot */ | |
| 284 | +&usdhc2 { | |
| 285 | + pinctrl-names = "default"; | |
| 286 | + pinctrl-0 = <&pinctrl_usdhc2>; | |
| 287 | + vmmc-supply = <®_mba6_3p3v>; | |
| 288 | + bus-width = <4>; | |
| 289 | + no-1-8-v; | |
| 290 | + no-mmc; | |
| 291 | + no-sdio; | |
| 292 | + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | |
| 293 | + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; | |
| 294 | + status = "okay"; | |
| 295 | +}; | |
| 296 | + | |
| 297 | +&wdog1 { | |
| 298 | + pinctrl-names = "default"; | |
| 299 | + pinctrl-0 = <&pinctrl_wdog1>; | |
| 300 | + /* does not work on unmodified starter kit */ | |
| 301 | + /* fsl,ext-reset-output; */ | |
| 302 | + status = "okay"; | |
| 303 | +}; | |
| 304 | + | |
| 305 | +&iomuxc { | |
| 306 | + pinctrl-names = "default"; | |
| 307 | + pinctrl-0 = <&pinctrl_hog>; | |
| 308 | + | |
| 309 | + pinctrl_audmux: audmuxgrp { | |
| 310 | + fsl,pins = < | |
| 311 | + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 | |
| 312 | + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 | |
| 313 | + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 | |
| 314 | + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 | |
| 315 | + >; | |
| 316 | + }; | |
| 317 | + | |
| 318 | + pinctrl_can1: can1grp { | |
| 319 | + fsl,pins = < | |
| 320 | + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 | |
| 321 | + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 | |
| 322 | + >; | |
| 323 | + }; | |
| 324 | + | |
| 325 | + pinctrl_can2: can2grp { | |
| 326 | + fsl,pins = < | |
| 327 | + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 | |
| 328 | + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 | |
| 329 | + >; | |
| 330 | + }; | |
| 331 | + | |
| 332 | + pinctrl_codec: codecgrp { | |
| 333 | + fsl,pins = < | |
| 334 | + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ | |
| 335 | + >; | |
| 336 | + }; | |
| 337 | + | |
| 338 | + pinctrl_ecspi1_mba6: ecspimba6grp { | |
| 339 | + fsl,pins = < | |
| 340 | + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ | |
| 341 | + >; | |
| 342 | + }; | |
| 343 | + | |
| 344 | + pinctrl_enet: enetgrp { | |
| 345 | + fsl,pins = < | |
| 346 | + /* FEC phy IRQ */ | |
| 347 | + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 | |
| 348 | + /* FEC phy reset */ | |
| 349 | + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 | |
| 350 | + /* DSE = 100, 100k up, SPEED = MED */ | |
| 351 | + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 | |
| 352 | + MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 | |
| 353 | + /* DSE = 111, pull 100k up */ | |
| 354 | + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 | |
| 355 | + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 | |
| 356 | + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 | |
| 357 | + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 | |
| 358 | + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 | |
| 359 | + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 | |
| 360 | + /* DSE = 111, pull external */ | |
| 361 | + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 | |
| 362 | + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 | |
| 363 | + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 | |
| 364 | + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 | |
| 365 | + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 | |
| 366 | + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 | |
| 367 | + /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ | |
| 368 | + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 | |
| 369 | + >; | |
| 370 | + }; | |
| 371 | + | |
| 372 | + pinctrl_gpiobeeper: gpiobeepergrp { | |
| 373 | + fsl,pins = < | |
| 374 | + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 | |
| 375 | + >; | |
| 376 | + }; | |
| 377 | + | |
| 378 | + pinctrl_gpiobuttons: gpiobuttongrp { | |
| 379 | + fsl,pins = < | |
| 380 | + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 | |
| 381 | + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 | |
| 382 | + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 | |
| 383 | + >; | |
| 384 | + }; | |
| 385 | + | |
| 386 | + pinctrl_gpioled: gpioledgrp { | |
| 387 | + fsl,pins = < | |
| 388 | + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ | |
| 389 | + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ | |
| 390 | + >; | |
| 391 | + }; | |
| 392 | + | |
| 393 | + pinctrl_hog: hoggrp { | |
| 394 | + fsl,pins = < | |
| 395 | + /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ | |
| 396 | + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 | |
| 397 | + | |
| 398 | + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 | |
| 399 | + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 | |
| 400 | + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 | |
| 401 | + | |
| 402 | + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 | |
| 403 | + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 | |
| 404 | + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 | |
| 405 | + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 | |
| 406 | + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 | |
| 407 | + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 | |
| 408 | + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 | |
| 409 | + | |
| 410 | + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 | |
| 411 | + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 | |
| 412 | + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 | |
| 413 | + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 | |
| 414 | + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 | |
| 415 | + | |
| 416 | + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 | |
| 417 | + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 | |
| 418 | + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 | |
| 419 | + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 | |
| 420 | + | |
| 421 | + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 | |
| 422 | + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 | |
| 423 | + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 | |
| 424 | + | |
| 425 | + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 | |
| 426 | + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 | |
| 427 | + >; | |
| 428 | + }; | |
| 429 | + | |
| 430 | + pinctrl_pcie: pciegrp { | |
| 431 | + fsl,pins = < | |
| 432 | + /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ | |
| 433 | + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ | |
| 434 | + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ | |
| 435 | + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ | |
| 436 | + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ | |
| 437 | + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ | |
| 438 | + >; | |
| 439 | + }; | |
| 440 | + | |
| 441 | + pinctrl_pwm1: pwm1grp { | |
| 442 | + fsl,pins = < | |
| 443 | + /* 100 k PD, DSE 120 OHM, SPPEED LO */ | |
| 444 | + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 | |
| 445 | + >; | |
| 446 | + }; | |
| 447 | + | |
| 448 | + pinctrl_pwm3: pwm3grp { | |
| 449 | + fsl,pins = < | |
| 450 | + /* 100 k PD, DSE 120 OHM, SPPEED LO */ | |
| 451 | + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 | |
| 452 | + >; | |
| 453 | + }; | |
| 454 | + | |
| 455 | + pinctrl_pwm4: pwm4grp { | |
| 456 | + fsl,pins = < | |
| 457 | + /* 100 k PD, DSE 120 OHM, SPPEED LO */ | |
| 458 | + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 | |
| 459 | + >; | |
| 460 | + }; | |
| 461 | + | |
| 462 | + pinctrl_uart2: uart2grp { | |
| 463 | + fsl,pins = < | |
| 464 | + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 | |
| 465 | + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 | |
| 466 | + >; | |
| 467 | + }; | |
| 468 | + | |
| 469 | + pinctrl_uart3: uart3grp { | |
| 470 | + fsl,pins = < | |
| 471 | + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 | |
| 472 | + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 | |
| 473 | + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 | |
| 474 | + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 | |
| 475 | + >; | |
| 476 | + }; | |
| 477 | + | |
| 478 | + pinctrl_uart4: uart4grp { | |
| 479 | + fsl,pins = < | |
| 480 | + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 | |
| 481 | + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 | |
| 482 | + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 | |
| 483 | + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 | |
| 484 | + >; | |
| 485 | + }; | |
| 486 | + | |
| 487 | + pinctrl_uart5: uart5grp { | |
| 488 | + fsl,pins = < | |
| 489 | + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 | |
| 490 | + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 | |
| 491 | + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 | |
| 492 | + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 | |
| 493 | + >; | |
| 494 | + }; | |
| 495 | + | |
| 496 | + pinctrl_usdhc2: usdhc2grp { | |
| 497 | + fsl,pins = < | |
| 498 | + /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ | |
| 499 | + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 | |
| 500 | + /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ | |
| 501 | + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 | |
| 502 | + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 | |
| 503 | + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 | |
| 504 | + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 | |
| 505 | + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 | |
| 506 | + | |
| 507 | + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ | |
| 508 | + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ | |
| 509 | + >; | |
| 510 | + }; | |
| 511 | + | |
| 512 | + pinctrl_usbotg: usbotggrp { | |
| 513 | + fsl,pins = < | |
| 514 | + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 | |
| 515 | + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 | |
| 516 | + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 | |
| 517 | + >; | |
| 518 | + }; | |
| 519 | + | |
| 520 | + pinctrl_wdog1: wdog1grp { | |
| 521 | + fsl,pins = < | |
| 522 | + /* Watchdog out */ | |
| 523 | + MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 | |
| 524 | + >; | |
| 525 | + }; | |
| 526 | +}; | |
| @@ -0,0 +1,36 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + aliases { | |
| 11 | + rtc0 = &rtc0; | |
| 12 | + }; | |
| 13 | +}; | |
| 14 | + | |
| 15 | +&fec { | |
| 16 | + pinctrl-names = "default"; | |
| 17 | + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +&i2c1 { | |
| 21 | + lm75: temperature-sensor@49 { | |
| 22 | + compatible = "national,lm75"; | |
| 23 | + reg = <0x49>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + m24c64_57: eeprom@57 { | |
| 27 | + compatible = "atmel,24c64"; | |
| 28 | + reg = <0x57>; | |
| 29 | + pagesize = <32>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + rtc0: rtc@68 { | |
| 33 | + compatible = "dallas,ds1339"; | |
| 34 | + reg = <0x68>; | |
| 35 | + }; | |
| 36 | +}; | |
| @@ -0,0 +1,52 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2013 Sascha Hauer, Pengutronix | |
| 4 | + * | |
| 5 | + * Copyright 2013-2021 TQ-Systems GmbH | |
| 6 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + aliases { | |
| 11 | + rtc0 = &rtc0; | |
| 12 | + }; | |
| 13 | +}; | |
| 14 | + | |
| 15 | +&fec { | |
| 16 | + pinctrl-names = "default"; | |
| 17 | + pinctrl-0 = <&pinctrl_enet>; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +&i2c1 { | |
| 21 | + clock-frequency = <100000>; | |
| 22 | + pinctrl-names = "default"; | |
| 23 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 24 | + status = "okay"; | |
| 25 | +}; | |
| 26 | + | |
| 27 | +&i2c3 { | |
| 28 | + lm75: temperature-sensor@49 { | |
| 29 | + compatible = "national,lm75"; | |
| 30 | + reg = <0x49>; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + m24c64_57: eeprom@57 { | |
| 34 | + compatible = "atmel,24c64"; | |
| 35 | + reg = <0x57>; | |
| 36 | + pagesize = <32>; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + rtc0: rtc@68 { | |
| 40 | + compatible = "dallas,ds1339"; | |
| 41 | + reg = <0x68>; | |
| 42 | + }; | |
| 43 | +}; | |
| 44 | + | |
| 45 | +&iomuxc { | |
| 46 | + pinctrl_i2c1: i2c1grp { | |
| 47 | + fsl,pins = < | |
| 48 | + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 | |
| 49 | + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 | |
| 50 | + >; | |
| 51 | + }; | |
| 52 | +}; | |
| @@ -0,0 +1,119 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2018 PHYTEC Messtechnik | |
| 4 | + * Author: Christian Hemp <c.hemp@phytec.de> | |
| 5 | + */ | |
| 6 | + | |
| 7 | +/ { | |
| 8 | + display: display0 { | |
| 9 | + #address-cells = <1>; | |
| 10 | + #size-cells = <0>; | |
| 11 | + compatible = "fsl,imx-parallel-display"; | |
| 12 | + pinctrl-names = "default"; | |
| 13 | + pinctrl-0 = <&pinctrl_disp0>; | |
| 14 | + interface-pix-fmt = "rgb24"; | |
| 15 | + status = "disabled"; | |
| 16 | + | |
| 17 | + port@0 { | |
| 18 | + reg = <0>; | |
| 19 | + | |
| 20 | + display0_in: endpoint { | |
| 21 | + remote-endpoint = <&ipu1_di0_disp0>; | |
| 22 | + }; | |
| 23 | + }; | |
| 24 | + | |
| 25 | + port@1 { | |
| 26 | + reg = <1>; | |
| 27 | + | |
| 28 | + display0_out: endpoint { | |
| 29 | + remote-endpoint = <&peb_panel_lcd_in>; | |
| 30 | + }; | |
| 31 | + }; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + panel-lcd { | |
| 35 | + compatible = "edt,etm0700g0edh6"; | |
| 36 | + pinctrl-names = "default"; | |
| 37 | + pinctrl-0 = <&pinctrl_disp0_pwr>; | |
| 38 | + power-supply = <®_display>; | |
| 39 | + enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; | |
| 40 | + backlight = <&backlight>; | |
| 41 | + status = "disabled"; | |
| 42 | + | |
| 43 | + port { | |
| 44 | + peb_panel_lcd_in: endpoint { | |
| 45 | + remote-endpoint = <&display0_out>; | |
| 46 | + }; | |
| 47 | + }; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + reg_display: regulator-peb-display { | |
| 51 | + compatible = "regulator-fixed"; | |
| 52 | + regulator-name = "peb-display"; | |
| 53 | + regulator-min-microvolt = <3300000>; | |
| 54 | + regulator-max-microvolt = <3300000>; | |
| 55 | + }; | |
| 56 | +}; | |
| 57 | + | |
| 58 | +&i2c1 { | |
| 59 | + edt_ft5x06: touchscreen@38 { | |
| 60 | + compatible = "edt,edt-ft5406"; | |
| 61 | + pinctrl-names = "default"; | |
| 62 | + pinctrl-0 = <&pinctrl_edt_ft5x06>; | |
| 63 | + reg = <0x38>; | |
| 64 | + interrupt-parent = <&gpio3>; | |
| 65 | + interrupts = <2 IRQ_TYPE_NONE>; | |
| 66 | + status = "disabled"; | |
| 67 | + }; | |
| 68 | +}; | |
| 69 | + | |
| 70 | +&ipu1_di0_disp0 { | |
| 71 | + remote-endpoint = <&display0_in>; | |
| 72 | +}; | |
| 73 | + | |
| 74 | +&iomuxc { | |
| 75 | + pinctrl_disp0: disp0grp { | |
| 76 | + fsl,pins = < | |
| 77 | + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 | |
| 78 | + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 | |
| 79 | + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 | |
| 80 | + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 | |
| 81 | + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 | |
| 82 | + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 | |
| 83 | + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 | |
| 84 | + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 | |
| 85 | + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 | |
| 86 | + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 | |
| 87 | + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 | |
| 88 | + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 | |
| 89 | + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 | |
| 90 | + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 | |
| 91 | + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 | |
| 92 | + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 | |
| 93 | + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 | |
| 94 | + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 | |
| 95 | + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 | |
| 96 | + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 | |
| 97 | + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 | |
| 98 | + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 | |
| 99 | + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 | |
| 100 | + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 | |
| 101 | + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 | |
| 102 | + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 | |
| 103 | + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 | |
| 104 | + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 | |
| 105 | + >; | |
| 106 | + }; | |
| 107 | + | |
| 108 | + pinctrl_disp0_pwr: disp0pwrgrp { | |
| 109 | + fsl,pins = < | |
| 110 | + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 | |
| 111 | + >; | |
| 112 | + }; | |
| 113 | + | |
| 114 | + pinctrl_edt_ft5x06: edtft5x06grp { | |
| 115 | + fsl,pins = < | |
| 116 | + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 | |
| 117 | + >; | |
| 118 | + }; | |
| 119 | +}; | |
| @@ -0,0 +1,71 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2018 PHYTEC Messtechnik | |
| 4 | + * Author: Christian Hemp <c.hemp@phytec.de> | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include <dt-bindings/input/input.h> | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + gpio-keys { | |
| 11 | + compatible = "gpio-keys"; | |
| 12 | + pinctrl-names = "default"; | |
| 13 | + pinctrl-0 = <&pinctrl_gpio_keys>; | |
| 14 | + status = "disabled"; | |
| 15 | + | |
| 16 | + power { | |
| 17 | + label = "Power Button"; | |
| 18 | + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; | |
| 19 | + linux,code = <KEY_WAKEUP>; | |
| 20 | + wakeup-source; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + sleep { | |
| 24 | + label = "Sleep Button"; | |
| 25 | + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; | |
| 26 | + linux,code = <KEY_SLEEP>; | |
| 27 | + }; | |
| 28 | + }; | |
| 29 | + | |
| 30 | + user_leds: user-leds { | |
| 31 | + compatible = "gpio-leds"; | |
| 32 | + pinctrl-names = "default"; | |
| 33 | + pinctrl-0 = <&pinctrl_user_leds>; | |
| 34 | + status = "disabled"; | |
| 35 | + | |
| 36 | + user-led1 { | |
| 37 | + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; | |
| 38 | + linux,default-trigger = "gpio"; | |
| 39 | + default-state = "on"; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + user-led2 { | |
| 43 | + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; | |
| 44 | + linux,default-trigger = "gpio"; | |
| 45 | + default-state = "on"; | |
| 46 | + }; | |
| 47 | + | |
| 48 | + user-led3 { | |
| 49 | + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; | |
| 50 | + linux,default-trigger = "gpio"; | |
| 51 | + default-state = "on"; | |
| 52 | + }; | |
| 53 | + }; | |
| 54 | +}; | |
| 55 | + | |
| 56 | +&iomuxc { | |
| 57 | + pinctrl_gpio_keys: gpiokeysgrp { | |
| 58 | + fsl,pins = < | |
| 59 | + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 | |
| 60 | + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 | |
| 61 | + >; | |
| 62 | + }; | |
| 63 | + | |
| 64 | + pinctrl_user_leds: userledsgrp { | |
| 65 | + fsl,pins = < | |
| 66 | + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 | |
| 67 | + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 | |
| 68 | + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 | |
| 69 | + >; | |
| 70 | + }; | |
| 71 | +}; | |
| @@ -0,0 +1,85 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2021 PHYTEC Messtechnik GmbH | |
| 4 | + * Author: Yunus Bas <y.bas@phytec.de> | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include <dt-bindings/gpio/gpio.h> | |
| 8 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + reg_wl_en: regulator-wl-en { | |
| 12 | + compatible = "regulator-fixed"; | |
| 13 | + regulator-name = "wlan_en"; | |
| 14 | + regulator-min-microvolt = <3300000>; | |
| 15 | + regulator-max-microvolt = <3300000>; | |
| 16 | + pinctrl-names = "default"; | |
| 17 | + pinctrl-0 = <&pinctrl_wl>; | |
| 18 | + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; | |
| 19 | + enable-active-high; | |
| 20 | + startup-delay-us = <100>; | |
| 21 | + status = "disabled"; | |
| 22 | + }; | |
| 23 | +}; | |
| 24 | + | |
| 25 | +&uart3 { | |
| 26 | + pinctrl-names = "default"; | |
| 27 | + pinctrl-0 = <&pinctrl_uart3_bt>; | |
| 28 | + uart-has-rtscts; | |
| 29 | + | |
| 30 | + bluetooth { | |
| 31 | + compatible = "brcm,bcm43438-bt"; | |
| 32 | + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; | |
| 33 | + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; | |
| 34 | + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; | |
| 35 | + status = "disabled"; | |
| 36 | + }; | |
| 37 | +}; | |
| 38 | + | |
| 39 | +&usdhc3 { | |
| 40 | + #address-cells = <1>; | |
| 41 | + #size-cells = <0>; | |
| 42 | + pinctrl-names = "default"; | |
| 43 | + pinctrl-0 = <&pinctrl_usdhc3_wl>; | |
| 44 | + vmmc-supply = <®_wl_en>; | |
| 45 | + bus-width = <4>; | |
| 46 | + non-removable; | |
| 47 | + no-1-8-v; | |
| 48 | + status = "disabled"; | |
| 49 | + | |
| 50 | + brmcf: wifi@1 { | |
| 51 | + compatible = "brcm,bcm4329-fmac"; | |
| 52 | + reg = <1>; | |
| 53 | + }; | |
| 54 | +}; | |
| 55 | + | |
| 56 | +&iomuxc { | |
| 57 | + pinctrl_uart3_bt: uart3grp-bt { | |
| 58 | + fsl,pins = < | |
| 59 | + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | |
| 60 | + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | |
| 61 | + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | |
| 62 | + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 | |
| 63 | + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */ | |
| 64 | + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */ | |
| 65 | + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */ | |
| 66 | + >; | |
| 67 | + }; | |
| 68 | + | |
| 69 | + pinctrl_usdhc3_wl: usdhc3grp-wl { | |
| 70 | + fsl,pins = < | |
| 71 | + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
| 72 | + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
| 73 | + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
| 74 | + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
| 75 | + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
| 76 | + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
| 77 | + >; | |
| 78 | + }; | |
| 79 | + | |
| 80 | + pinctrl_wl: wlgrp { | |
| 81 | + fsl,pins = < | |
| 82 | + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */ | |
| 83 | + >; | |
| 84 | + }; | |
| 85 | +}; | |
| @@ -4,6 +4,12 @@ · 3 unmodified lines | ||
| 4 | 4 | * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> |
| 5 | 5 | */ |
| 6 | 6 | |
| 7 | +&fec { | |
| 8 | + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, | |
| 9 | + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
| 10 | + fsl,err006687-workaround-present; | |
| 11 | +}; | |
| 12 | + | |
| 7 | 13 | &i2c1 { |
| 8 | 14 | pinctrl-names = "default"; |
| 9 | 15 | pinctrl-0 = <&pinctrl_i2c1>; |
| @@ -26,3 +32,17 @@ · 16 unmodified lines | ||
| 26 | 32 | pagesize = <32>; |
| 27 | 33 | }; |
| 28 | 34 | }; |
| 35 | + | |
| 36 | +&iomuxc { | |
| 37 | + /* | |
| 38 | + * This pinmuxing is required for the ERR006687 workaround. Board | |
| 39 | + * DTS files that enable the FEC controller with | |
| 40 | + * fsl,err006687-workaround-present must include this group. | |
| 41 | + */ | |
| 42 | + pinctrl_enet_fix: enetfixgrp { | |
| 43 | + fsl,pins = < | |
| 44 | + /* ENET ping patch */ | |
| 45 | + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 | |
| 46 | + >; | |
| 47 | + }; | |
| 48 | +}; | |
| @@ -259,18 +259,6 @@ · 258 unmodified lines | ||
| 259 | 259 | &gpio3 19 GPIO_ACTIVE_HIGH |
| 260 | 260 | >; |
| 261 | 261 | status = "disabled"; |
| 262 | − | |
| 263 | − spidev0: spi@0 { | |
| 264 | − compatible = "spidev"; | |
| 265 | − reg = <0>; | |
| 266 | − spi-max-frequency = <54000000>; | |
| 267 | − }; | |
| 268 | − | |
| 269 | − spidev1: spi@1 { | |
| 270 | − compatible = "spidev"; | |
| 271 | − reg = <1>; | |
| 272 | − spi-max-frequency = <54000000>; | |
| 273 | − }; | |
| 274 | 262 | }; |
| 275 | 263 | |
| 276 | 264 | &fec { |
| @@ -55,19 +55,19 @@ · 54 unmodified lines | ||
| 55 | 55 | |
| 56 | 56 | clocks { |
| 57 | 57 | ckil { |
| 58 | − compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 58 | + compatible = "fixed-clock"; | |
| 59 | 59 | #clock-cells = <0>; |
| 60 | 60 | clock-frequency = <32768>; |
| 61 | 61 | }; |
| 62 | 62 | |
| 63 | 63 | ckih1 { |
| 64 | − compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 64 | + compatible = "fixed-clock"; | |
| 65 | 65 | #clock-cells = <0>; |
| 66 | 66 | clock-frequency = <0>; |
| 67 | 67 | }; |
| 68 | 68 | |
| 69 | 69 | osc { |
| 70 | − compatible = "fsl,imx-osc", "fixed-clock"; | |
| 70 | + compatible = "fixed-clock"; | |
| 71 | 71 | #clock-cells = <0>; |
| 72 | 72 | clock-frequency = <24000000>; |
| 73 | 73 | }; |
| @@ -481,7 +481,7 @@ · 407 unmodified lines | ||
| 481 | 481 | status = "okay"; |
| 482 | 482 | }; |
| 483 | 483 | |
| 484 | − spba@203c000 { | |
| 484 | + spba-bus@203c000 { | |
| 485 | 485 | reg = <0x0203c000 0x4000>; |
| 486 | 486 | }; |
| 487 | 487 | }; |
| @@ -0,0 +1,18 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +/* | |
| 3 | + * Copyright 2015-2021 TQ-Systems GmbH | |
| 4 | + * Author: Markus Niebel <Markus.Niebel@tq-group.com> | |
| 5 | + */ | |
| 6 | +/dts-v1/; | |
| 7 | + | |
| 8 | +#include <dt-bindings/gpio/gpio.h> | |
| 9 | +#include "imx6qp-tqma6b.dtsi" | |
| 10 | +#include "imx6qdl-mba6.dtsi" | |
| 11 | +#include "imx6qdl-mba6b.dtsi" | |
| 12 | +#include "imx6q-mba6.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + model = "TQ TQMa6QP on MBa6x"; | |
| 16 | + compatible = "tq,imx6qp-mba6x-b", "tq,mba6b", | |
| 17 | + "tq,imx6qp-tqma6qp-b", "fsl,imx6qp"; | |
| 18 | +}; | |
| @@ -8,6 +8,9 @@ · 7 unmodified lines | ||
| 8 | 8 | #include "imx6qp.dtsi" |
| 9 | 9 | #include "imx6qdl-phytec-phycore-som.dtsi" |
| 10 | 10 | #include "imx6qdl-phytec-mira.dtsi" |
| 11 | +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" | |
| 12 | +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" | |
| 13 | +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" | |
| 11 | 14 | |
| 12 | 15 | / { |
| 13 | 16 | model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; |
| @@ -0,0 +1,54 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0 | |
| 2 | +// | |
| 3 | +// Copyright (C) 2021 Y Soft Corporation, a.s. | |
| 4 | + | |
| 5 | +/dts-v1/; | |
| 6 | + | |
| 7 | +#include "imx6qp.dtsi" | |
| 8 | +#include "imx6dl-yapp4-common.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + model = "Y Soft IOTA Crux+ i.MX6QuadPlus board"; | |
| 12 | + compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp"; | |
| 13 | + | |
| 14 | + memory@10000000 { | |
| 15 | + device_type = "memory"; | |
| 16 | + reg = <0x10000000 0xf0000000>; | |
| 17 | + }; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +&gpio_oled { | |
| 21 | + status = "okay"; | |
| 22 | +}; | |
| 23 | + | |
| 24 | +&leds { | |
| 25 | + status = "okay"; | |
| 26 | +}; | |
| 27 | + | |
| 28 | +&oled_1305 { | |
| 29 | + status = "okay"; | |
| 30 | +}; | |
| 31 | + | |
| 32 | +&oled_1309 { | |
| 33 | + status = "okay"; | |
| 34 | +}; | |
| 35 | + | |
| 36 | +®_usb_h1_vbus { | |
| 37 | + status = "okay"; | |
| 38 | +}; | |
| 39 | + | |
| 40 | +&touchkeys { | |
| 41 | + status = "okay"; | |
| 42 | +}; | |
| 43 | + | |
| 44 | +&uart2 { | |
| 45 | + status = "disabled"; | |
| 46 | +}; | |
| 47 | + | |
| 48 | +&usbh1 { | |
| 49 | + status = "okay"; | |
| 50 | +}; | |
| 51 | + | |
| 52 | +&usbphy2 { | |
| 53 | + status = "okay"; | |
| 54 | +}; | |
| @@ -114,18 +114,6 @@ · 113 unmodified lines | ||
| 114 | 114 | pinctrl-0 = <&pinctrl_ecspi4>; |
| 115 | 115 | cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; |
| 116 | 116 | status = "okay"; |
| 117 | − | |
| 118 | − spidev0: spi@0 { | |
| 119 | − compatible = "spidev"; | |
| 120 | − reg = <0>; | |
| 121 | − spi-max-frequency = <5000000>; | |
| 122 | − }; | |
| 123 | − | |
| 124 | − spidev1: spi@1 { | |
| 125 | − compatible = "spidev"; | |
| 126 | − reg = <1>; | |
| 127 | − spi-max-frequency = <5000000>; | |
| 128 | − }; | |
| 129 | 117 | }; |
| 130 | 118 | |
| 131 | 119 | &i2c1 { |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include "imx6ul-phytec-segin.dtsi" |
| 11 | 11 | #include "imx6ul-phytec-segin-peb-eval-01.dtsi" |
| 12 | 12 | #include "imx6ul-phytec-segin-peb-av-02.dtsi" |
| 13 | +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" | |
| 13 | 14 | |
| 14 | 15 | / { |
| 15 | 16 | model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; |
| @@ -0,0 +1,90 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2021 PHYTEC Messtechnik GmbH | |
| 4 | + * Author: Yunus Bas <y.bas@phytec.de> | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include <dt-bindings/gpio/gpio.h> | |
| 8 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + reg_wl_en: regulator-wl-en { | |
| 12 | + compatible = "regulator-fixed"; | |
| 13 | + regulator-name = "wlan_en"; | |
| 14 | + regulator-min-microvolt = <3300000>; | |
| 15 | + regulator-max-microvolt = <3300000>; | |
| 16 | + pinctrl-names = "default"; | |
| 17 | + pinctrl-0 = <&pinctrl_wl>; | |
| 18 | + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; | |
| 19 | + enable-active-high; | |
| 20 | + startup-delay-us = <100>; | |
| 21 | + status = "disabled"; | |
| 22 | + }; | |
| 23 | +}; | |
| 24 | + | |
| 25 | +&iomuxc { | |
| 26 | + pinctrl_bt: btgrp { | |
| 27 | + fsl,pins = < | |
| 28 | + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */ | |
| 29 | + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */ | |
| 30 | + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */ | |
| 31 | + >; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + pinctrl_uart2_bt: uart2grp-bt { | |
| 35 | + fsl,pins = < | |
| 36 | + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059 | |
| 37 | + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059 | |
| 38 | + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059 | |
| 39 | + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059 | |
| 40 | + >; | |
| 41 | + }; | |
| 42 | + | |
| 43 | + pinctrl_usdhc2_wl: usdhc2grp-wl { | |
| 44 | + fsl,pins = < | |
| 45 | + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051 | |
| 46 | + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061 | |
| 47 | + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051 | |
| 48 | + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051 | |
| 49 | + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051 | |
| 50 | + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051 | |
| 51 | + >; | |
| 52 | + }; | |
| 53 | + | |
| 54 | + pinctrl_wl: wlgrp { | |
| 55 | + fsl,pins = < | |
| 56 | + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */ | |
| 57 | + >; | |
| 58 | + }; | |
| 59 | +}; | |
| 60 | + | |
| 61 | +&uart2 { | |
| 62 | + pinctrl-names = "default"; | |
| 63 | + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>; | |
| 64 | + uart-has-rtscts; | |
| 65 | + status = "disabled"; | |
| 66 | + | |
| 67 | + bluetooth { | |
| 68 | + compatible = "brcm,bcm43438-bt"; | |
| 69 | + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; | |
| 70 | + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; | |
| 71 | + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; | |
| 72 | + }; | |
| 73 | +}; | |
| 74 | + | |
| 75 | +&usdhc2 { | |
| 76 | + #address-cells = <1>; | |
| 77 | + #size-cells = <0>; | |
| 78 | + pinctrl-names = "default"; | |
| 79 | + pinctrl-0 = <&pinctrl_usdhc2_wl>; | |
| 80 | + vmmc-supply = <®_wl_en>; | |
| 81 | + bus-width = <4>; | |
| 82 | + non-removable; | |
| 83 | + no-1-8-v; | |
| 84 | + status = "disabled"; | |
| 85 | + | |
| 86 | + brmcf: wifi@1 { | |
| 87 | + compatible = "brcm,bcm4329-fmac"; | |
| 88 | + reg = <1>; | |
| 89 | + }; | |
| 90 | +}; | |
| @@ -78,12 +78,6 @@ · 77 unmodified lines | ||
| 78 | 78 | pinctrl-names = "default"; |
| 79 | 79 | pinctrl-0 = <&pinctrl_ecspi2>; |
| 80 | 80 | status = "okay"; |
| 81 | − | |
| 82 | − spi@0 { | |
| 83 | − compatible = "spidev"; | |
| 84 | − reg = <0>; | |
| 85 | − spi-max-frequency = <1000000>; | |
| 86 | − }; | |
| 87 | 81 | }; |
| 88 | 82 | |
| 89 | 83 | &fec1 { |
| @@ -227,18 +227,6 @@ · 226 unmodified lines | ||
| 227 | 227 | &gpio1 10 GPIO_ACTIVE_HIGH |
| 228 | 228 | >; |
| 229 | 229 | status = "disabled"; |
| 230 | − | |
| 231 | − spi@0 { | |
| 232 | − compatible = "spidev"; | |
| 233 | − reg = <0>; | |
| 234 | − spi-max-frequency = <660000>; | |
| 235 | − }; | |
| 236 | − | |
| 237 | − spi@1 { | |
| 238 | − compatible = "spidev"; | |
| 239 | − reg = <1>; | |
| 240 | − spi-max-frequency = <660000>; | |
| 241 | − }; | |
| 242 | 230 | }; |
| 243 | 231 | |
| 244 | 232 | sound { |
| @@ -290,18 +278,6 @@ · 45 unmodified lines | ||
| 290 | 278 | &gpio1 10 GPIO_ACTIVE_HIGH |
| 291 | 279 | >; |
| 292 | 280 | status = "disabled"; |
| 293 | − | |
| 294 | − spidev0: spi@0 { | |
| 295 | − compatible = "spidev"; | |
| 296 | − reg = <0>; | |
| 297 | − spi-max-frequency = <60000000>; | |
| 298 | − }; | |
| 299 | − | |
| 300 | − spidev1: spi@1 { | |
| 301 | − compatible = "spidev"; | |
| 302 | − reg = <1>; | |
| 303 | − spi-max-frequency = <60000000>; | |
| 304 | − }; | |
| 305 | 281 | }; |
| 306 | 282 | |
| 307 | 283 | &fec1 { |
| @@ -0,0 +1,456 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT | |
| 2 | +/* | |
| 3 | + * Copyright (c) 2020 Protonic Holland | |
| 4 | + * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix | |
| 5 | + */ | |
| 6 | + | |
| 7 | +/dts-v1/; | |
| 8 | + | |
| 9 | +#include <dt-bindings/gpio/gpio.h> | |
| 10 | +#include <dt-bindings/leds/common.h> | |
| 11 | +#include "imx6ull.dtsi" | |
| 12 | + | |
| 13 | +/ { | |
| 14 | + model = "JOZ Access Point"; | |
| 15 | + compatible = "joz,jozacp", "fsl,imx6ull"; | |
| 16 | + | |
| 17 | + chosen { | |
| 18 | + stdout-path = &uart1; | |
| 19 | + }; | |
| 20 | + | |
| 21 | + /* On board name LED_RGB1 */ | |
| 22 | + led-controller-1 { | |
| 23 | + compatible = "pwm-leds"; | |
| 24 | + | |
| 25 | + led-0 { | |
| 26 | + color = <LED_COLOR_ID_RED>; | |
| 27 | + function = LED_FUNCTION_INDICATOR; | |
| 28 | + function-enumerator = <0>; | |
| 29 | + pwms = <&pwm1 0 10000000 0>; | |
| 30 | + max-brightness = <255>; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + led-1 { | |
| 34 | + color = <LED_COLOR_ID_GREEN>; | |
| 35 | + function = LED_FUNCTION_INDICATOR; | |
| 36 | + function-enumerator = <1>; | |
| 37 | + pwms = <&pwm3 0 10000000 0>; | |
| 38 | + max-brightness = <255>; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + led-2 { | |
| 42 | + color = <LED_COLOR_ID_BLUE>; | |
| 43 | + function = LED_FUNCTION_INDICATOR; | |
| 44 | + function-enumerator = <2>; | |
| 45 | + pwms = <&pwm5 0 10000000 0>; | |
| 46 | + max-brightness = <255>; | |
| 47 | + linux,default-trigger = "heartbeat"; | |
| 48 | + }; | |
| 49 | + }; | |
| 50 | + | |
| 51 | + /* On board name LED_RGB2 */ | |
| 52 | + led-controller-2 { | |
| 53 | + compatible = "pwm-leds"; | |
| 54 | + | |
| 55 | + led-3 { | |
| 56 | + color = <LED_COLOR_ID_RED>; | |
| 57 | + function = LED_FUNCTION_INDICATOR; | |
| 58 | + function-enumerator = <3>; | |
| 59 | + pwms = <&pwm2 0 10000000 0>; | |
| 60 | + max-brightness = <255>; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + led-4 { | |
| 64 | + color = <LED_COLOR_ID_GREEN>; | |
| 65 | + function = LED_FUNCTION_INDICATOR; | |
| 66 | + function-enumerator = <4>; | |
| 67 | + pwms = <&pwm4 0 10000000 0>; | |
| 68 | + max-brightness = <255>; | |
| 69 | + }; | |
| 70 | + | |
| 71 | + led-5 { | |
| 72 | + color = <LED_COLOR_ID_BLUE>; | |
| 73 | + function = LED_FUNCTION_INDICATOR; | |
| 74 | + function-enumerator = <5>; | |
| 75 | + pwms = <&pwm6 0 10000000 0>; | |
| 76 | + max-brightness = <255>; | |
| 77 | + }; | |
| 78 | + }; | |
| 79 | + | |
| 80 | + reg_3v3: regulator-3v3 { | |
| 81 | + compatible = "regulator-fixed"; | |
| 82 | + regulator-name = "3v3"; | |
| 83 | + regulator-min-microvolt = <3300000>; | |
| 84 | + regulator-max-microvolt = <3300000>; | |
| 85 | + vin-supply = <®_5v0>; | |
| 86 | + }; | |
| 87 | + | |
| 88 | + reg_5v0: regulator-5v0 { | |
| 89 | + compatible = "regulator-fixed"; | |
| 90 | + regulator-name = "5v0"; | |
| 91 | + regulator-min-microvolt = <5000000>; | |
| 92 | + regulator-max-microvolt = <5000000>; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + reg_vbus: regulator-vbus { | |
| 96 | + compatible = "regulator-fixed"; | |
| 97 | + pinctrl-names = "default"; | |
| 98 | + pinctrl-0 = <&pinctrl_vbus>; | |
| 99 | + regulator-name = "vbus"; | |
| 100 | + regulator-min-microvolt = <5000000>; | |
| 101 | + regulator-max-microvolt = <5000000>; | |
| 102 | + vin-supply = <®_5v0>; | |
| 103 | + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; | |
| 104 | + enable-active-high; | |
| 105 | + }; | |
| 106 | + | |
| 107 | + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { | |
| 108 | + compatible = "mmc-pwrseq-simple"; | |
| 109 | + pinctrl-names = "default"; | |
| 110 | + pinctrl-0 = <&pinctrl_wifi_npd>; | |
| 111 | + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; | |
| 112 | + }; | |
| 113 | +}; | |
| 114 | + | |
| 115 | +&can1 { | |
| 116 | + pinctrl-names = "default"; | |
| 117 | + pinctrl-0 = <&pinctrl_can1>; | |
| 118 | + status = "okay"; | |
| 119 | +}; | |
| 120 | + | |
| 121 | +&cpu0 { | |
| 122 | + clock-frequency = <792000000>; | |
| 123 | +}; | |
| 124 | + | |
| 125 | +&fec1 { | |
| 126 | + pinctrl-names = "default"; | |
| 127 | + pinctrl-0 = <&pinctrl_enet1>; | |
| 128 | + phy-mode = "rmii"; | |
| 129 | + phy-handle = <ðphy0>; | |
| 130 | + status = "okay"; | |
| 131 | + | |
| 132 | + mdio { | |
| 133 | + #address-cells = <1>; | |
| 134 | + #size-cells = <0>; | |
| 135 | + | |
| 136 | + ethphy0: ethernet-phy@0 { | |
| 137 | + reg = <0>; | |
| 138 | + clocks = <&clks IMX6UL_CLK_ENET_REF>; | |
| 139 | + clock-names = "rmii-ref"; | |
| 140 | + interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>; | |
| 141 | + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; | |
| 142 | + reset-assert-us = <10000>; | |
| 143 | + reset-deassert-us = <300>; | |
| 144 | + }; | |
| 145 | + }; | |
| 146 | +}; | |
| 147 | + | |
| 148 | +&i2c1 { | |
| 149 | + pinctrl-names = "default"; | |
| 150 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 151 | + clock-frequency = <100000>; | |
| 152 | + status = "okay"; | |
| 153 | +}; | |
| 154 | + | |
| 155 | +&i2c2 { | |
| 156 | + pinctrl-names = "default"; | |
| 157 | + pinctrl-0 = <&pinctrl_i2c2>; | |
| 158 | + clock-frequency = <100000>; | |
| 159 | + status = "okay"; | |
| 160 | + | |
| 161 | + rtc@51 { | |
| 162 | + compatible = "nxp,pcf8563"; | |
| 163 | + reg = <0x51>; | |
| 164 | + }; | |
| 165 | +}; | |
| 166 | + | |
| 167 | +&pwm1 { | |
| 168 | + pinctrl-names = "default"; | |
| 169 | + pinctrl-0 = <&pinctrl_pwm1>; | |
| 170 | + status = "okay"; | |
| 171 | +}; | |
| 172 | + | |
| 173 | +&pwm2 { | |
| 174 | + pinctrl-names = "default"; | |
| 175 | + pinctrl-0 = <&pinctrl_pwm2>; | |
| 176 | + status = "okay"; | |
| 177 | +}; | |
| 178 | + | |
| 179 | +&pwm3 { | |
| 180 | + pinctrl-names = "default"; | |
| 181 | + pinctrl-0 = <&pinctrl_pwm3>; | |
| 182 | + status = "okay"; | |
| 183 | +}; | |
| 184 | + | |
| 185 | +&pwm4 { | |
| 186 | + pinctrl-names = "default"; | |
| 187 | + pinctrl-0 = <&pinctrl_pwm4>; | |
| 188 | + status = "okay"; | |
| 189 | +}; | |
| 190 | + | |
| 191 | +&pwm5 { | |
| 192 | + pinctrl-names = "default"; | |
| 193 | + pinctrl-0 = <&pinctrl_pwm5>; | |
| 194 | + status = "okay"; | |
| 195 | +}; | |
| 196 | + | |
| 197 | +&pwm6 { | |
| 198 | + pinctrl-names = "default"; | |
| 199 | + pinctrl-0 = <&pinctrl_pwm6>; | |
| 200 | + status = "okay"; | |
| 201 | +}; | |
| 202 | + | |
| 203 | +&snvs_rtc { | |
| 204 | + status = "disabled"; | |
| 205 | +}; | |
| 206 | + | |
| 207 | +&uart1 { | |
| 208 | + pinctrl-names = "default"; | |
| 209 | + pinctrl-0 = <&pinctrl_uart1>; | |
| 210 | + status = "okay"; | |
| 211 | +}; | |
| 212 | + | |
| 213 | +&uart4 { | |
| 214 | + pinctrl-names = "default"; | |
| 215 | + pinctrl-0 = <&pinctrl_uart4>; | |
| 216 | + dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; | |
| 217 | + uart-has-rtscts; | |
| 218 | + status = "okay"; | |
| 219 | +}; | |
| 220 | + | |
| 221 | +&usbotg1 { | |
| 222 | + pinctrl-names = "default"; | |
| 223 | + pinctrl-0 = <&pinctrl_usbotg1>; | |
| 224 | + vbus-supply = <®_vbus>; | |
| 225 | + dr_mode = "host"; | |
| 226 | + over-current-active-low; | |
| 227 | + status = "okay"; | |
| 228 | +}; | |
| 229 | + | |
| 230 | +&usdhc1 { | |
| 231 | + pinctrl-names = "default"; | |
| 232 | + pinctrl-0 = <&pinctrl_usdhc1>; | |
| 233 | + vmmc-supply = <®_3v3>; | |
| 234 | + bus-width = <8>; | |
| 235 | + no-1-8-v; | |
| 236 | + non-removable; | |
| 237 | + cap-mmc-hw-reset; | |
| 238 | + no-sd; | |
| 239 | + no-sdio; | |
| 240 | + status = "okay"; | |
| 241 | +}; | |
| 242 | + | |
| 243 | +&usdhc2 { | |
| 244 | + pinctrl-names = "default"; | |
| 245 | + pinctrl-0 = <&pinctrl_usdhc2>; | |
| 246 | + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; | |
| 247 | + bus-width = <4>; | |
| 248 | + no-1-8-v; | |
| 249 | + no-mmc; | |
| 250 | + no-sd; | |
| 251 | + non-removable; | |
| 252 | + #address-cells = <1>; | |
| 253 | + #size-cells = <0>; | |
| 254 | + status = "okay"; | |
| 255 | + | |
| 256 | + wifi@1 { | |
| 257 | + compatible = "brcm,bcm4329-fmac"; | |
| 258 | + reg = <1>; | |
| 259 | + }; | |
| 260 | +}; | |
| 261 | + | |
| 262 | +&iomuxc { | |
| 263 | + pinctrl-names = "default"; | |
| 264 | + pinctrl-0 = <&pinctrl_hog>; | |
| 265 | + | |
| 266 | + pinctrl_can1: can1grp { | |
| 267 | + fsl,pins = < | |
| 268 | + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 | |
| 269 | + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 | |
| 270 | + >; | |
| 271 | + }; | |
| 272 | + | |
| 273 | + pinctrl_enet1: enet1grp { | |
| 274 | + fsl,pins = < | |
| 275 | + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 | |
| 276 | + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 | |
| 277 | + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 | |
| 278 | + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 | |
| 279 | + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 | |
| 280 | + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 | |
| 281 | + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 | |
| 282 | + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 | |
| 283 | + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 | |
| 284 | + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 | |
| 285 | + | |
| 286 | + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0 | |
| 287 | + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0 | |
| 288 | + >; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + pinctrl_hog: hoggrp { | |
| 292 | + fsl,pins = < | |
| 293 | + /* HW Revision */ | |
| 294 | + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 | |
| 295 | + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 | |
| 296 | + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 | |
| 297 | + | |
| 298 | + /* HW ID */ | |
| 299 | + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 | |
| 300 | + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 | |
| 301 | + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 | |
| 302 | + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 | |
| 303 | + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 | |
| 304 | + | |
| 305 | + /* Digital inputs */ | |
| 306 | + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000 | |
| 307 | + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000 | |
| 308 | + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000 | |
| 309 | + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000 | |
| 310 | + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000 | |
| 311 | + | |
| 312 | + /* Isolated outputs */ | |
| 313 | + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020 | |
| 314 | + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020 | |
| 315 | + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020 | |
| 316 | + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020 | |
| 317 | + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020 | |
| 318 | + >; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + pinctrl_i2c1: i2c1grp { | |
| 322 | + fsl,pins = < | |
| 323 | + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1 | |
| 324 | + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1 | |
| 325 | + >; | |
| 326 | + }; | |
| 327 | + | |
| 328 | + pinctrl_i2c2: i2c2grp { | |
| 329 | + fsl,pins = < | |
| 330 | + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1 | |
| 331 | + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1 | |
| 332 | + >; | |
| 333 | + }; | |
| 334 | + | |
| 335 | + pinctrl_pwm1: pwm1grp { | |
| 336 | + fsl,pins = < | |
| 337 | + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010 | |
| 338 | + >; | |
| 339 | + }; | |
| 340 | + | |
| 341 | + pinctrl_pwm2: pwm2grp { | |
| 342 | + fsl,pins = < | |
| 343 | + MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010 | |
| 344 | + >; | |
| 345 | + }; | |
| 346 | + | |
| 347 | + pinctrl_pwm3: pwm3grp { | |
| 348 | + fsl,pins = < | |
| 349 | + MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010 | |
| 350 | + >; | |
| 351 | + }; | |
| 352 | + | |
| 353 | + pinctrl_pwm4: pwm4grp { | |
| 354 | + fsl,pins = < | |
| 355 | + MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010 | |
| 356 | + >; | |
| 357 | + }; | |
| 358 | + | |
| 359 | + pinctrl_pwm5: pwm5grp { | |
| 360 | + fsl,pins = < | |
| 361 | + MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010 | |
| 362 | + >; | |
| 363 | + }; | |
| 364 | + | |
| 365 | + pinctrl_pwm6: pwm6grp { | |
| 366 | + fsl,pins = < | |
| 367 | + MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010 | |
| 368 | + >; | |
| 369 | + }; | |
| 370 | + | |
| 371 | + pinctrl_uart1: uart1grp { | |
| 372 | + fsl,pins = < | |
| 373 | + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 | |
| 374 | + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 | |
| 375 | + >; | |
| 376 | + }; | |
| 377 | + | |
| 378 | + pinctrl_uart4: uart4grp { | |
| 379 | + fsl,pins = < | |
| 380 | + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 | |
| 381 | + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 | |
| 382 | + MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0 | |
| 383 | + MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0 | |
| 384 | + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 | |
| 385 | + >; | |
| 386 | + }; | |
| 387 | + | |
| 388 | + pinctrl_usbotg1: usbotg1grp { | |
| 389 | + fsl,pins = < | |
| 390 | + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0 | |
| 391 | + >; | |
| 392 | + }; | |
| 393 | + | |
| 394 | + pinctrl_usdhc1: usdhc1grp { | |
| 395 | + fsl,pins = < | |
| 396 | + MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099 | |
| 397 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099 | |
| 398 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099 | |
| 399 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099 | |
| 400 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099 | |
| 401 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099 | |
| 402 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099 | |
| 403 | + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099 | |
| 404 | + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099 | |
| 405 | + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099 | |
| 406 | + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099 | |
| 407 | + >; | |
| 408 | + }; | |
| 409 | + | |
| 410 | + pinctrl_usdhc2: usdhc2grp { | |
| 411 | + fsl,pins = < | |
| 412 | + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 | |
| 413 | + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 | |
| 414 | + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 | |
| 415 | + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 | |
| 416 | + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 | |
| 417 | + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 | |
| 418 | + >; | |
| 419 | + }; | |
| 420 | + | |
| 421 | + pinctrl_vbus: vbus0grp { | |
| 422 | + fsl,pins = < | |
| 423 | + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0 | |
| 424 | + >; | |
| 425 | + }; | |
| 426 | + | |
| 427 | + pinctrl_wifi_npd: wifigrp { | |
| 428 | + fsl,pins = < | |
| 429 | + /* WL_REG_ON */ | |
| 430 | + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020 | |
| 431 | + >; | |
| 432 | + }; | |
| 433 | +}; | |
| 434 | + | |
| 435 | +&iomuxc_snvs { | |
| 436 | + pinctrl-names = "default"; | |
| 437 | + pinctrl-0 = <&pinctrl_snvs_hog>; | |
| 438 | + | |
| 439 | + pinctrl_snvs_hog: snvs-hog-grp { | |
| 440 | + fsl,pins = < | |
| 441 | + /* Digital outputs */ | |
| 442 | + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020 | |
| 443 | + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020 | |
| 444 | + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020 | |
| 445 | + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020 | |
| 446 | + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020 | |
| 447 | + | |
| 448 | + /* Digital outputs fault feedback */ | |
| 449 | + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000 | |
| 450 | + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000 | |
| 451 | + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000 | |
| 452 | + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000 | |
| 453 | + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000 | |
| 454 | + >; | |
| 455 | + }; | |
| 456 | +}; | |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include "imx6ull-phytec-segin.dtsi" |
| 11 | 11 | #include "imx6ull-phytec-segin-peb-eval-01.dtsi" |
| 12 | 12 | #include "imx6ull-phytec-segin-peb-av-02.dtsi" |
| 13 | +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" | |
| 13 | 14 | |
| 14 | 15 | / { |
| 15 | 16 | model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | #include "imx6ull-phytec-phycore-som.dtsi" |
| 10 | 10 | #include "imx6ull-phytec-segin.dtsi" |
| 11 | 11 | #include "imx6ull-phytec-segin-peb-eval-01.dtsi" |
| 12 | +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" | |
| 12 | 13 | |
| 13 | 14 | / { |
| 14 | 15 | model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; |
| @@ -0,0 +1,19 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2021 PHYTEC Messtechnik GmbH | |
| 4 | + * Author: Yunus Bas <y.bas@phytec.de> | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" | |
| 8 | + | |
| 9 | +&iomuxc { | |
| 10 | + /delete-node/ wlgrp; | |
| 11 | +}; | |
| 12 | + | |
| 13 | +&iomuxc_snvs { | |
| 14 | + pinctrl_wl: wlgrp { | |
| 15 | + fsl,pins = < | |
| 16 | + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 | |
| 17 | + >; | |
| 18 | + }; | |
| 19 | +}; | |
| @@ -0,0 +1,146 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2021 BSH Hausgeraete GmbH | |
| 4 | + */ | |
| 5 | + | |
| 6 | +/dts-v1/; | |
| 7 | + | |
| 8 | +#include <dt-bindings/input/input.h> | |
| 9 | +#include "imx6ulz.dtsi" | |
| 10 | + | |
| 11 | +/ { | |
| 12 | + model = "BSH SMM M2"; | |
| 13 | + compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; | |
| 14 | + | |
| 15 | + chosen { | |
| 16 | + stdout-path = &uart4; | |
| 17 | + }; | |
| 18 | + | |
| 19 | + usdhc2_pwrseq: usdhc2-pwrseq { | |
| 20 | + compatible = "mmc-pwrseq-simple"; | |
| 21 | + reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; | |
| 22 | + }; | |
| 23 | +}; | |
| 24 | + | |
| 25 | +&gpmi { | |
| 26 | + pinctrl-names = "default"; | |
| 27 | + pinctrl-0 = <&pinctrl_gpmi_nand>; | |
| 28 | + nand-on-flash-bbt; | |
| 29 | + status = "okay"; | |
| 30 | +}; | |
| 31 | + | |
| 32 | +&uart3 { | |
| 33 | + pinctrl-names = "default"; | |
| 34 | + pinctrl-0 = <&pinctrl_uart3>; | |
| 35 | + uart-has-rtscts; | |
| 36 | + status = "okay"; | |
| 37 | + | |
| 38 | + bluetooth { | |
| 39 | + compatible = "brcm,bcm4330-bt"; | |
| 40 | + max-speed = <3000000>; | |
| 41 | + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; | |
| 42 | + device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; | |
| 43 | + host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; | |
| 44 | + }; | |
| 45 | +}; | |
| 46 | + | |
| 47 | +&uart4 { | |
| 48 | + pinctrl-names = "default"; | |
| 49 | + pinctrl-0 = <&pinctrl_uart4>; | |
| 50 | + status = "okay"; | |
| 51 | +}; | |
| 52 | + | |
| 53 | +&usbotg1 { | |
| 54 | + dr_mode = "peripheral"; | |
| 55 | + srp-disable; | |
| 56 | + hnp-disable; | |
| 57 | + adp-disable; | |
| 58 | + status = "okay"; | |
| 59 | +}; | |
| 60 | + | |
| 61 | +&usbphy1 { | |
| 62 | + fsl,tx-d-cal = <106>; | |
| 63 | +}; | |
| 64 | + | |
| 65 | +&usdhc2 { | |
| 66 | + #address-cells = <1>; | |
| 67 | + #size-cells = <0>; | |
| 68 | + pinctrl-names = "default"; | |
| 69 | + pinctrl-0 = <&pinctrl_wlan>; | |
| 70 | + bus-width = <4>; | |
| 71 | + no-1-8-v; | |
| 72 | + non-removable; | |
| 73 | + cap-power-off-card; | |
| 74 | + keep-power-in-suspend; | |
| 75 | + cap-sdio-irq; | |
| 76 | + mmc-pwrseq = <&usdhc2_pwrseq>; | |
| 77 | + status = "okay"; | |
| 78 | + | |
| 79 | + brcmf: wifi@1 { | |
| 80 | + reg = <1>; | |
| 81 | + compatible = "brcm,bcm4329-fmac"; | |
| 82 | + interrupt-parent = <&gpio1>; | |
| 83 | + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; | |
| 84 | + interrupt-names = "host-wake"; | |
| 85 | + }; | |
| 86 | +}; | |
| 87 | + | |
| 88 | +&wdog1 { | |
| 89 | + status = "okay"; | |
| 90 | +}; | |
| 91 | + | |
| 92 | +&iomuxc { | |
| 93 | + pinctrl_gpmi_nand: gpmi-nand { | |
| 94 | + fsl,pins = < | |
| 95 | + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 | |
| 96 | + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 | |
| 97 | + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 | |
| 98 | + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 | |
| 99 | + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 | |
| 100 | + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 | |
| 101 | + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 | |
| 102 | + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 | |
| 103 | + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 | |
| 104 | + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 | |
| 105 | + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 | |
| 106 | + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 | |
| 107 | + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 | |
| 108 | + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 | |
| 109 | + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 | |
| 110 | + >; | |
| 111 | + }; | |
| 112 | + | |
| 113 | + pinctrl_uart3: uart3grp { | |
| 114 | + fsl,pins = < | |
| 115 | + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 | |
| 116 | + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 | |
| 117 | + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 | |
| 118 | + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 | |
| 119 | + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ | |
| 120 | + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ | |
| 121 | + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ | |
| 122 | + >; | |
| 123 | + }; | |
| 124 | + | |
| 125 | + pinctrl_uart4: uart4grp { | |
| 126 | + fsl,pins = < | |
| 127 | + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 | |
| 128 | + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 | |
| 129 | + >; | |
| 130 | + }; | |
| 131 | + | |
| 132 | + pinctrl_wlan: wlangrp { | |
| 133 | + fsl,pins = < | |
| 134 | + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 | |
| 135 | + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 | |
| 136 | + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 | |
| 137 | + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 | |
| 138 | + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 | |
| 139 | + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 | |
| 140 | + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ | |
| 141 | + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ | |
| 142 | + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ | |
| 143 | + MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ | |
| 144 | + >; | |
| 145 | + }; | |
| 146 | +}; | |
| @@ -34,6 +34,19 @@ · 33 unmodified lines | ||
| 34 | 34 | startup-delay-us = <150>; |
| 35 | 35 | }; |
| 36 | 36 | |
| 37 | + reg_digitizer: regulator-digitizer { | |
| 38 | + compatible = "regulator-fixed"; | |
| 39 | + regulator-name = "VDD_3V3_DIGITIZER"; | |
| 40 | + regulator-min-microvolt = <3300000>; | |
| 41 | + regulator-max-microvolt = <3300000>; | |
| 42 | + pinctrl-names = "default", "sleep"; | |
| 43 | + pinctrl-0 = <&pinctrl_digitizer_reg>; | |
| 44 | + pinctrl-1 = <&pinctrl_digitizer_reg>; | |
| 45 | + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; | |
| 46 | + enable-active-high; | |
| 47 | + startup-delay-us = <100000>; /* 100 ms */ | |
| 48 | + }; | |
| 49 | + | |
| 37 | 50 | wifi_pwrseq: wifi_pwrseq { |
| 38 | 51 | compatible = "mmc-pwrseq-simple"; |
| 39 | 52 | pinctrl-names = "default"; |
| @@ -51,6 +64,26 @@ · 11 unmodified lines | ||
| 51 | 64 | assigned-clock-rates = <0>, <32768>; |
| 52 | 65 | }; |
| 53 | 66 | |
| 67 | +&i2c1 { | |
| 68 | + clock-frequency = <400000>; | |
| 69 | + pinctrl-names = "default"; | |
| 70 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 71 | + status = "okay"; | |
| 72 | + | |
| 73 | + wacom_digitizer: digitizer@9 { | |
| 74 | + compatible = "hid-over-i2c"; | |
| 75 | + reg = <0x09>; | |
| 76 | + hid-descr-addr = <0x01>; | |
| 77 | + pinctrl-names = "default"; | |
| 78 | + pinctrl-0 = <&pinctrl_wacom>; | |
| 79 | + interrupt-parent = <&gpio1>; | |
| 80 | + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; | |
| 81 | + touchscreen-inverted-x; | |
| 82 | + touchscreen-inverted-y; | |
| 83 | + vdd-supply = <®_digitizer>; | |
| 84 | + }; | |
| 85 | +}; | |
| 86 | + | |
| 54 | 87 | &snvs_pwrkey { |
| 55 | 88 | status = "okay"; |
| 56 | 89 | }; |
| @@ -117,6 +150,25 @@ · 60 unmodified lines | ||
| 117 | 150 | fsl,ext-reset-output; |
| 118 | 151 | }; |
| 119 | 152 | |
| 153 | +&iomuxc_lpsr { | |
| 154 | + pinctrl_digitizer_reg: digitizerreggrp { | |
| 155 | + fsl,pins = < | |
| 156 | + /* DIGITIZER_PWR_EN */ | |
| 157 | + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 | |
| 158 | + >; | |
| 159 | + }; | |
| 160 | + | |
| 161 | + pinctrl_wacom: wacomgrp { | |
| 162 | + fsl,pins = < | |
| 163 | + /*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */ | |
| 164 | + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */ | |
| 165 | + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */ | |
| 166 | + /*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */ | |
| 167 | + /*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */ | |
| 168 | + >; | |
| 169 | + }; | |
| 170 | +}; | |
| 171 | + | |
| 120 | 172 | &iomuxc { |
| 121 | 173 | pinctrl_brcm_reg: brcmreggrp { |
| 122 | 174 | fsl,pins = < |
| @@ -125,6 +177,13 @@ · 2 unmodified lines | ||
| 125 | 177 | >; |
| 126 | 178 | }; |
| 127 | 179 | |
| 180 | + pinctrl_i2c1: i2c1grp { | |
| 181 | + fsl,pins = < | |
| 182 | + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f | |
| 183 | + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f | |
| 184 | + >; | |
| 185 | + }; | |
| 186 | + | |
| 128 | 187 | pinctrl_uart1: uart1grp { |
| 129 | 188 | fsl,pins = < |
| 130 | 189 | MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 |
| @@ -248,17 +248,17 @@ · 247 unmodified lines | ||
| 248 | 248 | |
| 249 | 249 | &mipi_csi { |
| 250 | 250 | clock-frequency = <166000000>; |
| 251 | − fsl,csis-hs-settle = <3>; | |
| 252 | 251 | status = "okay"; |
| 253 | 252 | |
| 254 | − port@0 { | |
| 255 | − reg = <0>; | |
| 253 | + ports { | |
| 254 | + port@0 { | |
| 255 | + reg = <0>; | |
| 256 | 256 | |
| 257 | − mipi_from_sensor: endpoint { | |
| 258 | − remote-endpoint = <&ov2680_to_mipi>; | |
| 259 | − data-lanes = <1>; | |
| 257 | + mipi_from_sensor: endpoint { | |
| 258 | + remote-endpoint = <&ov2680_to_mipi>; | |
| 259 | + data-lanes = <1>; | |
| 260 | + }; | |
| 260 | 261 | }; |
| 261 | − | |
| 262 | 262 | }; |
| 263 | 263 | }; |
| 264 | 264 | |
| @@ -809,8 +809,6 @@ · 808 unmodified lines | ||
| 809 | 809 | mipi_csi: mipi-csi@30750000 { |
| 810 | 810 | compatible = "fsl,imx7-mipi-csi2"; |
| 811 | 811 | reg = <0x30750000 0x10000>; |
| 812 | − #address-cells = <1>; | |
| 813 | − #size-cells = <0>; | |
| 814 | 812 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 815 | 813 | clocks = <&clks IMX7D_IPG_ROOT_CLK>, |
| 816 | 814 | <&clks IMX7D_MIPI_CSI_ROOT_CLK>, |
| @@ -819,18 +817,22 @@ · 2 unmodified lines | ||
| 819 | 817 | power-domains = <&pgc_mipi_phy>; |
| 820 | 818 | phy-supply = <®_1p0d>; |
| 821 | 819 | resets = <&src IMX7_RESET_MIPI_PHY_MRST>; |
| 822 | − reset-names = "mrst"; | |
| 823 | 820 | status = "disabled"; |
| 824 | 821 | |
| 825 | − port@0 { | |
| 826 | − reg = <0>; | |
| 827 | − }; | |
| 822 | + ports { | |
| 823 | + #address-cells = <1>; | |
| 824 | + #size-cells = <0>; | |
| 828 | 825 | |
| 829 | − port@1 { | |
| 830 | − reg = <1>; | |
| 826 | + port@0 { | |
| 827 | + reg = <0>; | |
| 828 | + }; | |
| 831 | 829 | |
| 832 | − mipi_vc0_to_csi_mux: endpoint { | |
| 833 | − remote-endpoint = <&csi_mux_from_mipi_vc0>; | |
| 830 | + port@1 { | |
| 831 | + reg = <1>; | |
| 832 | + | |
| 833 | + mipi_vc0_to_csi_mux: endpoint { | |
| 834 | + remote-endpoint = <&csi_mux_from_mipi_vc0>; | |
| 835 | + }; | |
| 834 | 836 | }; |
| 835 | 837 | }; |
| 836 | 838 | }; |
| @@ -97,6 +97,65 @@ · 96 unmodified lines | ||
| 97 | 97 | fis-index-block = <0x1f>; |
| 98 | 98 | }; |
| 99 | 99 | }; |
| 100 | + | |
| 101 | + /* Small syscon with some LEDs at CS2 */ | |
| 102 | + syscon@2,0 { | |
| 103 | + compatible = "freecom,fsg-cs2-system-controller", "syscon"; | |
| 104 | + reg = <2 0x0 0x200>; | |
| 105 | + reg-io-width = <2>; | |
| 106 | + #address-cells = <1>; | |
| 107 | + #size-cells = <1>; | |
| 108 | + ranges = <2 0x0 0x0 0x200>; | |
| 109 | + | |
| 110 | + led@0,0 { | |
| 111 | + compatible = "register-bit-led"; | |
| 112 | + reg = <0x00 0x02>; | |
| 113 | + mask = <0x01>; | |
| 114 | + label = "fsg:blue:wlan"; | |
| 115 | + linux,default-trigger = "wlan"; | |
| 116 | + default-state = "on"; | |
| 117 | + }; | |
| 118 | + led@0,1 { | |
| 119 | + compatible = "register-bit-led"; | |
| 120 | + reg = <0x00 0x02>; | |
| 121 | + mask = <0x02>; | |
| 122 | + label = "fsg:blue:wan"; | |
| 123 | + linux,default-trigger = ""; | |
| 124 | + default-state = "on"; | |
| 125 | + }; | |
| 126 | + led@0,2 { | |
| 127 | + compatible = "register-bit-led"; | |
| 128 | + reg = <0x00 0x02>; | |
| 129 | + mask = <0x04>; | |
| 130 | + label = "fsg:blue:sata"; | |
| 131 | + linux,default-trigger = ""; | |
| 132 | + default-state = "on"; | |
| 133 | + }; | |
| 134 | + led@0,3 { | |
| 135 | + compatible = "register-bit-led"; | |
| 136 | + reg = <0x00 0x02>; | |
| 137 | + mask = <0x04>; | |
| 138 | + label = "fsg:blue:usb"; | |
| 139 | + linux,default-trigger = ""; | |
| 140 | + default-state = "on"; | |
| 141 | + }; | |
| 142 | + led@0,4 { | |
| 143 | + compatible = "register-bit-led"; | |
| 144 | + reg = <0x00 0x02>; | |
| 145 | + mask = <0x08>; | |
| 146 | + label = "fsg:blue:sync"; | |
| 147 | + linux,default-trigger = ""; | |
| 148 | + default-state = "on"; | |
| 149 | + }; | |
| 150 | + led@0,5 { | |
| 151 | + compatible = "register-bit-led"; | |
| 152 | + reg = <0x00 0x02>; | |
| 153 | + mask = <0x10>; | |
| 154 | + label = "fsg:blue:ring"; | |
| 155 | + linux,default-trigger = ""; | |
| 156 | + default-state = "on"; | |
| 157 | + }; | |
| 158 | + }; | |
| 100 | 159 | }; |
| 101 | 160 | |
| 102 | 161 | pci@c0000000 { |
| @@ -0,0 +1,111 @@ | ||
| 1 | +// SPDX-License-Identifier: ISC | |
| 2 | +/* | |
| 3 | + * Device Tree file for Gateway 7001 AP | |
| 4 | + * Derived from boardfiles written by Imre Kaloz | |
| 5 | + */ | |
| 6 | + | |
| 7 | +/dts-v1/; | |
| 8 | + | |
| 9 | +#include "intel-ixp42x.dtsi" | |
| 10 | +#include <dt-bindings/input/input.h> | |
| 11 | + | |
| 12 | +/ { | |
| 13 | + model = "Gateway 7001 AP"; | |
| 14 | + compatible = "gateway,7001", "intel,ixp42x"; | |
| 15 | + #address-cells = <1>; | |
| 16 | + #size-cells = <1>; | |
| 17 | + | |
| 18 | + memory@0 { | |
| 19 | + /* 32 MB SDRAM */ | |
| 20 | + device_type = "memory"; | |
| 21 | + reg = <0x00000000 0x2000000>; | |
| 22 | + }; | |
| 23 | + | |
| 24 | + chosen { | |
| 25 | + bootargs = "console=ttyS0,115200n8"; | |
| 26 | + stdout-path = "uart1:115200n8"; | |
| 27 | + }; | |
| 28 | + | |
| 29 | + aliases { | |
| 30 | + /* second UART is the primary console */ | |
| 31 | + serial0 = &uart1; | |
| 32 | + serial1 = &uart0; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + soc { | |
| 36 | + bus@c4000000 { | |
| 37 | + flash@0,0 { | |
| 38 | + compatible = "intel,ixp4xx-flash", "cfi-flash"; | |
| 39 | + bank-width = <2>; | |
| 40 | + /* | |
| 41 | + * 8 MB of flash | |
| 42 | + */ | |
| 43 | + reg = <0 0x00000000 0x800000>; | |
| 44 | + | |
| 45 | + /* Configure expansion bus to allow writes */ | |
| 46 | + intel,ixp4xx-eb-write-enable = <1>; | |
| 47 | + | |
| 48 | + partitions { | |
| 49 | + compatible = "redboot-fis"; | |
| 50 | + /* Eraseblock at 0x7e0000 */ | |
| 51 | + fis-index-block = <0x3f>; | |
| 52 | + }; | |
| 53 | + }; | |
| 54 | + }; | |
| 55 | + | |
| 56 | + pci@c0000000 { | |
| 57 | + status = "ok"; | |
| 58 | + | |
| 59 | + /* | |
| 60 | + * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) | |
| 61 | + * We have slots (IDSEL) 1 and 2 with one assigned IRQ | |
| 62 | + * each handling all IRQs. | |
| 63 | + */ | |
| 64 | + interrupt-map = | |
| 65 | + /* IDSEL 1 */ | |
| 66 | + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ | |
| 67 | + <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */ | |
| 68 | + <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */ | |
| 69 | + <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */ | |
| 70 | + /* IDSEL 2 */ | |
| 71 | + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ | |
| 72 | + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ | |
| 73 | + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ | |
| 74 | + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ | |
| 75 | + }; | |
| 76 | + | |
| 77 | + ethernet@c8009000 { | |
| 78 | + status = "ok"; | |
| 79 | + queue-rx = <&qmgr 3>; | |
| 80 | + queue-txready = <&qmgr 20>; | |
| 81 | + phy-mode = "rgmii"; | |
| 82 | + phy-handle = <&phy1>; | |
| 83 | + | |
| 84 | + mdio { | |
| 85 | + #address-cells = <1>; | |
| 86 | + #size-cells = <0>; | |
| 87 | + | |
| 88 | + phy1: ethernet-phy@1 { | |
| 89 | + reg = <1>; | |
| 90 | + }; | |
| 91 | + }; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + ethernet@c800a000 { | |
| 95 | + status = "ok"; | |
| 96 | + queue-rx = <&qmgr 4>; | |
| 97 | + queue-txready = <&qmgr 21>; | |
| 98 | + phy-mode = "rgmii"; | |
| 99 | + phy-handle = <&phy2>; | |
| 100 | + | |
| 101 | + mdio { | |
| 102 | + #address-cells = <1>; | |
| 103 | + #size-cells = <0>; | |
| 104 | + | |
| 105 | + phy2: ethernet-phy@2 { | |
| 106 | + reg = <2>; | |
| 107 | + }; | |
| 108 | + }; | |
| 109 | + }; | |
| 110 | + }; | |
| 111 | +}; | |
| @@ -0,0 +1,180 @@ | ||
| 1 | +// SPDX-License-Identifier: ISC | |
| 2 | +/* | |
| 3 | + * Device Tree file for the Goramo MultiLink Router | |
| 4 | + * There are two variants: | |
| 5 | + * - MultiLink Basic (a box) | |
| 6 | + * - MultiLink Max (19" rack mount) | |
| 7 | + * This device tree supports MultiLink Basic. | |
| 8 | + * This machine is based on IXP425. | |
| 9 | + * This is one of the few devices supporting the IXP4xx High-Speed Serial | |
| 10 | + * (HSS) link for a V.35 WAN interface. | |
| 11 | + * The hardware originates in Poland. | |
| 12 | + */ | |
| 13 | + | |
| 14 | +/dts-v1/; | |
| 15 | + | |
| 16 | +#include "intel-ixp42x.dtsi" | |
| 17 | +#include <dt-bindings/input/input.h> | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + model = "Goramo MultiLink Router"; | |
| 21 | + compatible = "goramo,multilink-router", "intel,ixp42x"; | |
| 22 | + #address-cells = <1>; | |
| 23 | + #size-cells = <1>; | |
| 24 | + | |
| 25 | + memory@0 { | |
| 26 | + /* | |
| 27 | + * 64 MB of RAM according to the manual. The MultiLink | |
| 28 | + * Max has 128 MB. | |
| 29 | + */ | |
| 30 | + device_type = "memory"; | |
| 31 | + reg = <0x00000000 0x4000000>; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + chosen { | |
| 35 | + bootargs = "console=ttyS0,115200n8"; | |
| 36 | + stdout-path = "uart0:115200n8"; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + aliases { | |
| 40 | + serial0 = &uart0; | |
| 41 | + serial1 = &uart1; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + /* | |
| 45 | + * 74HC4094 which is used as a rudimentary GPIO expander | |
| 46 | + * FIXME: | |
| 47 | + * - Create device tree bindings for this as GPIO expander | |
| 48 | + * - Write a pure DT GPIO driver using these bindings | |
| 49 | + * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) | |
| 50 | + */ | |
| 51 | + gpio_74: gpio-74hc4094 { | |
| 52 | + compatible = "nxp,74hc4094"; | |
| 53 | + cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; | |
| 54 | + d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; | |
| 55 | + str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; | |
| 56 | + /* oe-gpios is optional */ | |
| 57 | + gpio-controller; | |
| 58 | + #gpio-cells = <2>; | |
| 59 | + /* We are not cascaded */ | |
| 60 | + registers-number = <1>; | |
| 61 | + gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N", | |
| 62 | + "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET", | |
| 63 | + "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N"; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + soc { | |
| 67 | + bus@c4000000 { | |
| 68 | + flash@0,0 { | |
| 69 | + compatible = "intel,ixp4xx-flash", "cfi-flash"; | |
| 70 | + bank-width = <2>; | |
| 71 | + /* Enable writes on the expansion bus */ | |
| 72 | + intel,ixp4xx-eb-write-enable = <1>; | |
| 73 | + /* 16 MB of Flash mapped in at CS0 */ | |
| 74 | + reg = <0 0x00000000 0x1000000>; | |
| 75 | + | |
| 76 | + partitions { | |
| 77 | + compatible = "redboot-fis"; | |
| 78 | + /* Eraseblock at 0x0fe0000 */ | |
| 79 | + fis-index-block = <0x7f>; | |
| 80 | + }; | |
| 81 | + }; | |
| 82 | + }; | |
| 83 | + | |
| 84 | + pci@c0000000 { | |
| 85 | + status = "ok"; | |
| 86 | + | |
| 87 | + /* | |
| 88 | + * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. | |
| 89 | + * The slots have Ethernet, Ethernet, NEC and MPCI. | |
| 90 | + * The IDSELs are 11, 12, 13, 14. | |
| 91 | + */ | |
| 92 | + interrupt-map = | |
| 93 | + /* IDSEL 11 - Ethernet A */ | |
| 94 | + <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ | |
| 95 | + <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ | |
| 96 | + <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */ | |
| 97 | + <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */ | |
| 98 | + /* IDSEL 12 - Ethernet B */ | |
| 99 | + <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ | |
| 100 | + <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ | |
| 101 | + <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ | |
| 102 | + <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ | |
| 103 | + /* IDSEL 13 - MPCI */ | |
| 104 | + <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */ | |
| 105 | + <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */ | |
| 106 | + <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */ | |
| 107 | + <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */ | |
| 108 | + /* IDSEL 14 - NEC */ | |
| 109 | + <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */ | |
| 110 | + <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */ | |
| 111 | + <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */ | |
| 112 | + <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */ | |
| 113 | + }; | |
| 114 | + | |
| 115 | + /* HSS links */ | |
| 116 | + npe@c8006000 { | |
| 117 | + hss@0 { | |
| 118 | + status = "okay"; | |
| 119 | + intel,queue-chl-rxtrig = <&qmgr 12>; | |
| 120 | + intel,queue-chl-txready = <&qmgr 34>; | |
| 121 | + intel,queue-pkt-rx = <&qmgr 13>; | |
| 122 | + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; | |
| 123 | + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; | |
| 124 | + intel,queue-pkt-txdone = <&qmgr 22>; | |
| 125 | + /* The Goramo GPIO-based clock etc control */ | |
| 126 | + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; | |
| 127 | + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; | |
| 128 | + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; | |
| 129 | + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; | |
| 130 | + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; | |
| 131 | + }; | |
| 132 | + hss@1 { | |
| 133 | + status = "okay"; | |
| 134 | + intel,queue-chl-rxtrig = <&qmgr 10>; | |
| 135 | + intel,queue-chl-txready = <&qmgr 35>; | |
| 136 | + intel,queue-pkt-rx = <&qmgr 0>; | |
| 137 | + intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>; | |
| 138 | + intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>; | |
| 139 | + intel,queue-pkt-txdone = <&qmgr 9>; | |
| 140 | + /* The Goramo GPIO-based clock etc control */ | |
| 141 | + cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; | |
| 142 | + rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; | |
| 143 | + dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; | |
| 144 | + dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>; | |
| 145 | + clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>; | |
| 146 | + }; | |
| 147 | + }; | |
| 148 | + | |
| 149 | + /* EthB */ | |
| 150 | + ethernet@c8009000 { | |
| 151 | + status = "ok"; | |
| 152 | + queue-rx = <&qmgr 3>; | |
| 153 | + queue-txready = <&qmgr 32>; | |
| 154 | + phy-mode = "rgmii"; | |
| 155 | + phy-handle = <&phy0>; | |
| 156 | + | |
| 157 | + mdio { | |
| 158 | + #address-cells = <1>; | |
| 159 | + #size-cells = <0>; | |
| 160 | + | |
| 161 | + phy0: ethernet-phy@0 { | |
| 162 | + reg = <0>; | |
| 163 | + }; | |
| 164 | + | |
| 165 | + phy1: ethernet-phy@1 { | |
| 166 | + reg = <1>; | |
| 167 | + }; | |
| 168 | + }; | |
| 169 | + }; | |
| 170 | + | |
| 171 | + /* EthC */ | |
| 172 | + ethernet@c800a000 { | |
| 173 | + status = "ok"; | |
| 174 | + queue-rx = <&qmgr 4>; | |
| 175 | + queue-txready = <&qmgr 33>; | |
| 176 | + phy-mode = "rgmii"; | |
| 177 | + phy-handle = <&phy1>; | |
| 178 | + }; | |
| 179 | + }; | |
| 180 | +}; | |
| @@ -139,6 +139,23 @@ · 138 unmodified lines | ||
| 139 | 139 | npe: npe@c8006000 { |
| 140 | 140 | compatible = "intel,ixp4xx-network-processing-engine"; |
| 141 | 141 | reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; |
| 142 | + #address-cells = <1>; | |
| 143 | + #size-cells = <0>; | |
| 144 | + | |
| 145 | + /* NPE-A contains two high-speed serial links */ | |
| 146 | + hss@0 { | |
| 147 | + compatible = "intel,ixp4xx-hss"; | |
| 148 | + reg = <0>; | |
| 149 | + intel,npe-handle = <&npe 0>; | |
| 150 | + status = "disabled"; | |
| 151 | + }; | |
| 152 | + | |
| 153 | + hss@1 { | |
| 154 | + compatible = "intel,ixp4xx-hss"; | |
| 155 | + reg = <1>; | |
| 156 | + intel,npe-handle = <&npe 0>; | |
| 157 | + status = "disabled"; | |
| 158 | + }; | |
| 142 | 159 | |
| 143 | 160 | /* NPE-C contains a crypto accelerator */ |
| 144 | 161 | crypto { |
| @@ -65,10 +65,18 @@ · 64 unmodified lines | ||
| 65 | 65 | <0x1d002000 0x1000>; /* CPU I/f base and size */ |
| 66 | 66 | }; |
| 67 | 67 | |
| 68 | + clk: clock-ctrl@1d021000 { | |
| 69 | + compatible = "socionext,milbeaut-m10v-ccu"; | |
| 70 | + #clock-cells = <1>; | |
| 71 | + reg = <0x1d021000 0x1000>; | |
| 72 | + clocks = <&uclk40xi>; | |
| 73 | + }; | |
| 74 | + | |
| 68 | 75 | timer@1e000050 { /* 32-bit Reload Timers */ |
| 69 | 76 | compatible = "socionext,milbeaut-timer"; |
| 70 | 77 | reg = <0x1e000050 0x20>; |
| 71 | 78 | interrupts = <0 91 4>; |
| 79 | + clocks = <&clk 4>; | |
| 72 | 80 | }; |
| 73 | 81 | |
| 74 | 82 | uart1: serial@1e700010 { /* PE4, PE5 */ |
| @@ -77,6 +85,7 @@ · 2 unmodified lines | ||
| 77 | 85 | reg = <0x1e700010 0x10>; |
| 78 | 86 | interrupts = <0 141 0x4>, <0 149 0x4>; |
| 79 | 87 | interrupt-names = "rx", "tx"; |
| 88 | + clocks = <&clk 2>; | |
| 80 | 89 | }; |
| 81 | 90 | |
| 82 | 91 | }; |
| @@ -310,7 +310,7 @@ · 309 unmodified lines | ||
| 310 | 310 | #address-cells = <1>; |
| 311 | 311 | #size-cells = <0>; |
| 312 | 312 | wlcore: wlcore@2 { |
| 313 | − compatible = "ti,wl1285", "ti,wl1283"; | |
| 313 | + compatible = "ti,wl1285"; | |
| 314 | 314 | reg = <2>; |
| 315 | 315 | /* gpio_100 with gpmc_wait2 pad as wakeirq */ |
| 316 | 316 | interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -0,0 +1,30 @@ | ||
| 1 | +// SPDX-License-Identifier: BSD-3-Clause | |
| 2 | +/* | |
| 3 | + * Copyright (c) 2021, Luca Weiss <luca@z3ntu.xyz> | |
| 4 | + */ | |
| 5 | + | |
| 6 | +/dts-v1/; | |
| 7 | +#include "mt6589.dtsi" | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + model = "Fairphone 1"; | |
| 11 | + compatible = "fairphone,fp1", "mediatek,mt6589"; | |
| 12 | + | |
| 13 | + chosen { | |
| 14 | + stdout-path = &uart3; | |
| 15 | + }; | |
| 16 | + | |
| 17 | + memory@80000000 { | |
| 18 | + device_type = "memory"; | |
| 19 | + reg = <0x80000000 0x40000000>; | |
| 20 | + }; | |
| 21 | +}; | |
| 22 | + | |
| 23 | +&cpus { | |
| 24 | + /* SMP is not stable on this board, makes the kernel panic */ | |
| 25 | + /delete-property/ enable-method; | |
| 26 | +}; | |
| 27 | + | |
| 28 | +&uart3 { | |
| 29 | + status = "okay"; | |
| 30 | +}; | |
| @@ -14,7 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | compatible = "mediatek,mt6589"; |
| 15 | 15 | interrupt-parent = <&sysirq>; |
| 16 | 16 | |
| 17 | − cpus { | |
| 17 | + cpus: cpus { | |
| 18 | 18 | #address-cells = <1>; |
| 19 | 19 | #size-cells = <0>; |
| 20 | 20 | enable-method = "mediatek,mt6589-smp"; |
| @@ -197,25 +197,11 @@ · 196 unmodified lines | ||
| 197 | 197 | &mcspi1 { |
| 198 | 198 | pinctrl-names = "default"; |
| 199 | 199 | pinctrl-0 = <&mcspi1_pins>; |
| 200 | − | |
| 201 | − spidev@0 { | |
| 202 | − compatible = "spidev"; | |
| 203 | − spi-max-frequency = <48000000>; | |
| 204 | − reg = <0>; | |
| 205 | − spi-cpha; | |
| 206 | − }; | |
| 207 | 200 | }; |
| 208 | 201 | |
| 209 | 202 | &mcspi3 { |
| 210 | 203 | pinctrl-names = "default"; |
| 211 | 204 | pinctrl-0 = <&mcspi3_pins>; |
| 212 | − | |
| 213 | − spidev@0 { | |
| 214 | − compatible = "spidev"; | |
| 215 | − spi-max-frequency = <48000000>; | |
| 216 | − reg = <0>; | |
| 217 | − spi-cpha; | |
| 218 | − }; | |
| 219 | 205 | }; |
| 220 | 206 | |
| 221 | 207 | #include "twl4030.dtsi" |
| @@ -0,0 +1,35 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +/* | |
| 3 | + * Copyright (C) 2020 Bytedance. | |
| 4 | + */ | |
| 5 | + | |
| 6 | +partitions { | |
| 7 | + compatible = "fixed-partitions"; | |
| 8 | + #address-cells = <1>; | |
| 9 | + #size-cells = <1>; | |
| 10 | + | |
| 11 | + u-boot@0 { | |
| 12 | + reg = <0x0 0xe0000>; // 896KB | |
| 13 | + label = "alt-u-boot"; | |
| 14 | + }; | |
| 15 | + | |
| 16 | + u-boot-env@e0000 { | |
| 17 | + reg = <0xe0000 0x20000>; // 128KB | |
| 18 | + label = "alt-u-boot-env"; | |
| 19 | + }; | |
| 20 | + | |
| 21 | + kernel@100000 { | |
| 22 | + reg = <0x100000 0x900000>; // 9MB | |
| 23 | + label = "alt-kernel"; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + rofs@a00000 { | |
| 27 | + reg = <0xa00000 0x2000000>; // 32MB | |
| 28 | + label = "alt-rofs"; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + rwfs@6000000 { | |
| 32 | + reg = <0x2a00000 0x1600000>; // 22MB | |
| 33 | + label = "alt-rwfs"; | |
| 34 | + }; | |
| 35 | +}; | |
| @@ -0,0 +1,2 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | +#include "arm64/qcom/apq8016-sbc.dts" | |
| @@ -19,7 +19,6 @@ · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | gpio-keys { |
| 21 | 21 | compatible = "gpio-keys"; |
| 22 | − input-name = "gpio-keys"; | |
| 23 | 22 | |
| 24 | 23 | pinctrl-names = "default"; |
| 25 | 24 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -637,7 +637,7 @@ · 636 unmodified lines | ||
| 637 | 637 | }; |
| 638 | 638 | |
| 639 | 639 | usb3: usb3@8af8800 { |
| 640 | − compatible = "qcom,dwc3"; | |
| 640 | + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; | |
| 641 | 641 | reg = <0x8af8800 0x100>; |
| 642 | 642 | #address-cells = <1>; |
| 643 | 643 | #size-cells = <1>; |
| @@ -669,7 +669,7 @@ · 25 unmodified lines | ||
| 669 | 669 | }; |
| 670 | 670 | |
| 671 | 671 | usb2: usb2@60f8800 { |
| 672 | − compatible = "qcom,dwc3"; | |
| 672 | + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; | |
| 673 | 673 | reg = <0x60f8800 0x100>; |
| 674 | 674 | #address-cells = <1>; |
| 675 | 675 | #size-cells = <1>; |
| @@ -1080,7 +1080,7 @@ · 1079 unmodified lines | ||
| 1080 | 1080 | }; |
| 1081 | 1081 | |
| 1082 | 1082 | usb3_0: usb3@100f8800 { |
| 1083 | − compatible = "qcom,dwc3", "syscon"; | |
| 1083 | + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; | |
| 1084 | 1084 | #address-cells = <1>; |
| 1085 | 1085 | #size-cells = <1>; |
| 1086 | 1086 | reg = <0x100f8800 0x8000>; |
| @@ -1122,7 +1122,7 @@ · 35 unmodified lines | ||
| 1122 | 1122 | }; |
| 1123 | 1123 | |
| 1124 | 1124 | usb3_1: usb3@110f8800 { |
| 1125 | − compatible = "qcom,dwc3", "syscon"; | |
| 1125 | + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; | |
| 1126 | 1126 | #address-cells = <1>; |
| 1127 | 1127 | #size-cells = <1>; |
| 1128 | 1128 | reg = <0x110f8800 0x8000>; |
| @@ -103,7 +103,7 @@ · 102 unmodified lines | ||
| 103 | 103 | |
| 104 | 104 | &gsbi3_spi { |
| 105 | 105 | spi@0 { |
| 106 | − compatible = "swir,mangoh-iotport-spi", "spidev"; | |
| 106 | + compatible = "swir,mangoh-iotport-spi"; | |
| 107 | 107 | spi-max-frequency = <24000000>; |
| 108 | 108 | reg = <0>; |
| 109 | 109 | }; |
| @@ -20,7 +20,6 @@ · 19 unmodified lines | ||
| 20 | 20 | |
| 21 | 21 | gpio-keys { |
| 22 | 22 | compatible = "gpio-keys"; |
| 23 | − input-name = "gpio-keys"; | |
| 24 | 23 | |
| 25 | 24 | pinctrl-names = "default"; |
| 26 | 25 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -450,7 +450,6 @@ · 449 unmodified lines | ||
| 450 | 450 | |
| 451 | 451 | gpio-keys { |
| 452 | 452 | compatible = "gpio-keys"; |
| 453 | − input-name = "gpio-keys"; | |
| 454 | 453 | |
| 455 | 454 | pinctrl-names = "default"; |
| 456 | 455 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -349,7 +349,6 @@ · 348 unmodified lines | ||
| 349 | 349 | |
| 350 | 350 | gpio-keys { |
| 351 | 351 | compatible = "gpio-keys"; |
| 352 | − input-name = "gpio-keys"; | |
| 353 | 352 | |
| 354 | 353 | pinctrl-names = "default"; |
| 355 | 354 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -20,7 +20,6 @@ · 19 unmodified lines | ||
| 20 | 20 | |
| 21 | 21 | gpio-keys { |
| 22 | 22 | compatible = "gpio-keys"; |
| 23 | − input-name = "gpio-keys"; | |
| 24 | 23 | |
| 25 | 24 | pinctrl-names = "default"; |
| 26 | 25 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -20,7 +20,6 @@ · 19 unmodified lines | ||
| 20 | 20 | |
| 21 | 21 | gpio-keys { |
| 22 | 22 | compatible = "gpio-keys"; |
| 23 | − input-name = "gpio-keys"; | |
| 24 | 23 | |
| 25 | 24 | pinctrl-names = "default"; |
| 26 | 25 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -20,7 +20,6 @@ · 19 unmodified lines | ||
| 20 | 20 | |
| 21 | 21 | gpio-keys { |
| 22 | 22 | compatible = "gpio-keys"; |
| 23 | − input-name = "gpio-keys"; | |
| 24 | 23 | |
| 25 | 24 | pinctrl-names = "default"; |
| 26 | 25 | pinctrl-0 = <&gpio_keys_pin_a>; |
| @@ -236,6 +236,12 @@ · 235 unmodified lines | ||
| 236 | 236 | status = "ok"; |
| 237 | 237 | }; |
| 238 | 238 | |
| 239 | +&ipa { | |
| 240 | + status = "okay"; | |
| 241 | + | |
| 242 | + memory-region = <&ipa_fw_mem>; | |
| 243 | +}; | |
| 244 | + | |
| 239 | 245 | &qpic_bam { |
| 240 | 246 | status = "ok"; |
| 241 | 247 | }; |
| @@ -236,6 +236,27 @@ · 235 unmodified lines | ||
| 236 | 236 | status = "ok"; |
| 237 | 237 | }; |
| 238 | 238 | |
| 239 | +&ipa { | |
| 240 | + status = "okay"; | |
| 241 | + | |
| 242 | + memory-region = <&ipa_fw_mem>; | |
| 243 | +}; | |
| 244 | + | |
| 245 | +&pcie0_phy { | |
| 246 | + status = "okay"; | |
| 247 | + | |
| 248 | + vdda-phy-supply = <&vreg_l1e_bb_1p2>; | |
| 249 | + vdda-pll-supply = <&vreg_l4e_bb_0p875>; | |
| 250 | +}; | |
| 251 | + | |
| 252 | +&pcie_ep { | |
| 253 | + status = "okay"; | |
| 254 | + | |
| 255 | + pinctrl-names = "default"; | |
| 256 | + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default | |
| 257 | + &pcie_ep_wake_default>; | |
| 258 | +}; | |
| 259 | + | |
| 239 | 260 | &qpic_bam { |
| 240 | 261 | status = "ok"; |
| 241 | 262 | }; |
| @@ -260,6 +281,44 @@ · 18 unmodified lines | ||
| 260 | 281 | memory-region = <&mpss_adsp_mem>; |
| 261 | 282 | }; |
| 262 | 283 | |
| 284 | +&tlmm { | |
| 285 | + pcie_ep_clkreq_default: pcie_ep_clkreq_default { | |
| 286 | + mux { | |
| 287 | + pins = "gpio56"; | |
| 288 | + function = "pcie_clkreq"; | |
| 289 | + }; | |
| 290 | + config { | |
| 291 | + pins = "gpio56"; | |
| 292 | + drive-strength = <2>; | |
| 293 | + bias-disable; | |
| 294 | + }; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + pcie_ep_perst_default: pcie_ep_perst_default { | |
| 298 | + mux { | |
| 299 | + pins = "gpio57"; | |
| 300 | + function = "gpio"; | |
| 301 | + }; | |
| 302 | + config { | |
| 303 | + pins = "gpio57"; | |
| 304 | + drive-strength = <2>; | |
| 305 | + bias-pull-down; | |
| 306 | + }; | |
| 307 | + }; | |
| 308 | + | |
| 309 | + pcie_ep_wake_default: pcie_ep_wake_default { | |
| 310 | + mux { | |
| 311 | + pins = "gpio53"; | |
| 312 | + function = "gpio"; | |
| 313 | + }; | |
| 314 | + config { | |
| 315 | + pins = "gpio53"; | |
| 316 | + drive-strength = <2>; | |
| 317 | + bias-disable; | |
| 318 | + }; | |
| 319 | + }; | |
| 320 | +}; | |
| 321 | + | |
| 263 | 322 | &usb_hsphy { |
| 264 | 323 | status = "okay"; |
| 265 | 324 | vdda-pll-supply = <&vreg_l4e_bb_0p875>; |
| @@ -8,6 +8,7 @@ · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | #include <dt-bindings/clock/qcom,gcc-sdx55.h> |
| 10 | 10 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 11 | +#include <dt-bindings/gpio/gpio.h> | |
| 11 | 12 | #include <dt-bindings/interconnect/qcom,sdx55.h> |
| 12 | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | 14 | #include <dt-bindings/power/qcom-rpmpd.h> |
| @@ -309,6 +310,41 @@ · 295 unmodified lines | ||
| 309 | 310 | status = "disabled"; |
| 310 | 311 | }; |
| 311 | 312 | |
| 313 | + pcie0_phy: phy@1c07000 { | |
| 314 | + compatible = "qcom,sdx55-qmp-pcie-phy"; | |
| 315 | + reg = <0x01c07000 0x1c4>; | |
| 316 | + #address-cells = <1>; | |
| 317 | + #size-cells = <1>; | |
| 318 | + ranges; | |
| 319 | + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, | |
| 320 | + <&gcc GCC_PCIE_CFG_AHB_CLK>, | |
| 321 | + <&gcc GCC_PCIE_0_CLKREF_CLK>, | |
| 322 | + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; | |
| 323 | + clock-names = "aux", "cfg_ahb", "ref", "refgen"; | |
| 324 | + | |
| 325 | + resets = <&gcc GCC_PCIE_PHY_BCR>; | |
| 326 | + reset-names = "phy"; | |
| 327 | + | |
| 328 | + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; | |
| 329 | + assigned-clock-rates = <100000000>; | |
| 330 | + | |
| 331 | + status = "disabled"; | |
| 332 | + | |
| 333 | + pcie0_lane: lanes@1c06000 { | |
| 334 | + reg = <0x01c06000 0x104>, /* tx0 */ | |
| 335 | + <0x01c06200 0x328>, /* rx0 */ | |
| 336 | + <0x01c07200 0x1e8>, /* pcs */ | |
| 337 | + <0x01c06800 0x104>, /* tx1 */ | |
| 338 | + <0x01c06a00 0x328>, /* rx1 */ | |
| 339 | + <0x01c07600 0x800>; /* pcs_misc */ | |
| 340 | + clocks = <&gcc GCC_PCIE_PIPE_CLK>; | |
| 341 | + clock-names = "pipe0"; | |
| 342 | + | |
| 343 | + #phy-cells = <0>; | |
| 344 | + clock-output-names = "pcie_pipe_clk"; | |
| 345 | + }; | |
| 346 | + }; | |
| 347 | + | |
| 312 | 348 | ipa: ipa@1e40000 { |
| 313 | 349 | compatible = "qcom,sdx55-ipa"; |
| 314 | 350 | |
| @@ -356,6 +392,11 @@ · 41 unmodified lines | ||
| 356 | 392 | #hwlock-cells = <1>; |
| 357 | 393 | }; |
| 358 | 394 | |
| 395 | + tcsr: syscon@1fcb000 { | |
| 396 | + compatible = "syscon"; | |
| 397 | + reg = <0x01fc0000 0x1000>; | |
| 398 | + }; | |
| 399 | + | |
| 359 | 400 | sdhc_1: sdhci@8804000 { |
| 360 | 401 | compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; |
| 361 | 402 | reg = <0x08804000 0x1000>; |
| @@ -368,6 +409,45 @@ · 6 unmodified lines | ||
| 368 | 409 | status = "disabled"; |
| 369 | 410 | }; |
| 370 | 411 | |
| 412 | + pcie_ep: pcie-ep@40000000 { | |
| 413 | + compatible = "qcom,sdx55-pcie-ep"; | |
| 414 | + reg = <0x01c00000 0x3000>, | |
| 415 | + <0x40000000 0xf1d>, | |
| 416 | + <0x40000f20 0xc8>, | |
| 417 | + <0x40001000 0x1000>, | |
| 418 | + <0x40002000 0x10000>, | |
| 419 | + <0x01c03000 0x3000>; | |
| 420 | + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", | |
| 421 | + "mmio"; | |
| 422 | + | |
| 423 | + qcom,perst-regs = <&tcsr 0xb258 0xb270>; | |
| 424 | + | |
| 425 | + clocks = <&gcc GCC_PCIE_AUX_CLK>, | |
| 426 | + <&gcc GCC_PCIE_CFG_AHB_CLK>, | |
| 427 | + <&gcc GCC_PCIE_MSTR_AXI_CLK>, | |
| 428 | + <&gcc GCC_PCIE_SLV_AXI_CLK>, | |
| 429 | + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, | |
| 430 | + <&gcc GCC_PCIE_SLEEP_CLK>, | |
| 431 | + <&gcc GCC_PCIE_0_CLKREF_CLK>; | |
| 432 | + clock-names = "aux", "cfg", "bus_master", "bus_slave", | |
| 433 | + "slave_q2a", "sleep", "ref"; | |
| 434 | + | |
| 435 | + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
| 436 | + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 437 | + interrupt-names = "global", "doorbell"; | |
| 438 | + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; | |
| 439 | + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; | |
| 440 | + resets = <&gcc GCC_PCIE_BCR>; | |
| 441 | + reset-names = "core"; | |
| 442 | + power-domains = <&gcc PCIE_GDSC>; | |
| 443 | + phys = <&pcie0_lane>; | |
| 444 | + phy-names = "pciephy"; | |
| 445 | + max-link-speed = <3>; | |
| 446 | + num-lanes = <2>; | |
| 447 | + | |
| 448 | + status = "disabled"; | |
| 449 | + }; | |
| 450 | + | |
| 371 | 451 | remoteproc_mpss: remoteproc@4080000 { |
| 372 | 452 | compatible = "qcom,sdx55-mpss-pas"; |
| 373 | 453 | reg = <0x04080000 0x4040>; |
| @@ -0,0 +1,25 @@ | ||
| 1 | +// SPDX-License-Identifier: BSD-3-Clause | |
| 2 | +/* | |
| 3 | + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. | |
| 4 | + */ | |
| 5 | +/dts-v1/; | |
| 6 | + | |
| 7 | +#include "qcom-sdx65.dtsi" | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + model = "Qualcomm Technologies, Inc. SDX65 MTP"; | |
| 11 | + compatible = "qcom,sdx65-mtp", "qcom,sdx65"; | |
| 12 | + qcom,board-id = <0x2010008 0x302>; | |
| 13 | + | |
| 14 | + aliases { | |
| 15 | + serial0 = &blsp1_uart3; | |
| 16 | + }; | |
| 17 | + | |
| 18 | + chosen { | |
| 19 | + stdout-path = "serial0:115200n8"; | |
| 20 | + }; | |
| 21 | +}; | |
| 22 | + | |
| 23 | +&blsp1_uart3 { | |
| 24 | + status = "ok"; | |
| 25 | +}; | |
| @@ -0,0 +1,222 @@ | ||
| 1 | +// SPDX-License-Identifier: BSD-3-Clause | |
| 2 | +/* | |
| 3 | + * SDX65 SoC device tree source | |
| 4 | + * | |
| 5 | + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. | |
| 6 | + * | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#include <dt-bindings/clock/qcom,gcc-sdx65.h> | |
| 10 | +#include <dt-bindings/clock/qcom,rpmh.h> | |
| 11 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 12 | +#include <dt-bindings/soc/qcom,rpmh-rsc.h> | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + #address-cells = <1>; | |
| 16 | + #size-cells = <1>; | |
| 17 | + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; | |
| 18 | + interrupt-parent = <&intc>; | |
| 19 | + | |
| 20 | + memory { | |
| 21 | + device_type = "memory"; | |
| 22 | + reg = <0 0>; | |
| 23 | + }; | |
| 24 | + | |
| 25 | + clocks { | |
| 26 | + xo_board: xo-board { | |
| 27 | + compatible = "fixed-clock"; | |
| 28 | + clock-frequency = <76800000>; | |
| 29 | + clock-output-names = "xo_board"; | |
| 30 | + #clock-cells = <0>; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + sleep_clk: sleep-clk { | |
| 34 | + compatible = "fixed-clock"; | |
| 35 | + clock-frequency = <32764>; | |
| 36 | + clock-output-names = "sleep_clk"; | |
| 37 | + #clock-cells = <0>; | |
| 38 | + }; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + cpus { | |
| 42 | + #address-cells = <1>; | |
| 43 | + #size-cells = <0>; | |
| 44 | + | |
| 45 | + cpu0: cpu@0 { | |
| 46 | + device_type = "cpu"; | |
| 47 | + compatible = "arm,cortex-a7"; | |
| 48 | + reg = <0x0>; | |
| 49 | + enable-method = "psci"; | |
| 50 | + }; | |
| 51 | + }; | |
| 52 | + | |
| 53 | + psci { | |
| 54 | + compatible = "arm,psci-1.0"; | |
| 55 | + method = "smc"; | |
| 56 | + }; | |
| 57 | + | |
| 58 | + reserved_memory: reserved-memory { | |
| 59 | + #address-cells = <1>; | |
| 60 | + #size-cells = <1>; | |
| 61 | + ranges; | |
| 62 | + | |
| 63 | + cmd_db: reserved-memory@8fee0000 { | |
| 64 | + compatible = "qcom,cmd-db"; | |
| 65 | + reg = <0x8fee0000 0x20000>; | |
| 66 | + no-map; | |
| 67 | + }; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + soc: soc { | |
| 71 | + #address-cells = <1>; | |
| 72 | + #size-cells = <1>; | |
| 73 | + ranges; | |
| 74 | + compatible = "simple-bus"; | |
| 75 | + | |
| 76 | + gcc: clock-controller@100000 { | |
| 77 | + compatible = "qcom,gcc-sdx65"; | |
| 78 | + reg = <0x00100000 0x001f7400>; | |
| 79 | + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; | |
| 80 | + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; | |
| 81 | + #clock-cells = <1>; | |
| 82 | + #reset-cells = <1>; | |
| 83 | + }; | |
| 84 | + | |
| 85 | + blsp1_uart3: serial@831000 { | |
| 86 | + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 87 | + reg = <0x00831000 0x200>; | |
| 88 | + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 89 | + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
| 90 | + clock-names = "core", "iface"; | |
| 91 | + status = "disabled"; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + tlmm: pinctrl@f100000 { | |
| 95 | + compatible = "qcom,sdx65-tlmm"; | |
| 96 | + reg = <0xf100000 0x300000>; | |
| 97 | + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; | |
| 98 | + gpio-controller; | |
| 99 | + #gpio-cells = <2>; | |
| 100 | + gpio-ranges = <&tlmm 0 0 109>; | |
| 101 | + interrupt-controller; | |
| 102 | + interrupt-parent = <&intc>; | |
| 103 | + #interrupt-cells = <2>; | |
| 104 | + }; | |
| 105 | + | |
| 106 | + pdc: interrupt-controller@b210000 { | |
| 107 | + compatible = "qcom,sdx65-pdc", "qcom,pdc"; | |
| 108 | + reg = <0xb210000 0x10000>; | |
| 109 | + qcom,pdc-ranges = <0 147 52>, <52 266 32>; | |
| 110 | + #interrupt-cells = <2>; | |
| 111 | + interrupt-parent = <&intc>; | |
| 112 | + interrupt-controller; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + intc: interrupt-controller@17800000 { | |
| 116 | + compatible = "qcom,msm-qgic2"; | |
| 117 | + interrupt-controller; | |
| 118 | + interrupt-parent = <&intc>; | |
| 119 | + #interrupt-cells = <3>; | |
| 120 | + reg = <0x17800000 0x1000>, | |
| 121 | + <0x17802000 0x1000>; | |
| 122 | + }; | |
| 123 | + | |
| 124 | + timer@17820000 { | |
| 125 | + #address-cells = <1>; | |
| 126 | + #size-cells = <1>; | |
| 127 | + ranges; | |
| 128 | + compatible = "arm,armv7-timer-mem"; | |
| 129 | + reg = <0x17820000 0x1000>; | |
| 130 | + clock-frequency = <19200000>; | |
| 131 | + | |
| 132 | + frame@17821000 { | |
| 133 | + frame-number = <0>; | |
| 134 | + interrupts = <GIC_SPI 7 0x4>, | |
| 135 | + <GIC_SPI 6 0x4>; | |
| 136 | + reg = <0x17821000 0x1000>, | |
| 137 | + <0x17822000 0x1000>; | |
| 138 | + }; | |
| 139 | + | |
| 140 | + frame@17823000 { | |
| 141 | + frame-number = <1>; | |
| 142 | + interrupts = <GIC_SPI 8 0x4>; | |
| 143 | + reg = <0x17823000 0x1000>; | |
| 144 | + status = "disabled"; | |
| 145 | + }; | |
| 146 | + | |
| 147 | + frame@17824000 { | |
| 148 | + frame-number = <2>; | |
| 149 | + interrupts = <GIC_SPI 9 0x4>; | |
| 150 | + reg = <0x17824000 0x1000>; | |
| 151 | + status = "disabled"; | |
| 152 | + }; | |
| 153 | + | |
| 154 | + frame@17825000 { | |
| 155 | + frame-number = <3>; | |
| 156 | + interrupts = <GIC_SPI 10 0x4>; | |
| 157 | + reg = <0x17825000 0x1000>; | |
| 158 | + status = "disabled"; | |
| 159 | + }; | |
| 160 | + | |
| 161 | + frame@17826000 { | |
| 162 | + frame-number = <4>; | |
| 163 | + interrupts = <GIC_SPI 11 0x4>; | |
| 164 | + reg = <0x17826000 0x1000>; | |
| 165 | + status = "disabled"; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + frame@17827000 { | |
| 169 | + frame-number = <5>; | |
| 170 | + interrupts = <GIC_SPI 12 0x4>; | |
| 171 | + reg = <0x17827000 0x1000>; | |
| 172 | + status = "disabled"; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + frame@17828000 { | |
| 176 | + frame-number = <6>; | |
| 177 | + interrupts = <GIC_SPI 13 0x4>; | |
| 178 | + reg = <0x17828000 0x1000>; | |
| 179 | + status = "disabled"; | |
| 180 | + }; | |
| 181 | + | |
| 182 | + frame@17829000 { | |
| 183 | + frame-number = <7>; | |
| 184 | + interrupts = <GIC_SPI 14 0x4>; | |
| 185 | + reg = <0x17829000 0x1000>; | |
| 186 | + status = "disabled"; | |
| 187 | + }; | |
| 188 | + }; | |
| 189 | + | |
| 190 | + apps_rsc: rsc@17830000 { | |
| 191 | + label = "apps_rsc"; | |
| 192 | + compatible = "qcom,rpmh-rsc"; | |
| 193 | + reg = <0x17830000 0x10000>, | |
| 194 | + <0x17840000 0x10000>; | |
| 195 | + reg-names = "drv-0", "drv-1"; | |
| 196 | + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
| 197 | + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 198 | + qcom,tcs-offset = <0xd00>; | |
| 199 | + qcom,drv-id = <1>; | |
| 200 | + qcom,tcs-config = <ACTIVE_TCS 2>, | |
| 201 | + <SLEEP_TCS 2>, | |
| 202 | + <WAKE_TCS 2>, | |
| 203 | + <CONTROL_TCS 1>; | |
| 204 | + | |
| 205 | + rpmhcc: clock-controller@1 { | |
| 206 | + compatible = "qcom,sdx65-rpmh-clk"; | |
| 207 | + #clock-cells = <1>; | |
| 208 | + clock-names = "xo"; | |
| 209 | + clocks = <&xo_board>; | |
| 210 | + }; | |
| 211 | + }; | |
| 212 | + }; | |
| 213 | + | |
| 214 | + timer { | |
| 215 | + compatible = "arm,armv7-timer"; | |
| 216 | + interrupts = <1 13 0xf08>, | |
| 217 | + <1 12 0xf08>, | |
| 218 | + <1 10 0xf08>, | |
| 219 | + <1 11 0xf08>; | |
| 220 | + clock-frequency = <19200000>; | |
| 221 | + }; | |
| 222 | +}; | |
| @@ -44,6 +44,22 @@ · 43 unmodified lines | ||
| 44 | 44 | #clock-cells = <0>; |
| 45 | 45 | clock-frequency = <26000000>; |
| 46 | 46 | }; |
| 47 | + | |
| 48 | + reg_1p8v: 1p8v { | |
| 49 | + compatible = "regulator-fixed"; | |
| 50 | + regulator-name = "1P8V"; | |
| 51 | + regulator-min-microvolt = <1800000>; | |
| 52 | + regulator-max-microvolt = <1800000>; | |
| 53 | + regulator-always-on; | |
| 54 | + }; | |
| 55 | + | |
| 56 | + reg_2p8v: 2p8v { | |
| 57 | + compatible = "regulator-fixed"; | |
| 58 | + regulator-name = "2P8V"; | |
| 59 | + regulator-min-microvolt = <2800000>; | |
| 60 | + regulator-max-microvolt = <2800000>; | |
| 61 | + regulator-always-on; | |
| 62 | + }; | |
| 47 | 63 | }; |
| 48 | 64 | |
| 49 | 65 | &avb { |
| @@ -17,6 +17,9 @@ · 16 unmodified lines | ||
| 17 | 17 | reg = <0x3c>; |
| 18 | 18 | clocks = <&MCLK_CAM>; |
| 19 | 19 | clock-names = "xclk"; |
| 20 | + AVDD-supply = <®_2p8v>; | |
| 21 | + DOVDD-supply = <®_2p8v>; | |
| 22 | + DVDD-supply = <®_1p8v>; | |
| 20 | 23 | status = "okay"; |
| 21 | 24 | |
| 22 | 25 | port { |
| @@ -288,6 +288,7 @@ · 287 unmodified lines | ||
| 288 | 288 | reg-names = "qspi_base", "qspi_mmap"; |
| 289 | 289 | interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; |
| 290 | 290 | clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; |
| 291 | + clock-names = "pclk"; | |
| 291 | 292 | #address-cells = <1>; |
| 292 | 293 | #size-cells = <0>; |
| 293 | 294 | status = "disabled"; |
| @@ -299,6 +300,7 @@ · 5 unmodified lines | ||
| 299 | 300 | reg-names = "qspi_base", "qspi_mmap"; |
| 300 | 301 | interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; |
| 301 | 302 | clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; |
| 303 | + clock-names = "pclk"; | |
| 302 | 304 | #address-cells = <1>; |
| 303 | 305 | #size-cells = <0>; |
| 304 | 306 | status = "disabled"; |
| @@ -765,7 +765,7 @@ · 764 unmodified lines | ||
| 765 | 765 | #define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) |
| 766 | 766 | #define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) |
| 767 | 767 | #define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) |
| 768 | −#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) | |
| 768 | +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) | |
| 769 | 769 | #define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) |
| 770 | 770 | #define PIN_PD21 117 |
| 771 | 771 | #define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) |
| @@ -181,6 +181,36 @@ · 180 unmodified lines | ||
| 181 | 181 | clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; |
| 182 | 182 | }; |
| 183 | 183 | |
| 184 | + qspi0: spi@e080c000 { | |
| 185 | + compatible = "microchip,sama7g5-ospi"; | |
| 186 | + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; | |
| 187 | + reg-names = "qspi_base", "qspi_mmap"; | |
| 188 | + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
| 189 | + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, | |
| 190 | + <&dma0 AT91_XDMAC_DT_PERID(40)>; | |
| 191 | + dma-names = "tx", "rx"; | |
| 192 | + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; | |
| 193 | + clock-names = "pclk", "gclk"; | |
| 194 | + #address-cells = <1>; | |
| 195 | + #size-cells = <0>; | |
| 196 | + status = "disabled"; | |
| 197 | + }; | |
| 198 | + | |
| 199 | + qspi1: spi@e0810000 { | |
| 200 | + compatible = "microchip,sama7g5-qspi"; | |
| 201 | + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; | |
| 202 | + reg-names = "qspi_base", "qspi_mmap"; | |
| 203 | + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 204 | + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, | |
| 205 | + <&dma0 AT91_XDMAC_DT_PERID(42)>; | |
| 206 | + dma-names = "tx", "rx"; | |
| 207 | + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; | |
| 208 | + clock-names = "pclk", "gclk"; | |
| 209 | + #address-cells = <1>; | |
| 210 | + #size-cells = <0>; | |
| 211 | + status = "disabled"; | |
| 212 | + }; | |
| 213 | + | |
| 184 | 214 | adc: adc@e1000000 { |
| 185 | 215 | compatible = "microchip,sama7g5-adc"; |
| 186 | 216 | reg = <0xe1000000 0x200>; |
| @@ -395,22 +395,6 @@ · 394 unmodified lines | ||
| 395 | 395 | pl022,wait-state = <0>; |
| 396 | 396 | pl022,duplex = <0>; |
| 397 | 397 | }; |
| 398 | − | |
| 399 | − spidev@2 { | |
| 400 | − compatible = "spidev"; | |
| 401 | − reg = <2>; | |
| 402 | − spi-max-frequency = <25000000>; | |
| 403 | − spi-cpha; | |
| 404 | − pl022,hierarchy = <0>; | |
| 405 | − pl022,interface = <0>; | |
| 406 | − pl022,slave-tx-disable; | |
| 407 | − pl022,com-mode = <0x2>; | |
| 408 | − pl022,rx-level-trig = <0>; | |
| 409 | − pl022,tx-level-trig = <0>; | |
| 410 | − pl022,ctrl-len = <0x11>; | |
| 411 | − pl022,wait-state = <0>; | |
| 412 | − pl022,duplex = <0>; | |
| 413 | − }; | |
| 414 | 398 | }; |
| 415 | 399 | |
| 416 | 400 | wdt@ec800620 { |
| @@ -489,22 +489,6 @@ · 488 unmodified lines | ||
| 489 | 489 | ts,i-drive = <1>; |
| 490 | 490 | }; |
| 491 | 491 | }; |
| 492 | − | |
| 493 | − spidev@2 { | |
| 494 | − compatible = "spidev"; | |
| 495 | − reg = <2>; | |
| 496 | − spi-max-frequency = <25000000>; | |
| 497 | − spi-cpha; | |
| 498 | − pl022,hierarchy = <0>; | |
| 499 | − pl022,interface = <0>; | |
| 500 | − pl022,slave-tx-disable; | |
| 501 | − pl022,com-mode = <0x2>; | |
| 502 | − pl022,rx-level-trig = <0>; | |
| 503 | − pl022,tx-level-trig = <0>; | |
| 504 | − pl022,ctrl-len = <0x11>; | |
| 505 | − pl022,wait-state = <0>; | |
| 506 | − pl022,duplex = <0>; | |
| 507 | − }; | |
| 508 | 492 | }; |
| 509 | 493 | |
| 510 | 494 | timer@ec800600 { |
| @@ -92,6 +92,7 @@ · 91 unmodified lines | ||
| 92 | 92 | gpiopinctrl: gpio@b4000000 { |
| 93 | 93 | compatible = "st,spear-plgpio"; |
| 94 | 94 | reg = <0xb4000000 0x1000>; |
| 95 | + regmap = <&pinmux>; | |
| 95 | 96 | #interrupt-cells = <1>; |
| 96 | 97 | interrupt-controller; |
| 97 | 98 | gpio-controller; |
| @@ -120,6 +120,7 @@ · 119 unmodified lines | ||
| 120 | 120 | gpiopinctrl: gpio@b3000000 { |
| 121 | 121 | compatible = "st,spear-plgpio"; |
| 122 | 122 | reg = <0xb3000000 0x1000>; |
| 123 | + regmap = <&pinmux>; | |
| 123 | 124 | #interrupt-cells = <1>; |
| 124 | 125 | interrupt-controller; |
| 125 | 126 | gpio-controller; |
| @@ -0,0 +1,24 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later | |
| 2 | +/* | |
| 3 | + * DTS file for SPEAr320s SoC | |
| 4 | + * | |
| 5 | + * Copyright 2021 Herve Codina <herve.codina@bootlin.com> | |
| 6 | + */ | |
| 7 | + | |
| 8 | +/include/ "spear320.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + ahb { | |
| 12 | + apb { | |
| 13 | + gpiopinctrl: gpio@b3000000 { | |
| 14 | + /* | |
| 15 | + * The "RM0321 SPEAr320s address and map | |
| 16 | + * registers" document mentions interrupt 6 | |
| 17 | + * (NPGIO_INTR) for the PL_GPIO interrupt. | |
| 18 | + */ | |
| 19 | + interrupts = <6>; | |
| 20 | + interrupt-parent = <&shirq>; | |
| 21 | + }; | |
| 22 | + }; | |
| 23 | + }; | |
| 24 | +}; | |
| @@ -5,6 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | |
| 6 | 6 | #include <dt-bindings/interrupt-controller/irq.h> |
| 7 | 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 8 | +#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> | |
| 8 | 9 | #include <dt-bindings/mfd/dbx500-prcmu.h> |
| 9 | 10 | #include <dt-bindings/arm/ux500_pm_domains.h> |
| 10 | 11 | #include <dt-bindings/gpio/gpio.h> |
| @@ -300,6 +301,10 @@ · 289 unmodified lines | ||
| 300 | 301 | #clock-cells = <2>; |
| 301 | 302 | }; |
| 302 | 303 | |
| 304 | + prcc_reset: prcc-reset-controller { | |
| 305 | + #reset-cells = <2>; | |
| 306 | + }; | |
| 307 | + | |
| 303 | 308 | rtc_clk: rtc32k-clock { |
| 304 | 309 | #clock-cells = <0>; |
| 305 | 310 | }; |
| @@ -662,6 +667,7 @@ · 356 unmodified lines | ||
| 662 | 667 | clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; |
| 663 | 668 | clock-names = "i2cclk", "apb_pclk"; |
| 664 | 669 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 670 | + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; | |
| 665 | 671 | |
| 666 | 672 | status = "disabled"; |
| 667 | 673 | }; |
| @@ -680,6 +686,7 @@ · 12 unmodified lines | ||
| 680 | 686 | clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; |
| 681 | 687 | clock-names = "i2cclk", "apb_pclk"; |
| 682 | 688 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 689 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; | |
| 683 | 690 | |
| 684 | 691 | status = "disabled"; |
| 685 | 692 | }; |
| @@ -698,6 +705,7 @@ · 12 unmodified lines | ||
| 698 | 705 | clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; |
| 699 | 706 | clock-names = "i2cclk", "apb_pclk"; |
| 700 | 707 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 708 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; | |
| 701 | 709 | |
| 702 | 710 | status = "disabled"; |
| 703 | 711 | }; |
| @@ -716,6 +724,7 @@ · 12 unmodified lines | ||
| 716 | 724 | clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; |
| 717 | 725 | clock-names = "i2cclk", "apb_pclk"; |
| 718 | 726 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 727 | + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; | |
| 719 | 728 | |
| 720 | 729 | status = "disabled"; |
| 721 | 730 | }; |
| @@ -734,6 +743,7 @@ · 12 unmodified lines | ||
| 734 | 743 | clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; |
| 735 | 744 | clock-names = "i2cclk", "apb_pclk"; |
| 736 | 745 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 746 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; | |
| 737 | 747 | |
| 738 | 748 | status = "disabled"; |
| 739 | 749 | }; |
| @@ -750,6 +760,7 @@ · 10 unmodified lines | ||
| 750 | 760 | <&dma 8 0 0x0>; /* Logical - MemToDev */ |
| 751 | 761 | dma-names = "rx", "tx"; |
| 752 | 762 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 763 | + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; | |
| 753 | 764 | |
| 754 | 765 | status = "disabled"; |
| 755 | 766 | }; |
| @@ -766,6 +777,7 @@ · 10 unmodified lines | ||
| 766 | 777 | <&dma 9 0 0x0>; /* Logical - MemToDev */ |
| 767 | 778 | dma-names = "rx", "tx"; |
| 768 | 779 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 780 | + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; | |
| 769 | 781 | |
| 770 | 782 | status = "disabled"; |
| 771 | 783 | }; |
| @@ -834,6 +846,7 @@ · 62 unmodified lines | ||
| 834 | 846 | <&dma 40 0 0x0>; /* Logical - MemToDev */ |
| 835 | 847 | dma-names = "rx", "tx"; |
| 836 | 848 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 849 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; | |
| 837 | 850 | |
| 838 | 851 | status = "disabled"; |
| 839 | 852 | }; |
| @@ -849,6 +862,7 @@ · 9 unmodified lines | ||
| 849 | 862 | |
| 850 | 863 | clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; |
| 851 | 864 | clock-names = "uart", "apb_pclk"; |
| 865 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; | |
| 852 | 866 | |
| 853 | 867 | status = "disabled"; |
| 854 | 868 | }; |
| @@ -864,6 +878,7 @@ · 9 unmodified lines | ||
| 864 | 878 | |
| 865 | 879 | clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; |
| 866 | 880 | clock-names = "uart", "apb_pclk"; |
| 881 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; | |
| 867 | 882 | |
| 868 | 883 | status = "disabled"; |
| 869 | 884 | }; |
| @@ -879,6 +894,7 @@ · 9 unmodified lines | ||
| 879 | 894 | |
| 880 | 895 | clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; |
| 881 | 896 | clock-names = "uart", "apb_pclk"; |
| 897 | + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; | |
| 882 | 898 | |
| 883 | 899 | status = "disabled"; |
| 884 | 900 | }; |
| @@ -895,6 +911,7 @@ · 10 unmodified lines | ||
| 895 | 911 | clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; |
| 896 | 912 | clock-names = "sdi", "apb_pclk"; |
| 897 | 913 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 914 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; | |
| 898 | 915 | |
| 899 | 916 | status = "disabled"; |
| 900 | 917 | }; |
| @@ -911,6 +928,7 @@ · 10 unmodified lines | ||
| 911 | 928 | clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; |
| 912 | 929 | clock-names = "sdi", "apb_pclk"; |
| 913 | 930 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 931 | + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; | |
| 914 | 932 | |
| 915 | 933 | status = "disabled"; |
| 916 | 934 | }; |
| @@ -927,6 +945,7 @@ · 10 unmodified lines | ||
| 927 | 945 | clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; |
| 928 | 946 | clock-names = "sdi", "apb_pclk"; |
| 929 | 947 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 948 | + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; | |
| 930 | 949 | |
| 931 | 950 | status = "disabled"; |
| 932 | 951 | }; |
| @@ -943,6 +962,7 @@ · 10 unmodified lines | ||
| 943 | 962 | clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; |
| 944 | 963 | clock-names = "sdi", "apb_pclk"; |
| 945 | 964 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 965 | + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; | |
| 946 | 966 | |
| 947 | 967 | status = "disabled"; |
| 948 | 968 | }; |
| @@ -959,6 +979,7 @@ · 10 unmodified lines | ||
| 959 | 979 | clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; |
| 960 | 980 | clock-names = "sdi", "apb_pclk"; |
| 961 | 981 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 982 | + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; | |
| 962 | 983 | |
| 963 | 984 | status = "disabled"; |
| 964 | 985 | }; |
| @@ -975,6 +996,7 @@ · 10 unmodified lines | ||
| 975 | 996 | clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; |
| 976 | 997 | clock-names = "sdi", "apb_pclk"; |
| 977 | 998 | power-domains = <&pm_domains DOMAIN_VAPE>; |
| 999 | + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; | |
| 978 | 1000 | |
| 979 | 1001 | status = "disabled"; |
| 980 | 1002 | }; |
| @@ -996,6 +1018,7 @@ · 15 unmodified lines | ||
| 996 | 1018 | |
| 997 | 1019 | clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; |
| 998 | 1020 | clock-names = "msp", "apb_pclk"; |
| 1021 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; | |
| 999 | 1022 | |
| 1000 | 1023 | status = "disabled"; |
| 1001 | 1024 | }; |
| @@ -1012,6 +1035,7 @@ · 10 unmodified lines | ||
| 1012 | 1035 | |
| 1013 | 1036 | clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; |
| 1014 | 1037 | clock-names = "msp", "apb_pclk"; |
| 1038 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; | |
| 1015 | 1039 | |
| 1016 | 1040 | status = "disabled"; |
| 1017 | 1041 | }; |
| @@ -1030,6 +1054,7 @@ · 12 unmodified lines | ||
| 1030 | 1054 | |
| 1031 | 1055 | clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; |
| 1032 | 1056 | clock-names = "msp", "apb_pclk"; |
| 1057 | + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; | |
| 1033 | 1058 | |
| 1034 | 1059 | status = "disabled"; |
| 1035 | 1060 | }; |
| @@ -1046,6 +1071,7 @@ · 10 unmodified lines | ||
| 1046 | 1071 | |
| 1047 | 1072 | clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; |
| 1048 | 1073 | clock-names = "msp", "apb_pclk"; |
| 1074 | + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; | |
| 1049 | 1075 | |
| 1050 | 1076 | status = "disabled"; |
| 1051 | 1077 | }; |
| @@ -232,19 +232,18 @@ · 231 unmodified lines | ||
| 232 | 232 | #address-cells = <1>; |
| 233 | 233 | #size-cells = <0>; |
| 234 | 234 | |
| 235 | − /* TODO: Memsic MMC328 magnetometer */ | |
| 236 | − magnetometer@30 { | |
| 237 | − compatible = "memsic,mmc328"; | |
| 238 | − reg = <0x30>; | |
| 239 | − /* TODO: if you have the schematic, check if both voltages come from AUX2 */ | |
| 240 | − /* VDA 1.8 V */ | |
| 241 | − vda-supply = <&ab8500_ldo_aux2_reg>; | |
| 242 | − /* VDD 1.8V */ | |
| 243 | − vdd-supply = <&ab8500_ldo_aux2_reg>; | |
| 244 | − /* GPIO204 */ | |
| 235 | + /* Yamaha YAS530 magnetometer */ | |
| 236 | + magnetometer@2e { | |
| 237 | + compatible = "yamaha,yas530"; | |
| 238 | + reg = <0x2e>; | |
| 239 | + /* VDD 3V */ | |
| 240 | + vdd-supply = <&ab8500_ldo_aux1_reg>; | |
| 241 | + /* IOVDD 1.8V */ | |
| 242 | + iovdd-supply = <&ab8500_ldo_aux2_reg>; | |
| 243 | + /* GPIO204 COMPASS_RST_N */ | |
| 245 | 244 | reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; |
| 246 | 245 | pinctrl-names = "default"; |
| 247 | − pinctrl-0 = <&mmc328_default>; | |
| 246 | + pinctrl-0 = <&yas530_default>; | |
| 248 | 247 | }; |
| 249 | 248 | /* TODO: this should also be used by the NCP6914 Camera power management unit */ |
| 250 | 249 | }; |
| @@ -645,6 +644,15 @@ · 394 unmodified lines | ||
| 645 | 644 | }; |
| 646 | 645 | }; |
| 647 | 646 | }; |
| 647 | + /* Reset line for the Yamaha YAS530 magnetometer */ | |
| 648 | + yas530 { | |
| 649 | + yas530_default: yas530_janice { | |
| 650 | + janice_cfg1 { | |
| 651 | + pins = "GPIO204_AF23"; | |
| 652 | + ste,config = <&gpio_out_hi>; | |
| 653 | + }; | |
| 654 | + }; | |
| 655 | + }; | |
| 648 | 656 | /* Flash and torch */ |
| 649 | 657 | flash { |
| 650 | 658 | gpio_flash_default_mode: flash_default { |
| @@ -747,15 +755,6 @@ · 96 unmodified lines | ||
| 747 | 755 | }; |
| 748 | 756 | }; |
| 749 | 757 | }; |
| 750 | − /* Reset line for the Memsic MMC328 magnetometer */ | |
| 751 | − mmc328 { | |
| 752 | − mmc328_default: mmc328_gavini { | |
| 753 | − gavini_cfg1 { | |
| 754 | − pins = "GPIO204_AF23"; | |
| 755 | − ste,config = <&gpio_out_hi>; | |
| 756 | − }; | |
| 757 | − }; | |
| 758 | − }; | |
| 759 | 758 | /* Interrupt line for Invensense MPU3050 gyroscope */ |
| 760 | 759 | mpu3050 { |
| 761 | 760 | mpu3050_default: mpu3050 { |
| @@ -192,7 +192,7 @@ · 191 unmodified lines | ||
| 192 | 192 | |
| 193 | 193 | display: display@1{ |
| 194 | 194 | /* Connect panel-ilitek-9341 to ltdc */ |
| 195 | − compatible = "st,sf-tc240t-9370-t"; | |
| 195 | + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; | |
| 196 | 196 | reg = <1>; |
| 197 | 197 | spi-3wire; |
| 198 | 198 | spi-max-frequency = <10000000>; |
| @@ -1718,7 +1718,7 @@ · 1717 unmodified lines | ||
| 1718 | 1718 | |
| 1719 | 1719 | stusb1600_pins_a: stusb1600-0 { |
| 1720 | 1720 | pins { |
| 1721 | − pinmux = <STM32_PINMUX('I', 11, ANALOG)>; | |
| 1721 | + pinmux = <STM32_PINMUX('I', 11, GPIO)>; | |
| 1722 | 1722 | bias-pull-up; |
| 1723 | 1723 | }; |
| 1724 | 1724 | }; |
| @@ -1737,20 +1737,20 @@ · 12 unmodified lines | ||
| 1737 | 1737 | }; |
| 1738 | 1738 | |
| 1739 | 1739 | uart4_idle_pins_a: uart4-idle-0 { |
| 1740 | − pins1 { | |
| 1741 | − pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ | |
| 1742 | − }; | |
| 1743 | − pins2 { | |
| 1744 | − pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ | |
| 1745 | − bias-disable; | |
| 1746 | − }; | |
| 1740 | + pins1 { | |
| 1741 | + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ | |
| 1742 | + }; | |
| 1743 | + pins2 { | |
| 1744 | + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ | |
| 1745 | + bias-disable; | |
| 1746 | + }; | |
| 1747 | 1747 | }; |
| 1748 | 1748 | |
| 1749 | 1749 | uart4_sleep_pins_a: uart4-sleep-0 { |
| 1750 | − pins { | |
| 1750 | + pins { | |
| 1751 | 1751 | pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ |
| 1752 | 1752 | <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ |
| 1753 | − }; | |
| 1753 | + }; | |
| 1754 | 1754 | }; |
| 1755 | 1755 | |
| 1756 | 1756 | uart4_pins_b: uart4-1 { |
| @@ -1816,7 +1816,7 @@ · 59 unmodified lines | ||
| 1816 | 1816 | }; |
| 1817 | 1817 | pins2 { |
| 1818 | 1818 | pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ |
| 1819 | − bias-disable; | |
| 1819 | + bias-pull-up; | |
| 1820 | 1820 | }; |
| 1821 | 1821 | }; |
| 1822 | 1822 | |
| @@ -1826,7 +1826,7 @@ · 3 unmodified lines | ||
| 1826 | 1826 | }; |
| 1827 | 1827 | pins2 { |
| 1828 | 1828 | pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ |
| 1829 | − bias-disable; | |
| 1829 | + bias-pull-up; | |
| 1830 | 1830 | }; |
| 1831 | 1831 | }; |
| 1832 | 1832 | |
| @@ -1971,7 +1971,7 @@ · 138 unmodified lines | ||
| 1971 | 1971 | pins2 { |
| 1972 | 1972 | pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ |
| 1973 | 1973 | <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ |
| 1974 | − bias-disable; | |
| 1974 | + bias-pull-up; | |
| 1975 | 1975 | }; |
| 1976 | 1976 | }; |
| 1977 | 1977 | |
| @@ -1988,7 +1988,7 @@ · 10 unmodified lines | ||
| 1988 | 1988 | }; |
| 1989 | 1989 | pins3 { |
| 1990 | 1990 | pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ |
| 1991 | − bias-disable; | |
| 1991 | + bias-pull-up; | |
| 1992 | 1992 | }; |
| 1993 | 1993 | }; |
| 1994 | 1994 | |
| @@ -2012,7 +2012,7 @@ · 17 unmodified lines | ||
| 2012 | 2012 | pins2 { |
| 2013 | 2013 | pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ |
| 2014 | 2014 | <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ |
| 2015 | − bias-disable; | |
| 2015 | + bias-pull-up; | |
| 2016 | 2016 | }; |
| 2017 | 2017 | }; |
| 2018 | 2018 | |
| @@ -2029,7 +2029,7 @@ · 10 unmodified lines | ||
| 2029 | 2029 | }; |
| 2030 | 2030 | pins3 { |
| 2031 | 2031 | pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ |
| 2032 | − bias-disable; | |
| 2032 | + bias-pull-up; | |
| 2033 | 2033 | }; |
| 2034 | 2034 | }; |
| 2035 | 2035 | |
| @@ -0,0 +1,132 @@ | ||
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) | |
| 2 | +/* | |
| 3 | + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved | |
| 4 | + * Copyright (c) 2020 Engicam srl | |
| 5 | + * Copyright (c) 2020 Amarula Solutons(India) | |
| 6 | + */ | |
| 7 | + | |
| 8 | +/dts-v1/; | |
| 9 | +#include "stm32mp157.dtsi" | |
| 10 | +#include "stm32mp157a-icore-stm32mp1.dtsi" | |
| 11 | +#include "stm32mp15-pinctrl.dtsi" | |
| 12 | +#include "stm32mp15xxaa-pinctrl.dtsi" | |
| 13 | +#include <dt-bindings/gpio/gpio.h> | |
| 14 | + | |
| 15 | +/ { | |
| 16 | + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; | |
| 17 | + compatible = "engicam,icore-stm32mp1-ctouch2-of10", | |
| 18 | + "engicam,icore-stm32mp1", "st,stm32mp157"; | |
| 19 | + | |
| 20 | + aliases { | |
| 21 | + serial0 = &uart4; | |
| 22 | + }; | |
| 23 | + | |
| 24 | + backlight: backlight { | |
| 25 | + compatible = "gpio-backlight"; | |
| 26 | + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; | |
| 27 | + default-on; | |
| 28 | + }; | |
| 29 | + | |
| 30 | + chosen { | |
| 31 | + stdout-path = "serial0:115200n8"; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + panel { | |
| 35 | + compatible = "ampire,am-1280800n3tzqw-t00h"; | |
| 36 | + backlight = <&backlight>; | |
| 37 | + power-supply = <&v3v3>; | |
| 38 | + | |
| 39 | + port { | |
| 40 | + panel_in_lvds: endpoint { | |
| 41 | + remote-endpoint = <&bridge_out>; | |
| 42 | + }; | |
| 43 | + }; | |
| 44 | + }; | |
| 45 | +}; | |
| 46 | + | |
| 47 | +&dsi { | |
| 48 | + status = "okay"; | |
| 49 | + phy-dsi-supply = <®18>; | |
| 50 | + | |
| 51 | + ports { | |
| 52 | + port@0 { | |
| 53 | + reg = <0>; | |
| 54 | + dsi_in: endpoint { | |
| 55 | + remote-endpoint = <<dc_ep0_out>; | |
| 56 | + }; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + port@1 { | |
| 60 | + reg = <1>; | |
| 61 | + dsi_out: endpoint { | |
| 62 | + remote-endpoint = <&bridge_in>; | |
| 63 | + }; | |
| 64 | + }; | |
| 65 | + }; | |
| 66 | +}; | |
| 67 | + | |
| 68 | +&i2c6 { | |
| 69 | + i2c-scl-falling-time-ns = <20>; | |
| 70 | + i2c-scl-rising-time-ns = <185>; | |
| 71 | + pinctrl-names = "default", "sleep"; | |
| 72 | + pinctrl-0 = <&i2c6_pins_a>; | |
| 73 | + pinctrl-1 = <&i2c6_sleep_pins_a>; | |
| 74 | + status = "okay"; | |
| 75 | + | |
| 76 | + bridge@2c { | |
| 77 | + compatible = "ti,sn65dsi84"; | |
| 78 | + reg = <0x2c>; | |
| 79 | + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; | |
| 80 | + | |
| 81 | + ports { | |
| 82 | + #address-cells = <1>; | |
| 83 | + #size-cells = <0>; | |
| 84 | + | |
| 85 | + port@0 { | |
| 86 | + reg = <0>; | |
| 87 | + bridge_in: endpoint { | |
| 88 | + remote-endpoint = <&dsi_out>; | |
| 89 | + data-lanes = <1 2>; | |
| 90 | + }; | |
| 91 | + }; | |
| 92 | + | |
| 93 | + port@2 { | |
| 94 | + reg = <2>; | |
| 95 | + bridge_out: endpoint { | |
| 96 | + remote-endpoint = <&panel_in_lvds>; | |
| 97 | + }; | |
| 98 | + }; | |
| 99 | + }; | |
| 100 | + }; | |
| 101 | +}; | |
| 102 | + | |
| 103 | +<dc { | |
| 104 | + status = "okay"; | |
| 105 | + | |
| 106 | + port { | |
| 107 | + ltdc_ep0_out: endpoint@0 { | |
| 108 | + reg = <0>; | |
| 109 | + remote-endpoint = <&dsi_in>; | |
| 110 | + }; | |
| 111 | + }; | |
| 112 | +}; | |
| 113 | + | |
| 114 | +&sdmmc1 { | |
| 115 | + bus-width = <4>; | |
| 116 | + disable-wp; | |
| 117 | + pinctrl-names = "default", "opendrain", "sleep"; | |
| 118 | + pinctrl-0 = <&sdmmc1_b4_pins_a>; | |
| 119 | + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; | |
| 120 | + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; | |
| 121 | + st,neg-edge; | |
| 122 | + vmmc-supply = <&v3v3>; | |
| 123 | + status = "okay"; | |
| 124 | +}; | |
| 125 | + | |
| 126 | +&uart4 { | |
| 127 | + pinctrl-names = "default", "sleep", "idle"; | |
| 128 | + pinctrl-0 = <&uart4_pins_a>; | |
| 129 | + pinctrl-1 = <&uart4_sleep_pins_a>; | |
| 130 | + pinctrl-2 = <&uart4_idle_pins_a>; | |
| 131 | + status = "okay"; | |
| 132 | +}; | |
| @@ -24,6 +24,91 @@ · 23 unmodified lines | ||
| 24 | 24 | chosen { |
| 25 | 25 | stdout-path = "serial0:115200n8"; |
| 26 | 26 | }; |
| 27 | + | |
| 28 | + backlight: backlight { | |
| 29 | + compatible = "gpio-backlight"; | |
| 30 | + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; | |
| 31 | + default-on; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + panel { | |
| 35 | + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; | |
| 36 | + backlight = <&backlight>; | |
| 37 | + power-supply = <&v3v3>; | |
| 38 | + | |
| 39 | + port { | |
| 40 | + panel_out_bridge: endpoint { | |
| 41 | + remote-endpoint = <&bridge_out_panel>; | |
| 42 | + }; | |
| 43 | + }; | |
| 44 | + }; | |
| 45 | +}; | |
| 46 | + | |
| 47 | +&dsi { | |
| 48 | + status = "okay"; | |
| 49 | + phy-dsi-supply = <®18>; | |
| 50 | + | |
| 51 | + ports { | |
| 52 | + port@0 { | |
| 53 | + reg = <0>; | |
| 54 | + dsi_in_ltdc: endpoint { | |
| 55 | + remote-endpoint = <<dc_out_dsi>; | |
| 56 | + }; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + port@1 { | |
| 60 | + reg = <1>; | |
| 61 | + dsi_out_bridge: endpoint { | |
| 62 | + remote-endpoint = <&bridge_in_dsi>; | |
| 63 | + }; | |
| 64 | + }; | |
| 65 | + }; | |
| 66 | +}; | |
| 67 | + | |
| 68 | +&i2c6 { | |
| 69 | + i2c-scl-falling-time-ns = <20>; | |
| 70 | + i2c-scl-rising-time-ns = <185>; | |
| 71 | + pinctrl-names = "default", "sleep"; | |
| 72 | + pinctrl-0 = <&i2c6_pins_a>; | |
| 73 | + pinctrl-1 = <&i2c6_sleep_pins_a>; | |
| 74 | + status = "okay"; | |
| 75 | + | |
| 76 | + bridge@2c { | |
| 77 | + compatible = "ti,sn65dsi84"; | |
| 78 | + reg = <0x2c>; | |
| 79 | + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; | |
| 80 | + | |
| 81 | + ports { | |
| 82 | + #address-cells = <1>; | |
| 83 | + #size-cells = <0>; | |
| 84 | + | |
| 85 | + port@0 { | |
| 86 | + reg = <0>; | |
| 87 | + bridge_in_dsi: endpoint { | |
| 88 | + remote-endpoint = <&dsi_out_bridge>; | |
| 89 | + data-lanes = <1 2>; | |
| 90 | + }; | |
| 91 | + }; | |
| 92 | + | |
| 93 | + port@2 { | |
| 94 | + reg = <2>; | |
| 95 | + bridge_out_panel: endpoint { | |
| 96 | + remote-endpoint = <&panel_out_bridge>; | |
| 97 | + }; | |
| 98 | + }; | |
| 99 | + }; | |
| 100 | + }; | |
| 101 | +}; | |
| 102 | + | |
| 103 | +<dc { | |
| 104 | + status = "okay"; | |
| 105 | + | |
| 106 | + port { | |
| 107 | + ltdc_out_dsi: endpoint@0 { | |
| 108 | + reg = <0>; | |
| 109 | + remote-endpoint = <&dsi_in_ltdc>; | |
| 110 | + }; | |
| 111 | + }; | |
| 27 | 112 | }; |
| 28 | 113 | |
| 29 | 114 | &sdmmc1 { |
| @@ -375,3 +375,25 @@ · 374 unmodified lines | ||
| 375 | 375 | &usbphyc { |
| 376 | 376 | status = "okay"; |
| 377 | 377 | }; |
| 378 | + | |
| 379 | +&usbphyc_port0 { | |
| 380 | + st,tune-hs-dc-level = <2>; | |
| 381 | + st,enable-fs-rftime-tuning; | |
| 382 | + st,enable-hs-rftime-reduction; | |
| 383 | + st,trim-hs-current = <15>; | |
| 384 | + st,trim-hs-impedance = <1>; | |
| 385 | + st,tune-squelch-level = <3>; | |
| 386 | + st,tune-hs-rx-offset = <2>; | |
| 387 | + st,no-lsfs-sc; | |
| 388 | +}; | |
| 389 | + | |
| 390 | +&usbphyc_port1 { | |
| 391 | + st,tune-hs-dc-level = <2>; | |
| 392 | + st,enable-fs-rftime-tuning; | |
| 393 | + st,enable-hs-rftime-reduction; | |
| 394 | + st,trim-hs-current = <15>; | |
| 395 | + st,trim-hs-impedance = <1>; | |
| 396 | + st,tune-squelch-level = <3>; | |
| 397 | + st,tune-hs-rx-offset = <2>; | |
| 398 | + st,no-lsfs-sc; | |
| 399 | +}; | |
| @@ -694,10 +694,26 @@ · 693 unmodified lines | ||
| 694 | 694 | |
| 695 | 695 | &usbphyc_port0 { |
| 696 | 696 | phy-supply = <&vdd_usb>; |
| 697 | + st,tune-hs-dc-level = <2>; | |
| 698 | + st,enable-fs-rftime-tuning; | |
| 699 | + st,enable-hs-rftime-reduction; | |
| 700 | + st,trim-hs-current = <15>; | |
| 701 | + st,trim-hs-impedance = <1>; | |
| 702 | + st,tune-squelch-level = <3>; | |
| 703 | + st,tune-hs-rx-offset = <2>; | |
| 704 | + st,no-lsfs-sc; | |
| 697 | 705 | }; |
| 698 | 706 | |
| 699 | 707 | &usbphyc_port1 { |
| 700 | 708 | phy-supply = <&vdd_usb>; |
| 709 | + st,tune-hs-dc-level = <2>; | |
| 710 | + st,enable-fs-rftime-tuning; | |
| 711 | + st,enable-hs-rftime-reduction; | |
| 712 | + st,trim-hs-current = <15>; | |
| 713 | + st,trim-hs-impedance = <1>; | |
| 714 | + st,tune-squelch-level = <3>; | |
| 715 | + st,tune-hs-rx-offset = <2>; | |
| 716 | + st,no-lsfs-sc; | |
| 701 | 717 | }; |
| 702 | 718 | |
| 703 | 719 | &vrefbuf { |
| @@ -52,8 +52,9 @@ · 51 unmodified lines | ||
| 52 | 52 | |
| 53 | 53 | sw4 { |
| 54 | 54 | label = "power"; |
| 55 | − linux,code = <BTN_0>; | |
| 55 | + linux,code = <KEY_POWER>; | |
| 56 | 56 | gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; |
| 57 | + wakeup-source; | |
| 57 | 58 | }; |
| 58 | 59 | }; |
| 59 | 60 | |
| @@ -57,6 +57,12 @@ · 56 unmodified lines | ||
| 57 | 57 | ethernet1 = &sdiowifi; |
| 58 | 58 | }; |
| 59 | 59 | |
| 60 | + cec-gpio { | |
| 61 | + compatible = "cec-gpio"; | |
| 62 | + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ | |
| 63 | + hdmi-phandle = <&hdmi>; | |
| 64 | + }; | |
| 65 | + | |
| 60 | 66 | chosen { |
| 61 | 67 | stdout-path = "serial0:115200n8"; |
| 62 | 68 | }; |
| @@ -87,11 +93,15 @@ · 24 unmodified lines | ||
| 87 | 93 | }; |
| 88 | 94 | }; |
| 89 | 95 | |
| 90 | − wifi_pwrseq: wifi_pwrseq { | |
| 91 | − compatible = "mmc-pwrseq-simple"; | |
| 92 | − reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ | |
| 93 | − clocks = <&rtc 1>; | |
| 94 | − clock-names = "ext_clock"; | |
| 96 | + r-gpio-keys { | |
| 97 | + compatible = "gpio-keys"; | |
| 98 | + | |
| 99 | + power { | |
| 100 | + label = "power"; | |
| 101 | + linux,code = <KEY_POWER>; | |
| 102 | + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; | |
| 103 | + wakeup-source; | |
| 104 | + }; | |
| 95 | 105 | }; |
| 96 | 106 | |
| 97 | 107 | sound_spdif { |
| @@ -112,15 +122,11 @@ · 14 unmodified lines | ||
| 112 | 122 | compatible = "linux,spdif-dit"; |
| 113 | 123 | }; |
| 114 | 124 | |
| 115 | − r-gpio-keys { | |
| 116 | − compatible = "gpio-keys"; | |
| 117 | − | |
| 118 | − power { | |
| 119 | − label = "power"; | |
| 120 | − linux,code = <KEY_POWER>; | |
| 121 | − gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; | |
| 122 | − wakeup-source; | |
| 123 | − }; | |
| 125 | + wifi_pwrseq: wifi_pwrseq { | |
| 126 | + compatible = "mmc-pwrseq-simple"; | |
| 127 | + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ | |
| 128 | + clocks = <&rtc 1>; | |
| 129 | + clock-names = "ext_clock"; | |
| 124 | 130 | }; |
| 125 | 131 | }; |
| 126 | 132 | |
| @@ -81,6 +81,7 @@ · 80 unmodified lines | ||
| 81 | 81 | label = "k1"; |
| 82 | 82 | linux,code = <KEY_POWER>; |
| 83 | 83 | gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; |
| 84 | + wakeup-source; | |
| 84 | 85 | }; |
| 85 | 86 | }; |
| 86 | 87 | }; |
| @@ -99,8 +99,9 @@ · 98 unmodified lines | ||
| 99 | 99 | |
| 100 | 100 | sw4 { |
| 101 | 101 | label = "sw4"; |
| 102 | − linux,code = <BTN_0>; | |
| 102 | + linux,code = <KEY_POWER>; | |
| 103 | 103 | gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; |
| 104 | + wakeup-source; | |
| 104 | 105 | }; |
| 105 | 106 | }; |
| 106 | 107 | |
| @@ -91,8 +91,9 @@ · 90 unmodified lines | ||
| 91 | 91 | |
| 92 | 92 | sw4 { |
| 93 | 93 | label = "sw4"; |
| 94 | − linux,code = <BTN_0>; | |
| 94 | + linux,code = <KEY_POWER>; | |
| 95 | 95 | gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; |
| 96 | + wakeup-source; | |
| 96 | 97 | }; |
| 97 | 98 | }; |
| 98 | 99 | }; |
| @@ -282,6 +282,10 @@ · 281 unmodified lines | ||
| 282 | 282 | compatible = "allwinner,sun8i-h3-de2-clk"; |
| 283 | 283 | }; |
| 284 | 284 | |
| 285 | +&mbus { | |
| 286 | + compatible = "allwinner,sun8i-h3-mbus"; | |
| 287 | +}; | |
| 288 | + | |
| 285 | 289 | &mmc0 { |
| 286 | 290 | compatible = "allwinner,sun7i-a20-mmc"; |
| 287 | 291 | clocks = <&ccu CLK_BUS_MMC0>, |
| @@ -1212,8 +1212,8 @@ · 1211 unmodified lines | ||
| 1212 | 1212 | reg-io-width = <1>; |
| 1213 | 1213 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
| 1214 | 1214 | clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, |
| 1215 | − <&ccu CLK_HDMI>; | |
| 1216 | − clock-names = "iahb", "isfr", "tmds"; | |
| 1215 | + <&ccu CLK_HDMI>, <&rtc 0>; | |
| 1216 | + clock-names = "iahb", "isfr", "tmds", "cec"; | |
| 1217 | 1217 | resets = <&ccu RST_BUS_HDMI1>; |
| 1218 | 1218 | reset-names = "ctrl"; |
| 1219 | 1219 | phys = <&hdmi_phy>; |
| @@ -82,8 +82,9 @@ · 81 unmodified lines | ||
| 82 | 82 | |
| 83 | 83 | sw4 { |
| 84 | 84 | label = "power"; |
| 85 | − linux,code = <BTN_0>; | |
| 85 | + linux,code = <KEY_POWER>; | |
| 86 | 86 | gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; |
| 87 | + wakeup-source; | |
| 87 | 88 | }; |
| 88 | 89 | }; |
| 89 | 90 | |
| @@ -568,9 +568,14 @@ · 567 unmodified lines | ||
| 568 | 568 | }; |
| 569 | 569 | |
| 570 | 570 | mbus: dram-controller@1c62000 { |
| 571 | − compatible = "allwinner,sun8i-h3-mbus"; | |
| 572 | − reg = <0x01c62000 0x1000>; | |
| 573 | − clocks = <&ccu CLK_MBUS>; | |
| 571 | + /* compatible is in per SoC .dtsi file */ | |
| 572 | + reg = <0x01c62000 0x1000>, | |
| 573 | + <0x01c63000 0x1000>; | |
| 574 | + reg-names = "mbus", "dram"; | |
| 575 | + clocks = <&ccu CLK_MBUS>, | |
| 576 | + <&ccu CLK_DRAM>, | |
| 577 | + <&ccu CLK_BUS_DRAM>; | |
| 578 | + clock-names = "mbus", "dram", "bus"; | |
| 574 | 579 | #address-cells = <1>; |
| 575 | 580 | #size-cells = <1>; |
| 576 | 581 | dma-ranges = <0x00000000 0x40000000 0xc0000000>; |
| @@ -813,8 +818,8 @@ · 236 unmodified lines | ||
| 813 | 818 | reg-io-width = <1>; |
| 814 | 819 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| 815 | 820 | clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, |
| 816 | − <&ccu CLK_HDMI>; | |
| 817 | − clock-names = "iahb", "isfr", "tmds"; | |
| 821 | + <&ccu CLK_HDMI>, <&rtc 0>; | |
| 822 | + clock-names = "iahb", "isfr", "tmds", "cec"; | |
| 818 | 823 | resets = <&ccu RST_BUS_HDMI1>; |
| 819 | 824 | reset-names = "ctrl"; |
| 820 | 825 | phys = <&hdmi_phy>; |
| @@ -49,6 +49,7 @@ · 48 unmodified lines | ||
| 49 | 49 | label = "power"; |
| 50 | 50 | linux,code = <KEY_POWER>; |
| 51 | 51 | gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ |
| 52 | + wakeup-source; | |
| 52 | 53 | }; |
| 53 | 54 | }; |
| 54 | 55 | |
| @@ -0,0 +1,807 @@ | ||
| 1 | +// SPDX-License-Identifier: GPL-2.0 | |
| 2 | + | |
| 3 | +/dts-v1/; | |
| 4 | + | |
| 5 | +#include <dt-bindings/input/gpio-keys.h> | |
| 6 | +#include <dt-bindings/input/input.h> | |
| 7 | + | |
| 8 | +#include "tegra114.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + model = "Asus Transformer Pad TF701T"; | |
| 12 | + compatible = "asus,tf701t", "nvidia,tegra114"; | |
| 13 | + chassis-type = "convertible"; | |
| 14 | + | |
| 15 | + aliases { | |
| 16 | + mmc0 = "/mmc@78000600"; /* eMMC */ | |
| 17 | + mmc1 = "/mmc@78000400"; /* uSD slot */ | |
| 18 | + mmc2 = "/mmc@78000000"; /* WiFi */ | |
| 19 | + | |
| 20 | + rtc0 = &palmas; | |
| 21 | + rtc1 = "/rtc@7000e000"; | |
| 22 | + | |
| 23 | + serial0 = &uartd; /* Console */ | |
| 24 | + serial1 = &uartc; /* Bluetooth */ | |
| 25 | + serial2 = &uartb; /* GPS */ | |
| 26 | + }; | |
| 27 | + | |
| 28 | + memory@80000000 { | |
| 29 | + reg = <0x80000000 0x80000000>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + reserved-memory { | |
| 33 | + #address-cells = <1>; | |
| 34 | + #size-cells = <1>; | |
| 35 | + ranges; | |
| 36 | + | |
| 37 | + linux,cma@80000000 { | |
| 38 | + compatible = "shared-dma-pool"; | |
| 39 | + alloc-ranges = <0x80000000 0x30000000>; | |
| 40 | + size = <0x10000000>; | |
| 41 | + linux,cma-default; | |
| 42 | + reusable; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + trustzone@bfe00000 { | |
| 46 | + reg = <0xbfe00000 0x200000>; | |
| 47 | + no-map; | |
| 48 | + }; | |
| 49 | + }; | |
| 50 | + | |
| 51 | + host1x@50000000 { | |
| 52 | + dsi@54300000 { | |
| 53 | + status = "okay"; | |
| 54 | + | |
| 55 | + avdd-dsi-csi-supply = <&tps65913_ldo2>; | |
| 56 | + | |
| 57 | + nvidia,ganged-mode = <&dsib>; | |
| 58 | + | |
| 59 | + panel_primary: panel@0 { | |
| 60 | + compatible = "sharp,lq101r1sx01"; | |
| 61 | + reg = <0>; | |
| 62 | + | |
| 63 | + link2 = <&panel_secondary>; | |
| 64 | + | |
| 65 | + power-supply = <&vdd_lcd>; | |
| 66 | + backlight = <&backlight>; | |
| 67 | + }; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + dsi@54400000 { | |
| 71 | + status = "okay"; | |
| 72 | + | |
| 73 | + avdd-dsi-csi-supply = <&tps65913_ldo2>; | |
| 74 | + | |
| 75 | + panel_secondary: panel@0 { | |
| 76 | + compatible = "sharp,lq101r1sx01"; | |
| 77 | + reg = <0>; | |
| 78 | + }; | |
| 79 | + }; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + pinmux@70000868 { | |
| 83 | + asus_pad_ec_default: asus-pad-ec-default { | |
| 84 | + ec-interrupt { | |
| 85 | + nvidia,pins = "kb_col5_pq5"; | |
| 86 | + nvidia,function = "kbc"; | |
| 87 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 88 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 89 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 90 | + }; | |
| 91 | + | |
| 92 | + ec-request { | |
| 93 | + nvidia,pins = "kb_col2_pq2"; | |
| 94 | + nvidia,function = "kbc"; | |
| 95 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 96 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 97 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 98 | + }; | |
| 99 | + }; | |
| 100 | + | |
| 101 | + backlight_default: backlight-default { | |
| 102 | + backlight-enable { | |
| 103 | + nvidia,pins = "gmi_ad10_ph2"; | |
| 104 | + nvidia,function = "gmi"; | |
| 105 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 106 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 107 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 108 | + }; | |
| 109 | + }; | |
| 110 | + | |
| 111 | + codec_default: codec-default { | |
| 112 | + ldo1-en { | |
| 113 | + nvidia,pins = "sdmmc1_wp_n_pv3"; | |
| 114 | + nvidia,function = "sdmmc1"; | |
| 115 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 116 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 117 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 118 | + }; | |
| 119 | + | |
| 120 | + interrupt { | |
| 121 | + nvidia,pins = "gpio_w2_aud_pw2", | |
| 122 | + "gpio_w3_aud_pw3"; | |
| 123 | + nvidia,function = "spi6"; | |
| 124 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 125 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 126 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 127 | + }; | |
| 128 | + }; | |
| 129 | + | |
| 130 | + gpio_keys_default: gpio-keys-default { | |
| 131 | + power { | |
| 132 | + nvidia,pins = "kb_col0_pq0"; | |
| 133 | + nvidia,function = "kbc"; | |
| 134 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 135 | + nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 136 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 137 | + }; | |
| 138 | + | |
| 139 | + volume { | |
| 140 | + nvidia,pins = "kb_row1_pr1", | |
| 141 | + "kb_row2_pr2"; | |
| 142 | + nvidia,function = "rsvd2"; | |
| 143 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 144 | + nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 145 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 146 | + }; | |
| 147 | + }; | |
| 148 | + | |
| 149 | + gpio_hall_sensor_default: gpio-hall-sensor-default { | |
| 150 | + ulpi_data4_po5 { | |
| 151 | + nvidia,pins = "ulpi_data4_po5"; | |
| 152 | + nvidia,function = "spi2"; | |
| 153 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 154 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 155 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 156 | + }; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + hp_det_default: hp-det-default { | |
| 160 | + gmi_iordy_pi5 { | |
| 161 | + nvidia,pins = "kb_row7_pr7"; | |
| 162 | + nvidia,function = "rsvd2"; | |
| 163 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 164 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 165 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 166 | + }; | |
| 167 | + }; | |
| 168 | + | |
| 169 | + imu_default: imu-default { | |
| 170 | + kb_row3_pr3 { | |
| 171 | + nvidia,pins = "kb_row3_pr3"; | |
| 172 | + nvidia,function = "rsvd3"; | |
| 173 | + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 174 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 175 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 176 | + }; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + pwm_default: pwm-default { | |
| 180 | + gmi_ad9_ph1 { | |
| 181 | + nvidia,pins = "gmi_ad9_ph1"; | |
| 182 | + nvidia,function = "pwm1"; | |
| 183 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 184 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 185 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 186 | + }; | |
| 187 | + }; | |
| 188 | + | |
| 189 | + /* XXX make this something more sensible */ | |
| 190 | + pwm_sleep: pwm-sleep { | |
| 191 | + gmi_ad9_ph1 { | |
| 192 | + nvidia,pins = "gmi_ad9_ph1"; | |
| 193 | + nvidia,function = "pwm1"; | |
| 194 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 195 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 196 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 197 | + }; | |
| 198 | + }; | |
| 199 | + | |
| 200 | + sdmmc3_default: sdmmc3-default { | |
| 201 | + sdmmc3_clk_pa6 { | |
| 202 | + nvidia,pins = "sdmmc3_clk_pa6"; | |
| 203 | + nvidia,function = "sdmmc3"; | |
| 204 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 205 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 206 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 207 | + }; | |
| 208 | + | |
| 209 | + sdmmc3_cmd_pa7 { | |
| 210 | + nvidia,pins = "sdmmc3_cmd_pa7", | |
| 211 | + "sdmmc3_dat0_pb7", | |
| 212 | + "sdmmc3_dat1_pb6", | |
| 213 | + "sdmmc3_dat2_pb5", | |
| 214 | + "sdmmc3_dat3_pb4", | |
| 215 | + "kb_col4_pq4", | |
| 216 | + "sdmmc3_clk_lb_out_pee4", | |
| 217 | + "sdmmc3_clk_lb_in_pee5", | |
| 218 | + "sdmmc3_cd_n_pv2"; | |
| 219 | + nvidia,function = "sdmmc3"; | |
| 220 | + nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 221 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 222 | + nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 223 | + }; | |
| 224 | + | |
| 225 | + drive_sdio3 { | |
| 226 | + nvidia,pins = "drive_sdio3"; | |
| 227 | + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
| 228 | + nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
| 229 | + nvidia,pull-down-strength = <22>; | |
| 230 | + nvidia,pull-up-strength = <36>; | |
| 231 | + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 232 | + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 233 | + }; | |
| 234 | + }; | |
| 235 | + | |
| 236 | + sdmmc3_vdd_default: sdmmc3-vdd-default { | |
| 237 | + gmi_clk_pk1 { | |
| 238 | + nvidia,pins = "gmi_clk_pk1"; | |
| 239 | + nvidia,function = "gmi"; | |
| 240 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 241 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 242 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 243 | + }; | |
| 244 | + }; | |
| 245 | + | |
| 246 | + vdd_lcd_default: vdd-lcd-default { | |
| 247 | + sdmmc4_clk_pcc4 { | |
| 248 | + nvidia,pins = "sdmmc4_clk_pcc4"; | |
| 249 | + nvidia,function = "sdmmc4"; | |
| 250 | + nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 251 | + nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 252 | + nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 253 | + }; | |
| 254 | + }; | |
| 255 | + }; | |
| 256 | + | |
| 257 | + serial@70006040 { | |
| 258 | + /* GPS */ | |
| 259 | + }; | |
| 260 | + | |
| 261 | + serial@70006200 { | |
| 262 | + /* Bluetooth */ | |
| 263 | + }; | |
| 264 | + | |
| 265 | + serial@70006300 { | |
| 266 | + status = "okay"; | |
| 267 | + }; | |
| 268 | + | |
| 269 | + pwm@7000a000 { | |
| 270 | + status = "okay"; | |
| 271 | + | |
| 272 | + pinctrl-names = "default", "sleep"; | |
| 273 | + pinctrl-0 = <&pwm_default>; | |
| 274 | + pinctrl-1 = <&pwm_sleep>; | |
| 275 | + }; | |
| 276 | + | |
| 277 | + i2c@7000c000 { | |
| 278 | + status = "okay"; | |
| 279 | + clock-frequency = <100000>; | |
| 280 | + | |
| 281 | + magnetometer@c { | |
| 282 | + compatible = "asahi-kasei,ak09911"; | |
| 283 | + reg = <0xc>; | |
| 284 | + | |
| 285 | + vdd-supply = <&vdd_3v3_sys>; | |
| 286 | + }; | |
| 287 | + | |
| 288 | + rt5639: audio-codec@1c { | |
| 289 | + compatible = "realtek,rt5639"; | |
| 290 | + reg = <0x1c>; | |
| 291 | + | |
| 292 | + interrupt-parent = <&gpio>; | |
| 293 | + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>; | |
| 294 | + | |
| 295 | + realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; | |
| 296 | + | |
| 297 | + pinctrl-names = "default"; | |
| 298 | + pinctrl-0 = <&codec_default>; | |
| 299 | + }; | |
| 300 | + | |
| 301 | + motion-tracker@68 { | |
| 302 | + compatible = "invensense,mpu6500"; | |
| 303 | + reg = <0x68>; | |
| 304 | + | |
| 305 | + interrupt-parent = <&gpio>; | |
| 306 | + interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>; | |
| 307 | + | |
| 308 | + mount-matrix = "0", "-1", "0", | |
| 309 | + "1", "0", "0", | |
| 310 | + "0", "0", "1"; | |
| 311 | + | |
| 312 | + pinctrl-names = "default"; | |
| 313 | + pinctrl-0 = <&imu_default>; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + temp_sensor: temperature-sensor@4c { | |
| 317 | + compatible = "onnn,nct1008"; | |
| 318 | + reg = <0x4c>; | |
| 319 | + | |
| 320 | + vcc-supply = <&vdd_3v3_sys>; | |
| 321 | + #thermal-sensor-cells = <1>; | |
| 322 | + }; | |
| 323 | + }; | |
| 324 | + | |
| 325 | + i2c@7000c400 { | |
| 326 | + status = "okay"; | |
| 327 | + clock-frequency = <100000>; | |
| 328 | + | |
| 329 | + power-sensor@44 { | |
| 330 | + compatible = "ti,ina230"; | |
| 331 | + reg = <0x44>; | |
| 332 | + }; | |
| 333 | + }; | |
| 334 | + | |
| 335 | + i2c@7000c500 { | |
| 336 | + status = "okay"; | |
| 337 | + clock-frequency = <400000>; | |
| 338 | + | |
| 339 | + light-sensor@1c { | |
| 340 | + compatible = "dynaimage,al3320a"; | |
| 341 | + reg = <0x1c>; | |
| 342 | + | |
| 343 | + vdd-supply = <&vdd_3v3_sys>; | |
| 344 | + }; | |
| 345 | + }; | |
| 346 | + | |
| 347 | + i2c@7000c700 { | |
| 348 | + /* HDMI DDC */ | |
| 349 | + }; | |
| 350 | + | |
| 351 | + i2c@7000d000 { | |
| 352 | + status = "okay"; | |
| 353 | + clock-frequency = <400000>; | |
| 354 | + | |
| 355 | + palmas: pmic@58 { | |
| 356 | + compatible = "ti,tps65913", "ti,palmas"; | |
| 357 | + reg = <0x58>; | |
| 358 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 359 | + | |
| 360 | + #interrupt-cells = <2>; | |
| 361 | + interrupt-controller; | |
| 362 | + | |
| 363 | + ti,system-power-controller; | |
| 364 | + | |
| 365 | + palmas_gpio: gpio { | |
| 366 | + compatible = "ti,palmas-gpio"; | |
| 367 | + gpio-controller; | |
| 368 | + #gpio-cells = <2>; | |
| 369 | + }; | |
| 370 | + | |
| 371 | + pmic { | |
| 372 | + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; | |
| 373 | + | |
| 374 | + ldo1-in-supply = <&tps65913_smps7>; | |
| 375 | + ldo2-in-supply = <&tps65913_smps7>; | |
| 376 | + ldo4-in-supply = <&tps65913_smps8>; | |
| 377 | + ldo5-in-supply = <&tps65913_smps9>; | |
| 378 | + ldo6-in-supply = <&tps65913_smps9>; | |
| 379 | + ldo7-in-supply = <&tps65913_smps9>; | |
| 380 | + ldo9-in-supply = <&tps65913_smps9>; | |
| 381 | + | |
| 382 | + regulators { | |
| 383 | + tps65913_smps123: smps123 { | |
| 384 | + regulator-name = "vdd-cpu"; | |
| 385 | + regulator-min-microvolt = <900000>; | |
| 386 | + regulator-max-microvolt = <1350000>; | |
| 387 | + regulator-always-on; | |
| 388 | + regulator-boot-on; | |
| 389 | + ti,roof-floor = <1>; | |
| 390 | + ti,mode-sleep = <3>; | |
| 391 | + }; | |
| 392 | + | |
| 393 | + tps65913_smps45: smps45 { | |
| 394 | + regulator-name = "vdd-core"; | |
| 395 | + regulator-min-microvolt = <900000>; | |
| 396 | + regulator-max-microvolt = <1400000>; | |
| 397 | + regulator-always-on; | |
| 398 | + regulator-boot-on; | |
| 399 | + ti,roof-floor = <3>; | |
| 400 | + }; | |
| 401 | + | |
| 402 | + smps6 { | |
| 403 | + regulator-name = "va-lcd-hv"; | |
| 404 | + regulator-min-microvolt = <1000000>; | |
| 405 | + regulator-max-microvolt = <1000000>; | |
| 406 | + regulator-always-on; | |
| 407 | + regulator-boot-on; | |
| 408 | + }; | |
| 409 | + | |
| 410 | + tps65913_smps7: smps7 { | |
| 411 | + regulator-name = "vdd-ddr"; | |
| 412 | + regulator-min-microvolt = <1350000>; | |
| 413 | + regulator-max-microvolt = <1350000>; | |
| 414 | + regulator-always-on; | |
| 415 | + regulator-boot-on; | |
| 416 | + }; | |
| 417 | + | |
| 418 | + tps65913_smps8: smps8 { | |
| 419 | + regulator-name = "vdd-1v8"; | |
| 420 | + regulator-min-microvolt = <1800000>; | |
| 421 | + regulator-max-microvolt = <1800000>; | |
| 422 | + regulator-always-on; | |
| 423 | + regulator-boot-on; | |
| 424 | + }; | |
| 425 | + | |
| 426 | + tps65913_smps9: smps9 { | |
| 427 | + regulator-name = "vdd-sd"; | |
| 428 | + regulator-min-microvolt = <2900000>; | |
| 429 | + regulator-max-microvolt = <2900000>; | |
| 430 | + regulator-always-on; | |
| 431 | + }; | |
| 432 | + | |
| 433 | + tps65913_smps10_out1: smps10_out1 { | |
| 434 | + regulator-name = "vd-smps10-out1"; | |
| 435 | + regulator-min-microvolt = <5000000>; | |
| 436 | + regulator-max-microvolt = <5000000>; | |
| 437 | + regulator-always-on; | |
| 438 | + regulator-boot-on; | |
| 439 | + }; | |
| 440 | + | |
| 441 | + tps65913_smps10_out2: smps10_out2 { | |
| 442 | + regulator-name = "vd-smps10-out2"; | |
| 443 | + regulator-min-microvolt = <5000000>; | |
| 444 | + regulator-max-microvolt = <5000000>; | |
| 445 | + regulator-always-on; | |
| 446 | + regulator-boot-on; | |
| 447 | + }; | |
| 448 | + | |
| 449 | + tps65913_ldo1: ldo1 { | |
| 450 | + regulator-name = "vdd-hdmi-pll"; | |
| 451 | + regulator-min-microvolt = <1050000>; | |
| 452 | + regulator-max-microvolt = <1050000>; | |
| 453 | + regulator-always-on; | |
| 454 | + ti,roof-floor = <3>; | |
| 455 | + }; | |
| 456 | + | |
| 457 | + tps65913_ldo2: ldo2 { | |
| 458 | + regulator-name = "vdd-2v8-dsi-csi"; | |
| 459 | + regulator-min-microvolt = <1200000>; | |
| 460 | + regulator-max-microvolt = <1200000>; | |
| 461 | + regulator-boot-on; | |
| 462 | + }; | |
| 463 | + | |
| 464 | + ldo3 { | |
| 465 | + regulator-name = "vpp-fuse"; | |
| 466 | + regulator-min-microvolt = <1800000>; | |
| 467 | + regulator-max-microvolt = <1800000>; | |
| 468 | + }; | |
| 469 | + | |
| 470 | + ldo4 { | |
| 471 | + regulator-name = "vdd-1v2-cam"; | |
| 472 | + regulator-min-microvolt = <1200000>; | |
| 473 | + regulator-max-microvolt = <1200000>; | |
| 474 | + }; | |
| 475 | + | |
| 476 | + ldo5 { | |
| 477 | + regulator-name = "vdd-cam"; | |
| 478 | + regulator-min-microvolt = <2800000>; | |
| 479 | + regulator-max-microvolt = <2800000>; | |
| 480 | + }; | |
| 481 | + | |
| 482 | + ldo6 { | |
| 483 | + regulator-name = "vdd-dev"; | |
| 484 | + regulator-min-microvolt = <2850000>; | |
| 485 | + regulator-max-microvolt = <2850000>; | |
| 486 | + regulator-boot-on; | |
| 487 | + }; | |
| 488 | + | |
| 489 | + ldo7 { | |
| 490 | + regulator-name = "vdd-2v8-cam"; | |
| 491 | + regulator-min-microvolt = <2800000>; | |
| 492 | + regulator-max-microvolt = <2800000>; | |
| 493 | + }; | |
| 494 | + | |
| 495 | + tps65913_ldo8: ldo8 { | |
| 496 | + regulator-name = "vdd-rtc"; | |
| 497 | + regulator-min-microvolt = <950000>; | |
| 498 | + regulator-max-microvolt = <950000>; | |
| 499 | + regulator-always-on; | |
| 500 | + regulator-boot-on; | |
| 501 | + ti,enable-ldo8-tracking; | |
| 502 | + }; | |
| 503 | + | |
| 504 | + tps65913_ldo9: ldo9 { | |
| 505 | + regulator-name = "vdd-sdmmc"; | |
| 506 | + regulator-min-microvolt = <1800000>; | |
| 507 | + regulator-max-microvolt = <2900000>; | |
| 508 | + }; | |
| 509 | + | |
| 510 | + tps65913_ldoln: ldoln { | |
| 511 | + regulator-name = "vdd-hdmi"; | |
| 512 | + regulator-min-microvolt = <3300000>; | |
| 513 | + regulator-max-microvolt = <3300000>; | |
| 514 | + }; | |
| 515 | + | |
| 516 | + ldousb { | |
| 517 | + regulator-name = "vdd-usb"; | |
| 518 | + regulator-min-microvolt = <3300000>; | |
| 519 | + regulator-max-microvolt = <3300000>; | |
| 520 | + regulator-always-on; | |
| 521 | + regulator-boot-on; | |
| 522 | + }; | |
| 523 | + }; | |
| 524 | + }; | |
| 525 | + | |
| 526 | + rtc { | |
| 527 | + compatible = "ti,palmas-rtc"; | |
| 528 | + interrupt-parent = <&palmas>; | |
| 529 | + interrupts = <8 0>; | |
| 530 | + }; | |
| 531 | + | |
| 532 | + pinmux { | |
| 533 | + compatible = "ti,tps65913-pinctrl"; | |
| 534 | + ti,palmas-enable-dvfs1; | |
| 535 | + | |
| 536 | + pinctrl-names = "default"; | |
| 537 | + pinctrl-0 = <&palmas_default>; | |
| 538 | + | |
| 539 | + palmas_default: pinmux { | |
| 540 | + pin_powergood { | |
| 541 | + pins = "powergood"; | |
| 542 | + function = "powergood"; | |
| 543 | + }; | |
| 544 | + | |
| 545 | + pin_vac { | |
| 546 | + pins = "vac"; | |
| 547 | + function = "vac"; | |
| 548 | + }; | |
| 549 | + | |
| 550 | + pin_gpio0 { | |
| 551 | + pins = "gpio0"; | |
| 552 | + function = "gpio"; | |
| 553 | + }; | |
| 554 | + | |
| 555 | + pin_gpio1 { | |
| 556 | + pins = "gpio1"; | |
| 557 | + function = "gpio"; | |
| 558 | + }; | |
| 559 | + | |
| 560 | + pin_gpio2 { | |
| 561 | + pins = "gpio2"; | |
| 562 | + function = "gpio"; | |
| 563 | + }; | |
| 564 | + | |
| 565 | + pin_gpio3 { | |
| 566 | + pins = "gpio3"; | |
| 567 | + function = "gpio"; | |
| 568 | + }; | |
| 569 | + | |
| 570 | + pin_gpio4 { | |
| 571 | + pins = "gpio4"; | |
| 572 | + function = "gpio"; | |
| 573 | + }; | |
| 574 | + | |
| 575 | + pin_gpio5 { | |
| 576 | + pins = "gpio5"; | |
| 577 | + function = "gpio"; | |
| 578 | + }; | |
| 579 | + | |
| 580 | + pin_gpio6 { | |
| 581 | + pins = "gpio6"; | |
| 582 | + function = "gpio"; | |
| 583 | + }; | |
| 584 | + | |
| 585 | + pin_gpio7 { | |
| 586 | + pins = "gpio7"; | |
| 587 | + function = "gpio"; | |
| 588 | + }; | |
| 589 | + }; | |
| 590 | + }; | |
| 591 | + }; | |
| 592 | + }; | |
| 593 | + | |
| 594 | + ahub@70080000 { | |
| 595 | + i2s@70080300 { | |
| 596 | + status = "okay"; | |
| 597 | + }; | |
| 598 | + }; | |
| 599 | + | |
| 600 | + mmc@78000000 { | |
| 601 | + /* WiFi */ | |
| 602 | + }; | |
| 603 | + | |
| 604 | + /* MicroSD card */ | |
| 605 | + mmc@78000400 { | |
| 606 | + status = "okay"; | |
| 607 | + | |
| 608 | + bus-width = <4>; | |
| 609 | + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
| 610 | + | |
| 611 | + nvidia,default-tap = <0x3>; | |
| 612 | + nvidia,default-trim = <0x3>; | |
| 613 | + | |
| 614 | + vmmc-supply = <&vdd_usd>; | |
| 615 | + vqmmc-supply = <&tps65913_ldo9>; | |
| 616 | + | |
| 617 | + pinctrl-names = "default"; | |
| 618 | + pinctrl-0 = <&sdmmc3_default>; | |
| 619 | + }; | |
| 620 | + | |
| 621 | + mmc@78000600 { | |
| 622 | + /* eMMC */ | |
| 623 | + }; | |
| 624 | + | |
| 625 | + usb@7d000000 { | |
| 626 | + compatible = "nvidia,tegra114-udc"; | |
| 627 | + status = "okay"; | |
| 628 | + dr_mode = "peripheral"; | |
| 629 | + | |
| 630 | + /* Peripheral USB via ASUS connector */ | |
| 631 | + }; | |
| 632 | + | |
| 633 | + usb-phy@7d000000 { | |
| 634 | + status = "okay"; | |
| 635 | + }; | |
| 636 | + | |
| 637 | + usb@7d008000 { | |
| 638 | + status = "okay"; | |
| 639 | + | |
| 640 | + /* Host USB via dock */ | |
| 641 | + }; | |
| 642 | + | |
| 643 | + usb-phy@7d008000 { | |
| 644 | + status = "okay"; | |
| 645 | + vbus-supply = <&vdd_5v0_sys>; | |
| 646 | + }; | |
| 647 | + | |
| 648 | + backlight: backlight { | |
| 649 | + compatible = "pwm-backlight"; | |
| 650 | + | |
| 651 | + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | |
| 652 | + power-supply = <&vdd_5v0_sys>; | |
| 653 | + pwms = <&pwm 1 1000000>; | |
| 654 | + | |
| 655 | + brightness-levels = <1 255>; | |
| 656 | + num-interpolated-steps = <254>; | |
| 657 | + default-brightness-level = <224>; | |
| 658 | + | |
| 659 | + pinctrl-names = "default"; | |
| 660 | + pinctrl-0 = <&backlight_default>; | |
| 661 | + }; | |
| 662 | + | |
| 663 | + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ | |
| 664 | + clk32k_in: clock-32k { | |
| 665 | + compatible = "fixed-clock"; | |
| 666 | + #clock-cells = <0>; | |
| 667 | + clock-frequency = <32768>; | |
| 668 | + clock-output-names = "pmic-oscillator"; | |
| 669 | + }; | |
| 670 | + | |
| 671 | + firmware { | |
| 672 | + trusted-foundations { | |
| 673 | + compatible = "tlm,trusted-foundations"; | |
| 674 | + tlm,version-major = <2>; | |
| 675 | + tlm,version-minor = <8>; | |
| 676 | + }; | |
| 677 | + }; | |
| 678 | + | |
| 679 | + gpio-keys { | |
| 680 | + compatible = "gpio-keys"; | |
| 681 | + | |
| 682 | + label = "GPIO Buttons"; | |
| 683 | + | |
| 684 | + pinctrl-names = "default"; | |
| 685 | + pinctrl-0 = <&gpio_keys_default>; | |
| 686 | + | |
| 687 | + power { | |
| 688 | + label = "Power"; | |
| 689 | + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
| 690 | + linux,code = <KEY_POWER>; | |
| 691 | + debounce-interval = <10>; | |
| 692 | + wakeup-source; | |
| 693 | + }; | |
| 694 | + | |
| 695 | + volume-up { | |
| 696 | + label = "Volume Up"; | |
| 697 | + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; | |
| 698 | + linux,code = <KEY_VOLUMEUP>; | |
| 699 | + debounce-interval = <10>; | |
| 700 | + }; | |
| 701 | + | |
| 702 | + volume-down { | |
| 703 | + label = "Volume Down"; | |
| 704 | + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; | |
| 705 | + linux,code = <KEY_VOLUMEDOWN>; | |
| 706 | + debounce-interval = <10>; | |
| 707 | + }; | |
| 708 | + }; | |
| 709 | + | |
| 710 | + gpio-hall-sensor { | |
| 711 | + compatible = "gpio-keys"; | |
| 712 | + | |
| 713 | + label = "GPIO Hall Effect Sensor"; | |
| 714 | + | |
| 715 | + pinctrl-names = "default"; | |
| 716 | + pinctrl-0 = <&gpio_hall_sensor_default>; | |
| 717 | + | |
| 718 | + hall-sensor { | |
| 719 | + label = "Hall Effect Sensor"; | |
| 720 | + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; | |
| 721 | + linux,input-type = <EV_SW>; | |
| 722 | + linux,code = <SW_LID>; | |
| 723 | + linux,can-disable; | |
| 724 | + wakeup-source; | |
| 725 | + }; | |
| 726 | + }; | |
| 727 | + | |
| 728 | + sound { | |
| 729 | + compatible = "asus,tegra-audio-rt5639-tf701t", | |
| 730 | + "nvidia,tegra-audio-rt5640"; | |
| 731 | + nvidia,model = "Asus Transformer Pad TF701T RT5639"; | |
| 732 | + | |
| 733 | + nvidia,audio-routing = | |
| 734 | + "Headphones", "HPOR", | |
| 735 | + "Headphones", "HPOL", | |
| 736 | + "Speakers", "SPORP", | |
| 737 | + "Speakers", "SPORN", | |
| 738 | + "Speakers", "SPOLP", | |
| 739 | + "Speakers", "SPOLN", | |
| 740 | + "Mic Jack", "MICBIAS1", | |
| 741 | + "IN2P", "Mic Jack"; | |
| 742 | + | |
| 743 | + nvidia,i2s-controller = <&tegra_i2s0>; | |
| 744 | + nvidia,audio-codec = <&rt5639>; | |
| 745 | + | |
| 746 | + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; | |
| 747 | + | |
| 748 | + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, | |
| 749 | + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, | |
| 750 | + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; | |
| 751 | + clock-names = "pll_a", "pll_a_out0", "mclk"; | |
| 752 | + | |
| 753 | + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, | |
| 754 | + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; | |
| 755 | + | |
| 756 | + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, | |
| 757 | + <&tegra_car TEGRA114_CLK_EXTERN1>; | |
| 758 | + | |
| 759 | + pinctrl-names = "default"; | |
| 760 | + pinctrl-0 = <&hp_det_default>; | |
| 761 | + }; | |
| 762 | + | |
| 763 | + vdd_5v0_sys: regulator-5v0-sys { | |
| 764 | + compatible = "regulator-fixed"; | |
| 765 | + regulator-name = "vdd_5v0"; | |
| 766 | + regulator-min-microvolt = <5000000>; | |
| 767 | + regulator-max-microvolt = <5000000>; | |
| 768 | + regulator-always-on; | |
| 769 | + regulator-boot-on; | |
| 770 | + }; | |
| 771 | + | |
| 772 | + vdd_3v3_sys: regulator-3v3-sys { | |
| 773 | + compatible = "regulator-fixed"; | |
| 774 | + regulator-name = "vdd_3v3"; | |
| 775 | + regulator-min-microvolt = <3300000>; | |
| 776 | + regulator-max-microvolt = <3300000>; | |
| 777 | + regulator-always-on; | |
| 778 | + regulator-boot-on; | |
| 779 | + }; | |
| 780 | + | |
| 781 | + vdd_lcd: regulator-vdd-lcd { | |
| 782 | + compatible = "regulator-fixed"; | |
| 783 | + regulator-name = "vdd_lcd_1v8"; | |
| 784 | + regulator-min-microvolt = <1800000>; | |
| 785 | + regulator-max-microvolt = <1800000>; | |
| 786 | + vin-supply = <&tps65913_smps8>; | |
| 787 | + enable-active-high; | |
| 788 | + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; | |
| 789 | + regulator-boot-on; | |
| 790 | + | |
| 791 | + pinctrl-names = "default"; | |
| 792 | + pinctrl-0 = <&vdd_lcd_default>; | |
| 793 | + }; | |
| 794 | + | |
| 795 | + vdd_usd: regulator-vdd-usd { | |
| 796 | + compatible = "regulator-fixed"; | |
| 797 | + regulator-name = "vdd_sd_slot"; | |
| 798 | + regulator-min-microvolt = <2900000>; | |
| 799 | + regulator-max-microvolt = <2900000>; | |
| 800 | + vin-supply = <&tps65913_smps9>; | |
| 801 | + enable-active-high; | |
| 802 | + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; | |
| 803 | + | |
| 804 | + pinctrl-names = "default"; | |
| 805 | + pinctrl-0 = <&sdmmc3_vdd_default>; | |
| 806 | + }; | |
| 807 | +}; | |
| @@ -894,7 +894,7 @@ · 893 unmodified lines | ||
| 894 | 894 | }; |
| 895 | 895 | |
| 896 | 896 | palmas: tps65913@58 { |
| 897 | − compatible = "ti,palmas"; | |
| 897 | + compatible = "ti,tps65913", "ti,palmas"; | |
| 898 | 898 | reg = <0x58>; |
| 899 | 899 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 900 | 900 | |
| @@ -1084,7 +1084,8 @@ · 183 unmodified lines | ||
| 1084 | 1084 | spi@7000da00 { |
| 1085 | 1085 | status = "okay"; |
| 1086 | 1086 | spi-max-frequency = <25000000>; |
| 1087 | − spi-flash@0 { | |
| 1087 | + | |
| 1088 | + flash@0 { | |
| 1088 | 1089 | compatible = "winbond,w25q32dw", "jedec,spi-nor"; |
| 1089 | 1090 | reg = <0>; |
| 1090 | 1091 | spi-max-frequency = <20000000>; |
| @@ -1151,7 +1152,7 @@ · 60 unmodified lines | ||
| 1151 | 1152 | default-brightness-level = <6>; |
| 1152 | 1153 | }; |
| 1153 | 1154 | |
| 1154 | − clk32k_in: clock@0 { | |
| 1155 | + clk32k_in: clock-32k { | |
| 1155 | 1156 | compatible = "fixed-clock"; |
| 1156 | 1157 | clock-frequency = <32768>; |
| 1157 | 1158 | #clock-cells = <0>; |
| @@ -1186,7 +1187,7 @@ · 28 unmodified lines | ||
| 1186 | 1187 | }; |
| 1187 | 1188 | }; |
| 1188 | 1189 | |
| 1189 | − vdd_ac_bat_reg: regulator@0 { | |
| 1190 | + vdd_ac_bat_reg: regulator-acbat { | |
| 1190 | 1191 | compatible = "regulator-fixed"; |
| 1191 | 1192 | regulator-name = "vdd_ac_bat"; |
| 1192 | 1193 | regulator-min-microvolt = <5000000>; |
| @@ -1194,7 +1195,7 @@ · 1 unmodified line | ||
| 1194 | 1195 | regulator-always-on; |
| 1195 | 1196 | }; |
| 1196 | 1197 | |
| 1197 | − dvdd_ts_reg: regulator@1 { | |
| 1198 | + dvdd_ts_reg: regulator-ts { | |
| 1198 | 1199 | compatible = "regulator-fixed"; |
| 1199 | 1200 | regulator-name = "dvdd_ts"; |
| 1200 | 1201 | regulator-min-microvolt = <1800000>; |
| @@ -1203,7 +1204,7 @@ · 2 unmodified lines | ||
| 1203 | 1204 | gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; |
| 1204 | 1205 | }; |
| 1205 | 1206 | |
| 1206 | − usb1_vbus_reg: regulator@3 { | |
| 1207 | + usb1_vbus_reg: regulator-usb1 { | |
| 1207 | 1208 | compatible = "regulator-fixed"; |
| 1208 | 1209 | regulator-name = "usb1_vbus"; |
| 1209 | 1210 | regulator-min-microvolt = <5000000>; |
| @@ -1214,7 +1215,7 @@ · 4 unmodified lines | ||
| 1214 | 1215 | vin-supply = <&tps65090_dcdc1_reg>; |
| 1215 | 1216 | }; |
| 1216 | 1217 | |
| 1217 | − usb3_vbus_reg: regulator@4 { | |
| 1218 | + usb3_vbus_reg: regulator-usb3 { | |
| 1218 | 1219 | compatible = "regulator-fixed"; |
| 1219 | 1220 | regulator-name = "usb2_vbus"; |
| 1220 | 1221 | regulator-min-microvolt = <5000000>; |
| @@ -1225,7 +1226,7 @@ · 4 unmodified lines | ||
| 1225 | 1226 | vin-supply = <&tps65090_dcdc1_reg>; |
| 1226 | 1227 | }; |
| 1227 | 1228 | |
| 1228 | − vdd_hdmi_reg: regulator@5 { | |
| 1229 | + vdd_hdmi_reg: regulator-hdmi { | |
| 1229 | 1230 | compatible = "regulator-fixed"; |
| 1230 | 1231 | regulator-name = "vdd_hdmi_5v0"; |
| 1231 | 1232 | regulator-min-microvolt = <5000000>; |
| @@ -1233,7 +1234,7 @@ · 1 unmodified line | ||
| 1233 | 1234 | vin-supply = <&tps65090_dcdc1_reg>; |
| 1234 | 1235 | }; |
| 1235 | 1236 | |
| 1236 | − vdd_cam_1v8_reg: regulator@6 { | |
| 1237 | + vdd_cam_1v8_reg: regulator-cam { | |
| 1237 | 1238 | compatible = "regulator-fixed"; |
| 1238 | 1239 | regulator-name = "vdd_cam_1v8_reg"; |
| 1239 | 1240 | regulator-min-microvolt = <1800000>; |
| @@ -1242,7 +1243,7 @@ · 2 unmodified lines | ||
| 1242 | 1243 | gpio = <&palmas_gpio 6 0>; |
| 1243 | 1244 | }; |
| 1244 | 1245 | |
| 1245 | − vdd_5v0_hdmi: regulator@7 { | |
| 1246 | + vdd_5v0_hdmi: regulator-hdmicon { | |
| 1246 | 1247 | compatible = "regulator-fixed"; |
| 1247 | 1248 | regulator-name = "VDD_5V0_HDMI_CON"; |
| 1248 | 1249 | regulator-min-microvolt = <5000000>; |
| @@ -801,7 +801,7 @@ · 800 unmodified lines | ||
| 801 | 801 | }; |
| 802 | 802 | |
| 803 | 803 | palmas: pmic@58 { |
| 804 | − compatible = "ti,palmas"; | |
| 804 | + compatible = "ti,tps65913", "ti,palmas"; | |
| 805 | 805 | reg = <0x58>; |
| 806 | 806 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 807 | 807 | |
| @@ -1016,7 +1016,7 @@ · 208 unmodified lines | ||
| 1016 | 1016 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 1017 | 1017 | }; |
| 1018 | 1018 | |
| 1019 | − clk32k_in: clock@0 { | |
| 1019 | + clk32k_in: clock-32k { | |
| 1020 | 1020 | compatible = "fixed-clock"; |
| 1021 | 1021 | clock-frequency = <32768>; |
| 1022 | 1022 | #clock-cells = <0>; |
| @@ -1045,7 +1045,7 @@ · 22 unmodified lines | ||
| 1045 | 1045 | }; |
| 1046 | 1046 | }; |
| 1047 | 1047 | |
| 1048 | − lcd_bl_en: regulator@0 { | |
| 1048 | + lcd_bl_en: regulator-lcden { | |
| 1049 | 1049 | compatible = "regulator-fixed"; |
| 1050 | 1050 | regulator-name = "lcd_bl_en"; |
| 1051 | 1051 | regulator-min-microvolt = <5000000>; |
| @@ -1053,7 +1053,7 @@ · 1 unmodified line | ||
| 1053 | 1053 | regulator-boot-on; |
| 1054 | 1054 | }; |
| 1055 | 1055 | |
| 1056 | − vdd_lcd: regulator@1 { | |
| 1056 | + vdd_lcd: regulator-lcd { | |
| 1057 | 1057 | compatible = "regulator-fixed"; |
| 1058 | 1058 | regulator-name = "vdd_lcd_1v8"; |
| 1059 | 1059 | regulator-min-microvolt = <1800000>; |
| @@ -1064,7 +1064,7 @@ · 4 unmodified lines | ||
| 1064 | 1064 | regulator-boot-on; |
| 1065 | 1065 | }; |
| 1066 | 1066 | |
| 1067 | − regulator@2 { | |
| 1067 | + regulator-1v8ts { | |
| 1068 | 1068 | compatible = "regulator-fixed"; |
| 1069 | 1069 | regulator-name = "vdd_1v8_ts"; |
| 1070 | 1070 | regulator-min-microvolt = <1800000>; |
| @@ -1073,7 +1073,7 @@ · 2 unmodified lines | ||
| 1073 | 1073 | regulator-boot-on; |
| 1074 | 1074 | }; |
| 1075 | 1075 | |
| 1076 | − regulator@3 { | |
| 1076 | + regulator-3v3ts { | |
| 1077 | 1077 | compatible = "regulator-fixed"; |
| 1078 | 1078 | regulator-name = "vdd_3v3_ts"; |
| 1079 | 1079 | regulator-min-microvolt = <3300000>; |
| @@ -1083,7 +1083,7 @@ · 3 unmodified lines | ||
| 1083 | 1083 | regulator-boot-on; |
| 1084 | 1084 | }; |
| 1085 | 1085 | |
| 1086 | − regulator@4 { | |
| 1086 | + regulator-1v8com { | |
| 1087 | 1087 | compatible = "regulator-fixed"; |
| 1088 | 1088 | regulator-name = "vdd_1v8_com"; |
| 1089 | 1089 | regulator-min-microvolt = <1800000>; |
| @@ -1094,7 +1094,7 @@ · 4 unmodified lines | ||
| 1094 | 1094 | regulator-boot-on; |
| 1095 | 1095 | }; |
| 1096 | 1096 | |
| 1097 | − regulator@5 { | |
| 1097 | + regulator-3v3com { | |
| 1098 | 1098 | compatible = "regulator-fixed"; |
| 1099 | 1099 | regulator-name = "vdd_3v3_com"; |
| 1100 | 1100 | regulator-min-microvolt = <3300000>; |
| @@ -62,7 +62,7 @@ · 61 unmodified lines | ||
| 62 | 62 | clock-frequency = <400000>; |
| 63 | 63 | |
| 64 | 64 | palmas: pmic@58 { |
| 65 | − compatible = "ti,palmas"; | |
| 65 | + compatible = "ti,tps65913", "ti,palmas"; | |
| 66 | 66 | reg = <0x58>; |
| 67 | 67 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 68 | 68 | |
| @@ -273,7 +273,7 @@ · 204 unmodified lines | ||
| 273 | 273 | power-supply = <&lcd_bl_en>; |
| 274 | 274 | }; |
| 275 | 275 | |
| 276 | − clk32k_in: clock@0 { | |
| 276 | + clk32k_in: clock-32k { | |
| 277 | 277 | compatible = "fixed-clock"; |
| 278 | 278 | clock-frequency = <32768>; |
| 279 | 279 | #clock-cells = <0>; |
| @@ -303,7 +303,7 @@ · 23 unmodified lines | ||
| 303 | 303 | }; |
| 304 | 304 | |
| 305 | 305 | /* FIXME: output of BQ24192 */ |
| 306 | − vs_sys: regulator@0 { | |
| 306 | + vs_sys: regulator-vs { | |
| 307 | 307 | compatible = "regulator-fixed"; |
| 308 | 308 | regulator-name = "VS_SYS"; |
| 309 | 309 | regulator-min-microvolt = <4200000>; |
| @@ -312,7 +312,7 @@ · 2 unmodified lines | ||
| 312 | 312 | regulator-boot-on; |
| 313 | 313 | }; |
| 314 | 314 | |
| 315 | − lcd_bl_en: regulator@1 { | |
| 315 | + lcd_bl_en: regulator-lcden { | |
| 316 | 316 | compatible = "regulator-fixed"; |
| 317 | 317 | regulator-name = "VDD_LCD_BL"; |
| 318 | 318 | regulator-min-microvolt = <16500000>; |
| @@ -323,7 +323,7 @@ · 4 unmodified lines | ||
| 323 | 323 | regulator-boot-on; |
| 324 | 324 | }; |
| 325 | 325 | |
| 326 | − vdd_lcd: regulator@2 { | |
| 326 | + vdd_lcd: regulator-lcd { | |
| 327 | 327 | compatible = "regulator-fixed"; |
| 328 | 328 | regulator-name = "VD_LCD_1V8"; |
| 329 | 329 | regulator-min-microvolt = <1800000>; |
| @@ -17,6 +17,19 @@ · 16 unmodified lines | ||
| 17 | 17 | reg = <0x80000000 0x0>; |
| 18 | 18 | }; |
| 19 | 19 | |
| 20 | + sram@40000000 { | |
| 21 | + compatible = "mmio-sram"; | |
| 22 | + reg = <0x40000000 0x40000>; | |
| 23 | + #address-cells = <1>; | |
| 24 | + #size-cells = <1>; | |
| 25 | + ranges = <0 0x40000000 0x40000>; | |
| 26 | + | |
| 27 | + vde_pool: sram@400 { | |
| 28 | + reg = <0x400 0x3fc00>; | |
| 29 | + pool; | |
| 30 | + }; | |
| 31 | + }; | |
| 32 | + | |
| 20 | 33 | host1x@50000000 { |
| 21 | 34 | compatible = "nvidia,tegra114-host1x"; |
| 22 | 35 | reg = <0x50000000 0x00028000>; |
| @@ -25,8 +38,8 @@ · 2 unmodified lines | ||
| 25 | 38 | interrupt-names = "syncpt", "host1x"; |
| 26 | 39 | clocks = <&tegra_car TEGRA114_CLK_HOST1X>; |
| 27 | 40 | clock-names = "host1x"; |
| 28 | − resets = <&tegra_car 28>; | |
| 29 | − reset-names = "host1x"; | |
| 41 | + resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; | |
| 42 | + reset-names = "host1x", "mc"; | |
| 30 | 43 | iommus = <&mc TEGRA_SWGROUP_HC>; |
| 31 | 44 | |
| 32 | 45 | #address-cells = <1>; |
| @@ -39,8 +52,8 @@ · 6 unmodified lines | ||
| 39 | 52 | reg = <0x54140000 0x00040000>; |
| 40 | 53 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 41 | 54 | clocks = <&tegra_car TEGRA114_CLK_GR2D>; |
| 42 | − resets = <&tegra_car 21>; | |
| 43 | − reset-names = "2d"; | |
| 55 | + resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; | |
| 56 | + reset-names = "2d", "mc"; | |
| 44 | 57 | |
| 45 | 58 | iommus = <&mc TEGRA_SWGROUP_G2>; |
| 46 | 59 | }; |
| @@ -49,8 +62,8 @@ · 2 unmodified lines | ||
| 49 | 62 | compatible = "nvidia,tegra114-gr3d"; |
| 50 | 63 | reg = <0x54180000 0x00040000>; |
| 51 | 64 | clocks = <&tegra_car TEGRA114_CLK_GR3D>; |
| 52 | − resets = <&tegra_car 24>; | |
| 53 | − reset-names = "3d"; | |
| 65 | + resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; | |
| 66 | + reset-names = "3d", "mc"; | |
| 54 | 67 | |
| 55 | 68 | iommus = <&mc TEGRA_SWGROUP_NV>; |
| 56 | 69 | }; |
| @@ -105,7 +118,7 @@ · 48 unmodified lines | ||
| 105 | 118 | status = "disabled"; |
| 106 | 119 | }; |
| 107 | 120 | |
| 108 | − dsi@54300000 { | |
| 121 | + dsia: dsi@54300000 { | |
| 109 | 122 | compatible = "nvidia,tegra114-dsi"; |
| 110 | 123 | reg = <0x54300000 0x00040000>; |
| 111 | 124 | clocks = <&tegra_car TEGRA114_CLK_DSIA>, |
| @@ -121,7 +134,7 @@ · 9 unmodified lines | ||
| 121 | 134 | #size-cells = <0>; |
| 122 | 135 | }; |
| 123 | 136 | |
| 124 | − dsi@54400000 { | |
| 137 | + dsib: dsi@54400000 { | |
| 125 | 138 | compatible = "nvidia,tegra114-dsi"; |
| 126 | 139 | reg = <0x54400000 0x00040000>; |
| 127 | 140 | clocks = <&tegra_car TEGRA114_CLK_DSIB>, |
| @@ -164,7 +177,7 @@ · 36 unmodified lines | ||
| 164 | 177 | }; |
| 165 | 178 | |
| 166 | 179 | timer@60005000 { |
| 167 | − compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | |
| 180 | + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; | |
| 168 | 181 | reg = <0x60005000 0x400>; |
| 169 | 182 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 170 | 183 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -248,9 +261,31 @@ · 77 unmodified lines | ||
| 248 | 261 | gpio-controller; |
| 249 | 262 | #interrupt-cells = <2>; |
| 250 | 263 | interrupt-controller; |
| 251 | − /* | |
| 252 | 264 | gpio-ranges = <&pinmux 0 0 246>; |
| 253 | − */ | |
| 265 | + }; | |
| 266 | + | |
| 267 | + vde@6001a000 { | |
| 268 | + compatible = "nvidia,tegra114-vde"; | |
| 269 | + reg = <0x6001a000 0x1000>, /* Syntax Engine */ | |
| 270 | + <0x6001b000 0x1000>, /* Video Bitstream Engine */ | |
| 271 | + <0x6001c000 0x100>, /* Macroblock Engine */ | |
| 272 | + <0x6001c200 0x100>, /* Post-processing Engine */ | |
| 273 | + <0x6001c400 0x100>, /* Motion Compensation Engine */ | |
| 274 | + <0x6001c600 0x100>, /* Transform Engine */ | |
| 275 | + <0x6001c800 0x100>, /* Pixel prediction block */ | |
| 276 | + <0x6001ca00 0x100>, /* Video DMA */ | |
| 277 | + <0x6001d800 0x400>; /* Video frame controls */ | |
| 278 | + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", | |
| 279 | + "tfe", "ppb", "vdma", "frameid"; | |
| 280 | + iram = <&vde_pool>; /* IRAM region */ | |
| 281 | + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ | |
| 282 | + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ | |
| 283 | + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ | |
| 284 | + interrupt-names = "sync-token", "bsev", "sxe"; | |
| 285 | + clocks = <&tegra_car TEGRA114_CLK_VDE>; | |
| 286 | + reset-names = "vde", "mc"; | |
| 287 | + resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; | |
| 288 | + iommus = <&mc TEGRA_SWGROUP_VDE>; | |
| 254 | 289 | }; |
| 255 | 290 | |
| 256 | 291 | apbmisc@70000800 { |
| @@ -542,6 +577,7 @@ · 285 unmodified lines | ||
| 542 | 577 | |
| 543 | 578 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 544 | 579 | |
| 580 | + #reset-cells = <1>; | |
| 545 | 581 | #iommu-cells = <1>; |
| 546 | 582 | }; |
| 547 | 583 | |
| @@ -15,66 +15,77 @@ · 14 unmodified lines | ||
| 15 | 15 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 16 | 16 | clock-names = "emc-parent"; |
| 17 | 17 | }; |
| 18 | + | |
| 18 | 19 | timing-20400000 { |
| 19 | 20 | clock-frequency = <20400000>; |
| 20 | 21 | nvidia,parent-clock-frequency = <408000000>; |
| 21 | 22 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 22 | 23 | clock-names = "emc-parent"; |
| 23 | 24 | }; |
| 25 | + | |
| 24 | 26 | timing-40800000 { |
| 25 | 27 | clock-frequency = <40800000>; |
| 26 | 28 | nvidia,parent-clock-frequency = <408000000>; |
| 27 | 29 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 28 | 30 | clock-names = "emc-parent"; |
| 29 | 31 | }; |
| 32 | + | |
| 30 | 33 | timing-68000000 { |
| 31 | 34 | clock-frequency = <68000000>; |
| 32 | 35 | nvidia,parent-clock-frequency = <408000000>; |
| 33 | 36 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 34 | 37 | clock-names = "emc-parent"; |
| 35 | 38 | }; |
| 39 | + | |
| 36 | 40 | timing-102000000 { |
| 37 | 41 | clock-frequency = <102000000>; |
| 38 | 42 | nvidia,parent-clock-frequency = <408000000>; |
| 39 | 43 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 40 | 44 | clock-names = "emc-parent"; |
| 41 | 45 | }; |
| 46 | + | |
| 42 | 47 | timing-204000000 { |
| 43 | 48 | clock-frequency = <204000000>; |
| 44 | 49 | nvidia,parent-clock-frequency = <408000000>; |
| 45 | 50 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 46 | 51 | clock-names = "emc-parent"; |
| 47 | 52 | }; |
| 53 | + | |
| 48 | 54 | timing-300000000 { |
| 49 | 55 | clock-frequency = <300000000>; |
| 50 | 56 | nvidia,parent-clock-frequency = <600000000>; |
| 51 | 57 | clocks = <&tegra_car TEGRA124_CLK_PLL_C>; |
| 52 | 58 | clock-names = "emc-parent"; |
| 53 | 59 | }; |
| 60 | + | |
| 54 | 61 | timing-396000000 { |
| 55 | 62 | clock-frequency = <396000000>; |
| 56 | 63 | nvidia,parent-clock-frequency = <792000000>; |
| 57 | 64 | clocks = <&tegra_car TEGRA124_CLK_PLL_M>; |
| 58 | 65 | clock-names = "emc-parent"; |
| 59 | 66 | }; |
| 67 | + | |
| 60 | 68 | timing-528000000 { |
| 61 | 69 | clock-frequency = <528000000>; |
| 62 | 70 | nvidia,parent-clock-frequency = <528000000>; |
| 63 | 71 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 64 | 72 | clock-names = "emc-parent"; |
| 65 | 73 | }; |
| 74 | + | |
| 66 | 75 | timing-600000000 { |
| 67 | 76 | clock-frequency = <600000000>; |
| 68 | 77 | nvidia,parent-clock-frequency = <600000000>; |
| 69 | 78 | clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; |
| 70 | 79 | clock-names = "emc-parent"; |
| 71 | 80 | }; |
| 81 | + | |
| 72 | 82 | timing-792000000 { |
| 73 | 83 | clock-frequency = <792000000>; |
| 74 | 84 | nvidia,parent-clock-frequency = <792000000>; |
| 75 | 85 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 76 | 86 | clock-names = "emc-parent"; |
| 77 | 87 | }; |
| 88 | + | |
| 78 | 89 | timing-924000000 { |
| 79 | 90 | clock-frequency = <924000000>; |
| 80 | 91 | nvidia,parent-clock-frequency = <924000000>; |
| @@ -84,6 +95,216 @@ · 3 unmodified lines | ||
| 84 | 95 | }; |
| 85 | 96 | }; |
| 86 | 97 | |
| 98 | + memory-controller@70019000 { | |
| 99 | + emc-timings-1 { | |
| 100 | + nvidia,ram-code = <1>; | |
| 101 | + | |
| 102 | + timing-12750000 { | |
| 103 | + clock-frequency = <12750000>; | |
| 104 | + | |
| 105 | + nvidia,emem-configuration = < | |
| 106 | + 0x40040001 0x8000000a | |
| 107 | + 0x00000001 0x00000001 | |
| 108 | + 0x00000002 0x00000000 | |
| 109 | + 0x00000002 0x00000001 | |
| 110 | + 0x00000003 0x00000008 | |
| 111 | + 0x00000003 0x00000002 | |
| 112 | + 0x00000003 0x00000006 | |
| 113 | + 0x06030203 0x000a0502 | |
| 114 | + 0x77e30303 0x70000f03 | |
| 115 | + 0x001f0000 | |
| 116 | + >; | |
| 117 | + }; | |
| 118 | + | |
| 119 | + timing-20400000 { | |
| 120 | + clock-frequency = <20400000>; | |
| 121 | + | |
| 122 | + nvidia,emem-configuration = < | |
| 123 | + 0x40020001 0x80000012 | |
| 124 | + 0x00000001 0x00000001 | |
| 125 | + 0x00000002 0x00000000 | |
| 126 | + 0x00000002 0x00000001 | |
| 127 | + 0x00000003 0x00000008 | |
| 128 | + 0x00000003 0x00000002 | |
| 129 | + 0x00000003 0x00000006 | |
| 130 | + 0x06030203 0x000a0502 | |
| 131 | + 0x76230303 0x70000f03 | |
| 132 | + 0x001f0000 | |
| 133 | + >; | |
| 134 | + }; | |
| 135 | + | |
| 136 | + timing-40800000 { | |
| 137 | + clock-frequency = <40800000>; | |
| 138 | + | |
| 139 | + nvidia,emem-configuration = < | |
| 140 | + 0xa0000001 0x80000017 | |
| 141 | + 0x00000001 0x00000001 | |
| 142 | + 0x00000002 0x00000000 | |
| 143 | + 0x00000002 0x00000001 | |
| 144 | + 0x00000003 0x00000008 | |
| 145 | + 0x00000003 0x00000002 | |
| 146 | + 0x00000003 0x00000006 | |
| 147 | + 0x06030203 0x000a0502 | |
| 148 | + 0x74a30303 0x70000f03 | |
| 149 | + 0x001f0000 | |
| 150 | + >; | |
| 151 | + }; | |
| 152 | + | |
| 153 | + timing-68000000 { | |
| 154 | + clock-frequency = <68000000>; | |
| 155 | + | |
| 156 | + nvidia,emem-configuration = < | |
| 157 | + 0x00000001 0x8000001e | |
| 158 | + 0x00000001 0x00000001 | |
| 159 | + 0x00000002 0x00000000 | |
| 160 | + 0x00000002 0x00000001 | |
| 161 | + 0x00000003 0x00000008 | |
| 162 | + 0x00000003 0x00000002 | |
| 163 | + 0x00000003 0x00000006 | |
| 164 | + 0x06030203 0x000a0502 | |
| 165 | + 0x74230403 0x70000f03 | |
| 166 | + 0x001f0000 | |
| 167 | + >; | |
| 168 | + }; | |
| 169 | + | |
| 170 | + timing-102000000 { | |
| 171 | + clock-frequency = <102000000>; | |
| 172 | + | |
| 173 | + nvidia,emem-configuration = < | |
| 174 | + 0x08000001 0x80000026 | |
| 175 | + 0x00000001 0x00000001 | |
| 176 | + 0x00000003 0x00000000 | |
| 177 | + 0x00000002 0x00000001 | |
| 178 | + 0x00000003 0x00000008 | |
| 179 | + 0x00000003 0x00000002 | |
| 180 | + 0x00000003 0x00000006 | |
| 181 | + 0x06030203 0x000a0503 | |
| 182 | + 0x73c30504 0x70000f03 | |
| 183 | + 0x001f0000 | |
| 184 | + >; | |
| 185 | + }; | |
| 186 | + | |
| 187 | + timing-204000000 { | |
| 188 | + clock-frequency = <204000000>; | |
| 189 | + | |
| 190 | + nvidia,emem-configuration = < | |
| 191 | + 0x01000003 0x80000040 | |
| 192 | + 0x00000001 0x00000001 | |
| 193 | + 0x00000004 0x00000002 | |
| 194 | + 0x00000003 0x00000001 | |
| 195 | + 0x00000003 0x00000008 | |
| 196 | + 0x00000003 0x00000002 | |
| 197 | + 0x00000004 0x00000006 | |
| 198 | + 0x06040203 0x000a0504 | |
| 199 | + 0x73840a05 0x70000f03 | |
| 200 | + 0x001f0000 | |
| 201 | + >; | |
| 202 | + }; | |
| 203 | + | |
| 204 | + timing-300000000 { | |
| 205 | + clock-frequency = <300000000>; | |
| 206 | + | |
| 207 | + nvidia,emem-configuration = < | |
| 208 | + 0x08000004 0x80000040 | |
| 209 | + 0x00000001 0x00000002 | |
| 210 | + 0x00000007 0x00000004 | |
| 211 | + 0x00000004 0x00000001 | |
| 212 | + 0x00000002 0x00000007 | |
| 213 | + 0x00000002 0x00000002 | |
| 214 | + 0x00000004 0x00000006 | |
| 215 | + 0x06040202 0x000b0607 | |
| 216 | + 0x77450e08 0x70000f03 | |
| 217 | + 0x001f0000 | |
| 218 | + >; | |
| 219 | + }; | |
| 220 | + | |
| 221 | + timing-396000000 { | |
| 222 | + clock-frequency = <396000000>; | |
| 223 | + | |
| 224 | + nvidia,emem-configuration = < | |
| 225 | + 0x0f000005 0x80000040 | |
| 226 | + 0x00000001 0x00000002 | |
| 227 | + 0x00000009 0x00000005 | |
| 228 | + 0x00000006 0x00000001 | |
| 229 | + 0x00000002 0x00000008 | |
| 230 | + 0x00000002 0x00000002 | |
| 231 | + 0x00000004 0x00000006 | |
| 232 | + 0x06040202 0x000d0709 | |
| 233 | + 0x7586120a 0x70000f03 | |
| 234 | + 0x001f0000 | |
| 235 | + >; | |
| 236 | + }; | |
| 237 | + | |
| 238 | + timing-528000000 { | |
| 239 | + clock-frequency = <528000000>; | |
| 240 | + | |
| 241 | + nvidia,emem-configuration = < | |
| 242 | + 0x0f000007 0x80000040 | |
| 243 | + 0x00000002 0x00000003 | |
| 244 | + 0x0000000c 0x00000007 | |
| 245 | + 0x00000008 0x00000001 | |
| 246 | + 0x00000002 0x00000009 | |
| 247 | + 0x00000002 0x00000002 | |
| 248 | + 0x00000005 0x00000006 | |
| 249 | + 0x06050202 0x0010090c | |
| 250 | + 0x7428180d 0x70000f03 | |
| 251 | + 0x001f0000 | |
| 252 | + >; | |
| 253 | + }; | |
| 254 | + | |
| 255 | + timing-600000000 { | |
| 256 | + clock-frequency = <600000000>; | |
| 257 | + | |
| 258 | + nvidia,emem-configuration = < | |
| 259 | + 0x00000009 0x80000040 | |
| 260 | + 0x00000003 0x00000004 | |
| 261 | + 0x0000000e 0x00000009 | |
| 262 | + 0x0000000a 0x00000001 | |
| 263 | + 0x00000003 0x0000000b | |
| 264 | + 0x00000002 0x00000002 | |
| 265 | + 0x00000005 0x00000007 | |
| 266 | + 0x07050202 0x00130b0e | |
| 267 | + 0x73a91b0f 0x70000f03 | |
| 268 | + 0x001f0000 | |
| 269 | + >; | |
| 270 | + }; | |
| 271 | + | |
| 272 | + timing-792000000 { | |
| 273 | + clock-frequency = <792000000>; | |
| 274 | + | |
| 275 | + nvidia,emem-configuration = < | |
| 276 | + 0x0e00000b 0x80000040 | |
| 277 | + 0x00000004 0x00000005 | |
| 278 | + 0x00000013 0x0000000c | |
| 279 | + 0x0000000d 0x00000002 | |
| 280 | + 0x00000003 0x0000000c | |
| 281 | + 0x00000002 0x00000002 | |
| 282 | + 0x00000006 0x00000008 | |
| 283 | + 0x08060202 0x00170e13 | |
| 284 | + 0x736c2414 0x70000f02 | |
| 285 | + 0x001f0000 | |
| 286 | + >; | |
| 287 | + }; | |
| 288 | + | |
| 289 | + timing-924000000 { | |
| 290 | + clock-frequency = <924000000>; | |
| 291 | + | |
| 292 | + nvidia,emem-configuration = < | |
| 293 | + 0x0e00000d 0x80000040 | |
| 294 | + 0x00000005 0x00000006 | |
| 295 | + 0x00000016 0x0000000e | |
| 296 | + 0x0000000f 0x00000002 | |
| 297 | + 0x00000004 0x0000000e | |
| 298 | + 0x00000002 0x00000002 | |
| 299 | + 0x00000006 0x00000009 | |
| 300 | + 0x09060202 0x001a1016 | |
| 301 | + 0x734e2a17 0x70000f02 | |
| 302 | + 0x001f0000 | |
| 303 | + >; | |
| 304 | + }; | |
| 305 | + }; | |
| 306 | + }; | |
| 307 | + | |
| 87 | 308 | external-memory-controller@7001b000 { |
| 88 | 309 | emc-timings-1 { |
| 89 | 310 | nvidia,ram-code = <1>; |
| @@ -1251,225 +1472,14 @@ · 1161 unmodified lines | ||
| 1251 | 1472 | 0x00000011 |
| 1252 | 1473 | >; |
| 1253 | 1474 | }; |
| 1254 | − | |
| 1255 | − }; | |
| 1256 | − }; | |
| 1257 | − | |
| 1258 | − memory-controller@70019000 { | |
| 1259 | − emc-timings-1 { | |
| 1260 | − nvidia,ram-code = <1>; | |
| 1261 | − | |
| 1262 | − timing-12750000 { | |
| 1263 | − clock-frequency = <12750000>; | |
| 1264 | − | |
| 1265 | − nvidia,emem-configuration = < | |
| 1266 | − 0x40040001 0x8000000a | |
| 1267 | − 0x00000001 0x00000001 | |
| 1268 | − 0x00000002 0x00000000 | |
| 1269 | − 0x00000002 0x00000001 | |
| 1270 | − 0x00000003 0x00000008 | |
| 1271 | − 0x00000003 0x00000002 | |
| 1272 | − 0x00000003 0x00000006 | |
| 1273 | − 0x06030203 0x000a0502 | |
| 1274 | − 0x77e30303 0x70000f03 | |
| 1275 | − 0x001f0000 | |
| 1276 | − >; | |
| 1277 | − }; | |
| 1278 | − | |
| 1279 | − timing-20400000 { | |
| 1280 | − clock-frequency = <20400000>; | |
| 1281 | − | |
| 1282 | − nvidia,emem-configuration = < | |
| 1283 | − 0x40020001 0x80000012 | |
| 1284 | − 0x00000001 0x00000001 | |
| 1285 | − 0x00000002 0x00000000 | |
| 1286 | − 0x00000002 0x00000001 | |
| 1287 | − 0x00000003 0x00000008 | |
| 1288 | − 0x00000003 0x00000002 | |
| 1289 | − 0x00000003 0x00000006 | |
| 1290 | − 0x06030203 0x000a0502 | |
| 1291 | − 0x76230303 0x70000f03 | |
| 1292 | − 0x001f0000 | |
| 1293 | − >; | |
| 1294 | − }; | |
| 1295 | − | |
| 1296 | − timing-40800000 { | |
| 1297 | − clock-frequency = <40800000>; | |
| 1298 | − | |
| 1299 | − nvidia,emem-configuration = < | |
| 1300 | − 0xa0000001 0x80000017 | |
| 1301 | − 0x00000001 0x00000001 | |
| 1302 | − 0x00000002 0x00000000 | |
| 1303 | − 0x00000002 0x00000001 | |
| 1304 | − 0x00000003 0x00000008 | |
| 1305 | − 0x00000003 0x00000002 | |
| 1306 | − 0x00000003 0x00000006 | |
| 1307 | − 0x06030203 0x000a0502 | |
| 1308 | − 0x74a30303 0x70000f03 | |
| 1309 | − 0x001f0000 | |
| 1310 | − >; | |
| 1311 | − }; | |
| 1312 | − | |
| 1313 | − timing-68000000 { | |
| 1314 | − clock-frequency = <68000000>; | |
| 1315 | − | |
| 1316 | − nvidia,emem-configuration = < | |
| 1317 | − 0x00000001 0x8000001e | |
| 1318 | − 0x00000001 0x00000001 | |
| 1319 | − 0x00000002 0x00000000 | |
| 1320 | − 0x00000002 0x00000001 | |
| 1321 | − 0x00000003 0x00000008 | |
| 1322 | − 0x00000003 0x00000002 | |
| 1323 | − 0x00000003 0x00000006 | |
| 1324 | − 0x06030203 0x000a0502 | |
| 1325 | − 0x74230403 0x70000f03 | |
| 1326 | − 0x001f0000 | |
| 1327 | − >; | |
| 1328 | − }; | |
| 1329 | − | |
| 1330 | − timing-102000000 { | |
| 1331 | − clock-frequency = <102000000>; | |
| 1332 | − | |
| 1333 | − nvidia,emem-configuration = < | |
| 1334 | − 0x08000001 0x80000026 | |
| 1335 | − 0x00000001 0x00000001 | |
| 1336 | − 0x00000003 0x00000000 | |
| 1337 | − 0x00000002 0x00000001 | |
| 1338 | − 0x00000003 0x00000008 | |
| 1339 | − 0x00000003 0x00000002 | |
| 1340 | − 0x00000003 0x00000006 | |
| 1341 | − 0x06030203 0x000a0503 | |
| 1342 | − 0x73c30504 0x70000f03 | |
| 1343 | − 0x001f0000 | |
| 1344 | − >; | |
| 1345 | − }; | |
| 1346 | − | |
| 1347 | − timing-204000000 { | |
| 1348 | − clock-frequency = <204000000>; | |
| 1349 | − | |
| 1350 | − nvidia,emem-configuration = < | |
| 1351 | − 0x01000003 0x80000040 | |
| 1352 | − 0x00000001 0x00000001 | |
| 1353 | − 0x00000004 0x00000002 | |
| 1354 | − 0x00000003 0x00000001 | |
| 1355 | − 0x00000003 0x00000008 | |
| 1356 | − 0x00000003 0x00000002 | |
| 1357 | − 0x00000004 0x00000006 | |
| 1358 | − 0x06040203 0x000a0504 | |
| 1359 | − 0x73840a05 0x70000f03 | |
| 1360 | − 0x001f0000 | |
| 1361 | − >; | |
| 1362 | − }; | |
| 1363 | − | |
| 1364 | − timing-300000000 { | |
| 1365 | − clock-frequency = <300000000>; | |
| 1366 | − | |
| 1367 | − nvidia,emem-configuration = < | |
| 1368 | − 0x08000004 0x80000040 | |
| 1369 | − 0x00000001 0x00000002 | |
| 1370 | − 0x00000007 0x00000004 | |
| 1371 | − 0x00000004 0x00000001 | |
| 1372 | − 0x00000002 0x00000007 | |
| 1373 | − 0x00000002 0x00000002 | |
| 1374 | − 0x00000004 0x00000006 | |
| 1375 | − 0x06040202 0x000b0607 | |
| 1376 | − 0x77450e08 0x70000f03 | |
| 1377 | − 0x001f0000 | |
| 1378 | − >; | |
| 1379 | − }; | |
| 1380 | − | |
| 1381 | − timing-396000000 { | |
| 1382 | − clock-frequency = <396000000>; | |
| 1383 | − | |
| 1384 | − nvidia,emem-configuration = < | |
| 1385 | − 0x0f000005 0x80000040 | |
| 1386 | − 0x00000001 0x00000002 | |
| 1387 | − 0x00000009 0x00000005 | |
| 1388 | − 0x00000006 0x00000001 | |
| 1389 | − 0x00000002 0x00000008 | |
| 1390 | − 0x00000002 0x00000002 | |
| 1391 | − 0x00000004 0x00000006 | |
| 1392 | − 0x06040202 0x000d0709 | |
| 1393 | − 0x7586120a 0x70000f03 | |
| 1394 | − 0x001f0000 | |
| 1395 | − >; | |
| 1396 | − }; | |
| 1397 | − | |
| 1398 | − timing-528000000 { | |
| 1399 | − clock-frequency = <528000000>; | |
| 1400 | − | |
| 1401 | − nvidia,emem-configuration = < | |
| 1402 | − 0x0f000007 0x80000040 | |
| 1403 | − 0x00000002 0x00000003 | |
| 1404 | − 0x0000000c 0x00000007 | |
| 1405 | − 0x00000008 0x00000001 | |
| 1406 | − 0x00000002 0x00000009 | |
| 1407 | − 0x00000002 0x00000002 | |
| 1408 | − 0x00000005 0x00000006 | |
| 1409 | − 0x06050202 0x0010090c | |
| 1410 | − 0x7428180d 0x70000f03 | |
| 1411 | − 0x001f0000 | |
| 1412 | − >; | |
| 1413 | − }; | |
| 1414 | − | |
| 1415 | − timing-600000000 { | |
| 1416 | − clock-frequency = <600000000>; | |
| 1417 | − | |
| 1418 | − nvidia,emem-configuration = < | |
| 1419 | − 0x00000009 0x80000040 | |
| 1420 | − 0x00000003 0x00000004 | |
| 1421 | − 0x0000000e 0x00000009 | |
| 1422 | − 0x0000000a 0x00000001 | |
| 1423 | − 0x00000003 0x0000000b | |
| 1424 | − 0x00000002 0x00000002 | |
| 1425 | − 0x00000005 0x00000007 | |
| 1426 | − 0x07050202 0x00130b0e | |
| 1427 | − 0x73a91b0f 0x70000f03 | |
| 1428 | − 0x001f0000 | |
| 1429 | − >; | |
| 1430 | − }; | |
| 1431 | − | |
| 1432 | − timing-792000000 { | |
| 1433 | − clock-frequency = <792000000>; | |
| 1434 | − | |
| 1435 | − nvidia,emem-configuration = < | |
| 1436 | − 0x0e00000b 0x80000040 | |
| 1437 | − 0x00000004 0x00000005 | |
| 1438 | − 0x00000013 0x0000000c | |
| 1439 | − 0x0000000d 0x00000002 | |
| 1440 | − 0x00000003 0x0000000c | |
| 1441 | − 0x00000002 0x00000002 | |
| 1442 | − 0x00000006 0x00000008 | |
| 1443 | − 0x08060202 0x00170e13 | |
| 1444 | − 0x736c2414 0x70000f02 | |
| 1445 | − 0x001f0000 | |
| 1446 | − >; | |
| 1447 | − }; | |
| 1448 | − | |
| 1449 | − timing-924000000 { | |
| 1450 | − clock-frequency = <924000000>; | |
| 1451 | − | |
| 1452 | − nvidia,emem-configuration = < | |
| 1453 | − 0x0e00000d 0x80000040 | |
| 1454 | − 0x00000005 0x00000006 | |
| 1455 | − 0x00000016 0x0000000e | |
| 1456 | − 0x0000000f 0x00000002 | |
| 1457 | − 0x00000004 0x0000000e | |
| 1458 | − 0x00000002 0x00000002 | |
| 1459 | − 0x00000006 0x00000009 | |
| 1460 | − 0x09060202 0x001a1016 | |
| 1461 | − 0x734e2a17 0x70000f02 | |
| 1462 | − 0x001f0000 | |
| 1463 | − >; | |
| 1464 | − }; | |
| 1465 | 1475 | }; |
| 1466 | 1476 | }; |
| 1467 | 1477 | }; |
| 1468 | 1478 | |
| 1469 | 1479 | &emc_icc_dvfs_opp_table { |
| 1470 | − /delete-node/ opp@1200000000,1100; | |
| 1480 | + /delete-node/ opp-1200000000-1100; | |
| 1471 | 1481 | }; |
| 1472 | 1482 | |
| 1473 | 1483 | &emc_bw_dfs_opp_table { |
| 1474 | − /delete-node/ opp@1200000000; | |
| 1484 | + /delete-node/ opp-1200000000; | |
| 1475 | 1485 | }; |
| @@ -246,7 +246,7 @@ · 245 unmodified lines | ||
| 246 | 246 | |
| 247 | 247 | &gpio { |
| 248 | 248 | /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ |
| 249 | − pex-perst-n { | |
| 249 | + pex-perst-n-hog { | |
| 250 | 250 | gpio-hog; |
| 251 | 251 | gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; |
| 252 | 252 | output-high; |
| @@ -248,7 +248,7 @@ · 247 unmodified lines | ||
| 248 | 248 | |
| 249 | 249 | &gpio { |
| 250 | 250 | /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ |
| 251 | − pex-perst-n { | |
| 251 | + pex-perst-n-hog { | |
| 252 | 252 | gpio-hog; |
| 253 | 253 | gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; |
| 254 | 254 | output-high; |
| @@ -57,7 +57,7 @@ · 56 unmodified lines | ||
| 57 | 57 | }; |
| 58 | 58 | }; |
| 59 | 59 | |
| 60 | − gpu@0,57000000 { | |
| 60 | + gpu@57000000 { | |
| 61 | 61 | /* |
| 62 | 62 | * Node left disabled on purpose - the bootloader will enable |
| 63 | 63 | * it after having set the VPR up |
| @@ -1539,14 +1539,17 @@ · 1475 unmodified lines | ||
| 1539 | 1539 | |
| 1540 | 1540 | serial@70006040 { |
| 1541 | 1541 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1542 | + /delete-property/ reg-shift; | |
| 1542 | 1543 | }; |
| 1543 | 1544 | |
| 1544 | 1545 | serial@70006200 { |
| 1545 | 1546 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1547 | + /delete-property/ reg-shift; | |
| 1546 | 1548 | }; |
| 1547 | 1549 | |
| 1548 | 1550 | serial@70006300 { |
| 1549 | 1551 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1552 | + /delete-property/ reg-shift; | |
| 1550 | 1553 | }; |
| 1551 | 1554 | |
| 1552 | 1555 | hdmi_ddc: i2c@7000c700 { |
| @@ -1885,6 +1888,7 @@ · 332 unmodified lines | ||
| 1885 | 1888 | usb2-0 { |
| 1886 | 1889 | status = "okay"; |
| 1887 | 1890 | mode = "otg"; |
| 1891 | + usb-role-switch; | |
| 1888 | 1892 | vbus-supply = <®_usbo1_vbus>; |
| 1889 | 1893 | }; |
| 1890 | 1894 | |
| @@ -2021,7 +2025,7 @@ · 130 unmodified lines | ||
| 2021 | 2025 | }; |
| 2022 | 2026 | |
| 2023 | 2027 | thermal-zones { |
| 2024 | − cpu { | |
| 2028 | + cpu-thermal { | |
| 2025 | 2029 | trips { |
| 2026 | 2030 | cpu-shutdown-trip { |
| 2027 | 2031 | temperature = <101000>; |
| @@ -2031,7 +2035,7 @@ · 3 unmodified lines | ||
| 2031 | 2035 | }; |
| 2032 | 2036 | }; |
| 2033 | 2037 | |
| 2034 | − mem { | |
| 2038 | + mem-thermal { | |
| 2035 | 2039 | trips { |
| 2036 | 2040 | mem-shutdown-trip { |
| 2037 | 2041 | temperature = <101000>; |
| @@ -2041,7 +2045,7 @@ · 3 unmodified lines | ||
| 2041 | 2045 | }; |
| 2042 | 2046 | }; |
| 2043 | 2047 | |
| 2044 | − gpu { | |
| 2048 | + gpu-thermal { | |
| 2045 | 2049 | trips { |
| 2046 | 2050 | gpu-shutdown-trip { |
| 2047 | 2051 | temperature = <101000>; |
| @@ -2055,7 +2059,7 @@ · 7 unmodified lines | ||
| 2055 | 2059 | |
| 2056 | 2060 | &gpio { |
| 2057 | 2061 | /* I210 Gigabit Ethernet Controller Reset */ |
| 2058 | − lan-reset-n { | |
| 2062 | + lan-reset-n-hog { | |
| 2059 | 2063 | gpio-hog; |
| 2060 | 2064 | gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; |
| 2061 | 2065 | output-high; |
| @@ -2063,7 +2067,7 @@ · 1 unmodified line | ||
| 2063 | 2067 | }; |
| 2064 | 2068 | |
| 2065 | 2069 | /* Control MXM3 pin 26 Reset Module Output Carrier Input */ |
| 2066 | − reset-moci-ctrl { | |
| 2070 | + reset-moci-ctrl-hog { | |
| 2067 | 2071 | gpio-hog; |
| 2068 | 2072 | gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; |
| 2069 | 2073 | output-high; |
| @@ -56,7 +56,7 @@ · 55 unmodified lines | ||
| 56 | 56 | }; |
| 57 | 57 | }; |
| 58 | 58 | |
| 59 | − gpu@0,57000000 { | |
| 59 | + gpu@57000000 { | |
| 60 | 60 | /* |
| 61 | 61 | * Node left disabled on purpose - the bootloader will enable |
| 62 | 62 | * it after having set the VPR up |
| @@ -1532,14 +1532,17 @@ · 1469 unmodified lines | ||
| 1532 | 1532 | |
| 1533 | 1533 | serial@70006040 { |
| 1534 | 1534 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1535 | + /delete-property/ reg-shift; | |
| 1535 | 1536 | }; |
| 1536 | 1537 | |
| 1537 | 1538 | serial@70006200 { |
| 1538 | 1539 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1540 | + /delete-property/ reg-shift; | |
| 1539 | 1541 | }; |
| 1540 | 1542 | |
| 1541 | 1543 | serial@70006300 { |
| 1542 | 1544 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1545 | + /delete-property/ reg-shift; | |
| 1543 | 1546 | }; |
| 1544 | 1547 | |
| 1545 | 1548 | hdmi_ddc: i2c@7000c400 { |
| @@ -1877,6 +1880,7 @@ · 331 unmodified lines | ||
| 1877 | 1880 | usb2-0 { |
| 1878 | 1881 | status = "okay"; |
| 1879 | 1882 | mode = "otg"; |
| 1883 | + usb-role-switch; | |
| 1880 | 1884 | vbus-supply = <®_usbo1_vbus>; |
| 1881 | 1885 | }; |
| 1882 | 1886 | |
| @@ -2013,7 +2017,7 @@ · 130 unmodified lines | ||
| 2013 | 2017 | }; |
| 2014 | 2018 | |
| 2015 | 2019 | thermal-zones { |
| 2016 | − cpu { | |
| 2020 | + cpu-thermal { | |
| 2017 | 2021 | trips { |
| 2018 | 2022 | cpu-shutdown-trip { |
| 2019 | 2023 | temperature = <101000>; |
| @@ -2023,7 +2027,7 @@ · 3 unmodified lines | ||
| 2023 | 2027 | }; |
| 2024 | 2028 | }; |
| 2025 | 2029 | |
| 2026 | − mem { | |
| 2030 | + mem-thermal { | |
| 2027 | 2031 | trips { |
| 2028 | 2032 | mem-shutdown-trip { |
| 2029 | 2033 | temperature = <101000>; |
| @@ -2033,7 +2037,7 @@ · 3 unmodified lines | ||
| 2033 | 2037 | }; |
| 2034 | 2038 | }; |
| 2035 | 2039 | |
| 2036 | − gpu { | |
| 2040 | + gpu-thermal { | |
| 2037 | 2041 | trips { |
| 2038 | 2042 | gpu-shutdown-trip { |
| 2039 | 2043 | temperature = <101000>; |
| @@ -2047,7 +2051,7 @@ · 7 unmodified lines | ||
| 2047 | 2051 | |
| 2048 | 2052 | &gpio { |
| 2049 | 2053 | /* I210 Gigabit Ethernet Controller Reset */ |
| 2050 | − lan-reset-n { | |
| 2054 | + lan-reset-n-hog { | |
| 2051 | 2055 | gpio-hog; |
| 2052 | 2056 | gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; |
| 2053 | 2057 | output-high; |
| @@ -2055,7 +2059,7 @@ · 1 unmodified line | ||
| 2055 | 2059 | }; |
| 2056 | 2060 | |
| 2057 | 2061 | /* Control MXM3 pin 26 Reset Module Output Carrier Input */ |
| 2058 | − reset-moci-ctrl { | |
| 2062 | + reset-moci-ctrl-hog { | |
| 2059 | 2063 | gpio-hog; |
| 2060 | 2064 | gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; |
| 2061 | 2065 | output-high; |
| @@ -10,66 +10,77 @@ · 9 unmodified lines | ||
| 10 | 10 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 11 | 11 | clock-names = "emc-parent"; |
| 12 | 12 | }; |
| 13 | + | |
| 13 | 14 | timing-20400000 { |
| 14 | 15 | clock-frequency = <20400000>; |
| 15 | 16 | nvidia,parent-clock-frequency = <408000000>; |
| 16 | 17 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 17 | 18 | clock-names = "emc-parent"; |
| 18 | 19 | }; |
| 20 | + | |
| 19 | 21 | timing-40800000 { |
| 20 | 22 | clock-frequency = <40800000>; |
| 21 | 23 | nvidia,parent-clock-frequency = <408000000>; |
| 22 | 24 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 23 | 25 | clock-names = "emc-parent"; |
| 24 | 26 | }; |
| 27 | + | |
| 25 | 28 | timing-68000000 { |
| 26 | 29 | clock-frequency = <68000000>; |
| 27 | 30 | nvidia,parent-clock-frequency = <408000000>; |
| 28 | 31 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 29 | 32 | clock-names = "emc-parent"; |
| 30 | 33 | }; |
| 34 | + | |
| 31 | 35 | timing-102000000 { |
| 32 | 36 | clock-frequency = <102000000>; |
| 33 | 37 | nvidia,parent-clock-frequency = <408000000>; |
| 34 | 38 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 35 | 39 | clock-names = "emc-parent"; |
| 36 | 40 | }; |
| 41 | + | |
| 37 | 42 | timing-204000000 { |
| 38 | 43 | clock-frequency = <204000000>; |
| 39 | 44 | nvidia,parent-clock-frequency = <408000000>; |
| 40 | 45 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 41 | 46 | clock-names = "emc-parent"; |
| 42 | 47 | }; |
| 48 | + | |
| 43 | 49 | timing-300000000 { |
| 44 | 50 | clock-frequency = <300000000>; |
| 45 | 51 | nvidia,parent-clock-frequency = <600000000>; |
| 46 | 52 | clocks = <&tegra_car TEGRA124_CLK_PLL_C>; |
| 47 | 53 | clock-names = "emc-parent"; |
| 48 | 54 | }; |
| 55 | + | |
| 49 | 56 | timing-396000000 { |
| 50 | 57 | clock-frequency = <396000000>; |
| 51 | 58 | nvidia,parent-clock-frequency = <792000000>; |
| 52 | 59 | clocks = <&tegra_car TEGRA124_CLK_PLL_M>; |
| 53 | 60 | clock-names = "emc-parent"; |
| 54 | 61 | }; |
| 62 | + | |
| 55 | 63 | timing-528000000 { |
| 56 | 64 | clock-frequency = <528000000>; |
| 57 | 65 | nvidia,parent-clock-frequency = <528000000>; |
| 58 | 66 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 59 | 67 | clock-names = "emc-parent"; |
| 60 | 68 | }; |
| 69 | + | |
| 61 | 70 | timing-600000000 { |
| 62 | 71 | clock-frequency = <600000000>; |
| 63 | 72 | nvidia,parent-clock-frequency = <600000000>; |
| 64 | 73 | clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; |
| 65 | 74 | clock-names = "emc-parent"; |
| 66 | 75 | }; |
| 76 | + | |
| 67 | 77 | timing-792000000 { |
| 68 | 78 | clock-frequency = <792000000>; |
| 69 | 79 | nvidia,parent-clock-frequency = <792000000>; |
| 70 | 80 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 71 | 81 | clock-names = "emc-parent"; |
| 72 | 82 | }; |
| 83 | + | |
| 73 | 84 | timing-924000000 { |
| 74 | 85 | clock-frequency = <924000000>; |
| 75 | 86 | nvidia,parent-clock-frequency = <924000000>; |
| @@ -79,516 +90,330 @@ · 3 unmodified lines | ||
| 79 | 90 | }; |
| 80 | 91 | }; |
| 81 | 92 | |
| 82 | − external-memory-controller@7001b000 { | |
| 93 | + memory-controller@70019000 { | |
| 83 | 94 | emc-timings-3 { |
| 84 | 95 | nvidia,ram-code = <3>; |
| 85 | 96 | |
| 86 | 97 | timing-12750000 { |
| 87 | 98 | clock-frequency = <12750000>; |
| 88 | 99 | |
| 89 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 90 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 91 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 92 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 93 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 94 | − nvidia,emc-cfg = <0x73240000>; | |
| 95 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 96 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 97 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 98 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 99 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 100 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 101 | − nvidia,emc-mrs-wait-cnt = <0x000e000e>; | |
| 102 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 103 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 104 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 105 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 106 | − | |
| 107 | − nvidia,emc-configuration = < | |
| 100 | + nvidia,emem-configuration = < | |
| 101 | + 0x40040001 | |
| 102 | + 0x8000000a | |
| 103 | + 0x00000001 | |
| 104 | + 0x00000001 | |
| 105 | + 0x00000002 | |
| 108 | 106 | 0x00000000 |
| 107 | + 0x00000002 | |
| 108 | + 0x00000001 | |
| 109 | 109 | 0x00000003 |
| 110 | − 0x00000000 | |
| 111 | − 0x00000000 | |
| 112 | − 0x00000000 | |
| 113 | − 0x00000004 | |
| 114 | − 0x0000000a | |
| 115 | − 0x00000005 | |
| 116 | − 0x0000000b | |
| 117 | − 0x00000000 | |
| 118 | − 0x00000000 | |
| 110 | + 0x00000008 | |
| 119 | 111 | 0x00000003 |
| 112 | + 0x00000002 | |
| 120 | 113 | 0x00000003 |
| 121 | − 0x00000000 | |
| 122 | − 0x00000006 | |
| 123 | − 0x00000006 | |
| 124 | 114 | 0x00000006 |
| 115 | + 0x06030203 | |
| 116 | + 0x000a0502 | |
| 117 | + 0x77e30303 | |
| 118 | + 0x70000f03 | |
| 119 | + 0x001f0000 | |
| 120 | + >; | |
| 121 | + }; | |
| 122 | + | |
| 123 | + timing-20400000 { | |
| 124 | + clock-frequency = <20400000>; | |
| 125 | + | |
| 126 | + nvidia,emem-configuration = < | |
| 127 | + 0x40020001 | |
| 128 | + 0x80000012 | |
| 129 | + 0x00000001 | |
| 130 | + 0x00000001 | |
| 125 | 131 | 0x00000002 |
| 126 | 132 | 0x00000000 |
| 127 | − 0x00000005 | |
| 128 | − 0x00000005 | |
| 129 | − 0x00010000 | |
| 130 | − 0x00000003 | |
| 131 | − 0x00000000 | |
| 132 | − 0x00000000 | |
| 133 | − 0x00000000 | |
| 134 | − 0x00000000 | |
| 135 | − 0x00000004 | |
| 136 | − 0x0000000c | |
| 137 | − 0x0000000d | |
| 138 | − 0x0000000f | |
| 139 | − 0x00000060 | |
| 140 | − 0x00000000 | |
| 141 | − 0x00000018 | |
| 142 | − 0x00000002 | |
| 143 | 133 | 0x00000002 |
| 144 | 134 | 0x00000001 |
| 145 | − 0x00000000 | |
| 146 | − 0x00000007 | |
| 147 | − 0x0000000f | |
| 148 | − 0x00000005 | |
| 149 | − 0x00000005 | |
| 150 | − 0x00000004 | |
| 151 | − 0x00000005 | |
| 152 | − 0x00000004 | |
| 153 | − 0x00000000 | |
| 154 | − 0x00000000 | |
| 155 | − 0x00000005 | |
| 156 | − 0x00000005 | |
| 157 | − 0x00000064 | |
| 158 | − 0x00000000 | |
| 159 | − 0x00000000 | |
| 160 | − 0x00000000 | |
| 161 | − 0x106aa298 | |
| 162 | − 0x002c00a0 | |
| 163 | − 0x00008000 | |
| 164 | − 0x00080000 | |
| 165 | − 0x00080000 | |
| 166 | − 0x00080000 | |
| 167 | − 0x00080000 | |
| 168 | − 0x00080000 | |
| 169 | − 0x00080000 | |
| 170 | − 0x00080000 | |
| 171 | − 0x00080000 | |
| 172 | − 0x00080000 | |
| 173 | − 0x00080000 | |
| 174 | − 0x00080000 | |
| 175 | − 0x00080000 | |
| 176 | − 0x00080000 | |
| 177 | − 0x00080000 | |
| 178 | − 0x00080000 | |
| 179 | − 0x00080000 | |
| 180 | − 0x00000000 | |
| 181 | − 0x00000000 | |
| 182 | − 0x00000000 | |
| 183 | − 0x00000000 | |
| 184 | − 0x00000000 | |
| 185 | − 0x00000000 | |
| 186 | − 0x00000000 | |
| 187 | − 0x00000000 | |
| 188 | − 0x00000000 | |
| 189 | − 0x00000000 | |
| 190 | − 0x00000000 | |
| 191 | − 0x00000000 | |
| 192 | − 0x00000000 | |
| 193 | − 0x00000000 | |
| 194 | − 0x00000000 | |
| 195 | − 0x00000000 | |
| 196 | − 0x00000000 | |
| 197 | − 0x00000000 | |
| 198 | − 0x00000000 | |
| 199 | − 0x00000000 | |
| 200 | − 0x00000000 | |
| 201 | − 0x00000000 | |
| 202 | − 0x00000000 | |
| 203 | − 0x00000000 | |
| 204 | − 0x00000000 | |
| 205 | − 0x00000000 | |
| 206 | − 0x00000000 | |
| 207 | − 0x00000000 | |
| 208 | − 0x00000000 | |
| 209 | − 0x00000000 | |
| 210 | − 0x00000000 | |
| 211 | − 0x00000000 | |
| 212 | − 0x00000000 | |
| 213 | − 0x00000000 | |
| 214 | − 0x00000000 | |
| 215 | − 0x00000000 | |
| 216 | − 0x00000000 | |
| 217 | − 0x00000000 | |
| 218 | − 0x000fc000 | |
| 219 | − 0x000fc000 | |
| 220 | − 0x000fc000 | |
| 221 | − 0x000fc000 | |
| 222 | − 0x0000fc00 | |
| 223 | − 0x0000fc00 | |
| 224 | − 0x0000fc00 | |
| 225 | − 0x0000fc00 | |
| 226 | − 0x10000280 | |
| 227 | − 0x00000000 | |
| 228 | − 0x00111111 | |
| 229 | − 0x00000000 | |
| 230 | − 0x00000000 | |
| 231 | − 0x77ffc081 | |
| 232 | − 0x00000e0e | |
| 233 | − 0x81f1f108 | |
| 234 | − 0x07070004 | |
| 235 | − 0x0000003f | |
| 236 | − 0x016eeeee | |
| 237 | − 0x51451400 | |
| 238 | − 0x00514514 | |
| 239 | − 0x00514514 | |
| 240 | − 0x51451400 | |
| 241 | − 0x0000003f | |
| 242 | − 0x00000007 | |
| 243 | − 0x00000000 | |
| 244 | − 0x00000042 | |
| 245 | − 0x000e000e | |
| 246 | − 0x00000000 | |
| 247 | 135 | 0x00000003 |
| 248 | − 0x0000f2f3 | |
| 249 | − 0x800001c5 | |
| 250 | − 0x0000000a | |
| 136 | + 0x00000008 | |
| 137 | + 0x00000003 | |
| 138 | + 0x00000002 | |
| 139 | + 0x00000003 | |
| 140 | + 0x00000006 | |
| 141 | + 0x06030203 | |
| 142 | + 0x000a0502 | |
| 143 | + 0x76230303 | |
| 144 | + 0x70000f03 | |
| 145 | + 0x001f0000 | |
| 251 | 146 | >; |
| 252 | 147 | }; |
| 253 | 148 | |
| 254 | − timing-20400000 { | |
| 255 | − clock-frequency = <20400000>; | |
| 256 | − | |
| 257 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 258 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 259 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 260 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 261 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 262 | − nvidia,emc-cfg = <0x73240000>; | |
| 263 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 264 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 265 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 266 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 267 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 268 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 269 | − nvidia,emc-mrs-wait-cnt = <0x000e000e>; | |
| 270 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 271 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 272 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 273 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 149 | + timing-40800000 { | |
| 150 | + clock-frequency = <40800000>; | |
| 274 | 151 | |
| 275 | − nvidia,emc-configuration = < | |
| 276 | − 0x00000000 | |
| 277 | − 0x00000005 | |
| 278 | − 0x00000000 | |
| 279 | − 0x00000000 | |
| 280 | − 0x00000000 | |
| 281 | − 0x00000004 | |
| 282 | − 0x0000000a | |
| 283 | − 0x00000005 | |
| 284 | − 0x0000000b | |
| 285 | − 0x00000000 | |
| 152 | + nvidia,emem-configuration = < | |
| 153 | + 0xa0000001 | |
| 154 | + 0x80000017 | |
| 155 | + 0x00000001 | |
| 156 | + 0x00000001 | |
| 157 | + 0x00000002 | |
| 286 | 158 | 0x00000000 |
| 159 | + 0x00000002 | |
| 160 | + 0x00000001 | |
| 287 | 161 | 0x00000003 |
| 162 | + 0x00000008 | |
| 288 | 163 | 0x00000003 |
| 289 | − 0x00000000 | |
| 290 | − 0x00000006 | |
| 291 | − 0x00000006 | |
| 292 | − 0x00000006 | |
| 293 | 164 | 0x00000002 |
| 294 | − 0x00000000 | |
| 295 | − 0x00000005 | |
| 296 | − 0x00000005 | |
| 297 | − 0x00010000 | |
| 298 | 165 | 0x00000003 |
| 299 | − 0x00000000 | |
| 300 | − 0x00000000 | |
| 301 | − 0x00000000 | |
| 302 | − 0x00000000 | |
| 303 | − 0x00000004 | |
| 304 | − 0x0000000c | |
| 305 | − 0x0000000d | |
| 306 | − 0x0000000f | |
| 307 | − 0x0000009a | |
| 308 | − 0x00000000 | |
| 309 | − 0x00000026 | |
| 166 | + 0x00000006 | |
| 167 | + 0x06030203 | |
| 168 | + 0x000a0502 | |
| 169 | + 0x74a30303 | |
| 170 | + 0x70000f03 | |
| 171 | + 0x001f0000 | |
| 172 | + >; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + timing-68000000 { | |
| 176 | + clock-frequency = <68000000>; | |
| 177 | + | |
| 178 | + nvidia,emem-configuration = < | |
| 179 | + 0x00000001 | |
| 180 | + 0x8000001e | |
| 181 | + 0x00000001 | |
| 182 | + 0x00000001 | |
| 310 | 183 | 0x00000002 |
| 184 | + 0x00000000 | |
| 311 | 185 | 0x00000002 |
| 312 | 186 | 0x00000001 |
| 313 | − 0x00000000 | |
| 314 | − 0x00000007 | |
| 315 | − 0x0000000f | |
| 316 | − 0x00000006 | |
| 317 | − 0x00000006 | |
| 318 | − 0x00000004 | |
| 319 | − 0x00000005 | |
| 320 | − 0x00000004 | |
| 321 | − 0x00000000 | |
| 322 | − 0x00000000 | |
| 323 | − 0x00000005 | |
| 324 | − 0x00000005 | |
| 325 | − 0x000000a0 | |
| 326 | − 0x00000000 | |
| 327 | − 0x00000000 | |
| 328 | − 0x00000000 | |
| 329 | − 0x106aa298 | |
| 330 | − 0x002c00a0 | |
| 331 | − 0x00008000 | |
| 332 | − 0x00080000 | |
| 333 | − 0x00080000 | |
| 334 | − 0x00080000 | |
| 335 | − 0x00080000 | |
| 336 | − 0x00080000 | |
| 337 | − 0x00080000 | |
| 338 | − 0x00080000 | |
| 339 | − 0x00080000 | |
| 340 | − 0x00080000 | |
| 341 | − 0x00080000 | |
| 342 | − 0x00080000 | |
| 343 | − 0x00080000 | |
| 344 | − 0x00080000 | |
| 345 | − 0x00080000 | |
| 346 | − 0x00080000 | |
| 347 | − 0x00080000 | |
| 348 | − 0x00000000 | |
| 349 | − 0x00000000 | |
| 350 | − 0x00000000 | |
| 351 | − 0x00000000 | |
| 352 | − 0x00000000 | |
| 353 | − 0x00000000 | |
| 354 | − 0x00000000 | |
| 355 | − 0x00000000 | |
| 356 | − 0x00000000 | |
| 357 | − 0x00000000 | |
| 358 | − 0x00000000 | |
| 359 | − 0x00000000 | |
| 360 | − 0x00000000 | |
| 361 | − 0x00000000 | |
| 362 | − 0x00000000 | |
| 363 | − 0x00000000 | |
| 364 | − 0x00000000 | |
| 365 | − 0x00000000 | |
| 366 | − 0x00000000 | |
| 367 | − 0x00000000 | |
| 368 | − 0x00000000 | |
| 369 | − 0x00000000 | |
| 370 | − 0x00000000 | |
| 371 | − 0x00000000 | |
| 372 | − 0x00000000 | |
| 373 | − 0x00000000 | |
| 374 | − 0x00000000 | |
| 375 | − 0x00000000 | |
| 376 | − 0x00000000 | |
| 377 | − 0x00000000 | |
| 378 | − 0x00000000 | |
| 379 | − 0x00000000 | |
| 380 | − 0x00000000 | |
| 381 | − 0x00000000 | |
| 382 | − 0x00000000 | |
| 383 | − 0x00000000 | |
| 384 | − 0x00000000 | |
| 385 | − 0x00000000 | |
| 386 | − 0x000fc000 | |
| 387 | − 0x000fc000 | |
| 388 | − 0x000fc000 | |
| 389 | − 0x000fc000 | |
| 390 | − 0x0000fc00 | |
| 391 | − 0x0000fc00 | |
| 392 | − 0x0000fc00 | |
| 393 | − 0x0000fc00 | |
| 394 | − 0x10000280 | |
| 395 | − 0x00000000 | |
| 396 | − 0x00111111 | |
| 397 | − 0x00000000 | |
| 398 | − 0x00000000 | |
| 399 | − 0x77ffc081 | |
| 400 | − 0x00000e0e | |
| 401 | − 0x81f1f108 | |
| 402 | − 0x07070004 | |
| 403 | − 0x0000003f | |
| 404 | − 0x016eeeee | |
| 405 | − 0x51451400 | |
| 406 | − 0x00514514 | |
| 407 | − 0x00514514 | |
| 408 | − 0x51451400 | |
| 409 | − 0x0000003f | |
| 410 | − 0x0000000b | |
| 411 | − 0x00000000 | |
| 412 | − 0x00000042 | |
| 413 | − 0x000e000e | |
| 414 | − 0x00000000 | |
| 415 | 187 | 0x00000003 |
| 416 | − 0x0000f2f3 | |
| 417 | − 0x8000023a | |
| 418 | − 0x0000000a | |
| 188 | + 0x00000008 | |
| 189 | + 0x00000003 | |
| 190 | + 0x00000002 | |
| 191 | + 0x00000003 | |
| 192 | + 0x00000006 | |
| 193 | + 0x06030203 | |
| 194 | + 0x000a0502 | |
| 195 | + 0x74230403 | |
| 196 | + 0x70000f03 | |
| 197 | + 0x001f0000 | |
| 419 | 198 | >; |
| 420 | 199 | }; |
| 421 | 200 | |
| 422 | − timing-40800000 { | |
| 423 | − clock-frequency = <40800000>; | |
| 424 | − | |
| 425 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 426 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 427 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 428 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 429 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 430 | − nvidia,emc-cfg = <0x73240000>; | |
| 431 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 432 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 433 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 434 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 435 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 436 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 437 | − nvidia,emc-mrs-wait-cnt = <0x000e000e>; | |
| 438 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 439 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 440 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 441 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 201 | + timing-102000000 { | |
| 202 | + clock-frequency = <102000000>; | |
| 442 | 203 | |
| 443 | − nvidia,emc-configuration = < | |
| 204 | + nvidia,emem-configuration = < | |
| 205 | + 0x08000001 | |
| 206 | + 0x80000026 | |
| 444 | 207 | 0x00000001 |
| 445 | − 0x0000000a | |
| 446 | − 0x00000000 | |
| 447 | 208 | 0x00000001 |
| 209 | + 0x00000003 | |
| 448 | 210 | 0x00000000 |
| 449 | − 0x00000004 | |
| 450 | − 0x0000000a | |
| 451 | − 0x00000005 | |
| 452 | − 0x0000000b | |
| 453 | − 0x00000000 | |
| 454 | − 0x00000000 | |
| 211 | + 0x00000002 | |
| 212 | + 0x00000001 | |
| 455 | 213 | 0x00000003 |
| 214 | + 0x00000008 | |
| 456 | 215 | 0x00000003 |
| 457 | − 0x00000000 | |
| 458 | − 0x00000006 | |
| 459 | − 0x00000006 | |
| 460 | − 0x00000006 | |
| 461 | 216 | 0x00000002 |
| 462 | − 0x00000000 | |
| 463 | − 0x00000005 | |
| 464 | − 0x00000005 | |
| 465 | − 0x00010000 | |
| 466 | 217 | 0x00000003 |
| 467 | − 0x00000000 | |
| 468 | − 0x00000000 | |
| 469 | − 0x00000000 | |
| 470 | − 0x00000000 | |
| 218 | + 0x00000006 | |
| 219 | + 0x06030203 | |
| 220 | + 0x000a0503 | |
| 221 | + 0x73c30504 | |
| 222 | + 0x70000f03 | |
| 223 | + 0x001f0000 | |
| 224 | + >; | |
| 225 | + }; | |
| 226 | + | |
| 227 | + timing-204000000 { | |
| 228 | + clock-frequency = <204000000>; | |
| 229 | + | |
| 230 | + nvidia,emem-configuration = < | |
| 231 | + 0x01000003 | |
| 232 | + 0x80000040 | |
| 233 | + 0x00000001 | |
| 234 | + 0x00000001 | |
| 471 | 235 | 0x00000004 |
| 472 | − 0x0000000c | |
| 473 | − 0x0000000d | |
| 474 | − 0x0000000f | |
| 475 | − 0x00000134 | |
| 476 | − 0x00000000 | |
| 477 | − 0x0000004d | |
| 478 | − 0x00000002 | |
| 479 | 236 | 0x00000002 |
| 237 | + 0x00000003 | |
| 480 | 238 | 0x00000001 |
| 481 | − 0x00000000 | |
| 239 | + 0x00000003 | |
| 482 | 240 | 0x00000008 |
| 483 | − 0x0000000f | |
| 484 | − 0x0000000c | |
| 485 | − 0x0000000c | |
| 241 | + 0x00000003 | |
| 242 | + 0x00000002 | |
| 486 | 243 | 0x00000004 |
| 487 | − 0x00000005 | |
| 244 | + 0x00000006 | |
| 245 | + 0x06040203 | |
| 246 | + 0x000a0504 | |
| 247 | + 0x73840a05 | |
| 248 | + 0x70000f03 | |
| 249 | + 0x001f0000 | |
| 250 | + >; | |
| 251 | + }; | |
| 252 | + | |
| 253 | + timing-300000000 { | |
| 254 | + clock-frequency = <300000000>; | |
| 255 | + | |
| 256 | + nvidia,emem-configuration = < | |
| 257 | + 0x08000004 | |
| 258 | + 0x80000040 | |
| 259 | + 0x00000001 | |
| 260 | + 0x00000002 | |
| 261 | + 0x00000007 | |
| 488 | 262 | 0x00000004 |
| 489 | − 0x00000000 | |
| 490 | − 0x00000000 | |
| 491 | − 0x00000005 | |
| 492 | − 0x00000005 | |
| 493 | − 0x0000013f | |
| 494 | − 0x00000000 | |
| 495 | − 0x00000000 | |
| 496 | − 0x00000000 | |
| 497 | − 0x106aa298 | |
| 498 | − 0x002c00a0 | |
| 499 | − 0x00008000 | |
| 500 | − 0x00080000 | |
| 501 | − 0x00080000 | |
| 502 | − 0x00080000 | |
| 503 | − 0x00080000 | |
| 504 | − 0x00080000 | |
| 505 | − 0x00080000 | |
| 506 | − 0x00080000 | |
| 507 | − 0x00080000 | |
| 508 | − 0x00080000 | |
| 509 | − 0x00080000 | |
| 510 | − 0x00080000 | |
| 511 | − 0x00080000 | |
| 512 | − 0x00080000 | |
| 513 | − 0x00080000 | |
| 514 | − 0x00080000 | |
| 515 | − 0x00080000 | |
| 516 | − 0x00000000 | |
| 517 | − 0x00000000 | |
| 518 | − 0x00000000 | |
| 519 | − 0x00000000 | |
| 520 | − 0x00000000 | |
| 521 | − 0x00000000 | |
| 522 | − 0x00000000 | |
| 523 | − 0x00000000 | |
| 524 | − 0x00000000 | |
| 525 | − 0x00000000 | |
| 526 | − 0x00000000 | |
| 527 | − 0x00000000 | |
| 528 | − 0x00000000 | |
| 529 | − 0x00000000 | |
| 530 | − 0x00000000 | |
| 531 | − 0x00000000 | |
| 532 | − 0x00000000 | |
| 533 | − 0x00000000 | |
| 534 | − 0x00000000 | |
| 535 | − 0x00000000 | |
| 536 | − 0x00000000 | |
| 537 | − 0x00000000 | |
| 538 | − 0x00000000 | |
| 539 | − 0x00000000 | |
| 540 | − 0x00000000 | |
| 541 | − 0x00000000 | |
| 542 | − 0x00000000 | |
| 543 | − 0x00000000 | |
| 544 | − 0x00000000 | |
| 545 | − 0x00000000 | |
| 546 | − 0x00000000 | |
| 547 | − 0x00000000 | |
| 548 | − 0x00000000 | |
| 549 | − 0x00000000 | |
| 550 | − 0x00000000 | |
| 551 | − 0x00000000 | |
| 552 | − 0x00000000 | |
| 553 | − 0x00000000 | |
| 554 | − 0x000fc000 | |
| 555 | − 0x000fc000 | |
| 556 | − 0x000fc000 | |
| 557 | − 0x000fc000 | |
| 558 | − 0x0000fc00 | |
| 559 | − 0x0000fc00 | |
| 560 | − 0x0000fc00 | |
| 561 | − 0x0000fc00 | |
| 562 | − 0x10000280 | |
| 563 | − 0x00000000 | |
| 564 | − 0x00111111 | |
| 565 | − 0x00000000 | |
| 566 | − 0x00000000 | |
| 567 | − 0x77ffc081 | |
| 568 | − 0x00000e0e | |
| 569 | − 0x81f1f108 | |
| 570 | − 0x07070004 | |
| 571 | − 0x0000003f | |
| 572 | − 0x016eeeee | |
| 573 | − 0x51451400 | |
| 574 | − 0x00514514 | |
| 575 | − 0x00514514 | |
| 576 | − 0x51451400 | |
| 577 | − 0x0000003f | |
| 578 | − 0x00000015 | |
| 579 | − 0x00000000 | |
| 580 | − 0x00000042 | |
| 581 | − 0x000e000e | |
| 582 | − 0x00000000 | |
| 263 | + 0x00000004 | |
| 264 | + 0x00000001 | |
| 265 | + 0x00000002 | |
| 266 | + 0x00000007 | |
| 267 | + 0x00000002 | |
| 268 | + 0x00000002 | |
| 269 | + 0x00000004 | |
| 270 | + 0x00000006 | |
| 271 | + 0x06040202 | |
| 272 | + 0x000b0607 | |
| 273 | + 0x77450e08 | |
| 274 | + 0x70000f03 | |
| 275 | + 0x001f0000 | |
| 276 | + >; | |
| 277 | + }; | |
| 278 | + | |
| 279 | + timing-396000000 { | |
| 280 | + clock-frequency = <396000000>; | |
| 281 | + | |
| 282 | + nvidia,emem-configuration = < | |
| 283 | + 0x0f000005 | |
| 284 | + 0x80000040 | |
| 285 | + 0x00000001 | |
| 286 | + 0x00000002 | |
| 287 | + 0x00000009 | |
| 288 | + 0x00000005 | |
| 289 | + 0x00000006 | |
| 290 | + 0x00000001 | |
| 291 | + 0x00000002 | |
| 292 | + 0x00000008 | |
| 293 | + 0x00000002 | |
| 294 | + 0x00000002 | |
| 295 | + 0x00000004 | |
| 296 | + 0x00000006 | |
| 297 | + 0x06040202 | |
| 298 | + 0x000d0709 | |
| 299 | + 0x7586120a | |
| 300 | + 0x70000f03 | |
| 301 | + 0x001f0000 | |
| 302 | + >; | |
| 303 | + }; | |
| 304 | + | |
| 305 | + timing-528000000 { | |
| 306 | + clock-frequency = <528000000>; | |
| 307 | + | |
| 308 | + nvidia,emem-configuration = < | |
| 309 | + 0x0f000007 | |
| 310 | + 0x80000040 | |
| 311 | + 0x00000002 | |
| 583 | 312 | 0x00000003 |
| 584 | − 0x0000f2f3 | |
| 585 | − 0x80000370 | |
| 313 | + 0x0000000c | |
| 314 | + 0x00000007 | |
| 315 | + 0x00000008 | |
| 316 | + 0x00000001 | |
| 317 | + 0x00000002 | |
| 318 | + 0x00000009 | |
| 319 | + 0x00000002 | |
| 320 | + 0x00000002 | |
| 321 | + 0x00000005 | |
| 322 | + 0x00000006 | |
| 323 | + 0x06050202 | |
| 324 | + 0x0010090c | |
| 325 | + 0x7428180d | |
| 326 | + 0x70000f03 | |
| 327 | + 0x001f0000 | |
| 328 | + >; | |
| 329 | + }; | |
| 330 | + | |
| 331 | + timing-600000000 { | |
| 332 | + clock-frequency = <600000000>; | |
| 333 | + | |
| 334 | + nvidia,emem-configuration = < | |
| 335 | + 0x00000009 | |
| 336 | + 0x80000040 | |
| 337 | + 0x00000003 | |
| 338 | + 0x00000004 | |
| 339 | + 0x0000000e | |
| 340 | + 0x00000009 | |
| 586 | 341 | 0x0000000a |
| 342 | + 0x00000001 | |
| 343 | + 0x00000003 | |
| 344 | + 0x0000000b | |
| 345 | + 0x00000002 | |
| 346 | + 0x00000002 | |
| 347 | + 0x00000005 | |
| 348 | + 0x00000007 | |
| 349 | + 0x07050202 | |
| 350 | + 0x00130b0e | |
| 351 | + 0x73a91b0f | |
| 352 | + 0x70000f03 | |
| 353 | + 0x001f0000 | |
| 587 | 354 | >; |
| 588 | 355 | }; |
| 589 | 356 | |
| 590 | − timing-68000000 { | |
| 591 | − clock-frequency = <68000000>; | |
| 357 | + timing-792000000 { | |
| 358 | + clock-frequency = <792000000>; | |
| 359 | + | |
| 360 | + nvidia,emem-configuration = < | |
| 361 | + 0x0e00000b | |
| 362 | + 0x80000040 | |
| 363 | + 0x00000004 | |
| 364 | + 0x00000005 | |
| 365 | + 0x00000013 | |
| 366 | + 0x0000000c | |
| 367 | + 0x0000000d | |
| 368 | + 0x00000002 | |
| 369 | + 0x00000003 | |
| 370 | + 0x0000000c | |
| 371 | + 0x00000002 | |
| 372 | + 0x00000002 | |
| 373 | + 0x00000006 | |
| 374 | + 0x00000008 | |
| 375 | + 0x08060202 | |
| 376 | + 0x00170e13 | |
| 377 | + 0x736c2414 | |
| 378 | + 0x70000f02 | |
| 379 | + 0x001f0000 | |
| 380 | + >; | |
| 381 | + }; | |
| 382 | + | |
| 383 | + timing-924000000 { | |
| 384 | + clock-frequency = <924000000>; | |
| 385 | + | |
| 386 | + nvidia,emem-configuration = < | |
| 387 | + 0x0e00000d | |
| 388 | + 0x80000040 | |
| 389 | + 0x00000005 | |
| 390 | + 0x00000006 | |
| 391 | + 0x00000016 | |
| 392 | + 0x0000000e | |
| 393 | + 0x0000000f | |
| 394 | + 0x00000002 | |
| 395 | + 0x00000004 | |
| 396 | + 0x0000000e | |
| 397 | + 0x00000002 | |
| 398 | + 0x00000002 | |
| 399 | + 0x00000006 | |
| 400 | + 0x00000009 | |
| 401 | + 0x09060202 | |
| 402 | + 0x001a1016 | |
| 403 | + 0x734e2a17 | |
| 404 | + 0x70000f02 | |
| 405 | + 0x001f0000 | |
| 406 | + >; | |
| 407 | + }; | |
| 408 | + }; | |
| 409 | + }; | |
| 410 | + | |
| 411 | + external-memory-controller@7001b000 { | |
| 412 | + emc-timings-3 { | |
| 413 | + nvidia,ram-code = <3>; | |
| 414 | + | |
| 415 | + timing-12750000 { | |
| 416 | + clock-frequency = <12750000>; | |
| 592 | 417 | |
| 593 | 418 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 594 | 419 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| @@ -609,10 +434,10 @@ · 14 unmodified lines | ||
| 609 | 434 | nvidia,emc-zcal-interval = <0x00000000>; |
| 610 | 435 | |
| 611 | 436 | nvidia,emc-configuration = < |
| 437 | + 0x00000000 | |
| 612 | 438 | 0x00000003 |
| 613 | − 0x00000011 | |
| 614 | 439 | 0x00000000 |
| 615 | − 0x00000002 | |
| 440 | + 0x00000000 | |
| 616 | 441 | 0x00000000 |
| 617 | 442 | 0x00000004 |
| 618 | 443 | 0x0000000a |
| @@ -640,25 +465,25 @@ · 21 unmodified lines | ||
| 640 | 465 | 0x0000000c |
| 641 | 466 | 0x0000000d |
| 642 | 467 | 0x0000000f |
| 643 | − 0x00000202 | |
| 468 | + 0x00000060 | |
| 644 | 469 | 0x00000000 |
| 645 | − 0x00000080 | |
| 470 | + 0x00000018 | |
| 646 | 471 | 0x00000002 |
| 647 | 472 | 0x00000002 |
| 648 | 473 | 0x00000001 |
| 649 | 474 | 0x00000000 |
| 475 | + 0x00000007 | |
| 650 | 476 | 0x0000000f |
| 651 | − 0x0000000f | |
| 652 | − 0x00000013 | |
| 653 | − 0x00000013 | |
| 477 | + 0x00000005 | |
| 478 | + 0x00000005 | |
| 654 | 479 | 0x00000004 |
| 655 | 480 | 0x00000005 |
| 656 | 481 | 0x00000004 |
| 657 | − 0x00000001 | |
| 482 | + 0x00000000 | |
| 658 | 483 | 0x00000000 |
| 659 | 484 | 0x00000005 |
| 660 | 485 | 0x00000005 |
| 661 | − 0x00000213 | |
| 486 | + 0x00000064 | |
| 662 | 487 | 0x00000000 |
| 663 | 488 | 0x00000000 |
| 664 | 489 | 0x00000000 |
| @@ -743,21 +568,21 @@ · 78 unmodified lines | ||
| 743 | 568 | 0x00514514 |
| 744 | 569 | 0x51451400 |
| 745 | 570 | 0x0000003f |
| 746 | − 0x00000022 | |
| 571 | + 0x00000007 | |
| 747 | 572 | 0x00000000 |
| 748 | 573 | 0x00000042 |
| 749 | 574 | 0x000e000e |
| 750 | 575 | 0x00000000 |
| 751 | 576 | 0x00000003 |
| 752 | 577 | 0x0000f2f3 |
| 753 | − 0x8000050e | |
| 578 | + 0x800001c5 | |
| 754 | 579 | 0x0000000a |
| 755 | 580 | >; |
| 756 | 581 | }; |
| 757 | 582 | |
| 758 | − timing-102000000 { | |
| 759 | − clock-frequency = <102000000>; | |
| 760 | − | |
| 583 | + timing-20400000 { | |
| 584 | + clock-frequency = <20400000>; | |
| 585 | + | |
| 761 | 586 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 762 | 587 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 763 | 588 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| @@ -777,17 +602,17 @@ · 13 unmodified lines | ||
| 777 | 602 | nvidia,emc-zcal-interval = <0x00000000>; |
| 778 | 603 | |
| 779 | 604 | nvidia,emc-configuration = < |
| 780 | − 0x00000004 | |
| 781 | − 0x0000001a | |
| 782 | 605 | 0x00000000 |
| 783 | − 0x00000003 | |
| 784 | − 0x00000001 | |
| 606 | + 0x00000005 | |
| 607 | + 0x00000000 | |
| 608 | + 0x00000000 | |
| 609 | + 0x00000000 | |
| 785 | 610 | 0x00000004 |
| 786 | 611 | 0x0000000a |
| 787 | 612 | 0x00000005 |
| 788 | 613 | 0x0000000b |
| 789 | − 0x00000001 | |
| 790 | − 0x00000001 | |
| 614 | + 0x00000000 | |
| 615 | + 0x00000000 | |
| 791 | 616 | 0x00000003 |
| 792 | 617 | 0x00000003 |
| 793 | 618 | 0x00000000 |
| @@ -808,25 +633,25 @@ · 14 unmodified lines | ||
| 808 | 633 | 0x0000000c |
| 809 | 634 | 0x0000000d |
| 810 | 635 | 0x0000000f |
| 811 | − 0x00000304 | |
| 636 | + 0x0000009a | |
| 812 | 637 | 0x00000000 |
| 813 | − 0x000000c1 | |
| 638 | + 0x00000026 | |
| 814 | 639 | 0x00000002 |
| 815 | 640 | 0x00000002 |
| 816 | 641 | 0x00000001 |
| 817 | 642 | 0x00000000 |
| 818 | − 0x00000018 | |
| 643 | + 0x00000007 | |
| 819 | 644 | 0x0000000f |
| 820 | − 0x0000001c | |
| 821 | − 0x0000001c | |
| 645 | + 0x00000006 | |
| 646 | + 0x00000006 | |
| 822 | 647 | 0x00000004 |
| 823 | 648 | 0x00000005 |
| 824 | 649 | 0x00000004 |
| 825 | − 0x00000002 | |
| 650 | + 0x00000000 | |
| 826 | 651 | 0x00000000 |
| 827 | 652 | 0x00000005 |
| 828 | 653 | 0x00000005 |
| 829 | − 0x0000031c | |
| 654 | + 0x000000a0 | |
| 830 | 655 | 0x00000000 |
| 831 | 656 | 0x00000000 |
| 832 | 657 | 0x00000000 |
| @@ -911,20 +736,20 @@ · 78 unmodified lines | ||
| 911 | 736 | 0x00514514 |
| 912 | 737 | 0x51451400 |
| 913 | 738 | 0x0000003f |
| 914 | − 0x00000033 | |
| 739 | + 0x0000000b | |
| 915 | 740 | 0x00000000 |
| 916 | 741 | 0x00000042 |
| 917 | 742 | 0x000e000e |
| 918 | 743 | 0x00000000 |
| 919 | 744 | 0x00000003 |
| 920 | 745 | 0x0000f2f3 |
| 921 | − 0x80000713 | |
| 746 | + 0x8000023a | |
| 922 | 747 | 0x0000000a |
| 923 | 748 | >; |
| 924 | 749 | }; |
| 925 | 750 | |
| 926 | − timing-204000000 { | |
| 927 | − clock-frequency = <204000000>; | |
| 751 | + timing-40800000 { | |
| 752 | + clock-frequency = <40800000>; | |
| 928 | 753 | |
| 929 | 754 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 930 | 755 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| @@ -932,7 +757,7 @@ · 1 unmodified line | ||
| 932 | 757 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 933 | 758 | nvidia,emc-bgbias-ctl0 = <0x00000008>; |
| 934 | 759 | nvidia,emc-cfg = <0x73240000>; |
| 935 | − nvidia,emc-cfg-2 = <0x000008cd>; | |
| 760 | + nvidia,emc-cfg-2 = <0x000008c5>; | |
| 936 | 761 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 937 | 762 | nvidia,emc-mode-1 = <0x80100003>; |
| 938 | 763 | nvidia,emc-mode-2 = <0x80200008>; |
| @@ -942,59 +767,59 @@ · 3 unmodified lines | ||
| 942 | 767 | nvidia,emc-sel-dpd-ctrl = <0x00040128>; |
| 943 | 768 | nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; |
| 944 | 769 | nvidia,emc-zcal-cnt-long = <0x00000042>; |
| 945 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 770 | + nvidia,emc-zcal-interval = <0x00000000>; | |
| 946 | 771 | |
| 947 | 772 | nvidia,emc-configuration = < |
| 948 | − 0x00000009 | |
| 949 | − 0x00000035 | |
| 773 | + 0x00000001 | |
| 774 | + 0x0000000a | |
| 950 | 775 | 0x00000000 |
| 951 | − 0x00000006 | |
| 952 | − 0x00000002 | |
| 953 | − 0x00000005 | |
| 776 | + 0x00000001 | |
| 777 | + 0x00000000 | |
| 778 | + 0x00000004 | |
| 954 | 779 | 0x0000000a |
| 955 | 780 | 0x00000005 |
| 956 | 781 | 0x0000000b |
| 957 | − 0x00000002 | |
| 958 | − 0x00000002 | |
| 782 | + 0x00000000 | |
| 783 | + 0x00000000 | |
| 959 | 784 | 0x00000003 |
| 960 | 785 | 0x00000003 |
| 961 | 786 | 0x00000000 |
| 962 | − 0x00000005 | |
| 963 | − 0x00000005 | |
| 787 | + 0x00000006 | |
| 788 | + 0x00000006 | |
| 964 | 789 | 0x00000006 |
| 965 | 790 | 0x00000002 |
| 966 | 791 | 0x00000000 |
| 967 | − 0x00000004 | |
| 968 | − 0x00000006 | |
| 792 | + 0x00000005 | |
| 793 | + 0x00000005 | |
| 969 | 794 | 0x00010000 |
| 970 | 795 | 0x00000003 |
| 971 | 796 | 0x00000000 |
| 972 | 797 | 0x00000000 |
| 973 | 798 | 0x00000000 |
| 974 | 799 | 0x00000000 |
| 975 | − 0x00000003 | |
| 800 | + 0x00000004 | |
| 801 | + 0x0000000c | |
| 976 | 802 | 0x0000000d |
| 977 | 803 | 0x0000000f |
| 978 | − 0x00000011 | |
| 979 | − 0x00000607 | |
| 804 | + 0x00000134 | |
| 980 | 805 | 0x00000000 |
| 981 | − 0x00000181 | |
| 806 | + 0x0000004d | |
| 982 | 807 | 0x00000002 |
| 983 | 808 | 0x00000002 |
| 984 | 809 | 0x00000001 |
| 985 | 810 | 0x00000000 |
| 986 | − 0x00000032 | |
| 811 | + 0x00000008 | |
| 987 | 812 | 0x0000000f |
| 988 | − 0x00000038 | |
| 989 | − 0x00000038 | |
| 813 | + 0x0000000c | |
| 814 | + 0x0000000c | |
| 990 | 815 | 0x00000004 |
| 991 | 816 | 0x00000005 |
| 992 | 817 | 0x00000004 |
| 993 | − 0x00000006 | |
| 818 | + 0x00000000 | |
| 994 | 819 | 0x00000000 |
| 995 | 820 | 0x00000005 |
| 996 | 821 | 0x00000005 |
| 997 | − 0x00000638 | |
| 822 | + 0x0000013f | |
| 998 | 823 | 0x00000000 |
| 999 | 824 | 0x00000000 |
| 1000 | 825 | 0x00000000 |
| @@ -1027,10 +852,8 @@ · 26 unmodified lines | ||
| 1027 | 852 | 0x00000000 |
| 1028 | 853 | 0x00000000 |
| 1029 | 854 | 0x00000000 |
| 1030 | − 0x00008000 | |
| 1031 | 855 | 0x00000000 |
| 1032 | 856 | 0x00000000 |
| 1033 | − 0x00008000 | |
| 1034 | 857 | 0x00000000 |
| 1035 | 858 | 0x00000000 |
| 1036 | 859 | 0x00000000 |
| @@ -1055,21 +878,23 @@ · 18 unmodified lines | ||
| 1055 | 878 | 0x00000000 |
| 1056 | 879 | 0x00000000 |
| 1057 | 880 | 0x00000000 |
| 1058 | − 0x00090000 | |
| 1059 | − 0x00090000 | |
| 1060 | − 0x00090000 | |
| 1061 | − 0x00090000 | |
| 1062 | − 0x00009000 | |
| 1063 | − 0x00009000 | |
| 1064 | − 0x00009000 | |
| 1065 | − 0x00009000 | |
| 881 | + 0x00000000 | |
| 882 | + 0x00000000 | |
| 883 | + 0x000fc000 | |
| 884 | + 0x000fc000 | |
| 885 | + 0x000fc000 | |
| 886 | + 0x000fc000 | |
| 887 | + 0x0000fc00 | |
| 888 | + 0x0000fc00 | |
| 889 | + 0x0000fc00 | |
| 890 | + 0x0000fc00 | |
| 1066 | 891 | 0x10000280 |
| 1067 | 892 | 0x00000000 |
| 1068 | 893 | 0x00111111 |
| 1069 | 894 | 0x00000000 |
| 1070 | 895 | 0x00000000 |
| 1071 | 896 | 0x77ffc081 |
| 1072 | − 0x00000707 | |
| 897 | + 0x00000e0e | |
| 1073 | 898 | 0x81f1f108 |
| 1074 | 899 | 0x07070004 |
| 1075 | 900 | 0x0000003f |
| @@ -1079,112 +904,112 @@ · 3 unmodified lines | ||
| 1079 | 904 | 0x00514514 |
| 1080 | 905 | 0x51451400 |
| 1081 | 906 | 0x0000003f |
| 1082 | − 0x00000066 | |
| 907 | + 0x00000015 | |
| 1083 | 908 | 0x00000000 |
| 1084 | − 0x00000100 | |
| 909 | + 0x00000042 | |
| 1085 | 910 | 0x000e000e |
| 1086 | 911 | 0x00000000 |
| 1087 | 912 | 0x00000003 |
| 1088 | − 0x0000d2b3 | |
| 1089 | − 0x80000d22 | |
| 913 | + 0x0000f2f3 | |
| 914 | + 0x80000370 | |
| 1090 | 915 | 0x0000000a |
| 1091 | 916 | >; |
| 1092 | 917 | }; |
| 1093 | 918 | |
| 1094 | − timing-300000000 { | |
| 1095 | − clock-frequency = <300000000>; | |
| 919 | + timing-68000000 { | |
| 920 | + clock-frequency = <68000000>; | |
| 1096 | 921 | |
| 1097 | 922 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 1098 | 923 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 1099 | 924 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| 1100 | 925 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1101 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1102 | − nvidia,emc-cfg = <0x73340000>; | |
| 1103 | − nvidia,emc-cfg-2 = <0x000008d5>; | |
| 926 | + nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 927 | + nvidia,emc-cfg = <0x73240000>; | |
| 928 | + nvidia,emc-cfg-2 = <0x000008c5>; | |
| 1104 | 929 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 1105 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1106 | − nvidia,emc-mode-2 = <0x80200000>; | |
| 930 | + nvidia,emc-mode-1 = <0x80100003>; | |
| 931 | + nvidia,emc-mode-2 = <0x80200008>; | |
| 1107 | 932 | nvidia,emc-mode-4 = <0x00000000>; |
| 1108 | − nvidia,emc-mode-reset = <0x80000321>; | |
| 1109 | − nvidia,emc-mrs-wait-cnt = <0x0173000e>; | |
| 933 | + nvidia,emc-mode-reset = <0x80001221>; | |
| 934 | + nvidia,emc-mrs-wait-cnt = <0x000e000e>; | |
| 1110 | 935 | nvidia,emc-sel-dpd-ctrl = <0x00040128>; |
| 1111 | − nvidia,emc-xm2dqspadctrl2 = <0x01231339>; | |
| 936 | + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 1112 | 937 | nvidia,emc-zcal-cnt-long = <0x00000042>; |
| 1113 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 938 | + nvidia,emc-zcal-interval = <0x00000000>; | |
| 1114 | 939 | |
| 1115 | 940 | nvidia,emc-configuration = < |
| 1116 | − 0x0000000d | |
| 1117 | − 0x0000004d | |
| 1118 | − 0x00000000 | |
| 1119 | − 0x00000009 | |
| 1120 | − 0x00000003 | |
| 1121 | − 0x00000004 | |
| 1122 | − 0x00000008 | |
| 1123 | − 0x00000002 | |
| 1124 | − 0x00000009 | |
| 1125 | 941 | 0x00000003 |
| 1126 | − 0x00000003 | |
| 1127 | − 0x00000002 | |
| 942 | + 0x00000011 | |
| 943 | + 0x00000000 | |
| 1128 | 944 | 0x00000002 |
| 1129 | 945 | 0x00000000 |
| 946 | + 0x00000004 | |
| 947 | + 0x0000000a | |
| 948 | + 0x00000005 | |
| 949 | + 0x0000000b | |
| 950 | + 0x00000000 | |
| 951 | + 0x00000000 | |
| 1130 | 952 | 0x00000003 |
| 1131 | 953 | 0x00000003 |
| 1132 | − 0x00000005 | |
| 1133 | − 0x00000002 | |
| 1134 | 954 | 0x00000000 |
| 955 | + 0x00000006 | |
| 956 | + 0x00000006 | |
| 957 | + 0x00000006 | |
| 1135 | 958 | 0x00000002 |
| 1136 | − 0x00000007 | |
| 1137 | − 0x00020000 | |
| 959 | + 0x00000000 | |
| 960 | + 0x00000005 | |
| 961 | + 0x00000005 | |
| 962 | + 0x00010000 | |
| 1138 | 963 | 0x00000003 |
| 1139 | 964 | 0x00000000 |
| 1140 | 965 | 0x00000000 |
| 1141 | 966 | 0x00000000 |
| 1142 | 967 | 0x00000000 |
| 1143 | − 0x00000001 | |
| 1144 | − 0x0000000e | |
| 1145 | − 0x00000010 | |
| 1146 | − 0x00000012 | |
| 1147 | − 0x000008e4 | |
| 968 | + 0x00000004 | |
| 969 | + 0x0000000c | |
| 970 | + 0x0000000d | |
| 971 | + 0x0000000f | |
| 972 | + 0x00000202 | |
| 1148 | 973 | 0x00000000 |
| 1149 | − 0x00000239 | |
| 1150 | − 0x00000001 | |
| 1151 | − 0x00000008 | |
| 974 | + 0x00000080 | |
| 975 | + 0x00000002 | |
| 976 | + 0x00000002 | |
| 1152 | 977 | 0x00000001 |
| 1153 | 978 | 0x00000000 |
| 1154 | − 0x0000004b | |
| 1155 | − 0x0000000e | |
| 1156 | − 0x00000052 | |
| 1157 | − 0x00000200 | |
| 979 | + 0x0000000f | |
| 980 | + 0x0000000f | |
| 981 | + 0x00000013 | |
| 982 | + 0x00000013 | |
| 1158 | 983 | 0x00000004 |
| 1159 | 984 | 0x00000005 |
| 1160 | 985 | 0x00000004 |
| 1161 | − 0x00000008 | |
| 986 | + 0x00000001 | |
| 1162 | 987 | 0x00000000 |
| 1163 | 988 | 0x00000005 |
| 1164 | 989 | 0x00000005 |
| 1165 | − 0x00000924 | |
| 990 | + 0x00000213 | |
| 1166 | 991 | 0x00000000 |
| 1167 | 992 | 0x00000000 |
| 1168 | 993 | 0x00000000 |
| 1169 | − 0x104ab098 | |
| 994 | + 0x106aa298 | |
| 1170 | 995 | 0x002c00a0 |
| 1171 | 996 | 0x00008000 |
| 1172 | − 0x00030000 | |
| 1173 | − 0x00030000 | |
| 1174 | − 0x00030000 | |
| 1175 | − 0x00030000 | |
| 1176 | − 0x00030000 | |
| 1177 | − 0x00030000 | |
| 1178 | − 0x00030000 | |
| 1179 | − 0x00030000 | |
| 1180 | − 0x00030000 | |
| 1181 | − 0x00030000 | |
| 1182 | − 0x00030000 | |
| 1183 | − 0x00030000 | |
| 1184 | − 0x00030000 | |
| 1185 | − 0x00030000 | |
| 1186 | − 0x00030000 | |
| 1187 | − 0x00030000 | |
| 997 | + 0x00080000 | |
| 998 | + 0x00080000 | |
| 999 | + 0x00080000 | |
| 1000 | + 0x00080000 | |
| 1001 | + 0x00080000 | |
| 1002 | + 0x00080000 | |
| 1003 | + 0x00080000 | |
| 1004 | + 0x00080000 | |
| 1005 | + 0x00080000 | |
| 1006 | + 0x00080000 | |
| 1007 | + 0x00080000 | |
| 1008 | + 0x00080000 | |
| 1009 | + 0x00080000 | |
| 1010 | + 0x00080000 | |
| 1011 | + 0x00080000 | |
| 1012 | + 0x00080000 | |
| 1188 | 1013 | 0x00000000 |
| 1189 | 1014 | 0x00000000 |
| 1190 | 1015 | 0x00000000 |
| @@ -1193,11 +1018,7 @@ · 2 unmodified lines | ||
| 1193 | 1018 | 0x00000000 |
| 1194 | 1019 | 0x00000000 |
| 1195 | 1020 | 0x00000000 |
| 1196 | − 0x00098000 | |
| 1197 | − 0x00098000 | |
| 1198 | 1021 | 0x00000000 |
| 1199 | − 0x00098000 | |
| 1200 | − 0x00098000 | |
| 1201 | 1022 | 0x00000000 |
| 1202 | 1023 | 0x00000000 |
| 1203 | 1024 | 0x00000000 |
| @@ -1223,136 +1044,140 @@ · 19 unmodified lines | ||
| 1223 | 1044 | 0x00000000 |
| 1224 | 1045 | 0x00000000 |
| 1225 | 1046 | 0x00000000 |
| 1226 | − 0x00050000 | |
| 1227 | − 0x00050000 | |
| 1228 | − 0x00050000 | |
| 1229 | − 0x00050000 | |
| 1230 | − 0x00005000 | |
| 1231 | − 0x00005000 | |
| 1232 | − 0x00005000 | |
| 1233 | − 0x00005000 | |
| 1047 | + 0x00000000 | |
| 1048 | + 0x00000000 | |
| 1049 | + 0x00000000 | |
| 1050 | + 0x00000000 | |
| 1051 | + 0x000fc000 | |
| 1052 | + 0x000fc000 | |
| 1053 | + 0x000fc000 | |
| 1054 | + 0x000fc000 | |
| 1055 | + 0x0000fc00 | |
| 1056 | + 0x0000fc00 | |
| 1057 | + 0x0000fc00 | |
| 1058 | + 0x0000fc00 | |
| 1234 | 1059 | 0x10000280 |
| 1235 | 1060 | 0x00000000 |
| 1236 | 1061 | 0x00111111 |
| 1237 | 1062 | 0x00000000 |
| 1238 | 1063 | 0x00000000 |
| 1239 | 1064 | 0x77ffc081 |
| 1240 | − 0x00000505 | |
| 1065 | + 0x00000e0e | |
| 1241 | 1066 | 0x81f1f108 |
| 1242 | 1067 | 0x07070004 |
| 1243 | − 0x00000000 | |
| 1068 | + 0x0000003f | |
| 1244 | 1069 | 0x016eeeee |
| 1245 | − 0x51451420 | |
| 1070 | + 0x51451400 | |
| 1246 | 1071 | 0x00514514 |
| 1247 | 1072 | 0x00514514 |
| 1248 | 1073 | 0x51451400 |
| 1249 | 1074 | 0x0000003f |
| 1250 | − 0x00000096 | |
| 1075 | + 0x00000022 | |
| 1251 | 1076 | 0x00000000 |
| 1252 | − 0x00000100 | |
| 1253 | − 0x0173000e | |
| 1077 | + 0x00000042 | |
| 1078 | + 0x000e000e | |
| 1254 | 1079 | 0x00000000 |
| 1255 | 1080 | 0x00000003 |
| 1256 | − 0x000052a3 | |
| 1257 | − 0x800012d7 | |
| 1258 | − 0x00000009 | |
| 1081 | + 0x0000f2f3 | |
| 1082 | + 0x8000050e | |
| 1083 | + 0x0000000a | |
| 1259 | 1084 | >; |
| 1260 | 1085 | }; |
| 1261 | 1086 | |
| 1262 | − timing-396000000 { | |
| 1263 | − clock-frequency = <396000000>; | |
| 1087 | + timing-102000000 { | |
| 1088 | + clock-frequency = <102000000>; | |
| 1264 | 1089 | |
| 1265 | 1090 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 1266 | 1091 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 1267 | 1092 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| 1268 | 1093 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1269 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1270 | − nvidia,emc-cfg = <0x73340000>; | |
| 1271 | − nvidia,emc-cfg-2 = <0x00000895>; | |
| 1094 | + nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 1095 | + nvidia,emc-cfg = <0x73240000>; | |
| 1096 | + nvidia,emc-cfg-2 = <0x000008c5>; | |
| 1272 | 1097 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 1273 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1274 | − nvidia,emc-mode-2 = <0x80200000>; | |
| 1098 | + nvidia,emc-mode-1 = <0x80100003>; | |
| 1099 | + nvidia,emc-mode-2 = <0x80200008>; | |
| 1275 | 1100 | nvidia,emc-mode-4 = <0x00000000>; |
| 1276 | − nvidia,emc-mode-reset = <0x80000521>; | |
| 1277 | − nvidia,emc-mrs-wait-cnt = <0x015b000e>; | |
| 1278 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1279 | − nvidia,emc-xm2dqspadctrl2 = <0x01231339>; | |
| 1101 | + nvidia,emc-mode-reset = <0x80001221>; | |
| 1102 | + nvidia,emc-mrs-wait-cnt = <0x000e000e>; | |
| 1103 | + nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 1104 | + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 1280 | 1105 | nvidia,emc-zcal-cnt-long = <0x00000042>; |
| 1281 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 1106 | + nvidia,emc-zcal-interval = <0x00000000>; | |
| 1282 | 1107 | |
| 1283 | 1108 | nvidia,emc-configuration = < |
| 1284 | − 0x00000011 | |
| 1285 | − 0x00000066 | |
| 1286 | − 0x00000000 | |
| 1287 | − 0x0000000c | |
| 1288 | 1109 | 0x00000004 |
| 1110 | + 0x0000001a | |
| 1111 | + 0x00000000 | |
| 1112 | + 0x00000003 | |
| 1113 | + 0x00000001 | |
| 1289 | 1114 | 0x00000004 |
| 1290 | − 0x00000008 | |
| 1291 | − 0x00000002 | |
| 1292 | 1115 | 0x0000000a |
| 1293 | − 0x00000004 | |
| 1294 | − 0x00000004 | |
| 1295 | − 0x00000002 | |
| 1296 | − 0x00000002 | |
| 1297 | − 0x00000000 | |
| 1116 | + 0x00000005 | |
| 1117 | + 0x0000000b | |
| 1118 | + 0x00000001 | |
| 1119 | + 0x00000001 | |
| 1298 | 1120 | 0x00000003 |
| 1299 | 1121 | 0x00000003 |
| 1300 | − 0x00000005 | |
| 1122 | + 0x00000000 | |
| 1123 | + 0x00000006 | |
| 1124 | + 0x00000006 | |
| 1125 | + 0x00000006 | |
| 1301 | 1126 | 0x00000002 |
| 1302 | 1127 | 0x00000000 |
| 1303 | − 0x00000001 | |
| 1304 | − 0x00000008 | |
| 1305 | − 0x00020000 | |
| 1128 | + 0x00000005 | |
| 1129 | + 0x00000005 | |
| 1130 | + 0x00010000 | |
| 1306 | 1131 | 0x00000003 |
| 1307 | 1132 | 0x00000000 |
| 1308 | 1133 | 0x00000000 |
| 1309 | 1134 | 0x00000000 |
| 1310 | 1135 | 0x00000000 |
| 1311 | − 0x00000000 | |
| 1136 | + 0x00000004 | |
| 1137 | + 0x0000000c | |
| 1138 | + 0x0000000d | |
| 1312 | 1139 | 0x0000000f |
| 1313 | − 0x00000010 | |
| 1314 | − 0x00000012 | |
| 1315 | − 0x00000bd1 | |
| 1140 | + 0x00000304 | |
| 1316 | 1141 | 0x00000000 |
| 1317 | − 0x000002f4 | |
| 1318 | − 0x00000001 | |
| 1319 | − 0x00000008 | |
| 1142 | + 0x000000c1 | |
| 1143 | + 0x00000002 | |
| 1144 | + 0x00000002 | |
| 1320 | 1145 | 0x00000001 |
| 1321 | 1146 | 0x00000000 |
| 1322 | − 0x00000063 | |
| 1147 | + 0x00000018 | |
| 1323 | 1148 | 0x0000000f |
| 1324 | − 0x0000006c | |
| 1325 | − 0x00000200 | |
| 1149 | + 0x0000001c | |
| 1150 | + 0x0000001c | |
| 1326 | 1151 | 0x00000004 |
| 1327 | 1152 | 0x00000005 |
| 1328 | 1153 | 0x00000004 |
| 1329 | − 0x0000000b | |
| 1154 | + 0x00000002 | |
| 1330 | 1155 | 0x00000000 |
| 1331 | 1156 | 0x00000005 |
| 1332 | 1157 | 0x00000005 |
| 1333 | − 0x00000c11 | |
| 1158 | + 0x0000031c | |
| 1334 | 1159 | 0x00000000 |
| 1335 | 1160 | 0x00000000 |
| 1336 | 1161 | 0x00000000 |
| 1337 | − 0x104ab098 | |
| 1162 | + 0x106aa298 | |
| 1338 | 1163 | 0x002c00a0 |
| 1339 | 1164 | 0x00008000 |
| 1340 | − 0x00030000 | |
| 1341 | − 0x00030000 | |
| 1342 | − 0x00030000 | |
| 1343 | − 0x00030000 | |
| 1344 | − 0x00030000 | |
| 1345 | − 0x00030000 | |
| 1346 | − 0x00030000 | |
| 1347 | − 0x00030000 | |
| 1348 | − 0x00030000 | |
| 1349 | − 0x00030000 | |
| 1350 | − 0x00030000 | |
| 1351 | − 0x00030000 | |
| 1352 | − 0x00030000 | |
| 1353 | − 0x00030000 | |
| 1354 | − 0x00030000 | |
| 1355 | − 0x00030000 | |
| 1165 | + 0x00080000 | |
| 1166 | + 0x00080000 | |
| 1167 | + 0x00080000 | |
| 1168 | + 0x00080000 | |
| 1169 | + 0x00080000 | |
| 1170 | + 0x00080000 | |
| 1171 | + 0x00080000 | |
| 1172 | + 0x00080000 | |
| 1173 | + 0x00080000 | |
| 1174 | + 0x00080000 | |
| 1175 | + 0x00080000 | |
| 1176 | + 0x00080000 | |
| 1177 | + 0x00080000 | |
| 1178 | + 0x00080000 | |
| 1179 | + 0x00080000 | |
| 1180 | + 0x00080000 | |
| 1356 | 1181 | 0x00000000 |
| 1357 | 1182 | 0x00000000 |
| 1358 | 1183 | 0x00000000 |
| @@ -1361,11 +1186,7 @@ · 2 unmodified lines | ||
| 1361 | 1186 | 0x00000000 |
| 1362 | 1187 | 0x00000000 |
| 1363 | 1188 | 0x00000000 |
| 1364 | − 0x00070000 | |
| 1365 | − 0x00070000 | |
| 1366 | 1189 | 0x00000000 |
| 1367 | − 0x00070000 | |
| 1368 | − 0x00070000 | |
| 1369 | 1190 | 0x00000000 |
| 1370 | 1191 | 0x00000000 |
| 1371 | 1192 | 0x00000000 |
| @@ -1391,136 +1212,140 @@ · 19 unmodified lines | ||
| 1391 | 1212 | 0x00000000 |
| 1392 | 1213 | 0x00000000 |
| 1393 | 1214 | 0x00000000 |
| 1394 | − 0x00038000 | |
| 1395 | − 0x00038000 | |
| 1396 | − 0x00038000 | |
| 1397 | − 0x00038000 | |
| 1398 | − 0x00003800 | |
| 1399 | − 0x00003800 | |
| 1400 | − 0x00003800 | |
| 1401 | − 0x00003800 | |
| 1215 | + 0x00000000 | |
| 1216 | + 0x00000000 | |
| 1217 | + 0x00000000 | |
| 1218 | + 0x00000000 | |
| 1219 | + 0x000fc000 | |
| 1220 | + 0x000fc000 | |
| 1221 | + 0x000fc000 | |
| 1222 | + 0x000fc000 | |
| 1223 | + 0x0000fc00 | |
| 1224 | + 0x0000fc00 | |
| 1225 | + 0x0000fc00 | |
| 1226 | + 0x0000fc00 | |
| 1402 | 1227 | 0x10000280 |
| 1403 | 1228 | 0x00000000 |
| 1404 | 1229 | 0x00111111 |
| 1405 | 1230 | 0x00000000 |
| 1406 | 1231 | 0x00000000 |
| 1407 | 1232 | 0x77ffc081 |
| 1408 | − 0x00000505 | |
| 1233 | + 0x00000e0e | |
| 1409 | 1234 | 0x81f1f108 |
| 1410 | 1235 | 0x07070004 |
| 1411 | − 0x00000000 | |
| 1236 | + 0x0000003f | |
| 1412 | 1237 | 0x016eeeee |
| 1413 | − 0x51451420 | |
| 1238 | + 0x51451400 | |
| 1414 | 1239 | 0x00514514 |
| 1415 | 1240 | 0x00514514 |
| 1416 | 1241 | 0x51451400 |
| 1417 | 1242 | 0x0000003f |
| 1418 | − 0x000000c6 | |
| 1243 | + 0x00000033 | |
| 1419 | 1244 | 0x00000000 |
| 1420 | − 0x00000100 | |
| 1421 | − 0x015b000e | |
| 1245 | + 0x00000042 | |
| 1246 | + 0x000e000e | |
| 1422 | 1247 | 0x00000000 |
| 1423 | 1248 | 0x00000003 |
| 1424 | − 0x000052a3 | |
| 1425 | − 0x8000188b | |
| 1426 | − 0x00000009 | |
| 1249 | + 0x0000f2f3 | |
| 1250 | + 0x80000713 | |
| 1251 | + 0x0000000a | |
| 1427 | 1252 | >; |
| 1428 | 1253 | }; |
| 1429 | 1254 | |
| 1430 | − timing-528000000 { | |
| 1431 | − clock-frequency = <528000000>; | |
| 1255 | + timing-204000000 { | |
| 1256 | + clock-frequency = <204000000>; | |
| 1432 | 1257 | |
| 1433 | 1258 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 1434 | 1259 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 1435 | 1260 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| 1436 | 1261 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1437 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1438 | − nvidia,emc-cfg = <0x73300000>; | |
| 1439 | − nvidia,emc-cfg-2 = <0x0000089d>; | |
| 1262 | + nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 1263 | + nvidia,emc-cfg = <0x73240000>; | |
| 1264 | + nvidia,emc-cfg-2 = <0x000008cd>; | |
| 1440 | 1265 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 1441 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1266 | + nvidia,emc-mode-1 = <0x80100003>; | |
| 1442 | 1267 | nvidia,emc-mode-2 = <0x80200008>; |
| 1443 | 1268 | nvidia,emc-mode-4 = <0x00000000>; |
| 1444 | − nvidia,emc-mode-reset = <0x80000941>; | |
| 1445 | − nvidia,emc-mrs-wait-cnt = <0x0139000e>; | |
| 1446 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1447 | − nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; | |
| 1269 | + nvidia,emc-mode-reset = <0x80001221>; | |
| 1270 | + nvidia,emc-mrs-wait-cnt = <0x000e000e>; | |
| 1271 | + nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 1272 | + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 1448 | 1273 | nvidia,emc-zcal-cnt-long = <0x00000042>; |
| 1449 | 1274 | nvidia,emc-zcal-interval = <0x00020000>; |
| 1450 | 1275 | |
| 1451 | 1276 | nvidia,emc-configuration = < |
| 1452 | − 0x00000018 | |
| 1453 | − 0x00000088 | |
| 1277 | + 0x00000009 | |
| 1278 | + 0x00000035 | |
| 1454 | 1279 | 0x00000000 |
| 1455 | − 0x00000010 | |
| 1456 | 1280 | 0x00000006 |
| 1457 | − 0x00000006 | |
| 1458 | − 0x00000009 | |
| 1459 | 1281 | 0x00000002 |
| 1460 | − 0x0000000d | |
| 1461 | − 0x00000006 | |
| 1462 | − 0x00000006 | |
| 1282 | + 0x00000005 | |
| 1283 | + 0x0000000a | |
| 1284 | + 0x00000005 | |
| 1285 | + 0x0000000b | |
| 1463 | 1286 | 0x00000002 |
| 1464 | 1287 | 0x00000002 |
| 1465 | − 0x00000000 | |
| 1466 | 1288 | 0x00000003 |
| 1467 | 1289 | 0x00000003 |
| 1290 | + 0x00000000 | |
| 1291 | + 0x00000005 | |
| 1292 | + 0x00000005 | |
| 1468 | 1293 | 0x00000006 |
| 1469 | 1294 | 0x00000002 |
| 1470 | 1295 | 0x00000000 |
| 1471 | − 0x00000001 | |
| 1472 | − 0x00000009 | |
| 1473 | − 0x00030000 | |
| 1296 | + 0x00000004 | |
| 1297 | + 0x00000006 | |
| 1298 | + 0x00010000 | |
| 1474 | 1299 | 0x00000003 |
| 1475 | 1300 | 0x00000000 |
| 1476 | 1301 | 0x00000000 |
| 1477 | 1302 | 0x00000000 |
| 1478 | 1303 | 0x00000000 |
| 1304 | + 0x00000003 | |
| 1305 | + 0x0000000d | |
| 1306 | + 0x0000000f | |
| 1307 | + 0x00000011 | |
| 1308 | + 0x00000607 | |
| 1479 | 1309 | 0x00000000 |
| 1480 | − 0x00000010 | |
| 1481 | − 0x00000012 | |
| 1482 | − 0x00000014 | |
| 1483 | − 0x00000fd6 | |
| 1484 | − 0x00000000 | |
| 1485 | − 0x000003f5 | |
| 1310 | + 0x00000181 | |
| 1311 | + 0x00000002 | |
| 1486 | 1312 | 0x00000002 |
| 1487 | − 0x0000000b | |
| 1488 | 1313 | 0x00000001 |
| 1489 | 1314 | 0x00000000 |
| 1490 | − 0x00000085 | |
| 1491 | − 0x00000012 | |
| 1492 | − 0x00000090 | |
| 1493 | − 0x00000200 | |
| 1315 | + 0x00000032 | |
| 1316 | + 0x0000000f | |
| 1317 | + 0x00000038 | |
| 1318 | + 0x00000038 | |
| 1494 | 1319 | 0x00000004 |
| 1495 | 1320 | 0x00000005 |
| 1496 | 1321 | 0x00000004 |
| 1497 | − 0x00000010 | |
| 1498 | − 0x00000000 | |
| 1499 | − 0x00000006 | |
| 1500 | 1322 | 0x00000006 |
| 1501 | − 0x00001017 | |
| 1502 | 1323 | 0x00000000 |
| 1324 | + 0x00000005 | |
| 1325 | + 0x00000005 | |
| 1326 | + 0x00000638 | |
| 1503 | 1327 | 0x00000000 |
| 1504 | 1328 | 0x00000000 |
| 1505 | − 0x104ab098 | |
| 1506 | − 0xe01200b1 | |
| 1329 | + 0x00000000 | |
| 1330 | + 0x106aa298 | |
| 1331 | + 0x002c00a0 | |
| 1507 | 1332 | 0x00008000 |
| 1508 | − 0x0000000a | |
| 1509 | − 0x0000000a | |
| 1510 | − 0x0000000a | |
| 1511 | − 0x0000000a | |
| 1512 | − 0x0000000a | |
| 1513 | − 0x0000000a | |
| 1514 | − 0x0000000a | |
| 1515 | − 0x0000000a | |
| 1516 | − 0x0000000a | |
| 1517 | − 0x0000000a | |
| 1518 | − 0x0000000a | |
| 1519 | − 0x0000000a | |
| 1520 | − 0x0000000a | |
| 1521 | − 0x0000000a | |
| 1522 | − 0x0000000a | |
| 1523 | − 0x0000000a | |
| 1333 | + 0x00080000 | |
| 1334 | + 0x00080000 | |
| 1335 | + 0x00080000 | |
| 1336 | + 0x00080000 | |
| 1337 | + 0x00080000 | |
| 1338 | + 0x00080000 | |
| 1339 | + 0x00080000 | |
| 1340 | + 0x00080000 | |
| 1341 | + 0x00080000 | |
| 1342 | + 0x00080000 | |
| 1343 | + 0x00080000 | |
| 1344 | + 0x00080000 | |
| 1345 | + 0x00080000 | |
| 1346 | + 0x00080000 | |
| 1347 | + 0x00080000 | |
| 1348 | + 0x00080000 | |
| 1524 | 1349 | 0x00000000 |
| 1525 | 1350 | 0x00000000 |
| 1526 | 1351 | 0x00000000 |
| @@ -1529,14 +1354,12 @@ · 2 unmodified lines | ||
| 1529 | 1354 | 0x00000000 |
| 1530 | 1355 | 0x00000000 |
| 1531 | 1356 | 0x00000000 |
| 1532 | − 0x00054000 | |
| 1533 | − 0x00054000 | |
| 1534 | 1357 | 0x00000000 |
| 1535 | − 0x00054000 | |
| 1536 | − 0x00054000 | |
| 1537 | 1358 | 0x00000000 |
| 1359 | + 0x00008000 | |
| 1538 | 1360 | 0x00000000 |
| 1539 | 1361 | 0x00000000 |
| 1362 | + 0x00008000 | |
| 1540 | 1363 | 0x00000000 |
| 1541 | 1364 | 0x00000000 |
| 1542 | 1365 | 0x00000000 |
| @@ -1559,136 +1382,138 @@ · 16 unmodified lines | ||
| 1559 | 1382 | 0x00000000 |
| 1560 | 1383 | 0x00000000 |
| 1561 | 1384 | 0x00000000 |
| 1562 | − 0x0000000c | |
| 1563 | − 0x0000000c | |
| 1564 | − 0x0000000c | |
| 1565 | − 0x0000000c | |
| 1566 | − 0x0000000c | |
| 1567 | − 0x0000000c | |
| 1568 | − 0x0000000c | |
| 1569 | − 0x0000000c | |
| 1570 | − 0x100002a0 | |
| 1385 | + 0x00000000 | |
| 1386 | + 0x00000000 | |
| 1387 | + 0x00090000 | |
| 1388 | + 0x00090000 | |
| 1389 | + 0x00090000 | |
| 1390 | + 0x00090000 | |
| 1391 | + 0x00009000 | |
| 1392 | + 0x00009000 | |
| 1393 | + 0x00009000 | |
| 1394 | + 0x00009000 | |
| 1395 | + 0x10000280 | |
| 1571 | 1396 | 0x00000000 |
| 1572 | 1397 | 0x00111111 |
| 1573 | 1398 | 0x00000000 |
| 1574 | 1399 | 0x00000000 |
| 1575 | − 0x77ffc085 | |
| 1576 | − 0x00000505 | |
| 1400 | + 0x77ffc081 | |
| 1401 | + 0x00000707 | |
| 1577 | 1402 | 0x81f1f108 |
| 1578 | 1403 | 0x07070004 |
| 1579 | − 0x00000000 | |
| 1404 | + 0x0000003f | |
| 1580 | 1405 | 0x016eeeee |
| 1581 | − 0x51451420 | |
| 1406 | + 0x51451400 | |
| 1582 | 1407 | 0x00514514 |
| 1583 | 1408 | 0x00514514 |
| 1584 | 1409 | 0x51451400 |
| 1585 | − 0x0606003f | |
| 1586 | − 0x00000000 | |
| 1410 | + 0x0000003f | |
| 1411 | + 0x00000066 | |
| 1587 | 1412 | 0x00000000 |
| 1588 | 1413 | 0x00000100 |
| 1589 | − 0x0139000e | |
| 1414 | + 0x000e000e | |
| 1590 | 1415 | 0x00000000 |
| 1591 | 1416 | 0x00000003 |
| 1592 | − 0x000042a0 | |
| 1593 | − 0x80002062 | |
| 1417 | + 0x0000d2b3 | |
| 1418 | + 0x80000d22 | |
| 1594 | 1419 | 0x0000000a |
| 1595 | 1420 | >; |
| 1596 | 1421 | }; |
| 1597 | 1422 | |
| 1598 | − timing-600000000 { | |
| 1599 | − clock-frequency = <600000000>; | |
| 1423 | + timing-300000000 { | |
| 1424 | + clock-frequency = <300000000>; | |
| 1600 | 1425 | |
| 1601 | 1426 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 1602 | 1427 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 1603 | 1428 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| 1604 | 1429 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1605 | 1430 | nvidia,emc-bgbias-ctl0 = <0x00000000>; |
| 1606 | − nvidia,emc-cfg = <0x73300000>; | |
| 1607 | − nvidia,emc-cfg-2 = <0x0000089d>; | |
| 1431 | + nvidia,emc-cfg = <0x73340000>; | |
| 1432 | + nvidia,emc-cfg-2 = <0x000008d5>; | |
| 1608 | 1433 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 1609 | 1434 | nvidia,emc-mode-1 = <0x80100002>; |
| 1610 | − nvidia,emc-mode-2 = <0x80200010>; | |
| 1435 | + nvidia,emc-mode-2 = <0x80200000>; | |
| 1611 | 1436 | nvidia,emc-mode-4 = <0x00000000>; |
| 1612 | − nvidia,emc-mode-reset = <0x80000b61>; | |
| 1613 | − nvidia,emc-mrs-wait-cnt = <0x0127000e>; | |
| 1614 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1615 | − nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; | |
| 1437 | + nvidia,emc-mode-reset = <0x80000321>; | |
| 1438 | + nvidia,emc-mrs-wait-cnt = <0x0173000e>; | |
| 1439 | + nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 1440 | + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; | |
| 1616 | 1441 | nvidia,emc-zcal-cnt-long = <0x00000042>; |
| 1617 | 1442 | nvidia,emc-zcal-interval = <0x00020000>; |
| 1618 | 1443 | |
| 1619 | 1444 | nvidia,emc-configuration = < |
| 1620 | − 0x0000001b | |
| 1621 | − 0x0000009b | |
| 1445 | + 0x0000000d | |
| 1446 | + 0x0000004d | |
| 1622 | 1447 | 0x00000000 |
| 1623 | − 0x00000013 | |
| 1624 | − 0x00000007 | |
| 1625 | − 0x00000007 | |
| 1626 | − 0x0000000b | |
| 1448 | + 0x00000009 | |
| 1449 | + 0x00000003 | |
| 1450 | + 0x00000004 | |
| 1451 | + 0x00000008 | |
| 1452 | + 0x00000002 | |
| 1453 | + 0x00000009 | |
| 1454 | + 0x00000003 | |
| 1627 | 1455 | 0x00000003 |
| 1628 | − 0x00000010 | |
| 1629 | − 0x00000007 | |
| 1630 | − 0x00000007 | |
| 1631 | 1456 | 0x00000002 |
| 1632 | 1457 | 0x00000002 |
| 1633 | 1458 | 0x00000000 |
| 1459 | + 0x00000003 | |
| 1460 | + 0x00000003 | |
| 1634 | 1461 | 0x00000005 |
| 1635 | − 0x00000005 | |
| 1636 | − 0x0000000a | |
| 1637 | 1462 | 0x00000002 |
| 1638 | 1463 | 0x00000000 |
| 1639 | − 0x00000003 | |
| 1640 | − 0x0000000b | |
| 1641 | − 0x00070000 | |
| 1464 | + 0x00000002 | |
| 1465 | + 0x00000007 | |
| 1466 | + 0x00020000 | |
| 1642 | 1467 | 0x00000003 |
| 1643 | 1468 | 0x00000000 |
| 1644 | 1469 | 0x00000000 |
| 1645 | 1470 | 0x00000000 |
| 1646 | 1471 | 0x00000000 |
| 1647 | − 0x00000002 | |
| 1472 | + 0x00000001 | |
| 1473 | + 0x0000000e | |
| 1474 | + 0x00000010 | |
| 1648 | 1475 | 0x00000012 |
| 1649 | − 0x00000016 | |
| 1650 | − 0x00000018 | |
| 1651 | − 0x00001208 | |
| 1476 | + 0x000008e4 | |
| 1652 | 1477 | 0x00000000 |
| 1653 | − 0x00000482 | |
| 1654 | − 0x00000002 | |
| 1655 | − 0x0000000d | |
| 1478 | + 0x00000239 | |
| 1479 | + 0x00000001 | |
| 1480 | + 0x00000008 | |
| 1656 | 1481 | 0x00000001 |
| 1657 | 1482 | 0x00000000 |
| 1658 | − 0x00000097 | |
| 1659 | − 0x00000015 | |
| 1660 | − 0x000000a3 | |
| 1483 | + 0x0000004b | |
| 1484 | + 0x0000000e | |
| 1485 | + 0x00000052 | |
| 1661 | 1486 | 0x00000200 |
| 1662 | 1487 | 0x00000004 |
| 1663 | 1488 | 0x00000005 |
| 1664 | 1489 | 0x00000004 |
| 1665 | − 0x00000013 | |
| 1490 | + 0x00000008 | |
| 1666 | 1491 | 0x00000000 |
| 1667 | − 0x00000006 | |
| 1668 | − 0x00000006 | |
| 1669 | − 0x00001248 | |
| 1492 | + 0x00000005 | |
| 1493 | + 0x00000005 | |
| 1494 | + 0x00000924 | |
| 1670 | 1495 | 0x00000000 |
| 1671 | 1496 | 0x00000000 |
| 1672 | 1497 | 0x00000000 |
| 1673 | 1498 | 0x104ab098 |
| 1674 | − 0xe00e00b1 | |
| 1499 | + 0x002c00a0 | |
| 1675 | 1500 | 0x00008000 |
| 1676 | − 0x0000000a | |
| 1677 | − 0x0000000a | |
| 1678 | − 0x0000000a | |
| 1679 | − 0x0000000a | |
| 1680 | − 0x0000000a | |
| 1681 | − 0x0000000a | |
| 1682 | − 0x0000000a | |
| 1683 | − 0x0000000a | |
| 1684 | − 0x0000000a | |
| 1685 | − 0x0000000a | |
| 1686 | − 0x0000000a | |
| 1687 | − 0x0000000a | |
| 1688 | − 0x0000000a | |
| 1689 | − 0x0000000a | |
| 1690 | − 0x0000000a | |
| 1691 | − 0x0000000a | |
| 1501 | + 0x00030000 | |
| 1502 | + 0x00030000 | |
| 1503 | + 0x00030000 | |
| 1504 | + 0x00030000 | |
| 1505 | + 0x00030000 | |
| 1506 | + 0x00030000 | |
| 1507 | + 0x00030000 | |
| 1508 | + 0x00030000 | |
| 1509 | + 0x00030000 | |
| 1510 | + 0x00030000 | |
| 1511 | + 0x00030000 | |
| 1512 | + 0x00030000 | |
| 1513 | + 0x00030000 | |
| 1514 | + 0x00030000 | |
| 1515 | + 0x00030000 | |
| 1516 | + 0x00030000 | |
| 1692 | 1517 | 0x00000000 |
| 1693 | 1518 | 0x00000000 |
| 1694 | 1519 | 0x00000000 |
| @@ -1697,11 +1522,11 @@ · 2 unmodified lines | ||
| 1697 | 1522 | 0x00000000 |
| 1698 | 1523 | 0x00000000 |
| 1699 | 1524 | 0x00000000 |
| 1700 | − 0x00048000 | |
| 1701 | − 0x00048000 | |
| 1525 | + 0x00098000 | |
| 1526 | + 0x00098000 | |
| 1702 | 1527 | 0x00000000 |
| 1703 | − 0x00048000 | |
| 1704 | − 0x00048000 | |
| 1528 | + 0x00098000 | |
| 1529 | + 0x00098000 | |
| 1705 | 1530 | 0x00000000 |
| 1706 | 1531 | 0x00000000 |
| 1707 | 1532 | 0x00000000 |
| @@ -1727,20 +1552,20 @@ · 19 unmodified lines | ||
| 1727 | 1552 | 0x00000000 |
| 1728 | 1553 | 0x00000000 |
| 1729 | 1554 | 0x00000000 |
| 1730 | − 0x0000000d | |
| 1731 | − 0x0000000d | |
| 1732 | − 0x0000000d | |
| 1733 | − 0x0000000d | |
| 1734 | − 0x0000000d | |
| 1735 | − 0x0000000d | |
| 1736 | − 0x0000000d | |
| 1737 | − 0x0000000d | |
| 1738 | − 0x100002a0 | |
| 1555 | + 0x00050000 | |
| 1556 | + 0x00050000 | |
| 1557 | + 0x00050000 | |
| 1558 | + 0x00050000 | |
| 1559 | + 0x00005000 | |
| 1560 | + 0x00005000 | |
| 1561 | + 0x00005000 | |
| 1562 | + 0x00005000 | |
| 1563 | + 0x10000280 | |
| 1739 | 1564 | 0x00000000 |
| 1740 | 1565 | 0x00111111 |
| 1741 | 1566 | 0x00000000 |
| 1742 | 1567 | 0x00000000 |
| 1743 | − 0x77ffc085 | |
| 1568 | + 0x77ffc081 | |
| 1744 | 1569 | 0x00000505 |
| 1745 | 1570 | 0x81f1f108 |
| 1746 | 1571 | 0x07070004 |
| @@ -1750,113 +1575,113 @@ · 3 unmodified lines | ||
| 1750 | 1575 | 0x00514514 |
| 1751 | 1576 | 0x00514514 |
| 1752 | 1577 | 0x51451400 |
| 1753 | − 0x0606003f | |
| 1754 | − 0x00000000 | |
| 1578 | + 0x0000003f | |
| 1579 | + 0x00000096 | |
| 1755 | 1580 | 0x00000000 |
| 1756 | 1581 | 0x00000100 |
| 1757 | − 0x0127000e | |
| 1582 | + 0x0173000e | |
| 1758 | 1583 | 0x00000000 |
| 1759 | 1584 | 0x00000003 |
| 1760 | − 0x000040a0 | |
| 1761 | − 0x800024aa | |
| 1762 | − 0x0000000e | |
| 1585 | + 0x000052a3 | |
| 1586 | + 0x800012d7 | |
| 1587 | + 0x00000009 | |
| 1763 | 1588 | >; |
| 1764 | 1589 | }; |
| 1765 | 1590 | |
| 1766 | − timing-792000000 { | |
| 1767 | − clock-frequency = <792000000>; | |
| 1591 | + timing-396000000 { | |
| 1592 | + clock-frequency = <396000000>; | |
| 1768 | 1593 | |
| 1769 | 1594 | nvidia,emc-auto-cal-config = <0xa1430000>; |
| 1770 | 1595 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 1771 | 1596 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| 1772 | 1597 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1773 | 1598 | nvidia,emc-bgbias-ctl0 = <0x00000000>; |
| 1774 | − nvidia,emc-cfg = <0x73300000>; | |
| 1775 | − nvidia,emc-cfg-2 = <0x0000089d>; | |
| 1599 | + nvidia,emc-cfg = <0x73340000>; | |
| 1600 | + nvidia,emc-cfg-2 = <0x00000895>; | |
| 1776 | 1601 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 1777 | 1602 | nvidia,emc-mode-1 = <0x80100002>; |
| 1778 | − nvidia,emc-mode-2 = <0x80200018>; | |
| 1603 | + nvidia,emc-mode-2 = <0x80200000>; | |
| 1779 | 1604 | nvidia,emc-mode-4 = <0x00000000>; |
| 1780 | − nvidia,emc-mode-reset = <0x80000d71>; | |
| 1781 | − nvidia,emc-mrs-wait-cnt = <0x00f7000e>; | |
| 1782 | − nvidia,emc-sel-dpd-ctrl = <0x00040000>; | |
| 1783 | − nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; | |
| 1605 | + nvidia,emc-mode-reset = <0x80000521>; | |
| 1606 | + nvidia,emc-mrs-wait-cnt = <0x015b000e>; | |
| 1607 | + nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1608 | + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; | |
| 1784 | 1609 | nvidia,emc-zcal-cnt-long = <0x00000042>; |
| 1785 | 1610 | nvidia,emc-zcal-interval = <0x00020000>; |
| 1786 | 1611 | |
| 1787 | 1612 | nvidia,emc-configuration = < |
| 1788 | − 0x00000024 | |
| 1789 | − 0x000000cd | |
| 1613 | + 0x00000011 | |
| 1614 | + 0x00000066 | |
| 1790 | 1615 | 0x00000000 |
| 1791 | − 0x00000019 | |
| 1792 | − 0x0000000a | |
| 1793 | − 0x00000008 | |
| 1794 | − 0x0000000d | |
| 1616 | + 0x0000000c | |
| 1795 | 1617 | 0x00000004 |
| 1796 | − 0x00000013 | |
| 1797 | − 0x0000000a | |
| 1618 | + 0x00000004 | |
| 1619 | + 0x00000008 | |
| 1620 | + 0x00000002 | |
| 1798 | 1621 | 0x0000000a |
| 1799 | 1622 | 0x00000004 |
| 1623 | + 0x00000004 | |
| 1800 | 1624 | 0x00000002 |
| 1801 | − 0x00000000 | |
| 1802 | − 0x00000006 | |
| 1803 | − 0x00000006 | |
| 1804 | − 0x0000000b | |
| 1805 | 1625 | 0x00000002 |
| 1806 | 1626 | 0x00000000 |
| 1627 | + 0x00000003 | |
| 1628 | + 0x00000003 | |
| 1629 | + 0x00000005 | |
| 1807 | 1630 | 0x00000002 |
| 1808 | − 0x0000000d | |
| 1809 | − 0x00080000 | |
| 1810 | − 0x00000004 | |
| 1811 | − 0x00000000 | |
| 1812 | − 0x00000000 | |
| 1813 | − 0x00000000 | |
| 1814 | 1631 | 0x00000000 |
| 1815 | 1632 | 0x00000001 |
| 1816 | − 0x00000014 | |
| 1817 | − 0x00000018 | |
| 1818 | − 0x0000001a | |
| 1819 | − 0x000017e2 | |
| 1820 | − 0x00000000 | |
| 1821 | − 0x000005f8 | |
| 1633 | + 0x00000008 | |
| 1634 | + 0x00020000 | |
| 1822 | 1635 | 0x00000003 |
| 1823 | − 0x00000011 | |
| 1636 | + 0x00000000 | |
| 1637 | + 0x00000000 | |
| 1638 | + 0x00000000 | |
| 1639 | + 0x00000000 | |
| 1640 | + 0x00000000 | |
| 1641 | + 0x0000000f | |
| 1642 | + 0x00000010 | |
| 1643 | + 0x00000012 | |
| 1644 | + 0x00000bd1 | |
| 1645 | + 0x00000000 | |
| 1646 | + 0x000002f4 | |
| 1647 | + 0x00000001 | |
| 1648 | + 0x00000008 | |
| 1824 | 1649 | 0x00000001 |
| 1825 | 1650 | 0x00000000 |
| 1826 | − 0x000000c7 | |
| 1827 | − 0x00000018 | |
| 1828 | − 0x000000d7 | |
| 1651 | + 0x00000063 | |
| 1652 | + 0x0000000f | |
| 1653 | + 0x0000006c | |
| 1829 | 1654 | 0x00000200 |
| 1655 | + 0x00000004 | |
| 1830 | 1656 | 0x00000005 |
| 1831 | − 0x00000006 | |
| 1832 | − 0x00000005 | |
| 1833 | − 0x00000019 | |
| 1657 | + 0x00000004 | |
| 1658 | + 0x0000000b | |
| 1834 | 1659 | 0x00000000 |
| 1835 | − 0x00000008 | |
| 1836 | − 0x00000008 | |
| 1837 | − 0x00001822 | |
| 1660 | + 0x00000005 | |
| 1661 | + 0x00000005 | |
| 1662 | + 0x00000c11 | |
| 1838 | 1663 | 0x00000000 |
| 1839 | 1664 | 0x00000000 |
| 1840 | 1665 | 0x00000000 |
| 1841 | 1666 | 0x104ab098 |
| 1842 | − 0xe00700b1 | |
| 1667 | + 0x002c00a0 | |
| 1843 | 1668 | 0x00008000 |
| 1844 | − 0x007fc008 | |
| 1845 | − 0x007fc008 | |
| 1846 | − 0x007fc008 | |
| 1847 | − 0x007fc008 | |
| 1848 | − 0x007fc008 | |
| 1849 | − 0x007fc008 | |
| 1850 | − 0x007fc008 | |
| 1851 | − 0x007fc008 | |
| 1852 | − 0x007fc008 | |
| 1853 | − 0x007fc008 | |
| 1854 | − 0x007fc008 | |
| 1855 | − 0x007fc008 | |
| 1856 | − 0x007fc008 | |
| 1857 | − 0x007fc008 | |
| 1858 | − 0x007fc008 | |
| 1859 | − 0x007fc008 | |
| 1669 | + 0x00030000 | |
| 1670 | + 0x00030000 | |
| 1671 | + 0x00030000 | |
| 1672 | + 0x00030000 | |
| 1673 | + 0x00030000 | |
| 1674 | + 0x00030000 | |
| 1675 | + 0x00030000 | |
| 1676 | + 0x00030000 | |
| 1677 | + 0x00030000 | |
| 1678 | + 0x00030000 | |
| 1679 | + 0x00030000 | |
| 1680 | + 0x00030000 | |
| 1681 | + 0x00030000 | |
| 1682 | + 0x00030000 | |
| 1683 | + 0x00030000 | |
| 1684 | + 0x00030000 | |
| 1860 | 1685 | 0x00000000 |
| 1861 | 1686 | 0x00000000 |
| 1862 | 1687 | 0x00000000 |
| @@ -1865,11 +1690,11 @@ · 2 unmodified lines | ||
| 1865 | 1690 | 0x00000000 |
| 1866 | 1691 | 0x00000000 |
| 1867 | 1692 | 0x00000000 |
| 1868 | − 0x00034000 | |
| 1869 | − 0x00034000 | |
| 1693 | + 0x00070000 | |
| 1694 | + 0x00070000 | |
| 1870 | 1695 | 0x00000000 |
| 1871 | − 0x00034000 | |
| 1872 | − 0x00034000 | |
| 1696 | + 0x00070000 | |
| 1697 | + 0x00070000 | |
| 1873 | 1698 | 0x00000000 |
| 1874 | 1699 | 0x00000000 |
| 1875 | 1700 | 0x00000000 |
| @@ -1879,62 +1704,62 @@ · 3 unmodified lines | ||
| 1879 | 1704 | 0x00000000 |
| 1880 | 1705 | 0x00000000 |
| 1881 | 1706 | 0x00000000 |
| 1882 | − 0x00000005 | |
| 1883 | − 0x00000005 | |
| 1884 | − 0x00000005 | |
| 1885 | − 0x00000005 | |
| 1886 | − 0x00000005 | |
| 1887 | − 0x00000005 | |
| 1888 | − 0x00000005 | |
| 1889 | − 0x00000005 | |
| 1890 | − 0x00000005 | |
| 1891 | − 0x00000005 | |
| 1892 | − 0x00000005 | |
| 1893 | − 0x00000005 | |
| 1894 | − 0x00000005 | |
| 1895 | − 0x00000005 | |
| 1896 | − 0x00000005 | |
| 1897 | − 0x00000005 | |
| 1898 | − 0x0000000a | |
| 1899 | − 0x0000000a | |
| 1900 | − 0x0000000a | |
| 1901 | − 0x0000000a | |
| 1902 | − 0x0000000a | |
| 1903 | − 0x0000000a | |
| 1904 | − 0x0000000a | |
| 1905 | − 0x0000000a | |
| 1906 | − 0x100002a0 | |
| 1907 | 1707 | 0x00000000 |
| 1908 | − 0x00111111 | |
| 1909 | 1708 | 0x00000000 |
| 1910 | 1709 | 0x00000000 |
| 1911 | − 0x77ffc085 | |
| 1912 | 1710 | 0x00000000 |
| 1711 | + 0x00000000 | |
| 1712 | + 0x00000000 | |
| 1713 | + 0x00000000 | |
| 1714 | + 0x00000000 | |
| 1715 | + 0x00000000 | |
| 1716 | + 0x00000000 | |
| 1717 | + 0x00000000 | |
| 1718 | + 0x00000000 | |
| 1719 | + 0x00000000 | |
| 1720 | + 0x00000000 | |
| 1721 | + 0x00000000 | |
| 1722 | + 0x00000000 | |
| 1723 | + 0x00038000 | |
| 1724 | + 0x00038000 | |
| 1725 | + 0x00038000 | |
| 1726 | + 0x00038000 | |
| 1727 | + 0x00003800 | |
| 1728 | + 0x00003800 | |
| 1729 | + 0x00003800 | |
| 1730 | + 0x00003800 | |
| 1731 | + 0x10000280 | |
| 1732 | + 0x00000000 | |
| 1733 | + 0x00111111 | |
| 1734 | + 0x00000000 | |
| 1735 | + 0x00000000 | |
| 1736 | + 0x77ffc081 | |
| 1737 | + 0x00000505 | |
| 1913 | 1738 | 0x81f1f108 |
| 1914 | 1739 | 0x07070004 |
| 1915 | 1740 | 0x00000000 |
| 1916 | 1741 | 0x016eeeee |
| 1917 | − 0x61861820 | |
| 1742 | + 0x51451420 | |
| 1918 | 1743 | 0x00514514 |
| 1919 | 1744 | 0x00514514 |
| 1920 | − 0x61861800 | |
| 1921 | − 0x0606003f | |
| 1922 | − 0x00000000 | |
| 1745 | + 0x51451400 | |
| 1746 | + 0x0000003f | |
| 1747 | + 0x000000c6 | |
| 1923 | 1748 | 0x00000000 |
| 1924 | 1749 | 0x00000100 |
| 1925 | − 0x00f7000e | |
| 1750 | + 0x015b000e | |
| 1926 | 1751 | 0x00000000 |
| 1927 | − 0x00000004 | |
| 1928 | − 0x00004080 | |
| 1929 | − 0x80003012 | |
| 1930 | − 0x0000000f | |
| 1752 | + 0x00000003 | |
| 1753 | + 0x000052a3 | |
| 1754 | + 0x8000188b | |
| 1755 | + 0x00000009 | |
| 1931 | 1756 | >; |
| 1932 | 1757 | }; |
| 1933 | 1758 | |
| 1934 | − timing-924000000 { | |
| 1935 | − clock-frequency = <924000000>; | |
| 1759 | + timing-528000000 { | |
| 1760 | + clock-frequency = <528000000>; | |
| 1936 | 1761 | |
| 1937 | − nvidia,emc-auto-cal-config = <0xa1430303>; | |
| 1762 | + nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1938 | 1763 | nvidia,emc-auto-cal-config2 = <0x00000000>; |
| 1939 | 1764 | nvidia,emc-auto-cal-config3 = <0x00000000>; |
| 1940 | 1765 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| @@ -1943,101 +1768,104 @@ · 2 unmodified lines | ||
| 1943 | 1768 | nvidia,emc-cfg-2 = <0x0000089d>; |
| 1944 | 1769 | nvidia,emc-ctt-term-ctrl = <0x00000802>; |
| 1945 | 1770 | nvidia,emc-mode-1 = <0x80100002>; |
| 1946 | − nvidia,emc-mode-2 = <0x80200020>; | |
| 1771 | + nvidia,emc-mode-2 = <0x80200008>; | |
| 1947 | 1772 | nvidia,emc-mode-4 = <0x00000000>; |
| 1948 | − nvidia,emc-mode-reset = <0x80000f15>; | |
| 1949 | − nvidia,emc-mrs-wait-cnt = <0x00cd000e>; | |
| 1950 | − nvidia,emc-sel-dpd-ctrl = <0x00040000>; | |
| 1951 | − nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; | |
| 1952 | − nvidia,emc-zcal-cnt-long = <0x0000004c>; | |
| 1773 | + nvidia,emc-mode-reset = <0x80000941>; | |
| 1774 | + nvidia,emc-mrs-wait-cnt = <0x0139000e>; | |
| 1775 | + nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1776 | + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; | |
| 1777 | + nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1953 | 1778 | nvidia,emc-zcal-interval = <0x00020000>; |
| 1954 | 1779 | |
| 1955 | 1780 | nvidia,emc-configuration = < |
| 1956 | − 0x0000002b | |
| 1957 | − 0x000000f0 | |
| 1781 | + 0x00000018 | |
| 1782 | + 0x00000088 | |
| 1958 | 1783 | 0x00000000 |
| 1959 | − 0x0000001e | |
| 1960 | − 0x0000000b | |
| 1784 | + 0x00000010 | |
| 1785 | + 0x00000006 | |
| 1786 | + 0x00000006 | |
| 1961 | 1787 | 0x00000009 |
| 1962 | − 0x0000000f | |
| 1963 | − 0x00000005 | |
| 1964 | − 0x00000016 | |
| 1965 | − 0x0000000b | |
| 1966 | − 0x0000000b | |
| 1967 | − 0x00000004 | |
| 1968 | 1788 | 0x00000002 |
| 1969 | − 0x00000000 | |
| 1970 | − 0x00000007 | |
| 1971 | − 0x00000007 | |
| 1972 | 1789 | 0x0000000d |
| 1790 | + 0x00000006 | |
| 1791 | + 0x00000006 | |
| 1792 | + 0x00000002 | |
| 1973 | 1793 | 0x00000002 |
| 1974 | 1794 | 0x00000000 |
| 1795 | + 0x00000003 | |
| 1796 | + 0x00000003 | |
| 1797 | + 0x00000006 | |
| 1975 | 1798 | 0x00000002 |
| 1976 | − 0x0000000f | |
| 1977 | − 0x000a0000 | |
| 1978 | − 0x00000004 | |
| 1979 | 1799 | 0x00000000 |
| 1800 | + 0x00000001 | |
| 1801 | + 0x00000009 | |
| 1802 | + 0x00030000 | |
| 1803 | + 0x00000003 | |
| 1980 | 1804 | 0x00000000 |
| 1981 | 1805 | 0x00000000 |
| 1982 | 1806 | 0x00000000 |
| 1983 | − 0x00000001 | |
| 1984 | − 0x00000016 | |
| 1985 | − 0x0000001a | |
| 1986 | − 0x0000001c | |
| 1987 | − 0x00001be7 | |
| 1988 | 1807 | 0x00000000 |
| 1989 | − 0x000006f9 | |
| 1990 | − 0x00000004 | |
| 1991 | − 0x00000015 | |
| 1808 | + 0x00000000 | |
| 1809 | + 0x00000010 | |
| 1810 | + 0x00000012 | |
| 1811 | + 0x00000014 | |
| 1812 | + 0x00000fd6 | |
| 1813 | + 0x00000000 | |
| 1814 | + 0x000003f5 | |
| 1815 | + 0x00000002 | |
| 1816 | + 0x0000000b | |
| 1992 | 1817 | 0x00000001 |
| 1993 | 1818 | 0x00000000 |
| 1994 | − 0x000000e7 | |
| 1995 | − 0x0000001b | |
| 1996 | − 0x000000fb | |
| 1819 | + 0x00000085 | |
| 1820 | + 0x00000012 | |
| 1821 | + 0x00000090 | |
| 1997 | 1822 | 0x00000200 |
| 1823 | + 0x00000004 | |
| 1824 | + 0x00000005 | |
| 1825 | + 0x00000004 | |
| 1826 | + 0x00000010 | |
| 1827 | + 0x00000000 | |
| 1998 | 1828 | 0x00000006 |
| 1999 | − 0x00000007 | |
| 2000 | 1829 | 0x00000006 |
| 2001 | − 0x0000001e | |
| 1830 | + 0x00001017 | |
| 1831 | + 0x00000000 | |
| 2002 | 1832 | 0x00000000 |
| 1833 | + 0x00000000 | |
| 1834 | + 0x104ab098 | |
| 1835 | + 0xe01200b1 | |
| 1836 | + 0x00008000 | |
| 1837 | + 0x0000000a | |
| 1838 | + 0x0000000a | |
| 1839 | + 0x0000000a | |
| 1840 | + 0x0000000a | |
| 1841 | + 0x0000000a | |
| 1842 | + 0x0000000a | |
| 1843 | + 0x0000000a | |
| 1844 | + 0x0000000a | |
| 1845 | + 0x0000000a | |
| 1846 | + 0x0000000a | |
| 1847 | + 0x0000000a | |
| 1848 | + 0x0000000a | |
| 1849 | + 0x0000000a | |
| 1850 | + 0x0000000a | |
| 2003 | 1851 | 0x0000000a |
| 2004 | 1852 | 0x0000000a |
| 2005 | − 0x00001c28 | |
| 2006 | 1853 | 0x00000000 |
| 2007 | 1854 | 0x00000000 |
| 2008 | 1855 | 0x00000000 |
| 2009 | − 0x104ab898 | |
| 2010 | − 0xe00400b1 | |
| 2011 | − 0x00008000 | |
| 2012 | − 0x007f800a | |
| 2013 | − 0x007f800a | |
| 2014 | − 0x007f800a | |
| 2015 | − 0x007f800a | |
| 2016 | − 0x007f800a | |
| 2017 | − 0x007f800a | |
| 2018 | − 0x007f800a | |
| 2019 | − 0x007f800a | |
| 2020 | − 0x007f800a | |
| 2021 | − 0x007f800a | |
| 2022 | − 0x007f800a | |
| 2023 | − 0x007f800a | |
| 2024 | − 0x007f800a | |
| 2025 | − 0x007f800a | |
| 2026 | − 0x007f800a | |
| 2027 | − 0x007f800a | |
| 2028 | 1856 | 0x00000000 |
| 2029 | 1857 | 0x00000000 |
| 2030 | 1858 | 0x00000000 |
| 2031 | 1859 | 0x00000000 |
| 2032 | 1860 | 0x00000000 |
| 1861 | + 0x00054000 | |
| 1862 | + 0x00054000 | |
| 2033 | 1863 | 0x00000000 |
| 1864 | + 0x00054000 | |
| 1865 | + 0x00054000 | |
| 2034 | 1866 | 0x00000000 |
| 2035 | 1867 | 0x00000000 |
| 2036 | − 0x0002c000 | |
| 2037 | − 0x0002c000 | |
| 2038 | 1868 | 0x00000000 |
| 2039 | − 0x0002c000 | |
| 2040 | − 0x0002c000 | |
| 2041 | 1869 | 0x00000000 |
| 2042 | 1870 | 0x00000000 |
| 2043 | 1871 | 0x00000000 |
| @@ -2047,374 +1875,556 @@ · 3 unmodified lines | ||
| 2047 | 1875 | 0x00000000 |
| 2048 | 1876 | 0x00000000 |
| 2049 | 1877 | 0x00000000 |
| 2050 | − 0x00000004 | |
| 2051 | − 0x00000004 | |
| 2052 | − 0x00000004 | |
| 2053 | − 0x00000004 | |
| 2054 | − 0x00000004 | |
| 2055 | − 0x00000004 | |
| 2056 | − 0x00000004 | |
| 2057 | − 0x00000004 | |
| 2058 | − 0x00000004 | |
| 2059 | − 0x00000004 | |
| 2060 | − 0x00000004 | |
| 2061 | − 0x00000004 | |
| 2062 | − 0x00000004 | |
| 2063 | − 0x00000004 | |
| 2064 | − 0x00000004 | |
| 2065 | − 0x00000004 | |
| 2066 | − 0x00000008 | |
| 2067 | − 0x00000008 | |
| 2068 | − 0x00000008 | |
| 2069 | − 0x00000008 | |
| 2070 | − 0x00000008 | |
| 2071 | − 0x00000008 | |
| 2072 | − 0x00000008 | |
| 2073 | − 0x00000008 | |
| 1878 | + 0x00000000 | |
| 1879 | + 0x00000000 | |
| 1880 | + 0x00000000 | |
| 1881 | + 0x00000000 | |
| 1882 | + 0x00000000 | |
| 1883 | + 0x00000000 | |
| 1884 | + 0x00000000 | |
| 1885 | + 0x00000000 | |
| 1886 | + 0x00000000 | |
| 1887 | + 0x00000000 | |
| 1888 | + 0x00000000 | |
| 1889 | + 0x00000000 | |
| 1890 | + 0x00000000 | |
| 1891 | + 0x0000000c | |
| 1892 | + 0x0000000c | |
| 1893 | + 0x0000000c | |
| 1894 | + 0x0000000c | |
| 1895 | + 0x0000000c | |
| 1896 | + 0x0000000c | |
| 1897 | + 0x0000000c | |
| 1898 | + 0x0000000c | |
| 2074 | 1899 | 0x100002a0 |
| 2075 | 1900 | 0x00000000 |
| 2076 | 1901 | 0x00111111 |
| 2077 | 1902 | 0x00000000 |
| 2078 | 1903 | 0x00000000 |
| 2079 | 1904 | 0x77ffc085 |
| 2080 | − 0x00000000 | |
| 1905 | + 0x00000505 | |
| 2081 | 1906 | 0x81f1f108 |
| 2082 | 1907 | 0x07070004 |
| 2083 | 1908 | 0x00000000 |
| 2084 | 1909 | 0x016eeeee |
| 2085 | − 0x5d75d720 | |
| 1910 | + 0x51451420 | |
| 2086 | 1911 | 0x00514514 |
| 2087 | 1912 | 0x00514514 |
| 2088 | − 0x5d75d700 | |
| 1913 | + 0x51451400 | |
| 2089 | 1914 | 0x0606003f |
| 2090 | 1915 | 0x00000000 |
| 2091 | 1916 | 0x00000000 |
| 2092 | − 0x00000128 | |
| 2093 | − 0x00cd000e | |
| 1917 | + 0x00000100 | |
| 1918 | + 0x0139000e | |
| 2094 | 1919 | 0x00000000 |
| 2095 | − 0x00000004 | |
| 2096 | − 0x00004080 | |
| 2097 | − 0x800037ea | |
| 2098 | − 0x00000011 | |
| 1920 | + 0x00000003 | |
| 1921 | + 0x000042a0 | |
| 1922 | + 0x80002062 | |
| 1923 | + 0x0000000a | |
| 2099 | 1924 | >; |
| 2100 | 1925 | }; |
| 2101 | 1926 | |
| 2102 | − }; | |
| 2103 | − }; | |
| 2104 | − | |
| 2105 | − memory-controller@70019000 { | |
| 2106 | − emc-timings-3 { | |
| 2107 | − nvidia,ram-code = <3>; | |
| 1927 | + timing-600000000 { | |
| 1928 | + clock-frequency = <600000000>; | |
| 2108 | 1929 | |
| 2109 | − timing-12750000 { | |
| 2110 | − clock-frequency = <12750000>; | |
| 1930 | + nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1931 | + nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 1932 | + nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 1933 | + nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 1934 | + nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1935 | + nvidia,emc-cfg = <0x73300000>; | |
| 1936 | + nvidia,emc-cfg-2 = <0x0000089d>; | |
| 1937 | + nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 1938 | + nvidia,emc-mode-1 = <0x80100002>; | |
| 1939 | + nvidia,emc-mode-2 = <0x80200010>; | |
| 1940 | + nvidia,emc-mode-4 = <0x00000000>; | |
| 1941 | + nvidia,emc-mode-reset = <0x80000b61>; | |
| 1942 | + nvidia,emc-mrs-wait-cnt = <0x0127000e>; | |
| 1943 | + nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1944 | + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; | |
| 1945 | + nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1946 | + nvidia,emc-zcal-interval = <0x00020000>; | |
| 2111 | 1947 | |
| 2112 | − nvidia,emem-configuration = < | |
| 2113 | − 0x40040001 | |
| 2114 | − 0x8000000a | |
| 2115 | − 0x00000001 | |
| 2116 | − 0x00000001 | |
| 2117 | − 0x00000002 | |
| 1948 | + nvidia,emc-configuration = < | |
| 1949 | + 0x0000001b | |
| 1950 | + 0x0000009b | |
| 2118 | 1951 | 0x00000000 |
| 2119 | − 0x00000002 | |
| 2120 | − 0x00000001 | |
| 2121 | − 0x00000003 | |
| 2122 | − 0x00000008 | |
| 1952 | + 0x00000013 | |
| 1953 | + 0x00000007 | |
| 1954 | + 0x00000007 | |
| 1955 | + 0x0000000b | |
| 2123 | 1956 | 0x00000003 |
| 1957 | + 0x00000010 | |
| 1958 | + 0x00000007 | |
| 1959 | + 0x00000007 | |
| 2124 | 1960 | 0x00000002 |
| 2125 | − 0x00000003 | |
| 2126 | − 0x00000006 | |
| 2127 | − 0x06030203 | |
| 2128 | − 0x000a0502 | |
| 2129 | − 0x77e30303 | |
| 2130 | − 0x70000f03 | |
| 2131 | − 0x001f0000 | |
| 2132 | − >; | |
| 2133 | − }; | |
| 2134 | − | |
| 2135 | − timing-20400000 { | |
| 2136 | − clock-frequency = <20400000>; | |
| 2137 | − | |
| 2138 | − nvidia,emem-configuration = < | |
| 2139 | − 0x40020001 | |
| 2140 | − 0x80000012 | |
| 2141 | − 0x00000001 | |
| 2142 | − 0x00000001 | |
| 2143 | 1961 | 0x00000002 |
| 2144 | 1962 | 0x00000000 |
| 2145 | − 0x00000002 | |
| 2146 | − 0x00000001 | |
| 2147 | − 0x00000003 | |
| 2148 | − 0x00000008 | |
| 2149 | − 0x00000003 | |
| 2150 | − 0x00000002 | |
| 2151 | − 0x00000003 | |
| 2152 | − 0x00000006 | |
| 2153 | − 0x06030203 | |
| 2154 | − 0x000a0502 | |
| 2155 | − 0x76230303 | |
| 2156 | − 0x70000f03 | |
| 2157 | − 0x001f0000 | |
| 2158 | − >; | |
| 2159 | − }; | |
| 2160 | − | |
| 2161 | − timing-40800000 { | |
| 2162 | − clock-frequency = <40800000>; | |
| 2163 | − | |
| 2164 | − nvidia,emem-configuration = < | |
| 2165 | − 0xa0000001 | |
| 2166 | − 0x80000017 | |
| 2167 | − 0x00000001 | |
| 2168 | − 0x00000001 | |
| 1963 | + 0x00000005 | |
| 1964 | + 0x00000005 | |
| 1965 | + 0x0000000a | |
| 2169 | 1966 | 0x00000002 |
| 2170 | 1967 | 0x00000000 |
| 2171 | − 0x00000002 | |
| 2172 | − 0x00000001 | |
| 2173 | − 0x00000003 | |
| 2174 | − 0x00000008 | |
| 2175 | 1968 | 0x00000003 |
| 2176 | − 0x00000002 | |
| 1969 | + 0x0000000b | |
| 1970 | + 0x00070000 | |
| 2177 | 1971 | 0x00000003 |
| 2178 | − 0x00000006 | |
| 2179 | − 0x06030203 | |
| 2180 | − 0x000a0502 | |
| 2181 | − 0x74a30303 | |
| 2182 | − 0x70000f03 | |
| 2183 | − 0x001f0000 | |
| 2184 | − >; | |
| 2185 | − }; | |
| 2186 | − | |
| 2187 | − timing-68000000 { | |
| 2188 | − clock-frequency = <68000000>; | |
| 2189 | − | |
| 2190 | − nvidia,emem-configuration = < | |
| 2191 | − 0x00000001 | |
| 2192 | − 0x8000001e | |
| 2193 | − 0x00000001 | |
| 2194 | − 0x00000001 | |
| 2195 | − 0x00000002 | |
| 1972 | + 0x00000000 | |
| 1973 | + 0x00000000 | |
| 1974 | + 0x00000000 | |
| 2196 | 1975 | 0x00000000 |
| 2197 | 1976 | 0x00000002 |
| 2198 | − 0x00000001 | |
| 2199 | − 0x00000003 | |
| 2200 | − 0x00000008 | |
| 2201 | − 0x00000003 | |
| 2202 | − 0x00000002 | |
| 2203 | − 0x00000003 | |
| 2204 | − 0x00000006 | |
| 2205 | − 0x06030203 | |
| 2206 | − 0x000a0502 | |
| 2207 | − 0x74230403 | |
| 2208 | − 0x70000f03 | |
| 2209 | − 0x001f0000 | |
| 2210 | − >; | |
| 2211 | − }; | |
| 2212 | − | |
| 2213 | − timing-102000000 { | |
| 2214 | − clock-frequency = <102000000>; | |
| 2215 | − | |
| 2216 | − nvidia,emem-configuration = < | |
| 2217 | − 0x08000001 | |
| 2218 | − 0x80000026 | |
| 2219 | − 0x00000001 | |
| 2220 | − 0x00000001 | |
| 2221 | − 0x00000003 | |
| 1977 | + 0x00000012 | |
| 1978 | + 0x00000016 | |
| 1979 | + 0x00000018 | |
| 1980 | + 0x00001208 | |
| 2222 | 1981 | 0x00000000 |
| 1982 | + 0x00000482 | |
| 2223 | 1983 | 0x00000002 |
| 1984 | + 0x0000000d | |
| 2224 | 1985 | 0x00000001 |
| 2225 | − 0x00000003 | |
| 2226 | − 0x00000008 | |
| 2227 | − 0x00000003 | |
| 2228 | − 0x00000002 | |
| 2229 | − 0x00000003 | |
| 1986 | + 0x00000000 | |
| 1987 | + 0x00000097 | |
| 1988 | + 0x00000015 | |
| 1989 | + 0x000000a3 | |
| 1990 | + 0x00000200 | |
| 1991 | + 0x00000004 | |
| 1992 | + 0x00000005 | |
| 1993 | + 0x00000004 | |
| 1994 | + 0x00000013 | |
| 1995 | + 0x00000000 | |
| 2230 | 1996 | 0x00000006 |
| 2231 | − 0x06030203 | |
| 2232 | − 0x000a0503 | |
| 2233 | − 0x73c30504 | |
| 2234 | − 0x70000f03 | |
| 2235 | − 0x001f0000 | |
| 2236 | − >; | |
| 2237 | − }; | |
| 2238 | − | |
| 2239 | − timing-204000000 { | |
| 2240 | − clock-frequency = <204000000>; | |
| 2241 | − | |
| 2242 | − nvidia,emem-configuration = < | |
| 2243 | − 0x01000003 | |
| 2244 | − 0x80000040 | |
| 2245 | − 0x00000001 | |
| 2246 | − 0x00000001 | |
| 2247 | − 0x00000004 | |
| 2248 | − 0x00000002 | |
| 2249 | − 0x00000003 | |
| 2250 | − 0x00000001 | |
| 2251 | − 0x00000003 | |
| 2252 | − 0x00000008 | |
| 2253 | − 0x00000003 | |
| 2254 | − 0x00000002 | |
| 2255 | − 0x00000004 | |
| 2256 | 1997 | 0x00000006 |
| 2257 | − 0x06040203 | |
| 2258 | − 0x000a0504 | |
| 2259 | − 0x73840a05 | |
| 2260 | − 0x70000f03 | |
| 2261 | − 0x001f0000 | |
| 1998 | + 0x00001248 | |
| 1999 | + 0x00000000 | |
| 2000 | + 0x00000000 | |
| 2001 | + 0x00000000 | |
| 2002 | + 0x104ab098 | |
| 2003 | + 0xe00e00b1 | |
| 2004 | + 0x00008000 | |
| 2005 | + 0x0000000a | |
| 2006 | + 0x0000000a | |
| 2007 | + 0x0000000a | |
| 2008 | + 0x0000000a | |
| 2009 | + 0x0000000a | |
| 2010 | + 0x0000000a | |
| 2011 | + 0x0000000a | |
| 2012 | + 0x0000000a | |
| 2013 | + 0x0000000a | |
| 2014 | + 0x0000000a | |
| 2015 | + 0x0000000a | |
| 2016 | + 0x0000000a | |
| 2017 | + 0x0000000a | |
| 2018 | + 0x0000000a | |
| 2019 | + 0x0000000a | |
| 2020 | + 0x0000000a | |
| 2021 | + 0x00000000 | |
| 2022 | + 0x00000000 | |
| 2023 | + 0x00000000 | |
| 2024 | + 0x00000000 | |
| 2025 | + 0x00000000 | |
| 2026 | + 0x00000000 | |
| 2027 | + 0x00000000 | |
| 2028 | + 0x00000000 | |
| 2029 | + 0x00048000 | |
| 2030 | + 0x00048000 | |
| 2031 | + 0x00000000 | |
| 2032 | + 0x00048000 | |
| 2033 | + 0x00048000 | |
| 2034 | + 0x00000000 | |
| 2035 | + 0x00000000 | |
| 2036 | + 0x00000000 | |
| 2037 | + 0x00000000 | |
| 2038 | + 0x00000000 | |
| 2039 | + 0x00000000 | |
| 2040 | + 0x00000000 | |
| 2041 | + 0x00000000 | |
| 2042 | + 0x00000000 | |
| 2043 | + 0x00000000 | |
| 2044 | + 0x00000000 | |
| 2045 | + 0x00000000 | |
| 2046 | + 0x00000000 | |
| 2047 | + 0x00000000 | |
| 2048 | + 0x00000000 | |
| 2049 | + 0x00000000 | |
| 2050 | + 0x00000000 | |
| 2051 | + 0x00000000 | |
| 2052 | + 0x00000000 | |
| 2053 | + 0x00000000 | |
| 2054 | + 0x00000000 | |
| 2055 | + 0x00000000 | |
| 2056 | + 0x00000000 | |
| 2057 | + 0x00000000 | |
| 2058 | + 0x00000000 | |
| 2059 | + 0x0000000d | |
| 2060 | + 0x0000000d | |
| 2061 | + 0x0000000d | |
| 2062 | + 0x0000000d | |
| 2063 | + 0x0000000d | |
| 2064 | + 0x0000000d | |
| 2065 | + 0x0000000d | |
| 2066 | + 0x0000000d | |
| 2067 | + 0x100002a0 | |
| 2068 | + 0x00000000 | |
| 2069 | + 0x00111111 | |
| 2070 | + 0x00000000 | |
| 2071 | + 0x00000000 | |
| 2072 | + 0x77ffc085 | |
| 2073 | + 0x00000505 | |
| 2074 | + 0x81f1f108 | |
| 2075 | + 0x07070004 | |
| 2076 | + 0x00000000 | |
| 2077 | + 0x016eeeee | |
| 2078 | + 0x51451420 | |
| 2079 | + 0x00514514 | |
| 2080 | + 0x00514514 | |
| 2081 | + 0x51451400 | |
| 2082 | + 0x0606003f | |
| 2083 | + 0x00000000 | |
| 2084 | + 0x00000000 | |
| 2085 | + 0x00000100 | |
| 2086 | + 0x0127000e | |
| 2087 | + 0x00000000 | |
| 2088 | + 0x00000003 | |
| 2089 | + 0x000040a0 | |
| 2090 | + 0x800024aa | |
| 2091 | + 0x0000000e | |
| 2262 | 2092 | >; |
| 2263 | 2093 | }; |
| 2264 | 2094 | |
| 2265 | − timing-300000000 { | |
| 2266 | − clock-frequency = <300000000>; | |
| 2095 | + timing-792000000 { | |
| 2096 | + clock-frequency = <792000000>; | |
| 2267 | 2097 | |
| 2268 | − nvidia,emem-configuration = < | |
| 2269 | − 0x08000004 | |
| 2270 | − 0x80000040 | |
| 2271 | − 0x00000001 | |
| 2272 | − 0x00000002 | |
| 2273 | − 0x00000007 | |
| 2098 | + nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 2099 | + nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 2100 | + nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 2101 | + nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 2102 | + nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 2103 | + nvidia,emc-cfg = <0x73300000>; | |
| 2104 | + nvidia,emc-cfg-2 = <0x0000089d>; | |
| 2105 | + nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 2106 | + nvidia,emc-mode-1 = <0x80100002>; | |
| 2107 | + nvidia,emc-mode-2 = <0x80200018>; | |
| 2108 | + nvidia,emc-mode-4 = <0x00000000>; | |
| 2109 | + nvidia,emc-mode-reset = <0x80000d71>; | |
| 2110 | + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; | |
| 2111 | + nvidia,emc-sel-dpd-ctrl = <0x00040000>; | |
| 2112 | + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; | |
| 2113 | + nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 2114 | + nvidia,emc-zcal-interval = <0x00020000>; | |
| 2115 | + | |
| 2116 | + nvidia,emc-configuration = < | |
| 2117 | + 0x00000024 | |
| 2118 | + 0x000000cd | |
| 2119 | + 0x00000000 | |
| 2120 | + 0x00000019 | |
| 2121 | + 0x0000000a | |
| 2122 | + 0x00000008 | |
| 2123 | + 0x0000000d | |
| 2274 | 2124 | 0x00000004 |
| 2125 | + 0x00000013 | |
| 2126 | + 0x0000000a | |
| 2127 | + 0x0000000a | |
| 2275 | 2128 | 0x00000004 |
| 2276 | − 0x00000001 | |
| 2277 | − 0x00000002 | |
| 2278 | − 0x00000007 | |
| 2279 | 2129 | 0x00000002 |
| 2280 | − 0x00000002 | |
| 2281 | − 0x00000004 | |
| 2130 | + 0x00000000 | |
| 2282 | 2131 | 0x00000006 |
| 2283 | − 0x06040202 | |
| 2284 | − 0x000b0607 | |
| 2285 | − 0x77450e08 | |
| 2286 | − 0x70000f03 | |
| 2287 | − 0x001f0000 | |
| 2288 | − >; | |
| 2289 | − }; | |
| 2290 | − | |
| 2291 | − timing-396000000 { | |
| 2292 | − clock-frequency = <396000000>; | |
| 2293 | − | |
| 2294 | − nvidia,emem-configuration = < | |
| 2295 | − 0x0f000005 | |
| 2296 | − 0x80000040 | |
| 2297 | − 0x00000001 | |
| 2298 | − 0x00000002 | |
| 2299 | − 0x00000009 | |
| 2300 | − 0x00000005 | |
| 2301 | 2132 | 0x00000006 |
| 2302 | − 0x00000001 | |
| 2303 | − 0x00000002 | |
| 2304 | − 0x00000008 | |
| 2133 | + 0x0000000b | |
| 2305 | 2134 | 0x00000002 |
| 2135 | + 0x00000000 | |
| 2306 | 2136 | 0x00000002 |
| 2137 | + 0x0000000d | |
| 2138 | + 0x00080000 | |
| 2307 | 2139 | 0x00000004 |
| 2308 | − 0x00000006 | |
| 2309 | − 0x06040202 | |
| 2310 | − 0x000d0709 | |
| 2311 | − 0x7586120a | |
| 2312 | − 0x70000f03 | |
| 2313 | − 0x001f0000 | |
| 2314 | − >; | |
| 2315 | − }; | |
| 2316 | − | |
| 2317 | − timing-528000000 { | |
| 2318 | − clock-frequency = <528000000>; | |
| 2319 | − | |
| 2320 | − nvidia,emem-configuration = < | |
| 2321 | − 0x0f000007 | |
| 2322 | − 0x80000040 | |
| 2323 | − 0x00000002 | |
| 2140 | + 0x00000000 | |
| 2141 | + 0x00000000 | |
| 2142 | + 0x00000000 | |
| 2143 | + 0x00000000 | |
| 2144 | + 0x00000001 | |
| 2145 | + 0x00000014 | |
| 2146 | + 0x00000018 | |
| 2147 | + 0x0000001a | |
| 2148 | + 0x000017e2 | |
| 2149 | + 0x00000000 | |
| 2150 | + 0x000005f8 | |
| 2324 | 2151 | 0x00000003 |
| 2325 | − 0x0000000c | |
| 2326 | − 0x00000007 | |
| 2327 | − 0x00000008 | |
| 2152 | + 0x00000011 | |
| 2328 | 2153 | 0x00000001 |
| 2329 | − 0x00000002 | |
| 2330 | − 0x00000009 | |
| 2331 | − 0x00000002 | |
| 2332 | − 0x00000002 | |
| 2154 | + 0x00000000 | |
| 2155 | + 0x000000c7 | |
| 2156 | + 0x00000018 | |
| 2157 | + 0x000000d7 | |
| 2158 | + 0x00000200 | |
| 2333 | 2159 | 0x00000005 |
| 2334 | 2160 | 0x00000006 |
| 2335 | − 0x06050202 | |
| 2336 | − 0x0010090c | |
| 2337 | − 0x7428180d | |
| 2338 | − 0x70000f03 | |
| 2339 | − 0x001f0000 | |
| 2340 | − >; | |
| 2341 | − }; | |
| 2342 | − | |
| 2343 | − timing-600000000 { | |
| 2344 | − clock-frequency = <600000000>; | |
| 2345 | − | |
| 2346 | − nvidia,emem-configuration = < | |
| 2347 | − 0x00000009 | |
| 2348 | − 0x80000040 | |
| 2349 | − 0x00000003 | |
| 2350 | − 0x00000004 | |
| 2351 | − 0x0000000e | |
| 2352 | − 0x00000009 | |
| 2353 | − 0x0000000a | |
| 2354 | − 0x00000001 | |
| 2355 | − 0x00000003 | |
| 2356 | − 0x0000000b | |
| 2357 | − 0x00000002 | |
| 2358 | − 0x00000002 | |
| 2359 | 2161 | 0x00000005 |
| 2360 | − 0x00000007 | |
| 2361 | − 0x07050202 | |
| 2362 | − 0x00130b0e | |
| 2363 | − 0x73a91b0f | |
| 2364 | − 0x70000f03 | |
| 2365 | − 0x001f0000 | |
| 2366 | − >; | |
| 2367 | − }; | |
| 2368 | − | |
| 2369 | − timing-792000000 { | |
| 2370 | − clock-frequency = <792000000>; | |
| 2371 | − | |
| 2372 | − nvidia,emem-configuration = < | |
| 2373 | − 0x0e00000b | |
| 2374 | − 0x80000040 | |
| 2375 | − 0x00000004 | |
| 2376 | − 0x00000005 | |
| 2377 | − 0x00000013 | |
| 2378 | − 0x0000000c | |
| 2379 | − 0x0000000d | |
| 2380 | − 0x00000002 | |
| 2381 | − 0x00000003 | |
| 2382 | − 0x0000000c | |
| 2383 | − 0x00000002 | |
| 2384 | − 0x00000002 | |
| 2385 | − 0x00000006 | |
| 2162 | + 0x00000019 | |
| 2163 | + 0x00000000 | |
| 2386 | 2164 | 0x00000008 |
| 2387 | − 0x08060202 | |
| 2388 | − 0x00170e13 | |
| 2389 | − 0x736c2414 | |
| 2390 | − 0x70000f02 | |
| 2391 | − 0x001f0000 | |
| 2165 | + 0x00000008 | |
| 2166 | + 0x00001822 | |
| 2167 | + 0x00000000 | |
| 2168 | + 0x00000000 | |
| 2169 | + 0x00000000 | |
| 2170 | + 0x104ab098 | |
| 2171 | + 0xe00700b1 | |
| 2172 | + 0x00008000 | |
| 2173 | + 0x007fc008 | |
| 2174 | + 0x007fc008 | |
| 2175 | + 0x007fc008 | |
| 2176 | + 0x007fc008 | |
| 2177 | + 0x007fc008 | |
| 2178 | + 0x007fc008 | |
| 2179 | + 0x007fc008 | |
| 2180 | + 0x007fc008 | |
| 2181 | + 0x007fc008 | |
| 2182 | + 0x007fc008 | |
| 2183 | + 0x007fc008 | |
| 2184 | + 0x007fc008 | |
| 2185 | + 0x007fc008 | |
| 2186 | + 0x007fc008 | |
| 2187 | + 0x007fc008 | |
| 2188 | + 0x007fc008 | |
| 2189 | + 0x00000000 | |
| 2190 | + 0x00000000 | |
| 2191 | + 0x00000000 | |
| 2192 | + 0x00000000 | |
| 2193 | + 0x00000000 | |
| 2194 | + 0x00000000 | |
| 2195 | + 0x00000000 | |
| 2196 | + 0x00000000 | |
| 2197 | + 0x00034000 | |
| 2198 | + 0x00034000 | |
| 2199 | + 0x00000000 | |
| 2200 | + 0x00034000 | |
| 2201 | + 0x00034000 | |
| 2202 | + 0x00000000 | |
| 2203 | + 0x00000000 | |
| 2204 | + 0x00000000 | |
| 2205 | + 0x00000000 | |
| 2206 | + 0x00000000 | |
| 2207 | + 0x00000000 | |
| 2208 | + 0x00000000 | |
| 2209 | + 0x00000000 | |
| 2210 | + 0x00000000 | |
| 2211 | + 0x00000005 | |
| 2212 | + 0x00000005 | |
| 2213 | + 0x00000005 | |
| 2214 | + 0x00000005 | |
| 2215 | + 0x00000005 | |
| 2216 | + 0x00000005 | |
| 2217 | + 0x00000005 | |
| 2218 | + 0x00000005 | |
| 2219 | + 0x00000005 | |
| 2220 | + 0x00000005 | |
| 2221 | + 0x00000005 | |
| 2222 | + 0x00000005 | |
| 2223 | + 0x00000005 | |
| 2224 | + 0x00000005 | |
| 2225 | + 0x00000005 | |
| 2226 | + 0x00000005 | |
| 2227 | + 0x0000000a | |
| 2228 | + 0x0000000a | |
| 2229 | + 0x0000000a | |
| 2230 | + 0x0000000a | |
| 2231 | + 0x0000000a | |
| 2232 | + 0x0000000a | |
| 2233 | + 0x0000000a | |
| 2234 | + 0x0000000a | |
| 2235 | + 0x100002a0 | |
| 2236 | + 0x00000000 | |
| 2237 | + 0x00111111 | |
| 2238 | + 0x00000000 | |
| 2239 | + 0x00000000 | |
| 2240 | + 0x77ffc085 | |
| 2241 | + 0x00000000 | |
| 2242 | + 0x81f1f108 | |
| 2243 | + 0x07070004 | |
| 2244 | + 0x00000000 | |
| 2245 | + 0x016eeeee | |
| 2246 | + 0x61861820 | |
| 2247 | + 0x00514514 | |
| 2248 | + 0x00514514 | |
| 2249 | + 0x61861800 | |
| 2250 | + 0x0606003f | |
| 2251 | + 0x00000000 | |
| 2252 | + 0x00000000 | |
| 2253 | + 0x00000100 | |
| 2254 | + 0x00f7000e | |
| 2255 | + 0x00000000 | |
| 2256 | + 0x00000004 | |
| 2257 | + 0x00004080 | |
| 2258 | + 0x80003012 | |
| 2259 | + 0x0000000f | |
| 2392 | 2260 | >; |
| 2393 | 2261 | }; |
| 2394 | 2262 | |
| 2395 | 2263 | timing-924000000 { |
| 2396 | 2264 | clock-frequency = <924000000>; |
| 2397 | 2265 | |
| 2398 | − nvidia,emem-configuration = < | |
| 2399 | − 0x0e00000d | |
| 2400 | − 0x80000040 | |
| 2266 | + nvidia,emc-auto-cal-config = <0xa1430303>; | |
| 2267 | + nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 2268 | + nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 2269 | + nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 2270 | + nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 2271 | + nvidia,emc-cfg = <0x73300000>; | |
| 2272 | + nvidia,emc-cfg-2 = <0x0000089d>; | |
| 2273 | + nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 2274 | + nvidia,emc-mode-1 = <0x80100002>; | |
| 2275 | + nvidia,emc-mode-2 = <0x80200020>; | |
| 2276 | + nvidia,emc-mode-4 = <0x00000000>; | |
| 2277 | + nvidia,emc-mode-reset = <0x80000f15>; | |
| 2278 | + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; | |
| 2279 | + nvidia,emc-sel-dpd-ctrl = <0x00040000>; | |
| 2280 | + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; | |
| 2281 | + nvidia,emc-zcal-cnt-long = <0x0000004c>; | |
| 2282 | + nvidia,emc-zcal-interval = <0x00020000>; | |
| 2283 | + | |
| 2284 | + nvidia,emc-configuration = < | |
| 2285 | + 0x0000002b | |
| 2286 | + 0x000000f0 | |
| 2287 | + 0x00000000 | |
| 2288 | + 0x0000001e | |
| 2289 | + 0x0000000b | |
| 2290 | + 0x00000009 | |
| 2291 | + 0x0000000f | |
| 2401 | 2292 | 0x00000005 |
| 2402 | − 0x00000006 | |
| 2403 | 2293 | 0x00000016 |
| 2404 | − 0x0000000e | |
| 2405 | − 0x0000000f | |
| 2406 | − 0x00000002 | |
| 2294 | + 0x0000000b | |
| 2295 | + 0x0000000b | |
| 2407 | 2296 | 0x00000004 |
| 2408 | − 0x0000000e | |
| 2409 | 2297 | 0x00000002 |
| 2298 | + 0x00000000 | |
| 2299 | + 0x00000007 | |
| 2300 | + 0x00000007 | |
| 2301 | + 0x0000000d | |
| 2302 | + 0x00000002 | |
| 2303 | + 0x00000000 | |
| 2410 | 2304 | 0x00000002 |
| 2305 | + 0x0000000f | |
| 2306 | + 0x000a0000 | |
| 2307 | + 0x00000004 | |
| 2308 | + 0x00000000 | |
| 2309 | + 0x00000000 | |
| 2310 | + 0x00000000 | |
| 2311 | + 0x00000000 | |
| 2312 | + 0x00000001 | |
| 2313 | + 0x00000016 | |
| 2314 | + 0x0000001a | |
| 2315 | + 0x0000001c | |
| 2316 | + 0x00001be7 | |
| 2317 | + 0x00000000 | |
| 2318 | + 0x000006f9 | |
| 2319 | + 0x00000004 | |
| 2320 | + 0x00000015 | |
| 2321 | + 0x00000001 | |
| 2322 | + 0x00000000 | |
| 2323 | + 0x000000e7 | |
| 2324 | + 0x0000001b | |
| 2325 | + 0x000000fb | |
| 2326 | + 0x00000200 | |
| 2411 | 2327 | 0x00000006 |
| 2412 | − 0x00000009 | |
| 2413 | − 0x09060202 | |
| 2414 | − 0x001a1016 | |
| 2415 | − 0x734e2a17 | |
| 2416 | − 0x70000f02 | |
| 2417 | − 0x001f0000 | |
| 2328 | + 0x00000007 | |
| 2329 | + 0x00000006 | |
| 2330 | + 0x0000001e | |
| 2331 | + 0x00000000 | |
| 2332 | + 0x0000000a | |
| 2333 | + 0x0000000a | |
| 2334 | + 0x00001c28 | |
| 2335 | + 0x00000000 | |
| 2336 | + 0x00000000 | |
| 2337 | + 0x00000000 | |
| 2338 | + 0x104ab898 | |
| 2339 | + 0xe00400b1 | |
| 2340 | + 0x00008000 | |
| 2341 | + 0x007f800a | |
| 2342 | + 0x007f800a | |
| 2343 | + 0x007f800a | |
| 2344 | + 0x007f800a | |
| 2345 | + 0x007f800a | |
| 2346 | + 0x007f800a | |
| 2347 | + 0x007f800a | |
| 2348 | + 0x007f800a | |
| 2349 | + 0x007f800a | |
| 2350 | + 0x007f800a | |
| 2351 | + 0x007f800a | |
| 2352 | + 0x007f800a | |
| 2353 | + 0x007f800a | |
| 2354 | + 0x007f800a | |
| 2355 | + 0x007f800a | |
| 2356 | + 0x007f800a | |
| 2357 | + 0x00000000 | |
| 2358 | + 0x00000000 | |
| 2359 | + 0x00000000 | |
| 2360 | + 0x00000000 | |
| 2361 | + 0x00000000 | |
| 2362 | + 0x00000000 | |
| 2363 | + 0x00000000 | |
| 2364 | + 0x00000000 | |
| 2365 | + 0x0002c000 | |
| 2366 | + 0x0002c000 | |
| 2367 | + 0x00000000 | |
| 2368 | + 0x0002c000 | |
| 2369 | + 0x0002c000 | |
| 2370 | + 0x00000000 | |
| 2371 | + 0x00000000 | |
| 2372 | + 0x00000000 | |
| 2373 | + 0x00000000 | |
| 2374 | + 0x00000000 | |
| 2375 | + 0x00000000 | |
| 2376 | + 0x00000000 | |
| 2377 | + 0x00000000 | |
| 2378 | + 0x00000000 | |
| 2379 | + 0x00000004 | |
| 2380 | + 0x00000004 | |
| 2381 | + 0x00000004 | |
| 2382 | + 0x00000004 | |
| 2383 | + 0x00000004 | |
| 2384 | + 0x00000004 | |
| 2385 | + 0x00000004 | |
| 2386 | + 0x00000004 | |
| 2387 | + 0x00000004 | |
| 2388 | + 0x00000004 | |
| 2389 | + 0x00000004 | |
| 2390 | + 0x00000004 | |
| 2391 | + 0x00000004 | |
| 2392 | + 0x00000004 | |
| 2393 | + 0x00000004 | |
| 2394 | + 0x00000004 | |
| 2395 | + 0x00000008 | |
| 2396 | + 0x00000008 | |
| 2397 | + 0x00000008 | |
| 2398 | + 0x00000008 | |
| 2399 | + 0x00000008 | |
| 2400 | + 0x00000008 | |
| 2401 | + 0x00000008 | |
| 2402 | + 0x00000008 | |
| 2403 | + 0x100002a0 | |
| 2404 | + 0x00000000 | |
| 2405 | + 0x00111111 | |
| 2406 | + 0x00000000 | |
| 2407 | + 0x00000000 | |
| 2408 | + 0x77ffc085 | |
| 2409 | + 0x00000000 | |
| 2410 | + 0x81f1f108 | |
| 2411 | + 0x07070004 | |
| 2412 | + 0x00000000 | |
| 2413 | + 0x016eeeee | |
| 2414 | + 0x5d75d720 | |
| 2415 | + 0x00514514 | |
| 2416 | + 0x00514514 | |
| 2417 | + 0x5d75d700 | |
| 2418 | + 0x0606003f | |
| 2419 | + 0x00000000 | |
| 2420 | + 0x00000000 | |
| 2421 | + 0x00000128 | |
| 2422 | + 0x00cd000e | |
| 2423 | + 0x00000000 | |
| 2424 | + 0x00000004 | |
| 2425 | + 0x00004080 | |
| 2426 | + 0x800037ea | |
| 2427 | + 0x00000011 | |
| 2418 | 2428 | >; |
| 2419 | 2429 | }; |
| 2420 | 2430 | }; |
| @@ -2422,9 +2432,9 @@ · 1 unmodified line | ||
| 2422 | 2432 | }; |
| 2423 | 2433 | |
| 2424 | 2434 | &emc_icc_dvfs_opp_table { |
| 2425 | − /delete-node/ opp@1200000000,1100; | |
| 2435 | + /delete-node/ opp-1200000000-1100; | |
| 2426 | 2436 | }; |
| 2427 | 2437 | |
| 2428 | 2438 | &emc_bw_dfs_opp_table { |
| 2429 | − /delete-node/ opp@1200000000; | |
| 2439 | + /delete-node/ opp-1200000000; | |
| 2430 | 2440 | }; |
| @@ -72,7 +72,7 @@ · 71 unmodified lines | ||
| 72 | 72 | status = "okay"; |
| 73 | 73 | }; |
| 74 | 74 | |
| 75 | − gpu@0,57000000 { | |
| 75 | + gpu@57000000 { | |
| 76 | 76 | /* |
| 77 | 77 | * Node left disabled on purpose - the bootloader will enable |
| 78 | 78 | * it after having set the VPR up |
| @@ -1389,6 +1389,7 @@ · 1310 unmodified lines | ||
| 1389 | 1389 | */ |
| 1390 | 1390 | serial@70006000 { |
| 1391 | 1391 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1392 | + /delete-property/ reg-shift; | |
| 1392 | 1393 | status = "okay"; |
| 1393 | 1394 | }; |
| 1394 | 1395 | |
| @@ -1401,6 +1402,7 @@ · 6 unmodified lines | ||
| 1401 | 1402 | */ |
| 1402 | 1403 | serial@70006040 { |
| 1403 | 1404 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1405 | + /delete-property/ reg-shift; | |
| 1404 | 1406 | status = "okay"; |
| 1405 | 1407 | }; |
| 1406 | 1408 | |
| @@ -1655,7 +1657,8 @@ · 248 unmodified lines | ||
| 1655 | 1657 | spi@7000da00 { |
| 1656 | 1658 | status = "okay"; |
| 1657 | 1659 | spi-max-frequency = <25000000>; |
| 1658 | − spi-flash@0 { | |
| 1660 | + | |
| 1661 | + flash@0 { | |
| 1659 | 1662 | compatible = "winbond,w25q32dw", "jedec,spi-nor"; |
| 1660 | 1663 | reg = <0>; |
| 1661 | 1664 | spi-max-frequency = <20000000>; |
| @@ -1868,7 +1871,7 @@ · 206 unmodified lines | ||
| 1868 | 1871 | vbus-supply = <&vdd_usb3_vbus>; |
| 1869 | 1872 | }; |
| 1870 | 1873 | |
| 1871 | − clk32k_in: clock@0 { | |
| 1874 | + clk32k_in: clock-32k { | |
| 1872 | 1875 | compatible = "fixed-clock"; |
| 1873 | 1876 | clock-frequency = <32768>; |
| 1874 | 1877 | #clock-cells = <0>; |
| @@ -1892,7 +1895,7 @@ · 17 unmodified lines | ||
| 1892 | 1895 | }; |
| 1893 | 1896 | }; |
| 1894 | 1897 | |
| 1895 | − vdd_mux: regulator@0 { | |
| 1898 | + vdd_mux: regulator-mux { | |
| 1896 | 1899 | compatible = "regulator-fixed"; |
| 1897 | 1900 | regulator-name = "+VDD_MUX"; |
| 1898 | 1901 | regulator-min-microvolt = <12000000>; |
| @@ -1901,7 +1904,7 @@ · 2 unmodified lines | ||
| 1901 | 1904 | regulator-boot-on; |
| 1902 | 1905 | }; |
| 1903 | 1906 | |
| 1904 | − vdd_5v0_sys: regulator@1 { | |
| 1907 | + vdd_5v0_sys: regulator-5v0sys { | |
| 1905 | 1908 | compatible = "regulator-fixed"; |
| 1906 | 1909 | regulator-name = "+5V_SYS"; |
| 1907 | 1910 | regulator-min-microvolt = <5000000>; |
| @@ -1911,7 +1914,7 @@ · 3 unmodified lines | ||
| 1911 | 1914 | vin-supply = <&vdd_mux>; |
| 1912 | 1915 | }; |
| 1913 | 1916 | |
| 1914 | − vdd_3v3_sys: regulator@2 { | |
| 1917 | + vdd_3v3_sys: regulator-3v3sys { | |
| 1915 | 1918 | compatible = "regulator-fixed"; |
| 1916 | 1919 | regulator-name = "+3.3V_SYS"; |
| 1917 | 1920 | regulator-min-microvolt = <3300000>; |
| @@ -1921,7 +1924,7 @@ · 3 unmodified lines | ||
| 1921 | 1924 | vin-supply = <&vdd_mux>; |
| 1922 | 1925 | }; |
| 1923 | 1926 | |
| 1924 | − vdd_3v3_run: regulator@3 { | |
| 1927 | + vdd_3v3_run: regulator-3v3run { | |
| 1925 | 1928 | compatible = "regulator-fixed"; |
| 1926 | 1929 | regulator-name = "+3.3V_RUN"; |
| 1927 | 1930 | regulator-min-microvolt = <3300000>; |
| @@ -1933,7 +1936,7 @@ · 5 unmodified lines | ||
| 1933 | 1936 | vin-supply = <&vdd_3v3_sys>; |
| 1934 | 1937 | }; |
| 1935 | 1938 | |
| 1936 | − vdd_3v3_hdmi: regulator@4 { | |
| 1939 | + vdd_3v3_hdmi: regulator-3v3hdmi { | |
| 1937 | 1940 | compatible = "regulator-fixed"; |
| 1938 | 1941 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
| 1939 | 1942 | regulator-min-microvolt = <3300000>; |
| @@ -1941,7 +1944,7 @@ · 1 unmodified line | ||
| 1941 | 1944 | vin-supply = <&vdd_3v3_run>; |
| 1942 | 1945 | }; |
| 1943 | 1946 | |
| 1944 | − vdd_usb1_vbus: regulator@5 { | |
| 1947 | + vdd_usb1_vbus: regulator-usb1 { | |
| 1945 | 1948 | compatible = "regulator-fixed"; |
| 1946 | 1949 | regulator-name = "+USB0_VBUS_SW"; |
| 1947 | 1950 | regulator-min-microvolt = <5000000>; |
| @@ -1952,7 +1955,7 @@ · 4 unmodified lines | ||
| 1952 | 1955 | vin-supply = <&vdd_5v0_sys>; |
| 1953 | 1956 | }; |
| 1954 | 1957 | |
| 1955 | − vdd_usb3_vbus: regulator@6 { | |
| 1958 | + vdd_usb3_vbus: regulator-usb3 { | |
| 1956 | 1959 | compatible = "regulator-fixed"; |
| 1957 | 1960 | regulator-name = "+5V_USB_HS"; |
| 1958 | 1961 | regulator-min-microvolt = <5000000>; |
| @@ -1963,7 +1966,7 @@ · 4 unmodified lines | ||
| 1963 | 1966 | vin-supply = <&vdd_5v0_sys>; |
| 1964 | 1967 | }; |
| 1965 | 1968 | |
| 1966 | − vdd_3v3_lp0: regulator@7 { | |
| 1969 | + vdd_3v3_lp0: regulator-lp0 { | |
| 1967 | 1970 | compatible = "regulator-fixed"; |
| 1968 | 1971 | regulator-name = "+3.3V_LP0"; |
| 1969 | 1972 | regulator-min-microvolt = <3300000>; |
| @@ -1975,7 +1978,7 @@ · 5 unmodified lines | ||
| 1975 | 1978 | vin-supply = <&vdd_3v3_sys>; |
| 1976 | 1979 | }; |
| 1977 | 1980 | |
| 1978 | − vdd_hdmi_pll: regulator@8 { | |
| 1981 | + vdd_hdmi_pll: regulator-hdmipll { | |
| 1979 | 1982 | compatible = "regulator-fixed"; |
| 1980 | 1983 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; |
| 1981 | 1984 | regulator-min-microvolt = <1050000>; |
| @@ -1984,7 +1987,7 @@ · 2 unmodified lines | ||
| 1984 | 1987 | vin-supply = <&vdd_1v05_run>; |
| 1985 | 1988 | }; |
| 1986 | 1989 | |
| 1987 | − vdd_5v0_hdmi: regulator@9 { | |
| 1990 | + vdd_5v0_hdmi: regulator-hdmicon { | |
| 1988 | 1991 | compatible = "regulator-fixed"; |
| 1989 | 1992 | regulator-name = "+5V_HDMI_CON"; |
| 1990 | 1993 | regulator-min-microvolt = <5000000>; |
| @@ -1995,7 +1998,7 @@ · 4 unmodified lines | ||
| 1995 | 1998 | }; |
| 1996 | 1999 | |
| 1997 | 2000 | /* Molex power connector */ |
| 1998 | − vdd_5v0_sata: regulator@10 { | |
| 2001 | + vdd_5v0_sata: regulator-5v0sata { | |
| 1999 | 2002 | compatible = "regulator-fixed"; |
| 2000 | 2003 | regulator-name = "+5V_SATA"; |
| 2001 | 2004 | regulator-min-microvolt = <5000000>; |
| @@ -2005,7 +2008,7 @@ · 3 unmodified lines | ||
| 2005 | 2008 | vin-supply = <&vdd_5v0_sys>; |
| 2006 | 2009 | }; |
| 2007 | 2010 | |
| 2008 | − vdd_12v0_sata: regulator@11 { | |
| 2011 | + vdd_12v0_sata: regulator-12v0sata { | |
| 2009 | 2012 | compatible = "regulator-fixed"; |
| 2010 | 2013 | regulator-name = "+12V_SATA"; |
| 2011 | 2014 | regulator-min-microvolt = <12000000>; |
| @@ -2044,7 +2047,7 @@ · 32 unmodified lines | ||
| 2044 | 2047 | }; |
| 2045 | 2048 | |
| 2046 | 2049 | thermal-zones { |
| 2047 | − cpu { | |
| 2050 | + cpu-thermal { | |
| 2048 | 2051 | trips { |
| 2049 | 2052 | cpu-shutdown-trip { |
| 2050 | 2053 | temperature = <101000>; |
| @@ -2054,7 +2057,7 @@ · 3 unmodified lines | ||
| 2054 | 2057 | }; |
| 2055 | 2058 | }; |
| 2056 | 2059 | |
| 2057 | − mem { | |
| 2060 | + mem-thermal { | |
| 2058 | 2061 | trips { |
| 2059 | 2062 | mem-shutdown-trip { |
| 2060 | 2063 | temperature = <101000>; |
| @@ -2064,7 +2067,7 @@ · 3 unmodified lines | ||
| 2064 | 2067 | }; |
| 2065 | 2068 | }; |
| 2066 | 2069 | |
| 2067 | − gpu { | |
| 2070 | + gpu-thermal { | |
| 2068 | 2071 | trips { |
| 2069 | 2072 | gpu-shutdown-trip { |
| 2070 | 2073 | temperature = <101000>; |
| @@ -14,60 +14,70 @@ · 13 unmodified lines | ||
| 14 | 14 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 15 | 15 | clock-names = "emc-parent"; |
| 16 | 16 | }; |
| 17 | + | |
| 17 | 18 | timing-20400000 { |
| 18 | 19 | clock-frequency = <20400000>; |
| 19 | 20 | nvidia,parent-clock-frequency = <408000000>; |
| 20 | 21 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 21 | 22 | clock-names = "emc-parent"; |
| 22 | 23 | }; |
| 24 | + | |
| 23 | 25 | timing-40800000 { |
| 24 | 26 | clock-frequency = <40800000>; |
| 25 | 27 | nvidia,parent-clock-frequency = <408000000>; |
| 26 | 28 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 27 | 29 | clock-names = "emc-parent"; |
| 28 | 30 | }; |
| 31 | + | |
| 29 | 32 | timing-68000000 { |
| 30 | 33 | clock-frequency = <68000000>; |
| 31 | 34 | nvidia,parent-clock-frequency = <408000000>; |
| 32 | 35 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 33 | 36 | clock-names = "emc-parent"; |
| 34 | 37 | }; |
| 38 | + | |
| 35 | 39 | timing-102000000 { |
| 36 | 40 | clock-frequency = <102000000>; |
| 37 | 41 | nvidia,parent-clock-frequency = <408000000>; |
| 38 | 42 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 39 | 43 | clock-names = "emc-parent"; |
| 40 | 44 | }; |
| 45 | + | |
| 41 | 46 | timing-204000000 { |
| 42 | 47 | clock-frequency = <204000000>; |
| 43 | 48 | nvidia,parent-clock-frequency = <408000000>; |
| 44 | 49 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 45 | 50 | clock-names = "emc-parent"; |
| 46 | 51 | }; |
| 52 | + | |
| 47 | 53 | timing-300000000 { |
| 48 | 54 | clock-frequency = <300000000>; |
| 49 | 55 | nvidia,parent-clock-frequency = <600000000>; |
| 50 | 56 | clocks = <&tegra_car TEGRA124_CLK_PLL_C>; |
| 51 | 57 | clock-names = "emc-parent"; |
| 52 | 58 | }; |
| 59 | + | |
| 53 | 60 | timing-396000000 { |
| 54 | 61 | clock-frequency = <396000000>; |
| 55 | 62 | nvidia,parent-clock-frequency = <792000000>; |
| 56 | 63 | clocks = <&tegra_car TEGRA124_CLK_PLL_M>; |
| 57 | 64 | clock-names = "emc-parent"; |
| 58 | 65 | }; |
| 66 | + | |
| 59 | 67 | timing-528000000 { |
| 60 | 68 | clock-frequency = <528000000>; |
| 61 | 69 | nvidia,parent-clock-frequency = <528000000>; |
| 62 | 70 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 63 | 71 | clock-names = "emc-parent"; |
| 64 | 72 | }; |
| 73 | + | |
| 65 | 74 | timing-600000000 { |
| 66 | 75 | clock-frequency = <600000000>; |
| 67 | 76 | nvidia,parent-clock-frequency = <600000000>; |
| 68 | 77 | clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; |
| 69 | 78 | clock-names = "emc-parent"; |
| 70 | 79 | }; |
| 80 | + | |
| 71 | 81 | timing-792000000 { |
| 72 | 82 | clock-frequency = <792000000>; |
| 73 | 83 | nvidia,parent-clock-frequency = <792000000>; |
| @@ -85,60 +95,70 @@ · 11 unmodified lines | ||
| 85 | 95 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 86 | 96 | clock-names = "emc-parent"; |
| 87 | 97 | }; |
| 98 | + | |
| 88 | 99 | timing-20400000 { |
| 89 | 100 | clock-frequency = <20400000>; |
| 90 | 101 | nvidia,parent-clock-frequency = <408000000>; |
| 91 | 102 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 92 | 103 | clock-names = "emc-parent"; |
| 93 | 104 | }; |
| 105 | + | |
| 94 | 106 | timing-40800000 { |
| 95 | 107 | clock-frequency = <40800000>; |
| 96 | 108 | nvidia,parent-clock-frequency = <408000000>; |
| 97 | 109 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 98 | 110 | clock-names = "emc-parent"; |
| 99 | 111 | }; |
| 112 | + | |
| 100 | 113 | timing-68000000 { |
| 101 | 114 | clock-frequency = <68000000>; |
| 102 | 115 | nvidia,parent-clock-frequency = <408000000>; |
| 103 | 116 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 104 | 117 | clock-names = "emc-parent"; |
| 105 | 118 | }; |
| 119 | + | |
| 106 | 120 | timing-102000000 { |
| 107 | 121 | clock-frequency = <102000000>; |
| 108 | 122 | nvidia,parent-clock-frequency = <408000000>; |
| 109 | 123 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 110 | 124 | clock-names = "emc-parent"; |
| 111 | 125 | }; |
| 126 | + | |
| 112 | 127 | timing-204000000 { |
| 113 | 128 | clock-frequency = <204000000>; |
| 114 | 129 | nvidia,parent-clock-frequency = <408000000>; |
| 115 | 130 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 116 | 131 | clock-names = "emc-parent"; |
| 117 | 132 | }; |
| 133 | + | |
| 118 | 134 | timing-300000000 { |
| 119 | 135 | clock-frequency = <300000000>; |
| 120 | 136 | nvidia,parent-clock-frequency = <600000000>; |
| 121 | 137 | clocks = <&tegra_car TEGRA124_CLK_PLL_C>; |
| 122 | 138 | clock-names = "emc-parent"; |
| 123 | 139 | }; |
| 140 | + | |
| 124 | 141 | timing-396000000 { |
| 125 | 142 | clock-frequency = <396000000>; |
| 126 | 143 | nvidia,parent-clock-frequency = <792000000>; |
| 127 | 144 | clocks = <&tegra_car TEGRA124_CLK_PLL_M>; |
| 128 | 145 | clock-names = "emc-parent"; |
| 129 | 146 | }; |
| 147 | + | |
| 130 | 148 | timing-528000000 { |
| 131 | 149 | clock-frequency = <528000000>; |
| 132 | 150 | nvidia,parent-clock-frequency = <528000000>; |
| 133 | 151 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 134 | 152 | clock-names = "emc-parent"; |
| 135 | 153 | }; |
| 154 | + | |
| 136 | 155 | timing-600000000 { |
| 137 | 156 | clock-frequency = <600000000>; |
| 138 | 157 | nvidia,parent-clock-frequency = <600000000>; |
| 139 | 158 | clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; |
| 140 | 159 | clock-names = "emc-parent"; |
| 141 | 160 | }; |
| 161 | + | |
| 142 | 162 | timing-792000000 { |
| 143 | 163 | clock-frequency = <792000000>; |
| 144 | 164 | nvidia,parent-clock-frequency = <792000000>; |
| @@ -156,60 +176,70 @@ · 11 unmodified lines | ||
| 156 | 176 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 157 | 177 | clock-names = "emc-parent"; |
| 158 | 178 | }; |
| 179 | + | |
| 159 | 180 | timing-20400000 { |
| 160 | 181 | clock-frequency = <20400000>; |
| 161 | 182 | nvidia,parent-clock-frequency = <408000000>; |
| 162 | 183 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 163 | 184 | clock-names = "emc-parent"; |
| 164 | 185 | }; |
| 186 | + | |
| 165 | 187 | timing-40800000 { |
| 166 | 188 | clock-frequency = <40800000>; |
| 167 | 189 | nvidia,parent-clock-frequency = <408000000>; |
| 168 | 190 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 169 | 191 | clock-names = "emc-parent"; |
| 170 | 192 | }; |
| 193 | + | |
| 171 | 194 | timing-68000000 { |
| 172 | 195 | clock-frequency = <68000000>; |
| 173 | 196 | nvidia,parent-clock-frequency = <408000000>; |
| 174 | 197 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 175 | 198 | clock-names = "emc-parent"; |
| 176 | 199 | }; |
| 200 | + | |
| 177 | 201 | timing-102000000 { |
| 178 | 202 | clock-frequency = <102000000>; |
| 179 | 203 | nvidia,parent-clock-frequency = <408000000>; |
| 180 | 204 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 181 | 205 | clock-names = "emc-parent"; |
| 182 | 206 | }; |
| 207 | + | |
| 183 | 208 | timing-204000000 { |
| 184 | 209 | clock-frequency = <204000000>; |
| 185 | 210 | nvidia,parent-clock-frequency = <408000000>; |
| 186 | 211 | clocks = <&tegra_car TEGRA124_CLK_PLL_P>; |
| 187 | 212 | clock-names = "emc-parent"; |
| 188 | 213 | }; |
| 214 | + | |
| 189 | 215 | timing-300000000 { |
| 190 | 216 | clock-frequency = <300000000>; |
| 191 | 217 | nvidia,parent-clock-frequency = <600000000>; |
| 192 | 218 | clocks = <&tegra_car TEGRA124_CLK_PLL_C>; |
| 193 | 219 | clock-names = "emc-parent"; |
| 194 | 220 | }; |
| 221 | + | |
| 195 | 222 | timing-396000000 { |
| 196 | 223 | clock-frequency = <396000000>; |
| 197 | 224 | nvidia,parent-clock-frequency = <792000000>; |
| 198 | 225 | clocks = <&tegra_car TEGRA124_CLK_PLL_M>; |
| 199 | 226 | clock-names = "emc-parent"; |
| 200 | 227 | }; |
| 228 | + | |
| 201 | 229 | timing-528000000 { |
| 202 | 230 | clock-frequency = <528000000>; |
| 203 | 231 | nvidia,parent-clock-frequency = <528000000>; |
| 204 | 232 | clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; |
| 205 | 233 | clock-names = "emc-parent"; |
| 206 | 234 | }; |
| 235 | + | |
| 207 | 236 | timing-600000000 { |
| 208 | 237 | clock-frequency = <600000000>; |
| 209 | 238 | nvidia,parent-clock-frequency = <600000000>; |
| 210 | 239 | clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; |
| 211 | 240 | clock-names = "emc-parent"; |
| 212 | 241 | }; |
| 242 | + | |
| 213 | 243 | timing-792000000 { |
| 214 | 244 | clock-frequency = <792000000>; |
| 215 | 245 | nvidia,parent-clock-frequency = <792000000>; |
| @@ -219,3707 +249,583 @@ · 3 unmodified lines | ||
| 219 | 249 | }; |
| 220 | 250 | }; |
| 221 | 251 | |
| 222 | − external-memory-controller@7001b000 { | |
| 252 | + memory-controller@70019000 { | |
| 223 | 253 | emc-timings-1 { |
| 224 | 254 | nvidia,ram-code = <1>; |
| 225 | 255 | |
| 226 | 256 | timing-12750000 { |
| 227 | 257 | clock-frequency = <12750000>; |
| 228 | 258 | |
| 229 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 230 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 231 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 232 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 233 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 234 | − nvidia,emc-cfg = <0x73240000>; | |
| 235 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 236 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 237 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 238 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 239 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 240 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 241 | − nvidia,emc-mrs-wait-cnt = <0x000c000c>; | |
| 242 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 243 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 244 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 245 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 246 | − | |
| 247 | − nvidia,emc-configuration = < | |
| 248 | − 0x00000000 /* EMC_RC */ | |
| 249 | − 0x00000003 /* EMC_RFC */ | |
| 250 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 251 | − 0x00000000 /* EMC_RAS */ | |
| 252 | − 0x00000000 /* EMC_RP */ | |
| 253 | − 0x00000004 /* EMC_R2W */ | |
| 254 | − 0x0000000a /* EMC_W2R */ | |
| 255 | − 0x00000003 /* EMC_R2P */ | |
| 256 | − 0x0000000b /* EMC_W2P */ | |
| 257 | − 0x00000000 /* EMC_RD_RCD */ | |
| 258 | − 0x00000000 /* EMC_WR_RCD */ | |
| 259 | − 0x00000003 /* EMC_RRD */ | |
| 260 | − 0x00000003 /* EMC_REXT */ | |
| 261 | − 0x00000000 /* EMC_WEXT */ | |
| 262 | − 0x00000006 /* EMC_WDV */ | |
| 263 | − 0x00000006 /* EMC_WDV_MASK */ | |
| 264 | − 0x00000006 /* EMC_QUSE */ | |
| 265 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 266 | − 0x00000000 /* EMC_IBDLY */ | |
| 267 | − 0x00000005 /* EMC_EINPUT */ | |
| 268 | − 0x00000005 /* EMC_EINPUT_DURATION */ | |
| 269 | − 0x00010000 /* EMC_PUTERM_EXTRA */ | |
| 270 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 271 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 272 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 273 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 274 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 275 | − 0x00000004 /* EMC_QRST */ | |
| 276 | − 0x0000000c /* EMC_QSAFE */ | |
| 277 | − 0x0000000d /* EMC_RDV */ | |
| 278 | − 0x0000000f /* EMC_RDV_MASK */ | |
| 279 | − 0x00000060 /* EMC_REFRESH */ | |
| 280 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 281 | − 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 282 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 283 | − 0x00000002 /* EMC_PDEX2RD */ | |
| 284 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 285 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 286 | − 0x00000007 /* EMC_AR2PDEN */ | |
| 287 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 288 | − 0x00000005 /* EMC_TXSR */ | |
| 289 | − 0x00000005 /* EMC_TXSRDLL */ | |
| 290 | − 0x00000004 /* EMC_TCKE */ | |
| 291 | − 0x00000005 /* EMC_TCKESR */ | |
| 292 | − 0x00000004 /* EMC_TPD */ | |
| 293 | − 0x00000000 /* EMC_TFAW */ | |
| 294 | − 0x00000000 /* EMC_TRPAB */ | |
| 295 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 296 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 297 | − 0x00000064 /* EMC_TREFBW */ | |
| 298 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 299 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 300 | − 0x00000000 /* EMC_ODT_READ */ | |
| 301 | − 0x106aa298 /* EMC_FBIO_CFG5 */ | |
| 302 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 303 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 304 | − 0x00064000 /* EMC_DLL_XFORM_DQS0 */ | |
| 305 | − 0x00064000 /* EMC_DLL_XFORM_DQS1 */ | |
| 306 | − 0x00064000 /* EMC_DLL_XFORM_DQS2 */ | |
| 307 | − 0x00064000 /* EMC_DLL_XFORM_DQS3 */ | |
| 308 | − 0x00064000 /* EMC_DLL_XFORM_DQS4 */ | |
| 309 | − 0x00064000 /* EMC_DLL_XFORM_DQS5 */ | |
| 310 | − 0x00064000 /* EMC_DLL_XFORM_DQS6 */ | |
| 311 | − 0x00064000 /* EMC_DLL_XFORM_DQS7 */ | |
| 312 | − 0x00064000 /* EMC_DLL_XFORM_DQS8 */ | |
| 313 | − 0x00064000 /* EMC_DLL_XFORM_DQS9 */ | |
| 314 | − 0x00064000 /* EMC_DLL_XFORM_DQS10 */ | |
| 315 | − 0x00064000 /* EMC_DLL_XFORM_DQS11 */ | |
| 316 | − 0x00064000 /* EMC_DLL_XFORM_DQS12 */ | |
| 317 | − 0x00064000 /* EMC_DLL_XFORM_DQS13 */ | |
| 318 | − 0x00064000 /* EMC_DLL_XFORM_DQS14 */ | |
| 319 | − 0x00064000 /* EMC_DLL_XFORM_DQS15 */ | |
| 320 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 321 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 322 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 323 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 324 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 325 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 326 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 327 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 328 | − 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 329 | − 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 330 | − 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 331 | − 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 332 | − 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 333 | − 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 334 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 335 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 336 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 337 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 338 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 339 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 340 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 341 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 342 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 343 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 344 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 345 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 346 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 347 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 348 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 349 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 350 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 351 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 352 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 353 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 354 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 355 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 356 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 357 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 358 | − 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ | |
| 359 | − 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ | |
| 360 | − 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ | |
| 361 | − 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ | |
| 362 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ | |
| 363 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ | |
| 364 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ | |
| 365 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ | |
| 366 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 367 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 368 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 369 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 370 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 371 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 372 | − 0x00000303 /* EMC_XM2CLKPADCTRL2 */ | |
| 373 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 374 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 375 | − 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ | |
| 376 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 377 | − 0x51451400 /* EMC_XM2DQSPADCTRL3 */ | |
| 378 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 379 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 380 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 381 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 382 | − 0x00000007 /* EMC_TXDSRVTTGEN */ | |
| 383 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 384 | − 0x00000042 /* EMC_ZCAL_WAIT_CNT */ | |
| 385 | − 0x000c000c /* EMC_MRS_WAIT_CNT2 */ | |
| 386 | − 0x00000000 /* EMC_CTT */ | |
| 387 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 388 | − 0x0000f2f3 /* EMC_CFG_PIPE */ | |
| 389 | − 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ | |
| 390 | − 0x0000000a /* EMC_QPOP */ | |
| 259 | + nvidia,emem-configuration = < | |
| 260 | + 0x40040001 /* MC_EMEM_ARB_CFG */ | |
| 261 | + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ | |
| 262 | + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ | |
| 263 | + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ | |
| 264 | + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ | |
| 265 | + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ | |
| 266 | + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ | |
| 267 | + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ | |
| 268 | + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ | |
| 269 | + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ | |
| 270 | + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ | |
| 271 | + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ | |
| 272 | + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ | |
| 273 | + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ | |
| 274 | + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ | |
| 275 | + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ | |
| 276 | + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ | |
| 277 | + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ | |
| 278 | + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ | |
| 391 | 279 | >; |
| 392 | 280 | }; |
| 393 | 281 | |
| 394 | 282 | timing-20400000 { |
| 395 | 283 | clock-frequency = <20400000>; |
| 396 | 284 | |
| 397 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 398 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 399 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 400 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 401 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 402 | − nvidia,emc-cfg = <0x73240000>; | |
| 403 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 404 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 405 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 406 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 407 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 408 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 409 | − nvidia,emc-mrs-wait-cnt = <0x000c000c>; | |
| 410 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 411 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 412 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 413 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 285 | + nvidia,emem-configuration = < | |
| 286 | + 0x40020001 /* MC_EMEM_ARB_CFG */ | |
| 287 | + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ | |
| 288 | + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ | |
| 289 | + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ | |
| 290 | + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ | |
| 291 | + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ | |
| 292 | + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ | |
| 293 | + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ | |
| 294 | + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ | |
| 295 | + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ | |
| 296 | + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ | |
| 297 | + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ | |
| 298 | + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ | |
| 299 | + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ | |
| 300 | + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ | |
| 301 | + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ | |
| 302 | + 0x76230303 /* MC_EMEM_ARB_MISC0 */ | |
| 303 | + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ | |
| 304 | + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ | |
| 305 | + >; | |
| 306 | + }; | |
| 414 | 307 | |
| 415 | − nvidia,emc-configuration = < | |
| 416 | − 0x00000000 /* EMC_RC */ | |
| 417 | − 0x00000005 /* EMC_RFC */ | |
| 418 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 419 | − 0x00000000 /* EMC_RAS */ | |
| 420 | − 0x00000000 /* EMC_RP */ | |
| 421 | − 0x00000004 /* EMC_R2W */ | |
| 422 | − 0x0000000a /* EMC_W2R */ | |
| 423 | − 0x00000003 /* EMC_R2P */ | |
| 424 | − 0x0000000b /* EMC_W2P */ | |
| 425 | − 0x00000000 /* EMC_RD_RCD */ | |
| 426 | − 0x00000000 /* EMC_WR_RCD */ | |
| 427 | − 0x00000003 /* EMC_RRD */ | |
| 428 | − 0x00000003 /* EMC_REXT */ | |
| 429 | − 0x00000000 /* EMC_WEXT */ | |
| 430 | − 0x00000006 /* EMC_WDV */ | |
| 431 | − 0x00000006 /* EMC_WDV_MASK */ | |
| 432 | − 0x00000006 /* EMC_QUSE */ | |
| 433 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 434 | − 0x00000000 /* EMC_IBDLY */ | |
| 435 | − 0x00000005 /* EMC_EINPUT */ | |
| 436 | − 0x00000005 /* EMC_EINPUT_DURATION */ | |
| 437 | − 0x00010000 /* EMC_PUTERM_EXTRA */ | |
| 438 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 439 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 440 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 441 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 442 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 443 | − 0x00000004 /* EMC_QRST */ | |
| 444 | − 0x0000000c /* EMC_QSAFE */ | |
| 445 | − 0x0000000d /* EMC_RDV */ | |
| 446 | − 0x0000000f /* EMC_RDV_MASK */ | |
| 447 | − 0x0000009a /* EMC_REFRESH */ | |
| 448 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 449 | − 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 450 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 451 | − 0x00000002 /* EMC_PDEX2RD */ | |
| 452 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 453 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 454 | − 0x00000007 /* EMC_AR2PDEN */ | |
| 455 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 456 | − 0x00000006 /* EMC_TXSR */ | |
| 457 | − 0x00000006 /* EMC_TXSRDLL */ | |
| 458 | − 0x00000004 /* EMC_TCKE */ | |
| 459 | − 0x00000005 /* EMC_TCKESR */ | |
| 460 | − 0x00000004 /* EMC_TPD */ | |
| 461 | − 0x00000000 /* EMC_TFAW */ | |
| 462 | − 0x00000000 /* EMC_TRPAB */ | |
| 463 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 464 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 465 | − 0x000000a0 /* EMC_TREFBW */ | |
| 466 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 467 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 468 | − 0x00000000 /* EMC_ODT_READ */ | |
| 469 | − 0x106aa298 /* EMC_FBIO_CFG5 */ | |
| 470 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 471 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 472 | − 0x00064000 /* EMC_DLL_XFORM_DQS0 */ | |
| 473 | − 0x00064000 /* EMC_DLL_XFORM_DQS1 */ | |
| 474 | − 0x00064000 /* EMC_DLL_XFORM_DQS2 */ | |
| 475 | − 0x00064000 /* EMC_DLL_XFORM_DQS3 */ | |
| 476 | − 0x00064000 /* EMC_DLL_XFORM_DQS4 */ | |
| 477 | − 0x00064000 /* EMC_DLL_XFORM_DQS5 */ | |
| 478 | − 0x00064000 /* EMC_DLL_XFORM_DQS6 */ | |
| 479 | − 0x00064000 /* EMC_DLL_XFORM_DQS7 */ | |
| 480 | − 0x00064000 /* EMC_DLL_XFORM_DQS8 */ | |
| 481 | − 0x00064000 /* EMC_DLL_XFORM_DQS9 */ | |
| 482 | − 0x00064000 /* EMC_DLL_XFORM_DQS10 */ | |
| 483 | − 0x00064000 /* EMC_DLL_XFORM_DQS11 */ | |
| 484 | − 0x00064000 /* EMC_DLL_XFORM_DQS12 */ | |
| 485 | − 0x00064000 /* EMC_DLL_XFORM_DQS13 */ | |
| 486 | − 0x00064000 /* EMC_DLL_XFORM_DQS14 */ | |
| 487 | − 0x00064000 /* EMC_DLL_XFORM_DQS15 */ | |
| 488 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 489 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 490 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 491 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 492 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 493 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 494 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 495 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 496 | − 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 497 | − 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 498 | − 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 499 | − 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 500 | − 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 501 | − 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 502 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 503 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 504 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 505 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 506 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 507 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 508 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 509 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 510 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 511 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 512 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 513 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 514 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 515 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 516 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 517 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 518 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 519 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 520 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 521 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 522 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 523 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 524 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 525 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 526 | − 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ | |
| 527 | − 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ | |
| 528 | − 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ | |
| 529 | − 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ | |
| 530 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ | |
| 531 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ | |
| 532 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ | |
| 533 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ | |
| 534 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 535 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 536 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 537 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 538 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 539 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 540 | − 0x00000303 /* EMC_XM2CLKPADCTRL2 */ | |
| 541 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 542 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 543 | − 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ | |
| 544 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 545 | − 0x51451400 /* EMC_XM2DQSPADCTRL3 */ | |
| 546 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 547 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 548 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 549 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 550 | − 0x0000000b /* EMC_TXDSRVTTGEN */ | |
| 551 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 552 | − 0x00000042 /* EMC_ZCAL_WAIT_CNT */ | |
| 553 | − 0x000c000c /* EMC_MRS_WAIT_CNT2 */ | |
| 554 | − 0x00000000 /* EMC_CTT */ | |
| 555 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 556 | − 0x0000f2f3 /* EMC_CFG_PIPE */ | |
| 557 | − 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ | |
| 558 | − 0x0000000a /* EMC_QPOP */ | |
| 559 | − >; | |
| 560 | − }; | |
| 561 | − | |
| 562 | − timing-40800000 { | |
| 563 | − clock-frequency = <40800000>; | |
| 564 | − | |
| 565 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 566 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 567 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 568 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 569 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 570 | − nvidia,emc-cfg = <0x73240000>; | |
| 571 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 572 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 573 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 574 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 575 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 576 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 577 | − nvidia,emc-mrs-wait-cnt = <0x000c000c>; | |
| 578 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 579 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 580 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 581 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 582 | − | |
| 583 | − nvidia,emc-configuration = < | |
| 584 | − 0x00000001 /* EMC_RC */ | |
| 585 | − 0x0000000a /* EMC_RFC */ | |
| 586 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 587 | − 0x00000001 /* EMC_RAS */ | |
| 588 | − 0x00000000 /* EMC_RP */ | |
| 589 | − 0x00000004 /* EMC_R2W */ | |
| 590 | − 0x0000000a /* EMC_W2R */ | |
| 591 | − 0x00000003 /* EMC_R2P */ | |
| 592 | − 0x0000000b /* EMC_W2P */ | |
| 593 | − 0x00000000 /* EMC_RD_RCD */ | |
| 594 | − 0x00000000 /* EMC_WR_RCD */ | |
| 595 | − 0x00000003 /* EMC_RRD */ | |
| 596 | − 0x00000003 /* EMC_REXT */ | |
| 597 | − 0x00000000 /* EMC_WEXT */ | |
| 598 | − 0x00000006 /* EMC_WDV */ | |
| 599 | − 0x00000006 /* EMC_WDV_MASK */ | |
| 600 | − 0x00000006 /* EMC_QUSE */ | |
| 601 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 602 | − 0x00000000 /* EMC_IBDLY */ | |
| 603 | − 0x00000005 /* EMC_EINPUT */ | |
| 604 | − 0x00000005 /* EMC_EINPUT_DURATION */ | |
| 605 | − 0x00010000 /* EMC_PUTERM_EXTRA */ | |
| 606 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 607 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 608 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 609 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 610 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 611 | − 0x00000004 /* EMC_QRST */ | |
| 612 | − 0x0000000c /* EMC_QSAFE */ | |
| 613 | − 0x0000000d /* EMC_RDV */ | |
| 614 | − 0x0000000f /* EMC_RDV_MASK */ | |
| 615 | − 0x00000134 /* EMC_REFRESH */ | |
| 616 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 617 | − 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 618 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 619 | − 0x00000002 /* EMC_PDEX2RD */ | |
| 620 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 621 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 622 | − 0x00000008 /* EMC_AR2PDEN */ | |
| 623 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 624 | − 0x0000000c /* EMC_TXSR */ | |
| 625 | − 0x0000000c /* EMC_TXSRDLL */ | |
| 626 | − 0x00000004 /* EMC_TCKE */ | |
| 627 | − 0x00000005 /* EMC_TCKESR */ | |
| 628 | − 0x00000004 /* EMC_TPD */ | |
| 629 | − 0x00000000 /* EMC_TFAW */ | |
| 630 | − 0x00000000 /* EMC_TRPAB */ | |
| 631 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 632 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 633 | − 0x0000013f /* EMC_TREFBW */ | |
| 634 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 635 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 636 | − 0x00000000 /* EMC_ODT_READ */ | |
| 637 | − 0x106aa298 /* EMC_FBIO_CFG5 */ | |
| 638 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 639 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 640 | − 0x00064000 /* EMC_DLL_XFORM_DQS0 */ | |
| 641 | − 0x00064000 /* EMC_DLL_XFORM_DQS1 */ | |
| 642 | − 0x00064000 /* EMC_DLL_XFORM_DQS2 */ | |
| 643 | − 0x00064000 /* EMC_DLL_XFORM_DQS3 */ | |
| 644 | − 0x00064000 /* EMC_DLL_XFORM_DQS4 */ | |
| 645 | − 0x00064000 /* EMC_DLL_XFORM_DQS5 */ | |
| 646 | − 0x00064000 /* EMC_DLL_XFORM_DQS6 */ | |
| 647 | − 0x00064000 /* EMC_DLL_XFORM_DQS7 */ | |
| 648 | − 0x00064000 /* EMC_DLL_XFORM_DQS8 */ | |
| 649 | − 0x00064000 /* EMC_DLL_XFORM_DQS9 */ | |
| 650 | − 0x00064000 /* EMC_DLL_XFORM_DQS10 */ | |
| 651 | − 0x00064000 /* EMC_DLL_XFORM_DQS11 */ | |
| 652 | − 0x00064000 /* EMC_DLL_XFORM_DQS12 */ | |
| 653 | − 0x00064000 /* EMC_DLL_XFORM_DQS13 */ | |
| 654 | − 0x00064000 /* EMC_DLL_XFORM_DQS14 */ | |
| 655 | − 0x00064000 /* EMC_DLL_XFORM_DQS15 */ | |
| 656 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 657 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 658 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 659 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 660 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 661 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 662 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 663 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 664 | − 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 665 | − 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 666 | − 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 667 | − 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 668 | − 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 669 | − 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 670 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 671 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 672 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 673 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 674 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 675 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 676 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 677 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 678 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 679 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 680 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 681 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 682 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 683 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 684 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 685 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 686 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 687 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 688 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 689 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 690 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 691 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 692 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 693 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 694 | − 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ | |
| 695 | − 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ | |
| 696 | − 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ | |
| 697 | − 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ | |
| 698 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ | |
| 699 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ | |
| 700 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ | |
| 701 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ | |
| 702 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 703 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 704 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 705 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 706 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 707 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 708 | − 0x00000303 /* EMC_XM2CLKPADCTRL2 */ | |
| 709 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 710 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 711 | − 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ | |
| 712 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 713 | − 0x51451400 /* EMC_XM2DQSPADCTRL3 */ | |
| 714 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 715 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 716 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 717 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 718 | − 0x00000015 /* EMC_TXDSRVTTGEN */ | |
| 719 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 720 | − 0x00000042 /* EMC_ZCAL_WAIT_CNT */ | |
| 721 | − 0x000c000c /* EMC_MRS_WAIT_CNT2 */ | |
| 722 | − 0x00000000 /* EMC_CTT */ | |
| 723 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 724 | − 0x0000f2f3 /* EMC_CFG_PIPE */ | |
| 725 | − 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ | |
| 726 | − 0x0000000a /* EMC_QPOP */ | |
| 727 | − >; | |
| 728 | − }; | |
| 729 | − | |
| 730 | − timing-68000000 { | |
| 731 | − clock-frequency = <68000000>; | |
| 732 | − | |
| 733 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 734 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 735 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 736 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 737 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 738 | − nvidia,emc-cfg = <0x73240000>; | |
| 739 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 740 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 741 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 742 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 743 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 744 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 745 | − nvidia,emc-mrs-wait-cnt = <0x000c000c>; | |
| 746 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 747 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 748 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 749 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 750 | − | |
| 751 | − nvidia,emc-configuration = < | |
| 752 | − 0x00000003 /* EMC_RC */ | |
| 753 | − 0x00000011 /* EMC_RFC */ | |
| 754 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 755 | − 0x00000002 /* EMC_RAS */ | |
| 756 | − 0x00000000 /* EMC_RP */ | |
| 757 | − 0x00000004 /* EMC_R2W */ | |
| 758 | − 0x0000000a /* EMC_W2R */ | |
| 759 | − 0x00000003 /* EMC_R2P */ | |
| 760 | − 0x0000000b /* EMC_W2P */ | |
| 761 | − 0x00000000 /* EMC_RD_RCD */ | |
| 762 | − 0x00000000 /* EMC_WR_RCD */ | |
| 763 | − 0x00000003 /* EMC_RRD */ | |
| 764 | − 0x00000003 /* EMC_REXT */ | |
| 765 | − 0x00000000 /* EMC_WEXT */ | |
| 766 | − 0x00000006 /* EMC_WDV */ | |
| 767 | − 0x00000006 /* EMC_WDV_MASK */ | |
| 768 | − 0x00000006 /* EMC_QUSE */ | |
| 769 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 770 | − 0x00000000 /* EMC_IBDLY */ | |
| 771 | − 0x00000005 /* EMC_EINPUT */ | |
| 772 | − 0x00000005 /* EMC_EINPUT_DURATION */ | |
| 773 | − 0x00010000 /* EMC_PUTERM_EXTRA */ | |
| 774 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 775 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 776 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 777 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 778 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 779 | − 0x00000004 /* EMC_QRST */ | |
| 780 | − 0x0000000c /* EMC_QSAFE */ | |
| 781 | − 0x0000000d /* EMC_RDV */ | |
| 782 | − 0x0000000f /* EMC_RDV_MASK */ | |
| 783 | − 0x00000202 /* EMC_REFRESH */ | |
| 784 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 785 | − 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 786 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 787 | − 0x00000002 /* EMC_PDEX2RD */ | |
| 788 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 789 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 790 | − 0x0000000f /* EMC_AR2PDEN */ | |
| 791 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 792 | − 0x00000013 /* EMC_TXSR */ | |
| 793 | − 0x00000013 /* EMC_TXSRDLL */ | |
| 794 | − 0x00000004 /* EMC_TCKE */ | |
| 795 | − 0x00000005 /* EMC_TCKESR */ | |
| 796 | − 0x00000004 /* EMC_TPD */ | |
| 797 | − 0x00000001 /* EMC_TFAW */ | |
| 798 | − 0x00000000 /* EMC_TRPAB */ | |
| 799 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 800 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 801 | − 0x00000213 /* EMC_TREFBW */ | |
| 802 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 803 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 804 | − 0x00000000 /* EMC_ODT_READ */ | |
| 805 | − 0x106aa298 /* EMC_FBIO_CFG5 */ | |
| 806 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 807 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 808 | − 0x00064000 /* EMC_DLL_XFORM_DQS0 */ | |
| 809 | − 0x00064000 /* EMC_DLL_XFORM_DQS1 */ | |
| 810 | − 0x00064000 /* EMC_DLL_XFORM_DQS2 */ | |
| 811 | − 0x00064000 /* EMC_DLL_XFORM_DQS3 */ | |
| 812 | − 0x00064000 /* EMC_DLL_XFORM_DQS4 */ | |
| 813 | − 0x00064000 /* EMC_DLL_XFORM_DQS5 */ | |
| 814 | − 0x00064000 /* EMC_DLL_XFORM_DQS6 */ | |
| 815 | − 0x00064000 /* EMC_DLL_XFORM_DQS7 */ | |
| 816 | − 0x00064000 /* EMC_DLL_XFORM_DQS8 */ | |
| 817 | − 0x00064000 /* EMC_DLL_XFORM_DQS9 */ | |
| 818 | − 0x00064000 /* EMC_DLL_XFORM_DQS10 */ | |
| 819 | − 0x00064000 /* EMC_DLL_XFORM_DQS11 */ | |
| 820 | − 0x00064000 /* EMC_DLL_XFORM_DQS12 */ | |
| 821 | − 0x00064000 /* EMC_DLL_XFORM_DQS13 */ | |
| 822 | − 0x00064000 /* EMC_DLL_XFORM_DQS14 */ | |
| 823 | − 0x00064000 /* EMC_DLL_XFORM_DQS15 */ | |
| 824 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 825 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 826 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 827 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 828 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 829 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 830 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 831 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 832 | − 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 833 | − 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 834 | − 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 835 | − 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 836 | − 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 837 | − 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 838 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 839 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 840 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 841 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 842 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 843 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 844 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 845 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 846 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 847 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 848 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 849 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 850 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 851 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 852 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 853 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 854 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 855 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 856 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 857 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 858 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 859 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 860 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 861 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 862 | − 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ | |
| 863 | − 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ | |
| 864 | − 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ | |
| 865 | − 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ | |
| 866 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ | |
| 867 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ | |
| 868 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ | |
| 869 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ | |
| 870 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 871 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 872 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 873 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 874 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 875 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 876 | − 0x00000303 /* EMC_XM2CLKPADCTRL2 */ | |
| 877 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 878 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 879 | − 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ | |
| 880 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 881 | − 0x51451400 /* EMC_XM2DQSPADCTRL3 */ | |
| 882 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 883 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 884 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 885 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 886 | − 0x00000022 /* EMC_TXDSRVTTGEN */ | |
| 887 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 888 | − 0x00000042 /* EMC_ZCAL_WAIT_CNT */ | |
| 889 | − 0x000c000c /* EMC_MRS_WAIT_CNT2 */ | |
| 890 | − 0x00000000 /* EMC_CTT */ | |
| 891 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 892 | − 0x0000f2f3 /* EMC_CFG_PIPE */ | |
| 893 | − 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ | |
| 894 | − 0x0000000a /* EMC_QPOP */ | |
| 895 | − >; | |
| 896 | − }; | |
| 897 | − | |
| 898 | − timing-102000000 { | |
| 899 | − clock-frequency = <102000000>; | |
| 900 | − | |
| 901 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 902 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 903 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 904 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 905 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 906 | − nvidia,emc-cfg = <0x73240000>; | |
| 907 | − nvidia,emc-cfg-2 = <0x000008c5>; | |
| 908 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 909 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 910 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 911 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 912 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 913 | − nvidia,emc-mrs-wait-cnt = <0x000c000c>; | |
| 914 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 915 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 916 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 917 | − nvidia,emc-zcal-interval = <0x00000000>; | |
| 918 | − | |
| 919 | − nvidia,emc-configuration = < | |
| 920 | − 0x00000004 /* EMC_RC */ | |
| 921 | − 0x0000001a /* EMC_RFC */ | |
| 922 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 923 | − 0x00000003 /* EMC_RAS */ | |
| 924 | − 0x00000001 /* EMC_RP */ | |
| 925 | − 0x00000004 /* EMC_R2W */ | |
| 926 | − 0x0000000a /* EMC_W2R */ | |
| 927 | − 0x00000003 /* EMC_R2P */ | |
| 928 | − 0x0000000b /* EMC_W2P */ | |
| 929 | − 0x00000001 /* EMC_RD_RCD */ | |
| 930 | − 0x00000001 /* EMC_WR_RCD */ | |
| 931 | − 0x00000003 /* EMC_RRD */ | |
| 932 | − 0x00000003 /* EMC_REXT */ | |
| 933 | − 0x00000000 /* EMC_WEXT */ | |
| 934 | − 0x00000006 /* EMC_WDV */ | |
| 935 | − 0x00000006 /* EMC_WDV_MASK */ | |
| 936 | − 0x00000006 /* EMC_QUSE */ | |
| 937 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 938 | − 0x00000000 /* EMC_IBDLY */ | |
| 939 | − 0x00000005 /* EMC_EINPUT */ | |
| 940 | − 0x00000005 /* EMC_EINPUT_DURATION */ | |
| 941 | − 0x00010000 /* EMC_PUTERM_EXTRA */ | |
| 942 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 943 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 944 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 945 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 946 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 947 | − 0x00000004 /* EMC_QRST */ | |
| 948 | − 0x0000000c /* EMC_QSAFE */ | |
| 949 | − 0x0000000d /* EMC_RDV */ | |
| 950 | − 0x0000000f /* EMC_RDV_MASK */ | |
| 951 | − 0x00000304 /* EMC_REFRESH */ | |
| 952 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 953 | − 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 954 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 955 | − 0x00000002 /* EMC_PDEX2RD */ | |
| 956 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 957 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 958 | − 0x00000018 /* EMC_AR2PDEN */ | |
| 959 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 960 | − 0x0000001c /* EMC_TXSR */ | |
| 961 | − 0x0000001c /* EMC_TXSRDLL */ | |
| 962 | − 0x00000004 /* EMC_TCKE */ | |
| 963 | − 0x00000005 /* EMC_TCKESR */ | |
| 964 | − 0x00000004 /* EMC_TPD */ | |
| 965 | − 0x00000003 /* EMC_TFAW */ | |
| 966 | − 0x00000000 /* EMC_TRPAB */ | |
| 967 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 968 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 969 | − 0x0000031c /* EMC_TREFBW */ | |
| 970 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 971 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 972 | − 0x00000000 /* EMC_ODT_READ */ | |
| 973 | − 0x106aa298 /* EMC_FBIO_CFG5 */ | |
| 974 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 975 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 976 | − 0x00064000 /* EMC_DLL_XFORM_DQS0 */ | |
| 977 | − 0x00064000 /* EMC_DLL_XFORM_DQS1 */ | |
| 978 | − 0x00064000 /* EMC_DLL_XFORM_DQS2 */ | |
| 979 | − 0x00064000 /* EMC_DLL_XFORM_DQS3 */ | |
| 980 | − 0x00064000 /* EMC_DLL_XFORM_DQS4 */ | |
| 981 | − 0x00064000 /* EMC_DLL_XFORM_DQS5 */ | |
| 982 | − 0x00064000 /* EMC_DLL_XFORM_DQS6 */ | |
| 983 | − 0x00064000 /* EMC_DLL_XFORM_DQS7 */ | |
| 984 | − 0x00064000 /* EMC_DLL_XFORM_DQS8 */ | |
| 985 | − 0x00064000 /* EMC_DLL_XFORM_DQS9 */ | |
| 986 | − 0x00064000 /* EMC_DLL_XFORM_DQS10 */ | |
| 987 | − 0x00064000 /* EMC_DLL_XFORM_DQS11 */ | |
| 988 | − 0x00064000 /* EMC_DLL_XFORM_DQS12 */ | |
| 989 | − 0x00064000 /* EMC_DLL_XFORM_DQS13 */ | |
| 990 | − 0x00064000 /* EMC_DLL_XFORM_DQS14 */ | |
| 991 | − 0x00064000 /* EMC_DLL_XFORM_DQS15 */ | |
| 992 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 993 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 994 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 995 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 996 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 997 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 998 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 999 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 1000 | − 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 1001 | − 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 1002 | − 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 1003 | − 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 1004 | − 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 1005 | − 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 1006 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 1007 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 1008 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 1009 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 1010 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 1011 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 1012 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 1013 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 1014 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 1015 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 1016 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 1017 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 1018 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 1019 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 1020 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 1021 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 1022 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 1023 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 1024 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 1025 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 1026 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 1027 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 1028 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 1029 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 1030 | − 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ | |
| 1031 | − 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ | |
| 1032 | − 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ | |
| 1033 | − 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ | |
| 1034 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ | |
| 1035 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ | |
| 1036 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ | |
| 1037 | − 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ | |
| 1038 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 1039 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 1040 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 1041 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 1042 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 1043 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 1044 | − 0x00000303 /* EMC_XM2CLKPADCTRL2 */ | |
| 1045 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 1046 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 1047 | − 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ | |
| 1048 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 1049 | − 0x51451400 /* EMC_XM2DQSPADCTRL3 */ | |
| 1050 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 1051 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 1052 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 1053 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 1054 | − 0x00000033 /* EMC_TXDSRVTTGEN */ | |
| 1055 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 1056 | − 0x00000042 /* EMC_ZCAL_WAIT_CNT */ | |
| 1057 | − 0x000c000c /* EMC_MRS_WAIT_CNT2 */ | |
| 1058 | − 0x00000000 /* EMC_CTT */ | |
| 1059 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 1060 | − 0x0000f2f3 /* EMC_CFG_PIPE */ | |
| 1061 | − 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ | |
| 1062 | − 0x0000000a /* EMC_QPOP */ | |
| 1063 | − >; | |
| 1064 | − }; | |
| 1065 | − | |
| 1066 | − timing-204000000 { | |
| 1067 | − clock-frequency = <204000000>; | |
| 1068 | − | |
| 1069 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1070 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 1071 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 1072 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 1073 | − nvidia,emc-bgbias-ctl0 = <0x00000008>; | |
| 1074 | − nvidia,emc-cfg = <0x73240000>; | |
| 1075 | − nvidia,emc-cfg-2 = <0x0000088d>; | |
| 1076 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 1077 | − nvidia,emc-mode-1 = <0x80100003>; | |
| 1078 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 1079 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 1080 | − nvidia,emc-mode-reset = <0x80001221>; | |
| 1081 | − nvidia,emc-mrs-wait-cnt = <0x000c000c>; | |
| 1082 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1083 | − nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; | |
| 1084 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1085 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 1086 | − | |
| 1087 | − nvidia,emc-configuration = < | |
| 1088 | − 0x00000009 /* EMC_RC */ | |
| 1089 | − 0x00000035 /* EMC_RFC */ | |
| 1090 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 1091 | − 0x00000007 /* EMC_RAS */ | |
| 1092 | − 0x00000002 /* EMC_RP */ | |
| 1093 | − 0x00000005 /* EMC_R2W */ | |
| 1094 | − 0x0000000a /* EMC_W2R */ | |
| 1095 | − 0x00000003 /* EMC_R2P */ | |
| 1096 | − 0x0000000b /* EMC_W2P */ | |
| 1097 | − 0x00000002 /* EMC_RD_RCD */ | |
| 1098 | − 0x00000002 /* EMC_WR_RCD */ | |
| 1099 | − 0x00000003 /* EMC_RRD */ | |
| 1100 | − 0x00000003 /* EMC_REXT */ | |
| 1101 | − 0x00000000 /* EMC_WEXT */ | |
| 1102 | − 0x00000005 /* EMC_WDV */ | |
| 1103 | − 0x00000005 /* EMC_WDV_MASK */ | |
| 1104 | − 0x00000006 /* EMC_QUSE */ | |
| 1105 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 1106 | − 0x00000000 /* EMC_IBDLY */ | |
| 1107 | − 0x00000004 /* EMC_EINPUT */ | |
| 1108 | − 0x00000006 /* EMC_EINPUT_DURATION */ | |
| 1109 | − 0x00010000 /* EMC_PUTERM_EXTRA */ | |
| 1110 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 1111 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 1112 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 1113 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 1114 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 1115 | − 0x00000003 /* EMC_QRST */ | |
| 1116 | − 0x0000000d /* EMC_QSAFE */ | |
| 1117 | − 0x0000000f /* EMC_RDV */ | |
| 1118 | − 0x00000011 /* EMC_RDV_MASK */ | |
| 1119 | − 0x00000607 /* EMC_REFRESH */ | |
| 1120 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 1121 | − 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 1122 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 1123 | − 0x00000002 /* EMC_PDEX2RD */ | |
| 1124 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 1125 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 1126 | − 0x00000032 /* EMC_AR2PDEN */ | |
| 1127 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 1128 | − 0x00000038 /* EMC_TXSR */ | |
| 1129 | − 0x00000038 /* EMC_TXSRDLL */ | |
| 1130 | − 0x00000004 /* EMC_TCKE */ | |
| 1131 | − 0x00000005 /* EMC_TCKESR */ | |
| 1132 | − 0x00000004 /* EMC_TPD */ | |
| 1133 | − 0x00000007 /* EMC_TFAW */ | |
| 1134 | − 0x00000000 /* EMC_TRPAB */ | |
| 1135 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 1136 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 1137 | − 0x00000638 /* EMC_TREFBW */ | |
| 1138 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 1139 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 1140 | − 0x00000000 /* EMC_ODT_READ */ | |
| 1141 | − 0x106aa298 /* EMC_FBIO_CFG5 */ | |
| 1142 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 1143 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 1144 | − 0x00064000 /* EMC_DLL_XFORM_DQS0 */ | |
| 1145 | − 0x00064000 /* EMC_DLL_XFORM_DQS1 */ | |
| 1146 | − 0x00064000 /* EMC_DLL_XFORM_DQS2 */ | |
| 1147 | − 0x00064000 /* EMC_DLL_XFORM_DQS3 */ | |
| 1148 | − 0x00064000 /* EMC_DLL_XFORM_DQS4 */ | |
| 1149 | − 0x00064000 /* EMC_DLL_XFORM_DQS5 */ | |
| 1150 | − 0x00064000 /* EMC_DLL_XFORM_DQS6 */ | |
| 1151 | − 0x00064000 /* EMC_DLL_XFORM_DQS7 */ | |
| 1152 | − 0x00064000 /* EMC_DLL_XFORM_DQS8 */ | |
| 1153 | − 0x00064000 /* EMC_DLL_XFORM_DQS9 */ | |
| 1154 | − 0x00064000 /* EMC_DLL_XFORM_DQS10 */ | |
| 1155 | − 0x00064000 /* EMC_DLL_XFORM_DQS11 */ | |
| 1156 | − 0x00064000 /* EMC_DLL_XFORM_DQS12 */ | |
| 1157 | − 0x00064000 /* EMC_DLL_XFORM_DQS13 */ | |
| 1158 | − 0x00064000 /* EMC_DLL_XFORM_DQS14 */ | |
| 1159 | − 0x00064000 /* EMC_DLL_XFORM_DQS15 */ | |
| 1160 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 1161 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 1162 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 1163 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 1164 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 1165 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 1166 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 1167 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 1168 | − 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 1169 | − 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 1170 | − 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 1171 | − 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 1172 | − 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 1173 | − 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 1174 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 1175 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 1176 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 1177 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 1178 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 1179 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 1180 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 1181 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 1182 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 1183 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 1184 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 1185 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 1186 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 1187 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 1188 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 1189 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 1190 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 1191 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 1192 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 1193 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 1194 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 1195 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 1196 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 1197 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 1198 | − 0x00090000 /* EMC_DLL_XFORM_DQ0 */ | |
| 1199 | − 0x00090000 /* EMC_DLL_XFORM_DQ1 */ | |
| 1200 | − 0x00094000 /* EMC_DLL_XFORM_DQ2 */ | |
| 1201 | − 0x00094000 /* EMC_DLL_XFORM_DQ3 */ | |
| 1202 | − 0x00009400 /* EMC_DLL_XFORM_DQ4 */ | |
| 1203 | − 0x00009000 /* EMC_DLL_XFORM_DQ5 */ | |
| 1204 | − 0x00009000 /* EMC_DLL_XFORM_DQ6 */ | |
| 1205 | − 0x00009000 /* EMC_DLL_XFORM_DQ7 */ | |
| 1206 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 1207 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 1208 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 1209 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 1210 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 1211 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 1212 | − 0x00000303 /* EMC_XM2CLKPADCTRL2 */ | |
| 1213 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 1214 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 1215 | − 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ | |
| 1216 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 1217 | − 0x51451400 /* EMC_XM2DQSPADCTRL3 */ | |
| 1218 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 1219 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 1220 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 1221 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 1222 | − 0x00000066 /* EMC_TXDSRVTTGEN */ | |
| 1223 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 1224 | − 0x00000100 /* EMC_ZCAL_WAIT_CNT */ | |
| 1225 | − 0x000c000c /* EMC_MRS_WAIT_CNT2 */ | |
| 1226 | − 0x00000000 /* EMC_CTT */ | |
| 1227 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 1228 | − 0x0000d2b3 /* EMC_CFG_PIPE */ | |
| 1229 | − 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ | |
| 1230 | − 0x0000000a /* EMC_QPOP */ | |
| 1231 | − >; | |
| 1232 | − }; | |
| 1233 | − | |
| 1234 | − timing-300000000 { | |
| 1235 | − clock-frequency = <300000000>; | |
| 1236 | − | |
| 1237 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1238 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 1239 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 1240 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 1241 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1242 | − nvidia,emc-cfg = <0x73340000>; | |
| 1243 | − nvidia,emc-cfg-2 = <0x000008d5>; | |
| 1244 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 1245 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1246 | − nvidia,emc-mode-2 = <0x80200000>; | |
| 1247 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 1248 | − nvidia,emc-mode-reset = <0x80000321>; | |
| 1249 | − nvidia,emc-mrs-wait-cnt = <0x0174000c>; | |
| 1250 | − nvidia,emc-sel-dpd-ctrl = <0x00040128>; | |
| 1251 | − nvidia,emc-xm2dqspadctrl2 = <0x01231339>; | |
| 1252 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1253 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 1254 | − | |
| 1255 | − nvidia,emc-configuration = < | |
| 1256 | − 0x0000000d /* EMC_RC */ | |
| 1257 | − 0x0000004c /* EMC_RFC */ | |
| 1258 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 1259 | − 0x00000009 /* EMC_RAS */ | |
| 1260 | − 0x00000003 /* EMC_RP */ | |
| 1261 | − 0x00000004 /* EMC_R2W */ | |
| 1262 | − 0x00000008 /* EMC_W2R */ | |
| 1263 | − 0x00000002 /* EMC_R2P */ | |
| 1264 | − 0x00000009 /* EMC_W2P */ | |
| 1265 | − 0x00000003 /* EMC_RD_RCD */ | |
| 1266 | − 0x00000003 /* EMC_WR_RCD */ | |
| 1267 | − 0x00000002 /* EMC_RRD */ | |
| 1268 | − 0x00000002 /* EMC_REXT */ | |
| 1269 | − 0x00000000 /* EMC_WEXT */ | |
| 1270 | − 0x00000003 /* EMC_WDV */ | |
| 1271 | − 0x00000003 /* EMC_WDV_MASK */ | |
| 1272 | − 0x00000005 /* EMC_QUSE */ | |
| 1273 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 1274 | − 0x00000000 /* EMC_IBDLY */ | |
| 1275 | − 0x00000002 /* EMC_EINPUT */ | |
| 1276 | − 0x00000007 /* EMC_EINPUT_DURATION */ | |
| 1277 | − 0x00020000 /* EMC_PUTERM_EXTRA */ | |
| 1278 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 1279 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 1280 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 1281 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 1282 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 1283 | − 0x00000001 /* EMC_QRST */ | |
| 1284 | − 0x0000000e /* EMC_QSAFE */ | |
| 1285 | − 0x00000010 /* EMC_RDV */ | |
| 1286 | − 0x00000012 /* EMC_RDV_MASK */ | |
| 1287 | − 0x000008e4 /* EMC_REFRESH */ | |
| 1288 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 1289 | − 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 1290 | − 0x00000001 /* EMC_PDEX2WR */ | |
| 1291 | − 0x00000008 /* EMC_PDEX2RD */ | |
| 1292 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 1293 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 1294 | − 0x0000004a /* EMC_AR2PDEN */ | |
| 1295 | − 0x0000000e /* EMC_RW2PDEN */ | |
| 1296 | − 0x00000051 /* EMC_TXSR */ | |
| 1297 | − 0x00000200 /* EMC_TXSRDLL */ | |
| 1298 | − 0x00000004 /* EMC_TCKE */ | |
| 1299 | − 0x00000005 /* EMC_TCKESR */ | |
| 1300 | − 0x00000004 /* EMC_TPD */ | |
| 1301 | − 0x00000009 /* EMC_TFAW */ | |
| 1302 | − 0x00000000 /* EMC_TRPAB */ | |
| 1303 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 1304 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 1305 | − 0x00000924 /* EMC_TREFBW */ | |
| 1306 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 1307 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 1308 | − 0x00000000 /* EMC_ODT_READ */ | |
| 1309 | − 0x104ab098 /* EMC_FBIO_CFG5 */ | |
| 1310 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 1311 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 1312 | − 0x00030000 /* EMC_DLL_XFORM_DQS0 */ | |
| 1313 | − 0x00030000 /* EMC_DLL_XFORM_DQS1 */ | |
| 1314 | − 0x00030000 /* EMC_DLL_XFORM_DQS2 */ | |
| 1315 | − 0x00030000 /* EMC_DLL_XFORM_DQS3 */ | |
| 1316 | − 0x00030000 /* EMC_DLL_XFORM_DQS4 */ | |
| 1317 | − 0x00030000 /* EMC_DLL_XFORM_DQS5 */ | |
| 1318 | − 0x00030000 /* EMC_DLL_XFORM_DQS6 */ | |
| 1319 | − 0x00030000 /* EMC_DLL_XFORM_DQS7 */ | |
| 1320 | − 0x00030000 /* EMC_DLL_XFORM_DQS8 */ | |
| 1321 | − 0x00030000 /* EMC_DLL_XFORM_DQS9 */ | |
| 1322 | − 0x00030000 /* EMC_DLL_XFORM_DQS10 */ | |
| 1323 | − 0x00030000 /* EMC_DLL_XFORM_DQS11 */ | |
| 1324 | − 0x00030000 /* EMC_DLL_XFORM_DQS12 */ | |
| 1325 | − 0x00030000 /* EMC_DLL_XFORM_DQS13 */ | |
| 1326 | − 0x00030000 /* EMC_DLL_XFORM_DQS14 */ | |
| 1327 | − 0x00030000 /* EMC_DLL_XFORM_DQS15 */ | |
| 1328 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 1329 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 1330 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 1331 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 1332 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 1333 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 1334 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 1335 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 1336 | − 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 1337 | − 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 1338 | − 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 1339 | − 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 1340 | − 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 1341 | − 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 1342 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 1343 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 1344 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 1345 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 1346 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 1347 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 1348 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 1349 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 1350 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 1351 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 1352 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 1353 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 1354 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 1355 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 1356 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 1357 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 1358 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 1359 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 1360 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 1361 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 1362 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 1363 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 1364 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 1365 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 1366 | − 0x00060000 /* EMC_DLL_XFORM_DQ0 */ | |
| 1367 | − 0x00060000 /* EMC_DLL_XFORM_DQ1 */ | |
| 1368 | − 0x00060000 /* EMC_DLL_XFORM_DQ2 */ | |
| 1369 | − 0x00060000 /* EMC_DLL_XFORM_DQ3 */ | |
| 1370 | − 0x00006000 /* EMC_DLL_XFORM_DQ4 */ | |
| 1371 | − 0x00006000 /* EMC_DLL_XFORM_DQ5 */ | |
| 1372 | − 0x00006000 /* EMC_DLL_XFORM_DQ6 */ | |
| 1373 | − 0x00006000 /* EMC_DLL_XFORM_DQ7 */ | |
| 1374 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 1375 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 1376 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 1377 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 1378 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 1379 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 1380 | − 0x00000101 /* EMC_XM2CLKPADCTRL2 */ | |
| 1381 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 1382 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 1383 | − 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ | |
| 1384 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 1385 | − 0x51451420 /* EMC_XM2DQSPADCTRL3 */ | |
| 1386 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 1387 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 1388 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 1389 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 1390 | − 0x00000096 /* EMC_TXDSRVTTGEN */ | |
| 1391 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 1392 | − 0x00000100 /* EMC_ZCAL_WAIT_CNT */ | |
| 1393 | − 0x0174000c /* EMC_MRS_WAIT_CNT2 */ | |
| 1394 | − 0x00000000 /* EMC_CTT */ | |
| 1395 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 1396 | − 0x000052a3 /* EMC_CFG_PIPE */ | |
| 1397 | − 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ | |
| 1398 | − 0x00000009 /* EMC_QPOP */ | |
| 1399 | − >; | |
| 1400 | − }; | |
| 1401 | − | |
| 1402 | − timing-396000000 { | |
| 1403 | − clock-frequency = <396000000>; | |
| 1404 | − | |
| 1405 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1406 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 1407 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 1408 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 1409 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1410 | − nvidia,emc-cfg = <0x73340000>; | |
| 1411 | − nvidia,emc-cfg-2 = <0x00000895>; | |
| 1412 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 1413 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1414 | − nvidia,emc-mode-2 = <0x80200000>; | |
| 1415 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 1416 | − nvidia,emc-mode-reset = <0x80000521>; | |
| 1417 | − nvidia,emc-mrs-wait-cnt = <0x015b000c>; | |
| 1418 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1419 | − nvidia,emc-xm2dqspadctrl2 = <0x01231339>; | |
| 1420 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1421 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 1422 | − | |
| 1423 | − nvidia,emc-configuration = < | |
| 1424 | − 0x00000012 /* EMC_RC */ | |
| 1425 | − 0x00000065 /* EMC_RFC */ | |
| 1426 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 1427 | − 0x0000000c /* EMC_RAS */ | |
| 1428 | − 0x00000004 /* EMC_RP */ | |
| 1429 | − 0x00000005 /* EMC_R2W */ | |
| 1430 | − 0x00000008 /* EMC_W2R */ | |
| 1431 | − 0x00000002 /* EMC_R2P */ | |
| 1432 | − 0x0000000a /* EMC_W2P */ | |
| 1433 | − 0x00000004 /* EMC_RD_RCD */ | |
| 1434 | − 0x00000004 /* EMC_WR_RCD */ | |
| 1435 | − 0x00000002 /* EMC_RRD */ | |
| 1436 | − 0x00000002 /* EMC_REXT */ | |
| 1437 | − 0x00000000 /* EMC_WEXT */ | |
| 1438 | − 0x00000003 /* EMC_WDV */ | |
| 1439 | − 0x00000003 /* EMC_WDV_MASK */ | |
| 1440 | − 0x00000005 /* EMC_QUSE */ | |
| 1441 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 1442 | − 0x00000000 /* EMC_IBDLY */ | |
| 1443 | − 0x00000001 /* EMC_EINPUT */ | |
| 1444 | − 0x00000008 /* EMC_EINPUT_DURATION */ | |
| 1445 | − 0x00020000 /* EMC_PUTERM_EXTRA */ | |
| 1446 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 1447 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 1448 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 1449 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 1450 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 1451 | − 0x00000000 /* EMC_QRST */ | |
| 1452 | − 0x0000000f /* EMC_QSAFE */ | |
| 1453 | − 0x00000010 /* EMC_RDV */ | |
| 1454 | − 0x00000012 /* EMC_RDV_MASK */ | |
| 1455 | − 0x00000bd1 /* EMC_REFRESH */ | |
| 1456 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 1457 | − 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 1458 | − 0x00000001 /* EMC_PDEX2WR */ | |
| 1459 | − 0x00000008 /* EMC_PDEX2RD */ | |
| 1460 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 1461 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 1462 | − 0x00000063 /* EMC_AR2PDEN */ | |
| 1463 | − 0x0000000f /* EMC_RW2PDEN */ | |
| 1464 | − 0x0000006b /* EMC_TXSR */ | |
| 1465 | − 0x00000200 /* EMC_TXSRDLL */ | |
| 1466 | − 0x00000004 /* EMC_TCKE */ | |
| 1467 | − 0x00000005 /* EMC_TCKESR */ | |
| 1468 | − 0x00000004 /* EMC_TPD */ | |
| 1469 | − 0x0000000d /* EMC_TFAW */ | |
| 1470 | − 0x00000000 /* EMC_TRPAB */ | |
| 1471 | − 0x00000005 /* EMC_TCLKSTABLE */ | |
| 1472 | − 0x00000005 /* EMC_TCLKSTOP */ | |
| 1473 | − 0x00000c11 /* EMC_TREFBW */ | |
| 1474 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 1475 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 1476 | − 0x00000000 /* EMC_ODT_READ */ | |
| 1477 | − 0x104ab098 /* EMC_FBIO_CFG5 */ | |
| 1478 | − 0x002c00a0 /* EMC_CFG_DIG_DLL */ | |
| 1479 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 1480 | − 0x00030000 /* EMC_DLL_XFORM_DQS0 */ | |
| 1481 | − 0x00030000 /* EMC_DLL_XFORM_DQS1 */ | |
| 1482 | − 0x00030000 /* EMC_DLL_XFORM_DQS2 */ | |
| 1483 | − 0x00030000 /* EMC_DLL_XFORM_DQS3 */ | |
| 1484 | − 0x00030000 /* EMC_DLL_XFORM_DQS4 */ | |
| 1485 | − 0x00030000 /* EMC_DLL_XFORM_DQS5 */ | |
| 1486 | − 0x00030000 /* EMC_DLL_XFORM_DQS6 */ | |
| 1487 | − 0x00030000 /* EMC_DLL_XFORM_DQS7 */ | |
| 1488 | − 0x00030000 /* EMC_DLL_XFORM_DQS8 */ | |
| 1489 | − 0x00030000 /* EMC_DLL_XFORM_DQS9 */ | |
| 1490 | − 0x00030000 /* EMC_DLL_XFORM_DQS10 */ | |
| 1491 | − 0x00030000 /* EMC_DLL_XFORM_DQS11 */ | |
| 1492 | − 0x00030000 /* EMC_DLL_XFORM_DQS12 */ | |
| 1493 | − 0x00030000 /* EMC_DLL_XFORM_DQS13 */ | |
| 1494 | − 0x00030000 /* EMC_DLL_XFORM_DQS14 */ | |
| 1495 | − 0x00030000 /* EMC_DLL_XFORM_DQS15 */ | |
| 1496 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 1497 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 1498 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 1499 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 1500 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 1501 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 1502 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 1503 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 1504 | − 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 1505 | − 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 1506 | − 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 1507 | − 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 1508 | − 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 1509 | − 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 1510 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 1511 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 1512 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 1513 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 1514 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 1515 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 1516 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 1517 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 1518 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 1519 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 1520 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 1521 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 1522 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 1523 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 1524 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 1525 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 1526 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 1527 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 1528 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 1529 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 1530 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 1531 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 1532 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 1533 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 1534 | − 0x00048000 /* EMC_DLL_XFORM_DQ0 */ | |
| 1535 | − 0x00048000 /* EMC_DLL_XFORM_DQ1 */ | |
| 1536 | − 0x00048000 /* EMC_DLL_XFORM_DQ2 */ | |
| 1537 | − 0x00048000 /* EMC_DLL_XFORM_DQ3 */ | |
| 1538 | − 0x00004800 /* EMC_DLL_XFORM_DQ4 */ | |
| 1539 | − 0x00004800 /* EMC_DLL_XFORM_DQ5 */ | |
| 1540 | − 0x00004800 /* EMC_DLL_XFORM_DQ6 */ | |
| 1541 | − 0x00004800 /* EMC_DLL_XFORM_DQ7 */ | |
| 1542 | − 0x10000280 /* EMC_XM2CMDPADCTRL */ | |
| 1543 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 1544 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 1545 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 1546 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 1547 | − 0x77ffc081 /* EMC_XM2CLKPADCTRL */ | |
| 1548 | − 0x00000101 /* EMC_XM2CLKPADCTRL2 */ | |
| 1549 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 1550 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 1551 | − 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ | |
| 1552 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 1553 | − 0x51451420 /* EMC_XM2DQSPADCTRL3 */ | |
| 1554 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 1555 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 1556 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 1557 | − 0x0000003f /* EMC_DSR_VTTGEN_DRV */ | |
| 1558 | − 0x000000c6 /* EMC_TXDSRVTTGEN */ | |
| 1559 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 1560 | − 0x00000100 /* EMC_ZCAL_WAIT_CNT */ | |
| 1561 | − 0x015b000c /* EMC_MRS_WAIT_CNT2 */ | |
| 1562 | − 0x00000000 /* EMC_CTT */ | |
| 1563 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 1564 | − 0x000052a3 /* EMC_CFG_PIPE */ | |
| 1565 | − 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ | |
| 1566 | − 0x00000009 /* EMC_QPOP */ | |
| 1567 | − >; | |
| 1568 | − }; | |
| 1569 | − | |
| 1570 | − timing-528000000 { | |
| 1571 | − clock-frequency = <528000000>; | |
| 1572 | − | |
| 1573 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1574 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 1575 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 1576 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 1577 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1578 | − nvidia,emc-cfg = <0x73300000>; | |
| 1579 | − nvidia,emc-cfg-2 = <0x0000089d>; | |
| 1580 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 1581 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1582 | − nvidia,emc-mode-2 = <0x80200008>; | |
| 1583 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 1584 | − nvidia,emc-mode-reset = <0x80000941>; | |
| 1585 | − nvidia,emc-mrs-wait-cnt = <0x013a000c>; | |
| 1586 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1587 | − nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; | |
| 1588 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1589 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 1590 | − | |
| 1591 | − nvidia,emc-configuration = < | |
| 1592 | − 0x00000018 /* EMC_RC */ | |
| 1593 | − 0x00000088 /* EMC_RFC */ | |
| 1594 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 1595 | − 0x00000011 /* EMC_RAS */ | |
| 1596 | − 0x00000006 /* EMC_RP */ | |
| 1597 | − 0x00000006 /* EMC_R2W */ | |
| 1598 | − 0x00000009 /* EMC_W2R */ | |
| 1599 | − 0x00000002 /* EMC_R2P */ | |
| 1600 | − 0x0000000d /* EMC_W2P */ | |
| 1601 | − 0x00000006 /* EMC_RD_RCD */ | |
| 1602 | − 0x00000006 /* EMC_WR_RCD */ | |
| 1603 | − 0x00000002 /* EMC_RRD */ | |
| 1604 | − 0x00000002 /* EMC_REXT */ | |
| 1605 | − 0x00000000 /* EMC_WEXT */ | |
| 1606 | − 0x00000003 /* EMC_WDV */ | |
| 1607 | − 0x00000003 /* EMC_WDV_MASK */ | |
| 1608 | − 0x00000007 /* EMC_QUSE */ | |
| 1609 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 1610 | − 0x00000000 /* EMC_IBDLY */ | |
| 1611 | − 0x00000002 /* EMC_EINPUT */ | |
| 1612 | − 0x00000009 /* EMC_EINPUT_DURATION */ | |
| 1613 | − 0x00040000 /* EMC_PUTERM_EXTRA */ | |
| 1614 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 1615 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 1616 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 1617 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 1618 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 1619 | − 0x00000001 /* EMC_QRST */ | |
| 1620 | − 0x00000010 /* EMC_QSAFE */ | |
| 1621 | − 0x00000013 /* EMC_RDV */ | |
| 1622 | − 0x00000015 /* EMC_RDV_MASK */ | |
| 1623 | − 0x00000fd6 /* EMC_REFRESH */ | |
| 1624 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 1625 | − 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 1626 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 1627 | − 0x0000000b /* EMC_PDEX2RD */ | |
| 1628 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 1629 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 1630 | − 0x00000084 /* EMC_AR2PDEN */ | |
| 1631 | − 0x00000012 /* EMC_RW2PDEN */ | |
| 1632 | − 0x0000008f /* EMC_TXSR */ | |
| 1633 | − 0x00000200 /* EMC_TXSRDLL */ | |
| 1634 | − 0x00000004 /* EMC_TCKE */ | |
| 1635 | − 0x00000005 /* EMC_TCKESR */ | |
| 1636 | − 0x00000004 /* EMC_TPD */ | |
| 1637 | − 0x00000013 /* EMC_TFAW */ | |
| 1638 | − 0x00000000 /* EMC_TRPAB */ | |
| 1639 | − 0x00000006 /* EMC_TCLKSTABLE */ | |
| 1640 | − 0x00000006 /* EMC_TCLKSTOP */ | |
| 1641 | − 0x00001017 /* EMC_TREFBW */ | |
| 1642 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 1643 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 1644 | − 0x00000000 /* EMC_ODT_READ */ | |
| 1645 | − 0x104ab098 /* EMC_FBIO_CFG5 */ | |
| 1646 | − 0xe01200b1 /* EMC_CFG_DIG_DLL */ | |
| 1647 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 1648 | − 0x0000000a /* EMC_DLL_XFORM_DQS0 */ | |
| 1649 | − 0x0000000a /* EMC_DLL_XFORM_DQS1 */ | |
| 1650 | − 0x0000000a /* EMC_DLL_XFORM_DQS2 */ | |
| 1651 | − 0x0000000a /* EMC_DLL_XFORM_DQS3 */ | |
| 1652 | − 0x0000000a /* EMC_DLL_XFORM_DQS4 */ | |
| 1653 | − 0x0000000a /* EMC_DLL_XFORM_DQS5 */ | |
| 1654 | − 0x0000000a /* EMC_DLL_XFORM_DQS6 */ | |
| 1655 | − 0x0000000a /* EMC_DLL_XFORM_DQS7 */ | |
| 1656 | − 0x0000000a /* EMC_DLL_XFORM_DQS8 */ | |
| 1657 | − 0x0000000a /* EMC_DLL_XFORM_DQS9 */ | |
| 1658 | − 0x0000000a /* EMC_DLL_XFORM_DQS10 */ | |
| 1659 | − 0x0000000a /* EMC_DLL_XFORM_DQS11 */ | |
| 1660 | − 0x0000000a /* EMC_DLL_XFORM_DQS12 */ | |
| 1661 | − 0x0000000a /* EMC_DLL_XFORM_DQS13 */ | |
| 1662 | − 0x0000000a /* EMC_DLL_XFORM_DQS14 */ | |
| 1663 | − 0x0000000a /* EMC_DLL_XFORM_DQS15 */ | |
| 1664 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 1665 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 1666 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 1667 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 1668 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 1669 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 1670 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 1671 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 1672 | − 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 1673 | − 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 1674 | − 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 1675 | − 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 1676 | − 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 1677 | − 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 1678 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 1679 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 1680 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 1681 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 1682 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 1683 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 1684 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 1685 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 1686 | − 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 1687 | − 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 1688 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 1689 | − 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 1690 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 1691 | − 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 1692 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 1693 | − 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 1694 | − 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 1695 | − 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 1696 | − 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 1697 | − 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 1698 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 1699 | − 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 1700 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 1701 | − 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 1702 | − 0x0000000e /* EMC_DLL_XFORM_DQ0 */ | |
| 1703 | − 0x0000000e /* EMC_DLL_XFORM_DQ1 */ | |
| 1704 | − 0x0000000e /* EMC_DLL_XFORM_DQ2 */ | |
| 1705 | − 0x0000000e /* EMC_DLL_XFORM_DQ3 */ | |
| 1706 | − 0x0000000e /* EMC_DLL_XFORM_DQ4 */ | |
| 1707 | − 0x0000000e /* EMC_DLL_XFORM_DQ5 */ | |
| 1708 | − 0x0000000e /* EMC_DLL_XFORM_DQ6 */ | |
| 1709 | − 0x0000000e /* EMC_DLL_XFORM_DQ7 */ | |
| 1710 | − 0x100002a0 /* EMC_XM2CMDPADCTRL */ | |
| 1711 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 1712 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 1713 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
| 1714 | − 0x00000000 /* EMC_XM2DQPADCTRL3 */ | |
| 1715 | − 0x77ffc085 /* EMC_XM2CLKPADCTRL */ | |
| 1716 | − 0x00000101 /* EMC_XM2CLKPADCTRL2 */ | |
| 1717 | − 0x81f1f108 /* EMC_XM2COMPPADCTRL */ | |
| 1718 | − 0x07070004 /* EMC_XM2VTTGENPADCTRL */ | |
| 1719 | − 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ | |
| 1720 | − 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ | |
| 1721 | − 0x51451420 /* EMC_XM2DQSPADCTRL3 */ | |
| 1722 | − 0x00514514 /* EMC_XM2DQSPADCTRL4 */ | |
| 1723 | − 0x00514514 /* EMC_XM2DQSPADCTRL5 */ | |
| 1724 | − 0x51451400 /* EMC_XM2DQSPADCTRL6 */ | |
| 1725 | − 0x0606003f /* EMC_DSR_VTTGEN_DRV */ | |
| 1726 | − 0x00000000 /* EMC_TXDSRVTTGEN */ | |
| 1727 | − 0x00000000 /* EMC_FBIO_SPARE */ | |
| 1728 | − 0x00000100 /* EMC_ZCAL_WAIT_CNT */ | |
| 1729 | − 0x013a000c /* EMC_MRS_WAIT_CNT2 */ | |
| 1730 | − 0x00000000 /* EMC_CTT */ | |
| 1731 | − 0x00000003 /* EMC_CTT_DURATION */ | |
| 1732 | − 0x000042a0 /* EMC_CFG_PIPE */ | |
| 1733 | − 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ | |
| 1734 | − 0x0000000b /* EMC_QPOP */ | |
| 1735 | − >; | |
| 1736 | − }; | |
| 1737 | − | |
| 1738 | − timing-600000000 { | |
| 1739 | − clock-frequency = <600000000>; | |
| 1740 | − | |
| 1741 | − nvidia,emc-auto-cal-config = <0xa1430000>; | |
| 1742 | − nvidia,emc-auto-cal-config2 = <0x00000000>; | |
| 1743 | − nvidia,emc-auto-cal-config3 = <0x00000000>; | |
| 1744 | − nvidia,emc-auto-cal-interval = <0x001fffff>; | |
| 1745 | − nvidia,emc-bgbias-ctl0 = <0x00000000>; | |
| 1746 | − nvidia,emc-cfg = <0x73300000>; | |
| 1747 | − nvidia,emc-cfg-2 = <0x0000089d>; | |
| 1748 | − nvidia,emc-ctt-term-ctrl = <0x00000802>; | |
| 1749 | − nvidia,emc-mode-1 = <0x80100002>; | |
| 1750 | − nvidia,emc-mode-2 = <0x80200010>; | |
| 1751 | − nvidia,emc-mode-4 = <0x00000000>; | |
| 1752 | − nvidia,emc-mode-reset = <0x80000b61>; | |
| 1753 | − nvidia,emc-mrs-wait-cnt = <0x0128000c>; | |
| 1754 | − nvidia,emc-sel-dpd-ctrl = <0x00040008>; | |
| 1755 | − nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; | |
| 1756 | − nvidia,emc-zcal-cnt-long = <0x00000042>; | |
| 1757 | − nvidia,emc-zcal-interval = <0x00020000>; | |
| 1758 | − | |
| 1759 | − nvidia,emc-configuration = < | |
| 1760 | − 0x0000001c /* EMC_RC */ | |
| 1761 | − 0x0000009a /* EMC_RFC */ | |
| 1762 | − 0x00000000 /* EMC_RFC_SLR */ | |
| 1763 | − 0x00000013 /* EMC_RAS */ | |
| 1764 | − 0x00000007 /* EMC_RP */ | |
| 1765 | − 0x00000007 /* EMC_R2W */ | |
| 1766 | − 0x0000000b /* EMC_W2R */ | |
| 1767 | − 0x00000003 /* EMC_R2P */ | |
| 1768 | − 0x00000010 /* EMC_W2P */ | |
| 1769 | − 0x00000007 /* EMC_RD_RCD */ | |
| 1770 | − 0x00000007 /* EMC_WR_RCD */ | |
| 1771 | − 0x00000002 /* EMC_RRD */ | |
| 1772 | − 0x00000002 /* EMC_REXT */ | |
| 1773 | − 0x00000000 /* EMC_WEXT */ | |
| 1774 | − 0x00000005 /* EMC_WDV */ | |
| 1775 | − 0x00000005 /* EMC_WDV_MASK */ | |
| 1776 | − 0x0000000a /* EMC_QUSE */ | |
| 1777 | − 0x00000002 /* EMC_QUSE_WIDTH */ | |
| 1778 | − 0x00000000 /* EMC_IBDLY */ | |
| 1779 | − 0x00000003 /* EMC_EINPUT */ | |
| 1780 | − 0x0000000b /* EMC_EINPUT_DURATION */ | |
| 1781 | − 0x00070000 /* EMC_PUTERM_EXTRA */ | |
| 1782 | − 0x00000003 /* EMC_PUTERM_WIDTH */ | |
| 1783 | − 0x00000000 /* EMC_PUTERM_ADJ */ | |
| 1784 | − 0x00000000 /* EMC_CDB_CNTL_1 */ | |
| 1785 | − 0x00000000 /* EMC_CDB_CNTL_2 */ | |
| 1786 | − 0x00000000 /* EMC_CDB_CNTL_3 */ | |
| 1787 | − 0x00000002 /* EMC_QRST */ | |
| 1788 | − 0x00000012 /* EMC_QSAFE */ | |
| 1789 | − 0x00000016 /* EMC_RDV */ | |
| 1790 | − 0x00000018 /* EMC_RDV_MASK */ | |
| 1791 | − 0x00001208 /* EMC_REFRESH */ | |
| 1792 | − 0x00000000 /* EMC_BURST_REFRESH_NUM */ | |
| 1793 | − 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ | |
| 1794 | − 0x00000002 /* EMC_PDEX2WR */ | |
| 1795 | − 0x0000000d /* EMC_PDEX2RD */ | |
| 1796 | − 0x00000001 /* EMC_PCHG2PDEN */ | |
| 1797 | − 0x00000000 /* EMC_ACT2PDEN */ | |
| 1798 | − 0x00000096 /* EMC_AR2PDEN */ | |
| 1799 | − 0x00000015 /* EMC_RW2PDEN */ | |
| 1800 | − 0x000000a2 /* EMC_TXSR */ | |
| 1801 | − 0x00000200 /* EMC_TXSRDLL */ | |
| 1802 | − 0x00000004 /* EMC_TCKE */ | |
| 1803 | − 0x00000005 /* EMC_TCKESR */ | |
| 1804 | − 0x00000004 /* EMC_TPD */ | |
| 1805 | − 0x00000015 /* EMC_TFAW */ | |
| 1806 | − 0x00000000 /* EMC_TRPAB */ | |
| 1807 | − 0x00000006 /* EMC_TCLKSTABLE */ | |
| 1808 | − 0x00000006 /* EMC_TCLKSTOP */ | |
| 1809 | − 0x00001249 /* EMC_TREFBW */ | |
| 1810 | − 0x00000000 /* EMC_FBIO_CFG6 */ | |
| 1811 | − 0x00000000 /* EMC_ODT_WRITE */ | |
| 1812 | − 0x00000000 /* EMC_ODT_READ */ | |
| 1813 | − 0x104ab098 /* EMC_FBIO_CFG5 */ | |
| 1814 | − 0xe00e00b1 /* EMC_CFG_DIG_DLL */ | |
| 1815 | − 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ | |
| 1816 | − 0x0000000a /* EMC_DLL_XFORM_DQS0 */ | |
| 1817 | − 0x0000000a /* EMC_DLL_XFORM_DQS1 */ | |
| 1818 | − 0x0000000a /* EMC_DLL_XFORM_DQS2 */ | |
| 1819 | − 0x0000000a /* EMC_DLL_XFORM_DQS3 */ | |
| 1820 | − 0x0000000a /* EMC_DLL_XFORM_DQS4 */ | |
| 1821 | − 0x0000000a /* EMC_DLL_XFORM_DQS5 */ | |
| 1822 | − 0x0000000a /* EMC_DLL_XFORM_DQS6 */ | |
| 1823 | − 0x0000000a /* EMC_DLL_XFORM_DQS7 */ | |
| 1824 | − 0x0000000a /* EMC_DLL_XFORM_DQS8 */ | |
| 1825 | − 0x0000000a /* EMC_DLL_XFORM_DQS9 */ | |
| 1826 | − 0x0000000a /* EMC_DLL_XFORM_DQS10 */ | |
| 1827 | − 0x0000000a /* EMC_DLL_XFORM_DQS11 */ | |
| 1828 | − 0x0000000a /* EMC_DLL_XFORM_DQS12 */ | |
| 1829 | − 0x0000000a /* EMC_DLL_XFORM_DQS13 */ | |
| 1830 | − 0x0000000a /* EMC_DLL_XFORM_DQS14 */ | |
| 1831 | − 0x0000000a /* EMC_DLL_XFORM_DQS15 */ | |
| 1832 | − 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ | |
| 1833 | − 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ | |
| 1834 | − 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ | |
| 1835 | − 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ | |
| 1836 | − 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ | |
| 1837 | − 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ | |
| 1838 | − 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ | |
| 1839 | − 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ | |
| 1840 | − 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ | |
| 1841 | − 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ | |
| 1842 | − 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ | |
| 1843 | − 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ | |
| 1844 | − 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ | |
| 1845 | − 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ | |
| 1846 | − 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ | |
| 1847 | − 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ | |
| 1848 | − 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ | |
| 1849 | − 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ | |
| 1850 | − 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ | |
| 1851 | − 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ | |
| 1852 | − 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ | |
| 1853 | − 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ | |
| 1854 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ | |
| 1855 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ | |
| 1856 | − 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ | |
| 1857 | − 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ | |
| 1858 | − 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ | |
| 1859 | − 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ | |
| 1860 | − 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ | |
| 1861 | − 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ | |
| 1862 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ | |
| 1863 | − 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ | |
| 1864 | − 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ | |
| 1865 | − 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ | |
| 1866 | − 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ | |
| 1867 | − 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ | |
| 1868 | − 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ | |
| 1869 | − 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ | |
| 1870 | − 0x0000000e /* EMC_DLL_XFORM_DQ0 */ | |
| 1871 | − 0x0000000e /* EMC_DLL_XFORM_DQ1 */ | |
| 1872 | − 0x0000000e /* EMC_DLL_XFORM_DQ2 */ | |
| 1873 | − 0x0000000e /* EMC_DLL_XFORM_DQ3 */ | |
| 1874 | − 0x0000000e /* EMC_DLL_XFORM_DQ4 */ | |
| 1875 | − 0x0000000e /* EMC_DLL_XFORM_DQ5 */ | |
| 1876 | − 0x0000000e /* EMC_DLL_XFORM_DQ6 */ | |
| 1877 | − 0x0000000e /* EMC_DLL_XFORM_DQ7 */ | |
| 1878 | − 0x100002a0 /* EMC_XM2CMDPADCTRL */ | |
| 1879 | − 0x00000000 /* EMC_XM2CMDPADCTRL4 */ | |
| 1880 | − 0x00111111 /* EMC_XM2CMDPADCTRL5 */ | |
| 1881 | − 0x00000000 /* EMC_XM2DQPADCTRL2 */ | |
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