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Merge tag 'renesas-drivers-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.8 - Add System Controller (SYSC) and Reset (RST) support for the new RZ/G1H (R8A7742) SoC. * tag 'renesas-drivers-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-rst: Add support for RZ/G1H soc: renesas: rcar-sysc: Add R8A7742 support clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros

Arnd Bergmann committed 6 years ago

Commit acb09ec2 parents a7afae5 2f718328 files · +123 −0Browse files

Unified · Split

8 files
  1. drivers/soc/renesas/Kconfig +4 −0
  2. drivers/soc/renesas/Makefile +1 −0
  3. drivers/soc/renesas/r8a7742-sysc.c +42 −0
  4. drivers/soc/renesas/rcar-rst.c +1 −0
  5. drivers/soc/renesas/rcar-sysc.c +3 −0
  6. drivers/soc/renesas/rcar-sysc.h +1 −0
  7. include/dt-bindings/clock/r8a7742-cpg-mssr.h +42 −0
  8. include/dt-bindings/power/r8a7742-sysc.h +29 −0
drivers/soc/renesas/Kconfig+4−0
@@ -261,6 +261,10 @@ config ARCH_R8A77995 · 260 unmodified lines
261endif # ARM64261endif # ARM64
262 262
263# SoC263# SoC
264config SYSC_R8A7742
265 bool "RZ/G1H System Controller support" if COMPILE_TEST
266 select SYSC_RCAR
267
264config SYSC_R8A7743268config SYSC_R8A7743
265 bool "RZ/G1M System Controller support" if COMPILE_TEST269 bool "RZ/G1M System Controller support" if COMPILE_TEST
266 select SYSC_RCAR270 select SYSC_RCAR
drivers/soc/renesas/Makefile+1−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
3obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o3obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
4 4
5# SoC5# SoC
6obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
6obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o7obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
7obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o8obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
8obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o9obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
drivers/soc/renesas/r8a7742-sysc.c+42−0
@@ -0,0 +1,42 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/G1H System Controller
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <linux/kernel.h>
9
10#include <dt-bindings/power/r8a7742-sysc.h>
11
12#include "rcar-sysc.h"
13
14static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
15 { "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
17 PD_SCU },
18 { "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
19 PD_CPU_NOCR },
20 { "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
21 PD_CPU_NOCR },
22 { "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
23 PD_CPU_NOCR },
24 { "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
25 PD_CPU_NOCR },
26 { "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
27 PD_SCU },
28 { "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
29 PD_CPU_NOCR },
30 { "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
31 PD_CPU_NOCR },
32 { "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
33 PD_CPU_NOCR },
34 { "ca7-cpu3", 0x1c0, 3, R8A7742_PD_CA7_CPU3, R8A7742_PD_CA7_SCU,
35 PD_CPU_NOCR },
36 { "rgx", 0xc0, 0, R8A7742_PD_RGX, R8A7742_PD_ALWAYS_ON },
37};
38
39const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
40 .areas = r8a7742_areas,
41 .num_areas = ARRAY_SIZE(r8a7742_areas),
42};
drivers/soc/renesas/rcar-rst.c+1−0
@@ -39,6 +39,7 @@ static const struct rst_config rcar_rst_gen3 __initconst = { · 38 unmodified lines
39 39
40static const struct of_device_id rcar_rst_matches[] __initconst = {40static const struct of_device_id rcar_rst_matches[] __initconst = {
41 /* RZ/G1 is handled like R-Car Gen2 */41 /* RZ/G1 is handled like R-Car Gen2 */
42 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
42 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },43 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
43 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },44 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
44 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },45 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
drivers/soc/renesas/rcar-sysc.c+3−0
@@ -273,6 +273,9 @@ finalize: · 272 unmodified lines
273}273}
274 274
275static const struct of_device_id rcar_sysc_matches[] __initconst = {275static const struct of_device_id rcar_sysc_matches[] __initconst = {
276#ifdef CONFIG_SYSC_R8A7742
277 { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
278#endif
276#ifdef CONFIG_SYSC_R8A7743279#ifdef CONFIG_SYSC_R8A7743
277 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },280 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
278 /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */281 /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
drivers/soc/renesas/rcar-sysc.h+1−0
@@ -49,6 +49,7 @@ struct rcar_sysc_info { · 48 unmodified lines
49 u32 extmask_val; /* SYSCEXTMASK register mask value */49 u32 extmask_val; /* SYSCEXTMASK register mask value */
50};50};
51 51
52extern const struct rcar_sysc_info r8a7742_sysc_info;
52extern const struct rcar_sysc_info r8a7743_sysc_info;53extern const struct rcar_sysc_info r8a7743_sysc_info;
53extern const struct rcar_sysc_info r8a7745_sysc_info;54extern const struct rcar_sysc_info r8a7745_sysc_info;
54extern const struct rcar_sysc_info r8a77470_sysc_info;55extern const struct rcar_sysc_info r8a77470_sysc_info;
include/dt-bindings/clock/r8a7742-cpg-mssr.h+42−0
@@ -0,0 +1,42 @@
1/* SPDX-License-Identifier: GPL-2.0+
2 *
3 * Copyright (C) 2020 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a7742 CPG Core Clocks */
11#define R8A7742_CLK_Z 0
12#define R8A7742_CLK_Z2 1
13#define R8A7742_CLK_ZG 2
14#define R8A7742_CLK_ZTR 3
15#define R8A7742_CLK_ZTRD2 4
16#define R8A7742_CLK_ZT 5
17#define R8A7742_CLK_ZX 6
18#define R8A7742_CLK_ZS 7
19#define R8A7742_CLK_HP 8
20#define R8A7742_CLK_B 9
21#define R8A7742_CLK_LB 10
22#define R8A7742_CLK_P 11
23#define R8A7742_CLK_CL 12
24#define R8A7742_CLK_M2 13
25#define R8A7742_CLK_ZB3 14
26#define R8A7742_CLK_ZB3D2 15
27#define R8A7742_CLK_DDR 16
28#define R8A7742_CLK_SDH 17
29#define R8A7742_CLK_SD0 18
30#define R8A7742_CLK_SD1 19
31#define R8A7742_CLK_SD2 20
32#define R8A7742_CLK_SD3 21
33#define R8A7742_CLK_MMC0 22
34#define R8A7742_CLK_MMC1 23
35#define R8A7742_CLK_MP 24
36#define R8A7742_CLK_QSPI 25
37#define R8A7742_CLK_CP 26
38#define R8A7742_CLK_RCAN 27
39#define R8A7742_CLK_R 28
40#define R8A7742_CLK_OSC 29
41
42#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
include/dt-bindings/power/r8a7742-sysc.h+29−0
@@ -0,0 +1,29 @@
1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2020 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__
6#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__
7
8/*
9 * These power domain indices match the numbers of the interrupt bits
10 * representing the power areas in the various Interrupt Registers
11 * (e.g. SYSCISR, Interrupt Status Register)
12 */
13
14#define R8A7742_PD_CA15_CPU0 0
15#define R8A7742_PD_CA15_CPU1 1
16#define R8A7742_PD_CA15_CPU2 2
17#define R8A7742_PD_CA15_CPU3 3
18#define R8A7742_PD_CA7_CPU0 5
19#define R8A7742_PD_CA7_CPU1 6
20#define R8A7742_PD_CA7_CPU2 7
21#define R8A7742_PD_CA7_CPU3 8
22#define R8A7742_PD_CA15_SCU 12
23#define R8A7742_PD_RGX 20
24#define R8A7742_PD_CA7_SCU 21
25
26/* Always-on power area */
27#define R8A7742_PD_ALWAYS_ON 32
28
29#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */