lael-labs/linux

Documentation/devicetree/bindings/hwmon/ina209.txtrenamed from Documentation/devicetree/bindings/i2c/ina209.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/hwmon/ina2xx.txtrenamed from Documentation/devicetree/bindings/i2c/ina2xx.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/hwmon/max6697.txtrenamed from Documentation/devicetree/bindings/i2c/max6697.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/i2c/i2c-cadence.txt+5−1

 Required properties:
   - reg: Physical base address and size of the controller's register area.
-  - compatible: Compatibility string. Must be 'cdns,i2c-r1p10'.
+  - compatible: Should contain one of:
+		* "cdns,i2c-r1p10"
+		Note:	Use this when cadence i2c controller version 1.0 is used.
+		* "cdns,i2c-r1p14"
+		Note:	Use this when cadence i2c controller version 1.4 is used.
   - clocks: Input clock specifier. Refer to common clock bindings.
   - interrupts: Interrupt specifier. Refer to interrupt bindings.
   - #address-cells: Should be 1.

Documentation/devicetree/bindings/i2c/i2c-emev2.txt+22−0

@@ -0,0 +1,22 @@
	1	Device tree configuration for Renesas EMEV2 IIC controller
	2
	3	Required properties:
	4	- compatible : "renesas,iic-emev2"
	5	- reg : address start and address range size of device
	6	- interrupts : specifier for the IIC controller interrupt
	7	- clocks : phandle to the IP core SCLK
	8	- clock-names : must be "sclk"
	9	- #address-cells : should be <1>
	10	- #size-cells : should be <0>
	11
	12	Example:
	13
	14	iic0: i2c@e0070000 {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17	compatible = "renesas,iic-emev2";
	18	reg = <0xe0070000 0x28>;
	19	interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
	20	clocks = <&iic0_sclk>;
	21	clock-names = "sclk";
	22	};

Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt+33−0

@@ -0,0 +1,33 @@
	1	NXP I2C controller for LPC2xxx/178x/18xx/43xx
	2
	3	Required properties:
	4	- compatible: must be "nxp,lpc1788-i2c"
	5	- reg: physical address and length of the device registers
	6	- interrupts: a single interrupt specifier
	7	- clocks: clock for the device
	8	- #address-cells: should be <1>
	9	- #size-cells: should be <0>
	10
	11	Optional properties:
	12	- clock-frequency: the desired I2C bus clock frequency in Hz; in
	13	absence of this property the default value is used (100 kHz).
	14
	15	Example:
	16	i2c0: i2c@400a1000 {
	17	compatible = "nxp,lpc1788-i2c";
	18	reg = <0x400a1000 0x1000>;
	19	interrupts = <18>;
	20	clocks = <&ccu1 CLK_APB1_I2C0>;
	21	#address-cells = <1>;
	22	#size-cells = <0>;
	23	};
	24
	25	&i2c0 {
	26	clock-frequency = <400000>;
	27
	28	lm75@48 {
	29	compatible = "nxp,lm75";
	30	reg = <0x48>;
	31	};
	32	};
	33

Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt+74−0

@@ -0,0 +1,74 @@
	1	Register-based I2C Bus Mux
	2
	3	This binding describes an I2C bus multiplexer that uses a single register
	4	to route the I2C signals.
	5
	6	Required properties:
	7	- compatible: i2c-mux-reg
	8	- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
	9	port is connected to.
	10	* Standard I2C mux properties. See mux.txt in this directory.
	11	* I2C child bus nodes. See mux.txt in this directory.
	12
	13	Optional properties:
	14	- reg: this pair of <offset size> specifies the register to control the mux.
	15	The <offset size> depends on its parent node. It can be any memory-mapped
	16	address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the
	17	resource of this device will be used.
	18	- little-endian: The existence indicates the register is in little endian.
	19	- big-endian: The existence indicates the register is in big endian.
	20	If both little-endian and big-endian are omitted, the endianness of the
	21	CPU will be used.
	22	- write-only: The existence indicates the register is write-only.
	23	- idle-state: value to set the muxer to when idle. When no value is
	24	given, it defaults to the last value used.
	25
	26	Whenever an access is made to a device on a child bus, the value set
	27	in the revelant node's reg property will be output to the register.
	28
	29	If an idle state is defined, using the idle-state (optional) property,
	30	whenever an access is not being made to a device on a child bus, the
	31	register will be set according to the idle value.
	32
	33	If an idle state is not defined, the most recently used value will be
	34	left programmed into the register.
	35
	36	Example of a mux on PCIe card, the host is a powerpc SoC (big endian):
	37
	38	i2c-mux {
	39	/* the <offset size> depends on the address translation
	40	* of the parent device. If omitted, device resource
	41	* will be used instead. The size is to determine
	42	* whether iowrite32, iowrite16, or iowrite8 will be used.
	43	*/
	44	reg = <0x6028 0x4>;
	45	little-endian; /* little endian register on PCIe */
	46	compatible = "i2c-mux-reg";
	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49	i2c-parent = <&i2c1>;
	50	i2c@0 {
	51	reg = <0>;
	52	#address-cells = <1>;
	53	#size-cells = <0>;
	54
	55	si5338: clock-generator@70 {
	56	compatible = "silabs,si5338";
	57	reg = <0x70>;
	58	/* other stuff */
	59	};
	60	};
	61
	62	i2c@1 {
	63	/* data is written using iowrite32 */
	64	reg = <1>;
	65	#address-cells = <1>;
	66	#size-cells = <0>;
	67
	68	si5338: clock-generator@70 {
	69	compatible = "silabs,si5338";
	70	reg = <0x70>;
	71	/* other stuff */
	72	};
	73	};
	74	};

Documentation/devicetree/bindings/i2c/i2c.txt+45−0

@@ -0,0 +1,45 @@
	1	Generic device tree bindings for I2C busses
	2	===========================================
	3
	4	This document describes generic bindings which can be used to describe I2C
	5	busses in a device tree.
	6
	7	Required properties
	8	-------------------
	9
	10	- #address-cells - should be <1>. Read more about addresses below.
	11	- #size-cells - should be <0>.
	12	- compatible - name of I2C bus controller following generic names
	13	recommended practice.
	14
	15	For other required properties e.g. to describe register sets,
	16	clocks, etc. check the binding documentation of the specific driver.
	17
	18	The cells properties above define that an address of children of an I2C bus
	19	are described by a single value. This is usually a 7 bit address. However,
	20	flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10
	21	bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address
	22	of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus.
	23	Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to
	24	be devices ourselves.
	25
	26	Optional properties
	27	-------------------
	28
	29	These properties may not be supported by all drivers. However, if a driver
	30	wants to support one of the below features, it should adapt the bindings below.
	31
	32	- clock-frequency - frequency of bus clock in Hz.
	33	- wakeup-source - device can be used as a wakeup source.
	34
	35	- interrupts - interrupts used by the device.
	36	- interrupt-names - "irq" and "wakeup" names are recognized by I2C core,
	37	other names are left to individual drivers.
	38
	39	Binding may contain optional "interrupts" property, describing interrupts
	40	used by the device. I2C core will assign "irq" interrupt (or the very first
	41	interrupt if not using interrupt names) as primary interrupt for the slave.
	42
	43	Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
	44	interrupt for the device. If "wakeup" interrupt name is not present in the
	45	binding, then primary interrupt will be used as wakeup interrupt.

Documentation/devicetree/bindings/i2c/trivial-devices.txt+2−0

@@ -95,6 +95,8 @@ stm,m41t00 Serial Access TIMEKEEPER · 94 unmodified lines
95	stm,m41t62 Serial real-time clock (RTC) with alarm	95	stm,m41t62 Serial real-time clock (RTC) with alarm
96	stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS	96	stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
97	taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface	97	taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
		98	ti,ads7828 8-Channels, 12-bit ADC
		99	ti,ads7830 8-Channels, 8-bit ADC
98	ti,tsc2003 I2C Touch-Screen Controller	100	ti,tsc2003 I2C Touch-Screen Controller
99	ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface	101	ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
100	ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface	102	ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface

Documentation/devicetree/bindings/rtc/ti,bq32k.txtrenamed from Documentation/devicetree/bindings/i2c/ti,bq32k.txt+0−0

File renamed without changes.

Documentation/i2c/busses/i2c-parport+1−0

@@ -20,6 +20,7 @@ It currently supports the following devices: · 19 unmodified lines
20	* (type=5) Analog Devices evaluation boards: ADM1025, ADM1030, ADM1031	20	* (type=5) Analog Devices evaluation boards: ADM1025, ADM1030, ADM1031
21	* (type=6) Barco LPT->DVI (K5800236) adapter	21	* (type=6) Barco LPT->DVI (K5800236) adapter
22	* (type=7) One For All JP1 parallel port adapter	22	* (type=7) One For All JP1 parallel port adapter
		23	* (type=8) VCT-jig
23		24
24	These devices use different pinout configurations, so you have to tell	25	These devices use different pinout configurations, so you have to tell
25	the driver what you have, using the type module parameter. There is no	26	the driver what you have, using the type module parameter. There is no

Documentation/i2c/slave-interface+6−3

@@ -31,10 +31,13 @@ User manual · 30 unmodified lines
31	===========	31	===========
32		32
33	I2C slave backends behave like standard I2C clients. So, you can instantiate	33	I2C slave backends behave like standard I2C clients. So, you can instantiate
34	them as described in the document 'instantiating-devices'. A quick example for	34	them as described in the document 'instantiating-devices'. The only difference
35	instantiating the slave-eeprom driver from userspace at address 0x64 on bus 1:	35	is that i2c slave backends have their own address space. So, you have to add
		36	0x1000 to the address you would originally request. An example for
		37	instantiating the slave-eeprom driver from userspace at the 7 bit address 0x64
		38	on bus 1:
36		39
37	# echo slave-24c02 0x64 > /sys/bus/i2c/devices/i2c-1/new_device	40	# echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device
38		41
39	Each backend should come with separate documentation to describe its specific	42	Each backend should come with separate documentation to describe its specific
40	behaviour and setup.	43	behaviour and setup.

Documentation/i2c/ten-bit-addresses+4−0

@@ -2,6 +2,10 @@ The I2C protocol knows about two kinds of device addresses: normal 7 bit · 1 unmodified line
2	addresses, and an extended set of 10 bit addresses. The sets of addresses	2	addresses, and an extended set of 10 bit addresses. The sets of addresses
3	do not intersect: the 7 bit address 0x10 is not the same as the 10 bit	3	do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
4	address 0x10 (though a single device could respond to both of them).	4	address 0x10 (though a single device could respond to both of them).
		5	To avoid ambiguity, the user sees 10 bit addresses mapped to a different
		6	address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
		7	10 bit mode. This is used for creating device names in sysfs. It is also
		8	needed when instantiating 10 bit devices via the new_device file in sysfs.
5		9
6	I2C messages to and from 10-bit address devices have a different format.	10	I2C messages to and from 10-bit address devices have a different format.
7	See the I2C specification for the details.	11	See the I2C specification for the details.

drivers/clk/shmobile/clk-emev2.c+6−0

 #define USIBU1_RSTCTRL 0x0ac
 #define USIBU2_RSTCTRL 0x0b0
 #define USIBU3_RSTCTRL 0x0b4
+#define IIC0_RSTCTRL 0x0dc
+#define IIC1_RSTCTRL 0x0e0
 #define STI_RSTCTRL 0x124
 #define STI_CLKSEL 0x688
 	emev2_smu_write(2, USIBU1_RSTCTRL);
 	emev2_smu_write(2, USIBU2_RSTCTRL);
 	emev2_smu_write(2, USIBU3_RSTCTRL);
+	/* deassert reset for IIC0->IIC1 */
+	emev2_smu_write(1, IIC0_RSTCTRL);
+	emev2_smu_write(1, IIC1_RSTCTRL);
 }
 static void __init emev2_smu_clkdiv_init(struct device_node *np)

drivers/i2c/busses/Kconfig+18−1

 	  ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
 	  ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+config I2C_EMEV2
+	tristate "EMMA Mobile series I2C adapter"
+	depends on HAVE_CLK
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C interface on the Renesas Electronics EM/EV family of processors.
 config I2C_EXYNOS5
 	tristate "Exynos5 high-speed I2C driver"
 	depends on ARCH_EXYNOS && OF
 	  This driver can also be built as a module. If so, the module
 	  will be called i2c-kempld.
+config I2C_LPC2K
+	tristate "I2C bus support for NXP LPC2K/LPC178x/18xx/43xx"
+	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
+	help
+	  This driver supports the I2C interface found several NXP
+	  devices including LPC2xxx, LPC178x/7x and LPC18xx/43xx.
+	  This driver can also be built as a module.  If so, the module
+	  will be called i2c-lpc2k.
 config I2C_MESON
 	tristate "Amlogic Meson I2C controller"
 	depends on ARCH_MESON
 config I2C_CROS_EC_TUNNEL
 	tristate "ChromeOS EC tunnel I2C bus"
-	depends on CROS_EC_PROTO
+	depends on MFD_CROS_EC
 	help
 	  If you say yes here you get an I2C bus that will tunnel i2c commands
 	  through to the other side of the ChromeOS EC to the i2c bus

drivers/i2c/busses/Makefile+2−0

 obj-$(CONFIG_I2C_DIGICOLOR)	+= i2c-digicolor.o
 obj-$(CONFIG_I2C_EFM32)		+= i2c-efm32.o
 obj-$(CONFIG_I2C_EG20T)		+= i2c-eg20t.o
+obj-$(CONFIG_I2C_EMEV2)		+= i2c-emev2.o
 obj-$(CONFIG_I2C_EXYNOS5)	+= i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO)		+= i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)	+= i2c-highlander.o
 obj-$(CONFIG_I2C_IOP3XX)	+= i2c-iop3xx.o
 obj-$(CONFIG_I2C_JZ4780)	+= i2c-jz4780.o
 obj-$(CONFIG_I2C_KEMPLD)	+= i2c-kempld.o
+obj-$(CONFIG_I2C_LPC2K)		+= i2c-lpc2k.o
 obj-$(CONFIG_I2C_MESON)		+= i2c-meson.o
 obj-$(CONFIG_I2C_MPC)		+= i2c-mpc.o
 obj-$(CONFIG_I2C_MT65XX)	+= i2c-mt65xx.o

drivers/i2c/busses/i2c-cadence.c+58−11

 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 /* Register offsets for the I2C device. */
 #define CDNS_I2C_CR_OFFSET		0x00 /* Control Register, RW */
 #define CDNS_I2C_TIMEOUT_MAX	0xFF
+#define CDNS_I2C_BROKEN_HOLD_BIT	BIT(0)
 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
  * @bus_hold_flag:	Flag used in repeated start for clearing HOLD bit
  * @clk:		Pointer to struct clk
  * @clk_rate_change_nb:	Notifier block for clock rate changes
+ * @quirks:		flag for broken hold bit usage in r1p10
  */
 struct cdns_i2c {
 	void __iomem *membase;
 	unsigned int bus_hold_flag;
 	struct clk *clk;
 	struct notifier_block clk_rate_change_nb;
+	u32 quirks;
+};
+struct cdns_platform_data {
+	u32 quirks;
 };
 #define to_cdns_i2c(_nb)	container_of(_nb, struct cdns_i2c, \
 		cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
 }
+static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
+{
+	return (hold_wrkaround &&
+		(id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
+}
 /**
  * cdns_i2c_isr - Interrupt handler for the I2C device
  * @irq:	irq number for the I2C device
 {
 	unsigned int isr_status, avail_bytes, updatetx;
 	unsigned int bytes_to_send;
+	bool hold_quirk;
 	struct cdns_i2c *id = ptr;
 	/* Signal completion only after everything is updated */
 	int done_flag = 0;
 	if (id->recv_count > id->curr_recv_count)
 		updatetx = 1;
+	hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 	/* When receiving, handle data interrupt and completion interrupt */
 	if (id->p_recv_buf &&
 	    ((isr_status & CDNS_I2C_IXR_COMP) ||
 			id->recv_count--;
 			id->curr_recv_count--;
-			if (updatetx &&
+			if (cdns_is_holdquirk(id, hold_quirk))
-			    (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1))
 				break;
 		}
 		 * maintain transfer size non-zero while performing a large
 		 * receive operation.
 		 */
-		if (updatetx &&
+		if (cdns_is_holdquirk(id, hold_quirk)) {
-		    (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)) {
 			/* wait while fifo is full */
 			while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
 			       (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 						  CDNS_I2C_XFER_SIZE_OFFSET);
 				id->curr_recv_count = id->recv_count;
 			}
+		} else if (id->recv_count && !hold_quirk &&
+						!id->curr_recv_count) {
+			/* Set the slave address in address register*/
+			cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
+						CDNS_I2C_ADDR_OFFSET);
+			if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
+				cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
+						CDNS_I2C_XFER_SIZE_OFFSET);
+				id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+			} else {
+				cdns_i2c_writereg(id->recv_count,
+						CDNS_I2C_XFER_SIZE_OFFSET);
+				id->curr_recv_count = id->recv_count;
+			}
 		}
 		/* Clear hold (if not repeated start) and signal completion */
 	int ret, count;
 	u32 reg;
 	struct cdns_i2c *id = adap->algo_data;
+	bool hold_quirk;
 	/* Check if the bus is free */
 	if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA)
 		return -EAGAIN;
+	hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 	/*
 	 * Set the flag to one when multiple messages are to be
 	 * processed with a repeated start.
 		 * followed by any other message, an error is returned
 		 * indicating that this sequence is not supported.
 		 */
-		for (count = 0; count < num - 1; count++) {
+		for (count = 0; (count < num - 1 && hold_quirk); count++) {
 			if (msgs[count].flags & I2C_M_RD) {
 				dev_warn(adap->dev.parent,
 					 "Can't do repeated start after a receive message\n");
 static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend,
 			 cdns_i2c_resume);
+static const struct cdns_platform_data r1p10_i2c_def = {
+	.quirks = CDNS_I2C_BROKEN_HOLD_BIT,
+};
+static const struct of_device_id cdns_i2c_of_match[] = {
+	{ .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
+	{ .compatible = "cdns,i2c-r1p14",},
+	{ /* end of table */ }
+};
+MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
 /**
  * cdns_i2c_probe - Platform registration call
  * @pdev:	Handle to the platform device structure
 	struct resource *r_mem;
 	struct cdns_i2c *id;
 	int ret;
+	const struct of_device_id *match;
 	id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
 	if (!id)
 	platform_set_drvdata(pdev, id);
+	match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
+	if (match && match->data) {
+		const struct cdns_platform_data *data = match->data;
+		id->quirks = data->quirks;
+	}
 	r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
 	if (IS_ERR(id->membase))
 	id->irq = platform_get_irq(pdev, 0);
+	id->adap.owner = THIS_MODULE;
 	id->adap.dev.of_node = pdev->dev.of_node;
 	id->adap.algo = &cdns_i2c_algo;
 	id->adap.timeout = CDNS_I2C_TIMEOUT;
 	return 0;
 }
-static const struct of_device_id cdns_i2c_of_match[] = {
-	{ .compatible = "cdns,i2c-r1p10", },
-	{ /* end of table */ }
-};
-MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
 static struct platform_driver cdns_i2c_drv = {
 	.driver = {
 		.name  = DRIVER_NAME,

drivers/i2c/busses/i2c-designware-core.c+1−2

@@ -777,8 +777,7 @@ irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) · 776 unmodified lines
777		777
778	enabled = dw_readl(dev, DW_IC_ENABLE);	778	enabled = dw_readl(dev, DW_IC_ENABLE);
779	stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);	779	stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
780	dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,	780	dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
781	dev->adapter.name, enabled, stat);
782	if (!enabled \|\| !(stat & ~DW_IC_INTR_ACTIVITY))	781	if (!enabled \|\| !(stat & ~DW_IC_INTR_ACTIVITY))
783	return IRQ_NONE;	782	return IRQ_NONE;
784		783

drivers/i2c/busses/i2c-designware-pcidrv.c+2−2

@@ -260,8 +260,8 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev, · 259 unmodified lines
260		260
261	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");	261	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
262		262
263	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,	263	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr,
264	adap->name, dev);	264	IRQF_SHARED \| IRQF_COND_SUSPEND, adap->name, dev);
265	if (r) {	265	if (r) {
266	dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);	266	dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
267	return r;	267	return r;

drivers/i2c/busses/i2c-emev2.c+332−0

@@ -0,0 +1,332 @@
	1	/*
	2	* I2C driver for the Renesas EMEV2 SoC
	3	*
	4	* Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
	5	* Copyright 2013 Codethink Ltd.
	6	* Copyright 2010-2015 Renesas Electronics Corporation
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2
	10	* as published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/completion.h>
	15	#include <linux/device.h>
	16	#include <linux/i2c.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/io.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/of_device.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/sched.h>
	25
	26	/* I2C Registers */
	27	#define I2C_OFS_IICACT0 0x00 /* start */
	28	#define I2C_OFS_IIC0 0x04 /* shift */
	29	#define I2C_OFS_IICC0 0x08 /* control */
	30	#define I2C_OFS_SVA0 0x0c /* slave address */
	31	#define I2C_OFS_IICCL0 0x10 /* clock select */
	32	#define I2C_OFS_IICX0 0x14 /* extension */
	33	#define I2C_OFS_IICS0 0x18 /* status */
	34	#define I2C_OFS_IICSE0 0x1c /* status For emulation */
	35	#define I2C_OFS_IICF0 0x20 /* IIC flag */
	36
	37	/* I2C IICACT0 Masks */
	38	#define I2C_BIT_IICE0 0x0001
	39
	40	/* I2C IICC0 Masks */
	41	#define I2C_BIT_LREL0 0x0040
	42	#define I2C_BIT_WREL0 0x0020
	43	#define I2C_BIT_SPIE0 0x0010
	44	#define I2C_BIT_WTIM0 0x0008
	45	#define I2C_BIT_ACKE0 0x0004
	46	#define I2C_BIT_STT0 0x0002
	47	#define I2C_BIT_SPT0 0x0001
	48
	49	/* I2C IICCL0 Masks */
	50	#define I2C_BIT_SMC0 0x0008
	51	#define I2C_BIT_DFC0 0x0004
	52
	53	/* I2C IICSE0 Masks */
	54	#define I2C_BIT_MSTS0 0x0080
	55	#define I2C_BIT_ALD0 0x0040
	56	#define I2C_BIT_EXC0 0x0020
	57	#define I2C_BIT_COI0 0x0010
	58	#define I2C_BIT_TRC0 0x0008
	59	#define I2C_BIT_ACKD0 0x0004
	60	#define I2C_BIT_STD0 0x0002
	61	#define I2C_BIT_SPD0 0x0001
	62
	63	/* I2C IICF0 Masks */
	64	#define I2C_BIT_STCF 0x0080
	65	#define I2C_BIT_IICBSY 0x0040
	66	#define I2C_BIT_STCEN 0x0002
	67	#define I2C_BIT_IICRSV 0x0001
	68
	69	struct em_i2c_device {
	70	void __iomem *base;
	71	struct i2c_adapter adap;
	72	struct completion msg_done;
	73	struct clk *sclk;
	74	};
	75
	76	static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
	77	{
	78	writeb((readb(priv->base + reg) & ~clear) \| set, priv->base + reg);
	79	}
	80
	81	static int em_i2c_wait_for_event(struct em_i2c_device *priv)
	82	{
	83	unsigned long time_left;
	84	int status;
	85
	86	reinit_completion(&priv->msg_done);
	87
	88	time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
	89
	90	if (!time_left)
	91	return -ETIMEDOUT;
	92
	93	status = readb(priv->base + I2C_OFS_IICSE0);
	94	return status & I2C_BIT_ALD0 ? -EAGAIN : status;
	95	}
	96
	97	static void em_i2c_stop(struct em_i2c_device *priv)
	98	{
	99	/* Send Stop condition */
	100	em_clear_set_bit(priv, 0, I2C_BIT_SPT0 \| I2C_BIT_SPIE0, I2C_OFS_IICC0);
	101
	102	/* Wait for stop condition */
	103	em_i2c_wait_for_event(priv);
	104	}
	105
	106	static void em_i2c_reset(struct i2c_adapter *adap)
	107	{
	108	struct em_i2c_device *priv = i2c_get_adapdata(adap);
	109	int retr;
	110
	111	/* If I2C active */
	112	if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
	113	/* Disable I2C operation */
	114	writeb(0, priv->base + I2C_OFS_IICACT0);
	115
	116	retr = 1000;
	117	while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
	118	retr--;
	119	WARN_ON(retr == 0);
	120	}
	121
	122	/* Transfer mode set */
	123	writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
	124
	125	/* Can Issue start without detecting a stop, Reservation disabled. */
	126	writeb(I2C_BIT_STCEN \| I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
	127
	128	/* I2C enable, 9 bit interrupt mode */
	129	writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
	130
	131	/* Enable I2C operation */
	132	writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
	133
	134	retr = 1000;
	135	while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
	136	retr--;
	137	WARN_ON(retr == 0);
	138	}
	139
	140	static int __em_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msg,
	141	int stop)
	142	{
	143	struct em_i2c_device *priv = i2c_get_adapdata(adap);
	144	int count, status, read = !!(msg->flags & I2C_M_RD);
	145
	146	/* Send start condition */
	147	em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 \| I2C_BIT_WTIM0, I2C_OFS_IICC0);
	148	em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
	149
	150	/* Send slave address and R/W type */
	151	writeb((msg->addr << 1) \| read, priv->base + I2C_OFS_IIC0);
	152
	153	/* Wait for transaction */
	154	status = em_i2c_wait_for_event(priv);
	155	if (status < 0)
	156	goto out_reset;
	157
	158	/* Received NACK (result of setting slave address and R/W) */
	159	if (!(status & I2C_BIT_ACKD0)) {
	160	em_i2c_stop(priv);
	161	goto out;
	162	}
	163
	164	/* Extra setup for read transactions */
	165	if (read) {
	166	/* 8 bit interrupt mode */
	167	em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
	168	em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
	169
	170	/* Wait for transaction */
	171	status = em_i2c_wait_for_event(priv);
	172	if (status < 0)
	173	goto out_reset;
	174	}
	175
	176	/* Send / receive data */
	177	for (count = 0; count < msg->len; count++) {
	178	if (read) { /* Read transaction */
	179	msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
	180	em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
	181
	182	} else { /* Write transaction */
	183	/* Received NACK */
	184	if (!(status & I2C_BIT_ACKD0)) {
	185	em_i2c_stop(priv);
	186	goto out;
	187	}
	188
	189	/* Write data */
	190	writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
	191	}
	192
	193	/* Wait for R/W transaction */
	194	status = em_i2c_wait_for_event(priv);
	195	if (status < 0)
	196	goto out_reset;
	197	}
	198
	199	if (stop)
	200	em_i2c_stop(priv);
	201
	202	return count;
	203
	204	out_reset:
	205	em_i2c_reset(adap);
	206	out:
	207	return status < 0 ? status : -ENXIO;
	208	}
	209
	210	static int em_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
	211	int num)
	212	{
	213	struct em_i2c_device *priv = i2c_get_adapdata(adap);
	214	int ret, i;
	215
	216	if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
	217	return -EAGAIN;
	218
	219	for (i = 0; i < num; i++) {
	220	ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
	221	if (ret < 0)
	222	return ret;
	223	}
	224
	225	/* I2C transfer completed */
	226	return num;
	227	}
	228
	229	static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
	230	{
	231	struct em_i2c_device *priv = dev_id;
	232
	233	complete(&priv->msg_done);
	234	return IRQ_HANDLED;
	235	}
	236
	237	static u32 em_i2c_func(struct i2c_adapter *adap)
	238	{
	239	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	240	}
	241
	242	static struct i2c_algorithm em_i2c_algo = {
	243	.master_xfer = em_i2c_xfer,
	244	.functionality = em_i2c_func,
	245	};
	246
	247	static int em_i2c_probe(struct platform_device *pdev)
	248	{
	249	struct em_i2c_device *priv;
	250	struct resource *r;
	251	int irq, ret;
	252
	253	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	254	if (!priv)
	255	return -ENOMEM;
	256
	257	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	258	priv->base = devm_ioremap_resource(&pdev->dev, r);
	259	if (IS_ERR(priv->base))
	260	return PTR_ERR(priv->base);
	261
	262	strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
	263
	264	priv->sclk = devm_clk_get(&pdev->dev, "sclk");
	265	if (IS_ERR(priv->sclk))
	266	return PTR_ERR(priv->sclk);
	267
	268	clk_prepare_enable(priv->sclk);
	269
	270	priv->adap.timeout = msecs_to_jiffies(100);
	271	priv->adap.retries = 5;
	272	priv->adap.dev.parent = &pdev->dev;
	273	priv->adap.algo = &em_i2c_algo;
	274	priv->adap.owner = THIS_MODULE;
	275	priv->adap.dev.of_node = pdev->dev.of_node;
	276
	277	init_completion(&priv->msg_done);
	278
	279	platform_set_drvdata(pdev, priv);
	280	i2c_set_adapdata(&priv->adap, priv);
	281
	282	em_i2c_reset(&priv->adap);
	283
	284	irq = platform_get_irq(pdev, 0);
	285	ret = devm_request_irq(&pdev->dev, irq, em_i2c_irq_handler, 0,
	286	"em_i2c", priv);
	287	if (ret)
	288	goto err_clk;
	289
	290	ret = i2c_add_adapter(&priv->adap);
	291
	292	if (ret)
	293	goto err_clk;
	294
	295	dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, irq);
	296
	297	return 0;
	298
	299	err_clk:
	300	clk_disable_unprepare(priv->sclk);
	301	return ret;
	302	}
	303
	304	static int em_i2c_remove(struct platform_device *dev)
	305	{
	306	struct em_i2c_device *priv = platform_get_drvdata(dev);
	307
	308	i2c_del_adapter(&priv->adap);
	309	clk_disable_unprepare(priv->sclk);
	310
	311	return 0;
	312	}
	313
	314	static const struct of_device_id em_i2c_ids[] = {
	315	{ .compatible = "renesas,iic-emev2", },
	316	{ }
	317	};
	318
	319	static struct platform_driver em_i2c_driver = {
	320	.probe = em_i2c_probe,
	321	.remove = em_i2c_remove,
	322	.driver = {
	323	.name = "em-i2c",
	324	.of_match_table = em_i2c_ids,
	325	}
	326	};
	327	module_platform_driver(em_i2c_driver);
	328
	329	MODULE_DESCRIPTION("EMEV2 I2C bus driver");
	330	MODULE_AUTHOR("Ian Molton and Wolfram Sang <wsa@sang-engineering.com>");
	331	MODULE_LICENSE("GPL v2");
	332	MODULE_DEVICE_TABLE(of, em_i2c_ids);

drivers/i2c/busses/i2c-lpc2k.c+513−0

@@ -0,0 +1,513 @@
	1	/*
	2	* Copyright (C) 2011 NXP Semiconductors
	3	*
	4	* Code portions referenced from the i2x-pxa and i2c-pnx drivers
	5	*
	6	* Make SMBus byte and word transactions work on LPC178x/7x
	7	* Copyright (c) 2012
	8	* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
	9	* Anton Protopopov, Emcraft Systems, antonp@emcraft.com
	10	*
	11	* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License, or
	16	* (at your option) any later version.
	17	*
	18	*/
	19
	20	#include <linux/clk.h>
	21	#include <linux/errno.h>
	22	#include <linux/i2c.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/io.h>
	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/of.h>
	28	#include <linux/of_device.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/sched.h>
	31	#include <linux/time.h>
	32
	33	/* LPC24xx register offsets and bits */
	34	#define LPC24XX_I2CONSET 0x00
	35	#define LPC24XX_I2STAT 0x04
	36	#define LPC24XX_I2DAT 0x08
	37	#define LPC24XX_I2ADDR 0x0c
	38	#define LPC24XX_I2SCLH 0x10
	39	#define LPC24XX_I2SCLL 0x14
	40	#define LPC24XX_I2CONCLR 0x18
	41
	42	#define LPC24XX_AA BIT(2)
	43	#define LPC24XX_SI BIT(3)
	44	#define LPC24XX_STO BIT(4)
	45	#define LPC24XX_STA BIT(5)
	46	#define LPC24XX_I2EN BIT(6)
	47
	48	#define LPC24XX_STO_AA (LPC24XX_STO \| LPC24XX_AA)
	49	#define LPC24XX_CLEAR_ALL (LPC24XX_AA \| LPC24XX_SI \| LPC24XX_STO \| \
	50	LPC24XX_STA \| LPC24XX_I2EN)
	51
	52	/* I2C SCL clock has different duty cycle depending on mode */
	53	#define I2C_STD_MODE_DUTY 46
	54	#define I2C_FAST_MODE_DUTY 36
	55	#define I2C_FAST_MODE_PLUS_DUTY 38
	56
	57	/*
	58	* 26 possible I2C status codes, but codes applicable only
	59	* to master are listed here and used in this driver
	60	*/
	61	enum {
	62	M_BUS_ERROR = 0x00,
	63	M_START = 0x08,
	64	M_REPSTART = 0x10,
	65	MX_ADDR_W_ACK = 0x18,
	66	MX_ADDR_W_NACK = 0x20,
	67	MX_DATA_W_ACK = 0x28,
	68	MX_DATA_W_NACK = 0x30,
	69	M_DATA_ARB_LOST = 0x38,
	70	MR_ADDR_R_ACK = 0x40,
	71	MR_ADDR_R_NACK = 0x48,
	72	MR_DATA_R_ACK = 0x50,
	73	MR_DATA_R_NACK = 0x58,
	74	M_I2C_IDLE = 0xf8,
	75	};
	76
	77	struct lpc2k_i2c {
	78	void __iomem *base;
	79	struct clk *clk;
	80	int irq;
	81	wait_queue_head_t wait;
	82	struct i2c_adapter adap;
	83	struct i2c_msg *msg;
	84	int msg_idx;
	85	int msg_status;
	86	int is_last;
	87	};
	88
	89	static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
	90	{
	91	/* Will force clear all statuses */
	92	writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
	93	writel(0, i2c->base + LPC24XX_I2ADDR);
	94	writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
	95	}
	96
	97	static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
	98	{
	99	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
	100
	101	/*
	102	* If the transfer needs to abort for some reason, we'll try to
	103	* force a stop condition to clear any pending bus conditions
	104	*/
	105	writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
	106
	107	/* Wait for status change */
	108	while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
	109	if (time_after(jiffies, timeout)) {
	110	/* Bus was not idle, try to reset adapter */
	111	i2c_lpc2k_reset(i2c);
	112	return -EBUSY;
	113	}
	114
	115	cpu_relax();
	116	}
	117
	118	return 0;
	119	}
	120
	121	static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
	122	{
	123	unsigned char data;
	124	u32 status;
	125
	126	/*
	127	* I2C in the LPC2xxx series is basically a state machine.
	128	* Just run through the steps based on the current status.
	129	*/
	130	status = readl(i2c->base + LPC24XX_I2STAT);
	131
	132	switch (status) {
	133	case M_START:
	134	case M_REPSTART:
	135	/* Start bit was just sent out, send out addr and dir */
	136	data = i2c->msg->addr << 1;
	137	if (i2c->msg->flags & I2C_M_RD)
	138	data \|= 1;
	139
	140	writel(data, i2c->base + LPC24XX_I2DAT);
	141	writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
	142	break;
	143
	144	case MX_ADDR_W_ACK:
	145	case MX_DATA_W_ACK:
	146	/*
	147	* Address or data was sent out with an ACK. If there is more
	148	* data to send, send it now
	149	*/
	150	if (i2c->msg_idx < i2c->msg->len) {
	151	writel(i2c->msg->buf[i2c->msg_idx],
	152	i2c->base + LPC24XX_I2DAT);
	153	} else if (i2c->is_last) {
	154	/* Last message, send stop */
	155	writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
	156	writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
	157	i2c->msg_status = 0;
	158	disable_irq_nosync(i2c->irq);
	159	} else {
	160	i2c->msg_status = 0;
	161	disable_irq_nosync(i2c->irq);
	162	}
	163
	164	i2c->msg_idx++;
	165	break;
	166
	167	case MR_ADDR_R_ACK:
	168	/* Receive first byte from slave */
	169	if (i2c->msg->len == 1) {
	170	/* Last byte, return NACK */
	171	writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
	172	} else {
	173	/* Not last byte, return ACK */
	174	writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
	175	}
	176
	177	writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
	178	break;
	179
	180	case MR_DATA_R_NACK:
	181	/*
	182	* The I2C shows NACK status on reads, so we need to accept
	183	* the NACK as an ACK here. This should be ok, as the real
	184	* BACK would of been caught on the address write.
	185	*/
	186	case MR_DATA_R_ACK:
	187	/* Data was received */
	188	if (i2c->msg_idx < i2c->msg->len) {
	189	i2c->msg->buf[i2c->msg_idx] =
	190	readl(i2c->base + LPC24XX_I2DAT);
	191	}
	192
	193	/* If transfer is done, send STOP */
	194	if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
	195	writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
	196	writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
	197	i2c->msg_status = 0;
	198	}
	199
	200	/* Message is done */
	201	if (i2c->msg_idx >= i2c->msg->len - 1) {
	202	i2c->msg_status = 0;
	203	disable_irq_nosync(i2c->irq);
	204	}
	205
	206	/*
	207	* One pre-last data input, send NACK to tell the slave that
	208	* this is going to be the last data byte to be transferred.
	209	*/
	210	if (i2c->msg_idx >= i2c->msg->len - 2) {
	211	/* One byte left to receive - NACK */
	212	writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
	213	} else {
	214	/* More than one byte left to receive - ACK */
	215	writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
	216	}
	217
	218	writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
	219	i2c->msg_idx++;
	220	break;
	221
	222	case MX_ADDR_W_NACK:
	223	case MX_DATA_W_NACK:
	224	case MR_ADDR_R_NACK:
	225	/* NACK processing is done */
	226	writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
	227	i2c->msg_status = -ENXIO;
	228	disable_irq_nosync(i2c->irq);
	229	break;
	230
	231	case M_DATA_ARB_LOST:
	232	/* Arbitration lost */
	233	i2c->msg_status = -EAGAIN;
	234
	235	/* Release the I2C bus */
	236	writel(LPC24XX_STA \| LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
	237	disable_irq_nosync(i2c->irq);
	238	break;
	239
	240	default:
	241	/* Unexpected statuses */
	242	i2c->msg_status = -EIO;
	243	disable_irq_nosync(i2c->irq);
	244	break;
	245	}
	246
	247	/* Exit on failure or all bytes transferred */
	248	if (i2c->msg_status != -EBUSY)
	249	wake_up(&i2c->wait);
	250
	251	/*
	252	* If `msg_status` is zero, then `lpc2k_process_msg()`
	253	* is responsible for clearing the SI flag.
	254	*/
	255	if (i2c->msg_status != 0)
	256	writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
	257	}
	258
	259	static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
	260	{
	261	/* A new transfer is kicked off by initiating a start condition */
	262	if (!msgidx) {
	263	writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
	264	} else {
	265	/*
	266	* A multi-message I2C transfer continues where the
	267	* previous I2C transfer left off and uses the
	268	* current condition of the I2C adapter.
	269	*/
	270	if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
	271	WARN_ON(i2c->msg->len == 0);
	272
	273	if (!(i2c->msg->flags & I2C_M_RD)) {
	274	/* Start transmit of data */
	275	writel(i2c->msg->buf[0],
	276	i2c->base + LPC24XX_I2DAT);
	277	i2c->msg_idx++;
	278	}
	279	} else {
	280	/* Start or repeated start */
	281	writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
	282	}
	283
	284	writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
	285	}
	286
	287	enable_irq(i2c->irq);
	288
	289	/* Wait for transfer completion */
	290	if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
	291	msecs_to_jiffies(1000)) == 0) {
	292	disable_irq_nosync(i2c->irq);
	293
	294	return -ETIMEDOUT;
	295	}
	296
	297	return i2c->msg_status;
	298	}
	299
	300	static int i2c_lpc2k_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
	301	int msg_num)
	302	{
	303	struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
	304	int ret, i;
	305	u32 stat;
	306
	307	/* Check for bus idle condition */
	308	stat = readl(i2c->base + LPC24XX_I2STAT);
	309	if (stat != M_I2C_IDLE) {
	310	/* Something is holding the bus, try to clear it */
	311	return i2c_lpc2k_clear_arb(i2c);
	312	}
	313
	314	/* Process a single message at a time */
	315	for (i = 0; i < msg_num; i++) {
	316	/* Save message pointer and current message data index */
	317	i2c->msg = &msgs[i];
	318	i2c->msg_idx = 0;
	319	i2c->msg_status = -EBUSY;
	320	i2c->is_last = (i == (msg_num - 1));
	321
	322	ret = lpc2k_process_msg(i2c, i);
	323	if (ret)
	324	return ret;
	325	}
	326
	327	return msg_num;
	328	}
	329
	330	static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
	331	{
	332	struct lpc2k_i2c *i2c = dev_id;
	333
	334	if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
	335	i2c_lpc2k_pump_msg(i2c);
	336	return IRQ_HANDLED;
	337	}
	338
	339	return IRQ_NONE;
	340	}
	341
	342	static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
	343	{
	344	/* Only emulated SMBus for now */
	345	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	346	}
	347
	348	static const struct i2c_algorithm i2c_lpc2k_algorithm = {
	349	.master_xfer = i2c_lpc2k_xfer,
	350	.functionality = i2c_lpc2k_functionality,
	351	};
	352
	353	static int i2c_lpc2k_probe(struct platform_device *pdev)
	354	{
	355	struct lpc2k_i2c *i2c;
	356	struct resource *res;
	357	u32 bus_clk_rate;
	358	u32 scl_high;
	359	u32 clkrate;
	360	int ret;
	361
	362	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	363	if (!i2c)
	364	return -ENOMEM;
	365
	366	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	367	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	368	if (IS_ERR(i2c->base))
	369	return PTR_ERR(i2c->base);
	370
	371	i2c->irq = platform_get_irq(pdev, 0);
	372	if (i2c->irq < 0) {
	373	dev_err(&pdev->dev, "can't get interrupt resource\n");
	374	return i2c->irq;
	375	}
	376
	377	init_waitqueue_head(&i2c->wait);
	378
	379	i2c->clk = devm_clk_get(&pdev->dev, NULL);
	380	if (IS_ERR(i2c->clk)) {
	381	dev_err(&pdev->dev, "error getting clock\n");
	382	return PTR_ERR(i2c->clk);
	383	}
	384
	385	ret = clk_prepare_enable(i2c->clk);
	386	if (ret) {
	387	dev_err(&pdev->dev, "unable to enable clock.\n");
	388	return ret;
	389	}
	390
	391	ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
	392	dev_name(&pdev->dev), i2c);
	393	if (ret < 0) {
	394	dev_err(&pdev->dev, "can't request interrupt.\n");
	395	goto fail_clk;
	396	}
	397
	398	disable_irq_nosync(i2c->irq);
	399
	400	/* Place controller is a known state */
	401	i2c_lpc2k_reset(i2c);
	402
	403	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
	404	&bus_clk_rate);
	405	if (ret)
	406	bus_clk_rate = 100000; /* 100 kHz default clock rate */
	407
	408	clkrate = clk_get_rate(i2c->clk);
	409	if (clkrate == 0) {
	410	dev_err(&pdev->dev, "can't get I2C base clock\n");
	411	ret = -EINVAL;
	412	goto fail_clk;
	413	}
	414
	415	/* Setup I2C dividers to generate clock with proper duty cycle */
	416	clkrate = clkrate / bus_clk_rate;
	417	if (bus_clk_rate <= 100000)
	418	scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
	419	else if (bus_clk_rate <= 400000)
	420	scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
	421	else
	422	scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
	423
	424	writel(scl_high, i2c->base + LPC24XX_I2SCLH);
	425	writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
	426
	427	platform_set_drvdata(pdev, i2c);
	428
	429	i2c_set_adapdata(&i2c->adap, i2c);
	430	i2c->adap.owner = THIS_MODULE;
	431	strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
	432	i2c->adap.algo = &i2c_lpc2k_algorithm;
	433	i2c->adap.dev.parent = &pdev->dev;
	434	i2c->adap.dev.of_node = pdev->dev.of_node;
	435
	436	ret = i2c_add_adapter(&i2c->adap);
	437	if (ret < 0) {
	438	dev_err(&pdev->dev, "failed to add adapter!\n");
	439	goto fail_clk;
	440	}
	441
	442	dev_info(&pdev->dev, "LPC2K I2C adapter\n");
	443
	444	return 0;
	445
	446	fail_clk:
	447	clk_disable_unprepare(i2c->clk);
	448	return ret;
	449	}
	450
	451	static int i2c_lpc2k_remove(struct platform_device *dev)
	452	{
	453	struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
	454
	455	i2c_del_adapter(&i2c->adap);
	456	clk_disable_unprepare(i2c->clk);
	457
	458	return 0;
	459	}
	460
	461	#ifdef CONFIG_PM
	462	static int i2c_lpc2k_suspend(struct device *dev)
	463	{
	464	struct platform_device *pdev = to_platform_device(dev);
	465	struct lpc2k_i2c *i2c = platform_get_drvdata(pdev);
	466
	467	clk_disable(i2c->clk);
	468
	469	return 0;
	470	}
	471
	472	static int i2c_lpc2k_resume(struct device *dev)
	473	{
	474	struct platform_device *pdev = to_platform_device(dev);
	475	struct lpc2k_i2c *i2c = platform_get_drvdata(pdev);
	476
	477	clk_enable(i2c->clk);
	478	i2c_lpc2k_reset(i2c);
	479
	480	return 0;
	481	}
	482
	483	static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
	484	.suspend_noirq = i2c_lpc2k_suspend,
	485	.resume_noirq = i2c_lpc2k_resume,
	486	};
	487
	488	#define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
	489	#else
	490	#define I2C_LPC2K_DEV_PM_OPS NULL
	491	#endif
	492
	493	static const struct of_device_id lpc2k_i2c_match[] = {
	494	{ .compatible = "nxp,lpc1788-i2c" },
	495	{},
	496	};
	497	MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
	498
	499	static struct platform_driver i2c_lpc2k_driver = {
	500	.probe = i2c_lpc2k_probe,
	501	.remove = i2c_lpc2k_remove,
	502	.driver = {
	503	.name = "lpc2k-i2c",
	504	.pm = I2C_LPC2K_DEV_PM_OPS,
	505	.of_match_table = lpc2k_i2c_match,
	506	},
	507	};
	508	module_platform_driver(i2c_lpc2k_driver);
	509
	510	MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
	511	MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
	512	MODULE_LICENSE("GPL");
	513	MODULE_ALIAS("platform:lpc2k-i2c");

drivers/i2c/busses/i2c-mt65xx.c+17−4

 #define I2C_DMA_START_EN		0x0001
 #define I2C_DMA_INT_FLAG_NONE		0x0000
 #define I2C_DMA_CLR_FLAG		0x0000
+#define I2C_DMA_HARD_RST		0x0002
 #define I2C_DEFAULT_SPEED		100000	/* hz */
 #define MAX_FS_MODE_SPEED		400000
 	OFFSET_INT_FLAG = 0x0,
 	OFFSET_INT_EN = 0x04,
 	OFFSET_EN = 0x08,
+	OFFSET_RST = 0x0c,
 	OFFSET_CON = 0x18,
 	OFFSET_TX_MEM_ADDR = 0x1c,
 	OFFSET_RX_MEM_ADDR = 0x20,
 		      I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 	writew(control_reg, i2c->base + OFFSET_CONTROL);
 	writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+	udelay(50);
+	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 }
 /*
 {
 	struct mtk_i2c *i2c = dev_id;
 	u16 restart_flag = 0;
+	u16 intr_stat;
 	if (i2c->dev_comp->auto_restart)
 		restart_flag = I2C_RS_TRANSFER;
-	i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
+	intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
-	writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
+	writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
-		| I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
-	complete(&i2c->msg_complete);
+	/*
+	 * when occurs ack error, i2c controller generate two interrupts
+	 * first is the ack error interrupt, then the complete interrupt
+	 * i2c->irq_stat need keep the two interrupt value.
+	 */
+	i2c->irq_stat |= intr_stat;
+	if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
+		complete(&i2c->msg_complete);
 	return IRQ_HANDLED;
 }

drivers/i2c/busses/i2c-omap.c+299−301

 	[OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
 };
-static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
+static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
 				      int reg, u16 val)
 {
-	writew_relaxed(val, i2c_dev->base +
+	writew_relaxed(val, omap->base +
-			(i2c_dev->regs[reg] << i2c_dev->reg_shift));
+			(omap->regs[reg] << omap->reg_shift));
 }
-static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
+static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
 {
-	return readw_relaxed(i2c_dev->base +
+	return readw_relaxed(omap->base +
-				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
+				(omap->regs[reg] << omap->reg_shift));
 }
-static void __omap_i2c_init(struct omap_i2c_dev *dev)
+static void __omap_i2c_init(struct omap_i2c_dev *omap)
 {
-	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
 	/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
-	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
+	omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
 	/* SCL low and high time values */
-	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
+	omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
-	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
+	omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
-	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
+	if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
-		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
+		omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
 	/* Take the I2C module out of reset: */
-	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+	omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 	/*
 	 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
 	 * Don't write to this register if the IE state is 0 as it can
 	 * cause deadlock.
 	 */
-	if (dev->iestate)
+	if (omap->iestate)
-		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
+		omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
 }
-static int omap_i2c_reset(struct omap_i2c_dev *dev)
+static int omap_i2c_reset(struct omap_i2c_dev *omap)
 {
 	unsigned long timeout;
 	u16 sysc;
-	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
+	if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
-		sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
+		sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
 		/* Disable I2C controller before soft reset */
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
+		omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
-			omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
+			omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
 				~(OMAP_I2C_CON_EN));
-		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
+		omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 		/* For some reason we need to set the EN bit before the
 		 * reset done bit gets set. */
 		timeout = jiffies + OMAP_I2C_TIMEOUT;
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+		omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
-		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
+		while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
 			 SYSS_RESETDONE_MASK)) {
 			if (time_after(jiffies, timeout)) {
-				dev_warn(dev->dev, "timeout waiting "
+				dev_warn(omap->dev, "timeout waiting "
 						"for controller reset\n");
 				return -ETIMEDOUT;
 			}
 		}
 		/* SYSC register is cleared by the reset; rewrite it */
-		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
+		omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
-		if (dev->rev > OMAP_I2C_REV_ON_3430_3530) {
+		if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
 			/* Schedule I2C-bus monitoring on the next transfer */
-			dev->bb_valid = 0;
+			omap->bb_valid = 0;
 		}
 	}
 	return 0;
 }
-static int omap_i2c_init(struct omap_i2c_dev *dev)
+static int omap_i2c_init(struct omap_i2c_dev *omap)
 {
 	u16 psc = 0, scll = 0, sclh = 0;
 	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 	unsigned long internal_clk = 0;
 	struct clk *fclk;
-	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
+	if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
 		/*
 		 * Enabling all wakup sources to stop I2C freezing on
 		 * WFI instruction.
 		 * REVISIT: Some wkup sources might not be needed.
 		 */
-		dev->westate = OMAP_I2C_WE_ALL;
+		omap->westate = OMAP_I2C_WE_ALL;
 	}
-	if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
+	if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
 		/*
 		 * The I2C functional clock is the armxor_ck, so there's
 		 * no need to get "armxor_ck" separately.  Now, if OMAP2420
 		 * always returns 12MHz for the functional clock, we can
 		 * do this bit unconditionally.
 		 */
-		fclk = clk_get(dev->dev, "fck");
+		fclk = clk_get(omap->dev, "fck");
 		fclk_rate = clk_get_rate(fclk);
 		clk_put(fclk);
 			psc = fclk_rate / 12000000;
 	}
-	if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
+	if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
 		/*
 		 * HSI2C controller internal clk rate should be 19.2 Mhz for
 		 * to get longer filter period for better noise suppression.
 		 * The filter is iclk (fclk for HS) period.
 		 */
-		if (dev->speed > 400 ||
+		if (omap->speed > 400 ||
-			       dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
+			       omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
 			internal_clk = 19200;
-		else if (dev->speed > 100)
+		else if (omap->speed > 100)
 			internal_clk = 9600;
 		else
 			internal_clk = 4000;
-		fclk = clk_get(dev->dev, "fck");
+		fclk = clk_get(omap->dev, "fck");
 		fclk_rate = clk_get_rate(fclk) / 1000;
 		clk_put(fclk);
 		psc = psc - 1;
 		/* If configured for High Speed */
-		if (dev->speed > 400) {
+		if (omap->speed > 400) {
 			unsigned long scl;
 			/* For first phase of HS mode */
 			fssclh = (scl / 3) - 5;
 			/* For second phase of HS mode */
-			scl = fclk_rate / dev->speed;
+			scl = fclk_rate / omap->speed;
 			hsscll = scl - (scl / 3) - 7;
 			hssclh = (scl / 3) - 5;
-		} else if (dev->speed > 100) {
+		} else if (omap->speed > 100) {
 			unsigned long scl;
 			/* Fast mode */
-			scl = internal_clk / dev->speed;
+			scl = internal_clk / omap->speed;
 			fsscll = scl - (scl / 3) - 7;
 			fssclh = (scl / 3) - 5;
 		} else {
 			/* Standard mode */
-			fsscll = internal_clk / (dev->speed * 2) - 7;
+			fsscll = internal_clk / (omap->speed * 2) - 7;
-			fssclh = internal_clk / (dev->speed * 2) - 5;
+			fssclh = internal_clk / (omap->speed * 2) - 5;
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 		fclk_rate /= (psc + 1) * 1000;
 		if (psc > 2)
 			psc = 2;
-		scll = fclk_rate / (dev->speed * 2) - 7 + psc;
+		scll = fclk_rate / (omap->speed * 2) - 7 + psc;
-		sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
+		sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
 	}
-	dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
+	omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 			OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
-			OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
+			OMAP_I2C_IE_AL)  | ((omap->fifo_size) ?
 				(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
-	dev->pscstate = psc;
+	omap->pscstate = psc;
-	dev->scllstate = scll;
+	omap->scllstate = scll;
-	dev->sclhstate = sclh;
+	omap->sclhstate = sclh;
-	if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) {
+	if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
 		/* Not implemented */
-		dev->bb_valid = 1;
+		omap->bb_valid = 1;
 	}
-	__omap_i2c_init(dev);
+	__omap_i2c_init(omap);
 	return 0;
 }
 /*
  * Waiting on Bus Busy
  */
-static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
+static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
 {
 	unsigned long timeout;
 	timeout = jiffies + OMAP_I2C_TIMEOUT;
-	while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
+	while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 		if (time_after(jiffies, timeout))
-			return i2c_recover_bus(&dev->adapter);
+			return i2c_recover_bus(&omap->adapter);
 		msleep(1);
 	}
  * 3. Any transfer started in the middle of another master's transfer
  *    results in unpredictable results and data corruption
  */
-static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev)
+static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
 {
 	unsigned long bus_free_timeout = 0;
 	unsigned long timeout;
 	int bus_free = 0;
 	u16 stat, systest;
-	if (dev->bb_valid)
+	if (omap->bb_valid)
 		return 0;
 	timeout = jiffies + OMAP_I2C_TIMEOUT;
 	while (1) {
-		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 		/*
 		 * We will see BB or BF event in a case IP had detected any
 		 * activity on the I2C bus. Now IP correctly tracks the bus
 		 * Otherwise, we must look signals on the bus to make
 		 * the right decision.
 		 */
-		systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
+		systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
 		if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
 		    (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
 			if (!bus_free) {
 		}
 		if (time_after(jiffies, timeout)) {
-			dev_warn(dev->dev, "timeout waiting for bus ready\n");
+			dev_warn(omap->dev, "timeout waiting for bus ready\n");
 			return -ETIMEDOUT;
 		}
 		msleep(1);
 	}
-	dev->bb_valid = 1;
+	omap->bb_valid = 1;
 	return 0;
 }
-static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
+static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
 {
 	u16		buf;
-	if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
+	if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
 		return;
 	/*
 	 * then we might use draining feature to transfer the remaining bytes.
 	 */
-	dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
+	omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
-	buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
+	buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
 	if (is_rx) {
 		/* Clear RX Threshold */
 		buf &= ~(0x3f << 8);
-		buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
+		buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
 	} else {
 		/* Clear TX Threshold */
 		buf &= ~0x3f;
-		buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
+		buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 	}
-	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
+	omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
-	if (dev->rev < OMAP_I2C_REV_ON_3630)
+	if (omap->rev < OMAP_I2C_REV_ON_3630)
-		dev->b_hw = 1; /* Enable hardware fixes */
+		omap->b_hw = 1; /* Enable hardware fixes */
 	/* calculate wakeup latency constraint for MPU */
-	if (dev->set_mpu_wkup_lat != NULL)
+	if (omap->set_mpu_wkup_lat != NULL)
-		dev->latency = (1000000 * dev->threshold) /
+		omap->latency = (1000000 * omap->threshold) /
-			(1000 * dev->speed / 8);
+			(1000 * omap->speed / 8);
 }
 /*
 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 			     struct i2c_msg *msg, int stop)
 {
-	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
+	struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
 	unsigned long timeout;
 	u16 w;
-	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
+	dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 		msg->addr, msg->len, msg->flags, stop);
 	if (msg->len == 0)
 		return -EINVAL;
-	dev->receiver = !!(msg->flags & I2C_M_RD);
+	omap->receiver = !!(msg->flags & I2C_M_RD);
-	omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
+	omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
-	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
+	omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
 	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
-	dev->buf = msg->buf;
+	omap->buf = msg->buf;
-	dev->buf_len = msg->len;
+	omap->buf_len = msg->len;
-	/* make sure writes to dev->buf_len are ordered */
+	/* make sure writes to omap->buf_len are ordered */
 	barrier();
-	omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
+	omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
 	/* Clear the FIFO Buffers */
-	w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
+	w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
 	w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
-	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
+	omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
-	reinit_completion(&dev->cmd_complete);
+	reinit_completion(&omap->cmd_complete);
-	dev->cmd_err = 0;
+	omap->cmd_err = 0;
 	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 	/* High speed configuration */
-	if (dev->speed > 400)
+	if (omap->speed > 400)
 		w |= OMAP_I2C_CON_OPMODE_HS;
 	if (msg->flags & I2C_M_STOP)
 	if (!(msg->flags & I2C_M_RD))
 		w |= OMAP_I2C_CON_TRX;
-	if (!dev->b_hw && stop)
+	if (!omap->b_hw && stop)
 		w |= OMAP_I2C_CON_STP;
 	/*
 	 * NOTE: STAT_BB bit could became 1 here if another master occupy
 	 * the bus. IP successfully complete transfer when the bus will be
 	 * free again (BB reset to 0).
 	 */
-	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
+	omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
 	/*
 	 * Don't write stt and stp together on some hardware.
 	 */
-	if (dev->b_hw && stop) {
+	if (omap->b_hw && stop) {
 		unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
-		u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
+		u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
 		while (con & OMAP_I2C_CON_STT) {
-			con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
+			con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
 			/* Let the user know if i2c is in a bad state */
 			if (time_after(jiffies, delay)) {
-				dev_err(dev->dev, "controller timed out "
+				dev_err(omap->dev, "controller timed out "
 				"waiting for start condition to finish\n");
 				return -ETIMEDOUT;
 			}
 		w |= OMAP_I2C_CON_STP;
 		w &= ~OMAP_I2C_CON_STT;
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
+		omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
 	}
 	/*
 	 * REVISIT: We should abort the transfer on signals, but the bus goes
 	 * into arbitration and we're currently unable to recover from it.
 	 */
-	timeout = wait_for_completion_timeout(&dev->cmd_complete,
+	timeout = wait_for_completion_timeout(&omap->cmd_complete,
 						OMAP_I2C_TIMEOUT);
 	if (timeout == 0) {
-		dev_err(dev->dev, "controller timed out\n");
+		dev_err(omap->dev, "controller timed out\n");
-		omap_i2c_reset(dev);
+		omap_i2c_reset(omap);
-		__omap_i2c_init(dev);
+		__omap_i2c_init(omap);
 		return -ETIMEDOUT;
 	}
-	if (likely(!dev->cmd_err))
+	if (likely(!omap->cmd_err))
 		return 0;
 	/* We have an error */
-	if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
+	if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
-		omap_i2c_reset(dev);
+		omap_i2c_reset(omap);
-		__omap_i2c_init(dev);
+		__omap_i2c_init(omap);
 		return -EIO;
 	}
-	if (dev->cmd_err & OMAP_I2C_STAT_AL)
+	if (omap->cmd_err & OMAP_I2C_STAT_AL)
 		return -EAGAIN;
-	if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
+	if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
 		if (msg->flags & I2C_M_IGNORE_NAK)
 			return 0;
-		w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
+		w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
 		w |= OMAP_I2C_CON_STP;
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
+		omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
 		return -EREMOTEIO;
 	}
 	return -EIO;
 static int
 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 {
-	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
+	struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
 	int i;
 	int r;
-	r = pm_runtime_get_sync(dev->dev);
+	r = pm_runtime_get_sync(omap->dev);
 	if (r < 0)
 		goto out;
-	r = omap_i2c_wait_for_bb_valid(dev);
+	r = omap_i2c_wait_for_bb_valid(omap);
 	if (r < 0)
 		goto out;
-	r = omap_i2c_wait_for_bb(dev);
+	r = omap_i2c_wait_for_bb(omap);
 	if (r < 0)
 		goto out;
-	if (dev->set_mpu_wkup_lat != NULL)
+	if (omap->set_mpu_wkup_lat != NULL)
-		dev->set_mpu_wkup_lat(dev->dev, dev->latency);
+		omap->set_mpu_wkup_lat(omap->dev, omap->latency);
 	for (i = 0; i < num; i++) {
 		r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 	if (r == 0)
 		r = num;
-	omap_i2c_wait_for_bb(dev);
+	omap_i2c_wait_for_bb(omap);
-	if (dev->set_mpu_wkup_lat != NULL)
+	if (omap->set_mpu_wkup_lat != NULL)
-		dev->set_mpu_wkup_lat(dev->dev, -1);
+		omap->set_mpu_wkup_lat(omap->dev, -1);
 out:
-	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_mark_last_busy(omap->dev);
-	pm_runtime_put_autosuspend(dev->dev);
+	pm_runtime_put_autosuspend(omap->dev);
 	return r;
 }
 }
 static inline void
-omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
+omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
 {
-	dev->cmd_err |= err;
+	omap->cmd_err |= err;
-	complete(&dev->cmd_complete);
+	complete(&omap->cmd_complete);
 }
 static inline void
-omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
+omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
 {
-	omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
+	omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
 }
-static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
+static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
 {
 	/*
 	 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 	 */
 	if (stat & OMAP_I2C_STAT_RDR) {
 		/* Step 1: If RDR is set, clear it */
-		omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
+		omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
 		/* Step 2: */
-		if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
+		if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
 						& OMAP_I2C_STAT_BB)) {
 			/* Step 3: */
-			if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
+			if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
 						& OMAP_I2C_STAT_RDR) {
-				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
+				omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
-				dev_dbg(dev->dev, "RDR when bus is busy.\n");
+				dev_dbg(omap->dev, "RDR when bus is busy.\n");
 			}
 		}
 static irqreturn_t
 omap_i2c_omap1_isr(int this_irq, void *dev_id)
 {
-	struct omap_i2c_dev *dev = dev_id;
+	struct omap_i2c_dev *omap = dev_id;
 	u16 iv, w;
-	if (pm_runtime_suspended(dev->dev))
+	if (pm_runtime_suspended(omap->dev))
 		return IRQ_NONE;
-	iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
+	iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
 	switch (iv) {
 	case 0x00:	/* None */
 		break;
 	case 0x01:	/* Arbitration lost */
-		dev_err(dev->dev, "Arbitration lost\n");
+		dev_err(omap->dev, "Arbitration lost\n");
-		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
+		omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
 		break;
 	case 0x02:	/* No acknowledgement */
-		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
+		omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
+		omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 		break;
 	case 0x03:	/* Register access ready */
-		omap_i2c_complete_cmd(dev, 0);
+		omap_i2c_complete_cmd(omap, 0);
 		break;
 	case 0x04:	/* Receive data ready */
-		if (dev->buf_len) {
+		if (omap->buf_len) {
-			w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+			w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
-			*dev->buf++ = w;
+			*omap->buf++ = w;
-			dev->buf_len--;
+			omap->buf_len--;
-			if (dev->buf_len) {
+			if (omap->buf_len) {
-				*dev->buf++ = w >> 8;
+				*omap->buf++ = w >> 8;
-				dev->buf_len--;
+				omap->buf_len--;
 			}
 		} else
-			dev_err(dev->dev, "RRDY IRQ while no data requested\n");
+			dev_err(omap->dev, "RRDY IRQ while no data requested\n");
 		break;
 	case 0x05:	/* Transmit data ready */
-		if (dev->buf_len) {
+		if (omap->buf_len) {
-			w = *dev->buf++;
+			w = *omap->buf++;
-			dev->buf_len--;
+			omap->buf_len--;
-			if (dev->buf_len) {
+			if (omap->buf_len) {
-				w |= *dev->buf++ << 8;
+				w |= *omap->buf++ << 8;
-				dev->buf_len--;
+				omap->buf_len--;
 			}
-			omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
+			omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
 		} else
-			dev_err(dev->dev, "XRDY IRQ while no data to send\n");
+			dev_err(omap->dev, "XRDY IRQ while no data to send\n");
 		break;
 	default:
 		return IRQ_NONE;
  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
  * them from the memory to the I2C interface.
  */
-static int errata_omap3_i462(struct omap_i2c_dev *dev)
+static int errata_omap3_i462(struct omap_i2c_dev *omap)
 {
 	unsigned long timeout = 10000;
 	u16 stat;
 	do {
-		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 		if (stat & OMAP_I2C_STAT_XUDF)
 			break;
 		if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
+			omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
 			if (stat & OMAP_I2C_STAT_NACK) {
-				dev->cmd_err |= OMAP_I2C_STAT_NACK;
+				omap->cmd_err |= OMAP_I2C_STAT_NACK;
-				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+				omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
 			}
 			if (stat & OMAP_I2C_STAT_AL) {
-				dev_err(dev->dev, "Arbitration lost\n");
+				dev_err(omap->dev, "Arbitration lost\n");
-				dev->cmd_err |= OMAP_I2C_STAT_AL;
+				omap->cmd_err |= OMAP_I2C_STAT_AL;
-				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
+				omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
 			}
 			return -EIO;
 	} while (--timeout);
 	if (!timeout) {
-		dev_err(dev->dev, "timeout waiting on XUDF bit\n");
+		dev_err(omap->dev, "timeout waiting on XUDF bit\n");
 		return 0;
 	}
 	return 0;
 }
-static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
+static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
 		bool is_rdr)
 {
 	u16		w;
 	while (num_bytes--) {
-		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+		w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
-		*dev->buf++ = w;
+		*omap->buf++ = w;
-		dev->buf_len--;
+		omap->buf_len--;
 		/*
 		 * Data reg in 2430, omap3 and
 		 * omap4 is 8 bit wide
 		 */
-		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
+		if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
-			*dev->buf++ = w >> 8;
+			*omap->buf++ = w >> 8;
-			dev->buf_len--;
+			omap->buf_len--;
 		}
 	}
 }
-static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
+static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
 		bool is_xdr)
 {
 	u16		w;
 	while (num_bytes--) {
-		w = *dev->buf++;
+		w = *omap->buf++;
-		dev->buf_len--;
+		omap->buf_len--;
 		/*
 		 * Data reg in 2430, omap3 and
 		 * omap4 is 8 bit wide
 		 */
-		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
+		if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
-			w |= *dev->buf++ << 8;
+			w |= *omap->buf++ << 8;
-			dev->buf_len--;
+			omap->buf_len--;
 		}
-		if (dev->errata & I2C_OMAP_ERRATA_I462) {
+		if (omap->errata & I2C_OMAP_ERRATA_I462) {
 			int ret;
-			ret = errata_omap3_i462(dev);
+			ret = errata_omap3_i462(omap);
 			if (ret < 0)
 				return ret;
 		}
-		omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
+		omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
 	}
 	return 0;
 static irqreturn_t
 omap_i2c_isr(int irq, void *dev_id)
 {
-	struct omap_i2c_dev *dev = dev_id;
+	struct omap_i2c_dev *omap = dev_id;
 	irqreturn_t ret = IRQ_HANDLED;
 	u16 mask;
 	u16 stat;
-	spin_lock(&dev->lock);
+	spin_lock(&omap->lock);
-	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+	mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
-	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+	stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 	if (stat & mask)
 		ret = IRQ_WAKE_THREAD;
-	spin_unlock(&dev->lock);
+	spin_unlock(&omap->lock);
 	return ret;
 }
 static irqreturn_t
 omap_i2c_isr_thread(int this_irq, void *dev_id)
 {
-	struct omap_i2c_dev *dev = dev_id;
+	struct omap_i2c_dev *omap = dev_id;
 	unsigned long flags;
 	u16 bits;
 	u16 stat;
 	int err = 0, count = 0;
-	spin_lock_irqsave(&dev->lock, flags);
+	spin_lock_irqsave(&omap->lock, flags);
 	do {
-		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+		bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
-		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 		stat &= bits;
 		/* If we're in receiver mode, ignore XDR/XRDY */
-		if (dev->receiver)
+		if (omap->receiver)
 			stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
 		else
 			stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
 			goto out;
 		}
-		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
+		dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
-			dev_warn(dev->dev, "Too much work in one IRQ\n");
+			dev_warn(omap->dev, "Too much work in one IRQ\n");
 			break;
 		}
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
 		}
 		if (stat & OMAP_I2C_STAT_AL) {
-			dev_err(dev->dev, "Arbitration lost\n");
+			dev_err(omap->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
 		}
 		/*
 		 * ProDB0017052: Clear ARDY bit twice
 		 */
 		if (stat & OMAP_I2C_STAT_ARDY)
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
 		if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 					OMAP_I2C_STAT_AL)) {
-			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
+			omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
 						OMAP_I2C_STAT_RDR |
 						OMAP_I2C_STAT_XRDY |
 						OMAP_I2C_STAT_XDR |
 		if (stat & OMAP_I2C_STAT_RDR) {
 			u8 num_bytes = 1;
-			if (dev->fifo_size)
+			if (omap->fifo_size)
-				num_bytes = dev->buf_len;
+				num_bytes = omap->buf_len;
-			if (dev->errata & I2C_OMAP_ERRATA_I207) {
+			if (omap->errata & I2C_OMAP_ERRATA_I207) {
-				i2c_omap_errata_i207(dev, stat);
+				i2c_omap_errata_i207(omap, stat);
-				num_bytes = (omap_i2c_read_reg(dev,
+				num_bytes = (omap_i2c_read_reg(omap,
 					OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
 			}
-			omap_i2c_receive_data(dev, num_bytes, true);
+			omap_i2c_receive_data(omap, num_bytes, true);
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
 			continue;
 		}
 		if (stat & OMAP_I2C_STAT_RRDY) {
 			u8 num_bytes = 1;
-			if (dev->threshold)
+			if (omap->threshold)
-				num_bytes = dev->threshold;
+				num_bytes = omap->threshold;
-			omap_i2c_receive_data(dev, num_bytes, false);
+			omap_i2c_receive_data(omap, num_bytes, false);
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
 			continue;
 		}
 			u8 num_bytes = 1;
 			int ret;
-			if (dev->fifo_size)
+			if (omap->fifo_size)
-				num_bytes = dev->buf_len;
+				num_bytes = omap->buf_len;
-			ret = omap_i2c_transmit_data(dev, num_bytes, true);
+			ret = omap_i2c_transmit_data(omap, num_bytes, true);
 			if (ret < 0)
 				break;
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
 			continue;
 		}
 			u8 num_bytes = 1;
 			int ret;
-			if (dev->threshold)
+			if (omap->threshold)
-				num_bytes = dev->threshold;
+				num_bytes = omap->threshold;
-			ret = omap_i2c_transmit_data(dev, num_bytes, false);
+			ret = omap_i2c_transmit_data(omap, num_bytes, false);
 			if (ret < 0)
 				break;
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
 			continue;
 		}
 		if (stat & OMAP_I2C_STAT_ROVR) {
-			dev_err(dev->dev, "Receive overrun\n");
+			dev_err(omap->dev, "Receive overrun\n");
 			err |= OMAP_I2C_STAT_ROVR;
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
 			break;
 		}
 		if (stat & OMAP_I2C_STAT_XUDF) {
-			dev_err(dev->dev, "Transmit underflow\n");
+			dev_err(omap->dev, "Transmit underflow\n");
 			err |= OMAP_I2C_STAT_XUDF;
-			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
+			omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
 			break;
 		}
 	} while (stat);
-	omap_i2c_complete_cmd(dev, err);
+	omap_i2c_complete_cmd(omap, err);
 out:
-	spin_unlock_irqrestore(&dev->lock, flags);
+	spin_unlock_irqrestore(&omap->lock, flags);
 	return IRQ_HANDLED;
 }
 static int
 omap_i2c_probe(struct platform_device *pdev)
 {
-	struct omap_i2c_dev	*dev;
+	struct omap_i2c_dev	*omap;
 	struct i2c_adapter	*adap;
 	struct resource		*mem;
 	const struct omap_i2c_bus_platform_data *pdata =
 		return irq;
 	}
-	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
+	omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
-	if (!dev)
+	if (!omap)
 		return -ENOMEM;
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	dev->base = devm_ioremap_resource(&pdev->dev, mem);
+	omap->base = devm_ioremap_resource(&pdev->dev, mem);
-	if (IS_ERR(dev->base))
+	if (IS_ERR(omap->base))
-		return PTR_ERR(dev->base);
+		return PTR_ERR(omap->base);
 	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
 	if (match) {
 		u32 freq = 100000; /* default to 100000 Hz */
 		pdata = match->data;
-		dev->flags = pdata->flags;
+		omap->flags = pdata->flags;
 		of_property_read_u32(node, "clock-frequency", &freq);
 		/* convert DT freq value in Hz into kHz for speed */
-		dev->speed = freq / 1000;
+		omap->speed = freq / 1000;
 	} else if (pdata != NULL) {
-		dev->speed = pdata->clkrate;
+		omap->speed = pdata->clkrate;
-		dev->flags = pdata->flags;
+		omap->flags = pdata->flags;
-		dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
+		omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
 	}
-	dev->dev = &pdev->dev;
+	omap->dev = &pdev->dev;
-	dev->irq = irq;
+	omap->irq = irq;
-	spin_lock_init(&dev->lock);
+	spin_lock_init(&omap->lock);
-	platform_set_drvdata(pdev, dev);
+	platform_set_drvdata(pdev, omap);
-	init_completion(&dev->cmd_complete);
+	init_completion(&omap->cmd_complete);
-	dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
+	omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
-	pm_runtime_enable(dev->dev);
+	pm_runtime_enable(omap->dev);
-	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
+	pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
-	pm_runtime_use_autosuspend(dev->dev);
+	pm_runtime_use_autosuspend(omap->dev);
-	r = pm_runtime_get_sync(dev->dev);
+	r = pm_runtime_get_sync(omap->dev);
 	if (r < 0)
 		goto err_free_mem;
 	 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
 	 * readw_relaxed is done.
 	 */
-	rev = readw_relaxed(dev->base + 0x04);
+	rev = readw_relaxed(omap->base + 0x04);
-	dev->scheme = OMAP_I2C_SCHEME(rev);
+	omap->scheme = OMAP_I2C_SCHEME(rev);
-	switch (dev->scheme) {
+	switch (omap->scheme) {
 	case OMAP_I2C_SCHEME_0:
-		dev->regs = (u8 *)reg_map_ip_v1;
+		omap->regs = (u8 *)reg_map_ip_v1;
-		dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
+		omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
-		minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
+		minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
-		major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
+		major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
 		break;
 	case OMAP_I2C_SCHEME_1:
 		/* FALLTHROUGH */
 	default:
-		dev->regs = (u8 *)reg_map_ip_v2;
+		omap->regs = (u8 *)reg_map_ip_v2;
 		rev = (rev << 16) |
-			omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
+			omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
 		minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
 		major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
-		dev->rev = rev;
+		omap->rev = rev;
 	}
-	dev->errata = 0;
+	omap->errata = 0;
-	if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
+	if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
-			dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
+			omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
-		dev->errata |= I2C_OMAP_ERRATA_I207;
+		omap->errata |= I2C_OMAP_ERRATA_I207;
-	if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
+	if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
-		dev->errata |= I2C_OMAP_ERRATA_I462;
+		omap->errata |= I2C_OMAP_ERRATA_I462;
-	if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
+	if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
 		u16 s;
 		/* Set up the fifo size - Get total size */
-		s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
+		s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
-		dev->fifo_size = 0x8 << s;
+		omap->fifo_size = 0x8 << s;
 		/*
 		 * Set up notification threshold as half the total available
 		 * call back latencies.
 		 */
-		dev->fifo_size = (dev->fifo_size / 2);
+		omap->fifo_size = (omap->fifo_size / 2);
-		if (dev->rev < OMAP_I2C_REV_ON_3630)
+		if (omap->rev < OMAP_I2C_REV_ON_3630)
-			dev->b_hw = 1; /* Enable hardware fixes */
+			omap->b_hw = 1; /* Enable hardware fixes */
 		/* calculate wakeup latency constraint for MPU */
-		if (dev->set_mpu_wkup_lat != NULL)
+		if (omap->set_mpu_wkup_lat != NULL)
-			dev->latency = (1000000 * dev->fifo_size) /
+			omap->latency = (1000000 * omap->fifo_size) /
-				       (1000 * dev->speed / 8);
+				       (1000 * omap->speed / 8);
 	}
 	/* reset ASAP, clearing any IRQs */
-	omap_i2c_init(dev);
+	omap_i2c_init(omap);
-	if (dev->rev < OMAP_I2C_OMAP1_REV_2)
+	if (omap->rev < OMAP_I2C_OMAP1_REV_2)
-		r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
+		r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
-				IRQF_NO_SUSPEND, pdev->name, dev);
+				IRQF_NO_SUSPEND, pdev->name, omap);
 	else
-		r = devm_request_threaded_irq(&pdev->dev, dev->irq,
+		r = devm_request_threaded_irq(&pdev->dev, omap->irq,
 				omap_i2c_isr, omap_i2c_isr_thread,
 				IRQF_NO_SUSPEND | IRQF_ONESHOT,
-				pdev->name, dev);
+				pdev->name, omap);
 	if (r) {
-		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
+		dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
 		goto err_unuse_clocks;
 	}
-	adap = &dev->adapter;
+	adap = &omap->adapter;
-	i2c_set_adapdata(adap, dev);
+	i2c_set_adapdata(adap, omap);
 	adap->owner = THIS_MODULE;
 	adap->class = I2C_CLASS_DEPRECATED;
 	strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 	adap->nr = pdev->id;
 	r = i2c_add_numbered_adapter(adap);
 	if (r) {
-		dev_err(dev->dev, "failure adding adapter\n");
+		dev_err(omap->dev, "failure adding adapter\n");
 		goto err_unuse_clocks;
 	}
-	dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
+	dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
-		 major, minor, dev->speed);
+		 major, minor, omap->speed);
-	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_mark_last_busy(omap->dev);
-	pm_runtime_put_autosuspend(dev->dev);
+	pm_runtime_put_autosuspend(omap->dev);
 	return 0;
 err_unuse_clocks:
-	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
-	pm_runtime_put(dev->dev);
+	pm_runtime_put(omap->dev);
 	pm_runtime_disable(&pdev->dev);
 err_free_mem:
 static int omap_i2c_remove(struct platform_device *pdev)
 {
-	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
+	struct omap_i2c_dev	*omap = platform_get_drvdata(pdev);
 	int ret;
-	i2c_del_adapter(&dev->adapter);
+	i2c_del_adapter(&omap->adapter);
 	ret = pm_runtime_get_sync(&pdev->dev);
 	if (ret < 0)
 		return ret;
-	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int omap_i2c_runtime_suspend(struct device *dev)
 {
-	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_i2c_dev *omap = dev_get_drvdata(dev);
-	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
-	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
+	omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
-	if (_dev->scheme == OMAP_I2C_SCHEME_0)
+	if (omap->scheme == OMAP_I2C_SCHEME_0)
-		omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+		omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
 	else
-		omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
+		omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
 				   OMAP_I2C_IP_V2_INTERRUPTS_MASK);
-	if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
+	if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
-		omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
+		omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
 	} else {
-		omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
+		omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
 		/* Flush posted write */
-		omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
+		omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 	}
 	pinctrl_pm_select_sleep_state(dev);
 static int omap_i2c_runtime_resume(struct device *dev)
 {
-	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_i2c_dev *omap = dev_get_drvdata(dev);
-	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
 	pinctrl_pm_select_default_state(dev);
-	if (!_dev->regs)
+	if (!omap->regs)
 		return 0;
-	__omap_i2c_init(_dev);
+	__omap_i2c_init(omap);
 	return 0;
 }

drivers/i2c/busses/i2c-parport.c+13−12

    GNU General Public License for more details.
  * ------------------------------------------------------------------------ */
+#define pr_fmt(fmt) "i2c-parport: " fmt
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 			break;
 	}
 	if (i == MAX_DEVICE) {
-		pr_debug("i2c-parport: Not using parport%d.\n", port->number);
+		pr_debug("Not using parport%d.\n", port->number);
 		return;
 	}
 	adapter = kzalloc(sizeof(struct i2c_par), GFP_KERNEL);
-	if (adapter == NULL) {
+	if (!adapter)
-		printk(KERN_ERR "i2c-parport: Failed to kzalloc\n");
 		return;
-	}
 	memset(&i2c_parport_cb, 0, sizeof(i2c_parport_cb));
 	i2c_parport_cb.flags = PARPORT_FLAG_EXCL;
 	i2c_parport_cb.irq_func = i2c_parport_irq;
 	i2c_parport_cb.private = adapter;
-	pr_debug("i2c-parport: attaching to %s\n", port->name);
+	pr_debug("attaching to %s\n", port->name);
 	parport_disable_irq(port);
 	adapter->pdev = parport_register_dev_model(port, "i2c-parport",
 						   &i2c_parport_cb, i);
 	if (!adapter->pdev) {
-		printk(KERN_ERR "i2c-parport: Unable to register with parport\n");
+		pr_err("Unable to register with parport\n");
 		goto err_free;
 	}
 	adapter->adapter.dev.parent = port->physport->dev;
 	if (parport_claim_or_block(adapter->pdev) < 0) {
-		printk(KERN_ERR "i2c-parport: Could not claim parallel port\n");
+		dev_err(&adapter->pdev->dev,
+			"Could not claim parallel port\n");
 		goto err_unregister;
 	}
 	}
 	if (i2c_bit_add_bus(&adapter->adapter) < 0) {
-		printk(KERN_ERR "i2c-parport: Unable to register with I2C\n");
+		dev_err(&adapter->pdev->dev, "Unable to register with I2C\n");
 		goto err_unregister;
 	}
 		if (adapter->ara)
 			parport_enable_irq(port);
 		else
-			printk(KERN_WARNING "i2c-parport: Failed to register "
+			dev_warn(&adapter->pdev->dev,
-			       "ARA client\n");
+				 "Failed to register ARA client\n");
 	}
 	/* Add the new adapter to the list */
 static int __init i2c_parport_init(void)
 {
 	if (type < 0) {
-		printk(KERN_WARNING "i2c-parport: adapter type unspecified\n");
+		pr_warn("adapter type unspecified\n");
 		return -ENODEV;
 	}
 	if (type >= ARRAY_SIZE(adapter_parm)) {
-		printk(KERN_WARNING "i2c-parport: invalid type (%d)\n", type);
+		pr_warn("invalid type (%d)\n", type);
 		return -ENODEV;
 	}

drivers/i2c/busses/i2c-parport.h+8−0

 		.getsda	= { 0x80, PORT_STAT, 1 },
 		.init	= { 0x04, PORT_DATA, 1 },
 	},
+	/* type 8: VCT-jig */
+	{
+		.setsda	= { 0x04, PORT_DATA, 1 },
+		.setscl	= { 0x01, PORT_DATA, 1 },
+		.getsda	= { 0x40, PORT_STAT, 0 },
+		.getscl	= { 0x80, PORT_STAT, 1 },
+	},
 };
 static int type = -1;
 	" 5 = ADM1025, ADM1030 and ADM1031 evaluation boards\n"
 	" 6 = Barco LPT->DVI (K5800236) adapter\n"
 	" 7 = One For All JP1 parallel port adapter\n"
+	" 8 = VCT-jig\n"
 );

drivers/i2c/busses/i2c-pxa.c+50−62

@@ -132,6 +132,7 @@ struct pxa_i2c { · 131 unmodified lines
132	unsigned int msg_idx;	132	unsigned int msg_idx;
133	unsigned int msg_ptr;	133	unsigned int msg_ptr;
134	unsigned int slave_addr;	134	unsigned int slave_addr;
		135	unsigned int req_slave_addr;
135		136
136	struct i2c_adapter adap;	137	struct i2c_adapter adap;
137	struct clk *clk;	138	struct clk *clk;
@@ -253,15 +254,20 @@ static void i2c_pxa_show_state(struct pxa_i2c i2c, int lno, const char fname) · 115 unmodified lines
253	static void i2c_pxa_scream_blue_murder(struct pxa_i2c i2c, const char why)	254	static void i2c_pxa_scream_blue_murder(struct pxa_i2c i2c, const char why)
254	{	255	{
255	unsigned int i;	256	unsigned int i;
256	printk(KERN_ERR "i2c: error: %s\n", why);	257	struct device *dev = &i2c->adap.dev;
257	printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",	258
		259	dev_err(dev, "slave_0x%x error: %s\n",
		260	i2c->req_slave_addr >> 1, why);
		261	dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
258	i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);	262	i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
259	printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",	263	dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
260	readl(_ICR(i2c)), readl(_ISR(i2c)));	264	readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
261	printk(KERN_DEBUG "i2c: log: ");	265	readl(_ISR(i2c)));
		266	dev_dbg(dev, "log: ");
262	for (i = 0; i < i2c->irqlogidx; i++)	267	for (i = 0; i < i2c->irqlogidx; i++)
263	printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);	268	pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
264	printk("\n");	269
		270	pr_debug("\n");
265	}	271	}
266		272
267	#else /* ifdef DEBUG */	273	#else /* ifdef DEBUG */
@@ -459,7 +465,7 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c) · 191 unmodified lines
459	writel(I2C_ISR_INIT, _ISR(i2c));	465	writel(I2C_ISR_INIT, _ISR(i2c));
460	writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));	466	writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
461		467
462	if (i2c->reg_isar)	468	if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
463	writel(i2c->slave_addr, _ISAR(i2c));	469	writel(i2c->slave_addr, _ISAR(i2c));
464		470
465	/* set control register values */	471	/* set control register values */
@@ -638,6 +644,7 @@ static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) · 172 unmodified lines
638	* Step 1: target slave address into IDBR	644	* Step 1: target slave address into IDBR
639	*/	645	*/
640	writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));	646	writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
		647	i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
641		648
642	/*	649	/*
643	* Step 2: initiate the write.	650	* Step 2: initiate the write.
@@ -745,8 +752,10 @@ static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, · 101 unmodified lines
745	ret = i2c->msg_idx;	752	ret = i2c->msg_idx;
746		753
747	out:	754	out:
748	if (timeout == 0)	755	if (timeout == 0) {
749	i2c_pxa_scream_blue_murder(i2c, "timeout");	756	i2c_pxa_scream_blue_murder(i2c, "timeout");
		757	ret = I2C_RETRY;
		758	}
750		759
751	return ret;	760	return ret;
752	}	761	}
@@ -949,6 +958,7 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) · 196 unmodified lines
949	* Write the next address.	958	* Write the next address.
950	*/	959	*/
951	writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));	960	writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
		961	i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
952		962
953	/*	963	/*
954	* And trigger a repeated start, and send the byte.	964	* And trigger a repeated start, and send the byte.
@@ -1114,7 +1124,9 @@ static int i2c_pxa_probe_dt(struct platform_device pdev, struct pxa_i2c i2c, · 159 unmodified lines
1114	i2c->use_pio = 1;	1124	i2c->use_pio = 1;
1115	if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))	1125	if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1116	i2c->fast_mode = 1;	1126	i2c->fast_mode = 1;
1117	*i2c_types = (u32)(of_id->data);	1127
		1128	*i2c_types = (enum pxa_i2c_types)(of_id->data);
		1129
1118	return 0;	1130	return 0;
1119	}	1131	}
1120		1132
@@ -1146,10 +1158,19 @@ static int i2c_pxa_probe(struct platform_device *dev) · 25 unmodified lines
1146	struct resource *res = NULL;	1158	struct resource *res = NULL;
1147	int ret, irq;	1159	int ret, irq;
1148		1160
1149	i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);	1161	i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1150	if (!i2c) {	1162	if (!i2c)
1151	ret = -ENOMEM;	1163	return -ENOMEM;
1152	goto emalloc;	1164
		1165	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
		1166	i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
		1167	if (IS_ERR(i2c->reg_base))
		1168	return PTR_ERR(i2c->reg_base);
		1169
		1170	irq = platform_get_irq(dev, 0);
		1171	if (irq < 0) {
		1172	dev_err(&dev->dev, "no irq resource: %d\n", irq);
		1173	return irq;
1153	}	1174	}
1154		1175
1155	/* Default adapter num to device id; i2c_pxa_probe_dt can override. */	1176	/* Default adapter num to device id; i2c_pxa_probe_dt can override. */
@@ -1159,19 +1180,7 @@ static int i2c_pxa_probe(struct platform_device *dev) · 3 unmodified lines
1159	if (ret > 0)	1180	if (ret > 0)
1160	ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);	1181	ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1161	if (ret < 0)	1182	if (ret < 0)
1162	goto eclk;	1183	return ret;
1163
1164	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1165	irq = platform_get_irq(dev, 0);
1166	if (res == NULL \|\| irq < 0) {
1167	ret = -ENODEV;
1168	goto eclk;
1169	}
1170
1171	if (!request_mem_region(res->start, resource_size(res), res->name)) {
1172	ret = -ENOMEM;
1173	goto eclk;
1174	}
1175		1184
1176	i2c->adap.owner = THIS_MODULE;	1185	i2c->adap.owner = THIS_MODULE;
1177	i2c->adap.retries = 5;	1186	i2c->adap.retries = 5;
@@ -1181,16 +1190,10 @@ static int i2c_pxa_probe(struct platform_device *dev) · 3 unmodified lines
1181		1190
1182	strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));	1191	strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1183		1192
1184	i2c->clk = clk_get(&dev->dev, NULL);	1193	i2c->clk = devm_clk_get(&dev->dev, NULL);
1185	if (IS_ERR(i2c->clk)) {	1194	if (IS_ERR(i2c->clk)) {
1186	ret = PTR_ERR(i2c->clk);	1195	dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1187	goto eclk;	1196	return PTR_ERR(i2c->clk);
1188	}
1189
1190	i2c->reg_base = ioremap(res->start, resource_size(res));
1191	if (!i2c->reg_base) {
1192	ret = -EIO;
1193	goto eremap;
1194	}	1197	}
1195		1198
1196	i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;	1199	i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
@@ -1232,10 +1235,13 @@ static int i2c_pxa_probe(struct platform_device *dev) · 35 unmodified lines
1232	i2c->adap.algo = &i2c_pxa_pio_algorithm;	1235	i2c->adap.algo = &i2c_pxa_pio_algorithm;
1233	} else {	1236	} else {
1234	i2c->adap.algo = &i2c_pxa_algorithm;	1237	i2c->adap.algo = &i2c_pxa_algorithm;
1235	ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED,	1238	ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1236	dev_name(&dev->dev), i2c);	1239	IRQF_SHARED \| IRQF_NO_SUSPEND,
1237	if (ret)	1240	dev_name(&dev->dev), i2c);
		1241	if (ret) {
		1242	dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1238	goto ereqirq;	1243	goto ereqirq;
		1244	}
1239	}	1245	}
1240		1246
1241	i2c_pxa_reset(i2c);	1247	i2c_pxa_reset(i2c);
@@ -1248,33 +1254,22 @@ static int i2c_pxa_probe(struct platform_device *dev) · 6 unmodified lines
1248		1254
1249	ret = i2c_add_numbered_adapter(&i2c->adap);	1255	ret = i2c_add_numbered_adapter(&i2c->adap);
1250	if (ret < 0) {	1256	if (ret < 0) {
1251	printk(KERN_INFO "I2C: Failed to add bus\n");	1257	dev_err(&dev->dev, "failed to add bus: %d\n", ret);
1252	goto eadapt;	1258	goto ereqirq;
1253	}	1259	}
1254		1260
1255	platform_set_drvdata(dev, i2c);	1261	platform_set_drvdata(dev, i2c);
1256		1262
1257	#ifdef CONFIG_I2C_PXA_SLAVE	1263	#ifdef CONFIG_I2C_PXA_SLAVE
1258	printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",	1264	dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1259	dev_name(&i2c->adap.dev), i2c->slave_addr);	1265	i2c->slave_addr);
1260	#else	1266	#else
1261	printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",	1267	dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1262	dev_name(&i2c->adap.dev));
1263	#endif	1268	#endif
1264	return 0;	1269	return 0;
1265		1270
1266	eadapt:
1267	if (!i2c->use_pio)
1268	free_irq(irq, i2c);
1269	ereqirq:	1271	ereqirq:
1270	clk_disable_unprepare(i2c->clk);	1272	clk_disable_unprepare(i2c->clk);
1271	iounmap(i2c->reg_base);
1272	eremap:
1273	clk_put(i2c->clk);
1274	eclk:
1275	kfree(i2c);
1276	emalloc:
1277	release_mem_region(res->start, resource_size(res));
1278	return ret;	1273	return ret;
1279	}	1274	}
1280		1275
@@ -1283,15 +1278,8 @@ static int i2c_pxa_remove(struct platform_device *dev) · 2 unmodified lines
1283	struct pxa_i2c *i2c = platform_get_drvdata(dev);	1278	struct pxa_i2c *i2c = platform_get_drvdata(dev);
1284		1279
1285	i2c_del_adapter(&i2c->adap);	1280	i2c_del_adapter(&i2c->adap);
1286	if (!i2c->use_pio)
1287	free_irq(i2c->irq, i2c);
1288		1281
1289	clk_disable_unprepare(i2c->clk);	1282	clk_disable_unprepare(i2c->clk);
1290	clk_put(i2c->clk);
1291
1292	iounmap(i2c->reg_base);
1293	release_mem_region(i2c->iobase, i2c->iosize);
1294	kfree(i2c);
1295		1283
1296	return 0;	1284	return 0;
1297	}	1285	}

drivers/i2c/busses/i2c-tegra.c+50−2

 #define I2C_HEADER_CONTINUE_XFER		(1<<15)
 #define I2C_HEADER_MASTER_ADDR_SHIFT		12
 #define I2C_HEADER_SLAVE_ADDR_SHIFT		1
+#define I2C_CONFIG_LOAD				0x08C
+#define I2C_MSTR_CONFIG_LOAD			(1 << 0)
+#define I2C_SLV_CONFIG_LOAD			(1 << 1)
+#define I2C_TIMEOUT_CONFIG_LOAD			(1 << 2)
 /*
  * msg_end_type: The bus control which need to be send at end of transfer.
  * @MSG_END_STOP: Send stop pulse at end of transfer.
  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
  *		and earlier Socs has two clock sources i.e. div-clk and
  *		fast-clk.
+ * @has_config_load_reg: Has the config load register to load the new
+ *		configuration.
  * @clk_divisor_hs_mode: Clock divisor in HS mode.
  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
  *		applicable if there is no fast clock source i.e. single clock
 	bool has_continue_xfer_support;
 	bool has_per_pkt_xfer_complete_irq;
 	bool has_single_clk_source;
+	bool has_config_load_reg;
 	int clk_divisor_hs_mode;
 	int clk_divisor_std_fast_mode;
+	u16 clk_divisor_fast_plus_mode;
 };
 /**
 	size_t msg_buf_remaining;
 	int msg_read;
 	u32 bus_clk_rate;
+	u16 clk_divisor_non_hs_mode;
 	bool is_suspended;
 };
 	u32 val;
 	int err = 0;
 	u32 clk_divisor;
+	unsigned long timeout = jiffies + HZ;
 	err = tegra_i2c_clock_enable(i2c_dev);
 	if (err < 0) {
 	/* Make sure clock divisor programmed correctly */
 	clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
-	clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
+	clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 					I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 	i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 	if (tegra_i2c_flush_fifos(i2c_dev))
 		err = -ETIMEDOUT;
+	if (i2c_dev->hw->has_config_load_reg) {
+		i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
+		while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
+			if (time_after(jiffies, timeout)) {
+				dev_warn(i2c_dev->dev,
+					"timeout waiting for config load\n");
+				return -ETIMEDOUT;
+			}
+			msleep(1);
+		}
+	}
 	tegra_i2c_clock_disable(i2c_dev);
 	if (i2c_dev->irq_disabled) {
 	.has_single_clk_source = false,
 	.clk_divisor_hs_mode = 3,
 	.clk_divisor_std_fast_mode = 0,
+	.clk_divisor_fast_plus_mode = 0,
+	.has_config_load_reg = false,
 };
 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 	.has_single_clk_source = false,
 	.clk_divisor_hs_mode = 3,
 	.clk_divisor_std_fast_mode = 0,
+	.clk_divisor_fast_plus_mode = 0,
+	.has_config_load_reg = false,
 };
 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 	.has_single_clk_source = true,
 	.clk_divisor_hs_mode = 1,
 	.clk_divisor_std_fast_mode = 0x19,
+	.clk_divisor_fast_plus_mode = 0x10,
+	.has_config_load_reg = false,
+};
+static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
+	.has_continue_xfer_support = true,
+	.has_per_pkt_xfer_complete_irq = true,
+	.has_single_clk_source = true,
+	.clk_divisor_hs_mode = 1,
+	.clk_divisor_std_fast_mode = 0x19,
+	.clk_divisor_fast_plus_mode = 0x10,
+	.has_config_load_reg = true,
 };
 /* Match table for of_platform binding */
 static const struct of_device_id tegra_i2c_of_match[] = {
+	{ .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 	{ .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 	{ .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 	{ .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 		}
 	}
-	clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
+	i2c_dev->clk_divisor_non_hs_mode =
+			i2c_dev->hw->clk_divisor_std_fast_mode;
+	if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
+		(i2c_dev->bus_clk_rate == 1000000))
+		i2c_dev->clk_divisor_non_hs_mode =
+			i2c_dev->hw->clk_divisor_fast_plus_mode;
+	clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 	ret = clk_set_rate(i2c_dev->div_clk,
 			   i2c_dev->bus_clk_rate * clk_multiplier);
 	if (ret) {

drivers/i2c/busses/i2c-viperboard.c+5−5

@@ -391,11 +391,11 @@ static int vprbrd_i2c_probe(struct platform_device *pdev) · 390 unmodified lines
391	VPRBRD_USB_REQUEST_I2C_FREQ, VPRBRD_USB_TYPE_OUT,	391	VPRBRD_USB_REQUEST_I2C_FREQ, VPRBRD_USB_TYPE_OUT,
392	0x0000, 0x0000, &vb_i2c->bus_freq_param, 1,	392	0x0000, 0x0000, &vb_i2c->bus_freq_param, 1,
393	VPRBRD_USB_TIMEOUT_MS);	393	VPRBRD_USB_TIMEOUT_MS);
394	if (ret != 1) {	394	if (ret != 1) {
395	dev_err(&pdev->dev,	395	dev_err(&pdev->dev, "failure setting i2c_bus_freq to %d\n",
396	"failure setting i2c_bus_freq to %d\n", i2c_bus_freq);	396	i2c_bus_freq);
397	return -EIO;	397	return -EIO;
398	}	398	}
399	} else {	399	} else {
400	dev_err(&pdev->dev,	400	dev_err(&pdev->dev,
401	"invalid i2c_bus_freq setting:%d\n", i2c_bus_freq);	401	"invalid i2c_bus_freq setting:%d\n", i2c_bus_freq);

drivers/i2c/busses/i2c-xgene-slimpro.c+4−4

 	int rc;
 	paddr = dma_map_single(ctx->dev, ctx->dma_buffer, readlen, DMA_FROM_DEVICE);
-	rc = dma_mapping_error(ctx->dev, paddr);
+	if (dma_mapping_error(ctx->dev, paddr)) {
-	if (rc) {
 		dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
 			ctx->dma_buffer);
+		rc = -ENOMEM;
 		goto err;
 	}
 	memcpy(ctx->dma_buffer, data, writelen);
 	paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen,
 			       DMA_TO_DEVICE);
-	rc = dma_mapping_error(ctx->dev, paddr);
+	if (dma_mapping_error(ctx->dev, paddr)) {
-	if (rc) {
 		dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
 			ctx->dma_buffer);
+		rc = -ENOMEM;
 		goto err;
 	}

drivers/i2c/busses/i2c-xiic.c+34−40

@@ -283,7 +283,7 @@ static void xiic_reinit(struct xiic_i2c *i2c) · 282 unmodified lines
283	/* Enable interrupts */	283	/* Enable interrupts */
284	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);	284	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
285		285
286	xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK \| XIIC_INTR_ARB_LOST_MASK);	286	xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
287	}	287	}
288		288
289	static void xiic_deinit(struct xiic_i2c *i2c)	289	static void xiic_deinit(struct xiic_i2c *i2c)
@@ -358,8 +358,9 @@ static void xiic_wakeup(struct xiic_i2c *i2c, int code) · 68 unmodified lines
358	wake_up(&i2c->wait);	358	wake_up(&i2c->wait);
359	}	359	}
360		360
361	static void xiic_process(struct xiic_i2c *i2c)	361	static irqreturn_t xiic_process(int irq, void *dev_id)
362	{	362	{
		363	struct xiic_i2c *i2c = dev_id;
363	u32 pend, isr, ier;	364	u32 pend, isr, ier;
364	u32 clr = 0;	365	u32 clr = 0;
365		366
@@ -368,6 +369,7 @@ static void xiic_process(struct xiic_i2c *i2c) · 2 unmodified lines
368	* To find which interrupts are pending; AND interrupts pending with	369	* To find which interrupts are pending; AND interrupts pending with
369	* interrupts masked.	370	* interrupts masked.
370	*/	371	*/
		372	spin_lock(&i2c->lock);
371	isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);	373	isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
372	ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);	374	ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
373	pend = isr & ier;	375	pend = isr & ier;
@@ -378,11 +380,6 @@ static void xiic_process(struct xiic_i2c *i2c) · 4 unmodified lines
378	__func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),	380	__func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
379	i2c->tx_msg, i2c->nmsgs);	381	i2c->tx_msg, i2c->nmsgs);
380		382
381	/* Do not processes a devices interrupts if the device has no
382	* interrupts pending
383	*/
384	if (!pend)
385	return;
386		383
387	/* Service requesting interrupt */	384	/* Service requesting interrupt */
388	if ((pend & XIIC_INTR_ARB_LOST_MASK) \|\|	385	if ((pend & XIIC_INTR_ARB_LOST_MASK) \|\|
@@ -402,13 +399,15 @@ static void xiic_process(struct xiic_i2c *i2c) · 13 unmodified lines
402	*/	399	*/
403	xiic_reinit(i2c);	400	xiic_reinit(i2c);
404		401
		402	if (i2c->rx_msg)
		403	xiic_wakeup(i2c, STATE_ERROR);
405	if (i2c->tx_msg)	404	if (i2c->tx_msg)
406	xiic_wakeup(i2c, STATE_ERROR);	405	xiic_wakeup(i2c, STATE_ERROR);
407		406	}
408	} else if (pend & XIIC_INTR_RX_FULL_MASK) {	407	if (pend & XIIC_INTR_RX_FULL_MASK) {
409	/* Receive register/FIFO is full */	408	/* Receive register/FIFO is full */
410		409
411	clr = XIIC_INTR_RX_FULL_MASK;	410	clr \|= XIIC_INTR_RX_FULL_MASK;
412	if (!i2c->rx_msg) {	411	if (!i2c->rx_msg) {
413	dev_dbg(i2c->adap.dev.parent,	412	dev_dbg(i2c->adap.dev.parent,
414	"%s unexpexted RX IRQ\n", __func__);	413	"%s unexpexted RX IRQ\n", __func__);
@@ -441,9 +440,10 @@ static void xiic_process(struct xiic_i2c *i2c) · 26 unmodified lines
441	__xiic_start_xfer(i2c);	440	__xiic_start_xfer(i2c);
442	}	441	}
443	}	442	}
444	} else if (pend & XIIC_INTR_BNB_MASK) {	443	}
		444	if (pend & XIIC_INTR_BNB_MASK) {
445	/* IIC bus has transitioned to not busy */	445	/* IIC bus has transitioned to not busy */
446	clr = XIIC_INTR_BNB_MASK;	446	clr \|= XIIC_INTR_BNB_MASK;
447		447
448	/* The bus is not busy, disable BusNotBusy interrupt */	448	/* The bus is not busy, disable BusNotBusy interrupt */
449	xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);	449	xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
@@ -456,12 +456,12 @@ static void xiic_process(struct xiic_i2c *i2c) · 6 unmodified lines
456	xiic_wakeup(i2c, STATE_DONE);	456	xiic_wakeup(i2c, STATE_DONE);
457	else	457	else
458	xiic_wakeup(i2c, STATE_ERROR);	458	xiic_wakeup(i2c, STATE_ERROR);
459		459	}
460	} else if (pend & (XIIC_INTR_TX_EMPTY_MASK \| XIIC_INTR_TX_HALF_MASK)) {	460	if (pend & (XIIC_INTR_TX_EMPTY_MASK \| XIIC_INTR_TX_HALF_MASK)) {
461	/* Transmit register/FIFO is empty or ½ empty */	461	/* Transmit register/FIFO is empty or ½ empty */
462		462
463	clr = pend &	463	clr \|= (pend &
464	(XIIC_INTR_TX_EMPTY_MASK \| XIIC_INTR_TX_HALF_MASK);	464	(XIIC_INTR_TX_EMPTY_MASK \| XIIC_INTR_TX_HALF_MASK));
465		465
466	if (!i2c->tx_msg) {	466	if (!i2c->tx_msg) {
467	dev_dbg(i2c->adap.dev.parent,	467	dev_dbg(i2c->adap.dev.parent,
@@ -492,16 +492,13 @@ static void xiic_process(struct xiic_i2c *i2c) · 24 unmodified lines
492	* make sure to disable tx half	492	* make sure to disable tx half
493	*/	493	*/
494	xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);	494	xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
495	} else {
496	/* got IRQ which is not acked */
497	dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
498	__func__);
499	clr = pend;
500	}	495	}
501	out:	496	out:
502	dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);	497	dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
503		498
504	xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);	499	xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
		500	spin_unlock(&i2c->lock);
		501	return IRQ_HANDLED;
505	}	502	}
506		503
507	static int xiic_bus_busy(struct xiic_i2c *i2c)	504	static int xiic_bus_busy(struct xiic_i2c *i2c)
@@ -525,7 +522,7 @@ static int xiic_busy(struct xiic_i2c *i2c) · 17 unmodified lines
525	*/	522	*/
526	err = xiic_bus_busy(i2c);	523	err = xiic_bus_busy(i2c);
527	while (err && tries--) {	524	while (err && tries--) {
528	mdelay(1);	525	msleep(1);
529	err = xiic_bus_busy(i2c);	526	err = xiic_bus_busy(i2c);
530	}	527	}
531		528
@@ -602,19 +599,21 @@ static void xiic_start_send(struct xiic_i2c *i2c) · 70 unmodified lines
602	static irqreturn_t xiic_isr(int irq, void *dev_id)	599	static irqreturn_t xiic_isr(int irq, void *dev_id)
603	{	600	{
604	struct xiic_i2c *i2c = dev_id;	601	struct xiic_i2c *i2c = dev_id;
605		602	u32 pend, isr, ier;
606	spin_lock(&i2c->lock);	603	irqreturn_t ret = IRQ_NONE;
607	/* disable interrupts globally */	604	/* Do not processes a devices interrupts if the device has no
608	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);	605	* interrupts pending
		606	*/
609		607
610	dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);	608	dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
611		609
612	xiic_process(i2c);	610	isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
613		611	ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
614	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);	612	pend = isr & ier;
615	spin_unlock(&i2c->lock);	613	if (pend)
		614	ret = IRQ_WAKE_THREAD;
616		615
617	return IRQ_HANDLED;	616	return ret;
618	}	617	}
619		618
620	static void __xiic_start_xfer(struct xiic_i2c *i2c)	619	static void __xiic_start_xfer(struct xiic_i2c *i2c)
@@ -663,16 +662,8 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) · 42 unmodified lines
663		662
664	static void xiic_start_xfer(struct xiic_i2c *i2c)	663	static void xiic_start_xfer(struct xiic_i2c *i2c)
665	{	664	{
666	unsigned long flags;
667
668	spin_lock_irqsave(&i2c->lock, flags);
669	xiic_reinit(i2c);
670	/* disable interrupts globally */
671	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
672	spin_unlock_irqrestore(&i2c->lock, flags);
673		665
674	__xiic_start_xfer(i2c);	666	__xiic_start_xfer(i2c);
675	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
676	}	667	}
677		668
678	static int xiic_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)	669	static int xiic_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
@@ -755,7 +746,10 @@ static int xiic_i2c_probe(struct platform_device *pdev) · 76 unmodified lines
755	spin_lock_init(&i2c->lock);	746	spin_lock_init(&i2c->lock);
756	init_waitqueue_head(&i2c->wait);	747	init_waitqueue_head(&i2c->wait);
757		748
758	ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c);	749	ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
		750	xiic_process, IRQF_ONESHOT,
		751	pdev->name, i2c);
		752
759	if (ret < 0) {	753	if (ret < 0) {
760	dev_err(&pdev->dev, "Cannot claim IRQ\n");	754	dev_err(&pdev->dev, "Cannot claim IRQ\n");
761	return ret;	755	return ret;

drivers/i2c/i2c-core.c+194−35

@@ -27,6 +27,7 @@ · 26 unmodified lines
27	I2C slave support (c) 2014 by Wolfram Sang <wsa@sang-engineering.com>	27	I2C slave support (c) 2014 by Wolfram Sang <wsa@sang-engineering.com>
28	*/	28	*/
29		29
		30	#include <dt-bindings/i2c/i2c.h>
30	#include <linux/module.h>	31	#include <linux/module.h>
31	#include <linux/kernel.h>	32	#include <linux/kernel.h>
32	#include <linux/delay.h>	33	#include <linux/delay.h>
@@ -47,6 +48,7 @@ · 14 unmodified lines
47	#include <linux/rwsem.h>	48	#include <linux/rwsem.h>
48	#include <linux/pm_runtime.h>	49	#include <linux/pm_runtime.h>
49	#include <linux/pm_domain.h>	50	#include <linux/pm_domain.h>
		51	#include <linux/pm_wakeirq.h>
50	#include <linux/acpi.h>	52	#include <linux/acpi.h>
51	#include <linux/jump_label.h>	53	#include <linux/jump_label.h>
52	#include <asm/uaccess.h>	54	#include <asm/uaccess.h>
@@ -57,6 +59,9 @@ · 4 unmodified lines
57	#define CREATE_TRACE_POINTS	59	#define CREATE_TRACE_POINTS
58	#include <trace/events/i2c.h>	60	#include <trace/events/i2c.h>
59		61
		62	#define I2C_ADDR_OFFSET_TEN_BIT 0xa000
		63	#define I2C_ADDR_OFFSET_SLAVE 0x1000
		64
60	/* core_lock protects i2c_adapter_idr, and guarantees	65	/* core_lock protects i2c_adapter_idr, and guarantees
61	that device detection, deletion of detected devices, and attach_adapter	66	that device detection, deletion of detected devices, and attach_adapter
62	calls are serialized */	67	calls are serialized */
@@ -641,11 +646,13 @@ static int i2c_device_probe(struct device *dev) · 578 unmodified lines
641	if (!client->irq) {	646	if (!client->irq) {
642	int irq = -ENOENT;	647	int irq = -ENOENT;
643		648
644	if (dev->of_node)	649	if (dev->of_node) {
645	irq = of_irq_get(dev->of_node, 0);	650	irq = of_irq_get_byname(dev->of_node, "irq");
646	else if (ACPI_COMPANION(dev))	651	if (irq == -EINVAL \|\| irq == -ENODATA)
		652	irq = of_irq_get(dev->of_node, 0);
		653	} else if (ACPI_COMPANION(dev)) {
647	irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);	654	irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
648		655	}
649	if (irq == -EPROBE_DEFER)	656	if (irq == -EPROBE_DEFER)
650	return irq;	657	return irq;
651	if (irq < 0)	658	if (irq < 0)
@@ -658,23 +665,49 @@ static int i2c_device_probe(struct device *dev) · 6 unmodified lines
658	if (!driver->probe \|\| !driver->id_table)	665	if (!driver->probe \|\| !driver->id_table)
659	return -ENODEV;	666	return -ENODEV;
660		667
661	if (!device_can_wakeup(&client->dev))	668	if (client->flags & I2C_CLIENT_WAKE) {
662	device_init_wakeup(&client->dev,	669	int wakeirq = -ENOENT;
663	client->flags & I2C_CLIENT_WAKE);	670
		671	if (dev->of_node) {
		672	wakeirq = of_irq_get_byname(dev->of_node, "wakeup");
		673	if (wakeirq == -EPROBE_DEFER)
		674	return wakeirq;
		675	}
		676
		677	device_init_wakeup(&client->dev, true);
		678
		679	if (wakeirq > 0 && wakeirq != client->irq)
		680	status = dev_pm_set_dedicated_wake_irq(dev, wakeirq);
		681	else if (client->irq > 0)
		682	status = dev_pm_set_wake_irq(dev, wakeirq);
		683	else
		684	status = 0;
		685
		686	if (status)
		687	dev_warn(&client->dev, "failed to set up wakeup irq");
		688	}
		689
664	dev_dbg(dev, "probe\n");	690	dev_dbg(dev, "probe\n");
665		691
666	status = of_clk_set_defaults(dev->of_node, false);	692	status = of_clk_set_defaults(dev->of_node, false);
667	if (status < 0)	693	if (status < 0)
668	return status;	694	goto err_clear_wakeup_irq;
669		695
670	status = dev_pm_domain_attach(&client->dev, true);	696	status = dev_pm_domain_attach(&client->dev, true);
671	if (status != -EPROBE_DEFER) {	697	if (status != -EPROBE_DEFER) {
672	status = driver->probe(client, i2c_match_id(driver->id_table,	698	status = driver->probe(client, i2c_match_id(driver->id_table,
673	client));	699	client));
674	if (status)	700	if (status)
675	dev_pm_domain_detach(&client->dev, true);	701	goto err_detach_pm_domain;
676	}	702	}
677		703
		704	return 0;
		705
		706	err_detach_pm_domain:
		707	dev_pm_domain_detach(&client->dev, true);
		708	err_clear_wakeup_irq:
		709	dev_pm_clear_wake_irq(&client->dev);
		710	device_init_wakeup(&client->dev, false);
678	return status;	711	return status;
679	}	712	}
680		713
@@ -694,6 +727,10 @@ static int i2c_device_remove(struct device *dev) · 13 unmodified lines
694	}	727	}
695		728
696	dev_pm_domain_detach(&client->dev, true);	729	dev_pm_domain_detach(&client->dev, true);
		730
		731	dev_pm_clear_wake_irq(&client->dev);
		732	device_init_wakeup(&client->dev, false);
		733
697	return status;	734	return status;
698	}	735	}
699		736
@@ -778,17 +815,32 @@ struct i2c_client i2c_verify_client(struct device dev) · 78 unmodified lines
778	EXPORT_SYMBOL(i2c_verify_client);	815	EXPORT_SYMBOL(i2c_verify_client);
779		816
780		817
		818	/* Return a unique address which takes the flags of the client into account */
		819	static unsigned short i2c_encode_flags_to_addr(struct i2c_client *client)
		820	{
		821	unsigned short addr = client->addr;
		822
		823	/* For some client flags, add an arbitrary offset to avoid collisions */
		824	if (client->flags & I2C_CLIENT_TEN)
		825	addr \|= I2C_ADDR_OFFSET_TEN_BIT;
		826
		827	if (client->flags & I2C_CLIENT_SLAVE)
		828	addr \|= I2C_ADDR_OFFSET_SLAVE;
		829
		830	return addr;
		831	}
		832
781	/* This is a permissive address validity check, I2C address map constraints	833	/* This is a permissive address validity check, I2C address map constraints
782	* are purposely not enforced, except for the general call address. */	834	* are purposely not enforced, except for the general call address. */
783	static int i2c_check_client_addr_validity(const struct i2c_client *client)	835	static int i2c_check_addr_validity(unsigned addr, unsigned short flags)
784	{	836	{
785	if (client->flags & I2C_CLIENT_TEN) {	837	if (flags & I2C_CLIENT_TEN) {
786	/* 10-bit address, all values are valid */	838	/* 10-bit address, all values are valid */
787	if (client->addr > 0x3ff)	839	if (addr > 0x3ff)
788	return -EINVAL;	840	return -EINVAL;
789	} else {	841	} else {
790	/* 7-bit address, reject the general call address */	842	/* 7-bit address, reject the general call address */
791	if (client->addr == 0x00 \|\| client->addr > 0x7f)	843	if (addr == 0x00 \|\| addr > 0x7f)
792	return -EINVAL;	844	return -EINVAL;
793	}	845	}
794	return 0;	846	return 0;
@@ -798,7 +850,7 @@ static int i2c_check_client_addr_validity(const struct i2c_client *client) · 3 unmodified lines
798	* device uses a reserved address, then it shouldn't be probed. 7-bit	850	* device uses a reserved address, then it shouldn't be probed. 7-bit
799	* addressing is assumed, 10-bit address devices are rare and should be	851	* addressing is assumed, 10-bit address devices are rare and should be
800	* explicitly enumerated. */	852	* explicitly enumerated. */
801	static int i2c_check_addr_validity(unsigned short addr)	853	static int i2c_check_7bit_addr_validity_strict(unsigned short addr)
802	{	854	{
803	/*	855	/*
804	* Reserved addresses per I2C specification:	856	* Reserved addresses per I2C specification:
@@ -820,7 +872,7 @@ static int __i2c_check_addr_busy(struct device dev, void addrp) · 15 unmodified lines
820	struct i2c_client *client = i2c_verify_client(dev);	872	struct i2c_client *client = i2c_verify_client(dev);
821	int addr = (int )addrp;	873	int addr = (int )addrp;
822		874
823	if (client && client->addr == addr)	875	if (client && i2c_encode_flags_to_addr(client) == addr)
824	return -EBUSY;	876	return -EBUSY;
825	return 0;	877	return 0;
826	}	878	}
@@ -923,10 +975,8 @@ static void i2c_dev_set_name(struct i2c_adapter *adap, · 96 unmodified lines
923	return;	975	return;
924	}	976	}
925		977
926	/* For 10-bit clients, add an arbitrary offset to avoid collisions */
927	dev_set_name(&client->dev, "%d-%04x", i2c_adapter_id(adap),	978	dev_set_name(&client->dev, "%d-%04x", i2c_adapter_id(adap),
928	client->addr \| ((client->flags & I2C_CLIENT_TEN)	979	i2c_encode_flags_to_addr(client));
929	? 0xa000 : 0));
930	}	980	}
931		981
932	/**	982	/**
@@ -968,8 +1018,7 @@ i2c_new_device(struct i2c_adapter adap, struct i2c_board_info const info) · 35 unmodified lines
968		1018
969	strlcpy(client->name, info->type, sizeof(client->name));	1019	strlcpy(client->name, info->type, sizeof(client->name));
970		1020
971	/* Check for address validity */	1021	status = i2c_check_addr_validity(client->addr, client->flags);
972	status = i2c_check_client_addr_validity(client);
973	if (status) {	1022	if (status) {
974	dev_err(&adap->dev, "Invalid %d-bit I2C address 0x%02hx\n",	1023	dev_err(&adap->dev, "Invalid %d-bit I2C address 0x%02hx\n",
975	client->flags & I2C_CLIENT_TEN ? 10 : 7, client->addr);	1024	client->flags & I2C_CLIENT_TEN ? 10 : 7, client->addr);
@@ -977,7 +1026,7 @@ i2c_new_device(struct i2c_adapter adap, struct i2c_board_info const info) · 1 unmodified line
977	}	1026	}
978		1027
979	/* Check for address business */	1028	/* Check for address business */
980	status = i2c_check_addr_busy(adap, client->addr);	1029	status = i2c_check_addr_busy(adap, i2c_encode_flags_to_addr(client));
981	if (status)	1030	if (status)
982	goto out_err;	1031	goto out_err;
983		1032
@@ -1142,6 +1191,16 @@ i2c_sysfs_new_device(struct device dev, struct device_attribute attr, · 158 unmodified lines
1142	return -EINVAL;	1191	return -EINVAL;
1143	}	1192	}
1144		1193
		1194	if ((info.addr & I2C_ADDR_OFFSET_TEN_BIT) == I2C_ADDR_OFFSET_TEN_BIT) {
		1195	info.addr &= ~I2C_ADDR_OFFSET_TEN_BIT;
		1196	info.flags \|= I2C_CLIENT_TEN;
		1197	}
		1198
		1199	if (info.addr & I2C_ADDR_OFFSET_SLAVE) {
		1200	info.addr &= ~I2C_ADDR_OFFSET_SLAVE;
		1201	info.flags \|= I2C_CLIENT_SLAVE;
		1202	}
		1203
1145	client = i2c_new_device(adap, &info);	1204	client = i2c_new_device(adap, &info);
1146	if (!client)	1205	if (!client)
1147	return -EINVAL;	1206	return -EINVAL;
@@ -1193,7 +1252,7 @@ i2c_sysfs_delete_device(struct device dev, struct device_attribute attr, · 45 unmodified lines
1193	i2c_adapter_depth(adap));	1252	i2c_adapter_depth(adap));
1194	list_for_each_entry_safe(client, next, &adap->userspace_clients,	1253	list_for_each_entry_safe(client, next, &adap->userspace_clients,
1195	detected) {	1254	detected) {
1196	if (client->addr == addr) {	1255	if (i2c_encode_flags_to_addr(client) == addr) {
1197	dev_info(dev, "%s: Deleting device %s at 0x%02hx\n",	1256	dev_info(dev, "%s: Deleting device %s at 0x%02hx\n",
1198	"delete_device", client->name, client->addr);	1257	"delete_device", client->name, client->addr);
1199		1258
@@ -1273,7 +1332,8 @@ static struct i2c_client of_i2c_register_device(struct i2c_adapter adap, · 73 unmodified lines
1273	struct i2c_client *result;	1332	struct i2c_client *result;
1274	struct i2c_board_info info = {};	1333	struct i2c_board_info info = {};
1275	struct dev_archdata dev_ad = {};	1334	struct dev_archdata dev_ad = {};
1276	const __be32 *addr;	1335	const __be32 *addr_be;
		1336	u32 addr;
1277	int len;	1337	int len;
1278		1338
1279	dev_dbg(&adap->dev, "of_i2c: register %s\n", node->full_name);	1339	dev_dbg(&adap->dev, "of_i2c: register %s\n", node->full_name);
@@ -1284,20 +1344,31 @@ static struct i2c_client of_i2c_register_device(struct i2c_adapter adap, · 4 unmodified lines
1284	return ERR_PTR(-EINVAL);	1344	return ERR_PTR(-EINVAL);
1285	}	1345	}
1286		1346
1287	addr = of_get_property(node, "reg", &len);	1347	addr_be = of_get_property(node, "reg", &len);
1288	if (!addr \|\| (len < sizeof(*addr))) {	1348	if (!addr_be \|\| (len < sizeof(*addr_be))) {
1289	dev_err(&adap->dev, "of_i2c: invalid reg on %s\n",	1349	dev_err(&adap->dev, "of_i2c: invalid reg on %s\n",
1290	node->full_name);	1350	node->full_name);
1291	return ERR_PTR(-EINVAL);	1351	return ERR_PTR(-EINVAL);
1292	}	1352	}
1293		1353
1294	info.addr = be32_to_cpup(addr);	1354	addr = be32_to_cpup(addr_be);
1295	if (info.addr > (1 << 10) - 1) {	1355	if (addr & I2C_TEN_BIT_ADDRESS) {
		1356	addr &= ~I2C_TEN_BIT_ADDRESS;
		1357	info.flags \|= I2C_CLIENT_TEN;
		1358	}
		1359
		1360	if (addr & I2C_OWN_SLAVE_ADDRESS) {
		1361	addr &= ~I2C_OWN_SLAVE_ADDRESS;
		1362	info.flags \|= I2C_CLIENT_SLAVE;
		1363	}
		1364
		1365	if (i2c_check_addr_validity(addr, info.flags)) {
1296	dev_err(&adap->dev, "of_i2c: invalid addr=%x on %s\n",	1366	dev_err(&adap->dev, "of_i2c: invalid addr=%x on %s\n",
1297	info.addr, node->full_name);	1367	info.addr, node->full_name);
1298	return ERR_PTR(-EINVAL);	1368	return ERR_PTR(-EINVAL);
1299	}	1369	}
1300		1370
		1371	info.addr = addr;
1301	info.of_node = of_node_get(node);	1372	info.of_node = of_node_get(node);
1302	info.archdata = &dev_ad;	1373	info.archdata = &dev_ad;
1303		1374
@@ -1371,6 +1442,24 @@ struct i2c_adapter of_find_i2c_adapter_by_node(struct device_node node) · 67 unmodified lines
1371	return adapter;	1442	return adapter;
1372	}	1443	}
1373	EXPORT_SYMBOL(of_find_i2c_adapter_by_node);	1444	EXPORT_SYMBOL(of_find_i2c_adapter_by_node);
		1445
		1446	/* must call i2c_put_adapter() when done with returned i2c_adapter device */
		1447	struct i2c_adapter of_get_i2c_adapter_by_node(struct device_node node)
		1448	{
		1449	struct i2c_adapter *adapter;
		1450
		1451	adapter = of_find_i2c_adapter_by_node(node);
		1452	if (!adapter)
		1453	return NULL;
		1454
		1455	if (!try_module_get(adapter->owner)) {
		1456	put_device(&adapter->dev);
		1457	adapter = NULL;
		1458	}
		1459
		1460	return adapter;
		1461	}
		1462	EXPORT_SYMBOL(of_get_i2c_adapter_by_node);
1374	#else	1463	#else
1375	static void of_i2c_register_devices(struct i2c_adapter *adap) { }	1464	static void of_i2c_register_devices(struct i2c_adapter *adap) { }
1376	#endif /* CONFIG_OF */	1465	#endif /* CONFIG_OF */
@@ -2262,14 +2351,14 @@ static int i2c_detect_address(struct i2c_client *temp_client, · 885 unmodified lines
2262	int err;	2351	int err;
2263		2352
2264	/* Make sure the address is valid */	2353	/* Make sure the address is valid */
2265	err = i2c_check_addr_validity(addr);	2354	err = i2c_check_7bit_addr_validity_strict(addr);
2266	if (err) {	2355	if (err) {
2267	dev_warn(&adapter->dev, "Invalid probe address 0x%02x\n",	2356	dev_warn(&adapter->dev, "Invalid probe address 0x%02x\n",
2268	addr);	2357	addr);
2269	return err;	2358	return err;
2270	}	2359	}
2271		2360
2272	/* Skip if already in use */	2361	/* Skip if already in use (7 bit, no need to encode flags) */
2273	if (i2c_check_addr_busy(adapter, addr))	2362	if (i2c_check_addr_busy(adapter, addr))
2274	return 0;	2363	return 0;
2275		2364
@@ -2379,13 +2468,13 @@ i2c_new_probed_device(struct i2c_adapter *adap, · 103 unmodified lines
2379		2468
2380	for (i = 0; addr_list[i] != I2C_CLIENT_END; i++) {	2469	for (i = 0; addr_list[i] != I2C_CLIENT_END; i++) {
2381	/* Check address validity */	2470	/* Check address validity */
2382	if (i2c_check_addr_validity(addr_list[i]) < 0) {	2471	if (i2c_check_7bit_addr_validity_strict(addr_list[i]) < 0) {
2383	dev_warn(&adap->dev, "Invalid 7-bit address "	2472	dev_warn(&adap->dev, "Invalid 7-bit address "
2384	"0x%02x\n", addr_list[i]);	2473	"0x%02x\n", addr_list[i]);
2385	continue;	2474	continue;
2386	}	2475	}
2387		2476
2388	/* Check address availability */	2477	/* Check address availability (7 bit, no need to encode flags) */
2389	if (i2c_check_addr_busy(adap, addr_list[i])) {	2478	if (i2c_check_addr_busy(adap, addr_list[i])) {
2390	dev_dbg(&adap->dev, "Address 0x%02x already in "	2479	dev_dbg(&adap->dev, "Address 0x%02x already in "
2391	"use, not probing\n", addr_list[i]);	2480	"use, not probing\n", addr_list[i]);
@@ -2413,9 +2502,15 @@ struct i2c_adapter *i2c_get_adapter(int nr) · 21 unmodified lines
2413		2502
2414	mutex_lock(&core_lock);	2503	mutex_lock(&core_lock);
2415	adapter = idr_find(&i2c_adapter_idr, nr);	2504	adapter = idr_find(&i2c_adapter_idr, nr);
2416	if (adapter && !try_module_get(adapter->owner))	2505	if (!adapter)
		2506	goto exit;
		2507
		2508	if (try_module_get(adapter->owner))
		2509	get_device(&adapter->dev);
		2510	else
2417	adapter = NULL;	2511	adapter = NULL;
2418		2512
		2513	exit:
2419	mutex_unlock(&core_lock);	2514	mutex_unlock(&core_lock);
2420	return adapter;	2515	return adapter;
2421	}	2516	}
@@ -2423,8 +2518,11 @@ EXPORT_SYMBOL(i2c_get_adapter); · 1 unmodified line
2423		2518
2424	void i2c_put_adapter(struct i2c_adapter *adap)	2519	void i2c_put_adapter(struct i2c_adapter *adap)
2425	{	2520	{
2426	if (adap)	2521	if (!adap)
2427	module_put(adap->owner);	2522	return;
		2523
		2524	put_device(&adap->dev);
		2525	module_put(adap->owner);
2428	}	2526	}
2429	EXPORT_SYMBOL(i2c_put_adapter);	2527	EXPORT_SYMBOL(i2c_put_adapter);
2430		2528
@@ -2942,6 +3040,63 @@ trace: · 511 unmodified lines
2942	}	3040	}
2943	EXPORT_SYMBOL(i2c_smbus_xfer);	3041	EXPORT_SYMBOL(i2c_smbus_xfer);
2944		3042
		3043	/**
		3044	* i2c_smbus_read_i2c_block_data_or_emulated - read block or emulate
		3045	* @client: Handle to slave device
		3046	* @command: Byte interpreted by slave
		3047	* @length: Size of data block; SMBus allows at most I2C_SMBUS_BLOCK_MAX bytes
		3048	* @values: Byte array into which data will be read; big enough to hold
		3049	* the data returned by the slave. SMBus allows at most
		3050	* I2C_SMBUS_BLOCK_MAX bytes.
		3051	*
		3052	* This executes the SMBus "block read" protocol if supported by the adapter.
		3053	* If block read is not supported, it emulates it using either word or byte
		3054	* read protocols depending on availability.
		3055	*
		3056	* The addresses of the I2C slave device that are accessed with this function
		3057	* must be mapped to a linear region, so that a block read will have the same
		3058	* effect as a byte read. Before using this function you must double-check
		3059	* if the I2C slave does support exchanging a block transfer with a byte
		3060	* transfer.
		3061	*/
		3062	s32 i2c_smbus_read_i2c_block_data_or_emulated(const struct i2c_client *client,
		3063	u8 command, u8 length, u8 *values)
		3064	{
		3065	u8 i = 0;
		3066	int status;
		3067
		3068	if (length > I2C_SMBUS_BLOCK_MAX)
		3069	length = I2C_SMBUS_BLOCK_MAX;
		3070
		3071	if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK))
		3072	return i2c_smbus_read_i2c_block_data(client, command, length, values);
		3073
		3074	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA))
		3075	return -EOPNOTSUPP;
		3076
		3077	if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_WORD_DATA)) {
		3078	while ((i + 2) <= length) {
		3079	status = i2c_smbus_read_word_data(client, command + i);
		3080	if (status < 0)
		3081	return status;
		3082	values[i] = status & 0xff;
		3083	values[i + 1] = status >> 8;
		3084	i += 2;
		3085	}
		3086	}
		3087
		3088	while (i < length) {
		3089	status = i2c_smbus_read_byte_data(client, command + i);
		3090	if (status < 0)
		3091	return status;
		3092	values[i] = status;
		3093	i++;
		3094	}
		3095
		3096	return i;
		3097	}
		3098	EXPORT_SYMBOL(i2c_smbus_read_i2c_block_data_or_emulated);
		3099
2945	#if IS_ENABLED(CONFIG_I2C_SLAVE)	3100	#if IS_ENABLED(CONFIG_I2C_SLAVE)
2946	int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)	3101	int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)
2947	{	3102	{
@@ -2952,9 +3107,13 @@ int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb) · 4 unmodified lines
2952	return -EINVAL;	3107	return -EINVAL;
2953	}	3108	}
2954		3109
		3110	if (!(client->flags & I2C_CLIENT_SLAVE))
		3111	dev_warn(&client->dev, "%s: client slave flag not set. You might see address collisions\n",
		3112	__func__);
		3113
2955	if (!(client->flags & I2C_CLIENT_TEN)) {	3114	if (!(client->flags & I2C_CLIENT_TEN)) {
2956	/* Enforce stricter address checking */	3115	/* Enforce stricter address checking */
2957	ret = i2c_check_addr_validity(client->addr);	3116	ret = i2c_check_7bit_addr_validity_strict(client->addr);
2958	if (ret) {	3117	if (ret) {
2959	dev_err(&client->dev, "%s: invalid address\n", __func__);	3118	dev_err(&client->dev, "%s: invalid address\n", __func__);
2960	return ret;	3119	return ret;

drivers/i2c/i2c-slave-eeprom.c+0−1

@@ -157,7 +157,6 @@ MODULE_DEVICE_TABLE(i2c, i2c_slave_eeprom_id); · 156 unmodified lines
157	static struct i2c_driver i2c_slave_eeprom_driver = {	157	static struct i2c_driver i2c_slave_eeprom_driver = {
158	.driver = {	158	.driver = {
159	.name = "i2c-slave-eeprom",	159	.name = "i2c-slave-eeprom",
160	.owner = THIS_MODULE,
161	},	160	},
162	.probe = i2c_slave_eeprom_probe,	161	.probe = i2c_slave_eeprom_probe,
163	.remove = i2c_slave_eeprom_remove,	162	.remove = i2c_slave_eeprom_remove,

drivers/i2c/muxes/Kconfig+11−0

@@ -61,4 +61,15 @@ config I2C_MUX_PINCTRL · 60 unmodified lines
61	This driver can also be built as a module. If so, the module will be	61	This driver can also be built as a module. If so, the module will be
62	called pinctrl-i2cmux.	62	called pinctrl-i2cmux.
63		63
		64	config I2C_MUX_REG
		65	tristate "Register-based I2C multiplexer"
		66	help
		67	If you say yes to this option, support will be included for a
		68	register based I2C multiplexer. This driver provides access to
		69	I2C busses connected through a MUX, which is controlled
		70	by a single register.
		71
		72	This driver can also be built as a module. If so, the module
		73	will be called i2c-mux-reg.
		74
64	endmenu	75	endmenu

drivers/i2c/muxes/Makefile+1−0

@@ -7,5 +7,6 @@ obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o · 6 unmodified lines
7	obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux-pca9541.o	7	obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux-pca9541.o
8	obj-$(CONFIG_I2C_MUX_PCA954x) += i2c-mux-pca954x.o	8	obj-$(CONFIG_I2C_MUX_PCA954x) += i2c-mux-pca954x.o
9	obj-$(CONFIG_I2C_MUX_PINCTRL) += i2c-mux-pinctrl.o	9	obj-$(CONFIG_I2C_MUX_PINCTRL) += i2c-mux-pinctrl.o
		10	obj-$(CONFIG_I2C_MUX_REG) += i2c-mux-reg.o
10		11
11	ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG	12	ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG

drivers/i2c/muxes/i2c-arb-gpio-challenge.c+2−1

 		dev_err(dev, "Cannot parse i2c-parent\n");
 		return -EINVAL;
 	}
-	arb->parent = of_find_i2c_adapter_by_node(parent_np);
+	arb->parent = of_get_i2c_adapter_by_node(parent_np);
+	of_node_put(parent_np);
 	if (!arb->parent) {
 		dev_err(dev, "Cannot find parent bus\n");
 		return -EPROBE_DEFER;

drivers/i2c/muxes/i2c-mux-gpio.c+1−0

@@ -76,6 +76,7 @@ static int i2c_mux_gpio_probe_dt(struct gpiomux *mux, · 75 unmodified lines
76	return -ENODEV;	76	return -ENODEV;
77	}	77	}
78	adapter = of_find_i2c_adapter_by_node(adapter_np);	78	adapter = of_find_i2c_adapter_by_node(adapter_np);
		79	of_node_put(adapter_np);
79	if (!adapter)	80	if (!adapter)
80	return -EPROBE_DEFER;	81	return -EPROBE_DEFER;
81		82

drivers/i2c/muxes/i2c-mux-pca9541.c+0−1

@@ -386,7 +386,6 @@ static int pca9541_remove(struct i2c_client *client) · 385 unmodified lines
386	static struct i2c_driver pca9541_driver = {	386	static struct i2c_driver pca9541_driver = {
387	.driver = {	387	.driver = {
388	.name = "pca9541",	388	.name = "pca9541",
389	.owner = THIS_MODULE,
390	},	389	},
391	.probe = pca9541_probe,	390	.probe = pca9541_probe,
392	.remove = pca9541_remove,	391	.remove = pca9541_remove,

drivers/i2c/muxes/i2c-mux-pca954x.c+0−1

@@ -300,7 +300,6 @@ static struct i2c_driver pca954x_driver = { · 299 unmodified lines
300	.driver = {	300	.driver = {
301	.name = "pca954x",	301	.name = "pca954x",
302	.pm = &pca954x_pm,	302	.pm = &pca954x_pm,
303	.owner = THIS_MODULE,
304	},	303	},
305	.probe = pca954x_probe,	304	.probe = pca954x_probe,
306	.remove = pca954x_remove,	305	.remove = pca954x_remove,

drivers/i2c/muxes/i2c-mux-pinctrl.c+1−0

@@ -111,6 +111,7 @@ static int i2c_mux_pinctrl_parse_dt(struct i2c_mux_pinctrl *mux, · 110 unmodified lines
111	return -ENODEV;	111	return -ENODEV;
112	}	112	}
113	adapter = of_find_i2c_adapter_by_node(adapter_np);	113	adapter = of_find_i2c_adapter_by_node(adapter_np);
		114	of_node_put(adapter_np);
114	if (!adapter) {	115	if (!adapter) {
115	dev_err(mux->dev, "Cannot find parent bus\n");	116	dev_err(mux->dev, "Cannot find parent bus\n");
116	return -EPROBE_DEFER;	117	return -EPROBE_DEFER;

drivers/i2c/muxes/i2c-mux-reg.c+290−0

@@ -0,0 +1,290 @@
	1	/*
	2	* I2C multiplexer using a single register
	3	*
	4	* Copyright 2015 Freescale Semiconductor
	5	* York Sun <yorksun@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#include <linux/i2c.h>
	14	#include <linux/i2c-mux.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/of_address.h>
	19	#include <linux/platform_data/i2c-mux-reg.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
	22
	23	struct regmux {
	24	struct i2c_adapter *parent;
	25	struct i2c_adapter *adap; / child busses */
	26	struct i2c_mux_reg_platform_data data;
	27	};
	28
	29	static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id)
	30	{
	31	if (!mux->data.reg)
	32	return -EINVAL;
	33
	34	/*
	35	* Write to the register, followed by a read to ensure the write is
	36	* completed on a "posted" bus, for example PCI or write buffers.
	37	* The endianness of reading doesn't matter and the return data
	38	* is not used.
	39	*/
	40	switch (mux->data.reg_size) {
	41	case 4:
	42	if (mux->data.little_endian)
	43	iowrite32(chan_id, mux->data.reg);
	44	else
	45	iowrite32be(chan_id, mux->data.reg);
	46	if (!mux->data.write_only)
	47	ioread32(mux->data.reg);
	48	break;
	49	case 2:
	50	if (mux->data.little_endian)
	51	iowrite16(chan_id, mux->data.reg);
	52	else
	53	iowrite16be(chan_id, mux->data.reg);
	54	if (!mux->data.write_only)
	55	ioread16(mux->data.reg);
	56	break;
	57	case 1:
	58	iowrite8(chan_id, mux->data.reg);
	59	if (!mux->data.write_only)
	60	ioread8(mux->data.reg);
	61	break;
	62	}
	63
	64	return 0;
	65	}
	66
	67	static int i2c_mux_reg_select(struct i2c_adapter adap, void data,
	68	unsigned int chan)
	69	{
	70	struct regmux *mux = data;
	71
	72	return i2c_mux_reg_set(mux, chan);
	73	}
	74
	75	static int i2c_mux_reg_deselect(struct i2c_adapter adap, void data,
	76	unsigned int chan)
	77	{
	78	struct regmux *mux = data;
	79
	80	if (mux->data.idle_in_use)
	81	return i2c_mux_reg_set(mux, mux->data.idle);
	82
	83	return 0;
	84	}
	85
	86	#ifdef CONFIG_OF
	87	static int i2c_mux_reg_probe_dt(struct regmux *mux,
	88	struct platform_device *pdev)
	89	{
	90	struct device_node *np = pdev->dev.of_node;
	91	struct device_node adapter_np, child;
	92	struct i2c_adapter *adapter;
	93	struct resource res;
	94	unsigned *values;
	95	int i = 0;
	96
	97	if (!np)
	98	return -ENODEV;
	99
	100	adapter_np = of_parse_phandle(np, "i2c-parent", 0);
	101	if (!adapter_np) {
	102	dev_err(&pdev->dev, "Cannot parse i2c-parent\n");
	103	return -ENODEV;
	104	}
	105	adapter = of_find_i2c_adapter_by_node(adapter_np);
	106	of_node_put(adapter_np);
	107	if (!adapter)
	108	return -EPROBE_DEFER;
	109
	110	mux->parent = adapter;
	111	mux->data.parent = i2c_adapter_id(adapter);
	112	put_device(&adapter->dev);
	113
	114	mux->data.n_values = of_get_child_count(np);
	115	if (of_find_property(np, "little-endian", NULL)) {
	116	mux->data.little_endian = true;
	117	} else if (of_find_property(np, "big-endian", NULL)) {
	118	mux->data.little_endian = false;
	119	} else {
	120	#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : \
	121	defined(__LITTLE_ENDIAN)
	122	mux->data.little_endian = true;
	123	#elif defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : \
	124	defined(__BIG_ENDIAN)
	125	mux->data.little_endian = false;
	126	#else
	127	#error Endianness not defined?
	128	#endif
	129	}
	130	if (of_find_property(np, "write-only", NULL))
	131	mux->data.write_only = true;
	132	else
	133	mux->data.write_only = false;
	134
	135	values = devm_kzalloc(&pdev->dev,
	136	sizeof(mux->data.values) mux->data.n_values,
	137	GFP_KERNEL);
	138	if (!values) {
	139	dev_err(&pdev->dev, "Cannot allocate values array");
	140	return -ENOMEM;
	141	}
	142
	143	for_each_child_of_node(np, child) {
	144	of_property_read_u32(child, "reg", values + i);
	145	i++;
	146	}
	147	mux->data.values = values;
	148
	149	if (!of_property_read_u32(np, "idle-state", &mux->data.idle))
	150	mux->data.idle_in_use = true;
	151
	152	/* map address from "reg" if exists */
	153	if (of_address_to_resource(np, 0, &res)) {
	154	mux->data.reg_size = resource_size(&res);
	155	mux->data.reg = devm_ioremap_resource(&pdev->dev, &res);
	156	if (IS_ERR(mux->data.reg))
	157	return PTR_ERR(mux->data.reg);
	158	}
	159
	160	return 0;
	161	}
	162	#else
	163	static int i2c_mux_reg_probe_dt(struct regmux *mux,
	164	struct platform_device *pdev)
	165	{
	166	return 0;
	167	}
	168	#endif
	169
	170	static int i2c_mux_reg_probe(struct platform_device *pdev)
	171	{
	172	struct regmux *mux;
	173	struct i2c_adapter *parent;
	174	struct resource *res;
	175	int (deselect)(struct i2c_adapter , void *, u32);
	176	unsigned int class;
	177	int i, ret, nr;
	178
	179	mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL);
	180	if (!mux)
	181	return -ENOMEM;
	182
	183	platform_set_drvdata(pdev, mux);
	184
	185	if (dev_get_platdata(&pdev->dev)) {
	186	memcpy(&mux->data, dev_get_platdata(&pdev->dev),
	187	sizeof(mux->data));
	188
	189	parent = i2c_get_adapter(mux->data.parent);
	190	if (!parent)
	191	return -EPROBE_DEFER;
	192
	193	mux->parent = parent;
	194	} else {
	195	ret = i2c_mux_reg_probe_dt(mux, pdev);
	196	if (ret < 0) {
	197	dev_err(&pdev->dev, "Error parsing device tree");
	198	return ret;
	199	}
	200	}
	201
	202	if (!mux->data.reg) {
	203	dev_info(&pdev->dev,
	204	"Register not set, using platform resource\n");
	205	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	206	mux->data.reg_size = resource_size(res);
	207	mux->data.reg = devm_ioremap_resource(&pdev->dev, res);
	208	if (IS_ERR(mux->data.reg))
	209	return PTR_ERR(mux->data.reg);
	210	}
	211
	212	if (mux->data.reg_size != 4 && mux->data.reg_size != 2 &&
	213	mux->data.reg_size != 1) {
	214	dev_err(&pdev->dev, "Invalid register size\n");
	215	return -EINVAL;
	216	}
	217
	218	mux->adap = devm_kzalloc(&pdev->dev,
	219	sizeof(mux->adap) mux->data.n_values,
	220	GFP_KERNEL);
	221	if (!mux->adap) {
	222	dev_err(&pdev->dev, "Cannot allocate i2c_adapter structure");
	223	return -ENOMEM;
	224	}
	225
	226	if (mux->data.idle_in_use)
	227	deselect = i2c_mux_reg_deselect;
	228	else
	229	deselect = NULL;
	230
	231	for (i = 0; i < mux->data.n_values; i++) {
	232	nr = mux->data.base_nr ? (mux->data.base_nr + i) : 0;
	233	class = mux->data.classes ? mux->data.classes[i] : 0;
	234
	235	mux->adap[i] = i2c_add_mux_adapter(mux->parent, &pdev->dev, mux,
	236	nr, mux->data.values[i],
	237	class, i2c_mux_reg_select,
	238	deselect);
	239	if (!mux->adap[i]) {
	240	ret = -ENODEV;
	241	dev_err(&pdev->dev, "Failed to add adapter %d\n", i);
	242	goto add_adapter_failed;
	243	}
	244	}
	245
	246	dev_dbg(&pdev->dev, "%d port mux on %s adapter\n",
	247	mux->data.n_values, mux->parent->name);
	248
	249	return 0;
	250
	251	add_adapter_failed:
	252	for (; i > 0; i--)
	253	i2c_del_mux_adapter(mux->adap[i - 1]);
	254
	255	return ret;
	256	}
	257
	258	static int i2c_mux_reg_remove(struct platform_device *pdev)
	259	{
	260	struct regmux *mux = platform_get_drvdata(pdev);
	261	int i;
	262
	263	for (i = 0; i < mux->data.n_values; i++)
	264	i2c_del_mux_adapter(mux->adap[i]);
	265
	266	i2c_put_adapter(mux->parent);
	267
	268	return 0;
	269	}
	270
	271	static const struct of_device_id i2c_mux_reg_of_match[] = {
	272	{ .compatible = "i2c-mux-reg", },
	273	{},
	274	};
	275	MODULE_DEVICE_TABLE(of, i2c_mux_reg_of_match);
	276
	277	static struct platform_driver i2c_mux_reg_driver = {
	278	.probe = i2c_mux_reg_probe,
	279	.remove = i2c_mux_reg_remove,
	280	.driver = {
	281	.name = "i2c-mux-reg",
	282	},
	283	};
	284
	285	module_platform_driver(i2c_mux_reg_driver);
	286
	287	MODULE_DESCRIPTION("Register-based I2C multiplexer driver");
	288	MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
	289	MODULE_LICENSE("GPL");
	290	MODULE_ALIAS("platform:i2c-mux-reg");

drivers/misc/eeprom/at24.c+6−31

@@ -186,19 +186,11 @@ static ssize_t at24_eeprom_read(struct at24_data at24, char buf, · 185 unmodified lines
186	if (count > io_limit)	186	if (count > io_limit)
187	count = io_limit;	187	count = io_limit;
188		188
189	switch (at24->use_smbus) {	189	if (at24->use_smbus) {
190	case I2C_SMBUS_I2C_BLOCK_DATA:
191	/* Smaller eeproms can work given some SMBus extension calls */	190	/* Smaller eeproms can work given some SMBus extension calls */
192	if (count > I2C_SMBUS_BLOCK_MAX)	191	if (count > I2C_SMBUS_BLOCK_MAX)
193	count = I2C_SMBUS_BLOCK_MAX;	192	count = I2C_SMBUS_BLOCK_MAX;
194	break;	193	} else {
195	case I2C_SMBUS_WORD_DATA:
196	count = 2;
197	break;
198	case I2C_SMBUS_BYTE_DATA:
199	count = 1;
200	break;
201	default:
202	/*	194	/*
203	* When we have a better choice than SMBus calls, use a	195	* When we have a better choice than SMBus calls, use a
204	* combined I2C message. Write address; then read up to	196	* combined I2C message. Write address; then read up to
@@ -229,27 +221,10 @@ static ssize_t at24_eeprom_read(struct at24_data at24, char buf, · 24 unmodified lines
229	timeout = jiffies + msecs_to_jiffies(write_timeout);	221	timeout = jiffies + msecs_to_jiffies(write_timeout);
230	do {	222	do {
231	read_time = jiffies;	223	read_time = jiffies;
232	switch (at24->use_smbus) {	224	if (at24->use_smbus) {
233	case I2C_SMBUS_I2C_BLOCK_DATA:	225	status = i2c_smbus_read_i2c_block_data_or_emulated(client, offset,
234	status = i2c_smbus_read_i2c_block_data(client, offset,	226	count, buf);
235	count, buf);	227	} else {
236	break;
237	case I2C_SMBUS_WORD_DATA:
238	status = i2c_smbus_read_word_data(client, offset);
239	if (status >= 0) {
240	buf[0] = status & 0xff;
241	buf[1] = status >> 8;
242	status = count;
243	}
244	break;
245	case I2C_SMBUS_BYTE_DATA:
246	status = i2c_smbus_read_byte_data(client, offset);
247	if (status >= 0) {
248	buf[0] = status;
249	status = count;
250	}
251	break;
252	default:
253	status = i2c_transfer(client->adapter, msg, 2);	228	status = i2c_transfer(client->adapter, msg, 2);
254	if (status == 2)	229	if (status == 2)
255	status = count;	230	status = count;

drivers/misc/eeprom/max6875.c+1−0

@@ -191,6 +191,7 @@ static const struct i2c_device_id max6875_id[] = { · 190 unmodified lines
191	{ "max6875", 0 },	191	{ "max6875", 0 },
192	{ }	192	{ }
193	};	193	};
		194	MODULE_DEVICE_TABLE(i2c, max6875_id);
194		195
195	static struct i2c_driver max6875_driver = {	196	static struct i2c_driver max6875_driver = {
196	.driver = {	197	.driver = {

drivers/of/irq.c+1−0

@@ -432,6 +432,7 @@ int of_irq_get_byname(struct device_node dev, const char name) · 431 unmodified lines
432		432
433	return of_irq_get(dev, index);	433	return of_irq_get(dev, index);
434	}	434	}
		435	EXPORT_SYMBOL_GPL(of_irq_get_byname);
435		436
436	/**	437	/**
437	* of_irq_count - Count the number of IRQs a node uses	438	* of_irq_count - Count the number of IRQs a node uses

include/dt-bindings/i2c/i2c.h+18−0

@@ -0,0 +1,18 @@
	1	/*
	2	* This header provides constants for I2C bindings
	3	*
	4	* Copyright (C) 2015 by Sang Engineering
	5	* Copyright (C) 2015 by Renesas Electronics Corporation
	6	*
	7	* Wolfram Sang <wsa@sang-engineering.com>
	8	*
	9	* GPLv2 only
	10	*/
	11
	12	#ifndef _DT_BINDINGS_I2C_I2C_H
	13	#define _DT_BINDINGS_I2C_I2C_H
	14
	15	#define I2C_TEN_BIT_ADDRESS (1 << 31)
	16	#define I2C_OWN_SLAVE_ADDRESS (1 << 30)
	17
	18	#endif

include/linux/i2c.h+15−4

 extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client,
 					  u8 command, u8 length,
 					  const u8 *values);
+extern s32
+i2c_smbus_read_i2c_block_data_or_emulated(const struct i2c_client *client,
+					  u8 command, u8 length, u8 *values);
 #endif /* I2C */
 /**
 void i2c_unlock_adapter(struct i2c_adapter *);
 /*flags for the client struct: */
-#define I2C_CLIENT_PEC	0x04		/* Use Packet Error Checking */
+#define I2C_CLIENT_PEC		0x04	/* Use Packet Error Checking */
-#define I2C_CLIENT_TEN	0x10		/* we have a ten bit chip address */
+#define I2C_CLIENT_TEN		0x10	/* we have a ten bit chip address */
 					/* Must equal I2C_M_TEN below */
-#define I2C_CLIENT_WAKE	0x80		/* for board_info; true iff can wake */
+#define I2C_CLIENT_SLAVE	0x20	/* we are the slave */
-#define I2C_CLIENT_SCCB	0x9000		/* Use Omnivision SCCB protocol */
+#define I2C_CLIENT_WAKE		0x80	/* for board_info; true iff can wake */
+#define I2C_CLIENT_SCCB		0x9000	/* Use Omnivision SCCB protocol */
 					/* Must match I2C_M_STOP|IGNORE_NAK */
 /* i2c adapter classes (bitmask) */
 /* must call put_device() when done with returned i2c_adapter device */
 extern struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node);
+/* must call i2c_put_adapter() when done with returned i2c_adapter device */
+struct i2c_adapter *of_get_i2c_adapter_by_node(struct device_node *node);
 #else
 static inline struct i2c_client *of_find_i2c_device_by_node(struct device_node *node)
 {
 	return NULL;
 }
+static inline struct i2c_adapter *of_get_i2c_adapter_by_node(struct device_node *node)
+{
+	return NULL;
+}
 #endif /* CONFIG_OF */
 #endif /* _LINUX_I2C_H */

include/linux/platform_data/i2c-mux-reg.h+44−0

@@ -0,0 +1,44 @@
	1	/*
	2	* I2C multiplexer using a single register
	3	*
	4	* Copyright 2015 Freescale Semiconductor
	5	* York Sun <yorksun@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#ifndef __LINUX_PLATFORM_DATA_I2C_MUX_REG_H
	14	#define __LINUX_PLATFORM_DATA_I2C_MUX_REG_H
	15
	16	/**
	17	* struct i2c_mux_reg_platform_data - Platform-dependent data for i2c-mux-reg
	18	* @parent: Parent I2C bus adapter number
	19	* @base_nr: Base I2C bus number to number adapters from or zero for dynamic
	20	* @values: Array of value for each channel
	21	* @n_values: Number of multiplexer channels
	22	* @little_endian: Indicating if the register is in little endian
	23	* @write_only: Reading the register is not allowed by hardware
	24	* @classes: Optional I2C auto-detection classes
	25	* @idle: Value to write to mux when idle
	26	* @idle_in_use: indicate if idle value is in use
	27	* @reg: Virtual address of the register to switch channel
	28	* @reg_size: register size in bytes
	29	*/
	30	struct i2c_mux_reg_platform_data {
	31	int parent;
	32	int base_nr;
	33	const unsigned int *values;
	34	int n_values;
	35	bool little_endian;
	36	bool write_only;
	37	const unsigned int *classes;
	38	u32 idle;
	39	bool idle_in_use;
	40	void __iomem *reg;
	41	resource_size_t reg_size;
	42	};
	43
	44	#endif /* __LINUX_PLATFORM_DATA_I2C_MUX_REG_H */