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| @@ -465,16 +465,27 @@ struct iommu_hwpt_arm_smmuv3 { · 464 unmodified lines | |||
| 465 | __aligned_le64 ste[2]; | 465 | __aligned_le64 ste[2]; |
| 466 | }; | 466 | }; |
| 467 | 467 | ||
| 468 | /** | ||
| 469 | * struct iommu_hwpt_amd_guest - AMD IOMMU guest I/O page table data | ||
| 470 | * (IOMMU_HWPT_DATA_AMD_GUEST) | ||
| 471 | * @dte: Guest Device Table Entry (DTE) | ||
| 472 | */ | ||
| 473 | struct iommu_hwpt_amd_guest { | ||
| 474 | __aligned_u64 dte[4]; | ||
| 475 | }; | ||
| 476 | |||
| 468 | /** | 477 | /** |
| 469 | * enum iommu_hwpt_data_type - IOMMU HWPT Data Type | 478 | * enum iommu_hwpt_data_type - IOMMU HWPT Data Type |
| 470 | * @IOMMU_HWPT_DATA_NONE: no data | 479 | * @IOMMU_HWPT_DATA_NONE: no data |
| 471 | * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table | 480 | * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table |
| 472 | * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table | 481 | * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table |
| 482 | * @IOMMU_HWPT_DATA_AMD_GUEST: AMD IOMMU guest page table | ||
| 473 | */ | 483 | */ |
| 474 | enum iommu_hwpt_data_type { | 484 | enum iommu_hwpt_data_type { |
| 475 | IOMMU_HWPT_DATA_NONE = 0, | 485 | IOMMU_HWPT_DATA_NONE = 0, |
| 476 | IOMMU_HWPT_DATA_VTD_S1 = 1, | 486 | IOMMU_HWPT_DATA_VTD_S1 = 1, |
| 477 | IOMMU_HWPT_DATA_ARM_SMMUV3 = 2, | 487 | IOMMU_HWPT_DATA_ARM_SMMUV3 = 2, |
| 488 | IOMMU_HWPT_DATA_AMD_GUEST = 3, | ||
| 478 | }; | 489 | }; |
| 479 | 490 | ||
| 480 | /** | 491 | /** |
| @@ -623,6 +634,32 @@ struct iommu_hw_info_tegra241_cmdqv { · 142 unmodified lines | |||
| 623 | __u8 __reserved; | 634 | __u8 __reserved; |
| 624 | }; | 635 | }; |
| 625 | 636 | ||
| 637 | /** | ||
| 638 | * struct iommu_hw_info_amd - AMD IOMMU device info | ||
| 639 | * | ||
| 640 | * @efr : Value of AMD IOMMU Extended Feature Register (EFR) | ||
| 641 | * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) | ||
| 642 | * | ||
| 643 | * Please See description of these registers in the following sections of | ||
| 644 | * the AMD I/O Virtualization Technology (IOMMU) Specification. | ||
| 645 | * (https://docs.amd.com/v/u/en-US/48882_3.10_PUB) | ||
| 646 | * | ||
| 647 | * - MMIO Offset 0030h IOMMU Extended Feature Register | ||
| 648 | * - MMIO Offset 01A0h IOMMU Extended Feature 2 Register | ||
| 649 | * | ||
| 650 | * Note: The EFR and EFR2 are raw values reported by hardware. | ||
| 651 | * VMM is responsible to determine the appropriate flags to be exposed to | ||
| 652 | * the VM since cetertain features are not currently supported by the kernel | ||
| 653 | * for HW-vIOMMU. | ||
| 654 | * | ||
| 655 | * Current VMM-allowed list of feature flags are: | ||
| 656 | * - EFR[GTSup, GASup, GioSup, PPRSup, EPHSup, GATS, GLX, PASmax] | ||
| 657 | */ | ||
| 658 | struct iommu_hw_info_amd { | ||
| 659 | __aligned_u64 efr; | ||
| 660 | __aligned_u64 efr2; | ||
| 661 | }; | ||
| 662 | |||
| 626 | /** | 663 | /** |
| 627 | * enum iommu_hw_info_type - IOMMU Hardware Info Types | 664 | * enum iommu_hw_info_type - IOMMU Hardware Info Types |
| 628 | * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware | 665 | * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware |
| @@ -632,6 +669,7 @@ struct iommu_hw_info_tegra241_cmdqv { · 3 unmodified lines | |||
| 632 | * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type | 669 | * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type |
| 633 | * @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM | 670 | * @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM |
| 634 | * SMMUv3) info type | 671 | * SMMUv3) info type |
| 672 | * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type | ||
| 635 | */ | 673 | */ |
| 636 | enum iommu_hw_info_type { | 674 | enum iommu_hw_info_type { |
| 637 | IOMMU_HW_INFO_TYPE_NONE = 0, | 675 | IOMMU_HW_INFO_TYPE_NONE = 0, |
| @@ -639,6 +677,7 @@ enum iommu_hw_info_type { · 1 unmodified line | |||
| 639 | IOMMU_HW_INFO_TYPE_INTEL_VTD = 1, | 677 | IOMMU_HW_INFO_TYPE_INTEL_VTD = 1, |
| 640 | IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, | 678 | IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, |
| 641 | IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, | 679 | IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, |
| 680 | IOMMU_HW_INFO_TYPE_AMD = 4, | ||
| 642 | }; | 681 | }; |
| 643 | 682 | ||
| 644 | /** | 683 | /** |
| @@ -964,6 +964,10 @@ struct vfio_device_bind_iommufd { · 963 unmodified lines | |||
| 964 | * hwpt corresponding to the given pt_id. | 964 | * hwpt corresponding to the given pt_id. |
| 965 | * | 965 | * |
| 966 | * Return: 0 on success, -errno on failure. | 966 | * Return: 0 on success, -errno on failure. |
| 967 | * | ||
| 968 | * When a device is resetting, -EBUSY will be returned to reject any concurrent | ||
| 969 | * attachment to the resetting device itself or any sibling device in the IOMMU | ||
| 970 | * group having the resetting device. | ||
| 967 | */ | 971 | */ |
| 968 | struct vfio_device_attach_iommufd_pt { | 972 | struct vfio_device_attach_iommufd_pt { |
| 969 | __u32 argsz; | 973 | __u32 argsz; |