History

Merge tag 'drm-fixes-2021-11-19' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "This week's fixes, pretty quiet, about right for rc2. amdgpu is the bulk of them but the scheduler ones have been reported in a few places I think. Otherwise just some minor i915 fixes and a few other scattered around: scheduler: - two refcounting fixes cma-helper: - use correct free path for noncoherent efifb: - probing fix amdgpu: - Better debugging info for SMU msgs - Better error reporting when adding IP blocks - Fix UVD powergating regression on CZ - Clock reporting fix for navi1x - OLED panel backlight fix - Fix scaling on VGA/DVI for non-DC display code - Fix GLFCLK handling for RGP on some APUs - fix potential memory leak amdkfd: - GPU reset fix i915: - return error handling fix - ADL-P display fix - TGL DSI display clocks fix nouveau: - infoframe corruption fix sun4i: - Kconfig fix" * tag 'drm-fixes-2021-11-19' of git://anongit.freedesktop.org/drm/drm: drm/amd/amdgpu: fix potential memleak drm/amd/amdkfd: Fix kernel panic when reset failed and been triggered again drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUs drm/amdgpu: fix set scaling mode Full/Full aspect/Center not works on vga and dvi connectors drm/amd/display: Fix OLED brightness control on eDP drm/amd/pm: Remove artificial freq level on Navi1x drm/amd/pm: avoid duplicate powergate/ungate setting drm/amdgpu: add error print when failing to add IP block(v2) drm/amd/pm: Enhanced reporting also for a stuck command drm/i915/guc: fix NULL vs IS_ERR() checking drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping" fbdev: Prevent probing generic drivers if a FB is already registered drm/scheduler: fix drm_sched_job_add_implicit_dependencies harder drm/scheduler: fix drm_sched_job_add_implicit_dependencies drm/sun4i: fix unmet dependency on RESET_CONTROLLER for PHY_SUN6I_MIPI_DPHY drm/cma-helper: Release non-coherent memory with dma_free_noncoherent() drm/nouveau: hdmigv100.c: fix corrupted HDMI Vendor InfoFrame

Linus Torvalds committed 4 years ago

Commit ad445182 parents 0dc636b 7d5104024 files · +200 −27Browse files

Unified · Split

24 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +1 −0
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +3 −0
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +36 −0
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +1 −0
  5. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +5 −0
  6. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +2 −1
  7. drivers/gpu/drm/amd/include/amd_shared.h +2 −1
  8. drivers/gpu/drm/amd/pm/amdgpu_dpm.c +10 −0
  9. drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +8 −0
  10. drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +20 −2
  11. drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +8 −5
  12. drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +26 −0
  13. drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +27 −0
  14. drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h +1 −0
  15. drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +6 −2
  16. drivers/gpu/drm/drm_gem_cma_helper.c +7 −2
  17. drivers/gpu/drm/i915/display/icl_dsi.c +4 −9
  18. drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +2 −2
  19. drivers/gpu/drm/i915/i915_reg.h +3 −1
  20. drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c +0 −1
  21. drivers/gpu/drm/scheduler/sched_main.c +5 −1
  22. drivers/gpu/drm/sun4i/Kconfig +1 −0
  23. drivers/video/fbdev/efifb.c +11 −0
  24. drivers/video/fbdev/simplefb.c +11 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+1−0
@@ -827,6 +827,7 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) · 826 unmodified lines
827 827
828 amdgpu_connector_get_edid(connector);828 amdgpu_connector_get_edid(connector);
829 ret = amdgpu_connector_ddc_get_modes(connector);829 ret = amdgpu_connector_ddc_get_modes(connector);
830 amdgpu_get_native_mode(connector);
830 831
831 return ret;832 return ret;
832}833}
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+3−0
@@ -3509,6 +3509,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 3508 unmodified lines
3509 adev->rmmio_size = pci_resource_len(adev->pdev, 2);3509 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3510 }3510 }
3511 3511
3512 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3513 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3514
3512 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);3515 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3513 if (adev->rmmio == NULL) {3516 if (adev->rmmio == NULL) {
3514 return -ENOMEM;3517 return -ENOMEM;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+36−0
@@ -587,6 +587,9 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) · 586 unmodified lines
587 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);587 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
588 break;588 break;
589 default:589 default:
590 dev_err(adev->dev,
591 "Failed to add common ip block(GC_HWIP:0x%x)\n",
592 adev->ip_versions[GC_HWIP][0]);
590 return -EINVAL;593 return -EINVAL;
591 }594 }
592 return 0;595 return 0;
@@ -619,6 +622,9 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) · 26 unmodified lines
619 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);622 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
620 break;623 break;
621 default:624 default:
625 dev_err(adev->dev,
626 "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
627 adev->ip_versions[GC_HWIP][0]);
622 return -EINVAL;628 return -EINVAL;
623 }629 }
624 return 0;630 return 0;
@@ -648,6 +654,9 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) · 23 unmodified lines
648 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);654 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
649 break;655 break;
650 default:656 default:
657 dev_err(adev->dev,
658 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
659 adev->ip_versions[OSSSYS_HWIP][0]);
651 return -EINVAL;660 return -EINVAL;
652 }661 }
653 return 0;662 return 0;
@@ -688,6 +697,9 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) · 34 unmodified lines
688 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);697 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
689 break;698 break;
690 default:699 default:
700 dev_err(adev->dev,
701 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
702 adev->ip_versions[MP0_HWIP][0]);
691 return -EINVAL;703 return -EINVAL;
692 }704 }
693 return 0;705 return 0;
@@ -726,6 +738,9 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) · 32 unmodified lines
726 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);738 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
727 break;739 break;
728 default:740 default:
741 dev_err(adev->dev,
742 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
743 adev->ip_versions[MP1_HWIP][0]);
729 return -EINVAL;744 return -EINVAL;
730 }745 }
731 return 0;746 return 0;
@@ -753,6 +768,9 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) · 21 unmodified lines
753 amdgpu_device_ip_block_add(adev, &dm_ip_block);768 amdgpu_device_ip_block_add(adev, &dm_ip_block);
754 break;769 break;
755 default:770 default:
771 dev_err(adev->dev,
772 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
773 adev->ip_versions[DCE_HWIP][0]);
756 return -EINVAL;774 return -EINVAL;
757 }775 }
758 } else if (adev->ip_versions[DCI_HWIP][0]) {776 } else if (adev->ip_versions[DCI_HWIP][0]) {
@@ -763,6 +781,9 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) · 4 unmodified lines
763 amdgpu_device_ip_block_add(adev, &dm_ip_block);781 amdgpu_device_ip_block_add(adev, &dm_ip_block);
764 break;782 break;
765 default:783 default:
784 dev_err(adev->dev,
785 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
786 adev->ip_versions[DCI_HWIP][0]);
766 return -EINVAL;787 return -EINVAL;
767 }788 }
768#endif789#endif
@@ -796,6 +817,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) · 27 unmodified lines
796 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);817 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
797 break;818 break;
798 default:819 default:
820 dev_err(adev->dev,
821 "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
822 adev->ip_versions[GC_HWIP][0]);
799 return -EINVAL;823 return -EINVAL;
800 }824 }
801 return 0;825 return 0;
@@ -829,6 +853,9 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) · 27 unmodified lines
829 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);853 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
830 break;854 break;
831 default:855 default:
856 dev_err(adev->dev,
857 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
858 adev->ip_versions[SDMA0_HWIP][0]);
832 return -EINVAL;859 return -EINVAL;
833 }860 }
834 return 0;861 return 0;
@@ -845,6 +872,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) · 10 unmodified lines
845 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);872 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
846 break;873 break;
847 default:874 default:
875 dev_err(adev->dev,
876 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
877 adev->ip_versions[UVD_HWIP][0]);
848 return -EINVAL;878 return -EINVAL;
849 }879 }
850 switch (adev->ip_versions[VCE_HWIP][0]) {880 switch (adev->ip_versions[VCE_HWIP][0]) {
@@ -855,6 +885,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) · 4 unmodified lines
855 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);885 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
856 break;886 break;
857 default:887 default:
888 dev_err(adev->dev,
889 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
890 adev->ip_versions[VCE_HWIP][0]);
858 return -EINVAL;891 return -EINVAL;
859 }892 }
860 } else {893 } else {
@@ -893,6 +926,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) · 32 unmodified lines
893 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);926 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
894 break;927 break;
895 default:928 default:
929 dev_err(adev->dev,
930 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
931 adev->ip_versions[UVD_HWIP][0]);
896 return -EINVAL;932 return -EINVAL;
897 }933 }
898 }934 }
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+1−0
@@ -386,6 +386,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) · 385 unmodified lines
386 "%s", "xgmi_hive_info");386 "%s", "xgmi_hive_info");
387 if (ret) {387 if (ret) {
388 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");388 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
389 kobject_put(&hive->kobj);
389 kfree(hive);390 kfree(hive);
390 hive = NULL;391 hive = NULL;
391 goto pro_end;392 goto pro_end;
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+5−0
@@ -1226,6 +1226,11 @@ static int stop_cpsch(struct device_queue_manager *dqm) · 1225 unmodified lines
1226 bool hanging;1226 bool hanging;
1227 1227
1228 dqm_lock(dqm);1228 dqm_lock(dqm);
1229 if (!dqm->sched_running) {
1230 dqm_unlock(dqm);
1231 return 0;
1232 }
1233
1229 if (!dqm->is_hws_hang)1234 if (!dqm->is_hws_hang)
1230 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);1235 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1231 hanging = dqm->is_hws_hang || dqm->is_resetting;1236 hanging = dqm->is_hws_hang || dqm->is_resetting;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+2−1
@@ -4242,7 +4242,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 4241 unmodified lines
4242 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {4242 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4243 amdgpu_dm_update_connector_after_detect(aconnector);4243 amdgpu_dm_update_connector_after_detect(aconnector);
4244 register_backlight_device(dm, link);4244 register_backlight_device(dm, link);
4245 4245 if (dm->num_of_edps)
4246 update_connector_ext_caps(aconnector);
4246 if (psr_feature_enabled)4247 if (psr_feature_enabled)
4247 amdgpu_dm_set_psr_caps(link);4248 amdgpu_dm_set_psr_caps(link);
4248 }4249 }
drivers/gpu/drm/amd/include/amd_shared.h+2−1
@@ -98,7 +98,8 @@ enum amd_ip_block_type { · 97 unmodified lines
98 AMD_IP_BLOCK_TYPE_ACP,98 AMD_IP_BLOCK_TYPE_ACP,
99 AMD_IP_BLOCK_TYPE_VCN,99 AMD_IP_BLOCK_TYPE_VCN,
100 AMD_IP_BLOCK_TYPE_MES,100 AMD_IP_BLOCK_TYPE_MES,
101 AMD_IP_BLOCK_TYPE_JPEG101 AMD_IP_BLOCK_TYPE_JPEG,
102 AMD_IP_BLOCK_TYPE_NUM,
102};103};
103 104
104enum amd_clockgating_state {105enum amd_clockgating_state {
drivers/gpu/drm/amd/pm/amdgpu_dpm.c+10−0
@@ -927,6 +927,13 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block · 926 unmodified lines
927{927{
928 int ret = 0;928 int ret = 0;
929 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;929 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
930 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
931
932 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) {
933 dev_dbg(adev->dev, "IP block%d already in the target %s state!",
934 block_type, gate ? "gate" : "ungate");
935 return 0;
936 }
930 937
931 switch (block_type) {938 switch (block_type) {
932 case AMD_IP_BLOCK_TYPE_UVD:939 case AMD_IP_BLOCK_TYPE_UVD:
@@ -979,6 +986,9 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block · 46 unmodified lines
979 break;986 break;
980 }987 }
981 988
989 if (!ret)
990 atomic_set(&adev->pm.pwr_state[block_type], pwr_state);
991
982 return ret;992 return ret;
983}993}
984 994
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h+8−0
@@ -417,6 +417,12 @@ struct amdgpu_dpm { · 416 unmodified lines
417 enum amd_dpm_forced_level forced_level;417 enum amd_dpm_forced_level forced_level;
418};418};
419 419
420enum ip_power_state {
421 POWER_STATE_UNKNOWN,
422 POWER_STATE_ON,
423 POWER_STATE_OFF,
424};
425
420struct amdgpu_pm {426struct amdgpu_pm {
421 struct mutex mutex;427 struct mutex mutex;
422 u32 current_sclk;428 u32 current_sclk;
@@ -452,6 +458,8 @@ struct amdgpu_pm { · 29 unmodified lines
452 struct i2c_adapter smu_i2c;458 struct i2c_adapter smu_i2c;
453 struct mutex smu_i2c_mutex;459 struct mutex smu_i2c_mutex;
454 struct list_head pm_attr_list;460 struct list_head pm_attr_list;
461
462 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM];
455};463};
456 464
457#define R600_SSTU_DFLT 0465#define R600_SSTU_DFLT 0
drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c+20−2
@@ -309,6 +309,7 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu, · 308 unmodified lines
309{309{
310 int ret = 0, size = 0;310 int ret = 0, size = 0;
311 uint32_t cur_value = 0;311 uint32_t cur_value = 0;
312 int i;
312 313
313 smu_cmn_get_sysfs_buf(&buf, &size);314 smu_cmn_get_sysfs_buf(&buf, &size);
314 315
@@ -334,8 +335,6 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu, · 19 unmodified lines
334 size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",335 size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
335 CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);336 CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
336 break;337 break;
337 case SMU_GFXCLK:
338 case SMU_SCLK:
339 case SMU_FCLK:338 case SMU_FCLK:
340 case SMU_MCLK:339 case SMU_MCLK:
341 case SMU_SOCCLK:340 case SMU_SOCCLK:
@@ -346,6 +345,25 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu, · 4 unmodified lines
346 return ret;345 return ret;
347 size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);346 size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
348 break;347 break;
348 case SMU_SCLK:
349 case SMU_GFXCLK:
350 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
351 if (ret)
352 return ret;
353 if (cur_value == CYAN_SKILLFISH_SCLK_MAX)
354 i = 2;
355 else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
356 i = 0;
357 else
358 i = 1;
359 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MIN,
360 i == 0 ? "*" : "");
361 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
362 i == 1 ? cur_value : cyan_skillfish_sclk_default,
363 i == 1 ? "*" : "");
364 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MAX,
365 i == 2 ? "*" : "");
366 break;
349 default:367 default:
350 dev_warn(smu->adev->dev, "Unsupported clock type\n");368 dev_warn(smu->adev->dev, "Unsupported clock type\n");
351 return ret;369 return ret;
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c+8−5
@@ -1265,7 +1265,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, · 1264 unmodified lines
1265 enum smu_clk_type clk_type, char *buf)1265 enum smu_clk_type clk_type, char *buf)
1266{1266{
1267 uint16_t *curve_settings;1267 uint16_t *curve_settings;
1268 int i, size = 0, ret = 0;1268 int i, levels, size = 0, ret = 0;
1269 uint32_t cur_value = 0, value = 0, count = 0;1269 uint32_t cur_value = 0, value = 0, count = 0;
1270 uint32_t freq_values[3] = {0};1270 uint32_t freq_values[3] = {0};
1271 uint32_t mark_index = 0;1271 uint32_t mark_index = 0;
@@ -1319,14 +1319,17 @@ static int navi10_print_clk_levels(struct smu_context *smu, · 47 unmodified lines
1319 freq_values[1] = cur_value;1319 freq_values[1] = cur_value;
1320 mark_index = cur_value == freq_values[0] ? 0 :1320 mark_index = cur_value == freq_values[0] ? 0 :
1321 cur_value == freq_values[2] ? 2 : 1;1321 cur_value == freq_values[2] ? 2 : 1;
1322 if (mark_index != 1)
1323 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
1324 1322
1325 for (i = 0; i < 3; i++) {1323 levels = 3;
1324 if (mark_index != 1) {
1325 levels = 2;
1326 freq_values[1] = freq_values[2];
1327 }
1328
1329 for (i = 0; i < levels; i++) {
1326 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],1330 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1327 i == mark_index ? "*" : "");1331 i == mark_index ? "*" : "");
1328 }1332 }
1329
1330 }1333 }
1331 break;1334 break;
1332 case SMU_PCIE:1335 case SMU_PCIE:
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c+26−0
@@ -683,6 +683,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu, · 682 unmodified lines
683 int i, size = 0, ret = 0;683 int i, size = 0, ret = 0;
684 uint32_t cur_value = 0, value = 0, count = 0;684 uint32_t cur_value = 0, value = 0, count = 0;
685 bool cur_value_match_level = false;685 bool cur_value_match_level = false;
686 uint32_t min, max;
686 687
687 memset(&metrics, 0, sizeof(metrics));688 memset(&metrics, 0, sizeof(metrics));
688 689
@@ -743,6 +744,13 @@ static int vangogh_print_clk_levels(struct smu_context *smu, · 54 unmodified lines
743 if (ret)744 if (ret)
744 return ret;745 return ret;
745 break;746 break;
747 case SMU_GFXCLK:
748 case SMU_SCLK:
749 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
750 if (ret) {
751 return ret;
752 }
753 break;
746 default:754 default:
747 break;755 break;
748 }756 }
@@ -768,6 +776,24 @@ static int vangogh_print_clk_levels(struct smu_context *smu, · 19 unmodified lines
768 if (!cur_value_match_level)776 if (!cur_value_match_level)
769 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);777 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
770 break;778 break;
779 case SMU_GFXCLK:
780 case SMU_SCLK:
781 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
782 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
783 if (cur_value == max)
784 i = 2;
785 else if (cur_value == min)
786 i = 0;
787 else
788 i = 1;
789 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
790 i == 0 ? "*" : "");
791 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
792 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
793 i == 1 ? "*" : "");
794 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
795 i == 2 ? "*" : "");
796 break;
771 default:797 default:
772 break;798 break;
773 }799 }
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c+27−0
@@ -697,6 +697,11 @@ static int yellow_carp_get_current_clk_freq(struct smu_context *smu, · 696 unmodified lines
697 case SMU_FCLK:697 case SMU_FCLK:
698 return smu_cmn_send_smc_msg_with_param(smu,698 return smu_cmn_send_smc_msg_with_param(smu,
699 SMU_MSG_GetFclkFrequency, 0, value);699 SMU_MSG_GetFclkFrequency, 0, value);
700 case SMU_GFXCLK:
701 case SMU_SCLK:
702 return smu_cmn_send_smc_msg_with_param(smu,
703 SMU_MSG_GetGfxclkFrequency, 0, value);
704 break;
700 default:705 default:
701 return -EINVAL;706 return -EINVAL;
702 }707 }
@@ -967,6 +972,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu, · 264 unmodified lines
967{972{
968 int i, size = 0, ret = 0;973 int i, size = 0, ret = 0;
969 uint32_t cur_value = 0, value = 0, count = 0;974 uint32_t cur_value = 0, value = 0, count = 0;
975 uint32_t min, max;
970 976
971 smu_cmn_get_sysfs_buf(&buf, &size);977 smu_cmn_get_sysfs_buf(&buf, &size);
972 978
@@ -1005,6 +1011,27 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu, · 32 unmodified lines
1005 cur_value == value ? "*" : "");1011 cur_value == value ? "*" : "");
1006 }1012 }
1007 break;1013 break;
1014 case SMU_GFXCLK:
1015 case SMU_SCLK:
1016 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1017 if (ret)
1018 goto print_clk_out;
1019 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1020 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1021 if (cur_value == max)
1022 i = 2;
1023 else if (cur_value == min)
1024 i = 0;
1025 else
1026 i = 1;
1027 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
1028 i == 0 ? "*" : "");
1029 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1030 i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
1031 i == 1 ? "*" : "");
1032 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
1033 i == 2 ? "*" : "");
1034 break;
1008 default:1035 default:
1009 break;1036 break;
1010 }1037 }
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h+1−0
@@ -24,5 +24,6 @@ · 23 unmodified lines
24#define __YELLOW_CARP_PPT_H__24#define __YELLOW_CARP_PPT_H__
25 25
26extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);26extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
27#define YELLOW_CARP_UMD_PSTATE_GFXCLK 1100
27 28
28#endif29#endif
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c+6−2
@@ -139,9 +139,13 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu, · 138 unmodified lines
139 const char *message = smu_get_message_name(smu, msg);139 const char *message = smu_get_message_name(smu, msg);
140 140
141 switch (reg_c2pmsg_90) {141 switch (reg_c2pmsg_90) {
142 case SMU_RESP_NONE:142 case SMU_RESP_NONE: {
143 u32 msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
144 u32 prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
143 dev_err_ratelimited(adev->dev,145 dev_err_ratelimited(adev->dev,
144 "SMU: I'm not done with your previous command!");146 "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
147 msg_idx, prm);
148 }
145 break;149 break;
146 case SMU_RESP_OK:150 case SMU_RESP_OK:
147 /* The SMU executed the command. It completed with a151 /* The SMU executed the command. It completed with a
drivers/gpu/drm/drm_gem_cma_helper.c+7−2
@@ -210,8 +210,13 @@ void drm_gem_cma_free_object(struct drm_gem_object *gem_obj) · 209 unmodified lines
210 dma_buf_vunmap(gem_obj->import_attach->dmabuf, &map);210 dma_buf_vunmap(gem_obj->import_attach->dmabuf, &map);
211 drm_prime_gem_destroy(gem_obj, cma_obj->sgt);211 drm_prime_gem_destroy(gem_obj, cma_obj->sgt);
212 } else if (cma_obj->vaddr) {212 } else if (cma_obj->vaddr) {
213 dma_free_wc(gem_obj->dev->dev, cma_obj->base.size,213 if (cma_obj->map_noncoherent)
214 cma_obj->vaddr, cma_obj->paddr);214 dma_free_noncoherent(gem_obj->dev->dev, cma_obj->base.size,
215 cma_obj->vaddr, cma_obj->paddr,
216 DMA_TO_DEVICE);
217 else
218 dma_free_wc(gem_obj->dev->dev, cma_obj->base.size,
219 cma_obj->vaddr, cma_obj->paddr);
215 }220 }
216 221
217 drm_gem_object_release(gem_obj);222 drm_gem_object_release(gem_obj);
drivers/gpu/drm/i915/display/icl_dsi.c+4−9
@@ -696,10 +696,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, · 695 unmodified lines
696 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);696 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
697 697
698 for_each_dsi_phy(phy, intel_dsi->phys) {698 for_each_dsi_phy(phy, intel_dsi->phys) {
699 if (DISPLAY_VER(dev_priv) >= 12)699 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
700 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
701 else
702 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
703 }700 }
704 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);701 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
705 702
@@ -1135,8 +1132,6 @@ static void · 429 unmodified lines
1135gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,1132gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1136 const struct intel_crtc_state *crtc_state)1133 const struct intel_crtc_state *crtc_state)
1137{1134{
1138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1139
1140 /* step 4a: power up all lanes of the DDI used by DSI */1135 /* step 4a: power up all lanes of the DDI used by DSI */
1141 gen11_dsi_power_up_lanes(encoder);1136 gen11_dsi_power_up_lanes(encoder);
1142 1137
@@ -1162,8 +1157,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, · 19 unmodified lines
1162 gen11_dsi_configure_transcoder(encoder, crtc_state);1157 gen11_dsi_configure_transcoder(encoder, crtc_state);
1163 1158
1164 /* Step 4l: Gate DDI clocks */1159 /* Step 4l: Gate DDI clocks */
1165 if (DISPLAY_VER(dev_priv) == 11)1160 gen11_dsi_gate_clocks(encoder);
1166 gen11_dsi_gate_clocks(encoder);
1167}1161}
1168 1162
1169static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)1163static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
@@ -1271,7 +1265,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) · 101 unmodified lines
1271 if (DISPLAY_VER(i915) == 13) {1265 if (DISPLAY_VER(i915) == 13) {
1272 for_each_dsi_port(port, intel_dsi->ports)1266 for_each_dsi_port(port, intel_dsi->ports)
1273 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),1267 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
1274 TGL_DSI_CHKN_LSHS_GB, 0x4);1268 TGL_DSI_CHKN_LSHS_GB_MASK,
1269 TGL_DSI_CHKN_LSHS_GB(4));
1275 }1270 }
1276}1271}
1277 1272
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c+2−2
@@ -3080,8 +3080,8 @@ guc_create_parallel(struct intel_engine_cs **engines, · 3079 unmodified lines
3080 3080
3081 ce = intel_engine_create_virtual(siblings, num_siblings,3081 ce = intel_engine_create_virtual(siblings, num_siblings,
3082 FORCE_VIRTUAL);3082 FORCE_VIRTUAL);
3083 if (!ce) {3083 if (IS_ERR(ce)) {
3084 err = ERR_PTR(-ENOMEM);3084 err = ERR_CAST(ce);
3085 goto unwind;3085 goto unwind;
3086 }3086 }
3087 3087
drivers/gpu/drm/i915/i915_reg.h+3−1
@@ -11717,7 +11717,9 @@ enum skl_power_gate { · 11716 unmodified lines
11717#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \11717#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
11718 _TGL_DSI_CHKN_REG_0, \11718 _TGL_DSI_CHKN_REG_0, \
11719 _TGL_DSI_CHKN_REG_1)11719 _TGL_DSI_CHKN_REG_1)
11720#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)11720#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
11721#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
11722 (byte_clocks))
11721 11723
11722/* Display Stream Splitter Control */11724/* Display Stream Splitter Control */
11723#define DSS_CTL1 _MMIO(0x67400)11725#define DSS_CTL1 _MMIO(0x67400)
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c+0−1
@@ -62,7 +62,6 @@ gv100_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, · 61 unmodified lines
62 nvkm_wr32(device, 0x6f0108 + hdmi, vendor_infoframe.header);62 nvkm_wr32(device, 0x6f0108 + hdmi, vendor_infoframe.header);
63 nvkm_wr32(device, 0x6f010c + hdmi, vendor_infoframe.subpack0_low);63 nvkm_wr32(device, 0x6f010c + hdmi, vendor_infoframe.subpack0_low);
64 nvkm_wr32(device, 0x6f0110 + hdmi, vendor_infoframe.subpack0_high);64 nvkm_wr32(device, 0x6f0110 + hdmi, vendor_infoframe.subpack0_high);
65 nvkm_wr32(device, 0x6f0110 + hdmi, 0x00000000);
66 nvkm_wr32(device, 0x6f0114 + hdmi, 0x00000000);65 nvkm_wr32(device, 0x6f0114 + hdmi, 0x00000000);
67 nvkm_wr32(device, 0x6f0118 + hdmi, 0x00000000);66 nvkm_wr32(device, 0x6f0118 + hdmi, 0x00000000);
68 nvkm_wr32(device, 0x6f011c + hdmi, 0x00000000);67 nvkm_wr32(device, 0x6f011c + hdmi, 0x00000000);
drivers/gpu/drm/scheduler/sched_main.c+5−1
@@ -704,9 +704,13 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, · 703 unmodified lines
704 int ret;704 int ret;
705 705
706 dma_resv_for_each_fence(&cursor, obj->resv, write, fence) {706 dma_resv_for_each_fence(&cursor, obj->resv, write, fence) {
707 /* Make sure to grab an additional ref on the added fence */
708 dma_fence_get(fence);
707 ret = drm_sched_job_add_dependency(job, fence);709 ret = drm_sched_job_add_dependency(job, fence);
708 if (ret)710 if (ret) {
711 dma_fence_put(fence);
709 return ret;712 return ret;
713 }
710 }714 }
711 return 0;715 return 0;
712}716}
drivers/gpu/drm/sun4i/Kconfig+1−0
@@ -46,6 +46,7 @@ config DRM_SUN6I_DSI · 45 unmodified lines
46 default MACH_SUN8I46 default MACH_SUN8I
47 select CRC_CCITT47 select CRC_CCITT
48 select DRM_MIPI_DSI48 select DRM_MIPI_DSI
49 select RESET_CONTROLLER
49 select PHY_SUN6I_MIPI_DPHY50 select PHY_SUN6I_MIPI_DPHY
50 help51 help
51 Choose this option if you want have an Allwinner SoC with52 Choose this option if you want have an Allwinner SoC with
drivers/video/fbdev/efifb.c+11−0
@@ -351,6 +351,17 @@ static int efifb_probe(struct platform_device *dev) · 350 unmodified lines
351 char *option = NULL;351 char *option = NULL;
352 efi_memory_desc_t md;352 efi_memory_desc_t md;
353 353
354 /*
355 * Generic drivers must not be registered if a framebuffer exists.
356 * If a native driver was probed, the display hardware was already
357 * taken and attempting to use the system framebuffer is dangerous.
358 */
359 if (num_registered_fb > 0) {
360 dev_err(&dev->dev,
361 "efifb: a framebuffer is already registered\n");
362 return -EINVAL;
363 }
364
354 if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI || pci_dev_disabled)365 if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI || pci_dev_disabled)
355 return -ENODEV;366 return -ENODEV;
356 367
drivers/video/fbdev/simplefb.c+11−0
@@ -407,6 +407,17 @@ static int simplefb_probe(struct platform_device *pdev) · 406 unmodified lines
407 struct simplefb_par *par;407 struct simplefb_par *par;
408 struct resource *mem;408 struct resource *mem;
409 409
410 /*
411 * Generic drivers must not be registered if a framebuffer exists.
412 * If a native driver was probed, the display hardware was already
413 * taken and attempting to use the system framebuffer is dangerous.
414 */
415 if (num_registered_fb > 0) {
416 dev_err(&pdev->dev,
417 "simplefb: a framebuffer is already registered\n");
418 return -EINVAL;
419 }
420
410 if (fb_get_options("simplefb", NULL))421 if (fb_get_options("simplefb", NULL))
411 return -ENODEV;422 return -ENODEV;
412 423

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