| @@ -844,7 +844,9 @@ static inline bool platform_pci_need_resume(struct pci_dev *dev) · 843 unmodified lines |
| 844 | 844 | |
| 845 | 845 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
| 846 | 846 | { |
| 847 | | − return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; |
| 847 | + if (pci_platform_pm && pci_platform_pm->bridge_d3) |
| 848 | + return pci_platform_pm->bridge_d3(dev); |
| 849 | + return false; |
| 848 | 850 | } |
| 849 | 851 | |
| 850 | 852 | /** |
| @@ -4636,7 +4638,8 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) · 3785 unmodified lines |
| 4636 | 4638 | * pcie_wait_for_link_delay - Wait until link is active or inactive |
| 4637 | 4639 | * @pdev: Bridge device |
| 4638 | 4640 | * @active: waiting for active or inactive? |
| 4639 | | − * @delay: Delay to wait after link has become active (in ms) |
| 4641 | + * @delay: Delay to wait after link has become active (in ms). Specify %0 |
| 4642 | + * for no delay. |
| 4640 | 4643 | * |
| 4641 | 4644 | * Use this to wait till link becomes active or inactive. |
| 4642 | 4645 | */ |
| @@ -4649,10 +4652,10 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, · 6 unmodified lines |
| 4649 | 4652 | |
| 4650 | 4653 | /* |
| 4651 | 4654 | * Some controllers might not implement link active reporting. In this |
| 4652 | | − * case, we wait for 1000 + 100 ms. |
| 4655 | + * case, we wait for 1000 ms + any delay requested by the caller. |
| 4653 | 4656 | */ |
| 4654 | 4657 | if (!pdev->link_active_reporting) { |
| 4655 | | − msleep(1100); |
| 4658 | + msleep(timeout + delay); |
| 4656 | 4659 | return true; |
| 4657 | 4660 | } |
| 4658 | 4661 | |
| @@ -4677,7 +4680,7 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, · 18 unmodified lines |
| 4677 | 4680 | msleep(10); |
| 4678 | 4681 | timeout -= 10; |
| 4679 | 4682 | } |
| 4680 | | − if (active && ret) |
| 4683 | + if (active && ret && delay) |
| 4681 | 4684 | msleep(delay); |
| 4682 | 4685 | else if (ret != active) |
| 4683 | 4686 | pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", |
| @@ -4798,17 +4801,28 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) · 114 unmodified lines |
| 4798 | 4801 | if (!pcie_downstream_port(dev)) |
| 4799 | 4802 | return; |
| 4800 | 4803 | |
| 4801 | | − if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) { |
| 4802 | | − pci_dbg(dev, "waiting %d ms for downstream link\n", delay); |
| 4803 | | − msleep(delay); |
| 4804 | | − } else { |
| 4805 | | − pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", |
| 4806 | | − delay); |
| 4807 | | − if (!pcie_wait_for_link_delay(dev, true, delay)) { |
| 4804 | + /* |
| 4805 | + * Per PCIe r5.0, sec 6.6.1, for downstream ports that support |
| 4806 | + * speeds > 5 GT/s, we must wait for link training to complete |
| 4807 | + * before the mandatory delay. |
| 4808 | + * |
| 4809 | + * We can only tell when link training completes via DLL Link |
| 4810 | + * Active, which is required for downstream ports that support |
| 4811 | + * speeds > 5 GT/s (sec 7.5.3.6). Unfortunately some common |
| 4812 | + * devices do not implement Link Active reporting even when it's |
| 4813 | + * required, so we'll check for that directly instead of checking |
| 4814 | + * the supported link speed. We assume devices without Link Active |
| 4815 | + * reporting can train in 100 ms regardless of speed. |
| 4816 | + */ |
| 4817 | + if (dev->link_active_reporting) { |
| 4818 | + pci_dbg(dev, "waiting for link to train\n"); |
| 4819 | + if (!pcie_wait_for_link_delay(dev, true, 0)) { |
| 4808 | 4820 | /* Did not train, no need to wait any further */ |
| 4809 | 4821 | return; |
| 4810 | 4822 | } |
| 4811 | 4823 | } |
| 4824 | + pci_dbg(child, "waiting %d ms to become accessible\n", delay); |
| 4825 | + msleep(delay); |
| 4812 | 4826 | |
| 4813 | 4827 | if (!pci_device_is_present(child)) { |
| 4814 | 4828 | pci_dbg(child, "waiting additional %d ms to become accessible\n", delay); |