Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle: "A number of fixes all across the MIPS tree. No area is particularly standing out and things have cooled down quite nicely for a release." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Function tracer: Fix broken function tracing mips: Move __virt_addr_valid() to a place for MIPS 64 MIPS: Netlogic: Fix UP compilation on XLR MIPS: AR71xx: Fix AR71XX_PCI_MEM_SIZE MIPS: AR724x: Fix AR724X_PCI_MEM_SIZE MIPS: Lantiq: Fix cp0_perfcount_irq mapping MIPS: DSP: Fix DSP mask for registers. MIPS: Fix build failure by adding definition of pfn_pmd(). MIPS: Octeon: Fix warning. MIPS: delay.c: Check BITS_PER_LONG instead of __SIZEOF_LONG__ MIPS: PNX833x: Fix comment. MIPS: Add struct p_format to union mips_instruction. MIPS: Export <asm/break.h>. MIPS: BCM47xx: Enable SSB prerequisite SSB_DRIVER_PCICORE. MIPS: BCM47xx: Select GPIOLIB for BCMA on bcm47xx platform MIPS: vpe.c: Fix null pointer dereference in print arguments.

Linus Torvalds committed 13 years ago

Commit aeb8eed2 parents 04c2eee 58b694018 files · +67 −22Browse files

Unified · Split

18 files

arch/mips/bcm47xx/Kconfig +3 −0
arch/mips/cavium-octeon/executive/cvmx-l2c.c +5 −4
arch/mips/include/asm/dsp.h +1 −1
arch/mips/include/asm/inst.h +1 −0
arch/mips/include/asm/mach-pnx833x/war.h +1 −1
arch/mips/include/asm/pgtable-64.h +1 −0
arch/mips/include/uapi/asm/Kbuild +1 −0
arch/mips/include/uapi/asm/break.h +0 −0
arch/mips/kernel/ftrace.c +35 −1
arch/mips/kernel/mcount.S +4 −3
arch/mips/kernel/vpe.c +1 −1
arch/mips/lantiq/irq.c +1 −1
arch/mips/lib/delay.c +1 −1
arch/mips/mm/ioremap.c +0 −6
arch/mips/mm/mmap.c +6 −0
arch/mips/netlogic/xlr/setup.c +4 −1
arch/mips/pci/pci-ar71xx.c +1 −1
arch/mips/pci/pci-ar724x.c +1 −1

arch/mips/bcm47xx/Kconfig+3−0

@@ -8,8 +8,10 @@ config BCM47XX_SSB · 7 unmodified lines
8	8	select SSB_DRIVER_EXTIF
9	9	select SSB_EMBEDDED
10	10	select SSB_B43_PCI_BRIDGE if PCI
	11	+ select SSB_DRIVER_PCICORE if PCI
11	12	select SSB_PCICORE_HOSTMODE if PCI
12	13	select SSB_DRIVER_GPIO
	14	+ select GPIOLIB
13	15	default y
14	16	help
15	17	Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
@@ -25,6 +27,7 @@ config BCM47XX_BCMA · 9 unmodified lines
25	27	select BCMA_HOST_PCI if PCI
26	28	select BCMA_DRIVER_PCI_HOSTMODE if PCI
27	29	select BCMA_DRIVER_GPIO
	30	+ select GPIOLIB
28	31	default y
29	32	help
30	33	Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.

arch/mips/cavium-octeon/executive/cvmx-l2c.c+5−4

@@ -30,6 +30,7 @@ · 29 unmodified lines
30	30	* measurement, and debugging facilities.
31	31	*/
32	32
	33	+#include <linux/compiler.h>
33	34	#include <linux/irqflags.h>
34	35	#include <asm/octeon/cvmx.h>
35	36	#include <asm/octeon/cvmx-l2c.h>
@@ -285,22 +286,22 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter) · 249 unmodified lines
285	286	*/
286	287	static void fault_in(uint64_t addr, int len)
287	288	{
288		− volatile char *ptr;
289		− volatile char dummy;
	289	+ char *ptr;
	290	+
290	291	/*
291	292	* Adjust addr and length so we get all cache lines even for
292	293	* small ranges spanning two cache lines.
293	294	*/
294	295	len += addr & CVMX_CACHE_LINE_MASK;
295	296	addr &= ~CVMX_CACHE_LINE_MASK;
296		− ptr = (volatile char *)cvmx_phys_to_ptr(addr);
	297	+ ptr = cvmx_phys_to_ptr(addr);
297	298	/*
298	299	* Invalidate L1 cache to make sure all loads result in data
299	300	* being in L2.
300	301	*/
301	302	CVMX_DCACHE_INVALIDATE;
302	303	while (len > 0) {
303		− dummy += *ptr;
	304	+ ACCESS_ONCE(*ptr);
304	305	len -= CVMX_CACHE_LINE_SIZE;
305	306	ptr += CVMX_CACHE_LINE_SIZE;
306	307	}

arch/mips/include/asm/dsp.h+1−1

@@ -16,7 +16,7 @@ · 15 unmodified lines
16	16	#include <asm/mipsregs.h>
17	17
18	18	#define DSP_DEFAULT 0x00000000
19		−#define DSP_MASK 0x3ff
	19	+#define DSP_MASK 0x3f
20	20
21	21	#define __enable_dsp_hazard() \
22	22	do { \

arch/mips/include/asm/inst.h+1−0

@@ -353,6 +353,7 @@ union mips_instruction { · 352 unmodified lines
353	353	struct u_format u_format;
354	354	struct c_format c_format;
355	355	struct r_format r_format;
	356	+ struct p_format p_format;
356	357	struct f_format f_format;
357	358	struct ma_format ma_format;
358	359	struct b_format b_format;

arch/mips/include/asm/mach-pnx833x/war.h+1−1

@@ -21,4 +21,4 @@ · 20 unmodified lines
21	21	#define R10000_LLSC_WAR 0
22	22	#define MIPS34K_MISSED_ITLB_WAR 0
23	23
24		−#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
	24	+#endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */

arch/mips/include/asm/pgtable-64.h+1−0

@@ -230,6 +230,7 @@ static inline void pud_clear(pud_t *pudp) · 229 unmodified lines
230	230	#else
231	231	#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
232	232	#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) \| pgprot_val(prot))
	233	+#define pfn_pmd(pfn, prot) __pmd(((pfn) << _PFN_SHIFT) \| pgprot_val(prot))
233	234	#endif
234	235
235	236	#define __pgd_offset(address) pgd_index(address)

arch/mips/include/uapi/asm/Kbuild+1−0

@@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm · 2 unmodified lines
3	3
4	4	header-y += auxvec.h
5	5	header-y += bitsperlong.h
	6	+header-y += break.h
6	7	header-y += byteorder.h
7	8	header-y += cachectl.h
8	9	header-y += errno.h

arch/mips/include/uapi/asm/break.hrenamed from arch/mips/include/asm/break.h+0−0

File renamed without changes.

arch/mips/kernel/ftrace.c+35−1

@@ -25,6 +25,12 @@ · 24 unmodified lines
25	25	#define MCOUNT_OFFSET_INSNS 4
26	26	#endif
27	27
	28	+/* Arch override because MIPS doesn't need to run this from stop_machine() */
	29	+void arch_ftrace_update_code(int command)
	30	+{
	31	+ ftrace_modify_all_code(command);
	32	+}
	33	+
28	34	/*
29	35	* Check if the address is in kernel space
30	36	*
@@ -89,6 +95,24 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) · 58 unmodified lines
89	95	return 0;
90	96	}
91	97
	98	+#ifndef CONFIG_64BIT
	99	+static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
	100	+ unsigned int new_code2)
	101	+{
	102	+ int faulted;
	103	+
	104	+ safe_store_code(new_code1, ip, faulted);
	105	+ if (unlikely(faulted))
	106	+ return -EFAULT;
	107	+ ip += 4;
	108	+ safe_store_code(new_code2, ip, faulted);
	109	+ if (unlikely(faulted))
	110	+ return -EFAULT;
	111	+ flush_icache_range(ip, ip + 8); /* original ip + 12 */
	112	+ return 0;
	113	+}
	114	+#endif
	115	+
92	116	/*
93	117	* The details about the calling site of mcount on MIPS
94	118	*
@@ -131,8 +155,18 @@ int ftrace_make_nop(struct module *mod, · 36 unmodified lines
131	155	* needed.
132	156	*/
133	157	new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F;
134		−
	158	+#ifdef CONFIG_64BIT
135	159	return ftrace_modify_code(ip, new);
	160	+#else
	161	+ /*
	162	+ * On 32 bit MIPS platforms, gcc adds a stack adjust
	163	+ * instruction in the delay slot after the branch to
	164	+ * mcount and expects mcount to restore the sp on return.
	165	+ * This is based on a legacy API and does nothing but
	166	+ * waste instructions so it's being removed at runtime.
	167	+ */
	168	+ return ftrace_modify_code_2(ip, new, INSN_NOP);
	169	+#endif
136	170	}
137	171
138	172	int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)

arch/mips/kernel/mcount.S+4−3

@@ -46,9 +46,8 @@ · 45 unmodified lines
46	46	PTR_L a5, PT_R9(sp)
47	47	PTR_L a6, PT_R10(sp)
48	48	PTR_L a7, PT_R11(sp)
49		− PTR_ADDIU sp, PT_SIZE
50	49	#else
51		− PTR_ADDIU sp, (PT_SIZE + 8)
	50	+ PTR_ADDIU sp, PT_SIZE
52	51	#endif
53	52	.endm
54	53
@@ -69,7 +68,9 @@ NESTED(ftrace_caller, PT_SIZE, ra) · 14 unmodified lines
69	68	.globl _mcount
70	69	_mcount:
71	70	b ftrace_stub
72		− nop
	71	+ addiu sp,sp,8
	72	+
	73	+ /* When tracing is activated, it calls ftrace_caller+8 (aka here) */
73	74	lw t1, function_trace_stop
74	75	bnez t1, ftrace_stub
75	76	nop

arch/mips/kernel/vpe.c+1−1

@@ -705,7 +705,7 @@ static int vpe_run(struct vpe * v) · 704 unmodified lines
705	705
706	706	printk(KERN_WARNING
707	707	"VPE loader: TC %d is already in use.\n",
708		− t->index);
	708	+ v->tc->index);
709	709	return -ENOEXEC;
710	710	}
711	711	} else {

arch/mips/lantiq/irq.c+1−1

@@ -408,7 +408,7 @@ int __init icu_of_init(struct device_node node, struct device_node parent) · 407 unmodified lines
408	408	#endif
409	409
410	410	/* tell oprofile which irq to use */
411		− cp0_perfcount_irq = LTQ_PERF_IRQ;
	411	+ cp0_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
412	412
413	413	/*
414	414	* if the timer irq is not one of the mips irqs we need to

arch/mips/lib/delay.c+1−1

@@ -21,7 +21,7 @@ void __delay(unsigned long loops) · 20 unmodified lines
21	21	" .set noreorder \n"
22	22	" .align 3 \n"
23	23	"1: bnez %0, 1b \n"
24		−#if __SIZEOF_LONG__ == 4
	24	+#if BITS_PER_LONG == 32
25	25	" subu %0, 1 \n"
26	26	#else
27	27	" dsubu %0, 1 \n"

arch/mips/mm/ioremap.c+0−6

@@ -190,9 +190,3 @@ void __iounmap(const volatile void __iomem *addr) · 189 unmodified lines
190	190
191	191	EXPORT_SYMBOL(__ioremap);
192	192	EXPORT_SYMBOL(__iounmap);
193		−
194		−int __virt_addr_valid(const volatile void *kaddr)
195		−{
196		− return pfn_valid(PFN_DOWN(virt_to_phys(kaddr)));
197		−}
198		−EXPORT_SYMBOL_GPL(__virt_addr_valid);

arch/mips/mm/mmap.c+6−0

@@ -192,3 +192,9 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) · 191 unmodified lines
192	192
193	193	return ret;
194	194	}
	195	+
	196	+int __virt_addr_valid(const volatile void *kaddr)
	197	+{
	198	+ return pfn_valid(PFN_DOWN(virt_to_phys(kaddr)));
	199	+}
	200	+EXPORT_SYMBOL_GPL(__virt_addr_valid);

arch/mips/netlogic/xlr/setup.c+4−1

@@ -193,8 +193,11 @@ static void nlm_init_node(void) · 192 unmodified lines
193	193
194	194	void __init prom_init(void)
195	195	{
196		− int i, argv, envp; /* passed as 32 bit ptrs */
	196	+ int argv, envp; /* passed as 32 bit ptrs */
197	197	struct psb_info *prom_infop;
	198	+#ifdef CONFIG_SMP
	199	+ int i;
	200	+#endif
198	201
199	202	/* truncate to 32 bit and sign extend all args */
200	203	argv = (int *)(long)(int)fw_arg1;

arch/mips/pci/pci-ar71xx.c+1−1

@@ -24,7 +24,7 @@ · 23 unmodified lines
24	24	#include <asm/mach-ath79/pci.h>
25	25
26	26	#define AR71XX_PCI_MEM_BASE 0x10000000
27		−#define AR71XX_PCI_MEM_SIZE 0x08000000
	27	+#define AR71XX_PCI_MEM_SIZE 0x07000000
28	28
29	29	#define AR71XX_PCI_WIN0_OFFS 0x10000000
30	30	#define AR71XX_PCI_WIN1_OFFS 0x11000000

arch/mips/pci/pci-ar724x.c+1−1

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	21	#define AR724X_PCI_CTRL_SIZE 0x100
22	22
23	23	#define AR724X_PCI_MEM_BASE 0x10000000
24		−#define AR724X_PCI_MEM_SIZE 0x08000000
	24	+#define AR724X_PCI_MEM_SIZE 0x04000000
25	25
26	26	#define AR724X_PCI_REG_RESET 0x18
27	27	#define AR724X_PCI_REG_INT_STATUS 0x4c