Pull networking updates from Davic Miller: 1) Support busy polling generically, for all NAPI drivers. From Eric Dumazet. 2) Add byte/packet counter support to nft_ct, from Floriani Westphal. 3) Add RSS/XPS support to mvneta driver, from Gregory Clement. 4) Implement IPV6_HDRINCL socket option for raw sockets, from Hannes Frederic Sowa. 5) Add support for T6 adapter to cxgb4 driver, from Hariprasad Shenai. 6) Add support for VLAN device bridging to mlxsw switch driver, from Ido Schimmel. 7) Add driver for Netronome NFP4000/NFP6000, from Jakub Kicinski. 8) Provide hwmon interface to mlxsw switch driver, from Jiri Pirko. 9) Reorganize wireless drivers into per-vendor directories just like we do for ethernet drivers. From Kalle Valo. 10) Provide a way for administrators "destroy" connected sockets via the SOCK_DESTROY socket netlink diag operation. From Lorenzo Colitti. 11) Add support to add/remove multicast routes via netlink, from Nikolay Aleksandrov. 12) Make TCP keepalive settings per-namespace, from Nikolay Borisov. 13) Add forwarding and packet duplication facilities to nf_tables, from Pablo Neira Ayuso. 14) Dead route support in MPLS, from Roopa Prabhu. 15) TSO support for thunderx chips, from Sunil Goutham. 16) Add driver for IBM's System i/p VNIC protocol, from Thomas Falcon. 17) Rationalize, consolidate, and more completely document the checksum offloading facilities in the networking stack. From Tom Herbert. 18) Support aborting an ongoing scan in mac80211/cfg80211, from Vidyullatha Kanchanapally. 19) Use per-bucket spinlock for bpf hash facility, from Tom Leiming. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1375 commits) net: bnxt: always return values from _bnxt_get_max_rings net: bpf: reject invalid shifts phonet: properly unshare skbs in phonet_rcv() dwc_eth_qos: Fix dma address for multi-fragment skbs phy: remove an unneeded condition mdio: remove an unneed condition mdio_bus: NULL dereference on allocation error net: Fix typo in netdev_intersect_features net: freescale: mac-fec: Fix build error from phy_device API change net: freescale: ucc_geth: Fix build error from phy_device API change bonding: Prevent IPv6 link local address on enslaved devices IB/mlx5: Add flow steering support net/mlx5_core: Export flow steering API net/mlx5_core: Make ipv4/ipv6 location more clear net/mlx5_core: Enable flow steering support for the IB driver net/mlx5_core: Initialize namespaces only when supported by device net/mlx5_core: Set priority attributes net/mlx5_core: Connect flow tables net/mlx5_core: Introduce modify flow table command net/mlx5_core: Managing root flow table ...
Unified · Split
| @@ -19,6 +19,25 @@ Description: · 18 unmodified lines | ||
| 19 | 19 | Set to 0 to pad all frames. Set greater than tx_max to |
| 20 | 20 | disable all padding. |
| 21 | 21 | |
| 22 | +What: /sys/class/net/<iface>/cdc_ncm/ndp_to_end | |
| 23 | +Date: Dec 2015 | |
| 24 | +KernelVersion: 4.5 | |
| 25 | +Contact: Bjørn Mork <bjorn@mork.no> | |
| 26 | +Description: | |
| 27 | + Boolean attribute showing the status of the "NDP to | |
| 28 | + end" quirk. Defaults to 'N', except for devices | |
| 29 | + already known to need it enabled. | |
| 30 | + | |
| 31 | + The "NDP to end" quirk makes the driver place the NDP | |
| 32 | + (the packet index table) after the payload. The NCM | |
| 33 | + specification does not mandate this, but some devices | |
| 34 | + are known to be more restrictive. Write 'Y' to this | |
| 35 | + attribute for temporary testing of a suspect device | |
| 36 | + failing to work with the default driver settings. | |
| 37 | + | |
| 38 | + A device entry should be added to the driver if this | |
| 39 | + quirk is found to be required. | |
| 40 | + | |
| 22 | 41 | What: /sys/class/net/<iface>/cdc_ncm/rx_max |
| 23 | 42 | Date: May 2014 |
| 24 | 43 | KernelVersion: 3.16 |
| @@ -8,7 +8,7 @@ Description: · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | What: /sys/class/net/<mesh_iface>/mesh/<vlan_subdir>/ap_isolation |
| 10 | 10 | Date: May 2011 |
| 11 | −Contact: Antonio Quartulli <antonio@meshcoding.com> | |
| 11 | +Contact: Antonio Quartulli <a@unstable.cc> | |
| 12 | 12 | Description: |
| 13 | 13 | Indicates whether the data traffic going from a |
| 14 | 14 | wireless client to another wireless client will be |
| @@ -70,7 +70,7 @@ Description: · 55 unmodified lines | ||
| 70 | 70 | |
| 71 | 71 | What: /sys/class/net/<mesh_iface>/mesh/isolation_mark |
| 72 | 72 | Date: Nov 2013 |
| 73 | −Contact: Antonio Quartulli <antonio@meshcoding.com> | |
| 73 | +Contact: Antonio Quartulli <a@unstable.cc> | |
| 74 | 74 | Description: |
| 75 | 75 | Defines the isolation mark (and its bitmask) which |
| 76 | 76 | is used to classify clients as "isolated" by the |
| @@ -0,0 +1,23 @@ | ||
| 1 | +What: /sys/class/net/<iface>/qmi/raw_ip | |
| 2 | +Date: Dec 2015 | |
| 3 | +KernelVersion: 4.4 | |
| 4 | +Contact: Bjørn Mork <bjorn@mork.no> | |
| 5 | +Description: | |
| 6 | + Boolean. Default: 'N' | |
| 7 | + | |
| 8 | + Set this to 'Y' to change the network device link | |
| 9 | + framing from '802.3' to 'raw-ip'. | |
| 10 | + | |
| 11 | + The netdev will change to reflect the link framing | |
| 12 | + mode. The netdev is an ordinary ethernet device in | |
| 13 | + '802.3' mode, and the driver expects to exchange | |
| 14 | + frames with an ethernet header over the USB link. The | |
| 15 | + netdev is a headerless p-t-p device in 'raw-ip' mode, | |
| 16 | + and the driver expects to echange IPv4 or IPv6 packets | |
| 17 | + without any L2 header over the USB link. | |
| 18 | + | |
| 19 | + Userspace is in full control of firmware configuration | |
| 20 | + through the delegation of the QMI protocol. Userspace | |
| 21 | + is responsible for coordination of driver and firmware | |
| 22 | + link framing mode, changing this setting to 'Y' if the | |
| 23 | + firmware is configured for 'raw-ip' mode. | |
| @@ -31,6 +31,8 @@ A switch child node has the following optional property: · 30 unmodified lines | ||
| 31 | 31 | switch. Must be set if the switch can not detect |
| 32 | 32 | the presence and/or size of a connected EEPROM, |
| 33 | 33 | otherwise optional. |
| 34 | +- reset-gpios : phandle and specifier to a gpio line connected to | |
| 35 | + reset pin of the switch chip. | |
| 34 | 36 | |
| 35 | 37 | A switch may have multiple "port" children nodes |
| 36 | 38 | |
| @@ -114,6 +116,7 @@ Example: · 77 unmodified lines | ||
| 114 | 116 | #size-cells = <0>; |
| 115 | 117 | reg = <17 1>; /* MDIO address 17, switch 1 in tree */ |
| 116 | 118 | mii-bus = <&mii_bus1>; |
| 119 | + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; | |
| 117 | 120 | |
| 118 | 121 | switch1port0: port@0 { |
| 119 | 122 | reg = <0>; |
| @@ -1,7 +1,12 @@ | ||
| 1 | 1 | Hisilicon MDIO bus controller |
| 2 | 2 | |
| 3 | 3 | Properties: |
| 4 | −- compatible: "hisilicon,mdio","hisilicon,hns-mdio". | |
| 4 | +- compatible: can be one of: | |
| 5 | + "hisilicon,hns-mdio" | |
| 6 | + "hisilicon,mdio" | |
| 7 | + "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs, | |
| 8 | + while "hisilicon,mdio" is optional for backwards compatibility only on | |
| 9 | + hip04 Soc. | |
| 5 | 10 | - reg: The base address of the MDIO bus controller register bank. |
| 6 | 11 | - #address-cells: Must be <1>. |
| 7 | 12 | - #size-cells: Must be <0>. MDIO addresses have no size component. |
| @@ -0,0 +1,18 @@ | ||
| 1 | +* ADF7242 IEEE 802.15.4 * | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | + - compatible: should be "adi,adf7242" | |
| 5 | + - spi-max-frequency: maximal bus speed (12.5 MHz) | |
| 6 | + - reg: the chipselect index | |
| 7 | + - interrupts: the interrupt generated by the device via pin IRQ1. | |
| 8 | + IRQ_TYPE_LEVEL_HIGH (4) or IRQ_TYPE_EDGE_FALLING (1) | |
| 9 | + | |
| 10 | +Example: | |
| 11 | + | |
| 12 | + adf7242@0 { | |
| 13 | + compatible = "adi,adf7242"; | |
| 14 | + spi-max-frequency = <10000000>; | |
| 15 | + reg = <0>; | |
| 16 | + interrupts = <98 IRQ_TYPE_LEVEL_HIGH>; | |
| 17 | + interrupt-parent = <&gpio3>; | |
| 18 | + }; | |
| @@ -4,6 +4,7 @@ Required properties: · 3 unmodified lines | ||
| 4 | 4 | - compatible: Should be "cdns,[<chip>-]{macb|gem}" |
| 5 | 5 | Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP |
| 6 | 6 | available on sama5d3 SoCs. |
| 7 | + Use "cdns,np4-macb" for NP4 SoC devices. | |
| 7 | 8 | Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". |
| 8 | 9 | Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on |
| 9 | 10 | the Cadence GEM, or the generic form: "cdns,gem". |
| @@ -19,6 +20,9 @@ Required properties: · 9 unmodified lines | ||
| 19 | 20 | Optional elements: 'tx_clk' |
| 20 | 21 | - clocks: Phandles to input clocks. |
| 21 | 22 | |
| 23 | +Optional properties for PHY child node: | |
| 24 | +- reset-gpios : Should specify the gpio for phy reset | |
| 25 | + | |
| 22 | 26 | Examples: |
| 23 | 27 | |
| 24 | 28 | macb0: ethernet@fffc4000 { |
| @@ -29,4 +33,8 @@ Examples: · 4 unmodified lines | ||
| 29 | 33 | local-mac-address = [3a 0e 03 04 05 06]; |
| 30 | 34 | clock-names = "pclk", "hclk", "tx_clk"; |
| 31 | 35 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; |
| 36 | + ethernet-phy@1 { | |
| 37 | + reg = <0x1>; | |
| 38 | + reset-gpios = <&pioE 6 1>; | |
| 39 | + }; | |
| 32 | 40 | }; |
| @@ -1,8 +1,9 @@ | ||
| 1 | 1 | Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY |
| 2 | 2 | |
| 3 | −Some boards require special tuning values, particularly when it comes to | |
| 4 | −clock delays. You can specify clock delay values by adding | |
| 5 | −micrel-specific properties to an Ethernet OF device node. | |
| 3 | +Some boards require special tuning values, particularly when it comes | |
| 4 | +to clock delays. You can specify clock delay values in the PHY OF | |
| 5 | +device node. Deprecated, but still supported, these properties can | |
| 6 | +also be added to an Ethernet OF device node. | |
| 6 | 7 | |
| 7 | 8 | Note that these settings are applied after any phy-specific fixup from |
| 8 | 9 | phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), |
| @@ -57,16 +58,6 @@ KSZ9031: · 48 unmodified lines | ||
| 57 | 58 | |
| 58 | 59 | Examples: |
| 59 | 60 | |
| 60 | − /* Attach to an Ethernet device with autodetected PHY */ | |
| 61 | − &enet { | |
| 62 | − rxc-skew-ps = <3000>; | |
| 63 | − rxdv-skew-ps = <0>; | |
| 64 | − txc-skew-ps = <3000>; | |
| 65 | − txen-skew-ps = <0>; | |
| 66 | − status = "okay"; | |
| 67 | − }; | |
| 68 | − | |
| 69 | − /* Attach to an explicitly-specified PHY */ | |
| 70 | 61 | mdio { |
| 71 | 62 | phy0: ethernet-phy@0 { |
| 72 | 63 | rxc-skew-ps = <3000>; |
| @@ -0,0 +1,50 @@ | ||
| 1 | +* STMicroelectronics : NFC Transceiver ST95HF | |
| 2 | + | |
| 3 | +ST NFC Transceiver is required to attach with SPI bus. | |
| 4 | +ST95HF node should be defined in DT as SPI slave device of SPI | |
| 5 | +master with which ST95HF transceiver is physically connected. | |
| 6 | +The properties defined below are required to be the part of DT | |
| 7 | +to include ST95HF transceiver into the platform. | |
| 8 | + | |
| 9 | +Required properties: | |
| 10 | +=================== | |
| 11 | +- reg: Address of SPI slave "ST95HF transceiver" on SPI master bus. | |
| 12 | + | |
| 13 | +- compatible: should be "st,st95hf" for ST95HF NFC transceiver | |
| 14 | + | |
| 15 | +- spi-max-frequency: Max. operating SPI frequency for ST95HF | |
| 16 | + transceiver. | |
| 17 | + | |
| 18 | +- enable-gpio: GPIO line to enable ST95HF transceiver. | |
| 19 | + | |
| 20 | +- interrupt-parent : Standard way to specify the controller to which | |
| 21 | + ST95HF transceiver's interrupt is routed. | |
| 22 | + | |
| 23 | +- interrupts : Standard way to define ST95HF transceiver's out | |
| 24 | + interrupt. | |
| 25 | + | |
| 26 | +Optional property: | |
| 27 | +================= | |
| 28 | +- st95hfvin-supply : This is an optional property. It contains a | |
| 29 | + phandle to ST95HF transceiver's regulator supply node in DT. | |
| 30 | + | |
| 31 | +Example: | |
| 32 | +======= | |
| 33 | +spi@9840000 { | |
| 34 | + reg = <0x9840000 0x110>; | |
| 35 | + #address-cells = <1>; | |
| 36 | + #size-cells = <0>; | |
| 37 | + cs-gpios = <&pio0 4>; | |
| 38 | + status = "okay"; | |
| 39 | + | |
| 40 | + st95hf@0{ | |
| 41 | + reg = <0>; | |
| 42 | + compatible = "st,st95hf"; | |
| 43 | + status = "okay"; | |
| 44 | + spi-max-frequency = <1000000>; | |
| 45 | + enable-gpio = <&pio4 0>; | |
| 46 | + interrupt-parent = <&pio0>; | |
| 47 | + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; | |
| 48 | + }; | |
| 49 | + | |
| 50 | +}; | |
| @@ -5,8 +5,18 @@ interface contains. · 4 unmodified lines | ||
| 5 | 5 | |
| 6 | 6 | Required properties: |
| 7 | 7 | - compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC. |
| 8 | + "renesas,etheravb-r8a7791" if the device is a part of R8A7791 SoC. | |
| 9 | + "renesas,etheravb-r8a7792" if the device is a part of R8A7792 SoC. | |
| 10 | + "renesas,etheravb-r8a7793" if the device is a part of R8A7793 SoC. | |
| 8 | 11 | "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC. |
| 9 | 12 | "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC. |
| 13 | + "renesas,etheravb-rcar-gen2" for generic R-Car Gen 2 compatible interface. | |
| 14 | + "renesas,etheravb-rcar-gen3" for generic R-Car Gen 3 compatible interface. | |
| 15 | + | |
| 16 | + When compatible with the generic version, nodes must list the | |
| 17 | + SoC-specific version corresponding to the platform first | |
| 18 | + followed by the generic version. | |
| 19 | + | |
| 10 | 20 | - reg: offset and length of (1) the register block and (2) the stream buffer. |
| 11 | 21 | - interrupts: A list of interrupt-specifiers, one for each entry in |
| 12 | 22 | interrupt-names. |
| @@ -37,7 +47,7 @@ Optional properties: · 24 unmodified lines | ||
| 37 | 47 | Example: |
| 38 | 48 | |
| 39 | 49 | ethernet@e6800000 { |
| 40 | − compatible = "renesas,etheravb-r8a7795"; | |
| 50 | + compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3"; | |
| 41 | 51 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
| 42 | 52 | interrupt-parent = <&gic>; |
| 43 | 53 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -11,6 +11,8 @@ Required properties: · 10 unmodified lines | ||
| 11 | 11 | designware version numbers documented in stmmac.txt |
| 12 | 12 | - altr,sysmgr-syscon : Should be the phandle to the system manager node that |
| 13 | 13 | encompasses the glue register, the register offset, and the register shift. |
| 14 | + - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock | |
| 15 | + for ptp ref clk. This affects all emacs as the clock is common. | |
| 14 | 16 | |
| 15 | 17 | Optional properties: |
| 16 | 18 | altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if |
| @@ -35,18 +35,18 @@ Optional properties: · 34 unmodified lines | ||
| 35 | 35 | - reset-names: Should contain the reset signal name "stmmaceth", if a |
| 36 | 36 | reset phandle is given |
| 37 | 37 | - max-frame-size: See ethernet.txt file in the same directory |
| 38 | −- clocks: If present, the first clock should be the GMAC main clock and | |
| 39 | − the second clock should be peripheral's register interface clock. Further | |
| 40 | − clocks may be specified in derived bindings. | |
| 41 | −- clock-names: One name for each entry in the clocks property, the | |
| 42 | − first one should be "stmmaceth" and the second one should be "pclk". | |
| 43 | −- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is | |
| 44 | − available this clock is used for programming the Timestamp Addend Register. | |
| 45 | − If not passed then the system clock will be used and this is fine on some | |
| 46 | − platforms. | |
| 38 | +- clocks: If present, the first clock should be the GMAC main clock | |
| 39 | + The optional second clock should be peripheral's register interface clock. | |
| 40 | + The third optional clock should be the ptp reference clock. | |
| 41 | + Further clocks may be specified in derived bindings. | |
| 42 | +- clock-names: One name for each entry in the clocks property. | |
| 43 | + The first one should be "stmmaceth". | |
| 44 | + The optional second one should be "pclk". | |
| 45 | + The optional third one should be "clk_ptp_ref". | |
| 47 | 46 | - snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register. |
| 48 | 47 | - tx-fifo-depth: See ethernet.txt file in the same directory |
| 49 | 48 | - rx-fifo-depth: See ethernet.txt file in the same directory |
| 49 | +- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. | |
| 50 | 50 | |
| 51 | 51 | Examples: |
| 52 | 52 | |
| @@ -65,4 +65,11 @@ Examples: · 12 unmodified lines | ||
| 65 | 65 | tx-fifo-depth = <16384>; |
| 66 | 66 | clocks = <&clock>; |
| 67 | 67 | clock-names = "stmmaceth"; |
| 68 | + mdio0 { | |
| 69 | + #address-cells = <1>; | |
| 70 | + #size-cells = <0>; | |
| 71 | + compatible = "snps,dwmac-mdio"; | |
| 72 | + phy1: ethernet-phy@0 { | |
| 73 | + }; | |
| 74 | + }; | |
| 68 | 75 | }; |
| @@ -10,6 +10,7 @@ modules that can be used to test the following notifiers. · 9 unmodified lines | ||
| 10 | 10 | * PM notifier |
| 11 | 11 | * Memory hotplug notifier |
| 12 | 12 | * powerpc pSeries reconfig notifier |
| 13 | + * Netdevice notifier | |
| 13 | 14 | |
| 14 | 15 | CPU notifier error injection module |
| 15 | 16 | ----------------------------------- |
| @@ -87,6 +88,30 @@ Possible pSeries reconfig notifier events to be failed are: · 71 unmodified lines | ||
| 87 | 88 | * PSERIES_DRCONF_MEM_ADD |
| 88 | 89 | * PSERIES_DRCONF_MEM_REMOVE |
| 89 | 90 | |
| 91 | +Netdevice notifier error injection module | |
| 92 | +---------------------------------------------- | |
| 93 | +This feature is controlled through debugfs interface | |
| 94 | +/sys/kernel/debug/notifier-error-inject/netdev/actions/<notifier event>/error | |
| 95 | + | |
| 96 | +Netdevice notifier events which can be failed are: | |
| 97 | + | |
| 98 | + * NETDEV_REGISTER | |
| 99 | + * NETDEV_CHANGEMTU | |
| 100 | + * NETDEV_CHANGENAME | |
| 101 | + * NETDEV_PRE_UP | |
| 102 | + * NETDEV_PRE_TYPE_CHANGE | |
| 103 | + * NETDEV_POST_INIT | |
| 104 | + * NETDEV_PRECHANGEMTU | |
| 105 | + * NETDEV_PRECHANGEUPPER | |
| 106 | + * NETDEV_CHANGEUPPER | |
| 107 | + | |
| 108 | +Example: Inject netdevice mtu change error (-22 == -EINVAL) | |
| 109 | + | |
| 110 | + # cd /sys/kernel/debug/notifier-error-inject/netdev | |
| 111 | + # echo -22 > actions/NETDEV_CHANGEMTU/error | |
| 112 | + # ip link set eth0 mtu 1024 | |
| 113 | + RTNETLINK answers: Invalid argument | |
| 114 | + | |
| 90 | 115 | For more usage examples |
| 91 | 116 | ----------------------- |
| 92 | 117 | There are tools/testing/selftests using the notifier error injection features |
| @@ -115,14 +115,17 @@ The "bat0" interface can be used like any other regular inter- · 114 unmodified lines | ||
| 115 | 115 | face. It needs an IP address which can be either statically con- |
| 116 | 116 | figured or dynamically (by using DHCP or similar services): |
| 117 | 117 | |
| 118 | −# NodeA: ifconfig bat0 192.168.0.1 | |
| 119 | −# NodeB: ifconfig bat0 192.168.0.2 | |
| 118 | +# NodeA: ip link set up dev bat0 | |
| 119 | +# NodeA: ip addr add 192.168.0.1/24 dev bat0 | |
| 120 | + | |
| 121 | +# NodeB: ip link set up dev bat0 | |
| 122 | +# NodeB: ip addr add 192.168.0.2/24 dev bat0 | |
| 120 | 123 | # NodeB: ping 192.168.0.1 |
| 121 | 124 | |
| 122 | 125 | Note: In order to avoid problems remove all IP addresses previ- |
| 123 | 126 | ously assigned to interfaces now used by batman advanced, e.g. |
| 124 | 127 | |
| 125 | −# ifconfig eth0 0.0.0.0 | |
| 128 | +# ip addr flush dev eth0 | |
| 126 | 129 | |
| 127 | 130 | |
| 128 | 131 | LOGGING/DEBUGGING |
| @@ -335,6 +335,14 @@ tcp_keepalive_intvl - INTEGER · 334 unmodified lines | ||
| 335 | 335 | after probes started. Default value: 75sec i.e. connection |
| 336 | 336 | will be aborted after ~11 minutes of retries. |
| 337 | 337 | |
| 338 | +tcp_l3mdev_accept - BOOLEAN | |
| 339 | + Enables child sockets to inherit the L3 master device index. | |
| 340 | + Enabling this option allows a "global" listen socket to work | |
| 341 | + across L3 master domains (e.g., VRFs) with connected sockets | |
| 342 | + derived from the listen socket to be bound to the L3 domain in | |
| 343 | + which the packets originated. Only valid when the kernel was | |
| 344 | + compiled with CONFIG_NET_L3_MASTER_DEV. | |
| 345 | + | |
| 338 | 346 | tcp_low_latency - BOOLEAN |
| 339 | 347 | If set, the TCP stack makes decisions that prefer lower |
| 340 | 348 | latency as opposed to higher throughput. By default, this |
| @@ -1723,6 +1731,25 @@ addip_enable - BOOLEAN · 1382 unmodified lines | ||
| 1723 | 1731 | |
| 1724 | 1732 | Default: 0 |
| 1725 | 1733 | |
| 1734 | +pf_enable - INTEGER | |
| 1735 | + Enable or disable pf (pf is short for potentially failed) state. A value | |
| 1736 | + of pf_retrans > path_max_retrans also disables pf state. That is, one of | |
| 1737 | + both pf_enable and pf_retrans > path_max_retrans can disable pf state. | |
| 1738 | + Since pf_retrans and path_max_retrans can be changed by userspace | |
| 1739 | + application, sometimes user expects to disable pf state by the value of | |
| 1740 | + pf_retrans > path_max_retrans, but occasionally the value of pf_retrans | |
| 1741 | + or path_max_retrans is changed by the user application, this pf state is | |
| 1742 | + enabled. As such, it is necessary to add this to dynamically enable | |
| 1743 | + and disable pf state. See: | |
| 1744 | + https://datatracker.ietf.org/doc/draft-ietf-tsvwg-sctp-failover for | |
| 1745 | + details. | |
| 1746 | + | |
| 1747 | + 1: Enable pf. | |
| 1748 | + | |
| 1749 | + 0: Disable pf. | |
| 1750 | + | |
| 1751 | + Default: 1 | |
| 1752 | + | |
| 1726 | 1753 | addip_noauth_enable - BOOLEAN |
| 1727 | 1754 | Dynamic Address Reconfiguration (ADD-IP) requires the use of |
| 1728 | 1755 | authentication to protect the operations of adding or removing new |
| @@ -1799,7 +1826,9 @@ pf_retrans - INTEGER · 70 unmodified lines | ||
| 1799 | 1826 | having to reduce path_max_retrans to a very low value. See: |
| 1800 | 1827 | http://www.ietf.org/id/draft-nishida-tsvwg-sctp-failover-05.txt |
| 1801 | 1828 | for details. Note also that a value of pf_retrans > path_max_retrans |
| 1802 | − disables this feature | |
| 1829 | + disables this feature. Since both pf_retrans and path_max_retrans can | |
| 1830 | + be changed by userspace application, a variable pf_enable is used to | |
| 1831 | + disable pf state. | |
| 1803 | 1832 | |
| 1804 | 1833 | Default: 0 |
| 1805 | 1834 | |
| @@ -304,8 +304,12 @@ certain netdevs from flooding unicast traffic for which there is no FDB entry. · 303 unmodified lines | ||
| 304 | 304 | IGMP Snooping |
| 305 | 305 | ^^^^^^^^^^^^^ |
| 306 | 306 | |
| 307 | −XXX: complete this section | |
| 308 | − | |
| 307 | +In order to support IGMP snooping, the port netdevs should trap to the bridge | |
| 308 | +driver all IGMP join and leave messages. | |
| 309 | +The bridge multicast module will notify port netdevs on every multicast group | |
| 310 | +changed whether it is static configured or dynamically joined/leave. | |
| 311 | +The hardware implementation should be forwarding all registered multicast | |
| 312 | +traffic groups only to the configured ports. | |
| 309 | 313 | |
| 310 | 314 | L3 Routing Offload |
| 311 | 315 | ------------------ |
| @@ -371,6 +371,15 @@ ADDRESS SPACE LAYOUT RANDOMIZATION (ASLR) · 370 unmodified lines | ||
| 371 | 371 | M: Jiri Kosina <jikos@kernel.org> |
| 372 | 372 | S: Maintained |
| 373 | 373 | |
| 374 | +ADF7242 IEEE 802.15.4 RADIO DRIVER | |
| 375 | +M: Michael Hennerich <michael.hennerich@analog.com> | |
| 376 | +W: https://wiki.analog.com/ADF7242 | |
| 377 | +W: http://ez.analog.com/community/linux-device-drivers | |
| 378 | +L: linux-wpan@vger.kernel.org | |
| 379 | +S: Supported | |
| 380 | +F: drivers/net/ieee802154/adf7242.c | |
| 381 | +F: Documentation/devicetree/bindings/net/ieee802154/adf7242.txt | |
| 382 | + | |
| 374 | 383 | ADM1025 HARDWARE MONITOR DRIVER |
| 375 | 384 | M: Jean Delvare <jdelvare@suse.com> |
| 376 | 385 | L: lm-sensors@lm-sensors.org |
| @@ -388,7 +397,7 @@ ADM8211 WIRELESS DRIVER · 11 unmodified lines | ||
| 388 | 397 | L: linux-wireless@vger.kernel.org |
| 389 | 398 | W: http://wireless.kernel.org/ |
| 390 | 399 | S: Orphan |
| 391 | −F: drivers/net/wireless/adm8211.* | |
| 400 | +F: drivers/net/wireless/admtek/adm8211.* | |
| 392 | 401 | |
| 393 | 402 | ADP1653 FLASH CONTROLLER DRIVER |
| 394 | 403 | M: Sakari Ailus <sakari.ailus@iki.fi> |
| @@ -1992,7 +2001,7 @@ L: linux-wireless@vger.kernel.org · 1597 unmodified lines | ||
| 1992 | 2001 | W: http://www.thekelleys.org.uk/atmel |
| 1993 | 2002 | W: http://atmelwlandriver.sourceforge.net/ |
| 1994 | 2003 | S: Maintained |
| 1995 | −F: drivers/net/wireless/atmel* | |
| 2004 | +F: drivers/net/wireless/atmel/atmel* | |
| 1996 | 2005 | |
| 1997 | 2006 | ATMEL MAXTOUCH DRIVER |
| 1998 | 2007 | M: Nick Dyer <nick.dyer@itdev.co.uk> |
| @@ -2081,7 +2090,7 @@ L: linux-wireless@vger.kernel.org · 82 unmodified lines | ||
| 2081 | 2090 | L: b43-dev@lists.infradead.org |
| 2082 | 2091 | W: http://wireless.kernel.org/en/users/Drivers/b43 |
| 2083 | 2092 | S: Odd Fixes |
| 2084 | −F: drivers/net/wireless/b43/ | |
| 2093 | +F: drivers/net/wireless/broadcom/b43/ | |
| 2085 | 2094 | |
| 2086 | 2095 | B43LEGACY WIRELESS DRIVER |
| 2087 | 2096 | M: Larry Finger <Larry.Finger@lwfinger.net> |
| @@ -2089,7 +2098,7 @@ L: linux-wireless@vger.kernel.org · 1 unmodified line | ||
| 2089 | 2098 | L: b43-dev@lists.infradead.org |
| 2090 | 2099 | W: http://wireless.kernel.org/en/users/Drivers/b43 |
| 2091 | 2100 | S: Maintained |
| 2092 | −F: drivers/net/wireless/b43legacy/ | |
| 2101 | +F: drivers/net/wireless/broadcom/b43legacy/ | |
| 2093 | 2102 | |
| 2094 | 2103 | BACKLIGHT CLASS/SUBSYSTEM |
| 2095 | 2104 | M: Jingoo Han <jingoohan1@gmail.com> |
| @@ -2101,7 +2110,7 @@ F: include/linux/backlight.h · 5 unmodified lines | ||
| 2101 | 2110 | BATMAN ADVANCED |
| 2102 | 2111 | M: Marek Lindner <mareklindner@neomailbox.ch> |
| 2103 | 2112 | M: Simon Wunderlich <sw@simonwunderlich.de> |
| 2104 | −M: Antonio Quartulli <antonio@meshcoding.com> | |
| 2113 | +M: Antonio Quartulli <a@unstable.cc> | |
| 2105 | 2114 | L: b.a.t.m.a.n@lists.open-mesh.org |
| 2106 | 2115 | W: http://www.open-mesh.org/ |
| 2107 | 2116 | S: Maintained |
| @@ -2391,7 +2400,7 @@ M: Hante Meuleman <meuleman@broadcom.com> · 283 unmodified lines | ||
| 2391 | 2400 | L: linux-wireless@vger.kernel.org |
| 2392 | 2401 | L: brcm80211-dev-list@broadcom.com |
| 2393 | 2402 | S: Supported |
| 2394 | −F: drivers/net/wireless/brcm80211/ | |
| 2403 | +F: drivers/net/wireless/broadcom/brcm80211/ | |
| 2395 | 2404 | |
| 2396 | 2405 | BROADCOM BNX2FC 10 GIGABIT FCOE DRIVER |
| 2397 | 2406 | M: QLogic-Storage-Upstream@qlogic.com |
| @@ -3113,7 +3122,7 @@ F: sound/pci/cs5535audio/ · 715 unmodified lines | ||
| 3113 | 3122 | CW1200 WLAN driver |
| 3114 | 3123 | M: Solomon Peachy <pizza@shaftnet.org> |
| 3115 | 3124 | S: Maintained |
| 3116 | −F: drivers/net/wireless/cw1200/ | |
| 3125 | +F: drivers/net/wireless/st/cw1200/ | |
| 3117 | 3126 | |
| 3118 | 3127 | CX18 VIDEO4LINUX DRIVER |
| 3119 | 3128 | M: Andy Walls <awalls@md.metrocast.net> |
| @@ -5035,7 +5044,7 @@ L: hostap@shmoo.com (subscribers-only) · 1915 unmodified lines | ||
| 5035 | 5044 | L: linux-wireless@vger.kernel.org |
| 5036 | 5045 | W: http://hostap.epitest.fi/ |
| 5037 | 5046 | S: Maintained |
| 5038 | −F: drivers/net/wireless/hostap/ | |
| 5047 | +F: drivers/net/wireless/intersil/hostap/ | |
| 5039 | 5048 | |
| 5040 | 5049 | HP COMPAQ TC1100 TABLET WMI EXTRAS DRIVER |
| 5041 | 5050 | L: platform-driver-x86@vger.kernel.org |
| @@ -5273,6 +5282,13 @@ L: netdev@vger.kernel.org · 231 unmodified lines | ||
| 5273 | 5282 | S: Supported |
| 5274 | 5283 | F: drivers/net/ethernet/ibm/ibmveth.* |
| 5275 | 5284 | |
| 5285 | +IBM Power SRIOV Virtual NIC Device Driver | |
| 5286 | +M: Thomas Falcon <tlfalcon@linux.vnet.ibm.com> | |
| 5287 | +M: John Allen <jallen@linux.vnet.ibm.com> | |
| 5288 | +L: netdev@vger.kernel.org | |
| 5289 | +S: Supported | |
| 5290 | +F: drivers/net/ethernet/ibm/ibmvnic.* | |
| 5291 | + | |
| 5276 | 5292 | IBM Power Virtual SCSI Device Drivers |
| 5277 | 5293 | M: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> |
| 5278 | 5294 | L: linux-scsi@vger.kernel.org |
| @@ -5603,7 +5619,7 @@ L: linux-wireless@vger.kernel.org · 324 unmodified lines | ||
| 5603 | 5619 | S: Maintained |
| 5604 | 5620 | F: Documentation/networking/README.ipw2100 |
| 5605 | 5621 | F: Documentation/networking/README.ipw2200 |
| 5606 | −F: drivers/net/wireless/ipw2x00/ | |
| 5622 | +F: drivers/net/wireless/intel/ipw2x00/ | |
| 5607 | 5623 | |
| 5608 | 5624 | INTEL(R) TRACE HUB |
| 5609 | 5625 | M: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| @@ -5635,7 +5651,7 @@ INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy) · 25 unmodified lines | ||
| 5635 | 5651 | M: Stanislaw Gruszka <sgruszka@redhat.com> |
| 5636 | 5652 | L: linux-wireless@vger.kernel.org |
| 5637 | 5653 | S: Supported |
| 5638 | −F: drivers/net/wireless/iwlegacy/ | |
| 5654 | +F: drivers/net/wireless/intel/iwlegacy/ | |
| 5639 | 5655 | |
| 5640 | 5656 | INTEL WIRELESS WIFI LINK (iwlwifi) |
| 5641 | 5657 | M: Johannes Berg <johannes.berg@intel.com> |
| @@ -5645,7 +5661,7 @@ L: linux-wireless@vger.kernel.org · 3 unmodified lines | ||
| 5645 | 5661 | W: http://intellinuxwireless.org |
| 5646 | 5662 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi.git |
| 5647 | 5663 | S: Supported |
| 5648 | −F: drivers/net/wireless/iwlwifi/ | |
| 5664 | +F: drivers/net/wireless/intel/iwlwifi/ | |
| 5649 | 5665 | |
| 5650 | 5666 | INTEL MANAGEMENT ENGINE (mei) |
| 5651 | 5667 | M: Tomas Winkler <tomas.winkler@intel.com> |
| @@ -6697,7 +6713,7 @@ F: drivers/net/ethernet/marvell/sk* · 1045 unmodified lines | ||
| 6697 | 6713 | MARVELL LIBERTAS WIRELESS DRIVER |
| 6698 | 6714 | L: libertas-dev@lists.infradead.org |
| 6699 | 6715 | S: Orphan |
| 6700 | −F: drivers/net/wireless/libertas/ | |
| 6716 | +F: drivers/net/wireless/marvell/libertas/ | |
| 6701 | 6717 | |
| 6702 | 6718 | MARVELL MV643XX ETHERNET DRIVER |
| 6703 | 6719 | M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
| @@ -6717,13 +6733,13 @@ M: Amitkumar Karwar <akarwar@marvell.com> · 13 unmodified lines | ||
| 6717 | 6733 | M: Nishant Sarmukadam <nishants@marvell.com> |
| 6718 | 6734 | L: linux-wireless@vger.kernel.org |
| 6719 | 6735 | S: Maintained |
| 6720 | −F: drivers/net/wireless/mwifiex/ | |
| 6736 | +F: drivers/net/wireless/marvell/mwifiex/ | |
| 6721 | 6737 | |
| 6722 | 6738 | MARVELL MWL8K WIRELESS DRIVER |
| 6723 | 6739 | M: Lennert Buytenhek <buytenh@wantstofly.org> |
| 6724 | 6740 | L: linux-wireless@vger.kernel.org |
| 6725 | 6741 | S: Odd Fixes |
| 6726 | −F: drivers/net/wireless/mwl8k.c | |
| 6742 | +F: drivers/net/wireless/marvell/mwl8k.c | |
| 6727 | 6743 | |
| 6728 | 6744 | MARVELL SOC MMC/SD/SDIO CONTROLLER DRIVER |
| 6729 | 6745 | M: Nicolas Pitre <nico@fluxnic.net> |
| @@ -7359,6 +7375,13 @@ F: include/net/netrom.h · 629 unmodified lines | ||
| 7359 | 7375 | F: include/uapi/linux/netrom.h |
| 7360 | 7376 | F: net/netrom/ |
| 7361 | 7377 | |
| 7378 | +NETRONOME ETHERNET DRIVERS | |
| 7379 | +M: Jakub Kicinski <jakub.kicinski@netronome.com> | |
| 7380 | +M: Rolf Neugebauer <rolf.neugebauer@netronome.com> | |
| 7381 | +L: oss-drivers@netronome.com | |
| 7382 | +S: Maintained | |
| 7383 | +F: drivers/net/ethernet/netronome/ | |
| 7384 | + | |
| 7362 | 7385 | NETWORK BLOCK DEVICE (NBD) |
| 7363 | 7386 | M: Markus Pargmann <mpa@pengutronix.de> |
| 7364 | 7387 | S: Maintained |
| @@ -7490,7 +7513,12 @@ F: net/nfc/ · 125 unmodified lines | ||
| 7490 | 7513 | F: include/net/nfc/ |
| 7491 | 7514 | F: include/uapi/linux/nfc.h |
| 7492 | 7515 | F: drivers/nfc/ |
| 7516 | +F: include/linux/platform_data/microread.h | |
| 7517 | +F: include/linux/platform_data/nfcmrvl.h | |
| 7518 | +F: include/linux/platform_data/nxp-nci.h | |
| 7493 | 7519 | F: include/linux/platform_data/pn544.h |
| 7520 | +F: include/linux/platform_data/st21nfca.h | |
| 7521 | +F: include/linux/platform_data/st-nci.h | |
| 7494 | 7522 | F: Documentation/devicetree/bindings/net/nfc/ |
| 7495 | 7523 | |
| 7496 | 7524 | NFS, SUNRPC, AND LOCKD CLIENTS |
| @@ -7940,7 +7968,7 @@ L: linux-wireless@vger.kernel.org · 443 unmodified lines | ||
| 7940 | 7968 | W: http://wireless.kernel.org/en/users/Drivers/orinoco |
| 7941 | 7969 | W: http://www.nongnu.org/orinoco/ |
| 7942 | 7970 | S: Orphan |
| 7943 | −F: drivers/net/wireless/orinoco/ | |
| 7971 | +F: drivers/net/wireless/intersil/orinoco/ | |
| 7944 | 7972 | |
| 7945 | 7973 | OSD LIBRARY and FILESYSTEM |
| 7946 | 7974 | M: Boaz Harrosh <ooo@electrozaur.com> |
| @@ -7966,7 +7994,7 @@ M: Christian Lamparter <chunkeey@googlemail.com> · 19 unmodified lines | ||
| 7966 | 7994 | L: linux-wireless@vger.kernel.org |
| 7967 | 7995 | W: http://wireless.kernel.org/en/users/Drivers/p54 |
| 7968 | 7996 | S: Maintained |
| 7969 | −F: drivers/net/wireless/p54/ | |
| 7997 | +F: drivers/net/wireless/intersil/p54/ | |
| 7970 | 7998 | |
| 7971 | 7999 | PA SEMI ETHERNET DRIVER |
| 7972 | 8000 | M: Olof Johansson <olof@lixom.net> |
| @@ -8517,7 +8545,7 @@ M: "Luis R. Rodriguez" <mcgrof@gmail.com> · 544 unmodified lines | ||
| 8517 | 8545 | L: linux-wireless@vger.kernel.org |
| 8518 | 8546 | W: http://wireless.kernel.org/en/users/Drivers/p54 |
| 8519 | 8547 | S: Obsolete |
| 8520 | −F: drivers/net/wireless/prism54/ | |
| 8548 | +F: drivers/net/wireless/intersil/prism54/ | |
| 8521 | 8549 | |
| 8522 | 8550 | PS3 NETWORK SUPPORT |
| 8523 | 8551 | M: Geoff Levand <geoff@infradead.org> |
| @@ -8821,7 +8849,7 @@ M: Stanislaw Gruszka <sgruszka@redhat.com> · 297 unmodified lines | ||
| 8821 | 8849 | M: Helmut Schaa <helmut.schaa@googlemail.com> |
| 8822 | 8850 | L: linux-wireless@vger.kernel.org |
| 8823 | 8851 | S: Maintained |
| 8824 | −F: drivers/net/wireless/rt2x00/ | |
| 8852 | +F: drivers/net/wireless/ralink/rt2x00/ | |
| 8825 | 8853 | |
| 8826 | 8854 | RAMDISK RAM BLOCK DEVICE DRIVER |
| 8827 | 8855 | M: Jens Axboe <axboe@kernel.dk> |
| @@ -9062,7 +9090,7 @@ L: linux-wireless@vger.kernel.org · 234 unmodified lines | ||
| 9062 | 9090 | W: http://wireless.kernel.org/ |
| 9063 | 9091 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git |
| 9064 | 9092 | S: Orphan |
| 9065 | −F: drivers/net/wireless/rtl818x/rtl8180/ | |
| 9093 | +F: drivers/net/wireless/realtek/rtl818x/rtl8180/ | |
| 9066 | 9094 | |
| 9067 | 9095 | RTL8187 WIRELESS DRIVER |
| 9068 | 9096 | M: Herton Ronaldo Krzesinski <herton@canonical.com> |
| @@ -9072,7 +9100,7 @@ L: linux-wireless@vger.kernel.org · 3 unmodified lines | ||
| 9072 | 9100 | W: http://wireless.kernel.org/ |
| 9073 | 9101 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git |
| 9074 | 9102 | S: Maintained |
| 9075 | −F: drivers/net/wireless/rtl818x/rtl8187/ | |
| 9103 | +F: drivers/net/wireless/realtek/rtl818x/rtl8187/ | |
| 9076 | 9104 | |
| 9077 | 9105 | RTL8192CE WIRELESS DRIVER |
| 9078 | 9106 | M: Larry Finger <Larry.Finger@lwfinger.net> |
| @@ -9081,8 +9109,8 @@ L: linux-wireless@vger.kernel.org · 2 unmodified lines | ||
| 9081 | 9109 | W: http://wireless.kernel.org/ |
| 9082 | 9110 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git |
| 9083 | 9111 | S: Maintained |
| 9084 | −F: drivers/net/wireless/rtlwifi/ | |
| 9085 | −F: drivers/net/wireless/rtlwifi/rtl8192ce/ | |
| 9112 | +F: drivers/net/wireless/realtek/rtlwifi/ | |
| 9113 | +F: drivers/net/wireless/realtek/rtlwifi/rtl8192ce/ | |
| 9086 | 9114 | |
| 9087 | 9115 | RTL8XXXU WIRELESS DRIVER (rtl8xxxu) |
| 9088 | 9116 | M: Jes Sorensen <Jes.Sorensen@redhat.com> |
| @@ -9126,7 +9154,7 @@ F: drivers/s390/block/dasd* · 37 unmodified lines | ||
| 9126 | 9154 | F: block/partitions/ibm.c |
| 9127 | 9155 | |
| 9128 | 9156 | S390 NETWORK DRIVERS |
| 9129 | −M: Ursula Braun <ursula.braun@de.ibm.com> | |
| 9157 | +M: Ursula Braun <ubraun@linux.vnet.ibm.com> | |
| 9130 | 9158 | L: linux-s390@vger.kernel.org |
| 9131 | 9159 | W: http://www.ibm.com/developerworks/linux/linux390/ |
| 9132 | 9160 | S: Supported |
| @@ -9156,7 +9184,7 @@ S: Supported · 23 unmodified lines | ||
| 9156 | 9184 | F: drivers/s390/scsi/zfcp_* |
| 9157 | 9185 | |
| 9158 | 9186 | S390 IUCV NETWORK LAYER |
| 9159 | −M: Ursula Braun <ursula.braun@de.ibm.com> | |
| 9187 | +M: Ursula Braun <ubraun@linux.vnet.ibm.com> | |
| 9160 | 9188 | L: linux-s390@vger.kernel.org |
| 9161 | 9189 | W: http://www.ibm.com/developerworks/linux/linux390/ |
| 9162 | 9190 | S: Supported |
| @@ -11185,6 +11213,13 @@ L: linux-usb@vger.kernel.org · 2022 unmodified lines | ||
| 11185 | 11213 | S: Supported |
| 11186 | 11214 | F: drivers/usb/class/usblp.c |
| 11187 | 11215 | |
| 11216 | +USB QMI WWAN NETWORK DRIVER | |
| 11217 | +M: Bjørn Mork <bjorn@mork.no> | |
| 11218 | +L: netdev@vger.kernel.org | |
| 11219 | +S: Maintained | |
| 11220 | +F: Documentation/ABI/testing/sysfs-class-net-qmi | |
| 11221 | +F: drivers/net/usb/qmi_wwan.c | |
| 11222 | + | |
| 11188 | 11223 | USB RTL8150 DRIVER |
| 11189 | 11224 | M: Petko Manolov <petkan@nucleusys.com> |
| 11190 | 11225 | L: linux-usb@vger.kernel.org |
| @@ -11281,7 +11316,7 @@ USB ZD1201 DRIVER · 90 unmodified lines | ||
| 11281 | 11316 | L: linux-wireless@vger.kernel.org |
| 11282 | 11317 | W: http://linux-lc100020.sourceforge.net |
| 11283 | 11318 | S: Orphan |
| 11284 | −F: drivers/net/wireless/zd1201.* | |
| 11319 | +F: drivers/net/wireless/zydas/zd1201.* | |
| 11285 | 11320 | |
| 11286 | 11321 | USB ZR364XX DRIVER |
| 11287 | 11322 | M: Antoine Jacquet <royale@zerezo.com> |
| @@ -11912,7 +11947,7 @@ W: http://zd1211.ath.cx/wiki/DriverRewrite · 624 unmodified lines | ||
| 11912 | 11947 | L: linux-wireless@vger.kernel.org |
| 11913 | 11948 | L: zd1211-devs@lists.sourceforge.net (subscribers-only) |
| 11914 | 11949 | S: Maintained |
| 11915 | −F: drivers/net/wireless/zd1211rw/ | |
| 11950 | +F: drivers/net/wireless/zydas/zd1211rw/ | |
| 11916 | 11951 | |
| 11917 | 11952 | ZPOOL COMPRESSED PAGE STORAGE API |
| 11918 | 11953 | M: Dan Streetman <ddstreet@ieee.org> |
| @@ -92,4 +92,7 @@ · 91 unmodified lines | ||
| 92 | 92 | #define SO_ATTACH_BPF 50 |
| 93 | 93 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 94 | 94 | |
| 95 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 96 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 97 | + | |
| 95 | 98 | #endif /* _UAPI_ASM_SOCKET_H */ |
| @@ -152,8 +152,6 @@ static void build_prologue(struct jit_ctx *ctx) · 151 unmodified lines | ||
| 152 | 152 | const u8 r8 = bpf2a64[BPF_REG_8]; |
| 153 | 153 | const u8 r9 = bpf2a64[BPF_REG_9]; |
| 154 | 154 | const u8 fp = bpf2a64[BPF_REG_FP]; |
| 155 | − const u8 ra = bpf2a64[BPF_REG_A]; | |
| 156 | − const u8 rx = bpf2a64[BPF_REG_X]; | |
| 157 | 155 | const u8 tmp1 = bpf2a64[TMP_REG_1]; |
| 158 | 156 | const u8 tmp2 = bpf2a64[TMP_REG_2]; |
| 159 | 157 | |
| @@ -200,10 +198,6 @@ static void build_prologue(struct jit_ctx *ctx) · 40 unmodified lines | ||
| 200 | 198 | |
| 201 | 199 | /* Set up function call stack */ |
| 202 | 200 | emit(A64_SUB_I(1, A64_SP, A64_SP, STACK_SIZE), ctx); |
| 203 | − | |
| 204 | − /* Clear registers A and X */ | |
| 205 | − emit_a64_mov_i64(ra, 0, ctx); | |
| 206 | − emit_a64_mov_i64(rx, 0, ctx); | |
| 207 | 201 | } |
| 208 | 202 | |
| 209 | 203 | static void build_epilogue(struct jit_ctx *ctx) |
| @@ -85,4 +85,7 @@ · 84 unmodified lines | ||
| 85 | 85 | #define SO_ATTACH_BPF 50 |
| 86 | 86 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 87 | 87 | |
| 88 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 89 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 90 | + | |
| 88 | 91 | #endif /* _UAPI__ASM_AVR32_SOCKET_H */ |
| @@ -85,5 +85,8 @@ · 84 unmodified lines | ||
| 85 | 85 | #define SO_ATTACH_BPF 50 |
| 86 | 86 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 87 | 87 | |
| 88 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 89 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 90 | + | |
| 88 | 91 | #endif /* _ASM_SOCKET_H */ |
| 89 | 92 | |
| @@ -94,4 +94,7 @@ · 93 unmodified lines | ||
| 94 | 94 | #define SO_ATTACH_BPF 50 |
| 95 | 95 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 96 | 96 | |
| 97 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 98 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 99 | + | |
| 97 | 100 | #endif /* _ASM_IA64_SOCKET_H */ |
| @@ -85,4 +85,7 @@ · 84 unmodified lines | ||
| 85 | 85 | #define SO_ATTACH_BPF 50 |
| 86 | 86 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 87 | 87 | |
| 88 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 89 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 90 | + | |
| 88 | 91 | #endif /* _ASM_M32R_SOCKET_H */ |
| @@ -101,50 +101,13 @@ static void bcm47xx_machine_halt(void) · 100 unmodified lines | ||
| 101 | 101 | } |
| 102 | 102 | |
| 103 | 103 | #ifdef CONFIG_BCM47XX_SSB |
| 104 | −static int bcm47xx_get_invariants(struct ssb_bus *bus, | |
| 105 | − struct ssb_init_invariants *iv) | |
| 106 | −{ | |
| 107 | − char buf[20]; | |
| 108 | − int len, err; | |
| 109 | − | |
| 110 | − /* Fill boardinfo structure */ | |
| 111 | − memset(&iv->boardinfo, 0 , sizeof(struct ssb_boardinfo)); | |
| 112 | − | |
| 113 | − len = bcm47xx_nvram_getenv("boardvendor", buf, sizeof(buf)); | |
| 114 | − if (len > 0) { | |
| 115 | − err = kstrtou16(strim(buf), 0, &iv->boardinfo.vendor); | |
| 116 | − if (err) | |
| 117 | − pr_warn("Couldn't parse nvram board vendor entry with value \"%s\"\n", | |
| 118 | − buf); | |
| 119 | − } | |
| 120 | − if (!iv->boardinfo.vendor) | |
| 121 | − iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM; | |
| 122 | − | |
| 123 | − len = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf)); | |
| 124 | − if (len > 0) { | |
| 125 | − err = kstrtou16(strim(buf), 0, &iv->boardinfo.type); | |
| 126 | − if (err) | |
| 127 | − pr_warn("Couldn't parse nvram board type entry with value \"%s\"\n", | |
| 128 | − buf); | |
| 129 | − } | |
| 130 | − | |
| 131 | − memset(&iv->sprom, 0, sizeof(struct ssb_sprom)); | |
| 132 | − bcm47xx_fill_sprom(&iv->sprom, NULL, false); | |
| 133 | − | |
| 134 | − if (bcm47xx_nvram_getenv("cardbus", buf, sizeof(buf)) >= 0) | |
| 135 | − iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10); | |
| 136 | − | |
| 137 | − return 0; | |
| 138 | −} | |
| 139 | − | |
| 140 | 104 | static void __init bcm47xx_register_ssb(void) |
| 141 | 105 | { |
| 142 | 106 | int err; |
| 143 | 107 | char buf[100]; |
| 144 | 108 | struct ssb_mipscore *mcore; |
| 145 | 109 | |
| 146 | − err = ssb_bus_ssbbus_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE, | |
| 147 | − bcm47xx_get_invariants); | |
| 110 | + err = ssb_bus_host_soc_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE); | |
| 148 | 111 | if (err) |
| 149 | 112 | panic("Failed to initialize SSB bus (err %d)", err); |
| 150 | 113 | |
| @@ -103,4 +103,7 @@ · 102 unmodified lines | ||
| 103 | 103 | #define SO_ATTACH_BPF 50 |
| 104 | 104 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 105 | 105 | |
| 106 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 107 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 108 | + | |
| 106 | 109 | #endif /* _UAPI_ASM_SOCKET_H */ |
| @@ -85,4 +85,7 @@ · 84 unmodified lines | ||
| 85 | 85 | #define SO_ATTACH_BPF 50 |
| 86 | 86 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 87 | 87 | |
| 88 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 89 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 90 | + | |
| 88 | 91 | #endif /* _ASM_SOCKET_H */ |
| @@ -84,4 +84,7 @@ · 83 unmodified lines | ||
| 84 | 84 | #define SO_ATTACH_BPF 0x402B |
| 85 | 85 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 86 | 86 | |
| 87 | +#define SO_ATTACH_REUSEPORT_CBPF 0x402C | |
| 88 | +#define SO_ATTACH_REUSEPORT_EBPF 0x402D | |
| 89 | + | |
| 87 | 90 | #endif /* _UAPI_ASM_SOCKET_H */ |
| @@ -258,11 +258,16 @@ · 257 unmodified lines | ||
| 258 | 258 | #define H_DEL_CONN 0x288 |
| 259 | 259 | #define H_JOIN 0x298 |
| 260 | 260 | #define H_VASI_STATE 0x2A4 |
| 261 | +#define H_VIOCTL 0x2A8 | |
| 261 | 262 | #define H_ENABLE_CRQ 0x2B0 |
| 262 | 263 | #define H_GET_EM_PARMS 0x2B8 |
| 263 | 264 | #define H_SET_MPP 0x2D0 |
| 264 | 265 | #define H_GET_MPP 0x2D4 |
| 266 | +#define H_REG_SUB_CRQ 0x2DC | |
| 265 | 267 | #define H_HOME_NODE_ASSOCIATIVITY 0x2EC |
| 268 | +#define H_FREE_SUB_CRQ 0x2E0 | |
| 269 | +#define H_SEND_SUB_CRQ 0x2E4 | |
| 270 | +#define H_SEND_SUB_CRQ_INDIRECT 0x2E8 | |
| 266 | 271 | #define H_BEST_ENERGY 0x2F4 |
| 267 | 272 | #define H_XIRR_X 0x2FC |
| 268 | 273 | #define H_RANDOM 0x300 |
| @@ -271,6 +276,21 @@ · 2 unmodified lines | ||
| 271 | 276 | #define H_SET_MODE 0x31C |
| 272 | 277 | #define MAX_HCALL_OPCODE H_SET_MODE |
| 273 | 278 | |
| 279 | +/* H_VIOCTL functions */ | |
| 280 | +#define H_GET_VIOA_DUMP_SIZE 0x01 | |
| 281 | +#define H_GET_VIOA_DUMP 0x02 | |
| 282 | +#define H_GET_ILLAN_NUM_VLAN_IDS 0x03 | |
| 283 | +#define H_GET_ILLAN_VLAN_ID_LIST 0x04 | |
| 284 | +#define H_GET_ILLAN_SWITCH_ID 0x05 | |
| 285 | +#define H_DISABLE_MIGRATION 0x06 | |
| 286 | +#define H_ENABLE_MIGRATION 0x07 | |
| 287 | +#define H_GET_PARTNER_INFO 0x08 | |
| 288 | +#define H_GET_PARTNER_WWPN_LIST 0x09 | |
| 289 | +#define H_DISABLE_ALL_VIO_INTS 0x0A | |
| 290 | +#define H_DISABLE_VIO_INTERRUPT 0x0B | |
| 291 | +#define H_ENABLE_VIO_INTERRUPT 0x0C | |
| 292 | + | |
| 293 | + | |
| 274 | 294 | /* Platform specific hcalls, used by KVM */ |
| 275 | 295 | #define H_RTAS 0xf000 |
| 276 | 296 | |
| @@ -92,4 +92,7 @@ · 91 unmodified lines | ||
| 92 | 92 | #define SO_ATTACH_BPF 50 |
| 93 | 93 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 94 | 94 | |
| 95 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 96 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 97 | + | |
| 95 | 98 | #endif /* _ASM_POWERPC_SOCKET_H */ |
| @@ -131,23 +131,15 @@ static int ep8248e_mdio_probe(struct platform_device *ofdev) · 130 unmodified lines | ||
| 131 | 131 | if (!bus) |
| 132 | 132 | return -ENOMEM; |
| 133 | 133 | |
| 134 | − bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
| 135 | − if (bus->irq == NULL) { | |
| 136 | − ret = -ENOMEM; | |
| 137 | − goto err_free_bus; | |
| 138 | − } | |
| 139 | − | |
| 140 | 134 | bus->name = "ep8248e-mdio-bitbang"; |
| 141 | 135 | bus->parent = &ofdev->dev; |
| 142 | 136 | snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); |
| 143 | 137 | |
| 144 | 138 | ret = of_mdiobus_register(bus, ofdev->dev.of_node); |
| 145 | 139 | if (ret) |
| 146 | − goto err_free_irq; | |
| 140 | + goto err_free_bus; | |
| 147 | 141 | |
| 148 | 142 | return 0; |
| 149 | −err_free_irq: | |
| 150 | − kfree(bus->irq); | |
| 151 | 143 | err_free_bus: |
| 152 | 144 | free_mdio_bitbang(bus); |
| 153 | 145 | return ret; |
| @@ -41,7 +41,6 @@ static void __iomem *gpio_regs; · 40 unmodified lines | ||
| 41 | 41 | struct gpio_priv { |
| 42 | 42 | int mdc_pin; |
| 43 | 43 | int mdio_pin; |
| 44 | − int mdio_irqs[PHY_MAX_ADDR]; | |
| 45 | 44 | }; |
| 46 | 45 | |
| 47 | 46 | #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin) |
| @@ -245,8 +244,6 @@ static int gpio_mdio_probe(struct platform_device *ofdev) · 197 unmodified lines | ||
| 245 | 244 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop); |
| 246 | 245 | new_bus->priv = priv; |
| 247 | 246 | |
| 248 | − new_bus->irq = priv->mdio_irqs; | |
| 249 | − | |
| 250 | 247 | prop = of_get_property(np, "mdc-pin", NULL); |
| 251 | 248 | priv->mdc_pin = *prop; |
| 252 | 249 | |
| @@ -91,4 +91,7 @@ · 90 unmodified lines | ||
| 91 | 91 | #define SO_ATTACH_BPF 50 |
| 92 | 92 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 93 | 93 | |
| 94 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 95 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 96 | + | |
| 94 | 97 | #endif /* _ASM_SOCKET_H */ |
| @@ -408,7 +408,7 @@ static void emit_load_skb_data_hlen(struct bpf_jit *jit) · 407 unmodified lines | ||
| 408 | 408 | * Save registers and create stack frame if necessary. |
| 409 | 409 | * See stack frame layout desription in "bpf_jit.h"! |
| 410 | 410 | */ |
| 411 | −static void bpf_jit_prologue(struct bpf_jit *jit, bool is_classic) | |
| 411 | +static void bpf_jit_prologue(struct bpf_jit *jit) | |
| 412 | 412 | { |
| 413 | 413 | if (jit->seen & SEEN_TAIL_CALL) { |
| 414 | 414 | /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ |
| @@ -448,15 +448,6 @@ static void bpf_jit_prologue(struct bpf_jit *jit, bool is_classic) · 33 unmodified lines | ||
| 448 | 448 | /* stg %b1,ST_OFF_SKBP(%r0,%r15) */ |
| 449 | 449 | EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, |
| 450 | 450 | STK_OFF_SKBP); |
| 451 | − /* Clear A (%b0) and X (%b7) registers for converted BPF programs */ | |
| 452 | − if (is_classic) { | |
| 453 | − if (REG_SEEN(BPF_REG_A)) | |
| 454 | − /* lghi %ba,0 */ | |
| 455 | − EMIT4_IMM(0xa7090000, BPF_REG_A, 0); | |
| 456 | − if (REG_SEEN(BPF_REG_X)) | |
| 457 | − /* lghi %bx,0 */ | |
| 458 | − EMIT4_IMM(0xa7090000, BPF_REG_X, 0); | |
| 459 | − } | |
| 460 | 451 | } |
| 461 | 452 | |
| 462 | 453 | /* |
| @@ -1245,7 +1236,7 @@ static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) · 782 unmodified lines | ||
| 1245 | 1236 | jit->lit = jit->lit_start; |
| 1246 | 1237 | jit->prg = 0; |
| 1247 | 1238 | |
| 1248 | − bpf_jit_prologue(jit, bpf_prog_was_classic(fp)); | |
| 1239 | + bpf_jit_prologue(jit); | |
| 1249 | 1240 | for (i = 0; i < fp->len; i += insn_count) { |
| 1250 | 1241 | insn_count = bpf_jit_insn(jit, fp, i); |
| 1251 | 1242 | if (insn_count < 0) |
| @@ -81,6 +81,9 @@ · 80 unmodified lines | ||
| 81 | 81 | #define SO_ATTACH_BPF 0x0034 |
| 82 | 82 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 83 | 83 | |
| 84 | +#define SO_ATTACH_REUSEPORT_CBPF 0x0035 | |
| 85 | +#define SO_ATTACH_REUSEPORT_EBPF 0x0036 | |
| 86 | + | |
| 84 | 87 | /* Security levels - as per NRL IPv6 - don't actually do anything */ |
| 85 | 88 | #define SO_SECURITY_AUTHENTICATION 0x5001 |
| 86 | 89 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 0x5002 |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | #include <linux/types.h> |
| 10 | 10 | #include <linux/init.h> |
| 11 | 11 | #include <linux/export.h> |
| 12 | +#include <linux/etherdevice.h> | |
| 12 | 13 | |
| 13 | 14 | #include <asm/oplib.h> |
| 14 | 15 | #include <asm/idprom.h> |
| @@ -60,6 +61,12 @@ static void __init display_system_type(unsigned char machtype) · 45 unmodified lines | ||
| 60 | 61 | { |
| 61 | 62 | } |
| 62 | 63 | #endif |
| 64 | + | |
| 65 | +unsigned char *arch_get_platform_mac_address(void) | |
| 66 | +{ | |
| 67 | + return idprom->id_ethaddr; | |
| 68 | +} | |
| 69 | + | |
| 63 | 70 | /* Calculate the IDPROM checksum (xor of the data bytes). */ |
| 64 | 71 | static unsigned char __init calc_idprom_cksum(struct idprom *idprom) |
| 65 | 72 | { |
| @@ -193,7 +193,7 @@ struct jit_context { · 192 unmodified lines | ||
| 193 | 193 | 32 /* space for rbx, r13, r14, r15 */ + \ |
| 194 | 194 | 8 /* space for skb_copy_bits() buffer */) |
| 195 | 195 | |
| 196 | −#define PROLOGUE_SIZE 51 | |
| 196 | +#define PROLOGUE_SIZE 48 | |
| 197 | 197 | |
| 198 | 198 | /* emit x64 prologue code for BPF program and check it's size. |
| 199 | 199 | * bpf_tail_call helper will skip it while jumping into another program |
| @@ -229,11 +229,15 @@ static void emit_prologue(u8 **pprog) · 29 unmodified lines | ||
| 229 | 229 | /* mov qword ptr [rbp-X],r15 */ |
| 230 | 230 | EMIT3_off32(0x4C, 0x89, 0xBD, -STACKSIZE + 24); |
| 231 | 231 | |
| 232 | − /* clear A and X registers */ | |
| 233 | − EMIT2(0x31, 0xc0); /* xor eax, eax */ | |
| 234 | − EMIT3(0x4D, 0x31, 0xED); /* xor r13, r13 */ | |
| 232 | + /* Clear the tail call counter (tail_call_cnt): for eBPF tail calls | |
| 233 | + * we need to reset the counter to 0. It's done in two instructions, | |
| 234 | + * resetting rax register to 0 (xor on eax gets 0 extended), and | |
| 235 | + * moving it to the counter location. | |
| 236 | + */ | |
| 235 | 237 | |
| 236 | − /* clear tail_cnt: mov qword ptr [rbp-X], rax */ | |
| 238 | + /* xor eax, eax */ | |
| 239 | + EMIT2(0x31, 0xc0); | |
| 240 | + /* mov qword ptr [rbp-X], rax */ | |
| 237 | 241 | EMIT3_off32(0x48, 0x89, 0x85, -STACKSIZE + 32); |
| 238 | 242 | |
| 239 | 243 | BUILD_BUG_ON(cnt != PROLOGUE_SIZE); |
| @@ -455,6 +459,18 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, · 215 unmodified lines | ||
| 455 | 459 | } |
| 456 | 460 | |
| 457 | 461 | case BPF_ALU | BPF_MOV | BPF_K: |
| 462 | + /* optimization: if imm32 is zero, use 'xor <dst>,<dst>' | |
| 463 | + * to save 3 bytes. | |
| 464 | + */ | |
| 465 | + if (imm32 == 0) { | |
| 466 | + if (is_ereg(dst_reg)) | |
| 467 | + EMIT1(add_2mod(0x40, dst_reg, dst_reg)); | |
| 468 | + b2 = 0x31; /* xor */ | |
| 469 | + b3 = 0xC0; | |
| 470 | + EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); | |
| 471 | + break; | |
| 472 | + } | |
| 473 | + | |
| 458 | 474 | /* mov %eax, imm32 */ |
| 459 | 475 | if (is_ereg(dst_reg)) |
| 460 | 476 | EMIT1(add_1mod(0x40, dst_reg)); |
| @@ -469,6 +485,20 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, · 8 unmodified lines | ||
| 469 | 485 | return -EINVAL; |
| 470 | 486 | } |
| 471 | 487 | |
| 488 | + /* optimization: if imm64 is zero, use 'xor <dst>,<dst>' | |
| 489 | + * to save 7 bytes. | |
| 490 | + */ | |
| 491 | + if (insn[0].imm == 0 && insn[1].imm == 0) { | |
| 492 | + b1 = add_2mod(0x48, dst_reg, dst_reg); | |
| 493 | + b2 = 0x31; /* xor */ | |
| 494 | + b3 = 0xC0; | |
| 495 | + EMIT3(b1, b2, add_2reg(b3, dst_reg, dst_reg)); | |
| 496 | + | |
| 497 | + insn++; | |
| 498 | + i++; | |
| 499 | + break; | |
| 500 | + } | |
| 501 | + | |
| 472 | 502 | /* movabsq %rax, imm64 */ |
| 473 | 503 | EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); |
| 474 | 504 | EMIT(insn[0].imm, 4); |
| @@ -96,4 +96,7 @@ · 95 unmodified lines | ||
| 96 | 96 | #define SO_ATTACH_BPF 50 |
| 97 | 97 | #define SO_DETACH_BPF SO_DETACH_FILTER |
| 98 | 98 | |
| 99 | +#define SO_ATTACH_REUSEPORT_CBPF 51 | |
| 100 | +#define SO_ATTACH_REUSEPORT_EBPF 52 | |
| 101 | + | |
| 99 | 102 | #endif /* _XTENSA_SOCKET_H */ |
| @@ -106,7 +106,7 @@ static void aead_wmem_wakeup(struct sock *sk) · 105 unmodified lines | ||
| 106 | 106 | |
| 107 | 107 | rcu_read_lock(); |
| 108 | 108 | wq = rcu_dereference(sk->sk_wq); |
| 109 | − if (wq_has_sleeper(wq)) | |
| 109 | + if (skwq_has_sleeper(wq)) | |
| 110 | 110 | wake_up_interruptible_sync_poll(&wq->wait, POLLIN | |
| 111 | 111 | POLLRDNORM | |
| 112 | 112 | POLLRDBAND); |
| @@ -157,7 +157,7 @@ static void aead_data_wakeup(struct sock *sk) · 44 unmodified lines | ||
| 157 | 157 | |
| 158 | 158 | rcu_read_lock(); |
| 159 | 159 | wq = rcu_dereference(sk->sk_wq); |
| 160 | − if (wq_has_sleeper(wq)) | |
| 160 | + if (skwq_has_sleeper(wq)) | |
| 161 | 161 | wake_up_interruptible_sync_poll(&wq->wait, POLLOUT | |
| 162 | 162 | POLLRDNORM | |
| 163 | 163 | POLLRDBAND); |
| @@ -238,7 +238,7 @@ static void skcipher_wmem_wakeup(struct sock *sk) · 237 unmodified lines | ||
| 238 | 238 | |
| 239 | 239 | rcu_read_lock(); |
| 240 | 240 | wq = rcu_dereference(sk->sk_wq); |
| 241 | − if (wq_has_sleeper(wq)) | |
| 241 | + if (skwq_has_sleeper(wq)) | |
| 242 | 242 | wake_up_interruptible_sync_poll(&wq->wait, POLLIN | |
| 243 | 243 | POLLRDNORM | |
| 244 | 244 | POLLRDBAND); |
| @@ -288,7 +288,7 @@ static void skcipher_data_wakeup(struct sock *sk) · 43 unmodified lines | ||
| 288 | 288 | |
| 289 | 289 | rcu_read_lock(); |
| 290 | 290 | wq = rcu_dereference(sk->sk_wq); |
| 291 | − if (wq_has_sleeper(wq)) | |
| 291 | + if (skwq_has_sleeper(wq)) | |
| 292 | 292 | wake_up_interruptible_sync_poll(&wq->wait, POLLOUT | |
| 293 | 293 | POLLRDNORM | |
| 294 | 294 | POLLRDBAND); |
| @@ -347,8 +347,8 @@ static char *next_string(struct sk_buff *skb) · 346 unmodified lines | ||
| 347 | 347 | */ |
| 348 | 348 | static int process_status(struct solos_card *card, int port, struct sk_buff *skb) |
| 349 | 349 | { |
| 350 | − char *str, *end, *state_str, *snr, *attn; | |
| 351 | − int ver, rate_up, rate_down; | |
| 350 | + char *str, *state_str, *snr, *attn; | |
| 351 | + int ver, rate_up, rate_down, err; | |
| 352 | 352 | |
| 353 | 353 | if (!card->atmdev[port]) |
| 354 | 354 | return -ENODEV; |
| @@ -357,7 +357,11 @@ static int process_status(struct solos_card *card, int port, struct sk_buff *skb · 2 unmodified lines | ||
| 357 | 357 | if (!str) |
| 358 | 358 | return -EIO; |
| 359 | 359 | |
| 360 | − ver = simple_strtol(str, NULL, 10); | |
| 360 | + err = kstrtoint(str, 10, &ver); | |
| 361 | + if (err) { | |
| 362 | + dev_warn(&card->dev->dev, "Unexpected status interrupt version\n"); | |
| 363 | + return err; | |
| 364 | + } | |
| 361 | 365 | if (ver < 1) { |
| 362 | 366 | dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n", |
| 363 | 367 | ver); |
| @@ -373,16 +377,16 @@ static int process_status(struct solos_card *card, int port, struct sk_buff *skb · 9 unmodified lines | ||
| 373 | 377 | return 0; |
| 374 | 378 | } |
| 375 | 379 | |
| 376 | − rate_down = simple_strtol(str, &end, 10); | |
| 377 | − if (*end) | |
| 378 | − return -EIO; | |
| 380 | + err = kstrtoint(str, 10, &rate_down); | |
| 381 | + if (err) | |
| 382 | + return err; | |
| 379 | 383 | |
| 380 | 384 | str = next_string(skb); |
| 381 | 385 | if (!str) |
| 382 | 386 | return -EIO; |
| 383 | − rate_up = simple_strtol(str, &end, 10); | |
| 384 | − if (*end) | |
| 385 | − return -EIO; | |
| 387 | + err = kstrtoint(str, 10, &rate_up); | |
| 388 | + if (err) | |
| 389 | + return err; | |
| 386 | 390 | |
| 387 | 391 | state_str = next_string(skb); |
| 388 | 392 | if (!state_str) |
| @@ -417,7 +421,7 @@ static int process_command(struct solos_card *card, int port, struct sk_buff *sk · 28 unmodified lines | ||
| 417 | 421 | struct solos_param *prm; |
| 418 | 422 | unsigned long flags; |
| 419 | 423 | int cmdpid; |
| 420 | − int found = 0; | |
| 424 | + int found = 0, err; | |
| 421 | 425 | |
| 422 | 426 | if (skb->len < 7) |
| 423 | 427 | return 0; |
| @@ -428,7 +432,9 @@ static int process_command(struct solos_card *card, int port, struct sk_buff *sk · 4 unmodified lines | ||
| 428 | 432 | skb->data[6] != '\n') |
| 429 | 433 | return 0; |
| 430 | 434 | |
| 431 | − cmdpid = simple_strtol(&skb->data[1], NULL, 10); | |
| 435 | + err = kstrtoint(&skb->data[1], 10, &cmdpid); | |
| 436 | + if (err) | |
| 437 | + return err; | |
| 432 | 438 | |
| 433 | 439 | spin_lock_irqsave(&card->param_queue_lock, flags); |
| 434 | 440 | list_for_each_entry(prm, &card->param_queue, list) { |
| @@ -519,7 +525,7 @@ struct geos_gpio_attr { · 84 unmodified lines | ||
| 519 | 525 | static ssize_t geos_gpio_store(struct device *dev, struct device_attribute *attr, |
| 520 | 526 | const char *buf, size_t count) |
| 521 | 527 | { |
| 522 | − struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
| 528 | + struct pci_dev *pdev = to_pci_dev(dev); | |
| 523 | 529 | struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr); |
| 524 | 530 | struct solos_card *card = pci_get_drvdata(pdev); |
| 525 | 531 | uint32_t data32; |
| @@ -545,7 +551,7 @@ static ssize_t geos_gpio_store(struct device *dev, struct device_attribute *attr · 19 unmodified lines | ||
| 545 | 551 | static ssize_t geos_gpio_show(struct device *dev, struct device_attribute *attr, |
| 546 | 552 | char *buf) |
| 547 | 553 | { |
| 548 | − struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
| 554 | + struct pci_dev *pdev = to_pci_dev(dev); | |
| 549 | 555 | struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr); |
| 550 | 556 | struct solos_card *card = pci_get_drvdata(pdev); |
| 551 | 557 | uint32_t data32; |
| @@ -559,7 +565,7 @@ static ssize_t geos_gpio_show(struct device *dev, struct device_attribute *attr, · 7 unmodified lines | ||
| 559 | 565 | static ssize_t hardware_show(struct device *dev, struct device_attribute *attr, |
| 560 | 566 | char *buf) |
| 561 | 567 | { |
| 562 | − struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
| 568 | + struct pci_dev *pdev = to_pci_dev(dev); | |
| 563 | 569 | struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr); |
| 564 | 570 | struct solos_card *card = pci_get_drvdata(pdev); |
| 565 | 571 | uint32_t data32; |
| @@ -668,11 +668,36 @@ static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env) · 667 unmodified lines | ||
| 668 | 668 | core->id.rev, core->id.class); |
| 669 | 669 | } |
| 670 | 670 | |
| 671 | −static int __init bcma_modinit(void) | |
| 671 | +static unsigned int bcma_bus_registered; | |
| 672 | + | |
| 673 | +/* | |
| 674 | + * If built-in, bus has to be registered early, before any driver calls | |
| 675 | + * bcma_driver_register. | |
| 676 | + * Otherwise registering driver would trigger BUG in driver_register. | |
| 677 | + */ | |
| 678 | +static int __init bcma_init_bus_register(void) | |
| 672 | 679 | { |
| 673 | 680 | int err; |
| 674 | 681 | |
| 682 | + if (bcma_bus_registered) | |
| 683 | + return 0; | |
| 684 | + | |
| 675 | 685 | err = bus_register(&bcma_bus_type); |
| 686 | + if (!err) | |
| 687 | + bcma_bus_registered = 1; | |
| 688 | + | |
| 689 | + return err; | |
| 690 | +} | |
| 691 | +#ifndef MODULE | |
| 692 | +fs_initcall(bcma_init_bus_register); | |
| 693 | +#endif | |
| 694 | + | |
| 695 | +/* Main initialization has to be done with SPI/mtd/NAND/SPROM available */ | |
| 696 | +static int __init bcma_modinit(void) | |
| 697 | +{ | |
| 698 | + int err; | |
| 699 | + | |
| 700 | + err = bcma_init_bus_register(); | |
| 676 | 701 | if (err) |
| 677 | 702 | return err; |
| 678 | 703 | |
| @@ -691,7 +716,7 @@ static int __init bcma_modinit(void) · 12 unmodified lines | ||
| 691 | 716 | |
| 692 | 717 | return err; |
| 693 | 718 | } |
| 694 | −fs_initcall(bcma_modinit); | |
| 719 | +module_init(bcma_modinit); | |
| 695 | 720 | |
| 696 | 721 | static void __exit bcma_modexit(void) |
| 697 | 722 | { |
| @@ -178,10 +178,8 @@ static int bcm203x_probe(struct usb_interface *intf, const struct usb_device_id · 177 unmodified lines | ||
| 178 | 178 | return -ENODEV; |
| 179 | 179 | |
| 180 | 180 | data = devm_kzalloc(&intf->dev, sizeof(*data), GFP_KERNEL); |
| 181 | − if (!data) { | |
| 182 | − BT_ERR("Can't allocate memory for data structure"); | |
| 181 | + if (!data) | |
| 183 | 182 | return -ENOMEM; |
| 184 | − } | |
| 185 | 183 | |
| 186 | 184 | data->udev = udev; |
| 187 | 185 | data->state = BCM203X_LOAD_MINIDRV; |
| @@ -324,7 +324,7 @@ static inline int bfusb_recv_block(struct bfusb_data *data, int hdr, unsigned ch · 323 unmodified lines | ||
| 324 | 324 | return -ENOMEM; |
| 325 | 325 | } |
| 326 | 326 | |
| 327 | − bt_cb(skb)->pkt_type = pkt_type; | |
| 327 | + hci_skb_pkt_type(skb) = pkt_type; | |
| 328 | 328 | |
| 329 | 329 | data->reassembly = skb; |
| 330 | 330 | } else { |
| @@ -469,9 +469,10 @@ static int bfusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 138 unmodified lines | ||
| 469 | 469 | unsigned char buf[3]; |
| 470 | 470 | int sent = 0, size, count; |
| 471 | 471 | |
| 472 | − BT_DBG("hdev %p skb %p type %d len %d", hdev, skb, bt_cb(skb)->pkt_type, skb->len); | |
| 472 | + BT_DBG("hdev %p skb %p type %d len %d", hdev, skb, | |
| 473 | + hci_skb_pkt_type(skb), skb->len); | |
| 473 | 474 | |
| 474 | − switch (bt_cb(skb)->pkt_type) { | |
| 475 | + switch (hci_skb_pkt_type(skb)) { | |
| 475 | 476 | case HCI_COMMAND_PKT: |
| 476 | 477 | hdev->stat.cmd_tx++; |
| 477 | 478 | break; |
| @@ -484,7 +485,7 @@ static int bfusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 6 unmodified lines | ||
| 484 | 485 | } |
| 485 | 486 | |
| 486 | 487 | /* Prepend skb with frame type */ |
| 487 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 488 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 488 | 489 | |
| 489 | 490 | count = skb->len; |
| 490 | 491 | |
| @@ -635,10 +636,8 @@ static int bfusb_probe(struct usb_interface *intf, const struct usb_device_id *i · 144 unmodified lines | ||
| 635 | 636 | |
| 636 | 637 | /* Initialize control structure and load firmware */ |
| 637 | 638 | data = devm_kzalloc(&intf->dev, sizeof(struct bfusb_data), GFP_KERNEL); |
| 638 | − if (!data) { | |
| 639 | − BT_ERR("Can't allocate memory for control structure"); | |
| 640 | − goto done; | |
| 641 | − } | |
| 639 | + if (!data) | |
| 640 | + return -ENOMEM; | |
| 642 | 641 | |
| 643 | 642 | data->udev = udev; |
| 644 | 643 | data->bulk_in_ep = bulk_in_ep->desc.bEndpointAddress; |
| @@ -261,7 +261,7 @@ static void bluecard_write_wakeup(struct bluecard_info *info) · 260 unmodified lines | ||
| 261 | 261 | if (!skb) |
| 262 | 262 | break; |
| 263 | 263 | |
| 264 | − if (bt_cb(skb)->pkt_type & 0x80) { | |
| 264 | + if (hci_skb_pkt_type(skb) & 0x80) { | |
| 265 | 265 | /* Disable RTS */ |
| 266 | 266 | info->ctrl_reg |= REG_CONTROL_RTS; |
| 267 | 267 | outb(info->ctrl_reg, iobase + REG_CONTROL); |
| @@ -279,13 +279,13 @@ static void bluecard_write_wakeup(struct bluecard_info *info) · 11 unmodified lines | ||
| 279 | 279 | /* Mark the buffer as dirty */ |
| 280 | 280 | clear_bit(ready_bit, &(info->tx_state)); |
| 281 | 281 | |
| 282 | − if (bt_cb(skb)->pkt_type & 0x80) { | |
| 282 | + if (hci_skb_pkt_type(skb) & 0x80) { | |
| 283 | 283 | DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq); |
| 284 | 284 | DEFINE_WAIT(wait); |
| 285 | 285 | |
| 286 | 286 | unsigned char baud_reg; |
| 287 | 287 | |
| 288 | − switch (bt_cb(skb)->pkt_type) { | |
| 288 | + switch (hci_skb_pkt_type(skb)) { | |
| 289 | 289 | case PKT_BAUD_RATE_460800: |
| 290 | 290 | baud_reg = REG_CONTROL_BAUD_RATE_460800; |
| 291 | 291 | break; |
| @@ -402,9 +402,9 @@ static void bluecard_receive(struct bluecard_info *info, · 110 unmodified lines | ||
| 402 | 402 | |
| 403 | 403 | if (info->rx_state == RECV_WAIT_PACKET_TYPE) { |
| 404 | 404 | |
| 405 | − bt_cb(info->rx_skb)->pkt_type = buf[i]; | |
| 405 | + hci_skb_pkt_type(info->rx_skb) = buf[i]; | |
| 406 | 406 | |
| 407 | − switch (bt_cb(info->rx_skb)->pkt_type) { | |
| 407 | + switch (hci_skb_pkt_type(info->rx_skb)) { | |
| 408 | 408 | |
| 409 | 409 | case 0x00: |
| 410 | 410 | /* init packet */ |
| @@ -436,7 +436,8 @@ static void bluecard_receive(struct bluecard_info *info, · 25 unmodified lines | ||
| 436 | 436 | |
| 437 | 437 | default: |
| 438 | 438 | /* unknown packet */ |
| 439 | − BT_ERR("Unknown HCI packet with type 0x%02x received", bt_cb(info->rx_skb)->pkt_type); | |
| 439 | + BT_ERR("Unknown HCI packet with type 0x%02x received", | |
| 440 | + hci_skb_pkt_type(info->rx_skb)); | |
| 440 | 441 | info->hdev->stat.err_rx++; |
| 441 | 442 | |
| 442 | 443 | kfree_skb(info->rx_skb); |
| @@ -578,21 +579,21 @@ static int bluecard_hci_set_baud_rate(struct hci_dev *hdev, int baud) · 135 unmodified lines | ||
| 578 | 579 | switch (baud) { |
| 579 | 580 | case 460800: |
| 580 | 581 | cmd[4] = 0x00; |
| 581 | − bt_cb(skb)->pkt_type = PKT_BAUD_RATE_460800; | |
| 582 | + hci_skb_pkt_type(skb) = PKT_BAUD_RATE_460800; | |
| 582 | 583 | break; |
| 583 | 584 | case 230400: |
| 584 | 585 | cmd[4] = 0x01; |
| 585 | − bt_cb(skb)->pkt_type = PKT_BAUD_RATE_230400; | |
| 586 | + hci_skb_pkt_type(skb) = PKT_BAUD_RATE_230400; | |
| 586 | 587 | break; |
| 587 | 588 | case 115200: |
| 588 | 589 | cmd[4] = 0x02; |
| 589 | − bt_cb(skb)->pkt_type = PKT_BAUD_RATE_115200; | |
| 590 | + hci_skb_pkt_type(skb) = PKT_BAUD_RATE_115200; | |
| 590 | 591 | break; |
| 591 | 592 | case 57600: |
| 592 | 593 | /* Fall through... */ |
| 593 | 594 | default: |
| 594 | 595 | cmd[4] = 0x03; |
| 595 | − bt_cb(skb)->pkt_type = PKT_BAUD_RATE_57600; | |
| 596 | + hci_skb_pkt_type(skb) = PKT_BAUD_RATE_57600; | |
| 596 | 597 | break; |
| 597 | 598 | } |
| 598 | 599 | |
| @@ -660,7 +661,7 @@ static int bluecard_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 61 unmodified lines | ||
| 660 | 661 | { |
| 661 | 662 | struct bluecard_info *info = hci_get_drvdata(hdev); |
| 662 | 663 | |
| 663 | − switch (bt_cb(skb)->pkt_type) { | |
| 664 | + switch (hci_skb_pkt_type(skb)) { | |
| 664 | 665 | case HCI_COMMAND_PKT: |
| 665 | 666 | hdev->stat.cmd_tx++; |
| 666 | 667 | break; |
| @@ -673,7 +674,7 @@ static int bluecard_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 6 unmodified lines | ||
| 673 | 674 | } |
| 674 | 675 | |
| 675 | 676 | /* Prepend skb with frame type */ |
| 676 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 677 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 677 | 678 | skb_queue_tail(&(info->txq), skb); |
| 678 | 679 | |
| 679 | 680 | bluecard_write_wakeup(info); |
| @@ -295,9 +295,9 @@ static int bpa10x_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 294 unmodified lines | ||
| 295 | 295 | return -ENOMEM; |
| 296 | 296 | |
| 297 | 297 | /* Prepend skb with frame type */ |
| 298 | − *skb_push(skb, 1) = bt_cb(skb)->pkt_type; | |
| 298 | + *skb_push(skb, 1) = hci_skb_pkt_type(skb); | |
| 299 | 299 | |
| 300 | − switch (bt_cb(skb)->pkt_type) { | |
| 300 | + switch (hci_skb_pkt_type(skb)) { | |
| 301 | 301 | case HCI_COMMAND_PKT: |
| 302 | 302 | dr = kmalloc(sizeof(*dr), GFP_ATOMIC); |
| 303 | 303 | if (!dr) { |
| @@ -246,10 +246,10 @@ static void bt3c_receive(struct bt3c_info *info) · 245 unmodified lines | ||
| 246 | 246 | |
| 247 | 247 | if (info->rx_state == RECV_WAIT_PACKET_TYPE) { |
| 248 | 248 | |
| 249 | − bt_cb(info->rx_skb)->pkt_type = inb(iobase + DATA_L); | |
| 249 | + hci_skb_pkt_type(info->rx_skb) = inb(iobase + DATA_L); | |
| 250 | 250 | inb(iobase + DATA_H); |
| 251 | 251 | |
| 252 | − switch (bt_cb(info->rx_skb)->pkt_type) { | |
| 252 | + switch (hci_skb_pkt_type(info->rx_skb)) { | |
| 253 | 253 | |
| 254 | 254 | case HCI_EVENT_PKT: |
| 255 | 255 | info->rx_state = RECV_WAIT_EVENT_HEADER; |
| @@ -268,7 +268,8 @@ static void bt3c_receive(struct bt3c_info *info) · 12 unmodified lines | ||
| 268 | 268 | |
| 269 | 269 | default: |
| 270 | 270 | /* Unknown packet */ |
| 271 | − BT_ERR("Unknown HCI packet with type 0x%02x received", bt_cb(info->rx_skb)->pkt_type); | |
| 271 | + BT_ERR("Unknown HCI packet with type 0x%02x received", | |
| 272 | + hci_skb_pkt_type(info->rx_skb)); | |
| 272 | 273 | info->hdev->stat.err_rx++; |
| 273 | 274 | |
| 274 | 275 | kfree_skb(info->rx_skb); |
| @@ -411,7 +412,7 @@ static int bt3c_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 136 unmodified lines | ||
| 411 | 412 | struct bt3c_info *info = hci_get_drvdata(hdev); |
| 412 | 413 | unsigned long flags; |
| 413 | 414 | |
| 414 | − switch (bt_cb(skb)->pkt_type) { | |
| 415 | + switch (hci_skb_pkt_type(skb)) { | |
| 415 | 416 | case HCI_COMMAND_PKT: |
| 416 | 417 | hdev->stat.cmd_tx++; |
| 417 | 418 | break; |
| @@ -424,7 +425,7 @@ static int bt3c_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 6 unmodified lines | ||
| 424 | 425 | } |
| 425 | 426 | |
| 426 | 427 | /* Prepend skb with frame type */ |
| 427 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 428 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 428 | 429 | skb_queue_tail(&(info->txq), skb); |
| 429 | 430 | |
| 430 | 431 | spin_lock_irqsave(&(info->lock), flags); |
| @@ -73,6 +73,48 @@ int btintel_check_bdaddr(struct hci_dev *hdev) · 72 unmodified lines | ||
| 73 | 73 | } |
| 74 | 74 | EXPORT_SYMBOL_GPL(btintel_check_bdaddr); |
| 75 | 75 | |
| 76 | +int btintel_enter_mfg(struct hci_dev *hdev) | |
| 77 | +{ | |
| 78 | + const u8 param[] = { 0x01, 0x00 }; | |
| 79 | + struct sk_buff *skb; | |
| 80 | + | |
| 81 | + skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT); | |
| 82 | + if (IS_ERR(skb)) { | |
| 83 | + bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)", | |
| 84 | + PTR_ERR(skb)); | |
| 85 | + return PTR_ERR(skb); | |
| 86 | + } | |
| 87 | + kfree_skb(skb); | |
| 88 | + | |
| 89 | + return 0; | |
| 90 | +} | |
| 91 | +EXPORT_SYMBOL_GPL(btintel_enter_mfg); | |
| 92 | + | |
| 93 | +int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) | |
| 94 | +{ | |
| 95 | + u8 param[] = { 0x00, 0x00 }; | |
| 96 | + struct sk_buff *skb; | |
| 97 | + | |
| 98 | + /* The 2nd command parameter specifies the manufacturing exit method: | |
| 99 | + * 0x00: Just disable the manufacturing mode (0x00). | |
| 100 | + * 0x01: Disable manufacturing mode and reset with patches deactivated. | |
| 101 | + * 0x02: Disable manufacturing mode and reset with patches activated. | |
| 102 | + */ | |
| 103 | + if (reset) | |
| 104 | + param[1] |= patched ? 0x02 : 0x01; | |
| 105 | + | |
| 106 | + skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT); | |
| 107 | + if (IS_ERR(skb)) { | |
| 108 | + bt_dev_err(hdev, "Exiting manufacturer mode failed (%ld)", | |
| 109 | + PTR_ERR(skb)); | |
| 110 | + return PTR_ERR(skb); | |
| 111 | + } | |
| 112 | + kfree_skb(skb); | |
| 113 | + | |
| 114 | + return 0; | |
| 115 | +} | |
| 116 | +EXPORT_SYMBOL_GPL(btintel_exit_mfg); | |
| 117 | + | |
| 76 | 118 | int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) |
| 77 | 119 | { |
| 78 | 120 | struct sk_buff *skb; |
| @@ -126,37 +168,19 @@ EXPORT_SYMBOL_GPL(btintel_set_diag); · 47 unmodified lines | ||
| 126 | 168 | |
| 127 | 169 | int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable) |
| 128 | 170 | { |
| 129 | − struct sk_buff *skb; | |
| 130 | − u8 param[2]; | |
| 131 | − int err; | |
| 132 | − | |
| 133 | − param[0] = 0x01; | |
| 134 | − param[1] = 0x00; | |
| 135 | − | |
| 136 | − skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_INIT_TIMEOUT); | |
| 137 | − if (IS_ERR(skb)) { | |
| 138 | − err = PTR_ERR(skb); | |
| 139 | − BT_ERR("%s: Entering Intel manufacturer mode failed (%d)", | |
| 140 | − hdev->name, err); | |
| 141 | − return PTR_ERR(skb); | |
| 142 | − } | |
| 143 | − kfree_skb(skb); | |
| 171 | + int err, ret; | |
| 144 | 172 | |
| 145 | − err = btintel_set_diag(hdev, enable); | |
| 173 | + err = btintel_enter_mfg(hdev); | |
| 174 | + if (err) | |
| 175 | + return err; | |
| 146 | 176 | |
| 147 | − param[0] = 0x00; | |
| 148 | − param[1] = 0x00; | |
| 177 | + ret = btintel_set_diag(hdev, enable); | |
| 149 | 178 | |
| 150 | − skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_INIT_TIMEOUT); | |
| 151 | − if (IS_ERR(skb)) { | |
| 152 | − err = PTR_ERR(skb); | |
| 153 | − BT_ERR("%s: Leaving Intel manufacturer mode failed (%d)", | |
| 154 | − hdev->name, err); | |
| 155 | − return PTR_ERR(skb); | |
| 156 | − } | |
| 157 | − kfree_skb(skb); | |
| 179 | + err = btintel_exit_mfg(hdev, false, false); | |
| 180 | + if (err) | |
| 181 | + return err; | |
| 158 | 182 | |
| 159 | − return err; | |
| 183 | + return ret; | |
| 160 | 184 | } |
| 161 | 185 | EXPORT_SYMBOL_GPL(btintel_set_diag_mfg); |
| 162 | 186 | |
| @@ -309,39 +333,46 @@ EXPORT_SYMBOL_GPL(btintel_set_event_mask); · 146 unmodified lines | ||
| 309 | 333 | |
| 310 | 334 | int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) |
| 311 | 335 | { |
| 312 | − struct sk_buff *skb; | |
| 313 | − u8 param[2]; | |
| 314 | − int err; | |
| 336 | + int err, ret; | |
| 315 | 337 | |
| 316 | − param[0] = 0x01; | |
| 317 | − param[1] = 0x00; | |
| 338 | + err = btintel_enter_mfg(hdev); | |
| 339 | + if (err) | |
| 340 | + return err; | |
| 318 | 341 | |
| 319 | − skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_INIT_TIMEOUT); | |
| 320 | − if (IS_ERR(skb)) { | |
| 321 | − err = PTR_ERR(skb); | |
| 322 | − BT_ERR("%s: Entering Intel manufacturer mode failed (%d)", | |
| 323 | − hdev->name, err); | |
| 324 | − return PTR_ERR(skb); | |
| 325 | − } | |
| 326 | − kfree_skb(skb); | |
| 342 | + ret = btintel_set_event_mask(hdev, debug); | |
| 327 | 343 | |
| 328 | − err = btintel_set_event_mask(hdev, debug); | |
| 344 | + err = btintel_exit_mfg(hdev, false, false); | |
| 345 | + if (err) | |
| 346 | + return err; | |
| 329 | 347 | |
| 330 | − param[0] = 0x00; | |
| 331 | − param[1] = 0x00; | |
| 348 | + return ret; | |
| 349 | +} | |
| 350 | +EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg); | |
| 332 | 351 | |
| 333 | − skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_INIT_TIMEOUT); | |
| 352 | +int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver) | |
| 353 | +{ | |
| 354 | + struct sk_buff *skb; | |
| 355 | + | |
| 356 | + skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT); | |
| 334 | 357 | if (IS_ERR(skb)) { |
| 335 | − err = PTR_ERR(skb); | |
| 336 | − BT_ERR("%s: Leaving Intel manufacturer mode failed (%d)", | |
| 337 | − hdev->name, err); | |
| 358 | + bt_dev_err(hdev, "Reading Intel version information failed (%ld)", | |
| 359 | + PTR_ERR(skb)); | |
| 338 | 360 | return PTR_ERR(skb); |
| 339 | 361 | } |
| 362 | + | |
| 363 | + if (skb->len != sizeof(*ver)) { | |
| 364 | + bt_dev_err(hdev, "Intel version event size mismatch"); | |
| 365 | + kfree_skb(skb); | |
| 366 | + return -EILSEQ; | |
| 367 | + } | |
| 368 | + | |
| 369 | + memcpy(ver, skb->data, sizeof(*ver)); | |
| 370 | + | |
| 340 | 371 | kfree_skb(skb); |
| 341 | 372 | |
| 342 | − return err; | |
| 373 | + return 0; | |
| 343 | 374 | } |
| 344 | −EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg); | |
| 375 | +EXPORT_SYMBOL_GPL(btintel_read_version); | |
| 345 | 376 | |
| 346 | 377 | /* ------- REGMAP IBT SUPPORT ------- */ |
| 347 | 378 | |
| @@ -72,6 +72,8 @@ struct intel_secure_send_result { · 71 unmodified lines | ||
| 72 | 72 | #if IS_ENABLED(CONFIG_BT_INTEL) |
| 73 | 73 | |
| 74 | 74 | int btintel_check_bdaddr(struct hci_dev *hdev); |
| 75 | +int btintel_enter_mfg(struct hci_dev *hdev); | |
| 76 | +int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched); | |
| 75 | 77 | int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); |
| 76 | 78 | int btintel_set_diag(struct hci_dev *hdev, bool enable); |
| 77 | 79 | int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable); |
| @@ -83,6 +85,7 @@ int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen, · 5 unmodified lines | ||
| 83 | 85 | int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name); |
| 84 | 86 | int btintel_set_event_mask(struct hci_dev *hdev, bool debug); |
| 85 | 87 | int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug); |
| 88 | +int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver); | |
| 86 | 89 | |
| 87 | 90 | struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, |
| 88 | 91 | u16 opcode_write); |
| @@ -94,6 +97,16 @@ static inline int btintel_check_bdaddr(struct hci_dev *hdev) · 5 unmodified lines | ||
| 94 | 97 | return -EOPNOTSUPP; |
| 95 | 98 | } |
| 96 | 99 | |
| 100 | +static inline int btintel_enter_mfg(struct hci_dev *hdev) | |
| 101 | +{ | |
| 102 | + return -EOPNOTSUPP; | |
| 103 | +} | |
| 104 | + | |
| 105 | +static inline int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) | |
| 106 | +{ | |
| 107 | + return -EOPNOTSUPP; | |
| 108 | +} | |
| 109 | + | |
| 97 | 110 | static inline int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) |
| 98 | 111 | { |
| 99 | 112 | return -EOPNOTSUPP; |
| @@ -140,6 +153,12 @@ static inline int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) · 40 unmodified lines | ||
| 140 | 153 | return -EOPNOTSUPP; |
| 141 | 154 | } |
| 142 | 155 | |
| 156 | +static inline int btintel_read_version(struct hci_dev *hdev, | |
| 157 | + struct intel_version *ver) | |
| 158 | +{ | |
| 159 | + return -EOPNOTSUPP; | |
| 160 | +} | |
| 161 | + | |
| 143 | 162 | static inline struct regmap *btintel_regmap_init(struct hci_dev *hdev, |
| 144 | 163 | u16 opcode_read, |
| 145 | 164 | u16 opcode_write) |
| @@ -89,6 +89,7 @@ struct btmrvl_adapter { · 88 unmodified lines | ||
| 89 | 89 | wait_queue_head_t event_hs_wait_q; |
| 90 | 90 | u8 cmd_complete; |
| 91 | 91 | bool is_suspended; |
| 92 | + bool is_suspending; | |
| 92 | 93 | }; |
| 93 | 94 | |
| 94 | 95 | struct btmrvl_private { |
| @@ -196,7 +196,7 @@ static int btmrvl_send_sync_cmd(struct btmrvl_private *priv, u16 opcode, · 195 unmodified lines | ||
| 196 | 196 | if (len) |
| 197 | 197 | memcpy(skb_put(skb, len), param, len); |
| 198 | 198 | |
| 199 | − bt_cb(skb)->pkt_type = MRVL_VENDOR_PKT; | |
| 199 | + hci_skb_pkt_type(skb) = MRVL_VENDOR_PKT; | |
| 200 | 200 | |
| 201 | 201 | skb_queue_head(&priv->adapter->tx_queue, skb); |
| 202 | 202 | |
| @@ -387,7 +387,7 @@ static int btmrvl_tx_pkt(struct btmrvl_private *priv, struct sk_buff *skb) · 184 unmodified lines | ||
| 387 | 387 | skb->data[0] = (skb->len & 0x0000ff); |
| 388 | 388 | skb->data[1] = (skb->len & 0x00ff00) >> 8; |
| 389 | 389 | skb->data[2] = (skb->len & 0xff0000) >> 16; |
| 390 | − skb->data[3] = bt_cb(skb)->pkt_type; | |
| 390 | + skb->data[3] = hci_skb_pkt_type(skb); | |
| 391 | 391 | |
| 392 | 392 | if (priv->hw_host_to_card) |
| 393 | 393 | ret = priv->hw_host_to_card(priv, skb->data, skb->len); |
| @@ -434,9 +434,14 @@ static int btmrvl_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 40 unmodified lines | ||
| 434 | 434 | { |
| 435 | 435 | struct btmrvl_private *priv = hci_get_drvdata(hdev); |
| 436 | 436 | |
| 437 | − BT_DBG("type=%d, len=%d", skb->pkt_type, skb->len); | |
| 437 | + BT_DBG("type=%d, len=%d", hci_skb_pkt_type(skb), skb->len); | |
| 438 | 438 | |
| 439 | − switch (bt_cb(skb)->pkt_type) { | |
| 439 | + if (priv->adapter->is_suspending || priv->adapter->is_suspended) { | |
| 440 | + BT_ERR("%s: Device is suspending or suspended", __func__); | |
| 441 | + return -EBUSY; | |
| 442 | + } | |
| 443 | + | |
| 444 | + switch (hci_skb_pkt_type(skb)) { | |
| 440 | 445 | case HCI_COMMAND_PKT: |
| 441 | 446 | hdev->stat.cmd_tx++; |
| 442 | 447 | break; |
| @@ -452,7 +457,8 @@ static int btmrvl_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 9 unmodified lines | ||
| 452 | 457 | |
| 453 | 458 | skb_queue_tail(&priv->adapter->tx_queue, skb); |
| 454 | 459 | |
| 455 | − wake_up_interruptible(&priv->main_thread.wait_q); | |
| 460 | + if (!priv->adapter->is_suspended) | |
| 461 | + wake_up_interruptible(&priv->main_thread.wait_q); | |
| 456 | 462 | |
| 457 | 463 | return 0; |
| 458 | 464 | } |
| @@ -543,7 +549,7 @@ static int btmrvl_setup(struct hci_dev *hdev) · 84 unmodified lines | ||
| 543 | 549 | if (ret) |
| 544 | 550 | return ret; |
| 545 | 551 | |
| 546 | − priv->btmrvl_dev.gpio_gap = 0xffff; | |
| 552 | + priv->btmrvl_dev.gpio_gap = 0xfffe; | |
| 547 | 553 | |
| 548 | 554 | btmrvl_check_device_tree(priv); |
| 549 | 555 | |
| @@ -643,7 +649,8 @@ static int btmrvl_service_main_thread(void *data) · 93 unmodified lines | ||
| 643 | 649 | if (adapter->ps_state == PS_SLEEP) |
| 644 | 650 | continue; |
| 645 | 651 | |
| 646 | − if (!priv->btmrvl_dev.tx_dnld_rdy) | |
| 652 | + if (!priv->btmrvl_dev.tx_dnld_rdy || | |
| 653 | + priv->adapter->is_suspended) | |
| 647 | 654 | continue; |
| 648 | 655 | |
| 649 | 656 | skb = skb_dequeue(&adapter->tx_queue); |
| @@ -698,7 +698,7 @@ static int btmrvl_sdio_card_to_host(struct btmrvl_private *priv) · 697 unmodified lines | ||
| 698 | 698 | case HCI_ACLDATA_PKT: |
| 699 | 699 | case HCI_SCODATA_PKT: |
| 700 | 700 | case HCI_EVENT_PKT: |
| 701 | − bt_cb(skb)->pkt_type = type; | |
| 701 | + hci_skb_pkt_type(skb) = type; | |
| 702 | 702 | skb_put(skb, buf_len); |
| 703 | 703 | skb_pull(skb, SDIO_HEADER_LEN); |
| 704 | 704 | |
| @@ -713,7 +713,7 @@ static int btmrvl_sdio_card_to_host(struct btmrvl_private *priv) · 8 unmodified lines | ||
| 713 | 713 | break; |
| 714 | 714 | |
| 715 | 715 | case MRVL_VENDOR_PKT: |
| 716 | − bt_cb(skb)->pkt_type = HCI_VENDOR_PKT; | |
| 716 | + hci_skb_pkt_type(skb) = HCI_VENDOR_PKT; | |
| 717 | 717 | skb_put(skb, buf_len); |
| 718 | 718 | skb_pull(skb, SDIO_HEADER_LEN); |
| 719 | 719 | |
| @@ -1112,7 +1112,8 @@ static int btmrvl_sdio_download_fw(struct btmrvl_sdio_card *card) · 392 unmodified lines | ||
| 1112 | 1112 | */ |
| 1113 | 1113 | if (btmrvl_sdio_verify_fw_download(card, pollnum)) { |
| 1114 | 1114 | BT_ERR("FW failed to be active in time!"); |
| 1115 | − return -ETIMEDOUT; | |
| 1115 | + ret = -ETIMEDOUT; | |
| 1116 | + goto done; | |
| 1116 | 1117 | } |
| 1117 | 1118 | |
| 1118 | 1119 | sdio_release_host(card->func); |
| @@ -1544,10 +1545,10 @@ static int btmrvl_sdio_suspend(struct device *dev) · 425 unmodified lines | ||
| 1544 | 1545 | } |
| 1545 | 1546 | |
| 1546 | 1547 | priv = card->priv; |
| 1548 | + priv->adapter->is_suspending = true; | |
| 1547 | 1549 | hcidev = priv->btmrvl_dev.hcidev; |
| 1548 | 1550 | BT_DBG("%s: SDIO suspend", hcidev->name); |
| 1549 | 1551 | hci_suspend_dev(hcidev); |
| 1550 | − skb_queue_purge(&priv->adapter->tx_queue); | |
| 1551 | 1552 | |
| 1552 | 1553 | if (priv->adapter->hs_state != HS_ACTIVATED) { |
| 1553 | 1554 | if (btmrvl_enable_hs(priv)) { |
| @@ -1556,6 +1557,7 @@ static int btmrvl_sdio_suspend(struct device *dev) · 2 unmodified lines | ||
| 1556 | 1557 | } |
| 1557 | 1558 | } |
| 1558 | 1559 | |
| 1560 | + priv->adapter->is_suspending = false; | |
| 1559 | 1561 | priv->adapter->is_suspended = true; |
| 1560 | 1562 | |
| 1561 | 1563 | /* We will keep the power when hs enabled successfully */ |
| @@ -86,7 +86,7 @@ static int btsdio_tx_packet(struct btsdio_data *data, struct sk_buff *skb) · 85 unmodified lines | ||
| 86 | 86 | skb->data[0] = (skb->len & 0x0000ff); |
| 87 | 87 | skb->data[1] = (skb->len & 0x00ff00) >> 8; |
| 88 | 88 | skb->data[2] = (skb->len & 0xff0000) >> 16; |
| 89 | − skb->data[3] = bt_cb(skb)->pkt_type; | |
| 89 | + skb->data[3] = hci_skb_pkt_type(skb); | |
| 90 | 90 | |
| 91 | 91 | err = sdio_writesb(data->func, REG_TDAT, skb->data, skb->len); |
| 92 | 92 | if (err < 0) { |
| @@ -158,7 +158,7 @@ static int btsdio_rx_packet(struct btsdio_data *data) · 65 unmodified lines | ||
| 158 | 158 | |
| 159 | 159 | data->hdev->stat.byte_rx += len; |
| 160 | 160 | |
| 161 | − bt_cb(skb)->pkt_type = hdr[3]; | |
| 161 | + hci_skb_pkt_type(skb) = hdr[3]; | |
| 162 | 162 | |
| 163 | 163 | err = hci_recv_frame(data->hdev, skb); |
| 164 | 164 | if (err < 0) |
| @@ -252,7 +252,7 @@ static int btsdio_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 87 unmodified lines | ||
| 252 | 252 | |
| 253 | 253 | BT_DBG("%s", hdev->name); |
| 254 | 254 | |
| 255 | − switch (bt_cb(skb)->pkt_type) { | |
| 255 | + switch (hci_skb_pkt_type(skb)) { | |
| 256 | 256 | case HCI_COMMAND_PKT: |
| 257 | 257 | hdev->stat.cmd_tx++; |
| 258 | 258 | break; |
| @@ -200,9 +200,9 @@ static void btuart_receive(struct btuart_info *info) · 199 unmodified lines | ||
| 200 | 200 | |
| 201 | 201 | if (info->rx_state == RECV_WAIT_PACKET_TYPE) { |
| 202 | 202 | |
| 203 | − bt_cb(info->rx_skb)->pkt_type = inb(iobase + UART_RX); | |
| 203 | + hci_skb_pkt_type(info->rx_skb) = inb(iobase + UART_RX); | |
| 204 | 204 | |
| 205 | − switch (bt_cb(info->rx_skb)->pkt_type) { | |
| 205 | + switch (hci_skb_pkt_type(info->rx_skb)) { | |
| 206 | 206 | |
| 207 | 207 | case HCI_EVENT_PKT: |
| 208 | 208 | info->rx_state = RECV_WAIT_EVENT_HEADER; |
| @@ -221,7 +221,8 @@ static void btuart_receive(struct btuart_info *info) · 12 unmodified lines | ||
| 221 | 221 | |
| 222 | 222 | default: |
| 223 | 223 | /* Unknown packet */ |
| 224 | − BT_ERR("Unknown HCI packet with type 0x%02x received", bt_cb(info->rx_skb)->pkt_type); | |
| 224 | + BT_ERR("Unknown HCI packet with type 0x%02x received", | |
| 225 | + hci_skb_pkt_type(info->rx_skb)); | |
| 225 | 226 | info->hdev->stat.err_rx++; |
| 226 | 227 | |
| 227 | 228 | kfree_skb(info->rx_skb); |
| @@ -424,7 +425,7 @@ static int btuart_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 196 unmodified lines | ||
| 424 | 425 | { |
| 425 | 426 | struct btuart_info *info = hci_get_drvdata(hdev); |
| 426 | 427 | |
| 427 | − switch (bt_cb(skb)->pkt_type) { | |
| 428 | + switch (hci_skb_pkt_type(skb)) { | |
| 428 | 429 | case HCI_COMMAND_PKT: |
| 429 | 430 | hdev->stat.cmd_tx++; |
| 430 | 431 | break; |
| @@ -437,7 +438,7 @@ static int btuart_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 6 unmodified lines | ||
| 437 | 438 | } |
| 438 | 439 | |
| 439 | 440 | /* Prepend skb with frame type */ |
| 440 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 441 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 441 | 442 | skb_queue_tail(&(info->txq), skb); |
| 442 | 443 | |
| 443 | 444 | btuart_write_wakeup(info); |
| @@ -153,6 +153,10 @@ static const struct usb_device_id btusb_table[] = { · 152 unmodified lines | ||
| 153 | 153 | { USB_VENDOR_AND_INTERFACE_INFO(0x13d3, 0xff, 0x01, 0x01), |
| 154 | 154 | .driver_info = BTUSB_BCM_PATCHRAM }, |
| 155 | 155 | |
| 156 | + /* Toshiba Corp - Broadcom based */ | |
| 157 | + { USB_VENDOR_AND_INTERFACE_INFO(0x0930, 0xff, 0x01, 0x01), | |
| 158 | + .driver_info = BTUSB_BCM_PATCHRAM }, | |
| 159 | + | |
| 156 | 160 | /* Intel Bluetooth USB Bootloader (RAM module) */ |
| 157 | 161 | { USB_DEVICE(0x8087, 0x0a5a), |
| 158 | 162 | .driver_info = BTUSB_INTEL_BOOT | BTUSB_BROKEN_ISOC }, |
| @@ -437,22 +441,22 @@ static int btusb_recv_intr(struct btusb_data *data, void *buffer, int count) · 278 unmodified lines | ||
| 437 | 441 | break; |
| 438 | 442 | } |
| 439 | 443 | |
| 440 | − bt_cb(skb)->pkt_type = HCI_EVENT_PKT; | |
| 441 | − bt_cb(skb)->expect = HCI_EVENT_HDR_SIZE; | |
| 444 | + hci_skb_pkt_type(skb) = HCI_EVENT_PKT; | |
| 445 | + hci_skb_expect(skb) = HCI_EVENT_HDR_SIZE; | |
| 442 | 446 | } |
| 443 | 447 | |
| 444 | − len = min_t(uint, bt_cb(skb)->expect, count); | |
| 448 | + len = min_t(uint, hci_skb_expect(skb), count); | |
| 445 | 449 | memcpy(skb_put(skb, len), buffer, len); |
| 446 | 450 | |
| 447 | 451 | count -= len; |
| 448 | 452 | buffer += len; |
| 449 | − bt_cb(skb)->expect -= len; | |
| 453 | + hci_skb_expect(skb) -= len; | |
| 450 | 454 | |
| 451 | 455 | if (skb->len == HCI_EVENT_HDR_SIZE) { |
| 452 | 456 | /* Complete event header */ |
| 453 | − bt_cb(skb)->expect = hci_event_hdr(skb)->plen; | |
| 457 | + hci_skb_expect(skb) = hci_event_hdr(skb)->plen; | |
| 454 | 458 | |
| 455 | − if (skb_tailroom(skb) < bt_cb(skb)->expect) { | |
| 459 | + if (skb_tailroom(skb) < hci_skb_expect(skb)) { | |
| 456 | 460 | kfree_skb(skb); |
| 457 | 461 | skb = NULL; |
| 458 | 462 | |
| @@ -461,7 +465,7 @@ static int btusb_recv_intr(struct btusb_data *data, void *buffer, int count) · 2 unmodified lines | ||
| 461 | 465 | } |
| 462 | 466 | } |
| 463 | 467 | |
| 464 | − if (bt_cb(skb)->expect == 0) { | |
| 468 | + if (!hci_skb_expect(skb)) { | |
| 465 | 469 | /* Complete frame */ |
| 466 | 470 | data->recv_event(data->hdev, skb); |
| 467 | 471 | skb = NULL; |
| @@ -492,24 +496,24 @@ static int btusb_recv_bulk(struct btusb_data *data, void *buffer, int count) · 24 unmodified lines | ||
| 492 | 496 | break; |
| 493 | 497 | } |
| 494 | 498 | |
| 495 | − bt_cb(skb)->pkt_type = HCI_ACLDATA_PKT; | |
| 496 | − bt_cb(skb)->expect = HCI_ACL_HDR_SIZE; | |
| 499 | + hci_skb_pkt_type(skb) = HCI_ACLDATA_PKT; | |
| 500 | + hci_skb_expect(skb) = HCI_ACL_HDR_SIZE; | |
| 497 | 501 | } |
| 498 | 502 | |
| 499 | − len = min_t(uint, bt_cb(skb)->expect, count); | |
| 503 | + len = min_t(uint, hci_skb_expect(skb), count); | |
| 500 | 504 | memcpy(skb_put(skb, len), buffer, len); |
| 501 | 505 | |
| 502 | 506 | count -= len; |
| 503 | 507 | buffer += len; |
| 504 | − bt_cb(skb)->expect -= len; | |
| 508 | + hci_skb_expect(skb) -= len; | |
| 505 | 509 | |
| 506 | 510 | if (skb->len == HCI_ACL_HDR_SIZE) { |
| 507 | 511 | __le16 dlen = hci_acl_hdr(skb)->dlen; |
| 508 | 512 | |
| 509 | 513 | /* Complete ACL header */ |
| 510 | − bt_cb(skb)->expect = __le16_to_cpu(dlen); | |
| 514 | + hci_skb_expect(skb) = __le16_to_cpu(dlen); | |
| 511 | 515 | |
| 512 | − if (skb_tailroom(skb) < bt_cb(skb)->expect) { | |
| 516 | + if (skb_tailroom(skb) < hci_skb_expect(skb)) { | |
| 513 | 517 | kfree_skb(skb); |
| 514 | 518 | skb = NULL; |
| 515 | 519 | |
| @@ -518,7 +522,7 @@ static int btusb_recv_bulk(struct btusb_data *data, void *buffer, int count) · 2 unmodified lines | ||
| 518 | 522 | } |
| 519 | 523 | } |
| 520 | 524 | |
| 521 | − if (bt_cb(skb)->expect == 0) { | |
| 525 | + if (!hci_skb_expect(skb)) { | |
| 522 | 526 | /* Complete frame */ |
| 523 | 527 | hci_recv_frame(data->hdev, skb); |
| 524 | 528 | skb = NULL; |
| @@ -549,22 +553,22 @@ static int btusb_recv_isoc(struct btusb_data *data, void *buffer, int count) · 24 unmodified lines | ||
| 549 | 553 | break; |
| 550 | 554 | } |
| 551 | 555 | |
| 552 | − bt_cb(skb)->pkt_type = HCI_SCODATA_PKT; | |
| 553 | − bt_cb(skb)->expect = HCI_SCO_HDR_SIZE; | |
| 556 | + hci_skb_pkt_type(skb) = HCI_SCODATA_PKT; | |
| 557 | + hci_skb_expect(skb) = HCI_SCO_HDR_SIZE; | |
| 554 | 558 | } |
| 555 | 559 | |
| 556 | − len = min_t(uint, bt_cb(skb)->expect, count); | |
| 560 | + len = min_t(uint, hci_skb_expect(skb), count); | |
| 557 | 561 | memcpy(skb_put(skb, len), buffer, len); |
| 558 | 562 | |
| 559 | 563 | count -= len; |
| 560 | 564 | buffer += len; |
| 561 | − bt_cb(skb)->expect -= len; | |
| 565 | + hci_skb_expect(skb) -= len; | |
| 562 | 566 | |
| 563 | 567 | if (skb->len == HCI_SCO_HDR_SIZE) { |
| 564 | 568 | /* Complete SCO header */ |
| 565 | − bt_cb(skb)->expect = hci_sco_hdr(skb)->dlen; | |
| 569 | + hci_skb_expect(skb) = hci_sco_hdr(skb)->dlen; | |
| 566 | 570 | |
| 567 | − if (skb_tailroom(skb) < bt_cb(skb)->expect) { | |
| 571 | + if (skb_tailroom(skb) < hci_skb_expect(skb)) { | |
| 568 | 572 | kfree_skb(skb); |
| 569 | 573 | skb = NULL; |
| 570 | 574 | |
| @@ -573,7 +577,7 @@ static int btusb_recv_isoc(struct btusb_data *data, void *buffer, int count) · 2 unmodified lines | ||
| 573 | 577 | } |
| 574 | 578 | } |
| 575 | 579 | |
| 576 | − if (bt_cb(skb)->expect == 0) { | |
| 580 | + if (!hci_skb_expect(skb)) { | |
| 577 | 581 | /* Complete frame */ |
| 578 | 582 | hci_recv_frame(data->hdev, skb); |
| 579 | 583 | skb = NULL; |
| @@ -1257,7 +1261,7 @@ static int btusb_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 677 unmodified lines | ||
| 1257 | 1261 | |
| 1258 | 1262 | BT_DBG("%s", hdev->name); |
| 1259 | 1263 | |
| 1260 | − switch (bt_cb(skb)->pkt_type) { | |
| 1264 | + switch (hci_skb_pkt_type(skb)) { | |
| 1261 | 1265 | case HCI_COMMAND_PKT: |
| 1262 | 1266 | urb = alloc_ctrl_urb(hdev, skb); |
| 1263 | 1267 | if (IS_ERR(urb)) |
| @@ -1642,13 +1646,8 @@ static int btusb_setup_intel(struct hci_dev *hdev) · 378 unmodified lines | ||
| 1642 | 1646 | struct sk_buff *skb; |
| 1643 | 1647 | const struct firmware *fw; |
| 1644 | 1648 | const u8 *fw_ptr; |
| 1645 | − int disable_patch; | |
| 1646 | − struct intel_version *ver; | |
| 1647 | − | |
| 1648 | − const u8 mfg_enable[] = { 0x01, 0x00 }; | |
| 1649 | − const u8 mfg_disable[] = { 0x00, 0x00 }; | |
| 1650 | − const u8 mfg_reset_deactivate[] = { 0x00, 0x01 }; | |
| 1651 | − const u8 mfg_reset_activate[] = { 0x00, 0x02 }; | |
| 1649 | + int disable_patch, err; | |
| 1650 | + struct intel_version ver; | |
| 1652 | 1651 | |
| 1653 | 1652 | BT_DBG("%s", hdev->name); |
| 1654 | 1653 | |
| @@ -1674,35 +1673,22 @@ static int btusb_setup_intel(struct hci_dev *hdev) · 19 unmodified lines | ||
| 1674 | 1673 | * The returned information are hardware variant and revision plus |
| 1675 | 1674 | * firmware variant, revision and build number. |
| 1676 | 1675 | */ |
| 1677 | − skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_INIT_TIMEOUT); | |
| 1678 | − if (IS_ERR(skb)) { | |
| 1679 | − BT_ERR("%s reading Intel fw version command failed (%ld)", | |
| 1680 | − hdev->name, PTR_ERR(skb)); | |
| 1681 | − return PTR_ERR(skb); | |
| 1682 | − } | |
| 1683 | − | |
| 1684 | − if (skb->len != sizeof(*ver)) { | |
| 1685 | − BT_ERR("%s Intel version event length mismatch", hdev->name); | |
| 1686 | − kfree_skb(skb); | |
| 1687 | − return -EIO; | |
| 1688 | − } | |
| 1689 | − | |
| 1690 | − ver = (struct intel_version *)skb->data; | |
| 1676 | + err = btintel_read_version(hdev, &ver); | |
| 1677 | + if (err) | |
| 1678 | + return err; | |
| 1691 | 1679 | |
| 1692 | 1680 | BT_INFO("%s: read Intel version: %02x%02x%02x%02x%02x%02x%02x%02x%02x", |
| 1693 | − hdev->name, ver->hw_platform, ver->hw_variant, | |
| 1694 | − ver->hw_revision, ver->fw_variant, ver->fw_revision, | |
| 1695 | − ver->fw_build_num, ver->fw_build_ww, ver->fw_build_yy, | |
| 1696 | − ver->fw_patch_num); | |
| 1681 | + hdev->name, ver.hw_platform, ver.hw_variant, ver.hw_revision, | |
| 1682 | + ver.fw_variant, ver.fw_revision, ver.fw_build_num, | |
| 1683 | + ver.fw_build_ww, ver.fw_build_yy, ver.fw_patch_num); | |
| 1697 | 1684 | |
| 1698 | 1685 | /* fw_patch_num indicates the version of patch the device currently |
| 1699 | 1686 | * have. If there is no patch data in the device, it is always 0x00. |
| 1700 | 1687 | * So, if it is other than 0x00, no need to patch the device again. |
| 1701 | 1688 | */ |
| 1702 | − if (ver->fw_patch_num) { | |
| 1689 | + if (ver.fw_patch_num) { | |
| 1703 | 1690 | BT_INFO("%s: Intel device is already patched. patch num: %02x", |
| 1704 | − hdev->name, ver->fw_patch_num); | |
| 1705 | − kfree_skb(skb); | |
| 1691 | + hdev->name, ver.fw_patch_num); | |
| 1706 | 1692 | goto complete; |
| 1707 | 1693 | } |
| 1708 | 1694 | |
| @@ -1712,31 +1698,21 @@ static int btusb_setup_intel(struct hci_dev *hdev) · 3 unmodified lines | ||
| 1712 | 1698 | * If no patch file is found, allow the device to operate without |
| 1713 | 1699 | * a patch. |
| 1714 | 1700 | */ |
| 1715 | − fw = btusb_setup_intel_get_fw(hdev, ver); | |
| 1716 | − if (!fw) { | |
| 1717 | − kfree_skb(skb); | |
| 1701 | + fw = btusb_setup_intel_get_fw(hdev, &ver); | |
| 1702 | + if (!fw) | |
| 1718 | 1703 | goto complete; |
| 1719 | − } | |
| 1720 | 1704 | fw_ptr = fw->data; |
| 1721 | 1705 | |
| 1722 | − kfree_skb(skb); | |
| 1723 | − | |
| 1724 | − /* This Intel specific command enables the manufacturer mode of the | |
| 1725 | − * controller. | |
| 1726 | − * | |
| 1706 | + /* Enable the manufacturer mode of the controller. | |
| 1727 | 1707 | * Only while this mode is enabled, the driver can download the |
| 1728 | 1708 | * firmware patch data and configuration parameters. |
| 1729 | 1709 | */ |
| 1730 | − skb = __hci_cmd_sync(hdev, 0xfc11, 2, mfg_enable, HCI_INIT_TIMEOUT); | |
| 1731 | − if (IS_ERR(skb)) { | |
| 1732 | − BT_ERR("%s entering Intel manufacturer mode failed (%ld)", | |
| 1733 | − hdev->name, PTR_ERR(skb)); | |
| 1710 | + err = btintel_enter_mfg(hdev); | |
| 1711 | + if (err) { | |
| 1734 | 1712 | release_firmware(fw); |
| 1735 | − return PTR_ERR(skb); | |
| 1713 | + return err; | |
| 1736 | 1714 | } |
| 1737 | 1715 | |
| 1738 | − kfree_skb(skb); | |
| 1739 | − | |
| 1740 | 1716 | disable_patch = 1; |
| 1741 | 1717 | |
| 1742 | 1718 | /* The firmware data file consists of list of Intel specific HCI |
| @@ -1776,14 +1752,9 @@ static int btusb_setup_intel(struct hci_dev *hdev) · 33 unmodified lines | ||
| 1776 | 1752 | /* Patching completed successfully and disable the manufacturer mode |
| 1777 | 1753 | * with reset and activate the downloaded firmware patches. |
| 1778 | 1754 | */ |
| 1779 | − skb = __hci_cmd_sync(hdev, 0xfc11, sizeof(mfg_reset_activate), | |
| 1780 | − mfg_reset_activate, HCI_INIT_TIMEOUT); | |
| 1781 | − if (IS_ERR(skb)) { | |
| 1782 | − BT_ERR("%s exiting Intel manufacturer mode failed (%ld)", | |
| 1783 | − hdev->name, PTR_ERR(skb)); | |
| 1784 | − return PTR_ERR(skb); | |
| 1785 | − } | |
| 1786 | − kfree_skb(skb); | |
| 1755 | + err = btintel_exit_mfg(hdev, true, true); | |
| 1756 | + if (err) | |
| 1757 | + return err; | |
| 1787 | 1758 | |
| 1788 | 1759 | BT_INFO("%s: Intel Bluetooth firmware patch completed and activated", |
| 1789 | 1760 | hdev->name); |
| @@ -1792,14 +1763,9 @@ static int btusb_setup_intel(struct hci_dev *hdev) · 2 unmodified lines | ||
| 1792 | 1763 | |
| 1793 | 1764 | exit_mfg_disable: |
| 1794 | 1765 | /* Disable the manufacturer mode without reset */ |
| 1795 | − skb = __hci_cmd_sync(hdev, 0xfc11, sizeof(mfg_disable), mfg_disable, | |
| 1796 | − HCI_INIT_TIMEOUT); | |
| 1797 | − if (IS_ERR(skb)) { | |
| 1798 | − BT_ERR("%s exiting Intel manufacturer mode failed (%ld)", | |
| 1799 | − hdev->name, PTR_ERR(skb)); | |
| 1800 | − return PTR_ERR(skb); | |
| 1801 | − } | |
| 1802 | − kfree_skb(skb); | |
| 1766 | + err = btintel_exit_mfg(hdev, false, false); | |
| 1767 | + if (err) | |
| 1768 | + return err; | |
| 1803 | 1769 | |
| 1804 | 1770 | BT_INFO("%s: Intel Bluetooth firmware patch completed", hdev->name); |
| 1805 | 1771 | |
| @@ -1811,14 +1777,9 @@ exit_mfg_deactivate: · 5 unmodified lines | ||
| 1811 | 1777 | /* Patching failed. Disable the manufacturer mode with reset and |
| 1812 | 1778 | * deactivate the downloaded firmware patches. |
| 1813 | 1779 | */ |
| 1814 | − skb = __hci_cmd_sync(hdev, 0xfc11, sizeof(mfg_reset_deactivate), | |
| 1815 | − mfg_reset_deactivate, HCI_INIT_TIMEOUT); | |
| 1816 | − if (IS_ERR(skb)) { | |
| 1817 | − BT_ERR("%s exiting Intel manufacturer mode failed (%ld)", | |
| 1818 | − hdev->name, PTR_ERR(skb)); | |
| 1819 | − return PTR_ERR(skb); | |
| 1820 | − } | |
| 1821 | − kfree_skb(skb); | |
| 1780 | + err = btintel_exit_mfg(hdev, true, false); | |
| 1781 | + if (err) | |
| 1782 | + return err; | |
| 1822 | 1783 | |
| 1823 | 1784 | BT_INFO("%s: Intel Bluetooth firmware patch completed and deactivated", |
| 1824 | 1785 | hdev->name); |
| @@ -1853,7 +1814,7 @@ static int inject_cmd_complete(struct hci_dev *hdev, __u16 opcode) · 28 unmodified lines | ||
| 1853 | 1814 | |
| 1854 | 1815 | *skb_put(skb, 1) = 0x00; |
| 1855 | 1816 | |
| 1856 | − bt_cb(skb)->pkt_type = HCI_EVENT_PKT; | |
| 1817 | + hci_skb_pkt_type(skb) = HCI_EVENT_PKT; | |
| 1857 | 1818 | |
| 1858 | 1819 | return hci_recv_frame(hdev, skb); |
| 1859 | 1820 | } |
| @@ -1945,7 +1906,7 @@ static int btusb_send_frame_intel(struct hci_dev *hdev, struct sk_buff *skb) · 85 unmodified lines | ||
| 1945 | 1906 | |
| 1946 | 1907 | BT_DBG("%s", hdev->name); |
| 1947 | 1908 | |
| 1948 | − switch (bt_cb(skb)->pkt_type) { | |
| 1909 | + switch (hci_skb_pkt_type(skb)) { | |
| 1949 | 1910 | case HCI_COMMAND_PKT: |
| 1950 | 1911 | if (test_bit(BTUSB_BOOTLOADER, &data->flags)) { |
| 1951 | 1912 | struct hci_command_hdr *cmd = (void *)skb->data; |
| @@ -2005,7 +1966,7 @@ static int btusb_setup_intel_new(struct hci_dev *hdev) · 53 unmodified lines | ||
| 2005 | 1966 | 0x00, 0x08, 0x04, 0x00 }; |
| 2006 | 1967 | struct btusb_data *data = hci_get_drvdata(hdev); |
| 2007 | 1968 | struct sk_buff *skb; |
| 2008 | − struct intel_version *ver; | |
| 1969 | + struct intel_version ver; | |
| 2009 | 1970 | struct intel_boot_params *params; |
| 2010 | 1971 | const struct firmware *fw; |
| 2011 | 1972 | const u8 *fw_ptr; |
| @@ -2023,28 +1984,16 @@ static int btusb_setup_intel_new(struct hci_dev *hdev) · 11 unmodified lines | ||
| 2023 | 1984 | * is in bootloader mode or if it already has operational firmware |
| 2024 | 1985 | * loaded. |
| 2025 | 1986 | */ |
| 2026 | − skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_INIT_TIMEOUT); | |
| 2027 | − if (IS_ERR(skb)) { | |
| 2028 | − BT_ERR("%s: Reading Intel version information failed (%ld)", | |
| 2029 | − hdev->name, PTR_ERR(skb)); | |
| 2030 | − return PTR_ERR(skb); | |
| 2031 | − } | |
| 2032 | − | |
| 2033 | − if (skb->len != sizeof(*ver)) { | |
| 2034 | − BT_ERR("%s: Intel version event size mismatch", hdev->name); | |
| 2035 | − kfree_skb(skb); | |
| 2036 | − return -EILSEQ; | |
| 2037 | − } | |
| 2038 | − | |
| 2039 | − ver = (struct intel_version *)skb->data; | |
| 1987 | + err = btintel_read_version(hdev, &ver); | |
| 1988 | + if (err) | |
| 1989 | + return err; | |
| 2040 | 1990 | |
| 2041 | 1991 | /* The hardware platform number has a fixed value of 0x37 and |
| 2042 | 1992 | * for now only accept this single value. |
| 2043 | 1993 | */ |
| 2044 | − if (ver->hw_platform != 0x37) { | |
| 1994 | + if (ver.hw_platform != 0x37) { | |
| 2045 | 1995 | BT_ERR("%s: Unsupported Intel hardware platform (%u)", |
| 2046 | − hdev->name, ver->hw_platform); | |
| 2047 | − kfree_skb(skb); | |
| 1996 | + hdev->name, ver.hw_platform); | |
| 2048 | 1997 | return -EINVAL; |
| 2049 | 1998 | } |
| 2050 | 1999 | |
| @@ -2053,14 +2002,13 @@ static int btusb_setup_intel_new(struct hci_dev *hdev) · 2 unmodified lines | ||
| 2053 | 2002 | * put in place to ensure correct forward compatibility options |
| 2054 | 2003 | * when newer hardware variants come along. |
| 2055 | 2004 | */ |
| 2056 | − if (ver->hw_variant != 0x0b) { | |
| 2005 | + if (ver.hw_variant != 0x0b) { | |
| 2057 | 2006 | BT_ERR("%s: Unsupported Intel hardware variant (%u)", |
| 2058 | − hdev->name, ver->hw_variant); | |
| 2059 | − kfree_skb(skb); | |
| 2007 | + hdev->name, ver.hw_variant); | |
| 2060 | 2008 | return -EINVAL; |
| 2061 | 2009 | } |
| 2062 | 2010 | |
| 2063 | − btintel_version_info(hdev, ver); | |
| 2011 | + btintel_version_info(hdev, &ver); | |
| 2064 | 2012 | |
| 2065 | 2013 | /* The firmware variant determines if the device is in bootloader |
| 2066 | 2014 | * mode or is running operational firmware. The value 0x06 identifies |
| @@ -2075,8 +2023,7 @@ static int btusb_setup_intel_new(struct hci_dev *hdev) · 8 unmodified lines | ||
| 2075 | 2023 | * It is not possible to use the Secure Boot Parameters in this |
| 2076 | 2024 | * case since that command is only available in bootloader mode. |
| 2077 | 2025 | */ |
| 2078 | − if (ver->fw_variant == 0x23) { | |
| 2079 | − kfree_skb(skb); | |
| 2026 | + if (ver.fw_variant == 0x23) { | |
| 2080 | 2027 | clear_bit(BTUSB_BOOTLOADER, &data->flags); |
| 2081 | 2028 | btintel_check_bdaddr(hdev); |
| 2082 | 2029 | return 0; |
| @@ -2085,15 +2032,12 @@ static int btusb_setup_intel_new(struct hci_dev *hdev) · 2 unmodified lines | ||
| 2085 | 2032 | /* If the device is not in bootloader mode, then the only possible |
| 2086 | 2033 | * choice is to return an error and abort the device initialization. |
| 2087 | 2034 | */ |
| 2088 | − if (ver->fw_variant != 0x06) { | |
| 2035 | + if (ver.fw_variant != 0x06) { | |
| 2089 | 2036 | BT_ERR("%s: Unsupported Intel firmware variant (%u)", |
| 2090 | − hdev->name, ver->fw_variant); | |
| 2091 | − kfree_skb(skb); | |
| 2037 | + hdev->name, ver.fw_variant); | |
| 2092 | 2038 | return -ENODEV; |
| 2093 | 2039 | } |
| 2094 | 2040 | |
| 2095 | − kfree_skb(skb); | |
| 2096 | − | |
| 2097 | 2041 | /* Read the secure boot parameters to identify the operating |
| 2098 | 2042 | * details of the bootloader. |
| 2099 | 2043 | */ |
| @@ -249,10 +249,10 @@ static int ti_st_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 248 unmodified lines | ||
| 249 | 249 | hst = hci_get_drvdata(hdev); |
| 250 | 250 | |
| 251 | 251 | /* Prepend skb with frame type */ |
| 252 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 252 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 253 | 253 | |
| 254 | − BT_DBG("%s: type %d len %d", hdev->name, bt_cb(skb)->pkt_type, | |
| 255 | − skb->len); | |
| 254 | + BT_DBG("%s: type %d len %d", hdev->name, hci_skb_pkt_type(skb), | |
| 255 | + skb->len); | |
| 256 | 256 | |
| 257 | 257 | /* Insert skb to shared transport layer's transmit queue. |
| 258 | 258 | * Freeing skb memory is taken care in shared transport layer, |
| @@ -268,7 +268,7 @@ static int ti_st_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 9 unmodified lines | ||
| 268 | 268 | |
| 269 | 269 | /* ST accepted our skb. So, Go ahead and do rest */ |
| 270 | 270 | hdev->stat.byte_tx += len; |
| 271 | − ti_st_tx_complete(hst, bt_cb(skb)->pkt_type); | |
| 271 | + ti_st_tx_complete(hst, hci_skb_pkt_type(skb)); | |
| 272 | 272 | |
| 273 | 273 | return 0; |
| 274 | 274 | } |
| @@ -239,7 +239,7 @@ static void dtl1_receive(struct dtl1_info *info) · 238 unmodified lines | ||
| 239 | 239 | info->rx_count = nsh->len + (nsh->len & 0x0001); |
| 240 | 240 | break; |
| 241 | 241 | case RECV_WAIT_DATA: |
| 242 | − bt_cb(info->rx_skb)->pkt_type = nsh->type; | |
| 242 | + hci_skb_pkt_type(info->rx_skb) = nsh->type; | |
| 243 | 243 | |
| 244 | 244 | /* remove PAD byte if it exists */ |
| 245 | 245 | if (nsh->len & 0x0001) { |
| @@ -250,7 +250,7 @@ static void dtl1_receive(struct dtl1_info *info) · 4 unmodified lines | ||
| 250 | 250 | /* remove NSH */ |
| 251 | 251 | skb_pull(info->rx_skb, NSHL); |
| 252 | 252 | |
| 253 | − switch (bt_cb(info->rx_skb)->pkt_type) { | |
| 253 | + switch (hci_skb_pkt_type(info->rx_skb)) { | |
| 254 | 254 | case 0x80: |
| 255 | 255 | /* control data for the Nokia Card */ |
| 256 | 256 | dtl1_control(info, info->rx_skb); |
| @@ -259,12 +259,13 @@ static void dtl1_receive(struct dtl1_info *info) · 2 unmodified lines | ||
| 259 | 259 | case 0x83: |
| 260 | 260 | case 0x84: |
| 261 | 261 | /* send frame to the HCI layer */ |
| 262 | − bt_cb(info->rx_skb)->pkt_type &= 0x0f; | |
| 262 | + hci_skb_pkt_type(info->rx_skb) &= 0x0f; | |
| 263 | 263 | hci_recv_frame(info->hdev, info->rx_skb); |
| 264 | 264 | break; |
| 265 | 265 | default: |
| 266 | 266 | /* unknown packet */ |
| 267 | − BT_ERR("Unknown HCI packet with type 0x%02x received", bt_cb(info->rx_skb)->pkt_type); | |
| 267 | + BT_ERR("Unknown HCI packet with type 0x%02x received", | |
| 268 | + hci_skb_pkt_type(info->rx_skb)); | |
| 268 | 269 | kfree_skb(info->rx_skb); |
| 269 | 270 | break; |
| 270 | 271 | } |
| @@ -386,7 +387,7 @@ static int dtl1_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 115 unmodified lines | ||
| 386 | 387 | struct sk_buff *s; |
| 387 | 388 | struct nsh nsh; |
| 388 | 389 | |
| 389 | − switch (bt_cb(skb)->pkt_type) { | |
| 390 | + switch (hci_skb_pkt_type(skb)) { | |
| 390 | 391 | case HCI_COMMAND_PKT: |
| 391 | 392 | hdev->stat.cmd_tx++; |
| 392 | 393 | nsh.type = 0x81; |
| @@ -205,7 +205,7 @@ static int ath_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 204 unmodified lines | ||
| 205 | 205 | { |
| 206 | 206 | struct ath_struct *ath = hu->priv; |
| 207 | 207 | |
| 208 | − if (bt_cb(skb)->pkt_type == HCI_SCODATA_PKT) { | |
| 208 | + if (hci_skb_pkt_type(skb) == HCI_SCODATA_PKT) { | |
| 209 | 209 | kfree_skb(skb); |
| 210 | 210 | return 0; |
| 211 | 211 | } |
| @@ -213,7 +213,7 @@ static int ath_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 1 unmodified line | ||
| 213 | 213 | /* Update power management enable flag with parameters of |
| 214 | 214 | * HCI sleep enable vendor specific HCI command. |
| 215 | 215 | */ |
| 216 | − if (bt_cb(skb)->pkt_type == HCI_COMMAND_PKT) { | |
| 216 | + if (hci_skb_pkt_type(skb) == HCI_COMMAND_PKT) { | |
| 217 | 217 | struct hci_command_hdr *hdr = (void *)skb->data; |
| 218 | 218 | |
| 219 | 219 | if (__le16_to_cpu(hdr->opcode) == HCI_OP_ATH_SLEEP) |
| @@ -223,7 +223,7 @@ static int ath_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 3 unmodified lines | ||
| 223 | 223 | BT_DBG("hu %p skb %p", hu, skb); |
| 224 | 224 | |
| 225 | 225 | /* Prepend skb with frame type */ |
| 226 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 226 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 227 | 227 | |
| 228 | 228 | skb_queue_tail(&ath->txq, skb); |
| 229 | 229 | set_bit(HCI_UART_SENDING, &hu->tx_state); |
| @@ -472,7 +472,7 @@ static int bcm_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 471 unmodified lines | ||
| 472 | 472 | bt_dev_dbg(hu->hdev, "hu %p skb %p", hu, skb); |
| 473 | 473 | |
| 474 | 474 | /* Prepend skb with frame type */ |
| 475 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 475 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 476 | 476 | skb_queue_tail(&bcm->txq, skb); |
| 477 | 477 | |
| 478 | 478 | return 0; |
| @@ -814,8 +814,16 @@ static const struct hci_uart_proto bcm_proto = { · 335 unmodified lines | ||
| 814 | 814 | |
| 815 | 815 | #ifdef CONFIG_ACPI |
| 816 | 816 | static const struct acpi_device_id bcm_acpi_match[] = { |
| 817 | + { "BCM2E1A", 0 }, | |
| 817 | 818 | { "BCM2E39", 0 }, |
| 819 | + { "BCM2E3A", 0 }, | |
| 820 | + { "BCM2E3D", 0 }, | |
| 821 | + { "BCM2E3F", 0 }, | |
| 822 | + { "BCM2E40", 0 }, | |
| 823 | + { "BCM2E64", 0 }, | |
| 824 | + { "BCM2E65", 0 }, | |
| 818 | 825 | { "BCM2E67", 0 }, |
| 826 | + { "BCM2E7B", 0 }, | |
| 819 | 827 | { }, |
| 820 | 828 | }; |
| 821 | 829 | MODULE_DEVICE_TABLE(acpi, bcm_acpi_match); |
| @@ -155,7 +155,7 @@ static int bcsp_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 154 unmodified lines | ||
| 155 | 155 | return 0; |
| 156 | 156 | } |
| 157 | 157 | |
| 158 | − switch (bt_cb(skb)->pkt_type) { | |
| 158 | + switch (hci_skb_pkt_type(skb)) { | |
| 159 | 159 | case HCI_ACLDATA_PKT: |
| 160 | 160 | case HCI_COMMAND_PKT: |
| 161 | 161 | skb_queue_tail(&bcsp->rel, skb); |
| @@ -231,7 +231,7 @@ static struct sk_buff *bcsp_prepare_pkt(struct bcsp_struct *bcsp, u8 *data, · 69 unmodified lines | ||
| 231 | 231 | if (!nskb) |
| 232 | 232 | return NULL; |
| 233 | 233 | |
| 234 | − bt_cb(nskb)->pkt_type = pkt_type; | |
| 234 | + hci_skb_pkt_type(nskb) = pkt_type; | |
| 235 | 235 | |
| 236 | 236 | bcsp_slip_msgdelim(nskb); |
| 237 | 237 | |
| @@ -291,7 +291,10 @@ static struct sk_buff *bcsp_dequeue(struct hci_uart *hu) · 53 unmodified lines | ||
| 291 | 291 | |
| 292 | 292 | skb = skb_dequeue(&bcsp->unrel); |
| 293 | 293 | if (skb != NULL) { |
| 294 | − struct sk_buff *nskb = bcsp_prepare_pkt(bcsp, skb->data, skb->len, bt_cb(skb)->pkt_type); | |
| 294 | + struct sk_buff *nskb; | |
| 295 | + | |
| 296 | + nskb = bcsp_prepare_pkt(bcsp, skb->data, skb->len, | |
| 297 | + hci_skb_pkt_type(skb)); | |
| 295 | 298 | if (nskb) { |
| 296 | 299 | kfree_skb(skb); |
| 297 | 300 | return nskb; |
| @@ -310,8 +313,10 @@ static struct sk_buff *bcsp_dequeue(struct hci_uart *hu) · 12 unmodified lines | ||
| 310 | 313 | if (bcsp->unack.qlen < BCSP_TXWINSIZE) { |
| 311 | 314 | skb = skb_dequeue(&bcsp->rel); |
| 312 | 315 | if (skb != NULL) { |
| 313 | − struct sk_buff *nskb = bcsp_prepare_pkt(bcsp, skb->data, skb->len, | |
| 314 | − bt_cb(skb)->pkt_type); | |
| 316 | + struct sk_buff *nskb; | |
| 317 | + | |
| 318 | + nskb = bcsp_prepare_pkt(bcsp, skb->data, skb->len, | |
| 319 | + hci_skb_pkt_type(skb)); | |
| 315 | 320 | if (nskb) { |
| 316 | 321 | __skb_queue_tail(&bcsp->unack, skb); |
| 317 | 322 | mod_timer(&bcsp->tbcsp, jiffies + HZ / 4); |
| @@ -412,7 +417,7 @@ static void bcsp_handle_le_pkt(struct hci_uart *hu) · 94 unmodified lines | ||
| 412 | 417 | if (!nskb) |
| 413 | 418 | return; |
| 414 | 419 | memcpy(skb_put(nskb, 4), conf_rsp_pkt, 4); |
| 415 | − bt_cb(nskb)->pkt_type = BCSP_LE_PKT; | |
| 420 | + hci_skb_pkt_type(nskb) = BCSP_LE_PKT; | |
| 416 | 421 | |
| 417 | 422 | skb_queue_head(&bcsp->unrel, nskb); |
| 418 | 423 | hci_uart_tx_wakeup(hu); |
| @@ -494,14 +499,14 @@ static void bcsp_complete_rx_pkt(struct hci_uart *hu) · 75 unmodified lines | ||
| 494 | 499 | bcsp_pkt_cull(bcsp); |
| 495 | 500 | if ((bcsp->rx_skb->data[1] & 0x0f) == 6 && |
| 496 | 501 | bcsp->rx_skb->data[0] & 0x80) { |
| 497 | − bt_cb(bcsp->rx_skb)->pkt_type = HCI_ACLDATA_PKT; | |
| 502 | + hci_skb_pkt_type(bcsp->rx_skb) = HCI_ACLDATA_PKT; | |
| 498 | 503 | pass_up = 1; |
| 499 | 504 | } else if ((bcsp->rx_skb->data[1] & 0x0f) == 5 && |
| 500 | 505 | bcsp->rx_skb->data[0] & 0x80) { |
| 501 | − bt_cb(bcsp->rx_skb)->pkt_type = HCI_EVENT_PKT; | |
| 506 | + hci_skb_pkt_type(bcsp->rx_skb) = HCI_EVENT_PKT; | |
| 502 | 507 | pass_up = 1; |
| 503 | 508 | } else if ((bcsp->rx_skb->data[1] & 0x0f) == 7) { |
| 504 | − bt_cb(bcsp->rx_skb)->pkt_type = HCI_SCODATA_PKT; | |
| 509 | + hci_skb_pkt_type(bcsp->rx_skb) = HCI_SCODATA_PKT; | |
| 505 | 510 | pass_up = 1; |
| 506 | 511 | } else if ((bcsp->rx_skb->data[1] & 0x0f) == 1 && |
| 507 | 512 | !(bcsp->rx_skb->data[0] & 0x80)) { |
| @@ -523,7 +528,7 @@ static void bcsp_complete_rx_pkt(struct hci_uart *hu) · 15 unmodified lines | ||
| 523 | 528 | hdr.evt = 0xff; |
| 524 | 529 | hdr.plen = bcsp->rx_skb->len; |
| 525 | 530 | memcpy(skb_push(bcsp->rx_skb, HCI_EVENT_HDR_SIZE), &hdr, HCI_EVENT_HDR_SIZE); |
| 526 | − bt_cb(bcsp->rx_skb)->pkt_type = HCI_EVENT_PKT; | |
| 531 | + hci_skb_pkt_type(bcsp->rx_skb) = HCI_EVENT_PKT; | |
| 527 | 532 | |
| 528 | 533 | hci_recv_frame(hu->hdev, bcsp->rx_skb); |
| 529 | 534 | } else { |
| @@ -108,7 +108,7 @@ static int h4_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 107 unmodified lines | ||
| 108 | 108 | BT_DBG("hu %p skb %p", hu, skb); |
| 109 | 109 | |
| 110 | 110 | /* Prepend skb with frame type */ |
| 111 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 111 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 112 | 112 | skb_queue_tail(&h4->txq, skb); |
| 113 | 113 | |
| 114 | 114 | return 0; |
| @@ -184,8 +184,8 @@ struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb, · 69 unmodified lines | ||
| 184 | 184 | if (!skb) |
| 185 | 185 | return ERR_PTR(-ENOMEM); |
| 186 | 186 | |
| 187 | − bt_cb(skb)->pkt_type = (&pkts[i])->type; | |
| 188 | − bt_cb(skb)->expect = (&pkts[i])->hlen; | |
| 187 | + hci_skb_pkt_type(skb) = (&pkts[i])->type; | |
| 188 | + hci_skb_expect(skb) = (&pkts[i])->hlen; | |
| 189 | 189 | break; |
| 190 | 190 | } |
| 191 | 191 | |
| @@ -197,18 +197,18 @@ struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb, · 5 unmodified lines | ||
| 197 | 197 | buffer += 1; |
| 198 | 198 | } |
| 199 | 199 | |
| 200 | − len = min_t(uint, bt_cb(skb)->expect - skb->len, count); | |
| 200 | + len = min_t(uint, hci_skb_expect(skb) - skb->len, count); | |
| 201 | 201 | memcpy(skb_put(skb, len), buffer, len); |
| 202 | 202 | |
| 203 | 203 | count -= len; |
| 204 | 204 | buffer += len; |
| 205 | 205 | |
| 206 | 206 | /* Check for partial packet */ |
| 207 | − if (skb->len < bt_cb(skb)->expect) | |
| 207 | + if (skb->len < hci_skb_expect(skb)) | |
| 208 | 208 | continue; |
| 209 | 209 | |
| 210 | 210 | for (i = 0; i < pkts_count; i++) { |
| 211 | − if (bt_cb(skb)->pkt_type == (&pkts[i])->type) | |
| 211 | + if (hci_skb_pkt_type(skb) == (&pkts[i])->type) | |
| 212 | 212 | break; |
| 213 | 213 | } |
| 214 | 214 | |
| @@ -228,7 +228,7 @@ struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb, · 13 unmodified lines | ||
| 228 | 228 | case 1: |
| 229 | 229 | /* Single octet variable length */ |
| 230 | 230 | dlen = skb->data[(&pkts[i])->loff]; |
| 231 | − bt_cb(skb)->expect += dlen; | |
| 231 | + hci_skb_expect(skb) += dlen; | |
| 232 | 232 | |
| 233 | 233 | if (skb_tailroom(skb) < dlen) { |
| 234 | 234 | kfree_skb(skb); |
| @@ -239,7 +239,7 @@ struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb, · 4 unmodified lines | ||
| 239 | 239 | /* Double octet variable length */ |
| 240 | 240 | dlen = get_unaligned_le16(skb->data + |
| 241 | 241 | (&pkts[i])->loff); |
| 242 | − bt_cb(skb)->expect += dlen; | |
| 242 | + hci_skb_expect(skb) += dlen; | |
| 243 | 243 | |
| 244 | 244 | if (skb_tailroom(skb) < dlen) { |
| 245 | 245 | kfree_skb(skb); |
| @@ -51,7 +51,7 @@ · 50 unmodified lines | ||
| 51 | 51 | #define H5_HDR_CRC(hdr) (((hdr)[0] >> 6) & 0x01) |
| 52 | 52 | #define H5_HDR_RELIABLE(hdr) (((hdr)[0] >> 7) & 0x01) |
| 53 | 53 | #define H5_HDR_PKT_TYPE(hdr) ((hdr)[1] & 0x0f) |
| 54 | −#define H5_HDR_LEN(hdr) ((((hdr)[1] >> 4) & 0xff) + ((hdr)[2] << 4)) | |
| 54 | +#define H5_HDR_LEN(hdr) ((((hdr)[1] >> 4) & 0x0f) + ((hdr)[2] << 4)) | |
| 55 | 55 | |
| 56 | 56 | #define SLIP_DELIMITER 0xc0 |
| 57 | 57 | #define SLIP_ESC 0xdb |
| @@ -107,7 +107,7 @@ static void h5_link_control(struct hci_uart *hu, const void *data, size_t len) · 49 unmodified lines | ||
| 107 | 107 | if (!nskb) |
| 108 | 108 | return; |
| 109 | 109 | |
| 110 | − bt_cb(nskb)->pkt_type = HCI_3WIRE_LINK_PKT; | |
| 110 | + hci_skb_pkt_type(nskb) = HCI_3WIRE_LINK_PKT; | |
| 111 | 111 | |
| 112 | 112 | memcpy(skb_put(nskb, len), data, len); |
| 113 | 113 | |
| @@ -116,18 +116,14 @@ static void h5_link_control(struct hci_uart *hu, const void *data, size_t len) · 2 unmodified lines | ||
| 116 | 116 | |
| 117 | 117 | static u8 h5_cfg_field(struct h5 *h5) |
| 118 | 118 | { |
| 119 | − u8 field = 0; | |
| 120 | − | |
| 121 | 119 | /* Sliding window size (first 3 bits) */ |
| 122 | − field |= (h5->tx_win & 7); | |
| 123 | − | |
| 124 | − return field; | |
| 120 | + return h5->tx_win & 0x07; | |
| 125 | 121 | } |
| 126 | 122 | |
| 127 | 123 | static void h5_timed_event(unsigned long arg) |
| 128 | 124 | { |
| 129 | 125 | const unsigned char sync_req[] = { 0x01, 0x7e }; |
| 130 | − unsigned char conf_req[] = { 0x03, 0xfc, 0x01 }; | |
| 126 | + unsigned char conf_req[3] = { 0x03, 0xfc }; | |
| 131 | 127 | struct hci_uart *hu = (struct hci_uart *)arg; |
| 132 | 128 | struct h5 *h5 = hu->priv; |
| 133 | 129 | struct sk_buff *skb; |
| @@ -285,7 +281,7 @@ static void h5_handle_internal_rx(struct hci_uart *hu) · 151 unmodified lines | ||
| 285 | 281 | struct h5 *h5 = hu->priv; |
| 286 | 282 | const unsigned char sync_req[] = { 0x01, 0x7e }; |
| 287 | 283 | const unsigned char sync_rsp[] = { 0x02, 0x7d }; |
| 288 | − unsigned char conf_req[] = { 0x03, 0xfc, 0x01 }; | |
| 284 | + unsigned char conf_req[3] = { 0x03, 0xfc }; | |
| 289 | 285 | const unsigned char conf_rsp[] = { 0x04, 0x7b }; |
| 290 | 286 | const unsigned char wakeup_req[] = { 0x05, 0xfa }; |
| 291 | 287 | const unsigned char woken_req[] = { 0x06, 0xf9 }; |
| @@ -317,7 +313,7 @@ static void h5_handle_internal_rx(struct hci_uart *hu) · 25 unmodified lines | ||
| 317 | 313 | h5_link_control(hu, conf_req, 3); |
| 318 | 314 | } else if (memcmp(data, conf_rsp, 2) == 0) { |
| 319 | 315 | if (H5_HDR_LEN(hdr) > 2) |
| 320 | − h5->tx_win = (data[2] & 7); | |
| 316 | + h5->tx_win = (data[2] & 0x07); | |
| 321 | 317 | BT_DBG("Three-wire init complete. tx_win %u", h5->tx_win); |
| 322 | 318 | h5->state = H5_ACTIVE; |
| 323 | 319 | hci_uart_init_ready(hu); |
| @@ -360,7 +356,7 @@ static void h5_complete_rx_pkt(struct hci_uart *hu) · 36 unmodified lines | ||
| 360 | 356 | case HCI_EVENT_PKT: |
| 361 | 357 | case HCI_ACLDATA_PKT: |
| 362 | 358 | case HCI_SCODATA_PKT: |
| 363 | − bt_cb(h5->rx_skb)->pkt_type = H5_HDR_PKT_TYPE(hdr); | |
| 359 | + hci_skb_pkt_type(h5->rx_skb) = H5_HDR_PKT_TYPE(hdr); | |
| 364 | 360 | |
| 365 | 361 | /* Remove Three-wire header */ |
| 366 | 362 | skb_pull(h5->rx_skb, 4); |
| @@ -562,7 +558,7 @@ static int h5_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 195 unmodified lines | ||
| 562 | 558 | return 0; |
| 563 | 559 | } |
| 564 | 560 | |
| 565 | − switch (bt_cb(skb)->pkt_type) { | |
| 561 | + switch (hci_skb_pkt_type(skb)) { | |
| 566 | 562 | case HCI_ACLDATA_PKT: |
| 567 | 563 | case HCI_COMMAND_PKT: |
| 568 | 564 | skb_queue_tail(&h5->rel, skb); |
| @@ -573,7 +569,7 @@ static int h5_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 4 unmodified lines | ||
| 573 | 569 | break; |
| 574 | 570 | |
| 575 | 571 | default: |
| 576 | − BT_ERR("Unknown packet type %u", bt_cb(skb)->pkt_type); | |
| 572 | + BT_ERR("Unknown packet type %u", hci_skb_pkt_type(skb)); | |
| 577 | 573 | kfree_skb(skb); |
| 578 | 574 | break; |
| 579 | 575 | } |
| @@ -642,7 +638,7 @@ static struct sk_buff *h5_prepare_pkt(struct hci_uart *hu, u8 pkt_type, · 62 unmodified lines | ||
| 642 | 638 | if (!nskb) |
| 643 | 639 | return NULL; |
| 644 | 640 | |
| 645 | − bt_cb(nskb)->pkt_type = pkt_type; | |
| 641 | + hci_skb_pkt_type(nskb) = pkt_type; | |
| 646 | 642 | |
| 647 | 643 | h5_slip_delim(nskb); |
| 648 | 644 | |
| @@ -697,7 +693,7 @@ static struct sk_buff *h5_dequeue(struct hci_uart *hu) · 48 unmodified lines | ||
| 697 | 693 | |
| 698 | 694 | skb = skb_dequeue(&h5->unrel); |
| 699 | 695 | if (skb) { |
| 700 | − nskb = h5_prepare_pkt(hu, bt_cb(skb)->pkt_type, | |
| 696 | + nskb = h5_prepare_pkt(hu, hci_skb_pkt_type(skb), | |
| 701 | 697 | skb->data, skb->len); |
| 702 | 698 | if (nskb) { |
| 703 | 699 | kfree_skb(skb); |
| @@ -715,7 +711,7 @@ static struct sk_buff *h5_dequeue(struct hci_uart *hu) · 11 unmodified lines | ||
| 715 | 711 | |
| 716 | 712 | skb = skb_dequeue(&h5->rel); |
| 717 | 713 | if (skb) { |
| 718 | − nskb = h5_prepare_pkt(hu, bt_cb(skb)->pkt_type, | |
| 714 | + nskb = h5_prepare_pkt(hu, hci_skb_pkt_type(skb), | |
| 719 | 715 | skb->data, skb->len); |
| 720 | 716 | if (nskb) { |
| 721 | 717 | __skb_queue_tail(&h5->unack, skb); |
| @@ -186,7 +186,7 @@ static int intel_lpm_suspend(struct hci_uart *hu) · 185 unmodified lines | ||
| 186 | 186 | } |
| 187 | 187 | |
| 188 | 188 | memcpy(skb_put(skb, sizeof(suspend)), suspend, sizeof(suspend)); |
| 189 | − bt_cb(skb)->pkt_type = HCI_LPM_PKT; | |
| 189 | + hci_skb_pkt_type(skb) = HCI_LPM_PKT; | |
| 190 | 190 | |
| 191 | 191 | set_bit(STATE_LPM_TRANSACTION, &intel->flags); |
| 192 | 192 | |
| @@ -230,7 +230,7 @@ static int intel_lpm_resume(struct hci_uart *hu) · 37 unmodified lines | ||
| 230 | 230 | return -ENOMEM; |
| 231 | 231 | } |
| 232 | 232 | |
| 233 | − bt_cb(skb)->pkt_type = HCI_LPM_WAKE_PKT; | |
| 233 | + hci_skb_pkt_type(skb) = HCI_LPM_WAKE_PKT; | |
| 234 | 234 | |
| 235 | 235 | set_bit(STATE_LPM_TRANSACTION, &intel->flags); |
| 236 | 236 | |
| @@ -272,7 +272,7 @@ static int intel_lpm_host_wake(struct hci_uart *hu) · 35 unmodified lines | ||
| 272 | 272 | |
| 273 | 273 | memcpy(skb_put(skb, sizeof(lpm_resume_ack)), lpm_resume_ack, |
| 274 | 274 | sizeof(lpm_resume_ack)); |
| 275 | − bt_cb(skb)->pkt_type = HCI_LPM_PKT; | |
| 275 | + hci_skb_pkt_type(skb) = HCI_LPM_PKT; | |
| 276 | 276 | |
| 277 | 277 | /* LPM flow is a priority, enqueue packet at list head */ |
| 278 | 278 | skb_queue_head(&intel->txq, skb); |
| @@ -467,7 +467,7 @@ static int inject_cmd_complete(struct hci_dev *hdev, __u16 opcode) · 188 unmodified lines | ||
| 467 | 467 | |
| 468 | 468 | *skb_put(skb, 1) = 0x00; |
| 469 | 469 | |
| 470 | − bt_cb(skb)->pkt_type = HCI_EVENT_PKT; | |
| 470 | + hci_skb_pkt_type(skb) = HCI_EVENT_PKT; | |
| 471 | 471 | |
| 472 | 472 | return hci_recv_frame(hdev, skb); |
| 473 | 473 | } |
| @@ -502,7 +502,7 @@ static int intel_set_baudrate(struct hci_uart *hu, unsigned int speed) · 28 unmodified lines | ||
| 502 | 502 | /* Device will not accept speed change if Intel version has not been |
| 503 | 503 | * previously requested. |
| 504 | 504 | */ |
| 505 | − skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_INIT_TIMEOUT); | |
| 505 | + skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT); | |
| 506 | 506 | if (IS_ERR(skb)) { |
| 507 | 507 | bt_dev_err(hdev, "Reading Intel version information failed (%ld)", |
| 508 | 508 | PTR_ERR(skb)); |
| @@ -517,7 +517,7 @@ static int intel_set_baudrate(struct hci_uart *hu, unsigned int speed) · 8 unmodified lines | ||
| 517 | 517 | } |
| 518 | 518 | |
| 519 | 519 | memcpy(skb_put(skb, sizeof(speed_cmd)), speed_cmd, sizeof(speed_cmd)); |
| 520 | − bt_cb(skb)->pkt_type = HCI_COMMAND_PKT; | |
| 520 | + hci_skb_pkt_type(skb) = HCI_COMMAND_PKT; | |
| 521 | 521 | |
| 522 | 522 | hci_uart_set_flow_control(hu, true); |
| 523 | 523 | |
| @@ -542,7 +542,7 @@ static int intel_setup(struct hci_uart *hu) · 18 unmodified lines | ||
| 542 | 542 | struct intel_device *idev = NULL; |
| 543 | 543 | struct hci_dev *hdev = hu->hdev; |
| 544 | 544 | struct sk_buff *skb; |
| 545 | − struct intel_version *ver; | |
| 545 | + struct intel_version ver; | |
| 546 | 546 | struct intel_boot_params *params; |
| 547 | 547 | struct list_head *p; |
| 548 | 548 | const struct firmware *fw; |
| @@ -590,35 +590,16 @@ static int intel_setup(struct hci_uart *hu) · 41 unmodified lines | ||
| 590 | 590 | * is in bootloader mode or if it already has operational firmware |
| 591 | 591 | * loaded. |
| 592 | 592 | */ |
| 593 | − skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_INIT_TIMEOUT); | |
| 594 | − if (IS_ERR(skb)) { | |
| 595 | − bt_dev_err(hdev, "Reading Intel version information failed (%ld)", | |
| 596 | − PTR_ERR(skb)); | |
| 597 | − return PTR_ERR(skb); | |
| 598 | − } | |
| 599 | − | |
| 600 | − if (skb->len != sizeof(*ver)) { | |
| 601 | − bt_dev_err(hdev, "Intel version event size mismatch"); | |
| 602 | − kfree_skb(skb); | |
| 603 | − return -EILSEQ; | |
| 604 | − } | |
| 605 | − | |
| 606 | − ver = (struct intel_version *)skb->data; | |
| 607 | − if (ver->status) { | |
| 608 | − bt_dev_err(hdev, "Intel version command failure (%02x)", | |
| 609 | − ver->status); | |
| 610 | − err = -bt_to_errno(ver->status); | |
| 611 | − kfree_skb(skb); | |
| 593 | + err = btintel_read_version(hdev, &ver); | |
| 594 | + if (err) | |
| 612 | 595 | return err; |
| 613 | − } | |
| 614 | 596 | |
| 615 | 597 | /* The hardware platform number has a fixed value of 0x37 and |
| 616 | 598 | * for now only accept this single value. |
| 617 | 599 | */ |
| 618 | − if (ver->hw_platform != 0x37) { | |
| 600 | + if (ver.hw_platform != 0x37) { | |
| 619 | 601 | bt_dev_err(hdev, "Unsupported Intel hardware platform (%u)", |
| 620 | − ver->hw_platform); | |
| 621 | − kfree_skb(skb); | |
| 602 | + ver.hw_platform); | |
| 622 | 603 | return -EINVAL; |
| 623 | 604 | } |
| 624 | 605 | |
| @@ -627,14 +608,13 @@ static int intel_setup(struct hci_uart *hu) · 2 unmodified lines | ||
| 627 | 608 | * put in place to ensure correct forward compatibility options |
| 628 | 609 | * when newer hardware variants come along. |
| 629 | 610 | */ |
| 630 | − if (ver->hw_variant != 0x0b) { | |
| 611 | + if (ver.hw_variant != 0x0b) { | |
| 631 | 612 | bt_dev_err(hdev, "Unsupported Intel hardware variant (%u)", |
| 632 | − ver->hw_variant); | |
| 633 | − kfree_skb(skb); | |
| 613 | + ver.hw_variant); | |
| 634 | 614 | return -EINVAL; |
| 635 | 615 | } |
| 636 | 616 | |
| 637 | − btintel_version_info(hdev, ver); | |
| 617 | + btintel_version_info(hdev, &ver); | |
| 638 | 618 | |
| 639 | 619 | /* The firmware variant determines if the device is in bootloader |
| 640 | 620 | * mode or is running operational firmware. The value 0x06 identifies |
| @@ -649,8 +629,7 @@ static int intel_setup(struct hci_uart *hu) · 8 unmodified lines | ||
| 649 | 629 | * It is not possible to use the Secure Boot Parameters in this |
| 650 | 630 | * case since that command is only available in bootloader mode. |
| 651 | 631 | */ |
| 652 | − if (ver->fw_variant == 0x23) { | |
| 653 | − kfree_skb(skb); | |
| 632 | + if (ver.fw_variant == 0x23) { | |
| 654 | 633 | clear_bit(STATE_BOOTLOADER, &intel->flags); |
| 655 | 634 | btintel_check_bdaddr(hdev); |
| 656 | 635 | return 0; |
| @@ -659,19 +638,16 @@ static int intel_setup(struct hci_uart *hu) · 2 unmodified lines | ||
| 659 | 638 | /* If the device is not in bootloader mode, then the only possible |
| 660 | 639 | * choice is to return an error and abort the device initialization. |
| 661 | 640 | */ |
| 662 | − if (ver->fw_variant != 0x06) { | |
| 641 | + if (ver.fw_variant != 0x06) { | |
| 663 | 642 | bt_dev_err(hdev, "Unsupported Intel firmware variant (%u)", |
| 664 | − ver->fw_variant); | |
| 665 | − kfree_skb(skb); | |
| 643 | + ver.fw_variant); | |
| 666 | 644 | return -ENODEV; |
| 667 | 645 | } |
| 668 | 646 | |
| 669 | − kfree_skb(skb); | |
| 670 | − | |
| 671 | 647 | /* Read the secure boot parameters to identify the operating |
| 672 | 648 | * details of the bootloader. |
| 673 | 649 | */ |
| 674 | − skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_INIT_TIMEOUT); | |
| 650 | + skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_CMD_TIMEOUT); | |
| 675 | 651 | if (IS_ERR(skb)) { |
| 676 | 652 | bt_dev_err(hdev, "Reading Intel boot parameters failed (%ld)", |
| 677 | 653 | PTR_ERR(skb)); |
| @@ -881,7 +857,7 @@ done: · 203 unmodified lines | ||
| 881 | 857 | set_bit(STATE_BOOTING, &intel->flags); |
| 882 | 858 | |
| 883 | 859 | skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(reset_param), reset_param, |
| 884 | − HCI_INIT_TIMEOUT); | |
| 860 | + HCI_CMD_TIMEOUT); | |
| 885 | 861 | if (IS_ERR(skb)) |
| 886 | 862 | return PTR_ERR(skb); |
| 887 | 863 | |
| @@ -1126,7 +1102,7 @@ static struct sk_buff *intel_dequeue(struct hci_uart *hu) · 238 unmodified lines | ||
| 1126 | 1102 | return skb; |
| 1127 | 1103 | |
| 1128 | 1104 | if (test_bit(STATE_BOOTLOADER, &intel->flags) && |
| 1129 | − (bt_cb(skb)->pkt_type == HCI_COMMAND_PKT)) { | |
| 1105 | + (hci_skb_pkt_type(skb) == HCI_COMMAND_PKT)) { | |
| 1130 | 1106 | struct hci_command_hdr *cmd = (void *)skb->data; |
| 1131 | 1107 | __u16 opcode = le16_to_cpu(cmd->opcode); |
| 1132 | 1108 | |
| @@ -1140,7 +1116,7 @@ static struct sk_buff *intel_dequeue(struct hci_uart *hu) · 7 unmodified lines | ||
| 1140 | 1116 | } |
| 1141 | 1117 | |
| 1142 | 1118 | /* Prepend skb with frame type */ |
| 1143 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 1119 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 1144 | 1120 | |
| 1145 | 1121 | return skb; |
| 1146 | 1122 | } |
| @@ -162,7 +162,7 @@ restart: · 161 unmodified lines | ||
| 162 | 162 | break; |
| 163 | 163 | } |
| 164 | 164 | |
| 165 | − hci_uart_tx_complete(hu, bt_cb(skb)->pkt_type); | |
| 165 | + hci_uart_tx_complete(hu, hci_skb_pkt_type(skb)); | |
| 166 | 166 | kfree_skb(skb); |
| 167 | 167 | } |
| 168 | 168 | |
| @@ -248,7 +248,8 @@ static int hci_uart_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 79 unmodified lines | ||
| 248 | 248 | { |
| 249 | 249 | struct hci_uart *hu = hci_get_drvdata(hdev); |
| 250 | 250 | |
| 251 | − BT_DBG("%s: type %d len %d", hdev->name, bt_cb(skb)->pkt_type, skb->len); | |
| 251 | + BT_DBG("%s: type %d len %d", hdev->name, hci_skb_pkt_type(skb), | |
| 252 | + skb->len); | |
| 252 | 253 | |
| 253 | 254 | hu->proto->enqueue(hu, skb); |
| 254 | 255 | |
| @@ -461,13 +462,7 @@ static int hci_uart_tty_open(struct tty_struct *tty) · 206 unmodified lines | ||
| 461 | 462 | INIT_WORK(&hu->init_ready, hci_uart_init_work); |
| 462 | 463 | INIT_WORK(&hu->write_work, hci_uart_write_work); |
| 463 | 464 | |
| 464 | − /* Flush any pending characters in the driver and line discipline. */ | |
| 465 | − | |
| 466 | − /* FIXME: why is this needed. Note don't use ldisc_ref here as the | |
| 467 | − open path is before the ldisc is referencable */ | |
| 468 | − | |
| 469 | − if (tty->ldisc->ops->flush_buffer) | |
| 470 | − tty->ldisc->ops->flush_buffer(tty); | |
| 465 | + /* Flush any pending characters in the driver */ | |
| 471 | 466 | tty_driver_flush_buffer(tty); |
| 472 | 467 | |
| 473 | 468 | return 0; |
| @@ -307,7 +307,7 @@ static int ll_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 306 unmodified lines | ||
| 307 | 307 | BT_DBG("hu %p skb %p", hu, skb); |
| 308 | 308 | |
| 309 | 309 | /* Prepend skb with frame type */ |
| 310 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 310 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 311 | 311 | |
| 312 | 312 | /* lock hcill state */ |
| 313 | 313 | spin_lock_irqsave(&ll->hcill_lock, flags); |
| @@ -493,7 +493,7 @@ static int ll_recv(struct hci_uart *hu, const void *data, int count) · 179 unmodified lines | ||
| 493 | 493 | return -ENOMEM; |
| 494 | 494 | } |
| 495 | 495 | |
| 496 | − bt_cb(ll->rx_skb)->pkt_type = type; | |
| 496 | + hci_skb_pkt_type(ll->rx_skb) = type; | |
| 497 | 497 | } |
| 498 | 498 | |
| 499 | 499 | return count; |
| @@ -678,7 +678,7 @@ static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb) · 677 unmodified lines | ||
| 678 | 678 | qca->tx_ibs_state); |
| 679 | 679 | |
| 680 | 680 | /* Prepend skb with frame type */ |
| 681 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 681 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 682 | 682 | |
| 683 | 683 | /* Don't go to sleep in middle of patch download or |
| 684 | 684 | * Out-Of-Band(GPIOs control) sleep is selected. |
| @@ -873,7 +873,7 @@ static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate) · 188 unmodified lines | ||
| 873 | 873 | |
| 874 | 874 | /* Assign commands to change baudrate and packet type. */ |
| 875 | 875 | memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd)); |
| 876 | − bt_cb(skb)->pkt_type = HCI_COMMAND_PKT; | |
| 876 | + hci_skb_pkt_type(skb) = HCI_COMMAND_PKT; | |
| 877 | 877 | |
| 878 | 878 | skb_queue_tail(&qca->txq, skb); |
| 879 | 879 | hci_uart_tx_wakeup(hu); |
| @@ -80,7 +80,7 @@ static int vhci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 79 unmodified lines | ||
| 80 | 80 | { |
| 81 | 81 | struct vhci_data *data = hci_get_drvdata(hdev); |
| 82 | 82 | |
| 83 | − memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); | |
| 83 | + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); | |
| 84 | 84 | skb_queue_tail(&data->readq, skb); |
| 85 | 85 | |
| 86 | 86 | wake_up_interruptible(&data->read_wait); |
| @@ -140,7 +140,7 @@ static int vhci_create_device(struct vhci_data *data, __u8 opcode) · 53 unmodified lines | ||
| 140 | 140 | return -EBUSY; |
| 141 | 141 | } |
| 142 | 142 | |
| 143 | − bt_cb(skb)->pkt_type = HCI_VENDOR_PKT; | |
| 143 | + hci_skb_pkt_type(skb) = HCI_VENDOR_PKT; | |
| 144 | 144 | |
| 145 | 145 | *skb_put(skb, 1) = 0xff; |
| 146 | 146 | *skb_put(skb, 1) = opcode; |
| @@ -183,7 +183,7 @@ static inline ssize_t vhci_get_user(struct vhci_data *data, · 36 unmodified lines | ||
| 183 | 183 | return -ENODEV; |
| 184 | 184 | } |
| 185 | 185 | |
| 186 | − bt_cb(skb)->pkt_type = pkt_type; | |
| 186 | + hci_skb_pkt_type(skb) = pkt_type; | |
| 187 | 187 | |
| 188 | 188 | ret = hci_recv_frame(data->hdev, skb); |
| 189 | 189 | break; |
| @@ -234,7 +234,7 @@ static inline ssize_t vhci_put_user(struct vhci_data *data, · 44 unmodified lines | ||
| 234 | 234 | |
| 235 | 235 | data->hdev->stat.byte_tx += len; |
| 236 | 236 | |
| 237 | − switch (bt_cb(skb)->pkt_type) { | |
| 237 | + switch (hci_skb_pkt_type(skb)) { | |
| 238 | 238 | case HCI_COMMAND_PKT: |
| 239 | 239 | data->hdev->stat.cmd_tx++; |
| 240 | 240 | break; |
| @@ -40,6 +40,7 @@ · 39 unmodified lines | ||
| 40 | 40 | #include <linux/gfp.h> |
| 41 | 41 | #include <rdma/ib_pma.h> |
| 42 | 42 | |
| 43 | +#include <linux/mlx4/driver.h> | |
| 43 | 44 | #include "mlx4_ib.h" |
| 44 | 45 | |
| 45 | 46 | enum { |
| @@ -606,8 +607,8 @@ static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port, · 560 unmodified lines | ||
| 606 | 607 | struct ib_mad *mad) |
| 607 | 608 | { |
| 608 | 609 | struct mlx4_ib_dev *dev = to_mdev(ibdev); |
| 609 | − int err; | |
| 610 | − int slave; | |
| 610 | + int err, other_port; | |
| 611 | + int slave = -1; | |
| 611 | 612 | u8 *slave_id; |
| 612 | 613 | int is_eth = 0; |
| 613 | 614 | |
| @@ -625,7 +626,17 @@ static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port, · 11 unmodified lines | ||
| 625 | 626 | mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n"); |
| 626 | 627 | return -EINVAL; |
| 627 | 628 | } |
| 628 | − if (mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave)) { | |
| 629 | + err = mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave); | |
| 630 | + if (err && mlx4_is_mf_bonded(dev->dev)) { | |
| 631 | + other_port = (port == 1) ? 2 : 1; | |
| 632 | + err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, grh->dgid.raw, &slave); | |
| 633 | + if (!err) { | |
| 634 | + port = other_port; | |
| 635 | + pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n", | |
| 636 | + slave, grh->dgid.raw, port, other_port); | |
| 637 | + } | |
| 638 | + } | |
| 639 | + if (err) { | |
| 629 | 640 | mlx4_ib_warn(ibdev, "failed matching grh\n"); |
| 630 | 641 | return -ENOENT; |
| 631 | 642 | } |
| @@ -43,6 +43,9 @@ · 42 unmodified lines | ||
| 43 | 43 | #include <linux/mlx5/vport.h> |
| 44 | 44 | #include <rdma/ib_smi.h> |
| 45 | 45 | #include <rdma/ib_umem.h> |
| 46 | +#include <linux/in.h> | |
| 47 | +#include <linux/etherdevice.h> | |
| 48 | +#include <linux/mlx5/fs.h> | |
| 46 | 49 | #include "user.h" |
| 47 | 50 | #include "mlx5_ib.h" |
| 48 | 51 | |
| @@ -835,6 +838,457 @@ static int mlx5_ib_dealloc_pd(struct ib_pd *pd) · 786 unmodified lines | ||
| 835 | 838 | return 0; |
| 836 | 839 | } |
| 837 | 840 | |
| 841 | +static bool outer_header_zero(u32 *match_criteria) | |
| 842 | +{ | |
| 843 | + int size = MLX5_ST_SZ_BYTES(fte_match_param); | |
| 844 | + char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
| 845 | + outer_headers); | |
| 846 | + | |
| 847 | + return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, | |
| 848 | + outer_headers_c + 1, | |
| 849 | + size - 1); | |
| 850 | +} | |
| 851 | + | |
| 852 | +static int parse_flow_attr(u32 *match_c, u32 *match_v, | |
| 853 | + union ib_flow_spec *ib_spec) | |
| 854 | +{ | |
| 855 | + void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
| 856 | + outer_headers); | |
| 857 | + void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
| 858 | + outer_headers); | |
| 859 | + switch (ib_spec->type) { | |
| 860 | + case IB_FLOW_SPEC_ETH: | |
| 861 | + if (ib_spec->size != sizeof(ib_spec->eth)) | |
| 862 | + return -EINVAL; | |
| 863 | + | |
| 864 | + ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
| 865 | + dmac_47_16), | |
| 866 | + ib_spec->eth.mask.dst_mac); | |
| 867 | + ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
| 868 | + dmac_47_16), | |
| 869 | + ib_spec->eth.val.dst_mac); | |
| 870 | + | |
| 871 | + if (ib_spec->eth.mask.vlan_tag) { | |
| 872 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
| 873 | + vlan_tag, 1); | |
| 874 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
| 875 | + vlan_tag, 1); | |
| 876 | + | |
| 877 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
| 878 | + first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); | |
| 879 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
| 880 | + first_vid, ntohs(ib_spec->eth.val.vlan_tag)); | |
| 881 | + | |
| 882 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
| 883 | + first_cfi, | |
| 884 | + ntohs(ib_spec->eth.mask.vlan_tag) >> 12); | |
| 885 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
| 886 | + first_cfi, | |
| 887 | + ntohs(ib_spec->eth.val.vlan_tag) >> 12); | |
| 888 | + | |
| 889 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
| 890 | + first_prio, | |
| 891 | + ntohs(ib_spec->eth.mask.vlan_tag) >> 13); | |
| 892 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
| 893 | + first_prio, | |
| 894 | + ntohs(ib_spec->eth.val.vlan_tag) >> 13); | |
| 895 | + } | |
| 896 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
| 897 | + ethertype, ntohs(ib_spec->eth.mask.ether_type)); | |
| 898 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
| 899 | + ethertype, ntohs(ib_spec->eth.val.ether_type)); | |
| 900 | + break; | |
| 901 | + case IB_FLOW_SPEC_IPV4: | |
| 902 | + if (ib_spec->size != sizeof(ib_spec->ipv4)) | |
| 903 | + return -EINVAL; | |
| 904 | + | |
| 905 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
| 906 | + ethertype, 0xffff); | |
| 907 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
| 908 | + ethertype, ETH_P_IP); | |
| 909 | + | |
| 910 | + memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
| 911 | + src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
| 912 | + &ib_spec->ipv4.mask.src_ip, | |
| 913 | + sizeof(ib_spec->ipv4.mask.src_ip)); | |
| 914 | + memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
| 915 | + src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
| 916 | + &ib_spec->ipv4.val.src_ip, | |
| 917 | + sizeof(ib_spec->ipv4.val.src_ip)); | |
| 918 | + memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
| 919 | + dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
| 920 | + &ib_spec->ipv4.mask.dst_ip, | |
| 921 | + sizeof(ib_spec->ipv4.mask.dst_ip)); | |
| 922 | + memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
| 923 | + dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
| 924 | + &ib_spec->ipv4.val.dst_ip, | |
| 925 | + sizeof(ib_spec->ipv4.val.dst_ip)); | |
| 926 | + break; | |
| 927 | + case IB_FLOW_SPEC_TCP: | |
| 928 | + if (ib_spec->size != sizeof(ib_spec->tcp_udp)) | |
| 929 | + return -EINVAL; | |
| 930 | + | |
| 931 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, | |
| 932 | + 0xff); | |
| 933 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, | |
| 934 | + IPPROTO_TCP); | |
| 935 | + | |
| 936 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, | |
| 937 | + ntohs(ib_spec->tcp_udp.mask.src_port)); | |
| 938 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, | |
| 939 | + ntohs(ib_spec->tcp_udp.val.src_port)); | |
| 940 | + | |
| 941 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, | |
| 942 | + ntohs(ib_spec->tcp_udp.mask.dst_port)); | |
| 943 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, | |
| 944 | + ntohs(ib_spec->tcp_udp.val.dst_port)); | |
| 945 | + break; | |
| 946 | + case IB_FLOW_SPEC_UDP: | |
| 947 | + if (ib_spec->size != sizeof(ib_spec->tcp_udp)) | |
| 948 | + return -EINVAL; | |
| 949 | + | |
| 950 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, | |
| 951 | + 0xff); | |
| 952 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, | |
| 953 | + IPPROTO_UDP); | |
| 954 | + | |
| 955 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, | |
| 956 | + ntohs(ib_spec->tcp_udp.mask.src_port)); | |
| 957 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, | |
| 958 | + ntohs(ib_spec->tcp_udp.val.src_port)); | |
| 959 | + | |
| 960 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, | |
| 961 | + ntohs(ib_spec->tcp_udp.mask.dst_port)); | |
| 962 | + MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, | |
| 963 | + ntohs(ib_spec->tcp_udp.val.dst_port)); | |
| 964 | + break; | |
| 965 | + default: | |
| 966 | + return -EINVAL; | |
| 967 | + } | |
| 968 | + | |
| 969 | + return 0; | |
| 970 | +} | |
| 971 | + | |
| 972 | +/* If a flow could catch both multicast and unicast packets, | |
| 973 | + * it won't fall into the multicast flow steering table and this rule | |
| 974 | + * could steal other multicast packets. | |
| 975 | + */ | |
| 976 | +static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) | |
| 977 | +{ | |
| 978 | + struct ib_flow_spec_eth *eth_spec; | |
| 979 | + | |
| 980 | + if (ib_attr->type != IB_FLOW_ATTR_NORMAL || | |
| 981 | + ib_attr->size < sizeof(struct ib_flow_attr) + | |
| 982 | + sizeof(struct ib_flow_spec_eth) || | |
| 983 | + ib_attr->num_of_specs < 1) | |
| 984 | + return false; | |
| 985 | + | |
| 986 | + eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); | |
| 987 | + if (eth_spec->type != IB_FLOW_SPEC_ETH || | |
| 988 | + eth_spec->size != sizeof(*eth_spec)) | |
| 989 | + return false; | |
| 990 | + | |
| 991 | + return is_multicast_ether_addr(eth_spec->mask.dst_mac) && | |
| 992 | + is_multicast_ether_addr(eth_spec->val.dst_mac); | |
| 993 | +} | |
| 994 | + | |
| 995 | +static bool is_valid_attr(struct ib_flow_attr *flow_attr) | |
| 996 | +{ | |
| 997 | + union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); | |
| 998 | + bool has_ipv4_spec = false; | |
| 999 | + bool eth_type_ipv4 = true; | |
| 1000 | + unsigned int spec_index; | |
| 1001 | + | |
| 1002 | + /* Validate that ethertype is correct */ | |
| 1003 | + for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
| 1004 | + if (ib_spec->type == IB_FLOW_SPEC_ETH && | |
| 1005 | + ib_spec->eth.mask.ether_type) { | |
| 1006 | + if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && | |
| 1007 | + ib_spec->eth.val.ether_type == htons(ETH_P_IP))) | |
| 1008 | + eth_type_ipv4 = false; | |
| 1009 | + } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { | |
| 1010 | + has_ipv4_spec = true; | |
| 1011 | + } | |
| 1012 | + ib_spec = (void *)ib_spec + ib_spec->size; | |
| 1013 | + } | |
| 1014 | + return !has_ipv4_spec || eth_type_ipv4; | |
| 1015 | +} | |
| 1016 | + | |
| 1017 | +static void put_flow_table(struct mlx5_ib_dev *dev, | |
| 1018 | + struct mlx5_ib_flow_prio *prio, bool ft_added) | |
| 1019 | +{ | |
| 1020 | + prio->refcount -= !!ft_added; | |
| 1021 | + if (!prio->refcount) { | |
| 1022 | + mlx5_destroy_flow_table(prio->flow_table); | |
| 1023 | + prio->flow_table = NULL; | |
| 1024 | + } | |
| 1025 | +} | |
| 1026 | + | |
| 1027 | +static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) | |
| 1028 | +{ | |
| 1029 | + struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); | |
| 1030 | + struct mlx5_ib_flow_handler *handler = container_of(flow_id, | |
| 1031 | + struct mlx5_ib_flow_handler, | |
| 1032 | + ibflow); | |
| 1033 | + struct mlx5_ib_flow_handler *iter, *tmp; | |
| 1034 | + | |
| 1035 | + mutex_lock(&dev->flow_db.lock); | |
| 1036 | + | |
| 1037 | + list_for_each_entry_safe(iter, tmp, &handler->list, list) { | |
| 1038 | + mlx5_del_flow_rule(iter->rule); | |
| 1039 | + list_del(&iter->list); | |
| 1040 | + kfree(iter); | |
| 1041 | + } | |
| 1042 | + | |
| 1043 | + mlx5_del_flow_rule(handler->rule); | |
| 1044 | + put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); | |
| 1045 | + mutex_unlock(&dev->flow_db.lock); | |
| 1046 | + | |
| 1047 | + kfree(handler); | |
| 1048 | + | |
| 1049 | + return 0; | |
| 1050 | +} | |
| 1051 | + | |
| 1052 | +#define MLX5_FS_MAX_TYPES 10 | |
| 1053 | +#define MLX5_FS_MAX_ENTRIES 32000UL | |
| 1054 | +static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, | |
| 1055 | + struct ib_flow_attr *flow_attr) | |
| 1056 | +{ | |
| 1057 | + struct mlx5_flow_namespace *ns = NULL; | |
| 1058 | + struct mlx5_ib_flow_prio *prio; | |
| 1059 | + struct mlx5_flow_table *ft; | |
| 1060 | + int num_entries; | |
| 1061 | + int num_groups; | |
| 1062 | + int priority; | |
| 1063 | + int err = 0; | |
| 1064 | + | |
| 1065 | + if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
| 1066 | + if (flow_is_multicast_only(flow_attr)) | |
| 1067 | + priority = MLX5_IB_FLOW_MCAST_PRIO; | |
| 1068 | + else | |
| 1069 | + priority = flow_attr->priority; | |
| 1070 | + ns = mlx5_get_flow_namespace(dev->mdev, | |
| 1071 | + MLX5_FLOW_NAMESPACE_BYPASS); | |
| 1072 | + num_entries = MLX5_FS_MAX_ENTRIES; | |
| 1073 | + num_groups = MLX5_FS_MAX_TYPES; | |
| 1074 | + prio = &dev->flow_db.prios[priority]; | |
| 1075 | + } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
| 1076 | + flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
| 1077 | + ns = mlx5_get_flow_namespace(dev->mdev, | |
| 1078 | + MLX5_FLOW_NAMESPACE_LEFTOVERS); | |
| 1079 | + build_leftovers_ft_param(&priority, | |
| 1080 | + &num_entries, | |
| 1081 | + &num_groups); | |
| 1082 | + prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; | |
| 1083 | + } | |
| 1084 | + | |
| 1085 | + if (!ns) | |
| 1086 | + return ERR_PTR(-ENOTSUPP); | |
| 1087 | + | |
| 1088 | + ft = prio->flow_table; | |
| 1089 | + if (!ft) { | |
| 1090 | + ft = mlx5_create_auto_grouped_flow_table(ns, priority, | |
| 1091 | + num_entries, | |
| 1092 | + num_groups); | |
| 1093 | + | |
| 1094 | + if (!IS_ERR(ft)) { | |
| 1095 | + prio->refcount = 0; | |
| 1096 | + prio->flow_table = ft; | |
| 1097 | + } else { | |
| 1098 | + err = PTR_ERR(ft); | |
| 1099 | + } | |
| 1100 | + } | |
| 1101 | + | |
| 1102 | + return err ? ERR_PTR(err) : prio; | |
| 1103 | +} | |
| 1104 | + | |
| 1105 | +static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, | |
| 1106 | + struct mlx5_ib_flow_prio *ft_prio, | |
| 1107 | + struct ib_flow_attr *flow_attr, | |
| 1108 | + struct mlx5_flow_destination *dst) | |
| 1109 | +{ | |
| 1110 | + struct mlx5_flow_table *ft = ft_prio->flow_table; | |
| 1111 | + struct mlx5_ib_flow_handler *handler; | |
| 1112 | + void *ib_flow = flow_attr + 1; | |
| 1113 | + u8 match_criteria_enable = 0; | |
| 1114 | + unsigned int spec_index; | |
| 1115 | + u32 *match_c; | |
| 1116 | + u32 *match_v; | |
| 1117 | + int err = 0; | |
| 1118 | + | |
| 1119 | + if (!is_valid_attr(flow_attr)) | |
| 1120 | + return ERR_PTR(-EINVAL); | |
| 1121 | + | |
| 1122 | + match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
| 1123 | + match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
| 1124 | + handler = kzalloc(sizeof(*handler), GFP_KERNEL); | |
| 1125 | + if (!handler || !match_c || !match_v) { | |
| 1126 | + err = -ENOMEM; | |
| 1127 | + goto free; | |
| 1128 | + } | |
| 1129 | + | |
| 1130 | + INIT_LIST_HEAD(&handler->list); | |
| 1131 | + | |
| 1132 | + for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
| 1133 | + err = parse_flow_attr(match_c, match_v, ib_flow); | |
| 1134 | + if (err < 0) | |
| 1135 | + goto free; | |
| 1136 | + | |
| 1137 | + ib_flow += ((union ib_flow_spec *)ib_flow)->size; | |
| 1138 | + } | |
| 1139 | + | |
| 1140 | + /* Outer header support only */ | |
| 1141 | + match_criteria_enable = (!outer_header_zero(match_c)) << 0; | |
| 1142 | + handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable, | |
| 1143 | + match_c, match_v, | |
| 1144 | + MLX5_FLOW_CONTEXT_ACTION_FWD_DEST, | |
| 1145 | + MLX5_FS_DEFAULT_FLOW_TAG, | |
| 1146 | + dst); | |
| 1147 | + | |
| 1148 | + if (IS_ERR(handler->rule)) { | |
| 1149 | + err = PTR_ERR(handler->rule); | |
| 1150 | + goto free; | |
| 1151 | + } | |
| 1152 | + | |
| 1153 | + handler->prio = ft_prio - dev->flow_db.prios; | |
| 1154 | + | |
| 1155 | + ft_prio->flow_table = ft; | |
| 1156 | +free: | |
| 1157 | + if (err) | |
| 1158 | + kfree(handler); | |
| 1159 | + kfree(match_c); | |
| 1160 | + kfree(match_v); | |
| 1161 | + return err ? ERR_PTR(err) : handler; | |
| 1162 | +} | |
| 1163 | + | |
| 1164 | +enum { | |
| 1165 | + LEFTOVERS_MC, | |
| 1166 | + LEFTOVERS_UC, | |
| 1167 | +}; | |
| 1168 | + | |
| 1169 | +static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, | |
| 1170 | + struct mlx5_ib_flow_prio *ft_prio, | |
| 1171 | + struct ib_flow_attr *flow_attr, | |
| 1172 | + struct mlx5_flow_destination *dst) | |
| 1173 | +{ | |
| 1174 | + struct mlx5_ib_flow_handler *handler_ucast = NULL; | |
| 1175 | + struct mlx5_ib_flow_handler *handler = NULL; | |
| 1176 | + | |
| 1177 | + static struct { | |
| 1178 | + struct ib_flow_attr flow_attr; | |
| 1179 | + struct ib_flow_spec_eth eth_flow; | |
| 1180 | + } leftovers_specs[] = { | |
| 1181 | + [LEFTOVERS_MC] = { | |
| 1182 | + .flow_attr = { | |
| 1183 | + .num_of_specs = 1, | |
| 1184 | + .size = sizeof(leftovers_specs[0]) | |
| 1185 | + }, | |
| 1186 | + .eth_flow = { | |
| 1187 | + .type = IB_FLOW_SPEC_ETH, | |
| 1188 | + .size = sizeof(struct ib_flow_spec_eth), | |
| 1189 | + .mask = {.dst_mac = {0x1} }, | |
| 1190 | + .val = {.dst_mac = {0x1} } | |
| 1191 | + } | |
| 1192 | + }, | |
| 1193 | + [LEFTOVERS_UC] = { | |
| 1194 | + .flow_attr = { | |
| 1195 | + .num_of_specs = 1, | |
| 1196 | + .size = sizeof(leftovers_specs[0]) | |
| 1197 | + }, | |
| 1198 | + .eth_flow = { | |
| 1199 | + .type = IB_FLOW_SPEC_ETH, | |
| 1200 | + .size = sizeof(struct ib_flow_spec_eth), | |
| 1201 | + .mask = {.dst_mac = {0x1} }, | |
| 1202 | + .val = {.dst_mac = {} } | |
| 1203 | + } | |
| 1204 | + } | |
| 1205 | + }; | |
| 1206 | + | |
| 1207 | + handler = create_flow_rule(dev, ft_prio, | |
| 1208 | + &leftovers_specs[LEFTOVERS_MC].flow_attr, | |
| 1209 | + dst); | |
| 1210 | + if (!IS_ERR(handler) && | |
| 1211 | + flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { | |
| 1212 | + handler_ucast = create_flow_rule(dev, ft_prio, | |
| 1213 | + &leftovers_specs[LEFTOVERS_UC].flow_attr, | |
| 1214 | + dst); | |
| 1215 | + if (IS_ERR(handler_ucast)) { | |
| 1216 | + kfree(handler); | |
| 1217 | + handler = handler_ucast; | |
| 1218 | + } else { | |
| 1219 | + list_add(&handler_ucast->list, &handler->list); | |
| 1220 | + } | |
| 1221 | + } | |
| 1222 | + | |
| 1223 | + return handler; | |
| 1224 | +} | |
| 1225 | + | |
| 1226 | +static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, | |
| 1227 | + struct ib_flow_attr *flow_attr, | |
| 1228 | + int domain) | |
| 1229 | +{ | |
| 1230 | + struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
| 1231 | + struct mlx5_ib_flow_handler *handler = NULL; | |
| 1232 | + struct mlx5_flow_destination *dst = NULL; | |
| 1233 | + struct mlx5_ib_flow_prio *ft_prio; | |
| 1234 | + int err; | |
| 1235 | + | |
| 1236 | + if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) | |
| 1237 | + return ERR_PTR(-ENOSPC); | |
| 1238 | + | |
| 1239 | + if (domain != IB_FLOW_DOMAIN_USER || | |
| 1240 | + flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || | |
| 1241 | + flow_attr->flags) | |
| 1242 | + return ERR_PTR(-EINVAL); | |
| 1243 | + | |
| 1244 | + dst = kzalloc(sizeof(*dst), GFP_KERNEL); | |
| 1245 | + if (!dst) | |
| 1246 | + return ERR_PTR(-ENOMEM); | |
| 1247 | + | |
| 1248 | + mutex_lock(&dev->flow_db.lock); | |
| 1249 | + | |
| 1250 | + ft_prio = get_flow_table(dev, flow_attr); | |
| 1251 | + if (IS_ERR(ft_prio)) { | |
| 1252 | + err = PTR_ERR(ft_prio); | |
| 1253 | + goto unlock; | |
| 1254 | + } | |
| 1255 | + | |
| 1256 | + dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; | |
| 1257 | + dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; | |
| 1258 | + | |
| 1259 | + if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
| 1260 | + handler = create_flow_rule(dev, ft_prio, flow_attr, | |
| 1261 | + dst); | |
| 1262 | + } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
| 1263 | + flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
| 1264 | + handler = create_leftovers_rule(dev, ft_prio, flow_attr, | |
| 1265 | + dst); | |
| 1266 | + } else { | |
| 1267 | + err = -EINVAL; | |
| 1268 | + goto destroy_ft; | |
| 1269 | + } | |
| 1270 | + | |
| 1271 | + if (IS_ERR(handler)) { | |
| 1272 | + err = PTR_ERR(handler); | |
| 1273 | + handler = NULL; | |
| 1274 | + goto destroy_ft; | |
| 1275 | + } | |
| 1276 | + | |
| 1277 | + ft_prio->refcount++; | |
| 1278 | + mutex_unlock(&dev->flow_db.lock); | |
| 1279 | + kfree(dst); | |
| 1280 | + | |
| 1281 | + return &handler->ibflow; | |
| 1282 | + | |
| 1283 | +destroy_ft: | |
| 1284 | + put_flow_table(dev, ft_prio, false); | |
| 1285 | +unlock: | |
| 1286 | + mutex_unlock(&dev->flow_db.lock); | |
| 1287 | + kfree(dst); | |
| 1288 | + kfree(handler); | |
| 1289 | + return ERR_PTR(err); | |
| 1290 | +} | |
| 1291 | + | |
| 838 | 1292 | static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) |
| 839 | 1293 | { |
| 840 | 1294 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
| @@ -1439,10 +1893,19 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) · 598 unmodified lines | ||
| 1439 | 1893 | (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); |
| 1440 | 1894 | } |
| 1441 | 1895 | |
| 1896 | + if (mlx5_ib_port_link_layer(&dev->ib_dev) == | |
| 1897 | + IB_LINK_LAYER_ETHERNET) { | |
| 1898 | + dev->ib_dev.create_flow = mlx5_ib_create_flow; | |
| 1899 | + dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; | |
| 1900 | + dev->ib_dev.uverbs_ex_cmd_mask |= | |
| 1901 | + (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | | |
| 1902 | + (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); | |
| 1903 | + } | |
| 1442 | 1904 | err = init_node_data(dev); |
| 1443 | 1905 | if (err) |
| 1444 | 1906 | goto err_dealloc; |
| 1445 | 1907 | |
| 1908 | + mutex_init(&dev->flow_db.lock); | |
| 1446 | 1909 | mutex_init(&dev->cap_mask_mutex); |
| 1447 | 1910 | |
| 1448 | 1911 | err = create_dev_resources(&dev->devr); |
| @@ -105,6 +105,36 @@ struct mlx5_ib_pd { · 104 unmodified lines | ||
| 105 | 105 | u32 pdn; |
| 106 | 106 | }; |
| 107 | 107 | |
| 108 | +#define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) | |
| 109 | +#define MLX5_IB_FLOW_LAST_PRIO (MLX5_IB_FLOW_MCAST_PRIO - 1) | |
| 110 | +#if (MLX5_IB_FLOW_LAST_PRIO <= 0) | |
| 111 | +#error "Invalid number of bypass priorities" | |
| 112 | +#endif | |
| 113 | +#define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) | |
| 114 | + | |
| 115 | +#define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) | |
| 116 | +struct mlx5_ib_flow_prio { | |
| 117 | + struct mlx5_flow_table *flow_table; | |
| 118 | + unsigned int refcount; | |
| 119 | +}; | |
| 120 | + | |
| 121 | +struct mlx5_ib_flow_handler { | |
| 122 | + struct list_head list; | |
| 123 | + struct ib_flow ibflow; | |
| 124 | + unsigned int prio; | |
| 125 | + struct mlx5_flow_rule *rule; | |
| 126 | +}; | |
| 127 | + | |
| 128 | +struct mlx5_ib_flow_db { | |
| 129 | + struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; | |
| 130 | + /* Protect flow steering bypass flow tables | |
| 131 | + * when add/del flow rules. | |
| 132 | + * only single add/removal of flow steering rule could be done | |
| 133 | + * simultaneously. | |
| 134 | + */ | |
| 135 | + struct mutex lock; | |
| 136 | +}; | |
| 137 | + | |
| 108 | 138 | /* Use macros here so that don't have to duplicate |
| 109 | 139 | * enum ib_send_flags and enum ib_qp_type for low-level driver |
| 110 | 140 | */ |
| @@ -171,9 +201,21 @@ struct mlx5_ib_pfault { · 60 unmodified lines | ||
| 171 | 201 | struct mlx5_pagefault mpfault; |
| 172 | 202 | }; |
| 173 | 203 | |
| 204 | +struct mlx5_ib_rq { | |
| 205 | + u32 tirn; | |
| 206 | +}; | |
| 207 | + | |
| 208 | +struct mlx5_ib_raw_packet_qp { | |
| 209 | + struct mlx5_ib_rq rq; | |
| 210 | +}; | |
| 211 | + | |
| 174 | 212 | struct mlx5_ib_qp { |
| 175 | 213 | struct ib_qp ibqp; |
| 176 | − struct mlx5_core_qp mqp; | |
| 214 | + union { | |
| 215 | + struct mlx5_core_qp mqp; | |
| 216 | + struct mlx5_ib_raw_packet_qp raw_packet_qp; | |
| 217 | + }; | |
| 218 | + | |
| 177 | 219 | struct mlx5_buf buf; |
| 178 | 220 | |
| 179 | 221 | struct mlx5_db db; |
| @@ -431,6 +473,7 @@ struct mlx5_ib_dev { · 251 unmodified lines | ||
| 431 | 473 | */ |
| 432 | 474 | struct srcu_struct mr_srcu; |
| 433 | 475 | #endif |
| 476 | + struct mlx5_ib_flow_db flow_db; | |
| 434 | 477 | }; |
| 435 | 478 | |
| 436 | 479 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) |
| @@ -10,7 +10,6 @@ obj-$(CONFIG_ISDN_DIVERSION) += divert/ · 9 unmodified lines | ||
| 10 | 10 | obj-$(CONFIG_ISDN_DRV_HISAX) += hisax/ |
| 11 | 11 | obj-$(CONFIG_ISDN_DRV_ICN) += icn/ |
| 12 | 12 | obj-$(CONFIG_ISDN_DRV_PCBIT) += pcbit/ |
| 13 | −obj-$(CONFIG_ISDN_DRV_SC) += sc/ | |
| 14 | 13 | obj-$(CONFIG_ISDN_DRV_LOOP) += isdnloop/ |
| 15 | 14 | obj-$(CONFIG_ISDN_DRV_ACT2000) += act2000/ |
| 16 | 15 | obj-$(CONFIG_HYSDN) += hysdn/ |
| @@ -37,7 +37,7 @@ MODULE_DESCRIPTION("ISDN4Linux: Driver for IBM Active 2000 ISDN card"); · 36 unmodified lines | ||
| 37 | 37 | MODULE_AUTHOR("Fritz Elfert"); |
| 38 | 38 | MODULE_LICENSE("GPL"); |
| 39 | 39 | MODULE_PARM_DESC(act_bus, "BusType of first card, 1=ISA, 2=MCA, 3=PCMCIA, currently only ISA"); |
| 40 | −MODULE_PARM_DESC(membase, "Base port address of first card"); | |
| 40 | +MODULE_PARM_DESC(act_port, "Base port address of first card"); | |
| 41 | 41 | MODULE_PARM_DESC(act_irq, "IRQ of first card"); |
| 42 | 42 | MODULE_PARM_DESC(act_id, "ID-String of first card"); |
| 43 | 43 | module_param(act_bus, int, 0); |
| @@ -130,8 +130,6 @@ source "drivers/isdn/icn/Kconfig" · 129 unmodified lines | ||
| 130 | 130 | |
| 131 | 131 | source "drivers/isdn/pcbit/Kconfig" |
| 132 | 132 | |
| 133 | −source "drivers/isdn/sc/Kconfig" | |
| 134 | − | |
| 135 | 133 | source "drivers/isdn/act2000/Kconfig" |
| 136 | 134 | |
| 137 | 135 | endmenu |
| @@ -1,8 +0,0 @@ | ||
| 1 | −config ISDN_DRV_SC | |
| 2 | − tristate "Spellcaster support" | |
| 3 | − depends on ISA | |
| 4 | − help | |
| 5 | − This enables support for the Spellcaster BRI ISDN boards. This | |
| 6 | − driver currently builds only in a modularized version. | |
| 7 | − To build it, choose M here: the module will be called sc. | |
| 8 | − See <file:Documentation/isdn/README.sc> for more information. | |
| @@ -1,10 +0,0 @@ | ||
| 1 | −# Makefile for the sc ISDN device driver | |
| 2 | − | |
| 3 | −# Each configuration option enables a list of files. | |
| 4 | − | |
| 5 | −obj-$(CONFIG_ISDN_DRV_SC) += sc.o | |
| 6 | − | |
| 7 | −# Multipart objects. | |
| 8 | − | |
| 9 | −sc-y := shmem.o init.o packet.o command.o event.o \ | |
| 10 | − ioctl.o interrupt.o message.o timer.o | |
| @@ -1,131 +0,0 @@ | ||
| 1 | −/* $Id: card.h,v 1.1.10.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Driver parameters for SpellCaster ISA ISDN adapters | |
| 4 | − * | |
| 5 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 6 | − * | |
| 7 | − * This software may be used and distributed according to the terms | |
| 8 | − * of the GNU General Public License, incorporated herein by reference. | |
| 9 | − * | |
| 10 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 11 | − * | |
| 12 | − * SpellCaster Telecommunications Inc. | |
| 13 | − * 5621 Finch Avenue East, Unit #3 | |
| 14 | − * Scarborough, Ontario Canada | |
| 15 | − * M1B 2T9 | |
| 16 | − * +1 (416) 297-8565 | |
| 17 | − * +1 (416) 297-6433 Facsimile | |
| 18 | − */ | |
| 19 | − | |
| 20 | −#ifndef CARD_H | |
| 21 | −#define CARD_H | |
| 22 | − | |
| 23 | −/* | |
| 24 | − * We need these if they're not already included | |
| 25 | − */ | |
| 26 | −#include <linux/timer.h> | |
| 27 | −#include <linux/time.h> | |
| 28 | −#include <linux/isdnif.h> | |
| 29 | −#include <linux/irqreturn.h> | |
| 30 | −#include "message.h" | |
| 31 | −#include "scioc.h" | |
| 32 | − | |
| 33 | −/* | |
| 34 | − * Amount of time to wait for a reset to complete | |
| 35 | − */ | |
| 36 | −#define CHECKRESET_TIME msecs_to_jiffies(4000) | |
| 37 | − | |
| 38 | −/* | |
| 39 | − * Amount of time between line status checks | |
| 40 | − */ | |
| 41 | −#define CHECKSTAT_TIME msecs_to_jiffies(8000) | |
| 42 | − | |
| 43 | −/* | |
| 44 | − * The maximum amount of time to wait for a message response | |
| 45 | − * to arrive. Use exclusively by send_and_receive | |
| 46 | − */ | |
| 47 | −#define SAR_TIMEOUT msecs_to_jiffies(10000) | |
| 48 | − | |
| 49 | −/* | |
| 50 | − * Macro to determine is a card id is valid | |
| 51 | − */ | |
| 52 | −#define IS_VALID_CARD(x) ((x >= 0) && (x <= cinst)) | |
| 53 | − | |
| 54 | −/* | |
| 55 | − * Per channel status and configuration | |
| 56 | − */ | |
| 57 | −typedef struct { | |
| 58 | − int l2_proto; | |
| 59 | − int l3_proto; | |
| 60 | − char dn[50]; | |
| 61 | − unsigned long first_sendbuf; /* Offset of first send buffer */ | |
| 62 | − unsigned int num_sendbufs; /* Number of send buffers */ | |
| 63 | − unsigned int free_sendbufs; /* Number of free sendbufs */ | |
| 64 | − unsigned int next_sendbuf; /* Next sequential buffer */ | |
| 65 | − char eazlist[50]; /* Set with SETEAZ */ | |
| 66 | − char sillist[50]; /* Set with SETSIL */ | |
| 67 | − int eazclear; /* Don't accept calls if TRUE */ | |
| 68 | −} bchan; | |
| 69 | − | |
| 70 | −/* | |
| 71 | − * Everything you want to know about the adapter ... | |
| 72 | − */ | |
| 73 | −typedef struct { | |
| 74 | − int model; | |
| 75 | − int driverId; /* LL Id */ | |
| 76 | − char devicename[20]; /* The device name */ | |
| 77 | − isdn_if *card; /* ISDN4Linux structure */ | |
| 78 | − bchan *channel; /* status of the B channels */ | |
| 79 | − char nChannels; /* Number of channels */ | |
| 80 | − unsigned int interrupt; /* Interrupt number */ | |
| 81 | − int iobase; /* I/O Base address */ | |
| 82 | − int ioport[MAX_IO_REGS]; /* Index to I/O ports */ | |
| 83 | − int shmem_pgport; /* port for the exp mem page reg. */ | |
| 84 | − int shmem_magic; /* adapter magic number */ | |
| 85 | − unsigned int rambase; /* Shared RAM base address */ | |
| 86 | − unsigned int ramsize; /* Size of shared memory */ | |
| 87 | − RspMessage async_msg; /* Async response message */ | |
| 88 | − int want_async_messages; /* Snoop the Q ? */ | |
| 89 | − unsigned char seq_no; /* Next send seq. number */ | |
| 90 | − struct timer_list reset_timer; /* Check reset timer */ | |
| 91 | − struct timer_list stat_timer; /* Check startproc timer */ | |
| 92 | − unsigned char nphystat; /* Latest PhyStat info */ | |
| 93 | − unsigned char phystat; /* Last PhyStat info */ | |
| 94 | − HWConfig_pl hwconfig; /* Hardware config info */ | |
| 95 | − char load_ver[11]; /* CommManage Version string */ | |
| 96 | − char proc_ver[11]; /* CommEngine Version */ | |
| 97 | − int StartOnReset; /* Indicates startproc after reset */ | |
| 98 | − int EngineUp; /* Indicates CommEngine Up */ | |
| 99 | − int trace_mode; /* Indicate if tracing is on */ | |
| 100 | − spinlock_t lock; /* local lock */ | |
| 101 | −} board; | |
| 102 | − | |
| 103 | − | |
| 104 | −extern board *sc_adapter[]; | |
| 105 | −extern int cinst; | |
| 106 | − | |
| 107 | −void memcpy_toshmem(int card, void *dest, const void *src, size_t n); | |
| 108 | −void memcpy_fromshmem(int card, void *dest, const void *src, size_t n); | |
| 109 | −int get_card_from_id(int driver); | |
| 110 | −int indicate_status(int card, int event, ulong Channel, char *Data); | |
| 111 | −irqreturn_t interrupt_handler(int interrupt, void *cardptr); | |
| 112 | −int sndpkt(int devId, int channel, int ack, struct sk_buff *data); | |
| 113 | −void rcvpkt(int card, RspMessage *rcvmsg); | |
| 114 | −int command(isdn_ctrl *cmd); | |
| 115 | −int reset(int card); | |
| 116 | −int startproc(int card); | |
| 117 | −int send_and_receive(int card, unsigned int procid, unsigned char type, | |
| 118 | − unsigned char class, unsigned char code, | |
| 119 | − unsigned char link, unsigned char data_len, | |
| 120 | − unsigned char *data, RspMessage *mesgdata, int timeout); | |
| 121 | −void flushreadfifo(int card); | |
| 122 | −int sendmessage(int card, unsigned int procid, unsigned int type, | |
| 123 | − unsigned int class, unsigned int code, unsigned int link, | |
| 124 | − unsigned int data_len, unsigned int *data); | |
| 125 | −int receivemessage(int card, RspMessage *rspmsg); | |
| 126 | −int sc_ioctl(int card, scs_ioctl *data); | |
| 127 | −int setup_buffers(int card, int c); | |
| 128 | −void sc_check_reset(unsigned long data); | |
| 129 | −void check_phystat(unsigned long data); | |
| 130 | − | |
| 131 | −#endif /* CARD_H */ | |
| @@ -1,363 +0,0 @@ | ||
| 1 | −/* $Id: command.c,v 1.4.10.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * This software may be used and distributed according to the terms | |
| 6 | − * of the GNU General Public License, incorporated herein by reference. | |
| 7 | − * | |
| 8 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 9 | − * | |
| 10 | − * SpellCaster Telecommunications Inc. | |
| 11 | − * 5621 Finch Avenue East, Unit #3 | |
| 12 | − * Scarborough, Ontario Canada | |
| 13 | − * M1B 2T9 | |
| 14 | − * +1 (416) 297-8565 | |
| 15 | − * +1 (416) 297-6433 Facsimile | |
| 16 | − */ | |
| 17 | − | |
| 18 | −#include <linux/module.h> | |
| 19 | −#include "includes.h" /* This must be first */ | |
| 20 | −#include "hardware.h" | |
| 21 | −#include "message.h" | |
| 22 | −#include "card.h" | |
| 23 | −#include "scioc.h" | |
| 24 | − | |
| 25 | −static int dial(int card, unsigned long channel, setup_parm setup); | |
| 26 | −static int hangup(int card, unsigned long channel); | |
| 27 | −static int answer(int card, unsigned long channel); | |
| 28 | −static int clreaz(int card, unsigned long channel); | |
| 29 | −static int seteaz(int card, unsigned long channel, char *); | |
| 30 | −static int setl2(int card, unsigned long arg); | |
| 31 | −static int setl3(int card, unsigned long arg); | |
| 32 | −static int acceptb(int card, unsigned long channel); | |
| 33 | − | |
| 34 | −#ifdef DEBUG | |
| 35 | −/* | |
| 36 | − * Translate command codes to strings | |
| 37 | − */ | |
| 38 | −static char *commands[] = { "ISDN_CMD_IOCTL", | |
| 39 | − "ISDN_CMD_DIAL", | |
| 40 | − "ISDN_CMD_ACCEPTB", | |
| 41 | − "ISDN_CMD_ACCEPTB", | |
| 42 | − "ISDN_CMD_HANGUP", | |
| 43 | − "ISDN_CMD_CLREAZ", | |
| 44 | − "ISDN_CMD_SETEAZ", | |
| 45 | − NULL, | |
| 46 | − NULL, | |
| 47 | − NULL, | |
| 48 | − "ISDN_CMD_SETL2", | |
| 49 | − NULL, | |
| 50 | − "ISDN_CMD_SETL3", | |
| 51 | − NULL, | |
| 52 | − NULL, | |
| 53 | − NULL, | |
| 54 | − NULL, | |
| 55 | − NULL, }; | |
| 56 | − | |
| 57 | −/* | |
| 58 | − * Translates ISDN4Linux protocol codes to strings for debug messages | |
| 59 | − */ | |
| 60 | −static char *l3protos[] = { "ISDN_PROTO_L3_TRANS" }; | |
| 61 | −static char *l2protos[] = { "ISDN_PROTO_L2_X75I", | |
| 62 | − "ISDN_PROTO_L2_X75UI", | |
| 63 | − "ISDN_PROTO_L2_X75BUI", | |
| 64 | − "ISDN_PROTO_L2_HDLC", | |
| 65 | − "ISDN_PROTO_L2_TRANS" }; | |
| 66 | −#endif | |
| 67 | − | |
| 68 | −int get_card_from_id(int driver) | |
| 69 | −{ | |
| 70 | − int i; | |
| 71 | − | |
| 72 | − for (i = 0; i < cinst; i++) { | |
| 73 | − if (sc_adapter[i]->driverId == driver) | |
| 74 | − return i; | |
| 75 | − } | |
| 76 | − return -ENODEV; | |
| 77 | −} | |
| 78 | − | |
| 79 | −/* | |
| 80 | − * command | |
| 81 | − */ | |
| 82 | − | |
| 83 | −int command(isdn_ctrl *cmd) | |
| 84 | −{ | |
| 85 | − int card; | |
| 86 | − | |
| 87 | − card = get_card_from_id(cmd->driver); | |
| 88 | − if (!IS_VALID_CARD(card)) { | |
| 89 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 90 | − return -ENODEV; | |
| 91 | − } | |
| 92 | − | |
| 93 | − /* | |
| 94 | − * Dispatch the command | |
| 95 | − */ | |
| 96 | − switch (cmd->command) { | |
| 97 | − case ISDN_CMD_IOCTL: | |
| 98 | − { | |
| 99 | − unsigned long cmdptr; | |
| 100 | − scs_ioctl ioc; | |
| 101 | − | |
| 102 | − memcpy(&cmdptr, cmd->parm.num, sizeof(unsigned long)); | |
| 103 | − if (copy_from_user(&ioc, (scs_ioctl __user *)cmdptr, | |
| 104 | − sizeof(scs_ioctl))) { | |
| 105 | − pr_debug("%s: Failed to verify user space 0x%lx\n", | |
| 106 | − sc_adapter[card]->devicename, cmdptr); | |
| 107 | − return -EFAULT; | |
| 108 | − } | |
| 109 | − return sc_ioctl(card, &ioc); | |
| 110 | − } | |
| 111 | − case ISDN_CMD_DIAL: | |
| 112 | − return dial(card, cmd->arg, cmd->parm.setup); | |
| 113 | − case ISDN_CMD_HANGUP: | |
| 114 | − return hangup(card, cmd->arg); | |
| 115 | − case ISDN_CMD_ACCEPTD: | |
| 116 | − return answer(card, cmd->arg); | |
| 117 | − case ISDN_CMD_ACCEPTB: | |
| 118 | − return acceptb(card, cmd->arg); | |
| 119 | − case ISDN_CMD_CLREAZ: | |
| 120 | − return clreaz(card, cmd->arg); | |
| 121 | − case ISDN_CMD_SETEAZ: | |
| 122 | − return seteaz(card, cmd->arg, cmd->parm.num); | |
| 123 | − case ISDN_CMD_SETL2: | |
| 124 | − return setl2(card, cmd->arg); | |
| 125 | − case ISDN_CMD_SETL3: | |
| 126 | − return setl3(card, cmd->arg); | |
| 127 | − default: | |
| 128 | − return -EINVAL; | |
| 129 | − } | |
| 130 | − return 0; | |
| 131 | −} | |
| 132 | − | |
| 133 | −/* | |
| 134 | − * start the onboard firmware | |
| 135 | − */ | |
| 136 | −int startproc(int card) | |
| 137 | −{ | |
| 138 | − int status; | |
| 139 | − | |
| 140 | − if (!IS_VALID_CARD(card)) { | |
| 141 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 142 | − return -ENODEV; | |
| 143 | − } | |
| 144 | − | |
| 145 | − /* | |
| 146 | − * send start msg | |
| 147 | − */ | |
| 148 | − status = sendmessage(card, CMPID, cmReqType2, | |
| 149 | − cmReqClass0, | |
| 150 | − cmReqStartProc, | |
| 151 | − 0, 0, NULL); | |
| 152 | − pr_debug("%s: Sent startProc\n", sc_adapter[card]->devicename); | |
| 153 | − | |
| 154 | − return status; | |
| 155 | −} | |
| 156 | − | |
| 157 | − | |
| 158 | −/* | |
| 159 | − * Dials the number passed in | |
| 160 | − */ | |
| 161 | −static int dial(int card, unsigned long channel, setup_parm setup) | |
| 162 | −{ | |
| 163 | − int status; | |
| 164 | − char Phone[48]; | |
| 165 | − | |
| 166 | − if (!IS_VALID_CARD(card)) { | |
| 167 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 168 | − return -ENODEV; | |
| 169 | − } | |
| 170 | − | |
| 171 | − /*extract ISDN number to dial from eaz/msn string*/ | |
| 172 | − strcpy(Phone, setup.phone); | |
| 173 | − | |
| 174 | − /*send the connection message*/ | |
| 175 | − status = sendmessage(card, CEPID, ceReqTypePhy, | |
| 176 | − ceReqClass1, | |
| 177 | − ceReqPhyConnect, | |
| 178 | − (unsigned char)channel + 1, | |
| 179 | − strlen(Phone), | |
| 180 | − (unsigned int *)Phone); | |
| 181 | − | |
| 182 | − pr_debug("%s: Dialing %s on channel %lu\n", | |
| 183 | − sc_adapter[card]->devicename, Phone, channel + 1); | |
| 184 | − | |
| 185 | − return status; | |
| 186 | −} | |
| 187 | − | |
| 188 | −/* | |
| 189 | − * Answer an incoming call | |
| 190 | − */ | |
| 191 | −static int answer(int card, unsigned long channel) | |
| 192 | −{ | |
| 193 | − if (!IS_VALID_CARD(card)) { | |
| 194 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 195 | − return -ENODEV; | |
| 196 | − } | |
| 197 | − | |
| 198 | − if (setup_buffers(card, channel + 1)) { | |
| 199 | − hangup(card, channel + 1); | |
| 200 | − return -ENOBUFS; | |
| 201 | − } | |
| 202 | − | |
| 203 | − indicate_status(card, ISDN_STAT_BCONN, channel, NULL); | |
| 204 | − pr_debug("%s: Answered incoming call on channel %lu\n", | |
| 205 | − sc_adapter[card]->devicename, channel + 1); | |
| 206 | − return 0; | |
| 207 | −} | |
| 208 | − | |
| 209 | −/* | |
| 210 | − * Hangup up the call on specified channel | |
| 211 | − */ | |
| 212 | −static int hangup(int card, unsigned long channel) | |
| 213 | −{ | |
| 214 | − int status; | |
| 215 | − | |
| 216 | − if (!IS_VALID_CARD(card)) { | |
| 217 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 218 | − return -ENODEV; | |
| 219 | − } | |
| 220 | − | |
| 221 | − status = sendmessage(card, CEPID, ceReqTypePhy, | |
| 222 | − ceReqClass1, | |
| 223 | − ceReqPhyDisconnect, | |
| 224 | − (unsigned char)channel + 1, | |
| 225 | − 0, | |
| 226 | − NULL); | |
| 227 | − pr_debug("%s: Sent HANGUP message to channel %lu\n", | |
| 228 | − sc_adapter[card]->devicename, channel + 1); | |
| 229 | − return status; | |
| 230 | −} | |
| 231 | − | |
| 232 | −/* | |
| 233 | − * Set the layer 2 protocol (X.25, HDLC, Raw) | |
| 234 | − */ | |
| 235 | −static int setl2(int card, unsigned long arg) | |
| 236 | −{ | |
| 237 | − int status = 0; | |
| 238 | − int protocol, channel; | |
| 239 | − | |
| 240 | − if (!IS_VALID_CARD(card)) { | |
| 241 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 242 | − return -ENODEV; | |
| 243 | − } | |
| 244 | − protocol = arg >> 8; | |
| 245 | − channel = arg & 0xff; | |
| 246 | − sc_adapter[card]->channel[channel].l2_proto = protocol; | |
| 247 | − | |
| 248 | − /* | |
| 249 | − * check that the adapter is also set to the correct protocol | |
| 250 | − */ | |
| 251 | − pr_debug("%s: Sending GetFrameFormat for channel %d\n", | |
| 252 | − sc_adapter[card]->devicename, channel + 1); | |
| 253 | − status = sendmessage(card, CEPID, ceReqTypeCall, | |
| 254 | − ceReqClass0, | |
| 255 | − ceReqCallGetFrameFormat, | |
| 256 | − (unsigned char)channel + 1, | |
| 257 | − 1, | |
| 258 | − (unsigned int *)protocol); | |
| 259 | − if (status) | |
| 260 | − return status; | |
| 261 | − return 0; | |
| 262 | −} | |
| 263 | − | |
| 264 | −/* | |
| 265 | − * Set the layer 3 protocol | |
| 266 | − */ | |
| 267 | −static int setl3(int card, unsigned long channel) | |
| 268 | −{ | |
| 269 | − int protocol = channel >> 8; | |
| 270 | − | |
| 271 | − if (!IS_VALID_CARD(card)) { | |
| 272 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 273 | − return -ENODEV; | |
| 274 | − } | |
| 275 | − | |
| 276 | − sc_adapter[card]->channel[channel].l3_proto = protocol; | |
| 277 | − return 0; | |
| 278 | −} | |
| 279 | − | |
| 280 | −static int acceptb(int card, unsigned long channel) | |
| 281 | −{ | |
| 282 | − if (!IS_VALID_CARD(card)) { | |
| 283 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 284 | − return -ENODEV; | |
| 285 | − } | |
| 286 | − | |
| 287 | − if (setup_buffers(card, channel + 1)) | |
| 288 | − { | |
| 289 | − hangup(card, channel + 1); | |
| 290 | − return -ENOBUFS; | |
| 291 | − } | |
| 292 | − | |
| 293 | − pr_debug("%s: B-Channel connection accepted on channel %lu\n", | |
| 294 | − sc_adapter[card]->devicename, channel + 1); | |
| 295 | − indicate_status(card, ISDN_STAT_BCONN, channel, NULL); | |
| 296 | − return 0; | |
| 297 | −} | |
| 298 | − | |
| 299 | −static int clreaz(int card, unsigned long arg) | |
| 300 | −{ | |
| 301 | − if (!IS_VALID_CARD(card)) { | |
| 302 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 303 | − return -ENODEV; | |
| 304 | − } | |
| 305 | − | |
| 306 | − strcpy(sc_adapter[card]->channel[arg].eazlist, ""); | |
| 307 | − sc_adapter[card]->channel[arg].eazclear = 1; | |
| 308 | − pr_debug("%s: EAZ List cleared for channel %lu\n", | |
| 309 | − sc_adapter[card]->devicename, arg + 1); | |
| 310 | − return 0; | |
| 311 | −} | |
| 312 | − | |
| 313 | −static int seteaz(int card, unsigned long arg, char *num) | |
| 314 | −{ | |
| 315 | − if (!IS_VALID_CARD(card)) { | |
| 316 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 317 | − return -ENODEV; | |
| 318 | − } | |
| 319 | − | |
| 320 | − strcpy(sc_adapter[card]->channel[arg].eazlist, num); | |
| 321 | − sc_adapter[card]->channel[arg].eazclear = 0; | |
| 322 | − pr_debug("%s: EAZ list for channel %lu set to: %s\n", | |
| 323 | − sc_adapter[card]->devicename, arg + 1, | |
| 324 | − sc_adapter[card]->channel[arg].eazlist); | |
| 325 | − return 0; | |
| 326 | −} | |
| 327 | − | |
| 328 | −int reset(int card) | |
| 329 | −{ | |
| 330 | − unsigned long flags; | |
| 331 | − | |
| 332 | − if (!IS_VALID_CARD(card)) { | |
| 333 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 334 | − return -ENODEV; | |
| 335 | − } | |
| 336 | − | |
| 337 | − indicate_status(card, ISDN_STAT_STOP, 0, NULL); | |
| 338 | − | |
| 339 | − if (sc_adapter[card]->EngineUp) { | |
| 340 | − del_timer(&sc_adapter[card]->stat_timer); | |
| 341 | − } | |
| 342 | − | |
| 343 | − sc_adapter[card]->EngineUp = 0; | |
| 344 | − | |
| 345 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 346 | − init_timer(&sc_adapter[card]->reset_timer); | |
| 347 | − sc_adapter[card]->reset_timer.function = sc_check_reset; | |
| 348 | − sc_adapter[card]->reset_timer.data = card; | |
| 349 | − sc_adapter[card]->reset_timer.expires = jiffies + CHECKRESET_TIME; | |
| 350 | − add_timer(&sc_adapter[card]->reset_timer); | |
| 351 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 352 | − | |
| 353 | − outb(0x1, sc_adapter[card]->ioport[SFT_RESET]); | |
| 354 | − | |
| 355 | − pr_debug("%s: Adapter Reset\n", sc_adapter[card]->devicename); | |
| 356 | − return 0; | |
| 357 | −} | |
| 358 | − | |
| 359 | −void flushreadfifo(int card) | |
| 360 | −{ | |
| 361 | − while (inb(sc_adapter[card]->ioport[FIFO_STATUS]) & RF_HAS_DATA) | |
| 362 | − inb(sc_adapter[card]->ioport[FIFO_READ]); | |
| 363 | −} | |
| @@ -1,68 +0,0 @@ | ||
| 1 | −/* $Id: event.c,v 1.4.8.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * This software may be used and distributed according to the terms | |
| 6 | − * of the GNU General Public License, incorporated herein by reference. | |
| 7 | − * | |
| 8 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 9 | − * | |
| 10 | − * SpellCaster Telecommunications Inc. | |
| 11 | − * 5621 Finch Avenue East, Unit #3 | |
| 12 | − * Scarborough, Ontario Canada | |
| 13 | − * M1B 2T9 | |
| 14 | − * +1 (416) 297-8565 | |
| 15 | − * +1 (416) 297-6433 Facsimile | |
| 16 | − */ | |
| 17 | − | |
| 18 | −#include "includes.h" | |
| 19 | −#include "hardware.h" | |
| 20 | −#include "message.h" | |
| 21 | −#include "card.h" | |
| 22 | − | |
| 23 | −#ifdef DEBUG | |
| 24 | −static char *events[] = { "ISDN_STAT_STAVAIL", | |
| 25 | − "ISDN_STAT_ICALL", | |
| 26 | − "ISDN_STAT_RUN", | |
| 27 | − "ISDN_STAT_STOP", | |
| 28 | − "ISDN_STAT_DCONN", | |
| 29 | − "ISDN_STAT_BCONN", | |
| 30 | − "ISDN_STAT_DHUP", | |
| 31 | − "ISDN_STAT_BHUP", | |
| 32 | − "ISDN_STAT_CINF", | |
| 33 | − "ISDN_STAT_LOAD", | |
| 34 | − "ISDN_STAT_UNLOAD", | |
| 35 | − "ISDN_STAT_BSENT", | |
| 36 | − "ISDN_STAT_NODCH", | |
| 37 | − "ISDN_STAT_ADDCH", | |
| 38 | − "ISDN_STAT_CAUSE" }; | |
| 39 | −#endif | |
| 40 | − | |
| 41 | −int indicate_status(int card, int event, ulong Channel, char *Data) | |
| 42 | −{ | |
| 43 | − isdn_ctrl cmd; | |
| 44 | − | |
| 45 | −#ifdef DEBUG | |
| 46 | − pr_debug("%s: Indicating event %s on Channel %d\n", | |
| 47 | − sc_adapter[card]->devicename, events[event - 256], Channel); | |
| 48 | −#endif | |
| 49 | − if (Data != NULL) { | |
| 50 | − pr_debug("%s: Event data: %s\n", sc_adapter[card]->devicename, | |
| 51 | − Data); | |
| 52 | − switch (event) { | |
| 53 | − case ISDN_STAT_BSENT: | |
| 54 | − memcpy(&cmd.parm.length, Data, sizeof(cmd.parm.length)); | |
| 55 | − break; | |
| 56 | − case ISDN_STAT_ICALL: | |
| 57 | − memcpy(&cmd.parm.setup, Data, sizeof(cmd.parm.setup)); | |
| 58 | − break; | |
| 59 | − default: | |
| 60 | − strlcpy(cmd.parm.num, Data, sizeof(cmd.parm.num)); | |
| 61 | − } | |
| 62 | − } | |
| 63 | − | |
| 64 | − cmd.command = event; | |
| 65 | − cmd.driver = sc_adapter[card]->driverId; | |
| 66 | − cmd.arg = Channel; | |
| 67 | − return sc_adapter[card]->card->statcallb(&cmd); | |
| 68 | −} | |
| @@ -1,110 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Hardware specific macros, defines and structures | |
| 3 | − * | |
| 4 | − * This software may be used and distributed according to the terms | |
| 5 | − * of the GNU General Public License, incorporated herein by reference. | |
| 6 | − * | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#ifndef HARDWARE_H | |
| 10 | −#define HARDWARE_H | |
| 11 | − | |
| 12 | −#include <asm/param.h> /* For HZ */ | |
| 13 | − | |
| 14 | −/* | |
| 15 | − * General hardware parameters common to all ISA adapters | |
| 16 | − */ | |
| 17 | − | |
| 18 | −#define MAX_CARDS 4 /* The maximum number of cards to | |
| 19 | − control or probe for. */ | |
| 20 | − | |
| 21 | −#define SIGNATURE 0x87654321 /* Board reset signature */ | |
| 22 | −#define SIG_OFFSET 0x1004 /* Where to find signature in shared RAM */ | |
| 23 | −#define TRACE_OFFSET 0x1008 /* Trace enable word offset in shared RAM */ | |
| 24 | −#define BUFFER_OFFSET 0x1800 /* Beginning of buffers */ | |
| 25 | − | |
| 26 | −/* I/O Port parameters */ | |
| 27 | −#define IOBASE_MIN 0x180 /* Lowest I/O port address */ | |
| 28 | −#define IOBASE_MAX 0x3C0 /* Highest I/O port address */ | |
| 29 | −#define IOBASE_OFFSET 0x20 /* Inter-board I/O port gap used during | |
| 30 | − probing */ | |
| 31 | −#define FIFORD_OFFSET 0x0 | |
| 32 | −#define FIFOWR_OFFSET 0x400 | |
| 33 | −#define FIFOSTAT_OFFSET 0x1000 | |
| 34 | −#define RESET_OFFSET 0x2800 | |
| 35 | −#define PG0_OFFSET 0x3000 /* Offset from I/O Base for Page 0 register */ | |
| 36 | −#define PG1_OFFSET 0x3400 /* Offset from I/O Base for Page 1 register */ | |
| 37 | −#define PG2_OFFSET 0x3800 /* Offset from I/O Base for Page 2 register */ | |
| 38 | −#define PG3_OFFSET 0x3C00 /* Offset from I/O Base for Page 3 register */ | |
| 39 | − | |
| 40 | −#define FIFO_READ 0 /* FIFO Read register */ | |
| 41 | −#define FIFO_WRITE 1 /* FIFO Write rgister */ | |
| 42 | −#define LO_ADDR_PTR 2 /* Extended RAM Low Addr Pointer */ | |
| 43 | −#define HI_ADDR_PTR 3 /* Extended RAM High Addr Pointer */ | |
| 44 | −#define NOT_USED_1 4 | |
| 45 | −#define FIFO_STATUS 5 /* FIFO Status Register */ | |
| 46 | −#define NOT_USED_2 6 | |
| 47 | −#define MEM_OFFSET 7 | |
| 48 | −#define SFT_RESET 10 /* Reset Register */ | |
| 49 | −#define EXP_BASE 11 /* Shared RAM Base address */ | |
| 50 | −#define EXP_PAGE0 12 /* Shared RAM Page0 register */ | |
| 51 | −#define EXP_PAGE1 13 /* Shared RAM Page1 register */ | |
| 52 | −#define EXP_PAGE2 14 /* Shared RAM Page2 register */ | |
| 53 | −#define EXP_PAGE3 15 /* Shared RAM Page3 register */ | |
| 54 | −#define IRQ_SELECT 16 /* IRQ selection register */ | |
| 55 | −#define MAX_IO_REGS 17 /* Total number of I/O ports */ | |
| 56 | − | |
| 57 | −/* FIFO register values */ | |
| 58 | −#define RF_HAS_DATA 0x01 /* fifo has data */ | |
| 59 | −#define RF_QUART_FULL 0x02 /* fifo quarter full */ | |
| 60 | −#define RF_HALF_FULL 0x04 /* fifo half full */ | |
| 61 | −#define RF_NOT_FULL 0x08 /* fifo not full */ | |
| 62 | −#define WF_HAS_DATA 0x10 /* fifo has data */ | |
| 63 | −#define WF_QUART_FULL 0x20 /* fifo quarter full */ | |
| 64 | −#define WF_HALF_FULL 0x40 /* fifo half full */ | |
| 65 | −#define WF_NOT_FULL 0x80 /* fifo not full */ | |
| 66 | − | |
| 67 | −/* Shared RAM parameters */ | |
| 68 | −#define SRAM_MIN 0xC0000 /* Lowest host shared RAM address */ | |
| 69 | −#define SRAM_MAX 0xEFFFF /* Highest host shared RAM address */ | |
| 70 | −#define SRAM_PAGESIZE 0x4000 /* Size of one RAM page (16K) */ | |
| 71 | − | |
| 72 | −/* Shared RAM buffer parameters */ | |
| 73 | −#define BUFFER_SIZE 0x800 /* The size of a buffer in bytes */ | |
| 74 | −#define BUFFER_BASE BUFFER_OFFSET /* Offset from start of shared RAM | |
| 75 | − where buffer start */ | |
| 76 | −#define BUFFERS_MAX 16 /* Maximum number of send/receive | |
| 77 | − buffers per channel */ | |
| 78 | −#define HDLC_PROTO 0x01 /* Frame Format for Layer 2 */ | |
| 79 | − | |
| 80 | −#define BRI_BOARD 0 | |
| 81 | −#define POTS_BOARD 1 | |
| 82 | −#define PRI_BOARD 2 | |
| 83 | − | |
| 84 | −/* | |
| 85 | − * Specific hardware parameters for the DataCommute/BRI | |
| 86 | − */ | |
| 87 | −#define BRI_CHANNELS 2 /* Number of B channels */ | |
| 88 | −#define BRI_BASEPG_VAL 0x98 | |
| 89 | −#define BRI_MAGIC 0x60000 /* Magic Number */ | |
| 90 | −#define BRI_MEMSIZE 0x10000 /* Amount of RAM (64K) */ | |
| 91 | −#define BRI_PARTNO "72-029" | |
| 92 | −#define BRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS; | |
| 93 | −/* | |
| 94 | − * Specific hardware parameters for the DataCommute/PRI | |
| 95 | − */ | |
| 96 | −#define PRI_CHANNELS 23 /* Number of B channels */ | |
| 97 | −#define PRI_BASEPG_VAL 0x88 | |
| 98 | −#define PRI_MAGIC 0x20000 /* Magic Number */ | |
| 99 | −#define PRI_MEMSIZE 0x100000 /* Amount of RAM (1M) */ | |
| 100 | −#define PRI_PARTNO "72-030" | |
| 101 | −#define PRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS; | |
| 102 | − | |
| 103 | −/* | |
| 104 | − * Some handy macros | |
| 105 | − */ | |
| 106 | − | |
| 107 | −/* Determine if a channel number is valid for the adapter */ | |
| 108 | −#define IS_VALID_CHANNEL(y, x) ((x > 0) && (x <= sc_adapter[y]->channels)) | |
| 109 | − | |
| 110 | −#endif | |
| @@ -1,16 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This software may be used and distributed according to the terms | |
| 3 | − * of the GNU General Public License, incorporated herein by reference. | |
| 4 | − * | |
| 5 | − */ | |
| 6 | − | |
| 7 | −#include <linux/errno.h> | |
| 8 | −#include <asm/io.h> | |
| 9 | −#include <linux/delay.h> | |
| 10 | −#include <linux/kernel.h> | |
| 11 | −#include <linux/slab.h> | |
| 12 | −#include <linux/mm.h> | |
| 13 | −#include <linux/ioport.h> | |
| 14 | −#include <linux/timer.h> | |
| 15 | −#include <linux/wait.h> | |
| 16 | −#include <linux/isdnif.h> | |
| @@ -1,549 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This software may be used and distributed according to the terms | |
| 3 | − * of the GNU General Public License, incorporated herein by reference. | |
| 4 | − * | |
| 5 | − */ | |
| 6 | − | |
| 7 | −#include <linux/module.h> | |
| 8 | −#include <linux/init.h> | |
| 9 | −#include <linux/interrupt.h> | |
| 10 | −#include <linux/delay.h> | |
| 11 | −#include <linux/sched.h> | |
| 12 | −#include <linux/slab.h> | |
| 13 | −#include "includes.h" | |
| 14 | −#include "hardware.h" | |
| 15 | −#include "card.h" | |
| 16 | − | |
| 17 | −MODULE_DESCRIPTION("ISDN4Linux: Driver for Spellcaster card"); | |
| 18 | −MODULE_AUTHOR("Spellcaster Telecommunications Inc."); | |
| 19 | −MODULE_LICENSE("GPL"); | |
| 20 | − | |
| 21 | −board *sc_adapter[MAX_CARDS]; | |
| 22 | −int cinst; | |
| 23 | − | |
| 24 | −static char devname[] = "scX"; | |
| 25 | −static const char version[] = "2.0b1"; | |
| 26 | − | |
| 27 | −static const char *boardname[] = { "DataCommute/BRI", "DataCommute/PRI", "TeleCommute/BRI" }; | |
| 28 | − | |
| 29 | −/* insmod set parameters */ | |
| 30 | −static unsigned int io[] = {0, 0, 0, 0}; | |
| 31 | −static unsigned char irq[] = {0, 0, 0, 0}; | |
| 32 | −static unsigned long ram[] = {0, 0, 0, 0}; | |
| 33 | −static bool do_reset; | |
| 34 | − | |
| 35 | −module_param_array(io, int, NULL, 0); | |
| 36 | −module_param_array(irq, byte, NULL, 0); | |
| 37 | −module_param_array(ram, long, NULL, 0); | |
| 38 | −module_param(do_reset, bool, 0); | |
| 39 | − | |
| 40 | −static int identify_board(unsigned long, unsigned int); | |
| 41 | − | |
| 42 | −static int __init sc_init(void) | |
| 43 | −{ | |
| 44 | − int b = -1; | |
| 45 | − int i, j; | |
| 46 | − int status = -ENODEV; | |
| 47 | − | |
| 48 | − unsigned long memsize = 0; | |
| 49 | − unsigned long features = 0; | |
| 50 | − isdn_if *interface; | |
| 51 | − unsigned char channels; | |
| 52 | − unsigned char pgport; | |
| 53 | − unsigned long magic; | |
| 54 | − int model; | |
| 55 | − int last_base = IOBASE_MIN; | |
| 56 | − int probe_exhasted = 0; | |
| 57 | − | |
| 58 | −#ifdef MODULE | |
| 59 | − pr_info("SpellCaster ISA ISDN Adapter Driver rev. %s Loaded\n", version); | |
| 60 | −#else | |
| 61 | − pr_info("SpellCaster ISA ISDN Adapter Driver rev. %s\n", version); | |
| 62 | −#endif | |
| 63 | − pr_info("Copyright (C) 1996 SpellCaster Telecommunications Inc.\n"); | |
| 64 | − | |
| 65 | − while (b++ < MAX_CARDS - 1) { | |
| 66 | − pr_debug("Probing for adapter #%d\n", b); | |
| 67 | − /* | |
| 68 | − * Initialize reusable variables | |
| 69 | − */ | |
| 70 | − model = -1; | |
| 71 | − magic = 0; | |
| 72 | − channels = 0; | |
| 73 | − pgport = 0; | |
| 74 | − | |
| 75 | − /* | |
| 76 | − * See if we should probe for IO base | |
| 77 | − */ | |
| 78 | − pr_debug("I/O Base for board %d is 0x%x, %s probe\n", b, io[b], | |
| 79 | − io[b] == 0 ? "will" : "won't"); | |
| 80 | − if (io[b]) { | |
| 81 | − /* | |
| 82 | − * No, I/O Base has been provided | |
| 83 | − */ | |
| 84 | − for (i = 0; i < MAX_IO_REGS - 1; i++) { | |
| 85 | − if (!request_region(io[b] + i * 0x400, 1, "sc test")) { | |
| 86 | − pr_debug("request_region for 0x%x failed\n", io[b] + i * 0x400); | |
| 87 | − io[b] = 0; | |
| 88 | − break; | |
| 89 | − } else | |
| 90 | − release_region(io[b] + i * 0x400, 1); | |
| 91 | − } | |
| 92 | − | |
| 93 | − /* | |
| 94 | − * Confirm the I/O Address with a test | |
| 95 | − */ | |
| 96 | − if (io[b] == 0) { | |
| 97 | − pr_debug("I/O Address invalid.\n"); | |
| 98 | − continue; | |
| 99 | − } | |
| 100 | − | |
| 101 | − outb(0x18, io[b] + 0x400 * EXP_PAGE0); | |
| 102 | − if (inb(io[b] + 0x400 * EXP_PAGE0) != 0x18) { | |
| 103 | − pr_debug("I/O Base 0x%x fails test\n", | |
| 104 | − io[b] + 0x400 * EXP_PAGE0); | |
| 105 | − continue; | |
| 106 | − } | |
| 107 | − } else { | |
| 108 | − /* | |
| 109 | − * Yes, probe for I/O Base | |
| 110 | − */ | |
| 111 | − if (probe_exhasted) { | |
| 112 | − pr_debug("All probe addresses exhausted, skipping\n"); | |
| 113 | − continue; | |
| 114 | − } | |
| 115 | − pr_debug("Probing for I/O...\n"); | |
| 116 | − for (i = last_base; i <= IOBASE_MAX; i += IOBASE_OFFSET) { | |
| 117 | − int found_io = 1; | |
| 118 | − if (i == IOBASE_MAX) { | |
| 119 | − probe_exhasted = 1; /* No more addresses to probe */ | |
| 120 | − pr_debug("End of Probes\n"); | |
| 121 | − } | |
| 122 | − last_base = i + IOBASE_OFFSET; | |
| 123 | − pr_debug(" checking 0x%x...", i); | |
| 124 | − for (j = 0; j < MAX_IO_REGS - 1; j++) { | |
| 125 | − if (!request_region(i + j * 0x400, 1, "sc test")) { | |
| 126 | − pr_debug("Failed\n"); | |
| 127 | − found_io = 0; | |
| 128 | − break; | |
| 129 | − } else | |
| 130 | − release_region(i + j * 0x400, 1); | |
| 131 | − } | |
| 132 | − | |
| 133 | − if (found_io) { | |
| 134 | − io[b] = i; | |
| 135 | − outb(0x18, io[b] + 0x400 * EXP_PAGE0); | |
| 136 | − if (inb(io[b] + 0x400 * EXP_PAGE0) != 0x18) { | |
| 137 | − pr_debug("Failed by test\n"); | |
| 138 | − continue; | |
| 139 | − } | |
| 140 | − pr_debug("Passed\n"); | |
| 141 | − break; | |
| 142 | − } | |
| 143 | − } | |
| 144 | − if (probe_exhasted) { | |
| 145 | − continue; | |
| 146 | − } | |
| 147 | − } | |
| 148 | − | |
| 149 | − /* | |
| 150 | − * See if we should probe for shared RAM | |
| 151 | − */ | |
| 152 | − if (do_reset) { | |
| 153 | − pr_debug("Doing a SAFE probe reset\n"); | |
| 154 | − outb(0xFF, io[b] + RESET_OFFSET); | |
| 155 | − msleep_interruptible(10000); | |
| 156 | − } | |
| 157 | − pr_debug("RAM Base for board %d is 0x%lx, %s probe\n", b, | |
| 158 | − ram[b], ram[b] == 0 ? "will" : "won't"); | |
| 159 | − | |
| 160 | − if (ram[b]) { | |
| 161 | − /* | |
| 162 | − * No, the RAM base has been provided | |
| 163 | − * Just look for a signature and ID the | |
| 164 | − * board model | |
| 165 | − */ | |
| 166 | − if (request_region(ram[b], SRAM_PAGESIZE, "sc test")) { | |
| 167 | − pr_debug("request_region for RAM base 0x%lx succeeded\n", ram[b]); | |
| 168 | − model = identify_board(ram[b], io[b]); | |
| 169 | − release_region(ram[b], SRAM_PAGESIZE); | |
| 170 | − } | |
| 171 | − } else { | |
| 172 | − /* | |
| 173 | − * Yes, probe for free RAM and look for | |
| 174 | − * a signature and id the board model | |
| 175 | − */ | |
| 176 | − for (i = SRAM_MIN; i < SRAM_MAX; i += SRAM_PAGESIZE) { | |
| 177 | − pr_debug("Checking RAM address 0x%x...\n", i); | |
| 178 | − if (request_region(i, SRAM_PAGESIZE, "sc test")) { | |
| 179 | − pr_debug(" request_region succeeded\n"); | |
| 180 | − model = identify_board(i, io[b]); | |
| 181 | − release_region(i, SRAM_PAGESIZE); | |
| 182 | − if (model >= 0) { | |
| 183 | − pr_debug(" Identified a %s\n", | |
| 184 | − boardname[model]); | |
| 185 | − ram[b] = i; | |
| 186 | − break; | |
| 187 | − } | |
| 188 | − pr_debug(" Unidentified or inaccessible\n"); | |
| 189 | − continue; | |
| 190 | − } | |
| 191 | − pr_debug(" request failed\n"); | |
| 192 | − } | |
| 193 | − } | |
| 194 | − /* | |
| 195 | − * See if we found free RAM and the board model | |
| 196 | − */ | |
| 197 | − if (!ram[b] || model < 0) { | |
| 198 | − /* | |
| 199 | − * Nope, there was no place in RAM for the | |
| 200 | − * board, or it couldn't be identified | |
| 201 | − */ | |
| 202 | − pr_debug("Failed to find an adapter at 0x%lx\n", ram[b]); | |
| 203 | − continue; | |
| 204 | − } | |
| 205 | − | |
| 206 | − /* | |
| 207 | − * Set the board's magic number, memory size and page register | |
| 208 | − */ | |
| 209 | − switch (model) { | |
| 210 | − case PRI_BOARD: | |
| 211 | − channels = 23; | |
| 212 | − magic = 0x20000; | |
| 213 | − memsize = 0x100000; | |
| 214 | − features = PRI_FEATURES; | |
| 215 | − break; | |
| 216 | − | |
| 217 | − case BRI_BOARD: | |
| 218 | − case POTS_BOARD: | |
| 219 | − channels = 2; | |
| 220 | − magic = 0x60000; | |
| 221 | − memsize = 0x10000; | |
| 222 | − features = BRI_FEATURES; | |
| 223 | − break; | |
| 224 | − } | |
| 225 | − switch (ram[b] >> 12 & 0x0F) { | |
| 226 | − case 0x0: | |
| 227 | − pr_debug("RAM Page register set to EXP_PAGE0\n"); | |
| 228 | − pgport = EXP_PAGE0; | |
| 229 | − break; | |
| 230 | − | |
| 231 | − case 0x4: | |
| 232 | − pr_debug("RAM Page register set to EXP_PAGE1\n"); | |
| 233 | − pgport = EXP_PAGE1; | |
| 234 | − break; | |
| 235 | − | |
| 236 | − case 0x8: | |
| 237 | − pr_debug("RAM Page register set to EXP_PAGE2\n"); | |
| 238 | − pgport = EXP_PAGE2; | |
| 239 | − break; | |
| 240 | − | |
| 241 | − case 0xC: | |
| 242 | − pr_debug("RAM Page register set to EXP_PAGE3\n"); | |
| 243 | − pgport = EXP_PAGE3; | |
| 244 | − break; | |
| 245 | − | |
| 246 | − default: | |
| 247 | − pr_debug("RAM base address doesn't fall on 16K boundary\n"); | |
| 248 | − continue; | |
| 249 | − } | |
| 250 | − | |
| 251 | − pr_debug("current IRQ: %d b: %d\n", irq[b], b); | |
| 252 | − | |
| 253 | − /* | |
| 254 | − * Make sure we got an IRQ | |
| 255 | − */ | |
| 256 | − if (!irq[b]) { | |
| 257 | − /* | |
| 258 | − * No interrupt could be used | |
| 259 | − */ | |
| 260 | − pr_debug("Failed to acquire an IRQ line\n"); | |
| 261 | − continue; | |
| 262 | − } | |
| 263 | − | |
| 264 | − /* | |
| 265 | − * Horray! We found a board, Make sure we can register | |
| 266 | − * it with ISDN4Linux | |
| 267 | − */ | |
| 268 | − interface = kzalloc(sizeof(isdn_if), GFP_KERNEL); | |
| 269 | − if (interface == NULL) { | |
| 270 | − /* | |
| 271 | − * Oops, can't malloc isdn_if | |
| 272 | − */ | |
| 273 | − continue; | |
| 274 | − } | |
| 275 | − | |
| 276 | − interface->owner = THIS_MODULE; | |
| 277 | − interface->hl_hdrlen = 0; | |
| 278 | − interface->channels = channels; | |
| 279 | − interface->maxbufsize = BUFFER_SIZE; | |
| 280 | − interface->features = features; | |
| 281 | − interface->writebuf_skb = sndpkt; | |
| 282 | − interface->writecmd = NULL; | |
| 283 | − interface->command = command; | |
| 284 | − strcpy(interface->id, devname); | |
| 285 | − interface->id[2] = '0' + cinst; | |
| 286 | − | |
| 287 | − /* | |
| 288 | − * Allocate the board structure | |
| 289 | − */ | |
| 290 | − sc_adapter[cinst] = kzalloc(sizeof(board), GFP_KERNEL); | |
| 291 | − if (sc_adapter[cinst] == NULL) { | |
| 292 | − /* | |
| 293 | − * Oops, can't alloc memory for the board | |
| 294 | − */ | |
| 295 | − kfree(interface); | |
| 296 | − continue; | |
| 297 | − } | |
| 298 | − spin_lock_init(&sc_adapter[cinst]->lock); | |
| 299 | − | |
| 300 | − if (!register_isdn(interface)) { | |
| 301 | − /* | |
| 302 | − * Oops, couldn't register for some reason | |
| 303 | − */ | |
| 304 | − kfree(interface); | |
| 305 | − kfree(sc_adapter[cinst]); | |
| 306 | − continue; | |
| 307 | − } | |
| 308 | − | |
| 309 | − sc_adapter[cinst]->card = interface; | |
| 310 | − sc_adapter[cinst]->driverId = interface->channels; | |
| 311 | − strcpy(sc_adapter[cinst]->devicename, interface->id); | |
| 312 | − sc_adapter[cinst]->nChannels = channels; | |
| 313 | − sc_adapter[cinst]->ramsize = memsize; | |
| 314 | − sc_adapter[cinst]->shmem_magic = magic; | |
| 315 | − sc_adapter[cinst]->shmem_pgport = pgport; | |
| 316 | − sc_adapter[cinst]->StartOnReset = 1; | |
| 317 | − | |
| 318 | − /* | |
| 319 | − * Allocate channels status structures | |
| 320 | − */ | |
| 321 | − sc_adapter[cinst]->channel = kzalloc(sizeof(bchan) * channels, GFP_KERNEL); | |
| 322 | − if (sc_adapter[cinst]->channel == NULL) { | |
| 323 | − /* | |
| 324 | − * Oops, can't alloc memory for the channels | |
| 325 | − */ | |
| 326 | − indicate_status(cinst, ISDN_STAT_UNLOAD, 0, NULL); /* Fix me */ | |
| 327 | − kfree(interface); | |
| 328 | − kfree(sc_adapter[cinst]); | |
| 329 | − continue; | |
| 330 | − } | |
| 331 | − | |
| 332 | − /* | |
| 333 | − * Lock down the hardware resources | |
| 334 | − */ | |
| 335 | − sc_adapter[cinst]->interrupt = irq[b]; | |
| 336 | − if (request_irq(sc_adapter[cinst]->interrupt, interrupt_handler, | |
| 337 | − 0, interface->id, | |
| 338 | − (void *)(unsigned long) cinst)) { | |
| 339 | − kfree(sc_adapter[cinst]->channel); | |
| 340 | − indicate_status(cinst, ISDN_STAT_UNLOAD, 0, NULL); /* Fix me */ | |
| 341 | − kfree(interface); | |
| 342 | − kfree(sc_adapter[cinst]); | |
| 343 | − continue; | |
| 344 | − | |
| 345 | − } | |
| 346 | − sc_adapter[cinst]->iobase = io[b]; | |
| 347 | − for (i = 0; i < MAX_IO_REGS - 1; i++) { | |
| 348 | − sc_adapter[cinst]->ioport[i] = io[b] + i * 0x400; | |
| 349 | − request_region(sc_adapter[cinst]->ioport[i], 1, | |
| 350 | − interface->id); | |
| 351 | − pr_debug("Requesting I/O Port %#x\n", | |
| 352 | − sc_adapter[cinst]->ioport[i]); | |
| 353 | − } | |
| 354 | − sc_adapter[cinst]->ioport[IRQ_SELECT] = io[b] + 0x2; | |
| 355 | − request_region(sc_adapter[cinst]->ioport[IRQ_SELECT], 1, | |
| 356 | − interface->id); | |
| 357 | − pr_debug("Requesting I/O Port %#x\n", | |
| 358 | − sc_adapter[cinst]->ioport[IRQ_SELECT]); | |
| 359 | − sc_adapter[cinst]->rambase = ram[b]; | |
| 360 | − request_region(sc_adapter[cinst]->rambase, SRAM_PAGESIZE, | |
| 361 | − interface->id); | |
| 362 | − | |
| 363 | − pr_info(" %s (%d) - %s %d channels IRQ %d, I/O Base 0x%x, RAM Base 0x%lx\n", | |
| 364 | − sc_adapter[cinst]->devicename, | |
| 365 | − sc_adapter[cinst]->driverId, | |
| 366 | − boardname[model], channels, irq[b], io[b], ram[b]); | |
| 367 | − | |
| 368 | − /* | |
| 369 | − * reset the adapter to put things in motion | |
| 370 | − */ | |
| 371 | − reset(cinst); | |
| 372 | − | |
| 373 | − cinst++; | |
| 374 | − status = 0; | |
| 375 | − } | |
| 376 | − if (status) | |
| 377 | − pr_info("Failed to find any adapters, driver unloaded\n"); | |
| 378 | − return status; | |
| 379 | −} | |
| 380 | − | |
| 381 | −static void __exit sc_exit(void) | |
| 382 | −{ | |
| 383 | − int i, j; | |
| 384 | − | |
| 385 | − for (i = 0; i < cinst; i++) { | |
| 386 | − pr_debug("Cleaning up after adapter %d\n", i); | |
| 387 | − /* | |
| 388 | − * kill the timers | |
| 389 | − */ | |
| 390 | − del_timer_sync(&(sc_adapter[i]->reset_timer)); | |
| 391 | − del_timer_sync(&(sc_adapter[i]->stat_timer)); | |
| 392 | − | |
| 393 | − /* | |
| 394 | − * Tell I4L we're toast | |
| 395 | − */ | |
| 396 | − indicate_status(i, ISDN_STAT_STOP, 0, NULL); | |
| 397 | − indicate_status(i, ISDN_STAT_UNLOAD, 0, NULL); | |
| 398 | − | |
| 399 | − /* | |
| 400 | − * Release shared RAM | |
| 401 | − */ | |
| 402 | − release_region(sc_adapter[i]->rambase, SRAM_PAGESIZE); | |
| 403 | − | |
| 404 | − /* | |
| 405 | − * Release the IRQ | |
| 406 | − */ | |
| 407 | − free_irq(sc_adapter[i]->interrupt, NULL); | |
| 408 | − | |
| 409 | − /* | |
| 410 | − * Reset for a clean start | |
| 411 | − */ | |
| 412 | − outb(0xFF, sc_adapter[i]->ioport[SFT_RESET]); | |
| 413 | − | |
| 414 | − /* | |
| 415 | − * Release the I/O Port regions | |
| 416 | − */ | |
| 417 | − for (j = 0; j < MAX_IO_REGS - 1; j++) { | |
| 418 | − release_region(sc_adapter[i]->ioport[j], 1); | |
| 419 | − pr_debug("Releasing I/O Port %#x\n", | |
| 420 | − sc_adapter[i]->ioport[j]); | |
| 421 | − } | |
| 422 | − release_region(sc_adapter[i]->ioport[IRQ_SELECT], 1); | |
| 423 | − pr_debug("Releasing I/O Port %#x\n", | |
| 424 | − sc_adapter[i]->ioport[IRQ_SELECT]); | |
| 425 | − | |
| 426 | − /* | |
| 427 | − * Release any memory we alloced | |
| 428 | − */ | |
| 429 | − kfree(sc_adapter[i]->channel); | |
| 430 | − kfree(sc_adapter[i]->card); | |
| 431 | − kfree(sc_adapter[i]); | |
| 432 | − } | |
| 433 | − pr_info("SpellCaster ISA ISDN Adapter Driver Unloaded.\n"); | |
| 434 | −} | |
| 435 | − | |
| 436 | −static int identify_board(unsigned long rambase, unsigned int iobase) | |
| 437 | −{ | |
| 438 | − unsigned int pgport; | |
| 439 | − unsigned long sig; | |
| 440 | − DualPortMemory *dpm; | |
| 441 | − RspMessage rcvmsg; | |
| 442 | − ReqMessage sndmsg; | |
| 443 | − HWConfig_pl hwci; | |
| 444 | − int x; | |
| 445 | − | |
| 446 | − pr_debug("Attempting to identify adapter @ 0x%lx io 0x%x\n", | |
| 447 | − rambase, iobase); | |
| 448 | − | |
| 449 | − /* | |
| 450 | − * Enable the base pointer | |
| 451 | − */ | |
| 452 | − outb(rambase >> 12, iobase + 0x2c00); | |
| 453 | − | |
| 454 | − switch (rambase >> 12 & 0x0F) { | |
| 455 | − case 0x0: | |
| 456 | − pgport = iobase + PG0_OFFSET; | |
| 457 | − pr_debug("Page Register offset is 0x%x\n", PG0_OFFSET); | |
| 458 | − break; | |
| 459 | − | |
| 460 | − case 0x4: | |
| 461 | − pgport = iobase + PG1_OFFSET; | |
| 462 | − pr_debug("Page Register offset is 0x%x\n", PG1_OFFSET); | |
| 463 | − break; | |
| 464 | − | |
| 465 | − case 0x8: | |
| 466 | − pgport = iobase + PG2_OFFSET; | |
| 467 | − pr_debug("Page Register offset is 0x%x\n", PG2_OFFSET); | |
| 468 | − break; | |
| 469 | − | |
| 470 | − case 0xC: | |
| 471 | − pgport = iobase + PG3_OFFSET; | |
| 472 | − pr_debug("Page Register offset is 0x%x\n", PG3_OFFSET); | |
| 473 | − break; | |
| 474 | − default: | |
| 475 | − pr_debug("Invalid rambase 0x%lx\n", rambase); | |
| 476 | − return -1; | |
| 477 | − } | |
| 478 | − | |
| 479 | − /* | |
| 480 | − * Try to identify a PRI card | |
| 481 | − */ | |
| 482 | − outb(PRI_BASEPG_VAL, pgport); | |
| 483 | − msleep_interruptible(1000); | |
| 484 | − sig = readl(rambase + SIG_OFFSET); | |
| 485 | − pr_debug("Looking for a signature, got 0x%lx\n", sig); | |
| 486 | − if (sig == SIGNATURE) | |
| 487 | − return PRI_BOARD; | |
| 488 | − | |
| 489 | − /* | |
| 490 | − * Try to identify a PRI card | |
| 491 | − */ | |
| 492 | − outb(BRI_BASEPG_VAL, pgport); | |
| 493 | − msleep_interruptible(1000); | |
| 494 | − sig = readl(rambase + SIG_OFFSET); | |
| 495 | − pr_debug("Looking for a signature, got 0x%lx\n", sig); | |
| 496 | − if (sig == SIGNATURE) | |
| 497 | − return BRI_BOARD; | |
| 498 | − | |
| 499 | − return -1; | |
| 500 | − | |
| 501 | − /* | |
| 502 | − * Try to spot a card | |
| 503 | − */ | |
| 504 | − sig = readl(rambase + SIG_OFFSET); | |
| 505 | − pr_debug("Looking for a signature, got 0x%lx\n", sig); | |
| 506 | − if (sig != SIGNATURE) | |
| 507 | − return -1; | |
| 508 | − | |
| 509 | − dpm = (DualPortMemory *) rambase; | |
| 510 | − | |
| 511 | − memset(&sndmsg, 0, MSG_LEN); | |
| 512 | − sndmsg.msg_byte_cnt = 3; | |
| 513 | − sndmsg.type = cmReqType1; | |
| 514 | − sndmsg.class = cmReqClass0; | |
| 515 | − sndmsg.code = cmReqHWConfig; | |
| 516 | − memcpy_toio(&(dpm->req_queue[dpm->req_head++]), &sndmsg, MSG_LEN); | |
| 517 | − outb(0, iobase + 0x400); | |
| 518 | − pr_debug("Sent HWConfig message\n"); | |
| 519 | − /* | |
| 520 | − * Wait for the response | |
| 521 | − */ | |
| 522 | − x = 0; | |
| 523 | − while ((inb(iobase + FIFOSTAT_OFFSET) & RF_HAS_DATA) && x < 100) { | |
| 524 | − schedule_timeout_interruptible(1); | |
| 525 | − x++; | |
| 526 | − } | |
| 527 | − if (x == 100) { | |
| 528 | − pr_debug("Timeout waiting for response\n"); | |
| 529 | − return -1; | |
| 530 | − } | |
| 531 | − | |
| 532 | − memcpy_fromio(&rcvmsg, &(dpm->rsp_queue[dpm->rsp_tail]), MSG_LEN); | |
| 533 | − pr_debug("Got HWConfig response, status = 0x%x\n", rcvmsg.rsp_status); | |
| 534 | − memcpy(&hwci, &(rcvmsg.msg_data.HWCresponse), sizeof(HWConfig_pl)); | |
| 535 | − pr_debug("Hardware Config: Interface: %s, RAM Size: %ld, Serial: %s\n" | |
| 536 | − " Part: %s, Rev: %s\n", | |
| 537 | − hwci.st_u_sense ? "S/T" : "U", hwci.ram_size, | |
| 538 | − hwci.serial_no, hwci.part_no, hwci.rev_no); | |
| 539 | − | |
| 540 | − if (!strncmp(PRI_PARTNO, hwci.part_no, 6)) | |
| 541 | − return PRI_BOARD; | |
| 542 | − if (!strncmp(BRI_PARTNO, hwci.part_no, 6)) | |
| 543 | − return BRI_BOARD; | |
| 544 | − | |
| 545 | − return -1; | |
| 546 | −} | |
| 547 | − | |
| 548 | −module_init(sc_init); | |
| 549 | −module_exit(sc_exit); | |
| @@ -1,247 +0,0 @@ | ||
| 1 | −/* $Id: interrupt.c,v 1.4.8.3 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * This software may be used and distributed according to the terms | |
| 6 | − * of the GNU General Public License, incorporated herein by reference. | |
| 7 | − * | |
| 8 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 9 | − * | |
| 10 | − * SpellCaster Telecommunications Inc. | |
| 11 | − * 5621 Finch Avenue East, Unit #3 | |
| 12 | − * Scarborough, Ontario Canada | |
| 13 | − * M1B 2T9 | |
| 14 | − * +1 (416) 297-8565 | |
| 15 | − * +1 (416) 297-6433 Facsimile | |
| 16 | − */ | |
| 17 | − | |
| 18 | −#include "includes.h" | |
| 19 | −#include "hardware.h" | |
| 20 | −#include "message.h" | |
| 21 | −#include "card.h" | |
| 22 | −#include <linux/interrupt.h> | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * | |
| 26 | − */ | |
| 27 | −irqreturn_t interrupt_handler(int dummy, void *card_inst) | |
| 28 | −{ | |
| 29 | − | |
| 30 | − RspMessage rcvmsg; | |
| 31 | − int channel; | |
| 32 | − int card = (int)(unsigned long) card_inst; | |
| 33 | − | |
| 34 | − if (!IS_VALID_CARD(card)) { | |
| 35 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 36 | − return IRQ_NONE; | |
| 37 | − } | |
| 38 | − | |
| 39 | − pr_debug("%s: Entered Interrupt handler\n", | |
| 40 | − sc_adapter[card]->devicename); | |
| 41 | − | |
| 42 | − /* | |
| 43 | − * Pull all of the waiting messages off the response queue | |
| 44 | − */ | |
| 45 | − while (!receivemessage(card, &rcvmsg)) { | |
| 46 | − /* | |
| 47 | − * Push the message to the adapter structure for | |
| 48 | − * send_and_receive to snoop | |
| 49 | − */ | |
| 50 | − if (sc_adapter[card]->want_async_messages) | |
| 51 | − memcpy(&(sc_adapter[card]->async_msg), | |
| 52 | − &rcvmsg, sizeof(RspMessage)); | |
| 53 | − | |
| 54 | − channel = (unsigned int) rcvmsg.phy_link_no; | |
| 55 | − | |
| 56 | − /* | |
| 57 | − * Trap Invalid request messages | |
| 58 | − */ | |
| 59 | − if (IS_CM_MESSAGE(rcvmsg, 0, 0, Invalid)) { | |
| 60 | − pr_debug("%s: Invalid request Message, rsp_status = %d\n", | |
| 61 | − sc_adapter[card]->devicename, | |
| 62 | − rcvmsg.rsp_status); | |
| 63 | − break; | |
| 64 | − } | |
| 65 | − | |
| 66 | − /* | |
| 67 | − * Check for a linkRead message | |
| 68 | − */ | |
| 69 | − if (IS_CE_MESSAGE(rcvmsg, Lnk, 1, Read)) | |
| 70 | − { | |
| 71 | − pr_debug("%s: Received packet 0x%x bytes long at 0x%lx\n", | |
| 72 | − sc_adapter[card]->devicename, | |
| 73 | − rcvmsg.msg_data.response.msg_len, | |
| 74 | − rcvmsg.msg_data.response.buff_offset); | |
| 75 | − rcvpkt(card, &rcvmsg); | |
| 76 | − continue; | |
| 77 | − | |
| 78 | − } | |
| 79 | − | |
| 80 | − /* | |
| 81 | − * Handle a write acknoledgement | |
| 82 | − */ | |
| 83 | − if (IS_CE_MESSAGE(rcvmsg, Lnk, 1, Write)) { | |
| 84 | − pr_debug("%s: Packet Send ACK on channel %d\n", | |
| 85 | − sc_adapter[card]->devicename, | |
| 86 | − rcvmsg.phy_link_no); | |
| 87 | − sc_adapter[card]->channel[rcvmsg.phy_link_no - 1].free_sendbufs++; | |
| 88 | − continue; | |
| 89 | − } | |
| 90 | − | |
| 91 | − /* | |
| 92 | − * Handle a connection message | |
| 93 | − */ | |
| 94 | − if (IS_CE_MESSAGE(rcvmsg, Phy, 1, Connect)) | |
| 95 | − { | |
| 96 | − unsigned int callid; | |
| 97 | − setup_parm setup; | |
| 98 | − pr_debug("%s: Connect message: line %d: status %d: cause 0x%x\n", | |
| 99 | − sc_adapter[card]->devicename, | |
| 100 | − rcvmsg.phy_link_no, | |
| 101 | − rcvmsg.rsp_status, | |
| 102 | − rcvmsg.msg_data.byte_array[2]); | |
| 103 | − | |
| 104 | − memcpy(&callid, rcvmsg.msg_data.byte_array, sizeof(int)); | |
| 105 | − if (callid >= 0x8000 && callid <= 0xFFFF) | |
| 106 | − { | |
| 107 | − pr_debug("%s: Got Dial-Out Rsp\n", | |
| 108 | − sc_adapter[card]->devicename); | |
| 109 | − indicate_status(card, ISDN_STAT_DCONN, | |
| 110 | − (unsigned long)rcvmsg.phy_link_no - 1, NULL); | |
| 111 | − | |
| 112 | − } | |
| 113 | − else if (callid >= 0x0000 && callid <= 0x7FFF) | |
| 114 | − { | |
| 115 | − int len; | |
| 116 | − | |
| 117 | − pr_debug("%s: Got Incoming Call\n", | |
| 118 | − sc_adapter[card]->devicename); | |
| 119 | − len = strlcpy(setup.phone, &(rcvmsg.msg_data.byte_array[4]), | |
| 120 | − sizeof(setup.phone)); | |
| 121 | − if (len >= sizeof(setup.phone)) | |
| 122 | − continue; | |
| 123 | − len = strlcpy(setup.eazmsn, | |
| 124 | − sc_adapter[card]->channel[rcvmsg.phy_link_no - 1].dn, | |
| 125 | − sizeof(setup.eazmsn)); | |
| 126 | − if (len >= sizeof(setup.eazmsn)) | |
| 127 | − continue; | |
| 128 | − setup.si1 = 7; | |
| 129 | − setup.si2 = 0; | |
| 130 | − setup.plan = 0; | |
| 131 | − setup.screen = 0; | |
| 132 | − | |
| 133 | − indicate_status(card, ISDN_STAT_ICALL, (unsigned long)rcvmsg.phy_link_no - 1, (char *)&setup); | |
| 134 | − indicate_status(card, ISDN_STAT_DCONN, (unsigned long)rcvmsg.phy_link_no - 1, NULL); | |
| 135 | − } | |
| 136 | − continue; | |
| 137 | − } | |
| 138 | − | |
| 139 | − /* | |
| 140 | − * Handle a disconnection message | |
| 141 | − */ | |
| 142 | − if (IS_CE_MESSAGE(rcvmsg, Phy, 1, Disconnect)) | |
| 143 | − { | |
| 144 | − pr_debug("%s: disconnect message: line %d: status %d: cause 0x%x\n", | |
| 145 | − sc_adapter[card]->devicename, | |
| 146 | − rcvmsg.phy_link_no, | |
| 147 | − rcvmsg.rsp_status, | |
| 148 | − rcvmsg.msg_data.byte_array[2]); | |
| 149 | − | |
| 150 | − indicate_status(card, ISDN_STAT_BHUP, (unsigned long)rcvmsg.phy_link_no - 1, NULL); | |
| 151 | − indicate_status(card, ISDN_STAT_DHUP, (unsigned long)rcvmsg.phy_link_no - 1, NULL); | |
| 152 | − continue; | |
| 153 | − | |
| 154 | − } | |
| 155 | − | |
| 156 | − /* | |
| 157 | − * Handle a startProc engine up message | |
| 158 | − */ | |
| 159 | − if (IS_CM_MESSAGE(rcvmsg, 5, 0, MiscEngineUp)) { | |
| 160 | − pr_debug("%s: Received EngineUp message\n", | |
| 161 | − sc_adapter[card]->devicename); | |
| 162 | − sc_adapter[card]->EngineUp = 1; | |
| 163 | − sendmessage(card, CEPID, ceReqTypeCall, ceReqClass0, ceReqCallGetMyNumber, 1, 0, NULL); | |
| 164 | − sendmessage(card, CEPID, ceReqTypeCall, ceReqClass0, ceReqCallGetMyNumber, 2, 0, NULL); | |
| 165 | − init_timer(&sc_adapter[card]->stat_timer); | |
| 166 | − sc_adapter[card]->stat_timer.function = check_phystat; | |
| 167 | − sc_adapter[card]->stat_timer.data = card; | |
| 168 | − sc_adapter[card]->stat_timer.expires = jiffies + CHECKSTAT_TIME; | |
| 169 | − add_timer(&sc_adapter[card]->stat_timer); | |
| 170 | − continue; | |
| 171 | − } | |
| 172 | − | |
| 173 | − /* | |
| 174 | − * Start proc response | |
| 175 | − */ | |
| 176 | − if (IS_CM_MESSAGE(rcvmsg, 2, 0, StartProc)) { | |
| 177 | − pr_debug("%s: StartProc Response Status %d\n", | |
| 178 | − sc_adapter[card]->devicename, | |
| 179 | − rcvmsg.rsp_status); | |
| 180 | − continue; | |
| 181 | − } | |
| 182 | − | |
| 183 | − /* | |
| 184 | − * Handle a GetMyNumber Rsp | |
| 185 | − */ | |
| 186 | − if (IS_CE_MESSAGE(rcvmsg, Call, 0, GetMyNumber)) { | |
| 187 | − strlcpy(sc_adapter[card]->channel[rcvmsg.phy_link_no - 1].dn, | |
| 188 | − rcvmsg.msg_data.byte_array, | |
| 189 | − sizeof(rcvmsg.msg_data.byte_array)); | |
| 190 | − continue; | |
| 191 | − } | |
| 192 | − | |
| 193 | − /* | |
| 194 | − * PhyStatus response | |
| 195 | − */ | |
| 196 | − if (IS_CE_MESSAGE(rcvmsg, Phy, 2, Status)) { | |
| 197 | − unsigned int b1stat, b2stat; | |
| 198 | − | |
| 199 | − /* | |
| 200 | − * Covert the message data to the adapter->phystat code | |
| 201 | − */ | |
| 202 | − b1stat = (unsigned int) rcvmsg.msg_data.byte_array[0]; | |
| 203 | − b2stat = (unsigned int) rcvmsg.msg_data.byte_array[1]; | |
| 204 | − | |
| 205 | − sc_adapter[card]->nphystat = (b2stat >> 8) | b1stat; /* endian?? */ | |
| 206 | − pr_debug("%s: PhyStat is 0x%2x\n", | |
| 207 | − sc_adapter[card]->devicename, | |
| 208 | − sc_adapter[card]->nphystat); | |
| 209 | − continue; | |
| 210 | − } | |
| 211 | − | |
| 212 | − | |
| 213 | − /* | |
| 214 | − * Handle a GetFramFormat | |
| 215 | − */ | |
| 216 | − if (IS_CE_MESSAGE(rcvmsg, Call, 0, GetFrameFormat)) { | |
| 217 | − if (rcvmsg.msg_data.byte_array[0] != HDLC_PROTO) { | |
| 218 | − unsigned int proto = HDLC_PROTO; | |
| 219 | − /* | |
| 220 | − * Set board format to HDLC if it wasn't already | |
| 221 | − */ | |
| 222 | − pr_debug("%s: current frame format: 0x%x, will change to HDLC\n", | |
| 223 | − sc_adapter[card]->devicename, | |
| 224 | − rcvmsg.msg_data.byte_array[0]); | |
| 225 | − sendmessage(card, CEPID, ceReqTypeCall, | |
| 226 | − ceReqClass0, | |
| 227 | − ceReqCallSetFrameFormat, | |
| 228 | − (unsigned char)channel + 1, | |
| 229 | − 1, &proto); | |
| 230 | − } | |
| 231 | − continue; | |
| 232 | − } | |
| 233 | − | |
| 234 | − /* | |
| 235 | − * Hmm... | |
| 236 | − */ | |
| 237 | − pr_debug("%s: Received unhandled message (%d,%d,%d) link %d\n", | |
| 238 | − sc_adapter[card]->devicename, | |
| 239 | − rcvmsg.type, rcvmsg.class, rcvmsg.code, | |
| 240 | − rcvmsg.phy_link_no); | |
| 241 | − | |
| 242 | − } /* while */ | |
| 243 | − | |
| 244 | − pr_debug("%s: Exiting Interrupt Handler\n", | |
| 245 | − sc_adapter[card]->devicename); | |
| 246 | − return IRQ_HANDLED; | |
| 247 | −} | |
| @@ -1,582 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 3 | − * | |
| 4 | − * This software may be used and distributed according to the terms | |
| 5 | − * of the GNU General Public License, incorporated herein by reference. | |
| 6 | − * | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#include "includes.h" | |
| 10 | −#include "hardware.h" | |
| 11 | −#include "message.h" | |
| 12 | −#include "card.h" | |
| 13 | −#include "scioc.h" | |
| 14 | − | |
| 15 | −static int GetStatus(int card, boardInfo *); | |
| 16 | − | |
| 17 | −/* | |
| 18 | − * Process private IOCTL messages (typically from scctrl) | |
| 19 | − */ | |
| 20 | −int sc_ioctl(int card, scs_ioctl *data) | |
| 21 | −{ | |
| 22 | − int status; | |
| 23 | − RspMessage *rcvmsg; | |
| 24 | − char *spid; | |
| 25 | − char *dn; | |
| 26 | − char switchtype; | |
| 27 | − char speed; | |
| 28 | − | |
| 29 | − rcvmsg = kmalloc(sizeof(RspMessage), GFP_KERNEL); | |
| 30 | − if (!rcvmsg) | |
| 31 | − return -ENOMEM; | |
| 32 | − | |
| 33 | − switch (data->command) { | |
| 34 | − case SCIOCRESET: /* Perform a hard reset of the adapter */ | |
| 35 | − { | |
| 36 | − pr_debug("%s: SCIOCRESET: ioctl received\n", | |
| 37 | − sc_adapter[card]->devicename); | |
| 38 | − sc_adapter[card]->StartOnReset = 0; | |
| 39 | − kfree(rcvmsg); | |
| 40 | − return reset(card); | |
| 41 | − } | |
| 42 | − | |
| 43 | − case SCIOCLOAD: | |
| 44 | − { | |
| 45 | − char *srec; | |
| 46 | − | |
| 47 | − srec = kmalloc(SCIOC_SRECSIZE, GFP_KERNEL); | |
| 48 | − if (!srec) { | |
| 49 | − kfree(rcvmsg); | |
| 50 | − return -ENOMEM; | |
| 51 | − } | |
| 52 | − pr_debug("%s: SCIOLOAD: ioctl received\n", | |
| 53 | − sc_adapter[card]->devicename); | |
| 54 | − if (sc_adapter[card]->EngineUp) { | |
| 55 | − pr_debug("%s: SCIOCLOAD: command failed, LoadProc while engine running.\n", | |
| 56 | − sc_adapter[card]->devicename); | |
| 57 | − kfree(rcvmsg); | |
| 58 | − kfree(srec); | |
| 59 | − return -1; | |
| 60 | − } | |
| 61 | − | |
| 62 | − /* | |
| 63 | − * Get the SRec from user space | |
| 64 | − */ | |
| 65 | − if (copy_from_user(srec, data->dataptr, SCIOC_SRECSIZE)) { | |
| 66 | − kfree(rcvmsg); | |
| 67 | − kfree(srec); | |
| 68 | − return -EFAULT; | |
| 69 | − } | |
| 70 | − | |
| 71 | − status = send_and_receive(card, CMPID, cmReqType2, cmReqClass0, cmReqLoadProc, | |
| 72 | − 0, SCIOC_SRECSIZE, srec, rcvmsg, SAR_TIMEOUT); | |
| 73 | − kfree(rcvmsg); | |
| 74 | − kfree(srec); | |
| 75 | − | |
| 76 | − if (status) { | |
| 77 | − pr_debug("%s: SCIOCLOAD: command failed, status = %d\n", | |
| 78 | − sc_adapter[card]->devicename, status); | |
| 79 | − return -1; | |
| 80 | − } | |
| 81 | − else { | |
| 82 | − pr_debug("%s: SCIOCLOAD: command successful\n", | |
| 83 | − sc_adapter[card]->devicename); | |
| 84 | − return 0; | |
| 85 | − } | |
| 86 | − } | |
| 87 | − | |
| 88 | − case SCIOCSTART: | |
| 89 | − { | |
| 90 | − kfree(rcvmsg); | |
| 91 | − pr_debug("%s: SCIOSTART: ioctl received\n", | |
| 92 | − sc_adapter[card]->devicename); | |
| 93 | − if (sc_adapter[card]->EngineUp) { | |
| 94 | − pr_debug("%s: SCIOCSTART: command failed, engine already running.\n", | |
| 95 | − sc_adapter[card]->devicename); | |
| 96 | − return -1; | |
| 97 | − } | |
| 98 | − | |
| 99 | − sc_adapter[card]->StartOnReset = 1; | |
| 100 | − startproc(card); | |
| 101 | − return 0; | |
| 102 | − } | |
| 103 | − | |
| 104 | − case SCIOCSETSWITCH: | |
| 105 | − { | |
| 106 | − pr_debug("%s: SCIOSETSWITCH: ioctl received\n", | |
| 107 | − sc_adapter[card]->devicename); | |
| 108 | − | |
| 109 | − /* | |
| 110 | − * Get the switch type from user space | |
| 111 | − */ | |
| 112 | − if (copy_from_user(&switchtype, data->dataptr, sizeof(char))) { | |
| 113 | − kfree(rcvmsg); | |
| 114 | − return -EFAULT; | |
| 115 | − } | |
| 116 | − | |
| 117 | − pr_debug("%s: SCIOCSETSWITCH: setting switch type to %d\n", | |
| 118 | − sc_adapter[card]->devicename, | |
| 119 | − switchtype); | |
| 120 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, ceReqCallSetSwitchType, | |
| 121 | − 0, sizeof(char), &switchtype, rcvmsg, SAR_TIMEOUT); | |
| 122 | − if (!status && !(rcvmsg->rsp_status)) { | |
| 123 | − pr_debug("%s: SCIOCSETSWITCH: command successful\n", | |
| 124 | − sc_adapter[card]->devicename); | |
| 125 | − kfree(rcvmsg); | |
| 126 | − return 0; | |
| 127 | − } | |
| 128 | − else { | |
| 129 | − pr_debug("%s: SCIOCSETSWITCH: command failed (status = %d)\n", | |
| 130 | − sc_adapter[card]->devicename, status); | |
| 131 | − kfree(rcvmsg); | |
| 132 | − return status; | |
| 133 | − } | |
| 134 | − } | |
| 135 | − | |
| 136 | − case SCIOCGETSWITCH: | |
| 137 | − { | |
| 138 | − pr_debug("%s: SCIOGETSWITCH: ioctl received\n", | |
| 139 | − sc_adapter[card]->devicename); | |
| 140 | − | |
| 141 | − /* | |
| 142 | − * Get the switch type from the board | |
| 143 | − */ | |
| 144 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, | |
| 145 | − ceReqCallGetSwitchType, 0, 0, NULL, rcvmsg, SAR_TIMEOUT); | |
| 146 | − if (!status && !(rcvmsg->rsp_status)) { | |
| 147 | − pr_debug("%s: SCIOCGETSWITCH: command successful\n", | |
| 148 | − sc_adapter[card]->devicename); | |
| 149 | − } | |
| 150 | − else { | |
| 151 | − pr_debug("%s: SCIOCGETSWITCH: command failed (status = %d)\n", | |
| 152 | − sc_adapter[card]->devicename, status); | |
| 153 | − kfree(rcvmsg); | |
| 154 | − return status; | |
| 155 | − } | |
| 156 | − | |
| 157 | − switchtype = rcvmsg->msg_data.byte_array[0]; | |
| 158 | − | |
| 159 | − /* | |
| 160 | − * Package the switch type and send to user space | |
| 161 | − */ | |
| 162 | − if (copy_to_user(data->dataptr, &switchtype, | |
| 163 | − sizeof(char))) { | |
| 164 | − kfree(rcvmsg); | |
| 165 | − return -EFAULT; | |
| 166 | − } | |
| 167 | − | |
| 168 | − kfree(rcvmsg); | |
| 169 | − return 0; | |
| 170 | − } | |
| 171 | − | |
| 172 | − case SCIOCGETSPID: | |
| 173 | − { | |
| 174 | − pr_debug("%s: SCIOGETSPID: ioctl received\n", | |
| 175 | − sc_adapter[card]->devicename); | |
| 176 | − | |
| 177 | − spid = kzalloc(SCIOC_SPIDSIZE, GFP_KERNEL); | |
| 178 | − if (!spid) { | |
| 179 | − kfree(rcvmsg); | |
| 180 | − return -ENOMEM; | |
| 181 | − } | |
| 182 | − /* | |
| 183 | − * Get the spid from the board | |
| 184 | − */ | |
| 185 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, ceReqCallGetSPID, | |
| 186 | − data->channel, 0, NULL, rcvmsg, SAR_TIMEOUT); | |
| 187 | − if (!status) { | |
| 188 | − pr_debug("%s: SCIOCGETSPID: command successful\n", | |
| 189 | − sc_adapter[card]->devicename); | |
| 190 | − } else { | |
| 191 | − pr_debug("%s: SCIOCGETSPID: command failed (status = %d)\n", | |
| 192 | − sc_adapter[card]->devicename, status); | |
| 193 | − kfree(spid); | |
| 194 | − kfree(rcvmsg); | |
| 195 | − return status; | |
| 196 | − } | |
| 197 | − strlcpy(spid, rcvmsg->msg_data.byte_array, SCIOC_SPIDSIZE); | |
| 198 | − | |
| 199 | − /* | |
| 200 | − * Package the switch type and send to user space | |
| 201 | − */ | |
| 202 | − if (copy_to_user(data->dataptr, spid, SCIOC_SPIDSIZE)) { | |
| 203 | − kfree(spid); | |
| 204 | − kfree(rcvmsg); | |
| 205 | − return -EFAULT; | |
| 206 | − } | |
| 207 | − | |
| 208 | − kfree(spid); | |
| 209 | − kfree(rcvmsg); | |
| 210 | − return 0; | |
| 211 | − } | |
| 212 | − | |
| 213 | − case SCIOCSETSPID: | |
| 214 | − { | |
| 215 | − pr_debug("%s: DCBIOSETSPID: ioctl received\n", | |
| 216 | − sc_adapter[card]->devicename); | |
| 217 | − | |
| 218 | − /* | |
| 219 | − * Get the spid from user space | |
| 220 | − */ | |
| 221 | − spid = memdup_user(data->dataptr, SCIOC_SPIDSIZE); | |
| 222 | − if (IS_ERR(spid)) { | |
| 223 | − kfree(rcvmsg); | |
| 224 | − return PTR_ERR(spid); | |
| 225 | − } | |
| 226 | − | |
| 227 | − pr_debug("%s: SCIOCSETSPID: setting channel %d spid to %s\n", | |
| 228 | − sc_adapter[card]->devicename, data->channel, spid); | |
| 229 | − status = send_and_receive(card, CEPID, ceReqTypeCall, | |
| 230 | − ceReqClass0, ceReqCallSetSPID, data->channel, | |
| 231 | − strlen(spid), spid, rcvmsg, SAR_TIMEOUT); | |
| 232 | − if (!status && !(rcvmsg->rsp_status)) { | |
| 233 | − pr_debug("%s: SCIOCSETSPID: command successful\n", | |
| 234 | − sc_adapter[card]->devicename); | |
| 235 | − kfree(rcvmsg); | |
| 236 | − kfree(spid); | |
| 237 | − return 0; | |
| 238 | − } | |
| 239 | − else { | |
| 240 | − pr_debug("%s: SCIOCSETSPID: command failed (status = %d)\n", | |
| 241 | − sc_adapter[card]->devicename, status); | |
| 242 | − kfree(rcvmsg); | |
| 243 | − kfree(spid); | |
| 244 | − return status; | |
| 245 | − } | |
| 246 | − } | |
| 247 | − | |
| 248 | − case SCIOCGETDN: | |
| 249 | − { | |
| 250 | − pr_debug("%s: SCIOGETDN: ioctl received\n", | |
| 251 | − sc_adapter[card]->devicename); | |
| 252 | − | |
| 253 | − /* | |
| 254 | − * Get the dn from the board | |
| 255 | − */ | |
| 256 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, ceReqCallGetMyNumber, | |
| 257 | − data->channel, 0, NULL, rcvmsg, SAR_TIMEOUT); | |
| 258 | − if (!status) { | |
| 259 | − pr_debug("%s: SCIOCGETDN: command successful\n", | |
| 260 | − sc_adapter[card]->devicename); | |
| 261 | − } | |
| 262 | − else { | |
| 263 | − pr_debug("%s: SCIOCGETDN: command failed (status = %d)\n", | |
| 264 | − sc_adapter[card]->devicename, status); | |
| 265 | − kfree(rcvmsg); | |
| 266 | − return status; | |
| 267 | − } | |
| 268 | − | |
| 269 | − dn = kzalloc(SCIOC_DNSIZE, GFP_KERNEL); | |
| 270 | − if (!dn) { | |
| 271 | − kfree(rcvmsg); | |
| 272 | − return -ENOMEM; | |
| 273 | − } | |
| 274 | − strlcpy(dn, rcvmsg->msg_data.byte_array, SCIOC_DNSIZE); | |
| 275 | − kfree(rcvmsg); | |
| 276 | − | |
| 277 | − /* | |
| 278 | − * Package the dn and send to user space | |
| 279 | − */ | |
| 280 | − if (copy_to_user(data->dataptr, dn, SCIOC_DNSIZE)) { | |
| 281 | − kfree(dn); | |
| 282 | − return -EFAULT; | |
| 283 | − } | |
| 284 | − kfree(dn); | |
| 285 | − return 0; | |
| 286 | − } | |
| 287 | − | |
| 288 | − case SCIOCSETDN: | |
| 289 | − { | |
| 290 | − pr_debug("%s: SCIOSETDN: ioctl received\n", | |
| 291 | − sc_adapter[card]->devicename); | |
| 292 | − | |
| 293 | − /* | |
| 294 | − * Get the spid from user space | |
| 295 | − */ | |
| 296 | − dn = memdup_user(data->dataptr, SCIOC_DNSIZE); | |
| 297 | − if (IS_ERR(dn)) { | |
| 298 | − kfree(rcvmsg); | |
| 299 | − return PTR_ERR(dn); | |
| 300 | − } | |
| 301 | − | |
| 302 | − pr_debug("%s: SCIOCSETDN: setting channel %d dn to %s\n", | |
| 303 | − sc_adapter[card]->devicename, data->channel, dn); | |
| 304 | − status = send_and_receive(card, CEPID, ceReqTypeCall, | |
| 305 | − ceReqClass0, ceReqCallSetMyNumber, data->channel, | |
| 306 | − strlen(dn), dn, rcvmsg, SAR_TIMEOUT); | |
| 307 | − if (!status && !(rcvmsg->rsp_status)) { | |
| 308 | − pr_debug("%s: SCIOCSETDN: command successful\n", | |
| 309 | − sc_adapter[card]->devicename); | |
| 310 | − kfree(rcvmsg); | |
| 311 | − kfree(dn); | |
| 312 | − return 0; | |
| 313 | − } | |
| 314 | − else { | |
| 315 | − pr_debug("%s: SCIOCSETDN: command failed (status = %d)\n", | |
| 316 | − sc_adapter[card]->devicename, status); | |
| 317 | − kfree(rcvmsg); | |
| 318 | − kfree(dn); | |
| 319 | − return status; | |
| 320 | − } | |
| 321 | − } | |
| 322 | − | |
| 323 | − case SCIOCTRACE: | |
| 324 | − | |
| 325 | − pr_debug("%s: SCIOTRACE: ioctl received\n", | |
| 326 | − sc_adapter[card]->devicename); | |
| 327 | −/* sc_adapter[card]->trace = !sc_adapter[card]->trace; | |
| 328 | − pr_debug("%s: SCIOCTRACE: tracing turned %s\n", | |
| 329 | − sc_adapter[card]->devicename, | |
| 330 | − sc_adapter[card]->trace ? "ON" : "OFF"); */ | |
| 331 | − break; | |
| 332 | − | |
| 333 | − case SCIOCSTAT: | |
| 334 | − { | |
| 335 | − boardInfo *bi; | |
| 336 | − | |
| 337 | − pr_debug("%s: SCIOSTAT: ioctl received\n", | |
| 338 | − sc_adapter[card]->devicename); | |
| 339 | − | |
| 340 | − bi = kzalloc(sizeof(boardInfo), GFP_KERNEL); | |
| 341 | − if (!bi) { | |
| 342 | − kfree(rcvmsg); | |
| 343 | − return -ENOMEM; | |
| 344 | − } | |
| 345 | − | |
| 346 | − kfree(rcvmsg); | |
| 347 | − GetStatus(card, bi); | |
| 348 | − | |
| 349 | − if (copy_to_user(data->dataptr, bi, sizeof(boardInfo))) { | |
| 350 | − kfree(bi); | |
| 351 | − return -EFAULT; | |
| 352 | − } | |
| 353 | − | |
| 354 | − kfree(bi); | |
| 355 | − return 0; | |
| 356 | − } | |
| 357 | − | |
| 358 | − case SCIOCGETSPEED: | |
| 359 | − { | |
| 360 | − pr_debug("%s: SCIOGETSPEED: ioctl received\n", | |
| 361 | − sc_adapter[card]->devicename); | |
| 362 | − | |
| 363 | − /* | |
| 364 | − * Get the speed from the board | |
| 365 | − */ | |
| 366 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, | |
| 367 | − ceReqCallGetCallType, data->channel, 0, NULL, rcvmsg, SAR_TIMEOUT); | |
| 368 | − if (!status && !(rcvmsg->rsp_status)) { | |
| 369 | − pr_debug("%s: SCIOCGETSPEED: command successful\n", | |
| 370 | − sc_adapter[card]->devicename); | |
| 371 | − } | |
| 372 | − else { | |
| 373 | − pr_debug("%s: SCIOCGETSPEED: command failed (status = %d)\n", | |
| 374 | − sc_adapter[card]->devicename, status); | |
| 375 | − kfree(rcvmsg); | |
| 376 | − return status; | |
| 377 | − } | |
| 378 | − | |
| 379 | − speed = rcvmsg->msg_data.byte_array[0]; | |
| 380 | − | |
| 381 | − kfree(rcvmsg); | |
| 382 | − | |
| 383 | − /* | |
| 384 | − * Package the switch type and send to user space | |
| 385 | − */ | |
| 386 | − | |
| 387 | − if (copy_to_user(data->dataptr, &speed, sizeof(char))) | |
| 388 | − return -EFAULT; | |
| 389 | − | |
| 390 | − return 0; | |
| 391 | − } | |
| 392 | − | |
| 393 | − case SCIOCSETSPEED: | |
| 394 | − pr_debug("%s: SCIOCSETSPEED: ioctl received\n", | |
| 395 | − sc_adapter[card]->devicename); | |
| 396 | − break; | |
| 397 | − | |
| 398 | − case SCIOCLOOPTST: | |
| 399 | − pr_debug("%s: SCIOCLOOPTST: ioctl received\n", | |
| 400 | − sc_adapter[card]->devicename); | |
| 401 | − break; | |
| 402 | − | |
| 403 | − default: | |
| 404 | − kfree(rcvmsg); | |
| 405 | − return -1; | |
| 406 | − } | |
| 407 | − | |
| 408 | − kfree(rcvmsg); | |
| 409 | − return 0; | |
| 410 | −} | |
| 411 | − | |
| 412 | −static int GetStatus(int card, boardInfo *bi) | |
| 413 | −{ | |
| 414 | − RspMessage rcvmsg; | |
| 415 | − int i, status; | |
| 416 | − | |
| 417 | − /* | |
| 418 | − * Fill in some of the basic info about the board | |
| 419 | − */ | |
| 420 | − bi->modelid = sc_adapter[card]->model; | |
| 421 | − strcpy(bi->serial_no, sc_adapter[card]->hwconfig.serial_no); | |
| 422 | − strcpy(bi->part_no, sc_adapter[card]->hwconfig.part_no); | |
| 423 | − bi->iobase = sc_adapter[card]->iobase; | |
| 424 | − bi->rambase = sc_adapter[card]->rambase; | |
| 425 | − bi->irq = sc_adapter[card]->interrupt; | |
| 426 | − bi->ramsize = sc_adapter[card]->hwconfig.ram_size; | |
| 427 | − bi->interface = sc_adapter[card]->hwconfig.st_u_sense; | |
| 428 | − strcpy(bi->load_ver, sc_adapter[card]->load_ver); | |
| 429 | − strcpy(bi->proc_ver, sc_adapter[card]->proc_ver); | |
| 430 | − | |
| 431 | − /* | |
| 432 | − * Get the current PhyStats and LnkStats | |
| 433 | − */ | |
| 434 | − status = send_and_receive(card, CEPID, ceReqTypePhy, ceReqClass2, | |
| 435 | − ceReqPhyStatus, 0, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 436 | − if (!status) { | |
| 437 | − if (sc_adapter[card]->model < PRI_BOARD) { | |
| 438 | − bi->l1_status = rcvmsg.msg_data.byte_array[2]; | |
| 439 | − for (i = 0; i < BRI_CHANNELS; i++) | |
| 440 | − bi->status.bristats[i].phy_stat = | |
| 441 | − rcvmsg.msg_data.byte_array[i]; | |
| 442 | − } | |
| 443 | − else { | |
| 444 | − bi->l1_status = rcvmsg.msg_data.byte_array[0]; | |
| 445 | − bi->l2_status = rcvmsg.msg_data.byte_array[1]; | |
| 446 | − for (i = 0; i < PRI_CHANNELS; i++) | |
| 447 | − bi->status.pristats[i].phy_stat = | |
| 448 | − rcvmsg.msg_data.byte_array[i + 2]; | |
| 449 | − } | |
| 450 | − } | |
| 451 | − | |
| 452 | − /* | |
| 453 | − * Get the call types for each channel | |
| 454 | − */ | |
| 455 | − for (i = 0; i < sc_adapter[card]->nChannels; i++) { | |
| 456 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, | |
| 457 | − ceReqCallGetCallType, 0, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 458 | − if (!status) { | |
| 459 | − if (sc_adapter[card]->model == PRI_BOARD) { | |
| 460 | − bi->status.pristats[i].call_type = | |
| 461 | − rcvmsg.msg_data.byte_array[0]; | |
| 462 | − } | |
| 463 | − else { | |
| 464 | − bi->status.bristats[i].call_type = | |
| 465 | − rcvmsg.msg_data.byte_array[0]; | |
| 466 | − } | |
| 467 | − } | |
| 468 | − } | |
| 469 | − | |
| 470 | − /* | |
| 471 | − * If PRI, get the call states and service states for each channel | |
| 472 | − */ | |
| 473 | − if (sc_adapter[card]->model == PRI_BOARD) { | |
| 474 | − /* | |
| 475 | − * Get the call states | |
| 476 | − */ | |
| 477 | − status = send_and_receive(card, CEPID, ceReqTypeStat, ceReqClass2, | |
| 478 | − ceReqPhyChCallState, 0, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 479 | − if (!status) { | |
| 480 | − for (i = 0; i < PRI_CHANNELS; i++) | |
| 481 | − bi->status.pristats[i].call_state = | |
| 482 | − rcvmsg.msg_data.byte_array[i]; | |
| 483 | − } | |
| 484 | − | |
| 485 | − /* | |
| 486 | − * Get the service states | |
| 487 | − */ | |
| 488 | − status = send_and_receive(card, CEPID, ceReqTypeStat, ceReqClass2, | |
| 489 | − ceReqPhyChServState, 0, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 490 | − if (!status) { | |
| 491 | − for (i = 0; i < PRI_CHANNELS; i++) | |
| 492 | − bi->status.pristats[i].serv_state = | |
| 493 | − rcvmsg.msg_data.byte_array[i]; | |
| 494 | − } | |
| 495 | − | |
| 496 | − /* | |
| 497 | − * Get the link stats for the channels | |
| 498 | − */ | |
| 499 | − for (i = 1; i <= PRI_CHANNELS; i++) { | |
| 500 | − status = send_and_receive(card, CEPID, ceReqTypeLnk, ceReqClass0, | |
| 501 | − ceReqLnkGetStats, i, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 502 | − if (!status) { | |
| 503 | − bi->status.pristats[i - 1].link_stats.tx_good = | |
| 504 | − (unsigned long)rcvmsg.msg_data.byte_array[0]; | |
| 505 | − bi->status.pristats[i - 1].link_stats.tx_bad = | |
| 506 | − (unsigned long)rcvmsg.msg_data.byte_array[4]; | |
| 507 | − bi->status.pristats[i - 1].link_stats.rx_good = | |
| 508 | − (unsigned long)rcvmsg.msg_data.byte_array[8]; | |
| 509 | − bi->status.pristats[i - 1].link_stats.rx_bad = | |
| 510 | − (unsigned long)rcvmsg.msg_data.byte_array[12]; | |
| 511 | − } | |
| 512 | − } | |
| 513 | − | |
| 514 | − /* | |
| 515 | − * Link stats for the D channel | |
| 516 | − */ | |
| 517 | − status = send_and_receive(card, CEPID, ceReqTypeLnk, ceReqClass0, | |
| 518 | − ceReqLnkGetStats, 0, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 519 | − if (!status) { | |
| 520 | − bi->dch_stats.tx_good = (unsigned long)rcvmsg.msg_data.byte_array[0]; | |
| 521 | − bi->dch_stats.tx_bad = (unsigned long)rcvmsg.msg_data.byte_array[4]; | |
| 522 | − bi->dch_stats.rx_good = (unsigned long)rcvmsg.msg_data.byte_array[8]; | |
| 523 | − bi->dch_stats.rx_bad = (unsigned long)rcvmsg.msg_data.byte_array[12]; | |
| 524 | − } | |
| 525 | − | |
| 526 | − return 0; | |
| 527 | − } | |
| 528 | − | |
| 529 | − /* | |
| 530 | − * If BRI or POTS, Get SPID, DN and call types for each channel | |
| 531 | − */ | |
| 532 | − | |
| 533 | − /* | |
| 534 | − * Get the link stats for the channels | |
| 535 | − */ | |
| 536 | − status = send_and_receive(card, CEPID, ceReqTypeLnk, ceReqClass0, | |
| 537 | − ceReqLnkGetStats, 0, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 538 | − if (!status) { | |
| 539 | − bi->dch_stats.tx_good = (unsigned long)rcvmsg.msg_data.byte_array[0]; | |
| 540 | − bi->dch_stats.tx_bad = (unsigned long)rcvmsg.msg_data.byte_array[4]; | |
| 541 | − bi->dch_stats.rx_good = (unsigned long)rcvmsg.msg_data.byte_array[8]; | |
| 542 | − bi->dch_stats.rx_bad = (unsigned long)rcvmsg.msg_data.byte_array[12]; | |
| 543 | − bi->status.bristats[0].link_stats.tx_good = | |
| 544 | − (unsigned long)rcvmsg.msg_data.byte_array[16]; | |
| 545 | − bi->status.bristats[0].link_stats.tx_bad = | |
| 546 | − (unsigned long)rcvmsg.msg_data.byte_array[20]; | |
| 547 | − bi->status.bristats[0].link_stats.rx_good = | |
| 548 | − (unsigned long)rcvmsg.msg_data.byte_array[24]; | |
| 549 | − bi->status.bristats[0].link_stats.rx_bad = | |
| 550 | − (unsigned long)rcvmsg.msg_data.byte_array[28]; | |
| 551 | − bi->status.bristats[1].link_stats.tx_good = | |
| 552 | − (unsigned long)rcvmsg.msg_data.byte_array[32]; | |
| 553 | − bi->status.bristats[1].link_stats.tx_bad = | |
| 554 | − (unsigned long)rcvmsg.msg_data.byte_array[36]; | |
| 555 | − bi->status.bristats[1].link_stats.rx_good = | |
| 556 | − (unsigned long)rcvmsg.msg_data.byte_array[40]; | |
| 557 | − bi->status.bristats[1].link_stats.rx_bad = | |
| 558 | − (unsigned long)rcvmsg.msg_data.byte_array[44]; | |
| 559 | − } | |
| 560 | − | |
| 561 | − /* | |
| 562 | − * Get the SPIDs | |
| 563 | − */ | |
| 564 | − for (i = 0; i < BRI_CHANNELS; i++) { | |
| 565 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, | |
| 566 | − ceReqCallGetSPID, i + 1, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 567 | − if (!status) | |
| 568 | − strcpy(bi->status.bristats[i].spid, rcvmsg.msg_data.byte_array); | |
| 569 | − } | |
| 570 | − | |
| 571 | − /* | |
| 572 | − * Get the DNs | |
| 573 | − */ | |
| 574 | − for (i = 0; i < BRI_CHANNELS; i++) { | |
| 575 | − status = send_and_receive(card, CEPID, ceReqTypeCall, ceReqClass0, | |
| 576 | − ceReqCallGetMyNumber, i + 1, 0, NULL, &rcvmsg, SAR_TIMEOUT); | |
| 577 | − if (!status) | |
| 578 | − strcpy(bi->status.bristats[i].dn, rcvmsg.msg_data.byte_array); | |
| 579 | − } | |
| 580 | − | |
| 581 | − return 0; | |
| 582 | −} | |
| @@ -1,230 +0,0 @@ | ||
| 1 | −/* $Id: message.c,v 1.5.8.2 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * functions for sending and receiving control messages | |
| 4 | − * | |
| 5 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 6 | − * | |
| 7 | − * This software may be used and distributed according to the terms | |
| 8 | − * of the GNU General Public License, incorporated herein by reference. | |
| 9 | − * | |
| 10 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 11 | − * | |
| 12 | − * SpellCaster Telecommunications Inc. | |
| 13 | − * 5621 Finch Avenue East, Unit #3 | |
| 14 | − * Scarborough, Ontario Canada | |
| 15 | − * M1B 2T9 | |
| 16 | − * +1 (416) 297-8565 | |
| 17 | − * +1 (416) 297-6433 Facsimile | |
| 18 | − */ | |
| 19 | −#include <linux/sched.h> | |
| 20 | −#include "includes.h" | |
| 21 | −#include "hardware.h" | |
| 22 | −#include "message.h" | |
| 23 | −#include "card.h" | |
| 24 | − | |
| 25 | −/* | |
| 26 | − * receive a message from the board | |
| 27 | − */ | |
| 28 | −int receivemessage(int card, RspMessage *rspmsg) | |
| 29 | −{ | |
| 30 | − DualPortMemory *dpm; | |
| 31 | − unsigned long flags; | |
| 32 | − | |
| 33 | − if (!IS_VALID_CARD(card)) { | |
| 34 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 35 | − return -EINVAL; | |
| 36 | − } | |
| 37 | − | |
| 38 | − pr_debug("%s: Entered receivemessage\n", | |
| 39 | − sc_adapter[card]->devicename); | |
| 40 | − | |
| 41 | − /* | |
| 42 | − * See if there are messages waiting | |
| 43 | − */ | |
| 44 | − if (inb(sc_adapter[card]->ioport[FIFO_STATUS]) & RF_HAS_DATA) { | |
| 45 | − /* | |
| 46 | − * Map in the DPM to the base page and copy the message | |
| 47 | − */ | |
| 48 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 49 | − outb((sc_adapter[card]->shmem_magic >> 14) | 0x80, | |
| 50 | − sc_adapter[card]->ioport[sc_adapter[card]->shmem_pgport]); | |
| 51 | − dpm = (DualPortMemory *) sc_adapter[card]->rambase; | |
| 52 | − memcpy_fromio(rspmsg, &(dpm->rsp_queue[dpm->rsp_tail]), | |
| 53 | − MSG_LEN); | |
| 54 | − dpm->rsp_tail = (dpm->rsp_tail + 1) % MAX_MESSAGES; | |
| 55 | − inb(sc_adapter[card]->ioport[FIFO_READ]); | |
| 56 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 57 | − /* | |
| 58 | − * Tell the board that the message is received | |
| 59 | − */ | |
| 60 | − pr_debug("%s: Received Message seq:%d pid:%d time:%d cmd:%d " | |
| 61 | − "cnt:%d (type,class,code):(%d,%d,%d) " | |
| 62 | − "link:%d stat:0x%x\n", | |
| 63 | − sc_adapter[card]->devicename, | |
| 64 | − rspmsg->sequence_no, | |
| 65 | − rspmsg->process_id, | |
| 66 | − rspmsg->time_stamp, | |
| 67 | − rspmsg->cmd_sequence_no, | |
| 68 | − rspmsg->msg_byte_cnt, | |
| 69 | − rspmsg->type, | |
| 70 | − rspmsg->class, | |
| 71 | − rspmsg->code, | |
| 72 | − rspmsg->phy_link_no, | |
| 73 | − rspmsg->rsp_status); | |
| 74 | − | |
| 75 | − return 0; | |
| 76 | − } | |
| 77 | − return -ENOMSG; | |
| 78 | −} | |
| 79 | − | |
| 80 | −/* | |
| 81 | − * send a message to the board | |
| 82 | − */ | |
| 83 | −int sendmessage(int card, | |
| 84 | − unsigned int procid, | |
| 85 | − unsigned int type, | |
| 86 | − unsigned int class, | |
| 87 | − unsigned int code, | |
| 88 | − unsigned int link, | |
| 89 | − unsigned int data_len, | |
| 90 | − unsigned int *data) | |
| 91 | −{ | |
| 92 | − DualPortMemory *dpm; | |
| 93 | − ReqMessage sndmsg; | |
| 94 | − unsigned long flags; | |
| 95 | − | |
| 96 | − if (!IS_VALID_CARD(card)) { | |
| 97 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 98 | − return -EINVAL; | |
| 99 | − } | |
| 100 | − | |
| 101 | − /* | |
| 102 | − * Make sure we only send CEPID messages when the engine is up | |
| 103 | − * and CMPID messages when it is down | |
| 104 | − */ | |
| 105 | − if (sc_adapter[card]->EngineUp && procid == CMPID) { | |
| 106 | − pr_debug("%s: Attempt to send CM message with engine up\n", | |
| 107 | − sc_adapter[card]->devicename); | |
| 108 | − return -ESRCH; | |
| 109 | − } | |
| 110 | − | |
| 111 | − if (!sc_adapter[card]->EngineUp && procid == CEPID) { | |
| 112 | − pr_debug("%s: Attempt to send CE message with engine down\n", | |
| 113 | − sc_adapter[card]->devicename); | |
| 114 | − return -ESRCH; | |
| 115 | − } | |
| 116 | − | |
| 117 | − memset(&sndmsg, 0, MSG_LEN); | |
| 118 | − sndmsg.msg_byte_cnt = 4; | |
| 119 | − sndmsg.type = type; | |
| 120 | − sndmsg.class = class; | |
| 121 | − sndmsg.code = code; | |
| 122 | − sndmsg.phy_link_no = link; | |
| 123 | − | |
| 124 | − if (data_len > 0) { | |
| 125 | − if (data_len > MSG_DATA_LEN) | |
| 126 | − data_len = MSG_DATA_LEN; | |
| 127 | − memcpy(&(sndmsg.msg_data), data, data_len); | |
| 128 | − sndmsg.msg_byte_cnt = data_len + 8; | |
| 129 | − } | |
| 130 | − | |
| 131 | − sndmsg.process_id = procid; | |
| 132 | − sndmsg.sequence_no = sc_adapter[card]->seq_no++ % 256; | |
| 133 | − | |
| 134 | − /* | |
| 135 | − * wait for an empty slot in the queue | |
| 136 | − */ | |
| 137 | − while (!(inb(sc_adapter[card]->ioport[FIFO_STATUS]) & WF_NOT_FULL)) | |
| 138 | − udelay(1); | |
| 139 | − | |
| 140 | − /* | |
| 141 | − * Disable interrupts and map in shared memory | |
| 142 | − */ | |
| 143 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 144 | − outb((sc_adapter[card]->shmem_magic >> 14) | 0x80, | |
| 145 | − sc_adapter[card]->ioport[sc_adapter[card]->shmem_pgport]); | |
| 146 | − dpm = (DualPortMemory *) sc_adapter[card]->rambase; /* Fix me */ | |
| 147 | − memcpy_toio(&(dpm->req_queue[dpm->req_head]), &sndmsg, MSG_LEN); | |
| 148 | − dpm->req_head = (dpm->req_head + 1) % MAX_MESSAGES; | |
| 149 | − outb(sndmsg.sequence_no, sc_adapter[card]->ioport[FIFO_WRITE]); | |
| 150 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 151 | − | |
| 152 | − pr_debug("%s: Sent Message seq:%d pid:%d time:%d " | |
| 153 | − "cnt:%d (type,class,code):(%d,%d,%d) " | |
| 154 | − "link:%d\n ", | |
| 155 | − sc_adapter[card]->devicename, | |
| 156 | − sndmsg.sequence_no, | |
| 157 | − sndmsg.process_id, | |
| 158 | − sndmsg.time_stamp, | |
| 159 | − sndmsg.msg_byte_cnt, | |
| 160 | − sndmsg.type, | |
| 161 | − sndmsg.class, | |
| 162 | − sndmsg.code, | |
| 163 | − sndmsg.phy_link_no); | |
| 164 | − | |
| 165 | − return 0; | |
| 166 | −} | |
| 167 | − | |
| 168 | −int send_and_receive(int card, | |
| 169 | − unsigned int procid, | |
| 170 | − unsigned char type, | |
| 171 | − unsigned char class, | |
| 172 | − unsigned char code, | |
| 173 | − unsigned char link, | |
| 174 | − unsigned char data_len, | |
| 175 | − unsigned char *data, | |
| 176 | − RspMessage *mesgdata, | |
| 177 | − int timeout) | |
| 178 | −{ | |
| 179 | − int retval; | |
| 180 | − int tries; | |
| 181 | − | |
| 182 | − if (!IS_VALID_CARD(card)) { | |
| 183 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 184 | − return -EINVAL; | |
| 185 | − } | |
| 186 | − | |
| 187 | − sc_adapter[card]->want_async_messages = 1; | |
| 188 | − retval = sendmessage(card, procid, type, class, code, link, | |
| 189 | − data_len, (unsigned int *) data); | |
| 190 | − | |
| 191 | − if (retval) { | |
| 192 | − pr_debug("%s: SendMessage failed in SAR\n", | |
| 193 | − sc_adapter[card]->devicename); | |
| 194 | − sc_adapter[card]->want_async_messages = 0; | |
| 195 | − return -EIO; | |
| 196 | − } | |
| 197 | − | |
| 198 | − tries = 0; | |
| 199 | − /* wait for the response */ | |
| 200 | − while (tries < timeout) { | |
| 201 | − schedule_timeout_interruptible(1); | |
| 202 | − | |
| 203 | − pr_debug("SAR waiting..\n"); | |
| 204 | − | |
| 205 | − /* | |
| 206 | − * See if we got our message back | |
| 207 | − */ | |
| 208 | − if ((sc_adapter[card]->async_msg.type == type) && | |
| 209 | − (sc_adapter[card]->async_msg.class == class) && | |
| 210 | − (sc_adapter[card]->async_msg.code == code) && | |
| 211 | − (sc_adapter[card]->async_msg.phy_link_no == link)) { | |
| 212 | − | |
| 213 | − /* | |
| 214 | − * Got it! | |
| 215 | − */ | |
| 216 | − pr_debug("%s: Got ASYNC message\n", | |
| 217 | − sc_adapter[card]->devicename); | |
| 218 | − memcpy(mesgdata, &(sc_adapter[card]->async_msg), | |
| 219 | − sizeof(RspMessage)); | |
| 220 | − sc_adapter[card]->want_async_messages = 0; | |
| 221 | − return 0; | |
| 222 | − } | |
| 223 | − | |
| 224 | − tries++; | |
| 225 | − } | |
| 226 | − | |
| 227 | − pr_debug("%s: SAR message timeout\n", sc_adapter[card]->devicename); | |
| 228 | − sc_adapter[card]->want_async_messages = 0; | |
| 229 | − return -ETIME; | |
| 230 | −} | |
| @@ -1,245 +0,0 @@ | ||
| 1 | −/* $Id: message.h,v 1.1.10.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * structures, macros and defines useful for sending | |
| 6 | − * messages to the adapter | |
| 7 | − * | |
| 8 | − * This software may be used and distributed according to the terms | |
| 9 | − * of the GNU General Public License, incorporated herein by reference. | |
| 10 | − * | |
| 11 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 12 | − * | |
| 13 | − * SpellCaster Telecommunications Inc. | |
| 14 | − * 5621 Finch Avenue East, Unit #3 | |
| 15 | − * Scarborough, Ontario Canada | |
| 16 | − * M1B 2T9 | |
| 17 | − * +1 (416) 297-8565 | |
| 18 | − * +1 (416) 297-6433 Facsimile | |
| 19 | − */ | |
| 20 | − | |
| 21 | −/* | |
| 22 | − * Board message macros, defines and structures | |
| 23 | − */ | |
| 24 | − | |
| 25 | −#ifndef MESSAGE_H | |
| 26 | −#define MESSAGE_H | |
| 27 | − | |
| 28 | −#define MAX_MESSAGES 32 /* Maximum messages that can be | |
| 29 | − queued */ | |
| 30 | −#define MSG_DATA_LEN 48 /* Maximum size of message payload */ | |
| 31 | −#define MSG_LEN 64 /* Size of a message */ | |
| 32 | −#define CMPID 0 /* Loader message process ID */ | |
| 33 | −#define CEPID 64 /* Firmware message process ID */ | |
| 34 | − | |
| 35 | −/* | |
| 36 | − * Macro to determine if a message is a loader message | |
| 37 | − */ | |
| 38 | −#define IS_CM_MESSAGE(mesg, tx, cx, dx) \ | |
| 39 | − ((mesg.type == cmRspType##tx) \ | |
| 40 | − && (mesg.class == cmRspClass##cx) \ | |
| 41 | − && (mesg.code == cmRsp##dx)) | |
| 42 | − | |
| 43 | −/* | |
| 44 | − * Macro to determine if a message is a firmware message | |
| 45 | − */ | |
| 46 | −#define IS_CE_MESSAGE(mesg, tx, cx, dx) \ | |
| 47 | − ((mesg.type == ceRspType##tx) \ | |
| 48 | − && (mesg.class == ceRspClass##cx) \ | |
| 49 | − && (mesg.code == ceRsp##tx##dx)) | |
| 50 | − | |
| 51 | −/* | |
| 52 | − * Loader Request and Response Messages | |
| 53 | − */ | |
| 54 | − | |
| 55 | −/* message types */ | |
| 56 | −#define cmReqType1 1 | |
| 57 | −#define cmReqType2 2 | |
| 58 | −#define cmRspType0 0 | |
| 59 | −#define cmRspType1 1 | |
| 60 | −#define cmRspType2 2 | |
| 61 | −#define cmRspType5 5 | |
| 62 | − | |
| 63 | −/* message classes */ | |
| 64 | −#define cmReqClass0 0 | |
| 65 | −#define cmRspClass0 0 | |
| 66 | − | |
| 67 | −/* message codes */ | |
| 68 | −#define cmReqHWConfig 1 /* 1,0,1 */ | |
| 69 | −#define cmReqMsgLpbk 2 /* 1,0,2 */ | |
| 70 | −#define cmReqVersion 3 /* 1,0,3 */ | |
| 71 | −#define cmReqLoadProc 1 /* 2,0,1 */ | |
| 72 | −#define cmReqStartProc 2 /* 2,0,2 */ | |
| 73 | −#define cmReqReadMem 6 /* 2,0,6 */ | |
| 74 | −#define cmRspHWConfig cmReqHWConfig | |
| 75 | −#define cmRspMsgLpbk cmReqMsgLpbk | |
| 76 | −#define cmRspVersion cmReqVersion | |
| 77 | −#define cmRspLoadProc cmReqLoadProc | |
| 78 | −#define cmRspStartProc cmReqStartProc | |
| 79 | −#define cmRspReadMem cmReqReadMem | |
| 80 | −#define cmRspMiscEngineUp 1 /* 5,0,1 */ | |
| 81 | −#define cmRspInvalid 0 /* 0,0,0 */ | |
| 82 | − | |
| 83 | − | |
| 84 | −/* | |
| 85 | − * Firmware Request and Response Messages | |
| 86 | − */ | |
| 87 | − | |
| 88 | −/* message types */ | |
| 89 | −#define ceReqTypePhy 1 | |
| 90 | −#define ceReqTypeLnk 2 | |
| 91 | −#define ceReqTypeCall 3 | |
| 92 | −#define ceReqTypeStat 1 | |
| 93 | −#define ceRspTypeErr 0 | |
| 94 | −#define ceRspTypePhy ceReqTypePhy | |
| 95 | −#define ceRspTypeLnk ceReqTypeLnk | |
| 96 | −#define ceRspTypeCall ceReqTypeCall | |
| 97 | −#define ceRspTypeStat ceReqTypeStat | |
| 98 | − | |
| 99 | −/* message classes */ | |
| 100 | −#define ceReqClass0 0 | |
| 101 | −#define ceReqClass1 1 | |
| 102 | −#define ceReqClass2 2 | |
| 103 | −#define ceReqClass3 3 | |
| 104 | −#define ceRspClass0 ceReqClass0 | |
| 105 | −#define ceRspClass1 ceReqClass1 | |
| 106 | −#define ceRspClass2 ceReqClass2 | |
| 107 | −#define ceRspClass3 ceReqClass3 | |
| 108 | − | |
| 109 | −/* message codes (B) = BRI only, (P) = PRI only, (V) = POTS only */ | |
| 110 | −#define ceReqPhyProcInfo 1 /* 1,0,1 */ | |
| 111 | −#define ceReqPhyConnect 1 /* 1,1,1 */ | |
| 112 | −#define ceReqPhyDisconnect 2 /* 1,1,2 */ | |
| 113 | −#define ceReqPhySetParams 3 /* 1,1,3 (P) */ | |
| 114 | −#define ceReqPhyGetParams 4 /* 1,1,4 (P) */ | |
| 115 | −#define ceReqPhyStatus 1 /* 1,2,1 */ | |
| 116 | −#define ceReqPhyAcfaStatus 2 /* 1,2,2 (P) */ | |
| 117 | −#define ceReqPhyChCallState 3 /* 1,2,3 (P) */ | |
| 118 | −#define ceReqPhyChServState 4 /* 1,2,4 (P) */ | |
| 119 | −#define ceReqPhyRLoopBack 1 /* 1,3,1 */ | |
| 120 | −#define ceRspPhyProcInfo ceReqPhyProcInfo | |
| 121 | −#define ceRspPhyConnect ceReqPhyConnect | |
| 122 | −#define ceRspPhyDisconnect ceReqPhyDisconnect | |
| 123 | −#define ceRspPhySetParams ceReqPhySetParams | |
| 124 | −#define ceRspPhyGetParams ceReqPhyGetParams | |
| 125 | −#define ceRspPhyStatus ceReqPhyStatus | |
| 126 | −#define ceRspPhyAcfaStatus ceReqPhyAcfaStatus | |
| 127 | −#define ceRspPhyChCallState ceReqPhyChCallState | |
| 128 | −#define ceRspPhyChServState ceReqPhyChServState | |
| 129 | −#define ceRspPhyRLoopBack ceReqphyRLoopBack | |
| 130 | −#define ceReqLnkSetParam 1 /* 2,0,1 */ | |
| 131 | −#define ceReqLnkGetParam 2 /* 2,0,2 */ | |
| 132 | −#define ceReqLnkGetStats 3 /* 2,0,3 */ | |
| 133 | −#define ceReqLnkWrite 1 /* 2,1,1 */ | |
| 134 | −#define ceReqLnkRead 2 /* 2,1,2 */ | |
| 135 | −#define ceReqLnkFlush 3 /* 2,1,3 */ | |
| 136 | −#define ceReqLnkWrBufTrc 4 /* 2,1,4 */ | |
| 137 | −#define ceReqLnkRdBufTrc 5 /* 2,1,5 */ | |
| 138 | −#define ceRspLnkSetParam ceReqLnkSetParam | |
| 139 | −#define ceRspLnkGetParam ceReqLnkGetParam | |
| 140 | −#define ceRspLnkGetStats ceReqLnkGetStats | |
| 141 | −#define ceRspLnkWrite ceReqLnkWrite | |
| 142 | −#define ceRspLnkRead ceReqLnkRead | |
| 143 | −#define ceRspLnkFlush ceReqLnkFlush | |
| 144 | −#define ceRspLnkWrBufTrc ceReqLnkWrBufTrc | |
| 145 | −#define ceRspLnkRdBufTrc ceReqLnkRdBufTrc | |
| 146 | −#define ceReqCallSetSwitchType 1 /* 3,0,1 */ | |
| 147 | −#define ceReqCallGetSwitchType 2 /* 3,0,2 */ | |
| 148 | −#define ceReqCallSetFrameFormat 3 /* 3,0,3 */ | |
| 149 | −#define ceReqCallGetFrameFormat 4 /* 3,0,4 */ | |
| 150 | −#define ceReqCallSetCallType 5 /* 3,0,5 */ | |
| 151 | −#define ceReqCallGetCallType 6 /* 3,0,6 */ | |
| 152 | −#define ceReqCallSetSPID 7 /* 3,0,7 (!P) */ | |
| 153 | −#define ceReqCallGetSPID 8 /* 3,0,8 (!P) */ | |
| 154 | −#define ceReqCallSetMyNumber 9 /* 3,0,9 (!P) */ | |
| 155 | −#define ceReqCallGetMyNumber 10 /* 3,0,10 (!P) */ | |
| 156 | −#define ceRspCallSetSwitchType ceReqCallSetSwitchType | |
| 157 | −#define ceRspCallGetSwitchType ceReqCallSetSwitchType | |
| 158 | −#define ceRspCallSetFrameFormat ceReqCallSetFrameFormat | |
| 159 | −#define ceRspCallGetFrameFormat ceReqCallGetFrameFormat | |
| 160 | −#define ceRspCallSetCallType ceReqCallSetCallType | |
| 161 | −#define ceRspCallGetCallType ceReqCallGetCallType | |
| 162 | −#define ceRspCallSetSPID ceReqCallSetSPID | |
| 163 | −#define ceRspCallGetSPID ceReqCallGetSPID | |
| 164 | −#define ceRspCallSetMyNumber ceReqCallSetMyNumber | |
| 165 | −#define ceRspCallGetMyNumber ceReqCallGetMyNumber | |
| 166 | −#define ceRspStatAcfaStatus 2 | |
| 167 | −#define ceRspStat | |
| 168 | −#define ceRspErrError 0 /* 0,0,0 */ | |
| 169 | − | |
| 170 | −/* | |
| 171 | − * Call Types | |
| 172 | − */ | |
| 173 | −#define CALLTYPE_64K 0 | |
| 174 | −#define CALLTYPE_56K 1 | |
| 175 | −#define CALLTYPE_SPEECH 2 | |
| 176 | −#define CALLTYPE_31KHZ 3 | |
| 177 | − | |
| 178 | −/* | |
| 179 | − * Link Level data contains a pointer to and the length of | |
| 180 | − * a buffer in shared RAM. Used by LnkRead and LnkWrite message | |
| 181 | − * types. Part of RspMsgStruct and ReqMsgStruct. | |
| 182 | − */ | |
| 183 | −typedef struct { | |
| 184 | − unsigned long buff_offset; | |
| 185 | − unsigned short msg_len; | |
| 186 | −} LLData; | |
| 187 | − | |
| 188 | − | |
| 189 | −/* | |
| 190 | − * Message payload template for an HWConfig message | |
| 191 | − */ | |
| 192 | −typedef struct { | |
| 193 | − char st_u_sense; | |
| 194 | − char powr_sense; | |
| 195 | − char sply_sense; | |
| 196 | − unsigned char asic_id; | |
| 197 | − long ram_size; | |
| 198 | − char serial_no[13]; | |
| 199 | − char part_no[13]; | |
| 200 | − char rev_no[2]; | |
| 201 | −} HWConfig_pl; | |
| 202 | − | |
| 203 | −/* | |
| 204 | − * A Message | |
| 205 | − */ | |
| 206 | −struct message { | |
| 207 | − unsigned char sequence_no; | |
| 208 | − unsigned char process_id; | |
| 209 | − unsigned char time_stamp; | |
| 210 | − unsigned char cmd_sequence_no; /* Rsp messages only */ | |
| 211 | − unsigned char reserved1[3]; | |
| 212 | − unsigned char msg_byte_cnt; | |
| 213 | − unsigned char type; | |
| 214 | − unsigned char class; | |
| 215 | − unsigned char code; | |
| 216 | − unsigned char phy_link_no; | |
| 217 | − unsigned char rsp_status; /* Rsp messages only */ | |
| 218 | − unsigned char reseved2[3]; | |
| 219 | − union { | |
| 220 | − unsigned char byte_array[MSG_DATA_LEN]; | |
| 221 | − LLData response; | |
| 222 | − HWConfig_pl HWCresponse; | |
| 223 | − } msg_data; | |
| 224 | −}; | |
| 225 | − | |
| 226 | −typedef struct message ReqMessage; /* Request message */ | |
| 227 | −typedef struct message RspMessage; /* Response message */ | |
| 228 | − | |
| 229 | −/* | |
| 230 | − * The first 5010 bytes of shared memory contain the message queues, | |
| 231 | − * indexes and other data. This structure is its template | |
| 232 | − */ | |
| 233 | −typedef struct { | |
| 234 | − volatile ReqMessage req_queue[MAX_MESSAGES]; | |
| 235 | − volatile RspMessage rsp_queue[MAX_MESSAGES]; | |
| 236 | − volatile unsigned char req_head; | |
| 237 | − volatile unsigned char req_tail; | |
| 238 | − volatile unsigned char rsp_head; | |
| 239 | − volatile unsigned char rsp_tail; | |
| 240 | − volatile unsigned long signature; | |
| 241 | − volatile unsigned long trace_enable; | |
| 242 | − volatile unsigned char reserved[4]; | |
| 243 | −} DualPortMemory; | |
| 244 | − | |
| 245 | −#endif | |
| @@ -1,204 +0,0 @@ | ||
| 1 | −/* $Id: packet.c,v 1.5.8.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * This software may be used and distributed according to the terms | |
| 6 | − * of the GNU General Public License, incorporated herein by reference. | |
| 7 | − * | |
| 8 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 9 | − * | |
| 10 | − * SpellCaster Telecommunications Inc. | |
| 11 | − * 5621 Finch Avenue East, Unit #3 | |
| 12 | − * Scarborough, Ontario Canada | |
| 13 | − * M1B 2T9 | |
| 14 | − * +1 (416) 297-8565 | |
| 15 | − * +1 (416) 297-6433 Facsimile | |
| 16 | − */ | |
| 17 | − | |
| 18 | −#include "includes.h" | |
| 19 | −#include "hardware.h" | |
| 20 | −#include "message.h" | |
| 21 | −#include "card.h" | |
| 22 | − | |
| 23 | −int sndpkt(int devId, int channel, int ack, struct sk_buff *data) | |
| 24 | −{ | |
| 25 | − LLData ReqLnkWrite; | |
| 26 | − int status; | |
| 27 | − int card; | |
| 28 | − unsigned long len; | |
| 29 | − | |
| 30 | − card = get_card_from_id(devId); | |
| 31 | − | |
| 32 | − if (!IS_VALID_CARD(card)) { | |
| 33 | − pr_debug("invalid param: %d is not a valid card id\n", card); | |
| 34 | − return -ENODEV; | |
| 35 | − } | |
| 36 | − | |
| 37 | − pr_debug("%s: sndpkt: frst = 0x%lx nxt = %d f = %d n = %d\n", | |
| 38 | − sc_adapter[card]->devicename, | |
| 39 | − sc_adapter[card]->channel[channel].first_sendbuf, | |
| 40 | − sc_adapter[card]->channel[channel].next_sendbuf, | |
| 41 | − sc_adapter[card]->channel[channel].free_sendbufs, | |
| 42 | − sc_adapter[card]->channel[channel].num_sendbufs); | |
| 43 | − | |
| 44 | − if (!sc_adapter[card]->channel[channel].free_sendbufs) { | |
| 45 | − pr_debug("%s: out of TX buffers\n", | |
| 46 | − sc_adapter[card]->devicename); | |
| 47 | − return -EINVAL; | |
| 48 | − } | |
| 49 | − | |
| 50 | − if (data->len > BUFFER_SIZE) { | |
| 51 | − pr_debug("%s: data overflows buffer size (data > buffer)\n", | |
| 52 | − sc_adapter[card]->devicename); | |
| 53 | − return -EINVAL; | |
| 54 | − } | |
| 55 | − | |
| 56 | − ReqLnkWrite.buff_offset = sc_adapter[card]->channel[channel].next_sendbuf * | |
| 57 | − BUFFER_SIZE + sc_adapter[card]->channel[channel].first_sendbuf; | |
| 58 | − ReqLnkWrite.msg_len = data->len; /* sk_buff size */ | |
| 59 | − pr_debug("%s: writing %d bytes to buffer offset 0x%lx\n", | |
| 60 | − sc_adapter[card]->devicename, | |
| 61 | − ReqLnkWrite.msg_len, ReqLnkWrite.buff_offset); | |
| 62 | − memcpy_toshmem(card, (char *)ReqLnkWrite.buff_offset, data->data, ReqLnkWrite.msg_len); | |
| 63 | − | |
| 64 | − /* | |
| 65 | − * sendmessage | |
| 66 | − */ | |
| 67 | − pr_debug("%s: sndpkt size=%d, buf_offset=0x%lx buf_indx=%d\n", | |
| 68 | − sc_adapter[card]->devicename, | |
| 69 | − ReqLnkWrite.msg_len, ReqLnkWrite.buff_offset, | |
| 70 | − sc_adapter[card]->channel[channel].next_sendbuf); | |
| 71 | − | |
| 72 | − status = sendmessage(card, CEPID, ceReqTypeLnk, ceReqClass1, ceReqLnkWrite, | |
| 73 | − channel + 1, sizeof(LLData), (unsigned int *)&ReqLnkWrite); | |
| 74 | − len = data->len; | |
| 75 | − if (status) { | |
| 76 | − pr_debug("%s: failed to send packet, status = %d\n", | |
| 77 | − sc_adapter[card]->devicename, status); | |
| 78 | − return -1; | |
| 79 | − } | |
| 80 | − else { | |
| 81 | − sc_adapter[card]->channel[channel].free_sendbufs--; | |
| 82 | − sc_adapter[card]->channel[channel].next_sendbuf = | |
| 83 | − ++sc_adapter[card]->channel[channel].next_sendbuf == | |
| 84 | − sc_adapter[card]->channel[channel].num_sendbufs ? 0 : | |
| 85 | − sc_adapter[card]->channel[channel].next_sendbuf; | |
| 86 | − pr_debug("%s: packet sent successfully\n", sc_adapter[card]->devicename); | |
| 87 | − dev_kfree_skb(data); | |
| 88 | − indicate_status(card, ISDN_STAT_BSENT, channel, (char *)&len); | |
| 89 | − } | |
| 90 | − return len; | |
| 91 | −} | |
| 92 | − | |
| 93 | −void rcvpkt(int card, RspMessage *rcvmsg) | |
| 94 | −{ | |
| 95 | − LLData newll; | |
| 96 | − struct sk_buff *skb; | |
| 97 | − | |
| 98 | − if (!IS_VALID_CARD(card)) { | |
| 99 | − pr_debug("invalid param: %d is not a valid card id\n", card); | |
| 100 | − return; | |
| 101 | − } | |
| 102 | − | |
| 103 | − switch (rcvmsg->rsp_status) { | |
| 104 | − case 0x01: | |
| 105 | − case 0x02: | |
| 106 | − case 0x70: | |
| 107 | − pr_debug("%s: error status code: 0x%x\n", | |
| 108 | − sc_adapter[card]->devicename, rcvmsg->rsp_status); | |
| 109 | − return; | |
| 110 | − case 0x00: | |
| 111 | − if (!(skb = dev_alloc_skb(rcvmsg->msg_data.response.msg_len))) { | |
| 112 | − printk(KERN_WARNING "%s: rcvpkt out of memory, dropping packet\n", | |
| 113 | − sc_adapter[card]->devicename); | |
| 114 | − return; | |
| 115 | − } | |
| 116 | − skb_put(skb, rcvmsg->msg_data.response.msg_len); | |
| 117 | − pr_debug("%s: getting data from offset: 0x%lx\n", | |
| 118 | − sc_adapter[card]->devicename, | |
| 119 | − rcvmsg->msg_data.response.buff_offset); | |
| 120 | − memcpy_fromshmem(card, | |
| 121 | − skb_put(skb, rcvmsg->msg_data.response.msg_len), | |
| 122 | − (char *)rcvmsg->msg_data.response.buff_offset, | |
| 123 | − rcvmsg->msg_data.response.msg_len); | |
| 124 | − sc_adapter[card]->card->rcvcallb_skb(sc_adapter[card]->driverId, | |
| 125 | − rcvmsg->phy_link_no - 1, skb); | |
| 126 | − | |
| 127 | − case 0x03: | |
| 128 | − /* | |
| 129 | − * Recycle the buffer | |
| 130 | − */ | |
| 131 | − pr_debug("%s: buffer size : %d\n", | |
| 132 | − sc_adapter[card]->devicename, BUFFER_SIZE); | |
| 133 | −/* memset_shmem(card, rcvmsg->msg_data.response.buff_offset, 0, BUFFER_SIZE); */ | |
| 134 | − newll.buff_offset = rcvmsg->msg_data.response.buff_offset; | |
| 135 | − newll.msg_len = BUFFER_SIZE; | |
| 136 | − pr_debug("%s: recycled buffer at offset 0x%lx size %d\n", | |
| 137 | − sc_adapter[card]->devicename, | |
| 138 | − newll.buff_offset, newll.msg_len); | |
| 139 | − sendmessage(card, CEPID, ceReqTypeLnk, ceReqClass1, ceReqLnkRead, | |
| 140 | − rcvmsg->phy_link_no, sizeof(LLData), (unsigned int *)&newll); | |
| 141 | − } | |
| 142 | − | |
| 143 | −} | |
| 144 | − | |
| 145 | −int setup_buffers(int card, int c) | |
| 146 | −{ | |
| 147 | − unsigned int nBuffers, i, cBase; | |
| 148 | − unsigned int buffer_size; | |
| 149 | − LLData RcvBuffOffset; | |
| 150 | − | |
| 151 | − if (!IS_VALID_CARD(card)) { | |
| 152 | − pr_debug("invalid param: %d is not a valid card id\n", card); | |
| 153 | − return -ENODEV; | |
| 154 | − } | |
| 155 | − | |
| 156 | − /* | |
| 157 | − * Calculate the buffer offsets (send/recv/send/recv) | |
| 158 | − */ | |
| 159 | − pr_debug("%s: setting up channel buffer space in shared RAM\n", | |
| 160 | − sc_adapter[card]->devicename); | |
| 161 | − buffer_size = BUFFER_SIZE; | |
| 162 | − nBuffers = ((sc_adapter[card]->ramsize - BUFFER_BASE) / buffer_size) / 2; | |
| 163 | − nBuffers = nBuffers > BUFFERS_MAX ? BUFFERS_MAX : nBuffers; | |
| 164 | − pr_debug("%s: calculating buffer space: %d buffers, %d big\n", | |
| 165 | − sc_adapter[card]->devicename, | |
| 166 | − nBuffers, buffer_size); | |
| 167 | − if (nBuffers < 2) { | |
| 168 | − pr_debug("%s: not enough buffer space\n", | |
| 169 | − sc_adapter[card]->devicename); | |
| 170 | − return -1; | |
| 171 | − } | |
| 172 | − cBase = (nBuffers * buffer_size) * (c - 1); | |
| 173 | − pr_debug("%s: channel buffer offset from shared RAM: 0x%x\n", | |
| 174 | − sc_adapter[card]->devicename, cBase); | |
| 175 | − sc_adapter[card]->channel[c - 1].first_sendbuf = BUFFER_BASE + cBase; | |
| 176 | − sc_adapter[card]->channel[c - 1].num_sendbufs = nBuffers / 2; | |
| 177 | − sc_adapter[card]->channel[c - 1].free_sendbufs = nBuffers / 2; | |
| 178 | − sc_adapter[card]->channel[c - 1].next_sendbuf = 0; | |
| 179 | − pr_debug("%s: send buffer setup complete: first=0x%lx n=%d f=%d, nxt=%d\n", | |
| 180 | − sc_adapter[card]->devicename, | |
| 181 | − sc_adapter[card]->channel[c - 1].first_sendbuf, | |
| 182 | − sc_adapter[card]->channel[c - 1].num_sendbufs, | |
| 183 | − sc_adapter[card]->channel[c - 1].free_sendbufs, | |
| 184 | − sc_adapter[card]->channel[c - 1].next_sendbuf); | |
| 185 | − | |
| 186 | − /* | |
| 187 | − * Prep the receive buffers | |
| 188 | − */ | |
| 189 | − pr_debug("%s: adding %d RecvBuffers:\n", | |
| 190 | − sc_adapter[card]->devicename, nBuffers / 2); | |
| 191 | − for (i = 0; i < nBuffers / 2; i++) { | |
| 192 | − RcvBuffOffset.buff_offset = | |
| 193 | − ((sc_adapter[card]->channel[c - 1].first_sendbuf + | |
| 194 | − (nBuffers / 2) * buffer_size) + (buffer_size * i)); | |
| 195 | − RcvBuffOffset.msg_len = buffer_size; | |
| 196 | − pr_debug("%s: adding RcvBuffer #%d offset=0x%lx sz=%d bufsz:%d\n", | |
| 197 | − sc_adapter[card]->devicename, | |
| 198 | − i + 1, RcvBuffOffset.buff_offset, | |
| 199 | − RcvBuffOffset.msg_len, buffer_size); | |
| 200 | − sendmessage(card, CEPID, ceReqTypeLnk, ceReqClass1, ceReqLnkRead, | |
| 201 | − c, sizeof(LLData), (unsigned int *)&RcvBuffOffset); | |
| 202 | − } | |
| 203 | − return 0; | |
| 204 | −} | |
| @@ -1,110 +0,0 @@ | ||
| 1 | −#ifndef __ISDN_SC_SCIOC_H__ | |
| 2 | −#define __ISDN_SC_SCIOC_H__ | |
| 3 | − | |
| 4 | −/* | |
| 5 | − * This software may be used and distributed according to the terms | |
| 6 | − * of the GNU General Public License, incorporated herein by reference. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −/* | |
| 10 | − * IOCTL Command Codes | |
| 11 | − */ | |
| 12 | −#define SCIOCLOAD 0x01 /* Load a firmware record */ | |
| 13 | −#define SCIOCRESET 0x02 /* Perform hard reset */ | |
| 14 | −#define SCIOCDEBUG 0x03 /* Set debug level */ | |
| 15 | −#define SCIOCREV 0x04 /* Get driver revision(s) */ | |
| 16 | −#define SCIOCSTART 0x05 /* Start the firmware */ | |
| 17 | −#define SCIOCGETSWITCH 0x06 /* Get switch type */ | |
| 18 | −#define SCIOCSETSWITCH 0x07 /* Set switch type */ | |
| 19 | −#define SCIOCGETSPID 0x08 /* Get channel SPID */ | |
| 20 | −#define SCIOCSETSPID 0x09 /* Set channel SPID */ | |
| 21 | −#define SCIOCGETDN 0x0A /* Get channel DN */ | |
| 22 | −#define SCIOCSETDN 0x0B /* Set channel DN */ | |
| 23 | −#define SCIOCTRACE 0x0C /* Toggle trace mode */ | |
| 24 | −#define SCIOCSTAT 0x0D /* Get line status */ | |
| 25 | −#define SCIOCGETSPEED 0x0E /* Set channel speed */ | |
| 26 | −#define SCIOCSETSPEED 0x0F /* Set channel speed */ | |
| 27 | −#define SCIOCLOOPTST 0x10 /* Perform loopback test */ | |
| 28 | − | |
| 29 | −typedef struct { | |
| 30 | − int device; | |
| 31 | − int channel; | |
| 32 | − unsigned long command; | |
| 33 | − void __user *dataptr; | |
| 34 | −} scs_ioctl; | |
| 35 | − | |
| 36 | −/* Size of strings */ | |
| 37 | −#define SCIOC_SPIDSIZE 49 | |
| 38 | −#define SCIOC_DNSIZE SCIOC_SPIDSIZE | |
| 39 | −#define SCIOC_REVSIZE SCIOC_SPIDSIZE | |
| 40 | −#define SCIOC_SRECSIZE 49 | |
| 41 | − | |
| 42 | −typedef struct { | |
| 43 | − unsigned long tx_good; | |
| 44 | − unsigned long tx_bad; | |
| 45 | − unsigned long rx_good; | |
| 46 | − unsigned long rx_bad; | |
| 47 | −} ChLinkStats; | |
| 48 | − | |
| 49 | −typedef struct { | |
| 50 | − char spid[49]; | |
| 51 | − char dn[49]; | |
| 52 | − char call_type; | |
| 53 | − char phy_stat; | |
| 54 | − ChLinkStats link_stats; | |
| 55 | −} BRIStat; | |
| 56 | − | |
| 57 | −typedef BRIStat POTStat; | |
| 58 | − | |
| 59 | −typedef struct { | |
| 60 | − char call_type; | |
| 61 | − char call_state; | |
| 62 | − char serv_state; | |
| 63 | − char phy_stat; | |
| 64 | − ChLinkStats link_stats; | |
| 65 | −} PRIStat; | |
| 66 | − | |
| 67 | −typedef char PRIInfo; | |
| 68 | −typedef char BRIInfo; | |
| 69 | −typedef char POTInfo; | |
| 70 | − | |
| 71 | − | |
| 72 | −typedef struct { | |
| 73 | − char acfa_nos; | |
| 74 | − char acfa_ais; | |
| 75 | − char acfa_los; | |
| 76 | − char acfa_rra; | |
| 77 | − char acfa_slpp; | |
| 78 | − char acfa_slpn; | |
| 79 | − char acfa_fsrf; | |
| 80 | −} ACFAStat; | |
| 81 | − | |
| 82 | −typedef struct { | |
| 83 | − unsigned char modelid; | |
| 84 | − char serial_no[13]; | |
| 85 | − char part_no[13]; | |
| 86 | − char load_ver[11]; | |
| 87 | − char proc_ver[11]; | |
| 88 | − int iobase; | |
| 89 | − long rambase; | |
| 90 | − char irq; | |
| 91 | − long ramsize; | |
| 92 | − char interface; | |
| 93 | − char switch_type; | |
| 94 | − char l1_status; | |
| 95 | − char l2_status; | |
| 96 | − ChLinkStats dch_stats; | |
| 97 | − ACFAStat AcfaStats; | |
| 98 | − union { | |
| 99 | − PRIStat pristats[23]; | |
| 100 | − BRIStat bristats[2]; | |
| 101 | − POTStat potsstats[2]; | |
| 102 | − } status; | |
| 103 | − union { | |
| 104 | − PRIInfo priinfo; | |
| 105 | − BRIInfo briinfo; | |
| 106 | − POTInfo potsinfo; | |
| 107 | − } info; | |
| 108 | −} boardInfo; | |
| 109 | − | |
| 110 | −#endif /* __ISDN_SC_SCIOC_H__ */ | |
| @@ -1,138 +0,0 @@ | ||
| 1 | −/* $Id: shmem.c,v 1.2.10.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * Card functions implementing ISDN4Linux functionality | |
| 6 | − * | |
| 7 | − * This software may be used and distributed according to the terms | |
| 8 | − * of the GNU General Public License, incorporated herein by reference. | |
| 9 | − * | |
| 10 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 11 | − * | |
| 12 | − * SpellCaster Telecommunications Inc. | |
| 13 | − * 5621 Finch Avenue East, Unit #3 | |
| 14 | − * Scarborough, Ontario Canada | |
| 15 | − * M1B 2T9 | |
| 16 | − * +1 (416) 297-8565 | |
| 17 | − * +1 (416) 297-6433 Facsimile | |
| 18 | − */ | |
| 19 | − | |
| 20 | −#include "includes.h" /* This must be first */ | |
| 21 | −#include "hardware.h" | |
| 22 | −#include "card.h" | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * | |
| 26 | − */ | |
| 27 | −void memcpy_toshmem(int card, void *dest, const void *src, size_t n) | |
| 28 | −{ | |
| 29 | − unsigned long flags; | |
| 30 | − unsigned char ch; | |
| 31 | − unsigned long dest_rem = ((unsigned long) dest) % 0x4000; | |
| 32 | − | |
| 33 | − if (!IS_VALID_CARD(card)) { | |
| 34 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 35 | − return; | |
| 36 | − } | |
| 37 | − | |
| 38 | − if (n > SRAM_PAGESIZE) | |
| 39 | − return; | |
| 40 | − | |
| 41 | − /* | |
| 42 | − * determine the page to load from the address | |
| 43 | − */ | |
| 44 | − ch = (unsigned long) dest / SRAM_PAGESIZE; | |
| 45 | − pr_debug("%s: loaded page %d\n", sc_adapter[card]->devicename, ch); | |
| 46 | − /* | |
| 47 | − * Block interrupts and load the page | |
| 48 | − */ | |
| 49 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 50 | − | |
| 51 | − outb(((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE) >> 14) | 0x80, | |
| 52 | − sc_adapter[card]->ioport[sc_adapter[card]->shmem_pgport]); | |
| 53 | − memcpy_toio((void __iomem *)(sc_adapter[card]->rambase + dest_rem), src, n); | |
| 54 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 55 | − pr_debug("%s: set page to %#x\n", sc_adapter[card]->devicename, | |
| 56 | − ((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE) >> 14) | 0x80); | |
| 57 | − pr_debug("%s: copying %zu bytes from %#lx to %#lx\n", | |
| 58 | − sc_adapter[card]->devicename, n, | |
| 59 | − (unsigned long) src, | |
| 60 | − sc_adapter[card]->rambase + ((unsigned long) dest % 0x4000)); | |
| 61 | −} | |
| 62 | − | |
| 63 | −/* | |
| 64 | − * Reverse of above | |
| 65 | − */ | |
| 66 | −void memcpy_fromshmem(int card, void *dest, const void *src, size_t n) | |
| 67 | −{ | |
| 68 | − unsigned long flags; | |
| 69 | − unsigned char ch; | |
| 70 | − | |
| 71 | − if (!IS_VALID_CARD(card)) { | |
| 72 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 73 | − return; | |
| 74 | − } | |
| 75 | − | |
| 76 | − if (n > SRAM_PAGESIZE) { | |
| 77 | − return; | |
| 78 | − } | |
| 79 | − | |
| 80 | − /* | |
| 81 | − * determine the page to load from the address | |
| 82 | − */ | |
| 83 | − ch = (unsigned long) src / SRAM_PAGESIZE; | |
| 84 | − pr_debug("%s: loaded page %d\n", sc_adapter[card]->devicename, ch); | |
| 85 | − | |
| 86 | − | |
| 87 | − /* | |
| 88 | − * Block interrupts and load the page | |
| 89 | − */ | |
| 90 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 91 | − | |
| 92 | − outb(((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE) >> 14) | 0x80, | |
| 93 | − sc_adapter[card]->ioport[sc_adapter[card]->shmem_pgport]); | |
| 94 | − memcpy_fromio(dest, (void *)(sc_adapter[card]->rambase + | |
| 95 | − ((unsigned long) src % 0x4000)), n); | |
| 96 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 97 | − pr_debug("%s: set page to %#x\n", sc_adapter[card]->devicename, | |
| 98 | − ((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE) >> 14) | 0x80); | |
| 99 | −/* pr_debug("%s: copying %d bytes from %#x to %#x\n", | |
| 100 | − sc_adapter[card]->devicename, n, | |
| 101 | − sc_adapter[card]->rambase + ((unsigned long) src %0x4000), (unsigned long) dest); */ | |
| 102 | −} | |
| 103 | − | |
| 104 | −#if 0 | |
| 105 | −void memset_shmem(int card, void *dest, int c, size_t n) | |
| 106 | −{ | |
| 107 | − unsigned long flags; | |
| 108 | − unsigned char ch; | |
| 109 | − | |
| 110 | − if (!IS_VALID_CARD(card)) { | |
| 111 | − pr_debug("Invalid param: %d is not a valid card id\n", card); | |
| 112 | − return; | |
| 113 | − } | |
| 114 | − | |
| 115 | − if (n > SRAM_PAGESIZE) { | |
| 116 | − return; | |
| 117 | − } | |
| 118 | − | |
| 119 | − /* | |
| 120 | − * determine the page to load from the address | |
| 121 | − */ | |
| 122 | − ch = (unsigned long) dest / SRAM_PAGESIZE; | |
| 123 | − pr_debug("%s: loaded page %d\n", sc_adapter[card]->devicename, ch); | |
| 124 | − | |
| 125 | − /* | |
| 126 | − * Block interrupts and load the page | |
| 127 | − */ | |
| 128 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 129 | − | |
| 130 | − outb(((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE) >> 14) | 0x80, | |
| 131 | − sc_adapter[card]->ioport[sc_adapter[card]->shmem_pgport]); | |
| 132 | − memset_io(sc_adapter[card]->rambase + | |
| 133 | − ((unsigned long) dest % 0x4000), c, n); | |
| 134 | − pr_debug("%s: set page to %#x\n", sc_adapter[card]->devicename, | |
| 135 | − ((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE) >> 14) | 0x80); | |
| 136 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 137 | −} | |
| 138 | −#endif /* 0 */ | |
| @@ -1,122 +0,0 @@ | ||
| 1 | −/* $Id: timer.c,v 1.3.6.1 2001/09/23 22:24:59 kai Exp $ | |
| 2 | − * | |
| 3 | − * Copyright (C) 1996 SpellCaster Telecommunications Inc. | |
| 4 | − * | |
| 5 | − * This software may be used and distributed according to the terms | |
| 6 | − * of the GNU General Public License, incorporated herein by reference. | |
| 7 | − * | |
| 8 | − * For more information, please contact gpl-info@spellcast.com or write: | |
| 9 | − * | |
| 10 | − * SpellCaster Telecommunications Inc. | |
| 11 | − * 5621 Finch Avenue East, Unit #3 | |
| 12 | − * Scarborough, Ontario Canada | |
| 13 | − * M1B 2T9 | |
| 14 | − * +1 (416) 297-8565 | |
| 15 | − * +1 (416) 297-6433 Facsimile | |
| 16 | − */ | |
| 17 | − | |
| 18 | −#include "includes.h" | |
| 19 | −#include "hardware.h" | |
| 20 | −#include "message.h" | |
| 21 | −#include "card.h" | |
| 22 | − | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * Write the proper values into the I/O ports following a reset | |
| 26 | − */ | |
| 27 | −static void setup_ports(int card) | |
| 28 | −{ | |
| 29 | − | |
| 30 | − outb((sc_adapter[card]->rambase >> 12), sc_adapter[card]->ioport[EXP_BASE]); | |
| 31 | − | |
| 32 | − /* And the IRQ */ | |
| 33 | − outb((sc_adapter[card]->interrupt | 0x80), | |
| 34 | − sc_adapter[card]->ioport[IRQ_SELECT]); | |
| 35 | −} | |
| 36 | − | |
| 37 | −/* | |
| 38 | − * Timed function to check the status of a previous reset | |
| 39 | − * Must be very fast as this function runs in the context of | |
| 40 | − * an interrupt handler. | |
| 41 | − * | |
| 42 | − * Setup the ioports for the board that were cleared by the reset. | |
| 43 | − * Then, check to see if the signate has been set. Next, set the | |
| 44 | − * signature to a known value and issue a startproc if needed. | |
| 45 | − */ | |
| 46 | −void sc_check_reset(unsigned long data) | |
| 47 | −{ | |
| 48 | − unsigned long flags; | |
| 49 | − unsigned long sig; | |
| 50 | − int card = (unsigned int) data; | |
| 51 | − | |
| 52 | − pr_debug("%s: check_timer timer called\n", | |
| 53 | − sc_adapter[card]->devicename); | |
| 54 | − | |
| 55 | − /* Setup the io ports */ | |
| 56 | − setup_ports(card); | |
| 57 | − | |
| 58 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 59 | − outb(sc_adapter[card]->ioport[sc_adapter[card]->shmem_pgport], | |
| 60 | − (sc_adapter[card]->shmem_magic >> 14) | 0x80); | |
| 61 | − sig = (unsigned long) *((unsigned long *)(sc_adapter[card]->rambase + SIG_OFFSET)); | |
| 62 | − | |
| 63 | − /* check the signature */ | |
| 64 | − if (sig == SIGNATURE) { | |
| 65 | − flushreadfifo(card); | |
| 66 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 67 | − /* See if we need to do a startproc */ | |
| 68 | − if (sc_adapter[card]->StartOnReset) | |
| 69 | − startproc(card); | |
| 70 | − } else { | |
| 71 | − pr_debug("%s: No signature yet, waiting another %lu jiffies.\n", | |
| 72 | − sc_adapter[card]->devicename, CHECKRESET_TIME); | |
| 73 | − mod_timer(&sc_adapter[card]->reset_timer, jiffies + CHECKRESET_TIME); | |
| 74 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 75 | − } | |
| 76 | −} | |
| 77 | − | |
| 78 | −/* | |
| 79 | − * Timed function to check the status of a previous reset | |
| 80 | − * Must be very fast as this function runs in the context of | |
| 81 | − * an interrupt handler. | |
| 82 | − * | |
| 83 | − * Send check sc_adapter->phystat to see if the channels are up | |
| 84 | − * If they are, tell ISDN4Linux that the board is up. If not, | |
| 85 | − * tell IADN4Linux that it is up. Always reset the timer to | |
| 86 | − * fire again (endless loop). | |
| 87 | − */ | |
| 88 | −void check_phystat(unsigned long data) | |
| 89 | −{ | |
| 90 | − unsigned long flags; | |
| 91 | − int card = (unsigned int) data; | |
| 92 | − | |
| 93 | − pr_debug("%s: Checking status...\n", sc_adapter[card]->devicename); | |
| 94 | − /* | |
| 95 | − * check the results of the last PhyStat and change only if | |
| 96 | − * has changed drastically | |
| 97 | − */ | |
| 98 | − if (sc_adapter[card]->nphystat && !sc_adapter[card]->phystat) { /* All is well */ | |
| 99 | − pr_debug("PhyStat transition to RUN\n"); | |
| 100 | − pr_info("%s: Switch contacted, transmitter enabled\n", | |
| 101 | − sc_adapter[card]->devicename); | |
| 102 | − indicate_status(card, ISDN_STAT_RUN, 0, NULL); | |
| 103 | − } | |
| 104 | − else if (!sc_adapter[card]->nphystat && sc_adapter[card]->phystat) { /* All is not well */ | |
| 105 | − pr_debug("PhyStat transition to STOP\n"); | |
| 106 | − pr_info("%s: Switch connection lost, transmitter disabled\n", | |
| 107 | − sc_adapter[card]->devicename); | |
| 108 | − | |
| 109 | − indicate_status(card, ISDN_STAT_STOP, 0, NULL); | |
| 110 | − } | |
| 111 | − | |
| 112 | − sc_adapter[card]->phystat = sc_adapter[card]->nphystat; | |
| 113 | − | |
| 114 | − /* Reinitialize the timer */ | |
| 115 | − spin_lock_irqsave(&sc_adapter[card]->lock, flags); | |
| 116 | − mod_timer(&sc_adapter[card]->stat_timer, jiffies + CHECKSTAT_TIME); | |
| 117 | − spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); | |
| 118 | − | |
| 119 | − /* Send a new cePhyStatus message */ | |
| 120 | − sendmessage(card, CEPID, ceReqTypePhy, ceReqClass2, | |
| 121 | − ceReqPhyStatus, 0, 0, NULL); | |
| 122 | −} | |
| @@ -93,7 +93,8 @@ enum ad_link_speed_type { · 92 unmodified lines | ||
| 93 | 93 | AD_LINK_SPEED_10000MBPS, |
| 94 | 94 | AD_LINK_SPEED_20000MBPS, |
| 95 | 95 | AD_LINK_SPEED_40000MBPS, |
| 96 | − AD_LINK_SPEED_56000MBPS | |
| 96 | + AD_LINK_SPEED_56000MBPS, | |
| 97 | + AD_LINK_SPEED_100000MBPS, | |
| 97 | 98 | }; |
| 98 | 99 | |
| 99 | 100 | /* compare MAC addresses */ |
| @@ -258,6 +259,7 @@ static inline int __check_agg_selection_timer(struct port *port) · 158 unmodified lines | ||
| 258 | 259 | * %AD_LINK_SPEED_20000MBPS |
| 259 | 260 | * %AD_LINK_SPEED_40000MBPS |
| 260 | 261 | * %AD_LINK_SPEED_56000MBPS |
| 262 | + * %AD_LINK_SPEED_100000MBPS | |
| 261 | 263 | */ |
| 262 | 264 | static u16 __get_link_speed(struct port *port) |
| 263 | 265 | { |
| @@ -305,6 +307,10 @@ static u16 __get_link_speed(struct port *port) · 41 unmodified lines | ||
| 305 | 307 | speed = AD_LINK_SPEED_56000MBPS; |
| 306 | 308 | break; |
| 307 | 309 | |
| 310 | + case SPEED_100000: | |
| 311 | + speed = AD_LINK_SPEED_100000MBPS; | |
| 312 | + break; | |
| 313 | + | |
| 308 | 314 | default: |
| 309 | 315 | /* unknown speed value from ethtool. shouldn't happen */ |
| 310 | 316 | speed = 0; |
| @@ -681,6 +687,9 @@ static u32 __get_agg_bandwidth(struct aggregator *aggregator) · 370 unmodified lines | ||
| 681 | 687 | case AD_LINK_SPEED_56000MBPS: |
| 682 | 688 | bandwidth = aggregator->num_of_ports * 56000; |
| 683 | 689 | break; |
| 690 | + case AD_LINK_SPEED_100000MBPS: | |
| 691 | + bandwidth = aggregator->num_of_ports * 100000; | |
| 692 | + break; | |
| 684 | 693 | default: |
| 685 | 694 | bandwidth = 0; /* to silence the compiler */ |
| 686 | 695 | } |
| @@ -830,7 +830,8 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active) · 829 unmodified lines | ||
| 830 | 830 | } |
| 831 | 831 | |
| 832 | 832 | new_active->delay = 0; |
| 833 | − bond_set_slave_link_state(new_active, BOND_LINK_UP); | |
| 833 | + bond_set_slave_link_state(new_active, BOND_LINK_UP, | |
| 834 | + BOND_SLAVE_NOTIFY_NOW); | |
| 834 | 835 | |
| 835 | 836 | if (BOND_MODE(bond) == BOND_MODE_8023AD) |
| 836 | 837 | bond_3ad_handle_link_change(new_active, BOND_LINK_UP); |
| @@ -1066,12 +1067,12 @@ static netdev_features_t bond_fix_features(struct net_device *dev, · 229 unmodified lines | ||
| 1066 | 1067 | return features; |
| 1067 | 1068 | } |
| 1068 | 1069 | |
| 1069 | −#define BOND_VLAN_FEATURES (NETIF_F_ALL_CSUM | NETIF_F_SG | \ | |
| 1070 | +#define BOND_VLAN_FEATURES (NETIF_F_HW_CSUM | NETIF_F_SG | \ | |
| 1070 | 1071 | NETIF_F_FRAGLIST | NETIF_F_ALL_TSO | \ |
| 1071 | 1072 | NETIF_F_HIGHDMA | NETIF_F_LRO) |
| 1072 | 1073 | |
| 1073 | −#define BOND_ENC_FEATURES (NETIF_F_ALL_CSUM | NETIF_F_SG | NETIF_F_RXCSUM |\ | |
| 1074 | − NETIF_F_ALL_TSO) | |
| 1074 | +#define BOND_ENC_FEATURES (NETIF_F_HW_CSUM | NETIF_F_SG | \ | |
| 1075 | + NETIF_F_RXCSUM | NETIF_F_ALL_TSO) | |
| 1075 | 1076 | |
| 1076 | 1077 | static void bond_compute_features(struct bonding *bond) |
| 1077 | 1078 | { |
| @@ -1198,26 +1199,42 @@ static rx_handler_result_t bond_handle_frame(struct sk_buff **pskb) · 120 unmodified lines | ||
| 1198 | 1199 | return ret; |
| 1199 | 1200 | } |
| 1200 | 1201 | |
| 1201 | −static int bond_master_upper_dev_link(struct net_device *bond_dev, | |
| 1202 | − struct net_device *slave_dev, | |
| 1203 | − struct slave *slave) | |
| 1202 | +static enum netdev_lag_tx_type bond_lag_tx_type(struct bonding *bond) | |
| 1204 | 1203 | { |
| 1204 | + switch (BOND_MODE(bond)) { | |
| 1205 | + case BOND_MODE_ROUNDROBIN: | |
| 1206 | + return NETDEV_LAG_TX_TYPE_ROUNDROBIN; | |
| 1207 | + case BOND_MODE_ACTIVEBACKUP: | |
| 1208 | + return NETDEV_LAG_TX_TYPE_ACTIVEBACKUP; | |
| 1209 | + case BOND_MODE_BROADCAST: | |
| 1210 | + return NETDEV_LAG_TX_TYPE_BROADCAST; | |
| 1211 | + case BOND_MODE_XOR: | |
| 1212 | + case BOND_MODE_8023AD: | |
| 1213 | + return NETDEV_LAG_TX_TYPE_HASH; | |
| 1214 | + default: | |
| 1215 | + return NETDEV_LAG_TX_TYPE_UNKNOWN; | |
| 1216 | + } | |
| 1217 | +} | |
| 1218 | + | |
| 1219 | +static int bond_master_upper_dev_link(struct bonding *bond, struct slave *slave) | |
| 1220 | +{ | |
| 1221 | + struct netdev_lag_upper_info lag_upper_info; | |
| 1205 | 1222 | int err; |
| 1206 | 1223 | |
| 1207 | − err = netdev_master_upper_dev_link_private(slave_dev, bond_dev, slave); | |
| 1224 | + lag_upper_info.tx_type = bond_lag_tx_type(bond); | |
| 1225 | + err = netdev_master_upper_dev_link(slave->dev, bond->dev, slave, | |
| 1226 | + &lag_upper_info); | |
| 1208 | 1227 | if (err) |
| 1209 | 1228 | return err; |
| 1210 | − slave_dev->flags |= IFF_SLAVE; | |
| 1211 | − rtmsg_ifinfo(RTM_NEWLINK, slave_dev, IFF_SLAVE, GFP_KERNEL); | |
| 1229 | + rtmsg_ifinfo(RTM_NEWLINK, slave->dev, IFF_SLAVE, GFP_KERNEL); | |
| 1212 | 1230 | return 0; |
| 1213 | 1231 | } |
| 1214 | 1232 | |
| 1215 | −static void bond_upper_dev_unlink(struct net_device *bond_dev, | |
| 1216 | − struct net_device *slave_dev) | |
| 1233 | +static void bond_upper_dev_unlink(struct bonding *bond, struct slave *slave) | |
| 1217 | 1234 | { |
| 1218 | − netdev_upper_dev_unlink(slave_dev, bond_dev); | |
| 1219 | − slave_dev->flags &= ~IFF_SLAVE; | |
| 1220 | − rtmsg_ifinfo(RTM_NEWLINK, slave_dev, IFF_SLAVE, GFP_KERNEL); | |
| 1235 | + netdev_upper_dev_unlink(slave->dev, bond->dev); | |
| 1236 | + slave->dev->flags &= ~IFF_SLAVE; | |
| 1237 | + rtmsg_ifinfo(RTM_NEWLINK, slave->dev, IFF_SLAVE, GFP_KERNEL); | |
| 1221 | 1238 | } |
| 1222 | 1239 | |
| 1223 | 1240 | static struct slave *bond_alloc_slave(struct bonding *bond) |
| @@ -1299,6 +1316,16 @@ void bond_queue_slave_event(struct slave *slave) · 75 unmodified lines | ||
| 1299 | 1316 | queue_delayed_work(slave->bond->wq, &nnw->work, 0); |
| 1300 | 1317 | } |
| 1301 | 1318 | |
| 1319 | +void bond_lower_state_changed(struct slave *slave) | |
| 1320 | +{ | |
| 1321 | + struct netdev_lag_lower_state_info info; | |
| 1322 | + | |
| 1323 | + info.link_up = slave->link == BOND_LINK_UP || | |
| 1324 | + slave->link == BOND_LINK_FAIL; | |
| 1325 | + info.tx_enabled = bond_is_active_slave(slave); | |
| 1326 | + netdev_lower_state_changed(slave->dev, &info); | |
| 1327 | +} | |
| 1328 | + | |
| 1302 | 1329 | /* enslave device <slave> to bond device <master> */ |
| 1303 | 1330 | int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev) |
| 1304 | 1331 | { |
| @@ -1351,7 +1378,7 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev) · 46 unmodified lines | ||
| 1351 | 1378 | * the current ifenslave will set the interface down prior to |
| 1352 | 1379 | * enslaving it; the old ifenslave will not. |
| 1353 | 1380 | */ |
| 1354 | − if ((slave_dev->flags & IFF_UP)) { | |
| 1381 | + if (slave_dev->flags & IFF_UP) { | |
| 1355 | 1382 | netdev_err(bond_dev, "%s is up - this may be due to an out of date ifenslave\n", |
| 1356 | 1383 | slave_dev->name); |
| 1357 | 1384 | res = -EPERM; |
| @@ -1465,6 +1492,9 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev) · 107 unmodified lines | ||
| 1465 | 1492 | } |
| 1466 | 1493 | } |
| 1467 | 1494 | |
| 1495 | + /* set slave flag before open to prevent IPv6 addrconf */ | |
| 1496 | + slave_dev->flags |= IFF_SLAVE; | |
| 1497 | + | |
| 1468 | 1498 | /* open the slave since the application closed it */ |
| 1469 | 1499 | res = dev_open(slave_dev); |
| 1470 | 1500 | if (res) { |
| @@ -1563,21 +1593,26 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev) · 92 unmodified lines | ||
| 1563 | 1593 | if (bond_check_dev_link(bond, slave_dev, 0) == BMSR_LSTATUS) { |
| 1564 | 1594 | if (bond->params.updelay) { |
| 1565 | 1595 | bond_set_slave_link_state(new_slave, |
| 1566 | − BOND_LINK_BACK); | |
| 1596 | + BOND_LINK_BACK, | |
| 1597 | + BOND_SLAVE_NOTIFY_NOW); | |
| 1567 | 1598 | new_slave->delay = bond->params.updelay; |
| 1568 | 1599 | } else { |
| 1569 | 1600 | bond_set_slave_link_state(new_slave, |
| 1570 | − BOND_LINK_UP); | |
| 1601 | + BOND_LINK_UP, | |
| 1602 | + BOND_SLAVE_NOTIFY_NOW); | |
| 1571 | 1603 | } |
| 1572 | 1604 | } else { |
| 1573 | − bond_set_slave_link_state(new_slave, BOND_LINK_DOWN); | |
| 1605 | + bond_set_slave_link_state(new_slave, BOND_LINK_DOWN, | |
| 1606 | + BOND_SLAVE_NOTIFY_NOW); | |
| 1574 | 1607 | } |
| 1575 | 1608 | } else if (bond->params.arp_interval) { |
| 1576 | 1609 | bond_set_slave_link_state(new_slave, |
| 1577 | 1610 | (netif_carrier_ok(slave_dev) ? |
| 1578 | − BOND_LINK_UP : BOND_LINK_DOWN)); | |
| 1611 | + BOND_LINK_UP : BOND_LINK_DOWN), | |
| 1612 | + BOND_SLAVE_NOTIFY_NOW); | |
| 1579 | 1613 | } else { |
| 1580 | − bond_set_slave_link_state(new_slave, BOND_LINK_UP); | |
| 1614 | + bond_set_slave_link_state(new_slave, BOND_LINK_UP, | |
| 1615 | + BOND_SLAVE_NOTIFY_NOW); | |
| 1581 | 1616 | } |
| 1582 | 1617 | |
| 1583 | 1618 | if (new_slave->link != BOND_LINK_DOWN) |
| @@ -1662,7 +1697,7 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev) · 78 unmodified lines | ||
| 1662 | 1697 | goto err_detach; |
| 1663 | 1698 | } |
| 1664 | 1699 | |
| 1665 | − res = bond_master_upper_dev_link(bond_dev, slave_dev, new_slave); | |
| 1700 | + res = bond_master_upper_dev_link(bond, new_slave); | |
| 1666 | 1701 | if (res) { |
| 1667 | 1702 | netdev_dbg(bond_dev, "Error %d calling bond_master_upper_dev_link\n", res); |
| 1668 | 1703 | goto err_unregister; |
| @@ -1698,7 +1733,7 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev) · 29 unmodified lines | ||
| 1698 | 1733 | |
| 1699 | 1734 | /* Undo stages on error */ |
| 1700 | 1735 | err_upper_unlink: |
| 1701 | − bond_upper_dev_unlink(bond_dev, slave_dev); | |
| 1736 | + bond_upper_dev_unlink(bond, new_slave); | |
| 1702 | 1737 | |
| 1703 | 1738 | err_unregister: |
| 1704 | 1739 | netdev_rx_handler_unregister(slave_dev); |
| @@ -1725,6 +1760,7 @@ err_close: · 20 unmodified lines | ||
| 1725 | 1760 | dev_close(slave_dev); |
| 1726 | 1761 | |
| 1727 | 1762 | err_restore_mac: |
| 1763 | + slave_dev->flags &= ~IFF_SLAVE; | |
| 1728 | 1764 | if (!bond->params.fail_over_mac || |
| 1729 | 1765 | BOND_MODE(bond) != BOND_MODE_ACTIVEBACKUP) { |
| 1730 | 1766 | /* XXX TODO - fom follow mode needs to change master's |
| @@ -1799,12 +1835,14 @@ static int __bond_release_one(struct net_device *bond_dev, · 68 unmodified lines | ||
| 1799 | 1835 | return -EINVAL; |
| 1800 | 1836 | } |
| 1801 | 1837 | |
| 1838 | + bond_set_slave_inactive_flags(slave, BOND_SLAVE_NOTIFY_NOW); | |
| 1839 | + | |
| 1802 | 1840 | bond_sysfs_slave_del(slave); |
| 1803 | 1841 | |
| 1804 | 1842 | /* recompute stats just before removing the slave */ |
| 1805 | 1843 | bond_get_stats(bond->dev, &bond->bond_stats); |
| 1806 | 1844 | |
| 1807 | − bond_upper_dev_unlink(bond_dev, slave_dev); | |
| 1845 | + bond_upper_dev_unlink(bond, slave); | |
| 1808 | 1846 | /* unregister rx_handler early so bond_handle_frame wouldn't be called |
| 1809 | 1847 | * for this slave anymore. |
| 1810 | 1848 | */ |
| @@ -1996,7 +2034,8 @@ static int bond_miimon_inspect(struct bonding *bond) · 185 unmodified lines | ||
| 1996 | 2034 | if (link_state) |
| 1997 | 2035 | continue; |
| 1998 | 2036 | |
| 1999 | − bond_set_slave_link_state(slave, BOND_LINK_FAIL); | |
| 2037 | + bond_set_slave_link_state(slave, BOND_LINK_FAIL, | |
| 2038 | + BOND_SLAVE_NOTIFY_LATER); | |
| 2000 | 2039 | slave->delay = bond->params.downdelay; |
| 2001 | 2040 | if (slave->delay) { |
| 2002 | 2041 | netdev_info(bond->dev, "link status down for %sinterface %s, disabling it in %d ms\n", |
| @@ -2011,7 +2050,8 @@ static int bond_miimon_inspect(struct bonding *bond) · 8 unmodified lines | ||
| 2011 | 2050 | case BOND_LINK_FAIL: |
| 2012 | 2051 | if (link_state) { |
| 2013 | 2052 | /* recovered before downdelay expired */ |
| 2014 | − bond_set_slave_link_state(slave, BOND_LINK_UP); | |
| 2053 | + bond_set_slave_link_state(slave, BOND_LINK_UP, | |
| 2054 | + BOND_SLAVE_NOTIFY_LATER); | |
| 2015 | 2055 | slave->last_link_up = jiffies; |
| 2016 | 2056 | netdev_info(bond->dev, "link status up again after %d ms for interface %s\n", |
| 2017 | 2057 | (bond->params.downdelay - slave->delay) * |
| @@ -2033,7 +2073,8 @@ static int bond_miimon_inspect(struct bonding *bond) · 15 unmodified lines | ||
| 2033 | 2073 | if (!link_state) |
| 2034 | 2074 | continue; |
| 2035 | 2075 | |
| 2036 | − bond_set_slave_link_state(slave, BOND_LINK_BACK); | |
| 2076 | + bond_set_slave_link_state(slave, BOND_LINK_BACK, | |
| 2077 | + BOND_SLAVE_NOTIFY_LATER); | |
| 2037 | 2078 | slave->delay = bond->params.updelay; |
| 2038 | 2079 | |
| 2039 | 2080 | if (slave->delay) { |
| @@ -2047,7 +2088,8 @@ static int bond_miimon_inspect(struct bonding *bond) · 7 unmodified lines | ||
| 2047 | 2088 | case BOND_LINK_BACK: |
| 2048 | 2089 | if (!link_state) { |
| 2049 | 2090 | bond_set_slave_link_state(slave, |
| 2050 | − BOND_LINK_DOWN); | |
| 2091 | + BOND_LINK_DOWN, | |
| 2092 | + BOND_SLAVE_NOTIFY_LATER); | |
| 2051 | 2093 | netdev_info(bond->dev, "link status down again after %d ms for interface %s\n", |
| 2052 | 2094 | (bond->params.updelay - slave->delay) * |
| 2053 | 2095 | bond->params.miimon, |
| @@ -2085,7 +2127,8 @@ static void bond_miimon_commit(struct bonding *bond) · 31 unmodified lines | ||
| 2085 | 2127 | continue; |
| 2086 | 2128 | |
| 2087 | 2129 | case BOND_LINK_UP: |
| 2088 | − bond_set_slave_link_state(slave, BOND_LINK_UP); | |
| 2130 | + bond_set_slave_link_state(slave, BOND_LINK_UP, | |
| 2131 | + BOND_SLAVE_NOTIFY_NOW); | |
| 2089 | 2132 | slave->last_link_up = jiffies; |
| 2090 | 2133 | |
| 2091 | 2134 | primary = rtnl_dereference(bond->primary_slave); |
| @@ -2125,7 +2168,8 @@ static void bond_miimon_commit(struct bonding *bond) · 33 unmodified lines | ||
| 2125 | 2168 | if (slave->link_failure_count < UINT_MAX) |
| 2126 | 2169 | slave->link_failure_count++; |
| 2127 | 2170 | |
| 2128 | − bond_set_slave_link_state(slave, BOND_LINK_DOWN); | |
| 2171 | + bond_set_slave_link_state(slave, BOND_LINK_DOWN, | |
| 2172 | + BOND_SLAVE_NOTIFY_NOW); | |
| 2129 | 2173 | |
| 2130 | 2174 | if (BOND_MODE(bond) == BOND_MODE_ACTIVEBACKUP || |
| 2131 | 2175 | BOND_MODE(bond) == BOND_MODE_8023AD) |
| @@ -2708,7 +2752,8 @@ static void bond_ab_arp_commit(struct bonding *bond) · 576 unmodified lines | ||
| 2708 | 2752 | struct slave *current_arp_slave; |
| 2709 | 2753 | |
| 2710 | 2754 | current_arp_slave = rtnl_dereference(bond->current_arp_slave); |
| 2711 | − bond_set_slave_link_state(slave, BOND_LINK_UP); | |
| 2755 | + bond_set_slave_link_state(slave, BOND_LINK_UP, | |
| 2756 | + BOND_SLAVE_NOTIFY_NOW); | |
| 2712 | 2757 | if (current_arp_slave) { |
| 2713 | 2758 | bond_set_slave_inactive_flags( |
| 2714 | 2759 | current_arp_slave, |
| @@ -2731,7 +2776,8 @@ static void bond_ab_arp_commit(struct bonding *bond) · 16 unmodified lines | ||
| 2731 | 2776 | if (slave->link_failure_count < UINT_MAX) |
| 2732 | 2777 | slave->link_failure_count++; |
| 2733 | 2778 | |
| 2734 | − bond_set_slave_link_state(slave, BOND_LINK_DOWN); | |
| 2779 | + bond_set_slave_link_state(slave, BOND_LINK_DOWN, | |
| 2780 | + BOND_SLAVE_NOTIFY_NOW); | |
| 2735 | 2781 | bond_set_slave_inactive_flags(slave, |
| 2736 | 2782 | BOND_SLAVE_NOTIFY_NOW); |
| 2737 | 2783 | |
| @@ -2810,7 +2856,8 @@ static bool bond_ab_arp_probe(struct bonding *bond) · 72 unmodified lines | ||
| 2810 | 2856 | * up when it is actually down |
| 2811 | 2857 | */ |
| 2812 | 2858 | if (!bond_slave_is_up(slave) && slave->link == BOND_LINK_UP) { |
| 2813 | − bond_set_slave_link_state(slave, BOND_LINK_DOWN); | |
| 2859 | + bond_set_slave_link_state(slave, BOND_LINK_DOWN, | |
| 2860 | + BOND_SLAVE_NOTIFY_LATER); | |
| 2814 | 2861 | if (slave->link_failure_count < UINT_MAX) |
| 2815 | 2862 | slave->link_failure_count++; |
| 2816 | 2863 | |
| @@ -2830,7 +2877,8 @@ static bool bond_ab_arp_probe(struct bonding *bond) · 13 unmodified lines | ||
| 2830 | 2877 | if (!new_slave) |
| 2831 | 2878 | goto check_state; |
| 2832 | 2879 | |
| 2833 | − bond_set_slave_link_state(new_slave, BOND_LINK_BACK); | |
| 2880 | + bond_set_slave_link_state(new_slave, BOND_LINK_BACK, | |
| 2881 | + BOND_SLAVE_NOTIFY_LATER); | |
| 2834 | 2882 | bond_set_slave_active_flags(new_slave, BOND_SLAVE_NOTIFY_LATER); |
| 2835 | 2883 | bond_arp_send_all(bond, new_slave); |
| 2836 | 2884 | new_slave->last_link_up = jiffies; |
| @@ -2838,7 +2886,7 @@ static bool bond_ab_arp_probe(struct bonding *bond) · 1 unmodified line | ||
| 2838 | 2886 | |
| 2839 | 2887 | check_state: |
| 2840 | 2888 | bond_for_each_slave_rcu(bond, slave, iter) { |
| 2841 | − if (slave->should_notify) { | |
| 2889 | + if (slave->should_notify || slave->should_notify_link) { | |
| 2842 | 2890 | should_notify_rtnl = BOND_SLAVE_NOTIFY_NOW; |
| 2843 | 2891 | break; |
| 2844 | 2892 | } |
| @@ -2893,8 +2941,10 @@ re_arm: · 48 unmodified lines | ||
| 2893 | 2941 | if (should_notify_peers) |
| 2894 | 2942 | call_netdevice_notifiers(NETDEV_NOTIFY_PEERS, |
| 2895 | 2943 | bond->dev); |
| 2896 | − if (should_notify_rtnl) | |
| 2944 | + if (should_notify_rtnl) { | |
| 2897 | 2945 | bond_slave_state_notify(bond); |
| 2946 | + bond_slave_link_notify(bond); | |
| 2947 | + } | |
| 2898 | 2948 | |
| 2899 | 2949 | rtnl_unlock(); |
| 2900 | 2950 | } |
| @@ -4135,7 +4185,6 @@ void bond_setup(struct net_device *bond_dev) · 1234 unmodified lines | ||
| 4135 | 4185 | NETIF_F_HW_VLAN_CTAG_RX | |
| 4136 | 4186 | NETIF_F_HW_VLAN_CTAG_FILTER; |
| 4137 | 4187 | |
| 4138 | − bond_dev->hw_features &= ~(NETIF_F_ALL_CSUM & ~NETIF_F_HW_CSUM); | |
| 4139 | 4188 | bond_dev->hw_features |= NETIF_F_GSO_ENCAP_ALL; |
| 4140 | 4189 | bond_dev->features |= bond_dev->hw_features; |
| 4141 | 4190 | } |
| @@ -42,7 +42,6 @@ · 41 unmodified lines | ||
| 42 | 42 | |
| 43 | 43 | #include <net/bonding.h> |
| 44 | 44 | |
| 45 | −#define to_dev(obj) container_of(obj, struct device, kobj) | |
| 46 | 45 | #define to_bond(cd) ((struct bonding *)(netdev_priv(to_net_dev(cd)))) |
| 47 | 46 | |
| 48 | 47 | /* "show" function for the bond_masters attribute. |
| @@ -481,7 +480,7 @@ static ssize_t bonding_show_mii_status(struct device *d, · 432 unmodified lines | ||
| 481 | 480 | char *buf) |
| 482 | 481 | { |
| 483 | 482 | struct bonding *bond = to_bond(d); |
| 484 | − bool active = !!rcu_access_pointer(bond->curr_active_slave); | |
| 483 | + bool active = netif_carrier_ok(bond->dev); | |
| 485 | 484 | |
| 486 | 485 | return sprintf(buf, "%s\n", active ? "up" : "down"); |
| 487 | 486 | } |
| @@ -32,6 +32,7 @@ · 31 unmodified lines | ||
| 32 | 32 | #include <linux/can/dev.h> |
| 33 | 33 | #include <linux/can/error.h> |
| 34 | 34 | #include <linux/can/led.h> |
| 35 | +#include <linux/pm_runtime.h> | |
| 35 | 36 | |
| 36 | 37 | #define DRIVER_NAME "xilinx_can" |
| 37 | 38 | |
| @@ -138,7 +139,7 @@ struct xcan_priv { · 100 unmodified lines | ||
| 138 | 139 | u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); |
| 139 | 140 | void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, |
| 140 | 141 | u32 val); |
| 141 | − struct net_device *dev; | |
| 142 | + struct device *dev; | |
| 142 | 143 | void __iomem *reg_base; |
| 143 | 144 | unsigned long irq_flags; |
| 144 | 145 | struct clk *bus_clk; |
| @@ -840,6 +841,13 @@ static int xcan_open(struct net_device *ndev) · 695 unmodified lines | ||
| 840 | 841 | struct xcan_priv *priv = netdev_priv(ndev); |
| 841 | 842 | int ret; |
| 842 | 843 | |
| 844 | + ret = pm_runtime_get_sync(priv->dev); | |
| 845 | + if (ret < 0) { | |
| 846 | + netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", | |
| 847 | + __func__, ret); | |
| 848 | + return ret; | |
| 849 | + } | |
| 850 | + | |
| 843 | 851 | ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, |
| 844 | 852 | ndev->name, ndev); |
| 845 | 853 | if (ret < 0) { |
| @@ -847,29 +855,17 @@ static int xcan_open(struct net_device *ndev) · 1 unmodified line | ||
| 847 | 855 | goto err; |
| 848 | 856 | } |
| 849 | 857 | |
| 850 | − ret = clk_prepare_enable(priv->can_clk); | |
| 851 | − if (ret) { | |
| 852 | − netdev_err(ndev, "unable to enable device clock\n"); | |
| 853 | − goto err_irq; | |
| 854 | − } | |
| 855 | − | |
| 856 | − ret = clk_prepare_enable(priv->bus_clk); | |
| 857 | − if (ret) { | |
| 858 | − netdev_err(ndev, "unable to enable bus clock\n"); | |
| 859 | − goto err_can_clk; | |
| 860 | − } | |
| 861 | − | |
| 862 | 858 | /* Set chip into reset mode */ |
| 863 | 859 | ret = set_reset_mode(ndev); |
| 864 | 860 | if (ret < 0) { |
| 865 | 861 | netdev_err(ndev, "mode resetting failed!\n"); |
| 866 | − goto err_bus_clk; | |
| 862 | + goto err_irq; | |
| 867 | 863 | } |
| 868 | 864 | |
| 869 | 865 | /* Common open */ |
| 870 | 866 | ret = open_candev(ndev); |
| 871 | 867 | if (ret) |
| 872 | − goto err_bus_clk; | |
| 868 | + goto err_irq; | |
| 873 | 869 | |
| 874 | 870 | ret = xcan_chip_start(ndev); |
| 875 | 871 | if (ret < 0) { |
| @@ -885,13 +881,11 @@ static int xcan_open(struct net_device *ndev) · 9 unmodified lines | ||
| 885 | 881 | |
| 886 | 882 | err_candev: |
| 887 | 883 | close_candev(ndev); |
| 888 | −err_bus_clk: | |
| 889 | − clk_disable_unprepare(priv->bus_clk); | |
| 890 | −err_can_clk: | |
| 891 | − clk_disable_unprepare(priv->can_clk); | |
| 892 | 884 | err_irq: |
| 893 | 885 | free_irq(ndev->irq, ndev); |
| 894 | 886 | err: |
| 887 | + pm_runtime_put(priv->dev); | |
| 888 | + | |
| 895 | 889 | return ret; |
| 896 | 890 | } |
| 897 | 891 | |
| @@ -908,12 +902,11 @@ static int xcan_close(struct net_device *ndev) · 10 unmodified lines | ||
| 908 | 902 | netif_stop_queue(ndev); |
| 909 | 903 | napi_disable(&priv->napi); |
| 910 | 904 | xcan_chip_stop(ndev); |
| 911 | − clk_disable_unprepare(priv->bus_clk); | |
| 912 | − clk_disable_unprepare(priv->can_clk); | |
| 913 | 905 | free_irq(ndev->irq, ndev); |
| 914 | 906 | close_candev(ndev); |
| 915 | 907 | |
| 916 | 908 | can_led_event(ndev, CAN_LED_EVENT_STOP); |
| 909 | + pm_runtime_put(priv->dev); | |
| 917 | 910 | |
| 918 | 911 | return 0; |
| 919 | 912 | } |
| @@ -932,27 +925,20 @@ static int xcan_get_berr_counter(const struct net_device *ndev, · 12 unmodified lines | ||
| 932 | 925 | struct xcan_priv *priv = netdev_priv(ndev); |
| 933 | 926 | int ret; |
| 934 | 927 | |
| 935 | − ret = clk_prepare_enable(priv->can_clk); | |
| 936 | − if (ret) | |
| 937 | − goto err; | |
| 938 | − | |
| 939 | − ret = clk_prepare_enable(priv->bus_clk); | |
| 940 | − if (ret) | |
| 941 | − goto err_clk; | |
| 928 | + ret = pm_runtime_get_sync(priv->dev); | |
| 929 | + if (ret < 0) { | |
| 930 | + netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", | |
| 931 | + __func__, ret); | |
| 932 | + return ret; | |
| 933 | + } | |
| 942 | 934 | |
| 943 | 935 | bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; |
| 944 | 936 | bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & |
| 945 | 937 | XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); |
| 946 | 938 | |
| 947 | − clk_disable_unprepare(priv->bus_clk); | |
| 948 | − clk_disable_unprepare(priv->can_clk); | |
| 939 | + pm_runtime_put(priv->dev); | |
| 949 | 940 | |
| 950 | 941 | return 0; |
| 951 | − | |
| 952 | −err_clk: | |
| 953 | − clk_disable_unprepare(priv->can_clk); | |
| 954 | −err: | |
| 955 | − return ret; | |
| 956 | 942 | } |
| 957 | 943 | |
| 958 | 944 | |
| @@ -965,15 +951,45 @@ static const struct net_device_ops xcan_netdev_ops = { · 6 unmodified lines | ||
| 965 | 951 | |
| 966 | 952 | /** |
| 967 | 953 | * xcan_suspend - Suspend method for the driver |
| 968 | − * @dev: Address of the platform_device structure | |
| 954 | + * @dev: Address of the device structure | |
| 969 | 955 | * |
| 970 | 956 | * Put the driver into low power mode. |
| 971 | − * Return: 0 always | |
| 957 | + * Return: 0 on success and failure value on error | |
| 972 | 958 | */ |
| 973 | 959 | static int __maybe_unused xcan_suspend(struct device *dev) |
| 974 | 960 | { |
| 975 | − struct platform_device *pdev = dev_get_drvdata(dev); | |
| 976 | − struct net_device *ndev = platform_get_drvdata(pdev); | |
| 961 | + if (!device_may_wakeup(dev)) | |
| 962 | + return pm_runtime_force_suspend(dev); | |
| 963 | + | |
| 964 | + return 0; | |
| 965 | +} | |
| 966 | + | |
| 967 | +/** | |
| 968 | + * xcan_resume - Resume from suspend | |
| 969 | + * @dev: Address of the device structure | |
| 970 | + * | |
| 971 | + * Resume operation after suspend. | |
| 972 | + * Return: 0 on success and failure value on error | |
| 973 | + */ | |
| 974 | +static int __maybe_unused xcan_resume(struct device *dev) | |
| 975 | +{ | |
| 976 | + if (!device_may_wakeup(dev)) | |
| 977 | + return pm_runtime_force_resume(dev); | |
| 978 | + | |
| 979 | + return 0; | |
| 980 | + | |
| 981 | +} | |
| 982 | + | |
| 983 | +/** | |
| 984 | + * xcan_runtime_suspend - Runtime suspend method for the driver | |
| 985 | + * @dev: Address of the device structure | |
| 986 | + * | |
| 987 | + * Put the driver into low power mode. | |
| 988 | + * Return: 0 always | |
| 989 | + */ | |
| 990 | +static int __maybe_unused xcan_runtime_suspend(struct device *dev) | |
| 991 | +{ | |
| 992 | + struct net_device *ndev = dev_get_drvdata(dev); | |
| 977 | 993 | struct xcan_priv *priv = netdev_priv(ndev); |
| 978 | 994 | |
| 979 | 995 | if (netif_running(ndev)) { |
| @@ -984,43 +1000,55 @@ static int __maybe_unused xcan_suspend(struct device *dev) · 4 unmodified lines | ||
| 984 | 1000 | priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK); |
| 985 | 1001 | priv->can.state = CAN_STATE_SLEEPING; |
| 986 | 1002 | |
| 987 | − clk_disable(priv->bus_clk); | |
| 988 | − clk_disable(priv->can_clk); | |
| 1003 | + clk_disable_unprepare(priv->bus_clk); | |
| 1004 | + clk_disable_unprepare(priv->can_clk); | |
| 989 | 1005 | |
| 990 | 1006 | return 0; |
| 991 | 1007 | } |
| 992 | 1008 | |
| 993 | 1009 | /** |
| 994 | − * xcan_resume - Resume from suspend | |
| 995 | − * @dev: Address of the platformdevice structure | |
| 1010 | + * xcan_runtime_resume - Runtime resume from suspend | |
| 1011 | + * @dev: Address of the device structure | |
| 996 | 1012 | * |
| 997 | 1013 | * Resume operation after suspend. |
| 998 | 1014 | * Return: 0 on success and failure value on error |
| 999 | 1015 | */ |
| 1000 | −static int __maybe_unused xcan_resume(struct device *dev) | |
| 1016 | +static int __maybe_unused xcan_runtime_resume(struct device *dev) | |
| 1001 | 1017 | { |
| 1002 | − struct platform_device *pdev = dev_get_drvdata(dev); | |
| 1003 | − struct net_device *ndev = platform_get_drvdata(pdev); | |
| 1018 | + struct net_device *ndev = dev_get_drvdata(dev); | |
| 1004 | 1019 | struct xcan_priv *priv = netdev_priv(ndev); |
| 1005 | 1020 | int ret; |
| 1021 | + u32 isr, status; | |
| 1006 | 1022 | |
| 1007 | − ret = clk_enable(priv->bus_clk); | |
| 1023 | + ret = clk_prepare_enable(priv->bus_clk); | |
| 1008 | 1024 | if (ret) { |
| 1009 | 1025 | dev_err(dev, "Cannot enable clock.\n"); |
| 1010 | 1026 | return ret; |
| 1011 | 1027 | } |
| 1012 | − ret = clk_enable(priv->can_clk); | |
| 1028 | + ret = clk_prepare_enable(priv->can_clk); | |
| 1013 | 1029 | if (ret) { |
| 1014 | 1030 | dev_err(dev, "Cannot enable clock.\n"); |
| 1015 | 1031 | clk_disable_unprepare(priv->bus_clk); |
| 1016 | 1032 | return ret; |
| 1017 | 1033 | } |
| 1018 | 1034 | |
| 1019 | − priv->write_reg(priv, XCAN_MSR_OFFSET, 0); | |
| 1020 | − priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); | |
| 1021 | − priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
| 1035 | + priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); | |
| 1036 | + isr = priv->read_reg(priv, XCAN_ISR_OFFSET); | |
| 1037 | + status = priv->read_reg(priv, XCAN_SR_OFFSET); | |
| 1022 | 1038 | |
| 1023 | 1039 | if (netif_running(ndev)) { |
| 1040 | + if (isr & XCAN_IXR_BSOFF_MASK) { | |
| 1041 | + priv->can.state = CAN_STATE_BUS_OFF; | |
| 1042 | + priv->write_reg(priv, XCAN_SRR_OFFSET, | |
| 1043 | + XCAN_SRR_RESET_MASK); | |
| 1044 | + } else if ((status & XCAN_SR_ESTAT_MASK) == | |
| 1045 | + XCAN_SR_ESTAT_MASK) { | |
| 1046 | + priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
| 1047 | + } else if (status & XCAN_SR_ERRWRN_MASK) { | |
| 1048 | + priv->can.state = CAN_STATE_ERROR_WARNING; | |
| 1049 | + } else { | |
| 1050 | + priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
| 1051 | + } | |
| 1024 | 1052 | netif_device_attach(ndev); |
| 1025 | 1053 | netif_start_queue(ndev); |
| 1026 | 1054 | } |
| @@ -1028,7 +1056,10 @@ static int __maybe_unused xcan_resume(struct device *dev) · 1 unmodified line | ||
| 1028 | 1056 | return 0; |
| 1029 | 1057 | } |
| 1030 | 1058 | |
| 1031 | −static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume); | |
| 1059 | +static const struct dev_pm_ops xcan_dev_pm_ops = { | |
| 1060 | + SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume) | |
| 1061 | + SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL) | |
| 1062 | +}; | |
| 1032 | 1063 | |
| 1033 | 1064 | /** |
| 1034 | 1065 | * xcan_probe - Platform registration call |
| @@ -1069,7 +1100,7 @@ static int xcan_probe(struct platform_device *pdev) · 34 unmodified lines | ||
| 1069 | 1100 | return -ENOMEM; |
| 1070 | 1101 | |
| 1071 | 1102 | priv = netdev_priv(ndev); |
| 1072 | − priv->dev = ndev; | |
| 1103 | + priv->dev = &pdev->dev; | |
| 1073 | 1104 | priv->can.bittiming_const = &xcan_bittiming_const; |
| 1074 | 1105 | priv->can.do_set_mode = xcan_do_set_mode; |
| 1075 | 1106 | priv->can.do_get_berr_counter = xcan_get_berr_counter; |
| @@ -1111,21 +1142,17 @@ static int xcan_probe(struct platform_device *pdev) · 35 unmodified lines | ||
| 1111 | 1142 | } |
| 1112 | 1143 | } |
| 1113 | 1144 | |
| 1114 | − ret = clk_prepare_enable(priv->can_clk); | |
| 1115 | − if (ret) { | |
| 1116 | − dev_err(&pdev->dev, "unable to enable device clock\n"); | |
| 1117 | − goto err_free; | |
| 1118 | − } | |
| 1119 | − | |
| 1120 | − ret = clk_prepare_enable(priv->bus_clk); | |
| 1121 | − if (ret) { | |
| 1122 | − dev_err(&pdev->dev, "unable to enable bus clock\n"); | |
| 1123 | − goto err_unprepare_disable_dev; | |
| 1124 | − } | |
| 1125 | − | |
| 1126 | 1145 | priv->write_reg = xcan_write_reg_le; |
| 1127 | 1146 | priv->read_reg = xcan_read_reg_le; |
| 1128 | 1147 | |
| 1148 | + pm_runtime_enable(&pdev->dev); | |
| 1149 | + ret = pm_runtime_get_sync(&pdev->dev); | |
| 1150 | + if (ret < 0) { | |
| 1151 | + netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", | |
| 1152 | + __func__, ret); | |
| 1153 | + goto err_pmdisable; | |
| 1154 | + } | |
| 1155 | + | |
| 1129 | 1156 | if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { |
| 1130 | 1157 | priv->write_reg = xcan_write_reg_be; |
| 1131 | 1158 | priv->read_reg = xcan_read_reg_be; |
| @@ -1138,22 +1165,23 @@ static int xcan_probe(struct platform_device *pdev) · 6 unmodified lines | ||
| 1138 | 1165 | ret = register_candev(ndev); |
| 1139 | 1166 | if (ret) { |
| 1140 | 1167 | dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); |
| 1141 | − goto err_unprepare_disable_busclk; | |
| 1168 | + goto err_disableclks; | |
| 1142 | 1169 | } |
| 1143 | 1170 | |
| 1144 | 1171 | devm_can_led_init(ndev); |
| 1145 | − clk_disable_unprepare(priv->bus_clk); | |
| 1146 | − clk_disable_unprepare(priv->can_clk); | |
| 1172 | + | |
| 1173 | + pm_runtime_put(&pdev->dev); | |
| 1174 | + | |
| 1147 | 1175 | netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n", |
| 1148 | 1176 | priv->reg_base, ndev->irq, priv->can.clock.freq, |
| 1149 | 1177 | priv->tx_max); |
| 1150 | 1178 | |
| 1151 | 1179 | return 0; |
| 1152 | 1180 | |
| 1153 | −err_unprepare_disable_busclk: | |
| 1154 | − clk_disable_unprepare(priv->bus_clk); | |
| 1155 | −err_unprepare_disable_dev: | |
| 1156 | − clk_disable_unprepare(priv->can_clk); | |
| 1181 | +err_disableclks: | |
| 1182 | + pm_runtime_put(priv->dev); | |
| 1183 | +err_pmdisable: | |
| 1184 | + pm_runtime_disable(&pdev->dev); | |
| 1157 | 1185 | err_free: |
| 1158 | 1186 | free_candev(ndev); |
| 1159 | 1187 | err: |
| @@ -1172,10 +1200,8 @@ static int xcan_remove(struct platform_device *pdev) · 12 unmodified lines | ||
| 1172 | 1200 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1173 | 1201 | struct xcan_priv *priv = netdev_priv(ndev); |
| 1174 | 1202 | |
| 1175 | − if (set_reset_mode(ndev) < 0) | |
| 1176 | − netdev_err(ndev, "mode resetting failed!\n"); | |
| 1177 | − | |
| 1178 | 1203 | unregister_candev(ndev); |
| 1204 | + pm_runtime_disable(&pdev->dev); | |
| 1179 | 1205 | netif_napi_del(&priv->napi); |
| 1180 | 1206 | free_candev(ndev); |
| 1181 | 1207 | |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | #include <linux/list.h> |
| 20 | 20 | #include <linux/module.h> |
| 21 | 21 | #include <linux/netdevice.h> |
| 22 | +#include <linux/gpio/consumer.h> | |
| 22 | 23 | #include <linux/phy.h> |
| 23 | 24 | #include <net/dsa.h> |
| 24 | 25 | #include <net/switchdev.h> |
| @@ -616,98 +617,112 @@ static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) · 591 unmodified lines | ||
| 616 | 617 | } |
| 617 | 618 | |
| 618 | 619 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
| 619 | − { "in_good_octets", 8, 0x00, }, | |
| 620 | − { "in_bad_octets", 4, 0x02, }, | |
| 621 | − { "in_unicast", 4, 0x04, }, | |
| 622 | − { "in_broadcasts", 4, 0x06, }, | |
| 623 | − { "in_multicasts", 4, 0x07, }, | |
| 624 | − { "in_pause", 4, 0x16, }, | |
| 625 | − { "in_undersize", 4, 0x18, }, | |
| 626 | − { "in_fragments", 4, 0x19, }, | |
| 627 | − { "in_oversize", 4, 0x1a, }, | |
| 628 | − { "in_jabber", 4, 0x1b, }, | |
| 629 | − { "in_rx_error", 4, 0x1c, }, | |
| 630 | − { "in_fcs_error", 4, 0x1d, }, | |
| 631 | − { "out_octets", 8, 0x0e, }, | |
| 632 | − { "out_unicast", 4, 0x10, }, | |
| 633 | − { "out_broadcasts", 4, 0x13, }, | |
| 634 | − { "out_multicasts", 4, 0x12, }, | |
| 635 | − { "out_pause", 4, 0x15, }, | |
| 636 | − { "excessive", 4, 0x11, }, | |
| 637 | − { "collisions", 4, 0x1e, }, | |
| 638 | − { "deferred", 4, 0x05, }, | |
| 639 | − { "single", 4, 0x14, }, | |
| 640 | − { "multiple", 4, 0x17, }, | |
| 641 | − { "out_fcs_error", 4, 0x03, }, | |
| 642 | − { "late", 4, 0x1f, }, | |
| 643 | − { "hist_64bytes", 4, 0x08, }, | |
| 644 | − { "hist_65_127bytes", 4, 0x09, }, | |
| 645 | − { "hist_128_255bytes", 4, 0x0a, }, | |
| 646 | − { "hist_256_511bytes", 4, 0x0b, }, | |
| 647 | − { "hist_512_1023bytes", 4, 0x0c, }, | |
| 648 | − { "hist_1024_max_bytes", 4, 0x0d, }, | |
| 649 | − /* Not all devices have the following counters */ | |
| 650 | − { "sw_in_discards", 4, 0x110, }, | |
| 651 | − { "sw_in_filtered", 2, 0x112, }, | |
| 652 | − { "sw_out_filtered", 2, 0x113, }, | |
| 653 | − | |
| 620 | + { "in_good_octets", 8, 0x00, BANK0, }, | |
| 621 | + { "in_bad_octets", 4, 0x02, BANK0, }, | |
| 622 | + { "in_unicast", 4, 0x04, BANK0, }, | |
| 623 | + { "in_broadcasts", 4, 0x06, BANK0, }, | |
| 624 | + { "in_multicasts", 4, 0x07, BANK0, }, | |
| 625 | + { "in_pause", 4, 0x16, BANK0, }, | |
| 626 | + { "in_undersize", 4, 0x18, BANK0, }, | |
| 627 | + { "in_fragments", 4, 0x19, BANK0, }, | |
| 628 | + { "in_oversize", 4, 0x1a, BANK0, }, | |
| 629 | + { "in_jabber", 4, 0x1b, BANK0, }, | |
| 630 | + { "in_rx_error", 4, 0x1c, BANK0, }, | |
| 631 | + { "in_fcs_error", 4, 0x1d, BANK0, }, | |
| 632 | + { "out_octets", 8, 0x0e, BANK0, }, | |
| 633 | + { "out_unicast", 4, 0x10, BANK0, }, | |
| 634 | + { "out_broadcasts", 4, 0x13, BANK0, }, | |
| 635 | + { "out_multicasts", 4, 0x12, BANK0, }, | |
| 636 | + { "out_pause", 4, 0x15, BANK0, }, | |
| 637 | + { "excessive", 4, 0x11, BANK0, }, | |
| 638 | + { "collisions", 4, 0x1e, BANK0, }, | |
| 639 | + { "deferred", 4, 0x05, BANK0, }, | |
| 640 | + { "single", 4, 0x14, BANK0, }, | |
| 641 | + { "multiple", 4, 0x17, BANK0, }, | |
| 642 | + { "out_fcs_error", 4, 0x03, BANK0, }, | |
| 643 | + { "late", 4, 0x1f, BANK0, }, | |
| 644 | + { "hist_64bytes", 4, 0x08, BANK0, }, | |
| 645 | + { "hist_65_127bytes", 4, 0x09, BANK0, }, | |
| 646 | + { "hist_128_255bytes", 4, 0x0a, BANK0, }, | |
| 647 | + { "hist_256_511bytes", 4, 0x0b, BANK0, }, | |
| 648 | + { "hist_512_1023bytes", 4, 0x0c, BANK0, }, | |
| 649 | + { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, | |
| 650 | + { "sw_in_discards", 4, 0x10, PORT, }, | |
| 651 | + { "sw_in_filtered", 2, 0x12, PORT, }, | |
| 652 | + { "sw_out_filtered", 2, 0x13, PORT, }, | |
| 653 | + { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 654 | + { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 655 | + { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 656 | + { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 657 | + { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 658 | + { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 659 | + { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 660 | + { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 661 | + { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 662 | + { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 663 | + { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 664 | + { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 665 | + { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 666 | + { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 667 | + { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 668 | + { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 669 | + { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 670 | + { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 671 | + { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 672 | + { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 673 | + { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 674 | + { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 675 | + { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 676 | + { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 677 | + { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 678 | + { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
| 654 | 679 | }; |
| 655 | 680 | |
| 656 | −static bool have_sw_in_discards(struct dsa_switch *ds) | |
| 681 | +static bool mv88e6xxx_has_stat(struct dsa_switch *ds, | |
| 682 | + struct mv88e6xxx_hw_stat *stat) | |
| 657 | 683 | { |
| 658 | − struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
| 659 | − | |
| 660 | − switch (ps->id) { | |
| 661 | − case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: | |
| 662 | − case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
| 663 | − case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
| 664 | − case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
| 665 | − case PORT_SWITCH_ID_6352: | |
| 684 | + switch (stat->type) { | |
| 685 | + case BANK0: | |
| 666 | 686 | return true; |
| 667 | − default: | |
| 668 | − return false; | |
| 669 | − } | |
| 670 | −} | |
| 671 | − | |
| 672 | −static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
| 673 | − int nr_stats, | |
| 674 | − struct mv88e6xxx_hw_stat *stats, | |
| 675 | − int port, uint8_t *data) | |
| 676 | −{ | |
| 677 | − int i; | |
| 678 | − | |
| 679 | − for (i = 0; i < nr_stats; i++) { | |
| 680 | − memcpy(data + i * ETH_GSTRING_LEN, | |
| 681 | − stats[i].string, ETH_GSTRING_LEN); | |
| 687 | + case BANK1: | |
| 688 | + return mv88e6xxx_6320_family(ds); | |
| 689 | + case PORT: | |
| 690 | + return mv88e6xxx_6095_family(ds) || | |
| 691 | + mv88e6xxx_6185_family(ds) || | |
| 692 | + mv88e6xxx_6097_family(ds) || | |
| 693 | + mv88e6xxx_6165_family(ds) || | |
| 694 | + mv88e6xxx_6351_family(ds) || | |
| 695 | + mv88e6xxx_6352_family(ds); | |
| 682 | 696 | } |
| 697 | + return false; | |
| 683 | 698 | } |
| 684 | 699 | |
| 685 | 700 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds, |
| 686 | − int stat, | |
| 687 | − struct mv88e6xxx_hw_stat *stats, | |
| 701 | + struct mv88e6xxx_hw_stat *s, | |
| 688 | 702 | int port) |
| 689 | 703 | { |
| 690 | − struct mv88e6xxx_hw_stat *s = stats + stat; | |
| 691 | 704 | u32 low; |
| 692 | 705 | u32 high = 0; |
| 693 | 706 | int ret; |
| 694 | 707 | u64 value; |
| 695 | 708 | |
| 696 | − if (s->reg >= 0x100) { | |
| 697 | − ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
| 698 | − s->reg - 0x100); | |
| 709 | + switch (s->type) { | |
| 710 | + case PORT: | |
| 711 | + ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg); | |
| 699 | 712 | if (ret < 0) |
| 700 | 713 | return UINT64_MAX; |
| 701 | 714 | |
| 702 | 715 | low = ret; |
| 703 | 716 | if (s->sizeof_stat == 4) { |
| 704 | 717 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), |
| 705 | − s->reg - 0x100 + 1); | |
| 718 | + s->reg + 1); | |
| 706 | 719 | if (ret < 0) |
| 707 | 720 | return UINT64_MAX; |
| 708 | 721 | high = ret; |
| 709 | 722 | } |
| 710 | − } else { | |
| 723 | + break; | |
| 724 | + case BANK0: | |
| 725 | + case BANK1: | |
| 711 | 726 | _mv88e6xxx_stats_read(ds, s->reg, &low); |
| 712 | 727 | if (s->sizeof_stat == 8) |
| 713 | 728 | _mv88e6xxx_stats_read(ds, s->reg + 1, &high); |
| @@ -716,61 +731,59 @@ static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds, · 2 unmodified lines | ||
| 716 | 731 | return value; |
| 717 | 732 | } |
| 718 | 733 | |
| 719 | −static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
| 720 | − int nr_stats, | |
| 721 | − struct mv88e6xxx_hw_stat *stats, | |
| 722 | − int port, uint64_t *data) | |
| 734 | +void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
| 723 | 735 | { |
| 724 | − struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
| 725 | − int ret; | |
| 726 | − int i; | |
| 727 | − | |
| 728 | − mutex_lock(&ps->smi_mutex); | |
| 736 | + struct mv88e6xxx_hw_stat *stat; | |
| 737 | + int i, j; | |
| 729 | 738 | |
| 730 | − ret = _mv88e6xxx_stats_snapshot(ds, port); | |
| 731 | − if (ret < 0) { | |
| 732 | − mutex_unlock(&ps->smi_mutex); | |
| 733 | − return; | |
| 739 | + for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
| 740 | + stat = &mv88e6xxx_hw_stats[i]; | |
| 741 | + if (mv88e6xxx_has_stat(ds, stat)) { | |
| 742 | + memcpy(data + j * ETH_GSTRING_LEN, stat->string, | |
| 743 | + ETH_GSTRING_LEN); | |
| 744 | + j++; | |
| 745 | + } | |
| 734 | 746 | } |
| 735 | − | |
| 736 | − /* Read each of the counters. */ | |
| 737 | − for (i = 0; i < nr_stats; i++) | |
| 738 | − data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port); | |
| 739 | − | |
| 740 | − mutex_unlock(&ps->smi_mutex); | |
| 741 | −} | |
| 742 | − | |
| 743 | −/* All the statistics in the table */ | |
| 744 | −void | |
| 745 | −mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
| 746 | −{ | |
| 747 | − if (have_sw_in_discards(ds)) | |
| 748 | − _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
| 749 | − mv88e6xxx_hw_stats, port, data); | |
| 750 | − else | |
| 751 | − _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
| 752 | − mv88e6xxx_hw_stats, port, data); | |
| 753 | 747 | } |
| 754 | 748 | |
| 755 | 749 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) |
| 756 | 750 | { |
| 757 | − if (have_sw_in_discards(ds)) | |
| 758 | − return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
| 759 | − return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
| 751 | + struct mv88e6xxx_hw_stat *stat; | |
| 752 | + int i, j; | |
| 753 | + | |
| 754 | + for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
| 755 | + stat = &mv88e6xxx_hw_stats[i]; | |
| 756 | + if (mv88e6xxx_has_stat(ds, stat)) | |
| 757 | + j++; | |
| 758 | + } | |
| 759 | + return j; | |
| 760 | 760 | } |
| 761 | 761 | |
| 762 | 762 | void |
| 763 | 763 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
| 764 | 764 | int port, uint64_t *data) |
| 765 | 765 | { |
| 766 | − if (have_sw_in_discards(ds)) | |
| 767 | − _mv88e6xxx_get_ethtool_stats( | |
| 768 | − ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
| 769 | − mv88e6xxx_hw_stats, port, data); | |
| 770 | − else | |
| 771 | − _mv88e6xxx_get_ethtool_stats( | |
| 772 | − ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
| 773 | − mv88e6xxx_hw_stats, port, data); | |
| 766 | + struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
| 767 | + struct mv88e6xxx_hw_stat *stat; | |
| 768 | + int ret; | |
| 769 | + int i, j; | |
| 770 | + | |
| 771 | + mutex_lock(&ps->smi_mutex); | |
| 772 | + | |
| 773 | + ret = _mv88e6xxx_stats_snapshot(ds, port); | |
| 774 | + if (ret < 0) { | |
| 775 | + mutex_unlock(&ps->smi_mutex); | |
| 776 | + return; | |
| 777 | + } | |
| 778 | + for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
| 779 | + stat = &mv88e6xxx_hw_stats[i]; | |
| 780 | + if (mv88e6xxx_has_stat(ds, stat)) { | |
| 781 | + data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port); | |
| 782 | + j++; | |
| 783 | + } | |
| 784 | + } | |
| 785 | + | |
| 786 | + mutex_unlock(&ps->smi_mutex); | |
| 774 | 787 | } |
| 775 | 788 | |
| 776 | 789 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
| @@ -2323,6 +2336,7 @@ int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) · 1546 unmodified lines | ||
| 2323 | 2336 | { |
| 2324 | 2337 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
| 2325 | 2338 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); |
| 2339 | + struct gpio_desc *gpiod = ds->pd->reset; | |
| 2326 | 2340 | unsigned long timeout; |
| 2327 | 2341 | int ret; |
| 2328 | 2342 | int i; |
| @@ -2336,6 +2350,14 @@ int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) · 7 unmodified lines | ||
| 2336 | 2350 | /* Wait for transmit queues to drain. */ |
| 2337 | 2351 | usleep_range(2000, 4000); |
| 2338 | 2352 | |
| 2353 | + /* If there is a gpio connected to the reset pin, toggle it */ | |
| 2354 | + if (gpiod) { | |
| 2355 | + gpiod_set_value_cansleep(gpiod, 1); | |
| 2356 | + usleep_range(10000, 20000); | |
| 2357 | + gpiod_set_value_cansleep(gpiod, 0); | |
| 2358 | + usleep_range(10000, 20000); | |
| 2359 | + } | |
| 2360 | + | |
| 2339 | 2361 | /* Reset the switch. Keep the PPU active if requested. The PPU |
| 2340 | 2362 | * needs to be active to support indirect phy register access |
| 2341 | 2363 | * through global registers 0x18 and 0x19. |
| @@ -288,6 +288,7 @@ · 287 unmodified lines | ||
| 288 | 288 | #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) |
| 289 | 289 | #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) |
| 290 | 290 | #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) |
| 291 | +#define GLOBAL_STATS_OP_BANK_1 BIT(9) | |
| 291 | 292 | #define GLOBAL_STATS_COUNTER_32 0x1e |
| 292 | 293 | #define GLOBAL_STATS_COUNTER_01 0x1f |
| 293 | 294 | |
| @@ -420,10 +421,17 @@ struct mv88e6xxx_priv_state { · 126 unmodified lines | ||
| 420 | 421 | struct work_struct bridge_work; |
| 421 | 422 | }; |
| 422 | 423 | |
| 424 | +enum stat_type { | |
| 425 | + BANK0, | |
| 426 | + BANK1, | |
| 427 | + PORT, | |
| 428 | +}; | |
| 429 | + | |
| 423 | 430 | struct mv88e6xxx_hw_stat { |
| 424 | 431 | char string[ETH_GSTRING_LEN]; |
| 425 | 432 | int sizeof_stat; |
| 426 | 433 | int reg; |
| 434 | + enum stat_type type; | |
| 427 | 435 | }; |
| 428 | 436 | |
| 429 | 437 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active); |
| @@ -562,7 +562,7 @@ static void el3_common_remove (struct net_device *dev) · 561 unmodified lines | ||
| 562 | 562 | } |
| 563 | 563 | |
| 564 | 564 | #ifdef CONFIG_EISA |
| 565 | −static int __init el3_eisa_probe (struct device *device) | |
| 565 | +static int el3_eisa_probe(struct device *device) | |
| 566 | 566 | { |
| 567 | 567 | short i; |
| 568 | 568 | int ioaddr, irq, if_port; |
| @@ -907,7 +907,7 @@ static struct eisa_device_id vortex_eisa_ids[] = { · 906 unmodified lines | ||
| 907 | 907 | }; |
| 908 | 908 | MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids); |
| 909 | 909 | |
| 910 | −static int __init vortex_eisa_probe(struct device *device) | |
| 910 | +static int vortex_eisa_probe(struct device *device) | |
| 911 | 911 | { |
| 912 | 912 | void __iomem *ioaddr; |
| 913 | 913 | struct eisa_device *edev; |
| @@ -372,7 +372,7 @@ static int ax_mii_probe(struct net_device *dev) · 371 unmodified lines | ||
| 372 | 372 | ax->phy_dev = phy_dev; |
| 373 | 373 | |
| 374 | 374 | netdev_info(dev, "PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
| 375 | − phy_dev->drv->name, dev_name(&phy_dev->dev), phy_dev->irq); | |
| 375 | + phy_dev->drv->name, phydev_name(phy_dev), phy_dev->irq); | |
| 376 | 376 | |
| 377 | 377 | return 0; |
| 378 | 378 | } |
| @@ -627,7 +627,7 @@ static int ax_mii_init(struct net_device *dev) · 248 unmodified lines | ||
| 627 | 627 | struct platform_device *pdev = to_platform_device(dev->dev.parent); |
| 628 | 628 | struct ei_device *ei_local = netdev_priv(dev); |
| 629 | 629 | struct ax_device *ax = to_ax_dev(dev); |
| 630 | − int err, i; | |
| 630 | + int err; | |
| 631 | 631 | |
| 632 | 632 | ax->bb_ctrl.ops = &bb_ops; |
| 633 | 633 | ax->addr_memr = ei_local->mem + AX_MEMR; |
| @@ -642,23 +642,12 @@ static int ax_mii_init(struct net_device *dev) · 8 unmodified lines | ||
| 642 | 642 | snprintf(ax->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
| 643 | 643 | pdev->name, pdev->id); |
| 644 | 644 | |
| 645 | − ax->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
| 646 | − if (!ax->mii_bus->irq) { | |
| 647 | − err = -ENOMEM; | |
| 648 | − goto out_free_mdio_bitbang; | |
| 649 | − } | |
| 650 | − | |
| 651 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 652 | − ax->mii_bus->irq[i] = PHY_POLL; | |
| 653 | − | |
| 654 | 645 | err = mdiobus_register(ax->mii_bus); |
| 655 | 646 | if (err) |
| 656 | − goto out_free_irq; | |
| 647 | + goto out_free_mdio_bitbang; | |
| 657 | 648 | |
| 658 | 649 | return 0; |
| 659 | 650 | |
| 660 | − out_free_irq: | |
| 661 | − kfree(ax->mii_bus->irq); | |
| 662 | 651 | out_free_mdio_bitbang: |
| 663 | 652 | free_mdio_bitbang(ax->mii_bus); |
| 664 | 653 | out: |
| @@ -122,6 +122,7 @@ config FEALNX · 121 unmodified lines | ||
| 122 | 122 | cards. <http://www.myson.com.tw/> |
| 123 | 123 | |
| 124 | 124 | source "drivers/net/ethernet/natsemi/Kconfig" |
| 125 | +source "drivers/net/ethernet/netronome/Kconfig" | |
| 125 | 126 | source "drivers/net/ethernet/8390/Kconfig" |
| 126 | 127 | |
| 127 | 128 | config NET_NETX |
| @@ -53,6 +53,7 @@ obj-$(CONFIG_NET_VENDOR_MOXART) += moxa/ · 52 unmodified lines | ||
| 53 | 53 | obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/ |
| 54 | 54 | obj-$(CONFIG_FEALNX) += fealnx.o |
| 55 | 55 | obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/ |
| 56 | +obj-$(CONFIG_NET_VENDOR_NETRONOME) += netronome/ | |
| 56 | 57 | obj-$(CONFIG_NET_NETX) += netx-eth.o |
| 57 | 58 | obj-$(CONFIG_NET_VENDOR_NUVOTON) += nuvoton/ |
| 58 | 59 | obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/ |
| @@ -380,9 +380,8 @@ static void bfin_mac_adjust_link(struct net_device *dev) · 379 unmodified lines | ||
| 380 | 380 | static int mii_probe(struct net_device *dev, int phy_mode) |
| 381 | 381 | { |
| 382 | 382 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 383 | − struct phy_device *phydev = NULL; | |
| 383 | + struct phy_device *phydev; | |
| 384 | 384 | unsigned short sysctl; |
| 385 | − int i; | |
| 386 | 385 | u32 sclk, mdc_div; |
| 387 | 386 | |
| 388 | 387 | /* Enable PHY output early */ |
| @@ -396,18 +395,7 @@ static int mii_probe(struct net_device *dev, int phy_mode) · 7 unmodified lines | ||
| 396 | 395 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
| 397 | 396 | bfin_write_EMAC_SYSCTL(sysctl); |
| 398 | 397 | |
| 399 | − /* search for connected PHY device */ | |
| 400 | − for (i = 0; i < PHY_MAX_ADDR; ++i) { | |
| 401 | − struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; | |
| 402 | − | |
| 403 | − if (!tmp_phydev) | |
| 404 | − continue; /* no PHY here... */ | |
| 405 | − | |
| 406 | − phydev = tmp_phydev; | |
| 407 | − break; /* found it */ | |
| 408 | − } | |
| 409 | − | |
| 410 | − /* now we are supposed to have a proper phydev, to attach to... */ | |
| 398 | + phydev = phy_find_first(lp->mii_bus); | |
| 411 | 399 | if (!phydev) { |
| 412 | 400 | netdev_err(dev, "no phy device found\n"); |
| 413 | 401 | return -ENODEV; |
| @@ -419,7 +407,7 @@ static int mii_probe(struct net_device *dev, int phy_mode) · 5 unmodified lines | ||
| 419 | 407 | return -EINVAL; |
| 420 | 408 | } |
| 421 | 409 | |
| 422 | − phydev = phy_connect(dev, dev_name(&phydev->dev), | |
| 410 | + phydev = phy_connect(dev, phydev_name(phydev), | |
| 423 | 411 | &bfin_mac_adjust_link, phy_mode); |
| 424 | 412 | |
| 425 | 413 | if (IS_ERR(phydev)) { |
| @@ -444,10 +432,8 @@ static int mii_probe(struct net_device *dev, int phy_mode) · 18 unmodified lines | ||
| 444 | 432 | lp->old_duplex = -1; |
| 445 | 433 | lp->phydev = phydev; |
| 446 | 434 | |
| 447 | − pr_info("attached PHY driver [%s] " | |
| 448 | − "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", | |
| 449 | − phydev->drv->name, dev_name(&phydev->dev), phydev->irq, | |
| 450 | − MDC_CLK, mdc_div, sclk/1000000); | |
| 435 | + phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", | |
| 436 | + MDC_CLK, mdc_div, sclk / 1000000); | |
| 451 | 437 | |
| 452 | 438 | return 0; |
| 453 | 439 | } |
| @@ -1840,12 +1826,6 @@ static int bfin_mii_bus_probe(struct platform_device *pdev) · 1386 unmodified lines | ||
| 1840 | 1826 | |
| 1841 | 1827 | snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x", |
| 1842 | 1828 | pdev->name, pdev->id); |
| 1843 | − miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
| 1844 | − if (!miibus->irq) | |
| 1845 | − goto out_err_irq_alloc; | |
| 1846 | − | |
| 1847 | − for (i = rc; i < PHY_MAX_ADDR; ++i) | |
| 1848 | − miibus->irq[i] = PHY_POLL; | |
| 1849 | 1829 | |
| 1850 | 1830 | rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR); |
| 1851 | 1831 | if (rc != mii_bus_pd->phydev_number) |
| @@ -1864,14 +1844,12 @@ static int bfin_mii_bus_probe(struct platform_device *pdev) · 12 unmodified lines | ||
| 1864 | 1844 | rc = mdiobus_register(miibus); |
| 1865 | 1845 | if (rc) { |
| 1866 | 1846 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); |
| 1867 | − goto out_err_mdiobus_register; | |
| 1847 | + goto out_err_irq_alloc; | |
| 1868 | 1848 | } |
| 1869 | 1849 | |
| 1870 | 1850 | platform_set_drvdata(pdev, miibus); |
| 1871 | 1851 | return 0; |
| 1872 | 1852 | |
| 1873 | −out_err_mdiobus_register: | |
| 1874 | − kfree(miibus->irq); | |
| 1875 | 1853 | out_err_irq_alloc: |
| 1876 | 1854 | mdiobus_free(miibus); |
| 1877 | 1855 | out_err_alloc: |
| @@ -1887,7 +1865,6 @@ static int bfin_mii_bus_remove(struct platform_device *pdev) · 9 unmodified lines | ||
| 1887 | 1865 | dev_get_platdata(&pdev->dev); |
| 1888 | 1866 | |
| 1889 | 1867 | mdiobus_unregister(miibus); |
| 1890 | − kfree(miibus->irq); | |
| 1891 | 1868 | mdiobus_free(miibus); |
| 1892 | 1869 | peripheral_free_list(mii_bus_pd->mac_peripherals); |
| 1893 | 1870 | |
| @@ -1912,21 +1889,21 @@ static struct platform_driver bfin_mac_driver = { · 18 unmodified lines | ||
| 1912 | 1889 | }, |
| 1913 | 1890 | }; |
| 1914 | 1891 | |
| 1892 | +static struct platform_driver * const drivers[] = { | |
| 1893 | + &bfin_mii_bus_driver, | |
| 1894 | + &bfin_mac_driver, | |
| 1895 | +}; | |
| 1896 | + | |
| 1915 | 1897 | static int __init bfin_mac_init(void) |
| 1916 | 1898 | { |
| 1917 | − int ret; | |
| 1918 | − ret = platform_driver_register(&bfin_mii_bus_driver); | |
| 1919 | − if (!ret) | |
| 1920 | − return platform_driver_register(&bfin_mac_driver); | |
| 1921 | − return -ENODEV; | |
| 1899 | + return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); | |
| 1922 | 1900 | } |
| 1923 | 1901 | |
| 1924 | 1902 | module_init(bfin_mac_init); |
| 1925 | 1903 | |
| 1926 | 1904 | static void __exit bfin_mac_cleanup(void) |
| 1927 | 1905 | { |
| 1928 | − platform_driver_unregister(&bfin_mac_driver); | |
| 1929 | − platform_driver_unregister(&bfin_mii_bus_driver); | |
| 1906 | + platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); | |
| 1930 | 1907 | } |
| 1931 | 1908 | |
| 1932 | 1909 | module_exit(bfin_mac_cleanup); |
| @@ -1337,11 +1337,6 @@ static int greth_mdio_init(struct greth_private *greth) · 1336 unmodified lines | ||
| 1337 | 1337 | greth->mdio->write = greth_mdio_write; |
| 1338 | 1338 | greth->mdio->priv = greth; |
| 1339 | 1339 | |
| 1340 | − greth->mdio->irq = greth->mdio_irqs; | |
| 1341 | − | |
| 1342 | − for (phy = 0; phy < PHY_MAX_ADDR; phy++) | |
| 1343 | − greth->mdio->irq[phy] = PHY_POLL; | |
| 1344 | − | |
| 1345 | 1340 | ret = mdiobus_register(greth->mdio); |
| 1346 | 1341 | if (ret) { |
| 1347 | 1342 | goto error; |
| @@ -125,7 +125,6 @@ struct greth_private { · 124 unmodified lines | ||
| 125 | 125 | |
| 126 | 126 | struct phy_device *phy; |
| 127 | 127 | struct mii_bus *mdio; |
| 128 | − int mdio_irqs[PHY_MAX_ADDR]; | |
| 129 | 128 | unsigned int link; |
| 130 | 129 | unsigned int speed; |
| 131 | 130 | unsigned int duplex; |
| @@ -1235,7 +1235,7 @@ static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) · 1234 unmodified lines | ||
| 1235 | 1235 | if (!phydev) |
| 1236 | 1236 | return -EIO; |
| 1237 | 1237 | |
| 1238 | − return et131x_phy_mii_read(adapter, phydev->addr, reg, value); | |
| 1238 | + return et131x_phy_mii_read(adapter, phydev->mdio.addr, reg, value); | |
| 1239 | 1239 | } |
| 1240 | 1240 | |
| 1241 | 1241 | static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg, |
| @@ -1462,7 +1462,7 @@ static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down) · 220 unmodified lines | ||
| 1462 | 1462 | data &= ~BMCR_PDOWN; |
| 1463 | 1463 | if (down) |
| 1464 | 1464 | data |= BMCR_PDOWN; |
| 1465 | − et131x_mii_write(adapter, phydev->addr, MII_BMCR, data); | |
| 1465 | + et131x_mii_write(adapter, phydev->mdio.addr, MII_BMCR, data); | |
| 1466 | 1466 | } |
| 1467 | 1467 | |
| 1468 | 1468 | /* et131x_xcvr_init - Init the phy if we are setting it into force mode */ |
| @@ -1490,7 +1490,7 @@ static void et131x_xcvr_init(struct et131x_adapter *adapter) · 21 unmodified lines | ||
| 1490 | 1490 | else |
| 1491 | 1491 | lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT); |
| 1492 | 1492 | |
| 1493 | − et131x_mii_write(adapter, phydev->addr, PHY_LED_2, lcr2); | |
| 1493 | + et131x_mii_write(adapter, phydev->mdio.addr, PHY_LED_2, lcr2); | |
| 1494 | 1494 | } |
| 1495 | 1495 | } |
| 1496 | 1496 | |
| @@ -3192,14 +3192,14 @@ static void et131x_adjust_link(struct net_device *netdev) · 1695 unmodified lines | ||
| 3192 | 3192 | |
| 3193 | 3193 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 3194 | 3194 | ®ister18); |
| 3195 | − et131x_mii_write(adapter, phydev->addr, | |
| 3195 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3196 | 3196 | PHY_MPHY_CONTROL_REG, |
| 3197 | 3197 | register18 | 0x4); |
| 3198 | − et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG, | |
| 3199 | − register18 | 0x8402); | |
| 3200 | − et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG, | |
| 3201 | − register18 | 511); | |
| 3202 | − et131x_mii_write(adapter, phydev->addr, | |
| 3198 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3199 | + PHY_INDEX_REG, register18 | 0x8402); | |
| 3200 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3201 | + PHY_DATA_REG, register18 | 511); | |
| 3202 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3203 | 3203 | PHY_MPHY_CONTROL_REG, register18); |
| 3204 | 3204 | } |
| 3205 | 3205 | |
| @@ -3212,8 +3212,8 @@ static void et131x_adjust_link(struct net_device *netdev) · 6 unmodified lines | ||
| 3212 | 3212 | et131x_mii_read(adapter, PHY_CONFIG, ®); |
| 3213 | 3213 | reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH; |
| 3214 | 3214 | reg |= ET_PHY_CONFIG_FIFO_DEPTH_32; |
| 3215 | − et131x_mii_write(adapter, phydev->addr, PHY_CONFIG, | |
| 3216 | − reg); | |
| 3215 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3216 | + PHY_CONFIG, reg); | |
| 3217 | 3217 | } |
| 3218 | 3218 | |
| 3219 | 3219 | et131x_set_rx_dma_timer(adapter); |
| @@ -3226,14 +3226,14 @@ static void et131x_adjust_link(struct net_device *netdev) · 6 unmodified lines | ||
| 3226 | 3226 | |
| 3227 | 3227 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 3228 | 3228 | ®ister18); |
| 3229 | − et131x_mii_write(adapter, phydev->addr, | |
| 3229 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3230 | 3230 | PHY_MPHY_CONTROL_REG, |
| 3231 | 3231 | register18 | 0x4); |
| 3232 | − et131x_mii_write(adapter, phydev->addr, | |
| 3232 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3233 | 3233 | PHY_INDEX_REG, register18 | 0x8402); |
| 3234 | − et131x_mii_write(adapter, phydev->addr, | |
| 3234 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3235 | 3235 | PHY_DATA_REG, register18 | 511); |
| 3236 | − et131x_mii_write(adapter, phydev->addr, | |
| 3236 | + et131x_mii_write(adapter, phydev->mdio.addr, | |
| 3237 | 3237 | PHY_MPHY_CONTROL_REG, register18); |
| 3238 | 3238 | } |
| 3239 | 3239 | |
| @@ -3265,7 +3265,7 @@ static int et131x_mii_probe(struct net_device *netdev) · 25 unmodified lines | ||
| 3265 | 3265 | return -ENODEV; |
| 3266 | 3266 | } |
| 3267 | 3267 | |
| 3268 | − phydev = phy_connect(netdev, dev_name(&phydev->dev), | |
| 3268 | + phydev = phy_connect(netdev, phydev_name(phydev), | |
| 3269 | 3269 | &et131x_adjust_link, PHY_INTERFACE_MODE_MII); |
| 3270 | 3270 | |
| 3271 | 3271 | if (IS_ERR(phydev)) { |
| @@ -3289,9 +3289,7 @@ static int et131x_mii_probe(struct net_device *netdev) · 17 unmodified lines | ||
| 3289 | 3289 | phydev->autoneg = AUTONEG_ENABLE; |
| 3290 | 3290 | adapter->phydev = phydev; |
| 3291 | 3291 | |
| 3292 | − dev_info(&adapter->pdev->dev, | |
| 3293 | − "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
| 3294 | − phydev->drv->name, dev_name(&phydev->dev)); | |
| 3292 | + phy_attached_info(phydev); | |
| 3295 | 3293 | |
| 3296 | 3294 | return 0; |
| 3297 | 3295 | } |
| @@ -3327,7 +3325,6 @@ static void et131x_pci_remove(struct pci_dev *pdev) · 29 unmodified lines | ||
| 3327 | 3325 | netif_napi_del(&adapter->napi); |
| 3328 | 3326 | phy_disconnect(adapter->phydev); |
| 3329 | 3327 | mdiobus_unregister(adapter->mii_bus); |
| 3330 | − kfree(adapter->mii_bus->irq); | |
| 3331 | 3328 | mdiobus_free(adapter->mii_bus); |
| 3332 | 3329 | |
| 3333 | 3330 | et131x_adapter_memory_free(adapter); |
| @@ -3946,7 +3943,6 @@ static int et131x_pci_setup(struct pci_dev *pdev, · 612 unmodified lines | ||
| 3946 | 3943 | struct net_device *netdev; |
| 3947 | 3944 | struct et131x_adapter *adapter; |
| 3948 | 3945 | int rc; |
| 3949 | − int ii; | |
| 3950 | 3946 | |
| 3951 | 3947 | rc = pci_enable_device(pdev); |
| 3952 | 3948 | if (rc < 0) { |
| @@ -4036,18 +4032,11 @@ static int et131x_pci_setup(struct pci_dev *pdev, · 83 unmodified lines | ||
| 4036 | 4032 | adapter->mii_bus->priv = netdev; |
| 4037 | 4033 | adapter->mii_bus->read = et131x_mdio_read; |
| 4038 | 4034 | adapter->mii_bus->write = et131x_mdio_write; |
| 4039 | − adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), | |
| 4040 | − GFP_KERNEL); | |
| 4041 | − if (!adapter->mii_bus->irq) | |
| 4042 | − goto err_mdio_free; | |
| 4043 | − | |
| 4044 | − for (ii = 0; ii < PHY_MAX_ADDR; ii++) | |
| 4045 | − adapter->mii_bus->irq[ii] = PHY_POLL; | |
| 4046 | 4035 | |
| 4047 | 4036 | rc = mdiobus_register(adapter->mii_bus); |
| 4048 | 4037 | if (rc < 0) { |
| 4049 | 4038 | dev_err(&pdev->dev, "failed to register MII bus\n"); |
| 4050 | − goto err_mdio_free_irq; | |
| 4039 | + goto err_mdio_free; | |
| 4051 | 4040 | } |
| 4052 | 4041 | |
| 4053 | 4042 | rc = et131x_mii_probe(netdev); |
| @@ -4087,8 +4076,6 @@ err_phy_disconnect: · 33 unmodified lines | ||
| 4087 | 4076 | phy_disconnect(adapter->phydev); |
| 4088 | 4077 | err_mdio_unregister: |
| 4089 | 4078 | mdiobus_unregister(adapter->mii_bus); |
| 4090 | −err_mdio_free_irq: | |
| 4091 | − kfree(adapter->mii_bus->irq); | |
| 4092 | 4079 | err_mdio_free: |
| 4093 | 4080 | mdiobus_free(adapter->mii_bus); |
| 4094 | 4081 | err_mem_free: |
| @@ -131,7 +131,6 @@ static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) · 130 unmodified lines | ||
| 131 | 131 | { |
| 132 | 132 | struct altera_tse_private *priv = netdev_priv(dev); |
| 133 | 133 | int ret; |
| 134 | − int i; | |
| 135 | 134 | struct device_node *mdio_node = NULL; |
| 136 | 135 | struct mii_bus *mdio = NULL; |
| 137 | 136 | struct device_node *child_node = NULL; |
| @@ -161,14 +160,6 @@ static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) · 23 unmodified lines | ||
| 161 | 160 | mdio->write = &altera_tse_mdio_write; |
| 162 | 161 | snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id); |
| 163 | 162 | |
| 164 | − mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); | |
| 165 | − if (mdio->irq == NULL) { | |
| 166 | − ret = -ENOMEM; | |
| 167 | − goto out_free_mdio; | |
| 168 | − } | |
| 169 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 170 | − mdio->irq[i] = PHY_POLL; | |
| 171 | − | |
| 172 | 163 | mdio->priv = dev; |
| 173 | 164 | mdio->parent = priv->device; |
| 174 | 165 | |
| @@ -176,7 +167,7 @@ static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) · 1 unmodified line | ||
| 176 | 167 | if (ret != 0) { |
| 177 | 168 | netdev_err(dev, "Cannot register MDIO bus %s\n", |
| 178 | 169 | mdio->id); |
| 179 | − goto out_free_mdio_irq; | |
| 170 | + goto out_free_mdio; | |
| 180 | 171 | } |
| 181 | 172 | |
| 182 | 173 | if (netif_msg_drv(priv)) |
| @@ -184,8 +175,6 @@ static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) · 1 unmodified line | ||
| 184 | 175 | |
| 185 | 176 | priv->mdio = mdio; |
| 186 | 177 | return 0; |
| 187 | −out_free_mdio_irq: | |
| 188 | − kfree(mdio->irq); | |
| 189 | 178 | out_free_mdio: |
| 190 | 179 | mdiobus_free(mdio); |
| 191 | 180 | mdio = NULL; |
| @@ -855,7 +844,7 @@ static int init_phy(struct net_device *dev) · 663 unmodified lines | ||
| 855 | 844 | } |
| 856 | 845 | |
| 857 | 846 | netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n", |
| 858 | − phydev->addr, phydev->phy_id, phydev->link); | |
| 847 | + phydev->mdio.addr, phydev->phy_id, phydev->link); | |
| 859 | 848 | |
| 860 | 849 | priv->phydev = phydev; |
| 861 | 850 | return 0; |
| @@ -344,9 +344,6 @@ static void au1000_mdio_write(struct net_device *dev, int phy_addr, · 343 unmodified lines | ||
| 344 | 344 | |
| 345 | 345 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
| 346 | 346 | { |
| 347 | − /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
| 348 | − * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) | |
| 349 | − */ | |
| 350 | 347 | struct net_device *const dev = bus->priv; |
| 351 | 348 | |
| 352 | 349 | /* make sure the MAC associated with this |
| @@ -502,7 +499,7 @@ static int au1000_mii_probe(struct net_device *dev) · 149 unmodified lines | ||
| 502 | 499 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); |
| 503 | 500 | |
| 504 | 501 | if (aup->phy_addr) |
| 505 | − phydev = aup->mii_bus->phy_map[aup->phy_addr]; | |
| 502 | + phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); | |
| 506 | 503 | else |
| 507 | 504 | netdev_info(dev, "using PHY-less setup\n"); |
| 508 | 505 | return 0; |
| @@ -512,8 +509,8 @@ static int au1000_mii_probe(struct net_device *dev) · 3 unmodified lines | ||
| 512 | 509 | * on the current MAC's MII bus |
| 513 | 510 | */ |
| 514 | 511 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) |
| 515 | − if (aup->mii_bus->phy_map[phy_addr]) { | |
| 516 | − phydev = aup->mii_bus->phy_map[phy_addr]; | |
| 512 | + if (mdiobus_get_phy(aup->mii_bus, aup->phy_addr)) { | |
| 513 | + phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); | |
| 517 | 514 | if (!aup->phy_search_highest_addr) |
| 518 | 515 | /* break out with first one found */ |
| 519 | 516 | break; |
| @@ -531,7 +528,8 @@ static int au1000_mii_probe(struct net_device *dev) · 11 unmodified lines | ||
| 531 | 528 | */ |
| 532 | 529 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { |
| 533 | 530 | struct phy_device *const tmp_phydev = |
| 534 | − aup->mii_bus->phy_map[phy_addr]; | |
| 531 | + mdiobus_get_phy(aup->mii_bus, | |
| 532 | + phy_addr); | |
| 535 | 533 | |
| 536 | 534 | if (aup->mac_id == 1) |
| 537 | 535 | break; |
| @@ -558,7 +556,7 @@ static int au1000_mii_probe(struct net_device *dev) · 20 unmodified lines | ||
| 558 | 556 | /* now we are supposed to have a proper phydev, to attach to... */ |
| 559 | 557 | BUG_ON(phydev->attached_dev); |
| 560 | 558 | |
| 561 | − phydev = phy_connect(dev, dev_name(&phydev->dev), | |
| 559 | + phydev = phy_connect(dev, phydev_name(phydev), | |
| 562 | 560 | &au1000_adjust_link, PHY_INTERFACE_MODE_MII); |
| 563 | 561 | |
| 564 | 562 | if (IS_ERR(phydev)) { |
| @@ -583,9 +581,7 @@ static int au1000_mii_probe(struct net_device *dev) · 18 unmodified lines | ||
| 583 | 581 | aup->old_duplex = -1; |
| 584 | 582 | aup->phy_dev = phydev; |
| 585 | 583 | |
| 586 | − netdev_info(dev, "attached PHY driver [%s] " | |
| 587 | − "(mii_bus:phy_addr=%s, irq=%d)\n", | |
| 588 | − phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
| 584 | + phy_attached_info(phydev); | |
| 589 | 585 | |
| 590 | 586 | return 0; |
| 591 | 587 | } |
| @@ -1293,14 +1289,7 @@ static int au1000_probe(struct platform_device *pdev) · 701 unmodified lines | ||
| 1293 | 1289 | aup->mii_bus->name = "au1000_eth_mii"; |
| 1294 | 1290 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
| 1295 | 1291 | pdev->name, aup->mac_id); |
| 1296 | − aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
| 1297 | − if (aup->mii_bus->irq == NULL) { | |
| 1298 | − err = -ENOMEM; | |
| 1299 | − goto err_out; | |
| 1300 | − } | |
| 1301 | 1292 | |
| 1302 | − for (i = 0; i < PHY_MAX_ADDR; ++i) | |
| 1303 | − aup->mii_bus->irq[i] = PHY_POLL; | |
| 1304 | 1293 | /* if known, set corresponding PHY IRQs */ |
| 1305 | 1294 | if (aup->phy_static_config) |
| 1306 | 1295 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) |
| @@ -2024,7 +2024,6 @@ read_again: · 2023 unmodified lines | ||
| 2024 | 2024 | skb->dev = netdev; |
| 2025 | 2025 | skb->protocol = eth_type_trans(skb, netdev); |
| 2026 | 2026 | skb_record_rx_queue(skb, channel->queue_index); |
| 2027 | − skb_mark_napi_id(skb, napi); | |
| 2028 | 2027 | |
| 2029 | 2028 | napi_gro_receive(napi, skb); |
| 2030 | 2029 | |
| @@ -869,7 +869,7 @@ void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata) · 868 unmodified lines | ||
| 869 | 869 | pdata->mdio_bus = NULL; |
| 870 | 870 | } |
| 871 | 871 | |
| 872 | −struct xgene_mac_ops xgene_gmac_ops = { | |
| 872 | +const struct xgene_mac_ops xgene_gmac_ops = { | |
| 873 | 873 | .init = xgene_gmac_init, |
| 874 | 874 | .reset = xgene_gmac_reset, |
| 875 | 875 | .rx_enable = xgene_gmac_rx_enable, |
| @@ -879,7 +879,7 @@ struct xgene_mac_ops xgene_gmac_ops = { · 3 unmodified lines | ||
| 879 | 879 | .set_mac_addr = xgene_gmac_set_mac_addr, |
| 880 | 880 | }; |
| 881 | 881 | |
| 882 | −struct xgene_port_ops xgene_gport_ops = { | |
| 882 | +const struct xgene_port_ops xgene_gport_ops = { | |
| 883 | 883 | .reset = xgene_enet_reset, |
| 884 | 884 | .cle_bypass = xgene_enet_cle_bypass, |
| 885 | 885 | .shutdown = xgene_gport_shutdown, |
| @@ -340,8 +340,8 @@ int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); · 339 unmodified lines | ||
| 340 | 340 | void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); |
| 341 | 341 | bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); |
| 342 | 342 | |
| 343 | −extern struct xgene_mac_ops xgene_gmac_ops; | |
| 344 | −extern struct xgene_port_ops xgene_gport_ops; | |
| 343 | +extern const struct xgene_mac_ops xgene_gmac_ops; | |
| 344 | +extern const struct xgene_port_ops xgene_gport_ops; | |
| 345 | 345 | extern struct xgene_ring_ops xgene_ring1_ops; |
| 346 | 346 | |
| 347 | 347 | #endif /* __XGENE_ENET_HW_H__ */ |
| @@ -690,7 +690,7 @@ static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata) · 689 unmodified lines | ||
| 690 | 690 | static int xgene_enet_open(struct net_device *ndev) |
| 691 | 691 | { |
| 692 | 692 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); |
| 693 | − struct xgene_mac_ops *mac_ops = pdata->mac_ops; | |
| 693 | + const struct xgene_mac_ops *mac_ops = pdata->mac_ops; | |
| 694 | 694 | int ret; |
| 695 | 695 | |
| 696 | 696 | mac_ops->tx_enable(pdata); |
| @@ -714,7 +714,7 @@ static int xgene_enet_open(struct net_device *ndev) · 17 unmodified lines | ||
| 714 | 714 | static int xgene_enet_close(struct net_device *ndev) |
| 715 | 715 | { |
| 716 | 716 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); |
| 717 | − struct xgene_mac_ops *mac_ops = pdata->mac_ops; | |
| 717 | + const struct xgene_mac_ops *mac_ops = pdata->mac_ops; | |
| 718 | 718 | |
| 719 | 719 | netif_stop_queue(ndev); |
| 720 | 720 | |
| @@ -1090,7 +1090,7 @@ static const struct net_device_ops xgene_ndev_ops = { · 369 unmodified lines | ||
| 1090 | 1090 | }; |
| 1091 | 1091 | |
| 1092 | 1092 | #ifdef CONFIG_ACPI |
| 1093 | −static int xgene_get_port_id_acpi(struct device *dev, | |
| 1093 | +static void xgene_get_port_id_acpi(struct device *dev, | |
| 1094 | 1094 | struct xgene_enet_pdata *pdata) |
| 1095 | 1095 | { |
| 1096 | 1096 | acpi_status status; |
| @@ -1103,24 +1103,19 @@ static int xgene_get_port_id_acpi(struct device *dev, · 6 unmodified lines | ||
| 1103 | 1103 | pdata->port_id = temp; |
| 1104 | 1104 | } |
| 1105 | 1105 | |
| 1106 | − return 0; | |
| 1106 | + return; | |
| 1107 | 1107 | } |
| 1108 | 1108 | #endif |
| 1109 | 1109 | |
| 1110 | −static int xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata) | |
| 1110 | +static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata) | |
| 1111 | 1111 | { |
| 1112 | 1112 | u32 id = 0; |
| 1113 | − int ret; | |
| 1114 | 1113 | |
| 1115 | − ret = of_property_read_u32(dev->of_node, "port-id", &id); | |
| 1116 | − if (ret) { | |
| 1117 | − pdata->port_id = 0; | |
| 1118 | − ret = 0; | |
| 1119 | − } else { | |
| 1120 | − pdata->port_id = id & BIT(0); | |
| 1121 | − } | |
| 1114 | + of_property_read_u32(dev->of_node, "port-id", &id); | |
| 1122 | 1115 | |
| 1123 | − return ret; | |
| 1116 | + pdata->port_id = id & BIT(0); | |
| 1117 | + | |
| 1118 | + return; | |
| 1124 | 1119 | } |
| 1125 | 1120 | |
| 1126 | 1121 | static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata) |
| @@ -1215,13 +1210,11 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) · 88 unmodified lines | ||
| 1215 | 1210 | } |
| 1216 | 1211 | |
| 1217 | 1212 | if (dev->of_node) |
| 1218 | − ret = xgene_get_port_id_dt(dev, pdata); | |
| 1213 | + xgene_get_port_id_dt(dev, pdata); | |
| 1219 | 1214 | #ifdef CONFIG_ACPI |
| 1220 | 1215 | else |
| 1221 | − ret = xgene_get_port_id_acpi(dev, pdata); | |
| 1216 | + xgene_get_port_id_acpi(dev, pdata); | |
| 1222 | 1217 | #endif |
| 1223 | − if (ret) | |
| 1224 | − return ret; | |
| 1225 | 1218 | |
| 1226 | 1219 | if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN)) |
| 1227 | 1220 | eth_hw_addr_random(ndev); |
| @@ -1429,7 +1422,7 @@ static int xgene_enet_probe(struct platform_device *pdev) · 201 unmodified lines | ||
| 1429 | 1422 | struct net_device *ndev; |
| 1430 | 1423 | struct xgene_enet_pdata *pdata; |
| 1431 | 1424 | struct device *dev = &pdev->dev; |
| 1432 | − struct xgene_mac_ops *mac_ops; | |
| 1425 | + const struct xgene_mac_ops *mac_ops; | |
| 1433 | 1426 | const struct of_device_id *of_id; |
| 1434 | 1427 | int ret; |
| 1435 | 1428 | |
| @@ -1516,7 +1509,7 @@ err: · 80 unmodified lines | ||
| 1516 | 1509 | static int xgene_enet_remove(struct platform_device *pdev) |
| 1517 | 1510 | { |
| 1518 | 1511 | struct xgene_enet_pdata *pdata; |
| 1519 | − struct xgene_mac_ops *mac_ops; | |
| 1512 | + const struct xgene_mac_ops *mac_ops; | |
| 1520 | 1513 | struct net_device *ndev; |
| 1521 | 1514 | |
| 1522 | 1515 | pdata = platform_get_drvdata(pdev); |
| @@ -174,8 +174,8 @@ struct xgene_enet_pdata { · 173 unmodified lines | ||
| 174 | 174 | int phy_mode; |
| 175 | 175 | enum xgene_enet_rm rm; |
| 176 | 176 | struct rtnl_link_stats64 stats; |
| 177 | − struct xgene_mac_ops *mac_ops; | |
| 178 | − struct xgene_port_ops *port_ops; | |
| 177 | + const struct xgene_mac_ops *mac_ops; | |
| 178 | + const struct xgene_port_ops *port_ops; | |
| 179 | 179 | struct xgene_ring_ops *ring_ops; |
| 180 | 180 | struct delayed_work link_work; |
| 181 | 181 | u32 port_id; |
| @@ -405,7 +405,7 @@ static void xgene_enet_link_state(struct work_struct *work) · 404 unmodified lines | ||
| 405 | 405 | schedule_delayed_work(&p->link_work, poll_interval); |
| 406 | 406 | } |
| 407 | 407 | |
| 408 | −struct xgene_mac_ops xgene_sgmac_ops = { | |
| 408 | +const struct xgene_mac_ops xgene_sgmac_ops = { | |
| 409 | 409 | .init = xgene_sgmac_init, |
| 410 | 410 | .reset = xgene_sgmac_reset, |
| 411 | 411 | .rx_enable = xgene_sgmac_rx_enable, |
| @@ -416,7 +416,7 @@ struct xgene_mac_ops xgene_sgmac_ops = { · 4 unmodified lines | ||
| 416 | 416 | .link_state = xgene_enet_link_state |
| 417 | 417 | }; |
| 418 | 418 | |
| 419 | −struct xgene_port_ops xgene_sgport_ops = { | |
| 419 | +const struct xgene_port_ops xgene_sgport_ops = { | |
| 420 | 420 | .reset = xgene_enet_reset, |
| 421 | 421 | .cle_bypass = xgene_enet_cle_bypass, |
| 422 | 422 | .shutdown = xgene_enet_shutdown |
| @@ -35,7 +35,7 @@ · 34 unmodified lines | ||
| 35 | 35 | #define MPA_IDLE_WITH_QMI_EMPTY BIT(12) |
| 36 | 36 | #define SG_RX_DV_GATE_REG_0_ADDR 0x0dfc |
| 37 | 37 | |
| 38 | −extern struct xgene_mac_ops xgene_sgmac_ops; | |
| 39 | −extern struct xgene_port_ops xgene_sgport_ops; | |
| 38 | +extern const struct xgene_mac_ops xgene_sgmac_ops; | |
| 39 | +extern const struct xgene_port_ops xgene_sgport_ops; | |
| 40 | 40 | |
| 41 | 41 | #endif /* __XGENE_ENET_SGMAC_H__ */ |
| @@ -326,7 +326,7 @@ static void xgene_enet_link_state(struct work_struct *work) · 325 unmodified lines | ||
| 326 | 326 | schedule_delayed_work(&pdata->link_work, poll_interval); |
| 327 | 327 | } |
| 328 | 328 | |
| 329 | −struct xgene_mac_ops xgene_xgmac_ops = { | |
| 329 | +const struct xgene_mac_ops xgene_xgmac_ops = { | |
| 330 | 330 | .init = xgene_xgmac_init, |
| 331 | 331 | .reset = xgene_xgmac_reset, |
| 332 | 332 | .rx_enable = xgene_xgmac_rx_enable, |
| @@ -338,7 +338,7 @@ struct xgene_mac_ops xgene_xgmac_ops = { · 5 unmodified lines | ||
| 338 | 338 | .link_state = xgene_enet_link_state |
| 339 | 339 | }; |
| 340 | 340 | |
| 341 | −struct xgene_port_ops xgene_xgport_ops = { | |
| 341 | +const struct xgene_port_ops xgene_xgport_ops = { | |
| 342 | 342 | .reset = xgene_enet_reset, |
| 343 | 343 | .cle_bypass = xgene_enet_xgcle_bypass, |
| 344 | 344 | .shutdown = xgene_enet_shutdown, |
| @@ -69,7 +69,7 @@ · 68 unmodified lines | ||
| 69 | 69 | #define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410 |
| 70 | 70 | #define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804 |
| 71 | 71 | |
| 72 | −extern struct xgene_mac_ops xgene_xgmac_ops; | |
| 73 | −extern struct xgene_port_ops xgene_xgport_ops; | |
| 72 | +extern const struct xgene_mac_ops xgene_xgmac_ops; | |
| 73 | +extern const struct xgene_port_ops xgene_xgport_ops; | |
| 74 | 74 | |
| 75 | 75 | #endif /* __XGENE_ENET_XGMAC_H__ */ |
| @@ -34,9 +34,9 @@ config EMAC_ROCKCHIP · 33 unmodified lines | ||
| 34 | 34 | select ARC_EMAC_CORE |
| 35 | 35 | depends on OF_IRQ && OF_NET && REGULATOR && HAS_DMA |
| 36 | 36 | ---help--- |
| 37 | − Support for Rockchip RK3066/RK3188 EMAC ethernet controllers. | |
| 37 | + Support for Rockchip RK3036/RK3066/RK3188 EMAC ethernet controllers. | |
| 38 | 38 | This selects Rockchip SoC glue layer support for the |
| 39 | − emac device driver. This driver is used for RK3066/RK3188 | |
| 39 | + emac device driver. This driver is used for RK3036/RK3066/RK3188 | |
| 40 | 40 | EMAC ethernet controller. |
| 41 | 41 | |
| 42 | 42 | endif # NET_VENDOR_ARC |
| @@ -25,17 +25,13 @@ · 24 unmodified lines | ||
| 25 | 25 | #include "emac.h" |
| 26 | 26 | |
| 27 | 27 | #define DRV_NAME "rockchip_emac" |
| 28 | −#define DRV_VERSION "1.0" | |
| 29 | − | |
| 30 | −#define GRF_MODE_MII (1UL << 0) | |
| 31 | −#define GRF_MODE_RMII (0UL << 0) | |
| 32 | −#define GRF_SPEED_10M (0UL << 1) | |
| 33 | −#define GRF_SPEED_100M (1UL << 1) | |
| 34 | −#define GRF_SPEED_ENABLE_BIT (1UL << 17) | |
| 35 | −#define GRF_MODE_ENABLE_BIT (1UL << 16) | |
| 28 | +#define DRV_VERSION "1.1" | |
| 36 | 29 | |
| 37 | 30 | struct emac_rockchip_soc_data { |
| 38 | − int grf_offset; | |
| 31 | + unsigned int grf_offset; | |
| 32 | + unsigned int grf_mode_offset; | |
| 33 | + unsigned int grf_speed_offset; | |
| 34 | + bool need_div_macclk; | |
| 39 | 35 | }; |
| 40 | 36 | |
| 41 | 37 | struct rockchip_priv_data { |
| @@ -44,23 +40,22 @@ struct rockchip_priv_data { · 2 unmodified lines | ||
| 44 | 40 | const struct emac_rockchip_soc_data *soc_data; |
| 45 | 41 | struct regulator *regulator; |
| 46 | 42 | struct clk *refclk; |
| 43 | + struct clk *macclk; | |
| 47 | 44 | }; |
| 48 | 45 | |
| 49 | 46 | static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed) |
| 50 | 47 | { |
| 51 | 48 | struct rockchip_priv_data *emac = priv; |
| 49 | + u32 speed_offset = emac->soc_data->grf_speed_offset; | |
| 52 | 50 | u32 data; |
| 53 | 51 | int err = 0; |
| 54 | 52 | |
| 55 | − /* write-enable bits */ | |
| 56 | − data = GRF_SPEED_ENABLE_BIT; | |
| 57 | − | |
| 58 | 53 | switch(speed) { |
| 59 | 54 | case 10: |
| 60 | − data |= GRF_SPEED_10M; | |
| 55 | + data = (1 << (speed_offset + 16)) | (0 << speed_offset); | |
| 61 | 56 | break; |
| 62 | 57 | case 100: |
| 63 | − data |= GRF_SPEED_100M; | |
| 58 | + data = (1 << (speed_offset + 16)) | (1 << speed_offset); | |
| 64 | 59 | break; |
| 65 | 60 | default: |
| 66 | 61 | pr_err("speed %u not supported\n", speed); |
| @@ -72,14 +67,25 @@ static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed) · 5 unmodified lines | ||
| 72 | 67 | pr_err("unable to apply speed %u to grf (%d)\n", speed, err); |
| 73 | 68 | } |
| 74 | 69 | |
| 75 | −static const struct emac_rockchip_soc_data emac_rockchip_dt_data[] = { | |
| 76 | − { .grf_offset = 0x154 }, /* rk3066 */ | |
| 77 | − { .grf_offset = 0x0a4 }, /* rk3188 */ | |
| 70 | +static const struct emac_rockchip_soc_data emac_rk3036_emac_data = { | |
| 71 | + .grf_offset = 0x140, .grf_mode_offset = 8, | |
| 72 | + .grf_speed_offset = 9, .need_div_macclk = 1, | |
| 73 | +}; | |
| 74 | + | |
| 75 | +static const struct emac_rockchip_soc_data emac_rk3066_emac_data = { | |
| 76 | + .grf_offset = 0x154, .grf_mode_offset = 0, | |
| 77 | + .grf_speed_offset = 1, .need_div_macclk = 0, | |
| 78 | +}; | |
| 79 | + | |
| 80 | +static const struct emac_rockchip_soc_data emac_rk3188_emac_data = { | |
| 81 | + .grf_offset = 0x0a4, .grf_mode_offset = 0, | |
| 82 | + .grf_speed_offset = 1, .need_div_macclk = 0, | |
| 78 | 83 | }; |
| 79 | 84 | |
| 80 | 85 | static const struct of_device_id emac_rockchip_dt_ids[] = { |
| 81 | − { .compatible = "rockchip,rk3066-emac", .data = &emac_rockchip_dt_data[0] }, | |
| 82 | − { .compatible = "rockchip,rk3188-emac", .data = &emac_rockchip_dt_data[1] }, | |
| 86 | + { .compatible = "rockchip,rk3036-emac", .data = &emac_rk3036_emac_data }, | |
| 87 | + { .compatible = "rockchip,rk3066-emac", .data = &emac_rk3066_emac_data }, | |
| 88 | + { .compatible = "rockchip,rk3188-emac", .data = &emac_rk3188_emac_data }, | |
| 83 | 89 | { /* Sentinel */ } |
| 84 | 90 | }; |
| 85 | 91 | |
| @@ -110,7 +116,7 @@ static int emac_rockchip_probe(struct platform_device *pdev) · 24 unmodified lines | ||
| 110 | 116 | |
| 111 | 117 | interface = of_get_phy_mode(dev->of_node); |
| 112 | 118 | |
| 113 | − /* RK3066 and RK3188 SoCs only support RMII */ | |
| 119 | + /* RK3036/RK3066/RK3188 SoCs only support RMII */ | |
| 114 | 120 | if (interface != PHY_INTERFACE_MODE_RMII) { |
| 115 | 121 | dev_err(dev, "unsupported phy interface mode %d\n", interface); |
| 116 | 122 | err = -ENOTSUPP; |
| @@ -164,15 +170,12 @@ static int emac_rockchip_probe(struct platform_device *pdev) · 47 unmodified lines | ||
| 164 | 170 | } |
| 165 | 171 | } |
| 166 | 172 | |
| 167 | − err = arc_emac_probe(ndev, interface); | |
| 168 | − if (err) | |
| 169 | − goto out_regulator_disable; | |
| 170 | − | |
| 171 | − /* write-enable bits */ | |
| 172 | − data = GRF_MODE_ENABLE_BIT | GRF_SPEED_ENABLE_BIT; | |
| 173 | − | |
| 174 | − data |= GRF_SPEED_100M; | |
| 175 | − data |= GRF_MODE_RMII; | |
| 173 | + /* Set speed 100M */ | |
| 174 | + data = (1 << (priv->soc_data->grf_speed_offset + 16)) | | |
| 175 | + (1 << priv->soc_data->grf_speed_offset); | |
| 176 | + /* Set RMII mode */ | |
| 177 | + data |= (1 << (priv->soc_data->grf_mode_offset + 16)) | | |
| 178 | + (0 << priv->soc_data->grf_mode_offset); | |
| 176 | 179 | |
| 177 | 180 | err = regmap_write(priv->grf, priv->soc_data->grf_offset, data); |
| 178 | 181 | if (err) { |
| @@ -184,6 +187,33 @@ static int emac_rockchip_probe(struct platform_device *pdev) · 5 unmodified lines | ||
| 184 | 187 | err = clk_set_rate(priv->refclk, 50000000); |
| 185 | 188 | if (err) |
| 186 | 189 | dev_err(dev, "failed to change reference clock rate (%d)\n", err); |
| 190 | + | |
| 191 | + if (priv->soc_data->need_div_macclk) { | |
| 192 | + priv->macclk = devm_clk_get(dev, "macclk"); | |
| 193 | + if (IS_ERR(priv->macclk)) { | |
| 194 | + dev_err(dev, "failed to retrieve mac clock (%ld)\n", PTR_ERR(priv->macclk)); | |
| 195 | + err = PTR_ERR(priv->macclk); | |
| 196 | + goto out_regulator_disable; | |
| 197 | + } | |
| 198 | + | |
| 199 | + err = clk_prepare_enable(priv->macclk); | |
| 200 | + if (err) { | |
| 201 | + dev_err(dev, "failed to enable mac clock (%d)\n", err); | |
| 202 | + goto out_regulator_disable; | |
| 203 | + } | |
| 204 | + | |
| 205 | + /* RMII TX/RX needs always a rate of 25MHz */ | |
| 206 | + err = clk_set_rate(priv->macclk, 25000000); | |
| 207 | + if (err) | |
| 208 | + dev_err(dev, "failed to change mac clock rate (%d)\n", err); | |
| 209 | + } | |
| 210 | + | |
| 211 | + err = arc_emac_probe(ndev, interface); | |
| 212 | + if (err) { | |
| 213 | + dev_err(dev, "failed to probe arc emac (%d)\n", err); | |
| 214 | + goto out_regulator_disable; | |
| 215 | + } | |
| 216 | + | |
| 187 | 217 | return 0; |
| 188 | 218 | |
| 189 | 219 | out_regulator_disable: |
| @@ -958,13 +958,13 @@ void alx_configure_basic(struct alx_hw *hw) · 957 unmodified lines | ||
| 958 | 958 | alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd); |
| 959 | 959 | alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt); |
| 960 | 960 | |
| 961 | − raw_mtu = hw->mtu + ETH_HLEN; | |
| 962 | − alx_write_mem32(hw, ALX_MTU, raw_mtu + 8); | |
| 963 | − if (raw_mtu > ALX_MTU_JUMBO_TH) | |
| 961 | + raw_mtu = ALX_RAW_MTU(hw->mtu); | |
| 962 | + alx_write_mem32(hw, ALX_MTU, raw_mtu); | |
| 963 | + if (raw_mtu > (ALX_MTU_JUMBO_TH + ETH_FCS_LEN + VLAN_HLEN)) | |
| 964 | 964 | hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE; |
| 965 | 965 | |
| 966 | − if ((raw_mtu + 8) < ALX_TXQ1_JUMBO_TSO_TH) | |
| 967 | − val = (raw_mtu + 8 + 7) >> 3; | |
| 966 | + if (raw_mtu < ALX_TXQ1_JUMBO_TSO_TH) | |
| 967 | + val = (raw_mtu + 7) >> 3; | |
| 968 | 968 | else |
| 969 | 969 | val = ALX_TXQ1_JUMBO_TSO_TH >> 3; |
| 970 | 970 | alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN); |
| @@ -37,6 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | #include <linux/types.h> |
| 38 | 38 | #include <linux/mdio.h> |
| 39 | 39 | #include <linux/pci.h> |
| 40 | +#include <linux/if_vlan.h> | |
| 40 | 41 | #include "reg.h" |
| 41 | 42 | |
| 42 | 43 | /* Transmit Packet Descriptor, contains 4 32-bit words. |
| @@ -343,12 +344,14 @@ struct alx_rrd { · 300 unmodified lines | ||
| 343 | 344 | ALX_RSS_HASH_TYPE_IPV4_TCP | \ |
| 344 | 345 | ALX_RSS_HASH_TYPE_IPV6 | \ |
| 345 | 346 | ALX_RSS_HASH_TYPE_IPV6_TCP) |
| 346 | −#define ALX_DEF_RXBUF_SIZE 1536 | |
| 347 | +#define ALX_FRAME_PAD 16 | |
| 348 | +#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) | |
| 349 | +#define ALX_MAX_FRAME_LEN(_mtu) (ALIGN((ALX_RAW_MTU(_mtu) + ALX_FRAME_PAD), 8)) | |
| 350 | +#define ALX_DEF_RXBUF_SIZE ALX_MAX_FRAME_LEN(1500) | |
| 347 | 351 | #define ALX_MAX_JUMBO_PKT_SIZE (9*1024) |
| 348 | 352 | #define ALX_MAX_TSO_PKT_SIZE (7*1024) |
| 349 | 353 | #define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE |
| 350 | −#define ALX_MIN_FRAME_SIZE 68 | |
| 351 | −#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) | |
| 354 | +#define ALX_MIN_FRAME_SIZE (ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) | |
| 352 | 355 | |
| 353 | 356 | #define ALX_MAX_RX_QUEUES 8 |
| 354 | 357 | #define ALX_MAX_TX_QUEUES 4 |
| @@ -577,7 +577,6 @@ static int alx_alloc_rings(struct alx_priv *alx) · 576 unmodified lines | ||
| 577 | 577 | |
| 578 | 578 | alx->int_mask &= ~ALX_ISR_ALL_QUEUES; |
| 579 | 579 | alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0; |
| 580 | − alx->tx_ringsz = alx->tx_ringsz; | |
| 581 | 580 | |
| 582 | 581 | netif_napi_add(alx->dev, &alx->napi, alx_poll, 64); |
| 583 | 582 | |
| @@ -705,7 +704,7 @@ static int alx_init_sw(struct alx_priv *alx) · 121 unmodified lines | ||
| 705 | 704 | |
| 706 | 705 | hw->smb_timer = 400; |
| 707 | 706 | hw->mtu = alx->dev->mtu; |
| 708 | − alx->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8); | |
| 707 | + alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu); | |
| 709 | 708 | alx->tx_ringsz = 256; |
| 710 | 709 | alx->rx_ringsz = 512; |
| 711 | 710 | hw->imt = 200; |
| @@ -806,7 +805,7 @@ static void alx_reinit(struct alx_priv *alx) · 94 unmodified lines | ||
| 806 | 805 | static int alx_change_mtu(struct net_device *netdev, int mtu) |
| 807 | 806 | { |
| 808 | 807 | struct alx_priv *alx = netdev_priv(netdev); |
| 809 | − int max_frame = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
| 808 | + int max_frame = ALX_MAX_FRAME_LEN(mtu); | |
| 810 | 809 | |
| 811 | 810 | if ((max_frame < ALX_MIN_FRAME_SIZE) || |
| 812 | 811 | (max_frame > ALX_MAX_FRAME_SIZE)) |
| @@ -817,8 +816,7 @@ static int alx_change_mtu(struct net_device *netdev, int mtu) · 4 unmodified lines | ||
| 817 | 816 | |
| 818 | 817 | netdev->mtu = mtu; |
| 819 | 818 | alx->hw.mtu = mtu; |
| 820 | − alx->rxbuf_size = mtu > ALX_DEF_RXBUF_SIZE ? | |
| 821 | − ALIGN(max_frame, 8) : ALX_DEF_RXBUF_SIZE; | |
| 819 | + alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE); | |
| 822 | 820 | netdev_update_features(netdev); |
| 823 | 821 | if (netif_running(netdev)) |
| 824 | 822 | alx_reinit(alx); |
| @@ -2263,24 +2263,16 @@ static int b44_register_phy_one(struct b44 *bp) · 2262 unmodified lines | ||
| 2263 | 2263 | mii_bus->parent = sdev->dev; |
| 2264 | 2264 | mii_bus->phy_mask = ~(1 << bp->phy_addr); |
| 2265 | 2265 | snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%x", instance); |
| 2266 | − mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
| 2267 | − if (!mii_bus->irq) { | |
| 2268 | − dev_err(sdev->dev, "mii_bus irq allocation failed\n"); | |
| 2269 | − err = -ENOMEM; | |
| 2270 | − goto err_out_mdiobus; | |
| 2271 | − } | |
| 2272 | − | |
| 2273 | − memset(mii_bus->irq, PHY_POLL, sizeof(int) * PHY_MAX_ADDR); | |
| 2274 | 2266 | |
| 2275 | 2267 | bp->mii_bus = mii_bus; |
| 2276 | 2268 | |
| 2277 | 2269 | err = mdiobus_register(mii_bus); |
| 2278 | 2270 | if (err) { |
| 2279 | 2271 | dev_err(sdev->dev, "failed to register MII bus\n"); |
| 2280 | − goto err_out_mdiobus_irq; | |
| 2272 | + goto err_out_mdiobus; | |
| 2281 | 2273 | } |
| 2282 | 2274 | |
| 2283 | − if (!bp->mii_bus->phy_map[bp->phy_addr] && | |
| 2275 | + if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) && | |
| 2284 | 2276 | (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) { |
| 2285 | 2277 | |
| 2286 | 2278 | dev_info(sdev->dev, |
| @@ -2313,19 +2305,15 @@ static int b44_register_phy_one(struct b44 *bp) · 26 unmodified lines | ||
| 2313 | 2305 | |
| 2314 | 2306 | bp->phydev = phydev; |
| 2315 | 2307 | bp->old_link = 0; |
| 2316 | − bp->phy_addr = phydev->addr; | |
| 2308 | + bp->phy_addr = phydev->mdio.addr; | |
| 2317 | 2309 | |
| 2318 | − dev_info(sdev->dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
| 2319 | − phydev->drv->name, dev_name(&phydev->dev)); | |
| 2310 | + phy_attached_info(phydev); | |
| 2320 | 2311 | |
| 2321 | 2312 | return 0; |
| 2322 | 2313 | |
| 2323 | 2314 | err_out_mdiobus_unregister: |
| 2324 | 2315 | mdiobus_unregister(mii_bus); |
| 2325 | 2316 | |
| 2326 | −err_out_mdiobus_irq: | |
| 2327 | − kfree(mii_bus->irq); | |
| 2328 | − | |
| 2329 | 2317 | err_out_mdiobus: |
| 2330 | 2318 | mdiobus_free(mii_bus); |
| 2331 | 2319 | |
| @@ -2339,7 +2327,6 @@ static void b44_unregister_phy_one(struct b44 *bp) · 7 unmodified lines | ||
| 2339 | 2327 | |
| 2340 | 2328 | phy_disconnect(bp->phydev); |
| 2341 | 2329 | mdiobus_unregister(mii_bus); |
| 2342 | − kfree(mii_bus->irq); | |
| 2343 | 2330 | mdiobus_free(mii_bus); |
| 2344 | 2331 | } |
| 2345 | 2332 | |
| @@ -908,8 +908,7 @@ static int bcm_enet_open(struct net_device *dev) · 907 unmodified lines | ||
| 908 | 908 | else |
| 909 | 909 | phydev->advertising &= ~SUPPORTED_Pause; |
| 910 | 910 | |
| 911 | − dev_info(kdev, "attached PHY at address %d [%s]\n", | |
| 912 | − phydev->addr, phydev->drv->name); | |
| 911 | + phy_attached_info(phydev); | |
| 913 | 912 | |
| 914 | 913 | priv->old_link = 0; |
| 915 | 914 | priv->old_duplex = -1; |
| @@ -1849,17 +1848,8 @@ static int bcm_enet_probe(struct platform_device *pdev) · 933 unmodified lines | ||
| 1849 | 1848 | * if a slave is not present on hw */ |
| 1850 | 1849 | bus->phy_mask = ~(1 << priv->phy_id); |
| 1851 | 1850 | |
| 1852 | − bus->irq = devm_kzalloc(&pdev->dev, sizeof(int) * PHY_MAX_ADDR, | |
| 1853 | − GFP_KERNEL); | |
| 1854 | − if (!bus->irq) { | |
| 1855 | − ret = -ENOMEM; | |
| 1856 | − goto out_free_mdio; | |
| 1857 | − } | |
| 1858 | − | |
| 1859 | 1851 | if (priv->has_phy_interrupt) |
| 1860 | 1852 | bus->irq[priv->phy_id] = priv->phy_interrupt; |
| 1861 | − else | |
| 1862 | − bus->irq[priv->phy_id] = PHY_POLL; | |
| 1863 | 1853 | |
| 1864 | 1854 | ret = mdiobus_register(bus); |
| 1865 | 1855 | if (ret) { |
| @@ -2884,33 +2874,21 @@ struct platform_driver bcm63xx_enet_shared_driver = { · 1018 unmodified lines | ||
| 2884 | 2874 | }, |
| 2885 | 2875 | }; |
| 2886 | 2876 | |
| 2877 | +static struct platform_driver * const drivers[] = { | |
| 2878 | + &bcm63xx_enet_shared_driver, | |
| 2879 | + &bcm63xx_enet_driver, | |
| 2880 | + &bcm63xx_enetsw_driver, | |
| 2881 | +}; | |
| 2882 | + | |
| 2887 | 2883 | /* entry point */ |
| 2888 | 2884 | static int __init bcm_enet_init(void) |
| 2889 | 2885 | { |
| 2890 | − int ret; | |
| 2891 | − | |
| 2892 | − ret = platform_driver_register(&bcm63xx_enet_shared_driver); | |
| 2893 | − if (ret) | |
| 2894 | − return ret; | |
| 2895 | − | |
| 2896 | − ret = platform_driver_register(&bcm63xx_enet_driver); | |
| 2897 | − if (ret) | |
| 2898 | − platform_driver_unregister(&bcm63xx_enet_shared_driver); | |
| 2899 | − | |
| 2900 | − ret = platform_driver_register(&bcm63xx_enetsw_driver); | |
| 2901 | − if (ret) { | |
| 2902 | − platform_driver_unregister(&bcm63xx_enet_driver); | |
| 2903 | − platform_driver_unregister(&bcm63xx_enet_shared_driver); | |
| 2904 | − } | |
| 2905 | − | |
| 2906 | − return ret; | |
| 2886 | + return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); | |
| 2907 | 2887 | } |
| 2908 | 2888 | |
| 2909 | 2889 | static void __exit bcm_enet_exit(void) |
| 2910 | 2890 | { |
| 2911 | − platform_driver_unregister(&bcm63xx_enet_driver); | |
| 2912 | − platform_driver_unregister(&bcm63xx_enetsw_driver); | |
| 2913 | − platform_driver_unregister(&bcm63xx_enet_shared_driver); | |
| 2891 | + platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); | |
| 2914 | 2892 | } |
| 2915 | 2893 | |
| 2916 | 2894 | |
| @@ -1216,7 +1216,7 @@ static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, · 1215 unmodified lines | ||
| 1216 | 1216 | /* Initialize SW view of the ring */ |
| 1217 | 1217 | spin_lock_init(&ring->lock); |
| 1218 | 1218 | ring->priv = priv; |
| 1219 | − netif_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); | |
| 1219 | + netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); | |
| 1220 | 1220 | ring->index = index; |
| 1221 | 1221 | ring->size = size; |
| 1222 | 1222 | ring->alloc_size = ring->size; |
| @@ -1471,7 +1471,7 @@ static int bgmac_mii_register(struct bgmac *bgmac) · 1470 unmodified lines | ||
| 1471 | 1471 | struct mii_bus *mii_bus; |
| 1472 | 1472 | struct phy_device *phy_dev; |
| 1473 | 1473 | char bus_id[MII_BUS_ID_SIZE + 3]; |
| 1474 | − int i, err = 0; | |
| 1474 | + int err = 0; | |
| 1475 | 1475 | |
| 1476 | 1476 | if (ci->id == BCMA_CHIP_ID_BCM4707 || |
| 1477 | 1477 | ci->id == BCMA_CHIP_ID_BCM53018) |
| @@ -1490,18 +1490,10 @@ static int bgmac_mii_register(struct bgmac *bgmac) · 12 unmodified lines | ||
| 1490 | 1490 | mii_bus->parent = &bgmac->core->dev; |
| 1491 | 1491 | mii_bus->phy_mask = ~(1 << bgmac->phyaddr); |
| 1492 | 1492 | |
| 1493 | − mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); | |
| 1494 | − if (!mii_bus->irq) { | |
| 1495 | − err = -ENOMEM; | |
| 1496 | − goto err_free_bus; | |
| 1497 | − } | |
| 1498 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 1499 | − mii_bus->irq[i] = PHY_POLL; | |
| 1500 | − | |
| 1501 | 1493 | err = mdiobus_register(mii_bus); |
| 1502 | 1494 | if (err) { |
| 1503 | 1495 | bgmac_err(bgmac, "Registration of mii bus failed\n"); |
| 1504 | − goto err_free_irq; | |
| 1496 | + goto err_free_bus; | |
| 1505 | 1497 | } |
| 1506 | 1498 | |
| 1507 | 1499 | bgmac->mii_bus = mii_bus; |
| @@ -1522,8 +1514,6 @@ static int bgmac_mii_register(struct bgmac *bgmac) · 14 unmodified lines | ||
| 1522 | 1514 | |
| 1523 | 1515 | err_unregister_bus: |
| 1524 | 1516 | mdiobus_unregister(mii_bus); |
| 1525 | −err_free_irq: | |
| 1526 | − kfree(mii_bus->irq); | |
| 1527 | 1517 | err_free_bus: |
| 1528 | 1518 | mdiobus_free(mii_bus); |
| 1529 | 1519 | return err; |
| @@ -1534,7 +1524,6 @@ static void bgmac_mii_unregister(struct bgmac *bgmac) · 4 unmodified lines | ||
| 1534 | 1524 | struct mii_bus *mii_bus = bgmac->mii_bus; |
| 1535 | 1525 | |
| 1536 | 1526 | mdiobus_unregister(mii_bus); |
| 1537 | − kfree(mii_bus->irq); | |
| 1538 | 1527 | mdiobus_free(mii_bus); |
| 1539 | 1528 | } |
| 1540 | 1529 | |
| @@ -540,10 +540,6 @@ struct bnx2x_fastpath { · 539 unmodified lines | ||
| 540 | 540 | |
| 541 | 541 | struct napi_struct napi; |
| 542 | 542 | |
| 543 | −#ifdef CONFIG_NET_RX_BUSY_POLL | |
| 544 | − unsigned long busy_poll_state; | |
| 545 | −#endif | |
| 546 | − | |
| 547 | 543 | union host_hc_status_block status_blk; |
| 548 | 544 | /* chip independent shortcuts into sb structure */ |
| 549 | 545 | __le16 *sb_index_values; |
| @@ -594,8 +590,6 @@ struct bnx2x_fastpath { · 44 unmodified lines | ||
| 594 | 590 | /* The last maximal completed SGE */ |
| 595 | 591 | u16 last_max_sge; |
| 596 | 592 | __le16 *rx_cons_sb; |
| 597 | − unsigned long rx_pkt, | |
| 598 | − rx_calls; | |
| 599 | 593 | |
| 600 | 594 | /* TPA related */ |
| 601 | 595 | struct bnx2x_agg_info *tpa_info; |
| @@ -617,115 +611,6 @@ struct bnx2x_fastpath { · 15 unmodified lines | ||
| 617 | 611 | #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) |
| 618 | 612 | #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) |
| 619 | 613 | |
| 620 | −#ifdef CONFIG_NET_RX_BUSY_POLL | |
| 621 | − | |
| 622 | −enum bnx2x_fp_state { | |
| 623 | − BNX2X_STATE_FP_NAPI = BIT(0), /* NAPI handler owns the queue */ | |
| 624 | − | |
| 625 | − BNX2X_STATE_FP_NAPI_REQ_BIT = 1, /* NAPI would like to own the queue */ | |
| 626 | − BNX2X_STATE_FP_NAPI_REQ = BIT(1), | |
| 627 | − | |
| 628 | − BNX2X_STATE_FP_POLL_BIT = 2, | |
| 629 | − BNX2X_STATE_FP_POLL = BIT(2), /* busy_poll owns the queue */ | |
| 630 | − | |
| 631 | − BNX2X_STATE_FP_DISABLE_BIT = 3, /* queue is dismantled */ | |
| 632 | −}; | |
| 633 | − | |
| 634 | −static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) | |
| 635 | −{ | |
| 636 | − WRITE_ONCE(fp->busy_poll_state, 0); | |
| 637 | −} | |
| 638 | − | |
| 639 | −/* called from the device poll routine to get ownership of a FP */ | |
| 640 | −static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) | |
| 641 | −{ | |
| 642 | − unsigned long prev, old = READ_ONCE(fp->busy_poll_state); | |
| 643 | − | |
| 644 | − while (1) { | |
| 645 | − switch (old) { | |
| 646 | − case BNX2X_STATE_FP_POLL: | |
| 647 | − /* make sure bnx2x_fp_lock_poll() wont starve us */ | |
| 648 | − set_bit(BNX2X_STATE_FP_NAPI_REQ_BIT, | |
| 649 | − &fp->busy_poll_state); | |
| 650 | − /* fallthrough */ | |
| 651 | − case BNX2X_STATE_FP_POLL | BNX2X_STATE_FP_NAPI_REQ: | |
| 652 | − return false; | |
| 653 | − default: | |
| 654 | − break; | |
| 655 | − } | |
| 656 | − prev = cmpxchg(&fp->busy_poll_state, old, BNX2X_STATE_FP_NAPI); | |
| 657 | − if (unlikely(prev != old)) { | |
| 658 | − old = prev; | |
| 659 | − continue; | |
| 660 | − } | |
| 661 | − return true; | |
| 662 | − } | |
| 663 | −} | |
| 664 | − | |
| 665 | −static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) | |
| 666 | −{ | |
| 667 | − smp_wmb(); | |
| 668 | − fp->busy_poll_state = 0; | |
| 669 | −} | |
| 670 | − | |
| 671 | −/* called from bnx2x_low_latency_poll() */ | |
| 672 | −static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) | |
| 673 | −{ | |
| 674 | − return cmpxchg(&fp->busy_poll_state, 0, BNX2X_STATE_FP_POLL) == 0; | |
| 675 | −} | |
| 676 | − | |
| 677 | −static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) | |
| 678 | −{ | |
| 679 | − smp_mb__before_atomic(); | |
| 680 | − clear_bit(BNX2X_STATE_FP_POLL_BIT, &fp->busy_poll_state); | |
| 681 | −} | |
| 682 | − | |
| 683 | −/* true if a socket is polling */ | |
| 684 | −static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) | |
| 685 | −{ | |
| 686 | − return READ_ONCE(fp->busy_poll_state) & BNX2X_STATE_FP_POLL; | |
| 687 | −} | |
| 688 | − | |
| 689 | −/* false if fp is currently owned */ | |
| 690 | −static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) | |
| 691 | −{ | |
| 692 | − set_bit(BNX2X_STATE_FP_DISABLE_BIT, &fp->busy_poll_state); | |
| 693 | − return !bnx2x_fp_ll_polling(fp); | |
| 694 | − | |
| 695 | −} | |
| 696 | −#else | |
| 697 | −static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) | |
| 698 | −{ | |
| 699 | −} | |
| 700 | − | |
| 701 | −static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) | |
| 702 | −{ | |
| 703 | − return true; | |
| 704 | −} | |
| 705 | − | |
| 706 | −static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) | |
| 707 | −{ | |
| 708 | −} | |
| 709 | − | |
| 710 | −static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) | |
| 711 | −{ | |
| 712 | − return false; | |
| 713 | −} | |
| 714 | − | |
| 715 | −static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) | |
| 716 | −{ | |
| 717 | −} | |
| 718 | − | |
| 719 | −static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) | |
| 720 | −{ | |
| 721 | − return false; | |
| 722 | −} | |
| 723 | −static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) | |
| 724 | −{ | |
| 725 | − return true; | |
| 726 | −} | |
| 727 | −#endif /* CONFIG_NET_RX_BUSY_POLL */ | |
| 728 | − | |
| 729 | 614 | /* Use 2500 as a mini-jumbo MTU for FCoE */ |
| 730 | 615 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 |
| 731 | 616 | |
| @@ -46,7 +46,6 @@ static void bnx2x_add_all_napi_cnic(struct bnx2x *bp) · 45 unmodified lines | ||
| 46 | 46 | for_each_rx_queue_cnic(bp, i) { |
| 47 | 47 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
| 48 | 48 | bnx2x_poll, NAPI_POLL_WEIGHT); |
| 49 | − napi_hash_add(&bnx2x_fp(bp, i, napi)); | |
| 50 | 49 | } |
| 51 | 50 | } |
| 52 | 51 | |
| @@ -58,7 +57,6 @@ static void bnx2x_add_all_napi(struct bnx2x *bp) · 5 unmodified lines | ||
| 58 | 57 | for_each_eth_queue(bp, i) { |
| 59 | 58 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
| 60 | 59 | bnx2x_poll, NAPI_POLL_WEIGHT); |
| 61 | − napi_hash_add(&bnx2x_fp(bp, i, napi)); | |
| 62 | 60 | } |
| 63 | 61 | } |
| 64 | 62 | |
| @@ -560,10 +558,8 @@ static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp, · 495 unmodified lines | ||
| 560 | 558 | put_page(pool->page); |
| 561 | 559 | |
| 562 | 560 | pool->page = alloc_pages(gfp_mask, PAGES_PER_SGE_SHIFT); |
| 563 | − if (unlikely(!pool->page)) { | |
| 564 | − BNX2X_ERR("Can't alloc sge\n"); | |
| 561 | + if (unlikely(!pool->page)) | |
| 565 | 562 | return -ENOMEM; |
| 566 | − } | |
| 567 | 563 | |
| 568 | 564 | pool->offset = 0; |
| 569 | 565 | } |
| @@ -747,7 +743,7 @@ static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp, · 177 unmodified lines | ||
| 747 | 743 | bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum); |
| 748 | 744 | break; |
| 749 | 745 | default: |
| 750 | − BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n", | |
| 746 | + WARN_ONCE(1, "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n", | |
| 751 | 747 | be16_to_cpu(skb->protocol)); |
| 752 | 748 | } |
| 753 | 749 | } |
| @@ -1094,12 +1090,7 @@ reuse_rx: · 340 unmodified lines | ||
| 1094 | 1090 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), |
| 1095 | 1091 | le16_to_cpu(cqe_fp->vlan_tag)); |
| 1096 | 1092 | |
| 1097 | − skb_mark_napi_id(skb, &fp->napi); | |
| 1098 | − | |
| 1099 | − if (bnx2x_fp_ll_polling(fp)) | |
| 1100 | − netif_receive_skb(skb); | |
| 1101 | − else | |
| 1102 | − napi_gro_receive(&fp->napi, skb); | |
| 1093 | + napi_gro_receive(&fp->napi, skb); | |
| 1103 | 1094 | next_rx: |
| 1104 | 1095 | rx_buf->data = NULL; |
| 1105 | 1096 | |
| @@ -1131,9 +1122,6 @@ next_cqe: · 25 unmodified lines | ||
| 1131 | 1122 | bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod, |
| 1132 | 1123 | fp->rx_sge_prod); |
| 1133 | 1124 | |
| 1134 | − fp->rx_pkt += rx_pkt; | |
| 1135 | − fp->rx_calls++; | |
| 1136 | − | |
| 1137 | 1125 | return rx_pkt; |
| 1138 | 1126 | } |
| 1139 | 1127 | |
| @@ -1869,7 +1857,6 @@ static void bnx2x_napi_enable_cnic(struct bnx2x *bp) · 729 unmodified lines | ||
| 1869 | 1857 | int i; |
| 1870 | 1858 | |
| 1871 | 1859 | for_each_rx_queue_cnic(bp, i) { |
| 1872 | − bnx2x_fp_busy_poll_init(&bp->fp[i]); | |
| 1873 | 1860 | napi_enable(&bnx2x_fp(bp, i, napi)); |
| 1874 | 1861 | } |
| 1875 | 1862 | } |
| @@ -1879,7 +1866,6 @@ static void bnx2x_napi_enable(struct bnx2x *bp) · 3 unmodified lines | ||
| 1879 | 1866 | int i; |
| 1880 | 1867 | |
| 1881 | 1868 | for_each_eth_queue(bp, i) { |
| 1882 | − bnx2x_fp_busy_poll_init(&bp->fp[i]); | |
| 1883 | 1869 | napi_enable(&bnx2x_fp(bp, i, napi)); |
| 1884 | 1870 | } |
| 1885 | 1871 | } |
| @@ -1890,8 +1876,6 @@ static void bnx2x_napi_disable_cnic(struct bnx2x *bp) · 4 unmodified lines | ||
| 1890 | 1876 | |
| 1891 | 1877 | for_each_rx_queue_cnic(bp, i) { |
| 1892 | 1878 | napi_disable(&bnx2x_fp(bp, i, napi)); |
| 1893 | − while (!bnx2x_fp_ll_disable(&bp->fp[i])) | |
| 1894 | − usleep_range(1000, 2000); | |
| 1895 | 1879 | } |
| 1896 | 1880 | } |
| 1897 | 1881 | |
| @@ -1901,8 +1885,6 @@ static void bnx2x_napi_disable(struct bnx2x *bp) · 3 unmodified lines | ||
| 1901 | 1885 | |
| 1902 | 1886 | for_each_eth_queue(bp, i) { |
| 1903 | 1887 | napi_disable(&bnx2x_fp(bp, i, napi)); |
| 1904 | − while (!bnx2x_fp_ll_disable(&bp->fp[i])) | |
| 1905 | − usleep_range(1000, 2000); | |
| 1906 | 1888 | } |
| 1907 | 1889 | } |
| 1908 | 1890 | |
| @@ -3219,49 +3201,32 @@ int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state) · 1310 unmodified lines | ||
| 3219 | 3201 | */ |
| 3220 | 3202 | static int bnx2x_poll(struct napi_struct *napi, int budget) |
| 3221 | 3203 | { |
| 3222 | − int work_done = 0; | |
| 3223 | − u8 cos; | |
| 3224 | 3204 | struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath, |
| 3225 | 3205 | napi); |
| 3226 | 3206 | struct bnx2x *bp = fp->bp; |
| 3207 | + int rx_work_done; | |
| 3208 | + u8 cos; | |
| 3227 | 3209 | |
| 3228 | − while (1) { | |
| 3229 | 3210 | #ifdef BNX2X_STOP_ON_ERROR |
| 3230 | − if (unlikely(bp->panic)) { | |
| 3231 | − napi_complete(napi); | |
| 3232 | − return 0; | |
| 3233 | − } | |
| 3211 | + if (unlikely(bp->panic)) { | |
| 3212 | + napi_complete(napi); | |
| 3213 | + return 0; | |
| 3214 | + } | |
| 3234 | 3215 | #endif |
| 3235 | − if (!bnx2x_fp_lock_napi(fp)) | |
| 3236 | − return budget; | |
| 3237 | − | |
| 3238 | − for_each_cos_in_tx_queue(fp, cos) | |
| 3239 | − if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) | |
| 3240 | − bnx2x_tx_int(bp, fp->txdata_ptr[cos]); | |
| 3241 | − | |
| 3242 | − if (bnx2x_has_rx_work(fp)) { | |
| 3243 | − work_done += bnx2x_rx_int(fp, budget - work_done); | |
| 3244 | − | |
| 3245 | − /* must not complete if we consumed full budget */ | |
| 3246 | − if (work_done >= budget) { | |
| 3247 | − bnx2x_fp_unlock_napi(fp); | |
| 3248 | − break; | |
| 3249 | − } | |
| 3250 | − } | |
| 3251 | − | |
| 3252 | − bnx2x_fp_unlock_napi(fp); | |
| 3216 | + for_each_cos_in_tx_queue(fp, cos) | |
| 3217 | + if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) | |
| 3218 | + bnx2x_tx_int(bp, fp->txdata_ptr[cos]); | |
| 3253 | 3219 | |
| 3254 | − /* Fall out from the NAPI loop if needed */ | |
| 3255 | − if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { | |
| 3220 | + rx_work_done = (bnx2x_has_rx_work(fp)) ? bnx2x_rx_int(fp, budget) : 0; | |
| 3256 | 3221 | |
| 3257 | − /* No need to update SB for FCoE L2 ring as long as | |
| 3258 | − * it's connected to the default SB and the SB | |
| 3259 | − * has been updated when NAPI was scheduled. | |
| 3260 | − */ | |
| 3261 | − if (IS_FCOE_FP(fp)) { | |
| 3262 | − napi_complete(napi); | |
| 3263 | − break; | |
| 3264 | − } | |
| 3222 | + if (rx_work_done < budget) { | |
| 3223 | + /* No need to update SB for FCoE L2 ring as long as | |
| 3224 | + * it's connected to the default SB and the SB | |
| 3225 | + * has been updated when NAPI was scheduled. | |
| 3226 | + */ | |
| 3227 | + if (IS_FCOE_FP(fp)) { | |
| 3228 | + napi_complete(napi); | |
| 3229 | + } else { | |
| 3265 | 3230 | bnx2x_update_fpsb_idx(fp); |
| 3266 | 3231 | /* bnx2x_has_rx_work() reads the status block, |
| 3267 | 3232 | * thus we need to ensure that status block indices |
| @@ -3286,40 +3251,15 @@ static int bnx2x_poll(struct napi_struct *napi, int budget) · 18 unmodified lines | ||
| 3286 | 3251 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, |
| 3287 | 3252 | le16_to_cpu(fp->fp_hc_idx), |
| 3288 | 3253 | IGU_INT_ENABLE, 1); |
| 3289 | − break; | |
| 3254 | + } else { | |
| 3255 | + rx_work_done = budget; | |
| 3290 | 3256 | } |
| 3291 | 3257 | } |
| 3292 | 3258 | } |
| 3293 | 3259 | |
| 3294 | − return work_done; | |
| 3260 | + return rx_work_done; | |
| 3295 | 3261 | } |
| 3296 | 3262 | |
| 3297 | −#ifdef CONFIG_NET_RX_BUSY_POLL | |
| 3298 | −/* must be called with local_bh_disable()d */ | |
| 3299 | −int bnx2x_low_latency_recv(struct napi_struct *napi) | |
| 3300 | −{ | |
| 3301 | − struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath, | |
| 3302 | − napi); | |
| 3303 | − struct bnx2x *bp = fp->bp; | |
| 3304 | − int found = 0; | |
| 3305 | − | |
| 3306 | − if ((bp->state == BNX2X_STATE_CLOSED) || | |
| 3307 | − (bp->state == BNX2X_STATE_ERROR) || | |
| 3308 | − (bp->dev->features & (NETIF_F_LRO | NETIF_F_GRO))) | |
| 3309 | − return LL_FLUSH_FAILED; | |
| 3310 | − | |
| 3311 | − if (!bnx2x_fp_lock_poll(fp)) | |
| 3312 | − return LL_FLUSH_BUSY; | |
| 3313 | − | |
| 3314 | − if (bnx2x_has_rx_work(fp)) | |
| 3315 | − found = bnx2x_rx_int(fp, 4); | |
| 3316 | − | |
| 3317 | − bnx2x_fp_unlock_poll(fp); | |
| 3318 | − | |
| 3319 | − return found; | |
| 3320 | −} | |
| 3321 | −#endif | |
| 3322 | − | |
| 3323 | 3263 | /* we split the first BD into headers and data BDs |
| 3324 | 3264 | * to ease the pain of our fellow microcode engineers |
| 3325 | 3265 | * we use one mapping for both BDs |
| @@ -4494,7 +4434,6 @@ static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, · 1168 unmodified lines | ||
| 4494 | 4434 | /* Limit the CQE producer by the CQE ring size */ |
| 4495 | 4435 | fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, |
| 4496 | 4436 | cqe_ring_prod); |
| 4497 | − fp->rx_pkt = fp->rx_calls = 0; | |
| 4498 | 4437 | |
| 4499 | 4438 | bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt; |
| 4500 | 4439 | |
| @@ -569,13 +569,6 @@ int bnx2x_enable_msix(struct bnx2x *bp); · 568 unmodified lines | ||
| 569 | 569 | */ |
| 570 | 570 | int bnx2x_enable_msi(struct bnx2x *bp); |
| 571 | 571 | |
| 572 | −/** | |
| 573 | − * bnx2x_low_latency_recv - LL callback | |
| 574 | − * | |
| 575 | − * @napi: napi structure | |
| 576 | − */ | |
| 577 | −int bnx2x_low_latency_recv(struct napi_struct *napi); | |
| 578 | − | |
| 579 | 572 | /** |
| 580 | 573 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
| 581 | 574 | * |
| @@ -52,7 +52,7 @@ static const struct { · 51 unmodified lines | ||
| 52 | 52 | { Q_STATS_OFFSET32(rx_skb_alloc_failed), |
| 53 | 53 | 4, "[%s]: rx_skb_alloc_discard" }, |
| 54 | 54 | { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, |
| 55 | − | |
| 55 | + { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, | |
| 56 | 56 | { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, |
| 57 | 57 | /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), |
| 58 | 58 | 8, "[%s]: tx_ucast_packets" }, |
| @@ -74,117 +74,115 @@ static const struct { · 15 unmodified lines | ||
| 74 | 74 | static const struct { |
| 75 | 75 | long offset; |
| 76 | 76 | int size; |
| 77 | − u32 flags; | |
| 78 | −#define STATS_FLAGS_PORT 1 | |
| 79 | −#define STATS_FLAGS_FUNC 2 | |
| 80 | −#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) | |
| 77 | + bool is_port_stat; | |
| 81 | 78 | char string[ETH_GSTRING_LEN]; |
| 82 | 79 | } bnx2x_stats_arr[] = { |
| 83 | 80 | /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), |
| 84 | − 8, STATS_FLAGS_BOTH, "rx_bytes" }, | |
| 81 | + 8, false, "rx_bytes" }, | |
| 85 | 82 | { STATS_OFFSET32(error_bytes_received_hi), |
| 86 | − 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, | |
| 83 | + 8, false, "rx_error_bytes" }, | |
| 87 | 84 | { STATS_OFFSET32(total_unicast_packets_received_hi), |
| 88 | − 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, | |
| 85 | + 8, false, "rx_ucast_packets" }, | |
| 89 | 86 | { STATS_OFFSET32(total_multicast_packets_received_hi), |
| 90 | − 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, | |
| 87 | + 8, false, "rx_mcast_packets" }, | |
| 91 | 88 | { STATS_OFFSET32(total_broadcast_packets_received_hi), |
| 92 | − 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, | |
| 89 | + 8, false, "rx_bcast_packets" }, | |
| 93 | 90 | { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), |
| 94 | − 8, STATS_FLAGS_PORT, "rx_crc_errors" }, | |
| 91 | + 8, true, "rx_crc_errors" }, | |
| 95 | 92 | { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), |
| 96 | − 8, STATS_FLAGS_PORT, "rx_align_errors" }, | |
| 93 | + 8, true, "rx_align_errors" }, | |
| 97 | 94 | { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), |
| 98 | − 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, | |
| 95 | + 8, true, "rx_undersize_packets" }, | |
| 99 | 96 | { STATS_OFFSET32(etherstatsoverrsizepkts_hi), |
| 100 | − 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, | |
| 97 | + 8, true, "rx_oversize_packets" }, | |
| 101 | 98 | /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), |
| 102 | − 8, STATS_FLAGS_PORT, "rx_fragments" }, | |
| 99 | + 8, true, "rx_fragments" }, | |
| 103 | 100 | { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), |
| 104 | − 8, STATS_FLAGS_PORT, "rx_jabbers" }, | |
| 101 | + 8, true, "rx_jabbers" }, | |
| 105 | 102 | { STATS_OFFSET32(no_buff_discard_hi), |
| 106 | − 8, STATS_FLAGS_BOTH, "rx_discards" }, | |
| 103 | + 8, false, "rx_discards" }, | |
| 107 | 104 | { STATS_OFFSET32(mac_filter_discard), |
| 108 | − 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, | |
| 105 | + 4, true, "rx_filtered_packets" }, | |
| 109 | 106 | { STATS_OFFSET32(mf_tag_discard), |
| 110 | − 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, | |
| 107 | + 4, true, "rx_mf_tag_discard" }, | |
| 111 | 108 | { STATS_OFFSET32(pfc_frames_received_hi), |
| 112 | − 8, STATS_FLAGS_PORT, "pfc_frames_received" }, | |
| 109 | + 8, true, "pfc_frames_received" }, | |
| 113 | 110 | { STATS_OFFSET32(pfc_frames_sent_hi), |
| 114 | − 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, | |
| 111 | + 8, true, "pfc_frames_sent" }, | |
| 115 | 112 | { STATS_OFFSET32(brb_drop_hi), |
| 116 | − 8, STATS_FLAGS_PORT, "rx_brb_discard" }, | |
| 113 | + 8, true, "rx_brb_discard" }, | |
| 117 | 114 | { STATS_OFFSET32(brb_truncate_hi), |
| 118 | − 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, | |
| 115 | + 8, true, "rx_brb_truncate" }, | |
| 119 | 116 | { STATS_OFFSET32(pause_frames_received_hi), |
| 120 | − 8, STATS_FLAGS_PORT, "rx_pause_frames" }, | |
| 117 | + 8, true, "rx_pause_frames" }, | |
| 121 | 118 | { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), |
| 122 | − 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, | |
| 119 | + 8, true, "rx_mac_ctrl_frames" }, | |
| 123 | 120 | { STATS_OFFSET32(nig_timer_max), |
| 124 | − 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, | |
| 121 | + 4, true, "rx_constant_pause_events" }, | |
| 125 | 122 | /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), |
| 126 | − 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, | |
| 123 | + 4, false, "rx_phy_ip_err_discards"}, | |
| 127 | 124 | { STATS_OFFSET32(rx_skb_alloc_failed), |
| 128 | − 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, | |
| 125 | + 4, false, "rx_skb_alloc_discard" }, | |
| 129 | 126 | { STATS_OFFSET32(hw_csum_err), |
| 130 | − 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, | |
| 131 | − | |
| 127 | + 4, false, "rx_csum_offload_errors" }, | |
| 128 | + { STATS_OFFSET32(driver_xoff), | |
| 129 | + 4, false, "tx_exhaustion_events" }, | |
| 132 | 130 | { STATS_OFFSET32(total_bytes_transmitted_hi), |
| 133 | − 8, STATS_FLAGS_BOTH, "tx_bytes" }, | |
| 131 | + 8, false, "tx_bytes" }, | |
| 134 | 132 | { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), |
| 135 | − 8, STATS_FLAGS_PORT, "tx_error_bytes" }, | |
| 133 | + 8, true, "tx_error_bytes" }, | |
| 136 | 134 | { STATS_OFFSET32(total_unicast_packets_transmitted_hi), |
| 137 | − 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, | |
| 135 | + 8, false, "tx_ucast_packets" }, | |
| 138 | 136 | { STATS_OFFSET32(total_multicast_packets_transmitted_hi), |
| 139 | − 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, | |
| 137 | + 8, false, "tx_mcast_packets" }, | |
| 140 | 138 | { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), |
| 141 | − 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, | |
| 139 | + 8, false, "tx_bcast_packets" }, | |
| 142 | 140 | { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), |
| 143 | − 8, STATS_FLAGS_PORT, "tx_mac_errors" }, | |
| 141 | + 8, true, "tx_mac_errors" }, | |
| 144 | 142 | { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), |
| 145 | − 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, | |
| 143 | + 8, true, "tx_carrier_errors" }, | |
| 146 | 144 | /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), |
| 147 | − 8, STATS_FLAGS_PORT, "tx_single_collisions" }, | |
| 145 | + 8, true, "tx_single_collisions" }, | |
| 148 | 146 | { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), |
| 149 | − 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, | |
| 147 | + 8, true, "tx_multi_collisions" }, | |
| 150 | 148 | { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), |
| 151 | − 8, STATS_FLAGS_PORT, "tx_deferred" }, | |
| 149 | + 8, true, "tx_deferred" }, | |
| 152 | 150 | { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), |
| 153 | − 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, | |
| 151 | + 8, true, "tx_excess_collisions" }, | |
| 154 | 152 | { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), |
| 155 | − 8, STATS_FLAGS_PORT, "tx_late_collisions" }, | |
| 153 | + 8, true, "tx_late_collisions" }, | |
| 156 | 154 | { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), |
| 157 | − 8, STATS_FLAGS_PORT, "tx_total_collisions" }, | |
| 155 | + 8, true, "tx_total_collisions" }, | |
| 158 | 156 | { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), |
| 159 | − 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, | |
| 157 | + 8, true, "tx_64_byte_packets" }, | |
| 160 | 158 | { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), |
| 161 | − 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, | |
| 159 | + 8, true, "tx_65_to_127_byte_packets" }, | |
| 162 | 160 | { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), |
| 163 | − 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, | |
| 161 | + 8, true, "tx_128_to_255_byte_packets" }, | |
| 164 | 162 | { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), |
| 165 | − 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, | |
| 163 | + 8, true, "tx_256_to_511_byte_packets" }, | |
| 166 | 164 | /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), |
| 167 | − 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, | |
| 165 | + 8, true, "tx_512_to_1023_byte_packets" }, | |
| 168 | 166 | { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), |
| 169 | − 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, | |
| 167 | + 8, true, "tx_1024_to_1522_byte_packets" }, | |
| 170 | 168 | { STATS_OFFSET32(etherstatspktsover1522octets_hi), |
| 171 | − 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, | |
| 169 | + 8, true, "tx_1523_to_9022_byte_packets" }, | |
| 172 | 170 | { STATS_OFFSET32(pause_frames_sent_hi), |
| 173 | − 8, STATS_FLAGS_PORT, "tx_pause_frames" }, | |
| 171 | + 8, true, "tx_pause_frames" }, | |
| 174 | 172 | { STATS_OFFSET32(total_tpa_aggregations_hi), |
| 175 | − 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, | |
| 173 | + 8, false, "tpa_aggregations" }, | |
| 176 | 174 | { STATS_OFFSET32(total_tpa_aggregated_frames_hi), |
| 177 | − 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, | |
| 175 | + 8, false, "tpa_aggregated_frames"}, | |
| 178 | 176 | { STATS_OFFSET32(total_tpa_bytes_hi), |
| 179 | − 8, STATS_FLAGS_FUNC, "tpa_bytes"}, | |
| 177 | + 8, false, "tpa_bytes"}, | |
| 180 | 178 | { STATS_OFFSET32(recoverable_error), |
| 181 | − 4, STATS_FLAGS_FUNC, "recoverable_errors" }, | |
| 179 | + 4, false, "recoverable_errors" }, | |
| 182 | 180 | { STATS_OFFSET32(unrecoverable_error), |
| 183 | − 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, | |
| 181 | + 4, false, "unrecoverable_errors" }, | |
| 184 | 182 | { STATS_OFFSET32(driver_filtered_tx_pkt), |
| 185 | − 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, | |
| 183 | + 4, false, "driver_filtered_tx_pkt" }, | |
| 186 | 184 | { STATS_OFFSET32(eee_tx_lpi), |
| 187 | − 4, STATS_FLAGS_PORT, "Tx LPI entry count"} | |
| 185 | + 4, true, "Tx LPI entry count"} | |
| 188 | 186 | }; |
| 189 | 187 | |
| 190 | 188 | #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) |
| @@ -3065,12 +3063,8 @@ static void bnx2x_self_test(struct net_device *dev, · 2874 unmodified lines | ||
| 3065 | 3063 | } |
| 3066 | 3064 | } |
| 3067 | 3065 | |
| 3068 | −#define IS_PORT_STAT(i) \ | |
| 3069 | − ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) | |
| 3070 | −#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) | |
| 3071 | −#define HIDE_PORT_STAT(bp) \ | |
| 3072 | − ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ | |
| 3073 | − IS_VF(bp)) | |
| 3066 | +#define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat) | |
| 3067 | +#define HIDE_PORT_STAT(bp) IS_VF(bp) | |
| 3074 | 3068 | |
| 3075 | 3069 | /* ethtool statistics are displayed for all regular ethernet queues and the |
| 3076 | 3070 | * fcoe L2 queue if not disabled |
| @@ -3094,7 +3088,7 @@ static int bnx2x_get_sset_count(struct net_device *dev, int stringset) · 17 unmodified lines | ||
| 3094 | 3088 | num_strings = 0; |
| 3095 | 3089 | if (HIDE_PORT_STAT(bp)) { |
| 3096 | 3090 | for (i = 0; i < BNX2X_NUM_STATS; i++) |
| 3097 | − if (IS_FUNC_STAT(i)) | |
| 3091 | + if (!IS_PORT_STAT(i)) | |
| 3098 | 3092 | num_strings++; |
| 3099 | 3093 | } else |
| 3100 | 3094 | num_strings += BNX2X_NUM_STATS; |
| @@ -3013,8 +3013,8 @@ struct afex_stats { · 3012 unmodified lines | ||
| 3013 | 3013 | }; |
| 3014 | 3014 | |
| 3015 | 3015 | #define BCM_5710_FW_MAJOR_VERSION 7 |
| 3016 | −#define BCM_5710_FW_MINOR_VERSION 12 | |
| 3017 | −#define BCM_5710_FW_REVISION_VERSION 30 | |
| 3016 | +#define BCM_5710_FW_MINOR_VERSION 13 | |
| 3017 | +#define BCM_5710_FW_REVISION_VERSION 1 | |
| 3018 | 3018 | #define BCM_5710_FW_ENGINEERING_VERSION 0 |
| 3019 | 3019 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
| 3020 | 3020 | |
| @@ -3583,7 +3583,7 @@ enum classify_rule { · 562 unmodified lines | ||
| 3583 | 3583 | CLASSIFY_RULE_OPCODE_MAC, |
| 3584 | 3584 | CLASSIFY_RULE_OPCODE_VLAN, |
| 3585 | 3585 | CLASSIFY_RULE_OPCODE_PAIR, |
| 3586 | − CLASSIFY_RULE_OPCODE_VXLAN, | |
| 3586 | + CLASSIFY_RULE_OPCODE_IMAC_VNI, | |
| 3587 | 3587 | MAX_CLASSIFY_RULE |
| 3588 | 3588 | }; |
| 3589 | 3589 | |
| @@ -3826,6 +3826,17 @@ struct eth_classify_header { · 236 unmodified lines | ||
| 3826 | 3826 | __le32 echo; |
| 3827 | 3827 | }; |
| 3828 | 3828 | |
| 3829 | +/* | |
| 3830 | + * Command for adding/removing a Inner-MAC/VNI classification rule | |
| 3831 | + */ | |
| 3832 | +struct eth_classify_imac_vni_cmd { | |
| 3833 | + struct eth_classify_cmd_header header; | |
| 3834 | + __le32 vni; | |
| 3835 | + __le16 imac_lsb; | |
| 3836 | + __le16 imac_mid; | |
| 3837 | + __le16 imac_msb; | |
| 3838 | + __le16 reserved1; | |
| 3839 | +}; | |
| 3829 | 3840 | |
| 3830 | 3841 | /* |
| 3831 | 3842 | * Command for adding/removing a MAC classification rule |
| @@ -3869,14 +3880,6 @@ struct eth_classify_vlan_cmd { · 37 unmodified lines | ||
| 3869 | 3880 | /* |
| 3870 | 3881 | * Command for adding/removing a VXLAN classification rule |
| 3871 | 3882 | */ |
| 3872 | −struct eth_classify_vxlan_cmd { | |
| 3873 | − struct eth_classify_cmd_header header; | |
| 3874 | − __le32 vni; | |
| 3875 | − __le16 inner_mac_lsb; | |
| 3876 | − __le16 inner_mac_mid; | |
| 3877 | − __le16 inner_mac_msb; | |
| 3878 | − __le16 reserved1; | |
| 3879 | −}; | |
| 3880 | 3883 | |
| 3881 | 3884 | /* |
| 3882 | 3885 | * union for eth classification rule |
| @@ -3885,7 +3888,7 @@ union eth_classify_rule_cmd { · 2 unmodified lines | ||
| 3885 | 3888 | struct eth_classify_mac_cmd mac; |
| 3886 | 3889 | struct eth_classify_vlan_cmd vlan; |
| 3887 | 3890 | struct eth_classify_pair_cmd pair; |
| 3888 | − struct eth_classify_vxlan_cmd vxlan; | |
| 3891 | + struct eth_classify_imac_vni_cmd imac_vni; | |
| 3889 | 3892 | }; |
| 3890 | 3893 | |
| 3891 | 3894 | /* |
| @@ -5623,6 +5626,14 @@ enum igu_mode { · 1731 unmodified lines | ||
| 5623 | 5626 | MAX_IGU_MODE |
| 5624 | 5627 | }; |
| 5625 | 5628 | |
| 5629 | +/* | |
| 5630 | + * Inner Headers Classification Type | |
| 5631 | + */ | |
| 5632 | +enum inner_clss_type { | |
| 5633 | + INNER_CLSS_DISABLED, | |
| 5634 | + INNER_CLSS_USE_VLAN, | |
| 5635 | + INNER_CLSS_USE_VNI, | |
| 5636 | + MAX_INNER_CLSS_TYPE}; | |
| 5626 | 5637 | |
| 5627 | 5638 | /* |
| 5628 | 5639 | * IP versions |
| @@ -5953,14 +5964,6 @@ enum ts_offset_cmd { · 324 unmodified lines | ||
| 5953 | 5964 | MAX_TS_OFFSET_CMD |
| 5954 | 5965 | }; |
| 5955 | 5966 | |
| 5956 | −/* Tunnel Mode */ | |
| 5957 | −enum tunnel_mode { | |
| 5958 | − TUNN_MODE_NONE, | |
| 5959 | − TUNN_MODE_VXLAN, | |
| 5960 | − TUNN_MODE_GRE, | |
| 5961 | − MAX_TUNNEL_MODE | |
| 5962 | −}; | |
| 5963 | − | |
| 5964 | 5967 | /* zone A per-queue data */ |
| 5965 | 5968 | struct ustorm_queue_zone_data { |
| 5966 | 5969 | struct ustorm_eth_rx_producers eth_rx_producers; |
| @@ -13004,9 +13004,6 @@ static const struct net_device_ops bnx2x_netdev_ops = { · 13003 unmodified lines | ||
| 13004 | 13004 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
| 13005 | 13005 | #endif |
| 13006 | 13006 | |
| 13007 | −#ifdef CONFIG_NET_RX_BUSY_POLL | |
| 13008 | − .ndo_busy_poll = bnx2x_low_latency_recv, | |
| 13009 | −#endif | |
| 13010 | 13007 | .ndo_get_phys_port_id = bnx2x_get_phys_port_id, |
| 13011 | 13008 | .ndo_set_vf_link_state = bnx2x_set_vf_link_state, |
| 13012 | 13009 | .ndo_features_check = bnx2x_features_check, |
| @@ -72,8 +72,10 @@ MODULE_VERSION(DRV_MODULE_VERSION); · 71 unmodified lines | ||
| 72 | 72 | #define BNXT_TX_PUSH_THRESH 92 |
| 73 | 73 | |
| 74 | 74 | enum board_idx { |
| 75 | + BCM57301, | |
| 75 | 76 | BCM57302, |
| 76 | 77 | BCM57304, |
| 78 | + BCM57402, | |
| 77 | 79 | BCM57404, |
| 78 | 80 | BCM57406, |
| 79 | 81 | BCM57304_VF, |
| @@ -84,17 +86,21 @@ enum board_idx { · 4 unmodified lines | ||
| 84 | 86 | static const struct { |
| 85 | 87 | char *name; |
| 86 | 88 | } board_info[] = { |
| 87 | − { "Broadcom BCM57302 NetXtreme-C Single-port 10Gb/25Gb/40Gb/50Gb Ethernet" }, | |
| 89 | + { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" }, | |
| 90 | + { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" }, | |
| 88 | 91 | { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" }, |
| 92 | + { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" }, | |
| 89 | 93 | { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" }, |
| 90 | − { "Broadcom BCM57406 NetXtreme-E Dual-port 10Gb Ethernet" }, | |
| 94 | + { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" }, | |
| 91 | 95 | { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" }, |
| 92 | 96 | { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" }, |
| 93 | 97 | }; |
| 94 | 98 | |
| 95 | 99 | static const struct pci_device_id bnxt_pci_tbl[] = { |
| 100 | + { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, | |
| 96 | 101 | { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, |
| 97 | 102 | { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, |
| 103 | + { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, | |
| 98 | 104 | { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, |
| 99 | 105 | { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, |
| 100 | 106 | #ifdef CONFIG_BNXT_SRIOV |
| @@ -173,7 +179,6 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) · 72 unmodified lines | ||
| 173 | 179 | u32 len, free_size, vlan_tag_flags, cfa_action, flags; |
| 174 | 180 | u16 prod, last_frag; |
| 175 | 181 | struct pci_dev *pdev = bp->pdev; |
| 176 | − struct bnxt_napi *bnapi; | |
| 177 | 182 | struct bnxt_tx_ring_info *txr; |
| 178 | 183 | struct bnxt_sw_tx_bd *tx_buf; |
| 179 | 184 | |
| @@ -183,8 +188,7 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) · 3 unmodified lines | ||
| 183 | 188 | return NETDEV_TX_OK; |
| 184 | 189 | } |
| 185 | 190 | |
| 186 | − bnapi = bp->bnapi[i]; | |
| 187 | − txr = &bnapi->tx_ring; | |
| 191 | + txr = &bp->tx_ring[i]; | |
| 188 | 192 | txq = netdev_get_tx_queue(dev, i); |
| 189 | 193 | prod = txr->tx_prod; |
| 190 | 194 | |
| @@ -417,8 +421,8 @@ tx_dma_error: · 226 unmodified lines | ||
| 417 | 421 | |
| 418 | 422 | static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) |
| 419 | 423 | { |
| 420 | − struct bnxt_tx_ring_info *txr = &bnapi->tx_ring; | |
| 421 | − int index = bnapi->index; | |
| 424 | + struct bnxt_tx_ring_info *txr = bnapi->tx_ring; | |
| 425 | + int index = txr - &bp->tx_ring[0]; | |
| 422 | 426 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index); |
| 423 | 427 | u16 cons = txr->tx_cons; |
| 424 | 428 | struct pci_dev *pdev = bp->pdev; |
| @@ -596,7 +600,7 @@ static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, · 171 unmodified lines | ||
| 596 | 600 | { |
| 597 | 601 | struct bnxt *bp = bnapi->bp; |
| 598 | 602 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 599 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 603 | + struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
| 600 | 604 | u16 prod = rxr->rx_agg_prod; |
| 601 | 605 | u16 sw_prod = rxr->rx_sw_agg_prod; |
| 602 | 606 | u32 i; |
| @@ -675,7 +679,7 @@ static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, · 72 unmodified lines | ||
| 675 | 679 | { |
| 676 | 680 | struct pci_dev *pdev = bp->pdev; |
| 677 | 681 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 678 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 682 | + struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
| 679 | 683 | u16 prod = rxr->rx_agg_prod; |
| 680 | 684 | u32 i; |
| 681 | 685 | |
| @@ -856,8 +860,13 @@ static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info, · 174 unmodified lines | ||
| 856 | 860 | struct tcphdr *th; |
| 857 | 861 | int payload_off, tcp_opt_len = 0; |
| 858 | 862 | int len, nw_off; |
| 863 | + u16 segs; | |
| 864 | + | |
| 865 | + segs = TPA_END_TPA_SEGS(tpa_end); | |
| 866 | + if (segs == 1) | |
| 867 | + return skb; | |
| 859 | 868 | |
| 860 | − NAPI_GRO_CB(skb)->count = TPA_END_TPA_SEGS(tpa_end); | |
| 869 | + NAPI_GRO_CB(skb)->count = segs; | |
| 861 | 870 | skb_shinfo(skb)->gso_size = |
| 862 | 871 | le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); |
| 863 | 872 | skb_shinfo(skb)->gso_type = tpa_info->gso_type; |
| @@ -929,7 +938,7 @@ static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, · 65 unmodified lines | ||
| 929 | 938 | bool *agg_event) |
| 930 | 939 | { |
| 931 | 940 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 932 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 941 | + struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
| 933 | 942 | u8 agg_id = TPA_END_AGG_ID(tpa_end); |
| 934 | 943 | u8 *data, agg_bufs; |
| 935 | 944 | u16 cp_cons = RING_CMP(*raw_cons); |
| @@ -1045,7 +1054,7 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, · 109 unmodified lines | ||
| 1045 | 1054 | bool *agg_event) |
| 1046 | 1055 | { |
| 1047 | 1056 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 1048 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 1057 | + struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
| 1049 | 1058 | struct net_device *dev = bp->dev; |
| 1050 | 1059 | struct rx_cmp *rxcmp; |
| 1051 | 1060 | struct rx_cmp_ext *rxcmp1; |
| @@ -1187,8 +1196,10 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, · 135 unmodified lines | ||
| 1187 | 1196 | skb->csum_level = RX_CMP_ENCAP(rxcmp1); |
| 1188 | 1197 | } |
| 1189 | 1198 | } else { |
| 1190 | − if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) | |
| 1191 | − cpr->rx_l4_csum_errors++; | |
| 1199 | + if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { | |
| 1200 | + if (dev->features & NETIF_F_RXCSUM) | |
| 1201 | + cpr->rx_l4_csum_errors++; | |
| 1202 | + } | |
| 1192 | 1203 | } |
| 1193 | 1204 | |
| 1194 | 1205 | skb_record_rx_queue(skb, bnapi->index); |
| @@ -1377,7 +1388,7 @@ static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) · 182 unmodified lines | ||
| 1377 | 1388 | bnxt_tx_int(bp, bnapi, tx_pkts); |
| 1378 | 1389 | |
| 1379 | 1390 | if (rx_event) { |
| 1380 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 1391 | + struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
| 1381 | 1392 | |
| 1382 | 1393 | writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); |
| 1383 | 1394 | writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); |
| @@ -1446,19 +1457,14 @@ static void bnxt_free_tx_skbs(struct bnxt *bp) · 62 unmodified lines | ||
| 1446 | 1457 | int i, max_idx; |
| 1447 | 1458 | struct pci_dev *pdev = bp->pdev; |
| 1448 | 1459 | |
| 1449 | − if (!bp->bnapi) | |
| 1460 | + if (!bp->tx_ring) | |
| 1450 | 1461 | return; |
| 1451 | 1462 | |
| 1452 | 1463 | max_idx = bp->tx_nr_pages * TX_DESC_CNT; |
| 1453 | 1464 | for (i = 0; i < bp->tx_nr_rings; i++) { |
| 1454 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 1455 | − struct bnxt_tx_ring_info *txr; | |
| 1465 | + struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; | |
| 1456 | 1466 | int j; |
| 1457 | 1467 | |
| 1458 | − if (!bnapi) | |
| 1459 | − continue; | |
| 1460 | − | |
| 1461 | − txr = &bnapi->tx_ring; | |
| 1462 | 1468 | for (j = 0; j < max_idx;) { |
| 1463 | 1469 | struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; |
| 1464 | 1470 | struct sk_buff *skb = tx_buf->skb; |
| @@ -1504,21 +1510,15 @@ static void bnxt_free_rx_skbs(struct bnxt *bp) · 39 unmodified lines | ||
| 1504 | 1510 | int i, max_idx, max_agg_idx; |
| 1505 | 1511 | struct pci_dev *pdev = bp->pdev; |
| 1506 | 1512 | |
| 1507 | − if (!bp->bnapi) | |
| 1513 | + if (!bp->rx_ring) | |
| 1508 | 1514 | return; |
| 1509 | 1515 | |
| 1510 | 1516 | max_idx = bp->rx_nr_pages * RX_DESC_CNT; |
| 1511 | 1517 | max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; |
| 1512 | 1518 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 1513 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 1514 | − struct bnxt_rx_ring_info *rxr; | |
| 1519 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 1515 | 1520 | int j; |
| 1516 | 1521 | |
| 1517 | − if (!bnapi) | |
| 1518 | − continue; | |
| 1519 | − | |
| 1520 | − rxr = &bnapi->rx_ring; | |
| 1521 | − | |
| 1522 | 1522 | if (rxr->rx_tpa) { |
| 1523 | 1523 | for (j = 0; j < MAX_TPA; j++) { |
| 1524 | 1524 | struct bnxt_tpa_info *tpa_info = |
| @@ -1646,19 +1646,13 @@ static void bnxt_free_rx_rings(struct bnxt *bp) · 121 unmodified lines | ||
| 1646 | 1646 | { |
| 1647 | 1647 | int i; |
| 1648 | 1648 | |
| 1649 | − if (!bp->bnapi) | |
| 1649 | + if (!bp->rx_ring) | |
| 1650 | 1650 | return; |
| 1651 | 1651 | |
| 1652 | 1652 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 1653 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 1654 | − struct bnxt_rx_ring_info *rxr; | |
| 1653 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 1655 | 1654 | struct bnxt_ring_struct *ring; |
| 1656 | 1655 | |
| 1657 | − if (!bnapi) | |
| 1658 | − continue; | |
| 1659 | − | |
| 1660 | − rxr = &bnapi->rx_ring; | |
| 1661 | − | |
| 1662 | 1656 | kfree(rxr->rx_tpa); |
| 1663 | 1657 | rxr->rx_tpa = NULL; |
| 1664 | 1658 | |
| @@ -1677,6 +1671,9 @@ static int bnxt_alloc_rx_rings(struct bnxt *bp) · 12 unmodified lines | ||
| 1677 | 1671 | { |
| 1678 | 1672 | int i, rc, agg_rings = 0, tpa_rings = 0; |
| 1679 | 1673 | |
| 1674 | + if (!bp->rx_ring) | |
| 1675 | + return -ENOMEM; | |
| 1676 | + | |
| 1680 | 1677 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
| 1681 | 1678 | agg_rings = 1; |
| 1682 | 1679 | |
| @@ -1684,14 +1681,9 @@ static int bnxt_alloc_rx_rings(struct bnxt *bp) · 1 unmodified line | ||
| 1684 | 1681 | tpa_rings = 1; |
| 1685 | 1682 | |
| 1686 | 1683 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 1687 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 1688 | − struct bnxt_rx_ring_info *rxr; | |
| 1684 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 1689 | 1685 | struct bnxt_ring_struct *ring; |
| 1690 | 1686 | |
| 1691 | − if (!bnapi) | |
| 1692 | − continue; | |
| 1693 | − | |
| 1694 | − rxr = &bnapi->rx_ring; | |
| 1695 | 1687 | ring = &rxr->rx_ring_struct; |
| 1696 | 1688 | |
| 1697 | 1689 | rc = bnxt_alloc_ring(bp, ring); |
| @@ -1729,19 +1721,13 @@ static void bnxt_free_tx_rings(struct bnxt *bp) · 31 unmodified lines | ||
| 1729 | 1721 | int i; |
| 1730 | 1722 | struct pci_dev *pdev = bp->pdev; |
| 1731 | 1723 | |
| 1732 | − if (!bp->bnapi) | |
| 1724 | + if (!bp->tx_ring) | |
| 1733 | 1725 | return; |
| 1734 | 1726 | |
| 1735 | 1727 | for (i = 0; i < bp->tx_nr_rings; i++) { |
| 1736 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 1737 | − struct bnxt_tx_ring_info *txr; | |
| 1728 | + struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; | |
| 1738 | 1729 | struct bnxt_ring_struct *ring; |
| 1739 | 1730 | |
| 1740 | − if (!bnapi) | |
| 1741 | − continue; | |
| 1742 | − | |
| 1743 | − txr = &bnapi->tx_ring; | |
| 1744 | − | |
| 1745 | 1731 | if (txr->tx_push) { |
| 1746 | 1732 | dma_free_coherent(&pdev->dev, bp->tx_push_size, |
| 1747 | 1733 | txr->tx_push, txr->tx_push_mapping); |
| @@ -1775,14 +1761,9 @@ static int bnxt_alloc_tx_rings(struct bnxt *bp) · 27 unmodified lines | ||
| 1775 | 1761 | } |
| 1776 | 1762 | |
| 1777 | 1763 | for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { |
| 1778 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 1779 | − struct bnxt_tx_ring_info *txr; | |
| 1764 | + struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; | |
| 1780 | 1765 | struct bnxt_ring_struct *ring; |
| 1781 | 1766 | |
| 1782 | − if (!bnapi) | |
| 1783 | − continue; | |
| 1784 | − | |
| 1785 | − txr = &bnapi->tx_ring; | |
| 1786 | 1767 | ring = &txr->tx_ring_struct; |
| 1787 | 1768 | |
| 1788 | 1769 | rc = bnxt_alloc_ring(bp, ring); |
| @@ -1885,7 +1866,10 @@ static void bnxt_init_ring_struct(struct bnxt *bp) · 96 unmodified lines | ||
| 1885 | 1866 | ring->dma_arr = cpr->cp_desc_mapping; |
| 1886 | 1867 | ring->vmem_size = 0; |
| 1887 | 1868 | |
| 1888 | − rxr = &bnapi->rx_ring; | |
| 1869 | + rxr = bnapi->rx_ring; | |
| 1870 | + if (!rxr) | |
| 1871 | + goto skip_rx; | |
| 1872 | + | |
| 1889 | 1873 | ring = &rxr->rx_ring_struct; |
| 1890 | 1874 | ring->nr_pages = bp->rx_nr_pages; |
| 1891 | 1875 | ring->page_size = HW_RXBD_RING_SIZE; |
| @@ -1902,7 +1886,11 @@ static void bnxt_init_ring_struct(struct bnxt *bp) · 10 unmodified lines | ||
| 1902 | 1886 | ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; |
| 1903 | 1887 | ring->vmem = (void **)&rxr->rx_agg_ring; |
| 1904 | 1888 | |
| 1905 | − txr = &bnapi->tx_ring; | |
| 1889 | +skip_rx: | |
| 1890 | + txr = bnapi->tx_ring; | |
| 1891 | + if (!txr) | |
| 1892 | + continue; | |
| 1893 | + | |
| 1906 | 1894 | ring = &txr->tx_ring_struct; |
| 1907 | 1895 | ring->nr_pages = bp->tx_nr_pages; |
| 1908 | 1896 | ring->page_size = HW_RXBD_RING_SIZE; |
| @@ -1938,22 +1926,18 @@ static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) · 29 unmodified lines | ||
| 1938 | 1926 | static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) |
| 1939 | 1927 | { |
| 1940 | 1928 | struct net_device *dev = bp->dev; |
| 1941 | − struct bnxt_napi *bnapi = bp->bnapi[ring_nr]; | |
| 1942 | 1929 | struct bnxt_rx_ring_info *rxr; |
| 1943 | 1930 | struct bnxt_ring_struct *ring; |
| 1944 | 1931 | u32 prod, type; |
| 1945 | 1932 | int i; |
| 1946 | 1933 | |
| 1947 | − if (!bnapi) | |
| 1948 | − return -EINVAL; | |
| 1949 | − | |
| 1950 | 1934 | type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | |
| 1951 | 1935 | RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; |
| 1952 | 1936 | |
| 1953 | 1937 | if (NET_IP_ALIGN == 2) |
| 1954 | 1938 | type |= RX_BD_FLAGS_SOP; |
| 1955 | 1939 | |
| 1956 | − rxr = &bnapi->rx_ring; | |
| 1940 | + rxr = &bp->rx_ring[ring_nr]; | |
| 1957 | 1941 | ring = &rxr->rx_ring_struct; |
| 1958 | 1942 | bnxt_init_rxbd_pages(ring, type); |
| 1959 | 1943 | |
| @@ -1969,11 +1953,12 @@ static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) · 9 unmodified lines | ||
| 1969 | 1953 | rxr->rx_prod = prod; |
| 1970 | 1954 | ring->fw_ring_id = INVALID_HW_RING_ID; |
| 1971 | 1955 | |
| 1956 | + ring = &rxr->rx_agg_ring_struct; | |
| 1957 | + ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 1958 | + | |
| 1972 | 1959 | if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) |
| 1973 | 1960 | return 0; |
| 1974 | 1961 | |
| 1975 | − ring = &rxr->rx_agg_ring_struct; | |
| 1976 | − | |
| 1977 | 1962 | type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) | |
| 1978 | 1963 | RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; |
| 1979 | 1964 | |
| @@ -1989,7 +1974,6 @@ static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) · 9 unmodified lines | ||
| 1989 | 1974 | prod = NEXT_RX_AGG(prod); |
| 1990 | 1975 | } |
| 1991 | 1976 | rxr->rx_agg_prod = prod; |
| 1992 | − ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 1993 | 1977 | |
| 1994 | 1978 | if (bp->flags & BNXT_FLAG_TPA) { |
| 1995 | 1979 | if (rxr->rx_tpa) { |
| @@ -2035,8 +2019,7 @@ static int bnxt_init_tx_rings(struct bnxt *bp) · 39 unmodified lines | ||
| 2035 | 2019 | MAX_SKB_FRAGS + 1); |
| 2036 | 2020 | |
| 2037 | 2021 | for (i = 0; i < bp->tx_nr_rings; i++) { |
| 2038 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 2039 | − struct bnxt_tx_ring_info *txr = &bnapi->tx_ring; | |
| 2022 | + struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; | |
| 2040 | 2023 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
| 2041 | 2024 | |
| 2042 | 2025 | ring->fw_ring_id = INVALID_HW_RING_ID; |
| @@ -2423,14 +2406,18 @@ static void bnxt_clear_ring_indices(struct bnxt *bp) · 380 unmodified lines | ||
| 2423 | 2406 | cpr = &bnapi->cp_ring; |
| 2424 | 2407 | cpr->cp_raw_cons = 0; |
| 2425 | 2408 | |
| 2426 | − txr = &bnapi->tx_ring; | |
| 2427 | − txr->tx_prod = 0; | |
| 2428 | − txr->tx_cons = 0; | |
| 2409 | + txr = bnapi->tx_ring; | |
| 2410 | + if (txr) { | |
| 2411 | + txr->tx_prod = 0; | |
| 2412 | + txr->tx_cons = 0; | |
| 2413 | + } | |
| 2429 | 2414 | |
| 2430 | − rxr = &bnapi->rx_ring; | |
| 2431 | − rxr->rx_prod = 0; | |
| 2432 | − rxr->rx_agg_prod = 0; | |
| 2433 | − rxr->rx_sw_agg_prod = 0; | |
| 2415 | + rxr = bnapi->rx_ring; | |
| 2416 | + if (rxr) { | |
| 2417 | + rxr->rx_prod = 0; | |
| 2418 | + rxr->rx_agg_prod = 0; | |
| 2419 | + rxr->rx_sw_agg_prod = 0; | |
| 2420 | + } | |
| 2434 | 2421 | } |
| 2435 | 2422 | } |
| 2436 | 2423 | |
| @@ -2496,6 +2483,10 @@ static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) · 59 unmodified lines | ||
| 2496 | 2483 | bnxt_free_stats(bp); |
| 2497 | 2484 | bnxt_free_ring_grps(bp); |
| 2498 | 2485 | bnxt_free_vnics(bp); |
| 2486 | + kfree(bp->tx_ring); | |
| 2487 | + bp->tx_ring = NULL; | |
| 2488 | + kfree(bp->rx_ring); | |
| 2489 | + bp->rx_ring = NULL; | |
| 2499 | 2490 | kfree(bp->bnapi); |
| 2500 | 2491 | bp->bnapi = NULL; |
| 2501 | 2492 | } else { |
| @@ -2505,7 +2496,7 @@ static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) · 3 unmodified lines | ||
| 2505 | 2496 | |
| 2506 | 2497 | static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) |
| 2507 | 2498 | { |
| 2508 | − int i, rc, size, arr_size; | |
| 2499 | + int i, j, rc, size, arr_size; | |
| 2509 | 2500 | void *bnapi; |
| 2510 | 2501 | |
| 2511 | 2502 | if (irq_re_init) { |
| @@ -2527,6 +2518,33 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) · 15 unmodified lines | ||
| 2527 | 2518 | bp->bnapi[i]->bp = bp; |
| 2528 | 2519 | } |
| 2529 | 2520 | |
| 2521 | + bp->rx_ring = kcalloc(bp->rx_nr_rings, | |
| 2522 | + sizeof(struct bnxt_rx_ring_info), | |
| 2523 | + GFP_KERNEL); | |
| 2524 | + if (!bp->rx_ring) | |
| 2525 | + return -ENOMEM; | |
| 2526 | + | |
| 2527 | + for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 2528 | + bp->rx_ring[i].bnapi = bp->bnapi[i]; | |
| 2529 | + bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; | |
| 2530 | + } | |
| 2531 | + | |
| 2532 | + bp->tx_ring = kcalloc(bp->tx_nr_rings, | |
| 2533 | + sizeof(struct bnxt_tx_ring_info), | |
| 2534 | + GFP_KERNEL); | |
| 2535 | + if (!bp->tx_ring) | |
| 2536 | + return -ENOMEM; | |
| 2537 | + | |
| 2538 | + if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
| 2539 | + j = 0; | |
| 2540 | + else | |
| 2541 | + j = bp->rx_nr_rings; | |
| 2542 | + | |
| 2543 | + for (i = 0; i < bp->tx_nr_rings; i++, j++) { | |
| 2544 | + bp->tx_ring[i].bnapi = bp->bnapi[j]; | |
| 2545 | + bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; | |
| 2546 | + } | |
| 2547 | + | |
| 2530 | 2548 | rc = bnxt_alloc_stats(bp); |
| 2531 | 2549 | if (rc) |
| 2532 | 2550 | goto alloc_mem_err; |
| @@ -2596,6 +2614,9 @@ int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) · 63 unmodified lines | ||
| 2596 | 2614 | /* Write request msg to hwrm channel */ |
| 2597 | 2615 | __iowrite32_copy(bp->bar0, data, msg_len / 4); |
| 2598 | 2616 | |
| 2617 | + for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4) | |
| 2618 | + writel(0, bp->bar0 + i); | |
| 2619 | + | |
| 2599 | 2620 | /* currently supports only one outstanding message */ |
| 2600 | 2621 | if (intr_process) |
| 2601 | 2622 | bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) & |
| @@ -2710,6 +2731,14 @@ static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) · 108 unmodified lines | ||
| 2710 | 2731 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2711 | 2732 | } |
| 2712 | 2733 | |
| 2734 | +static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) | |
| 2735 | +{ | |
| 2736 | + struct hwrm_func_drv_unrgtr_input req = {0}; | |
| 2737 | + | |
| 2738 | + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); | |
| 2739 | + return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
| 2740 | +} | |
| 2741 | + | |
| 2713 | 2742 | static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) |
| 2714 | 2743 | { |
| 2715 | 2744 | u32 rc = 0; |
| @@ -2772,7 +2801,7 @@ static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) · 56 unmodified lines | ||
| 2772 | 2801 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 2773 | 2802 | |
| 2774 | 2803 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); |
| 2775 | − req.dflt_vnic_id = cpu_to_le32(vnic->fw_vnic_id); | |
| 2804 | + req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); | |
| 2776 | 2805 | |
| 2777 | 2806 | req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); |
| 2778 | 2807 | req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); |
| @@ -2805,7 +2834,7 @@ static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, · 26 unmodified lines | ||
| 2805 | 2834 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ |
| 2806 | 2835 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ |
| 2807 | 2836 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ |
| 2808 | − CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID) | |
| 2837 | + CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) | |
| 2809 | 2838 | |
| 2810 | 2839 | static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, |
| 2811 | 2840 | struct bnxt_ntuple_filter *fltr) |
| @@ -2824,7 +2853,7 @@ static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, · 12 unmodified lines | ||
| 2824 | 2853 | |
| 2825 | 2854 | req.ethertype = htons(ETH_P_IP); |
| 2826 | 2855 | memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); |
| 2827 | − req.ipaddr_type = 4; | |
| 2856 | + req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; | |
| 2828 | 2857 | req.ip_protocol = keys->basic.ip_proto; |
| 2829 | 2858 | |
| 2830 | 2859 | req.src_ipaddr[0] = keys->addrs.v4addrs.src; |
| @@ -2837,7 +2866,7 @@ static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, · 6 unmodified lines | ||
| 2837 | 2866 | req.dst_port = keys->ports.dst; |
| 2838 | 2867 | req.dst_port_mask = cpu_to_be16(0xffff); |
| 2839 | 2868 | |
| 2840 | − req.dst_vnic_id = cpu_to_le16(vnic->fw_vnic_id); | |
| 2869 | + req.dst_id = cpu_to_le16(vnic->fw_vnic_id); | |
| 2841 | 2870 | mutex_lock(&bp->hwrm_cmd_lock); |
| 2842 | 2871 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2843 | 2872 | if (!rc) |
| @@ -2857,10 +2886,10 @@ static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, · 13 unmodified lines | ||
| 2857 | 2886 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); |
| 2858 | 2887 | req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX | |
| 2859 | 2888 | CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); |
| 2860 | − req.dst_vnic_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); | |
| 2889 | + req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); | |
| 2861 | 2890 | req.enables = |
| 2862 | 2891 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | |
| 2863 | − CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID | | |
| 2892 | + CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | | |
| 2864 | 2893 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); |
| 2865 | 2894 | memcpy(req.l2_addr, mac_addr, ETH_ALEN); |
| 2866 | 2895 | req.l2_addr_mask[0] = 0xff; |
| @@ -2930,7 +2959,8 @@ static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) · 63 unmodified lines | ||
| 2930 | 2959 | |
| 2931 | 2960 | req.enables = |
| 2932 | 2961 | cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | |
| 2933 | − VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS); | |
| 2962 | + VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | | |
| 2963 | + VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); | |
| 2934 | 2964 | |
| 2935 | 2965 | /* Number of segs are log2 units, and first packet is not |
| 2936 | 2966 | * included as part of this units. |
| @@ -2948,6 +2978,8 @@ static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) · 11 unmodified lines | ||
| 2948 | 2978 | segs = ilog2(nsegs); |
| 2949 | 2979 | req.max_agg_segs = cpu_to_le16(segs); |
| 2950 | 2980 | req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); |
| 2981 | + | |
| 2982 | + req.min_agg_len = cpu_to_le32(512); | |
| 2951 | 2983 | } |
| 2952 | 2984 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
| 2953 | 2985 | |
| @@ -3058,7 +3090,7 @@ static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id) · 104 unmodified lines | ||
| 3058 | 3090 | |
| 3059 | 3091 | static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) |
| 3060 | 3092 | { |
| 3061 | − int grp_idx = 0; | |
| 3093 | + unsigned int ring = 0, grp_idx; | |
| 3062 | 3094 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 3063 | 3095 | struct hwrm_vnic_cfg_input req = {0}; |
| 3064 | 3096 | |
| @@ -3069,10 +3101,11 @@ static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) · 4 unmodified lines | ||
| 3069 | 3101 | req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx); |
| 3070 | 3102 | req.cos_rule = cpu_to_le16(0xffff); |
| 3071 | 3103 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
| 3072 | − grp_idx = 0; | |
| 3104 | + ring = 0; | |
| 3073 | 3105 | else if (vnic->flags & BNXT_VNIC_RFS_FLAG) |
| 3074 | − grp_idx = vnic_id - 1; | |
| 3106 | + ring = vnic_id - 1; | |
| 3075 | 3107 | |
| 3108 | + grp_idx = bp->rx_ring[ring].bnapi->index; | |
| 3076 | 3109 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
| 3077 | 3110 | req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); |
| 3078 | 3111 | |
| @@ -3113,22 +3146,25 @@ static void bnxt_hwrm_vnic_free(struct bnxt *bp) · 34 unmodified lines | ||
| 3113 | 3146 | bnxt_hwrm_vnic_free_one(bp, i); |
| 3114 | 3147 | } |
| 3115 | 3148 | |
| 3116 | −static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, u16 start_grp_id, | |
| 3117 | − u16 end_grp_id) | |
| 3149 | +static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, | |
| 3150 | + unsigned int start_rx_ring_idx, | |
| 3151 | + unsigned int nr_rings) | |
| 3118 | 3152 | { |
| 3119 | − u32 rc = 0, i, j; | |
| 3153 | + int rc = 0; | |
| 3154 | + unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; | |
| 3120 | 3155 | struct hwrm_vnic_alloc_input req = {0}; |
| 3121 | 3156 | struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 3122 | 3157 | |
| 3123 | 3158 | /* map ring groups to this vnic */ |
| 3124 | − for (i = start_grp_id, j = 0; i < end_grp_id; i++, j++) { | |
| 3125 | − if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) { | |
| 3159 | + for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { | |
| 3160 | + grp_idx = bp->rx_ring[i].bnapi->index; | |
| 3161 | + if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { | |
| 3126 | 3162 | netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", |
| 3127 | − j, (end_grp_id - start_grp_id)); | |
| 3163 | + j, nr_rings); | |
| 3128 | 3164 | break; |
| 3129 | 3165 | } |
| 3130 | 3166 | bp->vnic_info[vnic_id].fw_grp_ids[j] = |
| 3131 | − bp->grp_info[i].fw_grp_id; | |
| 3167 | + bp->grp_info[grp_idx].fw_grp_id; | |
| 3132 | 3168 | } |
| 3133 | 3169 | |
| 3134 | 3170 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; |
| @@ -3155,20 +3191,22 @@ static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) · 20 unmodified lines | ||
| 3155 | 3191 | struct hwrm_ring_grp_alloc_input req = {0}; |
| 3156 | 3192 | struct hwrm_ring_grp_alloc_output *resp = |
| 3157 | 3193 | bp->hwrm_cmd_resp_addr; |
| 3194 | + unsigned int grp_idx = bp->rx_ring[i].bnapi->index; | |
| 3158 | 3195 | |
| 3159 | 3196 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); |
| 3160 | 3197 | |
| 3161 | − req.cr = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); | |
| 3162 | − req.rr = cpu_to_le16(bp->grp_info[i].rx_fw_ring_id); | |
| 3163 | − req.ar = cpu_to_le16(bp->grp_info[i].agg_fw_ring_id); | |
| 3164 | − req.sc = cpu_to_le16(bp->grp_info[i].fw_stats_ctx); | |
| 3198 | + req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); | |
| 3199 | + req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); | |
| 3200 | + req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); | |
| 3201 | + req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); | |
| 3165 | 3202 | |
| 3166 | 3203 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 3167 | 3204 | HWRM_CMD_TIMEOUT); |
| 3168 | 3205 | if (rc) |
| 3169 | 3206 | break; |
| 3170 | 3207 | |
| 3171 | − bp->grp_info[i].fw_grp_id = le32_to_cpu(resp->ring_group_id); | |
| 3208 | + bp->grp_info[grp_idx].fw_grp_id = | |
| 3209 | + le32_to_cpu(resp->ring_group_id); | |
| 3172 | 3210 | } |
| 3173 | 3211 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3174 | 3212 | return rc; |
| @@ -3293,75 +3331,66 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp) · 118 unmodified lines | ||
| 3293 | 3331 | { |
| 3294 | 3332 | int i, rc = 0; |
| 3295 | 3333 | |
| 3296 | − if (bp->cp_nr_rings) { | |
| 3297 | − for (i = 0; i < bp->cp_nr_rings; i++) { | |
| 3298 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3299 | − struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
| 3300 | − struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
| 3334 | + for (i = 0; i < bp->cp_nr_rings; i++) { | |
| 3335 | + struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3336 | + struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
| 3337 | + struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
| 3301 | 3338 | |
| 3302 | − rc = hwrm_ring_alloc_send_msg(bp, ring, | |
| 3303 | − HWRM_RING_ALLOC_CMPL, i, | |
| 3304 | − INVALID_STATS_CTX_ID); | |
| 3305 | − if (rc) | |
| 3306 | − goto err_out; | |
| 3307 | − cpr->cp_doorbell = bp->bar1 + i * 0x80; | |
| 3308 | − BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); | |
| 3309 | − bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; | |
| 3310 | − } | |
| 3339 | + rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, | |
| 3340 | + INVALID_STATS_CTX_ID); | |
| 3341 | + if (rc) | |
| 3342 | + goto err_out; | |
| 3343 | + cpr->cp_doorbell = bp->bar1 + i * 0x80; | |
| 3344 | + BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); | |
| 3345 | + bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; | |
| 3311 | 3346 | } |
| 3312 | 3347 | |
| 3313 | − if (bp->tx_nr_rings) { | |
| 3314 | − for (i = 0; i < bp->tx_nr_rings; i++) { | |
| 3315 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3316 | − struct bnxt_tx_ring_info *txr = &bnapi->tx_ring; | |
| 3317 | − struct bnxt_ring_struct *ring = &txr->tx_ring_struct; | |
| 3318 | − u16 fw_stats_ctx = bp->grp_info[i].fw_stats_ctx; | |
| 3348 | + for (i = 0; i < bp->tx_nr_rings; i++) { | |
| 3349 | + struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; | |
| 3350 | + struct bnxt_ring_struct *ring = &txr->tx_ring_struct; | |
| 3351 | + u32 map_idx = txr->bnapi->index; | |
| 3352 | + u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; | |
| 3319 | 3353 | |
| 3320 | − rc = hwrm_ring_alloc_send_msg(bp, ring, | |
| 3321 | − HWRM_RING_ALLOC_TX, i, | |
| 3322 | − fw_stats_ctx); | |
| 3323 | − if (rc) | |
| 3324 | − goto err_out; | |
| 3325 | − txr->tx_doorbell = bp->bar1 + i * 0x80; | |
| 3326 | − } | |
| 3354 | + rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, | |
| 3355 | + map_idx, fw_stats_ctx); | |
| 3356 | + if (rc) | |
| 3357 | + goto err_out; | |
| 3358 | + txr->tx_doorbell = bp->bar1 + map_idx * 0x80; | |
| 3327 | 3359 | } |
| 3328 | 3360 | |
| 3329 | − if (bp->rx_nr_rings) { | |
| 3330 | − for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 3331 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3332 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 3333 | − struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; | |
| 3361 | + for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 3362 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 3363 | + struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; | |
| 3364 | + u32 map_idx = rxr->bnapi->index; | |
| 3334 | 3365 | |
| 3335 | − rc = hwrm_ring_alloc_send_msg(bp, ring, | |
| 3336 | − HWRM_RING_ALLOC_RX, i, | |
| 3337 | − INVALID_STATS_CTX_ID); | |
| 3338 | − if (rc) | |
| 3339 | − goto err_out; | |
| 3340 | − rxr->rx_doorbell = bp->bar1 + i * 0x80; | |
| 3341 | − writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); | |
| 3342 | − bp->grp_info[i].rx_fw_ring_id = ring->fw_ring_id; | |
| 3343 | − } | |
| 3366 | + rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, | |
| 3367 | + map_idx, INVALID_STATS_CTX_ID); | |
| 3368 | + if (rc) | |
| 3369 | + goto err_out; | |
| 3370 | + rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; | |
| 3371 | + writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); | |
| 3372 | + bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; | |
| 3344 | 3373 | } |
| 3345 | 3374 | |
| 3346 | 3375 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { |
| 3347 | 3376 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 3348 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3349 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 3377 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 3350 | 3378 | struct bnxt_ring_struct *ring = |
| 3351 | 3379 | &rxr->rx_agg_ring_struct; |
| 3380 | + u32 grp_idx = rxr->bnapi->index; | |
| 3381 | + u32 map_idx = grp_idx + bp->rx_nr_rings; | |
| 3352 | 3382 | |
| 3353 | 3383 | rc = hwrm_ring_alloc_send_msg(bp, ring, |
| 3354 | 3384 | HWRM_RING_ALLOC_AGG, |
| 3355 | − bp->rx_nr_rings + i, | |
| 3385 | + map_idx, | |
| 3356 | 3386 | INVALID_STATS_CTX_ID); |
| 3357 | 3387 | if (rc) |
| 3358 | 3388 | goto err_out; |
| 3359 | 3389 | |
| 3360 | − rxr->rx_agg_doorbell = | |
| 3361 | − bp->bar1 + (bp->rx_nr_rings + i) * 0x80; | |
| 3390 | + rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; | |
| 3362 | 3391 | writel(DB_KEY_RX | rxr->rx_agg_prod, |
| 3363 | 3392 | rxr->rx_agg_doorbell); |
| 3364 | − bp->grp_info[i].agg_fw_ring_id = ring->fw_ring_id; | |
| 3393 | + bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; | |
| 3365 | 3394 | } |
| 3366 | 3395 | } |
| 3367 | 3396 | err_out: |
| @@ -3408,91 +3437,75 @@ static int hwrm_ring_free_send_msg(struct bnxt *bp, · 40 unmodified lines | ||
| 3408 | 3437 | return 0; |
| 3409 | 3438 | } |
| 3410 | 3439 | |
| 3411 | −static int bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) | |
| 3440 | +static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) | |
| 3412 | 3441 | { |
| 3413 | − int i, rc = 0; | |
| 3442 | + int i; | |
| 3414 | 3443 | |
| 3415 | 3444 | if (!bp->bnapi) |
| 3416 | − return 0; | |
| 3445 | + return; | |
| 3417 | 3446 | |
| 3418 | − if (bp->tx_nr_rings) { | |
| 3419 | − for (i = 0; i < bp->tx_nr_rings; i++) { | |
| 3420 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3421 | − struct bnxt_tx_ring_info *txr = &bnapi->tx_ring; | |
| 3422 | − struct bnxt_ring_struct *ring = &txr->tx_ring_struct; | |
| 3423 | − u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id; | |
| 3424 | − | |
| 3425 | − if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3426 | − hwrm_ring_free_send_msg( | |
| 3427 | − bp, ring, | |
| 3428 | − RING_FREE_REQ_RING_TYPE_TX, | |
| 3429 | − close_path ? cmpl_ring_id : | |
| 3430 | − INVALID_HW_RING_ID); | |
| 3431 | − ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3432 | − } | |
| 3447 | + for (i = 0; i < bp->tx_nr_rings; i++) { | |
| 3448 | + struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; | |
| 3449 | + struct bnxt_ring_struct *ring = &txr->tx_ring_struct; | |
| 3450 | + u32 grp_idx = txr->bnapi->index; | |
| 3451 | + u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; | |
| 3452 | + | |
| 3453 | + if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3454 | + hwrm_ring_free_send_msg(bp, ring, | |
| 3455 | + RING_FREE_REQ_RING_TYPE_TX, | |
| 3456 | + close_path ? cmpl_ring_id : | |
| 3457 | + INVALID_HW_RING_ID); | |
| 3458 | + ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3433 | 3459 | } |
| 3434 | 3460 | } |
| 3435 | 3461 | |
| 3436 | − if (bp->rx_nr_rings) { | |
| 3437 | − for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 3438 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3439 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 3440 | − struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; | |
| 3441 | − u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id; | |
| 3442 | − | |
| 3443 | − if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3444 | − hwrm_ring_free_send_msg( | |
| 3445 | − bp, ring, | |
| 3446 | − RING_FREE_REQ_RING_TYPE_RX, | |
| 3447 | − close_path ? cmpl_ring_id : | |
| 3448 | − INVALID_HW_RING_ID); | |
| 3449 | − ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3450 | − bp->grp_info[i].rx_fw_ring_id = | |
| 3451 | − INVALID_HW_RING_ID; | |
| 3452 | − } | |
| 3462 | + for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 3463 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 3464 | + struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; | |
| 3465 | + u32 grp_idx = rxr->bnapi->index; | |
| 3466 | + u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; | |
| 3467 | + | |
| 3468 | + if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3469 | + hwrm_ring_free_send_msg(bp, ring, | |
| 3470 | + RING_FREE_REQ_RING_TYPE_RX, | |
| 3471 | + close_path ? cmpl_ring_id : | |
| 3472 | + INVALID_HW_RING_ID); | |
| 3473 | + ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3474 | + bp->grp_info[grp_idx].rx_fw_ring_id = | |
| 3475 | + INVALID_HW_RING_ID; | |
| 3453 | 3476 | } |
| 3454 | 3477 | } |
| 3455 | 3478 | |
| 3456 | − if (bp->rx_agg_nr_pages) { | |
| 3457 | − for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 3458 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3459 | − struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring; | |
| 3460 | − struct bnxt_ring_struct *ring = | |
| 3461 | − &rxr->rx_agg_ring_struct; | |
| 3462 | − u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id; | |
| 3463 | − | |
| 3464 | − if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3465 | − hwrm_ring_free_send_msg( | |
| 3466 | − bp, ring, | |
| 3467 | − RING_FREE_REQ_RING_TYPE_RX, | |
| 3468 | − close_path ? cmpl_ring_id : | |
| 3469 | − INVALID_HW_RING_ID); | |
| 3470 | − ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3471 | − bp->grp_info[i].agg_fw_ring_id = | |
| 3472 | − INVALID_HW_RING_ID; | |
| 3473 | − } | |
| 3479 | + for (i = 0; i < bp->rx_nr_rings; i++) { | |
| 3480 | + struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; | |
| 3481 | + struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; | |
| 3482 | + u32 grp_idx = rxr->bnapi->index; | |
| 3483 | + u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; | |
| 3484 | + | |
| 3485 | + if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3486 | + hwrm_ring_free_send_msg(bp, ring, | |
| 3487 | + RING_FREE_REQ_RING_TYPE_RX, | |
| 3488 | + close_path ? cmpl_ring_id : | |
| 3489 | + INVALID_HW_RING_ID); | |
| 3490 | + ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3491 | + bp->grp_info[grp_idx].agg_fw_ring_id = | |
| 3492 | + INVALID_HW_RING_ID; | |
| 3474 | 3493 | } |
| 3475 | 3494 | } |
| 3476 | 3495 | |
| 3477 | − if (bp->cp_nr_rings) { | |
| 3478 | − for (i = 0; i < bp->cp_nr_rings; i++) { | |
| 3479 | − struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3480 | − struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
| 3481 | − struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
| 3482 | − | |
| 3483 | − if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3484 | − hwrm_ring_free_send_msg( | |
| 3485 | − bp, ring, | |
| 3486 | − RING_FREE_REQ_RING_TYPE_CMPL, | |
| 3487 | − INVALID_HW_RING_ID); | |
| 3488 | − ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3489 | − bp->grp_info[i].cp_fw_ring_id = | |
| 3490 | − INVALID_HW_RING_ID; | |
| 3491 | − } | |
| 3496 | + for (i = 0; i < bp->cp_nr_rings; i++) { | |
| 3497 | + struct bnxt_napi *bnapi = bp->bnapi[i]; | |
| 3498 | + struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
| 3499 | + struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; | |
| 3500 | + | |
| 3501 | + if (ring->fw_ring_id != INVALID_HW_RING_ID) { | |
| 3502 | + hwrm_ring_free_send_msg(bp, ring, | |
| 3503 | + RING_FREE_REQ_RING_TYPE_CMPL, | |
| 3504 | + INVALID_HW_RING_ID); | |
| 3505 | + ring->fw_ring_id = INVALID_HW_RING_ID; | |
| 3506 | + bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; | |
| 3492 | 3507 | } |
| 3493 | 3508 | } |
| 3494 | − | |
| 3495 | − return rc; | |
| 3496 | 3509 | } |
| 3497 | 3510 | |
| 3498 | 3511 | int bnxt_hwrm_set_coal(struct bnxt *bp) |
| @@ -3604,7 +3617,7 @@ static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) · 105 unmodified lines | ||
| 3604 | 3617 | return 0; |
| 3605 | 3618 | } |
| 3606 | 3619 | |
| 3607 | −static int bnxt_hwrm_func_qcaps(struct bnxt *bp) | |
| 3620 | +int bnxt_hwrm_func_qcaps(struct bnxt *bp) | |
| 3608 | 3621 | { |
| 3609 | 3622 | int rc = 0; |
| 3610 | 3623 | struct hwrm_func_qcaps_input req = {0}; |
| @@ -3628,9 +3641,10 @@ static int bnxt_hwrm_func_qcaps(struct bnxt *bp) · 17 unmodified lines | ||
| 3628 | 3641 | pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
| 3629 | 3642 | pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); |
| 3630 | 3643 | pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); |
| 3631 | − pf->max_pf_tx_rings = pf->max_tx_rings; | |
| 3632 | 3644 | pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); |
| 3633 | − pf->max_pf_rx_rings = pf->max_rx_rings; | |
| 3645 | + pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); | |
| 3646 | + if (!pf->max_hw_ring_grps) | |
| 3647 | + pf->max_hw_ring_grps = pf->max_tx_rings; | |
| 3634 | 3648 | pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); |
| 3635 | 3649 | pf->max_vnics = le16_to_cpu(resp->max_vnics); |
| 3636 | 3650 | pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); |
| @@ -3658,6 +3672,9 @@ static int bnxt_hwrm_func_qcaps(struct bnxt *bp) · 21 unmodified lines | ||
| 3658 | 3672 | vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); |
| 3659 | 3673 | vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); |
| 3660 | 3674 | vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); |
| 3675 | + vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); | |
| 3676 | + if (!vf->max_hw_ring_grps) | |
| 3677 | + vf->max_hw_ring_grps = vf->max_tx_rings; | |
| 3661 | 3678 | vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); |
| 3662 | 3679 | vf->max_vnics = le16_to_cpu(resp->max_vnics); |
| 3663 | 3680 | vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); |
| @@ -3734,14 +3751,11 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp) · 70 unmodified lines | ||
| 3734 | 3751 | |
| 3735 | 3752 | memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); |
| 3736 | 3753 | |
| 3737 | − if (req.hwrm_intf_maj != resp->hwrm_intf_maj || | |
| 3738 | − req.hwrm_intf_min != resp->hwrm_intf_min || | |
| 3739 | − req.hwrm_intf_upd != resp->hwrm_intf_upd) { | |
| 3740 | − netdev_warn(bp->dev, "HWRM interface %d.%d.%d does not match driver interface %d.%d.%d.\n", | |
| 3754 | + if (resp->hwrm_intf_maj < 1) { | |
| 3755 | + netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", | |
| 3741 | 3756 | resp->hwrm_intf_maj, resp->hwrm_intf_min, |
| 3742 | − resp->hwrm_intf_upd, req.hwrm_intf_maj, | |
| 3743 | − req.hwrm_intf_min, req.hwrm_intf_upd); | |
| 3744 | − netdev_warn(bp->dev, "Please update driver or firmware with matching interface versions.\n"); | |
| 3757 | + resp->hwrm_intf_upd); | |
| 3758 | + netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); | |
| 3745 | 3759 | } |
| 3746 | 3760 | snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d", |
| 3747 | 3761 | resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, |
| @@ -3867,7 +3881,7 @@ static int bnxt_alloc_rfs_vnics(struct bnxt *bp) · 119 unmodified lines | ||
| 3867 | 3881 | break; |
| 3868 | 3882 | |
| 3869 | 3883 | bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG; |
| 3870 | − rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, ring_id + 1); | |
| 3884 | + rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); | |
| 3871 | 3885 | if (rc) { |
| 3872 | 3886 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", |
| 3873 | 3887 | vnic_id, rc); |
| @@ -3944,8 +3958,7 @@ static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) · 70 unmodified lines | ||
| 3944 | 3958 | } |
| 3945 | 3959 | bp->vnic_info[0].uc_filter_count = 1; |
| 3946 | 3960 | |
| 3947 | − bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST | | |
| 3948 | − CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
| 3961 | + bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; | |
| 3949 | 3962 | |
| 3950 | 3963 | if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp)) |
| 3951 | 3964 | bp->vnic_info[0].rx_mask |= |
| @@ -4026,20 +4039,42 @@ static int bnxt_set_real_num_queues(struct bnxt *bp) · 74 unmodified lines | ||
| 4026 | 4039 | return rc; |
| 4027 | 4040 | |
| 4028 | 4041 | #ifdef CONFIG_RFS_ACCEL |
| 4029 | − if (bp->rx_nr_rings) | |
| 4042 | + if (bp->flags & BNXT_FLAG_RFS) | |
| 4030 | 4043 | dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); |
| 4031 | − if (!dev->rx_cpu_rmap) | |
| 4032 | − rc = -ENOMEM; | |
| 4033 | 4044 | #endif |
| 4034 | 4045 | |
| 4035 | 4046 | return rc; |
| 4036 | 4047 | } |
| 4037 | 4048 | |
| 4049 | +static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, | |
| 4050 | + bool shared) | |
| 4051 | +{ | |
| 4052 | + int _rx = *rx, _tx = *tx; | |
| 4053 | + | |
| 4054 | + if (shared) { | |
| 4055 | + *rx = min_t(int, _rx, max); | |
| 4056 | + *tx = min_t(int, _tx, max); | |
| 4057 | + } else { | |
| 4058 | + if (max < 2) | |
| 4059 | + return -ENOMEM; | |
| 4060 | + | |
| 4061 | + while (_rx + _tx > max) { | |
| 4062 | + if (_rx > _tx && _rx > 1) | |
| 4063 | + _rx--; | |
| 4064 | + else if (_tx > 1) | |
| 4065 | + _tx--; | |
| 4066 | + } | |
| 4067 | + *rx = _rx; | |
| 4068 | + *tx = _tx; | |
| 4069 | + } | |
| 4070 | + return 0; | |
| 4071 | +} | |
| 4072 | + | |
| 4038 | 4073 | static int bnxt_setup_msix(struct bnxt *bp) |
| 4039 | 4074 | { |
| 4040 | 4075 | struct msix_entry *msix_ent; |
| 4041 | 4076 | struct net_device *dev = bp->dev; |
| 4042 | − int i, total_vecs, rc = 0; | |
| 4077 | + int i, total_vecs, rc = 0, min = 1; | |
| 4043 | 4078 | const int len = sizeof(bp->irq_tbl[0].name); |
| 4044 | 4079 | |
| 4045 | 4080 | bp->flags &= ~BNXT_FLAG_USING_MSIX; |
| @@ -4054,7 +4089,10 @@ static int bnxt_setup_msix(struct bnxt *bp) · 8 unmodified lines | ||
| 4054 | 4089 | msix_ent[i].vector = 0; |
| 4055 | 4090 | } |
| 4056 | 4091 | |
| 4057 | − total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 1, total_vecs); | |
| 4092 | + if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) | |
| 4093 | + min = 2; | |
| 4094 | + | |
| 4095 | + total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); | |
| 4058 | 4096 | if (total_vecs < 0) { |
| 4059 | 4097 | rc = -ENODEV; |
| 4060 | 4098 | goto msix_setup_exit; |
| @@ -4065,8 +4103,11 @@ static int bnxt_setup_msix(struct bnxt *bp) · 4 unmodified lines | ||
| 4065 | 4103 | int tcs; |
| 4066 | 4104 | |
| 4067 | 4105 | /* Trim rings based upon num of vectors allocated */ |
| 4068 | − bp->rx_nr_rings = min_t(int, total_vecs, bp->rx_nr_rings); | |
| 4069 | − bp->tx_nr_rings = min_t(int, total_vecs, bp->tx_nr_rings); | |
| 4106 | + rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, | |
| 4107 | + total_vecs, min == 1); | |
| 4108 | + if (rc) | |
| 4109 | + goto msix_setup_exit; | |
| 4110 | + | |
| 4070 | 4111 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
| 4071 | 4112 | tcs = netdev_get_num_tc(dev); |
| 4072 | 4113 | if (tcs > 1) { |
| @@ -4085,12 +4126,21 @@ static int bnxt_setup_msix(struct bnxt *bp) · 12 unmodified lines | ||
| 4085 | 4126 | } |
| 4086 | 4127 | } |
| 4087 | 4128 | } |
| 4088 | − bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings); | |
| 4129 | + bp->cp_nr_rings = total_vecs; | |
| 4089 | 4130 | |
| 4090 | 4131 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4132 | + char *attr; | |
| 4133 | + | |
| 4091 | 4134 | bp->irq_tbl[i].vector = msix_ent[i].vector; |
| 4135 | + if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
| 4136 | + attr = "TxRx"; | |
| 4137 | + else if (i < bp->rx_nr_rings) | |
| 4138 | + attr = "rx"; | |
| 4139 | + else | |
| 4140 | + attr = "tx"; | |
| 4141 | + | |
| 4092 | 4142 | snprintf(bp->irq_tbl[i].name, len, |
| 4093 | − "%s-%s-%d", dev->name, "TxRx", i); | |
| 4143 | + "%s-%s-%d", dev->name, attr, i); | |
| 4094 | 4144 | bp->irq_tbl[i].handler = bnxt_msix; |
| 4095 | 4145 | } |
| 4096 | 4146 | rc = bnxt_set_real_num_queues(bp); |
| @@ -4128,6 +4178,7 @@ static int bnxt_setup_inta(struct bnxt *bp) · 31 unmodified lines | ||
| 4128 | 4178 | bp->tx_nr_rings = 1; |
| 4129 | 4179 | bp->cp_nr_rings = 1; |
| 4130 | 4180 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
| 4181 | + bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
| 4131 | 4182 | bp->irq_tbl[0].vector = bp->pdev->irq; |
| 4132 | 4183 | snprintf(bp->irq_tbl[0].name, len, |
| 4133 | 4184 | "%s-%s-%d", bp->dev->name, "TxRx", 0); |
| @@ -4176,7 +4227,7 @@ static void bnxt_free_irq(struct bnxt *bp) · 42 unmodified lines | ||
| 4176 | 4227 | |
| 4177 | 4228 | static int bnxt_request_irq(struct bnxt *bp) |
| 4178 | 4229 | { |
| 4179 | − int i, rc = 0; | |
| 4230 | + int i, j, rc = 0; | |
| 4180 | 4231 | unsigned long flags = 0; |
| 4181 | 4232 | #ifdef CONFIG_RFS_ACCEL |
| 4182 | 4233 | struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; |
| @@ -4185,14 +4236,15 @@ static int bnxt_request_irq(struct bnxt *bp) · 2 unmodified lines | ||
| 4185 | 4236 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) |
| 4186 | 4237 | flags = IRQF_SHARED; |
| 4187 | 4238 | |
| 4188 | − for (i = 0; i < bp->cp_nr_rings; i++) { | |
| 4239 | + for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { | |
| 4189 | 4240 | struct bnxt_irq *irq = &bp->irq_tbl[i]; |
| 4190 | 4241 | #ifdef CONFIG_RFS_ACCEL |
| 4191 | − if (rmap && (i < bp->rx_nr_rings)) { | |
| 4242 | + if (rmap && bp->bnapi[i]->rx_ring) { | |
| 4192 | 4243 | rc = irq_cpu_rmap_add(rmap, irq->vector); |
| 4193 | 4244 | if (rc) |
| 4194 | 4245 | netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", |
| 4195 | − i); | |
| 4246 | + j); | |
| 4247 | + j++; | |
| 4196 | 4248 | } |
| 4197 | 4249 | #endif |
| 4198 | 4250 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, |
| @@ -4230,12 +4282,10 @@ static void bnxt_init_napi(struct bnxt *bp) · 31 unmodified lines | ||
| 4230 | 4282 | bnapi = bp->bnapi[i]; |
| 4231 | 4283 | netif_napi_add(bp->dev, &bnapi->napi, |
| 4232 | 4284 | bnxt_poll, 64); |
| 4233 | − napi_hash_add(&bnapi->napi); | |
| 4234 | 4285 | } |
| 4235 | 4286 | } else { |
| 4236 | 4287 | bnapi = bp->bnapi[0]; |
| 4237 | 4288 | netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); |
| 4238 | − napi_hash_add(&bnapi->napi); | |
| 4239 | 4289 | } |
| 4240 | 4290 | } |
| 4241 | 4291 | |
| @@ -4265,14 +4315,12 @@ static void bnxt_enable_napi(struct bnxt *bp) · 23 unmodified lines | ||
| 4265 | 4315 | static void bnxt_tx_disable(struct bnxt *bp) |
| 4266 | 4316 | { |
| 4267 | 4317 | int i; |
| 4268 | − struct bnxt_napi *bnapi; | |
| 4269 | 4318 | struct bnxt_tx_ring_info *txr; |
| 4270 | 4319 | struct netdev_queue *txq; |
| 4271 | 4320 | |
| 4272 | − if (bp->bnapi) { | |
| 4321 | + if (bp->tx_ring) { | |
| 4273 | 4322 | for (i = 0; i < bp->tx_nr_rings; i++) { |
| 4274 | − bnapi = bp->bnapi[i]; | |
| 4275 | − txr = &bnapi->tx_ring; | |
| 4323 | + txr = &bp->tx_ring[i]; | |
| 4276 | 4324 | txq = netdev_get_tx_queue(bp->dev, i); |
| 4277 | 4325 | __netif_tx_lock(txq, smp_processor_id()); |
| 4278 | 4326 | txr->dev_state = BNXT_DEV_STATE_CLOSING; |
| @@ -4287,13 +4335,11 @@ static void bnxt_tx_disable(struct bnxt *bp) · 8 unmodified lines | ||
| 4287 | 4335 | static void bnxt_tx_enable(struct bnxt *bp) |
| 4288 | 4336 | { |
| 4289 | 4337 | int i; |
| 4290 | − struct bnxt_napi *bnapi; | |
| 4291 | 4338 | struct bnxt_tx_ring_info *txr; |
| 4292 | 4339 | struct netdev_queue *txq; |
| 4293 | 4340 | |
| 4294 | 4341 | for (i = 0; i < bp->tx_nr_rings; i++) { |
| 4295 | − bnapi = bp->bnapi[i]; | |
| 4296 | − txr = &bnapi->tx_ring; | |
| 4342 | + txr = &bp->tx_ring[i]; | |
| 4297 | 4343 | txq = netdev_get_tx_queue(bp->dev, i); |
| 4298 | 4344 | txr->dev_state = 0; |
| 4299 | 4345 | } |
| @@ -4355,7 +4401,7 @@ static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) · 55 unmodified lines | ||
| 4355 | 4401 | link_info->auto_mode = resp->auto_mode; |
| 4356 | 4402 | link_info->auto_pause_setting = resp->auto_pause; |
| 4357 | 4403 | link_info->force_pause_setting = resp->force_pause; |
| 4358 | − link_info->duplex_setting = resp->duplex_setting; | |
| 4404 | + link_info->duplex_setting = resp->duplex; | |
| 4359 | 4405 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
| 4360 | 4406 | link_info->link_speed = le16_to_cpu(resp->link_speed); |
| 4361 | 4407 | else |
| @@ -4932,9 +4978,32 @@ skip_uc: · 570 unmodified lines | ||
| 4932 | 4978 | return rc; |
| 4933 | 4979 | } |
| 4934 | 4980 | |
| 4981 | +static bool bnxt_rfs_capable(struct bnxt *bp) | |
| 4982 | +{ | |
| 4983 | +#ifdef CONFIG_RFS_ACCEL | |
| 4984 | + struct bnxt_pf_info *pf = &bp->pf; | |
| 4985 | + int vnics; | |
| 4986 | + | |
| 4987 | + if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP)) | |
| 4988 | + return false; | |
| 4989 | + | |
| 4990 | + vnics = 1 + bp->rx_nr_rings; | |
| 4991 | + if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) | |
| 4992 | + return false; | |
| 4993 | + | |
| 4994 | + return true; | |
| 4995 | +#else | |
| 4996 | + return false; | |
| 4997 | +#endif | |
| 4998 | +} | |
| 4999 | + | |
| 4935 | 5000 | static netdev_features_t bnxt_fix_features(struct net_device *dev, |
| 4936 | 5001 | netdev_features_t features) |
| 4937 | 5002 | { |
| 5003 | + struct bnxt *bp = netdev_priv(dev); | |
| 5004 | + | |
| 5005 | + if (!bnxt_rfs_capable(bp)) | |
| 5006 | + features &= ~NETIF_F_NTUPLE; | |
| 4938 | 5007 | return features; |
| 4939 | 5008 | } |
| 4940 | 5009 | |
| @@ -4975,7 +5044,7 @@ static int bnxt_set_features(struct net_device *dev, netdev_features_t features) · 34 unmodified lines | ||
| 4975 | 5044 | |
| 4976 | 5045 | bp->flags = flags; |
| 4977 | 5046 | |
| 4978 | − if (!netif_running(dev)) { | |
| 5047 | + if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { | |
| 4979 | 5048 | if (update_tpa) |
| 4980 | 5049 | bnxt_set_ring_params(bp); |
| 4981 | 5050 | return rc; |
| @@ -4999,31 +5068,53 @@ static int bnxt_set_features(struct net_device *dev, netdev_features_t features) · 17 unmodified lines | ||
| 4999 | 5068 | return rc; |
| 5000 | 5069 | } |
| 5001 | 5070 | |
| 5071 | +static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) | |
| 5072 | +{ | |
| 5073 | + struct bnxt_tx_ring_info *txr = bnapi->tx_ring; | |
| 5074 | + int i = bnapi->index; | |
| 5075 | + | |
| 5076 | + if (!txr) | |
| 5077 | + return; | |
| 5078 | + | |
| 5079 | + netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", | |
| 5080 | + i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, | |
| 5081 | + txr->tx_cons); | |
| 5082 | +} | |
| 5083 | + | |
| 5084 | +static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) | |
| 5085 | +{ | |
| 5086 | + struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; | |
| 5087 | + int i = bnapi->index; | |
| 5088 | + | |
| 5089 | + if (!rxr) | |
| 5090 | + return; | |
| 5091 | + | |
| 5092 | + netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", | |
| 5093 | + i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, | |
| 5094 | + rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, | |
| 5095 | + rxr->rx_sw_agg_prod); | |
| 5096 | +} | |
| 5097 | + | |
| 5098 | +static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) | |
| 5099 | +{ | |
| 5100 | + struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; | |
| 5101 | + int i = bnapi->index; | |
| 5102 | + | |
| 5103 | + netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", | |
| 5104 | + i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); | |
| 5105 | +} | |
| 5106 | + | |
| 5002 | 5107 | static void bnxt_dbg_dump_states(struct bnxt *bp) |
| 5003 | 5108 | { |
| 5004 | 5109 | int i; |
| 5005 | 5110 | struct bnxt_napi *bnapi; |
| 5006 | − struct bnxt_tx_ring_info *txr; | |
| 5007 | − struct bnxt_rx_ring_info *rxr; | |
| 5008 | − struct bnxt_cp_ring_info *cpr; | |
| 5009 | 5111 | |
| 5010 | 5112 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 5011 | 5113 | bnapi = bp->bnapi[i]; |
| 5012 | − txr = &bnapi->tx_ring; | |
| 5013 | − rxr = &bnapi->rx_ring; | |
| 5014 | − cpr = &bnapi->cp_ring; | |
| 5015 | 5114 | if (netif_msg_drv(bp)) { |
| 5016 | − netdev_info(bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", | |
| 5017 | − i, txr->tx_ring_struct.fw_ring_id, | |
| 5018 | − txr->tx_prod, txr->tx_cons); | |
| 5019 | − netdev_info(bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", | |
| 5020 | − i, rxr->rx_ring_struct.fw_ring_id, | |
| 5021 | − rxr->rx_prod, | |
| 5022 | − rxr->rx_agg_ring_struct.fw_ring_id, | |
| 5023 | − rxr->rx_agg_prod, rxr->rx_sw_agg_prod); | |
| 5024 | − netdev_info(bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", | |
| 5025 | − i, cpr->cp_ring_struct.fw_ring_id, | |
| 5026 | − cpr->cp_raw_cons); | |
| 5115 | + bnxt_dump_tx_sw_state(bnapi); | |
| 5116 | + bnxt_dump_rx_sw_state(bnapi); | |
| 5117 | + bnxt_dump_cp_sw_state(bnapi); | |
| 5027 | 5118 | } |
| 5028 | 5119 | } |
| 5029 | 5120 | } |
| @@ -5294,10 +5385,14 @@ static int bnxt_setup_tc(struct net_device *dev, u8 tc) · 264 unmodified lines | ||
| 5294 | 5385 | return 0; |
| 5295 | 5386 | |
| 5296 | 5387 | if (tc) { |
| 5297 | − int max_rx_rings, max_tx_rings; | |
| 5388 | + int max_rx_rings, max_tx_rings, rc; | |
| 5389 | + bool sh = false; | |
| 5390 | + | |
| 5391 | + if (bp->flags & BNXT_FLAG_SHARED_RINGS) | |
| 5392 | + sh = true; | |
| 5298 | 5393 | |
| 5299 | − bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings); | |
| 5300 | − if (bp->tx_nr_rings_per_tc * tc > max_tx_rings) | |
| 5394 | + rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); | |
| 5395 | + if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings) | |
| 5301 | 5396 | return -ENOMEM; |
| 5302 | 5397 | } |
| 5303 | 5398 | |
| @@ -5551,6 +5646,7 @@ static void bnxt_remove_one(struct pci_dev *pdev) · 247 unmodified lines | ||
| 5551 | 5646 | cancel_work_sync(&bp->sp_task); |
| 5552 | 5647 | bp->sp_event = 0; |
| 5553 | 5648 | |
| 5649 | + bnxt_hwrm_func_drv_unrgtr(bp); | |
| 5554 | 5650 | bnxt_free_hwrm_resources(bp); |
| 5555 | 5651 | pci_iounmap(pdev, bp->bar2); |
| 5556 | 5652 | pci_iounmap(pdev, bp->bar1); |
| @@ -5610,28 +5706,64 @@ static int bnxt_get_max_irq(struct pci_dev *pdev) · 53 unmodified lines | ||
| 5610 | 5706 | return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; |
| 5611 | 5707 | } |
| 5612 | 5708 | |
| 5613 | −void bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx) | |
| 5709 | +static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, | |
| 5710 | + int *max_cp) | |
| 5614 | 5711 | { |
| 5615 | − int max_rings = 0; | |
| 5712 | + int max_ring_grps = 0; | |
| 5616 | 5713 | |
| 5617 | − if (BNXT_PF(bp)) { | |
| 5618 | − *max_tx = bp->pf.max_pf_tx_rings; | |
| 5619 | − *max_rx = bp->pf.max_pf_rx_rings; | |
| 5620 | − max_rings = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); | |
| 5621 | − max_rings = min_t(int, max_rings, bp->pf.max_stat_ctxs); | |
| 5622 | − } else { | |
| 5623 | 5714 | #ifdef CONFIG_BNXT_SRIOV |
| 5715 | + if (!BNXT_PF(bp)) { | |
| 5624 | 5716 | *max_tx = bp->vf.max_tx_rings; |
| 5625 | 5717 | *max_rx = bp->vf.max_rx_rings; |
| 5626 | − max_rings = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); | |
| 5627 | − max_rings = min_t(int, max_rings, bp->vf.max_stat_ctxs); | |
| 5718 | + *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); | |
| 5719 | + *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs); | |
| 5720 | + max_ring_grps = bp->vf.max_hw_ring_grps; | |
| 5721 | + } else | |
| 5628 | 5722 | #endif |
| 5723 | + { | |
| 5724 | + *max_tx = bp->pf.max_tx_rings; | |
| 5725 | + *max_rx = bp->pf.max_rx_rings; | |
| 5726 | + *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); | |
| 5727 | + *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs); | |
| 5728 | + max_ring_grps = bp->pf.max_hw_ring_grps; | |
| 5629 | 5729 | } |
| 5730 | + | |
| 5630 | 5731 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
| 5631 | 5732 | *max_rx >>= 1; |
| 5733 | + *max_rx = min_t(int, *max_rx, max_ring_grps); | |
| 5734 | +} | |
| 5735 | + | |
| 5736 | +int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) | |
| 5737 | +{ | |
| 5738 | + int rx, tx, cp; | |
| 5739 | + | |
| 5740 | + _bnxt_get_max_rings(bp, &rx, &tx, &cp); | |
| 5741 | + if (!rx || !tx || !cp) | |
| 5742 | + return -ENOMEM; | |
| 5632 | 5743 | |
| 5633 | − *max_rx = min_t(int, *max_rx, max_rings); | |
| 5634 | − *max_tx = min_t(int, *max_tx, max_rings); | |
| 5744 | + *max_rx = rx; | |
| 5745 | + *max_tx = tx; | |
| 5746 | + return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); | |
| 5747 | +} | |
| 5748 | + | |
| 5749 | +static int bnxt_set_dflt_rings(struct bnxt *bp) | |
| 5750 | +{ | |
| 5751 | + int dflt_rings, max_rx_rings, max_tx_rings, rc; | |
| 5752 | + bool sh = true; | |
| 5753 | + | |
| 5754 | + if (sh) | |
| 5755 | + bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
| 5756 | + dflt_rings = netif_get_num_default_rss_queues(); | |
| 5757 | + rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); | |
| 5758 | + if (rc) | |
| 5759 | + return rc; | |
| 5760 | + bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); | |
| 5761 | + bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); | |
| 5762 | + bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
| 5763 | + bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : | |
| 5764 | + bp->tx_nr_rings + bp->rx_nr_rings; | |
| 5765 | + bp->num_stat_ctxs = bp->cp_nr_rings; | |
| 5766 | + return rc; | |
| 5635 | 5767 | } |
| 5636 | 5768 | |
| 5637 | 5769 | static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| @@ -5639,7 +5771,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 1 unmodified line | ||
| 5639 | 5771 | static int version_printed; |
| 5640 | 5772 | struct net_device *dev; |
| 5641 | 5773 | struct bnxt *bp; |
| 5642 | − int rc, max_rx_rings, max_tx_rings, max_irqs, dflt_rings; | |
| 5774 | + int rc, max_irqs; | |
| 5643 | 5775 | |
| 5644 | 5776 | if (version_printed++ == 0) |
| 5645 | 5777 | pr_info("%s", version); |
| @@ -5654,11 +5786,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 8 unmodified lines | ||
| 5654 | 5786 | if (bnxt_vf_pciid(ent->driver_data)) |
| 5655 | 5787 | bp->flags |= BNXT_FLAG_VF; |
| 5656 | 5788 | |
| 5657 | − if (pdev->msix_cap) { | |
| 5789 | + if (pdev->msix_cap) | |
| 5658 | 5790 | bp->flags |= BNXT_FLAG_MSIX_CAP; |
| 5659 | − if (BNXT_PF(bp)) | |
| 5660 | − bp->flags |= BNXT_FLAG_RFS; | |
| 5661 | − } | |
| 5662 | 5791 | |
| 5663 | 5792 | rc = bnxt_init_board(pdev, dev); |
| 5664 | 5793 | if (rc < 0) |
| @@ -5677,9 +5806,6 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 12 unmodified lines | ||
| 5677 | 5806 | NETIF_F_RXHASH | |
| 5678 | 5807 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO; |
| 5679 | 5808 | |
| 5680 | − if (bp->flags & BNXT_FLAG_RFS) | |
| 5681 | − dev->hw_features |= NETIF_F_NTUPLE; | |
| 5682 | − | |
| 5683 | 5809 | dev->hw_enc_features = |
| 5684 | 5810 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
| 5685 | 5811 | NETIF_F_TSO | NETIF_F_TSO6 | |
| @@ -5724,19 +5850,21 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 38 unmodified lines | ||
| 5724 | 5850 | |
| 5725 | 5851 | bnxt_set_tpa_flags(bp); |
| 5726 | 5852 | bnxt_set_ring_params(bp); |
| 5727 | − dflt_rings = netif_get_num_default_rss_queues(); | |
| 5728 | 5853 | if (BNXT_PF(bp)) |
| 5729 | 5854 | bp->pf.max_irqs = max_irqs; |
| 5730 | 5855 | #if defined(CONFIG_BNXT_SRIOV) |
| 5731 | 5856 | else |
| 5732 | 5857 | bp->vf.max_irqs = max_irqs; |
| 5733 | 5858 | #endif |
| 5734 | − bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings); | |
| 5735 | − bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); | |
| 5736 | − bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); | |
| 5737 | − bp->tx_nr_rings = bp->tx_nr_rings_per_tc; | |
| 5738 | − bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings); | |
| 5739 | − bp->num_stat_ctxs = bp->cp_nr_rings; | |
| 5859 | + bnxt_set_dflt_rings(bp); | |
| 5860 | + | |
| 5861 | + if (BNXT_PF(bp)) { | |
| 5862 | + dev->hw_features |= NETIF_F_NTUPLE; | |
| 5863 | + if (bnxt_rfs_capable(bp)) { | |
| 5864 | + bp->flags |= BNXT_FLAG_RFS; | |
| 5865 | + dev->features |= NETIF_F_NTUPLE; | |
| 5866 | + } | |
| 5867 | + } | |
| 5740 | 5868 | |
| 5741 | 5869 | if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
| 5742 | 5870 | bp->flags |= BNXT_FLAG_STRIP_VLAN; |
| @@ -11,11 +11,11 @@ · 10 unmodified lines | ||
| 11 | 11 | #define BNXT_H |
| 12 | 12 | |
| 13 | 13 | #define DRV_MODULE_NAME "bnxt_en" |
| 14 | −#define DRV_MODULE_VERSION "0.1.24" | |
| 14 | +#define DRV_MODULE_VERSION "1.0.0" | |
| 15 | 15 | |
| 16 | −#define DRV_VER_MAJ 0 | |
| 17 | −#define DRV_VER_MIN 1 | |
| 18 | −#define DRV_VER_UPD 24 | |
| 16 | +#define DRV_VER_MAJ 1 | |
| 17 | +#define DRV_VER_MIN 0 | |
| 18 | +#define DRV_VER_UPD 0 | |
| 19 | 19 | |
| 20 | 20 | struct tx_bd { |
| 21 | 21 | __le32 tx_bd_len_flags_type; |
| @@ -528,6 +528,7 @@ struct tx_push_bd { · 506 unmodified lines | ||
| 528 | 528 | }; |
| 529 | 529 | |
| 530 | 530 | struct bnxt_tx_ring_info { |
| 531 | + struct bnxt_napi *bnapi; | |
| 531 | 532 | u16 tx_prod; |
| 532 | 533 | u16 tx_cons; |
| 533 | 534 | void __iomem *tx_doorbell; |
| @@ -558,6 +559,7 @@ struct bnxt_tpa_info { · 24 unmodified lines | ||
| 558 | 559 | }; |
| 559 | 560 | |
| 560 | 561 | struct bnxt_rx_ring_info { |
| 562 | + struct bnxt_napi *bnapi; | |
| 561 | 563 | u16 rx_prod; |
| 562 | 564 | u16 rx_agg_prod; |
| 563 | 565 | u16 rx_sw_agg_prod; |
| @@ -604,8 +606,8 @@ struct bnxt_napi { · 40 unmodified lines | ||
| 604 | 606 | |
| 605 | 607 | int index; |
| 606 | 608 | struct bnxt_cp_ring_info cp_ring; |
| 607 | − struct bnxt_rx_ring_info rx_ring; | |
| 608 | − struct bnxt_tx_ring_info tx_ring; | |
| 609 | + struct bnxt_rx_ring_info *rx_ring; | |
| 610 | + struct bnxt_tx_ring_info *tx_ring; | |
| 609 | 611 | |
| 610 | 612 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 611 | 613 | atomic_t poll_state; |
| @@ -695,6 +697,7 @@ struct bnxt_vf_info { · 83 unmodified lines | ||
| 695 | 697 | u16 max_cp_rings; |
| 696 | 698 | u16 max_tx_rings; |
| 697 | 699 | u16 max_rx_rings; |
| 700 | + u16 max_hw_ring_grps; | |
| 698 | 701 | u16 max_l2_ctxs; |
| 699 | 702 | u16 max_irqs; |
| 700 | 703 | u16 max_vnics; |
| @@ -722,9 +725,8 @@ struct bnxt_pf_info { · 21 unmodified lines | ||
| 722 | 725 | u16 max_rsscos_ctxs; |
| 723 | 726 | u16 max_cp_rings; |
| 724 | 727 | u16 max_tx_rings; /* HW assigned max tx rings for this PF */ |
| 725 | − u16 max_pf_tx_rings; /* runtime max tx rings owned by PF */ | |
| 726 | 728 | u16 max_rx_rings; /* HW assigned max rx rings for this PF */ |
| 727 | − u16 max_pf_rx_rings; /* runtime max rx rings owned by PF */ | |
| 729 | + u16 max_hw_ring_grps; | |
| 728 | 730 | u16 max_irqs; |
| 729 | 731 | u16 max_l2_ctxs; |
| 730 | 732 | u16 max_vnics; |
| @@ -875,6 +877,8 @@ struct bnxt { · 144 unmodified lines | ||
| 875 | 877 | #define BNXT_FLAG_USING_MSIX 0x40 |
| 876 | 878 | #define BNXT_FLAG_MSIX_CAP 0x80 |
| 877 | 879 | #define BNXT_FLAG_RFS 0x100 |
| 880 | + #define BNXT_FLAG_SHARED_RINGS 0x200 | |
| 881 | + | |
| 878 | 882 | #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ |
| 879 | 883 | BNXT_FLAG_RFS | \ |
| 880 | 884 | BNXT_FLAG_STRIP_VLAN) |
| @@ -884,6 +888,9 @@ struct bnxt { · 3 unmodified lines | ||
| 884 | 888 | |
| 885 | 889 | struct bnxt_napi **bnapi; |
| 886 | 890 | |
| 891 | + struct bnxt_rx_ring_info *rx_ring; | |
| 892 | + struct bnxt_tx_ring_info *tx_ring; | |
| 893 | + | |
| 887 | 894 | u32 rx_buf_size; |
| 888 | 895 | u32 rx_buf_use_size; /* useable size */ |
| 889 | 896 | u32 rx_ring_size; |
| @@ -913,6 +920,8 @@ struct bnxt { · 23 unmodified lines | ||
| 913 | 920 | int cp_nr_rings; |
| 914 | 921 | |
| 915 | 922 | int num_stat_ctxs; |
| 923 | + | |
| 924 | + /* grp_info indexed by completion ring index */ | |
| 916 | 925 | struct bnxt_ring_grp_info *grp_info; |
| 917 | 926 | struct bnxt_vnic_info *vnic_info; |
| 918 | 927 | int nr_vnics; |
| @@ -1084,9 +1093,10 @@ void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); · 165 unmodified lines | ||
| 1084 | 1093 | int _hwrm_send_message(struct bnxt *, void *, u32, int); |
| 1085 | 1094 | int hwrm_send_message(struct bnxt *, void *, u32, int); |
| 1086 | 1095 | int bnxt_hwrm_set_coal(struct bnxt *); |
| 1096 | +int bnxt_hwrm_func_qcaps(struct bnxt *); | |
| 1087 | 1097 | int bnxt_hwrm_set_pause(struct bnxt *); |
| 1088 | 1098 | int bnxt_hwrm_set_link_setting(struct bnxt *, bool); |
| 1089 | 1099 | int bnxt_open_nic(struct bnxt *, bool, bool); |
| 1090 | 1100 | int bnxt_close_nic(struct bnxt *, bool, bool); |
| 1091 | −void bnxt_get_max_rings(struct bnxt *, int *, int *); | |
| 1101 | +int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); | |
| 1092 | 1102 | #endif |
| @@ -211,7 +211,10 @@ static void bnxt_get_channels(struct net_device *dev, · 210 unmodified lines | ||
| 211 | 211 | struct bnxt *bp = netdev_priv(dev); |
| 212 | 212 | int max_rx_rings, max_tx_rings, tcs; |
| 213 | 213 | |
| 214 | − bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings); | |
| 214 | + bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); | |
| 215 | + channel->max_combined = max_rx_rings; | |
| 216 | + | |
| 217 | + bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false); | |
| 215 | 218 | tcs = netdev_get_num_tc(dev); |
| 216 | 219 | if (tcs > 1) |
| 217 | 220 | max_tx_rings /= tcs; |
| @@ -219,9 +222,12 @@ static void bnxt_get_channels(struct net_device *dev, · 1 unmodified line | ||
| 219 | 222 | channel->max_rx = max_rx_rings; |
| 220 | 223 | channel->max_tx = max_tx_rings; |
| 221 | 224 | channel->max_other = 0; |
| 222 | − channel->max_combined = 0; | |
| 223 | − channel->rx_count = bp->rx_nr_rings; | |
| 224 | − channel->tx_count = bp->tx_nr_rings_per_tc; | |
| 225 | + if (bp->flags & BNXT_FLAG_SHARED_RINGS) { | |
| 226 | + channel->combined_count = bp->rx_nr_rings; | |
| 227 | + } else { | |
| 228 | + channel->rx_count = bp->rx_nr_rings; | |
| 229 | + channel->tx_count = bp->tx_nr_rings_per_tc; | |
| 230 | + } | |
| 225 | 231 | } |
| 226 | 232 | |
| 227 | 233 | static int bnxt_set_channels(struct net_device *dev, |
| @@ -230,19 +236,35 @@ static int bnxt_set_channels(struct net_device *dev, · 2 unmodified lines | ||
| 230 | 236 | struct bnxt *bp = netdev_priv(dev); |
| 231 | 237 | int max_rx_rings, max_tx_rings, tcs; |
| 232 | 238 | u32 rc = 0; |
| 239 | + bool sh = false; | |
| 240 | + | |
| 241 | + if (channel->other_count) | |
| 242 | + return -EINVAL; | |
| 243 | + | |
| 244 | + if (!channel->combined_count && | |
| 245 | + (!channel->rx_count || !channel->tx_count)) | |
| 246 | + return -EINVAL; | |
| 233 | 247 | |
| 234 | − if (channel->other_count || channel->combined_count || | |
| 235 | − !channel->rx_count || !channel->tx_count) | |
| 248 | + if (channel->combined_count && | |
| 249 | + (channel->rx_count || channel->tx_count)) | |
| 236 | 250 | return -EINVAL; |
| 237 | 251 | |
| 238 | − bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings); | |
| 252 | + if (channel->combined_count) | |
| 253 | + sh = true; | |
| 254 | + | |
| 255 | + bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); | |
| 256 | + | |
| 239 | 257 | tcs = netdev_get_num_tc(dev); |
| 240 | 258 | if (tcs > 1) |
| 241 | 259 | max_tx_rings /= tcs; |
| 242 | 260 | |
| 243 | − if (channel->rx_count > max_rx_rings || | |
| 244 | − channel->tx_count > max_tx_rings) | |
| 245 | − return -EINVAL; | |
| 261 | + if (sh && (channel->combined_count > max_rx_rings || | |
| 262 | + channel->combined_count > max_tx_rings)) | |
| 263 | + return -ENOMEM; | |
| 264 | + | |
| 265 | + if (!sh && (channel->rx_count > max_rx_rings || | |
| 266 | + channel->tx_count > max_tx_rings)) | |
| 267 | + return -ENOMEM; | |
| 246 | 268 | |
| 247 | 269 | if (netif_running(dev)) { |
| 248 | 270 | if (BNXT_PF(bp)) { |
| @@ -258,14 +280,27 @@ static int bnxt_set_channels(struct net_device *dev, · 9 unmodified lines | ||
| 258 | 280 | } |
| 259 | 281 | } |
| 260 | 282 | |
| 261 | − bp->rx_nr_rings = channel->rx_count; | |
| 262 | − bp->tx_nr_rings_per_tc = channel->tx_count; | |
| 283 | + if (sh) { | |
| 284 | + bp->flags |= BNXT_FLAG_SHARED_RINGS; | |
| 285 | + bp->rx_nr_rings = channel->combined_count; | |
| 286 | + bp->tx_nr_rings_per_tc = channel->combined_count; | |
| 287 | + } else { | |
| 288 | + bp->flags &= ~BNXT_FLAG_SHARED_RINGS; | |
| 289 | + bp->rx_nr_rings = channel->rx_count; | |
| 290 | + bp->tx_nr_rings_per_tc = channel->tx_count; | |
| 291 | + } | |
| 292 | + | |
| 263 | 293 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; |
| 264 | 294 | if (tcs > 1) |
| 265 | 295 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs; |
| 266 | − bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings); | |
| 296 | + | |
| 297 | + bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : | |
| 298 | + bp->tx_nr_rings + bp->rx_nr_rings; | |
| 299 | + | |
| 267 | 300 | bp->num_stat_ctxs = bp->cp_nr_rings; |
| 268 | 301 | |
| 302 | + /* After changing number of rx channels, update NTUPLE feature. */ | |
| 303 | + netdev_update_features(dev); | |
| 269 | 304 | if (netif_running(dev)) { |
| 270 | 305 | rc = bnxt_open_nic(bp, true, false); |
| 271 | 306 | if ((!rc) && BNXT_PF(bp)) { |
| @@ -802,6 +837,45 @@ static int bnxt_flash_nvram(struct net_device *dev, · 530 unmodified lines | ||
| 802 | 837 | return rc; |
| 803 | 838 | } |
| 804 | 839 | |
| 840 | +static int bnxt_firmware_reset(struct net_device *dev, | |
| 841 | + u16 dir_type) | |
| 842 | +{ | |
| 843 | + struct bnxt *bp = netdev_priv(dev); | |
| 844 | + struct hwrm_fw_reset_input req = {0}; | |
| 845 | + | |
| 846 | + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); | |
| 847 | + | |
| 848 | + /* TODO: Support ASAP ChiMP self-reset (e.g. upon PF driver unload) */ | |
| 849 | + /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ | |
| 850 | + /* (e.g. when firmware isn't already running) */ | |
| 851 | + switch (dir_type) { | |
| 852 | + case BNX_DIR_TYPE_CHIMP_PATCH: | |
| 853 | + case BNX_DIR_TYPE_BOOTCODE: | |
| 854 | + case BNX_DIR_TYPE_BOOTCODE_2: | |
| 855 | + req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; | |
| 856 | + /* Self-reset ChiMP upon next PCIe reset: */ | |
| 857 | + req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; | |
| 858 | + break; | |
| 859 | + case BNX_DIR_TYPE_APE_FW: | |
| 860 | + case BNX_DIR_TYPE_APE_PATCH: | |
| 861 | + req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; | |
| 862 | + break; | |
| 863 | + case BNX_DIR_TYPE_KONG_FW: | |
| 864 | + case BNX_DIR_TYPE_KONG_PATCH: | |
| 865 | + req.embedded_proc_type = | |
| 866 | + FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; | |
| 867 | + break; | |
| 868 | + case BNX_DIR_TYPE_BONO_FW: | |
| 869 | + case BNX_DIR_TYPE_BONO_PATCH: | |
| 870 | + req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; | |
| 871 | + break; | |
| 872 | + default: | |
| 873 | + return -EINVAL; | |
| 874 | + } | |
| 875 | + | |
| 876 | + return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
| 877 | +} | |
| 878 | + | |
| 805 | 879 | static int bnxt_flash_firmware(struct net_device *dev, |
| 806 | 880 | u16 dir_type, |
| 807 | 881 | const u8 *fw_data, |
| @@ -818,6 +892,9 @@ static int bnxt_flash_firmware(struct net_device *dev, · 10 unmodified lines | ||
| 818 | 892 | case BNX_DIR_TYPE_BOOTCODE_2: |
| 819 | 893 | code_type = CODE_BOOT; |
| 820 | 894 | break; |
| 895 | + case BNX_DIR_TYPE_APE_FW: | |
| 896 | + code_type = CODE_MCTP_PASSTHRU; | |
| 897 | + break; | |
| 821 | 898 | default: |
| 822 | 899 | netdev_err(dev, "Unsupported directory entry type: %u\n", |
| 823 | 900 | dir_type); |
| @@ -856,10 +933,9 @@ static int bnxt_flash_firmware(struct net_device *dev, · 32 unmodified lines | ||
| 856 | 933 | /* TODO: Validate digital signature (RSA-encrypted SHA-256 hash) here */ |
| 857 | 934 | rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, |
| 858 | 935 | 0, 0, fw_data, fw_size); |
| 859 | − if (rc == 0) { /* Firmware update successful */ | |
| 860 | − /* TODO: Notify processor it needs to reset itself | |
| 861 | − */ | |
| 862 | − } | |
| 936 | + if (rc == 0) /* Firmware update successful */ | |
| 937 | + rc = bnxt_firmware_reset(dev, dir_type); | |
| 938 | + | |
| 863 | 939 | return rc; |
| 864 | 940 | } |
| 865 | 941 | |
| @@ -103,19 +103,22 @@ struct hwrm_async_event_cmpl { · 102 unmodified lines | ||
| 103 | 103 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) |
| 104 | 104 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) |
| 105 | 105 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) |
| 106 | + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0) | |
| 106 | 107 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) |
| 107 | 108 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) |
| 108 | 109 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) |
| 109 | − #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x20UL << 0) | |
| 110 | + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0) | |
| 110 | 111 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0) |
| 111 | 112 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) |
| 113 | + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0) | |
| 112 | 114 | #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0) |
| 113 | 115 | __le32 event_data2; |
| 114 | 116 | u8 opaque_v; |
| 115 | 117 | #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL |
| 116 | 118 | #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL |
| 117 | 119 | #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 |
| 118 | − u8 unused_1[3]; | |
| 120 | + u8 timestamp_lo; | |
| 121 | + __le16 timestamp_hi; | |
| 119 | 122 | __le32 event_data1; |
| 120 | 123 | }; |
| 121 | 124 | |
| @@ -132,9 +135,16 @@ struct hwrm_async_event_cmpl_link_status_change { · 10 unmodified lines | ||
| 132 | 135 | #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL |
| 133 | 136 | #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL |
| 134 | 137 | #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 |
| 135 | − u8 unused_1[3]; | |
| 138 | + u8 timestamp_lo; | |
| 139 | + __le16 timestamp_hi; | |
| 136 | 140 | __le32 event_data1; |
| 137 | − #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_UP 0x1UL | |
| 141 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL | |
| 142 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) | |
| 143 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) | |
| 144 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL | |
| 145 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 | |
| 146 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL | |
| 147 | + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 | |
| 138 | 148 | }; |
| 139 | 149 | |
| 140 | 150 | /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ |
| @@ -150,7 +160,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { · 9 unmodified lines | ||
| 150 | 160 | #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL |
| 151 | 161 | #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL |
| 152 | 162 | #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 |
| 153 | − u8 unused_1[3]; | |
| 163 | + u8 timestamp_lo; | |
| 164 | + __le16 timestamp_hi; | |
| 154 | 165 | __le32 event_data1; |
| 155 | 166 | #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL |
| 156 | 167 | #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 |
| @@ -169,7 +180,8 @@ struct hwrm_async_event_cmpl_link_speed_change { · 12 unmodified lines | ||
| 169 | 180 | #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL |
| 170 | 181 | #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL |
| 171 | 182 | #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 |
| 172 | − u8 unused_1[3]; | |
| 183 | + u8 timestamp_lo; | |
| 184 | + __le16 timestamp_hi; | |
| 173 | 185 | __le32 event_data1; |
| 174 | 186 | #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL |
| 175 | 187 | #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL |
| @@ -200,7 +212,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { · 24 unmodified lines | ||
| 200 | 212 | #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL |
| 201 | 213 | #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL |
| 202 | 214 | #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 |
| 203 | − u8 unused_1[3]; | |
| 215 | + u8 timestamp_lo; | |
| 216 | + __le16 timestamp_hi; | |
| 204 | 217 | __le32 event_data1; |
| 205 | 218 | #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL |
| 206 | 219 | #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 |
| @@ -219,7 +232,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { · 12 unmodified lines | ||
| 219 | 232 | #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL |
| 220 | 233 | #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL |
| 221 | 234 | #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 |
| 222 | − u8 unused_1[3]; | |
| 235 | + u8 timestamp_lo; | |
| 236 | + __le16 timestamp_hi; | |
| 223 | 237 | __le32 event_data1; |
| 224 | 238 | #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL |
| 225 | 239 | #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 |
| @@ -238,7 +252,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { · 12 unmodified lines | ||
| 238 | 252 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL |
| 239 | 253 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL |
| 240 | 254 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 |
| 241 | − u8 unused_1[3]; | |
| 255 | + u8 timestamp_lo; | |
| 256 | + __le16 timestamp_hi; | |
| 242 | 257 | __le32 event_data1; |
| 243 | 258 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL |
| 244 | 259 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 |
| @@ -257,7 +272,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { · 12 unmodified lines | ||
| 257 | 272 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL |
| 258 | 273 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL |
| 259 | 274 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 |
| 260 | − u8 unused_1[3]; | |
| 275 | + u8 timestamp_lo; | |
| 276 | + __le16 timestamp_hi; | |
| 261 | 277 | __le32 event_data1; |
| 262 | 278 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL |
| 263 | 279 | #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 |
| @@ -276,10 +292,13 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { · 12 unmodified lines | ||
| 276 | 292 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL |
| 277 | 293 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL |
| 278 | 294 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 |
| 279 | − u8 unused_1[3]; | |
| 295 | + u8 timestamp_lo; | |
| 296 | + __le16 timestamp_hi; | |
| 280 | 297 | __le32 event_data1; |
| 281 | 298 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL |
| 282 | 299 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 |
| 300 | + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL | |
| 301 | + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 | |
| 283 | 302 | }; |
| 284 | 303 | |
| 285 | 304 | /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ |
| @@ -289,16 +308,19 @@ struct hwrm_async_event_cmpl_pf_drvr_load { · 3 unmodified lines | ||
| 289 | 308 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 |
| 290 | 309 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) |
| 291 | 310 | __le16 event_id; |
| 292 | − #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x20UL << 0) | |
| 311 | + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0) | |
| 293 | 312 | __le32 event_data2; |
| 294 | 313 | u8 opaque_v; |
| 295 | 314 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL |
| 296 | 315 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL |
| 297 | 316 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 |
| 298 | − u8 unused_1[3]; | |
| 317 | + u8 timestamp_lo; | |
| 318 | + __le16 timestamp_hi; | |
| 299 | 319 | __le32 event_data1; |
| 300 | 320 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL |
| 301 | 321 | #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 |
| 322 | + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL | |
| 323 | + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 | |
| 302 | 324 | }; |
| 303 | 325 | |
| 304 | 326 | /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ |
| @@ -314,7 +336,8 @@ struct hwrm_async_event_cmpl_vf_flr { · 9 unmodified lines | ||
| 314 | 336 | #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL |
| 315 | 337 | #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL |
| 316 | 338 | #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 |
| 317 | − u8 unused_1[3]; | |
| 339 | + u8 timestamp_lo; | |
| 340 | + __le16 timestamp_hi; | |
| 318 | 341 | __le32 event_data1; |
| 319 | 342 | #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL |
| 320 | 343 | #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 |
| @@ -333,7 +356,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { · 12 unmodified lines | ||
| 333 | 356 | #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL |
| 334 | 357 | #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL |
| 335 | 358 | #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 |
| 336 | − u8 unused_1[3]; | |
| 359 | + u8 timestamp_lo; | |
| 360 | + __le16 timestamp_hi; | |
| 337 | 361 | __le32 event_data1; |
| 338 | 362 | #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL |
| 339 | 363 | #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 |
| @@ -357,18 +381,20 @@ struct hwrm_async_event_cmpl_hwrm_error { · 17 unmodified lines | ||
| 357 | 381 | #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL |
| 358 | 382 | #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL |
| 359 | 383 | #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 |
| 360 | − u8 unused_1[3]; | |
| 384 | + u8 timestamp_lo; | |
| 385 | + __le16 timestamp_hi; | |
| 361 | 386 | __le32 event_data1; |
| 362 | 387 | #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL |
| 363 | 388 | }; |
| 364 | 389 | |
| 365 | −/* HW Resource Manager Specification 0.7.8 */ | |
| 366 | −#define HWRM_VERSION_MAJOR 0 | |
| 367 | −#define HWRM_VERSION_MINOR 7 | |
| 368 | −#define HWRM_VERSION_UPDATE 8 | |
| 390 | +/* HW Resource Manager Specification 1.0.0 */ | |
| 391 | +#define HWRM_VERSION_MAJOR 1 | |
| 392 | +#define HWRM_VERSION_MINOR 0 | |
| 393 | +#define HWRM_VERSION_UPDATE 0 | |
| 369 | 394 | |
| 370 | −#define HWRM_VERSION_STR "0.7.8" | |
| 371 | −/* Following is the signature for HWRM message field that indicates not | |
| 395 | +#define HWRM_VERSION_STR "1.0.0" | |
| 396 | +/* | |
| 397 | + * Following is the signature for HWRM message field that indicates not | |
| 372 | 398 | * applicable (All F's). Need to cast it the size of the field if needed. |
| 373 | 399 | */ |
| 374 | 400 | #define HWRM_NA_SIGNATURE ((__le32)(-1)) |
| @@ -398,7 +424,9 @@ struct output { · 23 unmodified lines | ||
| 398 | 424 | struct cmd_nums { |
| 399 | 425 | __le16 req_type; |
| 400 | 426 | #define HWRM_VER_GET (0x0UL) |
| 401 | − #define HWRM_FUNC_DISABLE (0x10UL) | |
| 427 | + #define HWRM_FUNC_BUF_UNRGTR (0xeUL) | |
| 428 | + #define HWRM_FUNC_VF_CFG (0xfUL) | |
| 429 | + #define RESERVED1 (0x10UL) | |
| 402 | 430 | #define HWRM_FUNC_RESET (0x11UL) |
| 403 | 431 | #define HWRM_FUNC_GETFID (0x12UL) |
| 404 | 432 | #define HWRM_FUNC_VF_ALLOC (0x13UL) |
| @@ -414,10 +442,9 @@ struct cmd_nums { · 9 unmodified lines | ||
| 414 | 442 | #define HWRM_FUNC_DRV_RGTR (0x1dUL) |
| 415 | 443 | #define HWRM_FUNC_DRV_QVER (0x1eUL) |
| 416 | 444 | #define HWRM_FUNC_BUF_RGTR (0x1fUL) |
| 417 | − #define HWRM_FUNC_VF_CFG (0x20UL) | |
| 418 | 445 | #define HWRM_PORT_PHY_CFG (0x20UL) |
| 419 | 446 | #define HWRM_PORT_MAC_CFG (0x21UL) |
| 420 | − #define HWRM_PORT_ENABLE (0x22UL) | |
| 447 | + #define RESERVED2 (0x22UL) | |
| 421 | 448 | #define HWRM_PORT_QSTATS (0x23UL) |
| 422 | 449 | #define HWRM_PORT_LPBK_QSTATS (0x24UL) |
| 423 | 450 | #define HWRM_PORT_CLR_STATS (0x25UL) |
| @@ -455,13 +482,11 @@ struct cmd_nums { · 31 unmodified lines | ||
| 455 | 482 | #define HWRM_RING_GRP_FREE (0x61UL) |
| 456 | 483 | #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) |
| 457 | 484 | #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) |
| 458 | − #define HWRM_ARB_GRP_ALLOC (0x80UL) | |
| 459 | − #define HWRM_ARB_GRP_CFG (0x81UL) | |
| 460 | 485 | #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) |
| 461 | 486 | #define HWRM_CFA_L2_FILTER_FREE (0x91UL) |
| 462 | 487 | #define HWRM_CFA_L2_FILTER_CFG (0x92UL) |
| 463 | 488 | #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) |
| 464 | − #define HWRM_CFA_L2_SET_BCASTMCAST_MIRRORING (0x94UL) | |
| 489 | + #define RESERVED3 (0x94UL) | |
| 465 | 490 | #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) |
| 466 | 491 | #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) |
| 467 | 492 | #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) |
| @@ -469,6 +494,9 @@ struct cmd_nums { · 1 unmodified line | ||
| 469 | 494 | #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) |
| 470 | 495 | #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) |
| 471 | 496 | #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) |
| 497 | + #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) | |
| 498 | + #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) | |
| 499 | + #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) | |
| 472 | 500 | #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) |
| 473 | 501 | #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) |
| 474 | 502 | #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) |
| @@ -483,8 +511,6 @@ struct cmd_nums { · 8 unmodified lines | ||
| 483 | 511 | #define HWRM_FWD_RESP (0xd2UL) |
| 484 | 512 | #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) |
| 485 | 513 | #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) |
| 486 | − #define HWRM_MGMT_L2_FILTER_ALLOC (0x100UL) | |
| 487 | − #define HWRM_MGMT_L2_FILTER_FREE (0x101UL) | |
| 488 | 514 | #define HWRM_DBG_READ_DIRECT (0xff10UL) |
| 489 | 515 | #define HWRM_DBG_READ_INDIRECT (0xff11UL) |
| 490 | 516 | #define HWRM_DBG_WRITE_DIRECT (0xff12UL) |
| @@ -505,7 +531,6 @@ struct cmd_nums { · 14 unmodified lines | ||
| 505 | 531 | __le16 unused_0[3]; |
| 506 | 532 | }; |
| 507 | 533 | |
| 508 | −/* Return Codes (8 bytes) */ | |
| 509 | 534 | struct ret_codes { |
| 510 | 535 | __le16 error_code; |
| 511 | 536 | #define HWRM_ERR_CODE_SUCCESS (0x0UL) |
| @@ -529,7 +554,7 @@ struct hwrm_err_output { · 17 unmodified lines | ||
| 529 | 554 | __le16 resp_len; |
| 530 | 555 | __le32 opaque_0; |
| 531 | 556 | __le16 opaque_1; |
| 532 | − u8 opaque_2; | |
| 557 | + u8 cmd_err; | |
| 533 | 558 | u8 valid; |
| 534 | 559 | }; |
| 535 | 560 | |
| @@ -686,65 +711,38 @@ struct hwrm_ver_get_output { · 150 unmodified lines | ||
| 686 | 711 | u8 hwrm_fw_min; |
| 687 | 712 | u8 hwrm_fw_bld; |
| 688 | 713 | u8 hwrm_fw_rsvd; |
| 689 | − u8 ape_fw_maj; | |
| 690 | − u8 ape_fw_min; | |
| 691 | − u8 ape_fw_bld; | |
| 692 | − u8 ape_fw_rsvd; | |
| 693 | − u8 kong_fw_maj; | |
| 694 | − u8 kong_fw_min; | |
| 695 | − u8 kong_fw_bld; | |
| 696 | − u8 kong_fw_rsvd; | |
| 697 | − u8 tang_fw_maj; | |
| 698 | − u8 tang_fw_min; | |
| 699 | − u8 tang_fw_bld; | |
| 700 | − u8 tang_fw_rsvd; | |
| 701 | − u8 bono_fw_maj; | |
| 702 | − u8 bono_fw_min; | |
| 703 | − u8 bono_fw_bld; | |
| 704 | − u8 bono_fw_rsvd; | |
| 714 | + u8 mgmt_fw_maj; | |
| 715 | + u8 mgmt_fw_min; | |
| 716 | + u8 mgmt_fw_bld; | |
| 717 | + u8 mgmt_fw_rsvd; | |
| 718 | + u8 netctrl_fw_maj; | |
| 719 | + u8 netctrl_fw_min; | |
| 720 | + u8 netctrl_fw_bld; | |
| 721 | + u8 netctrl_fw_rsvd; | |
| 722 | + __le32 reserved1; | |
| 723 | + u8 roce_fw_maj; | |
| 724 | + u8 roce_fw_min; | |
| 725 | + u8 roce_fw_bld; | |
| 726 | + u8 roce_fw_rsvd; | |
| 705 | 727 | char hwrm_fw_name[16]; |
| 706 | − char ape_fw_name[16]; | |
| 707 | − char kong_fw_name[16]; | |
| 708 | − char tang_fw_name[16]; | |
| 709 | − char bono_fw_name[16]; | |
| 728 | + char mgmt_fw_name[16]; | |
| 729 | + char netctrl_fw_name[16]; | |
| 730 | + __le32 reserved2[4]; | |
| 731 | + char roce_fw_name[16]; | |
| 710 | 732 | __le16 chip_num; |
| 711 | 733 | u8 chip_rev; |
| 712 | 734 | u8 chip_metal; |
| 713 | 735 | u8 chip_bond_id; |
| 714 | − u8 unused_0; | |
| 736 | + u8 chip_platform_type; | |
| 737 | + #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC (0x0UL << 0) | |
| 738 | + #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA (0x1UL << 0) | |
| 739 | + #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM (0x2UL << 0) | |
| 715 | 740 | __le16 max_req_win_len; |
| 716 | 741 | __le16 max_resp_len; |
| 717 | 742 | __le16 def_req_timeout; |
| 743 | + u8 unused_0; | |
| 718 | 744 | u8 unused_1; |
| 719 | 745 | u8 unused_2; |
| 720 | − u8 unused_3; | |
| 721 | − u8 valid; | |
| 722 | −}; | |
| 723 | − | |
| 724 | −/* hwrm_func_disable */ | |
| 725 | −/* Input (24 bytes) */ | |
| 726 | −struct hwrm_func_disable_input { | |
| 727 | − __le16 req_type; | |
| 728 | − __le16 cmpl_ring; | |
| 729 | − __le16 seq_id; | |
| 730 | − __le16 target_id; | |
| 731 | − __le64 resp_addr; | |
| 732 | − __le32 enables; | |
| 733 | − #define FUNC_DISABLE_REQ_ENABLES_VF_ID_VALID 0x1UL | |
| 734 | − __le16 vf_id; | |
| 735 | − __le16 unused_0; | |
| 736 | −}; | |
| 737 | − | |
| 738 | −/* Output (16 bytes) */ | |
| 739 | −struct hwrm_func_disable_output { | |
| 740 | − __le16 error_code; | |
| 741 | − __le16 req_type; | |
| 742 | − __le16 seq_id; | |
| 743 | − __le16 resp_len; | |
| 744 | − __le32 unused_0; | |
| 745 | − u8 unused_1; | |
| 746 | − u8 unused_2; | |
| 747 | − u8 unused_3; | |
| 748 | 746 | u8 valid; |
| 749 | 747 | }; |
| 750 | 748 | |
| @@ -759,7 +757,12 @@ struct hwrm_func_reset_input { · 8 unmodified lines | ||
| 759 | 757 | __le32 enables; |
| 760 | 758 | #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL |
| 761 | 759 | __le16 vf_id; |
| 762 | − __le16 unused_0; | |
| 760 | + u8 func_reset_level; | |
| 761 | + #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL (0x0UL << 0) | |
| 762 | + #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME (0x1UL << 0) | |
| 763 | + #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN (0x2UL << 0) | |
| 764 | + #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF (0x3UL << 0) | |
| 765 | + u8 unused_0; | |
| 763 | 766 | }; |
| 764 | 767 | |
| 765 | 768 | /* Output (16 bytes) */ |
| @@ -861,7 +864,7 @@ struct hwrm_func_vf_free_output { · 95 unmodified lines | ||
| 861 | 864 | }; |
| 862 | 865 | |
| 863 | 866 | /* hwrm_func_vf_cfg */ |
| 864 | −/* Input (24 bytes) */ | |
| 867 | +/* Input (32 bytes) */ | |
| 865 | 868 | struct hwrm_func_vf_cfg_input { |
| 866 | 869 | __le16 req_type; |
| 867 | 870 | __le16 cmpl_ring; |
| @@ -871,8 +874,11 @@ struct hwrm_func_vf_cfg_input { · 3 unmodified lines | ||
| 871 | 874 | __le32 enables; |
| 872 | 875 | #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL |
| 873 | 876 | #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL |
| 877 | + #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL | |
| 874 | 878 | __le16 mtu; |
| 875 | 879 | __le16 guest_vlan; |
| 880 | + __le16 async_event_cr; | |
| 881 | + __le16 unused_0[3]; | |
| 876 | 882 | }; |
| 877 | 883 | |
| 878 | 884 | /* Output (16 bytes) */ |
| @@ -944,7 +950,7 @@ struct hwrm_func_cfg_input { · 65 unmodified lines | ||
| 944 | 950 | __le16 seq_id; |
| 945 | 951 | __le16 target_id; |
| 946 | 952 | __le64 resp_addr; |
| 947 | − __le16 vf_id; | |
| 953 | + __le16 fid; | |
| 948 | 954 | u8 unused_0; |
| 949 | 955 | u8 unused_1; |
| 950 | 956 | __le32 flags; |
| @@ -1000,10 +1006,6 @@ struct hwrm_func_cfg_input { · 49 unmodified lines | ||
| 1000 | 1006 | #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0) |
| 1001 | 1007 | #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0) |
| 1002 | 1008 | u8 allowed_vlan_pris; |
| 1003 | − #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_NOCHECK (0x0UL << 0) | |
| 1004 | − #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_VALIDATE_VLAN (0x1UL << 0) | |
| 1005 | − #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_INSERT_IF_VLANDNE (0x2UL << 0) | |
| 1006 | − #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0) | |
| 1007 | 1009 | u8 evb_mode; |
| 1008 | 1010 | #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0) |
| 1009 | 1011 | #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0) |
| @@ -1166,6 +1168,15 @@ struct hwrm_func_drv_rgtr_input { · 156 unmodified lines | ||
| 1166 | 1168 | #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL |
| 1167 | 1169 | #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL |
| 1168 | 1170 | __le16 os_type; |
| 1171 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN (0x0UL << 0) | |
| 1172 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER (0x1UL << 0) | |
| 1173 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS (0xeUL << 0) | |
| 1174 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS (0x1dUL << 0) | |
| 1175 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX (0x24UL << 0) | |
| 1176 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD (0x2aUL << 0) | |
| 1177 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI (0x68UL << 0) | |
| 1178 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 (0x73UL << 0) | |
| 1179 | + #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 (0x74UL << 0) | |
| 1169 | 1180 | u8 ver_maj; |
| 1170 | 1181 | u8 ver_min; |
| 1171 | 1182 | u8 ver_upd; |
| @@ -1276,9 +1287,7 @@ struct hwrm_func_drv_qver_input { · 104 unmodified lines | ||
| 1276 | 1287 | __le16 seq_id; |
| 1277 | 1288 | __le16 target_id; |
| 1278 | 1289 | __le64 resp_addr; |
| 1279 | − __le32 enables; | |
| 1280 | − #define FUNC_DRV_QVER_REQ_ENABLES_OS_TYPE_VALID 0x1UL | |
| 1281 | − #define FUNC_DRV_QVER_REQ_ENABLES_VER_VALID 0x2UL | |
| 1290 | + __le32 reserved; | |
| 1282 | 1291 | __le16 fid; |
| 1283 | 1292 | __le16 unused_0; |
| 1284 | 1293 | }; |
| @@ -1290,6 +1299,15 @@ struct hwrm_func_drv_qver_output { · 5 unmodified lines | ||
| 1290 | 1299 | __le16 seq_id; |
| 1291 | 1300 | __le16 resp_len; |
| 1292 | 1301 | __le16 os_type; |
| 1302 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN (0x0UL << 0) | |
| 1303 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER (0x1UL << 0) | |
| 1304 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS (0xeUL << 0) | |
| 1305 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS (0x1dUL << 0) | |
| 1306 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX (0x24UL << 0) | |
| 1307 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD (0x2aUL << 0) | |
| 1308 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI (0x68UL << 0) | |
| 1309 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 (0x73UL << 0) | |
| 1310 | + #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 (0x74UL << 0) | |
| 1293 | 1311 | u8 ver_maj; |
| 1294 | 1312 | u8 ver_min; |
| 1295 | 1313 | u8 ver_upd; |
| @@ -1498,9 +1516,7 @@ struct hwrm_port_phy_qcfg_output { · 202 unmodified lines | ||
| 1498 | 1516 | u8 force_pause; |
| 1499 | 1517 | #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL |
| 1500 | 1518 | #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL |
| 1501 | − u8 duplex_setting; | |
| 1502 | − #define PORT_PHY_QCFG_RESP_DUPLEX_SETTING_HALF (0x0UL << 0) | |
| 1503 | − #define PORT_PHY_QCFG_RESP_DUPLEX_SETTING_FULL (0x1UL << 0) | |
| 1519 | + u8 reserved1; | |
| 1504 | 1520 | __le32 preemphasis; |
| 1505 | 1521 | u8 phy_maj; |
| 1506 | 1522 | u8 phy_min; |
| @@ -1601,33 +1617,6 @@ struct hwrm_port_mac_cfg_output { · 94 unmodified lines | ||
| 1601 | 1617 | u8 valid; |
| 1602 | 1618 | }; |
| 1603 | 1619 | |
| 1604 | −/* hwrm_port_enable */ | |
| 1605 | −/* Input (24 bytes) */ | |
| 1606 | −struct hwrm_port_enable_input { | |
| 1607 | − __le16 req_type; | |
| 1608 | − __le16 cmpl_ring; | |
| 1609 | − __le16 seq_id; | |
| 1610 | − __le16 target_id; | |
| 1611 | − __le64 resp_addr; | |
| 1612 | − __le32 flags; | |
| 1613 | − #define PORT_ENABLE_REQ_FLAGS_FORWARD_TRAFFIC 0x1UL | |
| 1614 | − __le16 port_id; | |
| 1615 | − __le16 unused_0; | |
| 1616 | −}; | |
| 1617 | − | |
| 1618 | −/* Output (16 bytes) */ | |
| 1619 | −struct hwrm_port_enable_output { | |
| 1620 | − __le16 error_code; | |
| 1621 | − __le16 req_type; | |
| 1622 | − __le16 seq_id; | |
| 1623 | − __le16 resp_len; | |
| 1624 | − __le32 unused_0; | |
| 1625 | − u8 unused_1; | |
| 1626 | − u8 unused_2; | |
| 1627 | − u8 unused_3; | |
| 1628 | − u8 valid; | |
| 1629 | −}; | |
| 1630 | − | |
| 1631 | 1620 | /* hwrm_port_qstats */ |
| 1632 | 1621 | /* Input (40 bytes) */ |
| 1633 | 1622 | struct hwrm_port_qstats_input { |
| @@ -1651,10 +1640,11 @@ struct hwrm_port_qstats_output { · 17 unmodified lines | ||
| 1651 | 1640 | __le16 req_type; |
| 1652 | 1641 | __le16 seq_id; |
| 1653 | 1642 | __le16 resp_len; |
| 1654 | − __le32 unused_0; | |
| 1643 | + __le16 tx_stat_size; | |
| 1644 | + __le16 rx_stat_size; | |
| 1645 | + u8 unused_0; | |
| 1655 | 1646 | u8 unused_1; |
| 1656 | 1647 | u8 unused_2; |
| 1657 | − u8 unused_3; | |
| 1658 | 1648 | u8 valid; |
| 1659 | 1649 | }; |
| 1660 | 1650 | |
| @@ -1668,7 +1658,7 @@ struct hwrm_port_lpbk_qstats_input { · 7 unmodified lines | ||
| 1668 | 1658 | __le64 resp_addr; |
| 1669 | 1659 | }; |
| 1670 | 1660 | |
| 1671 | −/* Output (64 bytes) */ | |
| 1661 | +/* Output (96 bytes) */ | |
| 1672 | 1662 | struct hwrm_port_lpbk_qstats_output { |
| 1673 | 1663 | __le16 error_code; |
| 1674 | 1664 | __le16 req_type; |
| @@ -1680,6 +1670,10 @@ struct hwrm_port_lpbk_qstats_output { · 5 unmodified lines | ||
| 1680 | 1670 | __le64 lpbk_ucast_bytes; |
| 1681 | 1671 | __le64 lpbk_mcast_bytes; |
| 1682 | 1672 | __le64 lpbk_bcast_bytes; |
| 1673 | + __le64 tx_stat_discard; | |
| 1674 | + __le64 tx_stat_error; | |
| 1675 | + __le64 rx_stat_discard; | |
| 1676 | + __le64 rx_stat_error; | |
| 1683 | 1677 | __le32 unused_0; |
| 1684 | 1678 | u8 unused_1; |
| 1685 | 1679 | u8 unused_2; |
| @@ -1884,12 +1878,11 @@ struct hwrm_queue_buffers_cfg_input { · 198 unmodified lines | ||
| 1884 | 1878 | __le32 enables; |
| 1885 | 1879 | #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL |
| 1886 | 1880 | #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL |
| 1887 | − #define QUEUE_BUFFERS_CFG_REQ_ENABLES_GROUP 0x4UL | |
| 1888 | − #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x8UL | |
| 1889 | − #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x10UL | |
| 1890 | − #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x20UL | |
| 1891 | − #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x40UL | |
| 1892 | − #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x80UL | |
| 1881 | + #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x4UL | |
| 1882 | + #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x8UL | |
| 1883 | + #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x10UL | |
| 1884 | + #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x20UL | |
| 1885 | + #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x40UL | |
| 1893 | 1886 | __le32 queue_id; |
| 1894 | 1887 | __le32 reserved; |
| 1895 | 1888 | __le32 shared; |
| @@ -1921,15 +1914,15 @@ struct hwrm_queue_pfcenable_cfg_input { · 25 unmodified lines | ||
| 1921 | 1914 | __le16 seq_id; |
| 1922 | 1915 | __le16 target_id; |
| 1923 | 1916 | __le64 resp_addr; |
| 1924 | − __le32 enables; | |
| 1925 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI0_PFC_ENABLED 0x1UL | |
| 1926 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI1_PFC_ENABLED 0x2UL | |
| 1927 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI2_PFC_ENABLED 0x4UL | |
| 1928 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI3_PFC_ENABLED 0x8UL | |
| 1929 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI4_PFC_ENABLED 0x10UL | |
| 1930 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI5_PFC_ENABLED 0x20UL | |
| 1931 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI6_PFC_ENABLED 0x40UL | |
| 1932 | − #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI7_PFC_ENABLED 0x80UL | |
| 1917 | + __le32 flags; | |
| 1918 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL | |
| 1919 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL | |
| 1920 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL | |
| 1921 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL | |
| 1922 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL | |
| 1923 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL | |
| 1924 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL | |
| 1925 | + #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL | |
| 1933 | 1926 | __le16 port_id; |
| 1934 | 1927 | __le16 unused_0; |
| 1935 | 1928 | }; |
| @@ -1962,14 +1955,14 @@ struct hwrm_queue_pri2cos_cfg_input { · 26 unmodified lines | ||
| 1962 | 1955 | #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL |
| 1963 | 1956 | __le32 enables; |
| 1964 | 1957 | u8 port_id; |
| 1965 | − u8 pri0_cos; | |
| 1966 | − u8 pri1_cos; | |
| 1967 | − u8 pri2_cos; | |
| 1968 | − u8 pri3_cos; | |
| 1969 | − u8 pri4_cos; | |
| 1970 | − u8 pri5_cos; | |
| 1971 | − u8 pri6_cos; | |
| 1972 | − u8 pri7_cos; | |
| 1958 | + u8 pri0_cos_queue_id; | |
| 1959 | + u8 pri1_cos_queue_id; | |
| 1960 | + u8 pri2_cos_queue_id; | |
| 1961 | + u8 pri3_cos_queue_id; | |
| 1962 | + u8 pri4_cos_queue_id; | |
| 1963 | + u8 pri5_cos_queue_id; | |
| 1964 | + u8 pri6_cos_queue_id; | |
| 1965 | + u8 pri7_cos_queue_id; | |
| 1973 | 1966 | u8 unused_0[7]; |
| 1974 | 1967 | }; |
| 1975 | 1968 | |
| @@ -2164,6 +2157,7 @@ struct hwrm_vnic_cfg_input { · 188 unmodified lines | ||
| 2164 | 2157 | __le32 flags; |
| 2165 | 2158 | #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL |
| 2166 | 2159 | #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL |
| 2160 | + #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL | |
| 2167 | 2161 | __le32 enables; |
| 2168 | 2162 | #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL |
| 2169 | 2163 | #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL |
| @@ -2380,18 +2374,16 @@ struct hwrm_ring_alloc_input { · 210 unmodified lines | ||
| 2380 | 2374 | __le16 target_id; |
| 2381 | 2375 | __le64 resp_addr; |
| 2382 | 2376 | __le32 enables; |
| 2383 | − #define RING_ALLOC_REQ_ENABLES_ARB_GRP_ID_VALID 0x1UL | |
| 2384 | − #define RING_ALLOC_REQ_ENABLES_INPUT_NUM_VALID 0x2UL | |
| 2385 | − #define RING_ALLOC_REQ_ENABLES_WEIGHT_VALID 0x4UL | |
| 2377 | + #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL | |
| 2378 | + #define RING_ALLOC_REQ_ENABLES_RESERVED2 0x2UL | |
| 2379 | + #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL | |
| 2386 | 2380 | #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL |
| 2387 | − #define RING_ALLOC_REQ_ENABLES_MIN_BW_VALID 0x10UL | |
| 2381 | + #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL | |
| 2388 | 2382 | #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL |
| 2389 | 2383 | u8 ring_type; |
| 2390 | 2384 | #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0) |
| 2391 | 2385 | #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0) |
| 2392 | 2386 | #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0) |
| 2393 | − #define RING_ALLOC_REQ_RING_TYPE_STATUS (0x3UL << 0) | |
| 2394 | − #define RING_ALLOC_REQ_RING_TYPE_CMD (0x4UL << 0) | |
| 2395 | 2387 | u8 unused_0; |
| 2396 | 2388 | __le16 unused_1; |
| 2397 | 2389 | __le64 page_tbl_addr; |
| @@ -2406,17 +2398,17 @@ struct hwrm_ring_alloc_input { · 8 unmodified lines | ||
| 2406 | 2398 | __le16 queue_id; |
| 2407 | 2399 | u8 unused_4; |
| 2408 | 2400 | u8 unused_5; |
| 2409 | − __le32 arb_grp_id; | |
| 2410 | − __le16 input_number; | |
| 2401 | + __le32 reserved1; | |
| 2402 | + __le16 reserved2; | |
| 2411 | 2403 | u8 unused_6; |
| 2412 | 2404 | u8 unused_7; |
| 2413 | − __le32 weight; | |
| 2405 | + __le32 reserved3; | |
| 2414 | 2406 | __le32 stat_ctx_id; |
| 2415 | − __le32 min_bw; | |
| 2407 | + __le32 reserved4; | |
| 2416 | 2408 | __le32 max_bw; |
| 2417 | 2409 | u8 int_mode; |
| 2418 | 2410 | #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0) |
| 2419 | − #define RING_ALLOC_REQ_INT_MODE_MSI (0x1UL << 0) | |
| 2411 | + #define RING_ALLOC_REQ_INT_MODE_RSVD (0x1UL << 0) | |
| 2420 | 2412 | #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0) |
| 2421 | 2413 | #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0) |
| 2422 | 2414 | u8 unused_8[3]; |
| @@ -2448,8 +2440,6 @@ struct hwrm_ring_free_input { · 25 unmodified lines | ||
| 2448 | 2440 | #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0) |
| 2449 | 2441 | #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0) |
| 2450 | 2442 | #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0) |
| 2451 | − #define RING_FREE_REQ_RING_TYPE_STATUS (0x3UL << 0) | |
| 2452 | − #define RING_FREE_REQ_RING_TYPE_CMD (0x4UL << 0) | |
| 2453 | 2443 | u8 unused_0; |
| 2454 | 2444 | __le16 ring_id; |
| 2455 | 2445 | __le32 unused_1; |
| @@ -2550,8 +2540,6 @@ struct hwrm_ring_reset_input { · 94 unmodified lines | ||
| 2550 | 2540 | #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0) |
| 2551 | 2541 | #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0) |
| 2552 | 2542 | #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0) |
| 2553 | − #define RING_RESET_REQ_RING_TYPE_STATUS (0x3UL << 0) | |
| 2554 | − #define RING_RESET_REQ_RING_TYPE_CMD (0x4UL << 0) | |
| 2555 | 2543 | u8 unused_0; |
| 2556 | 2544 | __le16 ring_id; |
| 2557 | 2545 | __le32 unused_1; |
| @@ -2622,61 +2610,6 @@ struct hwrm_ring_grp_free_output { · 64 unmodified lines | ||
| 2622 | 2610 | u8 valid; |
| 2623 | 2611 | }; |
| 2624 | 2612 | |
| 2625 | −/* hwrm_arb_grp_alloc */ | |
| 2626 | −/* Input (24 bytes) */ | |
| 2627 | −struct hwrm_arb_grp_alloc_input { | |
| 2628 | − __le16 req_type; | |
| 2629 | − __le16 cmpl_ring; | |
| 2630 | − __le16 seq_id; | |
| 2631 | − __le16 target_id; | |
| 2632 | − __le64 resp_addr; | |
| 2633 | − __le16 input_number; | |
| 2634 | − __le16 unused_0[3]; | |
| 2635 | −}; | |
| 2636 | − | |
| 2637 | −/* Output (16 bytes) */ | |
| 2638 | −struct hwrm_arb_grp_alloc_output { | |
| 2639 | − __le16 error_code; | |
| 2640 | − __le16 req_type; | |
| 2641 | − __le16 seq_id; | |
| 2642 | − __le16 resp_len; | |
| 2643 | − __le16 arb_grp_id; | |
| 2644 | − u8 unused_0; | |
| 2645 | − u8 unused_1; | |
| 2646 | − u8 unused_2; | |
| 2647 | − u8 unused_3; | |
| 2648 | − u8 unused_4; | |
| 2649 | − u8 valid; | |
| 2650 | −}; | |
| 2651 | − | |
| 2652 | −/* hwrm_arb_grp_cfg */ | |
| 2653 | −/* Input (32 bytes) */ | |
| 2654 | −struct hwrm_arb_grp_cfg_input { | |
| 2655 | − __le16 req_type; | |
| 2656 | − __le16 cmpl_ring; | |
| 2657 | − __le16 seq_id; | |
| 2658 | − __le16 target_id; | |
| 2659 | − __le64 resp_addr; | |
| 2660 | − __le32 arb_grp_id; | |
| 2661 | − __le16 input_number; | |
| 2662 | − __le16 tx_ring; | |
| 2663 | − __le32 weight; | |
| 2664 | − __le32 unused_0; | |
| 2665 | −}; | |
| 2666 | − | |
| 2667 | −/* Output (16 bytes) */ | |
| 2668 | −struct hwrm_arb_grp_cfg_output { | |
| 2669 | − __le16 error_code; | |
| 2670 | − __le16 req_type; | |
| 2671 | − __le16 seq_id; | |
| 2672 | − __le16 resp_len; | |
| 2673 | − __le32 unused_0; | |
| 2674 | − u8 unused_1; | |
| 2675 | − u8 unused_2; | |
| 2676 | − u8 unused_3; | |
| 2677 | − u8 valid; | |
| 2678 | −}; | |
| 2679 | − | |
| 2680 | 2613 | /* hwrm_cfa_l2_filter_alloc */ |
| 2681 | 2614 | /* Input (96 bytes) */ |
| 2682 | 2615 | struct hwrm_cfa_l2_filter_alloc_input { |
| @@ -2708,7 +2641,7 @@ struct hwrm_cfa_l2_filter_alloc_input { · 25 unmodified lines | ||
| 2708 | 2641 | #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL |
| 2709 | 2642 | #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL |
| 2710 | 2643 | #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL |
| 2711 | − #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x8000UL | |
| 2644 | + #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL | |
| 2712 | 2645 | #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL |
| 2713 | 2646 | u8 l2_addr[6]; |
| 2714 | 2647 | u8 unused_0; |
| @@ -2751,7 +2684,7 @@ struct hwrm_cfa_l2_filter_alloc_input { · 36 unmodified lines | ||
| 2751 | 2684 | #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) |
| 2752 | 2685 | #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) |
| 2753 | 2686 | u8 unused_7; |
| 2754 | − __le16 dst_vnic_id; | |
| 2687 | + __le16 dst_id; | |
| 2755 | 2688 | __le16 mirror_vnic_id; |
| 2756 | 2689 | u8 pri_hint; |
| 2757 | 2690 | #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) |
| @@ -2816,10 +2749,11 @@ struct hwrm_cfa_l2_filter_cfg_input { · 58 unmodified lines | ||
| 2816 | 2749 | #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) |
| 2817 | 2750 | #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL |
| 2818 | 2751 | __le32 enables; |
| 2819 | − #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_VNIC_ID_VALID 0x1UL | |
| 2752 | + #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL | |
| 2753 | + #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL | |
| 2820 | 2754 | __le64 l2_filter_id; |
| 2821 | − __le32 dst_vnic_id; | |
| 2822 | − __le32 unused_0; | |
| 2755 | + __le32 dst_id; | |
| 2756 | + __le32 new_mirror_vnic_id; | |
| 2823 | 2757 | }; |
| 2824 | 2758 | |
| 2825 | 2759 | /* Output (16 bytes) */ |
| @@ -2843,9 +2777,9 @@ struct hwrm_cfa_l2_set_rx_mask_input { · 17 unmodified lines | ||
| 2843 | 2777 | __le16 seq_id; |
| 2844 | 2778 | __le16 target_id; |
| 2845 | 2779 | __le64 resp_addr; |
| 2846 | − __le32 dflt_vnic_id; | |
| 2780 | + __le32 vnic_id; | |
| 2847 | 2781 | __le32 mask; |
| 2848 | − #define CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST 0x1UL | |
| 2782 | + #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL | |
| 2849 | 2783 | #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL |
| 2850 | 2784 | #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL |
| 2851 | 2785 | #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL |
| @@ -2869,46 +2803,6 @@ struct hwrm_cfa_l2_set_rx_mask_output { · 17 unmodified lines | ||
| 2869 | 2803 | u8 valid; |
| 2870 | 2804 | }; |
| 2871 | 2805 | |
| 2872 | −/* hwrm_cfa_l2_set_bcastmcast_mirroring */ | |
| 2873 | −/* Input (32 bytes) */ | |
| 2874 | −struct hwrm_cfa_l2_set_bcastmcast_mirroring_input { | |
| 2875 | − __le16 req_type; | |
| 2876 | − __le16 cmpl_ring; | |
| 2877 | − __le16 seq_id; | |
| 2878 | − __le16 target_id; | |
| 2879 | − __le64 resp_addr; | |
| 2880 | − __le32 dflt_vnic_id; | |
| 2881 | − __le32 mirroring_flags; | |
| 2882 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_BCAST_MIRRORING 0x1UL | |
| 2883 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_MCAST_MIRRORING 0x2UL | |
| 2884 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_BCAST_SRC_KNOCKOUT 0x4UL | |
| 2885 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_MCAST_SRC_KNOCKOUT 0x8UL | |
| 2886 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_VLAN_ID_VALID 0x10UL | |
| 2887 | − __le16 vlan_id; | |
| 2888 | − u8 bcast_domain; | |
| 2889 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_PFONLY (0x0UL << 0) | |
| 2890 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_ALLPFS (0x1UL << 0) | |
| 2891 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_ALLPFSVFS (0x2UL << 0) | |
| 2892 | − u8 mcast_domain; | |
| 2893 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_PFONLY (0x0UL << 0) | |
| 2894 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_ALLPFS (0x1UL << 0) | |
| 2895 | − #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_ALLPFSVFS (0x2UL << 0) | |
| 2896 | − __le32 unused_0; | |
| 2897 | −}; | |
| 2898 | − | |
| 2899 | −/* Output (16 bytes) */ | |
| 2900 | −struct hwrm_cfa_l2_set_bcastmcast_mirroring_output { | |
| 2901 | − __le16 error_code; | |
| 2902 | − __le16 req_type; | |
| 2903 | − __le16 seq_id; | |
| 2904 | − __le16 resp_len; | |
| 2905 | − __le32 unused_0; | |
| 2906 | − u8 unused_1; | |
| 2907 | − u8 unused_2; | |
| 2908 | − u8 unused_3; | |
| 2909 | − u8 valid; | |
| 2910 | −}; | |
| 2911 | − | |
| 2912 | 2806 | /* hwrm_cfa_tunnel_filter_alloc */ |
| 2913 | 2807 | /* Input (88 bytes) */ |
| 2914 | 2808 | struct hwrm_cfa_tunnel_filter_alloc_input { |
| @@ -3017,17 +2911,16 @@ struct hwrm_cfa_encap_record_alloc_input { · 102 unmodified lines | ||
| 3017 | 2911 | __le32 encap_data[16]; |
| 3018 | 2912 | }; |
| 3019 | 2913 | |
| 3020 | −/* Output (24 bytes) */ | |
| 2914 | +/* Output (16 bytes) */ | |
| 3021 | 2915 | struct hwrm_cfa_encap_record_alloc_output { |
| 3022 | 2916 | __le16 error_code; |
| 3023 | 2917 | __le16 req_type; |
| 3024 | 2918 | __le16 seq_id; |
| 3025 | 2919 | __le16 resp_len; |
| 3026 | − __le64 encap_record_id; | |
| 3027 | − __le32 unused_0; | |
| 2920 | + __le32 encap_record_id; | |
| 2921 | + u8 unused_0; | |
| 3028 | 2922 | u8 unused_1; |
| 3029 | 2923 | u8 unused_2; |
| 3030 | − u8 unused_3; | |
| 3031 | 2924 | u8 valid; |
| 3032 | 2925 | }; |
| 3033 | 2926 | |
| @@ -3039,7 +2932,8 @@ struct hwrm_cfa_encap_record_free_input { · 5 unmodified lines | ||
| 3039 | 2932 | __le16 seq_id; |
| 3040 | 2933 | __le16 target_id; |
| 3041 | 2934 | __le64 resp_addr; |
| 3042 | − __le64 encap_record_id; | |
| 2935 | + __le32 encap_record_id; | |
| 2936 | + __le32 unused_0; | |
| 3043 | 2937 | }; |
| 3044 | 2938 | |
| 3045 | 2939 | /* Output (16 bytes) */ |
| @@ -3083,14 +2977,21 @@ struct hwrm_cfa_ntuple_filter_alloc_input { · 37 unmodified lines | ||
| 3083 | 2977 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL |
| 3084 | 2978 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL |
| 3085 | 2979 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL |
| 3086 | − #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x10000UL | |
| 2980 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL | |
| 3087 | 2981 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL |
| 2982 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL | |
| 3088 | 2983 | __le64 l2_filter_id; |
| 3089 | 2984 | u8 src_macaddr[6]; |
| 3090 | 2985 | __be16 ethertype; |
| 3091 | − u8 ipaddr_type; | |
| 2986 | + u8 ip_addr_type; | |
| 2987 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN (0x0UL << 0) | |
| 2988 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 (0x4UL << 0) | |
| 2989 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 (0x6UL << 0) | |
| 3092 | 2990 | u8 ip_protocol; |
| 3093 | − __le16 dst_vnic_id; | |
| 2991 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN (0x0UL << 0) | |
| 2992 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP (0x6UL << 0) | |
| 2993 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP (0x11UL << 0) | |
| 2994 | + __le16 dst_id; | |
| 3094 | 2995 | __le16 mirror_vnic_id; |
| 3095 | 2996 | u8 tunnel_type; |
| 3096 | 2997 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) |
| @@ -3104,6 +3005,11 @@ struct hwrm_cfa_ntuple_filter_alloc_input { · 7 unmodified lines | ||
| 3104 | 3005 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) |
| 3105 | 3006 | #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) |
| 3106 | 3007 | u8 pri_hint; |
| 3008 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) | |
| 3009 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE (0x1UL << 0) | |
| 3010 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW (0x2UL << 0) | |
| 3011 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST (0x3UL << 0) | |
| 3012 | + #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST (0x4UL << 0) | |
| 3107 | 3013 | __be32 src_ipaddr[4]; |
| 3108 | 3014 | __be32 src_ipaddr_mask[4]; |
| 3109 | 3015 | __be32 dst_ipaddr[4]; |
| @@ -3162,11 +3068,11 @@ struct hwrm_cfa_ntuple_filter_cfg_input { · 52 unmodified lines | ||
| 3162 | 3068 | __le16 target_id; |
| 3163 | 3069 | __le64 resp_addr; |
| 3164 | 3070 | __le32 enables; |
| 3165 | − #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_VNIC_ID_VALID 0x1UL | |
| 3166 | − #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID_VALID 0x2UL | |
| 3071 | + #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL | |
| 3072 | + #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL | |
| 3167 | 3073 | __le32 unused_0; |
| 3168 | 3074 | __le64 ntuple_filter_id; |
| 3169 | − __le32 new_dst_vnic_id; | |
| 3075 | + __le32 new_dst_id; | |
| 3170 | 3076 | __le32 new_mirror_vnic_id; |
| 3171 | 3077 | }; |
| 3172 | 3078 | |
| @@ -3192,16 +3098,8 @@ struct hwrm_tunnel_dst_port_query_input { · 19 unmodified lines | ||
| 3192 | 3098 | __le16 target_id; |
| 3193 | 3099 | __le64 resp_addr; |
| 3194 | 3100 | u8 tunnel_type; |
| 3195 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) | |
| 3196 | 3101 | #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) |
| 3197 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) | |
| 3198 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) | |
| 3199 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) | |
| 3200 | 3102 | #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) |
| 3201 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) | |
| 3202 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_STT (0x7UL << 0) | |
| 3203 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) | |
| 3204 | − #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) | |
| 3205 | 3103 | u8 unused_0[7]; |
| 3206 | 3104 | }; |
| 3207 | 3105 | |
| @@ -3228,16 +3126,8 @@ struct hwrm_tunnel_dst_port_alloc_input { · 20 unmodified lines | ||
| 3228 | 3126 | __le16 target_id; |
| 3229 | 3127 | __le64 resp_addr; |
| 3230 | 3128 | u8 tunnel_type; |
| 3231 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) | |
| 3232 | 3129 | #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) |
| 3233 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) | |
| 3234 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) | |
| 3235 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) | |
| 3236 | 3130 | #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) |
| 3237 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) | |
| 3238 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) | |
| 3239 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) | |
| 3240 | − #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) | |
| 3241 | 3131 | u8 unused_0; |
| 3242 | 3132 | __be16 tunnel_dst_port_val; |
| 3243 | 3133 | __le32 unused_1; |
| @@ -3267,16 +3157,8 @@ struct hwrm_tunnel_dst_port_free_input { · 23 unmodified lines | ||
| 3267 | 3157 | __le16 target_id; |
| 3268 | 3158 | __le64 resp_addr; |
| 3269 | 3159 | u8 tunnel_type; |
| 3270 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) | |
| 3271 | 3160 | #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) |
| 3272 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) | |
| 3273 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) | |
| 3274 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) | |
| 3275 | 3161 | #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) |
| 3276 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) | |
| 3277 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_STT (0x7UL << 0) | |
| 3278 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) | |
| 3279 | − #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) | |
| 3280 | 3162 | u8 unused_0; |
| 3281 | 3163 | __le16 tunnel_dst_port_id; |
| 3282 | 3164 | __le32 unused_1; |
| @@ -3416,68 +3298,145 @@ struct hwrm_stat_ctx_clr_stats_output { · 133 unmodified lines | ||
| 3416 | 3298 | u8 valid; |
| 3417 | 3299 | }; |
| 3418 | 3300 | |
| 3419 | −/* hwrm_mgmt_l2_filter_alloc */ | |
| 3420 | −/* Input (56 bytes) */ | |
| 3421 | −struct hwrm_mgmt_l2_filter_alloc_input { | |
| 3301 | +/* hwrm_fw_reset */ | |
| 3302 | +/* Input (24 bytes) */ | |
| 3303 | +struct hwrm_fw_reset_input { | |
| 3422 | 3304 | __le16 req_type; |
| 3423 | 3305 | __le16 cmpl_ring; |
| 3424 | 3306 | __le16 seq_id; |
| 3425 | 3307 | __le16 target_id; |
| 3426 | 3308 | __le64 resp_addr; |
| 3427 | − __le32 flags; | |
| 3428 | − #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL | |
| 3429 | − #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) | |
| 3430 | − #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) | |
| 3431 | − __le32 enables; | |
| 3432 | − #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDRESS 0x1UL | |
| 3433 | − #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_OVLAN 0x2UL | |
| 3434 | − #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_IVLAN 0x4UL | |
| 3435 | − #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_ACTION_ID 0x8UL | |
| 3436 | − u8 l2_address[6]; | |
| 3309 | + u8 embedded_proc_type; | |
| 3310 | + #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0) | |
| 3311 | + #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0) | |
| 3312 | + #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0) | |
| 3313 | + #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0) | |
| 3314 | + #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0) | |
| 3315 | + u8 selfrst_status; | |
| 3316 | + #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) | |
| 3317 | + #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) | |
| 3318 | + #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) | |
| 3319 | + __le16 unused_0[3]; | |
| 3320 | +}; | |
| 3321 | + | |
| 3322 | +/* Output (16 bytes) */ | |
| 3323 | +struct hwrm_fw_reset_output { | |
| 3324 | + __le16 error_code; | |
| 3325 | + __le16 req_type; | |
| 3326 | + __le16 seq_id; | |
| 3327 | + __le16 resp_len; | |
| 3328 | + u8 selfrst_status; | |
| 3329 | + #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) | |
| 3330 | + #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) | |
| 3331 | + #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) | |
| 3437 | 3332 | u8 unused_0; |
| 3333 | + __le16 unused_1; | |
| 3334 | + u8 unused_2; | |
| 3335 | + u8 unused_3; | |
| 3336 | + u8 unused_4; | |
| 3337 | + u8 valid; | |
| 3338 | +}; | |
| 3339 | + | |
| 3340 | +/* hwrm_exec_fwd_resp */ | |
| 3341 | +/* Input (128 bytes) */ | |
| 3342 | +struct hwrm_exec_fwd_resp_input { | |
| 3343 | + __le16 req_type; | |
| 3344 | + __le16 cmpl_ring; | |
| 3345 | + __le16 seq_id; | |
| 3346 | + __le16 target_id; | |
| 3347 | + __le64 resp_addr; | |
| 3348 | + __le32 encap_request[26]; | |
| 3349 | + __le16 encap_resp_target_id; | |
| 3350 | + __le16 unused_0[3]; | |
| 3351 | +}; | |
| 3352 | + | |
| 3353 | +/* Output (16 bytes) */ | |
| 3354 | +struct hwrm_exec_fwd_resp_output { | |
| 3355 | + __le16 error_code; | |
| 3356 | + __le16 req_type; | |
| 3357 | + __le16 seq_id; | |
| 3358 | + __le16 resp_len; | |
| 3359 | + __le32 unused_0; | |
| 3438 | 3360 | u8 unused_1; |
| 3439 | − u8 l2_address_mask[6]; | |
| 3440 | − __le16 ovlan; | |
| 3441 | − __le16 ovlan_mask; | |
| 3442 | − __le16 ivlan; | |
| 3443 | − __le16 ivlan_mask; | |
| 3444 | 3361 | u8 unused_2; |
| 3445 | 3362 | u8 unused_3; |
| 3446 | − __le32 action_id; | |
| 3447 | − u8 action_bypass; | |
| 3448 | − #define MGMT_L2_FILTER_ALLOC_REQ_ACTION_BYPASS 0x1UL | |
| 3449 | − u8 unused_5[3]; | |
| 3363 | + u8 valid; | |
| 3364 | +}; | |
| 3365 | + | |
| 3366 | +/* hwrm_reject_fwd_resp */ | |
| 3367 | +/* Input (128 bytes) */ | |
| 3368 | +struct hwrm_reject_fwd_resp_input { | |
| 3369 | + __le16 req_type; | |
| 3370 | + __le16 cmpl_ring; | |
| 3371 | + __le16 seq_id; | |
| 3372 | + __le16 target_id; | |
| 3373 | + __le64 resp_addr; | |
| 3374 | + __le32 encap_request[26]; | |
| 3375 | + __le16 encap_resp_target_id; | |
| 3376 | + __le16 unused_0[3]; | |
| 3450 | 3377 | }; |
| 3451 | 3378 | |
| 3452 | 3379 | /* Output (16 bytes) */ |
| 3453 | −struct hwrm_mgmt_l2_filter_alloc_output { | |
| 3380 | +struct hwrm_reject_fwd_resp_output { | |
| 3454 | 3381 | __le16 error_code; |
| 3455 | 3382 | __le16 req_type; |
| 3456 | 3383 | __le16 seq_id; |
| 3457 | 3384 | __le16 resp_len; |
| 3458 | − __le16 mgmt_l2_filter_id; | |
| 3385 | + __le32 unused_0; | |
| 3386 | + u8 unused_1; | |
| 3387 | + u8 unused_2; | |
| 3388 | + u8 unused_3; | |
| 3389 | + u8 valid; | |
| 3390 | +}; | |
| 3391 | + | |
| 3392 | +/* hwrm_fwd_resp */ | |
| 3393 | +/* Input (40 bytes) */ | |
| 3394 | +struct hwrm_fwd_resp_input { | |
| 3395 | + __le16 req_type; | |
| 3396 | + __le16 cmpl_ring; | |
| 3397 | + __le16 seq_id; | |
| 3398 | + __le16 target_id; | |
| 3399 | + __le64 resp_addr; | |
| 3400 | + __le16 encap_resp_target_id; | |
| 3401 | + __le16 encap_resp_cmpl_ring; | |
| 3402 | + __le16 encap_resp_len; | |
| 3459 | 3403 | u8 unused_0; |
| 3460 | 3404 | u8 unused_1; |
| 3405 | + __le64 encap_resp_addr; | |
| 3406 | + __le32 encap_resp[24]; | |
| 3407 | +}; | |
| 3408 | + | |
| 3409 | +/* Output (16 bytes) */ | |
| 3410 | +struct hwrm_fwd_resp_output { | |
| 3411 | + __le16 error_code; | |
| 3412 | + __le16 req_type; | |
| 3413 | + __le16 seq_id; | |
| 3414 | + __le16 resp_len; | |
| 3415 | + __le32 unused_0; | |
| 3416 | + u8 unused_1; | |
| 3461 | 3417 | u8 unused_2; |
| 3462 | 3418 | u8 unused_3; |
| 3463 | − u8 unused_4; | |
| 3464 | 3419 | u8 valid; |
| 3465 | 3420 | }; |
| 3466 | 3421 | |
| 3467 | −/* hwrm_mgmt_l2_filter_free */ | |
| 3468 | −/* Input (24 bytes) */ | |
| 3469 | −struct hwrm_mgmt_l2_filter_free_input { | |
| 3422 | +/* hwrm_fwd_async_event_cmpl */ | |
| 3423 | +/* Input (32 bytes) */ | |
| 3424 | +struct hwrm_fwd_async_event_cmpl_input { | |
| 3470 | 3425 | __le16 req_type; |
| 3471 | 3426 | __le16 cmpl_ring; |
| 3472 | 3427 | __le16 seq_id; |
| 3473 | 3428 | __le16 target_id; |
| 3474 | 3429 | __le64 resp_addr; |
| 3475 | − __le16 mgmt_l2_filter_id; | |
| 3476 | − __le16 unused_0[3]; | |
| 3430 | + __le16 encap_async_event_target_id; | |
| 3431 | + u8 unused_0; | |
| 3432 | + u8 unused_1; | |
| 3433 | + u8 unused_2[3]; | |
| 3434 | + u8 unused_3; | |
| 3435 | + __le32 encap_async_event_cmpl[4]; | |
| 3477 | 3436 | }; |
| 3478 | 3437 | |
| 3479 | 3438 | /* Output (16 bytes) */ |
| 3480 | −struct hwrm_mgmt_l2_filter_free_output { | |
| 3439 | +struct hwrm_fwd_async_event_cmpl_output { | |
| 3481 | 3440 | __le16 error_code; |
| 3482 | 3441 | __le16 req_type; |
| 3483 | 3442 | __le16 seq_id; |
| @@ -3489,6 +3448,31 @@ struct hwrm_mgmt_l2_filter_free_output { · 5 unmodified lines | ||
| 3489 | 3448 | u8 valid; |
| 3490 | 3449 | }; |
| 3491 | 3450 | |
| 3451 | +/* hwrm_temp_monitor_query */ | |
| 3452 | +/* Input (16 bytes) */ | |
| 3453 | +struct hwrm_temp_monitor_query_input { | |
| 3454 | + __le16 req_type; | |
| 3455 | + __le16 cmpl_ring; | |
| 3456 | + __le16 seq_id; | |
| 3457 | + __le16 target_id; | |
| 3458 | + __le64 resp_addr; | |
| 3459 | +}; | |
| 3460 | + | |
| 3461 | +/* Output (16 bytes) */ | |
| 3462 | +struct hwrm_temp_monitor_query_output { | |
| 3463 | + __le16 error_code; | |
| 3464 | + __le16 req_type; | |
| 3465 | + __le16 seq_id; | |
| 3466 | + __le16 resp_len; | |
| 3467 | + u8 temp; | |
| 3468 | + u8 unused_0; | |
| 3469 | + __le16 unused_1; | |
| 3470 | + u8 unused_2; | |
| 3471 | + u8 unused_3; | |
| 3472 | + u8 unused_4; | |
| 3473 | + u8 valid; | |
| 3474 | +}; | |
| 3475 | + | |
| 3492 | 3476 | /* hwrm_nvm_raw_write_blk */ |
| 3493 | 3477 | /* Input (32 bytes) */ |
| 3494 | 3478 | struct hwrm_nvm_raw_write_blk_input { |
| @@ -3621,7 +3605,7 @@ struct hwrm_nvm_get_dir_info_output { · 126 unmodified lines | ||
| 3621 | 3605 | }; |
| 3622 | 3606 | |
| 3623 | 3607 | /* hwrm_nvm_write */ |
| 3624 | −/* Input (40 bytes) */ | |
| 3608 | +/* Input (48 bytes) */ | |
| 3625 | 3609 | struct hwrm_nvm_write_input { |
| 3626 | 3610 | __le16 req_type; |
| 3627 | 3611 | __le16 cmpl_ring; |
| @@ -3637,6 +3621,8 @@ struct hwrm_nvm_write_input { · 9 unmodified lines | ||
| 3637 | 3621 | __le16 option; |
| 3638 | 3622 | __le16 flags; |
| 3639 | 3623 | #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL |
| 3624 | + __le32 dir_item_length; | |
| 3625 | + __le32 unused_0; | |
| 3640 | 3626 | }; |
| 3641 | 3627 | |
| 3642 | 3628 | /* Output (16 bytes) */ |
| @@ -3645,10 +3631,9 @@ struct hwrm_nvm_write_output { · 2 unmodified lines | ||
| 3645 | 3631 | __le16 req_type; |
| 3646 | 3632 | __le16 seq_id; |
| 3647 | 3633 | __le16 resp_len; |
| 3648 | − __le32 unused_0; | |
| 3649 | − u8 unused_1; | |
| 3650 | − u8 unused_2; | |
| 3651 | − u8 unused_3; | |
| 3634 | + __le32 dir_item_length; | |
| 3635 | + __le16 dir_idx; | |
| 3636 | + u8 unused_0; | |
| 3652 | 3637 | u8 valid; |
| 3653 | 3638 | }; |
| 3654 | 3639 | |
| @@ -3833,214 +3818,4 @@ struct hwrm_nvm_verify_update_output { · 178 unmodified lines | ||
| 3833 | 3818 | u8 valid; |
| 3834 | 3819 | }; |
| 3835 | 3820 | |
| 3836 | −/* hwrm_exec_fwd_resp */ | |
| 3837 | −/* Input (120 bytes) */ | |
| 3838 | −struct hwrm_exec_fwd_resp_input { | |
| 3839 | − __le16 req_type; | |
| 3840 | − __le16 cmpl_ring; | |
| 3841 | − __le16 seq_id; | |
| 3842 | − __le16 target_id; | |
| 3843 | − __le64 resp_addr; | |
| 3844 | − __le32 encap_request[24]; | |
| 3845 | − __le16 encap_resp_target_id; | |
| 3846 | − __le16 unused_0[3]; | |
| 3847 | −}; | |
| 3848 | − | |
| 3849 | −/* Output (16 bytes) */ | |
| 3850 | −struct hwrm_exec_fwd_resp_output { | |
| 3851 | − __le16 error_code; | |
| 3852 | − __le16 req_type; | |
| 3853 | − __le16 seq_id; | |
| 3854 | − __le16 resp_len; | |
| 3855 | − __le32 unused_0; | |
| 3856 | − u8 unused_1; | |
| 3857 | − u8 unused_2; | |
| 3858 | − u8 unused_3; | |
| 3859 | − u8 valid; | |
| 3860 | −}; | |
| 3861 | − | |
| 3862 | −/* hwrm_reject_fwd_resp */ | |
| 3863 | −/* Input (120 bytes) */ | |
| 3864 | −struct hwrm_reject_fwd_resp_input { | |
| 3865 | − __le16 req_type; | |
| 3866 | − __le16 cmpl_ring; | |
| 3867 | − __le16 seq_id; | |
| 3868 | − __le16 target_id; | |
| 3869 | − __le64 resp_addr; | |
| 3870 | − __le32 encap_request[24]; | |
| 3871 | − __le16 encap_resp_target_id; | |
| 3872 | − __le16 unused_0[3]; | |
| 3873 | −}; | |
| 3874 | − | |
| 3875 | −/* Output (16 bytes) */ | |
| 3876 | −struct hwrm_reject_fwd_resp_output { | |
| 3877 | − __le16 error_code; | |
| 3878 | − __le16 req_type; | |
| 3879 | − __le16 seq_id; | |
| 3880 | − __le16 resp_len; | |
| 3881 | − __le32 unused_0; | |
| 3882 | − u8 unused_1; | |
| 3883 | − u8 unused_2; | |
| 3884 | − u8 unused_3; | |
| 3885 | − u8 valid; | |
| 3886 | −}; | |
| 3887 | − | |
| 3888 | −/* hwrm_fwd_resp */ | |
| 3889 | −/* Input (40 bytes) */ | |
| 3890 | −struct hwrm_fwd_resp_input { | |
| 3891 | − __le16 req_type; | |
| 3892 | − __le16 cmpl_ring; | |
| 3893 | − __le16 seq_id; | |
| 3894 | − __le16 target_id; | |
| 3895 | − __le64 resp_addr; | |
| 3896 | − __le16 encap_resp_target_id; | |
| 3897 | − __le16 encap_resp_cmpl_ring; | |
| 3898 | − __le16 encap_resp_len; | |
| 3899 | − u8 unused_0; | |
| 3900 | − u8 unused_1; | |
| 3901 | − __le64 encap_resp_addr; | |
| 3902 | − __le32 encap_resp[24]; | |
| 3903 | −}; | |
| 3904 | − | |
| 3905 | −/* Output (16 bytes) */ | |
| 3906 | −struct hwrm_fwd_resp_output { | |
| 3907 | − __le16 error_code; | |
| 3908 | − __le16 req_type; | |
| 3909 | − __le16 seq_id; | |
| 3910 | − __le16 resp_len; | |
| 3911 | − __le32 unused_0; | |
| 3912 | − u8 unused_1; | |
| 3913 | − u8 unused_2; | |
| 3914 | − u8 unused_3; | |
| 3915 | − u8 valid; | |
| 3916 | −}; | |
| 3917 | − | |
| 3918 | −/* hwrm_fwd_async_event_cmpl */ | |
| 3919 | −/* Input (32 bytes) */ | |
| 3920 | −struct hwrm_fwd_async_event_cmpl_input { | |
| 3921 | − __le16 req_type; | |
| 3922 | − __le16 cmpl_ring; | |
| 3923 | − __le16 seq_id; | |
| 3924 | − __le16 target_id; | |
| 3925 | − __le64 resp_addr; | |
| 3926 | − __le16 encap_async_event_target_id; | |
| 3927 | − u8 unused_0; | |
| 3928 | − u8 unused_1; | |
| 3929 | − u8 unused_2[3]; | |
| 3930 | − u8 unused_3; | |
| 3931 | − __le32 encap_async_event_cmpl[4]; | |
| 3932 | −}; | |
| 3933 | − | |
| 3934 | −/* Output (16 bytes) */ | |
| 3935 | −struct hwrm_fwd_async_event_cmpl_output { | |
| 3936 | − __le16 error_code; | |
| 3937 | − __le16 req_type; | |
| 3938 | − __le16 seq_id; | |
| 3939 | − __le16 resp_len; | |
| 3940 | − __le32 unused_0; | |
| 3941 | − u8 unused_1; | |
| 3942 | − u8 unused_2; | |
| 3943 | − u8 unused_3; | |
| 3944 | − u8 valid; | |
| 3945 | −}; | |
| 3946 | − | |
| 3947 | −/* hwrm_fw_reset */ | |
| 3948 | −/* Input (24 bytes) */ | |
| 3949 | −struct hwrm_fw_reset_input { | |
| 3950 | − __le16 req_type; | |
| 3951 | − __le16 cmpl_ring; | |
| 3952 | − __le16 seq_id; | |
| 3953 | − __le16 target_id; | |
| 3954 | − __le64 resp_addr; | |
| 3955 | − u8 embedded_proc_type; | |
| 3956 | − #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIMP (0x0UL << 0) | |
| 3957 | − #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_APE (0x1UL << 0) | |
| 3958 | − #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_KONG (0x2UL << 0) | |
| 3959 | − #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BONO (0x3UL << 0) | |
| 3960 | − #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_TANG (0x4UL << 0) | |
| 3961 | − u8 selfrst_status; | |
| 3962 | − #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) | |
| 3963 | − #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) | |
| 3964 | − #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) | |
| 3965 | − __le16 unused_0[3]; | |
| 3966 | −}; | |
| 3967 | − | |
| 3968 | −/* Output (16 bytes) */ | |
| 3969 | −struct hwrm_fw_reset_output { | |
| 3970 | − __le16 error_code; | |
| 3971 | − __le16 req_type; | |
| 3972 | − __le16 seq_id; | |
| 3973 | − __le16 resp_len; | |
| 3974 | − u8 selfrst_status; | |
| 3975 | − #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) | |
| 3976 | − #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) | |
| 3977 | − #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) | |
| 3978 | − u8 unused_0; | |
| 3979 | − __le16 unused_1; | |
| 3980 | − u8 unused_2; | |
| 3981 | − u8 unused_3; | |
| 3982 | − u8 unused_4; | |
| 3983 | − u8 valid; | |
| 3984 | −}; | |
| 3985 | − | |
| 3986 | −/* hwrm_fw_qstatus */ | |
| 3987 | −/* Input (24 bytes) */ | |
| 3988 | −struct hwrm_fw_qstatus_input { | |
| 3989 | − __le16 req_type; | |
| 3990 | − __le16 cmpl_ring; | |
| 3991 | − __le16 seq_id; | |
| 3992 | − __le16 target_id; | |
| 3993 | − __le64 resp_addr; | |
| 3994 | − u8 embedded_proc_type; | |
| 3995 | − #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIMP (0x0UL << 0) | |
| 3996 | − #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_APE (0x1UL << 0) | |
| 3997 | − #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_KONG (0x2UL << 0) | |
| 3998 | − #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BONO (0x3UL << 0) | |
| 3999 | − #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_TANG (0x4UL << 0) | |
| 4000 | − u8 unused_0[7]; | |
| 4001 | −}; | |
| 4002 | − | |
| 4003 | −/* Output (16 bytes) */ | |
| 4004 | −struct hwrm_fw_qstatus_output { | |
| 4005 | − __le16 error_code; | |
| 4006 | − __le16 req_type; | |
| 4007 | − __le16 seq_id; | |
| 4008 | − __le16 resp_len; | |
| 4009 | − u8 selfrst_status; | |
| 4010 | − #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) | |
| 4011 | − #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) | |
| 4012 | − #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) | |
| 4013 | − u8 unused_0; | |
| 4014 | − __le16 unused_1; | |
| 4015 | − u8 unused_2; | |
| 4016 | − u8 unused_3; | |
| 4017 | − u8 unused_4; | |
| 4018 | − u8 valid; | |
| 4019 | −}; | |
| 4020 | − | |
| 4021 | −/* hwrm_temp_monitor_query */ | |
| 4022 | −/* Input (16 bytes) */ | |
| 4023 | −struct hwrm_temp_monitor_query_input { | |
| 4024 | − __le16 req_type; | |
| 4025 | − __le16 cmpl_ring; | |
| 4026 | − __le16 seq_id; | |
| 4027 | − __le16 target_id; | |
| 4028 | − __le64 resp_addr; | |
| 4029 | −}; | |
| 4030 | − | |
| 4031 | −/* Output (16 bytes) */ | |
| 4032 | −struct hwrm_temp_monitor_query_output { | |
| 4033 | − __le16 error_code; | |
| 4034 | − __le16 req_type; | |
| 4035 | − __le16 seq_id; | |
| 4036 | − __le16 resp_len; | |
| 4037 | − u8 temp; | |
| 4038 | − u8 unused_0; | |
| 4039 | − __le16 unused_1; | |
| 4040 | − u8 unused_2; | |
| 4041 | − u8 unused_3; | |
| 4042 | − u8 unused_4; | |
| 4043 | − u8 valid; | |
| 4044 | −}; | |
| 4045 | − | |
| 4046 | 3821 | #endif |
| @@ -64,7 +64,7 @@ int bnxt_set_vf_spoofchk(struct net_device *dev, int vf_id, bool setting) · 63 unmodified lines | ||
| 64 | 64 | * the spoof check should also include vlan anti-spoofing |
| 65 | 65 | */ |
| 66 | 66 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); |
| 67 | − req.vf_id = cpu_to_le16(vf->fw_fid); | |
| 67 | + req.fid = cpu_to_le16(vf->fw_fid); | |
| 68 | 68 | req.flags = cpu_to_le32(func_flags); |
| 69 | 69 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 70 | 70 | if (!rc) { |
| @@ -128,7 +128,7 @@ int bnxt_set_vf_mac(struct net_device *dev, int vf_id, u8 *mac) · 57 unmodified lines | ||
| 128 | 128 | |
| 129 | 129 | memcpy(vf->mac_addr, mac, ETH_ALEN); |
| 130 | 130 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); |
| 131 | − req.vf_id = cpu_to_le16(vf->fw_fid); | |
| 131 | + req.fid = cpu_to_le16(vf->fw_fid); | |
| 132 | 132 | req.flags = cpu_to_le32(vf->func_flags); |
| 133 | 133 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR); |
| 134 | 134 | memcpy(req.dflt_mac_addr, mac, ETH_ALEN); |
| @@ -159,7 +159,7 @@ int bnxt_set_vf_vlan(struct net_device *dev, int vf_id, u16 vlan_id, u8 qos) · 24 unmodified lines | ||
| 159 | 159 | return 0; |
| 160 | 160 | |
| 161 | 161 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); |
| 162 | − req.vf_id = cpu_to_le16(vf->fw_fid); | |
| 162 | + req.fid = cpu_to_le16(vf->fw_fid); | |
| 163 | 163 | req.flags = cpu_to_le32(vf->func_flags); |
| 164 | 164 | req.dflt_vlan = cpu_to_le16(vlan_tag); |
| 165 | 165 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_DFLT_VLAN); |
| @@ -198,7 +198,7 @@ int bnxt_set_vf_bw(struct net_device *dev, int vf_id, int min_tx_rate, · 32 unmodified lines | ||
| 198 | 198 | if (min_tx_rate == vf->min_tx_rate && max_tx_rate == vf->max_tx_rate) |
| 199 | 199 | return 0; |
| 200 | 200 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); |
| 201 | − req.vf_id = cpu_to_le16(vf->fw_fid); | |
| 201 | + req.fid = cpu_to_le16(vf->fw_fid); | |
| 202 | 202 | req.flags = cpu_to_le32(vf->func_flags); |
| 203 | 203 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_MAX_BW); |
| 204 | 204 | req.max_bw = cpu_to_le32(max_tx_rate); |
| @@ -363,10 +363,11 @@ static int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp) · 158 unmodified lines | ||
| 363 | 363 | } |
| 364 | 364 | |
| 365 | 365 | /* only call by PF to reserve resources for VF */ |
| 366 | −static int bnxt_hwrm_func_cfg(struct bnxt *bp, int *num_vfs) | |
| 366 | +static int bnxt_hwrm_func_cfg(struct bnxt *bp, int num_vfs) | |
| 367 | 367 | { |
| 368 | 368 | u32 rc = 0, mtu, i; |
| 369 | 369 | u16 vf_tx_rings, vf_rx_rings, vf_cp_rings, vf_stat_ctx, vf_vnics; |
| 370 | + u16 vf_ring_grps; | |
| 370 | 371 | struct hwrm_func_cfg_input req = {0}; |
| 371 | 372 | struct bnxt_pf_info *pf = &bp->pf; |
| 372 | 373 | |
| @@ -378,18 +379,18 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int *num_vfs) · 5 unmodified lines | ||
| 378 | 379 | * be removed once new HWRM provides HW ring groups capability in |
| 379 | 380 | * hwrm_func_qcap. |
| 380 | 381 | */ |
| 381 | − vf_cp_rings = min_t(u16, bp->pf.max_cp_rings, bp->pf.max_stat_ctxs); | |
| 382 | − vf_cp_rings = (vf_cp_rings - bp->cp_nr_rings) / *num_vfs; | |
| 382 | + vf_cp_rings = min_t(u16, pf->max_cp_rings, pf->max_stat_ctxs); | |
| 383 | + vf_cp_rings = (vf_cp_rings - bp->cp_nr_rings) / num_vfs; | |
| 383 | 384 | /* TODO: restore this logic below once the WA above is removed */ |
| 384 | − /* vf_cp_rings = (bp->pf.max_cp_rings - bp->cp_nr_rings) / *num_vfs; */ | |
| 385 | − vf_stat_ctx = (bp->pf.max_stat_ctxs - bp->num_stat_ctxs) / *num_vfs; | |
| 385 | + /* vf_cp_rings = (pf->max_cp_rings - bp->cp_nr_rings) / num_vfs; */ | |
| 386 | + vf_stat_ctx = (pf->max_stat_ctxs - bp->num_stat_ctxs) / num_vfs; | |
| 386 | 387 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
| 387 | − vf_rx_rings = (bp->pf.max_rx_rings - bp->rx_nr_rings * 2) / | |
| 388 | − *num_vfs; | |
| 388 | + vf_rx_rings = (pf->max_rx_rings - bp->rx_nr_rings * 2) / | |
| 389 | + num_vfs; | |
| 389 | 390 | else |
| 390 | − vf_rx_rings = (bp->pf.max_rx_rings - bp->rx_nr_rings) / | |
| 391 | − *num_vfs; | |
| 392 | − vf_tx_rings = (bp->pf.max_tx_rings - bp->tx_nr_rings) / *num_vfs; | |
| 391 | + vf_rx_rings = (pf->max_rx_rings - bp->rx_nr_rings) / num_vfs; | |
| 392 | + vf_ring_grps = (bp->pf.max_hw_ring_grps - bp->rx_nr_rings) / num_vfs; | |
| 393 | + vf_tx_rings = (pf->max_tx_rings - bp->tx_nr_rings) / num_vfs; | |
| 393 | 394 | |
| 394 | 395 | req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_MTU | |
| 395 | 396 | FUNC_CFG_REQ_ENABLES_MRU | |
| @@ -399,7 +400,8 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int *num_vfs) · 3 unmodified lines | ||
| 399 | 400 | FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS | |
| 400 | 401 | FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS | |
| 401 | 402 | FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS | |
| 402 | − FUNC_CFG_REQ_ENABLES_NUM_VNICS); | |
| 403 | + FUNC_CFG_REQ_ENABLES_NUM_VNICS | | |
| 404 | + FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS); | |
| 403 | 405 | |
| 404 | 406 | mtu = bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
| 405 | 407 | req.mru = cpu_to_le16(mtu); |
| @@ -409,6 +411,7 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int *num_vfs) · 3 unmodified lines | ||
| 409 | 411 | req.num_cmpl_rings = cpu_to_le16(vf_cp_rings); |
| 410 | 412 | req.num_tx_rings = cpu_to_le16(vf_tx_rings); |
| 411 | 413 | req.num_rx_rings = cpu_to_le16(vf_rx_rings); |
| 414 | + req.num_hw_ring_grps = cpu_to_le16(vf_ring_grps); | |
| 412 | 415 | req.num_l2_ctxs = cpu_to_le16(4); |
| 413 | 416 | vf_vnics = 1; |
| 414 | 417 | |
| @@ -417,22 +420,24 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int *num_vfs) · 2 unmodified lines | ||
| 417 | 420 | req.num_stat_ctxs = cpu_to_le16(vf_stat_ctx); |
| 418 | 421 | |
| 419 | 422 | mutex_lock(&bp->hwrm_cmd_lock); |
| 420 | − for (i = 0; i < *num_vfs; i++) { | |
| 421 | − req.vf_id = cpu_to_le16(pf->first_vf_id + i); | |
| 423 | + for (i = 0; i < num_vfs; i++) { | |
| 424 | + req.fid = cpu_to_le16(pf->first_vf_id + i); | |
| 422 | 425 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 423 | 426 | HWRM_CMD_TIMEOUT); |
| 424 | 427 | if (rc) |
| 425 | 428 | break; |
| 426 | − bp->pf.active_vfs = i + 1; | |
| 427 | − bp->pf.vf[i].fw_fid = le16_to_cpu(req.vf_id); | |
| 429 | + pf->active_vfs = i + 1; | |
| 430 | + pf->vf[i].fw_fid = le16_to_cpu(req.fid); | |
| 428 | 431 | } |
| 429 | 432 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 430 | 433 | if (!rc) { |
| 431 | − bp->pf.max_pf_tx_rings = bp->tx_nr_rings; | |
| 432 | − if (bp->flags & BNXT_FLAG_AGG_RINGS) | |
| 433 | − bp->pf.max_pf_rx_rings = bp->rx_nr_rings * 2; | |
| 434 | − else | |
| 435 | − bp->pf.max_pf_rx_rings = bp->rx_nr_rings; | |
| 434 | + pf->max_tx_rings -= vf_tx_rings * num_vfs; | |
| 435 | + pf->max_rx_rings -= vf_rx_rings * num_vfs; | |
| 436 | + pf->max_hw_ring_grps -= vf_ring_grps * num_vfs; | |
| 437 | + pf->max_cp_rings -= vf_cp_rings * num_vfs; | |
| 438 | + pf->max_rsscos_ctxs -= num_vfs; | |
| 439 | + pf->max_stat_ctxs -= vf_stat_ctx * num_vfs; | |
| 440 | + pf->max_vnics -= vf_vnics * num_vfs; | |
| 436 | 441 | } |
| 437 | 442 | return rc; |
| 438 | 443 | } |
| @@ -492,7 +497,7 @@ static int bnxt_sriov_enable(struct bnxt *bp, int *num_vfs) · 53 unmodified lines | ||
| 492 | 497 | goto err_out1; |
| 493 | 498 | |
| 494 | 499 | /* Reserve resources for VFs */ |
| 495 | − rc = bnxt_hwrm_func_cfg(bp, num_vfs); | |
| 500 | + rc = bnxt_hwrm_func_cfg(bp, *num_vfs); | |
| 496 | 501 | if (rc) |
| 497 | 502 | goto err_out2; |
| 498 | 503 | |
| @@ -536,8 +541,8 @@ void bnxt_sriov_disable(struct bnxt *bp) · 37 unmodified lines | ||
| 536 | 541 | bnxt_free_vf_resources(bp); |
| 537 | 542 | |
| 538 | 543 | bp->pf.active_vfs = 0; |
| 539 | − bp->pf.max_pf_rx_rings = bp->pf.max_rx_rings; | |
| 540 | − bp->pf.max_pf_tx_rings = bp->pf.max_tx_rings; | |
| 544 | + /* Reclaim all resources for the PF. */ | |
| 545 | + bnxt_hwrm_func_qcaps(bp); | |
| 541 | 546 | } |
| 542 | 547 | |
| 543 | 548 | int bnxt_sriov_configure(struct pci_dev *pdev, int num_vfs) |
| @@ -595,6 +600,7 @@ static int bnxt_hwrm_fwd_resp(struct bnxt *bp, struct bnxt_vf_info *vf, · 51 unmodified lines | ||
| 595 | 600 | |
| 596 | 601 | /* Set the new target id */ |
| 597 | 602 | req.target_id = cpu_to_le16(vf->fw_fid); |
| 603 | + req.encap_resp_target_id = cpu_to_le16(vf->fw_fid); | |
| 598 | 604 | req.encap_resp_len = cpu_to_le16(msg_size); |
| 599 | 605 | req.encap_resp_addr = encap_resp_addr; |
| 600 | 606 | req.encap_resp_cmpl_ring = encap_resp_cpr; |
| @@ -629,6 +635,7 @@ static int bnxt_hwrm_fwd_err_resp(struct bnxt *bp, struct bnxt_vf_info *vf, · 28 unmodified lines | ||
| 629 | 635 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_REJECT_FWD_RESP, -1, -1); |
| 630 | 636 | /* Set the new target id */ |
| 631 | 637 | req.target_id = cpu_to_le16(vf->fw_fid); |
| 638 | + req.encap_resp_target_id = cpu_to_le16(vf->fw_fid); | |
| 632 | 639 | memcpy(req.encap_request, vf->hwrm_cmd_req_addr, msg_size); |
| 633 | 640 | |
| 634 | 641 | mutex_lock(&bp->hwrm_cmd_lock); |
| @@ -660,6 +667,7 @@ static int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, struct bnxt_vf_info *vf, · 25 unmodified lines | ||
| 660 | 667 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_EXEC_FWD_RESP, -1, -1); |
| 661 | 668 | /* Set the new target id */ |
| 662 | 669 | req.target_id = cpu_to_le16(vf->fw_fid); |
| 670 | + req.encap_resp_target_id = cpu_to_le16(vf->fw_fid); | |
| 663 | 671 | memcpy(req.encap_request, vf->hwrm_cmd_req_addr, msg_size); |
| 664 | 672 | |
| 665 | 673 | mutex_lock(&bp->hwrm_cmd_lock); |
| @@ -2041,11 +2041,11 @@ static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) · 2040 unmodified lines | ||
| 2041 | 2041 | |
| 2042 | 2042 | for (i = 0; i < priv->hw_params->tx_queues; ++i) { |
| 2043 | 2043 | ring = &priv->tx_rings[i]; |
| 2044 | − netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); | |
| 2044 | + netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); | |
| 2045 | 2045 | } |
| 2046 | 2046 | |
| 2047 | 2047 | ring = &priv->tx_rings[DESC_INDEX]; |
| 2048 | − netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); | |
| 2048 | + netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); | |
| 2049 | 2049 | } |
| 2050 | 2050 | |
| 2051 | 2051 | static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) |
| @@ -401,9 +401,7 @@ int bcmgenet_mii_probe(struct net_device *dev) · 400 unmodified lines | ||
| 401 | 401 | * Ethernet MAC ISRs |
| 402 | 402 | */ |
| 403 | 403 | if (priv->internal_phy) |
| 404 | − priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT; | |
| 405 | − else | |
| 406 | − priv->mii_bus->irq[phydev->addr] = PHY_POLL; | |
| 404 | + priv->mii_bus->irq[phydev->mdio.addr] = PHY_IGNORE_INTERRUPT; | |
| 407 | 405 | |
| 408 | 406 | return 0; |
| 409 | 407 | } |
| @@ -477,12 +475,6 @@ static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) · 67 unmodified lines | ||
| 477 | 475 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", |
| 478 | 476 | priv->pdev->name, priv->pdev->id); |
| 479 | 477 | |
| 480 | − bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); | |
| 481 | − if (!bus->irq) { | |
| 482 | − mdiobus_free(priv->mii_bus); | |
| 483 | − return -ENOMEM; | |
| 484 | − } | |
| 485 | − | |
| 486 | 478 | return 0; |
| 487 | 479 | } |
| 488 | 480 | |
| @@ -581,7 +573,7 @@ static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) · 92 unmodified lines | ||
| 581 | 573 | } |
| 582 | 574 | |
| 583 | 575 | if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) |
| 584 | − phydev = mdio->phy_map[pd->phy_address]; | |
| 576 | + phydev = mdiobus_get_phy(mdio, pd->phy_address); | |
| 585 | 577 | else |
| 586 | 578 | phydev = phy_find_first(mdio); |
| 587 | 579 | |
| @@ -648,7 +640,6 @@ int bcmgenet_mii_init(struct net_device *dev) · 60 unmodified lines | ||
| 648 | 640 | out: |
| 649 | 641 | of_node_put(priv->phy_dn); |
| 650 | 642 | mdiobus_unregister(priv->mii_bus); |
| 651 | − kfree(priv->mii_bus->irq); | |
| 652 | 643 | mdiobus_free(priv->mii_bus); |
| 653 | 644 | return ret; |
| 654 | 645 | } |
| @@ -659,6 +650,5 @@ void bcmgenet_mii_exit(struct net_device *dev) · 4 unmodified lines | ||
| 659 | 650 | |
| 660 | 651 | of_node_put(priv->phy_dn); |
| 661 | 652 | mdiobus_unregister(priv->mii_bus); |
| 662 | − kfree(priv->mii_bus->irq); | |
| 663 | 653 | mdiobus_free(priv->mii_bus); |
| 664 | 654 | } |
| @@ -238,7 +238,6 @@ struct sbmac_softc { · 237 unmodified lines | ||
| 238 | 238 | struct napi_struct napi; |
| 239 | 239 | struct phy_device *phy_dev; /* the associated PHY device */ |
| 240 | 240 | struct mii_bus *mii_bus; /* the MII bus */ |
| 241 | − int phy_irq[PHY_MAX_ADDR]; | |
| 242 | 241 | spinlock_t sbm_lock; /* spin lock */ |
| 243 | 242 | int sbm_devflags; /* current device flags */ |
| 244 | 243 | |
| @@ -2250,9 +2249,6 @@ static int sbmac_init(struct platform_device *pldev, long long base) · 2005 unmodified lines | ||
| 2250 | 2249 | sc->mii_bus->priv = sc; |
| 2251 | 2250 | sc->mii_bus->read = sbmac_mii_read; |
| 2252 | 2251 | sc->mii_bus->write = sbmac_mii_write; |
| 2253 | − sc->mii_bus->irq = sc->phy_irq; | |
| 2254 | − for (i = 0; i < PHY_MAX_ADDR; ++i) | |
| 2255 | − sc->mii_bus->irq[i] = SBMAC_PHY_INT; | |
| 2256 | 2252 | |
| 2257 | 2253 | sc->mii_bus->parent = &pldev->dev; |
| 2258 | 2254 | /* |
| @@ -2358,20 +2354,15 @@ static int sbmac_mii_probe(struct net_device *dev) · 99 unmodified lines | ||
| 2358 | 2354 | { |
| 2359 | 2355 | struct sbmac_softc *sc = netdev_priv(dev); |
| 2360 | 2356 | struct phy_device *phy_dev; |
| 2361 | − int i; | |
| 2362 | 2357 | |
| 2363 | − for (i = 0; i < PHY_MAX_ADDR; i++) { | |
| 2364 | − phy_dev = sc->mii_bus->phy_map[i]; | |
| 2365 | − if (phy_dev) | |
| 2366 | − break; | |
| 2367 | − } | |
| 2358 | + phy_dev = phy_find_first(sc->mii_bus); | |
| 2368 | 2359 | if (!phy_dev) { |
| 2369 | 2360 | printk(KERN_ERR "%s: no PHY found\n", dev->name); |
| 2370 | 2361 | return -ENXIO; |
| 2371 | 2362 | } |
| 2372 | 2363 | |
| 2373 | − phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll, | |
| 2374 | − PHY_INTERFACE_MODE_GMII); | |
| 2364 | + phy_dev = phy_connect(dev, dev_name(&phy_dev->mdio.dev), | |
| 2365 | + &sbmac_mii_poll, PHY_INTERFACE_MODE_GMII); | |
| 2375 | 2366 | if (IS_ERR(phy_dev)) { |
| 2376 | 2367 | printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); |
| 2377 | 2368 | return PTR_ERR(phy_dev); |
| @@ -2388,11 +2379,10 @@ static int sbmac_mii_probe(struct net_device *dev) · 10 unmodified lines | ||
| 2388 | 2379 | SUPPORTED_MII | |
| 2389 | 2380 | SUPPORTED_Pause | |
| 2390 | 2381 | SUPPORTED_Asym_Pause; |
| 2391 | − phy_dev->advertising = phy_dev->supported; | |
| 2392 | 2382 | |
| 2393 | − pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
| 2394 | − dev->name, phy_dev->drv->name, | |
| 2395 | − dev_name(&phy_dev->dev), phy_dev->irq); | |
| 2383 | + phy_attached_info(phy_dev); | |
| 2384 | + | |
| 2385 | + phy_dev->advertising = phy_dev->supported; | |
| 2396 | 2386 | |
| 2397 | 2387 | sc->phy_dev = phy_dev; |
| 2398 | 2388 | |
| @@ -1406,7 +1406,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp) · 1405 unmodified lines | ||
| 1406 | 1406 | u32 val; |
| 1407 | 1407 | struct phy_device *phydev; |
| 1408 | 1408 | |
| 1409 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 1409 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 1410 | 1410 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
| 1411 | 1411 | case PHY_ID_BCM50610: |
| 1412 | 1412 | case PHY_ID_BCM50610M: |
| @@ -1538,10 +1538,6 @@ static int tg3_mdio_init(struct tg3 *tp) · 125 unmodified lines | ||
| 1538 | 1538 | tp->mdio_bus->read = &tg3_mdio_read; |
| 1539 | 1539 | tp->mdio_bus->write = &tg3_mdio_write; |
| 1540 | 1540 | tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); |
| 1541 | − tp->mdio_bus->irq = &tp->mdio_irq[0]; | |
| 1542 | − | |
| 1543 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 1544 | − tp->mdio_bus->irq[i] = PHY_POLL; | |
| 1545 | 1541 | |
| 1546 | 1542 | /* The bus registration will look for all the PHYs on the mdio bus. |
| 1547 | 1543 | * Unfortunately, it does not ensure the PHY is powered up before |
| @@ -1558,7 +1554,7 @@ static int tg3_mdio_init(struct tg3 *tp) · 10 unmodified lines | ||
| 1558 | 1554 | return i; |
| 1559 | 1555 | } |
| 1560 | 1556 | |
| 1561 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 1557 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 1562 | 1558 | |
| 1563 | 1559 | if (!phydev || !phydev->drv) { |
| 1564 | 1560 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
| @@ -1968,7 +1964,7 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) · 403 unmodified lines | ||
| 1968 | 1964 | u32 old_tx_mode = tp->tx_mode; |
| 1969 | 1965 | |
| 1970 | 1966 | if (tg3_flag(tp, USE_PHYLIB)) |
| 1971 | − autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg; | |
| 1967 | + autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; | |
| 1972 | 1968 | else |
| 1973 | 1969 | autoneg = tp->link_config.autoneg; |
| 1974 | 1970 | |
| @@ -2004,7 +2000,7 @@ static void tg3_adjust_link(struct net_device *dev) · 29 unmodified lines | ||
| 2004 | 2000 | u8 oldflowctrl, linkmesg = 0; |
| 2005 | 2001 | u32 mac_mode, lcl_adv, rmt_adv; |
| 2006 | 2002 | struct tg3 *tp = netdev_priv(dev); |
| 2007 | − struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 2003 | + struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 2008 | 2004 | |
| 2009 | 2005 | spin_lock_bh(&tp->lock); |
| 2010 | 2006 | |
| @@ -2093,10 +2089,10 @@ static int tg3_phy_init(struct tg3 *tp) · 82 unmodified lines | ||
| 2093 | 2089 | /* Bring the PHY back to a known state. */ |
| 2094 | 2090 | tg3_bmcr_reset(tp); |
| 2095 | 2091 | |
| 2096 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 2092 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 2097 | 2093 | |
| 2098 | 2094 | /* Attach the MAC to the PHY. */ |
| 2099 | − phydev = phy_connect(tp->dev, dev_name(&phydev->dev), | |
| 2095 | + phydev = phy_connect(tp->dev, phydev_name(phydev), | |
| 2100 | 2096 | tg3_adjust_link, phydev->interface); |
| 2101 | 2097 | if (IS_ERR(phydev)) { |
| 2102 | 2098 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
| @@ -2120,7 +2116,7 @@ static int tg3_phy_init(struct tg3 *tp) · 17 unmodified lines | ||
| 2120 | 2116 | SUPPORTED_Asym_Pause); |
| 2121 | 2117 | break; |
| 2122 | 2118 | default: |
| 2123 | − phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]); | |
| 2119 | + phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); | |
| 2124 | 2120 | return -EINVAL; |
| 2125 | 2121 | } |
| 2126 | 2122 | |
| @@ -2128,6 +2124,8 @@ static int tg3_phy_init(struct tg3 *tp) · 1 unmodified line | ||
| 2128 | 2124 | |
| 2129 | 2125 | phydev->advertising = phydev->supported; |
| 2130 | 2126 | |
| 2127 | + phy_attached_info(phydev); | |
| 2128 | + | |
| 2131 | 2129 | return 0; |
| 2132 | 2130 | } |
| 2133 | 2131 | |
| @@ -2138,7 +2136,7 @@ static void tg3_phy_start(struct tg3 *tp) · 4 unmodified lines | ||
| 2138 | 2136 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 2139 | 2137 | return; |
| 2140 | 2138 | |
| 2141 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 2139 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 2142 | 2140 | |
| 2143 | 2141 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
| 2144 | 2142 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
| @@ -2158,13 +2156,13 @@ static void tg3_phy_stop(struct tg3 *tp) · 13 unmodified lines | ||
| 2158 | 2156 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 2159 | 2157 | return; |
| 2160 | 2158 | |
| 2161 | − phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]); | |
| 2159 | + phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); | |
| 2162 | 2160 | } |
| 2163 | 2161 | |
| 2164 | 2162 | static void tg3_phy_fini(struct tg3 *tp) |
| 2165 | 2163 | { |
| 2166 | 2164 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
| 2167 | − phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]); | |
| 2165 | + phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); | |
| 2168 | 2166 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
| 2169 | 2167 | } |
| 2170 | 2168 | } |
| @@ -4048,7 +4046,7 @@ static int tg3_power_down_prepare(struct tg3 *tp) · 1877 unmodified lines | ||
| 4048 | 4046 | struct phy_device *phydev; |
| 4049 | 4047 | u32 phyid, advertising; |
| 4050 | 4048 | |
| 4051 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 4049 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 4052 | 4050 | |
| 4053 | 4051 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
| 4054 | 4052 | |
| @@ -12076,7 +12074,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) · 8021 unmodified lines | ||
| 12076 | 12074 | struct phy_device *phydev; |
| 12077 | 12075 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 12078 | 12076 | return -EAGAIN; |
| 12079 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 12077 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 12080 | 12078 | return phy_ethtool_gset(phydev, cmd); |
| 12081 | 12079 | } |
| 12082 | 12080 | |
| @@ -12143,7 +12141,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) · 60 unmodified lines | ||
| 12143 | 12141 | struct phy_device *phydev; |
| 12144 | 12142 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 12145 | 12143 | return -EAGAIN; |
| 12146 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 12144 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 12147 | 12145 | return phy_ethtool_sset(phydev, cmd); |
| 12148 | 12146 | } |
| 12149 | 12147 | |
| @@ -12298,7 +12296,7 @@ static int tg3_nway_reset(struct net_device *dev) · 148 unmodified lines | ||
| 12298 | 12296 | if (tg3_flag(tp, USE_PHYLIB)) { |
| 12299 | 12297 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 12300 | 12298 | return -EAGAIN; |
| 12301 | − r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]); | |
| 12299 | + r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); | |
| 12302 | 12300 | } else { |
| 12303 | 12301 | u32 bmcr; |
| 12304 | 12302 | |
| @@ -12416,7 +12414,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam · 111 unmodified lines | ||
| 12416 | 12414 | u32 newadv; |
| 12417 | 12415 | struct phy_device *phydev; |
| 12418 | 12416 | |
| 12419 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 12417 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 12420 | 12418 | |
| 12421 | 12419 | if (!(phydev->supported & SUPPORTED_Pause) || |
| 12422 | 12420 | (!(phydev->supported & SUPPORTED_Asym_Pause) && |
| @@ -13926,7 +13924,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) · 1503 unmodified lines | ||
| 13926 | 13924 | struct phy_device *phydev; |
| 13927 | 13925 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 13928 | 13926 | return -EAGAIN; |
| 13929 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 13927 | + phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); | |
| 13930 | 13928 | return phy_mii_ioctl(phydev, ifr, cmd); |
| 13931 | 13929 | } |
| 13932 | 13930 | |
| @@ -17898,13 +17896,7 @@ static int tg3_init_one(struct pci_dev *pdev, · 3965 unmodified lines | ||
| 17898 | 17896 | tg3_bus_string(tp, str), |
| 17899 | 17897 | dev->dev_addr); |
| 17900 | 17898 | |
| 17901 | − if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { | |
| 17902 | − struct phy_device *phydev; | |
| 17903 | − phydev = tp->mdio_bus->phy_map[tp->phy_addr]; | |
| 17904 | − netdev_info(dev, | |
| 17905 | − "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
| 17906 | − phydev->drv->name, dev_name(&phydev->dev)); | |
| 17907 | − } else { | |
| 17899 | + if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { | |
| 17908 | 17900 | char *ethtype; |
| 17909 | 17901 | |
| 17910 | 17902 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
| @@ -3254,7 +3254,6 @@ struct tg3 { · 3253 unmodified lines | ||
| 3254 | 3254 | int pcie_readrq; |
| 3255 | 3255 | |
| 3256 | 3256 | struct mii_bus *mdio_bus; |
| 3257 | − int mdio_irq[PHY_MAX_ADDR]; | |
| 3258 | 3257 | int old_link; |
| 3259 | 3258 | |
| 3260 | 3259 | u8 phy_addr; |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | #include <linux/init.h> |
| 20 | 20 | #include <linux/io.h> |
| 21 | 21 | #include <linux/gpio.h> |
| 22 | +#include <linux/gpio/consumer.h> | |
| 22 | 23 | #include <linux/interrupt.h> |
| 23 | 24 | #include <linux/netdevice.h> |
| 24 | 25 | #include <linux/etherdevice.h> |
| @@ -28,6 +29,7 @@ · 3 unmodified lines | ||
| 28 | 29 | #include <linux/phy.h> |
| 29 | 30 | #include <linux/of.h> |
| 30 | 31 | #include <linux/of_device.h> |
| 32 | +#include <linux/of_gpio.h> | |
| 31 | 33 | #include <linux/of_mdio.h> |
| 32 | 34 | #include <linux/of_net.h> |
| 33 | 35 | |
| @@ -439,12 +441,6 @@ static int macb_mii_init(struct macb *bp) · 405 unmodified lines | ||
| 439 | 441 | bp->mii_bus->parent = &bp->dev->dev; |
| 440 | 442 | pdata = dev_get_platdata(&bp->pdev->dev); |
| 441 | 443 | |
| 442 | − bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
| 443 | − if (!bp->mii_bus->irq) { | |
| 444 | − err = -ENOMEM; | |
| 445 | − goto err_out_free_mdiobus; | |
| 446 | − } | |
| 447 | − | |
| 448 | 444 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
| 449 | 445 | |
| 450 | 446 | np = bp->pdev->dev.of_node; |
| @@ -469,9 +465,6 @@ static int macb_mii_init(struct macb *bp) · 18 unmodified lines | ||
| 469 | 465 | goto err_out_unregister_bus; |
| 470 | 466 | } |
| 471 | 467 | } else { |
| 472 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 473 | − bp->mii_bus->irq[i] = PHY_POLL; | |
| 474 | − | |
| 475 | 468 | if (pdata) |
| 476 | 469 | bp->mii_bus->phy_mask = pdata->phy_mask; |
| 477 | 470 | |
| @@ -479,7 +472,7 @@ static int macb_mii_init(struct macb *bp) · 1 unmodified line | ||
| 479 | 472 | } |
| 480 | 473 | |
| 481 | 474 | if (err) |
| 482 | − goto err_out_free_mdio_irq; | |
| 475 | + goto err_out_free_mdiobus; | |
| 483 | 476 | |
| 484 | 477 | err = macb_mii_probe(bp->dev); |
| 485 | 478 | if (err) |
| @@ -489,8 +482,6 @@ static int macb_mii_init(struct macb *bp) · 3 unmodified lines | ||
| 489 | 482 | |
| 490 | 483 | err_out_unregister_bus: |
| 491 | 484 | mdiobus_unregister(bp->mii_bus); |
| 492 | −err_out_free_mdio_irq: | |
| 493 | − kfree(bp->mii_bus->irq); | |
| 494 | 485 | err_out_free_mdiobus: |
| 495 | 486 | mdiobus_free(bp->mii_bus); |
| 496 | 487 | err_out: |
| @@ -2122,7 +2113,8 @@ static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, · 1625 unmodified lines | ||
| 2122 | 2113 | regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); |
| 2123 | 2114 | regs_buff[11] = macb_tx_dma(&bp->queues[0], head); |
| 2124 | 2115 | |
| 2125 | − regs_buff[12] = macb_or_gem_readl(bp, USRIO); | |
| 2116 | + if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) | |
| 2117 | + regs_buff[12] = macb_or_gem_readl(bp, USRIO); | |
| 2126 | 2118 | if (macb_is_gem(bp)) { |
| 2127 | 2119 | regs_buff[13] = gem_readl(bp, DMACFG); |
| 2128 | 2120 | } |
| @@ -2401,19 +2393,21 @@ static int macb_init(struct platform_device *pdev) · 272 unmodified lines | ||
| 2401 | 2393 | dev->hw_features &= ~NETIF_F_SG; |
| 2402 | 2394 | dev->features = dev->hw_features; |
| 2403 | 2395 | |
| 2404 | − val = 0; | |
| 2405 | − if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
| 2406 | − val = GEM_BIT(RGMII); | |
| 2407 | − else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && | |
| 2408 | − (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII)) | |
| 2409 | − val = MACB_BIT(RMII); | |
| 2410 | − else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII)) | |
| 2411 | − val = MACB_BIT(MII); | |
| 2396 | + if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { | |
| 2397 | + val = 0; | |
| 2398 | + if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
| 2399 | + val = GEM_BIT(RGMII); | |
| 2400 | + else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && | |
| 2401 | + (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII)) | |
| 2402 | + val = MACB_BIT(RMII); | |
| 2403 | + else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII)) | |
| 2404 | + val = MACB_BIT(MII); | |
| 2412 | 2405 | |
| 2413 | − if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) | |
| 2414 | − val |= MACB_BIT(CLKEN); | |
| 2406 | + if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) | |
| 2407 | + val |= MACB_BIT(CLKEN); | |
| 2415 | 2408 | |
| 2416 | − macb_or_gem_writel(bp, USRIO, val); | |
| 2409 | + macb_or_gem_writel(bp, USRIO, val); | |
| 2410 | + } | |
| 2417 | 2411 | |
| 2418 | 2412 | /* Set MII management clock divider */ |
| 2419 | 2413 | val = macb_mdc_clk_div(bp); |
| @@ -2776,6 +2770,11 @@ static const struct macb_config emac_config = { · 356 unmodified lines | ||
| 2776 | 2770 | .init = at91ether_init, |
| 2777 | 2771 | }; |
| 2778 | 2772 | |
| 2773 | +static const struct macb_config np4_config = { | |
| 2774 | + .caps = MACB_CAPS_USRIO_DISABLED, | |
| 2775 | + .clk_init = macb_clk_init, | |
| 2776 | + .init = macb_init, | |
| 2777 | +}; | |
| 2779 | 2778 | |
| 2780 | 2779 | static const struct macb_config zynqmp_config = { |
| 2781 | 2780 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO, |
| @@ -2796,6 +2795,7 @@ static const struct of_device_id macb_dt_ids[] = { · 14 unmodified lines | ||
| 2796 | 2795 | { .compatible = "cdns,at32ap7000-macb" }, |
| 2797 | 2796 | { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, |
| 2798 | 2797 | { .compatible = "cdns,macb" }, |
| 2798 | + { .compatible = "cdns,np4-macb", .data = &np4_config }, | |
| 2799 | 2799 | { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, |
| 2800 | 2800 | { .compatible = "cdns,gem", .data = &pc302gem_config }, |
| 2801 | 2801 | { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config }, |
| @@ -2817,6 +2817,7 @@ static int macb_probe(struct platform_device *pdev) · 15 unmodified lines | ||
| 2817 | 2817 | = macb_clk_init; |
| 2818 | 2818 | int (*init)(struct platform_device *) = macb_init; |
| 2819 | 2819 | struct device_node *np = pdev->dev.of_node; |
| 2820 | + struct device_node *phy_node; | |
| 2820 | 2821 | const struct macb_config *macb_config = NULL; |
| 2821 | 2822 | struct clk *pclk, *hclk, *tx_clk; |
| 2822 | 2823 | unsigned int queue_mask, num_queues; |
| @@ -2904,6 +2905,16 @@ static int macb_probe(struct platform_device *pdev) · 81 unmodified lines | ||
| 2904 | 2905 | else |
| 2905 | 2906 | macb_get_hwaddr(bp); |
| 2906 | 2907 | |
| 2908 | + /* Power up the PHY if there is a GPIO reset */ | |
| 2909 | + phy_node = of_get_next_available_child(np, NULL); | |
| 2910 | + if (phy_node) { | |
| 2911 | + int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0); | |
| 2912 | + if (gpio_is_valid(gpio)) | |
| 2913 | + bp->reset_gpio = gpio_to_desc(gpio); | |
| 2914 | + gpiod_set_value(bp->reset_gpio, GPIOD_OUT_HIGH); | |
| 2915 | + } | |
| 2916 | + of_node_put(phy_node); | |
| 2917 | + | |
| 2907 | 2918 | err = of_get_phy_mode(np); |
| 2908 | 2919 | if (err < 0) { |
| 2909 | 2920 | pdata = dev_get_platdata(&pdev->dev); |
| @@ -2937,8 +2948,7 @@ static int macb_probe(struct platform_device *pdev) · 27 unmodified lines | ||
| 2937 | 2948 | dev->base_addr, dev->irq, dev->dev_addr); |
| 2938 | 2949 | |
| 2939 | 2950 | phydev = bp->phy_dev; |
| 2940 | − netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
| 2941 | − phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
| 2951 | + phy_attached_info(phydev); | |
| 2942 | 2952 | |
| 2943 | 2953 | return 0; |
| 2944 | 2954 | |
| @@ -2968,8 +2978,11 @@ static int macb_remove(struct platform_device *pdev) · 23 unmodified lines | ||
| 2968 | 2978 | if (bp->phy_dev) |
| 2969 | 2979 | phy_disconnect(bp->phy_dev); |
| 2970 | 2980 | mdiobus_unregister(bp->mii_bus); |
| 2971 | − kfree(bp->mii_bus->irq); | |
| 2972 | 2981 | mdiobus_free(bp->mii_bus); |
| 2982 | + | |
| 2983 | + /* Shutdown the PHY if there is a GPIO reset */ | |
| 2984 | + gpiod_set_value(bp->reset_gpio, GPIOD_OUT_LOW); | |
| 2985 | + | |
| 2973 | 2986 | unregister_netdev(dev); |
| 2974 | 2987 | clk_disable_unprepare(bp->tx_clk); |
| 2975 | 2988 | clk_disable_unprepare(bp->hclk); |
| @@ -400,6 +400,7 @@ · 399 unmodified lines | ||
| 400 | 400 | #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 |
| 401 | 401 | #define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x00000004 |
| 402 | 402 | #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 |
| 403 | +#define MACB_CAPS_USRIO_DISABLED 0x00000010 | |
| 403 | 404 | #define MACB_CAPS_FIFO_MODE 0x10000000 |
| 404 | 405 | #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 |
| 405 | 406 | #define MACB_CAPS_SG_DISABLED 0x40000000 |
| @@ -829,6 +830,7 @@ struct macb { · 423 unmodified lines | ||
| 829 | 830 | unsigned int dma_burst_length; |
| 830 | 831 | |
| 831 | 832 | phy_interface_t phy_interface; |
| 833 | + struct gpio_desc *reset_gpio; | |
| 832 | 834 | |
| 833 | 835 | /* AT91RM9200 transmit */ |
| 834 | 836 | struct sk_buff *skb; /* holds skb until xmit interrupt completes */ |
| @@ -265,6 +265,7 @@ struct nicvf { · 264 unmodified lines | ||
| 265 | 265 | u8 tns_mode:1; |
| 266 | 266 | u8 sqs_mode:1; |
| 267 | 267 | u8 loopback_supported:1; |
| 268 | + bool hw_tso; | |
| 268 | 269 | u16 mtu; |
| 269 | 270 | struct queue_set *qs; |
| 270 | 271 | #define MAX_SQS_PER_VF_SINGLE_NODE 5 |
| @@ -489,6 +490,11 @@ static inline int nic_get_node_id(struct pci_dev *pdev) · 218 unmodified lines | ||
| 489 | 490 | return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); |
| 490 | 491 | } |
| 491 | 492 | |
| 493 | +static inline bool pass1_silicon(struct pci_dev *pdev) | |
| 494 | +{ | |
| 495 | + return pdev->revision < 8; | |
| 496 | +} | |
| 497 | + | |
| 492 | 498 | int nicvf_set_real_num_queues(struct net_device *netdev, |
| 493 | 499 | int tx_queues, int rx_queues); |
| 494 | 500 | int nicvf_open(struct net_device *netdev); |
| @@ -54,11 +54,6 @@ struct nicpf { · 53 unmodified lines | ||
| 54 | 54 | bool irq_allocated[NIC_PF_MSIX_VECTORS]; |
| 55 | 55 | }; |
| 56 | 56 | |
| 57 | −static inline bool pass1_silicon(struct nicpf *nic) | |
| 58 | −{ | |
| 59 | − return nic->pdev->revision < 8; | |
| 60 | −} | |
| 61 | − | |
| 62 | 57 | /* Supported devices */ |
| 63 | 58 | static const struct pci_device_id nic_id_table[] = { |
| 64 | 59 | { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) }, |
| @@ -122,7 +117,7 @@ static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) · 57 unmodified lines | ||
| 122 | 117 | * when PF writes to MBOX(1), in next revisions when |
| 123 | 118 | * PF writes to MBOX(0) |
| 124 | 119 | */ |
| 125 | − if (pass1_silicon(nic)) { | |
| 120 | + if (pass1_silicon(nic->pdev)) { | |
| 126 | 121 | /* see the comment for nic_reg_write()/nic_reg_read() |
| 127 | 122 | * functions above |
| 128 | 123 | */ |
| @@ -397,7 +392,7 @@ static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) · 268 unmodified lines | ||
| 397 | 392 | padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ |
| 398 | 393 | |
| 399 | 394 | /* Leave RSS_SIZE as '0' to disable RSS */ |
| 400 | − if (pass1_silicon(nic)) { | |
| 395 | + if (pass1_silicon(nic->pdev)) { | |
| 401 | 396 | nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), |
| 402 | 397 | (vnic << 24) | (padd << 16) | |
| 403 | 398 | (rssi_base + rssi)); |
| @@ -467,7 +462,7 @@ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) · 63 unmodified lines | ||
| 467 | 462 | } |
| 468 | 463 | |
| 469 | 464 | cpi_base = nic->cpi_base[cfg->vf_id]; |
| 470 | − if (pass1_silicon(nic)) | |
| 465 | + if (pass1_silicon(nic->pdev)) | |
| 471 | 466 | idx_addr = NIC_PF_CPI_0_2047_CFG; |
| 472 | 467 | else |
| 473 | 468 | idx_addr = NIC_PF_MPI_0_2047_CFG; |
| @@ -525,14 +525,22 @@ static void nicvf_snd_pkt_handler(struct net_device *netdev, · 524 unmodified lines | ||
| 525 | 525 | __func__, cqe_tx->sq_qs, cqe_tx->sq_idx, |
| 526 | 526 | cqe_tx->sqe_ptr, hdr->subdesc_cnt); |
| 527 | 527 | |
| 528 | − nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); | |
| 529 | 528 | nicvf_check_cqe_tx_errs(nic, cq, cqe_tx); |
| 530 | 529 | skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr]; |
| 531 | − /* For TSO offloaded packets only one head SKB needs to be freed */ | |
| 530 | + /* For TSO offloaded packets only one SQE will have a valid SKB */ | |
| 532 | 531 | if (skb) { |
| 532 | + nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); | |
| 533 | 533 | prefetch(skb); |
| 534 | 534 | dev_consume_skb_any(skb); |
| 535 | 535 | sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL; |
| 536 | + } else { | |
| 537 | + /* In case of HW TSO, HW sends a CQE for each segment of a TSO | |
| 538 | + * packet instead of a single CQE for the whole TSO packet | |
| 539 | + * transmitted. Each of this CQE points to the same SQE, so | |
| 540 | + * avoid freeing same SQE multiple times. | |
| 541 | + */ | |
| 542 | + if (!nic->hw_tso) | |
| 543 | + nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); | |
| 536 | 544 | } |
| 537 | 545 | } |
| 538 | 546 | |
| @@ -1549,6 +1557,9 @@ static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 1010 unmodified lines | ||
| 1549 | 1557 | |
| 1550 | 1558 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
| 1551 | 1559 | |
| 1560 | + if (!pass1_silicon(nic->pdev)) | |
| 1561 | + nic->hw_tso = true; | |
| 1562 | + | |
| 1552 | 1563 | netdev->netdev_ops = &nicvf_netdev_ops; |
| 1553 | 1564 | netdev->watchdog_timeo = NICVF_TX_TIMEOUT; |
| 1554 | 1565 | |
| @@ -18,14 +18,6 @@ · 17 unmodified lines | ||
| 18 | 18 | #include "q_struct.h" |
| 19 | 19 | #include "nicvf_queues.h" |
| 20 | 20 | |
| 21 | −struct rbuf_info { | |
| 22 | − struct page *page; | |
| 23 | − void *data; | |
| 24 | − u64 offset; | |
| 25 | −}; | |
| 26 | − | |
| 27 | −#define GET_RBUF_INFO(x) ((struct rbuf_info *)(x - NICVF_RCV_BUF_ALIGN_BYTES)) | |
| 28 | − | |
| 29 | 21 | /* Poll a register for a specific value */ |
| 30 | 22 | static int nicvf_poll_reg(struct nicvf *nic, int qidx, |
| 31 | 23 | u64 reg, int bit_pos, int bits, int val) |
| @@ -86,8 +78,6 @@ static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem) · 54 unmodified lines | ||
| 86 | 78 | static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp, |
| 87 | 79 | u32 buf_len, u64 **rbuf) |
| 88 | 80 | { |
| 89 | − u64 data; | |
| 90 | − struct rbuf_info *rinfo; | |
| 91 | 81 | int order = get_order(buf_len); |
| 92 | 82 | |
| 93 | 83 | /* Check if request can be accomodated in previous allocated page */ |
| @@ -113,46 +103,28 @@ static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp, · 19 unmodified lines | ||
| 113 | 103 | nic->rb_page_offset = 0; |
| 114 | 104 | } |
| 115 | 105 | |
| 116 | − data = (u64)page_address(nic->rb_page) + nic->rb_page_offset; | |
| 117 | − | |
| 118 | − /* Align buffer addr to cache line i.e 128 bytes */ | |
| 119 | − rinfo = (struct rbuf_info *)(data + NICVF_RCV_BUF_ALIGN_LEN(data)); | |
| 120 | − /* Save page address for reference updation */ | |
| 121 | − rinfo->page = nic->rb_page; | |
| 122 | − /* Store start address for later retrieval */ | |
| 123 | − rinfo->data = (void *)data; | |
| 124 | − /* Store alignment offset */ | |
| 125 | − rinfo->offset = NICVF_RCV_BUF_ALIGN_LEN(data); | |
| 106 | + *rbuf = (u64 *)((u64)page_address(nic->rb_page) + nic->rb_page_offset); | |
| 126 | 107 | |
| 127 | − data += rinfo->offset; | |
| 128 | − | |
| 129 | − /* Give next aligned address to hw for DMA */ | |
| 130 | − *rbuf = (u64 *)(data + NICVF_RCV_BUF_ALIGN_BYTES); | |
| 131 | 108 | return 0; |
| 132 | 109 | } |
| 133 | 110 | |
| 134 | −/* Retrieve actual buffer start address and build skb for received packet */ | |
| 111 | +/* Build skb around receive buffer */ | |
| 135 | 112 | static struct sk_buff *nicvf_rb_ptr_to_skb(struct nicvf *nic, |
| 136 | 113 | u64 rb_ptr, int len) |
| 137 | 114 | { |
| 115 | + void *data; | |
| 138 | 116 | struct sk_buff *skb; |
| 139 | − struct rbuf_info *rinfo; | |
| 140 | 117 | |
| 141 | − rb_ptr = (u64)phys_to_virt(rb_ptr); | |
| 142 | − /* Get buffer start address and alignment offset */ | |
| 143 | − rinfo = GET_RBUF_INFO(rb_ptr); | |
| 118 | + data = phys_to_virt(rb_ptr); | |
| 144 | 119 | |
| 145 | 120 | /* Now build an skb to give to stack */ |
| 146 | − skb = build_skb(rinfo->data, RCV_FRAG_LEN); | |
| 121 | + skb = build_skb(data, RCV_FRAG_LEN); | |
| 147 | 122 | if (!skb) { |
| 148 | − put_page(rinfo->page); | |
| 123 | + put_page(virt_to_page(data)); | |
| 149 | 124 | return NULL; |
| 150 | 125 | } |
| 151 | 126 | |
| 152 | − /* Set correct skb->data */ | |
| 153 | − skb_reserve(skb, rinfo->offset + NICVF_RCV_BUF_ALIGN_BYTES); | |
| 154 | − | |
| 155 | − prefetch((void *)rb_ptr); | |
| 127 | + prefetch(skb->data); | |
| 156 | 128 | return skb; |
| 157 | 129 | } |
| 158 | 130 | |
| @@ -196,7 +168,6 @@ static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr) · 37 unmodified lines | ||
| 196 | 168 | int head, tail; |
| 197 | 169 | u64 buf_addr; |
| 198 | 170 | struct rbdr_entry_t *desc; |
| 199 | − struct rbuf_info *rinfo; | |
| 200 | 171 | |
| 201 | 172 | if (!rbdr) |
| 202 | 173 | return; |
| @@ -212,16 +183,14 @@ static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr) · 9 unmodified lines | ||
| 212 | 183 | while (head != tail) { |
| 213 | 184 | desc = GET_RBDR_DESC(rbdr, head); |
| 214 | 185 | buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN; |
| 215 | − rinfo = GET_RBUF_INFO((u64)phys_to_virt(buf_addr)); | |
| 216 | − put_page(rinfo->page); | |
| 186 | + put_page(virt_to_page(phys_to_virt(buf_addr))); | |
| 217 | 187 | head++; |
| 218 | 188 | head &= (rbdr->dmem.q_len - 1); |
| 219 | 189 | } |
| 220 | 190 | /* Free SKB of tail desc */ |
| 221 | 191 | desc = GET_RBDR_DESC(rbdr, tail); |
| 222 | 192 | buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN; |
| 223 | − rinfo = GET_RBUF_INFO((u64)phys_to_virt(buf_addr)); | |
| 224 | − put_page(rinfo->page); | |
| 193 | + put_page(virt_to_page(phys_to_virt(buf_addr))); | |
| 225 | 194 | |
| 226 | 195 | /* Free RBDR ring */ |
| 227 | 196 | nicvf_free_q_desc_mem(nic, &rbdr->dmem); |
| @@ -330,7 +299,7 @@ static int nicvf_init_cmp_queue(struct nicvf *nic, · 102 unmodified lines | ||
| 330 | 299 | return err; |
| 331 | 300 | |
| 332 | 301 | cq->desc = cq->dmem.base; |
| 333 | − cq->thresh = CMP_QUEUE_CQE_THRESH; | |
| 302 | + cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH; | |
| 334 | 303 | nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1; |
| 335 | 304 | |
| 336 | 305 | return 0; |
| @@ -956,7 +925,7 @@ static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb) · 619 unmodified lines | ||
| 956 | 925 | { |
| 957 | 926 | int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT; |
| 958 | 927 | |
| 959 | − if (skb_shinfo(skb)->gso_size) { | |
| 928 | + if (skb_shinfo(skb)->gso_size && !nic->hw_tso) { | |
| 960 | 929 | subdesc_cnt = nicvf_tso_count_subdescs(skb); |
| 961 | 930 | return subdesc_cnt; |
| 962 | 931 | } |
| @@ -971,7 +940,7 @@ static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb) · 8 unmodified lines | ||
| 971 | 940 | * First subdescriptor for every send descriptor. |
| 972 | 941 | */ |
| 973 | 942 | static inline void |
| 974 | −nicvf_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry, | |
| 943 | +nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry, | |
| 975 | 944 | int subdesc_cnt, struct sk_buff *skb, int len) |
| 976 | 945 | { |
| 977 | 946 | int proto; |
| @@ -1007,6 +976,15 @@ nicvf_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry, · 29 unmodified lines | ||
| 1007 | 976 | break; |
| 1008 | 977 | } |
| 1009 | 978 | } |
| 979 | + | |
| 980 | + if (nic->hw_tso && skb_shinfo(skb)->gso_size) { | |
| 981 | + hdr->tso = 1; | |
| 982 | + hdr->tso_start = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
| 983 | + hdr->tso_max_paysize = skb_shinfo(skb)->gso_size; | |
| 984 | + /* For non-tunneled pkts, point this to L2 ethertype */ | |
| 985 | + hdr->inner_l3_offset = skb_network_offset(skb) - 2; | |
| 986 | + nic->drv_stats.tx_tso++; | |
| 987 | + } | |
| 1010 | 988 | } |
| 1011 | 989 | |
| 1012 | 990 | /* SQ GATHER subdescriptor |
| @@ -1076,7 +1054,7 @@ static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq, · 63 unmodified lines | ||
| 1076 | 1054 | data_left -= size; |
| 1077 | 1055 | tso_build_data(skb, &tso, size); |
| 1078 | 1056 | } |
| 1079 | − nicvf_sq_add_hdr_subdesc(sq, hdr_qentry, | |
| 1057 | + nicvf_sq_add_hdr_subdesc(nic, sq, hdr_qentry, | |
| 1080 | 1058 | seg_subdescs - 1, skb, seg_len); |
| 1081 | 1059 | sq->skbuff[hdr_qentry] = (u64)NULL; |
| 1082 | 1060 | qentry = nicvf_get_nxt_sqentry(sq, qentry); |
| @@ -1129,11 +1107,12 @@ int nicvf_sq_append_skb(struct nicvf *nic, struct sk_buff *skb) · 46 unmodified lines | ||
| 1129 | 1107 | qentry = nicvf_get_sq_desc(sq, subdesc_cnt); |
| 1130 | 1108 | |
| 1131 | 1109 | /* Check if its a TSO packet */ |
| 1132 | − if (skb_shinfo(skb)->gso_size) | |
| 1110 | + if (skb_shinfo(skb)->gso_size && !nic->hw_tso) | |
| 1133 | 1111 | return nicvf_sq_append_tso(nic, sq, sq_num, qentry, skb); |
| 1134 | 1112 | |
| 1135 | 1113 | /* Add SQ header subdesc */ |
| 1136 | − nicvf_sq_add_hdr_subdesc(sq, qentry, subdesc_cnt - 1, skb, skb->len); | |
| 1114 | + nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1, | |
| 1115 | + skb, skb->len); | |
| 1137 | 1116 | |
| 1138 | 1117 | /* Add SQ gather subdescs */ |
| 1139 | 1118 | qentry = nicvf_get_nxt_sqentry(sq, qentry); |
| @@ -1234,153 +1213,93 @@ struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx) · 94 unmodified lines | ||
| 1234 | 1213 | return skb; |
| 1235 | 1214 | } |
| 1236 | 1215 | |
| 1237 | −/* Enable interrupt */ | |
| 1238 | −void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx) | |
| 1216 | +static u64 nicvf_int_type_to_mask(int int_type, int q_idx) | |
| 1239 | 1217 | { |
| 1240 | 1218 | u64 reg_val; |
| 1241 | 1219 | |
| 1242 | − reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); | |
| 1243 | − | |
| 1244 | 1220 | switch (int_type) { |
| 1245 | 1221 | case NICVF_INTR_CQ: |
| 1246 | − reg_val |= ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); | |
| 1222 | + reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); | |
| 1247 | 1223 | break; |
| 1248 | 1224 | case NICVF_INTR_SQ: |
| 1249 | − reg_val |= ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); | |
| 1225 | + reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); | |
| 1250 | 1226 | break; |
| 1251 | 1227 | case NICVF_INTR_RBDR: |
| 1252 | − reg_val |= ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); | |
| 1228 | + reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); | |
| 1253 | 1229 | break; |
| 1254 | 1230 | case NICVF_INTR_PKT_DROP: |
| 1255 | − reg_val |= (1ULL << NICVF_INTR_PKT_DROP_SHIFT); | |
| 1231 | + reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT); | |
| 1256 | 1232 | break; |
| 1257 | 1233 | case NICVF_INTR_TCP_TIMER: |
| 1258 | − reg_val |= (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); | |
| 1234 | + reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); | |
| 1259 | 1235 | break; |
| 1260 | 1236 | case NICVF_INTR_MBOX: |
| 1261 | − reg_val |= (1ULL << NICVF_INTR_MBOX_SHIFT); | |
| 1237 | + reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT); | |
| 1262 | 1238 | break; |
| 1263 | 1239 | case NICVF_INTR_QS_ERR: |
| 1264 | − reg_val |= (1ULL << NICVF_INTR_QS_ERR_SHIFT); | |
| 1240 | + reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT); | |
| 1265 | 1241 | break; |
| 1266 | 1242 | default: |
| 1267 | − netdev_err(nic->netdev, | |
| 1268 | − "Failed to enable interrupt: unknown type\n"); | |
| 1269 | − break; | |
| 1243 | + reg_val = 0; | |
| 1270 | 1244 | } |
| 1271 | 1245 | |
| 1272 | − nicvf_reg_write(nic, NIC_VF_ENA_W1S, reg_val); | |
| 1246 | + return reg_val; | |
| 1247 | +} | |
| 1248 | + | |
| 1249 | +/* Enable interrupt */ | |
| 1250 | +void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx) | |
| 1251 | +{ | |
| 1252 | + u64 mask = nicvf_int_type_to_mask(int_type, q_idx); | |
| 1253 | + | |
| 1254 | + if (!mask) { | |
| 1255 | + netdev_dbg(nic->netdev, | |
| 1256 | + "Failed to enable interrupt: unknown type\n"); | |
| 1257 | + return; | |
| 1258 | + } | |
| 1259 | + nicvf_reg_write(nic, NIC_VF_ENA_W1S, | |
| 1260 | + nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask); | |
| 1273 | 1261 | } |
| 1274 | 1262 | |
| 1275 | 1263 | /* Disable interrupt */ |
| 1276 | 1264 | void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx) |
| 1277 | 1265 | { |
| 1278 | − u64 reg_val = 0; | |
| 1266 | + u64 mask = nicvf_int_type_to_mask(int_type, q_idx); | |
| 1279 | 1267 | |
| 1280 | − switch (int_type) { | |
| 1281 | − case NICVF_INTR_CQ: | |
| 1282 | − reg_val |= ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); | |
| 1283 | − break; | |
| 1284 | − case NICVF_INTR_SQ: | |
| 1285 | − reg_val |= ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); | |
| 1286 | − break; | |
| 1287 | − case NICVF_INTR_RBDR: | |
| 1288 | − reg_val |= ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); | |
| 1289 | − break; | |
| 1290 | − case NICVF_INTR_PKT_DROP: | |
| 1291 | − reg_val |= (1ULL << NICVF_INTR_PKT_DROP_SHIFT); | |
| 1292 | − break; | |
| 1293 | − case NICVF_INTR_TCP_TIMER: | |
| 1294 | − reg_val |= (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); | |
| 1295 | − break; | |
| 1296 | − case NICVF_INTR_MBOX: | |
| 1297 | − reg_val |= (1ULL << NICVF_INTR_MBOX_SHIFT); | |
| 1298 | − break; | |
| 1299 | − case NICVF_INTR_QS_ERR: | |
| 1300 | − reg_val |= (1ULL << NICVF_INTR_QS_ERR_SHIFT); | |
| 1301 | − break; | |
| 1302 | − default: | |
| 1303 | − netdev_err(nic->netdev, | |
| 1268 | + if (!mask) { | |
| 1269 | + netdev_dbg(nic->netdev, | |
| 1304 | 1270 | "Failed to disable interrupt: unknown type\n"); |
| 1305 | − break; | |
| 1271 | + return; | |
| 1306 | 1272 | } |
| 1307 | 1273 | |
| 1308 | − nicvf_reg_write(nic, NIC_VF_ENA_W1C, reg_val); | |
| 1274 | + nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask); | |
| 1309 | 1275 | } |
| 1310 | 1276 | |
| 1311 | 1277 | /* Clear interrupt */ |
| 1312 | 1278 | void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx) |
| 1313 | 1279 | { |
| 1314 | − u64 reg_val = 0; | |
| 1280 | + u64 mask = nicvf_int_type_to_mask(int_type, q_idx); | |
| 1315 | 1281 | |
| 1316 | − switch (int_type) { | |
| 1317 | − case NICVF_INTR_CQ: | |
| 1318 | − reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); | |
| 1319 | − break; | |
| 1320 | − case NICVF_INTR_SQ: | |
| 1321 | − reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); | |
| 1322 | − break; | |
| 1323 | − case NICVF_INTR_RBDR: | |
| 1324 | − reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); | |
| 1325 | − break; | |
| 1326 | − case NICVF_INTR_PKT_DROP: | |
| 1327 | − reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT); | |
| 1328 | − break; | |
| 1329 | − case NICVF_INTR_TCP_TIMER: | |
| 1330 | − reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); | |
| 1331 | − break; | |
| 1332 | − case NICVF_INTR_MBOX: | |
| 1333 | − reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT); | |
| 1334 | − break; | |
| 1335 | − case NICVF_INTR_QS_ERR: | |
| 1336 | − reg_val |= (1ULL << NICVF_INTR_QS_ERR_SHIFT); | |
| 1337 | − break; | |
| 1338 | − default: | |
| 1339 | − netdev_err(nic->netdev, | |
| 1282 | + if (!mask) { | |
| 1283 | + netdev_dbg(nic->netdev, | |
| 1340 | 1284 | "Failed to clear interrupt: unknown type\n"); |
| 1341 | − break; | |
| 1285 | + return; | |
| 1342 | 1286 | } |
| 1343 | 1287 | |
| 1344 | − nicvf_reg_write(nic, NIC_VF_INT, reg_val); | |
| 1288 | + nicvf_reg_write(nic, NIC_VF_INT, mask); | |
| 1345 | 1289 | } |
| 1346 | 1290 | |
| 1347 | 1291 | /* Check if interrupt is enabled */ |
| 1348 | 1292 | int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx) |
| 1349 | 1293 | { |
| 1350 | − u64 reg_val; | |
| 1351 | − u64 mask = 0xff; | |
| 1352 | − | |
| 1353 | − reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); | |
| 1354 | − | |
| 1355 | − switch (int_type) { | |
| 1356 | − case NICVF_INTR_CQ: | |
| 1357 | − mask = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); | |
| 1358 | − break; | |
| 1359 | − case NICVF_INTR_SQ: | |
| 1360 | − mask = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); | |
| 1361 | − break; | |
| 1362 | − case NICVF_INTR_RBDR: | |
| 1363 | − mask = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); | |
| 1364 | − break; | |
| 1365 | − case NICVF_INTR_PKT_DROP: | |
| 1366 | − mask = NICVF_INTR_PKT_DROP_MASK; | |
| 1367 | − break; | |
| 1368 | − case NICVF_INTR_TCP_TIMER: | |
| 1369 | − mask = NICVF_INTR_TCP_TIMER_MASK; | |
| 1370 | − break; | |
| 1371 | − case NICVF_INTR_MBOX: | |
| 1372 | − mask = NICVF_INTR_MBOX_MASK; | |
| 1373 | − break; | |
| 1374 | − case NICVF_INTR_QS_ERR: | |
| 1375 | − mask = NICVF_INTR_QS_ERR_MASK; | |
| 1376 | − break; | |
| 1377 | − default: | |
| 1378 | − netdev_err(nic->netdev, | |
| 1294 | + u64 mask = nicvf_int_type_to_mask(int_type, q_idx); | |
| 1295 | + /* If interrupt type is unknown, we treat it disabled. */ | |
| 1296 | + if (!mask) { | |
| 1297 | + netdev_dbg(nic->netdev, | |
| 1379 | 1298 | "Failed to check interrupt enable: unknown type\n"); |
| 1380 | − break; | |
| 1299 | + return 0; | |
| 1381 | 1300 | } |
| 1382 | 1301 | |
| 1383 | − return (reg_val & mask); | |
| 1302 | + return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S); | |
| 1384 | 1303 | } |
| 1385 | 1304 | |
| 1386 | 1305 | void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx) |
| @@ -75,7 +75,7 @@ · 74 unmodified lines | ||
| 75 | 75 | */ |
| 76 | 76 | #define CMP_QSIZE CMP_QUEUE_SIZE2 |
| 77 | 77 | #define CMP_QUEUE_LEN (1ULL << (CMP_QSIZE + 10)) |
| 78 | −#define CMP_QUEUE_CQE_THRESH 0 | |
| 78 | +#define CMP_QUEUE_CQE_THRESH (NAPI_POLL_WEIGHT / 2) | |
| 79 | 79 | #define CMP_QUEUE_TIMER_THRESH 80 /* ~2usec */ |
| 80 | 80 | |
| 81 | 81 | #define RBDR_SIZE RBDR_SIZE0 |
| @@ -83,10 +83,8 @@ · 1 unmodified line | ||
| 83 | 83 | #define MAX_RCV_BUF_COUNT (1ULL << (RBDR_SIZE6 + 13)) |
| 84 | 84 | #define RBDR_THRESH (RCV_BUF_COUNT / 2) |
| 85 | 85 | #define DMA_BUFFER_LEN 2048 /* In multiples of 128bytes */ |
| 86 | −#define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \ | |
| 87 | − SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \ | |
| 88 | − (NICVF_RCV_BUF_ALIGN_BYTES * 2)) | |
| 89 | −#define RCV_DATA_OFFSET NICVF_RCV_BUF_ALIGN_BYTES | |
| 86 | +#define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \ | |
| 87 | + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
| 90 | 88 | |
| 91 | 89 | #define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \ |
| 92 | 90 | MAX_CQE_PER_PKT_XMIT) |
| @@ -108,10 +106,6 @@ · 15 unmodified lines | ||
| 108 | 106 | #define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */ |
| 109 | 107 | |
| 110 | 108 | #define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES) |
| 111 | −#define NICVF_ADDR_ALIGN_LEN(ADDR, BYTES)\ | |
| 112 | − (NICVF_ALIGNED_ADDR(ADDR, BYTES) - BYTES) | |
| 113 | −#define NICVF_RCV_BUF_ALIGN_LEN(X)\ | |
| 114 | − (NICVF_ALIGNED_ADDR(X, NICVF_RCV_BUF_ALIGN_BYTES) - X) | |
| 115 | 109 | |
| 116 | 110 | /* Queue enable/disable */ |
| 117 | 111 | #define NICVF_SQ_EN BIT_ULL(19) |
| @@ -545,25 +545,28 @@ struct sq_hdr_subdesc { · 544 unmodified lines | ||
| 545 | 545 | u64 subdesc_cnt:8; |
| 546 | 546 | u64 csum_l4:2; |
| 547 | 547 | u64 csum_l3:1; |
| 548 | − u64 rsvd0:5; | |
| 548 | + u64 csum_inner_l4:2; | |
| 549 | + u64 csum_inner_l3:1; | |
| 550 | + u64 rsvd0:2; | |
| 549 | 551 | u64 l4_offset:8; |
| 550 | 552 | u64 l3_offset:8; |
| 551 | 553 | u64 rsvd1:4; |
| 552 | 554 | u64 tot_len:20; /* W0 */ |
| 553 | 555 | |
| 554 | − u64 tso_sdc_cont:8; | |
| 555 | − u64 tso_sdc_first:8; | |
| 556 | − u64 tso_l4_offset:8; | |
| 557 | − u64 tso_flags_last:12; | |
| 558 | − u64 tso_flags_first:12; | |
| 559 | − u64 rsvd2:2; | |
| 556 | + u64 rsvd2:24; | |
| 557 | + u64 inner_l4_offset:8; | |
| 558 | + u64 inner_l3_offset:8; | |
| 559 | + u64 tso_start:8; | |
| 560 | + u64 rsvd3:2; | |
| 560 | 561 | u64 tso_max_paysize:14; /* W1 */ |
| 561 | 562 | #elif defined(__LITTLE_ENDIAN_BITFIELD) |
| 562 | 563 | u64 tot_len:20; |
| 563 | 564 | u64 rsvd1:4; |
| 564 | 565 | u64 l3_offset:8; |
| 565 | 566 | u64 l4_offset:8; |
| 566 | − u64 rsvd0:5; | |
| 567 | + u64 rsvd0:2; | |
| 568 | + u64 csum_inner_l3:1; | |
| 569 | + u64 csum_inner_l4:2; | |
| 567 | 570 | u64 csum_l3:1; |
| 568 | 571 | u64 csum_l4:2; |
| 569 | 572 | u64 subdesc_cnt:8; |
| @@ -574,12 +577,11 @@ struct sq_hdr_subdesc { · 4 unmodified lines | ||
| 574 | 577 | u64 subdesc_type:4; /* W0 */ |
| 575 | 578 | |
| 576 | 579 | u64 tso_max_paysize:14; |
| 577 | − u64 rsvd2:2; | |
| 578 | − u64 tso_flags_first:12; | |
| 579 | − u64 tso_flags_last:12; | |
| 580 | − u64 tso_l4_offset:8; | |
| 581 | − u64 tso_sdc_first:8; | |
| 582 | − u64 tso_sdc_cont:8; /* W1 */ | |
| 580 | + u64 rsvd3:2; | |
| 581 | + u64 tso_start:8; | |
| 582 | + u64 inner_l3_offset:8; | |
| 583 | + u64 inner_l4_offset:8; | |
| 584 | + u64 rsvd2:24; /* W1 */ | |
| 583 | 585 | #endif |
| 584 | 586 | }; |
| 585 | 587 | |
| @@ -65,13 +65,14 @@ config CHELSIO_T3 · 64 unmodified lines | ||
| 65 | 65 | will be called cxgb3. |
| 66 | 66 | |
| 67 | 67 | config CHELSIO_T4 |
| 68 | − tristate "Chelsio Communications T4/T5 Ethernet support" | |
| 68 | + tristate "Chelsio Communications T4/T5/T6 Ethernet support" | |
| 69 | 69 | depends on PCI && (IPV6 || IPV6=n) |
| 70 | 70 | select FW_LOADER |
| 71 | 71 | select MDIO |
| 72 | 72 | ---help--- |
| 73 | − This driver supports Chelsio T4 and T5 based gigabit, 10Gb Ethernet | |
| 74 | − adapter and T5 based 40Gb Ethernet adapter. | |
| 73 | + This driver supports Chelsio T4, T5 & T6 based gigabit, 10Gb Ethernet | |
| 74 | + adapter and T5/T6 based 40Gb and T6 based 25Gb, 50Gb and 100Gb | |
| 75 | + Ethernet adapters. | |
| 75 | 76 | |
| 76 | 77 | For general information about Chelsio and our products, visit |
| 77 | 78 | our website at <http://www.chelsio.com>. |
| @@ -85,7 +86,7 @@ config CHELSIO_T4 · 7 unmodified lines | ||
| 85 | 86 | will be called cxgb4. |
| 86 | 87 | |
| 87 | 88 | config CHELSIO_T4_DCB |
| 88 | − bool "Data Center Bridging (DCB) Support for Chelsio T4/T5 cards" | |
| 89 | + bool "Data Center Bridging (DCB) Support for Chelsio T4/T5/T6 cards" | |
| 89 | 90 | default n |
| 90 | 91 | depends on CHELSIO_T4 && DCB |
| 91 | 92 | ---help--- |
| @@ -107,12 +108,12 @@ config CHELSIO_T4_FCOE · 15 unmodified lines | ||
| 107 | 108 | If unsure, say N. |
| 108 | 109 | |
| 109 | 110 | config CHELSIO_T4VF |
| 110 | − tristate "Chelsio Communications T4/T5 Virtual Function Ethernet support" | |
| 111 | + tristate "Chelsio Communications T4/T5/T6 Virtual Function Ethernet support" | |
| 111 | 112 | depends on PCI |
| 112 | 113 | ---help--- |
| 113 | − This driver supports Chelsio T4 and T5 based gigabit, 10Gb Ethernet | |
| 114 | − adapters and T5 based 40Gb Ethernet adapters with PCI-E SR-IOV Virtual | |
| 115 | − Functions. | |
| 114 | + This driver supports Chelsio T4, T5 & T6 based gigabit, 10Gb Ethernet | |
| 115 | + adapters and T5/T6 based 40Gb and T6 based 25Gb, 50Gb and 100Gb | |
| 116 | + Ethernet adapters with PCI-E SR-IOV Virtual Functions. | |
| 116 | 117 | |
| 117 | 118 | For general information about Chelsio and our products, visit |
| 118 | 119 | our website at <http://www.chelsio.com>. |
| @@ -137,7 +137,7 @@ static inline int simple_mdio_write(struct cphy *cphy, int reg, · 136 unmodified lines | ||
| 137 | 137 | |
| 138 | 138 | /* Convenience initializer */ |
| 139 | 139 | static inline void cphy_init(struct cphy *phy, struct net_device *dev, |
| 140 | − int phy_addr, struct cphy_ops *phy_ops, | |
| 140 | + int phy_addr, const struct cphy_ops *phy_ops, | |
| 141 | 141 | const struct mdio_ops *mdio_ops) |
| 142 | 142 | { |
| 143 | 143 | struct adapter *adapter = netdev_priv(dev); |
| @@ -337,7 +337,7 @@ static void mv88e1xxx_destroy(struct cphy *cphy) · 336 unmodified lines | ||
| 337 | 337 | kfree(cphy); |
| 338 | 338 | } |
| 339 | 339 | |
| 340 | −static struct cphy_ops mv88e1xxx_ops = { | |
| 340 | +static const struct cphy_ops mv88e1xxx_ops = { | |
| 341 | 341 | .destroy = mv88e1xxx_destroy, |
| 342 | 342 | .reset = mv88e1xxx_reset, |
| 343 | 343 | .interrupt_enable = mv88e1xxx_interrupt_enable, |
| @@ -195,7 +195,7 @@ static void mv88x201x_destroy(struct cphy *cphy) · 194 unmodified lines | ||
| 195 | 195 | kfree(cphy); |
| 196 | 196 | } |
| 197 | 197 | |
| 198 | −static struct cphy_ops mv88x201x_ops = { | |
| 198 | +static const struct cphy_ops mv88x201x_ops = { | |
| 199 | 199 | .destroy = mv88x201x_destroy, |
| 200 | 200 | .reset = mv88x201x_reset, |
| 201 | 201 | .interrupt_enable = mv88x201x_interrupt_enable, |
| @@ -154,7 +154,7 @@ static void my3126_destroy(struct cphy *cphy) · 153 unmodified lines | ||
| 154 | 154 | kfree(cphy); |
| 155 | 155 | } |
| 156 | 156 | |
| 157 | −static struct cphy_ops my3126_ops = { | |
| 157 | +static const struct cphy_ops my3126_ops = { | |
| 158 | 158 | .destroy = my3126_destroy, |
| 159 | 159 | .reset = my3126_reset, |
| 160 | 160 | .interrupt_enable = my3126_interrupt_enable, |
| @@ -570,7 +570,7 @@ static void pm3393_destroy(struct cmac *cmac) · 569 unmodified lines | ||
| 570 | 570 | kfree(cmac); |
| 571 | 571 | } |
| 572 | 572 | |
| 573 | −static struct cmac_ops pm3393_ops = { | |
| 573 | +static const struct cmac_ops pm3393_ops = { | |
| 574 | 574 | .destroy = pm3393_destroy, |
| 575 | 575 | .reset = pm3393_reset, |
| 576 | 576 | .interrupt_enable = pm3393_interrupt_enable, |
| @@ -666,7 +666,7 @@ static void mac_destroy(struct cmac *mac) · 665 unmodified lines | ||
| 666 | 666 | kfree(mac); |
| 667 | 667 | } |
| 668 | 668 | |
| 669 | −static struct cmac_ops vsc7326_ops = { | |
| 669 | +static const struct cmac_ops vsc7326_ops = { | |
| 670 | 670 | .destroy = mac_destroy, |
| 671 | 671 | .reset = mac_reset, |
| 672 | 672 | .interrupt_handler = mac_intr_handler, |
| @@ -198,7 +198,7 @@ static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed, · 197 unmodified lines | ||
| 198 | 198 | return 0; |
| 199 | 199 | } |
| 200 | 200 | |
| 201 | −static struct cphy_ops ael1002_ops = { | |
| 201 | +static const struct cphy_ops ael1002_ops = { | |
| 202 | 202 | .reset = ael1002_reset, |
| 203 | 203 | .intr_enable = ael1002_intr_noop, |
| 204 | 204 | .intr_disable = ael1002_intr_noop, |
| @@ -224,7 +224,7 @@ static int ael1006_reset(struct cphy *phy, int wait) · 19 unmodified lines | ||
| 224 | 224 | return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait); |
| 225 | 225 | } |
| 226 | 226 | |
| 227 | −static struct cphy_ops ael1006_ops = { | |
| 227 | +static const struct cphy_ops ael1006_ops = { | |
| 228 | 228 | .reset = ael1006_reset, |
| 229 | 229 | .intr_enable = t3_phy_lasi_intr_enable, |
| 230 | 230 | .intr_disable = t3_phy_lasi_intr_disable, |
| @@ -495,7 +495,7 @@ static int ael2005_intr_handler(struct cphy *phy) · 264 unmodified lines | ||
| 495 | 495 | return ret ? ret : cphy_cause_link_change; |
| 496 | 496 | } |
| 497 | 497 | |
| 498 | −static struct cphy_ops ael2005_ops = { | |
| 498 | +static const struct cphy_ops ael2005_ops = { | |
| 499 | 499 | .reset = ael2005_reset, |
| 500 | 500 | .intr_enable = ael2005_intr_enable, |
| 501 | 501 | .intr_disable = ael2005_intr_disable, |
| @@ -801,7 +801,7 @@ static int ael2020_intr_handler(struct cphy *phy) · 299 unmodified lines | ||
| 801 | 801 | return ret ? ret : cphy_cause_link_change; |
| 802 | 802 | } |
| 803 | 803 | |
| 804 | −static struct cphy_ops ael2020_ops = { | |
| 804 | +static const struct cphy_ops ael2020_ops = { | |
| 805 | 805 | .reset = ael2020_reset, |
| 806 | 806 | .intr_enable = ael2020_intr_enable, |
| 807 | 807 | .intr_disable = ael2020_intr_disable, |
| @@ -856,7 +856,7 @@ static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed, · 48 unmodified lines | ||
| 856 | 856 | return 0; |
| 857 | 857 | } |
| 858 | 858 | |
| 859 | −static struct cphy_ops qt2045_ops = { | |
| 859 | +static const struct cphy_ops qt2045_ops = { | |
| 860 | 860 | .reset = ael1006_reset, |
| 861 | 861 | .intr_enable = t3_phy_lasi_intr_enable, |
| 862 | 862 | .intr_disable = t3_phy_lasi_intr_disable, |
| @@ -921,7 +921,7 @@ static int xaui_direct_power_down(struct cphy *phy, int enable) · 58 unmodified lines | ||
| 921 | 921 | return 0; |
| 922 | 922 | } |
| 923 | 923 | |
| 924 | −static struct cphy_ops xaui_direct_ops = { | |
| 924 | +static const struct cphy_ops xaui_direct_ops = { | |
| 925 | 925 | .reset = xaui_direct_reset, |
| 926 | 926 | .intr_enable = ael1002_intr_noop, |
| 927 | 927 | .intr_disable = ael1002_intr_noop, |
| @@ -247,7 +247,7 @@ static int aq100x_get_link_status(struct cphy *phy, int *link_ok, · 246 unmodified lines | ||
| 247 | 247 | return 0; |
| 248 | 248 | } |
| 249 | 249 | |
| 250 | −static struct cphy_ops aq100x_ops = { | |
| 250 | +static const struct cphy_ops aq100x_ops = { | |
| 251 | 251 | .reset = aq100x_reset, |
| 252 | 252 | .intr_enable = aq100x_intr_enable, |
| 253 | 253 | .intr_disable = aq100x_intr_disable, |
| @@ -575,7 +575,7 @@ static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg, · 574 unmodified lines | ||
| 575 | 575 | |
| 576 | 576 | /* Convenience initializer */ |
| 577 | 577 | static inline void cphy_init(struct cphy *phy, struct adapter *adapter, |
| 578 | − int phy_addr, struct cphy_ops *phy_ops, | |
| 578 | + int phy_addr, const struct cphy_ops *phy_ops, | |
| 579 | 579 | const struct mdio_ops *mdio_ops, |
| 580 | 580 | unsigned int caps, const char *desc) |
| 581 | 581 | { |
| @@ -701,15 +701,16 @@ static ssize_t attr_store(struct device *d, · 700 unmodified lines | ||
| 701 | 701 | ssize_t(*set) (struct net_device *, unsigned int), |
| 702 | 702 | unsigned int min_val, unsigned int max_val) |
| 703 | 703 | { |
| 704 | − char *endp; | |
| 705 | 704 | ssize_t ret; |
| 706 | 705 | unsigned int val; |
| 707 | 706 | |
| 708 | 707 | if (!capable(CAP_NET_ADMIN)) |
| 709 | 708 | return -EPERM; |
| 710 | 709 | |
| 711 | − val = simple_strtoul(buf, &endp, 0); | |
| 712 | − if (endp == buf || val < min_val || val > max_val) | |
| 710 | + ret = kstrtouint(buf, 0, &val); | |
| 711 | + if (ret) | |
| 712 | + return ret; | |
| 713 | + if (val < min_val || val > max_val) | |
| 713 | 714 | return -EINVAL; |
| 714 | 715 | |
| 715 | 716 | rtnl_lock(); |
| @@ -829,14 +830,15 @@ static ssize_t tm_attr_store(struct device *d, · 113 unmodified lines | ||
| 829 | 830 | struct port_info *pi = netdev_priv(to_net_dev(d)); |
| 830 | 831 | struct adapter *adap = pi->adapter; |
| 831 | 832 | unsigned int val; |
| 832 | − char *endp; | |
| 833 | 833 | ssize_t ret; |
| 834 | 834 | |
| 835 | 835 | if (!capable(CAP_NET_ADMIN)) |
| 836 | 836 | return -EPERM; |
| 837 | 837 | |
| 838 | − val = simple_strtoul(buf, &endp, 0); | |
| 839 | − if (endp == buf || val > 10000000) | |
| 838 | + ret = kstrtouint(buf, 0, &val); | |
| 839 | + if (ret) | |
| 840 | + return ret; | |
| 841 | + if (val > 10000000) | |
| 840 | 842 | return -EINVAL; |
| 841 | 843 | |
| 842 | 844 | rtnl_lock(); |
| @@ -709,11 +709,21 @@ static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) · 708 unmodified lines | ||
| 709 | 709 | return ret; |
| 710 | 710 | } |
| 711 | 711 | |
| 712 | − p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10); | |
| 713 | − p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10); | |
| 714 | − p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10); | |
| 715 | − p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10); | |
| 716 | − p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10); | |
| 712 | + ret = kstrtouint(vpd.cclk_data, 10, &p->cclk); | |
| 713 | + if (ret) | |
| 714 | + return ret; | |
| 715 | + ret = kstrtouint(vpd.mclk_data, 10, &p->mclk); | |
| 716 | + if (ret) | |
| 717 | + return ret; | |
| 718 | + ret = kstrtouint(vpd.uclk_data, 10, &p->uclk); | |
| 719 | + if (ret) | |
| 720 | + return ret; | |
| 721 | + ret = kstrtouint(vpd.mdc_data, 10, &p->mdc); | |
| 722 | + if (ret) | |
| 723 | + return ret; | |
| 724 | + ret = kstrtouint(vpd.mt_data, 10, &p->mem_timing); | |
| 725 | + if (ret) | |
| 726 | + return ret; | |
| 717 | 727 | memcpy(p->sn, vpd.sn_data, SERNUM_LEN); |
| 718 | 728 | |
| 719 | 729 | /* Old eeproms didn't have port information */ |
| @@ -723,8 +733,12 @@ static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) · 3 unmodified lines | ||
| 723 | 733 | } else { |
| 724 | 734 | p->port_type[0] = hex_to_bin(vpd.port0_data[0]); |
| 725 | 735 | p->port_type[1] = hex_to_bin(vpd.port1_data[0]); |
| 726 | − p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16); | |
| 727 | − p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16); | |
| 736 | + ret = kstrtou16(vpd.xaui0cfg_data, 16, &p->xauicfg[0]); | |
| 737 | + if (ret) | |
| 738 | + return ret; | |
| 739 | + ret = kstrtou16(vpd.xaui1cfg_data, 16, &p->xauicfg[1]); | |
| 740 | + if (ret) | |
| 741 | + return ret; | |
| 728 | 742 | } |
| 729 | 743 | |
| 730 | 744 | ret = hex2bin(p->eth_base, vpd.na_data, 6); |
| @@ -336,7 +336,7 @@ static int vsc8211_intr_handler(struct cphy *cphy) · 335 unmodified lines | ||
| 336 | 336 | return cphy_cause; |
| 337 | 337 | } |
| 338 | 338 | |
| 339 | −static struct cphy_ops vsc8211_ops = { | |
| 339 | +static const struct cphy_ops vsc8211_ops = { | |
| 340 | 340 | .reset = vsc8211_reset, |
| 341 | 341 | .intr_enable = vsc8211_intr_enable, |
| 342 | 342 | .intr_disable = vsc8211_intr_disable, |
| @@ -350,7 +350,7 @@ static struct cphy_ops vsc8211_ops = { · 7 unmodified lines | ||
| 350 | 350 | .power_down = vsc8211_power_down, |
| 351 | 351 | }; |
| 352 | 352 | |
| 353 | −static struct cphy_ops vsc8211_fiber_ops = { | |
| 353 | +static const struct cphy_ops vsc8211_fiber_ops = { | |
| 354 | 354 | .reset = vsc8211_reset, |
| 355 | 355 | .intr_enable = vsc8211_intr_enable, |
| 356 | 356 | .intr_disable = vsc8211_intr_disable, |
| @@ -118,6 +118,11 @@ int cxgb4_clip_get(const struct net_device *dev, const u32 *lip, u8 v6) · 117 unmodified lines | ||
| 118 | 118 | ret = clip6_get_mbox(dev, (const struct in6_addr *)lip); |
| 119 | 119 | if (ret) { |
| 120 | 120 | write_unlock_bh(&ctbl->lock); |
| 121 | + dev_err(adap->pdev_dev, | |
| 122 | + "CLIP FW cmd failed with error %d, " | |
| 123 | + "Connections using %pI6c wont be " | |
| 124 | + "offloaded", | |
| 125 | + ret, ce->addr6.sin6_addr.s6_addr); | |
| 121 | 126 | return ret; |
| 122 | 127 | } |
| 123 | 128 | } else { |
| @@ -127,6 +132,9 @@ int cxgb4_clip_get(const struct net_device *dev, const u32 *lip, u8 v6) · 3 unmodified lines | ||
| 127 | 132 | } |
| 128 | 133 | } else { |
| 129 | 134 | write_unlock_bh(&ctbl->lock); |
| 135 | + dev_info(adap->pdev_dev, "CLIP table overflow, " | |
| 136 | + "Connections using %pI6c wont be offloaded", | |
| 137 | + (void *)lip); | |
| 130 | 138 | return -ENOMEM; |
| 131 | 139 | } |
| 132 | 140 | write_unlock_bh(&ctbl->lock); |
| @@ -146,6 +154,9 @@ void cxgb4_clip_release(const struct net_device *dev, const u32 *lip, u8 v6) · 13 unmodified lines | ||
| 146 | 154 | int hash; |
| 147 | 155 | int ret = -1; |
| 148 | 156 | |
| 157 | + if (!ctbl) | |
| 158 | + return; | |
| 159 | + | |
| 149 | 160 | hash = clip_addr_hash(ctbl, addr, v6); |
| 150 | 161 | |
| 151 | 162 | read_lock_bh(&ctbl->lock); |
| @@ -301,6 +301,8 @@ struct devlog_params { · 300 unmodified lines | ||
| 301 | 301 | /* Stores chip specific parameters */ |
| 302 | 302 | struct arch_specific_params { |
| 303 | 303 | u8 nchan; |
| 304 | + u8 pm_stats_cnt; | |
| 305 | + u8 cng_ch_bits_log; /* congestion channel map bits width */ | |
| 304 | 306 | u16 mps_rplc_size; |
| 305 | 307 | u16 vfcount; |
| 306 | 308 | u32 sge_fl_db; |
| @@ -398,11 +400,10 @@ struct link_config { · 91 unmodified lines | ||
| 398 | 400 | |
| 399 | 401 | enum { |
| 400 | 402 | MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ |
| 401 | − MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ | |
| 403 | + MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ | |
| 402 | 404 | MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ |
| 403 | 405 | MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ |
| 404 | 406 | MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ |
| 405 | − MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ | |
| 406 | 407 | }; |
| 407 | 408 | |
| 408 | 409 | enum { |
| @@ -420,7 +421,7 @@ enum { · 11 unmodified lines | ||
| 420 | 421 | INGQ_EXTRAS = 2, /* firmware event queue and */ |
| 421 | 422 | /* forwarded interrupts */ |
| 422 | 423 | MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES |
| 423 | − + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, | |
| 424 | + + MAX_RDMA_CIQS + INGQ_EXTRAS, | |
| 424 | 425 | }; |
| 425 | 426 | |
| 426 | 427 | struct adapter; |
| @@ -483,6 +484,8 @@ struct sge_fl { /* SGE free-buffer queue state */ · 56 unmodified lines | ||
| 483 | 484 | unsigned int pidx; /* producer index */ |
| 484 | 485 | unsigned long alloc_failed; /* # of times buffer allocation failed */ |
| 485 | 486 | unsigned long large_alloc_failed; |
| 487 | + unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ | |
| 488 | + unsigned long low; /* # of times momentarily starving */ | |
| 486 | 489 | unsigned long starving; |
| 487 | 490 | /* RO fields */ |
| 488 | 491 | unsigned int cntxt_id; /* SGE context id for the free list */ |
| @@ -618,6 +621,7 @@ struct sge_ofld_txq { /* state for an SGE offload Tx queue */ · 129 unmodified lines | ||
| 618 | 621 | struct adapter *adap; |
| 619 | 622 | struct sk_buff_head sendq; /* list of backpressured packets */ |
| 620 | 623 | struct tasklet_struct qresume_tsk; /* restarts the queue */ |
| 624 | + bool service_ofldq_running; /* service_ofldq() is processing sendq */ | |
| 621 | 625 | u8 full; /* the Tx ring is full */ |
| 622 | 626 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ |
| 623 | 627 | } ____cacheline_aligned_in_smp; |
| @@ -636,7 +640,7 @@ struct sge { · 12 unmodified lines | ||
| 636 | 640 | struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; |
| 637 | 641 | |
| 638 | 642 | struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; |
| 639 | − struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; | |
| 643 | + struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS]; | |
| 640 | 644 | struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; |
| 641 | 645 | struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; |
| 642 | 646 | struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; |
| @@ -647,10 +651,10 @@ struct sge { · 4 unmodified lines | ||
| 647 | 651 | u16 max_ethqsets; /* # of available Ethernet queue sets */ |
| 648 | 652 | u16 ethqsets; /* # of active Ethernet queue sets */ |
| 649 | 653 | u16 ethtxq_rover; /* Tx queue to clean up next */ |
| 650 | − u16 ofldqsets; /* # of active offload queue sets */ | |
| 654 | + u16 iscsiqsets; /* # of active iSCSI queue sets */ | |
| 651 | 655 | u16 rdmaqs; /* # of available RDMA Rx queues */ |
| 652 | 656 | u16 rdmaciqs; /* # of available RDMA concentrator IQs */ |
| 653 | − u16 ofld_rxq[MAX_OFLD_QSETS]; | |
| 657 | + u16 iscsi_rxq[MAX_OFLD_QSETS]; | |
| 654 | 658 | u16 rdma_rxq[MAX_RDMA_QUEUES]; |
| 655 | 659 | u16 rdma_ciq[MAX_RDMA_CIQS]; |
| 656 | 660 | u16 timer_val[SGE_NTIMERS]; |
| @@ -676,7 +680,7 @@ struct sge { · 19 unmodified lines | ||
| 676 | 680 | }; |
| 677 | 681 | |
| 678 | 682 | #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) |
| 679 | −#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) | |
| 683 | +#define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++) | |
| 680 | 684 | #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) |
| 681 | 685 | #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) |
| 682 | 686 | |
| @@ -1253,6 +1257,7 @@ int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); · 570 unmodified lines | ||
| 1253 | 1257 | int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); |
| 1254 | 1258 | int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, |
| 1255 | 1259 | const u8 *fw_data, unsigned int size, int force); |
| 1260 | +int t4_fl_pkt_align(struct adapter *adap); | |
| 1256 | 1261 | unsigned int t4_flash_cfg_addr(struct adapter *adapter); |
| 1257 | 1262 | int t4_check_fw_version(struct adapter *adap); |
| 1258 | 1263 | int t4_get_fw_version(struct adapter *adapter, u32 *vers); |
| @@ -757,8 +757,8 @@ static int pm_stats_show(struct seq_file *seq, void *v) · 756 unmodified lines | ||
| 757 | 757 | }; |
| 758 | 758 | |
| 759 | 759 | int i; |
| 760 | − u32 tx_cnt[PM_NSTATS], rx_cnt[PM_NSTATS]; | |
| 761 | − u64 tx_cyc[PM_NSTATS], rx_cyc[PM_NSTATS]; | |
| 760 | + u32 tx_cnt[T6_PM_NSTATS], rx_cnt[T6_PM_NSTATS]; | |
| 761 | + u64 tx_cyc[T6_PM_NSTATS], rx_cyc[T6_PM_NSTATS]; | |
| 762 | 762 | struct adapter *adap = seq->private; |
| 763 | 763 | |
| 764 | 764 | t4_pmtx_get_stats(adap, tx_cnt, tx_cyc); |
| @@ -773,6 +773,32 @@ static int pm_stats_show(struct seq_file *seq, void *v) · 8 unmodified lines | ||
| 773 | 773 | for (i = 0; i < PM_NSTATS - 1; i++) |
| 774 | 774 | seq_printf(seq, "%-13s %10u %20llu\n", |
| 775 | 775 | rx_pm_stats[i], rx_cnt[i], rx_cyc[i]); |
| 776 | + | |
| 777 | + if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { | |
| 778 | + /* In T5 the granularity of the total wait is too fine. | |
| 779 | + * It is not useful as it reaches the max value too fast. | |
| 780 | + * Hence display this Input FIFO wait for T6 onwards. | |
| 781 | + */ | |
| 782 | + seq_printf(seq, "%13s %10s %20s\n", | |
| 783 | + " ", "Total wait", "Total Occupancy"); | |
| 784 | + seq_printf(seq, "Tx FIFO wait %10u %20llu\n", | |
| 785 | + tx_cnt[i], tx_cyc[i]); | |
| 786 | + seq_printf(seq, "Rx FIFO wait %10u %20llu\n", | |
| 787 | + rx_cnt[i], rx_cyc[i]); | |
| 788 | + | |
| 789 | + /* Skip index 6 as there is nothing useful ihere */ | |
| 790 | + i += 2; | |
| 791 | + | |
| 792 | + /* At index 7, a new stat for read latency (count, total wait) | |
| 793 | + * is added. | |
| 794 | + */ | |
| 795 | + seq_printf(seq, "%13s %10s %20s\n", | |
| 796 | + " ", "Reads", "Total wait"); | |
| 797 | + seq_printf(seq, "Tx latency %10u %20llu\n", | |
| 798 | + tx_cnt[i], tx_cyc[i]); | |
| 799 | + seq_printf(seq, "Rx latency %10u %20llu\n", | |
| 800 | + rx_cnt[i], rx_cyc[i]); | |
| 801 | + } | |
| 776 | 802 | return 0; |
| 777 | 803 | } |
| 778 | 804 | |
| @@ -1559,25 +1585,35 @@ static int mps_tcam_show(struct seq_file *seq, void *v) · 780 unmodified lines | ||
| 1559 | 1585 | { |
| 1560 | 1586 | struct adapter *adap = seq->private; |
| 1561 | 1587 | unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); |
| 1562 | − | |
| 1563 | 1588 | if (v == SEQ_START_TOKEN) { |
| 1564 | − if (adap->params.arch.mps_rplc_size > 128) | |
| 1589 | + if (chip_ver > CHELSIO_T5) { | |
| 1565 | 1590 | seq_puts(seq, "Idx Ethernet address Mask " |
| 1591 | + " VNI Mask IVLAN Vld " | |
| 1592 | + "DIP_Hit Lookup Port " | |
| 1566 | 1593 | "Vld Ports PF VF " |
| 1567 | 1594 | "Replication " |
| 1568 | 1595 | " P0 P1 P2 P3 ML\n"); |
| 1569 | − else | |
| 1570 | − seq_puts(seq, "Idx Ethernet address Mask " | |
| 1571 | − "Vld Ports PF VF Replication" | |
| 1572 | − " P0 P1 P2 P3 ML\n"); | |
| 1596 | + } else { | |
| 1597 | + if (adap->params.arch.mps_rplc_size > 128) | |
| 1598 | + seq_puts(seq, "Idx Ethernet address Mask " | |
| 1599 | + "Vld Ports PF VF " | |
| 1600 | + "Replication " | |
| 1601 | + " P0 P1 P2 P3 ML\n"); | |
| 1602 | + else | |
| 1603 | + seq_puts(seq, "Idx Ethernet address Mask " | |
| 1604 | + "Vld Ports PF VF Replication" | |
| 1605 | + " P0 P1 P2 P3 ML\n"); | |
| 1606 | + } | |
| 1573 | 1607 | } else { |
| 1574 | 1608 | u64 mask; |
| 1575 | 1609 | u8 addr[ETH_ALEN]; |
| 1576 | − bool replicate; | |
| 1610 | + bool replicate, dip_hit = false, vlan_vld = false; | |
| 1577 | 1611 | unsigned int idx = (uintptr_t)v - 2; |
| 1578 | 1612 | u64 tcamy, tcamx, val; |
| 1579 | − u32 cls_lo, cls_hi, ctl; | |
| 1613 | + u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0; | |
| 1580 | 1614 | u32 rplc[8] = {0}; |
| 1615 | + u8 lookup_type = 0, port_num = 0; | |
| 1616 | + u16 ivlan = 0; | |
| 1581 | 1617 | |
| 1582 | 1618 | if (chip_ver > CHELSIO_T5) { |
| 1583 | 1619 | /* CtlCmdType - 0: Read, 1: Write |
| @@ -1596,6 +1632,22 @@ static int mps_tcam_show(struct seq_file *seq, void *v) · 12 unmodified lines | ||
| 1596 | 1632 | val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); |
| 1597 | 1633 | tcamy = DMACH_G(val) << 32; |
| 1598 | 1634 | tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); |
| 1635 | + data2 = t4_read_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A); | |
| 1636 | + lookup_type = DATALKPTYPE_G(data2); | |
| 1637 | + /* 0 - Outer header, 1 - Inner header | |
| 1638 | + * [71:48] bit locations are overloaded for | |
| 1639 | + * outer vs. inner lookup types. | |
| 1640 | + */ | |
| 1641 | + if (lookup_type && (lookup_type != DATALKPTYPE_M)) { | |
| 1642 | + /* Inner header VNI */ | |
| 1643 | + vniy = ((data2 & DATAVIDH2_F) << 23) | | |
| 1644 | + (DATAVIDH1_G(data2) << 16) | VIDL_G(val); | |
| 1645 | + dip_hit = data2 & DATADIPHIT_F; | |
| 1646 | + } else { | |
| 1647 | + vlan_vld = data2 & DATAVIDH2_F; | |
| 1648 | + ivlan = VIDL_G(val); | |
| 1649 | + } | |
| 1650 | + port_num = DATAPORTNUM_G(data2); | |
| 1599 | 1651 | |
| 1600 | 1652 | /* Read tcamx. Change the control param */ |
| 1601 | 1653 | ctl |= CTLXYBITSEL_V(1); |
| @@ -1603,6 +1655,12 @@ static int mps_tcam_show(struct seq_file *seq, void *v) · 1 unmodified line | ||
| 1603 | 1655 | val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); |
| 1604 | 1656 | tcamx = DMACH_G(val) << 32; |
| 1605 | 1657 | tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); |
| 1658 | + data2 = t4_read_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A); | |
| 1659 | + if (lookup_type && (lookup_type != DATALKPTYPE_M)) { | |
| 1660 | + /* Inner header VNI mask */ | |
| 1661 | + vnix = ((data2 & DATAVIDH2_F) << 23) | | |
| 1662 | + (DATAVIDH1_G(data2) << 16) | VIDL_G(val); | |
| 1663 | + } | |
| 1606 | 1664 | } else { |
| 1607 | 1665 | tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx)); |
| 1608 | 1666 | tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx)); |
| @@ -1662,17 +1720,47 @@ static int mps_tcam_show(struct seq_file *seq, void *v) · 53 unmodified lines | ||
| 1662 | 1720 | } |
| 1663 | 1721 | |
| 1664 | 1722 | tcamxy2valmask(tcamx, tcamy, addr, &mask); |
| 1665 | − if (chip_ver > CHELSIO_T5) | |
| 1666 | − seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x " | |
| 1667 | − "%012llx%3c %#x%4u%4d", | |
| 1668 | − idx, addr[0], addr[1], addr[2], addr[3], | |
| 1669 | − addr[4], addr[5], (unsigned long long)mask, | |
| 1670 | − (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', | |
| 1671 | − PORTMAP_G(cls_hi), | |
| 1672 | − T6_PF_G(cls_lo), | |
| 1673 | − (cls_lo & T6_VF_VALID_F) ? | |
| 1674 | − T6_VF_G(cls_lo) : -1); | |
| 1675 | − else | |
| 1723 | + if (chip_ver > CHELSIO_T5) { | |
| 1724 | + /* Inner header lookup */ | |
| 1725 | + if (lookup_type && (lookup_type != DATALKPTYPE_M)) { | |
| 1726 | + seq_printf(seq, | |
| 1727 | + "%3u %02x:%02x:%02x:%02x:%02x:%02x " | |
| 1728 | + "%012llx %06x %06x - - %3c" | |
| 1729 | + " 'I' %4x " | |
| 1730 | + "%3c %#x%4u%4d", idx, addr[0], | |
| 1731 | + addr[1], addr[2], addr[3], | |
| 1732 | + addr[4], addr[5], | |
| 1733 | + (unsigned long long)mask, | |
| 1734 | + vniy, vnix, dip_hit ? 'Y' : 'N', | |
| 1735 | + port_num, | |
| 1736 | + (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', | |
| 1737 | + PORTMAP_G(cls_hi), | |
| 1738 | + T6_PF_G(cls_lo), | |
| 1739 | + (cls_lo & T6_VF_VALID_F) ? | |
| 1740 | + T6_VF_G(cls_lo) : -1); | |
| 1741 | + } else { | |
| 1742 | + seq_printf(seq, | |
| 1743 | + "%3u %02x:%02x:%02x:%02x:%02x:%02x " | |
| 1744 | + "%012llx - - ", | |
| 1745 | + idx, addr[0], addr[1], addr[2], | |
| 1746 | + addr[3], addr[4], addr[5], | |
| 1747 | + (unsigned long long)mask); | |
| 1748 | + | |
| 1749 | + if (vlan_vld) | |
| 1750 | + seq_printf(seq, "%4u Y ", ivlan); | |
| 1751 | + else | |
| 1752 | + seq_puts(seq, " - N "); | |
| 1753 | + | |
| 1754 | + seq_printf(seq, | |
| 1755 | + "- %3c %4x %3c %#x%4u%4d", | |
| 1756 | + lookup_type ? 'I' : 'O', port_num, | |
| 1757 | + (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', | |
| 1758 | + PORTMAP_G(cls_hi), | |
| 1759 | + T6_PF_G(cls_lo), | |
| 1760 | + (cls_lo & T6_VF_VALID_F) ? | |
| 1761 | + T6_VF_G(cls_lo) : -1); | |
| 1762 | + } | |
| 1763 | + } else | |
| 1676 | 1764 | seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x " |
| 1677 | 1765 | "%012llx%3c %#x%4u%4d", |
| 1678 | 1766 | idx, addr[0], addr[1], addr[2], addr[3], |
| @@ -2245,7 +2333,7 @@ static int sge_qinfo_show(struct seq_file *seq, void *v) · 566 unmodified lines | ||
| 2245 | 2333 | { |
| 2246 | 2334 | struct adapter *adap = seq->private; |
| 2247 | 2335 | int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4); |
| 2248 | − int iscsi_entries = DIV_ROUND_UP(adap->sge.ofldqsets, 4); | |
| 2336 | + int iscsi_entries = DIV_ROUND_UP(adap->sge.iscsiqsets, 4); | |
| 2249 | 2337 | int rdma_entries = DIV_ROUND_UP(adap->sge.rdmaqs, 4); |
| 2250 | 2338 | int ciq_entries = DIV_ROUND_UP(adap->sge.rdmaciqs, 4); |
| 2251 | 2339 | int ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4); |
| @@ -2325,14 +2413,16 @@ do { \ · 73 unmodified lines | ||
| 2325 | 2413 | TL("TxMapErr:", mapping_err); |
| 2326 | 2414 | RL("FLAllocErr:", fl.alloc_failed); |
| 2327 | 2415 | RL("FLLrgAlcErr:", fl.large_alloc_failed); |
| 2416 | + RL("FLMapErr:", fl.mapping_err); | |
| 2417 | + RL("FLLow:", fl.low); | |
| 2328 | 2418 | RL("FLStarving:", fl.starving); |
| 2329 | 2419 | |
| 2330 | 2420 | } else if (iscsi_idx < iscsi_entries) { |
| 2331 | 2421 | const struct sge_ofld_rxq *rx = |
| 2332 | − &adap->sge.ofldrxq[iscsi_idx * 4]; | |
| 2422 | + &adap->sge.iscsirxq[iscsi_idx * 4]; | |
| 2333 | 2423 | const struct sge_ofld_txq *tx = |
| 2334 | 2424 | &adap->sge.ofldtxq[iscsi_idx * 4]; |
| 2335 | − int n = min(4, adap->sge.ofldqsets - 4 * iscsi_idx); | |
| 2425 | + int n = min(4, adap->sge.iscsiqsets - 4 * iscsi_idx); | |
| 2336 | 2426 | |
| 2337 | 2427 | S("QType:", "iSCSI"); |
| 2338 | 2428 | T("TxQ ID:", q.cntxt_id); |
| @@ -2359,6 +2449,8 @@ do { \ · 20 unmodified lines | ||
| 2359 | 2449 | RL("RxNoMem:", stats.nomem); |
| 2360 | 2450 | RL("FLAllocErr:", fl.alloc_failed); |
| 2361 | 2451 | RL("FLLrgAlcErr:", fl.large_alloc_failed); |
| 2452 | + RL("FLMapErr:", fl.mapping_err); | |
| 2453 | + RL("FLLow:", fl.low); | |
| 2362 | 2454 | RL("FLStarving:", fl.starving); |
| 2363 | 2455 | |
| 2364 | 2456 | } else if (rdma_idx < rdma_entries) { |
| @@ -2388,6 +2480,8 @@ do { \ · 23 unmodified lines | ||
| 2388 | 2480 | RL("RxNoMem:", stats.nomem); |
| 2389 | 2481 | RL("FLAllocErr:", fl.alloc_failed); |
| 2390 | 2482 | RL("FLLrgAlcErr:", fl.large_alloc_failed); |
| 2483 | + RL("FLMapErr:", fl.mapping_err); | |
| 2484 | + RL("FLLow:", fl.low); | |
| 2391 | 2485 | RL("FLStarving:", fl.starving); |
| 2392 | 2486 | |
| 2393 | 2487 | } else if (ciq_idx < ciq_entries) { |
| @@ -2448,7 +2542,7 @@ do { \ · 54 unmodified lines | ||
| 2448 | 2542 | static int sge_queue_entries(const struct adapter *adap) |
| 2449 | 2543 | { |
| 2450 | 2544 | return DIV_ROUND_UP(adap->sge.ethqsets, 4) + |
| 2451 | − DIV_ROUND_UP(adap->sge.ofldqsets, 4) + | |
| 2545 | + DIV_ROUND_UP(adap->sge.iscsiqsets, 4) + | |
| 2452 | 2546 | DIV_ROUND_UP(adap->sge.rdmaqs, 4) + |
| 2453 | 2547 | DIV_ROUND_UP(adap->sge.rdmaciqs, 4) + |
| 2454 | 2548 | DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1; |
| @@ -35,79 +35,79 @@ static void set_msglevel(struct net_device *dev, u32 val) · 34 unmodified lines | ||
| 35 | 35 | } |
| 36 | 36 | |
| 37 | 37 | static const char stats_strings[][ETH_GSTRING_LEN] = { |
| 38 | − "tx_octets_ok ", | |
| 39 | − "tx_frames_ok ", | |
| 40 | − "tx_broadcast_frames ", | |
| 41 | − "tx_multicast_frames ", | |
| 42 | − "tx_unicast_frames ", | |
| 43 | − "tx_error_frames ", | |
| 44 | − | |
| 45 | − "tx_frames_64 ", | |
| 46 | − "tx_frames_65_to_127 ", | |
| 47 | − "tx_frames_128_to_255 ", | |
| 48 | − "tx_frames_256_to_511 ", | |
| 49 | − "tx_frames_512_to_1023 ", | |
| 50 | − "tx_frames_1024_to_1518 ", | |
| 51 | − "tx_frames_1519_to_max ", | |
| 52 | − | |
| 53 | − "tx_frames_dropped ", | |
| 54 | − "tx_pause_frames ", | |
| 55 | − "tx_ppp0_frames ", | |
| 56 | − "tx_ppp1_frames ", | |
| 57 | − "tx_ppp2_frames ", | |
| 58 | − "tx_ppp3_frames ", | |
| 59 | − "tx_ppp4_frames ", | |
| 60 | − "tx_ppp5_frames ", | |
| 61 | − "tx_ppp6_frames ", | |
| 62 | − "tx_ppp7_frames ", | |
| 63 | − | |
| 64 | − "rx_octets_ok ", | |
| 65 | − "rx_frames_ok ", | |
| 66 | − "rx_broadcast_frames ", | |
| 67 | − "rx_multicast_frames ", | |
| 68 | − "rx_unicast_frames ", | |
| 69 | − | |
| 70 | − "rx_frames_too_long ", | |
| 71 | − "rx_jabber_errors ", | |
| 72 | − "rx_fcs_errors ", | |
| 73 | − "rx_length_errors ", | |
| 74 | − "rx_symbol_errors ", | |
| 75 | − "rx_runt_frames ", | |
| 76 | − | |
| 77 | − "rx_frames_64 ", | |
| 78 | − "rx_frames_65_to_127 ", | |
| 79 | − "rx_frames_128_to_255 ", | |
| 80 | − "rx_frames_256_to_511 ", | |
| 81 | − "rx_frames_512_to_1023 ", | |
| 82 | − "rx_frames_1024_to_1518 ", | |
| 83 | − "rx_frames_1519_to_max ", | |
| 84 | − | |
| 85 | − "rx_pause_frames ", | |
| 86 | − "rx_ppp0_frames ", | |
| 87 | − "rx_ppp1_frames ", | |
| 88 | − "rx_ppp2_frames ", | |
| 89 | − "rx_ppp3_frames ", | |
| 90 | − "rx_ppp4_frames ", | |
| 91 | − "rx_ppp5_frames ", | |
| 92 | − "rx_ppp6_frames ", | |
| 93 | − "rx_ppp7_frames ", | |
| 94 | − | |
| 95 | − "rx_bg0_frames_dropped ", | |
| 96 | − "rx_bg1_frames_dropped ", | |
| 97 | − "rx_bg2_frames_dropped ", | |
| 98 | − "rx_bg3_frames_dropped ", | |
| 99 | − "rx_bg0_frames_trunc ", | |
| 100 | − "rx_bg1_frames_trunc ", | |
| 101 | − "rx_bg2_frames_trunc ", | |
| 102 | − "rx_bg3_frames_trunc ", | |
| 103 | − | |
| 104 | − "tso ", | |
| 105 | − "tx_csum_offload ", | |
| 106 | − "rx_csum_good ", | |
| 107 | − "vlan_extractions ", | |
| 108 | − "vlan_insertions ", | |
| 109 | − "gro_packets ", | |
| 110 | − "gro_merged ", | |
| 38 | + "tx_octets_ok ", | |
| 39 | + "tx_frames_ok ", | |
| 40 | + "tx_broadcast_frames ", | |
| 41 | + "tx_multicast_frames ", | |
| 42 | + "tx_unicast_frames ", | |
| 43 | + "tx_error_frames ", | |
| 44 | + | |
| 45 | + "tx_frames_64 ", | |
| 46 | + "tx_frames_65_to_127 ", | |
| 47 | + "tx_frames_128_to_255 ", | |
| 48 | + "tx_frames_256_to_511 ", | |
| 49 | + "tx_frames_512_to_1023 ", | |
| 50 | + "tx_frames_1024_to_1518 ", | |
| 51 | + "tx_frames_1519_to_max ", | |
| 52 | + | |
| 53 | + "tx_frames_dropped ", | |
| 54 | + "tx_pause_frames ", | |
| 55 | + "tx_ppp0_frames ", | |
| 56 | + "tx_ppp1_frames ", | |
| 57 | + "tx_ppp2_frames ", | |
| 58 | + "tx_ppp3_frames ", | |
| 59 | + "tx_ppp4_frames ", | |
| 60 | + "tx_ppp5_frames ", | |
| 61 | + "tx_ppp6_frames ", | |
| 62 | + "tx_ppp7_frames ", | |
| 63 | + | |
| 64 | + "rx_octets_ok ", | |
| 65 | + "rx_frames_ok ", | |
| 66 | + "rx_broadcast_frames ", | |
| 67 | + "rx_multicast_frames ", | |
| 68 | + "rx_unicast_frames ", | |
| 69 | + | |
| 70 | + "rx_frames_too_long ", | |
| 71 | + "rx_jabber_errors ", | |
| 72 | + "rx_fcs_errors ", | |
| 73 | + "rx_length_errors ", | |
| 74 | + "rx_symbol_errors ", | |
| 75 | + "rx_runt_frames ", | |
| 76 | + | |
| 77 | + "rx_frames_64 ", | |
| 78 | + "rx_frames_65_to_127 ", | |
| 79 | + "rx_frames_128_to_255 ", | |
| 80 | + "rx_frames_256_to_511 ", | |
| 81 | + "rx_frames_512_to_1023 ", | |
| 82 | + "rx_frames_1024_to_1518 ", | |
| 83 | + "rx_frames_1519_to_max ", | |
| 84 | + | |
| 85 | + "rx_pause_frames ", | |
| 86 | + "rx_ppp0_frames ", | |
| 87 | + "rx_ppp1_frames ", | |
| 88 | + "rx_ppp2_frames ", | |
| 89 | + "rx_ppp3_frames ", | |
| 90 | + "rx_ppp4_frames ", | |
| 91 | + "rx_ppp5_frames ", | |
| 92 | + "rx_ppp6_frames ", | |
| 93 | + "rx_ppp7_frames ", | |
| 94 | + | |
| 95 | + "rx_bg0_frames_dropped ", | |
| 96 | + "rx_bg1_frames_dropped ", | |
| 97 | + "rx_bg2_frames_dropped ", | |
| 98 | + "rx_bg3_frames_dropped ", | |
| 99 | + "rx_bg0_frames_trunc ", | |
| 100 | + "rx_bg1_frames_trunc ", | |
| 101 | + "rx_bg2_frames_trunc ", | |
| 102 | + "rx_bg3_frames_trunc ", | |
| 103 | + | |
| 104 | + "tso ", | |
| 105 | + "tx_csum_offload ", | |
| 106 | + "rx_csum_good ", | |
| 107 | + "vlan_extractions ", | |
| 108 | + "vlan_insertions ", | |
| 109 | + "gro_packets ", | |
| 110 | + "gro_merged ", | |
| 111 | 111 | }; |
| 112 | 112 | |
| 113 | 113 | static char adapter_stats_strings[][ETH_GSTRING_LEN] = { |
| @@ -686,7 +686,7 @@ static int set_pauseparam(struct net_device *dev, · 572 unmodified lines | ||
| 686 | 686 | if (epause->tx_pause) |
| 687 | 687 | lc->requested_fc |= PAUSE_TX; |
| 688 | 688 | if (netif_running(dev)) |
| 689 | − return t4_link_l1cfg(p->adapter, p->adapter->pf, p->tx_chan, | |
| 689 | + return t4_link_l1cfg(p->adapter, p->adapter->mbox, p->tx_chan, | |
| 690 | 690 | lc); |
| 691 | 691 | return 0; |
| 692 | 692 | } |
| @@ -162,19 +162,8 @@ MODULE_FIRMWARE(FW6_FNAME); · 161 unmodified lines | ||
| 162 | 162 | static uint force_init; |
| 163 | 163 | |
| 164 | 164 | module_param(force_init, uint, 0644); |
| 165 | −MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter"); | |
| 166 | − | |
| 167 | −/* | |
| 168 | − * Normally if the firmware we connect to has Configuration File support, we | |
| 169 | − * use that and only fall back to the old Driver-based initialization if the | |
| 170 | − * Configuration File fails for some reason. If force_old_init is set, then | |
| 171 | − * we'll always use the old Driver-based initialization sequence. | |
| 172 | − */ | |
| 173 | −static uint force_old_init; | |
| 174 | − | |
| 175 | −module_param(force_old_init, uint, 0644); | |
| 176 | −MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated" | |
| 177 | − " parameter"); | |
| 165 | +MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter," | |
| 166 | + "deprecated parameter"); | |
| 178 | 167 | |
| 179 | 168 | static int dflt_msg_enable = DFLT_MSG_ENABLE; |
| 180 | 169 | |
| @@ -195,23 +184,6 @@ static int msi = 2; · 14 unmodified lines | ||
| 195 | 184 | module_param(msi, int, 0644); |
| 196 | 185 | MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); |
| 197 | 186 | |
| 198 | −/* | |
| 199 | − * Queue interrupt hold-off timer values. Queues default to the first of these | |
| 200 | − * upon creation. | |
| 201 | − */ | |
| 202 | −static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 }; | |
| 203 | − | |
| 204 | −module_param_array(intr_holdoff, uint, NULL, 0644); | |
| 205 | −MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers " | |
| 206 | − "0..4 in microseconds, deprecated parameter"); | |
| 207 | − | |
| 208 | −static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 }; | |
| 209 | − | |
| 210 | −module_param_array(intr_cnt, uint, NULL, 0644); | |
| 211 | −MODULE_PARM_DESC(intr_cnt, | |
| 212 | − "thresholds 1..3 for queue interrupt packet counters, " | |
| 213 | − "deprecated parameter"); | |
| 214 | − | |
| 215 | 187 | /* |
| 216 | 188 | * Normally we tell the chip to deliver Ingress Packets into our DMA buffers |
| 217 | 189 | * offset by 2 bytes in order to have the IP headers line up on 4-byte |
| @@ -226,13 +198,7 @@ MODULE_PARM_DESC(intr_cnt, · 8 unmodified lines | ||
| 226 | 198 | */ |
| 227 | 199 | static int rx_dma_offset = 2; |
| 228 | 200 | |
| 229 | −static bool vf_acls; | |
| 230 | − | |
| 231 | 201 | #ifdef CONFIG_PCI_IOV |
| 232 | −module_param(vf_acls, bool, 0644); | |
| 233 | −MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, " | |
| 234 | − "deprecated parameter"); | |
| 235 | − | |
| 236 | 202 | /* Configure the number of PCI-E Virtual Function which are to be instantiated |
| 237 | 203 | * on SR-IOV Capable Physical Functions. |
| 238 | 204 | */ |
| @@ -253,12 +219,6 @@ module_param(select_queue, int, 0644); · 14 unmodified lines | ||
| 253 | 219 | MODULE_PARM_DESC(select_queue, |
| 254 | 220 | "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); |
| 255 | 221 | |
| 256 | −static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC; | |
| 257 | − | |
| 258 | −module_param(tp_vlan_pri_map, uint, 0644); | |
| 259 | −MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, " | |
| 260 | − "deprecated parameter"); | |
| 261 | − | |
| 262 | 222 | static struct dentry *cxgb4_debugfs_root; |
| 263 | 223 | |
| 264 | 224 | static LIST_HEAD(adapter_list); |
| @@ -766,8 +726,8 @@ static void name_msix_vecs(struct adapter *adap) · 501 unmodified lines | ||
| 766 | 726 | } |
| 767 | 727 | |
| 768 | 728 | /* offload queues */ |
| 769 | − for_each_ofldrxq(&adap->sge, i) | |
| 770 | − snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d", | |
| 729 | + for_each_iscsirxq(&adap->sge, i) | |
| 730 | + snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iscsi%d", | |
| 771 | 731 | adap->port[0]->name, i); |
| 772 | 732 | |
| 773 | 733 | for_each_rdmarxq(&adap->sge, i) |
| @@ -782,7 +742,7 @@ static void name_msix_vecs(struct adapter *adap) · 8 unmodified lines | ||
| 782 | 742 | static int request_msix_queue_irqs(struct adapter *adap) |
| 783 | 743 | { |
| 784 | 744 | struct sge *s = &adap->sge; |
| 785 | − int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0; | |
| 745 | + int err, ethqidx, iscsiqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0; | |
| 786 | 746 | int msi_index = 2; |
| 787 | 747 | |
| 788 | 748 | err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, |
| @@ -799,11 +759,11 @@ static int request_msix_queue_irqs(struct adapter *adap) · 10 unmodified lines | ||
| 799 | 759 | goto unwind; |
| 800 | 760 | msi_index++; |
| 801 | 761 | } |
| 802 | − for_each_ofldrxq(s, ofldqidx) { | |
| 762 | + for_each_iscsirxq(s, iscsiqidx) { | |
| 803 | 763 | err = request_irq(adap->msix_info[msi_index].vec, |
| 804 | 764 | t4_sge_intr_msix, 0, |
| 805 | 765 | adap->msix_info[msi_index].desc, |
| 806 | − &s->ofldrxq[ofldqidx].rspq); | |
| 766 | + &s->iscsirxq[iscsiqidx].rspq); | |
| 807 | 767 | if (err) |
| 808 | 768 | goto unwind; |
| 809 | 769 | msi_index++; |
| @@ -835,9 +795,9 @@ unwind: · 25 unmodified lines | ||
| 835 | 795 | while (--rdmaqidx >= 0) |
| 836 | 796 | free_irq(adap->msix_info[--msi_index].vec, |
| 837 | 797 | &s->rdmarxq[rdmaqidx].rspq); |
| 838 | − while (--ofldqidx >= 0) | |
| 798 | + while (--iscsiqidx >= 0) | |
| 839 | 799 | free_irq(adap->msix_info[--msi_index].vec, |
| 840 | − &s->ofldrxq[ofldqidx].rspq); | |
| 800 | + &s->iscsirxq[iscsiqidx].rspq); | |
| 841 | 801 | while (--ethqidx >= 0) |
| 842 | 802 | free_irq(adap->msix_info[--msi_index].vec, |
| 843 | 803 | &s->ethrxq[ethqidx].rspq); |
| @@ -853,8 +813,9 @@ static void free_msix_queue_irqs(struct adapter *adap) · 9 unmodified lines | ||
| 853 | 813 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); |
| 854 | 814 | for_each_ethrxq(s, i) |
| 855 | 815 | free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); |
| 856 | − for_each_ofldrxq(s, i) | |
| 857 | − free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq); | |
| 816 | + for_each_iscsirxq(s, i) | |
| 817 | + free_irq(adap->msix_info[msi_index++].vec, | |
| 818 | + &s->iscsirxq[i].rspq); | |
| 858 | 819 | for_each_rdmarxq(s, i) |
| 859 | 820 | free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq); |
| 860 | 821 | for_each_rdmaciq(s, i) |
| @@ -1093,8 +1054,8 @@ freeout: t4_free_sge_resources(adap); · 232 unmodified lines | ||
| 1093 | 1054 | } |
| 1094 | 1055 | } |
| 1095 | 1056 | |
| 1096 | − j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */ | |
| 1097 | − for_each_ofldrxq(s, i) { | |
| 1057 | + j = s->iscsiqsets / adap->params.nports; /* iscsi queues per channel */ | |
| 1058 | + for_each_iscsirxq(s, i) { | |
| 1098 | 1059 | err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], |
| 1099 | 1060 | adap->port[i / j], |
| 1100 | 1061 | s->fw_evtq.cntxt_id); |
| @@ -1110,7 +1071,7 @@ freeout: t4_free_sge_resources(adap); · 9 unmodified lines | ||
| 1110 | 1071 | msi_idx += nq; \ |
| 1111 | 1072 | } while (0) |
| 1112 | 1073 | |
| 1113 | − ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq); | |
| 1074 | + ALLOC_OFLD_RXQS(s->iscsirxq, s->iscsiqsets, j, s->iscsi_rxq); | |
| 1114 | 1075 | ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq); |
| 1115 | 1076 | j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */ |
| 1116 | 1077 | ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq); |
| @@ -1181,15 +1142,9 @@ static int set_filter_wr(struct adapter *adapter, int fidx) · 64 unmodified lines | ||
| 1181 | 1142 | */ |
| 1182 | 1143 | if (f->fs.newdmac || f->fs.newvlan) { |
| 1183 | 1144 | /* allocate L2T entry for new filter */ |
| 1184 | − f->l2t = t4_l2t_alloc_switching(adapter->l2t); | |
| 1145 | + f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan, | |
| 1146 | + f->fs.eport, f->fs.dmac); | |
| 1185 | 1147 | if (f->l2t == NULL) { |
| 1186 | − kfree_skb(skb); | |
| 1187 | − return -EAGAIN; | |
| 1188 | − } | |
| 1189 | − if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan, | |
| 1190 | − f->fs.eport, f->fs.dmac)) { | |
| 1191 | − cxgb4_l2t_release(f->l2t); | |
| 1192 | − f->l2t = NULL; | |
| 1193 | 1148 | kfree_skb(skb); |
| 1194 | 1149 | return -ENOMEM; |
| 1195 | 1150 | } |
| @@ -1511,7 +1466,7 @@ int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) · 315 unmodified lines | ||
| 1511 | 1466 | else |
| 1512 | 1467 | stid = -1; |
| 1513 | 1468 | } else { |
| 1514 | − stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2); | |
| 1469 | + stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); | |
| 1515 | 1470 | if (stid < 0) |
| 1516 | 1471 | stid = -1; |
| 1517 | 1472 | } |
| @@ -1525,7 +1480,7 @@ int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) · 7 unmodified lines | ||
| 1525 | 1480 | if (family == PF_INET) |
| 1526 | 1481 | t->stids_in_use++; |
| 1527 | 1482 | else |
| 1528 | − t->stids_in_use += 4; | |
| 1483 | + t->stids_in_use += 2; | |
| 1529 | 1484 | } |
| 1530 | 1485 | spin_unlock_bh(&t->stid_lock); |
| 1531 | 1486 | return stid; |
| @@ -1576,13 +1531,13 @@ void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) · 44 unmodified lines | ||
| 1576 | 1531 | if (family == PF_INET) |
| 1577 | 1532 | __clear_bit(stid, t->stid_bmap); |
| 1578 | 1533 | else |
| 1579 | − bitmap_release_region(t->stid_bmap, stid, 2); | |
| 1534 | + bitmap_release_region(t->stid_bmap, stid, 1); | |
| 1580 | 1535 | t->stid_tab[stid].data = NULL; |
| 1581 | 1536 | if (stid < t->nstids) { |
| 1582 | 1537 | if (family == PF_INET) |
| 1583 | 1538 | t->stids_in_use--; |
| 1584 | 1539 | else |
| 1585 | − t->stids_in_use -= 4; | |
| 1540 | + t->stids_in_use -= 2; | |
| 1586 | 1541 | } else { |
| 1587 | 1542 | t->sftids_in_use--; |
| 1588 | 1543 | } |
| @@ -2283,7 +2238,7 @@ static void disable_dbs(struct adapter *adap) · 694 unmodified lines | ||
| 2283 | 2238 | |
| 2284 | 2239 | for_each_ethrxq(&adap->sge, i) |
| 2285 | 2240 | disable_txq_db(&adap->sge.ethtxq[i].q); |
| 2286 | − for_each_ofldrxq(&adap->sge, i) | |
| 2241 | + for_each_iscsirxq(&adap->sge, i) | |
| 2287 | 2242 | disable_txq_db(&adap->sge.ofldtxq[i].q); |
| 2288 | 2243 | for_each_port(adap, i) |
| 2289 | 2244 | disable_txq_db(&adap->sge.ctrlq[i].q); |
| @@ -2295,7 +2250,7 @@ static void enable_dbs(struct adapter *adap) · 5 unmodified lines | ||
| 2295 | 2250 | |
| 2296 | 2251 | for_each_ethrxq(&adap->sge, i) |
| 2297 | 2252 | enable_txq_db(adap, &adap->sge.ethtxq[i].q); |
| 2298 | − for_each_ofldrxq(&adap->sge, i) | |
| 2253 | + for_each_iscsirxq(&adap->sge, i) | |
| 2299 | 2254 | enable_txq_db(adap, &adap->sge.ofldtxq[i].q); |
| 2300 | 2255 | for_each_port(adap, i) |
| 2301 | 2256 | enable_txq_db(adap, &adap->sge.ctrlq[i].q); |
| @@ -2365,7 +2320,7 @@ static void recover_all_queues(struct adapter *adap) · 63 unmodified lines | ||
| 2365 | 2320 | |
| 2366 | 2321 | for_each_ethrxq(&adap->sge, i) |
| 2367 | 2322 | sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); |
| 2368 | − for_each_ofldrxq(&adap->sge, i) | |
| 2323 | + for_each_iscsirxq(&adap->sge, i) | |
| 2369 | 2324 | sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q); |
| 2370 | 2325 | for_each_port(adap, i) |
| 2371 | 2326 | sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); |
| @@ -2449,10 +2404,10 @@ static void uld_attach(struct adapter *adap, unsigned int uld) · 77 unmodified lines | ||
| 2449 | 2404 | lli.nrxq = adap->sge.rdmaqs; |
| 2450 | 2405 | lli.nciq = adap->sge.rdmaciqs; |
| 2451 | 2406 | } else if (uld == CXGB4_ULD_ISCSI) { |
| 2452 | − lli.rxq_ids = adap->sge.ofld_rxq; | |
| 2453 | − lli.nrxq = adap->sge.ofldqsets; | |
| 2407 | + lli.rxq_ids = adap->sge.iscsi_rxq; | |
| 2408 | + lli.nrxq = adap->sge.iscsiqsets; | |
| 2454 | 2409 | } |
| 2455 | − lli.ntxq = adap->sge.ofldqsets; | |
| 2410 | + lli.ntxq = adap->sge.iscsiqsets; | |
| 2456 | 2411 | lli.nchan = adap->params.nports; |
| 2457 | 2412 | lli.nports = adap->params.nports; |
| 2458 | 2413 | lli.wr_cred = adap->params.ofldq_wr_cred; |
| @@ -3146,16 +3101,6 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) · 687 unmodified lines | ||
| 3146 | 3101 | if (ret < 0) |
| 3147 | 3102 | return ret; |
| 3148 | 3103 | |
| 3149 | − /* select capabilities we'll be using */ | |
| 3150 | − if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) { | |
| 3151 | − if (!vf_acls) | |
| 3152 | − c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); | |
| 3153 | − else | |
| 3154 | − c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM); | |
| 3155 | − } else if (vf_acls) { | |
| 3156 | − dev_err(adap->pdev_dev, "virtualization ACLs not supported"); | |
| 3157 | − return ret; | |
| 3158 | − } | |
| 3159 | 3104 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
| 3160 | 3105 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); |
| 3161 | 3106 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); |
| @@ -4348,11 +4293,11 @@ static void cfg_queues(struct adapter *adap) · 1186 unmodified lines | ||
| 4348 | 4293 | * capped by the number of available cores. |
| 4349 | 4294 | */ |
| 4350 | 4295 | if (n10g) { |
| 4351 | − i = min_t(int, ARRAY_SIZE(s->ofldrxq), | |
| 4296 | + i = min_t(int, ARRAY_SIZE(s->iscsirxq), | |
| 4352 | 4297 | num_online_cpus()); |
| 4353 | − s->ofldqsets = roundup(i, adap->params.nports); | |
| 4298 | + s->iscsiqsets = roundup(i, adap->params.nports); | |
| 4354 | 4299 | } else |
| 4355 | − s->ofldqsets = adap->params.nports; | |
| 4300 | + s->iscsiqsets = adap->params.nports; | |
| 4356 | 4301 | /* For RDMA one Rx queue per channel suffices */ |
| 4357 | 4302 | s->rdmaqs = adap->params.nports; |
| 4358 | 4303 | /* Try and allow at least 1 CIQ per cpu rounding down |
| @@ -4383,8 +4328,8 @@ static void cfg_queues(struct adapter *adap) · 24 unmodified lines | ||
| 4383 | 4328 | for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) |
| 4384 | 4329 | s->ofldtxq[i].q.size = 1024; |
| 4385 | 4330 | |
| 4386 | − for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) { | |
| 4387 | − struct sge_ofld_rxq *r = &s->ofldrxq[i]; | |
| 4331 | + for (i = 0; i < ARRAY_SIZE(s->iscsirxq); i++) { | |
| 4332 | + struct sge_ofld_rxq *r = &s->iscsirxq[i]; | |
| 4388 | 4333 | |
| 4389 | 4334 | init_rspq(adap, &r->rspq, 5, 1, 1024, 64); |
| 4390 | 4335 | r->rspq.uld = CXGB4_ULD_ISCSI; |
| @@ -4465,7 +4410,7 @@ static int enable_msix(struct adapter *adap) · 74 unmodified lines | ||
| 4465 | 4410 | |
| 4466 | 4411 | want = s->max_ethqsets + EXTRA_VECS; |
| 4467 | 4412 | if (is_offload(adap)) { |
| 4468 | − want += s->rdmaqs + s->rdmaciqs + s->ofldqsets; | |
| 4413 | + want += s->rdmaqs + s->rdmaciqs + s->iscsiqsets; | |
| 4469 | 4414 | /* need nchan for each possible ULD */ |
| 4470 | 4415 | ofld_need = 3 * nchan; |
| 4471 | 4416 | } |
| @@ -4504,13 +4449,13 @@ static int enable_msix(struct adapter *adap) · 32 unmodified lines | ||
| 4504 | 4449 | /* leftovers go to OFLD */ |
| 4505 | 4450 | i = allocated - EXTRA_VECS - s->max_ethqsets - |
| 4506 | 4451 | s->rdmaqs - s->rdmaciqs; |
| 4507 | − s->ofldqsets = (i / nchan) * nchan; /* round down */ | |
| 4452 | + s->iscsiqsets = (i / nchan) * nchan; /* round down */ | |
| 4508 | 4453 | } |
| 4509 | 4454 | for (i = 0; i < allocated; ++i) |
| 4510 | 4455 | adap->msix_info[i].vec = entries[i].vector; |
| 4511 | 4456 | dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " |
| 4512 | 4457 | "nic %d iscsi %d rdma cpl %d rdma ciq %d\n", |
| 4513 | − allocated, s->max_ethqsets, s->ofldqsets, s->rdmaqs, | |
| 4458 | + allocated, s->max_ethqsets, s->iscsiqsets, s->rdmaqs, | |
| 4514 | 4459 | s->rdmaciqs); |
| 4515 | 4460 | |
| 4516 | 4461 | kfree(entries); |
| @@ -4538,6 +4483,79 @@ static int init_rss(struct adapter *adap) · 21 unmodified lines | ||
| 4538 | 4483 | return 0; |
| 4539 | 4484 | } |
| 4540 | 4485 | |
| 4486 | +static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, | |
| 4487 | + enum pci_bus_speed *speed, | |
| 4488 | + enum pcie_link_width *width) | |
| 4489 | +{ | |
| 4490 | + u32 lnkcap1, lnkcap2; | |
| 4491 | + int err1, err2; | |
| 4492 | + | |
| 4493 | +#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
| 4494 | + | |
| 4495 | + *speed = PCI_SPEED_UNKNOWN; | |
| 4496 | + *width = PCIE_LNK_WIDTH_UNKNOWN; | |
| 4497 | + | |
| 4498 | + err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, | |
| 4499 | + &lnkcap1); | |
| 4500 | + err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, | |
| 4501 | + &lnkcap2); | |
| 4502 | + if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
| 4503 | + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
| 4504 | + *speed = PCIE_SPEED_8_0GT; | |
| 4505 | + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
| 4506 | + *speed = PCIE_SPEED_5_0GT; | |
| 4507 | + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
| 4508 | + *speed = PCIE_SPEED_2_5GT; | |
| 4509 | + } | |
| 4510 | + if (!err1) { | |
| 4511 | + *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
| 4512 | + if (!lnkcap2) { /* pre-r3.0 */ | |
| 4513 | + if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
| 4514 | + *speed = PCIE_SPEED_5_0GT; | |
| 4515 | + else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
| 4516 | + *speed = PCIE_SPEED_2_5GT; | |
| 4517 | + } | |
| 4518 | + } | |
| 4519 | + | |
| 4520 | + if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
| 4521 | + return err1 ? err1 : err2 ? err2 : -EINVAL; | |
| 4522 | + return 0; | |
| 4523 | +} | |
| 4524 | + | |
| 4525 | +static void cxgb4_check_pcie_caps(struct adapter *adap) | |
| 4526 | +{ | |
| 4527 | + enum pcie_link_width width, width_cap; | |
| 4528 | + enum pci_bus_speed speed, speed_cap; | |
| 4529 | + | |
| 4530 | +#define PCIE_SPEED_STR(speed) \ | |
| 4531 | + (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
| 4532 | + speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
| 4533 | + speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
| 4534 | + "Unknown") | |
| 4535 | + | |
| 4536 | + if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { | |
| 4537 | + dev_warn(adap->pdev_dev, | |
| 4538 | + "Unable to determine PCIe device BW capabilities\n"); | |
| 4539 | + return; | |
| 4540 | + } | |
| 4541 | + | |
| 4542 | + if (pcie_get_minimum_link(adap->pdev, &speed, &width) || | |
| 4543 | + speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
| 4544 | + dev_warn(adap->pdev_dev, | |
| 4545 | + "Unable to determine PCI Express bandwidth.\n"); | |
| 4546 | + return; | |
| 4547 | + } | |
| 4548 | + | |
| 4549 | + dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", | |
| 4550 | + PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
| 4551 | + dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", | |
| 4552 | + width, width_cap); | |
| 4553 | + if (speed < speed_cap || width < width_cap) | |
| 4554 | + dev_info(adap->pdev_dev, | |
| 4555 | + "A slot with more lanes and/or higher speed is " | |
| 4556 | + "suggested for optimal performance.\n"); | |
| 4557 | +} | |
| 4558 | + | |
| 4541 | 4559 | static void print_port_info(const struct net_device *dev) |
| 4542 | 4560 | { |
| 4543 | 4561 | char buf[80]; |
| @@ -4565,10 +4583,10 @@ static void print_port_info(const struct net_device *dev) · 21 unmodified lines | ||
| 4565 | 4583 | --bufp; |
| 4566 | 4584 | sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); |
| 4567 | 4585 | |
| 4568 | − netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n", | |
| 4586 | + netdev_info(dev, "Chelsio %s rev %d %s %sNIC %s\n", | |
| 4569 | 4587 | adap->params.vpd.id, |
| 4570 | 4588 | CHELSIO_CHIP_RELEASE(adap->params.chip), buf, |
| 4571 | − is_offload(adap) ? "R" : "", adap->params.pci.width, spd, | |
| 4589 | + is_offload(adap) ? "R" : "", | |
| 4572 | 4590 | (adap->flags & USING_MSIX) ? " MSI-X" : |
| 4573 | 4591 | (adap->flags & USING_MSI) ? " MSI" : ""); |
| 4574 | 4592 | netdev_info(dev, "S/N: %s, P/N: %s\n", |
| @@ -4787,8 +4805,9 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 212 unmodified lines | ||
| 4787 | 4805 | |
| 4788 | 4806 | /* configure SGE_STAT_CFG_A to read WC stats */ |
| 4789 | 4807 | if (!is_t4(adapter->params.chip)) |
| 4790 | − t4_write_reg(adapter, SGE_STAT_CFG_A, | |
| 4791 | − STATSOURCE_T5_V(7) | STATMODE_V(0)); | |
| 4808 | + t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | | |
| 4809 | + (is_t5(adapter->params.chip) ? STATMODE_V(0) : | |
| 4810 | + T6_STATMODE_V(0))); | |
| 4792 | 4811 | |
| 4793 | 4812 | for_each_port(adapter, i) { |
| 4794 | 4813 | struct net_device *netdev; |
| @@ -4865,15 +4884,25 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 70 unmodified lines | ||
| 4865 | 4884 | } |
| 4866 | 4885 | |
| 4867 | 4886 | #if IS_ENABLED(CONFIG_IPV6) |
| 4868 | − adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
| 4869 | − adapter->clipt_end); | |
| 4870 | − if (!adapter->clipt) { | |
| 4871 | − /* We tolerate a lack of clip_table, giving up | |
| 4872 | − * some functionality | |
| 4887 | + if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && | |
| 4888 | + (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { | |
| 4889 | + /* CLIP functionality is not present in hardware, | |
| 4890 | + * hence disable all offload features | |
| 4873 | 4891 | */ |
| 4874 | 4892 | dev_warn(&pdev->dev, |
| 4875 | − "could not allocate Clip table, continuing\n"); | |
| 4893 | + "CLIP not enabled in hardware, continuing\n"); | |
| 4876 | 4894 | adapter->params.offload = 0; |
| 4895 | + } else { | |
| 4896 | + adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
| 4897 | + adapter->clipt_end); | |
| 4898 | + if (!adapter->clipt) { | |
| 4899 | + /* We tolerate a lack of clip_table, giving up | |
| 4900 | + * some functionality | |
| 4901 | + */ | |
| 4902 | + dev_warn(&pdev->dev, | |
| 4903 | + "could not allocate Clip table, continuing\n"); | |
| 4904 | + adapter->params.offload = 0; | |
| 4905 | + } | |
| 4877 | 4906 | } |
| 4878 | 4907 | #endif |
| 4879 | 4908 | if (is_offload(adapter) && tid_init(&adapter->tids) < 0) { |
| @@ -4904,6 +4933,9 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 24 unmodified lines | ||
| 4904 | 4933 | else if (msi > 0 && pci_enable_msi(pdev) == 0) |
| 4905 | 4934 | adapter->flags |= USING_MSI; |
| 4906 | 4935 | |
| 4936 | + /* check for PCI Express bandwidth capabiltites */ | |
| 4937 | + cxgb4_check_pcie_caps(adapter); | |
| 4938 | + | |
| 4907 | 4939 | err = init_rss(adapter); |
| 4908 | 4940 | if (err) |
| 4909 | 4941 | goto out_free_dev; |
| @@ -66,7 +66,7 @@ struct l2t_data { · 65 unmodified lines | ||
| 66 | 66 | |
| 67 | 67 | static inline unsigned int vlan_prio(const struct l2t_entry *e) |
| 68 | 68 | { |
| 69 | − return e->vlan >> 13; | |
| 69 | + return e->vlan >> VLAN_PRIO_SHIFT; | |
| 70 | 70 | } |
| 71 | 71 | |
| 72 | 72 | static inline void l2t_hold(struct l2t_data *d, struct l2t_entry *e) |
| @@ -161,8 +161,7 @@ static int write_l2e(struct adapter *adap, struct l2t_entry *e, int sync) · 88 unmodified lines | ||
| 161 | 161 | memcpy(e->dmac, e->neigh->ha, sizeof(e->dmac)); |
| 162 | 162 | memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac)); |
| 163 | 163 | |
| 164 | − set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); | |
| 165 | − t4_ofld_send(adap, skb); | |
| 164 | + t4_mgmt_tx(adap, skb); | |
| 166 | 165 | |
| 167 | 166 | if (sync && e->state != L2T_STATE_SWITCHING) |
| 168 | 167 | e->state = L2T_STATE_SYNC_WRITE; |
| @@ -175,14 +174,10 @@ static int write_l2e(struct adapter *adap, struct l2t_entry *e, int sync) · 6 unmodified lines | ||
| 175 | 174 | */ |
| 176 | 175 | static void send_pending(struct adapter *adap, struct l2t_entry *e) |
| 177 | 176 | { |
| 178 | − while (e->arpq_head) { | |
| 179 | − struct sk_buff *skb = e->arpq_head; | |
| 177 | + struct sk_buff *skb; | |
| 180 | 178 | |
| 181 | − e->arpq_head = skb->next; | |
| 182 | − skb->next = NULL; | |
| 179 | + while ((skb = __skb_dequeue(&e->arpq)) != NULL) | |
| 183 | 180 | t4_ofld_send(adap, skb); |
| 184 | − } | |
| 185 | − e->arpq_tail = NULL; | |
| 186 | 181 | } |
| 187 | 182 | |
| 188 | 183 | /* |
| @@ -222,12 +217,7 @@ void do_l2t_write_rpl(struct adapter *adap, const struct cpl_l2t_write_rpl *rpl) · 33 unmodified lines | ||
| 222 | 217 | */ |
| 223 | 218 | static inline void arpq_enqueue(struct l2t_entry *e, struct sk_buff *skb) |
| 224 | 219 | { |
| 225 | − skb->next = NULL; | |
| 226 | − if (e->arpq_head) | |
| 227 | − e->arpq_tail->next = skb; | |
| 228 | − else | |
| 229 | − e->arpq_head = skb; | |
| 230 | − e->arpq_tail = skb; | |
| 220 | + __skb_queue_tail(&e->arpq, skb); | |
| 231 | 221 | } |
| 232 | 222 | |
| 233 | 223 | int cxgb4_l2t_send(struct net_device *dev, struct sk_buff *skb, |
| @@ -259,7 +249,8 @@ again: · 25 unmodified lines | ||
| 259 | 249 | if (e->state == L2T_STATE_RESOLVING && |
| 260 | 250 | !neigh_event_send(e->neigh, NULL)) { |
| 261 | 251 | spin_lock_bh(&e->lock); |
| 262 | − if (e->state == L2T_STATE_RESOLVING && e->arpq_head) | |
| 252 | + if (e->state == L2T_STATE_RESOLVING && | |
| 253 | + !skb_queue_empty(&e->arpq)) | |
| 263 | 254 | write_l2e(adap, e, 1); |
| 264 | 255 | spin_unlock_bh(&e->lock); |
| 265 | 256 | } |
| @@ -305,12 +296,82 @@ found: · 39 unmodified lines | ||
| 305 | 296 | return e; |
| 306 | 297 | } |
| 307 | 298 | |
| 308 | −/* | |
| 309 | − * Called when an L2T entry has no more users. | |
| 299 | +static struct l2t_entry *find_or_alloc_l2e(struct l2t_data *d, u16 vlan, | |
| 300 | + u8 port, u8 *dmac) | |
| 301 | +{ | |
| 302 | + struct l2t_entry *end, *e, **p; | |
| 303 | + struct l2t_entry *first_free = NULL; | |
| 304 | + | |
| 305 | + for (e = &d->l2tab[0], end = &d->l2tab[d->l2t_size]; e != end; ++e) { | |
| 306 | + if (atomic_read(&e->refcnt) == 0) { | |
| 307 | + if (!first_free) | |
| 308 | + first_free = e; | |
| 309 | + } else { | |
| 310 | + if (e->state == L2T_STATE_SWITCHING) { | |
| 311 | + if (ether_addr_equal(e->dmac, dmac) && | |
| 312 | + (e->vlan == vlan) && (e->lport == port)) | |
| 313 | + goto exists; | |
| 314 | + } | |
| 315 | + } | |
| 316 | + } | |
| 317 | + | |
| 318 | + if (first_free) { | |
| 319 | + e = first_free; | |
| 320 | + goto found; | |
| 321 | + } | |
| 322 | + | |
| 323 | + return NULL; | |
| 324 | + | |
| 325 | +found: | |
| 326 | + /* The entry we found may be an inactive entry that is | |
| 327 | + * presently in the hash table. We need to remove it. | |
| 328 | + */ | |
| 329 | + if (e->state < L2T_STATE_SWITCHING) | |
| 330 | + for (p = &d->l2tab[e->hash].first; *p; p = &(*p)->next) | |
| 331 | + if (*p == e) { | |
| 332 | + *p = e->next; | |
| 333 | + e->next = NULL; | |
| 334 | + break; | |
| 335 | + } | |
| 336 | + e->state = L2T_STATE_UNUSED; | |
| 337 | + | |
| 338 | +exists: | |
| 339 | + return e; | |
| 340 | +} | |
| 341 | + | |
| 342 | +/* Called when an L2T entry has no more users. The entry is left in the hash | |
| 343 | + * table since it is likely to be reused but we also bump nfree to indicate | |
| 344 | + * that the entry can be reallocated for a different neighbor. We also drop | |
| 345 | + * the existing neighbor reference in case the neighbor is going away and is | |
| 346 | + * waiting on our reference. | |
| 347 | + * | |
| 348 | + * Because entries can be reallocated to other neighbors once their ref count | |
| 349 | + * drops to 0 we need to take the entry's lock to avoid races with a new | |
| 350 | + * incarnation. | |
| 310 | 351 | */ |
| 352 | +static void _t4_l2e_free(struct l2t_entry *e) | |
| 353 | +{ | |
| 354 | + struct l2t_data *d; | |
| 355 | + struct sk_buff *skb; | |
| 356 | + | |
| 357 | + if (atomic_read(&e->refcnt) == 0) { /* hasn't been recycled */ | |
| 358 | + if (e->neigh) { | |
| 359 | + neigh_release(e->neigh); | |
| 360 | + e->neigh = NULL; | |
| 361 | + } | |
| 362 | + while ((skb = __skb_dequeue(&e->arpq)) != NULL) | |
| 363 | + kfree_skb(skb); | |
| 364 | + } | |
| 365 | + | |
| 366 | + d = container_of(e, struct l2t_data, l2tab[e->idx]); | |
| 367 | + atomic_inc(&d->nfree); | |
| 368 | +} | |
| 369 | + | |
| 370 | +/* Locked version of _t4_l2e_free */ | |
| 311 | 371 | static void t4_l2e_free(struct l2t_entry *e) |
| 312 | 372 | { |
| 313 | 373 | struct l2t_data *d; |
| 374 | + struct sk_buff *skb; | |
| 314 | 375 | |
| 315 | 376 | spin_lock_bh(&e->lock); |
| 316 | 377 | if (atomic_read(&e->refcnt) == 0) { /* hasn't been recycled */ |
| @@ -318,13 +379,8 @@ static void t4_l2e_free(struct l2t_entry *e) · 1 unmodified line | ||
| 318 | 379 | neigh_release(e->neigh); |
| 319 | 380 | e->neigh = NULL; |
| 320 | 381 | } |
| 321 | − while (e->arpq_head) { | |
| 322 | − struct sk_buff *skb = e->arpq_head; | |
| 323 | − | |
| 324 | − e->arpq_head = skb->next; | |
| 382 | + while ((skb = __skb_dequeue(&e->arpq)) != NULL) | |
| 325 | 383 | kfree_skb(skb); |
| 326 | − } | |
| 327 | − e->arpq_tail = NULL; | |
| 328 | 384 | } |
| 329 | 385 | spin_unlock_bh(&e->lock); |
| 330 | 386 | |
| @@ -457,18 +513,19 @@ EXPORT_SYMBOL(cxgb4_select_ntuple); · 126 unmodified lines | ||
| 457 | 513 | * on the arpq head. If a packet specifies a failure handler it is invoked, |
| 458 | 514 | * otherwise the packet is sent to the device. |
| 459 | 515 | */ |
| 460 | −static void handle_failed_resolution(struct adapter *adap, struct sk_buff *arpq) | |
| 516 | +static void handle_failed_resolution(struct adapter *adap, struct l2t_entry *e) | |
| 461 | 517 | { |
| 462 | − while (arpq) { | |
| 463 | − struct sk_buff *skb = arpq; | |
| 518 | + struct sk_buff *skb; | |
| 519 | + | |
| 520 | + while ((skb = __skb_dequeue(&e->arpq)) != NULL) { | |
| 464 | 521 | const struct l2t_skb_cb *cb = L2T_SKB_CB(skb); |
| 465 | 522 | |
| 466 | − arpq = skb->next; | |
| 467 | − skb->next = NULL; | |
| 523 | + spin_unlock(&e->lock); | |
| 468 | 524 | if (cb->arp_err_handler) |
| 469 | 525 | cb->arp_err_handler(cb->handle, skb); |
| 470 | 526 | else |
| 471 | 527 | t4_ofld_send(adap, skb); |
| 528 | + spin_lock(&e->lock); | |
| 472 | 529 | } |
| 473 | 530 | } |
| 474 | 531 | |
| @@ -479,7 +536,7 @@ static void handle_failed_resolution(struct adapter *adap, struct sk_buff *arpq) · 4 unmodified lines | ||
| 479 | 536 | void t4_l2t_update(struct adapter *adap, struct neighbour *neigh) |
| 480 | 537 | { |
| 481 | 538 | struct l2t_entry *e; |
| 482 | − struct sk_buff *arpq = NULL; | |
| 539 | + struct sk_buff_head *arpq = NULL; | |
| 483 | 540 | struct l2t_data *d = adap->l2t; |
| 484 | 541 | int addr_len = neigh->tbl->key_len; |
| 485 | 542 | u32 *addr = (u32 *) neigh->primary_key; |
| @@ -506,10 +563,9 @@ void t4_l2t_update(struct adapter *adap, struct neighbour *neigh) · 20 unmodified lines | ||
| 506 | 563 | |
| 507 | 564 | if (e->state == L2T_STATE_RESOLVING) { |
| 508 | 565 | if (neigh->nud_state & NUD_FAILED) { |
| 509 | − arpq = e->arpq_head; | |
| 510 | − e->arpq_head = e->arpq_tail = NULL; | |
| 566 | + arpq = &e->arpq; | |
| 511 | 567 | } else if ((neigh->nud_state & (NUD_CONNECTED | NUD_STALE)) && |
| 512 | − e->arpq_head) { | |
| 568 | + !skb_queue_empty(&e->arpq)) { | |
| 513 | 569 | write_l2e(adap, e, 1); |
| 514 | 570 | } |
| 515 | 571 | } else { |
| @@ -519,43 +575,66 @@ void t4_l2t_update(struct adapter *adap, struct neighbour *neigh) · 3 unmodified lines | ||
| 519 | 575 | write_l2e(adap, e, 0); |
| 520 | 576 | } |
| 521 | 577 | |
| 522 | − spin_unlock_bh(&e->lock); | |
| 523 | − | |
| 524 | 578 | if (arpq) |
| 525 | − handle_failed_resolution(adap, arpq); | |
| 579 | + handle_failed_resolution(adap, e); | |
| 580 | + spin_unlock_bh(&e->lock); | |
| 526 | 581 | } |
| 527 | 582 | |
| 528 | 583 | /* Allocate an L2T entry for use by a switching rule. Such need to be |
| 529 | 584 | * explicitly freed and while busy they are not on any hash chain, so normal |
| 530 | 585 | * address resolution updates do not see them. |
| 531 | 586 | */ |
| 532 | −struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *d) | |
| 587 | +struct l2t_entry *t4_l2t_alloc_switching(struct adapter *adap, u16 vlan, | |
| 588 | + u8 port, u8 *eth_addr) | |
| 533 | 589 | { |
| 590 | + struct l2t_data *d = adap->l2t; | |
| 534 | 591 | struct l2t_entry *e; |
| 592 | + int ret; | |
| 535 | 593 | |
| 536 | 594 | write_lock_bh(&d->lock); |
| 537 | − e = alloc_l2e(d); | |
| 595 | + e = find_or_alloc_l2e(d, vlan, port, eth_addr); | |
| 538 | 596 | if (e) { |
| 539 | 597 | spin_lock(&e->lock); /* avoid race with t4_l2t_free */ |
| 540 | − e->state = L2T_STATE_SWITCHING; | |
| 541 | − atomic_set(&e->refcnt, 1); | |
| 598 | + if (!atomic_read(&e->refcnt)) { | |
| 599 | + e->state = L2T_STATE_SWITCHING; | |
| 600 | + e->vlan = vlan; | |
| 601 | + e->lport = port; | |
| 602 | + ether_addr_copy(e->dmac, eth_addr); | |
| 603 | + atomic_set(&e->refcnt, 1); | |
| 604 | + ret = write_l2e(adap, e, 0); | |
| 605 | + if (ret < 0) { | |
| 606 | + _t4_l2e_free(e); | |
| 607 | + spin_unlock(&e->lock); | |
| 608 | + write_unlock_bh(&d->lock); | |
| 609 | + return NULL; | |
| 610 | + } | |
| 611 | + } else { | |
| 612 | + atomic_inc(&e->refcnt); | |
| 613 | + } | |
| 614 | + | |
| 542 | 615 | spin_unlock(&e->lock); |
| 543 | 616 | } |
| 544 | 617 | write_unlock_bh(&d->lock); |
| 545 | 618 | return e; |
| 546 | 619 | } |
| 547 | 620 | |
| 548 | −/* Sets/updates the contents of a switching L2T entry that has been allocated | |
| 549 | − * with an earlier call to @t4_l2t_alloc_switching. | |
| 621 | +/** | |
| 622 | + * @dev: net_device pointer | |
| 623 | + * @vlan: VLAN Id | |
| 624 | + * @port: Associated port | |
| 625 | + * @dmac: Destination MAC address to add to L2T | |
| 626 | + * Returns pointer to the allocated l2t entry | |
| 627 | + * | |
| 628 | + * Allocates an L2T entry for use by switching rule of a filter | |
| 550 | 629 | */ |
| 551 | −int t4_l2t_set_switching(struct adapter *adap, struct l2t_entry *e, u16 vlan, | |
| 552 | − u8 port, u8 *eth_addr) | |
| 630 | +struct l2t_entry *cxgb4_l2t_alloc_switching(struct net_device *dev, u16 vlan, | |
| 631 | + u8 port, u8 *dmac) | |
| 553 | 632 | { |
| 554 | − e->vlan = vlan; | |
| 555 | − e->lport = port; | |
| 556 | − memcpy(e->dmac, eth_addr, ETH_ALEN); | |
| 557 | − return write_l2e(adap, e, 0); | |
| 633 | + struct adapter *adap = netdev2adap(dev); | |
| 634 | + | |
| 635 | + return t4_l2t_alloc_switching(adap, vlan, port, dmac); | |
| 558 | 636 | } |
| 637 | +EXPORT_SYMBOL(cxgb4_l2t_alloc_switching); | |
| 559 | 638 | |
| 560 | 639 | struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end) |
| 561 | 640 | { |
| @@ -585,6 +664,7 @@ struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end) · 23 unmodified lines | ||
| 585 | 664 | d->l2tab[i].state = L2T_STATE_UNUSED; |
| 586 | 665 | spin_lock_init(&d->l2tab[i].lock); |
| 587 | 666 | atomic_set(&d->l2tab[i].refcnt, 0); |
| 667 | + skb_queue_head_init(&d->l2tab[i].arpq); | |
| 588 | 668 | } |
| 589 | 669 | return d; |
| 590 | 670 | } |
| @@ -619,7 +699,8 @@ static char l2e_state(const struct l2t_entry *e) · 28 unmodified lines | ||
| 619 | 699 | case L2T_STATE_VALID: return 'V'; |
| 620 | 700 | case L2T_STATE_STALE: return 'S'; |
| 621 | 701 | case L2T_STATE_SYNC_WRITE: return 'W'; |
| 622 | − case L2T_STATE_RESOLVING: return e->arpq_head ? 'A' : 'R'; | |
| 702 | + case L2T_STATE_RESOLVING: | |
| 703 | + return skb_queue_empty(&e->arpq) ? 'R' : 'A'; | |
| 623 | 704 | case L2T_STATE_SWITCHING: return 'X'; |
| 624 | 705 | default: |
| 625 | 706 | return 'U'; |
| @@ -76,8 +76,7 @@ struct l2t_entry { · 75 unmodified lines | ||
| 76 | 76 | struct neighbour *neigh; /* associated neighbour */ |
| 77 | 77 | struct l2t_entry *first; /* start of hash chain */ |
| 78 | 78 | struct l2t_entry *next; /* next l2t_entry on chain */ |
| 79 | − struct sk_buff *arpq_head; /* queue of packets awaiting resolution */ | |
| 80 | − struct sk_buff *arpq_tail; | |
| 79 | + struct sk_buff_head arpq; /* packet queue awaiting resolution */ | |
| 81 | 80 | spinlock_t lock; |
| 82 | 81 | atomic_t refcnt; /* entry reference count */ |
| 83 | 82 | u16 hash; /* hash bucket the entry is on */ |
| @@ -114,10 +113,11 @@ struct l2t_entry *cxgb4_l2t_get(struct l2t_data *d, struct neighbour *neigh, · 30 unmodified lines | ||
| 114 | 113 | unsigned int priority); |
| 115 | 114 | u64 cxgb4_select_ntuple(struct net_device *dev, |
| 116 | 115 | const struct l2t_entry *l2t); |
| 116 | +struct l2t_entry *cxgb4_l2t_alloc_switching(struct net_device *dev, u16 vlan, | |
| 117 | + u8 port, u8 *dmac); | |
| 117 | 118 | void t4_l2t_update(struct adapter *adap, struct neighbour *neigh); |
| 118 | −struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *d); | |
| 119 | −int t4_l2t_set_switching(struct adapter *adap, struct l2t_entry *e, u16 vlan, | |
| 120 | − u8 port, u8 *eth_addr); | |
| 119 | +struct l2t_entry *t4_l2t_alloc_switching(struct adapter *adap, u16 vlan, | |
| 120 | + u8 port, u8 *dmac); | |
| 121 | 121 | struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end); |
| 122 | 122 | void do_l2t_write_rpl(struct adapter *p, const struct cpl_l2t_write_rpl *rpl); |
| 123 | 123 | |
| @@ -406,7 +406,7 @@ static void free_tx_desc(struct adapter *adap, struct sge_txq *q, · 405 unmodified lines | ||
| 406 | 406 | */ |
| 407 | 407 | static inline int reclaimable(const struct sge_txq *q) |
| 408 | 408 | { |
| 409 | − int hw_cidx = ntohs(q->stat->cidx); | |
| 409 | + int hw_cidx = ntohs(ACCESS_ONCE(q->stat->cidx)); | |
| 410 | 410 | hw_cidx -= q->cidx; |
| 411 | 411 | return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx; |
| 412 | 412 | } |
| @@ -613,6 +613,7 @@ static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n, · 200 unmodified lines | ||
| 613 | 613 | PCI_DMA_FROMDEVICE); |
| 614 | 614 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { |
| 615 | 615 | __free_pages(pg, s->fl_pg_order); |
| 616 | + q->mapping_err++; | |
| 616 | 617 | goto out; /* do not try small pages for this error */ |
| 617 | 618 | } |
| 618 | 619 | mapping |= RX_LARGE_PG_BUF; |
| @@ -642,6 +643,7 @@ alloc_small_pages: · 23 unmodified lines | ||
| 642 | 643 | PCI_DMA_FROMDEVICE); |
| 643 | 644 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { |
| 644 | 645 | put_page(pg); |
| 646 | + q->mapping_err++; | |
| 645 | 647 | goto out; |
| 646 | 648 | } |
| 647 | 649 | *d++ = cpu_to_be64(mapping); |
| @@ -663,6 +665,7 @@ out: cred = q->avail - cred; · 15 unmodified lines | ||
| 663 | 665 | |
| 664 | 666 | if (unlikely(fl_starving(adap, q))) { |
| 665 | 667 | smp_wmb(); |
| 668 | + q->low++; | |
| 666 | 669 | set_bit(q->cntxt_id - adap->sge.egr_start, |
| 667 | 670 | adap->sge.starving_fl); |
| 668 | 671 | } |
| @@ -1029,6 +1032,30 @@ static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, · 360 unmodified lines | ||
| 1029 | 1032 | *p = 0; |
| 1030 | 1033 | } |
| 1031 | 1034 | |
| 1035 | +static void *inline_tx_skb_header(const struct sk_buff *skb, | |
| 1036 | + const struct sge_txq *q, void *pos, | |
| 1037 | + int length) | |
| 1038 | +{ | |
| 1039 | + u64 *p; | |
| 1040 | + int left = (void *)q->stat - pos; | |
| 1041 | + | |
| 1042 | + if (likely(length <= left)) { | |
| 1043 | + memcpy(pos, skb->data, length); | |
| 1044 | + pos += length; | |
| 1045 | + } else { | |
| 1046 | + memcpy(pos, skb->data, left); | |
| 1047 | + memcpy(q->desc, skb->data + left, length - left); | |
| 1048 | + pos = (void *)q->desc + (length - left); | |
| 1049 | + } | |
| 1050 | + /* 0-pad to multiple of 16 */ | |
| 1051 | + p = PTR_ALIGN(pos, 8); | |
| 1052 | + if ((uintptr_t)p & 8) { | |
| 1053 | + *p = 0; | |
| 1054 | + return p + 1; | |
| 1055 | + } | |
| 1056 | + return p; | |
| 1057 | +} | |
| 1058 | + | |
| 1032 | 1059 | /* |
| 1033 | 1060 | * Figure out what HW csum a packet wants and return the appropriate control |
| 1034 | 1061 | * bits. |
| @@ -1320,7 +1347,7 @@ out_free: dev_kfree_skb_any(skb); · 285 unmodified lines | ||
| 1320 | 1347 | */ |
| 1321 | 1348 | static inline void reclaim_completed_tx_imm(struct sge_txq *q) |
| 1322 | 1349 | { |
| 1323 | − int hw_cidx = ntohs(q->stat->cidx); | |
| 1350 | + int hw_cidx = ntohs(ACCESS_ONCE(q->stat->cidx)); | |
| 1324 | 1351 | int reclaim = hw_cidx - q->cidx; |
| 1325 | 1352 | |
| 1326 | 1353 | if (reclaim < 0) |
| @@ -1542,24 +1569,50 @@ static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb) · 215 unmodified lines | ||
| 1542 | 1569 | } |
| 1543 | 1570 | |
| 1544 | 1571 | /** |
| 1545 | − * service_ofldq - restart a suspended offload queue | |
| 1572 | + * service_ofldq - service/restart a suspended offload queue | |
| 1546 | 1573 | * @q: the offload queue |
| 1547 | 1574 | * |
| 1548 | − * Services an offload Tx queue by moving packets from its packet queue | |
| 1549 | − * to the HW Tx ring. The function starts and ends with the queue locked. | |
| 1575 | + * Services an offload Tx queue by moving packets from its Pending Send | |
| 1576 | + * Queue to the Hardware TX ring. The function starts and ends with the | |
| 1577 | + * Send Queue locked, but drops the lock while putting the skb at the | |
| 1578 | + * head of the Send Queue onto the Hardware TX Ring. Dropping the lock | |
| 1579 | + * allows more skbs to be added to the Send Queue by other threads. | |
| 1580 | + * The packet being processed at the head of the Pending Send Queue is | |
| 1581 | + * left on the queue in case we experience DMA Mapping errors, etc. | |
| 1582 | + * and need to give up and restart later. | |
| 1583 | + * | |
| 1584 | + * service_ofldq() can be thought of as a task which opportunistically | |
| 1585 | + * uses other threads execution contexts. We use the Offload Queue | |
| 1586 | + * boolean "service_ofldq_running" to make sure that only one instance | |
| 1587 | + * is ever running at a time ... | |
| 1550 | 1588 | */ |
| 1551 | 1589 | static void service_ofldq(struct sge_ofld_txq *q) |
| 1552 | 1590 | { |
| 1553 | − u64 *pos; | |
| 1591 | + u64 *pos, *before, *end; | |
| 1554 | 1592 | int credits; |
| 1555 | 1593 | struct sk_buff *skb; |
| 1594 | + struct sge_txq *txq; | |
| 1595 | + unsigned int left; | |
| 1556 | 1596 | unsigned int written = 0; |
| 1557 | 1597 | unsigned int flits, ndesc; |
| 1558 | 1598 | |
| 1599 | + /* If another thread is currently in service_ofldq() processing the | |
| 1600 | + * Pending Send Queue then there's nothing to do. Otherwise, flag | |
| 1601 | + * that we're doing the work and continue. Examining/modifying | |
| 1602 | + * the Offload Queue boolean "service_ofldq_running" must be done | |
| 1603 | + * while holding the Pending Send Queue Lock. | |
| 1604 | + */ | |
| 1605 | + if (q->service_ofldq_running) | |
| 1606 | + return; | |
| 1607 | + q->service_ofldq_running = true; | |
| 1608 | + | |
| 1559 | 1609 | while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) { |
| 1560 | − /* | |
| 1561 | − * We drop the lock but leave skb on sendq, thus retaining | |
| 1562 | − * exclusive access to the state of the queue. | |
| 1610 | + /* We drop the lock while we're working with the skb at the | |
| 1611 | + * head of the Pending Send Queue. This allows more skbs to | |
| 1612 | + * be added to the Pending Send Queue while we're working on | |
| 1613 | + * this one. We don't need to lock to guard the TX Ring | |
| 1614 | + * updates because only one thread of execution is ever | |
| 1615 | + * allowed into service_ofldq() at a time. | |
| 1563 | 1616 | */ |
| 1564 | 1617 | spin_unlock(&q->sendq.lock); |
| 1565 | 1618 | |
| @@ -1583,9 +1636,32 @@ static void service_ofldq(struct sge_ofld_txq *q) · 17 unmodified lines | ||
| 1583 | 1636 | } else { |
| 1584 | 1637 | int last_desc, hdr_len = skb_transport_offset(skb); |
| 1585 | 1638 | |
| 1586 | − memcpy(pos, skb->data, hdr_len); | |
| 1587 | − write_sgl(skb, &q->q, (void *)pos + hdr_len, | |
| 1588 | − pos + flits, hdr_len, | |
| 1639 | + /* The WR headers may not fit within one descriptor. | |
| 1640 | + * So we need to deal with wrap-around here. | |
| 1641 | + */ | |
| 1642 | + before = (u64 *)pos; | |
| 1643 | + end = (u64 *)pos + flits; | |
| 1644 | + txq = &q->q; | |
| 1645 | + pos = (void *)inline_tx_skb_header(skb, &q->q, | |
| 1646 | + (void *)pos, | |
| 1647 | + hdr_len); | |
| 1648 | + if (before > (u64 *)pos) { | |
| 1649 | + left = (u8 *)end - (u8 *)txq->stat; | |
| 1650 | + end = (void *)txq->desc + left; | |
| 1651 | + } | |
| 1652 | + | |
| 1653 | + /* If current position is already at the end of the | |
| 1654 | + * ofld queue, reset the current to point to | |
| 1655 | + * start of the queue and update the end ptr as well. | |
| 1656 | + */ | |
| 1657 | + if (pos == (u64 *)txq->stat) { | |
| 1658 | + left = (u8 *)end - (u8 *)txq->stat; | |
| 1659 | + end = (void *)txq->desc + left; | |
| 1660 | + pos = (void *)txq->desc; | |
| 1661 | + } | |
| 1662 | + | |
| 1663 | + write_sgl(skb, &q->q, (void *)pos, | |
| 1664 | + end, hdr_len, | |
| 1589 | 1665 | (dma_addr_t *)skb->head); |
| 1590 | 1666 | #ifdef CONFIG_NEED_DMA_MAP_STATE |
| 1591 | 1667 | skb->dev = q->adap->port[0]; |
| @@ -1604,6 +1680,11 @@ static void service_ofldq(struct sge_ofld_txq *q) · 12 unmodified lines | ||
| 1604 | 1680 | written = 0; |
| 1605 | 1681 | } |
| 1606 | 1682 | |
| 1683 | + /* Reacquire the Pending Send Queue Lock so we can unlink the | |
| 1684 | + * skb we've just successfully transferred to the TX Ring and | |
| 1685 | + * loop for the next skb which may be at the head of the | |
| 1686 | + * Pending Send Queue. | |
| 1687 | + */ | |
| 1607 | 1688 | spin_lock(&q->sendq.lock); |
| 1608 | 1689 | __skb_unlink(skb, &q->sendq); |
| 1609 | 1690 | if (is_ofld_imm(skb)) |
| @@ -1611,6 +1692,11 @@ static void service_ofldq(struct sge_ofld_txq *q) · 1 unmodified line | ||
| 1611 | 1692 | } |
| 1612 | 1693 | if (likely(written)) |
| 1613 | 1694 | ring_tx_db(q->adap, &q->q, written); |
| 1695 | + | |
| 1696 | + /*Indicate that no thread is processing the Pending Send Queue | |
| 1697 | + * currently. | |
| 1698 | + */ | |
| 1699 | + q->service_ofldq_running = false; | |
| 1614 | 1700 | } |
| 1615 | 1701 | |
| 1616 | 1702 | /** |
| @@ -1624,9 +1710,19 @@ static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb) · 7 unmodified lines | ||
| 1624 | 1710 | { |
| 1625 | 1711 | skb->priority = calc_tx_flits_ofld(skb); /* save for restart */ |
| 1626 | 1712 | spin_lock(&q->sendq.lock); |
| 1713 | + | |
| 1714 | + /* Queue the new skb onto the Offload Queue's Pending Send Queue. If | |
| 1715 | + * that results in this new skb being the only one on the queue, start | |
| 1716 | + * servicing it. If there are other skbs already on the list, then | |
| 1717 | + * either the queue is currently being processed or it's been stopped | |
| 1718 | + * for some reason and it'll be restarted at a later time. Restart | |
| 1719 | + * paths are triggered by events like experiencing a DMA Mapping Error | |
| 1720 | + * or filling the Hardware TX Ring. | |
| 1721 | + */ | |
| 1627 | 1722 | __skb_queue_tail(&q->sendq, skb); |
| 1628 | 1723 | if (q->sendq.qlen == 1) |
| 1629 | 1724 | service_ofldq(q); |
| 1725 | + | |
| 1630 | 1726 | spin_unlock(&q->sendq.lock); |
| 1631 | 1727 | return NET_XMIT_SUCCESS; |
| 1632 | 1728 | } |
| @@ -1864,7 +1960,6 @@ static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, · 231 unmodified lines | ||
| 1864 | 1960 | skb->truesize += skb->data_len; |
| 1865 | 1961 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1866 | 1962 | skb_record_rx_queue(skb, rxq->rspq.idx); |
| 1867 | − skb_mark_napi_id(skb, &rxq->rspq.napi); | |
| 1868 | 1963 | pi = netdev_priv(skb->dev); |
| 1869 | 1964 | if (pi->rxtstamp) |
| 1870 | 1965 | cxgb4_sgetim_to_hwtstamp(adapter, skb_hwtstamps(skb), |
| @@ -2193,7 +2288,7 @@ static int napi_rx_handler(struct napi_struct *napi, int budget) · 322 unmodified lines | ||
| 2193 | 2288 | if (likely(work_done < budget)) { |
| 2194 | 2289 | int timer_index; |
| 2195 | 2290 | |
| 2196 | − napi_complete(napi); | |
| 2291 | + napi_complete_done(napi, work_done); | |
| 2197 | 2292 | timer_index = QINTR_TIMER_IDX_G(q->next_intr_params); |
| 2198 | 2293 | |
| 2199 | 2294 | if (q->adaptive_rx) { |
| @@ -2460,7 +2555,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, · 260 unmodified lines | ||
| 2460 | 2555 | iq->size = roundup(iq->size, 16); |
| 2461 | 2556 | |
| 2462 | 2557 | iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0, |
| 2463 | − &iq->phys_addr, NULL, 0, NUMA_NO_NODE); | |
| 2558 | + &iq->phys_addr, NULL, 0, | |
| 2559 | + dev_to_node(adap->pdev_dev)); | |
| 2464 | 2560 | if (!iq->desc) |
| 2465 | 2561 | return -ENOMEM; |
| 2466 | 2562 | |
| @@ -2500,7 +2596,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, · 33 unmodified lines | ||
| 2500 | 2596 | fl->size = roundup(fl->size, 8); |
| 2501 | 2597 | fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64), |
| 2502 | 2598 | sizeof(struct rx_sw_desc), &fl->addr, |
| 2503 | − &fl->sdesc, s->stat_len, NUMA_NO_NODE); | |
| 2599 | + &fl->sdesc, s->stat_len, | |
| 2600 | + dev_to_node(adap->pdev_dev)); | |
| 2504 | 2601 | if (!fl->desc) |
| 2505 | 2602 | goto fl_nomem; |
| 2506 | 2603 | |
| @@ -2528,7 +2625,6 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, · 21 unmodified lines | ||
| 2528 | 2625 | goto err; |
| 2529 | 2626 | |
| 2530 | 2627 | netif_napi_add(dev, &iq->napi, napi_rx_handler, 64); |
| 2531 | − napi_hash_add(&iq->napi); | |
| 2532 | 2628 | iq->cur_desc = iq->desc; |
| 2533 | 2629 | iq->cidx = 0; |
| 2534 | 2630 | iq->gen = 1; |
| @@ -2574,8 +2670,9 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, · 39 unmodified lines | ||
| 2574 | 2670 | * simple (and hopefully less wrong). |
| 2575 | 2671 | */ |
| 2576 | 2672 | if (!is_t4(adap->params.chip) && cong >= 0) { |
| 2577 | − u32 param, val; | |
| 2673 | + u32 param, val, ch_map = 0; | |
| 2578 | 2674 | int i; |
| 2675 | + u16 cng_ch_bits_log = adap->params.arch.cng_ch_bits_log; | |
| 2579 | 2676 | |
| 2580 | 2677 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
| 2581 | 2678 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | |
| @@ -2587,9 +2684,9 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, · 5 unmodified lines | ||
| 2587 | 2684 | CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X); |
| 2588 | 2685 | for (i = 0; i < 4; i++) { |
| 2589 | 2686 | if (cong & (1 << i)) |
| 2590 | − val |= | |
| 2591 | − CONMCTXT_CNGCHMAP_V(1 << (i << 2)); | |
| 2687 | + ch_map |= 1 << (i << cng_ch_bits_log); | |
| 2592 | 2688 | } |
| 2689 | + val |= CONMCTXT_CNGCHMAP_V(ch_map); | |
| 2593 | 2690 | } |
| 2594 | 2691 | ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
| 2595 | 2692 | ¶m, &val); |
| @@ -2884,7 +2981,7 @@ void t4_free_sge_resources(struct adapter *adap) · 288 unmodified lines | ||
| 2884 | 2981 | } |
| 2885 | 2982 | |
| 2886 | 2983 | /* clean up RDMA and iSCSI Rx queues */ |
| 2887 | − t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq); | |
| 2984 | + t4_free_ofld_rxqs(adap, adap->sge.iscsiqsets, adap->sge.iscsirxq); | |
| 2888 | 2985 | t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq); |
| 2889 | 2986 | t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq); |
| 2890 | 2987 | |
| @@ -3077,8 +3174,7 @@ static int t4_sge_init_soft(struct adapter *adap) · 186 unmodified lines | ||
| 3077 | 3174 | int t4_sge_init(struct adapter *adap) |
| 3078 | 3175 | { |
| 3079 | 3176 | struct sge *s = &adap->sge; |
| 3080 | − u32 sge_control, sge_control2, sge_conm_ctrl; | |
| 3081 | − unsigned int ingpadboundary, ingpackboundary; | |
| 3177 | + u32 sge_control, sge_conm_ctrl; | |
| 3082 | 3178 | int ret, egress_threshold; |
| 3083 | 3179 | |
| 3084 | 3180 | /* |
| @@ -3089,35 +3185,7 @@ int t4_sge_init(struct adapter *adap) · 4 unmodified lines | ||
| 3089 | 3185 | s->pktshift = PKTSHIFT_G(sge_control); |
| 3090 | 3186 | s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64; |
| 3091 | 3187 | |
| 3092 | − /* T4 uses a single control field to specify both the PCIe Padding and | |
| 3093 | − * Packing Boundary. T5 introduced the ability to specify these | |
| 3094 | − * separately. The actual Ingress Packet Data alignment boundary | |
| 3095 | − * within Packed Buffer Mode is the maximum of these two | |
| 3096 | − * specifications. (Note that it makes no real practical sense to | |
| 3097 | − * have the Pading Boudary be larger than the Packing Boundary but you | |
| 3098 | − * could set the chip up that way and, in fact, legacy T4 code would | |
| 3099 | − * end doing this because it would initialize the Padding Boundary and | |
| 3100 | − * leave the Packing Boundary initialized to 0 (16 bytes).) | |
| 3101 | − */ | |
| 3102 | − ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + | |
| 3103 | − INGPADBOUNDARY_SHIFT_X); | |
| 3104 | − if (is_t4(adap->params.chip)) { | |
| 3105 | − s->fl_align = ingpadboundary; | |
| 3106 | − } else { | |
| 3107 | − /* T5 has a different interpretation of one of the PCIe Packing | |
| 3108 | − * Boundary values. | |
| 3109 | − */ | |
| 3110 | − sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); | |
| 3111 | − ingpackboundary = INGPACKBOUNDARY_G(sge_control2); | |
| 3112 | − if (ingpackboundary == INGPACKBOUNDARY_16B_X) | |
| 3113 | − ingpackboundary = 16; | |
| 3114 | − else | |
| 3115 | − ingpackboundary = 1 << (ingpackboundary + | |
| 3116 | − INGPACKBOUNDARY_SHIFT_X); | |
| 3117 | − | |
| 3118 | − s->fl_align = max(ingpadboundary, ingpackboundary); | |
| 3119 | − } | |
| 3120 | − | |
| 3188 | + s->fl_align = t4_fl_pkt_align(adap); | |
| 3121 | 3189 | ret = t4_sge_init_soft(adap); |
| 3122 | 3190 | if (ret < 0) |
| 3123 | 3191 | return ret; |
| @@ -3135,10 +3203,21 @@ int t4_sge_init(struct adapter *adap) · 11 unmodified lines | ||
| 3135 | 3203 | * buffers. |
| 3136 | 3204 | */ |
| 3137 | 3205 | sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A); |
| 3138 | − if (is_t4(adap->params.chip)) | |
| 3206 | + switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { | |
| 3207 | + case CHELSIO_T4: | |
| 3139 | 3208 | egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl); |
| 3140 | − else | |
| 3209 | + break; | |
| 3210 | + case CHELSIO_T5: | |
| 3141 | 3211 | egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl); |
| 3212 | + break; | |
| 3213 | + case CHELSIO_T6: | |
| 3214 | + egress_threshold = T6_EGRTHRESHOLDPACKING_G(sge_conm_ctrl); | |
| 3215 | + break; | |
| 3216 | + default: | |
| 3217 | + dev_err(adap->pdev_dev, "Unsupported Chip version %d\n", | |
| 3218 | + CHELSIO_CHIP_VERSION(adap->params.chip)); | |
| 3219 | + return -EINVAL; | |
| 3220 | + } | |
| 3142 | 3221 | s->fl_starve_thres = 2*egress_threshold + 1; |
| 3143 | 3222 | |
| 3144 | 3223 | t4_idma_monitor_init(adap, &s->idma_monitor); |
| @@ -1942,8 +1942,12 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) · 1941 unmodified lines | ||
| 1942 | 1942 | 0x1190, 0x1194, |
| 1943 | 1943 | 0x11a0, 0x11a4, |
| 1944 | 1944 | 0x11b0, 0x11b4, |
| 1945 | − 0x11fc, 0x1254, | |
| 1946 | − 0x1280, 0x133c, | |
| 1945 | + 0x11fc, 0x1258, | |
| 1946 | + 0x1280, 0x12d4, | |
| 1947 | + 0x12d9, 0x12d9, | |
| 1948 | + 0x12de, 0x12de, | |
| 1949 | + 0x12e3, 0x12e3, | |
| 1950 | + 0x12e8, 0x133c, | |
| 1947 | 1951 | 0x1800, 0x18fc, |
| 1948 | 1952 | 0x3000, 0x302c, |
| 1949 | 1953 | 0x3060, 0x30b0, |
| @@ -1973,7 +1977,7 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) · 23 unmodified lines | ||
| 1973 | 1977 | 0x5e50, 0x5e94, |
| 1974 | 1978 | 0x5ea0, 0x5eb0, |
| 1975 | 1979 | 0x5ec0, 0x5ec0, |
| 1976 | − 0x5ec8, 0x5ecc, | |
| 1980 | + 0x5ec8, 0x5ed0, | |
| 1977 | 1981 | 0x6000, 0x6020, |
| 1978 | 1982 | 0x6028, 0x6040, |
| 1979 | 1983 | 0x6058, 0x609c, |
| @@ -2048,7 +2052,8 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) · 68 unmodified lines | ||
| 2048 | 2052 | 0x19150, 0x19194, |
| 2049 | 2053 | 0x1919c, 0x191b0, |
| 2050 | 2054 | 0x191d0, 0x191e8, |
| 2051 | − 0x19238, 0x192b0, | |
| 2055 | + 0x19238, 0x19290, | |
| 2056 | + 0x192a4, 0x192b0, | |
| 2052 | 2057 | 0x192bc, 0x192bc, |
| 2053 | 2058 | 0x19348, 0x1934c, |
| 2054 | 2059 | 0x193f8, 0x19418, |
| @@ -2442,7 +2447,8 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) · 387 unmodified lines | ||
| 2442 | 2447 | 0x40280, 0x40280, |
| 2443 | 2448 | 0x40304, 0x40304, |
| 2444 | 2449 | 0x40330, 0x4033c, |
| 2445 | − 0x41304, 0x413c8, | |
| 2450 | + 0x41304, 0x413b8, | |
| 2451 | + 0x413c0, 0x413c8, | |
| 2446 | 2452 | 0x413d0, 0x413dc, |
| 2447 | 2453 | 0x413f0, 0x413f0, |
| 2448 | 2454 | 0x41400, 0x4140c, |
| @@ -5254,7 +5260,7 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) · 2805 unmodified lines | ||
| 5254 | 5260 | int i; |
| 5255 | 5261 | u32 data[2]; |
| 5256 | 5262 | |
| 5257 | − for (i = 0; i < PM_NSTATS; i++) { | |
| 5263 | + for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { | |
| 5258 | 5264 | t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); |
| 5259 | 5265 | cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); |
| 5260 | 5266 | if (is_t4(adap->params.chip)) { |
| @@ -5281,7 +5287,7 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) · 20 unmodified lines | ||
| 5281 | 5287 | int i; |
| 5282 | 5288 | u32 data[2]; |
| 5283 | 5289 | |
| 5284 | − for (i = 0; i < PM_NSTATS; i++) { | |
| 5290 | + for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { | |
| 5285 | 5291 | t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); |
| 5286 | 5292 | cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); |
| 5287 | 5293 | if (is_t4(adap->params.chip)) { |
| @@ -5310,7 +5316,14 @@ unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) · 22 unmodified lines | ||
| 5310 | 5316 | |
| 5311 | 5317 | if (n == 0) |
| 5312 | 5318 | return idx == 0 ? 0xf : 0; |
| 5313 | − if (n == 1) | |
| 5319 | + /* In T6 (which is a 2 port card), | |
| 5320 | + * port 0 is mapped to channel 0 and port 1 is mapped to channel 1. | |
| 5321 | + * For 2 port T4/T5 adapter, | |
| 5322 | + * port 0 is mapped to channel 0 and 1, | |
| 5323 | + * port 1 is mapped to channel 2 and 3. | |
| 5324 | + */ | |
| 5325 | + if ((n == 1) && | |
| 5326 | + (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) | |
| 5314 | 5327 | return idx < 2 ? (3 << (2 * idx)) : 0; |
| 5315 | 5328 | return 1 << idx; |
| 5316 | 5329 | } |
| @@ -5689,6 +5702,39 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state) · 372 unmodified lines | ||
| 5689 | 5702 | "IDMA_FL_SEND_PADDING", |
| 5690 | 5703 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", |
| 5691 | 5704 | }; |
| 5705 | + static const char * const t6_decode[] = { | |
| 5706 | + "IDMA_IDLE", | |
| 5707 | + "IDMA_PUSH_MORE_CPL_FIFO", | |
| 5708 | + "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | |
| 5709 | + "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", | |
| 5710 | + "IDMA_PHYSADDR_SEND_PCIEHDR", | |
| 5711 | + "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | |
| 5712 | + "IDMA_PHYSADDR_SEND_PAYLOAD", | |
| 5713 | + "IDMA_FL_REQ_DATA_FL", | |
| 5714 | + "IDMA_FL_DROP", | |
| 5715 | + "IDMA_FL_DROP_SEND_INC", | |
| 5716 | + "IDMA_FL_H_REQ_HEADER_FL", | |
| 5717 | + "IDMA_FL_H_SEND_PCIEHDR", | |
| 5718 | + "IDMA_FL_H_PUSH_CPL_FIFO", | |
| 5719 | + "IDMA_FL_H_SEND_CPL", | |
| 5720 | + "IDMA_FL_H_SEND_IP_HDR_FIRST", | |
| 5721 | + "IDMA_FL_H_SEND_IP_HDR", | |
| 5722 | + "IDMA_FL_H_REQ_NEXT_HEADER_FL", | |
| 5723 | + "IDMA_FL_H_SEND_NEXT_PCIEHDR", | |
| 5724 | + "IDMA_FL_H_SEND_IP_HDR_PADDING", | |
| 5725 | + "IDMA_FL_D_SEND_PCIEHDR", | |
| 5726 | + "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | |
| 5727 | + "IDMA_FL_D_REQ_NEXT_DATA_FL", | |
| 5728 | + "IDMA_FL_SEND_PCIEHDR", | |
| 5729 | + "IDMA_FL_PUSH_CPL_FIFO", | |
| 5730 | + "IDMA_FL_SEND_CPL", | |
| 5731 | + "IDMA_FL_SEND_PAYLOAD_FIRST", | |
| 5732 | + "IDMA_FL_SEND_PAYLOAD", | |
| 5733 | + "IDMA_FL_REQ_NEXT_DATA_FL", | |
| 5734 | + "IDMA_FL_SEND_NEXT_PCIEHDR", | |
| 5735 | + "IDMA_FL_SEND_PADDING", | |
| 5736 | + "IDMA_FL_SEND_COMPLETION_TO_IMSG", | |
| 5737 | + }; | |
| 5692 | 5738 | static const u32 sge_regs[] = { |
| 5693 | 5739 | SGE_DEBUG_DATA_LOW_INDEX_2_A, |
| 5694 | 5740 | SGE_DEBUG_DATA_LOW_INDEX_3_A, |
| @@ -5697,6 +5743,32 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state) · 2 unmodified lines | ||
| 5697 | 5743 | const char **sge_idma_decode; |
| 5698 | 5744 | int sge_idma_decode_nstates; |
| 5699 | 5745 | int i; |
| 5746 | + unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); | |
| 5747 | + | |
| 5748 | + /* Select the right set of decode strings to dump depending on the | |
| 5749 | + * adapter chip type. | |
| 5750 | + */ | |
| 5751 | + switch (chip_version) { | |
| 5752 | + case CHELSIO_T4: | |
| 5753 | + sge_idma_decode = (const char **)t4_decode; | |
| 5754 | + sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); | |
| 5755 | + break; | |
| 5756 | + | |
| 5757 | + case CHELSIO_T5: | |
| 5758 | + sge_idma_decode = (const char **)t5_decode; | |
| 5759 | + sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); | |
| 5760 | + break; | |
| 5761 | + | |
| 5762 | + case CHELSIO_T6: | |
| 5763 | + sge_idma_decode = (const char **)t6_decode; | |
| 5764 | + sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); | |
| 5765 | + break; | |
| 5766 | + | |
| 5767 | + default: | |
| 5768 | + dev_err(adapter->pdev_dev, | |
| 5769 | + "Unsupported chip version %d\n", chip_version); | |
| 5770 | + return; | |
| 5771 | + } | |
| 5700 | 5772 | |
| 5701 | 5773 | if (is_t4(adapter->params.chip)) { |
| 5702 | 5774 | sge_idma_decode = (const char **)t4_decode; |
| @@ -6096,6 +6168,59 @@ int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, · 393 unmodified lines | ||
| 6096 | 6168 | return t4_fw_restart(adap, mbox, reset); |
| 6097 | 6169 | } |
| 6098 | 6170 | |
| 6171 | +/** | |
| 6172 | + * t4_fl_pkt_align - return the fl packet alignment | |
| 6173 | + * @adap: the adapter | |
| 6174 | + * | |
| 6175 | + * T4 has a single field to specify the packing and padding boundary. | |
| 6176 | + * T5 onwards has separate fields for this and hence the alignment for | |
| 6177 | + * next packet offset is maximum of these two. | |
| 6178 | + * | |
| 6179 | + */ | |
| 6180 | +int t4_fl_pkt_align(struct adapter *adap) | |
| 6181 | +{ | |
| 6182 | + u32 sge_control, sge_control2; | |
| 6183 | + unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift; | |
| 6184 | + | |
| 6185 | + sge_control = t4_read_reg(adap, SGE_CONTROL_A); | |
| 6186 | + | |
| 6187 | + /* T4 uses a single control field to specify both the PCIe Padding and | |
| 6188 | + * Packing Boundary. T5 introduced the ability to specify these | |
| 6189 | + * separately. The actual Ingress Packet Data alignment boundary | |
| 6190 | + * within Packed Buffer Mode is the maximum of these two | |
| 6191 | + * specifications. (Note that it makes no real practical sense to | |
| 6192 | + * have the Pading Boudary be larger than the Packing Boundary but you | |
| 6193 | + * could set the chip up that way and, in fact, legacy T4 code would | |
| 6194 | + * end doing this because it would initialize the Padding Boundary and | |
| 6195 | + * leave the Packing Boundary initialized to 0 (16 bytes).) | |
| 6196 | + * Padding Boundary values in T6 starts from 8B, | |
| 6197 | + * where as it is 32B for T4 and T5. | |
| 6198 | + */ | |
| 6199 | + if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) | |
| 6200 | + ingpad_shift = INGPADBOUNDARY_SHIFT_X; | |
| 6201 | + else | |
| 6202 | + ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X; | |
| 6203 | + | |
| 6204 | + ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift); | |
| 6205 | + | |
| 6206 | + fl_align = ingpadboundary; | |
| 6207 | + if (!is_t4(adap->params.chip)) { | |
| 6208 | + /* T5 has a weird interpretation of one of the PCIe Packing | |
| 6209 | + * Boundary values. No idea why ... | |
| 6210 | + */ | |
| 6211 | + sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); | |
| 6212 | + ingpackboundary = INGPACKBOUNDARY_G(sge_control2); | |
| 6213 | + if (ingpackboundary == INGPACKBOUNDARY_16B_X) | |
| 6214 | + ingpackboundary = 16; | |
| 6215 | + else | |
| 6216 | + ingpackboundary = 1 << (ingpackboundary + | |
| 6217 | + INGPACKBOUNDARY_SHIFT_X); | |
| 6218 | + | |
| 6219 | + fl_align = max(ingpadboundary, ingpackboundary); | |
| 6220 | + } | |
| 6221 | + return fl_align; | |
| 6222 | +} | |
| 6223 | + | |
| 6099 | 6224 | /** |
| 6100 | 6225 | * t4_fixup_host_params - fix up host-dependent parameters |
| 6101 | 6226 | * @adap: the adapter |
| @@ -6114,6 +6239,7 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, · 12 unmodified lines | ||
| 6114 | 6239 | unsigned int stat_len = cache_line_size > 64 ? 128 : 64; |
| 6115 | 6240 | unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; |
| 6116 | 6241 | unsigned int fl_align_log = fls(fl_align) - 1; |
| 6242 | + unsigned int ingpad; | |
| 6117 | 6243 | |
| 6118 | 6244 | t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, |
| 6119 | 6245 | HOSTPAGESIZEPF0_V(sge_hps) | |
| @@ -6161,10 +6287,16 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, · 41 unmodified lines | ||
| 6161 | 6287 | fl_align = 64; |
| 6162 | 6288 | fl_align_log = 6; |
| 6163 | 6289 | } |
| 6290 | + | |
| 6291 | + if (is_t5(adap->params.chip)) | |
| 6292 | + ingpad = INGPCIEBOUNDARY_32B_X; | |
| 6293 | + else | |
| 6294 | + ingpad = T6_INGPADBOUNDARY_32B_X; | |
| 6295 | + | |
| 6164 | 6296 | t4_set_reg_field(adap, SGE_CONTROL_A, |
| 6165 | 6297 | INGPADBOUNDARY_V(INGPADBOUNDARY_M) | |
| 6166 | 6298 | EGRSTATUSPAGESIZE_F, |
| 6167 | − INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) | | |
| 6299 | + INGPADBOUNDARY_V(ingpad) | | |
| 6168 | 6300 | EGRSTATUSPAGESIZE_V(stat_len != 64)); |
| 6169 | 6301 | t4_set_reg_field(adap, SGE_CONTROL2_A, |
| 6170 | 6302 | INGPACKBOUNDARY_V(INGPACKBOUNDARY_M), |
| @@ -7060,7 +7192,12 @@ int t4_prep_adapter(struct adapter *adapter) · 889 unmodified lines | ||
| 7060 | 7192 | NUM_MPS_CLS_SRAM_L_INSTANCES; |
| 7061 | 7193 | adapter->params.arch.mps_rplc_size = 128; |
| 7062 | 7194 | adapter->params.arch.nchan = NCHAN; |
| 7195 | + adapter->params.arch.pm_stats_cnt = PM_NSTATS; | |
| 7063 | 7196 | adapter->params.arch.vfcount = 128; |
| 7197 | + /* Congestion map is for 4 channels so that | |
| 7198 | + * MPS can have 4 priority per port. | |
| 7199 | + */ | |
| 7200 | + adapter->params.arch.cng_ch_bits_log = 2; | |
| 7064 | 7201 | break; |
| 7065 | 7202 | case CHELSIO_T5: |
| 7066 | 7203 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
| @@ -7069,7 +7206,9 @@ int t4_prep_adapter(struct adapter *adapter) · 2 unmodified lines | ||
| 7069 | 7206 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; |
| 7070 | 7207 | adapter->params.arch.mps_rplc_size = 128; |
| 7071 | 7208 | adapter->params.arch.nchan = NCHAN; |
| 7209 | + adapter->params.arch.pm_stats_cnt = PM_NSTATS; | |
| 7072 | 7210 | adapter->params.arch.vfcount = 128; |
| 7211 | + adapter->params.arch.cng_ch_bits_log = 2; | |
| 7073 | 7212 | break; |
| 7074 | 7213 | case CHELSIO_T6: |
| 7075 | 7214 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); |
| @@ -7078,7 +7217,12 @@ int t4_prep_adapter(struct adapter *adapter) · 2 unmodified lines | ||
| 7078 | 7217 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; |
| 7079 | 7218 | adapter->params.arch.mps_rplc_size = 256; |
| 7080 | 7219 | adapter->params.arch.nchan = 2; |
| 7220 | + adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS; | |
| 7081 | 7221 | adapter->params.arch.vfcount = 256; |
| 7222 | + /* Congestion map will be for 2 channels so that | |
| 7223 | + * MPS can have 8 priority per port. | |
| 7224 | + */ | |
| 7225 | + adapter->params.arch.cng_ch_bits_log = 3; | |
| 7082 | 7226 | break; |
| 7083 | 7227 | default: |
| 7084 | 7228 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", |
| @@ -48,6 +48,7 @@ enum { · 47 unmodified lines | ||
| 48 | 48 | NMTUS = 16, /* size of MTU table */ |
| 49 | 49 | NCCTRL_WIN = 32, /* # of congestion control windows */ |
| 50 | 50 | PM_NSTATS = 5, /* # of PM stats */ |
| 51 | + T6_PM_NSTATS = 7, /* # of PM stats in T6 */ | |
| 51 | 52 | MBOX_LEN = 64, /* mailbox size in bytes */ |
| 52 | 53 | TRACE_LEN = 112, /* length of trace data and mask */ |
| 53 | 54 | FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ |
| @@ -162,6 +162,9 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN · 161 unmodified lines | ||
| 162 | 162 | CH_PCI_ID_TABLE_FENTRY(0x5095), /* Custom T540-CR-SO */ |
| 163 | 163 | CH_PCI_ID_TABLE_FENTRY(0x5096), /* Custom T580-CR */ |
| 164 | 164 | CH_PCI_ID_TABLE_FENTRY(0x5097), /* Custom T520-KR */ |
| 165 | + CH_PCI_ID_TABLE_FENTRY(0x5098), /* Custom 2x40G QSFP */ | |
| 166 | + CH_PCI_ID_TABLE_FENTRY(0x5099), /* Custom 2x40G QSFP */ | |
| 167 | + CH_PCI_ID_TABLE_FENTRY(0x509a), /* Custom T520-CR */ | |
| 165 | 168 | |
| 166 | 169 | /* T6 adapters: |
| 167 | 170 | */ |
| @@ -492,6 +492,9 @@ · 491 unmodified lines | ||
| 492 | 492 | #define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S) |
| 493 | 493 | #define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M) |
| 494 | 494 | |
| 495 | +#define T6_STATMODE_S 0 | |
| 496 | +#define T6_STATMODE_V(x) ((x) << T6_STATMODE_S) | |
| 497 | + | |
| 495 | 498 | #define SGE_DBFIFO_STATUS2_A 0x1118 |
| 496 | 499 | |
| 497 | 500 | #define HP_INT_THRESH_T5_S 10 |
| @@ -2395,6 +2398,30 @@ · 1897 unmodified lines | ||
| 2395 | 2398 | #define MPS_CLS_TCAM_DATA0_A 0xf000 |
| 2396 | 2399 | #define MPS_CLS_TCAM_DATA1_A 0xf004 |
| 2397 | 2400 | |
| 2401 | +#define VIDL_S 16 | |
| 2402 | +#define VIDL_M 0xffffU | |
| 2403 | +#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M) | |
| 2404 | + | |
| 2405 | +#define DATALKPTYPE_S 10 | |
| 2406 | +#define DATALKPTYPE_M 0x3U | |
| 2407 | +#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M) | |
| 2408 | + | |
| 2409 | +#define DATAPORTNUM_S 12 | |
| 2410 | +#define DATAPORTNUM_M 0xfU | |
| 2411 | +#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M) | |
| 2412 | + | |
| 2413 | +#define DATADIPHIT_S 8 | |
| 2414 | +#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S) | |
| 2415 | +#define DATADIPHIT_F DATADIPHIT_V(1U) | |
| 2416 | + | |
| 2417 | +#define DATAVIDH2_S 7 | |
| 2418 | +#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S) | |
| 2419 | +#define DATAVIDH2_F DATAVIDH2_V(1U) | |
| 2420 | + | |
| 2421 | +#define DATAVIDH1_S 0 | |
| 2422 | +#define DATAVIDH1_M 0x7fU | |
| 2423 | +#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M) | |
| 2424 | + | |
| 2398 | 2425 | #define USED_S 16 |
| 2399 | 2426 | #define USED_M 0x7ffU |
| 2400 | 2427 | #define USED_G(x) (((x) >> USED_S) & USED_M) |
| @@ -2802,6 +2829,10 @@ · 401 unmodified lines | ||
| 2802 | 2829 | #define HASHEN_V(x) ((x) << HASHEN_S) |
| 2803 | 2830 | #define HASHEN_F HASHEN_V(1U) |
| 2804 | 2831 | |
| 2832 | +#define ASLIPCOMPEN_S 17 | |
| 2833 | +#define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S) | |
| 2834 | +#define ASLIPCOMPEN_F ASLIPCOMPEN_V(1U) | |
| 2835 | + | |
| 2805 | 2836 | #define REQQPARERR_S 16 |
| 2806 | 2837 | #define REQQPARERR_V(x) ((x) << REQQPARERR_S) |
| 2807 | 2838 | #define REQQPARERR_F REQQPARERR_V(1U) |
| @@ -53,6 +53,9 @@ · 52 unmodified lines | ||
| 53 | 53 | |
| 54 | 54 | #define INGPADBOUNDARY_SHIFT_X 5 |
| 55 | 55 | |
| 56 | +#define T6_INGPADBOUNDARY_SHIFT_X 3 | |
| 57 | +#define T6_INGPADBOUNDARY_32B_X 2 | |
| 58 | + | |
| 56 | 59 | /* CONTROL2 register */ |
| 57 | 60 | #define INGPACKBOUNDARY_SHIFT_X 5 |
| 58 | 61 | #define INGPACKBOUNDARY_16B_X 0 |
| @@ -2607,7 +2607,7 @@ int t4vf_sge_init(struct adapter *adapter) · 2606 unmodified lines | ||
| 2607 | 2607 | u32 fl0 = sge_params->sge_fl_buffer_size[0]; |
| 2608 | 2608 | u32 fl1 = sge_params->sge_fl_buffer_size[1]; |
| 2609 | 2609 | struct sge *s = &adapter->sge; |
| 2610 | − unsigned int ingpadboundary, ingpackboundary; | |
| 2610 | + unsigned int ingpadboundary, ingpackboundary, ingpad_shift; | |
| 2611 | 2611 | |
| 2612 | 2612 | /* |
| 2613 | 2613 | * Start by vetting the basic SGE parameters which have been set up by |
| @@ -2642,9 +2642,16 @@ int t4vf_sge_init(struct adapter *adapter) · 28 unmodified lines | ||
| 2642 | 2642 | * could set the chip up that way and, in fact, legacy T4 code would |
| 2643 | 2643 | * end doing this because it would initialize the Padding Boundary and |
| 2644 | 2644 | * leave the Packing Boundary initialized to 0 (16 bytes).) |
| 2645 | + * Padding Boundary values in T6 starts from 8B, | |
| 2646 | + * where as it is 32B for T4 and T5. | |
| 2645 | 2647 | */ |
| 2648 | + if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) | |
| 2649 | + ingpad_shift = INGPADBOUNDARY_SHIFT_X; | |
| 2650 | + else | |
| 2651 | + ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X; | |
| 2652 | + | |
| 2646 | 2653 | ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_params->sge_control) + |
| 2647 | − INGPADBOUNDARY_SHIFT_X); | |
| 2654 | + ingpad_shift); | |
| 2648 | 2655 | if (is_t4(adapter->params.chip)) { |
| 2649 | 2656 | s->fl_align = ingpadboundary; |
| 2650 | 2657 | } else { |
| @@ -54,6 +54,7 @@ · 53 unmodified lines | ||
| 54 | 54 | #define T4VF_MPS_BASE_ADDR 0x0100 |
| 55 | 55 | #define T4VF_PL_BASE_ADDR 0x0200 |
| 56 | 56 | #define T4VF_MBDATA_BASE_ADDR 0x0240 |
| 57 | +#define T6VF_MBDATA_BASE_ADDR 0x0280 | |
| 57 | 58 | #define T4VF_CIM_BASE_ADDR 0x0300 |
| 58 | 59 | |
| 59 | 60 | #define T4VF_REGMAP_START 0x0000 |
| @@ -120,12 +120,19 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size, · 119 unmodified lines | ||
| 120 | 120 | 1, 1, 3, 5, 10, 10, 20, 50, 100 |
| 121 | 121 | }; |
| 122 | 122 | |
| 123 | − u32 v; | |
| 123 | + u32 v, mbox_data; | |
| 124 | 124 | int i, ms, delay_idx; |
| 125 | 125 | const __be64 *p; |
| 126 | − u32 mbox_data = T4VF_MBDATA_BASE_ADDR; | |
| 127 | 126 | u32 mbox_ctl = T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL; |
| 128 | 127 | |
| 128 | + /* In T6, mailbox size is changed to 128 bytes to avoid | |
| 129 | + * invalidating the entire prefetch buffer. | |
| 130 | + */ | |
| 131 | + if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) | |
| 132 | + mbox_data = T4VF_MBDATA_BASE_ADDR; | |
| 133 | + else | |
| 134 | + mbox_data = T6VF_MBDATA_BASE_ADDR; | |
| 135 | + | |
| 129 | 136 | /* |
| 130 | 137 | * Commands must be multiples of 16 bytes in length and may not be |
| 131 | 138 | * larger than the size of the Mailbox Data register array. |
| @@ -2458,13 +2458,11 @@ static int enic_dev_init(struct enic *enic) · 2457 unmodified lines | ||
| 2458 | 2458 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
| 2459 | 2459 | default: |
| 2460 | 2460 | netif_napi_add(netdev, &enic->napi[0], enic_poll, 64); |
| 2461 | − napi_hash_add(&enic->napi[0]); | |
| 2462 | 2461 | break; |
| 2463 | 2462 | case VNIC_DEV_INTR_MODE_MSIX: |
| 2464 | 2463 | for (i = 0; i < enic->rq_count; i++) { |
| 2465 | 2464 | netif_napi_add(netdev, &enic->napi[i], |
| 2466 | 2465 | enic_poll_msix_rq, NAPI_POLL_WEIGHT); |
| 2467 | − napi_hash_add(&enic->napi[i]); | |
| 2468 | 2466 | } |
| 2469 | 2467 | for (i = 0; i < enic->wq_count; i++) |
| 2470 | 2468 | netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)], |
| @@ -1990,7 +1990,7 @@ SetMulticastFilter(struct net_device *dev) · 1989 unmodified lines | ||
| 1990 | 1990 | |
| 1991 | 1991 | static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST; |
| 1992 | 1992 | |
| 1993 | −static int __init de4x5_eisa_probe (struct device *gendev) | |
| 1993 | +static int de4x5_eisa_probe(struct device *gendev) | |
| 1994 | 1994 | { |
| 1995 | 1995 | struct eisa_device *edev; |
| 1996 | 1996 | u_long iobase; |
| @@ -70,7 +70,6 @@ static const int multicast_filter_limit = 0x40; · 69 unmodified lines | ||
| 70 | 70 | static int rio_open (struct net_device *dev); |
| 71 | 71 | static void rio_timer (unsigned long data); |
| 72 | 72 | static void rio_tx_timeout (struct net_device *dev); |
| 73 | −static void alloc_list (struct net_device *dev); | |
| 74 | 73 | static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev); |
| 75 | 74 | static irqreturn_t rio_interrupt (int irq, void *dev_instance); |
| 76 | 75 | static void rio_free_tx (struct net_device *dev, int irq); |
| @@ -253,19 +252,6 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) · 176 unmodified lines | ||
| 253 | 252 | if (err) |
| 254 | 253 | goto err_out_unmap_rx; |
| 255 | 254 | |
| 256 | − if (np->chip_id == CHIP_IP1000A && | |
| 257 | − (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) { | |
| 258 | − /* PHY magic taken from ipg driver, undocumented registers */ | |
| 259 | − mii_write(dev, np->phy_addr, 31, 0x0001); | |
| 260 | − mii_write(dev, np->phy_addr, 27, 0x01e0); | |
| 261 | − mii_write(dev, np->phy_addr, 31, 0x0002); | |
| 262 | − mii_write(dev, np->phy_addr, 27, 0xeb8e); | |
| 263 | − mii_write(dev, np->phy_addr, 31, 0x0000); | |
| 264 | − mii_write(dev, np->phy_addr, 30, 0x005e); | |
| 265 | − /* advertise 1000BASE-T half & full duplex, prefer MASTER */ | |
| 266 | − mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700); | |
| 267 | − } | |
| 268 | − | |
| 269 | 255 | /* Fiber device? */ |
| 270 | 256 | np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0; |
| 271 | 257 | np->link_status = 0; |
| @@ -275,13 +261,11 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) · 3 unmodified lines | ||
| 275 | 261 | if (np->an_enable == 2) { |
| 276 | 262 | np->an_enable = 1; |
| 277 | 263 | } |
| 278 | − mii_set_media_pcs (dev); | |
| 279 | 264 | } else { |
| 280 | 265 | /* Auto-Negotiation is mandatory for 1000BASE-T, |
| 281 | 266 | IEEE 802.3ab Annex 28D page 14 */ |
| 282 | 267 | if (np->speed == 1000) |
| 283 | 268 | np->an_enable = 1; |
| 284 | − mii_set_media (dev); | |
| 285 | 269 | } |
| 286 | 270 | |
| 287 | 271 | err = register_netdev (dev); |
| @@ -446,19 +430,106 @@ static void rio_set_led_mode(struct net_device *dev) · 158 unmodified lines | ||
| 446 | 430 | dw32(ASICCtrl, mode); |
| 447 | 431 | } |
| 448 | 432 | |
| 449 | −static int | |
| 450 | −rio_open (struct net_device *dev) | |
| 433 | +static inline dma_addr_t desc_to_dma(struct netdev_desc *desc) | |
| 434 | +{ | |
| 435 | + return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48); | |
| 436 | +} | |
| 437 | + | |
| 438 | +static void free_list(struct net_device *dev) | |
| 439 | +{ | |
| 440 | + struct netdev_private *np = netdev_priv(dev); | |
| 441 | + struct sk_buff *skb; | |
| 442 | + int i; | |
| 443 | + | |
| 444 | + /* Free all the skbuffs in the queue. */ | |
| 445 | + for (i = 0; i < RX_RING_SIZE; i++) { | |
| 446 | + skb = np->rx_skbuff[i]; | |
| 447 | + if (skb) { | |
| 448 | + pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]), | |
| 449 | + skb->len, PCI_DMA_FROMDEVICE); | |
| 450 | + dev_kfree_skb(skb); | |
| 451 | + np->rx_skbuff[i] = NULL; | |
| 452 | + } | |
| 453 | + np->rx_ring[i].status = 0; | |
| 454 | + np->rx_ring[i].fraginfo = 0; | |
| 455 | + } | |
| 456 | + for (i = 0; i < TX_RING_SIZE; i++) { | |
| 457 | + skb = np->tx_skbuff[i]; | |
| 458 | + if (skb) { | |
| 459 | + pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]), | |
| 460 | + skb->len, PCI_DMA_TODEVICE); | |
| 461 | + dev_kfree_skb(skb); | |
| 462 | + np->tx_skbuff[i] = NULL; | |
| 463 | + } | |
| 464 | + } | |
| 465 | +} | |
| 466 | + | |
| 467 | +static void rio_reset_ring(struct netdev_private *np) | |
| 468 | +{ | |
| 469 | + int i; | |
| 470 | + | |
| 471 | + np->cur_rx = 0; | |
| 472 | + np->cur_tx = 0; | |
| 473 | + np->old_rx = 0; | |
| 474 | + np->old_tx = 0; | |
| 475 | + | |
| 476 | + for (i = 0; i < TX_RING_SIZE; i++) | |
| 477 | + np->tx_ring[i].status = cpu_to_le64(TFDDone); | |
| 478 | + | |
| 479 | + for (i = 0; i < RX_RING_SIZE; i++) | |
| 480 | + np->rx_ring[i].status = 0; | |
| 481 | +} | |
| 482 | + | |
| 483 | + /* allocate and initialize Tx and Rx descriptors */ | |
| 484 | +static int alloc_list(struct net_device *dev) | |
| 485 | +{ | |
| 486 | + struct netdev_private *np = netdev_priv(dev); | |
| 487 | + int i; | |
| 488 | + | |
| 489 | + rio_reset_ring(np); | |
| 490 | + np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32); | |
| 491 | + | |
| 492 | + /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */ | |
| 493 | + for (i = 0; i < TX_RING_SIZE; i++) { | |
| 494 | + np->tx_skbuff[i] = NULL; | |
| 495 | + np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma + | |
| 496 | + ((i + 1) % TX_RING_SIZE) * | |
| 497 | + sizeof(struct netdev_desc)); | |
| 498 | + } | |
| 499 | + | |
| 500 | + /* Initialize Rx descriptors & allocate buffers */ | |
| 501 | + for (i = 0; i < RX_RING_SIZE; i++) { | |
| 502 | + /* Allocated fixed size of skbuff */ | |
| 503 | + struct sk_buff *skb; | |
| 504 | + | |
| 505 | + skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); | |
| 506 | + np->rx_skbuff[i] = skb; | |
| 507 | + if (!skb) { | |
| 508 | + free_list(dev); | |
| 509 | + return -ENOMEM; | |
| 510 | + } | |
| 511 | + | |
| 512 | + np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma + | |
| 513 | + ((i + 1) % RX_RING_SIZE) * | |
| 514 | + sizeof(struct netdev_desc)); | |
| 515 | + /* Rubicon now supports 40 bits of addressing space. */ | |
| 516 | + np->rx_ring[i].fraginfo = | |
| 517 | + cpu_to_le64(pci_map_single( | |
| 518 | + np->pdev, skb->data, np->rx_buf_sz, | |
| 519 | + PCI_DMA_FROMDEVICE)); | |
| 520 | + np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); | |
| 521 | + } | |
| 522 | + | |
| 523 | + return 0; | |
| 524 | +} | |
| 525 | + | |
| 526 | +static void rio_hw_init(struct net_device *dev) | |
| 451 | 527 | { |
| 452 | 528 | struct netdev_private *np = netdev_priv(dev); |
| 453 | 529 | void __iomem *ioaddr = np->ioaddr; |
| 454 | − const int irq = np->pdev->irq; | |
| 455 | 530 | int i; |
| 456 | 531 | u16 macctrl; |
| 457 | 532 | |
| 458 | − i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev); | |
| 459 | − if (i) | |
| 460 | − return i; | |
| 461 | − | |
| 462 | 533 | /* Reset all logic functions */ |
| 463 | 534 | dw16(ASICCtrl + 2, |
| 464 | 535 | GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset); |
| @@ -469,11 +540,31 @@ rio_open (struct net_device *dev) · 4 unmodified lines | ||
| 469 | 540 | /* DebugCtrl bit 4, 5, 9 must set */ |
| 470 | 541 | dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230); |
| 471 | 542 | |
| 543 | + if (np->chip_id == CHIP_IP1000A && | |
| 544 | + (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) { | |
| 545 | + /* PHY magic taken from ipg driver, undocumented registers */ | |
| 546 | + mii_write(dev, np->phy_addr, 31, 0x0001); | |
| 547 | + mii_write(dev, np->phy_addr, 27, 0x01e0); | |
| 548 | + mii_write(dev, np->phy_addr, 31, 0x0002); | |
| 549 | + mii_write(dev, np->phy_addr, 27, 0xeb8e); | |
| 550 | + mii_write(dev, np->phy_addr, 31, 0x0000); | |
| 551 | + mii_write(dev, np->phy_addr, 30, 0x005e); | |
| 552 | + /* advertise 1000BASE-T half & full duplex, prefer MASTER */ | |
| 553 | + mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700); | |
| 554 | + } | |
| 555 | + | |
| 556 | + if (np->phy_media) | |
| 557 | + mii_set_media_pcs(dev); | |
| 558 | + else | |
| 559 | + mii_set_media(dev); | |
| 560 | + | |
| 472 | 561 | /* Jumbo frame */ |
| 473 | 562 | if (np->jumbo != 0) |
| 474 | 563 | dw16(MaxFrameSize, MAX_JUMBO+14); |
| 475 | 564 | |
| 476 | − alloc_list (dev); | |
| 565 | + /* Set RFDListPtr */ | |
| 566 | + dw32(RFDListPtr0, np->rx_ring_dma); | |
| 567 | + dw32(RFDListPtr1, 0); | |
| 477 | 568 | |
| 478 | 569 | /* Set station address */ |
| 479 | 570 | /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works |
| @@ -509,10 +600,6 @@ rio_open (struct net_device *dev) · 29 unmodified lines | ||
| 509 | 600 | dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging); |
| 510 | 601 | } |
| 511 | 602 | |
| 512 | − setup_timer(&np->timer, rio_timer, (unsigned long)dev); | |
| 513 | − np->timer.expires = jiffies + 1*HZ; | |
| 514 | − add_timer (&np->timer); | |
| 515 | − | |
| 516 | 603 | /* Start Tx/Rx */ |
| 517 | 604 | dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable); |
| 518 | 605 | |
| @@ -522,6 +609,42 @@ rio_open (struct net_device *dev) · 3 unmodified lines | ||
| 522 | 609 | macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0; |
| 523 | 610 | macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0; |
| 524 | 611 | dw16(MACCtrl, macctrl); |
| 612 | +} | |
| 613 | + | |
| 614 | +static void rio_hw_stop(struct net_device *dev) | |
| 615 | +{ | |
| 616 | + struct netdev_private *np = netdev_priv(dev); | |
| 617 | + void __iomem *ioaddr = np->ioaddr; | |
| 618 | + | |
| 619 | + /* Disable interrupts */ | |
| 620 | + dw16(IntEnable, 0); | |
| 621 | + | |
| 622 | + /* Stop Tx and Rx logics */ | |
| 623 | + dw32(MACCtrl, TxDisable | RxDisable | StatsDisable); | |
| 624 | +} | |
| 625 | + | |
| 626 | +static int rio_open(struct net_device *dev) | |
| 627 | +{ | |
| 628 | + struct netdev_private *np = netdev_priv(dev); | |
| 629 | + const int irq = np->pdev->irq; | |
| 630 | + int i; | |
| 631 | + | |
| 632 | + i = alloc_list(dev); | |
| 633 | + if (i) | |
| 634 | + return i; | |
| 635 | + | |
| 636 | + rio_hw_init(dev); | |
| 637 | + | |
| 638 | + i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev); | |
| 639 | + if (i) { | |
| 640 | + rio_hw_stop(dev); | |
| 641 | + free_list(dev); | |
| 642 | + return i; | |
| 643 | + } | |
| 644 | + | |
| 645 | + setup_timer(&np->timer, rio_timer, (unsigned long)dev); | |
| 646 | + np->timer.expires = jiffies + 1 * HZ; | |
| 647 | + add_timer(&np->timer); | |
| 525 | 648 | |
| 526 | 649 | netif_start_queue (dev); |
| 527 | 650 | |
| @@ -586,60 +709,6 @@ rio_tx_timeout (struct net_device *dev) · 58 unmodified lines | ||
| 586 | 709 | dev->trans_start = jiffies; /* prevent tx timeout */ |
| 587 | 710 | } |
| 588 | 711 | |
| 589 | − /* allocate and initialize Tx and Rx descriptors */ | |
| 590 | −static void | |
| 591 | −alloc_list (struct net_device *dev) | |
| 592 | −{ | |
| 593 | − struct netdev_private *np = netdev_priv(dev); | |
| 594 | − void __iomem *ioaddr = np->ioaddr; | |
| 595 | − int i; | |
| 596 | − | |
| 597 | − np->cur_rx = np->cur_tx = 0; | |
| 598 | − np->old_rx = np->old_tx = 0; | |
| 599 | − np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32); | |
| 600 | − | |
| 601 | − /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */ | |
| 602 | − for (i = 0; i < TX_RING_SIZE; i++) { | |
| 603 | − np->tx_skbuff[i] = NULL; | |
| 604 | − np->tx_ring[i].status = cpu_to_le64 (TFDDone); | |
| 605 | − np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma + | |
| 606 | − ((i+1)%TX_RING_SIZE) * | |
| 607 | − sizeof (struct netdev_desc)); | |
| 608 | − } | |
| 609 | − | |
| 610 | − /* Initialize Rx descriptors */ | |
| 611 | − for (i = 0; i < RX_RING_SIZE; i++) { | |
| 612 | − np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma + | |
| 613 | − ((i + 1) % RX_RING_SIZE) * | |
| 614 | − sizeof (struct netdev_desc)); | |
| 615 | − np->rx_ring[i].status = 0; | |
| 616 | − np->rx_ring[i].fraginfo = 0; | |
| 617 | − np->rx_skbuff[i] = NULL; | |
| 618 | − } | |
| 619 | − | |
| 620 | − /* Allocate the rx buffers */ | |
| 621 | − for (i = 0; i < RX_RING_SIZE; i++) { | |
| 622 | − /* Allocated fixed size of skbuff */ | |
| 623 | − struct sk_buff *skb; | |
| 624 | − | |
| 625 | − skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); | |
| 626 | − np->rx_skbuff[i] = skb; | |
| 627 | − if (skb == NULL) | |
| 628 | − break; | |
| 629 | − | |
| 630 | − /* Rubicon now supports 40 bits of addressing space. */ | |
| 631 | − np->rx_ring[i].fraginfo = | |
| 632 | − cpu_to_le64 ( pci_map_single ( | |
| 633 | − np->pdev, skb->data, np->rx_buf_sz, | |
| 634 | − PCI_DMA_FROMDEVICE)); | |
| 635 | − np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); | |
| 636 | − } | |
| 637 | − | |
| 638 | − /* Set RFDListPtr */ | |
| 639 | − dw32(RFDListPtr0, np->rx_ring_dma); | |
| 640 | − dw32(RFDListPtr1, 0); | |
| 641 | −} | |
| 642 | − | |
| 643 | 712 | static netdev_tx_t |
| 644 | 713 | start_xmit (struct sk_buff *skb, struct net_device *dev) |
| 645 | 714 | { |
| @@ -748,11 +817,6 @@ rio_interrupt (int irq, void *dev_instance) · 102 unmodified lines | ||
| 748 | 817 | return IRQ_RETVAL(handled); |
| 749 | 818 | } |
| 750 | 819 | |
| 751 | −static inline dma_addr_t desc_to_dma(struct netdev_desc *desc) | |
| 752 | −{ | |
| 753 | − return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48); | |
| 754 | −} | |
| 755 | − | |
| 756 | 820 | static void |
| 757 | 821 | rio_free_tx (struct net_device *dev, int irq) |
| 758 | 822 | { |
| @@ -1730,44 +1794,16 @@ static int · 971 unmodified lines | ||
| 1730 | 1794 | rio_close (struct net_device *dev) |
| 1731 | 1795 | { |
| 1732 | 1796 | struct netdev_private *np = netdev_priv(dev); |
| 1733 | − void __iomem *ioaddr = np->ioaddr; | |
| 1734 | − | |
| 1735 | 1797 | struct pci_dev *pdev = np->pdev; |
| 1736 | − struct sk_buff *skb; | |
| 1737 | − int i; | |
| 1738 | 1798 | |
| 1739 | 1799 | netif_stop_queue (dev); |
| 1740 | 1800 | |
| 1741 | − /* Disable interrupts */ | |
| 1742 | − dw16(IntEnable, 0); | |
| 1743 | − | |
| 1744 | − /* Stop Tx and Rx logics */ | |
| 1745 | − dw32(MACCtrl, TxDisable | RxDisable | StatsDisable); | |
| 1801 | + rio_hw_stop(dev); | |
| 1746 | 1802 | |
| 1747 | 1803 | free_irq(pdev->irq, dev); |
| 1748 | 1804 | del_timer_sync (&np->timer); |
| 1749 | 1805 | |
| 1750 | − /* Free all the skbuffs in the queue. */ | |
| 1751 | − for (i = 0; i < RX_RING_SIZE; i++) { | |
| 1752 | − skb = np->rx_skbuff[i]; | |
| 1753 | − if (skb) { | |
| 1754 | − pci_unmap_single(pdev, desc_to_dma(&np->rx_ring[i]), | |
| 1755 | − skb->len, PCI_DMA_FROMDEVICE); | |
| 1756 | − dev_kfree_skb (skb); | |
| 1757 | − np->rx_skbuff[i] = NULL; | |
| 1758 | − } | |
| 1759 | − np->rx_ring[i].status = 0; | |
| 1760 | − np->rx_ring[i].fraginfo = 0; | |
| 1761 | − } | |
| 1762 | − for (i = 0; i < TX_RING_SIZE; i++) { | |
| 1763 | − skb = np->tx_skbuff[i]; | |
| 1764 | − if (skb) { | |
| 1765 | − pci_unmap_single(pdev, desc_to_dma(&np->tx_ring[i]), | |
| 1766 | − skb->len, PCI_DMA_TODEVICE); | |
| 1767 | − dev_kfree_skb (skb); | |
| 1768 | − np->tx_skbuff[i] = NULL; | |
| 1769 | − } | |
| 1770 | − } | |
| 1806 | + free_list(dev); | |
| 1771 | 1807 | |
| 1772 | 1808 | return 0; |
| 1773 | 1809 | } |
| @@ -1795,11 +1831,55 @@ rio_remove1 (struct pci_dev *pdev) · 21 unmodified lines | ||
| 1795 | 1831 | } |
| 1796 | 1832 | } |
| 1797 | 1833 | |
| 1834 | +#ifdef CONFIG_PM_SLEEP | |
| 1835 | +static int rio_suspend(struct device *device) | |
| 1836 | +{ | |
| 1837 | + struct net_device *dev = dev_get_drvdata(device); | |
| 1838 | + struct netdev_private *np = netdev_priv(dev); | |
| 1839 | + | |
| 1840 | + if (!netif_running(dev)) | |
| 1841 | + return 0; | |
| 1842 | + | |
| 1843 | + netif_device_detach(dev); | |
| 1844 | + del_timer_sync(&np->timer); | |
| 1845 | + rio_hw_stop(dev); | |
| 1846 | + | |
| 1847 | + return 0; | |
| 1848 | +} | |
| 1849 | + | |
| 1850 | +static int rio_resume(struct device *device) | |
| 1851 | +{ | |
| 1852 | + struct net_device *dev = dev_get_drvdata(device); | |
| 1853 | + struct netdev_private *np = netdev_priv(dev); | |
| 1854 | + | |
| 1855 | + if (!netif_running(dev)) | |
| 1856 | + return 0; | |
| 1857 | + | |
| 1858 | + rio_reset_ring(np); | |
| 1859 | + rio_hw_init(dev); | |
| 1860 | + np->timer.expires = jiffies + 1 * HZ; | |
| 1861 | + add_timer(&np->timer); | |
| 1862 | + netif_device_attach(dev); | |
| 1863 | + dl2k_enable_int(np); | |
| 1864 | + | |
| 1865 | + return 0; | |
| 1866 | +} | |
| 1867 | + | |
| 1868 | +static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume); | |
| 1869 | +#define RIO_PM_OPS (&rio_pm_ops) | |
| 1870 | + | |
| 1871 | +#else | |
| 1872 | + | |
| 1873 | +#define RIO_PM_OPS NULL | |
| 1874 | + | |
| 1875 | +#endif /* CONFIG_PM_SLEEP */ | |
| 1876 | + | |
| 1798 | 1877 | static struct pci_driver rio_driver = { |
| 1799 | 1878 | .name = "dl2k", |
| 1800 | 1879 | .id_table = rio_pci_tbl, |
| 1801 | 1880 | .probe = rio_probe1, |
| 1802 | 1881 | .remove = rio_remove1, |
| 1882 | + .driver.pm = RIO_PM_OPS, | |
| 1803 | 1883 | }; |
| 1804 | 1884 | |
| 1805 | 1885 | module_pci_driver(rio_driver); |
| @@ -255,15 +255,9 @@ static int dnet_mii_probe(struct net_device *dev) · 254 unmodified lines | ||
| 255 | 255 | { |
| 256 | 256 | struct dnet *bp = netdev_priv(dev); |
| 257 | 257 | struct phy_device *phydev = NULL; |
| 258 | − int phy_addr; | |
| 259 | 258 | |
| 260 | 259 | /* find the first phy */ |
| 261 | − for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
| 262 | − if (bp->mii_bus->phy_map[phy_addr]) { | |
| 263 | − phydev = bp->mii_bus->phy_map[phy_addr]; | |
| 264 | − break; | |
| 265 | − } | |
| 266 | − } | |
| 260 | + phydev = phy_find_first(bp->mii_bus); | |
| 267 | 261 | |
| 268 | 262 | if (!phydev) { |
| 269 | 263 | printk(KERN_ERR "%s: no PHY found\n", dev->name); |
| @@ -274,11 +268,11 @@ static int dnet_mii_probe(struct net_device *dev) · 4 unmodified lines | ||
| 274 | 268 | |
| 275 | 269 | /* attach the mac to the phy */ |
| 276 | 270 | if (bp->capabilities & DNET_HAS_RMII) { |
| 277 | − phydev = phy_connect(dev, dev_name(&phydev->dev), | |
| 271 | + phydev = phy_connect(dev, phydev_name(phydev), | |
| 278 | 272 | &dnet_handle_link_change, |
| 279 | 273 | PHY_INTERFACE_MODE_RMII); |
| 280 | 274 | } else { |
| 281 | − phydev = phy_connect(dev, dev_name(&phydev->dev), | |
| 275 | + phydev = phy_connect(dev, phydev_name(phydev), | |
| 282 | 276 | &dnet_handle_link_change, |
| 283 | 277 | PHY_INTERFACE_MODE_MII); |
| 284 | 278 | } |
| @@ -308,7 +302,7 @@ static int dnet_mii_probe(struct net_device *dev) · 23 unmodified lines | ||
| 308 | 302 | |
| 309 | 303 | static int dnet_mii_init(struct dnet *bp) |
| 310 | 304 | { |
| 311 | − int err, i; | |
| 305 | + int err; | |
| 312 | 306 | |
| 313 | 307 | bp->mii_bus = mdiobus_alloc(); |
| 314 | 308 | if (bp->mii_bus == NULL) |
| @@ -323,16 +317,6 @@ static int dnet_mii_init(struct dnet *bp) · 8 unmodified lines | ||
| 323 | 317 | |
| 324 | 318 | bp->mii_bus->priv = bp; |
| 325 | 319 | |
| 326 | − bp->mii_bus->irq = devm_kmalloc(&bp->pdev->dev, | |
| 327 | − sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
| 328 | − if (!bp->mii_bus->irq) { | |
| 329 | − err = -ENOMEM; | |
| 330 | − goto err_out; | |
| 331 | − } | |
| 332 | − | |
| 333 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 334 | − bp->mii_bus->irq[i] = PHY_POLL; | |
| 335 | − | |
| 336 | 320 | if (mdiobus_register(bp->mii_bus)) { |
| 337 | 321 | err = -ENXIO; |
| 338 | 322 | goto err_out; |
| @@ -892,9 +876,7 @@ static int dnet_probe(struct platform_device *pdev) · 553 unmodified lines | ||
| 892 | 876 | (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ", |
| 893 | 877 | (bp->capabilities & DNET_HAS_DMA) ? "" : "no "); |
| 894 | 878 | phydev = bp->phy_dev; |
| 895 | − dev_info(&pdev->dev, "attached PHY driver [%s] " | |
| 896 | − "(mii_bus:phy_addr=%s, irq=%d)\n", | |
| 897 | − phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
| 879 | + phy_attached_info(phydev); | |
| 898 | 880 | |
| 899 | 881 | return 0; |
| 900 | 882 | |
| @@ -37,7 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | #include "be_hw.h" |
| 38 | 38 | #include "be_roce.h" |
| 39 | 39 | |
| 40 | −#define DRV_VER "10.6.0.3" | |
| 40 | +#define DRV_VER "11.0.0.0" | |
| 41 | 41 | #define DRV_NAME "be2net" |
| 42 | 42 | #define BE_NAME "Emulex BladeEngine2" |
| 43 | 43 | #define BE3_NAME "Emulex BladeEngine3" |
| @@ -521,7 +521,7 @@ struct be_adapter { · 477 unmodified lines | ||
| 521 | 521 | struct be_drv_stats drv_stats; |
| 522 | 522 | struct be_aic_obj aic_obj[MAX_EVT_QS]; |
| 523 | 523 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
| 524 | − u16 recommended_prio; /* Recommended Priority */ | |
| 524 | + u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */ | |
| 525 | 525 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
| 526 | 526 | |
| 527 | 527 | struct be_dma_mem stats_cmd; |
| @@ -547,10 +547,6 @@ struct be_adapter { · 19 unmodified lines | ||
| 547 | 547 | |
| 548 | 548 | u32 beacon_state; /* for set_phys_id */ |
| 549 | 549 | |
| 550 | − bool eeh_error; | |
| 551 | − bool fw_timeout; | |
| 552 | − bool hw_error; | |
| 553 | − | |
| 554 | 550 | u32 port_num; |
| 555 | 551 | char port_name; |
| 556 | 552 | u8 mc_type; |
| @@ -574,6 +570,8 @@ struct be_adapter { · 17 unmodified lines | ||
| 574 | 570 | struct be_resources pool_res; /* resources available for the port */ |
| 575 | 571 | struct be_resources res; /* resources available for the func */ |
| 576 | 572 | u16 num_vfs; /* Number of VFs provisioned by PF */ |
| 573 | + u8 pf_num; /* Numbering used by FW, starts at 0 */ | |
| 574 | + u8 vf_num; /* Numbering used by FW, starts at 1 */ | |
| 577 | 575 | u8 virtfn; |
| 578 | 576 | struct be_vf_cfg *vf_cfg; |
| 579 | 577 | bool be3_native; |
| @@ -591,11 +589,10 @@ struct be_adapter { · 11 unmodified lines | ||
| 591 | 589 | u32 msg_enable; |
| 592 | 590 | int be_get_temp_freq; |
| 593 | 591 | struct be_hwmon hwmon_info; |
| 594 | − u8 pf_number; | |
| 595 | − u8 pci_func_num; | |
| 596 | 592 | struct rss_info rss_info; |
| 597 | 593 | /* Filters for packets that need to be sent to BMC */ |
| 598 | 594 | u32 bmc_filt_mask; |
| 595 | + u32 fat_dump_len; | |
| 599 | 596 | u16 serial_num[CNTL_SERIAL_NUM_WORDS]; |
| 600 | 597 | }; |
| 601 | 598 | |
| @@ -308,8 +308,7 @@ static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, · 307 unmodified lines | ||
| 308 | 308 | |
| 309 | 309 | if (evt->valid) { |
| 310 | 310 | adapter->vlan_prio_bmap = evt->available_priority_bmap; |
| 311 | − adapter->recommended_prio &= ~VLAN_PRIO_MASK; | |
| 312 | − adapter->recommended_prio = | |
| 311 | + adapter->recommended_prio_bits = | |
| 313 | 312 | evt->reco_default_priority << VLAN_PRIO_SHIFT; |
| 314 | 313 | } |
| 315 | 314 | } |
| @@ -1713,49 +1712,40 @@ err: · 1397 unmodified lines | ||
| 1713 | 1712 | } |
| 1714 | 1713 | |
| 1715 | 1714 | /* Uses synchronous mcc */ |
| 1716 | −int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) | |
| 1715 | +int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size) | |
| 1717 | 1716 | { |
| 1718 | − struct be_mcc_wrb *wrb; | |
| 1717 | + struct be_mcc_wrb wrb = {0}; | |
| 1719 | 1718 | struct be_cmd_req_get_fat *req; |
| 1720 | 1719 | int status; |
| 1721 | 1720 | |
| 1722 | − spin_lock_bh(&adapter->mcc_lock); | |
| 1723 | − | |
| 1724 | − wrb = wrb_from_mccq(adapter); | |
| 1725 | − if (!wrb) { | |
| 1726 | − status = -EBUSY; | |
| 1727 | − goto err; | |
| 1728 | − } | |
| 1729 | − req = embedded_payload(wrb); | |
| 1721 | + req = embedded_payload(&wrb); | |
| 1730 | 1722 | |
| 1731 | 1723 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
| 1732 | − OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, | |
| 1733 | − NULL); | |
| 1724 | + OPCODE_COMMON_MANAGE_FAT, sizeof(*req), | |
| 1725 | + &wrb, NULL); | |
| 1734 | 1726 | req->fat_operation = cpu_to_le32(QUERY_FAT); |
| 1735 | − status = be_mcc_notify_wait(adapter); | |
| 1727 | + status = be_cmd_notify_wait(adapter, &wrb); | |
| 1736 | 1728 | if (!status) { |
| 1737 | − struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); | |
| 1729 | + struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb); | |
| 1738 | 1730 | |
| 1739 | − if (log_size && resp->log_size) | |
| 1740 | − *log_size = le32_to_cpu(resp->log_size) - | |
| 1731 | + if (dump_size && resp->log_size) | |
| 1732 | + *dump_size = le32_to_cpu(resp->log_size) - | |
| 1741 | 1733 | sizeof(u32); |
| 1742 | 1734 | } |
| 1743 | −err: | |
| 1744 | − spin_unlock_bh(&adapter->mcc_lock); | |
| 1745 | 1735 | return status; |
| 1746 | 1736 | } |
| 1747 | 1737 | |
| 1748 | −int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) | |
| 1738 | +int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf) | |
| 1749 | 1739 | { |
| 1750 | 1740 | struct be_dma_mem get_fat_cmd; |
| 1751 | 1741 | struct be_mcc_wrb *wrb; |
| 1752 | 1742 | struct be_cmd_req_get_fat *req; |
| 1753 | 1743 | u32 offset = 0, total_size, buf_size, |
| 1754 | 1744 | log_offset = sizeof(u32), payload_len; |
| 1755 | − int status = 0; | |
| 1745 | + int status; | |
| 1756 | 1746 | |
| 1757 | 1747 | if (buf_len == 0) |
| 1758 | − return -EIO; | |
| 1748 | + return 0; | |
| 1759 | 1749 | |
| 1760 | 1750 | total_size = buf_len; |
| 1761 | 1751 | |
| @@ -1763,11 +1753,8 @@ int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) · 1 unmodified line | ||
| 1763 | 1753 | get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, |
| 1764 | 1754 | get_fat_cmd.size, |
| 1765 | 1755 | &get_fat_cmd.dma, GFP_ATOMIC); |
| 1766 | − if (!get_fat_cmd.va) { | |
| 1767 | − dev_err(&adapter->pdev->dev, | |
| 1768 | − "Memory allocation failure while reading FAT data\n"); | |
| 1756 | + if (!get_fat_cmd.va) | |
| 1769 | 1757 | return -ENOMEM; |
| 1770 | − } | |
| 1771 | 1758 | |
| 1772 | 1759 | spin_lock_bh(&adapter->mcc_lock); |
| 1773 | 1760 | |
| @@ -2291,10 +2278,11 @@ err: · 517 unmodified lines | ||
| 2291 | 2278 | return status; |
| 2292 | 2279 | } |
| 2293 | 2280 | |
| 2294 | −int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, | |
| 2295 | − u32 data_size, u32 data_offset, | |
| 2296 | − const char *obj_name, u32 *data_written, | |
| 2297 | − u8 *change_status, u8 *addn_status) | |
| 2281 | +static int lancer_cmd_write_object(struct be_adapter *adapter, | |
| 2282 | + struct be_dma_mem *cmd, u32 data_size, | |
| 2283 | + u32 data_offset, const char *obj_name, | |
| 2284 | + u32 *data_written, u8 *change_status, | |
| 2285 | + u8 *addn_status) | |
| 2298 | 2286 | { |
| 2299 | 2287 | struct be_mcc_wrb *wrb; |
| 2300 | 2288 | struct lancer_cmd_req_write_object *req; |
| @@ -2410,7 +2398,8 @@ int be_cmd_query_sfp_info(struct be_adapter *adapter) · 109 unmodified lines | ||
| 2410 | 2398 | return status; |
| 2411 | 2399 | } |
| 2412 | 2400 | |
| 2413 | −int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name) | |
| 2401 | +static int lancer_cmd_delete_object(struct be_adapter *adapter, | |
| 2402 | + const char *obj_name) | |
| 2414 | 2403 | { |
| 2415 | 2404 | struct lancer_cmd_req_delete_object *req; |
| 2416 | 2405 | struct be_mcc_wrb *wrb; |
| @@ -2485,9 +2474,9 @@ err_unlock: · 68 unmodified lines | ||
| 2485 | 2474 | return status; |
| 2486 | 2475 | } |
| 2487 | 2476 | |
| 2488 | −int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, | |
| 2489 | − u32 flash_type, u32 flash_opcode, u32 img_offset, | |
| 2490 | − u32 buf_size) | |
| 2477 | +static int be_cmd_write_flashrom(struct be_adapter *adapter, | |
| 2478 | + struct be_dma_mem *cmd, u32 flash_type, | |
| 2479 | + u32 flash_opcode, u32 img_offset, u32 buf_size) | |
| 2491 | 2480 | { |
| 2492 | 2481 | struct be_mcc_wrb *wrb; |
| 2493 | 2482 | struct be_cmd_write_flashrom *req; |
| @@ -2533,8 +2522,8 @@ err_unlock: · 39 unmodified lines | ||
| 2533 | 2522 | return status; |
| 2534 | 2523 | } |
| 2535 | 2524 | |
| 2536 | −int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, | |
| 2537 | − u16 img_optype, u32 img_offset, u32 crc_offset) | |
| 2525 | +static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, | |
| 2526 | + u16 img_optype, u32 img_offset, u32 crc_offset) | |
| 2538 | 2527 | { |
| 2539 | 2528 | struct be_cmd_read_flash_crc *req; |
| 2540 | 2529 | struct be_mcc_wrb *wrb; |
| @@ -2571,6 +2560,579 @@ err: · 30 unmodified lines | ||
| 2571 | 2560 | return status; |
| 2572 | 2561 | } |
| 2573 | 2562 | |
| 2563 | +static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "}; | |
| 2564 | + | |
| 2565 | +static bool phy_flashing_required(struct be_adapter *adapter) | |
| 2566 | +{ | |
| 2567 | + return (adapter->phy.phy_type == PHY_TYPE_TN_8022 && | |
| 2568 | + adapter->phy.interface_type == PHY_TYPE_BASET_10GB); | |
| 2569 | +} | |
| 2570 | + | |
| 2571 | +static bool is_comp_in_ufi(struct be_adapter *adapter, | |
| 2572 | + struct flash_section_info *fsec, int type) | |
| 2573 | +{ | |
| 2574 | + int i = 0, img_type = 0; | |
| 2575 | + struct flash_section_info_g2 *fsec_g2 = NULL; | |
| 2576 | + | |
| 2577 | + if (BE2_chip(adapter)) | |
| 2578 | + fsec_g2 = (struct flash_section_info_g2 *)fsec; | |
| 2579 | + | |
| 2580 | + for (i = 0; i < MAX_FLASH_COMP; i++) { | |
| 2581 | + if (fsec_g2) | |
| 2582 | + img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type); | |
| 2583 | + else | |
| 2584 | + img_type = le32_to_cpu(fsec->fsec_entry[i].type); | |
| 2585 | + | |
| 2586 | + if (img_type == type) | |
| 2587 | + return true; | |
| 2588 | + } | |
| 2589 | + return false; | |
| 2590 | +} | |
| 2591 | + | |
| 2592 | +static struct flash_section_info *get_fsec_info(struct be_adapter *adapter, | |
| 2593 | + int header_size, | |
| 2594 | + const struct firmware *fw) | |
| 2595 | +{ | |
| 2596 | + struct flash_section_info *fsec = NULL; | |
| 2597 | + const u8 *p = fw->data; | |
| 2598 | + | |
| 2599 | + p += header_size; | |
| 2600 | + while (p < (fw->data + fw->size)) { | |
| 2601 | + fsec = (struct flash_section_info *)p; | |
| 2602 | + if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie))) | |
| 2603 | + return fsec; | |
| 2604 | + p += 32; | |
| 2605 | + } | |
| 2606 | + return NULL; | |
| 2607 | +} | |
| 2608 | + | |
| 2609 | +static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p, | |
| 2610 | + u32 img_offset, u32 img_size, int hdr_size, | |
| 2611 | + u16 img_optype, bool *crc_match) | |
| 2612 | +{ | |
| 2613 | + u32 crc_offset; | |
| 2614 | + int status; | |
| 2615 | + u8 crc[4]; | |
| 2616 | + | |
| 2617 | + status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset, | |
| 2618 | + img_size - 4); | |
| 2619 | + if (status) | |
| 2620 | + return status; | |
| 2621 | + | |
| 2622 | + crc_offset = hdr_size + img_offset + img_size - 4; | |
| 2623 | + | |
| 2624 | + /* Skip flashing, if crc of flashed region matches */ | |
| 2625 | + if (!memcmp(crc, p + crc_offset, 4)) | |
| 2626 | + *crc_match = true; | |
| 2627 | + else | |
| 2628 | + *crc_match = false; | |
| 2629 | + | |
| 2630 | + return status; | |
| 2631 | +} | |
| 2632 | + | |
| 2633 | +static int be_flash(struct be_adapter *adapter, const u8 *img, | |
| 2634 | + struct be_dma_mem *flash_cmd, int optype, int img_size, | |
| 2635 | + u32 img_offset) | |
| 2636 | +{ | |
| 2637 | + u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0; | |
| 2638 | + struct be_cmd_write_flashrom *req = flash_cmd->va; | |
| 2639 | + int status; | |
| 2640 | + | |
| 2641 | + while (total_bytes) { | |
| 2642 | + num_bytes = min_t(u32, 32 * 1024, total_bytes); | |
| 2643 | + | |
| 2644 | + total_bytes -= num_bytes; | |
| 2645 | + | |
| 2646 | + if (!total_bytes) { | |
| 2647 | + if (optype == OPTYPE_PHY_FW) | |
| 2648 | + flash_op = FLASHROM_OPER_PHY_FLASH; | |
| 2649 | + else | |
| 2650 | + flash_op = FLASHROM_OPER_FLASH; | |
| 2651 | + } else { | |
| 2652 | + if (optype == OPTYPE_PHY_FW) | |
| 2653 | + flash_op = FLASHROM_OPER_PHY_SAVE; | |
| 2654 | + else | |
| 2655 | + flash_op = FLASHROM_OPER_SAVE; | |
| 2656 | + } | |
| 2657 | + | |
| 2658 | + memcpy(req->data_buf, img, num_bytes); | |
| 2659 | + img += num_bytes; | |
| 2660 | + status = be_cmd_write_flashrom(adapter, flash_cmd, optype, | |
| 2661 | + flash_op, img_offset + | |
| 2662 | + bytes_sent, num_bytes); | |
| 2663 | + if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST && | |
| 2664 | + optype == OPTYPE_PHY_FW) | |
| 2665 | + break; | |
| 2666 | + else if (status) | |
| 2667 | + return status; | |
| 2668 | + | |
| 2669 | + bytes_sent += num_bytes; | |
| 2670 | + } | |
| 2671 | + return 0; | |
| 2672 | +} | |
| 2673 | + | |
| 2674 | +/* For BE2, BE3 and BE3-R */ | |
| 2675 | +static int be_flash_BEx(struct be_adapter *adapter, | |
| 2676 | + const struct firmware *fw, | |
| 2677 | + struct be_dma_mem *flash_cmd, int num_of_images) | |
| 2678 | +{ | |
| 2679 | + int img_hdrs_size = (num_of_images * sizeof(struct image_hdr)); | |
| 2680 | + struct device *dev = &adapter->pdev->dev; | |
| 2681 | + struct flash_section_info *fsec = NULL; | |
| 2682 | + int status, i, filehdr_size, num_comp; | |
| 2683 | + const struct flash_comp *pflashcomp; | |
| 2684 | + bool crc_match; | |
| 2685 | + const u8 *p; | |
| 2686 | + | |
| 2687 | + struct flash_comp gen3_flash_types[] = { | |
| 2688 | + { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE, | |
| 2689 | + BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI}, | |
| 2690 | + { BE3_REDBOOT_START, OPTYPE_REDBOOT, | |
| 2691 | + BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE}, | |
| 2692 | + { BE3_ISCSI_BIOS_START, OPTYPE_BIOS, | |
| 2693 | + BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI}, | |
| 2694 | + { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS, | |
| 2695 | + BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE}, | |
| 2696 | + { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS, | |
| 2697 | + BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE}, | |
| 2698 | + { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP, | |
| 2699 | + BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI}, | |
| 2700 | + { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE, | |
| 2701 | + BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE}, | |
| 2702 | + { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP, | |
| 2703 | + BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}, | |
| 2704 | + { BE3_NCSI_START, OPTYPE_NCSI_FW, | |
| 2705 | + BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI}, | |
| 2706 | + { BE3_PHY_FW_START, OPTYPE_PHY_FW, | |
| 2707 | + BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY} | |
| 2708 | + }; | |
| 2709 | + | |
| 2710 | + struct flash_comp gen2_flash_types[] = { | |
| 2711 | + { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE, | |
| 2712 | + BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI}, | |
| 2713 | + { BE2_REDBOOT_START, OPTYPE_REDBOOT, | |
| 2714 | + BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE}, | |
| 2715 | + { BE2_ISCSI_BIOS_START, OPTYPE_BIOS, | |
| 2716 | + BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI}, | |
| 2717 | + { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS, | |
| 2718 | + BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE}, | |
| 2719 | + { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS, | |
| 2720 | + BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE}, | |
| 2721 | + { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP, | |
| 2722 | + BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI}, | |
| 2723 | + { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE, | |
| 2724 | + BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE}, | |
| 2725 | + { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP, | |
| 2726 | + BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE} | |
| 2727 | + }; | |
| 2728 | + | |
| 2729 | + if (BE3_chip(adapter)) { | |
| 2730 | + pflashcomp = gen3_flash_types; | |
| 2731 | + filehdr_size = sizeof(struct flash_file_hdr_g3); | |
| 2732 | + num_comp = ARRAY_SIZE(gen3_flash_types); | |
| 2733 | + } else { | |
| 2734 | + pflashcomp = gen2_flash_types; | |
| 2735 | + filehdr_size = sizeof(struct flash_file_hdr_g2); | |
| 2736 | + num_comp = ARRAY_SIZE(gen2_flash_types); | |
| 2737 | + img_hdrs_size = 0; | |
| 2738 | + } | |
| 2739 | + | |
| 2740 | + /* Get flash section info*/ | |
| 2741 | + fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw); | |
| 2742 | + if (!fsec) { | |
| 2743 | + dev_err(dev, "Invalid Cookie. FW image may be corrupted\n"); | |
| 2744 | + return -1; | |
| 2745 | + } | |
| 2746 | + for (i = 0; i < num_comp; i++) { | |
| 2747 | + if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type)) | |
| 2748 | + continue; | |
| 2749 | + | |
| 2750 | + if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) && | |
| 2751 | + memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0) | |
| 2752 | + continue; | |
| 2753 | + | |
| 2754 | + if (pflashcomp[i].optype == OPTYPE_PHY_FW && | |
| 2755 | + !phy_flashing_required(adapter)) | |
| 2756 | + continue; | |
| 2757 | + | |
| 2758 | + if (pflashcomp[i].optype == OPTYPE_REDBOOT) { | |
| 2759 | + status = be_check_flash_crc(adapter, fw->data, | |
| 2760 | + pflashcomp[i].offset, | |
| 2761 | + pflashcomp[i].size, | |
| 2762 | + filehdr_size + | |
| 2763 | + img_hdrs_size, | |
| 2764 | + OPTYPE_REDBOOT, &crc_match); | |
| 2765 | + if (status) { | |
| 2766 | + dev_err(dev, | |
| 2767 | + "Could not get CRC for 0x%x region\n", | |
| 2768 | + pflashcomp[i].optype); | |
| 2769 | + continue; | |
| 2770 | + } | |
| 2771 | + | |
| 2772 | + if (crc_match) | |
| 2773 | + continue; | |
| 2774 | + } | |
| 2775 | + | |
| 2776 | + p = fw->data + filehdr_size + pflashcomp[i].offset + | |
| 2777 | + img_hdrs_size; | |
| 2778 | + if (p + pflashcomp[i].size > fw->data + fw->size) | |
| 2779 | + return -1; | |
| 2780 | + | |
| 2781 | + status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype, | |
| 2782 | + pflashcomp[i].size, 0); | |
| 2783 | + if (status) { | |
| 2784 | + dev_err(dev, "Flashing section type 0x%x failed\n", | |
| 2785 | + pflashcomp[i].img_type); | |
| 2786 | + return status; | |
| 2787 | + } | |
| 2788 | + } | |
| 2789 | + return 0; | |
| 2790 | +} | |
| 2791 | + | |
| 2792 | +static u16 be_get_img_optype(struct flash_section_entry fsec_entry) | |
| 2793 | +{ | |
| 2794 | + u32 img_type = le32_to_cpu(fsec_entry.type); | |
| 2795 | + u16 img_optype = le16_to_cpu(fsec_entry.optype); | |
| 2796 | + | |
| 2797 | + if (img_optype != 0xFFFF) | |
| 2798 | + return img_optype; | |
| 2799 | + | |
| 2800 | + switch (img_type) { | |
| 2801 | + case IMAGE_FIRMWARE_ISCSI: | |
| 2802 | + img_optype = OPTYPE_ISCSI_ACTIVE; | |
| 2803 | + break; | |
| 2804 | + case IMAGE_BOOT_CODE: | |
| 2805 | + img_optype = OPTYPE_REDBOOT; | |
| 2806 | + break; | |
| 2807 | + case IMAGE_OPTION_ROM_ISCSI: | |
| 2808 | + img_optype = OPTYPE_BIOS; | |
| 2809 | + break; | |
| 2810 | + case IMAGE_OPTION_ROM_PXE: | |
| 2811 | + img_optype = OPTYPE_PXE_BIOS; | |
| 2812 | + break; | |
| 2813 | + case IMAGE_OPTION_ROM_FCOE: | |
| 2814 | + img_optype = OPTYPE_FCOE_BIOS; | |
| 2815 | + break; | |
| 2816 | + case IMAGE_FIRMWARE_BACKUP_ISCSI: | |
| 2817 | + img_optype = OPTYPE_ISCSI_BACKUP; | |
| 2818 | + break; | |
| 2819 | + case IMAGE_NCSI: | |
| 2820 | + img_optype = OPTYPE_NCSI_FW; | |
| 2821 | + break; | |
| 2822 | + case IMAGE_FLASHISM_JUMPVECTOR: | |
| 2823 | + img_optype = OPTYPE_FLASHISM_JUMPVECTOR; | |
| 2824 | + break; | |
| 2825 | + case IMAGE_FIRMWARE_PHY: | |
| 2826 | + img_optype = OPTYPE_SH_PHY_FW; | |
| 2827 | + break; | |
| 2828 | + case IMAGE_REDBOOT_DIR: | |
| 2829 | + img_optype = OPTYPE_REDBOOT_DIR; | |
| 2830 | + break; | |
| 2831 | + case IMAGE_REDBOOT_CONFIG: | |
| 2832 | + img_optype = OPTYPE_REDBOOT_CONFIG; | |
| 2833 | + break; | |
| 2834 | + case IMAGE_UFI_DIR: | |
| 2835 | + img_optype = OPTYPE_UFI_DIR; | |
| 2836 | + break; | |
| 2837 | + default: | |
| 2838 | + break; | |
| 2839 | + } | |
| 2840 | + | |
| 2841 | + return img_optype; | |
| 2842 | +} | |
| 2843 | + | |
| 2844 | +static int be_flash_skyhawk(struct be_adapter *adapter, | |
| 2845 | + const struct firmware *fw, | |
| 2846 | + struct be_dma_mem *flash_cmd, int num_of_images) | |
| 2847 | +{ | |
| 2848 | + int img_hdrs_size = num_of_images * sizeof(struct image_hdr); | |
| 2849 | + bool crc_match, old_fw_img, flash_offset_support = true; | |
| 2850 | + struct device *dev = &adapter->pdev->dev; | |
| 2851 | + struct flash_section_info *fsec = NULL; | |
| 2852 | + u32 img_offset, img_size, img_type; | |
| 2853 | + u16 img_optype, flash_optype; | |
| 2854 | + int status, i, filehdr_size; | |
| 2855 | + const u8 *p; | |
| 2856 | + | |
| 2857 | + filehdr_size = sizeof(struct flash_file_hdr_g3); | |
| 2858 | + fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw); | |
| 2859 | + if (!fsec) { | |
| 2860 | + dev_err(dev, "Invalid Cookie. FW image may be corrupted\n"); | |
| 2861 | + return -EINVAL; | |
| 2862 | + } | |
| 2863 | + | |
| 2864 | +retry_flash: | |
| 2865 | + for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) { | |
| 2866 | + img_offset = le32_to_cpu(fsec->fsec_entry[i].offset); | |
| 2867 | + img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size); | |
| 2868 | + img_type = le32_to_cpu(fsec->fsec_entry[i].type); | |
| 2869 | + img_optype = be_get_img_optype(fsec->fsec_entry[i]); | |
| 2870 | + old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF; | |
| 2871 | + | |
| 2872 | + if (img_optype == 0xFFFF) | |
| 2873 | + continue; | |
| 2874 | + | |
| 2875 | + if (flash_offset_support) | |
| 2876 | + flash_optype = OPTYPE_OFFSET_SPECIFIED; | |
| 2877 | + else | |
| 2878 | + flash_optype = img_optype; | |
| 2879 | + | |
| 2880 | + /* Don't bother verifying CRC if an old FW image is being | |
| 2881 | + * flashed | |
| 2882 | + */ | |
| 2883 | + if (old_fw_img) | |
| 2884 | + goto flash; | |
| 2885 | + | |
| 2886 | + status = be_check_flash_crc(adapter, fw->data, img_offset, | |
| 2887 | + img_size, filehdr_size + | |
| 2888 | + img_hdrs_size, flash_optype, | |
| 2889 | + &crc_match); | |
| 2890 | + if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST || | |
| 2891 | + base_status(status) == MCC_STATUS_ILLEGAL_FIELD) { | |
| 2892 | + /* The current FW image on the card does not support | |
| 2893 | + * OFFSET based flashing. Retry using older mechanism | |
| 2894 | + * of OPTYPE based flashing | |
| 2895 | + */ | |
| 2896 | + if (flash_optype == OPTYPE_OFFSET_SPECIFIED) { | |
| 2897 | + flash_offset_support = false; | |
| 2898 | + goto retry_flash; | |
| 2899 | + } | |
| 2900 | + | |
| 2901 | + /* The current FW image on the card does not recognize | |
| 2902 | + * the new FLASH op_type. The FW download is partially | |
| 2903 | + * complete. Reboot the server now to enable FW image | |
| 2904 | + * to recognize the new FLASH op_type. To complete the | |
| 2905 | + * remaining process, download the same FW again after | |
| 2906 | + * the reboot. | |
| 2907 | + */ | |
| 2908 | + dev_err(dev, "Flash incomplete. Reset the server\n"); | |
| 2909 | + dev_err(dev, "Download FW image again after reset\n"); | |
| 2910 | + return -EAGAIN; | |
| 2911 | + } else if (status) { | |
| 2912 | + dev_err(dev, "Could not get CRC for 0x%x region\n", | |
| 2913 | + img_optype); | |
| 2914 | + return -EFAULT; | |
| 2915 | + } | |
| 2916 | + | |
| 2917 | + if (crc_match) | |
| 2918 | + continue; | |
| 2919 | + | |
| 2920 | +flash: | |
| 2921 | + p = fw->data + filehdr_size + img_offset + img_hdrs_size; | |
| 2922 | + if (p + img_size > fw->data + fw->size) | |
| 2923 | + return -1; | |
| 2924 | + | |
| 2925 | + status = be_flash(adapter, p, flash_cmd, flash_optype, img_size, | |
| 2926 | + img_offset); | |
| 2927 | + | |
| 2928 | + /* The current FW image on the card does not support OFFSET | |
| 2929 | + * based flashing. Retry using older mechanism of OPTYPE based | |
| 2930 | + * flashing | |
| 2931 | + */ | |
| 2932 | + if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD && | |
| 2933 | + flash_optype == OPTYPE_OFFSET_SPECIFIED) { | |
| 2934 | + flash_offset_support = false; | |
| 2935 | + goto retry_flash; | |
| 2936 | + } | |
| 2937 | + | |
| 2938 | + /* For old FW images ignore ILLEGAL_FIELD error or errors on | |
| 2939 | + * UFI_DIR region | |
| 2940 | + */ | |
| 2941 | + if (old_fw_img && | |
| 2942 | + (base_status(status) == MCC_STATUS_ILLEGAL_FIELD || | |
| 2943 | + (img_optype == OPTYPE_UFI_DIR && | |
| 2944 | + base_status(status) == MCC_STATUS_FAILED))) { | |
| 2945 | + continue; | |
| 2946 | + } else if (status) { | |
| 2947 | + dev_err(dev, "Flashing section type 0x%x failed\n", | |
| 2948 | + img_type); | |
| 2949 | + | |
| 2950 | + switch (addl_status(status)) { | |
| 2951 | + case MCC_ADDL_STATUS_MISSING_SIGNATURE: | |
| 2952 | + dev_err(dev, | |
| 2953 | + "Digital signature missing in FW\n"); | |
| 2954 | + return -EINVAL; | |
| 2955 | + case MCC_ADDL_STATUS_INVALID_SIGNATURE: | |
| 2956 | + dev_err(dev, | |
| 2957 | + "Invalid digital signature in FW\n"); | |
| 2958 | + return -EINVAL; | |
| 2959 | + default: | |
| 2960 | + return -EFAULT; | |
| 2961 | + } | |
| 2962 | + } | |
| 2963 | + } | |
| 2964 | + return 0; | |
| 2965 | +} | |
| 2966 | + | |
| 2967 | +int lancer_fw_download(struct be_adapter *adapter, | |
| 2968 | + const struct firmware *fw) | |
| 2969 | +{ | |
| 2970 | + struct device *dev = &adapter->pdev->dev; | |
| 2971 | + struct be_dma_mem flash_cmd; | |
| 2972 | + const u8 *data_ptr = NULL; | |
| 2973 | + u8 *dest_image_ptr = NULL; | |
| 2974 | + size_t image_size = 0; | |
| 2975 | + u32 chunk_size = 0; | |
| 2976 | + u32 data_written = 0; | |
| 2977 | + u32 offset = 0; | |
| 2978 | + int status = 0; | |
| 2979 | + u8 add_status = 0; | |
| 2980 | + u8 change_status; | |
| 2981 | + | |
| 2982 | + if (!IS_ALIGNED(fw->size, sizeof(u32))) { | |
| 2983 | + dev_err(dev, "FW image size should be multiple of 4\n"); | |
| 2984 | + return -EINVAL; | |
| 2985 | + } | |
| 2986 | + | |
| 2987 | + flash_cmd.size = sizeof(struct lancer_cmd_req_write_object) | |
| 2988 | + + LANCER_FW_DOWNLOAD_CHUNK; | |
| 2989 | + flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, | |
| 2990 | + &flash_cmd.dma, GFP_KERNEL); | |
| 2991 | + if (!flash_cmd.va) | |
| 2992 | + return -ENOMEM; | |
| 2993 | + | |
| 2994 | + dest_image_ptr = flash_cmd.va + | |
| 2995 | + sizeof(struct lancer_cmd_req_write_object); | |
| 2996 | + image_size = fw->size; | |
| 2997 | + data_ptr = fw->data; | |
| 2998 | + | |
| 2999 | + while (image_size) { | |
| 3000 | + chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK); | |
| 3001 | + | |
| 3002 | + /* Copy the image chunk content. */ | |
| 3003 | + memcpy(dest_image_ptr, data_ptr, chunk_size); | |
| 3004 | + | |
| 3005 | + status = lancer_cmd_write_object(adapter, &flash_cmd, | |
| 3006 | + chunk_size, offset, | |
| 3007 | + LANCER_FW_DOWNLOAD_LOCATION, | |
| 3008 | + &data_written, &change_status, | |
| 3009 | + &add_status); | |
| 3010 | + if (status) | |
| 3011 | + break; | |
| 3012 | + | |
| 3013 | + offset += data_written; | |
| 3014 | + data_ptr += data_written; | |
| 3015 | + image_size -= data_written; | |
| 3016 | + } | |
| 3017 | + | |
| 3018 | + if (!status) { | |
| 3019 | + /* Commit the FW written */ | |
| 3020 | + status = lancer_cmd_write_object(adapter, &flash_cmd, | |
| 3021 | + 0, offset, | |
| 3022 | + LANCER_FW_DOWNLOAD_LOCATION, | |
| 3023 | + &data_written, &change_status, | |
| 3024 | + &add_status); | |
| 3025 | + } | |
| 3026 | + | |
| 3027 | + dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma); | |
| 3028 | + if (status) { | |
| 3029 | + dev_err(dev, "Firmware load error\n"); | |
| 3030 | + return be_cmd_status(status); | |
| 3031 | + } | |
| 3032 | + | |
| 3033 | + dev_info(dev, "Firmware flashed successfully\n"); | |
| 3034 | + | |
| 3035 | + if (change_status == LANCER_FW_RESET_NEEDED) { | |
| 3036 | + dev_info(dev, "Resetting adapter to activate new FW\n"); | |
| 3037 | + status = lancer_physdev_ctrl(adapter, | |
| 3038 | + PHYSDEV_CONTROL_FW_RESET_MASK); | |
| 3039 | + if (status) { | |
| 3040 | + dev_err(dev, "Adapter busy, could not reset FW\n"); | |
| 3041 | + dev_err(dev, "Reboot server to activate new FW\n"); | |
| 3042 | + } | |
| 3043 | + } else if (change_status != LANCER_NO_RESET_NEEDED) { | |
| 3044 | + dev_info(dev, "Reboot server to activate new FW\n"); | |
| 3045 | + } | |
| 3046 | + | |
| 3047 | + return 0; | |
| 3048 | +} | |
| 3049 | + | |
| 3050 | +/* Check if the flash image file is compatible with the adapter that | |
| 3051 | + * is being flashed. | |
| 3052 | + */ | |
| 3053 | +static bool be_check_ufi_compatibility(struct be_adapter *adapter, | |
| 3054 | + struct flash_file_hdr_g3 *fhdr) | |
| 3055 | +{ | |
| 3056 | + if (!fhdr) { | |
| 3057 | + dev_err(&adapter->pdev->dev, "Invalid FW UFI file"); | |
| 3058 | + return false; | |
| 3059 | + } | |
| 3060 | + | |
| 3061 | + /* First letter of the build version is used to identify | |
| 3062 | + * which chip this image file is meant for. | |
| 3063 | + */ | |
| 3064 | + switch (fhdr->build[0]) { | |
| 3065 | + case BLD_STR_UFI_TYPE_SH: | |
| 3066 | + if (!skyhawk_chip(adapter)) | |
| 3067 | + return false; | |
| 3068 | + break; | |
| 3069 | + case BLD_STR_UFI_TYPE_BE3: | |
| 3070 | + if (!BE3_chip(adapter)) | |
| 3071 | + return false; | |
| 3072 | + break; | |
| 3073 | + case BLD_STR_UFI_TYPE_BE2: | |
| 3074 | + if (!BE2_chip(adapter)) | |
| 3075 | + return false; | |
| 3076 | + break; | |
| 3077 | + default: | |
| 3078 | + return false; | |
| 3079 | + } | |
| 3080 | + | |
| 3081 | + /* In BE3 FW images the "asic_type_rev" field doesn't track the | |
| 3082 | + * asic_rev of the chips it is compatible with. | |
| 3083 | + * When asic_type_rev is 0 the image is compatible only with | |
| 3084 | + * pre-BE3-R chips (asic_rev < 0x10) | |
| 3085 | + */ | |
| 3086 | + if (BEx_chip(adapter) && fhdr->asic_type_rev == 0) | |
| 3087 | + return adapter->asic_rev < 0x10; | |
| 3088 | + else | |
| 3089 | + return (fhdr->asic_type_rev >= adapter->asic_rev); | |
| 3090 | +} | |
| 3091 | + | |
| 3092 | +int be_fw_download(struct be_adapter *adapter, const struct firmware *fw) | |
| 3093 | +{ | |
| 3094 | + struct device *dev = &adapter->pdev->dev; | |
| 3095 | + struct flash_file_hdr_g3 *fhdr3; | |
| 3096 | + struct image_hdr *img_hdr_ptr; | |
| 3097 | + int status = 0, i, num_imgs; | |
| 3098 | + struct be_dma_mem flash_cmd; | |
| 3099 | + | |
| 3100 | + fhdr3 = (struct flash_file_hdr_g3 *)fw->data; | |
| 3101 | + if (!be_check_ufi_compatibility(adapter, fhdr3)) { | |
| 3102 | + dev_err(dev, "Flash image is not compatible with adapter\n"); | |
| 3103 | + return -EINVAL; | |
| 3104 | + } | |
| 3105 | + | |
| 3106 | + flash_cmd.size = sizeof(struct be_cmd_write_flashrom); | |
| 3107 | + flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma, | |
| 3108 | + GFP_KERNEL); | |
| 3109 | + if (!flash_cmd.va) | |
| 3110 | + return -ENOMEM; | |
| 3111 | + | |
| 3112 | + num_imgs = le32_to_cpu(fhdr3->num_imgs); | |
| 3113 | + for (i = 0; i < num_imgs; i++) { | |
| 3114 | + img_hdr_ptr = (struct image_hdr *)(fw->data + | |
| 3115 | + (sizeof(struct flash_file_hdr_g3) + | |
| 3116 | + i * sizeof(struct image_hdr))); | |
| 3117 | + if (!BE2_chip(adapter) && | |
| 3118 | + le32_to_cpu(img_hdr_ptr->imageid) != 1) | |
| 3119 | + continue; | |
| 3120 | + | |
| 3121 | + if (skyhawk_chip(adapter)) | |
| 3122 | + status = be_flash_skyhawk(adapter, fw, &flash_cmd, | |
| 3123 | + num_imgs); | |
| 3124 | + else | |
| 3125 | + status = be_flash_BEx(adapter, fw, &flash_cmd, | |
| 3126 | + num_imgs); | |
| 3127 | + } | |
| 3128 | + | |
| 3129 | + dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma); | |
| 3130 | + if (!status) | |
| 3131 | + dev_info(dev, "Firmware flashed successfully\n"); | |
| 3132 | + | |
| 3133 | + return status; | |
| 3134 | +} | |
| 3135 | + | |
| 2574 | 3136 | int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, |
| 2575 | 3137 | struct be_dma_mem *nonemb_cmd) |
| 2576 | 3138 | { |
| @@ -2892,7 +3454,6 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter) · 315 unmodified lines | ||
| 2892 | 3454 | if (!status) { |
| 2893 | 3455 | attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); |
| 2894 | 3456 | adapter->hba_port_num = attribs->hba_attribs.phy_port; |
| 2895 | − adapter->pci_func_num = attribs->pci_func_num; | |
| 2896 | 3457 | serial_num = attribs->hba_attribs.controller_serial_number; |
| 2897 | 3458 | for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++) |
| 2898 | 3459 | adapter->serial_num[i] = le32_to_cpu(serial_num[i]) & |
| @@ -3575,14 +4136,16 @@ int be_cmd_query_port_name(struct be_adapter *adapter) · 676 unmodified lines | ||
| 3575 | 4136 | return status; |
| 3576 | 4137 | } |
| 3577 | 4138 | |
| 3578 | −/* Descriptor type */ | |
| 3579 | −enum { | |
| 3580 | − FUNC_DESC = 1, | |
| 3581 | − VFT_DESC = 2 | |
| 3582 | −}; | |
| 3583 | − | |
| 4139 | +/* When more than 1 NIC descriptor is present in the descriptor list, | |
| 4140 | + * the caller must specify the pf_num to obtain the NIC descriptor | |
| 4141 | + * corresponding to its pci function. | |
| 4142 | + * get_vft must be true when the caller wants the VF-template desc of the | |
| 4143 | + * PF-pool. | |
| 4144 | + * The pf_num should be set to PF_NUM_IGNORE when the caller knows | |
| 4145 | + * that only it's NIC descriptor is present in the descriptor list. | |
| 4146 | + */ | |
| 3584 | 4147 | static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count, |
| 3585 | − int desc_type) | |
| 4148 | + bool get_vft, u8 pf_num) | |
| 3586 | 4149 | { |
| 3587 | 4150 | struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; |
| 3588 | 4151 | struct be_nic_res_desc *nic; |
| @@ -3592,40 +4155,42 @@ static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count, · 3 unmodified lines | ||
| 3592 | 4155 | if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || |
| 3593 | 4156 | hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) { |
| 3594 | 4157 | nic = (struct be_nic_res_desc *)hdr; |
| 3595 | − if (desc_type == FUNC_DESC || | |
| 3596 | − (desc_type == VFT_DESC && | |
| 3597 | − nic->flags & (1 << VFT_SHIFT))) | |
| 4158 | + | |
| 4159 | + if ((pf_num == PF_NUM_IGNORE || | |
| 4160 | + nic->pf_num == pf_num) && | |
| 4161 | + (!get_vft || nic->flags & BIT(VFT_SHIFT))) | |
| 3598 | 4162 | return nic; |
| 3599 | 4163 | } |
| 3600 | − | |
| 3601 | 4164 | hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0; |
| 3602 | 4165 | hdr = (void *)hdr + hdr->desc_len; |
| 3603 | 4166 | } |
| 3604 | 4167 | return NULL; |
| 3605 | 4168 | } |
| 3606 | 4169 | |
| 3607 | −static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count) | |
| 4170 | +static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count, | |
| 4171 | + u8 pf_num) | |
| 3608 | 4172 | { |
| 3609 | − return be_get_nic_desc(buf, desc_count, VFT_DESC); | |
| 4173 | + return be_get_nic_desc(buf, desc_count, true, pf_num); | |
| 3610 | 4174 | } |
| 3611 | 4175 | |
| 3612 | −static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count) | |
| 4176 | +static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count, | |
| 4177 | + u8 pf_num) | |
| 3613 | 4178 | { |
| 3614 | − return be_get_nic_desc(buf, desc_count, FUNC_DESC); | |
| 4179 | + return be_get_nic_desc(buf, desc_count, false, pf_num); | |
| 3615 | 4180 | } |
| 3616 | 4181 | |
| 3617 | −static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf, | |
| 3618 | − u32 desc_count) | |
| 4182 | +static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count, | |
| 4183 | + u8 pf_num) | |
| 3619 | 4184 | { |
| 3620 | 4185 | struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf; |
| 3621 | 4186 | struct be_pcie_res_desc *pcie; |
| 3622 | 4187 | int i; |
| 3623 | 4188 | |
| 3624 | 4189 | for (i = 0; i < desc_count; i++) { |
| 3625 | − if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 || | |
| 3626 | − hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) { | |
| 3627 | − pcie = (struct be_pcie_res_desc *)hdr; | |
| 3628 | − if (pcie->pf_num == devfn) | |
| 4190 | + if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 || | |
| 4191 | + hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) { | |
| 4192 | + pcie = (struct be_pcie_res_desc *)hdr; | |
| 4193 | + if (pcie->pf_num == pf_num) | |
| 3629 | 4194 | return pcie; |
| 3630 | 4195 | } |
| 3631 | 4196 | |
| @@ -3710,13 +4275,23 @@ int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res) · 78 unmodified lines | ||
| 3710 | 4275 | u32 desc_count = le32_to_cpu(resp->desc_count); |
| 3711 | 4276 | struct be_nic_res_desc *desc; |
| 3712 | 4277 | |
| 3713 | − desc = be_get_func_nic_desc(resp->func_param, desc_count); | |
| 4278 | + /* GET_FUNC_CONFIG returns resource descriptors of the | |
| 4279 | + * current function only. So, pf_num should be set to | |
| 4280 | + * PF_NUM_IGNORE. | |
| 4281 | + */ | |
| 4282 | + desc = be_get_func_nic_desc(resp->func_param, desc_count, | |
| 4283 | + PF_NUM_IGNORE); | |
| 3714 | 4284 | if (!desc) { |
| 3715 | 4285 | status = -EINVAL; |
| 3716 | 4286 | goto err; |
| 3717 | 4287 | } |
| 3718 | − adapter->pf_number = desc->pf_num; | |
| 3719 | − be_copy_nic_desc(res, desc); | |
| 4288 | + | |
| 4289 | + /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */ | |
| 4290 | + adapter->pf_num = desc->pf_num; | |
| 4291 | + adapter->vf_num = desc->vf_num; | |
| 4292 | + | |
| 4293 | + if (res) | |
| 4294 | + be_copy_nic_desc(res, desc); | |
| 3720 | 4295 | } |
| 3721 | 4296 | err: |
| 3722 | 4297 | mutex_unlock(&adapter->mbox_lock); |
| @@ -3726,10 +4301,7 @@ err: · 3 unmodified lines | ||
| 3726 | 4301 | return status; |
| 3727 | 4302 | } |
| 3728 | 4303 | |
| 3729 | −/* Will use MBOX only if MCCQ has not been created | |
| 3730 | − * non-zero domain => a PF is querying this on behalf of a VF | |
| 3731 | − * zero domain => a PF or a VF is querying this for itself | |
| 3732 | − */ | |
| 4304 | +/* Will use MBOX only if MCCQ has not been created */ | |
| 3733 | 4305 | int be_cmd_get_profile_config(struct be_adapter *adapter, |
| 3734 | 4306 | struct be_resources *res, u8 query, u8 domain) |
| 3735 | 4307 | { |
| @@ -3759,12 +4331,7 @@ int be_cmd_get_profile_config(struct be_adapter *adapter, · 23 unmodified lines | ||
| 3759 | 4331 | if (!lancer_chip(adapter)) |
| 3760 | 4332 | req->hdr.version = 1; |
| 3761 | 4333 | req->type = ACTIVE_PROFILE_TYPE; |
| 3762 | − /* When a function is querying profile information relating to | |
| 3763 | − * itself hdr.pf_number must be set to it's pci_func_num + 1 | |
| 3764 | − */ | |
| 3765 | 4334 | req->hdr.domain = domain; |
| 3766 | − if (domain == 0) | |
| 3767 | − req->hdr.pf_num = adapter->pci_func_num + 1; | |
| 3768 | 4335 | |
| 3769 | 4336 | /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the |
| 3770 | 4337 | * descriptors with all bits set to "1" for the fields which can be |
| @@ -3780,8 +4347,8 @@ int be_cmd_get_profile_config(struct be_adapter *adapter, · 9 unmodified lines | ||
| 3780 | 4347 | resp = cmd.va; |
| 3781 | 4348 | desc_count = le16_to_cpu(resp->desc_count); |
| 3782 | 4349 | |
| 3783 | − pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param, | |
| 3784 | − desc_count); | |
| 4350 | + pcie = be_get_pcie_desc(resp->func_param, desc_count, | |
| 4351 | + adapter->pf_num); | |
| 3785 | 4352 | if (pcie) |
| 3786 | 4353 | res->max_vfs = le16_to_cpu(pcie->num_vfs); |
| 3787 | 4354 | |
| @@ -3789,11 +4356,13 @@ int be_cmd_get_profile_config(struct be_adapter *adapter, · 1 unmodified line | ||
| 3789 | 4356 | if (port) |
| 3790 | 4357 | adapter->mc_type = port->mc_type; |
| 3791 | 4358 | |
| 3792 | − nic = be_get_func_nic_desc(resp->func_param, desc_count); | |
| 4359 | + nic = be_get_func_nic_desc(resp->func_param, desc_count, | |
| 4360 | + adapter->pf_num); | |
| 3793 | 4361 | if (nic) |
| 3794 | 4362 | be_copy_nic_desc(res, nic); |
| 3795 | 4363 | |
| 3796 | − vf_res = be_get_vft_desc(resp->func_param, desc_count); | |
| 4364 | + vf_res = be_get_vft_desc(resp->func_param, desc_count, | |
| 4365 | + adapter->pf_num); | |
| 3797 | 4366 | if (vf_res) |
| 3798 | 4367 | res->vf_if_cap_flags = vf_res->cap_flags; |
| 3799 | 4368 | err: |
| @@ -3883,7 +4452,7 @@ int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed, · 83 unmodified lines | ||
| 3883 | 4452 | return be_cmd_set_qos(adapter, max_rate / 10, domain); |
| 3884 | 4453 | |
| 3885 | 4454 | be_reset_nic_desc(&nic_desc); |
| 3886 | − nic_desc.pf_num = adapter->pf_number; | |
| 4455 | + nic_desc.pf_num = adapter->pf_num; | |
| 3887 | 4456 | nic_desc.vf_num = domain; |
| 3888 | 4457 | nic_desc.bw_min = 0; |
| 3889 | 4458 | if (lancer_chip(adapter)) { |
| @@ -4260,16 +4829,13 @@ err: · 370 unmodified lines | ||
| 4260 | 4829 | return status; |
| 4261 | 4830 | } |
| 4262 | 4831 | |
| 4263 | −int be_cmd_set_logical_link_config(struct be_adapter *adapter, | |
| 4264 | − int link_state, u8 domain) | |
| 4832 | +int __be_cmd_set_logical_link_config(struct be_adapter *adapter, | |
| 4833 | + int link_state, int version, u8 domain) | |
| 4265 | 4834 | { |
| 4266 | 4835 | struct be_mcc_wrb *wrb; |
| 4267 | 4836 | struct be_cmd_req_set_ll_link *req; |
| 4268 | 4837 | int status; |
| 4269 | 4838 | |
| 4270 | − if (BEx_chip(adapter) || lancer_chip(adapter)) | |
| 4271 | − return -EOPNOTSUPP; | |
| 4272 | − | |
| 4273 | 4839 | spin_lock_bh(&adapter->mcc_lock); |
| 4274 | 4840 | |
| 4275 | 4841 | wrb = wrb_from_mccq(adapter); |
| @@ -4284,14 +4850,15 @@ int be_cmd_set_logical_link_config(struct be_adapter *adapter, · 8 unmodified lines | ||
| 4284 | 4850 | OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG, |
| 4285 | 4851 | sizeof(*req), wrb, NULL); |
| 4286 | 4852 | |
| 4287 | − req->hdr.version = 1; | |
| 4853 | + req->hdr.version = version; | |
| 4288 | 4854 | req->hdr.domain = domain; |
| 4289 | 4855 | |
| 4290 | − if (link_state == IFLA_VF_LINK_STATE_ENABLE) | |
| 4291 | − req->link_config |= 1; | |
| 4856 | + if (link_state == IFLA_VF_LINK_STATE_ENABLE || | |
| 4857 | + link_state == IFLA_VF_LINK_STATE_AUTO) | |
| 4858 | + req->link_config |= PLINK_ENABLE; | |
| 4292 | 4859 | |
| 4293 | 4860 | if (link_state == IFLA_VF_LINK_STATE_AUTO) |
| 4294 | − req->link_config |= 1 << PLINK_TRACK_SHIFT; | |
| 4861 | + req->link_config |= PLINK_TRACK; | |
| 4295 | 4862 | |
| 4296 | 4863 | status = be_mcc_notify_wait(adapter); |
| 4297 | 4864 | err: |
| @@ -4299,6 +4866,25 @@ err: · 1 unmodified line | ||
| 4299 | 4866 | return status; |
| 4300 | 4867 | } |
| 4301 | 4868 | |
| 4869 | +int be_cmd_set_logical_link_config(struct be_adapter *adapter, | |
| 4870 | + int link_state, u8 domain) | |
| 4871 | +{ | |
| 4872 | + int status; | |
| 4873 | + | |
| 4874 | + if (BEx_chip(adapter)) | |
| 4875 | + return -EOPNOTSUPP; | |
| 4876 | + | |
| 4877 | + status = __be_cmd_set_logical_link_config(adapter, link_state, | |
| 4878 | + 2, domain); | |
| 4879 | + | |
| 4880 | + /* Version 2 of the command will not be recognized by older FW. | |
| 4881 | + * On such a failure issue version 1 of the command. | |
| 4882 | + */ | |
| 4883 | + if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST) | |
| 4884 | + status = __be_cmd_set_logical_link_config(adapter, link_state, | |
| 4885 | + 1, domain); | |
| 4886 | + return status; | |
| 4887 | +} | |
| 4302 | 4888 | int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, |
| 4303 | 4889 | int wrb_payload_size, u16 *cmd_status, u16 *ext_status) |
| 4304 | 4890 | { |
| @@ -66,7 +66,9 @@ enum mcc_addl_status { · 65 unmodified lines | ||
| 66 | 66 | MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, |
| 67 | 67 | MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, |
| 68 | 68 | MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a, |
| 69 | − MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab | |
| 69 | + MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab, | |
| 70 | + MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56, | |
| 71 | + MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57 | |
| 70 | 72 | }; |
| 71 | 73 | |
| 72 | 74 | #define CQE_BASE_STATUS_MASK 0xFFFF |
| @@ -289,9 +291,7 @@ struct be_cmd_req_hdr { · 216 unmodified lines | ||
| 289 | 291 | u32 timeout; /* dword 1 */ |
| 290 | 292 | u32 request_length; /* dword 2 */ |
| 291 | 293 | u8 version; /* dword 3 */ |
| 292 | − u8 rsvd1; /* dword 3 */ | |
| 293 | − u8 pf_num; /* dword 3 */ | |
| 294 | − u8 rsvd2; /* dword 3 */ | |
| 294 | + u8 rsvd[3]; /* dword 3 */ | |
| 295 | 295 | }; |
| 296 | 296 | |
| 297 | 297 | #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ |
| @@ -1207,68 +1207,85 @@ struct be_cmd_resp_get_beacon_state { · 909 unmodified lines | ||
| 1207 | 1207 | /* Flashrom related descriptors */ |
| 1208 | 1208 | #define MAX_FLASH_COMP 32 |
| 1209 | 1209 | |
| 1210 | −#define OPTYPE_ISCSI_ACTIVE 0 | |
| 1211 | −#define OPTYPE_REDBOOT 1 | |
| 1212 | −#define OPTYPE_BIOS 2 | |
| 1213 | −#define OPTYPE_PXE_BIOS 3 | |
| 1214 | −#define OPTYPE_OFFSET_SPECIFIED 7 | |
| 1215 | −#define OPTYPE_FCOE_BIOS 8 | |
| 1216 | −#define OPTYPE_ISCSI_BACKUP 9 | |
| 1217 | −#define OPTYPE_FCOE_FW_ACTIVE 10 | |
| 1218 | −#define OPTYPE_FCOE_FW_BACKUP 11 | |
| 1219 | −#define OPTYPE_NCSI_FW 13 | |
| 1220 | −#define OPTYPE_REDBOOT_DIR 18 | |
| 1221 | −#define OPTYPE_REDBOOT_CONFIG 19 | |
| 1222 | −#define OPTYPE_SH_PHY_FW 21 | |
| 1223 | −#define OPTYPE_FLASHISM_JUMPVECTOR 22 | |
| 1224 | −#define OPTYPE_UFI_DIR 23 | |
| 1225 | −#define OPTYPE_PHY_FW 99 | |
| 1226 | − | |
| 1227 | −#define FLASH_BIOS_IMAGE_MAX_SIZE_g2 262144 /* Max OPTION ROM image sz */ | |
| 1228 | −#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 262144 /* Max Redboot image sz */ | |
| 1229 | −#define FLASH_IMAGE_MAX_SIZE_g2 1310720 /* Max firmware image size */ | |
| 1230 | − | |
| 1231 | −#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 262144 | |
| 1232 | −#define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144 | |
| 1233 | −#define FLASH_BIOS_IMAGE_MAX_SIZE_g3 524288 /* Max OPTION ROM image sz */ | |
| 1234 | −#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 1048576 /* Max Redboot image sz */ | |
| 1235 | −#define FLASH_IMAGE_MAX_SIZE_g3 2097152 /* Max firmware image size */ | |
| 1236 | − | |
| 1237 | −/* Offsets for components on Flash. */ | |
| 1238 | −#define FLASH_REDBOOT_START_g2 0 | |
| 1239 | −#define FLASH_FCoE_BIOS_START_g2 524288 | |
| 1240 | −#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 1048576 | |
| 1241 | −#define FLASH_iSCSI_BACKUP_IMAGE_START_g2 2359296 | |
| 1242 | −#define FLASH_FCoE_PRIMARY_IMAGE_START_g2 3670016 | |
| 1243 | −#define FLASH_FCoE_BACKUP_IMAGE_START_g2 4980736 | |
| 1244 | −#define FLASH_iSCSI_BIOS_START_g2 7340032 | |
| 1245 | −#define FLASH_PXE_BIOS_START_g2 7864320 | |
| 1246 | − | |
| 1247 | −#define FLASH_REDBOOT_START_g3 262144 | |
| 1248 | −#define FLASH_PHY_FW_START_g3 1310720 | |
| 1249 | −#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 2097152 | |
| 1250 | −#define FLASH_iSCSI_BACKUP_IMAGE_START_g3 4194304 | |
| 1251 | −#define FLASH_FCoE_PRIMARY_IMAGE_START_g3 6291456 | |
| 1252 | −#define FLASH_FCoE_BACKUP_IMAGE_START_g3 8388608 | |
| 1253 | −#define FLASH_iSCSI_BIOS_START_g3 12582912 | |
| 1254 | −#define FLASH_PXE_BIOS_START_g3 13107200 | |
| 1255 | −#define FLASH_FCoE_BIOS_START_g3 13631488 | |
| 1256 | −#define FLASH_NCSI_START_g3 15990784 | |
| 1257 | − | |
| 1258 | −#define IMAGE_NCSI 16 | |
| 1259 | −#define IMAGE_OPTION_ROM_PXE 32 | |
| 1260 | −#define IMAGE_OPTION_ROM_FCoE 33 | |
| 1261 | −#define IMAGE_OPTION_ROM_ISCSI 34 | |
| 1262 | −#define IMAGE_FLASHISM_JUMPVECTOR 48 | |
| 1263 | −#define IMAGE_FIRMWARE_iSCSI 160 | |
| 1264 | −#define IMAGE_FIRMWARE_FCoE 162 | |
| 1265 | −#define IMAGE_FIRMWARE_BACKUP_iSCSI 176 | |
| 1266 | −#define IMAGE_FIRMWARE_BACKUP_FCoE 178 | |
| 1267 | −#define IMAGE_FIRMWARE_PHY 192 | |
| 1268 | −#define IMAGE_REDBOOT_DIR 208 | |
| 1269 | −#define IMAGE_REDBOOT_CONFIG 209 | |
| 1270 | −#define IMAGE_UFI_DIR 210 | |
| 1271 | −#define IMAGE_BOOT_CODE 224 | |
| 1210 | +/* Optypes of each component in the UFI */ | |
| 1211 | +enum { | |
| 1212 | + OPTYPE_ISCSI_ACTIVE = 0, | |
| 1213 | + OPTYPE_REDBOOT = 1, | |
| 1214 | + OPTYPE_BIOS = 2, | |
| 1215 | + OPTYPE_PXE_BIOS = 3, | |
| 1216 | + OPTYPE_OFFSET_SPECIFIED = 7, | |
| 1217 | + OPTYPE_FCOE_BIOS = 8, | |
| 1218 | + OPTYPE_ISCSI_BACKUP = 9, | |
| 1219 | + OPTYPE_FCOE_FW_ACTIVE = 10, | |
| 1220 | + OPTYPE_FCOE_FW_BACKUP = 11, | |
| 1221 | + OPTYPE_NCSI_FW = 13, | |
| 1222 | + OPTYPE_REDBOOT_DIR = 18, | |
| 1223 | + OPTYPE_REDBOOT_CONFIG = 19, | |
| 1224 | + OPTYPE_SH_PHY_FW = 21, | |
| 1225 | + OPTYPE_FLASHISM_JUMPVECTOR = 22, | |
| 1226 | + OPTYPE_UFI_DIR = 23, | |
| 1227 | + OPTYPE_PHY_FW = 99 | |
| 1228 | +}; | |
| 1229 | + | |
| 1230 | +/* Maximum sizes of components in BE2 FW UFI */ | |
| 1231 | +enum { | |
| 1232 | + BE2_BIOS_COMP_MAX_SIZE = 0x40000, | |
| 1233 | + BE2_REDBOOT_COMP_MAX_SIZE = 0x40000, | |
| 1234 | + BE2_COMP_MAX_SIZE = 0x140000 | |
| 1235 | +}; | |
| 1236 | + | |
| 1237 | +/* Maximum sizes of components in BE3 FW UFI */ | |
| 1238 | +enum { | |
| 1239 | + BE3_NCSI_COMP_MAX_SIZE = 0x40000, | |
| 1240 | + BE3_PHY_FW_COMP_MAX_SIZE = 0x40000, | |
| 1241 | + BE3_BIOS_COMP_MAX_SIZE = 0x80000, | |
| 1242 | + BE3_REDBOOT_COMP_MAX_SIZE = 0x100000, | |
| 1243 | + BE3_COMP_MAX_SIZE = 0x200000 | |
| 1244 | +}; | |
| 1245 | + | |
| 1246 | +/* Offsets for components in BE2 FW UFI */ | |
| 1247 | +enum { | |
| 1248 | + BE2_REDBOOT_START = 0x8000, | |
| 1249 | + BE2_FCOE_BIOS_START = 0x80000, | |
| 1250 | + BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000, | |
| 1251 | + BE2_ISCSI_BACKUP_IMAGE_START = 0x240000, | |
| 1252 | + BE2_FCOE_PRIMARY_IMAGE_START = 0x380000, | |
| 1253 | + BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000, | |
| 1254 | + BE2_ISCSI_BIOS_START = 0x700000, | |
| 1255 | + BE2_PXE_BIOS_START = 0x780000 | |
| 1256 | +}; | |
| 1257 | + | |
| 1258 | +/* Offsets for components in BE3 FW UFI */ | |
| 1259 | +enum { | |
| 1260 | + BE3_REDBOOT_START = 0x40000, | |
| 1261 | + BE3_PHY_FW_START = 0x140000, | |
| 1262 | + BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000, | |
| 1263 | + BE3_ISCSI_BACKUP_IMAGE_START = 0x400000, | |
| 1264 | + BE3_FCOE_PRIMARY_IMAGE_START = 0x600000, | |
| 1265 | + BE3_FCOE_BACKUP_IMAGE_START = 0x800000, | |
| 1266 | + BE3_ISCSI_BIOS_START = 0xc00000, | |
| 1267 | + BE3_PXE_BIOS_START = 0xc80000, | |
| 1268 | + BE3_FCOE_BIOS_START = 0xd00000, | |
| 1269 | + BE3_NCSI_START = 0xf40000 | |
| 1270 | +}; | |
| 1271 | + | |
| 1272 | +/* Component entry types */ | |
| 1273 | +enum { | |
| 1274 | + IMAGE_NCSI = 0x10, | |
| 1275 | + IMAGE_OPTION_ROM_PXE = 0x20, | |
| 1276 | + IMAGE_OPTION_ROM_FCOE = 0x21, | |
| 1277 | + IMAGE_OPTION_ROM_ISCSI = 0x22, | |
| 1278 | + IMAGE_FLASHISM_JUMPVECTOR = 0x30, | |
| 1279 | + IMAGE_FIRMWARE_ISCSI = 0xa0, | |
| 1280 | + IMAGE_FIRMWARE_FCOE = 0xa2, | |
| 1281 | + IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0, | |
| 1282 | + IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2, | |
| 1283 | + IMAGE_FIRMWARE_PHY = 0xc0, | |
| 1284 | + IMAGE_REDBOOT_DIR = 0xd0, | |
| 1285 | + IMAGE_REDBOOT_CONFIG = 0xd1, | |
| 1286 | + IMAGE_UFI_DIR = 0xd2, | |
| 1287 | + IMAGE_BOOT_CODE = 0xe2 | |
| 1288 | +}; | |
| 1272 | 1289 | |
| 1273 | 1290 | struct controller_id { |
| 1274 | 1291 | u32 vendor; |
| @@ -1394,6 +1411,9 @@ struct be_cmd_read_flash_crc { · 119 unmodified lines | ||
| 1394 | 1411 | } __packed; |
| 1395 | 1412 | |
| 1396 | 1413 | /**************** Lancer Firmware Flash ************/ |
| 1414 | +#define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024) | |
| 1415 | +#define LANCER_FW_DOWNLOAD_LOCATION "/prg" | |
| 1416 | + | |
| 1397 | 1417 | struct amap_lancer_write_obj_context { |
| 1398 | 1418 | u8 write_length[24]; |
| 1399 | 1419 | u8 reserved1[7]; |
| @@ -1654,11 +1674,7 @@ struct mgmt_hba_attribs { · 254 unmodified lines | ||
| 1654 | 1674 | |
| 1655 | 1675 | struct mgmt_controller_attrib { |
| 1656 | 1676 | struct mgmt_hba_attribs hba_attribs; |
| 1657 | − u32 rsvd0[2]; | |
| 1658 | − u16 rsvd1; | |
| 1659 | − u8 pci_func_num; | |
| 1660 | − u8 rsvd2; | |
| 1661 | − u32 rsvd3[7]; | |
| 1677 | + u32 rsvd0[10]; | |
| 1662 | 1678 | } __packed; |
| 1663 | 1679 | |
| 1664 | 1680 | struct be_cmd_req_cntl_attribs { |
| @@ -2083,6 +2099,7 @@ struct be_port_res_desc { · 418 unmodified lines | ||
| 2083 | 2099 | #define NV_TYPE_VXLAN 3 |
| 2084 | 2100 | #define SOCVID_SHIFT 2 /* Strip outer vlan */ |
| 2085 | 2101 | #define RCVID_SHIFT 4 /* Report vlan */ |
| 2102 | +#define PF_NUM_IGNORE 255 | |
| 2086 | 2103 | u8 nv_flags; |
| 2087 | 2104 | u8 rsvd2; |
| 2088 | 2105 | __le16 nv_port; /* vxlan/gre port */ |
| @@ -2246,7 +2263,8 @@ struct be_cmd_resp_get_iface_list { · 157 unmodified lines | ||
| 2246 | 2263 | }; |
| 2247 | 2264 | |
| 2248 | 2265 | /*************** Set logical link ********************/ |
| 2249 | −#define PLINK_TRACK_SHIFT 8 | |
| 2266 | +#define PLINK_ENABLE BIT(0) | |
| 2267 | +#define PLINK_TRACK BIT(8) | |
| 2250 | 2268 | struct be_cmd_req_set_ll_link { |
| 2251 | 2269 | struct be_cmd_req_hdr hdr; |
| 2252 | 2270 | u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ |
| @@ -2321,19 +2339,11 @@ int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, · 68 unmodified lines | ||
| 2321 | 2339 | u8 page_num, u8 *data); |
| 2322 | 2340 | int be_cmd_query_cable_type(struct be_adapter *adapter); |
| 2323 | 2341 | int be_cmd_query_sfp_info(struct be_adapter *adapter); |
| 2324 | −int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, | |
| 2325 | − u32 flash_oper, u32 flash_opcode, u32 img_offset, | |
| 2326 | − u32 buf_size); | |
| 2327 | −int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, | |
| 2328 | − u32 data_size, u32 data_offset, | |
| 2329 | − const char *obj_name, u32 *data_written, | |
| 2330 | − u8 *change_status, u8 *addn_status); | |
| 2331 | 2342 | int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, |
| 2332 | 2343 | u32 data_size, u32 data_offset, const char *obj_name, |
| 2333 | 2344 | u32 *data_read, u32 *eof, u8 *addn_status); |
| 2334 | −int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name); | |
| 2335 | −int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, | |
| 2336 | − u16 img_optype, u32 img_offset, u32 crc_offset); | |
| 2345 | +int lancer_fw_download(struct be_adapter *adapter, const struct firmware *fw); | |
| 2346 | +int be_fw_download(struct be_adapter *adapter, const struct firmware *fw); | |
| 2337 | 2347 | int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, |
| 2338 | 2348 | struct be_dma_mem *nonemb_cmd); |
| 2339 | 2349 | int be_cmd_fw_init(struct be_adapter *adapter); |
| @@ -2355,9 +2365,9 @@ int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, · 15 unmodified lines | ||
| 2355 | 2365 | void be_detect_error(struct be_adapter *adapter); |
| 2356 | 2366 | int be_cmd_get_die_temperature(struct be_adapter *adapter); |
| 2357 | 2367 | int be_cmd_get_cntl_attributes(struct be_adapter *adapter); |
| 2368 | +int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size); | |
| 2369 | +int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf); | |
| 2358 | 2370 | int be_cmd_req_native_mode(struct be_adapter *adapter); |
| 2359 | −int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); | |
| 2360 | −int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); | |
| 2361 | 2371 | int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, |
| 2362 | 2372 | u32 domain); |
| 2363 | 2373 | int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, |
| @@ -241,17 +241,28 @@ static u32 lancer_cmd_get_file_len(struct be_adapter *adapter, u8 *file_name) · 240 unmodified lines | ||
| 241 | 241 | u32 data_read = 0, eof; |
| 242 | 242 | u8 addn_status; |
| 243 | 243 | struct be_dma_mem data_len_cmd; |
| 244 | − int status; | |
| 245 | 244 | |
| 246 | 245 | memset(&data_len_cmd, 0, sizeof(data_len_cmd)); |
| 247 | 246 | /* data_offset and data_size should be 0 to get reg len */ |
| 248 | − status = lancer_cmd_read_object(adapter, &data_len_cmd, 0, 0, | |
| 249 | − file_name, &data_read, &eof, | |
| 250 | − &addn_status); | |
| 247 | + lancer_cmd_read_object(adapter, &data_len_cmd, 0, 0, file_name, | |
| 248 | + &data_read, &eof, &addn_status); | |
| 251 | 249 | |
| 252 | 250 | return data_read; |
| 253 | 251 | } |
| 254 | 252 | |
| 253 | +static int be_get_dump_len(struct be_adapter *adapter) | |
| 254 | +{ | |
| 255 | + u32 dump_size = 0; | |
| 256 | + | |
| 257 | + if (lancer_chip(adapter)) | |
| 258 | + dump_size = lancer_cmd_get_file_len(adapter, | |
| 259 | + LANCER_FW_DUMP_FILE); | |
| 260 | + else | |
| 261 | + dump_size = adapter->fat_dump_len; | |
| 262 | + | |
| 263 | + return dump_size; | |
| 264 | +} | |
| 265 | + | |
| 255 | 266 | static int lancer_cmd_read_file(struct be_adapter *adapter, u8 *file_name, |
| 256 | 267 | u32 buf_len, void *buf) |
| 257 | 268 | { |
| @@ -293,37 +304,18 @@ static int lancer_cmd_read_file(struct be_adapter *adapter, u8 *file_name, · 35 unmodified lines | ||
| 293 | 304 | return status; |
| 294 | 305 | } |
| 295 | 306 | |
| 296 | −static int be_get_reg_len(struct net_device *netdev) | |
| 307 | +static int be_read_dump_data(struct be_adapter *adapter, u32 dump_len, | |
| 308 | + void *buf) | |
| 297 | 309 | { |
| 298 | − struct be_adapter *adapter = netdev_priv(netdev); | |
| 299 | − u32 log_size = 0; | |
| 300 | − | |
| 301 | − if (!check_privilege(adapter, MAX_PRIVILEGES)) | |
| 302 | − return 0; | |
| 303 | − | |
| 304 | − if (be_physfn(adapter)) { | |
| 305 | − if (lancer_chip(adapter)) | |
| 306 | − log_size = lancer_cmd_get_file_len(adapter, | |
| 307 | − LANCER_FW_DUMP_FILE); | |
| 308 | − else | |
| 309 | − be_cmd_get_reg_len(adapter, &log_size); | |
| 310 | − } | |
| 311 | − return log_size; | |
| 312 | −} | |
| 310 | + int status = 0; | |
| 313 | 311 | |
| 314 | −static void | |
| 315 | −be_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *buf) | |
| 316 | −{ | |
| 317 | − struct be_adapter *adapter = netdev_priv(netdev); | |
| 312 | + if (lancer_chip(adapter)) | |
| 313 | + status = lancer_cmd_read_file(adapter, LANCER_FW_DUMP_FILE, | |
| 314 | + dump_len, buf); | |
| 315 | + else | |
| 316 | + status = be_cmd_get_fat_dump(adapter, dump_len, buf); | |
| 318 | 317 | |
| 319 | − if (be_physfn(adapter)) { | |
| 320 | − memset(buf, 0, regs->len); | |
| 321 | − if (lancer_chip(adapter)) | |
| 322 | − lancer_cmd_read_file(adapter, LANCER_FW_DUMP_FILE, | |
| 323 | − regs->len, buf); | |
| 324 | − else | |
| 325 | − be_cmd_get_regs(adapter, regs->len, buf); | |
| 326 | − } | |
| 318 | + return status; | |
| 327 | 319 | } |
| 328 | 320 | |
| 329 | 321 | static int be_get_coalesce(struct net_device *netdev, |
| @@ -916,6 +908,34 @@ static int be_do_flash(struct net_device *netdev, struct ethtool_flash *efl) · 586 unmodified lines | ||
| 916 | 908 | return be_load_fw(adapter, efl->data); |
| 917 | 909 | } |
| 918 | 910 | |
| 911 | +static int | |
| 912 | +be_get_dump_flag(struct net_device *netdev, struct ethtool_dump *dump) | |
| 913 | +{ | |
| 914 | + struct be_adapter *adapter = netdev_priv(netdev); | |
| 915 | + | |
| 916 | + if (!check_privilege(adapter, MAX_PRIVILEGES)) | |
| 917 | + return -EOPNOTSUPP; | |
| 918 | + | |
| 919 | + dump->len = be_get_dump_len(adapter); | |
| 920 | + dump->version = 1; | |
| 921 | + dump->flag = 0x1; /* FW dump is enabled */ | |
| 922 | + return 0; | |
| 923 | +} | |
| 924 | + | |
| 925 | +static int | |
| 926 | +be_get_dump_data(struct net_device *netdev, struct ethtool_dump *dump, | |
| 927 | + void *buf) | |
| 928 | +{ | |
| 929 | + struct be_adapter *adapter = netdev_priv(netdev); | |
| 930 | + int status; | |
| 931 | + | |
| 932 | + if (!check_privilege(adapter, MAX_PRIVILEGES)) | |
| 933 | + return -EOPNOTSUPP; | |
| 934 | + | |
| 935 | + status = be_read_dump_data(adapter, dump->len, buf); | |
| 936 | + return be_cmd_status(status); | |
| 937 | +} | |
| 938 | + | |
| 919 | 939 | static int be_get_eeprom_len(struct net_device *netdev) |
| 920 | 940 | { |
| 921 | 941 | struct be_adapter *adapter = netdev_priv(netdev); |
| @@ -1313,8 +1333,6 @@ const struct ethtool_ops be_ethtool_ops = { · 391 unmodified lines | ||
| 1313 | 1333 | .set_msglevel = be_set_msg_level, |
| 1314 | 1334 | .get_sset_count = be_get_sset_count, |
| 1315 | 1335 | .get_ethtool_stats = be_get_ethtool_stats, |
| 1316 | − .get_regs_len = be_get_reg_len, | |
| 1317 | − .get_regs = be_get_regs, | |
| 1318 | 1336 | .flash_device = be_do_flash, |
| 1319 | 1337 | .self_test = be_self_test, |
| 1320 | 1338 | .get_rxnfc = be_get_rxnfc, |
| @@ -1323,6 +1341,8 @@ const struct ethtool_ops be_ethtool_ops = { · 2 unmodified lines | ||
| 1323 | 1341 | .get_rxfh_key_size = be_get_rxfh_key_size, |
| 1324 | 1342 | .get_rxfh = be_get_rxfh, |
| 1325 | 1343 | .set_rxfh = be_set_rxfh, |
| 1344 | + .get_dump_flag = be_get_dump_flag, | |
| 1345 | + .get_dump_data = be_get_dump_data, | |
| 1326 | 1346 | .get_channels = be_get_channels, |
| 1327 | 1347 | .set_channels = be_set_channels, |
| 1328 | 1348 | .get_module_info = be_get_module_info, |
| @@ -729,7 +729,7 @@ static inline u16 be_get_tx_vlan_tag(struct be_adapter *adapter, · 728 unmodified lines | ||
| 729 | 729 | /* If vlan priority provided by OS is NOT in available bmap */ |
| 730 | 730 | if (!(adapter->vlan_prio_bmap & (1 << vlan_prio))) |
| 731 | 731 | vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) | |
| 732 | − adapter->recommended_prio; | |
| 732 | + adapter->recommended_prio_bits; | |
| 733 | 733 | |
| 734 | 734 | return vlan_tag; |
| 735 | 735 | } |
| @@ -2184,7 +2184,6 @@ static void be_rx_compl_process_gro(struct be_rx_obj *rxo, · 1448 unmodified lines | ||
| 2184 | 2184 | skb_set_hash(skb, rxcp->rss_hash, PKT_HASH_TYPE_L3); |
| 2185 | 2185 | |
| 2186 | 2186 | skb->csum_level = rxcp->tunneled; |
| 2187 | − skb_mark_napi_id(skb, napi); | |
| 2188 | 2187 | |
| 2189 | 2188 | if (rxcp->vlanf) |
| 2190 | 2189 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rxcp->vlan_tag); |
| @@ -2631,7 +2630,6 @@ static int be_evt_queues_create(struct be_adapter *adapter) · 440 unmodified lines | ||
| 2631 | 2630 | eqo->affinity_mask); |
| 2632 | 2631 | netif_napi_add(adapter->netdev, &eqo->napi, be_poll, |
| 2633 | 2632 | BE_NAPI_WEIGHT); |
| 2634 | − napi_hash_add(&eqo->napi); | |
| 2635 | 2633 | } |
| 2636 | 2634 | return 0; |
| 2637 | 2635 | } |
| @@ -4204,10 +4202,17 @@ static int be_get_config(struct be_adapter *adapter) · 1566 unmodified lines | ||
| 4204 | 4202 | int status, level; |
| 4205 | 4203 | u16 profile_id; |
| 4206 | 4204 | |
| 4205 | + status = be_cmd_get_cntl_attributes(adapter); | |
| 4206 | + if (status) | |
| 4207 | + return status; | |
| 4208 | + | |
| 4207 | 4209 | status = be_cmd_query_fw_cfg(adapter); |
| 4208 | 4210 | if (status) |
| 4209 | 4211 | return status; |
| 4210 | 4212 | |
| 4213 | + if (!lancer_chip(adapter) && be_physfn(adapter)) | |
| 4214 | + be_cmd_get_fat_dump_len(adapter, &adapter->fat_dump_len); | |
| 4215 | + | |
| 4211 | 4216 | if (BEx_chip(adapter)) { |
| 4212 | 4217 | level = be_cmd_get_fw_log_level(adapter); |
| 4213 | 4218 | adapter->msg_enable = |
| @@ -4402,10 +4407,14 @@ static int be_setup(struct be_adapter *adapter) · 188 unmodified lines | ||
| 4402 | 4407 | if (!lancer_chip(adapter)) |
| 4403 | 4408 | be_cmd_req_native_mode(adapter); |
| 4404 | 4409 | |
| 4405 | − /* Need to invoke this cmd first to get the PCI Function Number */ | |
| 4406 | − status = be_cmd_get_cntl_attributes(adapter); | |
| 4407 | − if (status) | |
| 4408 | − return status; | |
| 4410 | + /* invoke this cmd first to get pf_num and vf_num which are needed | |
| 4411 | + * for issuing profile related cmds | |
| 4412 | + */ | |
| 4413 | + if (!BEx_chip(adapter)) { | |
| 4414 | + status = be_cmd_get_func_config(adapter, NULL); | |
| 4415 | + if (status) | |
| 4416 | + return status; | |
| 4417 | + } | |
| 4409 | 4418 | |
| 4410 | 4419 | if (!BE2_chip(adapter) && be_physfn(adapter)) |
| 4411 | 4420 | be_alloc_sriov_res(adapter); |
| @@ -4490,570 +4499,6 @@ static void be_netpoll(struct net_device *netdev) · 78 unmodified lines | ||
| 4490 | 4499 | } |
| 4491 | 4500 | #endif |
| 4492 | 4501 | |
| 4493 | −static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "}; | |
| 4494 | − | |
| 4495 | −static bool phy_flashing_required(struct be_adapter *adapter) | |
| 4496 | −{ | |
| 4497 | − return (adapter->phy.phy_type == PHY_TYPE_TN_8022 && | |
| 4498 | − adapter->phy.interface_type == PHY_TYPE_BASET_10GB); | |
| 4499 | −} | |
| 4500 | − | |
| 4501 | −static bool is_comp_in_ufi(struct be_adapter *adapter, | |
| 4502 | − struct flash_section_info *fsec, int type) | |
| 4503 | −{ | |
| 4504 | − int i = 0, img_type = 0; | |
| 4505 | − struct flash_section_info_g2 *fsec_g2 = NULL; | |
| 4506 | − | |
| 4507 | − if (BE2_chip(adapter)) | |
| 4508 | − fsec_g2 = (struct flash_section_info_g2 *)fsec; | |
| 4509 | − | |
| 4510 | − for (i = 0; i < MAX_FLASH_COMP; i++) { | |
| 4511 | − if (fsec_g2) | |
| 4512 | − img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type); | |
| 4513 | − else | |
| 4514 | − img_type = le32_to_cpu(fsec->fsec_entry[i].type); | |
| 4515 | − | |
| 4516 | − if (img_type == type) | |
| 4517 | − return true; | |
| 4518 | − } | |
| 4519 | − return false; | |
| 4520 | − | |
| 4521 | −} | |
| 4522 | − | |
| 4523 | −static struct flash_section_info *get_fsec_info(struct be_adapter *adapter, | |
| 4524 | − int header_size, | |
| 4525 | − const struct firmware *fw) | |
| 4526 | −{ | |
| 4527 | − struct flash_section_info *fsec = NULL; | |
| 4528 | − const u8 *p = fw->data; | |
| 4529 | − | |
| 4530 | − p += header_size; | |
| 4531 | − while (p < (fw->data + fw->size)) { | |
| 4532 | − fsec = (struct flash_section_info *)p; | |
| 4533 | − if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie))) | |
| 4534 | − return fsec; | |
| 4535 | − p += 32; | |
| 4536 | − } | |
| 4537 | − return NULL; | |
| 4538 | −} | |
| 4539 | − | |
| 4540 | −static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p, | |
| 4541 | − u32 img_offset, u32 img_size, int hdr_size, | |
| 4542 | − u16 img_optype, bool *crc_match) | |
| 4543 | −{ | |
| 4544 | − u32 crc_offset; | |
| 4545 | − int status; | |
| 4546 | − u8 crc[4]; | |
| 4547 | − | |
| 4548 | − status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset, | |
| 4549 | − img_size - 4); | |
| 4550 | − if (status) | |
| 4551 | − return status; | |
| 4552 | − | |
| 4553 | − crc_offset = hdr_size + img_offset + img_size - 4; | |
| 4554 | − | |
| 4555 | − /* Skip flashing, if crc of flashed region matches */ | |
| 4556 | − if (!memcmp(crc, p + crc_offset, 4)) | |
| 4557 | − *crc_match = true; | |
| 4558 | − else | |
| 4559 | − *crc_match = false; | |
| 4560 | − | |
| 4561 | − return status; | |
| 4562 | −} | |
| 4563 | − | |
| 4564 | −static int be_flash(struct be_adapter *adapter, const u8 *img, | |
| 4565 | − struct be_dma_mem *flash_cmd, int optype, int img_size, | |
| 4566 | − u32 img_offset) | |
| 4567 | −{ | |
| 4568 | − u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0; | |
| 4569 | − struct be_cmd_write_flashrom *req = flash_cmd->va; | |
| 4570 | − int status; | |
| 4571 | − | |
| 4572 | − while (total_bytes) { | |
| 4573 | − num_bytes = min_t(u32, 32*1024, total_bytes); | |
| 4574 | − | |
| 4575 | − total_bytes -= num_bytes; | |
| 4576 | − | |
| 4577 | − if (!total_bytes) { | |
| 4578 | − if (optype == OPTYPE_PHY_FW) | |
| 4579 | − flash_op = FLASHROM_OPER_PHY_FLASH; | |
| 4580 | − else | |
| 4581 | − flash_op = FLASHROM_OPER_FLASH; | |
| 4582 | − } else { | |
| 4583 | − if (optype == OPTYPE_PHY_FW) | |
| 4584 | − flash_op = FLASHROM_OPER_PHY_SAVE; | |
| 4585 | − else | |
| 4586 | − flash_op = FLASHROM_OPER_SAVE; | |
| 4587 | − } | |
| 4588 | − | |
| 4589 | − memcpy(req->data_buf, img, num_bytes); | |
| 4590 | − img += num_bytes; | |
| 4591 | − status = be_cmd_write_flashrom(adapter, flash_cmd, optype, | |
| 4592 | − flash_op, img_offset + | |
| 4593 | − bytes_sent, num_bytes); | |
| 4594 | − if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST && | |
| 4595 | − optype == OPTYPE_PHY_FW) | |
| 4596 | − break; | |
| 4597 | − else if (status) | |
| 4598 | − return status; | |
| 4599 | − | |
| 4600 | − bytes_sent += num_bytes; | |
| 4601 | − } | |
| 4602 | − return 0; | |
| 4603 | −} | |
| 4604 | − | |
| 4605 | −/* For BE2, BE3 and BE3-R */ | |
| 4606 | −static int be_flash_BEx(struct be_adapter *adapter, | |
| 4607 | − const struct firmware *fw, | |
| 4608 | − struct be_dma_mem *flash_cmd, int num_of_images) | |
| 4609 | −{ | |
| 4610 | − int img_hdrs_size = (num_of_images * sizeof(struct image_hdr)); | |
| 4611 | − struct device *dev = &adapter->pdev->dev; | |
| 4612 | − struct flash_section_info *fsec = NULL; | |
| 4613 | − int status, i, filehdr_size, num_comp; | |
| 4614 | − const struct flash_comp *pflashcomp; | |
| 4615 | − bool crc_match; | |
| 4616 | − const u8 *p; | |
| 4617 | − | |
| 4618 | − struct flash_comp gen3_flash_types[] = { | |
| 4619 | − { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, OPTYPE_ISCSI_ACTIVE, | |
| 4620 | − FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_iSCSI}, | |
| 4621 | − { FLASH_REDBOOT_START_g3, OPTYPE_REDBOOT, | |
| 4622 | − FLASH_REDBOOT_IMAGE_MAX_SIZE_g3, IMAGE_BOOT_CODE}, | |
| 4623 | − { FLASH_iSCSI_BIOS_START_g3, OPTYPE_BIOS, | |
| 4624 | − FLASH_BIOS_IMAGE_MAX_SIZE_g3, IMAGE_OPTION_ROM_ISCSI}, | |
| 4625 | − { FLASH_PXE_BIOS_START_g3, OPTYPE_PXE_BIOS, | |
| 4626 | − FLASH_BIOS_IMAGE_MAX_SIZE_g3, IMAGE_OPTION_ROM_PXE}, | |
| 4627 | − { FLASH_FCoE_BIOS_START_g3, OPTYPE_FCOE_BIOS, | |
| 4628 | − FLASH_BIOS_IMAGE_MAX_SIZE_g3, IMAGE_OPTION_ROM_FCoE}, | |
| 4629 | − { FLASH_iSCSI_BACKUP_IMAGE_START_g3, OPTYPE_ISCSI_BACKUP, | |
| 4630 | − FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_BACKUP_iSCSI}, | |
| 4631 | − { FLASH_FCoE_PRIMARY_IMAGE_START_g3, OPTYPE_FCOE_FW_ACTIVE, | |
| 4632 | − FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_FCoE}, | |
| 4633 | − { FLASH_FCoE_BACKUP_IMAGE_START_g3, OPTYPE_FCOE_FW_BACKUP, | |
| 4634 | − FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_BACKUP_FCoE}, | |
| 4635 | − { FLASH_NCSI_START_g3, OPTYPE_NCSI_FW, | |
| 4636 | − FLASH_NCSI_IMAGE_MAX_SIZE_g3, IMAGE_NCSI}, | |
| 4637 | − { FLASH_PHY_FW_START_g3, OPTYPE_PHY_FW, | |
| 4638 | − FLASH_PHY_FW_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_PHY} | |
| 4639 | − }; | |
| 4640 | − | |
| 4641 | − struct flash_comp gen2_flash_types[] = { | |
| 4642 | − { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, OPTYPE_ISCSI_ACTIVE, | |
| 4643 | − FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_iSCSI}, | |
| 4644 | − { FLASH_REDBOOT_START_g2, OPTYPE_REDBOOT, | |
| 4645 | − FLASH_REDBOOT_IMAGE_MAX_SIZE_g2, IMAGE_BOOT_CODE}, | |
| 4646 | − { FLASH_iSCSI_BIOS_START_g2, OPTYPE_BIOS, | |
| 4647 | − FLASH_BIOS_IMAGE_MAX_SIZE_g2, IMAGE_OPTION_ROM_ISCSI}, | |
| 4648 | − { FLASH_PXE_BIOS_START_g2, OPTYPE_PXE_BIOS, | |
| 4649 | − FLASH_BIOS_IMAGE_MAX_SIZE_g2, IMAGE_OPTION_ROM_PXE}, | |
| 4650 | − { FLASH_FCoE_BIOS_START_g2, OPTYPE_FCOE_BIOS, | |
| 4651 | − FLASH_BIOS_IMAGE_MAX_SIZE_g2, IMAGE_OPTION_ROM_FCoE}, | |
| 4652 | − { FLASH_iSCSI_BACKUP_IMAGE_START_g2, OPTYPE_ISCSI_BACKUP, | |
| 4653 | − FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_BACKUP_iSCSI}, | |
| 4654 | − { FLASH_FCoE_PRIMARY_IMAGE_START_g2, OPTYPE_FCOE_FW_ACTIVE, | |
| 4655 | − FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_FCoE}, | |
| 4656 | − { FLASH_FCoE_BACKUP_IMAGE_START_g2, OPTYPE_FCOE_FW_BACKUP, | |
| 4657 | − FLASH_IMAGE_MAX_SIZE_g2, IMAGE_FIRMWARE_BACKUP_FCoE} | |
| 4658 | − }; | |
| 4659 | − | |
| 4660 | − if (BE3_chip(adapter)) { | |
| 4661 | − pflashcomp = gen3_flash_types; | |
| 4662 | − filehdr_size = sizeof(struct flash_file_hdr_g3); | |
| 4663 | − num_comp = ARRAY_SIZE(gen3_flash_types); | |
| 4664 | − } else { | |
| 4665 | − pflashcomp = gen2_flash_types; | |
| 4666 | − filehdr_size = sizeof(struct flash_file_hdr_g2); | |
| 4667 | − num_comp = ARRAY_SIZE(gen2_flash_types); | |
| 4668 | − img_hdrs_size = 0; | |
| 4669 | − } | |
| 4670 | − | |
| 4671 | − /* Get flash section info*/ | |
| 4672 | − fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw); | |
| 4673 | − if (!fsec) { | |
| 4674 | − dev_err(dev, "Invalid Cookie. FW image may be corrupted\n"); | |
| 4675 | − return -1; | |
| 4676 | − } | |
| 4677 | − for (i = 0; i < num_comp; i++) { | |
| 4678 | − if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type)) | |
| 4679 | − continue; | |
| 4680 | − | |
| 4681 | − if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) && | |
| 4682 | − memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0) | |
| 4683 | − continue; | |
| 4684 | − | |
| 4685 | − if (pflashcomp[i].optype == OPTYPE_PHY_FW && | |
| 4686 | − !phy_flashing_required(adapter)) | |
| 4687 | − continue; | |
| 4688 | − | |
| 4689 | − if (pflashcomp[i].optype == OPTYPE_REDBOOT) { | |
| 4690 | − status = be_check_flash_crc(adapter, fw->data, | |
| 4691 | − pflashcomp[i].offset, | |
| 4692 | − pflashcomp[i].size, | |
| 4693 | − filehdr_size + | |
| 4694 | − img_hdrs_size, | |
| 4695 | − OPTYPE_REDBOOT, &crc_match); | |
| 4696 | − if (status) { | |
| 4697 | − dev_err(dev, | |
| 4698 | − "Could not get CRC for 0x%x region\n", | |
| 4699 | − pflashcomp[i].optype); | |
| 4700 | − continue; | |
| 4701 | − } | |
| 4702 | − | |
| 4703 | − if (crc_match) | |
| 4704 | − continue; | |
| 4705 | − } | |
| 4706 | − | |
| 4707 | − p = fw->data + filehdr_size + pflashcomp[i].offset + | |
| 4708 | − img_hdrs_size; | |
| 4709 | − if (p + pflashcomp[i].size > fw->data + fw->size) | |
| 4710 | − return -1; | |
| 4711 | − | |
| 4712 | − status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype, | |
| 4713 | − pflashcomp[i].size, 0); | |
| 4714 | − if (status) { | |
| 4715 | − dev_err(dev, "Flashing section type 0x%x failed\n", | |
| 4716 | − pflashcomp[i].img_type); | |
| 4717 | − return status; | |
| 4718 | − } | |
| 4719 | − } | |
| 4720 | − return 0; | |
| 4721 | −} | |
| 4722 | − | |
| 4723 | −static u16 be_get_img_optype(struct flash_section_entry fsec_entry) | |
| 4724 | −{ | |
| 4725 | − u32 img_type = le32_to_cpu(fsec_entry.type); | |
| 4726 | − u16 img_optype = le16_to_cpu(fsec_entry.optype); | |
| 4727 | − | |
| 4728 | − if (img_optype != 0xFFFF) | |
| 4729 | − return img_optype; | |
| 4730 | − | |
| 4731 | − switch (img_type) { | |
| 4732 | − case IMAGE_FIRMWARE_iSCSI: | |
| 4733 | − img_optype = OPTYPE_ISCSI_ACTIVE; | |
| 4734 | − break; | |
| 4735 | − case IMAGE_BOOT_CODE: | |
| 4736 | − img_optype = OPTYPE_REDBOOT; | |
| 4737 | − break; | |
| 4738 | − case IMAGE_OPTION_ROM_ISCSI: | |
| 4739 | − img_optype = OPTYPE_BIOS; | |
| 4740 | − break; | |
| 4741 | − case IMAGE_OPTION_ROM_PXE: | |
| 4742 | − img_optype = OPTYPE_PXE_BIOS; | |
| 4743 | − break; | |
| 4744 | − case IMAGE_OPTION_ROM_FCoE: | |
| 4745 | − img_optype = OPTYPE_FCOE_BIOS; | |
| 4746 | − break; | |
| 4747 | − case IMAGE_FIRMWARE_BACKUP_iSCSI: | |
| 4748 | − img_optype = OPTYPE_ISCSI_BACKUP; | |
| 4749 | − break; | |
| 4750 | − case IMAGE_NCSI: | |
| 4751 | − img_optype = OPTYPE_NCSI_FW; | |
| 4752 | − break; | |
| 4753 | − case IMAGE_FLASHISM_JUMPVECTOR: | |
| 4754 | − img_optype = OPTYPE_FLASHISM_JUMPVECTOR; | |
| 4755 | − break; | |
| 4756 | − case IMAGE_FIRMWARE_PHY: | |
| 4757 | − img_optype = OPTYPE_SH_PHY_FW; | |
| 4758 | − break; | |
| 4759 | − case IMAGE_REDBOOT_DIR: | |
| 4760 | − img_optype = OPTYPE_REDBOOT_DIR; | |
| 4761 | − break; | |
| 4762 | − case IMAGE_REDBOOT_CONFIG: | |
| 4763 | − img_optype = OPTYPE_REDBOOT_CONFIG; | |
| 4764 | − break; | |
| 4765 | − case IMAGE_UFI_DIR: | |
| 4766 | − img_optype = OPTYPE_UFI_DIR; | |
| 4767 | − break; | |
| 4768 | − default: | |
| 4769 | − break; | |
| 4770 | − } | |
| 4771 | − | |
| 4772 | − return img_optype; | |
| 4773 | −} | |
| 4774 | − | |
| 4775 | −static int be_flash_skyhawk(struct be_adapter *adapter, | |
| 4776 | − const struct firmware *fw, | |
| 4777 | − struct be_dma_mem *flash_cmd, int num_of_images) | |
| 4778 | −{ | |
| 4779 | − int img_hdrs_size = num_of_images * sizeof(struct image_hdr); | |
| 4780 | − bool crc_match, old_fw_img, flash_offset_support = true; | |
| 4781 | − struct device *dev = &adapter->pdev->dev; | |
| 4782 | − struct flash_section_info *fsec = NULL; | |
| 4783 | − u32 img_offset, img_size, img_type; | |
| 4784 | − u16 img_optype, flash_optype; | |
| 4785 | − int status, i, filehdr_size; | |
| 4786 | − const u8 *p; | |
| 4787 | − | |
| 4788 | − filehdr_size = sizeof(struct flash_file_hdr_g3); | |
| 4789 | − fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw); | |
| 4790 | − if (!fsec) { | |
| 4791 | − dev_err(dev, "Invalid Cookie. FW image may be corrupted\n"); | |
| 4792 | − return -EINVAL; | |
| 4793 | − } | |
| 4794 | − | |
| 4795 | −retry_flash: | |
| 4796 | − for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) { | |
| 4797 | − img_offset = le32_to_cpu(fsec->fsec_entry[i].offset); | |
| 4798 | − img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size); | |
| 4799 | − img_type = le32_to_cpu(fsec->fsec_entry[i].type); | |
| 4800 | − img_optype = be_get_img_optype(fsec->fsec_entry[i]); | |
| 4801 | − old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF; | |
| 4802 | − | |
| 4803 | − if (img_optype == 0xFFFF) | |
| 4804 | − continue; | |
| 4805 | − | |
| 4806 | − if (flash_offset_support) | |
| 4807 | − flash_optype = OPTYPE_OFFSET_SPECIFIED; | |
| 4808 | − else | |
| 4809 | − flash_optype = img_optype; | |
| 4810 | − | |
| 4811 | − /* Don't bother verifying CRC if an old FW image is being | |
| 4812 | − * flashed | |
| 4813 | − */ | |
| 4814 | − if (old_fw_img) | |
| 4815 | − goto flash; | |
| 4816 | − | |
| 4817 | − status = be_check_flash_crc(adapter, fw->data, img_offset, | |
| 4818 | − img_size, filehdr_size + | |
| 4819 | − img_hdrs_size, flash_optype, | |
| 4820 | − &crc_match); | |
| 4821 | − if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST || | |
| 4822 | − base_status(status) == MCC_STATUS_ILLEGAL_FIELD) { | |
| 4823 | − /* The current FW image on the card does not support | |
| 4824 | − * OFFSET based flashing. Retry using older mechanism | |
| 4825 | − * of OPTYPE based flashing | |
| 4826 | − */ | |
| 4827 | − if (flash_optype == OPTYPE_OFFSET_SPECIFIED) { | |
| 4828 | − flash_offset_support = false; | |
| 4829 | − goto retry_flash; | |
| 4830 | − } | |
| 4831 | − | |
| 4832 | − /* The current FW image on the card does not recognize | |
| 4833 | − * the new FLASH op_type. The FW download is partially | |
| 4834 | − * complete. Reboot the server now to enable FW image | |
| 4835 | − * to recognize the new FLASH op_type. To complete the | |
| 4836 | − * remaining process, download the same FW again after | |
| 4837 | − * the reboot. | |
| 4838 | − */ | |
| 4839 | − dev_err(dev, "Flash incomplete. Reset the server\n"); | |
| 4840 | − dev_err(dev, "Download FW image again after reset\n"); | |
| 4841 | − return -EAGAIN; | |
| 4842 | − } else if (status) { | |
| 4843 | − dev_err(dev, "Could not get CRC for 0x%x region\n", | |
| 4844 | − img_optype); | |
| 4845 | − return -EFAULT; | |
| 4846 | − } | |
| 4847 | − | |
| 4848 | − if (crc_match) | |
| 4849 | − continue; | |
| 4850 | − | |
| 4851 | −flash: | |
| 4852 | − p = fw->data + filehdr_size + img_offset + img_hdrs_size; | |
| 4853 | − if (p + img_size > fw->data + fw->size) | |
| 4854 | − return -1; | |
| 4855 | − | |
| 4856 | − status = be_flash(adapter, p, flash_cmd, flash_optype, img_size, | |
| 4857 | − img_offset); | |
| 4858 | − | |
| 4859 | − /* The current FW image on the card does not support OFFSET | |
| 4860 | − * based flashing. Retry using older mechanism of OPTYPE based | |
| 4861 | − * flashing | |
| 4862 | − */ | |
| 4863 | − if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD && | |
| 4864 | − flash_optype == OPTYPE_OFFSET_SPECIFIED) { | |
| 4865 | − flash_offset_support = false; | |
| 4866 | − goto retry_flash; | |
| 4867 | − } | |
| 4868 | − | |
| 4869 | − /* For old FW images ignore ILLEGAL_FIELD error or errors on | |
| 4870 | − * UFI_DIR region | |
| 4871 | − */ | |
| 4872 | − if (old_fw_img && | |
| 4873 | − (base_status(status) == MCC_STATUS_ILLEGAL_FIELD || | |
| 4874 | − (img_optype == OPTYPE_UFI_DIR && | |
| 4875 | − base_status(status) == MCC_STATUS_FAILED))) { | |
| 4876 | − continue; | |
| 4877 | − } else if (status) { | |
| 4878 | − dev_err(dev, "Flashing section type 0x%x failed\n", | |
| 4879 | − img_type); | |
| 4880 | − return -EFAULT; | |
| 4881 | − } | |
| 4882 | − } | |
| 4883 | − return 0; | |
| 4884 | −} | |
| 4885 | − | |
| 4886 | −static int lancer_fw_download(struct be_adapter *adapter, | |
| 4887 | − const struct firmware *fw) | |
| 4888 | −{ | |
| 4889 | −#define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024) | |
| 4890 | −#define LANCER_FW_DOWNLOAD_LOCATION "/prg" | |
| 4891 | − struct device *dev = &adapter->pdev->dev; | |
| 4892 | − struct be_dma_mem flash_cmd; | |
| 4893 | − const u8 *data_ptr = NULL; | |
| 4894 | − u8 *dest_image_ptr = NULL; | |
| 4895 | − size_t image_size = 0; | |
| 4896 | − u32 chunk_size = 0; | |
| 4897 | − u32 data_written = 0; | |
| 4898 | − u32 offset = 0; | |
| 4899 | − int status = 0; | |
| 4900 | − u8 add_status = 0; | |
| 4901 | − u8 change_status; | |
| 4902 | − | |
| 4903 | − if (!IS_ALIGNED(fw->size, sizeof(u32))) { | |
| 4904 | − dev_err(dev, "FW image size should be multiple of 4\n"); | |
| 4905 | − return -EINVAL; | |
| 4906 | − } | |
| 4907 | − | |
| 4908 | − flash_cmd.size = sizeof(struct lancer_cmd_req_write_object) | |
| 4909 | − + LANCER_FW_DOWNLOAD_CHUNK; | |
| 4910 | − flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, | |
| 4911 | − &flash_cmd.dma, GFP_KERNEL); | |
| 4912 | − if (!flash_cmd.va) | |
| 4913 | − return -ENOMEM; | |
| 4914 | − | |
| 4915 | − dest_image_ptr = flash_cmd.va + | |
| 4916 | − sizeof(struct lancer_cmd_req_write_object); | |
| 4917 | − image_size = fw->size; | |
| 4918 | − data_ptr = fw->data; | |
| 4919 | − | |
| 4920 | − while (image_size) { | |
| 4921 | − chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK); | |
| 4922 | − | |
| 4923 | − /* Copy the image chunk content. */ | |
| 4924 | − memcpy(dest_image_ptr, data_ptr, chunk_size); | |
| 4925 | − | |
| 4926 | − status = lancer_cmd_write_object(adapter, &flash_cmd, | |
| 4927 | − chunk_size, offset, | |
| 4928 | − LANCER_FW_DOWNLOAD_LOCATION, | |
| 4929 | − &data_written, &change_status, | |
| 4930 | − &add_status); | |
| 4931 | − if (status) | |
| 4932 | − break; | |
| 4933 | − | |
| 4934 | − offset += data_written; | |
| 4935 | − data_ptr += data_written; | |
| 4936 | − image_size -= data_written; | |
| 4937 | − } | |
| 4938 | − | |
| 4939 | − if (!status) { | |
| 4940 | − /* Commit the FW written */ | |
| 4941 | − status = lancer_cmd_write_object(adapter, &flash_cmd, | |
| 4942 | − 0, offset, | |
| 4943 | − LANCER_FW_DOWNLOAD_LOCATION, | |
| 4944 | − &data_written, &change_status, | |
| 4945 | − &add_status); | |
| 4946 | − } | |
| 4947 | − | |
| 4948 | − dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma); | |
| 4949 | − if (status) { | |
| 4950 | − dev_err(dev, "Firmware load error\n"); | |
| 4951 | − return be_cmd_status(status); | |
| 4952 | − } | |
| 4953 | − | |
| 4954 | − dev_info(dev, "Firmware flashed successfully\n"); | |
| 4955 | − | |
| 4956 | − if (change_status == LANCER_FW_RESET_NEEDED) { | |
| 4957 | − dev_info(dev, "Resetting adapter to activate new FW\n"); | |
| 4958 | − status = lancer_physdev_ctrl(adapter, | |
| 4959 | − PHYSDEV_CONTROL_FW_RESET_MASK); | |
| 4960 | − if (status) { | |
| 4961 | − dev_err(dev, "Adapter busy, could not reset FW\n"); | |
| 4962 | − dev_err(dev, "Reboot server to activate new FW\n"); | |
| 4963 | − } | |
| 4964 | − } else if (change_status != LANCER_NO_RESET_NEEDED) { | |
| 4965 | − dev_info(dev, "Reboot server to activate new FW\n"); | |
| 4966 | − } | |
| 4967 | − | |
| 4968 | − return 0; | |
| 4969 | −} | |
| 4970 | − | |
| 4971 | −/* Check if the flash image file is compatible with the adapter that | |
| 4972 | − * is being flashed. | |
| 4973 | − */ | |
| 4974 | −static bool be_check_ufi_compatibility(struct be_adapter *adapter, | |
| 4975 | − struct flash_file_hdr_g3 *fhdr) | |
| 4976 | −{ | |
| 4977 | − if (!fhdr) { | |
| 4978 | − dev_err(&adapter->pdev->dev, "Invalid FW UFI file"); | |
| 4979 | − return false; | |
| 4980 | − } | |
| 4981 | − | |
| 4982 | − /* First letter of the build version is used to identify | |
| 4983 | − * which chip this image file is meant for. | |
| 4984 | − */ | |
| 4985 | − switch (fhdr->build[0]) { | |
| 4986 | − case BLD_STR_UFI_TYPE_SH: | |
| 4987 | − if (!skyhawk_chip(adapter)) | |
| 4988 | − return false; | |
| 4989 | − break; | |
| 4990 | − case BLD_STR_UFI_TYPE_BE3: | |
| 4991 | − if (!BE3_chip(adapter)) | |
| 4992 | − return false; | |
| 4993 | − break; | |
| 4994 | − case BLD_STR_UFI_TYPE_BE2: | |
| 4995 | − if (!BE2_chip(adapter)) | |
| 4996 | − return false; | |
| 4997 | − break; | |
| 4998 | − default: | |
| 4999 | − return false; | |
| 5000 | − } | |
| 5001 | − | |
| 5002 | − /* In BE3 FW images the "asic_type_rev" field doesn't track the | |
| 5003 | − * asic_rev of the chips it is compatible with. | |
| 5004 | − * When asic_type_rev is 0 the image is compatible only with | |
| 5005 | − * pre-BE3-R chips (asic_rev < 0x10) | |
| 5006 | − */ | |
| 5007 | − if (BEx_chip(adapter) && fhdr->asic_type_rev == 0) | |
| 5008 | − return adapter->asic_rev < 0x10; | |
| 5009 | − else | |
| 5010 | − return (fhdr->asic_type_rev >= adapter->asic_rev); | |
| 5011 | −} | |
| 5012 | − | |
| 5013 | −static int be_fw_download(struct be_adapter *adapter, const struct firmware* fw) | |
| 5014 | −{ | |
| 5015 | − struct device *dev = &adapter->pdev->dev; | |
| 5016 | − struct flash_file_hdr_g3 *fhdr3; | |
| 5017 | − struct image_hdr *img_hdr_ptr; | |
| 5018 | − int status = 0, i, num_imgs; | |
| 5019 | − struct be_dma_mem flash_cmd; | |
| 5020 | − | |
| 5021 | − fhdr3 = (struct flash_file_hdr_g3 *)fw->data; | |
| 5022 | − if (!be_check_ufi_compatibility(adapter, fhdr3)) { | |
| 5023 | − dev_err(dev, "Flash image is not compatible with adapter\n"); | |
| 5024 | − return -EINVAL; | |
| 5025 | − } | |
| 5026 | − | |
| 5027 | − flash_cmd.size = sizeof(struct be_cmd_write_flashrom); | |
| 5028 | − flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma, | |
| 5029 | − GFP_KERNEL); | |
| 5030 | − if (!flash_cmd.va) | |
| 5031 | − return -ENOMEM; | |
| 5032 | − | |
| 5033 | − num_imgs = le32_to_cpu(fhdr3->num_imgs); | |
| 5034 | − for (i = 0; i < num_imgs; i++) { | |
| 5035 | − img_hdr_ptr = (struct image_hdr *)(fw->data + | |
| 5036 | − (sizeof(struct flash_file_hdr_g3) + | |
| 5037 | − i * sizeof(struct image_hdr))); | |
| 5038 | − if (!BE2_chip(adapter) && | |
| 5039 | − le32_to_cpu(img_hdr_ptr->imageid) != 1) | |
| 5040 | − continue; | |
| 5041 | − | |
| 5042 | − if (skyhawk_chip(adapter)) | |
| 5043 | − status = be_flash_skyhawk(adapter, fw, &flash_cmd, | |
| 5044 | − num_imgs); | |
| 5045 | − else | |
| 5046 | − status = be_flash_BEx(adapter, fw, &flash_cmd, | |
| 5047 | − num_imgs); | |
| 5048 | − } | |
| 5049 | − | |
| 5050 | − dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma); | |
| 5051 | − if (!status) | |
| 5052 | − dev_info(dev, "Firmware flashed successfully\n"); | |
| 5053 | − | |
| 5054 | − return status; | |
| 5055 | −} | |
| 5056 | − | |
| 5057 | 4502 | int be_load_fw(struct be_adapter *adapter, u8 *fw_file) |
| 5058 | 4503 | { |
| 5059 | 4504 | const struct firmware *fw; |
| @@ -5108,6 +4553,9 @@ static int be_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, · 48 unmodified lines | ||
| 5108 | 4553 | return -EINVAL; |
| 5109 | 4554 | |
| 5110 | 4555 | mode = nla_get_u16(attr); |
| 4556 | + if (BE3_chip(adapter) && mode == BRIDGE_MODE_VEPA) | |
| 4557 | + return -EOPNOTSUPP; | |
| 4558 | + | |
| 5111 | 4559 | if (mode != BRIDGE_MODE_VEPA && mode != BRIDGE_MODE_VEB) |
| 5112 | 4560 | return -EINVAL; |
| 5113 | 4561 | |
| @@ -5289,7 +4737,7 @@ static netdev_features_t be_features_check(struct sk_buff *skb, · 175 unmodified lines | ||
| 5289 | 4737 | skb->inner_protocol != htons(ETH_P_TEB) || |
| 5290 | 4738 | skb_inner_mac_header(skb) - skb_transport_header(skb) != |
| 5291 | 4739 | sizeof(struct udphdr) + sizeof(struct vxlanhdr)) |
| 5292 | − return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); | |
| 4740 | + return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
| 5293 | 4741 | |
| 5294 | 4742 | return features; |
| 5295 | 4743 | } |
| @@ -678,7 +678,7 @@ static int ethoc_mdio_probe(struct net_device *dev) · 677 unmodified lines | ||
| 678 | 678 | int err; |
| 679 | 679 | |
| 680 | 680 | if (priv->phy_id != -1) |
| 681 | − phy = priv->mdio->phy_map[priv->phy_id]; | |
| 681 | + phy = mdiobus_get_phy(priv->mdio, priv->phy_id); | |
| 682 | 682 | else |
| 683 | 683 | phy = phy_find_first(priv->mdio); |
| 684 | 684 | |
| @@ -766,7 +766,7 @@ static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) · 81 unmodified lines | ||
| 766 | 766 | if (mdio->phy_id >= PHY_MAX_ADDR) |
| 767 | 767 | return -ERANGE; |
| 768 | 768 | |
| 769 | − phy = priv->mdio->phy_map[mdio->phy_id]; | |
| 769 | + phy = mdiobus_get_phy(priv->mdio, mdio->phy_id); | |
| 770 | 770 | if (!phy) |
| 771 | 771 | return -ENODEV; |
| 772 | 772 | } else { |
| @@ -1015,7 +1015,6 @@ static int ethoc_probe(struct platform_device *pdev) · 242 unmodified lines | ||
| 1015 | 1015 | struct resource *mmio = NULL; |
| 1016 | 1016 | struct resource *mem = NULL; |
| 1017 | 1017 | struct ethoc *priv = NULL; |
| 1018 | − unsigned int phy; | |
| 1019 | 1018 | int num_bd; |
| 1020 | 1019 | int ret = 0; |
| 1021 | 1020 | bool random_mac = false; |
| @@ -1206,19 +1205,10 @@ static int ethoc_probe(struct platform_device *pdev) · 184 unmodified lines | ||
| 1206 | 1205 | priv->mdio->write = ethoc_mdio_write; |
| 1207 | 1206 | priv->mdio->priv = priv; |
| 1208 | 1207 | |
| 1209 | − priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
| 1210 | − if (!priv->mdio->irq) { | |
| 1211 | − ret = -ENOMEM; | |
| 1212 | − goto free_mdio; | |
| 1213 | − } | |
| 1214 | − | |
| 1215 | − for (phy = 0; phy < PHY_MAX_ADDR; phy++) | |
| 1216 | − priv->mdio->irq[phy] = PHY_POLL; | |
| 1217 | − | |
| 1218 | 1208 | ret = mdiobus_register(priv->mdio); |
| 1219 | 1209 | if (ret) { |
| 1220 | 1210 | dev_err(&netdev->dev, "failed to register MDIO bus\n"); |
| 1221 | − goto free_mdio; | |
| 1211 | + goto free; | |
| 1222 | 1212 | } |
| 1223 | 1213 | |
| 1224 | 1214 | ret = ethoc_mdio_probe(netdev); |
| @@ -1250,8 +1240,6 @@ error2: · 25 unmodified lines | ||
| 1250 | 1240 | netif_napi_del(&priv->napi); |
| 1251 | 1241 | error: |
| 1252 | 1242 | mdiobus_unregister(priv->mdio); |
| 1253 | −free_mdio: | |
| 1254 | − kfree(priv->mdio->irq); | |
| 1255 | 1243 | mdiobus_free(priv->mdio); |
| 1256 | 1244 | free: |
| 1257 | 1245 | if (priv->clk) |
| @@ -71,7 +71,6 @@ struct ftgmac100 { · 70 unmodified lines | ||
| 71 | 71 | struct napi_struct napi; |
| 72 | 72 | |
| 73 | 73 | struct mii_bus *mii_bus; |
| 74 | − int phy_irq[PHY_MAX_ADDR]; | |
| 75 | 74 | struct phy_device *phydev; |
| 76 | 75 | int old_speed; |
| 77 | 76 | }; |
| @@ -835,26 +834,15 @@ static void ftgmac100_adjust_link(struct net_device *netdev) · 757 unmodified lines | ||
| 835 | 834 | static int ftgmac100_mii_probe(struct ftgmac100 *priv) |
| 836 | 835 | { |
| 837 | 836 | struct net_device *netdev = priv->netdev; |
| 838 | − struct phy_device *phydev = NULL; | |
| 839 | − int i; | |
| 840 | − | |
| 841 | − /* search for connect PHY device */ | |
| 842 | − for (i = 0; i < PHY_MAX_ADDR; i++) { | |
| 843 | − struct phy_device *tmp = priv->mii_bus->phy_map[i]; | |
| 844 | − | |
| 845 | − if (tmp) { | |
| 846 | − phydev = tmp; | |
| 847 | − break; | |
| 848 | − } | |
| 849 | − } | |
| 837 | + struct phy_device *phydev; | |
| 850 | 838 | |
| 851 | − /* now we are supposed to have a proper phydev, to attach to... */ | |
| 839 | + phydev = phy_find_first(priv->mii_bus); | |
| 852 | 840 | if (!phydev) { |
| 853 | 841 | netdev_info(netdev, "%s: no PHY found\n", netdev->name); |
| 854 | 842 | return -ENODEV; |
| 855 | 843 | } |
| 856 | 844 | |
| 857 | − phydev = phy_connect(netdev, dev_name(&phydev->dev), | |
| 845 | + phydev = phy_connect(netdev, phydev_name(phydev), | |
| 858 | 846 | &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); |
| 859 | 847 | |
| 860 | 848 | if (IS_ERR(phydev)) { |
| @@ -1188,7 +1176,6 @@ static int ftgmac100_probe(struct platform_device *pdev) · 327 unmodified lines | ||
| 1188 | 1176 | struct net_device *netdev; |
| 1189 | 1177 | struct ftgmac100 *priv; |
| 1190 | 1178 | int err; |
| 1191 | − int i; | |
| 1192 | 1179 | |
| 1193 | 1180 | if (!pdev) |
| 1194 | 1181 | return -ENODEV; |
| @@ -1257,10 +1244,6 @@ static int ftgmac100_probe(struct platform_device *pdev) · 62 unmodified lines | ||
| 1257 | 1244 | priv->mii_bus->priv = netdev; |
| 1258 | 1245 | priv->mii_bus->read = ftgmac100_mdiobus_read; |
| 1259 | 1246 | priv->mii_bus->write = ftgmac100_mdiobus_write; |
| 1260 | − priv->mii_bus->irq = priv->phy_irq; | |
| 1261 | − | |
| 1262 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 1263 | − priv->mii_bus->irq[i] = PHY_POLL; | |
| 1264 | 1247 | |
| 1265 | 1248 | err = mdiobus_register(priv->mii_bus); |
| 1266 | 1249 | if (err) { |
| @@ -54,6 +54,7 @@ config FEC_MPC52xx_MDIO · 53 unmodified lines | ||
| 54 | 54 | If compiled as module, it will be called fec_mpc52xx_phy. |
| 55 | 55 | |
| 56 | 56 | source "drivers/net/ethernet/freescale/fs_enet/Kconfig" |
| 57 | +source "drivers/net/ethernet/freescale/fman/Kconfig" | |
| 57 | 58 | |
| 58 | 59 | config FSL_PQ_MDIO |
| 59 | 60 | tristate "Freescale PQ MDIO" |
| @@ -17,3 +17,5 @@ gianfar_driver-objs := gianfar.o \ · 16 unmodified lines | ||
| 17 | 17 | gianfar_ethtool.o |
| 18 | 18 | obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o |
| 19 | 19 | ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o |
| 20 | + | |
| 21 | +obj-$(CONFIG_FSL_FMAN) += fman/ | |
| @@ -48,6 +48,7 @@ · 47 unmodified lines | ||
| 48 | 48 | #include <linux/irq.h> |
| 49 | 49 | #include <linux/clk.h> |
| 50 | 50 | #include <linux/platform_device.h> |
| 51 | +#include <linux/mdio.h> | |
| 51 | 52 | #include <linux/phy.h> |
| 52 | 53 | #include <linux/fec.h> |
| 53 | 54 | #include <linux/of.h> |
| @@ -1926,11 +1927,7 @@ static int fec_enet_mii_probe(struct net_device *ndev) · 1872 unmodified lines | ||
| 1926 | 1927 | } else { |
| 1927 | 1928 | /* check for attached phy */ |
| 1928 | 1929 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { |
| 1929 | − if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
| 1930 | − continue; | |
| 1931 | − if (fep->mii_bus->phy_map[phy_id] == NULL) | |
| 1932 | − continue; | |
| 1933 | − if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
| 1930 | + if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) | |
| 1934 | 1931 | continue; |
| 1935 | 1932 | if (dev_id--) |
| 1936 | 1933 | continue; |
| @@ -1972,9 +1969,7 @@ static int fec_enet_mii_probe(struct net_device *ndev) · 35 unmodified lines | ||
| 1972 | 1969 | fep->link = 0; |
| 1973 | 1970 | fep->full_duplex = 0; |
| 1974 | 1971 | |
| 1975 | − netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
| 1976 | − fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
| 1977 | − fep->phy_dev->irq); | |
| 1972 | + phy_attached_info(phy_dev); | |
| 1978 | 1973 | |
| 1979 | 1974 | return 0; |
| 1980 | 1975 | } |
| @@ -1985,7 +1980,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) · 4 unmodified lines | ||
| 1985 | 1980 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1986 | 1981 | struct fec_enet_private *fep = netdev_priv(ndev); |
| 1987 | 1982 | struct device_node *node; |
| 1988 | − int err = -ENXIO, i; | |
| 1983 | + int err = -ENXIO; | |
| 1989 | 1984 | u32 mii_speed, holdtime; |
| 1990 | 1985 | |
| 1991 | 1986 | /* |
| @@ -2067,15 +2062,6 @@ static int fec_enet_mii_init(struct platform_device *pdev) · 75 unmodified lines | ||
| 2067 | 2062 | fep->mii_bus->priv = fep; |
| 2068 | 2063 | fep->mii_bus->parent = &pdev->dev; |
| 2069 | 2064 | |
| 2070 | − fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
| 2071 | − if (!fep->mii_bus->irq) { | |
| 2072 | − err = -ENOMEM; | |
| 2073 | − goto err_out_free_mdiobus; | |
| 2074 | − } | |
| 2075 | − | |
| 2076 | − for (i = 0; i < PHY_MAX_ADDR; i++) | |
| 2077 | − fep->mii_bus->irq[i] = PHY_POLL; | |
| 2078 | − | |
| 2079 | 2065 | node = of_get_child_by_name(pdev->dev.of_node, "mdio"); |
| 2080 | 2066 | if (node) { |
| 2081 | 2067 | err = of_mdiobus_register(fep->mii_bus, node); |
| @@ -2085,7 +2071,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) · 3 unmodified lines | ||
| 2085 | 2071 | } |
| 2086 | 2072 | |
| 2087 | 2073 | if (err) |
| 2088 | − goto err_out_free_mdio_irq; | |
| 2074 | + goto err_out_free_mdiobus; | |
| 2089 | 2075 | |
| 2090 | 2076 | mii_cnt++; |
| 2091 | 2077 | |
| @@ -2095,8 +2081,6 @@ static int fec_enet_mii_init(struct platform_device *pdev) · 3 unmodified lines | ||
| 2095 | 2081 | |
| 2096 | 2082 | return 0; |
| 2097 | 2083 | |
| 2098 | −err_out_free_mdio_irq: | |
| 2099 | − kfree(fep->mii_bus->irq); | |
| 2100 | 2084 | err_out_free_mdiobus: |
| 2101 | 2085 | mdiobus_free(fep->mii_bus); |
| 2102 | 2086 | err_out: |
| @@ -2107,7 +2091,6 @@ static void fec_enet_mii_remove(struct fec_enet_private *fep) · 4 unmodified lines | ||
| 2107 | 2091 | { |
| 2108 | 2092 | if (--mii_cnt == 0) { |
| 2109 | 2093 | mdiobus_unregister(fep->mii_bus); |
| 2110 | − kfree(fep->mii_bus->irq); | |
| 2111 | 2094 | mdiobus_free(fep->mii_bus); |
| 2112 | 2095 | } |
| 2113 | 2096 | } |
| @@ -3277,7 +3260,6 @@ static void · 1163 unmodified lines | ||
| 3277 | 3260 | fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) |
| 3278 | 3261 | { |
| 3279 | 3262 | struct device_node *np = pdev->dev.of_node; |
| 3280 | − int err; | |
| 3281 | 3263 | |
| 3282 | 3264 | *num_tx = *num_rx = 1; |
| 3283 | 3265 | |
| @@ -3285,13 +3267,9 @@ fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) · 1 unmodified line | ||
| 3285 | 3267 | return; |
| 3286 | 3268 | |
| 3287 | 3269 | /* parse the num of tx and rx queues */ |
| 3288 | − err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx); | |
| 3289 | − if (err) | |
| 3290 | − *num_tx = 1; | |
| 3270 | + of_property_read_u32(np, "fsl,num-tx-queues", num_tx); | |
| 3291 | 3271 | |
| 3292 | − err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx); | |
| 3293 | − if (err) | |
| 3294 | − *num_rx = 1; | |
| 3272 | + of_property_read_u32(np, "fsl,num-rx-queues", num_rx); | |
| 3295 | 3273 | |
| 3296 | 3274 | if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { |
| 3297 | 3275 | dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", |
| @@ -1084,27 +1084,23 @@ static struct platform_driver mpc52xx_fec_driver = { · 1083 unmodified lines | ||
| 1084 | 1084 | /* Module */ |
| 1085 | 1085 | /* ======================================================================== */ |
| 1086 | 1086 | |
| 1087 | +static struct platform_driver * const drivers[] = { | |
| 1088 | +#ifdef CONFIG_FEC_MPC52xx_MDIO | |
| 1089 | + &mpc52xx_fec_mdio_driver, | |
| 1090 | +#endif | |
| 1091 | + &mpc52xx_fec_driver, | |
| 1092 | +}; | |
| 1093 | + | |
| 1087 | 1094 | static int __init |
| 1088 | 1095 | mpc52xx_fec_init(void) |
| 1089 | 1096 | { |
| 1090 | −#ifdef CONFIG_FEC_MPC52xx_MDIO | |
| 1091 | − int ret; | |
| 1092 | − ret = platform_driver_register(&mpc52xx_fec_mdio_driver); | |
| 1093 | − if (ret) { | |
| 1094 | − pr_err("failed to register mdio driver\n"); | |
| 1095 | − return ret; | |
| 1096 | − } | |
| 1097 | −#endif | |
| 1098 | − return platform_driver_register(&mpc52xx_fec_driver); | |
| 1097 | + return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); | |
| 1099 | 1098 | } |
| 1100 | 1099 | |
| 1101 | 1100 | static void __exit |
| 1102 | 1101 | mpc52xx_fec_exit(void) |
| 1103 | 1102 | { |
| 1104 | − platform_driver_unregister(&mpc52xx_fec_driver); | |
| 1105 | −#ifdef CONFIG_FEC_MPC52xx_MDIO | |
| 1106 | − platform_driver_unregister(&mpc52xx_fec_mdio_driver); | |
| 1107 | −#endif | |
| 1103 | + platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); | |
| 1108 | 1104 | } |
| 1109 | 1105 | |
| 1110 | 1106 | |
| @@ -22,7 +22,6 @@ · 21 unmodified lines | ||
| 22 | 22 | |
| 23 | 23 | struct mpc52xx_fec_mdio_priv { |
| 24 | 24 | struct mpc52xx_fec __iomem *regs; |
| 25 | − int mdio_irqs[PHY_MAX_ADDR]; | |
| 26 | 25 | }; |
| 27 | 26 | |
| 28 | 27 | static int mpc52xx_fec_mdio_transfer(struct mii_bus *bus, int phy_id, |
| @@ -83,9 +82,6 @@ static int mpc52xx_fec_mdio_probe(struct platform_device *of) · 54 unmodified lines | ||
| 83 | 82 | bus->read = mpc52xx_fec_mdio_read; |
| 84 | 83 | bus->write = mpc52xx_fec_mdio_write; |
| 85 | 84 | |
| 86 | − /* setup irqs */ | |
| 87 | − bus->irq = priv->mdio_irqs; | |
| 88 | − | |
| 89 | 85 | /* setup registers */ |
| 90 | 86 | err = of_address_to_resource(np, 0, &res); |
| 91 | 87 | if (err) |
| @@ -0,0 +1,9 @@ | ||
| 1 | +config FSL_FMAN | |
| 2 | + tristate "FMan support" | |
| 3 | + depends on FSL_SOC || COMPILE_TEST | |
| 4 | + select GENERIC_ALLOCATOR | |
| 5 | + select PHYLIB | |
| 6 | + default n | |
| 7 | + help | |
| 8 | + Freescale Data-Path Acceleration Architecture Frame Manager | |
| 9 | + (FMan) support | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +subdir-ccflags-y += -I$(srctree)/drivers/net/ethernet/freescale/fman | |
| 2 | + | |
| 3 | +obj-y += fsl_fman.o fsl_fman_mac.o fsl_mac.o | |
| 4 | + | |
| 5 | +fsl_fman-objs := fman_muram.o fman.o fman_sp.o fman_port.o | |
| 6 | +fsl_fman_mac-objs := fman_dtsec.o fman_memac.o fman_tgec.o | |
| 7 | +fsl_mac-objs += mac.o | |
| @@ -0,0 +1,2871 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2008-2015 Freescale Semiconductor Inc. | |
| 3 | + * | |
| 4 | + * Redistribution and use in source and binary forms, with or without | |
| 5 | + * modification, are permitted provided that the following conditions are met: | |
| 6 | + * * Redistributions of source code must retain the above copyright | |
| 7 | + * notice, this list of conditions and the following disclaimer. | |
| 8 | + * * Redistributions in binary form must reproduce the above copyright | |
| 9 | + * notice, this list of conditions and the following disclaimer in the | |
| 10 | + * documentation and/or other materials provided with the distribution. | |
| 11 | + * * Neither the name of Freescale Semiconductor nor the | |
| 12 | + * names of its contributors may be used to endorse or promote products | |
| 13 | + * derived from this software without specific prior written permission. | |
| 14 | + * | |
| 15 | + * | |
| 16 | + * ALTERNATIVELY, this software may be distributed under the terms of the | |
| 17 | + * GNU General Public License ("GPL") as published by the Free Software | |
| 18 | + * Foundation, either version 2 of that License or (at your option) any | |
| 19 | + * later version. | |
| 20 | + * | |
| 21 | + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY | |
| 22 | + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
| 23 | + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 24 | + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY | |
| 25 | + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| 26 | + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 27 | + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| 28 | + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
| 30 | + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + */ | |
| 32 | + | |
| 33 | +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
| 34 | + | |
| 35 | +#include "fman.h" | |
| 36 | +#include "fman_muram.h" | |
| 37 | + | |
| 38 | +#include <linux/slab.h> | |
| 39 | +#include <linux/delay.h> | |
| 40 | +#include <linux/module.h> | |
| 41 | +#include <linux/of_platform.h> | |
| 42 | +#include <linux/clk.h> | |
| 43 | +#include <linux/of_address.h> | |
| 44 | +#include <linux/of_irq.h> | |
| 45 | +#include <linux/interrupt.h> | |
| 46 | +#include <linux/libfdt_env.h> | |
| 47 | + | |
| 48 | +/* General defines */ | |
| 49 | +#define FMAN_LIODN_TBL 64 /* size of LIODN table */ | |
| 50 | +#define MAX_NUM_OF_MACS 10 | |
| 51 | +#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 | |
| 52 | +#define BASE_RX_PORTID 0x08 | |
| 53 | +#define BASE_TX_PORTID 0x28 | |
| 54 | + | |
| 55 | +/* Modules registers offsets */ | |
| 56 | +#define BMI_OFFSET 0x00080000 | |
| 57 | +#define QMI_OFFSET 0x00080400 | |
| 58 | +#define DMA_OFFSET 0x000C2000 | |
| 59 | +#define FPM_OFFSET 0x000C3000 | |
| 60 | +#define IMEM_OFFSET 0x000C4000 | |
| 61 | +#define CGP_OFFSET 0x000DB000 | |
| 62 | + | |
| 63 | +/* Exceptions bit map */ | |
| 64 | +#define EX_DMA_BUS_ERROR 0x80000000 | |
| 65 | +#define EX_DMA_READ_ECC 0x40000000 | |
| 66 | +#define EX_DMA_SYSTEM_WRITE_ECC 0x20000000 | |
| 67 | +#define EX_DMA_FM_WRITE_ECC 0x10000000 | |
| 68 | +#define EX_FPM_STALL_ON_TASKS 0x08000000 | |
| 69 | +#define EX_FPM_SINGLE_ECC 0x04000000 | |
| 70 | +#define EX_FPM_DOUBLE_ECC 0x02000000 | |
| 71 | +#define EX_QMI_SINGLE_ECC 0x01000000 | |
| 72 | +#define EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 | |
| 73 | +#define EX_QMI_DOUBLE_ECC 0x00400000 | |
| 74 | +#define EX_BMI_LIST_RAM_ECC 0x00200000 | |
| 75 | +#define EX_BMI_STORAGE_PROFILE_ECC 0x00100000 | |
| 76 | +#define EX_BMI_STATISTICS_RAM_ECC 0x00080000 | |
| 77 | +#define EX_IRAM_ECC 0x00040000 | |
| 78 | +#define EX_MURAM_ECC 0x00020000 | |
| 79 | +#define EX_BMI_DISPATCH_RAM_ECC 0x00010000 | |
| 80 | +#define EX_DMA_SINGLE_PORT_ECC 0x00008000 | |
| 81 | + | |
| 82 | +/* DMA defines */ | |
| 83 | +/* masks */ | |
| 84 | +#define DMA_MODE_BER 0x00200000 | |
| 85 | +#define DMA_MODE_ECC 0x00000020 | |
| 86 | +#define DMA_MODE_SECURE_PROT 0x00000800 | |
| 87 | +#define DMA_MODE_AXI_DBG_MASK 0x0F000000 | |
| 88 | + | |
| 89 | +#define DMA_TRANSFER_PORTID_MASK 0xFF000000 | |
| 90 | +#define DMA_TRANSFER_TNUM_MASK 0x00FF0000 | |
| 91 | +#define DMA_TRANSFER_LIODN_MASK 0x00000FFF | |
| 92 | + | |
| 93 | +#define DMA_STATUS_BUS_ERR 0x08000000 | |
| 94 | +#define DMA_STATUS_READ_ECC 0x04000000 | |
| 95 | +#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 | |
| 96 | +#define DMA_STATUS_FM_WRITE_ECC 0x01000000 | |
| 97 | +#define DMA_STATUS_FM_SPDAT_ECC 0x00080000 | |
| 98 | + | |
| 99 | +#define DMA_MODE_CACHE_OR_SHIFT 30 | |
| 100 | +#define DMA_MODE_AXI_DBG_SHIFT 24 | |
| 101 | +#define DMA_MODE_CEN_SHIFT 13 | |
| 102 | +#define DMA_MODE_CEN_MASK 0x00000007 | |
| 103 | +#define DMA_MODE_DBG_SHIFT 7 | |
| 104 | +#define DMA_MODE_AID_MODE_SHIFT 4 | |
| 105 | + | |
| 106 | +#define DMA_THRESH_COMMQ_SHIFT 24 | |
| 107 | +#define DMA_THRESH_READ_INT_BUF_SHIFT 16 | |
| 108 | +#define DMA_THRESH_READ_INT_BUF_MASK 0x0000003f | |
| 109 | +#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000003f | |
| 110 | + | |
| 111 | +#define DMA_TRANSFER_PORTID_SHIFT 24 | |
| 112 | +#define DMA_TRANSFER_TNUM_SHIFT 16 | |
| 113 | + | |
| 114 | +#define DMA_CAM_SIZEOF_ENTRY 0x40 | |
| 115 | +#define DMA_CAM_UNITS 8 | |
| 116 | + | |
| 117 | +#define DMA_LIODN_SHIFT 16 | |
| 118 | +#define DMA_LIODN_BASE_MASK 0x00000FFF | |
| 119 | + | |
| 120 | +/* FPM defines */ | |
| 121 | +#define FPM_EV_MASK_DOUBLE_ECC 0x80000000 | |
| 122 | +#define FPM_EV_MASK_STALL 0x40000000 | |
| 123 | +#define FPM_EV_MASK_SINGLE_ECC 0x20000000 | |
| 124 | +#define FPM_EV_MASK_RELEASE_FM 0x00010000 | |
| 125 | +#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 | |
| 126 | +#define FPM_EV_MASK_STALL_EN 0x00004000 | |
| 127 | +#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 | |
| 128 | +#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 | |
| 129 | +#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 | |
| 130 | + | |
| 131 | +#define FPM_RAM_MURAM_ECC 0x00008000 | |
| 132 | +#define FPM_RAM_IRAM_ECC 0x00004000 | |
| 133 | +#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 | |
| 134 | +#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 | |
| 135 | +#define FPM_RAM_IRAM_ECC_EN 0x40000000 | |
| 136 | +#define FPM_RAM_RAMS_ECC_EN 0x80000000 | |
| 137 | +#define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000 | |
| 138 | + | |
| 139 | +#define FPM_REV1_MAJOR_MASK 0x0000FF00 | |
| 140 | +#define FPM_REV1_MINOR_MASK 0x000000FF | |
| 141 | + | |
| 142 | +#define FPM_DISP_LIMIT_SHIFT 24 | |
| 143 | + | |
| 144 | +#define FPM_PRT_FM_CTL1 0x00000001 | |
| 145 | +#define FPM_PRT_FM_CTL2 0x00000002 | |
| 146 | +#define FPM_PORT_FM_CTL_PORTID_SHIFT 24 | |
| 147 | +#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 | |
| 148 | + | |
| 149 | +#define FPM_THR1_PRS_SHIFT 24 | |
| 150 | +#define FPM_THR1_KG_SHIFT 16 | |
| 151 | +#define FPM_THR1_PLCR_SHIFT 8 | |
| 152 | +#define FPM_THR1_BMI_SHIFT 0 | |
| 153 | + | |
| 154 | +#define FPM_THR2_QMI_ENQ_SHIFT 24 | |
| 155 | +#define FPM_THR2_QMI_DEQ_SHIFT 0 | |
| 156 | +#define FPM_THR2_FM_CTL1_SHIFT 16 | |
| 157 | +#define FPM_THR2_FM_CTL2_SHIFT 8 | |
| 158 | + | |
| 159 | +#define FPM_EV_MASK_CAT_ERR_SHIFT 1 | |
| 160 | +#define FPM_EV_MASK_DMA_ERR_SHIFT 0 | |
| 161 | + | |
| 162 | +#define FPM_REV1_MAJOR_SHIFT 8 | |
| 163 | + | |
| 164 | +#define FPM_RSTC_FM_RESET 0x80000000 | |
| 165 | +#define FPM_RSTC_MAC0_RESET 0x40000000 | |
| 166 | +#define FPM_RSTC_MAC1_RESET 0x20000000 | |
| 167 | +#define FPM_RSTC_MAC2_RESET 0x10000000 | |
| 168 | +#define FPM_RSTC_MAC3_RESET 0x08000000 | |
| 169 | +#define FPM_RSTC_MAC8_RESET 0x04000000 | |
| 170 | +#define FPM_RSTC_MAC4_RESET 0x02000000 | |
| 171 | +#define FPM_RSTC_MAC5_RESET 0x01000000 | |
| 172 | +#define FPM_RSTC_MAC6_RESET 0x00800000 | |
| 173 | +#define FPM_RSTC_MAC7_RESET 0x00400000 | |
| 174 | +#define FPM_RSTC_MAC9_RESET 0x00200000 | |
| 175 | + | |
| 176 | +#define FPM_TS_INT_SHIFT 16 | |
| 177 | +#define FPM_TS_CTL_EN 0x80000000 | |
| 178 | + | |
| 179 | +/* BMI defines */ | |
| 180 | +#define BMI_INIT_START 0x80000000 | |
| 181 | +#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000 | |
| 182 | +#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 | |
| 183 | +#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 | |
| 184 | +#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 | |
| 185 | +#define BMI_NUM_OF_TASKS_MASK 0x3F000000 | |
| 186 | +#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 | |
| 187 | +#define BMI_NUM_OF_DMAS_MASK 0x00000F00 | |
| 188 | +#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F | |
| 189 | +#define BMI_FIFO_SIZE_MASK 0x000003FF | |
| 190 | +#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 | |
| 191 | +#define BMI_CFG2_DMAS_MASK 0x0000003F | |
| 192 | +#define BMI_CFG2_TASKS_MASK 0x0000003F | |
| 193 | + | |
| 194 | +#define BMI_CFG2_TASKS_SHIFT 16 | |
| 195 | +#define BMI_CFG2_DMAS_SHIFT 0 | |
| 196 | +#define BMI_CFG1_FIFO_SIZE_SHIFT 16 | |
| 197 | +#define BMI_NUM_OF_TASKS_SHIFT 24 | |
| 198 | +#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 | |
| 199 | +#define BMI_NUM_OF_DMAS_SHIFT 8 | |
| 200 | +#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 | |
| 201 | + | |
| 202 | +#define BMI_FIFO_ALIGN 0x100 | |
| 203 | + | |
| 204 | +#define BMI_EXTRA_FIFO_SIZE_SHIFT 16 | |
| 205 | + | |
| 206 | +/* QMI defines */ | |
| 207 | +#define QMI_CFG_ENQ_EN 0x80000000 | |
| 208 | +#define QMI_CFG_DEQ_EN 0x40000000 | |
| 209 | +#define QMI_CFG_EN_COUNTERS 0x10000000 | |
| 210 | +#define QMI_CFG_DEQ_MASK 0x0000003F | |
| 211 | +#define QMI_CFG_ENQ_MASK 0x00003F00 | |
| 212 | +#define QMI_CFG_ENQ_SHIFT 8 | |
| 213 | + | |
| 214 | +#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 | |
| 215 | +#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 | |
| 216 | +#define QMI_INTR_EN_SINGLE_ECC 0x80000000 | |
| 217 | + | |
| 218 | +#define QMI_GS_HALT_NOT_BUSY 0x00000002 | |
| 219 | + | |
| 220 | +/* IRAM defines */ | |
| 221 | +#define IRAM_IADD_AIE 0x80000000 | |
| 222 | +#define IRAM_READY 0x80000000 | |
| 223 | + | |
| 224 | +/* Default values */ | |
| 225 | +#define DEFAULT_CATASTROPHIC_ERR 0 | |
| 226 | +#define DEFAULT_DMA_ERR 0 | |
| 227 | +#define DEFAULT_AID_MODE FMAN_DMA_AID_OUT_TNUM | |
| 228 | +#define DEFAULT_DMA_COMM_Q_LOW 0x2A | |
| 229 | +#define DEFAULT_DMA_COMM_Q_HIGH 0x3F | |
| 230 | +#define DEFAULT_CACHE_OVERRIDE 0 | |
| 231 | +#define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64 | |
| 232 | +#define DEFAULT_DMA_DBG_CNT_MODE 0 | |
| 233 | +#define DEFAULT_DMA_SOS_EMERGENCY 0 | |
| 234 | +#define DEFAULT_DMA_WATCHDOG 0 | |
| 235 | +#define DEFAULT_DISP_LIMIT 0 | |
| 236 | +#define DEFAULT_PRS_DISP_TH 16 | |
| 237 | +#define DEFAULT_PLCR_DISP_TH 16 | |
| 238 | +#define DEFAULT_KG_DISP_TH 16 | |
| 239 | +#define DEFAULT_BMI_DISP_TH 16 | |
| 240 | +#define DEFAULT_QMI_ENQ_DISP_TH 16 | |
| 241 | +#define DEFAULT_QMI_DEQ_DISP_TH 16 | |
| 242 | +#define DEFAULT_FM_CTL1_DISP_TH 16 | |
| 243 | +#define DEFAULT_FM_CTL2_DISP_TH 16 | |
| 244 | + | |
| 245 | +#define DFLT_AXI_DBG_NUM_OF_BEATS 1 | |
| 246 | + | |
| 247 | +#define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf) \ | |
| 248 | + ((dma_thresh_max_buf + 1) / 2) | |
| 249 | +#define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf) \ | |
| 250 | + ((dma_thresh_max_buf + 1) * 3 / 4) | |
| 251 | +#define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf) \ | |
| 252 | + ((dma_thresh_max_buf + 1) / 2) | |
| 253 | +#define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\ | |
| 254 | + ((dma_thresh_max_buf + 1) * 3 / 4) | |
| 255 | + | |
| 256 | +#define DMA_COMM_Q_LOW_FMAN_V3 0x2A | |
| 257 | +#define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq) \ | |
| 258 | + ((dma_thresh_max_commq + 1) / 2) | |
| 259 | +#define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq) \ | |
| 260 | + ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 : \ | |
| 261 | + DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)) | |
| 262 | + | |
| 263 | +#define DMA_COMM_Q_HIGH_FMAN_V3 0x3f | |
| 264 | +#define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq) \ | |
| 265 | + ((dma_thresh_max_commq + 1) * 3 / 4) | |
| 266 | +#define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq) \ | |
| 267 | + ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 : \ | |
| 268 | + DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)) | |
| 269 | + | |
| 270 | +#define TOTAL_NUM_OF_TASKS_FMAN_V3L 59 | |
| 271 | +#define TOTAL_NUM_OF_TASKS_FMAN_V3H 124 | |
| 272 | +#define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks) \ | |
| 273 | + ((major == 6) ? ((minor == 1 || minor == 4) ? \ | |
| 274 | + TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) : \ | |
| 275 | + bmi_max_num_of_tasks) | |
| 276 | + | |
| 277 | +#define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 64 | |
| 278 | +#define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2 32 | |
| 279 | +#define DFLT_DMA_CAM_NUM_OF_ENTRIES(major) \ | |
| 280 | + (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 : \ | |
| 281 | + DMA_CAM_NUM_OF_ENTRIES_FMAN_V2) | |
| 282 | + | |
| 283 | +#define FM_TIMESTAMP_1_USEC_BIT 8 | |
| 284 | + | |
| 285 | +/* Defines used for enabling/disabling FMan interrupts */ | |
| 286 | +#define ERR_INTR_EN_DMA 0x00010000 | |
| 287 | +#define ERR_INTR_EN_FPM 0x80000000 | |
| 288 | +#define ERR_INTR_EN_BMI 0x00800000 | |
| 289 | +#define ERR_INTR_EN_QMI 0x00400000 | |
| 290 | +#define ERR_INTR_EN_MURAM 0x00040000 | |
| 291 | +#define ERR_INTR_EN_MAC0 0x00004000 | |
| 292 | +#define ERR_INTR_EN_MAC1 0x00002000 | |
| 293 | +#define ERR_INTR_EN_MAC2 0x00001000 | |
| 294 | +#define ERR_INTR_EN_MAC3 0x00000800 | |
| 295 | +#define ERR_INTR_EN_MAC4 0x00000400 | |
| 296 | +#define ERR_INTR_EN_MAC5 0x00000200 | |
| 297 | +#define ERR_INTR_EN_MAC6 0x00000100 | |
| 298 | +#define ERR_INTR_EN_MAC7 0x00000080 | |
| 299 | +#define ERR_INTR_EN_MAC8 0x00008000 | |
| 300 | +#define ERR_INTR_EN_MAC9 0x00000040 | |
| 301 | + | |
| 302 | +#define INTR_EN_QMI 0x40000000 | |
| 303 | +#define INTR_EN_MAC0 0x00080000 | |
| 304 | +#define INTR_EN_MAC1 0x00040000 | |
| 305 | +#define INTR_EN_MAC2 0x00020000 | |
| 306 | +#define INTR_EN_MAC3 0x00010000 | |
| 307 | +#define INTR_EN_MAC4 0x00000040 | |
| 308 | +#define INTR_EN_MAC5 0x00000020 | |
| 309 | +#define INTR_EN_MAC6 0x00000008 | |
| 310 | +#define INTR_EN_MAC7 0x00000002 | |
| 311 | +#define INTR_EN_MAC8 0x00200000 | |
| 312 | +#define INTR_EN_MAC9 0x00100000 | |
| 313 | +#define INTR_EN_REV0 0x00008000 | |
| 314 | +#define INTR_EN_REV1 0x00004000 | |
| 315 | +#define INTR_EN_REV2 0x00002000 | |
| 316 | +#define INTR_EN_REV3 0x00001000 | |
| 317 | +#define INTR_EN_TMR 0x01000000 | |
| 318 | + | |
| 319 | +enum fman_dma_aid_mode { | |
| 320 | + FMAN_DMA_AID_OUT_PORT_ID = 0, /* 4 LSB of PORT_ID */ | |
| 321 | + FMAN_DMA_AID_OUT_TNUM /* 4 LSB of TNUM */ | |
| 322 | +}; | |
| 323 | + | |
| 324 | +struct fman_iram_regs { | |
| 325 | + u32 iadd; /* FM IRAM instruction address register */ | |
| 326 | + u32 idata; /* FM IRAM instruction data register */ | |
| 327 | + u32 itcfg; /* FM IRAM timing config register */ | |
| 328 | + u32 iready; /* FM IRAM ready register */ | |
| 329 | +}; | |
| 330 | + | |
| 331 | +struct fman_fpm_regs { | |
| 332 | + u32 fmfp_tnc; /* FPM TNUM Control 0x00 */ | |
| 333 | + u32 fmfp_prc; /* FPM Port_ID FmCtl Association 0x04 */ | |
| 334 | + u32 fmfp_brkc; /* FPM Breakpoint Control 0x08 */ | |
| 335 | + u32 fmfp_mxd; /* FPM Flush Control 0x0c */ | |
| 336 | + u32 fmfp_dist1; /* FPM Dispatch Thresholds1 0x10 */ | |
| 337 | + u32 fmfp_dist2; /* FPM Dispatch Thresholds2 0x14 */ | |
| 338 | + u32 fm_epi; /* FM Error Pending Interrupts 0x18 */ | |
| 339 | + u32 fm_rie; /* FM Error Interrupt Enable 0x1c */ | |
| 340 | + u32 fmfp_fcev[4]; /* FPM FMan-Controller Event 1-4 0x20-0x2f */ | |
| 341 | + u32 res0030[4]; /* res 0x30 - 0x3f */ | |
| 342 | + u32 fmfp_cee[4]; /* PM FMan-Controller Event 1-4 0x40-0x4f */ | |
| 343 | + u32 res0050[4]; /* res 0x50-0x5f */ | |
| 344 | + u32 fmfp_tsc1; /* FPM TimeStamp Control1 0x60 */ | |
| 345 | + u32 fmfp_tsc2; /* FPM TimeStamp Control2 0x64 */ | |
| 346 | + u32 fmfp_tsp; /* FPM Time Stamp 0x68 */ | |
| 347 | + u32 fmfp_tsf; /* FPM Time Stamp Fraction 0x6c */ | |
| 348 | + u32 fm_rcr; /* FM Rams Control 0x70 */ | |
| 349 | + u32 fmfp_extc; /* FPM External Requests Control 0x74 */ | |
| 350 | + u32 fmfp_ext1; /* FPM External Requests Config1 0x78 */ | |
| 351 | + u32 fmfp_ext2; /* FPM External Requests Config2 0x7c */ | |
| 352 | + u32 fmfp_drd[16]; /* FPM Data_Ram Data 0-15 0x80 - 0xbf */ | |
| 353 | + u32 fmfp_dra; /* FPM Data Ram Access 0xc0 */ | |
| 354 | + u32 fm_ip_rev_1; /* FM IP Block Revision 1 0xc4 */ | |
| 355 | + u32 fm_ip_rev_2; /* FM IP Block Revision 2 0xc8 */ | |
| 356 | + u32 fm_rstc; /* FM Reset Command 0xcc */ | |
| 357 | + u32 fm_cld; /* FM Classifier Debug 0xd0 */ | |
| 358 | + u32 fm_npi; /* FM Normal Pending Interrupts 0xd4 */ | |
| 359 | + u32 fmfp_exte; /* FPM External Requests Enable 0xd8 */ | |
| 360 | + u32 fmfp_ee; /* FPM Event&Mask 0xdc */ | |
| 361 | + u32 fmfp_cev[4]; /* FPM CPU Event 1-4 0xe0-0xef */ | |
| 362 | + u32 res00f0[4]; /* res 0xf0-0xff */ | |
| 363 | + u32 fmfp_ps[50]; /* FPM Port Status 0x100-0x1c7 */ | |
| 364 | + u32 res01c8[14]; /* res 0x1c8-0x1ff */ | |
| 365 | + u32 fmfp_clfabc; /* FPM CLFABC 0x200 */ | |
| 366 | + u32 fmfp_clfcc; /* FPM CLFCC 0x204 */ | |
| 367 | + u32 fmfp_clfaval; /* FPM CLFAVAL 0x208 */ | |
| 368 | + u32 fmfp_clfbval; /* FPM CLFBVAL 0x20c */ | |
| 369 | + u32 fmfp_clfcval; /* FPM CLFCVAL 0x210 */ | |
| 370 | + u32 fmfp_clfamsk; /* FPM CLFAMSK 0x214 */ | |
| 371 | + u32 fmfp_clfbmsk; /* FPM CLFBMSK 0x218 */ | |
| 372 | + u32 fmfp_clfcmsk; /* FPM CLFCMSK 0x21c */ | |
| 373 | + u32 fmfp_clfamc; /* FPM CLFAMC 0x220 */ | |
| 374 | + u32 fmfp_clfbmc; /* FPM CLFBMC 0x224 */ | |
| 375 | + u32 fmfp_clfcmc; /* FPM CLFCMC 0x228 */ | |
| 376 | + u32 fmfp_decceh; /* FPM DECCEH 0x22c */ | |
| 377 | + u32 res0230[116]; /* res 0x230 - 0x3ff */ | |
| 378 | + u32 fmfp_ts[128]; /* 0x400: FPM Task Status 0x400 - 0x5ff */ | |
| 379 | + u32 res0600[0x400 - 384]; | |
| 380 | +}; | |
| 381 | + | |
| 382 | +struct fman_bmi_regs { | |
| 383 | + u32 fmbm_init; /* BMI Initialization 0x00 */ | |
| 384 | + u32 fmbm_cfg1; /* BMI Configuration 1 0x04 */ | |
| 385 | + u32 fmbm_cfg2; /* BMI Configuration 2 0x08 */ | |
| 386 | + u32 res000c[5]; /* 0x0c - 0x1f */ | |
| 387 | + u32 fmbm_ievr; /* Interrupt Event Register 0x20 */ | |
| 388 | + u32 fmbm_ier; /* Interrupt Enable Register 0x24 */ | |
| 389 | + u32 fmbm_ifr; /* Interrupt Force Register 0x28 */ | |
| 390 | + u32 res002c[5]; /* 0x2c - 0x3f */ | |
| 391 | + u32 fmbm_arb[8]; /* BMI Arbitration 0x40 - 0x5f */ | |
| 392 | + u32 res0060[12]; /* 0x60 - 0x8f */ | |
| 393 | + u32 fmbm_dtc[3]; /* Debug Trap Counter 0x90 - 0x9b */ | |
| 394 | + u32 res009c; /* 0x9c */ | |
| 395 | + u32 fmbm_dcv[3][4]; /* Debug Compare val 0xa0-0xcf */ | |
| 396 | + u32 fmbm_dcm[3][4]; /* Debug Compare Mask 0xd0-0xff */ | |
| 397 | + u32 fmbm_gde; /* BMI Global Debug Enable 0x100 */ | |
| 398 | + u32 fmbm_pp[63]; /* BMI Port Parameters 0x104 - 0x1ff */ | |
| 399 | + u32 res0200; /* 0x200 */ | |
| 400 | + u32 fmbm_pfs[63]; /* BMI Port FIFO Size 0x204 - 0x2ff */ | |
| 401 | + u32 res0300; /* 0x300 */ | |
| 402 | + u32 fmbm_spliodn[63]; /* Port Partition ID 0x304 - 0x3ff */ | |
| 403 | +}; | |
| 404 | + | |
| 405 | +struct fman_qmi_regs { | |
| 406 | + u32 fmqm_gc; /* General Configuration Register 0x00 */ | |
| 407 | + u32 res0004; /* 0x04 */ | |
| 408 | + u32 fmqm_eie; /* Error Interrupt Event Register 0x08 */ | |
| 409 | + u32 fmqm_eien; /* Error Interrupt Enable Register 0x0c */ | |
| 410 | + u32 fmqm_eif; /* Error Interrupt Force Register 0x10 */ | |
| 411 | + u32 fmqm_ie; /* Interrupt Event Register 0x14 */ | |
| 412 | + u32 fmqm_ien; /* Interrupt Enable Register 0x18 */ | |
| 413 | + u32 fmqm_if; /* Interrupt Force Register 0x1c */ | |
| 414 | + u32 fmqm_gs; /* Global Status Register 0x20 */ | |
| 415 | + u32 fmqm_ts; /* Task Status Register 0x24 */ | |
| 416 | + u32 fmqm_etfc; /* Enqueue Total Frame Counter 0x28 */ | |
| 417 | + u32 fmqm_dtfc; /* Dequeue Total Frame Counter 0x2c */ | |
| 418 | + u32 fmqm_dc0; /* Dequeue Counter 0 0x30 */ | |
| 419 | + u32 fmqm_dc1; /* Dequeue Counter 1 0x34 */ | |
| 420 | + u32 fmqm_dc2; /* Dequeue Counter 2 0x38 */ | |
| 421 | + u32 fmqm_dc3; /* Dequeue Counter 3 0x3c */ | |
| 422 | + u32 fmqm_dfdc; /* Dequeue FQID from Default Counter 0x40 */ | |
| 423 | + u32 fmqm_dfcc; /* Dequeue FQID from Context Counter 0x44 */ | |
| 424 | + u32 fmqm_dffc; /* Dequeue FQID from FD Counter 0x48 */ | |
| 425 | + u32 fmqm_dcc; /* Dequeue Confirm Counter 0x4c */ | |
| 426 | + u32 res0050[7]; /* 0x50 - 0x6b */ | |
| 427 | + u32 fmqm_tapc; /* Tnum Aging Period Control 0x6c */ | |
| 428 | + u32 fmqm_dmcvc; /* Dequeue MAC Command Valid Counter 0x70 */ | |
| 429 | + u32 fmqm_difdcc; /* Dequeue Invalid FD Command Counter 0x74 */ | |
| 430 | + u32 fmqm_da1v; /* Dequeue A1 Valid Counter 0x78 */ | |
| 431 | + u32 res007c; /* 0x7c */ | |
| 432 | + u32 fmqm_dtc; /* 0x80 Debug Trap Counter 0x80 */ | |
| 433 | + u32 fmqm_efddd; /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */ | |
| 434 | + u32 res0088[2]; /* 0x88 - 0x8f */ | |
| 435 | + struct { | |
| 436 | + u32 fmqm_dtcfg1; /* 0x90 dbg trap cfg 1 Register 0x00 */ | |
| 437 | + u32 fmqm_dtval1; /* Debug Trap Value 1 Register 0x04 */ | |
| 438 | + u32 fmqm_dtm1; /* Debug Trap Mask 1 Register 0x08 */ | |
| 439 | + u32 fmqm_dtc1; /* Debug Trap Counter 1 Register 0x0c */ | |
| 440 | + u32 fmqm_dtcfg2; /* dbg Trap cfg 2 Register 0x10 */ | |
| 441 | + u32 fmqm_dtval2; /* Debug Trap Value 2 Register 0x14 */ | |
| 442 | + u32 fmqm_dtm2; /* Debug Trap Mask 2 Register 0x18 */ | |
| 443 | + u32 res001c; /* 0x1c */ | |
| 444 | + } dbg_traps[3]; /* 0x90 - 0xef */ | |
| 445 | + u8 res00f0[0x400 - 0xf0]; /* 0xf0 - 0x3ff */ | |
| 446 | +}; | |
| 447 | + | |
| 448 | +struct fman_dma_regs { | |
| 449 | + u32 fmdmsr; /* FM DMA status register 0x00 */ | |
| 450 | + u32 fmdmmr; /* FM DMA mode register 0x04 */ | |
| 451 | + u32 fmdmtr; /* FM DMA bus threshold register 0x08 */ | |
| 452 | + u32 fmdmhy; /* FM DMA bus hysteresis register 0x0c */ | |
| 453 | + u32 fmdmsetr; /* FM DMA SOS emergency Threshold Register 0x10 */ | |
| 454 | + u32 fmdmtah; /* FM DMA transfer bus address high reg 0x14 */ | |
| 455 | + u32 fmdmtal; /* FM DMA transfer bus address low reg 0x18 */ | |
| 456 | + u32 fmdmtcid; /* FM DMA transfer bus communication ID reg 0x1c */ | |
| 457 | + u32 fmdmra; /* FM DMA bus internal ram address register 0x20 */ | |
| 458 | + u32 fmdmrd; /* FM DMA bus internal ram data register 0x24 */ | |
| 459 | + u32 fmdmwcr; /* FM DMA CAM watchdog counter value 0x28 */ | |
| 460 | + u32 fmdmebcr; /* FM DMA CAM base in MURAM register 0x2c */ | |
| 461 | + u32 fmdmccqdr; /* FM DMA CAM and CMD Queue Debug reg 0x30 */ | |
| 462 | + u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */ | |
| 463 | + u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */ | |
| 464 | + u32 fmdmcqvr3; /* FM DMA CMD Queue Value register #3 0x3c */ | |
| 465 | + u32 fmdmcqvr4; /* FM DMA CMD Queue Value register #4 0x40 */ | |
| 466 | + u32 fmdmcqvr5; /* FM DMA CMD Queue Value register #5 0x44 */ | |
| 467 | + u32 fmdmsefrc; /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */ | |
| 468 | + u32 fmdmsqfrc; /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */ | |
| 469 | + u32 fmdmssrc; /* FM DMA Semaphore SYNC Reject Counter 0x50 */ | |
| 470 | + u32 fmdmdcr; /* FM DMA Debug Counter 0x54 */ | |
| 471 | + u32 fmdmemsr; /* FM DMA Emergency Smoother Register 0x58 */ | |
| 472 | + u32 res005c; /* 0x5c */ | |
| 473 | + u32 fmdmplr[FMAN_LIODN_TBL / 2]; /* DMA LIODN regs 0x60-0xdf */ | |
| 474 | + u32 res00e0[0x400 - 56]; | |
| 475 | +}; | |
| 476 | + | |
| 477 | +/* Structure that holds current FMan state. | |
| 478 | + * Used for saving run time information. | |
| 479 | + */ | |
| 480 | +struct fman_state_struct { | |
| 481 | + u8 fm_id; | |
| 482 | + u16 fm_clk_freq; | |
| 483 | + struct fman_rev_info rev_info; | |
| 484 | + bool enabled_time_stamp; | |
| 485 | + u8 count1_micro_bit; | |
| 486 | + u8 total_num_of_tasks; | |
| 487 | + u8 accumulated_num_of_tasks; | |
| 488 | + u32 accumulated_fifo_size; | |
| 489 | + u8 accumulated_num_of_open_dmas; | |
| 490 | + u8 accumulated_num_of_deq_tnums; | |
| 491 | + u32 exceptions; | |
| 492 | + u32 extra_fifo_pool_size; | |
| 493 | + u8 extra_tasks_pool_size; | |
| 494 | + u8 extra_open_dmas_pool_size; | |
| 495 | + u16 port_mfl[MAX_NUM_OF_MACS]; | |
| 496 | + u16 mac_mfl[MAX_NUM_OF_MACS]; | |
| 497 | + | |
| 498 | + /* SOC specific */ | |
| 499 | + u32 fm_iram_size; | |
| 500 | + /* DMA */ | |
| 501 | + u32 dma_thresh_max_commq; | |
| 502 | + u32 dma_thresh_max_buf; | |
| 503 | + u32 max_num_of_open_dmas; | |
| 504 | + /* QMI */ | |
| 505 | + u32 qmi_max_num_of_tnums; | |
| 506 | + u32 qmi_def_tnums_thresh; | |
| 507 | + /* BMI */ | |
| 508 | + u32 bmi_max_num_of_tasks; | |
| 509 | + u32 bmi_max_fifo_size; | |
| 510 | + /* General */ | |
| 511 | + u32 fm_port_num_of_cg; | |
| 512 | + u32 num_of_rx_ports; | |
| 513 | + u32 total_fifo_size; | |
| 514 | + | |
| 515 | + u32 qman_channel_base; | |
| 516 | + u32 num_of_qman_channels; | |
| 517 | + | |
| 518 | + struct resource *res; | |
| 519 | +}; | |
| 520 | + | |
| 521 | +/* Structure that holds FMan initial configuration */ | |
| 522 | +struct fman_cfg { | |
| 523 | + u8 disp_limit_tsh; | |
| 524 | + u8 prs_disp_tsh; | |
| 525 | + u8 plcr_disp_tsh; | |
| 526 | + u8 kg_disp_tsh; | |
| 527 | + u8 bmi_disp_tsh; | |
| 528 | + u8 qmi_enq_disp_tsh; | |
| 529 | + u8 qmi_deq_disp_tsh; | |
| 530 | + u8 fm_ctl1_disp_tsh; | |
| 531 | + u8 fm_ctl2_disp_tsh; | |
| 532 | + int dma_cache_override; | |
| 533 | + enum fman_dma_aid_mode dma_aid_mode; | |
| 534 | + u32 dma_axi_dbg_num_of_beats; | |
| 535 | + u32 dma_cam_num_of_entries; | |
| 536 | + u32 dma_watchdog; | |
| 537 | + u8 dma_comm_qtsh_asrt_emer; | |
| 538 | + u32 dma_write_buf_tsh_asrt_emer; | |
| 539 | + u32 dma_read_buf_tsh_asrt_emer; | |
| 540 | + u8 dma_comm_qtsh_clr_emer; | |
| 541 | + u32 dma_write_buf_tsh_clr_emer; | |
| 542 | + u32 dma_read_buf_tsh_clr_emer; | |
| 543 | + u32 dma_sos_emergency; | |
| 544 | + int dma_dbg_cnt_mode; | |
| 545 | + int catastrophic_err; | |
| 546 | + int dma_err; | |
| 547 | + u32 exceptions; | |
| 548 | + u16 clk_freq; | |
| 549 | + u32 cam_base_addr; | |
| 550 | + u32 fifo_base_addr; | |
| 551 | + u32 total_fifo_size; | |
| 552 | + u32 total_num_of_tasks; | |
| 553 | + u32 qmi_def_tnums_thresh; | |
| 554 | +}; | |
| 555 | + | |
| 556 | +/* Structure that holds information received from device tree */ | |
| 557 | +struct fman_dts_params { | |
| 558 | + void __iomem *base_addr; /* FMan virtual address */ | |
| 559 | + struct resource *res; /* FMan memory resource */ | |
| 560 | + u8 id; /* FMan ID */ | |
| 561 | + | |
| 562 | + int err_irq; /* FMan Error IRQ */ | |
| 563 | + | |
| 564 | + u16 clk_freq; /* FMan clock freq (In Mhz) */ | |
| 565 | + | |
| 566 | + u32 qman_channel_base; /* QMan channels base */ | |
| 567 | + u32 num_of_qman_channels; /* Number of QMan channels */ | |
| 568 | + | |
| 569 | + struct resource muram_res; /* MURAM resource */ | |
| 570 | +}; | |
| 571 | + | |
| 572 | +/** fman_exceptions_cb | |
| 573 | + * fman - Pointer to FMan | |
| 574 | + * exception - The exception. | |
| 575 | + * | |
| 576 | + * Exceptions user callback routine, will be called upon an exception | |
| 577 | + * passing the exception identification. | |
| 578 | + * | |
| 579 | + * Return: irq status | |
| 580 | + */ | |
| 581 | +typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman, | |
| 582 | + enum fman_exceptions exception); | |
| 583 | + | |
| 584 | +/** fman_bus_error_cb | |
| 585 | + * fman - Pointer to FMan | |
| 586 | + * port_id - Port id | |
| 587 | + * addr - Address that caused the error | |
| 588 | + * tnum - Owner of error | |
| 589 | + * liodn - Logical IO device number | |
| 590 | + * | |
| 591 | + * Bus error user callback routine, will be called upon bus error, | |
| 592 | + * passing parameters describing the errors and the owner. | |
| 593 | + * | |
| 594 | + * Return: IRQ status | |
| 595 | + */ | |
| 596 | +typedef irqreturn_t (fman_bus_error_cb)(struct fman *fman, u8 port_id, | |
| 597 | + u64 addr, u8 tnum, u16 liodn); | |
| 598 | + | |
| 599 | +struct fman { | |
| 600 | + struct device *dev; | |
| 601 | + void __iomem *base_addr; | |
| 602 | + struct fman_intr_src intr_mng[FMAN_EV_CNT]; | |
| 603 | + | |
| 604 | + struct fman_fpm_regs __iomem *fpm_regs; | |
| 605 | + struct fman_bmi_regs __iomem *bmi_regs; | |
| 606 | + struct fman_qmi_regs __iomem *qmi_regs; | |
| 607 | + struct fman_dma_regs __iomem *dma_regs; | |
| 608 | + fman_exceptions_cb *exception_cb; | |
| 609 | + fman_bus_error_cb *bus_error_cb; | |
| 610 | + /* Spinlock for FMan use */ | |
| 611 | + spinlock_t spinlock; | |
| 612 | + struct fman_state_struct *state; | |
| 613 | + | |
| 614 | + struct fman_cfg *cfg; | |
| 615 | + struct muram_info *muram; | |
| 616 | + /* cam section in muram */ | |
| 617 | + int cam_offset; | |
| 618 | + size_t cam_size; | |
| 619 | + /* Fifo in MURAM */ | |
| 620 | + int fifo_offset; | |
| 621 | + size_t fifo_size; | |
| 622 | + | |
| 623 | + u32 liodn_base[64]; | |
| 624 | + u32 liodn_offset[64]; | |
| 625 | + | |
| 626 | + struct fman_dts_params dts_params; | |
| 627 | +}; | |
| 628 | + | |
| 629 | +static irqreturn_t fman_exceptions(struct fman *fman, | |
| 630 | + enum fman_exceptions exception) | |
| 631 | +{ | |
| 632 | + dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n", | |
| 633 | + __func__, fman->state->fm_id, exception); | |
| 634 | + | |
| 635 | + return IRQ_HANDLED; | |
| 636 | +} | |
| 637 | + | |
| 638 | +static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id, | |
| 639 | + u64 __maybe_unused addr, | |
| 640 | + u8 __maybe_unused tnum, | |
| 641 | + u16 __maybe_unused liodn) | |
| 642 | +{ | |
| 643 | + dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n", | |
| 644 | + __func__, fman->state->fm_id, port_id); | |
| 645 | + | |
| 646 | + return IRQ_HANDLED; | |
| 647 | +} | |
| 648 | + | |
| 649 | +static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id) | |
| 650 | +{ | |
| 651 | + if (fman->intr_mng[id].isr_cb) { | |
| 652 | + fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle); | |
| 653 | + | |
| 654 | + return IRQ_HANDLED; | |
| 655 | + } | |
| 656 | + | |
| 657 | + return IRQ_NONE; | |
| 658 | +} | |
| 659 | + | |
| 660 | +static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id) | |
| 661 | +{ | |
| 662 | + u8 sw_port_id = 0; | |
| 663 | + | |
| 664 | + if (hw_port_id >= BASE_TX_PORTID) | |
| 665 | + sw_port_id = hw_port_id - BASE_TX_PORTID; | |
| 666 | + else if (hw_port_id >= BASE_RX_PORTID) | |
| 667 | + sw_port_id = hw_port_id - BASE_RX_PORTID; | |
| 668 | + else | |
| 669 | + sw_port_id = 0; | |
| 670 | + | |
| 671 | + return sw_port_id; | |
| 672 | +} | |
| 673 | + | |
| 674 | +static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg, | |
| 675 | + u8 port_id) | |
| 676 | +{ | |
| 677 | + u32 tmp = 0; | |
| 678 | + | |
| 679 | + tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT; | |
| 680 | + | |
| 681 | + tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1; | |
| 682 | + | |
| 683 | + /* order restoration */ | |
| 684 | + if (port_id % 2) | |
| 685 | + tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT; | |
| 686 | + else | |
| 687 | + tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT; | |
| 688 | + | |
| 689 | + iowrite32be(tmp, &fpm_rg->fmfp_prc); | |
| 690 | +} | |
| 691 | + | |
| 692 | +static void set_port_liodn(struct fman *fman, u8 port_id, | |
| 693 | + u32 liodn_base, u32 liodn_ofst) | |
| 694 | +{ | |
| 695 | + u32 tmp; | |
| 696 | + | |
| 697 | + /* set LIODN base for this port */ | |
| 698 | + tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]); | |
| 699 | + if (port_id % 2) { | |
| 700 | + tmp &= ~DMA_LIODN_BASE_MASK; | |
| 701 | + tmp |= liodn_base; | |
| 702 | + } else { | |
| 703 | + tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT); | |
| 704 | + tmp |= liodn_base << DMA_LIODN_SHIFT; | |
| 705 | + } | |
| 706 | + iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]); | |
| 707 | + iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]); | |
| 708 | +} | |
| 709 | + | |
| 710 | +static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg) | |
| 711 | +{ | |
| 712 | + u32 tmp; | |
| 713 | + | |
| 714 | + tmp = ioread32be(&fpm_rg->fm_rcr); | |
| 715 | + if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) | |
| 716 | + iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); | |
| 717 | + else | |
| 718 | + iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN | | |
| 719 | + FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); | |
| 720 | +} | |
| 721 | + | |
| 722 | +static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg) | |
| 723 | +{ | |
| 724 | + u32 tmp; | |
| 725 | + | |
| 726 | + tmp = ioread32be(&fpm_rg->fm_rcr); | |
| 727 | + if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) | |
| 728 | + iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); | |
| 729 | + else | |
| 730 | + iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN), | |
| 731 | + &fpm_rg->fm_rcr); | |
| 732 | +} | |
| 733 | + | |
| 734 | +static void fman_defconfig(struct fman_cfg *cfg) | |
| 735 | +{ | |
| 736 | + memset(cfg, 0, sizeof(struct fman_cfg)); | |
| 737 | + | |
| 738 | + cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR; | |
| 739 | + cfg->dma_err = DEFAULT_DMA_ERR; | |
| 740 | + cfg->dma_aid_mode = DEFAULT_AID_MODE; | |
| 741 | + cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW; | |
| 742 | + cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH; | |
| 743 | + cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE; | |
| 744 | + cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES; | |
| 745 | + cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE; | |
| 746 | + cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY; | |
| 747 | + cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG; | |
| 748 | + cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT; | |
| 749 | + cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH; | |
| 750 | + cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH; | |
| 751 | + cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH; | |
| 752 | + cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH; | |
| 753 | + cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH; | |
| 754 | + cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH; | |
| 755 | + cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH; | |
| 756 | + cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH; | |
| 757 | +} | |
| 758 | + | |
| 759 | +static int dma_init(struct fman *fman) | |
| 760 | +{ | |
| 761 | + struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; | |
| 762 | + struct fman_cfg *cfg = fman->cfg; | |
| 763 | + u32 tmp_reg; | |
| 764 | + | |
| 765 | + /* Init DMA Registers */ | |
| 766 | + | |
| 767 | + /* clear status reg events */ | |
| 768 | + tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC | | |
| 769 | + DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC); | |
| 770 | + iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr); | |
| 771 | + | |
| 772 | + /* configure mode register */ | |
| 773 | + tmp_reg = 0; | |
| 774 | + tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT; | |
| 775 | + if (cfg->exceptions & EX_DMA_BUS_ERROR) | |
| 776 | + tmp_reg |= DMA_MODE_BER; | |
| 777 | + if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) | | |
| 778 | + (cfg->exceptions & EX_DMA_READ_ECC) | | |
| 779 | + (cfg->exceptions & EX_DMA_FM_WRITE_ECC)) | |
| 780 | + tmp_reg |= DMA_MODE_ECC; | |
| 781 | + if (cfg->dma_axi_dbg_num_of_beats) | |
| 782 | + tmp_reg |= (DMA_MODE_AXI_DBG_MASK & | |
| 783 | + ((cfg->dma_axi_dbg_num_of_beats - 1) | |
| 784 | + << DMA_MODE_AXI_DBG_SHIFT)); | |
| 785 | + | |
| 786 | + tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) & | |
| 787 | + DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT; | |
| 788 | + tmp_reg |= DMA_MODE_SECURE_PROT; | |
| 789 | + tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT; | |
| 790 | + tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT; | |
| 791 | + | |
| 792 | + iowrite32be(tmp_reg, &dma_rg->fmdmmr); | |
| 793 | + | |
| 794 | + /* configure thresholds register */ | |
| 795 | + tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer << | |
| 796 | + DMA_THRESH_COMMQ_SHIFT); | |
| 797 | + tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer & | |
| 798 | + DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT; | |
| 799 | + tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer & | |
| 800 | + DMA_THRESH_WRITE_INT_BUF_MASK; | |
| 801 | + | |
| 802 | + iowrite32be(tmp_reg, &dma_rg->fmdmtr); | |
| 803 | + | |
| 804 | + /* configure hysteresis register */ | |
| 805 | + tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer << | |
| 806 | + DMA_THRESH_COMMQ_SHIFT); | |
| 807 | + tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer & | |
| 808 | + DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT; | |
| 809 | + tmp_reg |= cfg->dma_write_buf_tsh_clr_emer & | |
| 810 | + DMA_THRESH_WRITE_INT_BUF_MASK; | |
| 811 | + | |
| 812 | + iowrite32be(tmp_reg, &dma_rg->fmdmhy); | |
| 813 | + | |
| 814 | + /* configure emergency threshold */ | |
| 815 | + iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr); | |
| 816 | + | |
| 817 | + /* configure Watchdog */ | |
| 818 | + iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr); | |
| 819 | + | |
| 820 | + iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr); | |
| 821 | + | |
| 822 | + /* Allocate MURAM for CAM */ | |
| 823 | + fman->cam_size = | |
| 824 | + (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY); | |
| 825 | + fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size); | |
| 826 | + if (IS_ERR_VALUE(fman->cam_offset)) { | |
| 827 | + dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n", | |
| 828 | + __func__); | |
| 829 | + return -ENOMEM; | |
| 830 | + } | |
| 831 | + | |
| 832 | + if (fman->state->rev_info.major == 2) { | |
| 833 | + u32 __iomem *cam_base_addr; | |
| 834 | + | |
| 835 | + fman_muram_free_mem(fman->muram, fman->cam_offset, | |
| 836 | + fman->cam_size); | |
| 837 | + | |
| 838 | + fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128; | |
| 839 | + fman->cam_offset = fman_muram_alloc(fman->muram, | |
| 840 | + fman->cam_size); | |
| 841 | + if (IS_ERR_VALUE(fman->cam_offset)) { | |
| 842 | + dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n", | |
| 843 | + __func__); | |
| 844 | + return -ENOMEM; | |
| 845 | + } | |
| 846 | + | |
| 847 | + if (fman->cfg->dma_cam_num_of_entries % 8 || | |
| 848 | + fman->cfg->dma_cam_num_of_entries > 32) { | |
| 849 | + dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n", | |
| 850 | + __func__); | |
| 851 | + return -EINVAL; | |
| 852 | + } | |
| 853 | + | |
| 854 | + cam_base_addr = (u32 __iomem *) | |
| 855 | + fman_muram_offset_to_vbase(fman->muram, | |
| 856 | + fman->cam_offset); | |
| 857 | + iowrite32be(~((1 << | |
| 858 | + (32 - fman->cfg->dma_cam_num_of_entries)) - 1), | |
| 859 | + cam_base_addr); | |
| 860 | + } | |
| 861 | + | |
| 862 | + fman->cfg->cam_base_addr = fman->cam_offset; | |
| 863 | + | |
| 864 | + return 0; | |
| 865 | +} | |
| 866 | + | |
| 867 | +static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg) | |
| 868 | +{ | |
| 869 | + u32 tmp_reg; | |
| 870 | + int i; | |
| 871 | + | |
| 872 | + /* Init FPM Registers */ | |
| 873 | + | |
| 874 | + tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT); | |
| 875 | + iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd); | |
| 876 | + | |
| 877 | + tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) | | |
| 878 | + ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) | | |
| 879 | + ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) | | |
| 880 | + ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT)); | |
| 881 | + iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1); | |
| 882 | + | |
| 883 | + tmp_reg = | |
| 884 | + (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) | | |
| 885 | + ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) | | |
| 886 | + ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) | | |
| 887 | + ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT)); | |
| 888 | + iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2); | |
| 889 | + | |
| 890 | + /* define exceptions and error behavior */ | |
| 891 | + tmp_reg = 0; | |
| 892 | + /* Clear events */ | |
| 893 | + tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC | | |
| 894 | + FPM_EV_MASK_SINGLE_ECC); | |
| 895 | + /* enable interrupts */ | |
| 896 | + if (cfg->exceptions & EX_FPM_STALL_ON_TASKS) | |
| 897 | + tmp_reg |= FPM_EV_MASK_STALL_EN; | |
| 898 | + if (cfg->exceptions & EX_FPM_SINGLE_ECC) | |
| 899 | + tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN; | |
| 900 | + if (cfg->exceptions & EX_FPM_DOUBLE_ECC) | |
| 901 | + tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN; | |
| 902 | + tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT); | |
| 903 | + tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT); | |
| 904 | + /* FMan is not halted upon external halt activation */ | |
| 905 | + tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT; | |
| 906 | + /* Man is not halted upon Unrecoverable ECC error behavior */ | |
| 907 | + tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT; | |
| 908 | + iowrite32be(tmp_reg, &fpm_rg->fmfp_ee); | |
| 909 | + | |
| 910 | + /* clear all fmCtls event registers */ | |
| 911 | + for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++) | |
| 912 | + iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]); | |
| 913 | + | |
| 914 | + /* RAM ECC - enable and clear events */ | |
| 915 | + /* first we need to clear all parser memory, | |
| 916 | + * as it is uninitialized and may cause ECC errors | |
| 917 | + */ | |
| 918 | + /* event bits */ | |
| 919 | + tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC); | |
| 920 | + | |
| 921 | + iowrite32be(tmp_reg, &fpm_rg->fm_rcr); | |
| 922 | + | |
| 923 | + tmp_reg = 0; | |
| 924 | + if (cfg->exceptions & EX_IRAM_ECC) { | |
| 925 | + tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN; | |
| 926 | + enable_rams_ecc(fpm_rg); | |
| 927 | + } | |
| 928 | + if (cfg->exceptions & EX_MURAM_ECC) { | |
| 929 | + tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN; | |
| 930 | + enable_rams_ecc(fpm_rg); | |
| 931 | + } | |
| 932 | + iowrite32be(tmp_reg, &fpm_rg->fm_rie); | |
| 933 | +} | |
| 934 | + | |
| 935 | +static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg, | |
| 936 | + struct fman_cfg *cfg) | |
| 937 | +{ | |
| 938 | + u32 tmp_reg; | |
| 939 | + | |
| 940 | + /* Init BMI Registers */ | |
| 941 | + | |
| 942 | + /* define common resources */ | |
| 943 | + tmp_reg = cfg->fifo_base_addr; | |
| 944 | + tmp_reg = tmp_reg / BMI_FIFO_ALIGN; | |
| 945 | + | |
| 946 | + tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) << | |
| 947 | + BMI_CFG1_FIFO_SIZE_SHIFT); | |
| 948 | + iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1); | |
| 949 | + | |
| 950 | + tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) << | |
| 951 | + BMI_CFG2_TASKS_SHIFT; | |
| 952 | + /* num of DMA's will be dynamically updated when each port is set */ | |
| 953 | + iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2); | |
| 954 | + | |
| 955 | + /* define unmaskable exceptions, enable and clear events */ | |
| 956 | + tmp_reg = 0; | |
| 957 | + iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC | | |
| 958 | + BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC | | |
| 959 | + BMI_ERR_INTR_EN_STATISTICS_RAM_ECC | | |
| 960 | + BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr); | |
| 961 | + | |
| 962 | + if (cfg->exceptions & EX_BMI_LIST_RAM_ECC) | |
| 963 | + tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC; | |
| 964 | + if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC) | |
| 965 | + tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; | |
| 966 | + if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC) | |
| 967 | + tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; | |
| 968 | + if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC) | |
| 969 | + tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; | |
| 970 | + iowrite32be(tmp_reg, &bmi_rg->fmbm_ier); | |
| 971 | +} | |
| 972 | + | |
| 973 | +static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg, | |
| 974 | + struct fman_cfg *cfg) | |
| 975 | +{ | |
| 976 | + u32 tmp_reg; | |
| 977 | + | |
| 978 | + /* Init QMI Registers */ | |
| 979 | + | |
| 980 | + /* Clear error interrupt events */ | |
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