Pull dmaengine updates from Vinod Koul: "Nothing special, this includes a couple of new device support and new driver support and bunch of driver updates. New support: - Tegra gpcdma driver support - Qualcomm SM8350, Sm8450 and SC7280 device support - Renesas RZN1 dma and platform support Updates: - stm32 device pause/resume support and updates - DMA memset ops Documentation and usage clarification - deprecate '#dma-channels' & '#dma-requests' bindings - driver updates for stm32, ptdma idsx etc" * tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (87 commits) dmaengine: idxd: make idxd_wq_enable() return 0 if wq is already enabled dmaengine: sun6i: Add support for the D1 variant dmaengine: sun6i: Add support for 34-bit physical addresses dmaengine: sun6i: Do not use virt_to_phys dt-bindings: dma: sun50i-a64: Add compatible for D1 dmaengine: tegra: Remove unused switch case dmaengine: tegra: Fix uninitialized variable usage dmaengine: stm32-dma: add device_pause/device_resume support dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done() dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg dmaengine: stm32-dmamux: avoid reset of dmamux if used by coprocessor dmaengine: qcom: gpi: Add support for sc7280 dt-bindings: dma: pl330: Add power-domains dmaengine: stm32-mdma: use dev_dbg on non-busy channel spurious it dmaengine: stm32-mdma: fix chan initialization in stm32_mdma_irq_handler() dmaengine: stm32-mdma: remove GISR1 register dmaengine: ti: deprecate '#dma-channels' dmaengine: mmp: deprecate '#dma-channels' dmaengine: pxa: deprecate '#dma-channels' and '#dma-requests' ...
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| @@ -53,6 +53,11 @@ enum idxd_scmd_stat { · 52 unmodified lines | |||
| 53 | 53 | ||
| 54 | /* IAX */ | 54 | /* IAX */ |
| 55 | #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 | 55 | #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 |
| 56 | #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 | ||
| 57 | #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 | ||
| 58 | #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 | ||
| 59 | #define IDXD_OP_FLAG_SRC2_STS 0x100000 | ||
| 60 | #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 | ||
| 56 | 61 | ||
| 57 | /* Opcode */ | 62 | /* Opcode */ |
| 58 | enum dsa_opcode { | 63 | enum dsa_opcode { |
| @@ -81,6 +86,18 @@ enum iax_opcode { · 22 unmodified lines | |||
| 81 | IAX_OPCODE_MEMMOVE, | 86 | IAX_OPCODE_MEMMOVE, |
| 82 | IAX_OPCODE_DECOMPRESS = 0x42, | 87 | IAX_OPCODE_DECOMPRESS = 0x42, |
| 83 | IAX_OPCODE_COMPRESS, | 88 | IAX_OPCODE_COMPRESS, |
| 89 | IAX_OPCODE_CRC64, | ||
| 90 | IAX_OPCODE_ZERO_DECOMP_32 = 0x48, | ||
| 91 | IAX_OPCODE_ZERO_DECOMP_16, | ||
| 92 | IAX_OPCODE_DECOMP_32 = 0x4c, | ||
| 93 | IAX_OPCODE_DECOMP_16, | ||
| 94 | IAX_OPCODE_SCAN = 0x50, | ||
| 95 | IAX_OPCODE_SET_MEMBER, | ||
| 96 | IAX_OPCODE_EXTRACT, | ||
| 97 | IAX_OPCODE_SELECT, | ||
| 98 | IAX_OPCODE_RLE_BURST, | ||
| 99 | IAX_OPCDE_FIND_UNIQUE, | ||
| 100 | IAX_OPCODE_EXPAND, | ||
| 84 | }; | 101 | }; |
| 85 | 102 | ||
| 86 | /* Completion record status */ | 103 | /* Completion record status */ |
| @@ -120,6 +137,7 @@ enum iax_completion_status { · 33 unmodified lines | |||
| 120 | IAX_COMP_NONE = 0, | 137 | IAX_COMP_NONE = 0, |
| 121 | IAX_COMP_SUCCESS, | 138 | IAX_COMP_SUCCESS, |
| 122 | IAX_COMP_PAGE_FAULT_IR = 0x04, | 139 | IAX_COMP_PAGE_FAULT_IR = 0x04, |
| 140 | IAX_COMP_ANALYTICS_ERROR = 0x0a, | ||
| 123 | IAX_COMP_OUTBUF_OVERFLOW, | 141 | IAX_COMP_OUTBUF_OVERFLOW, |
| 124 | IAX_COMP_BAD_OPCODE = 0x10, | 142 | IAX_COMP_BAD_OPCODE = 0x10, |
| 125 | IAX_COMP_INVALID_FLAGS, | 143 | IAX_COMP_INVALID_FLAGS, |
| @@ -140,7 +158,10 @@ enum iax_completion_status { · 14 unmodified lines | |||
| 140 | IAX_COMP_WATCHDOG, | 158 | IAX_COMP_WATCHDOG, |
| 141 | IAX_COMP_INVALID_COMP_FLAG = 0x30, | 159 | IAX_COMP_INVALID_COMP_FLAG = 0x30, |
| 142 | IAX_COMP_INVALID_FILTER_FLAG, | 160 | IAX_COMP_INVALID_FILTER_FLAG, |
| 143 | IAX_COMP_INVALID_NUM_ELEMS = 0x33, | 161 | IAX_COMP_INVALID_INPUT_SIZE, |
| 162 | IAX_COMP_INVALID_NUM_ELEMS, | ||
| 163 | IAX_COMP_INVALID_SRC1_WIDTH, | ||
| 164 | IAX_COMP_INVALID_INVERT_OUT, | ||
| 144 | }; | 165 | }; |
| 145 | 166 | ||
| 146 | #define DSA_COMP_STATUS_MASK 0x7f | 167 | #define DSA_COMP_STATUS_MASK 0x7f |
| @@ -319,8 +340,12 @@ struct iax_completion_record { · 172 unmodified lines | |||
| 319 | uint32_t output_size; | 340 | uint32_t output_size; |
| 320 | uint8_t output_bits; | 341 | uint8_t output_bits; |
| 321 | uint8_t rsvd3; | 342 | uint8_t rsvd3; |
| 322 | uint16_t rsvd4; | 343 | uint16_t xor_csum; |
| 323 | uint64_t rsvd5[4]; | 344 | uint32_t crc; |
| 345 | uint32_t min; | ||
| 346 | uint32_t max; | ||
| 347 | uint32_t sum; | ||
| 348 | uint64_t rsvd4[2]; | ||
| 324 | } __attribute__((packed)); | 349 | } __attribute__((packed)); |
| 325 | 350 | ||
| 326 | struct iax_raw_completion_record { | 351 | struct iax_raw_completion_record { |