lael-labs/linux

.mailmap+3−0

 Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
 Andrey Ryabinin <ryabinin.a.a@gmail.com> <aryabinin@virtuozzo.com>
 Andrzej Hajda <andrzej.hajda@intel.com> <a.hajda@samsung.com>
+André Almeida <andrealmeid@igalia.com> <andrealmeid@collabora.com>
 Andy Adamson <andros@citi.umich.edu>
 Antoine Tenart <atenart@kernel.org> <antoine.tenart@bootlin.com>
 Antoine Tenart <atenart@kernel.org> <antoine.tenart@free-electrons.com>
 Juha Yrjola <juha.yrjola@nokia.com>
 Juha Yrjola <juha.yrjola@solidboot.com>
 Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
+Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>
 Kalyan Thota <quic_kalyant@quicinc.com> <kalyan_t@codeaurora.org>
 Kay Sievers <kay.sievers@vrfy.org>
 Kees Cook <keescook@chromium.org> <kees.cook@canonical.com>
 Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
 Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
 Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
+Martyna Szapar-Mudlaw <martyna.szapar-mudlaw@linux.intel.com> <martyna.szapar-mudlaw@intel.com>
 Mathieu Othacehe <m.othacehe@gmail.com>
 Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
 Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>

Documentation/arm64/memory-tagging-extension.rst+2−2

@@ -228,10 +228,10 @@ Core dump support · 227 unmodified lines
228	-----------------	228	-----------------
229		229
230	The allocation tags for user memory mapped with ``PROT_MTE`` are dumped	230	The allocation tags for user memory mapped with ``PROT_MTE`` are dumped
231	in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The	231	in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The
232	program header for such segment is defined as:	232	program header for such segment is defined as:
233		233
234	:``p_type``: ``PT_ARM_MEMTAG_MTE``	234	:``p_type``: ``PT_AARCH64_MEMTAG_MTE``
235	:``p_flags``: 0	235	:``p_flags``: 0
236	:``p_offset``: segment file offset	236	:``p_offset``: segment file offset
237	:``p_vaddr``: segment virtual address, same as the corresponding	237	:``p_vaddr``: segment virtual address, same as the corresponding

Documentation/arm64/silicon-errata.rst+3−0

 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1024718       |
 +----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
 +----------------+-----------------+-----------------+-----------------------------+

Documentation/devicetree/bindings/clock/imx8m-clock.yaml+0−4

     then:
       properties:
         clocks:
-          minItems: 7
-          maxItems: 7
           items:
             - description: 32k osc
             - description: 25m osc
             - description: ext3 clock input
             - description: ext4 clock input
         clock-names:
-          minItems: 7
-          maxItems: 7
           items:
             - const: ckil
             - const: osc_25m

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml+11−2

     const: microchip,mpfs-clkcfg
   reg:
-    maxItems: 1
+    items:
+      - description: |
+          clock config registers:
+          These registers contain enable, reset & divider tables for the, cpu,
+          axi, ahb and rtc/mtimer reference clocks as well as enable and reset
+          for the peripheral clocks.
+      - description: |
+          mss pll dri registers:
+          Block of registers responsible for dynamic reconfiguration of the mss
+          pll
   clocks:
     maxItems: 1
             #size-cells = <2>;
             clkcfg: clock-controller@20002000 {
                 compatible = "microchip,mpfs-clkcfg";
-                reg = <0x0 0x20002000 0x0 0x1000>;
+                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
                 clocks = <&ref>;
                 #clock-cells = <1>;
         };

Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml+0−4

   properties:
     clocks:
       minItems: 1
-      maxItems: 4
       items:
         - description: Functional clock
         - description: EXTAL input clock
     clock-names:
       minItems: 1
-      maxItems: 4
       items:
         - const: fck
         # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
 else:
   properties:
     clocks:
-      maxItems: 1
       items:
         - description: Functional clock
     clock-names:
-      maxItems: 1
       items:
         - const: fck

Documentation/devicetree/bindings/display/renesas,du.yaml+0−23

       properties:
         clocks:
           minItems: 1
-          maxItems: 3
           items:
             - description: Functional clock
             - description: DU_DOTCLKIN0 input clock
         clock-names:
           minItems: 1
-          maxItems: 3
           items:
             - const: du.0
             - pattern: '^dclkin\.[01]$'
       properties:
         clocks:
           minItems: 2
-          maxItems: 4
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 2
-          maxItems: 4
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 2
-          maxItems: 4
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 2
-          maxItems: 4
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 2
-          maxItems: 4
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 2
-          maxItems: 4
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 2
-          maxItems: 4
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 2
-          maxItems: 4
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 3
-          maxItems: 6
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 3
-          maxItems: 6
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 4
-          maxItems: 8
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 4
-          maxItems: 8
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 3
-          maxItems: 6
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 3
-          maxItems: 6
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 3
-          maxItems: 6
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 3
-          maxItems: 6
           items:
             - const: du.0
             - const: du.1
       properties:
         clocks:
           minItems: 1
-          maxItems: 2
           items:
             - description: Functional clock for DU0
             - description: DU_DOTCLKIN0 input clock
         clock-names:
           minItems: 1
-          maxItems: 2
           items:
             - const: du.0
             - const: dclkin.0
       properties:
         clocks:
           minItems: 2
-          maxItems: 4
           items:
             - description: Functional clock for DU0
             - description: Functional clock for DU1
         clock-names:
           minItems: 2
-          maxItems: 4
           items:
             - const: du.0
             - const: du.1
             - description: Functional clock
         clock-names:
-          maxItems: 1
           items:
             - const: du.0

Documentation/devicetree/bindings/hwmon/ti,tmp421.yaml+3−4

         description: |
           The value (two's complement) to be programmed in the channel specific N correction register.
           For remote channels only.
-        $ref: /schemas/types.yaml#/definitions/uint32
+        $ref: /schemas/types.yaml#/definitions/int32
-        items:
+        minimum: -128
-          minimum: 0
+        maximum: 127
-          maximum: 255
     required:
       - reg

Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml+0−2

             - const: bus
             - const: adc
           minItems: 1
-          maxItems: 2
         interrupts:
           items:
             - const: bus
             - const: adc
           minItems: 1
-          maxItems: 2
         interrupts:
           items:

Documentation/devicetree/bindings/iommu/arm,smmu.yaml+23−2

               - qcom,sc7180-smmu-500
               - qcom,sc7280-smmu-500
               - qcom,sc8180x-smmu-500
+              - qcom,sc8280xp-smmu-500
               - qcom,sdm845-smmu-500
               - qcom,sdx55-smmu-500
+              - qcom,sdx65-smmu-500
               - qcom,sm6350-smmu-500
               - qcom,sm8150-smmu-500
               - qcom,sm8250-smmu-500
           for improved performance.
         items:
           - enum:
-              - nvidia,tegra194-smmu
               - nvidia,tegra186-smmu
+              - nvidia,tegra194-smmu
+              - nvidia,tegra234-smmu
           - const: nvidia,smmu-500
       - items:
           - const: arm,mmu-500
   power-domains:
     maxItems: 1
+  nvidia,memory-controller:
+    description: |
+      A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
+      The memory controller needs to be programmed with a mapping of memory
+      client IDs to ARM SMMU stream IDs.
+      If this property is absent, the mapping programmed by early firmware
+      will be used and it is not guaranteed that IOMMU translations will be
+      enabled for any given device.
+    $ref: /schemas/types.yaml#/definitions/phandle
 required:
   - compatible
   - reg
         compatible:
           contains:
             enum:
-              - nvidia,tegra194-smmu
               - nvidia,tegra186-smmu
+              - nvidia,tegra194-smmu
+              - nvidia,tegra234-smmu
     then:
       properties:
         reg:
           minItems: 1
           maxItems: 2
+      # The reference to the memory controller is required to ensure that the
+      # memory client to stream ID mapping can be done synchronously with the
+      # IOMMU attachment.
+      required:
+        - nvidia,memory-controller
     else:
       properties:
         reg:

Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml+23−11

           - mediatek,mt8167-m4u  # generation two
           - mediatek,mt8173-m4u  # generation two
           - mediatek,mt8183-m4u  # generation two
+          - mediatek,mt8186-iommu-mm         # generation two
           - mediatek,mt8192-m4u  # generation two
+          - mediatek,mt8195-iommu-vdo        # generation two
+          - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
       - description: mt7623 generation one
         items:
       dt-binding/memory/mt8167-larb-port.h for mt8167,
       dt-binding/memory/mt8173-larb-port.h for mt8173,
       dt-binding/memory/mt8183-larb-port.h for mt8183,
+      dt-binding/memory/mt8186-memory-port.h for mt8186,
       dt-binding/memory/mt8192-larb-port.h for mt8192.
+      dt-binding/memory/mt8195-memory-port.h for mt8195.
   power-domains:
     maxItems: 1
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 allOf:
               - mediatek,mt2701-m4u
               - mediatek,mt2712-m4u
               - mediatek,mt8173-m4u
+              - mediatek,mt8186-iommu-mm
               - mediatek,mt8192-m4u
+              - mediatek,mt8195-iommu-vdo
+              - mediatek,mt8195-iommu-vpp
     then:
       required:
       properties:
         compatible:
           enum:
+            - mediatek,mt8186-iommu-mm
             - mediatek,mt8192-m4u
+            - mediatek,mt8195-iommu-vdo
+            - mediatek,mt8195-iommu-vpp
     then:
       required:
         - power-domains
+  - if: # The IOMMUs don't have larbs.
+      not:
+        properties:
+          compatible:
+            contains:
+              const: mediatek,mt8195-iommu-infra
+    then:
+      required:
+        - mediatek,larbs
 additionalProperties: false
 examples:
                              <&larb3>, <&larb4>, <&larb5>;
             #iommu-cells = <1>;
     };
-  - |
-    #include <dt-bindings/memory/mt8173-larb-port.h>
-    /* Example for a client device */
-    display {
-           compatible = "mediatek,mt8173-disp";
-           iommus = <&iommu M4U_PORT_DISP_OVL0>,
-                    <&iommu M4U_PORT_DISP_RDMA0>;
-     };

Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml+0−10

@@ -86,16 +86,6 @@ examples: · 85 unmodified lines
86	- \|	86	- \|
87	#include <dt-bindings/clock/exynos5250.h>	87	#include <dt-bindings/clock/exynos5250.h>
88		88
89	gsc_0: scaler@13e00000 {
90	compatible = "samsung,exynos5-gsc";
91	reg = <0x13e00000 0x1000>;
92	interrupts = <0 85 0>;
93	power-domains = <&pd_gsc>;
94	clocks = <&clock CLK_GSCL0>;
95	clock-names = "gscl";
96	iommus = <&sysmmu_gsc0>;
97	};
98
99	sysmmu_gsc0: iommu@13e80000 {	89	sysmmu_gsc0: iommu@13e80000 {
100	compatible = "samsung,exynos-sysmmu";	90	compatible = "samsung,exynos-sysmmu";
101	reg = <0x13E80000 0x1000>;	91	reg = <0x13E80000 0x1000>;

Documentation/devicetree/bindings/leds/leds-mt6360.yaml+0−2

@@ -43,8 +43,6 @@ patternProperties: · 42 unmodified lines
43	- 4 # LED output FLASH1	43	- 4 # LED output FLASH1
44	- 5 # LED output FLASH2	44	- 5 # LED output FLASH2
45		45
46	unevaluatedProperties: false
47
48	required:	46	required:
49	- compatible	47	- compatible
50	- "#address-cells"	48	- "#address-cells"

Documentation/devicetree/bindings/mfd/atmel-flexcom.txt+1−1

@@ -54,7 +54,7 @@ flexcom@f8034000 { · 53 unmodified lines
54	clock-names = "spi_clk";	54	clock-names = "spi_clk";
55	atmel,fifo-size = <32>;	55	atmel,fifo-size = <32>;
56		56
57	mtd_dataflash@0 {	57	flash@0 {
58	compatible = "atmel,at25f512b";	58	compatible = "atmel,at25f512b";
59	reg = <0>;	59	reg = <0>;
60	spi-max-frequency = <20000000>;	60	spi-max-frequency = <20000000>;

Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml+1−6

@@ -202,22 +202,17 @@ allOf: · 201 unmodified lines
202	clocks:	202	clocks:
203	items:	203	items:
204	- description: module clock	204	- description: module clock
205	minItems: 1
206	maxItems: 1
207	else:	205	else:
208	properties:	206	properties:
209	clocks:	207	clocks:
210	items:	208	items:
211	- description: module clock	209	- description: module clock
212	- description: timeout clock	210	- description: timeout clock
213	minItems: 2	211
214	maxItems: 2
215	clock-names:	212	clock-names:
216	items:	213	items:
217	- const: sdhci	214	- const: sdhci
218	- const: tmclk	215	- const: tmclk
219	minItems: 2
220	maxItems: 2
221	required:	216	required:
222	- clock-names	217	- clock-names
223		218

Documentation/devicetree/bindings/mtd/gpmi-nand.yaml+0−2

             - description: SoC gpmi io clock
             - description: SoC gpmi bch apb clock
         clock-names:
-          minItems: 2
-          maxItems: 2
           items:
             - const: gpmi_io
             - const: gpmi_bch_apb

Documentation/devicetree/bindings/net/can/bosch,c_can.yaml+0−3

 then:
   properties:
     interrupts:
-      minItems: 4
-      maxItems: 4
       items:
         - description: Error and status IRQ
         - description: Message object IRQ
 else:
   properties:
     interrupts:
-      maxItems: 1
       items:
         - description: Error and status IRQ

Documentation/devicetree/bindings/net/dsa/realtek.yaml+14−21

   The realtek-mdio driver is an MDIO driver and it must be inserted inside
   an MDIO node.
+  The compatible string is only used to identify which (silicon) family the
+  switch belongs to. Roughly speaking, a family is any set of Realtek switches
+  whose chip identification register(s) have a common location and semantics.
+  The different models in a given family can be automatically disambiguated by
+  parsing the chip identification register(s) according to the given family,
+  avoiding the need for a unique compatible string for each model.
 properties:
   compatible:
     enum:
       - realtek,rtl8365mb
-      - realtek,rtl8366
       - realtek,rtl8366rb
-      - realtek,rtl8366s
-      - realtek,rtl8367
-      - realtek,rtl8367b
-      - realtek,rtl8367rb
-      - realtek,rtl8367s
-      - realtek,rtl8368s
-      - realtek,rtl8369
-      - realtek,rtl8370
     description: |
-      realtek,rtl8365mb: 4+1 ports
+      realtek,rtl8365mb:
-      realtek,rtl8366: 5+1 ports
+        Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
-      realtek,rtl8366rb: 5+1 ports
+        RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
-      realtek,rtl8366s: 5+1 ports
+        RTL8367SB, RTL8370MB, RTL8310SR
-      realtek,rtl8367:
+      realtek,rtl8366rb:
-      realtek,rtl8367b:
+        Use with models RTL8366RB, RTL8366S
-      realtek,rtl8367rb: 5+2 ports
-      realtek,rtl8367s: 5+2 ports
-      realtek,rtl8368s: 8 ports
-      realtek,rtl8369: 8+1 ports
-      realtek,rtl8370: 8+2 ports
   mdc-gpios:
     description: GPIO line for the MDC clock line.
             #size-cells = <0>;
             switch@29 {
-                    compatible = "realtek,rtl8367s";
+                    compatible = "realtek,rtl8365mb";
                     reg = <29>;
                     reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;

Documentation/devicetree/bindings/pci/apple,pcie.yaml+0−3

           device_type = "pci";
           reg = <0x0 0x0 0x0 0x0 0x0>;
           reset-gpios = <&pinctrl_ap 152 0>;
-          max-link-speed = <2>;
           #address-cells = <3>;
           #size-cells = <2>;
           device_type = "pci";
           reg = <0x800 0x0 0x0 0x0 0x0>;
           reset-gpios = <&pinctrl_ap 153 0>;
-          max-link-speed = <2>;
           #address-cells = <3>;
           #size-cells = <2>;
           device_type = "pci";
           reg = <0x1000 0x0 0x0 0x0 0x0>;
           reset-gpios = <&pinctrl_ap 33 0>;
-          max-link-speed = <1>;
           #address-cells = <3>;
           #size-cells = <2>;

Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml+4−6

 then:
   properties:
     reg:
-      maxItems: 2
+      minItems: 2
     reg-names:
-      items:
+      minItems: 2
-        - const: "phy"
-        - const: "phy-ctrl"
 else:
   properties:
     reg:
       maxItems: 1
     reg-names:
       maxItems: 1
-      items:
-        - const: "phy"
 required:
   - compatible

Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml+10−2

       hardware supporting it the pull strength in Ohm.
   drive-push-pull:
-    type: boolean
+    oneOf:
+      - type: boolean
+      - $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [ 0, 1 ]
+        deprecated: true
     description: drive actively high and low
   drive-open-drain:
-    type: boolean
+    oneOf:
+      - type: boolean
+      - $ref: /schemas/types.yaml#/definitions/uint32
+        const: 1    # No known cases of 0
+        deprecated: true
     description: drive with open drain
   drive-open-source:

Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml+1−1

@@ -58,7 +58,7 @@ properties: · 57 unmodified lines
58	type: object	58	type: object
59	$ref: regulator.yaml#	59	$ref: regulator.yaml#
60	description: \|	60	description: \|
61	regulator description for buck1 and buck4.	61	regulator description for buck1 to buck4, and ldo.
62		62
63	properties:	63	properties:
64	regulator-allowed-modes:	64	regulator-allowed-modes:

Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml+0−10

     then:
       properties:
         clock-output-names:
-          minItems: 1
           maxItems: 1
   - if:
       properties:
         clock-output-names:
           minItems: 3
-          maxItems: 3
   - if:
       properties:
     then:
       properties:
         clocks:
-          minItems: 3
-          maxItems: 3
           items:
             - description: Bus clock for register access
             - description: 24 MHz oscillator
             - description: 32 kHz clock from the CCU
         clock-names:
-          minItems: 3
-          maxItems: 3
           items:
             - const: bus
             - const: hosc
       properties:
         clocks:
           minItems: 3
-          maxItems: 4
           items:
             - description: Bus clock for register access
             - description: 24 MHz oscillator
         clock-names:
           minItems: 3
-          maxItems: 4
           items:
             - const: bus
             - const: hosc
     then:
       properties:
         interrupts:
-          minItems: 1
           maxItems: 1
     else:
       properties:
         interrupts:
           minItems: 2
-          maxItems: 2
 required:
   - "#clock-cells"

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml+12−3

           to that of the RTC's count register.
   clocks:
-    maxItems: 1
+    items:
+      - description: |
+          AHB clock
+      - description: |
+          Reference clock: divided by the prescaler to create a time-based
+          strobe (typically 1 Hz) for the calendar counter. By default, the rtc
+          on the PolarFire SoC shares it's reference with MTIMER so this will
+          be a 1 MHz clock.
   clock-names:
     items:
       - const: rtc
+      - const: rtcref
 required:
   - compatible
 examples:
   - |
+    #include "dt-bindings/clock/microchip,mpfs-clock.h"
     rtc@20124000 {
         compatible = "microchip,mpfs-rtc";
         reg = <0x20124000 0x1000>;
-        clocks = <&clkcfg 21>;
+        clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
-        clock-names = "rtc";
+        clock-names = "rtc", "rtcref";
         interrupts = <80>, <81>;
     };
 ...

Documentation/devicetree/bindings/serial/samsung_uart.yaml+0−4

           maxItems: 3
         clock-names:
           minItems: 2
-          maxItems: 3
           items:
             - const: uart
             - pattern: '^clk_uart_baud[0-1]$'
     then:
       properties:
         clocks:
-          minItems: 2
           maxItems: 2
         clock-names:
-          minItems: 2
-          maxItems: 2
           items:
             - const: uart
             - const: clk_uart_baud0

Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml+0−1

@@ -89,7 +89,6 @@ allOf: · 88 unmodified lines
89	properties:	89	properties:
90	dmas:	90	dmas:
91	minItems: 1	91	minItems: 1
92	maxItems: 2
93	items:	92	items:
94	- description: RX DMA Channel	93	- description: RX DMA Channel
95	- description: TX DMA Channel	94	- description: TX DMA Channel

Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml+0−2

     then:
       properties:
         clocks:
-          minItems: 6
           items:
             - description: AUXCLK clock for McASP used by CPB audio
             - description: Parent for CPB_McASP auxclk (for 48KHz)
     then:
       properties:
         clocks:
-          maxItems: 4
           items:
             - description: AUXCLK clock for McASP used by CPB audio
             - description: Parent for CPB_McASP auxclk (for 48KHz)

Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml+0−1

@@ -67,7 +67,6 @@ then: · 66 unmodified lines
67	properties:	67	properties:
68	reg:	68	reg:
69	minItems: 2	69	minItems: 2
70	maxItems: 3
71	items:	70	items:
72	- description: TSC1 registers	71	- description: TSC1 registers
73	- description: TSC2 registers	72	- description: TSC2 registers

Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml+3−0

@@ -43,6 +43,9 @@ properties: · 42 unmodified lines
43	- const: phy_clk	43	- const: phy_clk
44	- const: ref_clk	44	- const: ref_clk
45		45
		46	power-domains:
		47	maxItems: 1
		48
46	reg:	49	reg:
47	maxItems: 1	50	maxItems: 1
48		51

Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml+1−0

@@ -62,6 +62,7 @@ required: · 61 unmodified lines
62	- interrupts	62	- interrupts
63	- phys	63	- phys
64	- phy-names	64	- phy-names
		65	- reg
65		66
66	allOf:	67	allOf:
67	- if:	68	- if:

Documentation/filesystems/f2fs.rst+0−70

@@ -235,12 +235,6 @@ offgrpjquota Turn off group journalled quota. · 234 unmodified lines
235	offprjjquota Turn off project journalled quota.	235	offprjjquota Turn off project journalled quota.
236	quota Enable plain user disk quota accounting.	236	quota Enable plain user disk quota accounting.
237	noquota Disable all plain disk quota option.	237	noquota Disable all plain disk quota option.
238	whint_mode=%s Control which write hints are passed down to block
239	layer. This supports "off", "user-based", and
240	"fs-based". In "off" mode (default), f2fs does not pass
241	down hints. In "user-based" mode, f2fs tries to pass
242	down hints given by users. And in "fs-based" mode, f2fs
243	passes down hints with its policy.
244	alloc_mode=%s Adjust block allocation policy, which supports "reuse"	238	alloc_mode=%s Adjust block allocation policy, which supports "reuse"
245	and "default".	239	and "default".
246	fsync_mode=%s Control the policy of fsync. Currently supports "posix",	240	fsync_mode=%s Control the policy of fsync. Currently supports "posix",
@@ -751,70 +745,6 @@ In order to identify whether the data in the victim segment are valid or not, · 504 unmodified lines
751	F2FS manages a bitmap. Each bit represents the validity of a block, and the	745	F2FS manages a bitmap. Each bit represents the validity of a block, and the
752	bitmap is composed of a bit stream covering whole blocks in main area.	746	bitmap is composed of a bit stream covering whole blocks in main area.
753		747
754	Write-hint Policy
755	-----------------
756
757	1) whint_mode=off. F2FS only passes down WRITE_LIFE_NOT_SET.
758
759	2) whint_mode=user-based. F2FS tries to pass down hints given by
760	users.
761
762	===================== ======================== ===================
763	User F2FS Block
764	===================== ======================== ===================
765	N/A META WRITE_LIFE_NOT_SET
766	N/A HOT_NODE "
767	N/A WARM_NODE "
768	N/A COLD_NODE "
769	ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
770	extension list " "
771
772	-- buffered io
773	WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
774	WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
775	WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
776	WRITE_LIFE_NONE " "
777	WRITE_LIFE_MEDIUM " "
778	WRITE_LIFE_LONG " "
779
780	-- direct io
781	WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
782	WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
783	WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
784	WRITE_LIFE_NONE " WRITE_LIFE_NONE
785	WRITE_LIFE_MEDIUM " WRITE_LIFE_MEDIUM
786	WRITE_LIFE_LONG " WRITE_LIFE_LONG
787	===================== ======================== ===================
788
789	3) whint_mode=fs-based. F2FS passes down hints with its policy.
790
791	===================== ======================== ===================
792	User F2FS Block
793	===================== ======================== ===================
794	N/A META WRITE_LIFE_MEDIUM;
795	N/A HOT_NODE WRITE_LIFE_NOT_SET
796	N/A WARM_NODE "
797	N/A COLD_NODE WRITE_LIFE_NONE
798	ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
799	extension list " "
800
801	-- buffered io
802	WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
803	WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
804	WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_LONG
805	WRITE_LIFE_NONE " "
806	WRITE_LIFE_MEDIUM " "
807	WRITE_LIFE_LONG " "
808
809	-- direct io
810	WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
811	WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
812	WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
813	WRITE_LIFE_NONE " WRITE_LIFE_NONE
814	WRITE_LIFE_MEDIUM " WRITE_LIFE_MEDIUM
815	WRITE_LIFE_LONG " WRITE_LIFE_LONG
816	===================== ======================== ===================
817
818	Fallocate(2) Policy	748	Fallocate(2) Policy
819	-------------------	749	-------------------
820		750

Documentation/process/embargoed-hardware-issues.rst+4−3

 an involved disclosed party. The current ambassadors list:
   ============= ========================================================
-  ARM           Grant Likely <grant.likely@arm.com>
   AMD		Tom Lendacky <tom.lendacky@amd.com>
-  IBM Z         Christian Borntraeger <borntraeger@de.ibm.com>
+  Ampere	Darren Hart <darren@os.amperecomputing.com>
-  IBM Power     Anton Blanchard <anton@linux.ibm.com>
+  ARM		Catalin Marinas <catalin.marinas@arm.com>
+  IBM Power	Anton Blanchard <anton@linux.ibm.com>
+  IBM Z		Christian Borntraeger <borntraeger@de.ibm.com>
   Intel		Tony Luck <tony.luck@intel.com>
   Qualcomm	Trilok Soni <tsoni@codeaurora.org>

Documentation/security/siphash.rst+28−18

@@ -121,26 +121,36 @@ even scarier, uses an easily brute-forcable 64-bit key (with a 32-bit output) · 120 unmodified lines
121	instead of SipHash's 128-bit key. However, this may appeal to some	121	instead of SipHash's 128-bit key. However, this may appeal to some
122	high-performance `jhash` users.	122	high-performance `jhash` users.
123		123
124	Danger!	124	HalfSipHash support is provided through the "hsiphash" family of functions.
125		125
126	Do not ever use HalfSipHash except for as a hashtable key function, and only	126	.. warning::
127	then when you can be absolutely certain that the outputs will never be	127	Do not ever use the hsiphash functions except for as a hashtable key
128	transmitted out of the kernel. This is only remotely useful over `jhash` as a	128	function, and only then when you can be absolutely certain that the outputs
129	means of mitigating hashtable flooding denial of service attacks.	129	will never be transmitted out of the kernel. This is only remotely useful
130		130	over `jhash` as a means of mitigating hashtable flooding denial of service
131	Generating a HalfSipHash key	131	attacks.
132	============================	132
		133	On 64-bit kernels, the hsiphash functions actually implement SipHash-1-3, a
		134	reduced-round variant of SipHash, instead of HalfSipHash-1-3. This is because in
		135	64-bit code, SipHash-1-3 is no slower than HalfSipHash-1-3, and can be faster.
		136	Note, this does not mean that in 64-bit kernels the hsiphash functions are the
		137	same as the siphash ones, or that they are secure; the hsiphash functions still
		138	use a less secure reduced-round algorithm and truncate their outputs to 32
		139	bits.
		140
		141	Generating a hsiphash key
		142	=========================
133		143
134	Keys should always be generated from a cryptographically secure source of	144	Keys should always be generated from a cryptographically secure source of
135	random numbers, either using get_random_bytes or get_random_once:	145	random numbers, either using get_random_bytes or get_random_once::
136		146
137	hsiphash_key_t key;	147	hsiphash_key_t key;
138	get_random_bytes(&key, sizeof(key));	148	get_random_bytes(&key, sizeof(key));
139		149
140	If you're not deriving your key from here, you're doing it wrong.	150	If you're not deriving your key from here, you're doing it wrong.
141		151
142	Using the HalfSipHash functions	152	Using the hsiphash functions
143	===============================	153	============================
144		154
145	There are two variants of the function, one that takes a list of integers, and	155	There are two variants of the function, one that takes a list of integers, and
146	one that takes a buffer::	156	one that takes a buffer::
@@ -183,7 +193,7 @@ You may then iterate like usual over the returned hash bucket. · 36 unmodified lines
183	Performance	193	Performance
184	===========	194	===========
185		195
186	HalfSipHash is roughly 3 times slower than JenkinsHash. For many replacements,	196	hsiphash() is roughly 3 times slower than jhash(). For many replacements, this
187	this will not be a problem, as the hashtable lookup isn't the bottleneck. And	197	will not be a problem, as the hashtable lookup isn't the bottleneck. And in
188	in general, this is probably a good sacrifice to make for the security and DoS	198	general, this is probably a good sacrifice to make for the security and DoS
189	resistance of HalfSipHash.	199	resistance of hsiphash().

Documentation/virt/kvm/api.rst+17−7

   #define KVM_SYSTEM_EVENT_RESET          2
   #define KVM_SYSTEM_EVENT_CRASH          3
 			__u32 type;
-			__u64 flags;
+                        __u32 ndata;
+                        __u64 data[16];
 		} system_event;
 If exit_reason is KVM_EXIT_SYSTEM_EVENT then the vcpu has triggered
 a system-level event using some architecture specific mechanism (hypercall
 or some special instruction). In case of ARM64, this is triggered using
-HVC instruction based PSCI call from the vcpu. The 'type' field describes
+HVC instruction based PSCI call from the vcpu.
-the system-level event type. The 'flags' field describes architecture
-specific flags for the system-level event.
+The 'type' field describes the system-level event type.
 Valid values for 'type' are:
  - KVM_SYSTEM_EVENT_SHUTDOWN -- the guest has requested a shutdown of the
    to ignore the request, or to gather VM memory core dump and/or
    reset/shutdown of the VM.
-Valid flags are:
+If KVM_CAP_SYSTEM_EVENT_DATA is present, the 'data' field can contain
+architecture specific information for the system-level event.  Only
+the first `ndata` items (possibly zero) of the data array are valid.
- - KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (arm64 only) -- the guest issued
+ - for arm64, data[0] is set to KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 if
-   a SYSTEM_RESET2 call according to v1.1 of the PSCI specification.
+   the guest issued a SYSTEM_RESET2 call according to v1.1 of the PSCI
+   specification.
+ - for RISC-V, data[0] is set to the value of the second argument of the
+   ``sbi_system_reset`` call.
+Previous versions of Linux defined a `flags` member in this struct.  The
+field is now aliased to `data[0]`.  Userspace can assume that it is only
+written if ndata is greater than 0.
 ::

Documentation/vm/page_owner.rst+3−2

    If you want to sort by the page nums of buf, use the ``-m`` parameter.
    The detailed parameters are:
-   fundamental function:
+   fundamental function::
 	Sort:
 		-a		Sort by memory allocation time.
 		-s		Sort by stack trace.
 		-t		Sort by times (default).
-   additional function:
+   additional function::
 	Cull:
 		--cull <rules>
 STANDARD FORMAT SPECIFIERS
 ==========================
+::
 	KEY		LONG		DESCRIPTION
 	p		pid		process ID

MAINTAINERS+36−16

 S:	Maintained
 C:	irc://irc.libera.chat/linux-exynos
 Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
+B:	mailto:linux-samsung-soc@vger.kernel.org
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
 F:	Documentation/arm/samsung/
 F:	Documentation/devicetree/bindings/arm/samsung/
 L:	netdev@vger.kernel.org
 S:	Supported
 W:	http://sourceforge.net/projects/bonding/
+F:	Documentation/networking/bonding.rst
 F:	drivers/net/bonding/
-F:	include/net/bonding.h
+F:	include/net/bond*
 F:	include/uapi/linux/if_bonding.h
 BOSCH SENSORTEC BMA400 ACCELEROMETER IIO DRIVER
 M:	Michael Chan <michael.chan@broadcom.com>
 L:	netdev@vger.kernel.org
 S:	Supported
+F:	drivers/firmware/broadcom/tee_bnxt_fw.c
 F:	drivers/net/ethernet/broadcom/bnxt/
+F:	include/linux/firmware/broadcom/tee_bnxt_fw.h
 BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
 M:	Arend van Spriel <aspriel@gmail.com>
 DATA ACCESS MONITOR
 M:	SeongJae Park <sj@kernel.org>
+L:	damon@lists.linux.dev
 L:	linux-mm@kvack.org
 S:	Maintained
 F:	Documentation/ABI/testing/sysfs-kernel-mm-damon
 R:	Liam Mark <lmark@codeaurora.org>
 R:	Laura Abbott <labbott@redhat.com>
 R:	Brian Starkey <Brian.Starkey@arm.com>
-R:	John Stultz <john.stultz@linaro.org>
+R:	John Stultz <jstultz@google.com>
 L:	linux-media@vger.kernel.org
 L:	dri-devel@lists.freedesktop.org
 L:	linaro-mm-sig@lists.linaro.org (moderated for non-subscribers)
 DRM DRIVERS FOR HISILICON
 M:	Xinliang Liu <xinliang.liu@linaro.org>
 M:	Tian Tao  <tiantao6@hisilicon.com>
-R:	John Stultz <john.stultz@linaro.org>
+R:	John Stultz <jstultz@google.com>
 R:	Xinwei Kong <kong.kongxinwei@hisilicon.com>
 R:	Chen Feng <puck.chen@hisilicon.com>
 L:	dri-devel@lists.freedesktop.org
 F:	drivers/hwmon/f71805f.c
 FADDR2LINE
-M:	Josh Poimboeuf <jpoimboe@redhat.com>
+M:	Josh Poimboeuf <jpoimboe@kernel.org>
 S:	Maintained
 F:	scripts/faddr2line
 R:	Peter Zijlstra <peterz@infradead.org>
 R:	Darren Hart <dvhart@infradead.org>
 R:	Davidlohr Bueso <dave@stgolabs.net>
-R:	André Almeida <andrealmeid@collabora.com>
+R:	André Almeida <andrealmeid@igalia.com>
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git locking/core
 M:	Bartosz Golaszewski <brgl@bgdev.pl>
 L:	linux-gpio@vger.kernel.org
 S:	Maintained
-T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
 F:	Documentation/ABI/obsolete/sysfs-gpio
 F:	Documentation/ABI/testing/gpio-cdev
 F:	Documentation/admin-guide/gpio/
 F:	drivers/net/ethernet/hisilicon/
 HIKEY960 ONBOARD USB GPIO HUB DRIVER
-M:	John Stultz <john.stultz@linaro.org>
+M:	John Stultz <jstultz@google.com>
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 F:	drivers/misc/hisi_hikey_usb.c
 F:	drivers/net/wireless/intel/iwlegacy/
 INTEL WIRELESS WIFI LINK (iwlwifi)
-M:	Luca Coelho <luciano.coelho@intel.com>
+M:	Gregory Greenman <gregory.greenman@intel.com>
 L:	linux-wireless@vger.kernel.org
 S:	Supported
 W:	https://wireless.wiki.kernel.org/en/users/drivers/iwlwifi
 IOMAP FILESYSTEM LIBRARY
 M:	Christoph Hellwig <hch@infradead.org>
 M:	Darrick J. Wong <djwong@kernel.org>
-M:	linux-xfs@vger.kernel.org
-M:	linux-fsdevel@vger.kernel.org
 L:	linux-xfs@vger.kernel.org
 L:	linux-fsdevel@vger.kernel.org
 S:	Supported
 N:	litex
 LIVE PATCHING
-M:	Josh Poimboeuf <jpoimboe@redhat.com>
+M:	Josh Poimboeuf <jpoimboe@kernel.org>
 M:	Jiri Kosina <jikos@kernel.org>
 M:	Miroslav Benes <mbenes@suse.cz>
 M:	Petr Mladek <pmladek@suse.com>
 M:	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
 L:	linux-pm@vger.kernel.org
 S:	Supported
+B:	mailto:linux-samsung-soc@vger.kernel.org
 F:	Documentation/devicetree/bindings/power/supply/maxim,max14577.yaml
 F:	Documentation/devicetree/bindings/power/supply/maxim,max77693.yaml
 F:	drivers/power/supply/max14577_charger.c
 M:	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
 L:	linux-kernel@vger.kernel.org
 S:	Supported
+B:	mailto:linux-samsung-soc@vger.kernel.org
 F:	Documentation/devicetree/bindings/*/maxim,max14577.yaml
 F:	Documentation/devicetree/bindings/*/maxim,max77686.yaml
 F:	Documentation/devicetree/bindings/*/maxim,max77693.yaml
 M:	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
+B:	mailto:krzysztof.kozlowski@linaro.org
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
 F:	Documentation/devicetree/bindings/memory-controllers/
 F:	drivers/memory/
 NETWORKING DRIVERS
 M:	"David S. Miller" <davem@davemloft.net>
+M:	Eric Dumazet <edumazet@google.com>
 M:	Jakub Kicinski <kuba@kernel.org>
 M:	Paolo Abeni <pabeni@redhat.com>
 L:	netdev@vger.kernel.org
 NETWORKING [GENERAL]
 M:	"David S. Miller" <davem@davemloft.net>
+M:	Eric Dumazet <edumazet@google.com>
 M:	Jakub Kicinski <kuba@kernel.org>
 M:	Paolo Abeni <pabeni@redhat.com>
 L:	netdev@vger.kernel.org
 F:	lib/test_objagg.c
 OBJTOOL
-M:	Josh Poimboeuf <jpoimboe@redhat.com>
+M:	Josh Poimboeuf <jpoimboe@kernel.org>
 M:	Peter Zijlstra <peterz@infradead.org>
 S:	Supported
 F:	tools/objtool/
 PERFORMANCE EVENTS TOOLING ARM64
 R:	John Garry <john.garry@huawei.com>
 R:	Will Deacon <will@kernel.org>
-R:	Mathieu Poirier <mathieu.poirier@linaro.org>
+R:	James Clark <james.clark@arm.com>
+R:	Mike Leach <mike.leach@linaro.org>
 R:	Leo Yan <leo.yan@linaro.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
 S:	Maintained
 C:	irc://irc.libera.chat/linux-exynos
 Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
+B:	mailto:linux-samsung-soc@vger.kernel.org
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
 F:	Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml
 F:	drivers/pinctrl/samsung/
 M:	Sylwester Nawrocki <s.nawrocki@samsung.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Supported
+B:	mailto:linux-samsung-soc@vger.kernel.org
 F:	Documentation/devicetree/bindings/sound/samsung*
 F:	sound/soc/samsung/
 L:	linux-kernel@vger.kernel.org
 L:	linux-samsung-soc@vger.kernel.org
 S:	Supported
+B:	mailto:linux-samsung-soc@vger.kernel.org
 F:	Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
 F:	Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml
 F:	Documentation/devicetree/bindings/mfd/samsung,s5m*.yaml
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
-M:	Josh Poimboeuf <jpoimboe@redhat.com>
+M:	Josh Poimboeuf <jpoimboe@kernel.org>
 M:	Jason Baron <jbaron@akamai.com>
 R:	Steven Rostedt <rostedt@goodmis.org>
 R:	Ard Biesheuvel <ardb@kernel.org>
 F:	include/linux/wl12xx.h
 TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
-M:	John Stultz <john.stultz@linaro.org>
+M:	John Stultz <jstultz@google.com>
 M:	Thomas Gleixner <tglx@linutronix.de>
 R:	Stephen Boyd <sboyd@kernel.org>
 L:	linux-kernel@vger.kernel.org
 F:	arch/x86/kernel/apic/x2apic_uv_x.c
 F:	arch/x86/platform/uv/
+X86 STACK UNWINDING
+M:	Josh Poimboeuf <jpoimboe@kernel.org>
+M:	Peter Zijlstra <peterz@infradead.org>
+S:	Supported
+F:	arch/x86/include/asm/unwind*.h
+F:	arch/x86/kernel/dumpstack.c
+F:	arch/x86/kernel/stacktrace.c
+F:	arch/x86/kernel/unwind_*.c
 X86 VDSO
 M:	Andy Lutomirski <luto@kernel.org>
 L:	linux-kernel@vger.kernel.org
 XFS FILESYSTEM
 C:	irc://irc.oftc.net/xfs
 M:	Darrick J. Wong <djwong@kernel.org>
-M:	linux-xfs@vger.kernel.org
 L:	linux-xfs@vger.kernel.org
 S:	Supported
 W:	http://xfs.org/

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 5	2	VERSION = 5
3	PATCHLEVEL = 18	3	PATCHLEVEL = 18
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc4	5	EXTRAVERSION = -rc7
6	NAME = Superb Owl	6	NAME = Superb Owl
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/arm/boot/dts/am33xx-l4.dtsi+2−0

 				compatible = "ti,am3359-tscadc";
 				reg = <0x0 0x1000>;
 				interrupts = <16>;
+				clocks = <&adc_tsc_fck>;
+				clock-names = "fck";
 				status = "disabled";
 				dmas = <&edma 53 0>, <&edma 57 0>;
 				dma-names = "fifo0", "fifo1";

arch/arm/boot/dts/am3517-evm.dts+40−5

@@ -161,6 +161,8 @@ · 160 unmodified lines
161		161
162	/* HS USB Host PHY on PORT 1 */	162	/* HS USB Host PHY on PORT 1 */
163	hsusb1_phy: hsusb1_phy {	163	hsusb1_phy: hsusb1_phy {
		164	pinctrl-names = "default";
		165	pinctrl-0 = <&hsusb1_rst_pins>;
164	compatible = "usb-nop-xceiv";	166	compatible = "usb-nop-xceiv";
165	reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */	167	reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
166	#phy-cells = <0>;	168	#phy-cells = <0>;
@@ -168,7 +170,9 @@ · 1 unmodified line
168	};	170	};
169		171
170	&davinci_emac {	172	&davinci_emac {
171	status = "okay";	173	pinctrl-names = "default";
		174	pinctrl-0 = <&ethernet_pins>;
		175	status = "okay";
172	};	176	};
173		177
174	&davinci_mdio {	178	&davinci_mdio {
@@ -193,6 +197,8 @@ · 18 unmodified lines
193	};	197	};
194		198
195	&i2c2 {	199	&i2c2 {
		200	pinctrl-names = "default";
		201	pinctrl-0 = <&i2c2_pins>;
196	clock-frequency = <400000>;	202	clock-frequency = <400000>;
197	/* User DIP swithes [1:8] / User LEDS [1:2] */	203	/* User DIP swithes [1:8] / User LEDS [1:2] */
198	tca6416: gpio@21 {	204	tca6416: gpio@21 {
@@ -205,6 +211,8 @@ · 6 unmodified lines
205	};	211	};
206		212
207	&i2c3 {	213	&i2c3 {
		214	pinctrl-names = "default";
		215	pinctrl-0 = <&i2c3_pins>;
208	clock-frequency = <400000>;	216	clock-frequency = <400000>;
209	};	217	};
210		218
@@ -223,6 +231,8 @@ · 12 unmodified lines
223	};	231	};
224		232
225	&usbhshost {	233	&usbhshost {
		234	pinctrl-names = "default";
		235	pinctrl-0 = <&hsusb1_pins>;
226	port1-mode = "ehci-phy";	236	port1-mode = "ehci-phy";
227	};	237	};
228		238
@@ -231,8 +241,35 @@ · 2 unmodified lines
231	};	241	};
232		242
233	&omap3_pmx_core {	243	&omap3_pmx_core {
234	pinctrl-names = "default";	244
235	pinctrl-0 = <&hsusb1_rst_pins>;	245	ethernet_pins: pinmux_ethernet_pins {
		246	pinctrl-single,pins = <
		247	OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT \| MUX_MODE0) /* rmii_mdio_data */
		248	OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */
		249	OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* rmii_rxd0 */
		250	OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* rmii_rxd1 */
		251	OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* rmii_crs_dv */
		252	OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* rmii_rxer */
		253	OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* rmii_txd0 */
		254	OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* rmii_txd1 */
		255	OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN \|MUX_MODE0) /* rmii_txen */
		256	OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* rmii_50mhz_clk */
		257	>;
		258	};
		259
		260	i2c2_pins: pinmux_i2c2_pins {
		261	pinctrl-single,pins = <
		262	OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c2_scl */
		263	OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c2_sda */
		264	>;
		265	};
		266
		267	i2c3_pins: pinmux_i2c3_pins {
		268	pinctrl-single,pins = <
		269	OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c3_scl */
		270	OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c3_sda */
		271	>;
		272	};
236		273
237	leds_pins: pinmux_leds_pins {	274	leds_pins: pinmux_leds_pins {
238	pinctrl-single,pins = <	275	pinctrl-single,pins = <
@@ -300,8 +337,6 @@ · 61 unmodified lines
300	};	337	};
301		338
302	&omap3_pmx_core2 {	339	&omap3_pmx_core2 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&hsusb1_pins>;
305		340
306	hsusb1_pins: pinmux_hsusb1_pins {	341	hsusb1_pins: pinmux_hsusb1_pins {
307	pinctrl-single,pins = <	342	pinctrl-single,pins = <

arch/arm/boot/dts/am3517-som.dtsi+9−0

 };
 &i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
 	clock-frequency = <400000>;
 	s35390a: s35390a@30 {
 &omap3_pmx_core {
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c1_scl */
+			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c1_sda */
+		>;
+	};
 	wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4)  /* mmc1_dat7.gpio_129 */

arch/arm/boot/dts/at91-dvk_su60_somc.dtsi+1−1

@@ -44,7 +44,7 @@ · 43 unmodified lines
44	status = "okay";	44	status = "okay";
45		45
46	/* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */	46	/* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */
47	spi-flash@0 {	47	flash@0 {
48	compatible = "mxicy,mx25u4035", "jedec,spi-nor";	48	compatible = "mxicy,mx25u4035", "jedec,spi-nor";
49	spi-max-frequency = <33000000>;	49	spi-max-frequency = <33000000>;
50	reg = <0>;	50	reg = <0>;

arch/arm/boot/dts/at91-kizbox3-hs.dts+1−1

@@ -225,7 +225,7 @@ · 224 unmodified lines
225	pinctrl_pio_io_reset: gpio_io_reset {	225	pinctrl_pio_io_reset: gpio_io_reset {
226	pinmux = <PIN_PB30__GPIO>;	226	pinmux = <PIN_PB30__GPIO>;
227	bias-disable;	227	bias-disable;
228	drive-open-drain;	228	drive-open-drain = <1>;
229	output-low;	229	output-low;
230	};	230	};
231	pinctrl_pio_input: gpio_input {	231	pinctrl_pio_input: gpio_input {

arch/arm/boot/dts/at91-kizbox3_common.dtsi+1−1

@@ -211,7 +211,7 @@ · 210 unmodified lines
211	pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA	211	pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA
212	<PIN_PD13__FLEXCOM4_IO1>; //CLK	212	<PIN_PD13__FLEXCOM4_IO1>; //CLK
213	bias-disable;	213	bias-disable;
214	drive-open-drain;	214	drive-open-drain = <1>;
215	};	215	};
216		216
217	pinctrl_pwm0 {	217	pinctrl_pwm0 {

arch/arm/boot/dts/at91-q5xr5.dts+1−1

@@ -125,7 +125,7 @@ · 124 unmodified lines
125	cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;	125	cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
126	status = "okay";	126	status = "okay";
127		127
128	m25p80@0 {	128	flash@0 {
129	compatible = "jedec,spi-nor";	129	compatible = "jedec,spi-nor";
130	spi-max-frequency = <20000000>;	130	spi-max-frequency = <20000000>;
131	reg = <0>;	131	reg = <0>;

arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi+1−1

@@ -214,7 +214,7 @@ · 213 unmodified lines
214	pinctrl-0 = <&pinctrl_qspi1_default>;	214	pinctrl-0 = <&pinctrl_qspi1_default>;
215	status = "disabled";	215	status = "disabled";
216		216
217	qspi1_flash: spi_flash@0 {	217	qspi1_flash: flash@0 {
218	#address-cells = <1>;	218	#address-cells = <1>;
219	#size-cells = <1>;	219	#size-cells = <1>;
220	compatible = "jedec,spi-nor";	220	compatible = "jedec,spi-nor";

arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts+1−1

@@ -191,7 +191,7 @@ · 190 unmodified lines
191	&qspi1 {	191	&qspi1 {
192	status = "okay";	192	status = "okay";
193		193
194	qspi1_flash: spi_flash@0 {	194	qspi1_flash: flash@0 {
195	status = "okay";	195	status = "okay";
196	};	196	};
197	};	197	};

arch/arm/boot/dts/at91-sama5d2_xplained.dts+1−1

@@ -137,7 +137,7 @@ · 136 unmodified lines
137	pinctrl-0 = <&pinctrl_spi0_default>;	137	pinctrl-0 = <&pinctrl_spi0_default>;
138	status = "okay";	138	status = "okay";
139		139
140	m25p80@0 {	140	flash@0 {
141	compatible = "atmel,at25df321a";	141	compatible = "atmel,at25df321a";
142	reg = <0>;	142	reg = <0>;
143	spi-max-frequency = <50000000>;	143	spi-max-frequency = <50000000>;

arch/arm/boot/dts/at91-sama5d3_xplained.dts+4−4

@@ -57,8 +57,8 @@ · 56 unmodified lines
57	};	57	};
58		58
59	spi0: spi@f0004000 {	59	spi0: spi@f0004000 {
60	pinctrl-names = "default";	60	pinctrl-names = "default", "cs";
61	pinctrl-0 = <&pinctrl_spi0_cs>;	61	pinctrl-1 = <&pinctrl_spi0_cs>;
62	cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;	62	cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
63	status = "okay";	63	status = "okay";
64	};	64	};
@@ -171,8 +171,8 @@ · 106 unmodified lines
171	};	171	};
172		172
173	spi1: spi@f8008000 {	173	spi1: spi@f8008000 {
174	pinctrl-names = "default";	174	pinctrl-names = "default", "cs";
175	pinctrl-0 = <&pinctrl_spi1_cs>;	175	pinctrl-1 = <&pinctrl_spi1_cs>;
176	cs-gpios = <&pioC 25 0>;	176	cs-gpios = <&pioC 25 0>;
177	status = "okay";	177	status = "okay";
178	};	178	};

arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi+1−1

@@ -49,7 +49,7 @@ · 48 unmodified lines
49	cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;	49	cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
50	status = "okay";	50	status = "okay";
51		51
52	m25p80@0 {	52	flash@0 {
53	compatible = "atmel,at25df321a";	53	compatible = "atmel,at25df321a";
54	spi-max-frequency = <50000000>;	54	spi-max-frequency = <50000000>;
55	reg = <0>;	55	reg = <0>;

arch/arm/boot/dts/at91-sama5d4_xplained.dts+3−3

@@ -81,8 +81,8 @@ · 80 unmodified lines
81	};	81	};
82		82
83	spi1: spi@fc018000 {	83	spi1: spi@fc018000 {
84	pinctrl-names = "default";	84	pinctrl-names = "default", "cs";
85	pinctrl-0 = <&pinctrl_spi0_cs>;	85	pinctrl-1 = <&pinctrl_spi1_cs>;
86	cs-gpios = <&pioB 21 0>;	86	cs-gpios = <&pioB 21 0>;
87	status = "okay";	87	status = "okay";
88	};	88	};
@@ -140,7 +140,7 @@ · 51 unmodified lines
140	atmel,pins =	140	atmel,pins =
141	<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;	141	<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
142	};	142	};
143	pinctrl_spi0_cs: spi0_cs_default {	143	pinctrl_spi1_cs: spi1_cs_default {
144	atmel,pins =	144	atmel,pins =
145	<AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;	145	<AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
146	};	146	};

arch/arm/boot/dts/at91-sama5d4ek.dts+1−1

@@ -65,7 +65,7 @@ · 64 unmodified lines
65	spi0: spi@f8010000 {	65	spi0: spi@f8010000 {
66	cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;	66	cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
67	status = "okay";	67	status = "okay";
68	m25p80@0 {	68	flash@0 {
69	compatible = "atmel,at25df321a";	69	compatible = "atmel,at25df321a";
70	spi-max-frequency = <50000000>;	70	spi-max-frequency = <50000000>;
71	reg = <0>;	71	reg = <0>;

arch/arm/boot/dts/at91-sama7g5ek.dts+2−2

@@ -495,7 +495,7 @@ · 494 unmodified lines
495	pinctrl_flx3_default: flx3_default {	495	pinctrl_flx3_default: flx3_default {
496	pinmux = <PIN_PD16__FLEXCOM3_IO0>,	496	pinmux = <PIN_PD16__FLEXCOM3_IO0>,
497	<PIN_PD17__FLEXCOM3_IO1>;	497	<PIN_PD17__FLEXCOM3_IO1>;
498	bias-disable;	498	bias-pull-up;
499	};	499	};
500		500
501	pinctrl_flx4_default: flx4_default {	501	pinctrl_flx4_default: flx4_default {
@@ -655,7 +655,7 @@ · 153 unmodified lines
655	<PIN_PB21__QSPI0_INT>;	655	<PIN_PB21__QSPI0_INT>;
656	bias-disable;	656	bias-disable;
657	slew-rate = <0>;	657	slew-rate = <0>;
658	atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;	658	atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
659	};	659	};
660		660
661	pinctrl_sdmmc0_default: sdmmc0_default {	661	pinctrl_sdmmc0_default: sdmmc0_default {

arch/arm/boot/dts/at91-vinco.dts+1−1

@@ -59,7 +59,7 @@ · 58 unmodified lines
59	spi0: spi@f8010000 {	59	spi0: spi@f8010000 {
60	cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;	60	cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
61	status = "okay";	61	status = "okay";
62	m25p80@0 {	62	flash@0 {
63	compatible = "n25q32b", "jedec,spi-nor";	63	compatible = "n25q32b", "jedec,spi-nor";
64	spi-max-frequency = <50000000>;	64	spi-max-frequency = <50000000>;
65	reg = <0>;	65	reg = <0>;

arch/arm/boot/dts/at91rm9200ek.dts+2−2

@@ -73,7 +73,7 @@ · 72 unmodified lines
73	spi0: spi@fffe0000 {	73	spi0: spi@fffe0000 {
74	status = "okay";	74	status = "okay";
75	cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;	75	cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
76	mtd_dataflash@0 {	76	flash@0 {
77	compatible = "atmel,at45", "atmel,dataflash";	77	compatible = "atmel,at45", "atmel,dataflash";
78	spi-max-frequency = <15000000>;	78	spi-max-frequency = <15000000>;
79	reg = <0>;	79	reg = <0>;
@@ -94,7 +94,7 @@ · 14 unmodified lines
94	status = "okay";	94	status = "okay";
95	};	95	};
96		96
97	nor_flash@10000000 {	97	flash@10000000 {
98	compatible = "cfi-flash";	98	compatible = "cfi-flash";
99	reg = <0x10000000 0x800000>;	99	reg = <0x10000000 0x800000>;
100	linux,mtd-name = "physmap-flash.0";	100	linux,mtd-name = "physmap-flash.0";

arch/arm/boot/dts/at91sam9260ek.dts+1−1

@@ -92,7 +92,7 @@ · 91 unmodified lines
92		92
93	spi0: spi@fffc8000 {	93	spi0: spi@fffc8000 {
94	cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;	94	cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
95	mtd_dataflash@1 {	95	flash@1 {
96	compatible = "atmel,at45", "atmel,dataflash";	96	compatible = "atmel,at45", "atmel,dataflash";
97	spi-max-frequency = <50000000>;	97	spi-max-frequency = <50000000>;
98	reg = <1>;	98	reg = <1>;

arch/arm/boot/dts/at91sam9261ek.dts+1−1

@@ -145,7 +145,7 @@ · 144 unmodified lines
145	cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;	145	cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
146	status = "okay";	146	status = "okay";
147		147
148	mtd_dataflash@0 {	148	flash@0 {
149	compatible = "atmel,at45", "atmel,dataflash";	149	compatible = "atmel,at45", "atmel,dataflash";
150	reg = <0>;	150	reg = <0>;
151	spi-max-frequency = <15000000>;	151	spi-max-frequency = <15000000>;

arch/arm/boot/dts/at91sam9263ek.dts+1−1

@@ -95,7 +95,7 @@ · 94 unmodified lines
95	spi0: spi@fffa4000 {	95	spi0: spi@fffa4000 {
96	status = "okay";	96	status = "okay";
97	cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;	97	cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
98	mtd_dataflash@0 {	98	flash@0 {
99	compatible = "atmel,at45", "atmel,dataflash";	99	compatible = "atmel,at45", "atmel,dataflash";
100	spi-max-frequency = <50000000>;	100	spi-max-frequency = <50000000>;
101	reg = <0>;	101	reg = <0>;

arch/arm/boot/dts/at91sam9g20ek_common.dtsi+44−1

@@ -110,7 +110,7 @@ · 109 unmodified lines
110		110
111	spi0: spi@fffc8000 {	111	spi0: spi@fffc8000 {
112	cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;	112	cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
113	mtd_dataflash@1 {	113	flash@1 {
114	compatible = "atmel,at45", "atmel,dataflash";	114	compatible = "atmel,at45", "atmel,dataflash";
115	spi-max-frequency = <50000000>;	115	spi-max-frequency = <50000000>;
116	reg = <1>;	116	reg = <1>;
@@ -214,11 +214,23 @@ · 97 unmodified lines
214	24c512@50 {	214	24c512@50 {
215	compatible = "atmel,24c512";	215	compatible = "atmel,24c512";
216	reg = <0x50>;	216	reg = <0x50>;
		217	vcc-supply = <&reg_3v3>;
217	};	218	};
218		219
219	wm8731: wm8731@1b {	220	wm8731: wm8731@1b {
220	compatible = "wm8731";	221	compatible = "wm8731";
221	reg = <0x1b>;	222	reg = <0x1b>;
		223
		224	/* PCK0 at 12MHz */
		225	clocks = <&pmc PMC_TYPE_SYSTEM 8>;
		226	clock-names = "mclk";
		227	assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
		228	assigned-clock-rates = <12000000>;
		229
		230	HPVDD-supply = <&vcc_dac>;
		231	AVDD-supply = <&vcc_dac>;
		232	DCVDD-supply = <&reg_3v3>;
		233	DBVDD-supply = <&reg_3v3>;
222	};	234	};
223	};	235	};
224		236
@@ -254,4 +266,35 @@ · 29 unmodified lines
254	atmel,ssc-controller = <&ssc0>;	266	atmel,ssc-controller = <&ssc0>;
255	atmel,audio-codec = <&wm8731>;	267	atmel,audio-codec = <&wm8731>;
256	};	268	};
		269
		270	reg_5v: fixedregulator0 {
		271	compatible = "regulator-fixed";
		272	regulator-name = "5V";
		273	regulator-min-microvolt = <5000000>;
		274	regulator-max-microvolt = <5000000>;
		275	};
		276
		277	reg_3v3: fixedregulator1 {
		278	compatible = "regulator-fixed";
		279	regulator-name = "3V3";
		280	vin-supply = <&reg_5v>;
		281	regulator-min-microvolt = <3300000>;
		282	regulator-max-microvolt = <3300000>;
		283	};
		284
		285	reg_1v: fixedregulator2 {
		286	compatible = "regulator-fixed";
		287	regulator-name = "1V";
		288	vin-supply = <&reg_5v>;
		289	regulator-min-microvolt = <1000000>;
		290	regulator-max-microvolt = <1000000>;
		291	};
		292
		293	vcc_dac: fixedregulator3 {
		294	compatible = "regulator-fixed";
		295	regulator-name = "VCC_DAC";
		296	vin-supply = <&reg_3v3>;
		297	regulator-min-microvolt = <3300000>;
		298	regulator-max-microvolt = <3300000>;
		299	};
257	};	300	};

arch/arm/boot/dts/at91sam9m10g45ek.dts+1−1

@@ -167,7 +167,7 @@ · 166 unmodified lines
167	spi0: spi@fffa4000{	167	spi0: spi@fffa4000{
168	status = "okay";	168	status = "okay";
169	cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;	169	cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
170	mtd_dataflash@0 {	170	flash@0 {
171	compatible = "atmel,at45", "atmel,dataflash";	171	compatible = "atmel,at45", "atmel,dataflash";
172	spi-max-frequency = <13000000>;	172	spi-max-frequency = <13000000>;
173	reg = <0>;	173	reg = <0>;

arch/arm/boot/dts/at91sam9n12ek.dts+1−1

@@ -119,7 +119,7 @@ · 118 unmodified lines
119	spi0: spi@f0000000 {	119	spi0: spi@f0000000 {
120	status = "okay";	120	status = "okay";
121	cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;	121	cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
122	m25p80@0 {	122	flash@0 {
123	compatible = "atmel,at25df321a";	123	compatible = "atmel,at25df321a";
124	spi-max-frequency = <50000000>;	124	spi-max-frequency = <50000000>;
125	reg = <0>;	125	reg = <0>;

arch/arm/boot/dts/at91sam9rlek.dts+1−1

@@ -180,7 +180,7 @@ · 179 unmodified lines
180	spi0: spi@fffcc000 {	180	spi0: spi@fffcc000 {
181	status = "okay";	181	status = "okay";
182	cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;	182	cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;
183	mtd_dataflash@0 {	183	flash@0 {
184	compatible = "atmel,at45", "atmel,dataflash";	184	compatible = "atmel,at45", "atmel,dataflash";
185	spi-max-frequency = <15000000>;	185	spi-max-frequency = <15000000>;
186	reg = <0>;	186	reg = <0>;

arch/arm/boot/dts/at91sam9x5ek.dtsi+1−1

@@ -125,7 +125,7 @@ · 124 unmodified lines
125	cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;	125	cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
126	status = "disabled"; /* conflicts with mmc1 */	126	status = "disabled"; /* conflicts with mmc1 */
127		127
128	m25p80@0 {	128	flash@0 {
129	compatible = "atmel,at25df321a";	129	compatible = "atmel,at25df321a";
130	spi-max-frequency = <50000000>;	130	spi-max-frequency = <50000000>;
131	reg = <0>;	131	reg = <0>;

arch/arm/boot/dts/dra7-l4.dtsi+2−2

 			reg = <0x1d0010 0x4>;
 			reg-names = "sysc";
 			ti,sysc-midle = <SYSC_IDLE_FORCE>,
-					<SYSC_IDLE_NO>,
+					<SYSC_IDLE_NO>;
-					<SYSC_IDLE_SMART>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>;
+			power-domains = <&prm_vpe>;
 			clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
 			clock-names = "fck";
 			#address-cells = <1>;

arch/arm/boot/dts/imx6qdl-apalis.dtsi+8−2

 	codec: sgtl5000@a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
 		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_module_3v3_audio>;
 		VDDIO-supply = <&reg_module_3v3>;
 			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD	0x130b0
 			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS	0x130b0
 			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD	0x130b0
-			/* SGTL5000 sys_mclk */
-			MX6QDL_PAD_GPIO_5__CCM_CLKO1		0x130b0
 		>;
 	};
 		>;
 	};
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_5__CCM_CLKO1	0x130b0
+		>;
+	};
 	pinctrl_spdif: spdifgrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0

arch/arm/boot/dts/imx6ull-colibri.dtsi+1−1

@@ -37,7 +37,7 @@ · 36 unmodified lines
37		37
38	reg_sd1_vmmc: regulator-sd1-vmmc {	38	reg_sd1_vmmc: regulator-sd1-vmmc {
39	compatible = "regulator-gpio";	39	compatible = "regulator-gpio";
40	gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;	40	gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
41	pinctrl-names = "default";	41	pinctrl-names = "default";
42	pinctrl-0 = <&pinctrl_snvs_reg_sd>;	42	pinctrl-0 = <&pinctrl_snvs_reg_sd>;
43	regulator-always-on;	43	regulator-always-on;

arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts+15−0

@@ -11,3 +11,18 @@ · 10 unmodified lines
11	model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";	11	model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
12	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";	12	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
13	};	13	};
		14
		15	&omap3_pmx_core2 {
		16	pinctrl-names = "default";
		17	pinctrl-0 = <&hsusb2_2_pins>;
		18	hsusb2_2_pins: pinmux_hsusb2_2_pins {
		19	pinctrl-single,pins = <
		20	OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT \| MUX_MODE3) /* etk_d10.hsusb2_clk */
		21	OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT \| MUX_MODE3) /* etk_d11.hsusb2_stp */
		22	OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d12.hsusb2_dir */
		23	OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d13.hsusb2_nxt */
		24	OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d14.hsusb2_data0 */
		25	OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d15.hsusb2_data1 */
		26	>;
		27	};
		28	};

arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts+15−0

@@ -11,3 +11,18 @@ · 10 unmodified lines
11	model = "LogicPD Zoom DM3730 SOM-LV Development Kit";	11	model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
12	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";	12	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
13	};	13	};
		14
		15	&omap3_pmx_core2 {
		16	pinctrl-names = "default";
		17	pinctrl-0 = <&hsusb2_2_pins>;
		18	hsusb2_2_pins: pinmux_hsusb2_2_pins {
		19	pinctrl-single,pins = <
		20	OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT \| MUX_MODE3) /* etk_d10.hsusb2_clk */
		21	OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT \| MUX_MODE3) /* etk_d11.hsusb2_stp */
		22	OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d12.hsusb2_dir */
		23	OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d13.hsusb2_nxt */
		24	OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d14.hsusb2_data0 */
		25	OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d15.hsusb2_data1 */
		26	>;
		27	};
		28	};

arch/arm/boot/dts/logicpd-som-lv.dtsi+0−15

@@ -265,21 +265,6 @@ · 264 unmodified lines
265	};	265	};
266	};	266	};
267		267
268	&omap3_pmx_core2 {
269	pinctrl-names = "default";
270	pinctrl-0 = <&hsusb2_2_pins>;
271	hsusb2_2_pins: pinmux_hsusb2_2_pins {
272	pinctrl-single,pins = <
273	OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT \| MUX_MODE3) /* etk_d10.hsusb2_clk */
274	OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT \| MUX_MODE3) /* etk_d11.hsusb2_stp */
275	OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d12.hsusb2_dir */
276	OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d13.hsusb2_nxt */
277	OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d14.hsusb2_data0 */
278	OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN \| MUX_MODE3) /* etk_d15.hsusb2_data1 */
279	>;
280	};
281	};
282
283	&uart2 {	268	&uart2 {
284	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;	269	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
285	pinctrl-names = "default";	270	pinctrl-names = "default";

arch/arm/boot/dts/omap3-gta04.dtsi+2−0

@@ -31,6 +31,8 @@ · 30 unmodified lines
31	aliases {	31	aliases {
32	display0 = &lcd;	32	display0 = &lcd;
33	display1 = &tv0;	33	display1 = &tv0;
		34	/delete-property/ mmc2;
		35	/delete-property/ mmc3;
34	};	36	};
35		37
36	ldo_3v3: fixedregulator {	38	ldo_3v3: fixedregulator {

arch/arm/boot/dts/sama5d3xmb.dtsi+1−1

@@ -26,7 +26,7 @@ · 25 unmodified lines
26	spi0: spi@f0004000 {	26	spi0: spi@f0004000 {
27	dmas = <0>, <0>; /* Do not use DMA for spi0 */	27	dmas = <0>, <0>; /* Do not use DMA for spi0 */
28		28
29	m25p80@0 {	29	flash@0 {
30	compatible = "atmel,at25df321a";	30	compatible = "atmel,at25df321a";
31	spi-max-frequency = <50000000>;	31	spi-max-frequency = <50000000>;
32	reg = <0>;	32	reg = <0>;

arch/arm/boot/dts/sama5d3xmb_cmp.dtsi+1−1

@@ -25,7 +25,7 @@ · 24 unmodified lines
25	spi0: spi@f0004000 {	25	spi0: spi@f0004000 {
26	dmas = <0>, <0>; /* Do not use DMA for spi0 */	26	dmas = <0>, <0>; /* Do not use DMA for spi0 */
27		27
28	m25p80@0 {	28	flash@0 {
29	compatible = "atmel,at25df321a";	29	compatible = "atmel,at25df321a";
30	spi-max-frequency = <50000000>;	30	spi-max-frequency = <50000000>;
31	reg = <0>;	31	reg = <0>;

arch/arm/boot/dts/sama7g5.dtsi+9−9

@@ -601,9 +601,9 @@ · 600 unmodified lines
601	#size-cells = <0>;	601	#size-cells = <0>;
602	clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;	602	clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
603	atmel,fifo-size = <32>;	603	atmel,fifo-size = <32>;
604	dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,	604	dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
605	<&dma0 AT91_XDMAC_DT_PERID(8)>;	605	<&dma0 AT91_XDMAC_DT_PERID(7)>;
606	dma-names = "rx", "tx";	606	dma-names = "tx", "rx";
607	status = "disabled";	607	status = "disabled";
608	};	608	};
609	};	609	};
@@ -786,9 +786,9 @@ · 176 unmodified lines
786	#size-cells = <0>;	786	#size-cells = <0>;
787	clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;	787	clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
788	atmel,fifo-size = <32>;	788	atmel,fifo-size = <32>;
789	dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,	789	dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
790	<&dma0 AT91_XDMAC_DT_PERID(22)>;	790	<&dma0 AT91_XDMAC_DT_PERID(21)>;
791	dma-names = "rx", "tx";	791	dma-names = "tx", "rx";
792	status = "disabled";	792	status = "disabled";
793	};	793	};
794	};	794	};
@@ -810,9 +810,9 @@ · 15 unmodified lines
810	#size-cells = <0>;	810	#size-cells = <0>;
811	clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;	811	clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
812	atmel,fifo-size = <32>;	812	atmel,fifo-size = <32>;
813	dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,	813	dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
814	<&dma0 AT91_XDMAC_DT_PERID(24)>;	814	<&dma0 AT91_XDMAC_DT_PERID(23)>;
815	dma-names = "rx", "tx";	815	dma-names = "tx", "rx";
816	status = "disabled";	816	status = "disabled";
817	};	817	};
818	};	818	};

arch/arm/boot/dts/usb_a9263.dts+1−1

@@ -60,7 +60,7 @@ · 59 unmodified lines
60	spi0: spi@fffa4000 {	60	spi0: spi@fffa4000 {
61	cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;	61	cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
62	status = "okay";	62	status = "okay";
63	mtd_dataflash@0 {	63	flash@0 {
64	compatible = "atmel,at45", "atmel,dataflash";	64	compatible = "atmel,at45", "atmel,dataflash";
65	reg = <0>;	65	reg = <0>;
66	spi-max-frequency = <15000000>;	66	spi-max-frequency = <15000000>;

arch/arm/configs/multi_v7_defconfig+1−0

@@ -673,6 +673,7 @@ CONFIG_VIDEO_STI_DELTA=m · 672 unmodified lines
673	CONFIG_VIDEO_RENESAS_FDP1=m	673	CONFIG_VIDEO_RENESAS_FDP1=m
674	CONFIG_VIDEO_RENESAS_JPU=m	674	CONFIG_VIDEO_RENESAS_JPU=m
675	CONFIG_VIDEO_RENESAS_VSP1=m	675	CONFIG_VIDEO_RENESAS_VSP1=m
		676	CONFIG_VIDEO_TEGRA_VDE=m
676	CONFIG_V4L_TEST_DRIVERS=y	677	CONFIG_V4L_TEST_DRIVERS=y
677	CONFIG_VIDEO_VIVID=m	678	CONFIG_VIDEO_VIVID=m
678	CONFIG_VIDEO_ADV7180=m	679	CONFIG_VIDEO_ADV7180=m

arch/arm/configs/tegra_defconfig+2−1

 CONFIG_NVEC_POWER=y
 CONFIG_NVEC_PAZ00=y
 CONFIG_STAGING_MEDIA=y
-CONFIG_TEGRA_VDE=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_TEGRA_VDE=y
 CONFIG_CHROME_PLATFORMS=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_I2C=m

arch/arm/include/asm/io.h+3−0

 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
+					unsigned long flags);
+#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
 #endif
 /*

arch/arm/mach-exynos/Kconfig+0−1

@@ -17,7 +17,6 @@ menuconfig ARCH_EXYNOS · 16 unmodified lines
17	select EXYNOS_PMU	17	select EXYNOS_PMU
18	select EXYNOS_SROM	18	select EXYNOS_SROM
19	select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS	19	select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
20	select GPIOLIB
21	select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5	20	select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
22	select HAVE_ARM_SCU if SMP	21	select HAVE_ARM_SCU if SMP
23	select PINCTRL	22	select PINCTRL

arch/arm/mach-omap2/omap4-common.c+2−0

 	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
 	gic_dist_base_addr = of_iomap(np, 0);
+	of_node_put(np);
 	WARN_ON(!gic_dist_base_addr);
 	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
 	twd_base = of_iomap(np, 0);
+	of_node_put(np);
 	WARN_ON(!twd_base);
 skip_errata_init:

arch/arm/mm/ioremap.c+8−0

@@ -493,3 +493,11 @@ void __init early_ioremap_init(void) · 492 unmodified lines
493	{	493	{
494	early_ioremap_setup();	494	early_ioremap_setup();
495	}	495	}
		496
		497	bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
		498	unsigned long flags)
		499	{
		500	unsigned long pfn = PHYS_PFN(offset);
		501
		502	return memblock_is_map_memory(pfn);
		503	}

arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi+0−40

@@ -11,26 +11,6 @@ · 10 unmodified lines
11	compatible = "operating-points-v2";	11	compatible = "operating-points-v2";
12	opp-shared;	12	opp-shared;
13		13
14	opp-100000000 {
15	opp-hz = /bits/ 64 <100000000>;
16	opp-microvolt = <731000>;
17	};
18
19	opp-250000000 {
20	opp-hz = /bits/ 64 <250000000>;
21	opp-microvolt = <731000>;
22	};
23
24	opp-500000000 {
25	opp-hz = /bits/ 64 <500000000>;
26	opp-microvolt = <731000>;
27	};
28
29	opp-667000000 {
30	opp-hz = /bits/ 64 <667000000>;
31	opp-microvolt = <731000>;
32	};
33
34	opp-1000000000 {	14	opp-1000000000 {
35	opp-hz = /bits/ 64 <1000000000>;	15	opp-hz = /bits/ 64 <1000000000>;
36	opp-microvolt = <761000>;	16	opp-microvolt = <761000>;
@@ -71,26 +51,6 @@ · 34 unmodified lines
71	compatible = "operating-points-v2";	51	compatible = "operating-points-v2";
72	opp-shared;	52	opp-shared;
73		53
74	opp-100000000 {
75	opp-hz = /bits/ 64 <100000000>;
76	opp-microvolt = <731000>;
77	};
78
79	opp-250000000 {
80	opp-hz = /bits/ 64 <250000000>;
81	opp-microvolt = <731000>;
82	};
83
84	opp-500000000 {
85	opp-hz = /bits/ 64 <500000000>;
86	opp-microvolt = <731000>;
87	};
88
89	opp-667000000 {
90	opp-hz = /bits/ 64 <667000000>;
91	opp-microvolt = <731000>;
92	};
93
94	opp-1000000000 {	54	opp-1000000000 {
95	opp-hz = /bits/ 64 <1000000000>;	55	opp-hz = /bits/ 64 <1000000000>;
96	opp-microvolt = <731000>;	56	opp-microvolt = <731000>;

arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi+0−40

@@ -11,26 +11,6 @@ · 10 unmodified lines
11	compatible = "operating-points-v2";	11	compatible = "operating-points-v2";
12	opp-shared;	12	opp-shared;
13		13
14	opp-100000000 {
15	opp-hz = /bits/ 64 <100000000>;
16	opp-microvolt = <731000>;
17	};
18
19	opp-250000000 {
20	opp-hz = /bits/ 64 <250000000>;
21	opp-microvolt = <731000>;
22	};
23
24	opp-500000000 {
25	opp-hz = /bits/ 64 <500000000>;
26	opp-microvolt = <731000>;
27	};
28
29	opp-667000000 {
30	opp-hz = /bits/ 64 <667000000>;
31	opp-microvolt = <731000>;
32	};
33
34	opp-1000000000 {	14	opp-1000000000 {
35	opp-hz = /bits/ 64 <1000000000>;	15	opp-hz = /bits/ 64 <1000000000>;
36	opp-microvolt = <731000>;	16	opp-microvolt = <731000>;
@@ -76,26 +56,6 @@ · 39 unmodified lines
76	compatible = "operating-points-v2";	56	compatible = "operating-points-v2";
77	opp-shared;	57	opp-shared;
78		58
79	opp-100000000 {
80	opp-hz = /bits/ 64 <100000000>;
81	opp-microvolt = <751000>;
82	};
83
84	opp-250000000 {
85	opp-hz = /bits/ 64 <250000000>;
86	opp-microvolt = <751000>;
87	};
88
89	opp-500000000 {
90	opp-hz = /bits/ 64 <500000000>;
91	opp-microvolt = <751000>;
92	};
93
94	opp-667000000 {
95	opp-hz = /bits/ 64 <667000000>;
96	opp-microvolt = <751000>;
97	};
98
99	opp-1000000000 {	59	opp-1000000000 {
100	opp-hz = /bits/ 64 <1000000000>;	60	opp-hz = /bits/ 64 <1000000000>;
101	opp-microvolt = <771000>;	61	opp-microvolt = <771000>;

arch/arm64/boot/dts/amlogic/meson-s4.dtsi+4−4

@@ -13,28 +13,28 @@ · 12 unmodified lines
13		13
14	cpu0: cpu@0 {	14	cpu0: cpu@0 {
15	device_type = "cpu";	15	device_type = "cpu";
16	compatible = "arm,cortex-a35","arm,armv8";	16	compatible = "arm,cortex-a35";
17	reg = <0x0 0x0>;	17	reg = <0x0 0x0>;
18	enable-method = "psci";	18	enable-method = "psci";
19	};	19	};
20		20
21	cpu1: cpu@1 {	21	cpu1: cpu@1 {
22	device_type = "cpu";	22	device_type = "cpu";
23	compatible = "arm,cortex-a35","arm,armv8";	23	compatible = "arm,cortex-a35";
24	reg = <0x0 0x1>;	24	reg = <0x0 0x1>;
25	enable-method = "psci";	25	enable-method = "psci";
26	};	26	};
27		27
28	cpu2: cpu@2 {	28	cpu2: cpu@2 {
29	device_type = "cpu";	29	device_type = "cpu";
30	compatible = "arm,cortex-a35","arm,armv8";	30	compatible = "arm,cortex-a35";
31	reg = <0x0 0x2>;	31	reg = <0x0 0x2>;
32	enable-method = "psci";	32	enable-method = "psci";
33	};	33	};
34		34
35	cpu3: cpu@3 {	35	cpu3: cpu@3 {
36	device_type = "cpu";	36	device_type = "cpu";
37	compatible = "arm,cortex-a35","arm,armv8";	37	compatible = "arm,cortex-a35";
38	reg = <0x0 0x3>;	38	reg = <0x0 0x3>;
39	enable-method = "psci";	39	enable-method = "psci";
40	};	40	};

arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts+1−0

@@ -437,6 +437,7 @@ · 436 unmodified lines
437	"",	437	"",
438	"eMMC_RST#", /* BOOT_12 */	438	"eMMC_RST#", /* BOOT_12 */
439	"eMMC_DS", /* BOOT_13 */	439	"eMMC_DS", /* BOOT_13 */
		440	"", "",
440	/* GPIOC */	441	/* GPIOC */
441	"SD_D0_B", /* GPIOC_0 */	442	"SD_D0_B", /* GPIOC_0 */
442	"SD_D1_B", /* GPIOC_1 */	443	"SD_D1_B", /* GPIOC_1 */

arch/arm64/boot/dts/amlogic/meson-sm1.dtsi+0−20

@@ -95,26 +95,6 @@ · 94 unmodified lines
95	compatible = "operating-points-v2";	95	compatible = "operating-points-v2";
96	opp-shared;	96	opp-shared;
97		97
98	opp-100000000 {
99	opp-hz = /bits/ 64 <100000000>;
100	opp-microvolt = <730000>;
101	};
102
103	opp-250000000 {
104	opp-hz = /bits/ 64 <250000000>;
105	opp-microvolt = <730000>;
106	};
107
108	opp-500000000 {
109	opp-hz = /bits/ 64 <500000000>;
110	opp-microvolt = <730000>;
111	};
112
113	opp-667000000 {
114	opp-hz = /bits/ 64 <666666666>;
115	opp-microvolt = <750000>;
116	};
117
118	opp-1000000000 {	98	opp-1000000000 {
119	opp-hz = /bits/ 64 <1000000000>;	99	opp-hz = /bits/ 64 <1000000000>;
120	opp-microvolt = <770000>;	100	opp-microvolt = <770000>;

arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi+3−1

 &usbotg1 {
 	dr_mode = "otg";
+	over-current-active-low;
 	vbus-supply = <&reg_usb_otg1_vbus>;
 	status = "okay";
 };
 &usbotg2 {
 	dr_mode = "host";
+	disable-over-current;
 	status = "okay";
 };
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
 		>;
 	};

arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi+3−1

 &usbotg1 {
 	dr_mode = "otg";
+	over-current-active-low;
 	vbus-supply = <&reg_usb_otg1_vbus>;
 	status = "okay";
 };
 &usbotg2 {
 	dr_mode = "host";
+	disable-over-current;
 	vbus-supply = <&reg_usb_otg2_vbus>;
 	status = "okay";
 };
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
 		>;
 	};

arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi+3−1

 &usbotg1 {
 	dr_mode = "otg";
+	over-current-active-low;
 	vbus-supply = <&reg_usb_otg1_vbus>;
 	status = "okay";
 };
 &usbotg2 {
 	dr_mode = "host";
+	disable-over-current;
 	vbus-supply = <&reg_usb_otg2_vbus>;
 	status = "okay";
 };
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
 		>;
 	};

arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts+4−0

 		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 		rohm,reset-snvs-powered;
+		#clock-cells = <0>;
+		clocks = <&osc_32k 0>;
+		clock-output-names = "clk-32k-out";
 		regulators {
 			buck1_reg: BUCK1 {
 				regulator-name = "buck1";

arch/arm64/boot/dts/freescale/imx8mn.dtsi+5−5

@@ -293,7 +293,7 @@ · 292 unmodified lines
293	ranges;	293	ranges;
294		294
295	sai2: sai@30020000 {	295	sai2: sai@30020000 {
296	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";	296	compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
297	reg = <0x30020000 0x10000>;	297	reg = <0x30020000 0x10000>;
298	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;	298	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
299	clocks = <&clk IMX8MN_CLK_SAI2_IPG>,	299	clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
@@ -307,7 +307,7 @@ · 7 unmodified lines
307	};	307	};
308		308
309	sai3: sai@30030000 {	309	sai3: sai@30030000 {
310	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";	310	compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
311	reg = <0x30030000 0x10000>;	311	reg = <0x30030000 0x10000>;
312	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;	312	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
313	clocks = <&clk IMX8MN_CLK_SAI3_IPG>,	313	clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
@@ -321,7 +321,7 @@ · 7 unmodified lines
321	};	321	};
322		322
323	sai5: sai@30050000 {	323	sai5: sai@30050000 {
324	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";	324	compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
325	reg = <0x30050000 0x10000>;	325	reg = <0x30050000 0x10000>;
326	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;	326	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
327	clocks = <&clk IMX8MN_CLK_SAI5_IPG>,	327	clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
@@ -337,7 +337,7 @@ · 9 unmodified lines
337	};	337	};
338		338
339	sai6: sai@30060000 {	339	sai6: sai@30060000 {
340	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";	340	compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
341	reg = <0x30060000 0x10000>;	341	reg = <0x30060000 0x10000>;
342	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;	342	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
343	clocks = <&clk IMX8MN_CLK_SAI6_IPG>,	343	clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
@@ -394,7 +394,7 @@ · 50 unmodified lines
394	};	394	};
395		395
396	sai7: sai@300b0000 {	396	sai7: sai@300b0000 {
397	compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";	397	compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
398	reg = <0x300b0000 0x10000>;	398	reg = <0x300b0000 0x10000>;
399	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;	399	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
400	clocks = <&clk IMX8MN_CLK_SAI7_IPG>,	400	clocks = <&clk IMX8MN_CLK_SAI7_IPG>,

arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi+1−1

@@ -253,7 +253,7 @@ · 252 unmodified lines
253	#address-cells = <1>;	253	#address-cells = <1>;
254	#size-cells = <1>;	254	#size-cells = <1>;
255	spi-max-frequency = <84000000>;	255	spi-max-frequency = <84000000>;
256	spi-tx-bus-width = <4>;	256	spi-tx-bus-width = <1>;
257	spi-rx-bus-width = <4>;	257	spi-rx-bus-width = <4>;
258	};	258	};
259	};	259	};

arch/arm64/boot/dts/freescale/imx8qm.dtsi+1−1

@@ -196,7 +196,7 @@ · 195 unmodified lines
196	};	196	};
197		197
198	clk: clock-controller {	198	clk: clock-controller {
199	compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";	199	compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
200	#clock-cells = <2>;	200	#clock-cells = <2>;
201	};	201	};
202		202

arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi+4−4

@@ -262,25 +262,25 @@ · 261 unmodified lines
262	gpio4 {	262	gpio4 {
263	pins = "gpio4";	263	pins = "gpio4";
264	function = "32k-out1";	264	function = "32k-out1";
265	drive-push-pull;	265	drive-push-pull = <1>;
266	};	266	};
267		267
268	gpio5 {	268	gpio5 {
269	pins = "gpio5";	269	pins = "gpio5";
270	function = "gpio";	270	function = "gpio";
271	drive-push-pull;	271	drive-push-pull = <0>;
272	};	272	};
273		273
274	gpio6 {	274	gpio6 {
275	pins = "gpio6";	275	pins = "gpio6";
276	function = "gpio";	276	function = "gpio";
277	drive-push-pull;	277	drive-push-pull = <1>;
278	};	278	};
279		279
280	gpio7 {	280	gpio7 {
281	pins = "gpio7";	281	pins = "gpio7";
282	function = "gpio";	282	function = "gpio";
283	drive-push-pull;	283	drive-push-pull = <0>;
284	};	284	};
285	};	285	};
286		286

arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts+4−4

@@ -462,25 +462,25 @@ · 461 unmodified lines
462	gpio4 {	462	gpio4 {
463	pins = "gpio4";	463	pins = "gpio4";
464	function = "32k-out1";	464	function = "32k-out1";
465	drive-push-pull;	465	drive-push-pull = <1>;
466	};	466	};
467		467
468	gpio5 {	468	gpio5 {
469	pins = "gpio5";	469	pins = "gpio5";
470	function = "gpio";	470	function = "gpio";
471	drive-push-pull;	471	drive-push-pull = <0>;
472	};	472	};
473		473
474	gpio6 {	474	gpio6 {
475	pins = "gpio6";	475	pins = "gpio6";
476	function = "gpio";	476	function = "gpio";
477	drive-push-pull;	477	drive-push-pull = <1>;
478	};	478	};
479		479
480	gpio7 {	480	gpio7 {
481	pins = "gpio7";	481	pins = "gpio7";
482	function = "gpio";	482	function = "gpio";
483	drive-push-pull;	483	drive-push-pull = <1>;
484	};	484	};
485	};	485	};
486		486

arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi+3−3

@@ -174,19 +174,19 @@ · 173 unmodified lines
174	gpio4 {	174	gpio4 {
175	pins = "gpio4";	175	pins = "gpio4";
176	function = "32k-out1";	176	function = "32k-out1";
177	drive-push-pull;	177	drive-push-pull = <1>;
178	};	178	};
179		179
180	gpio6 {	180	gpio6 {
181	pins = "gpio6";	181	pins = "gpio6";
182	function = "gpio";	182	function = "gpio";
183	drive-push-pull;	183	drive-push-pull = <1>;
184	};	184	};
185		185
186	gpio7 {	186	gpio7 {
187	pins = "gpio7";	187	pins = "gpio7";
188	function = "gpio";	188	function = "gpio";
189	drive-push-pull;	189	drive-push-pull = <0>;
190	};	190	};
191	};	191	};
192		192

arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi+3−3

@@ -148,19 +148,19 @@ · 147 unmodified lines
148	gpio4 {	148	gpio4 {
149	pins = "gpio4";	149	pins = "gpio4";
150	function = "32k-out1";	150	function = "32k-out1";
151	drive-push-pull;	151	drive-push-pull = <1>;
152	};	152	};
153		153
154	gpio6 {	154	gpio6 {
155	pins = "gpio6";	155	pins = "gpio6";
156	function = "gpio";	156	function = "gpio";
157	drive-push-pull;	157	drive-push-pull = <1>;
158	};	158	};
159		159
160	gpio7 {	160	gpio7 {
161	pins = "gpio7";	161	pins = "gpio7";
162	function = "gpio";	162	function = "gpio";
163	drive-push-pull;	163	drive-push-pull = <0>;
164	};	164	};
165	};	165	};
166		166

arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi+3−3

@@ -59,7 +59,7 @@ · 58 unmodified lines
59	gpio1 {	59	gpio1 {
60	pins = "gpio1";	60	pins = "gpio1";
61	function = "fps-out";	61	function = "fps-out";
62	drive-push-pull;	62	drive-push-pull = <1>;
63	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	63	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
64	maxim,active-fps-power-up-slot = <7>;	64	maxim,active-fps-power-up-slot = <7>;
65	maxim,active-fps-power-down-slot = <0>;	65	maxim,active-fps-power-down-slot = <0>;
@@ -68,7 +68,7 @@ · 2 unmodified lines
68	gpio2_3 {	68	gpio2_3 {
69	pins = "gpio2", "gpio3";	69	pins = "gpio2", "gpio3";
70	function = "fps-out";	70	function = "fps-out";
71	drive-open-drain;	71	drive-open-drain = <1>;
72	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	72	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
73	};	73	};
74		74
@@ -80,7 +80,7 @@ · 5 unmodified lines
80	gpio5_6_7 {	80	gpio5_6_7 {
81	pins = "gpio5", "gpio6", "gpio7";	81	pins = "gpio5", "gpio6", "gpio7";
82	function = "gpio";	82	function = "gpio";
83	drive-push-pull;	83	drive-push-pull = <1>;
84	};	84	};
85	};	85	};
86		86

arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi+4−4

@@ -1351,7 +1351,7 @@ · 1350 unmodified lines
1351	gpio1 {	1351	gpio1 {
1352	pins = "gpio1";	1352	pins = "gpio1";
1353	function = "fps-out";	1353	function = "fps-out";
1354	drive-push-pull;	1354	drive-push-pull = <1>;
1355	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	1355	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1356	maxim,active-fps-power-up-slot = <7>;	1356	maxim,active-fps-power-up-slot = <7>;
1357	maxim,active-fps-power-down-slot = <0>;	1357	maxim,active-fps-power-down-slot = <0>;
@@ -1360,14 +1360,14 @@ · 2 unmodified lines
1360	gpio2 {	1360	gpio2 {
1361	pins = "gpio2";	1361	pins = "gpio2";
1362	function = "fps-out";	1362	function = "fps-out";
1363	drive-open-drain;	1363	drive-open-drain = <1>;
1364	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	1364	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1365	};	1365	};
1366		1366
1367	gpio3 {	1367	gpio3 {
1368	pins = "gpio3";	1368	pins = "gpio3";
1369	function = "fps-out";	1369	function = "fps-out";
1370	drive-open-drain;	1370	drive-open-drain = <1>;
1371	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	1371	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1372	};	1372	};
1373		1373
@@ -1379,7 +1379,7 @@ · 5 unmodified lines
1379	gpio5_6_7 {	1379	gpio5_6_7 {
1380	pins = "gpio5", "gpio6", "gpio7";	1380	pins = "gpio5", "gpio6", "gpio7";
1381	function = "gpio";	1381	function = "gpio";
1382	drive-push-pull;	1382	drive-push-pull = <1>;
1383	};	1383	};
1384	};	1384	};
1385		1385

arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts+4−4

@@ -195,7 +195,7 @@ · 194 unmodified lines
195	gpio1 {	195	gpio1 {
196	pins = "gpio1";	196	pins = "gpio1";
197	function = "fps-out";	197	function = "fps-out";
198	drive-push-pull;	198	drive-push-pull = <1>;
199	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;	199	maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
200	maxim,active-fps-power-up-slot = <0>;	200	maxim,active-fps-power-up-slot = <0>;
201	maxim,active-fps-power-down-slot = <7>;	201	maxim,active-fps-power-down-slot = <7>;
@@ -204,7 +204,7 @@ · 2 unmodified lines
204	gpio2 {	204	gpio2 {
205	pins = "gpio2";	205	pins = "gpio2";
206	function = "fps-out";	206	function = "fps-out";
207	drive-open-drain;	207	drive-open-drain = <1>;
208	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	208	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
209	maxim,active-fps-power-up-slot = <0>;	209	maxim,active-fps-power-up-slot = <0>;
210	maxim,active-fps-power-down-slot = <7>;	210	maxim,active-fps-power-down-slot = <7>;
@@ -213,7 +213,7 @@ · 2 unmodified lines
213	gpio3 {	213	gpio3 {
214	pins = "gpio3";	214	pins = "gpio3";
215	function = "fps-out";	215	function = "fps-out";
216	drive-open-drain;	216	drive-open-drain = <1>;
217	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	217	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218	maxim,active-fps-power-up-slot = <4>;	218	maxim,active-fps-power-up-slot = <4>;
219	maxim,active-fps-power-down-slot = <3>;	219	maxim,active-fps-power-down-slot = <3>;
@@ -227,7 +227,7 @@ · 7 unmodified lines
227	gpio5_6_7 {	227	gpio5_6_7 {
228	pins = "gpio5", "gpio6", "gpio7";	228	pins = "gpio5", "gpio6", "gpio7";
229	function = "gpio";	229	function = "gpio";
230	drive-push-pull;	230	drive-push-pull = <1>;
231	};	231	};
232	};	232	};
233		233

arch/arm64/boot/dts/nvidia/tegra210-smaug.dts+2−2

@@ -1386,7 +1386,7 @@ · 1385 unmodified lines
1386	gpio3 {	1386	gpio3 {
1387	pins = "gpio3";	1387	pins = "gpio3";
1388	function = "fps-out";	1388	function = "fps-out";
1389	drive-open-drain;	1389	drive-open-drain = <1>;
1390	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;	1390	maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1391	maxim,active-fps-power-up-slot = <4>;	1391	maxim,active-fps-power-up-slot = <4>;
1392	maxim,active-fps-power-down-slot = <2>;	1392	maxim,active-fps-power-down-slot = <2>;
@@ -1395,7 +1395,7 @@ · 2 unmodified lines
1395	gpio5_6 {	1395	gpio5_6 {
1396	pins = "gpio5", "gpio6";	1396	pins = "gpio5", "gpio6";
1397	function = "gpio";	1397	function = "gpio";
1398	drive-push-pull;	1398	drive-push-pull = <1>;
1399	};	1399	};
1400		1400
1401	gpio4 {	1401	gpio4 {

arch/arm64/include/asm/io.h+4−0

@@ -192,4 +192,8 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); · 191 unmodified lines
192	extern int valid_phys_addr_range(phys_addr_t addr, size_t size);	192	extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
193	extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);	193	extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
194		194
		195	extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
		196	unsigned long flags);
		197	#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
		198
195	#endif /* __ASM_IO_H */	199	#endif /* __ASM_IO_H */

arch/arm64/include/asm/kvm_emulate.h+1−0

@@ -40,6 +40,7 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu); · 39 unmodified lines
40	void kvm_inject_vabt(struct kvm_vcpu *vcpu);	40	void kvm_inject_vabt(struct kvm_vcpu *vcpu);
41	void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);	41	void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
42	void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);	42	void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
		43	void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
43		44
44	void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);	45	void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
45		46

arch/arm64/kernel/Makefile+4−0

 obj-y					+= vdso-wrap.o
 obj-$(CONFIG_COMPAT_VDSO)		+= vdso32-wrap.o
+# Force dependency (vdso*-wrap.S includes vdso.so through incbin)
+$(obj)/vdso-wrap.o: $(obj)/vdso/vdso.so
+$(obj)/vdso32-wrap.o: $(obj)/vdso32/vdso.so
 obj-y					+= probes/
 head-y					:= head.o
 extra-y					+= $(head-y) vmlinux.lds

arch/arm64/kernel/cpu_errata.c+2−0

 #ifdef CONFIG_ARM64_ERRATUM_1286807
 	{
 		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
+		/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
+		ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
 	},
 #endif
 	{},

arch/arm64/kernel/cpufeature.c+1−2

 	ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
 			       &id_aa64isar1_override),
-	ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
 			       &id_aa64isar2_override),
 		 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
 		 * to work correctly.
 		 */
-		BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
+		BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
 	}
 }

arch/arm64/kernel/elfcore.c+1−1

@@ -95,7 +95,7 @@ int elf_core_write_extra_phdrs(struct coredump_params *cprm, loff_t offset) · 94 unmodified lines
95	for_each_mte_vma(current, vma) {	95	for_each_mte_vma(current, vma) {
96	struct elf_phdr phdr;	96	struct elf_phdr phdr;
97		97
98	phdr.p_type = PT_ARM_MEMTAG_MTE;	98	phdr.p_type = PT_AARCH64_MEMTAG_MTE;
99	phdr.p_offset = offset;	99	phdr.p_offset = offset;
100	phdr.p_vaddr = vma->vm_start;	100	phdr.p_vaddr = vma->vm_start;
101	phdr.p_paddr = 0;	101	phdr.p_paddr = 0;

arch/arm64/kernel/vdso/Makefile+0−3

@@ -52,9 +52,6 @@ GCOV_PROFILE := n · 51 unmodified lines
52	targets += vdso.lds	52	targets += vdso.lds
53	CPPFLAGS_vdso.lds += -P -C -U$(ARCH)	53	CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
54		54
55	# Force dependency (incbin is bad)
56	$(obj)/vdso.o : $(obj)/vdso.so
57
58	# Link rule for the .so file, .lds has to be first	55	# Link rule for the .so file, .lds has to be first
59	$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE	56	$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE
60	$(call if_changed,vdsold_and_vdso_check)	57	$(call if_changed,vdsold_and_vdso_check)

arch/arm64/kernel/vdso32/Makefile+0−3

@@ -131,9 +131,6 @@ obj-vdso := $(c-obj-vdso) $(c-obj-vdso-gettimeofday) $(asm-obj-vdso) · 130 unmodified lines
131	targets += vdso.lds	131	targets += vdso.lds
132	CPPFLAGS_vdso.lds += -P -C -U$(ARCH)	132	CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
133		133
134	# Force dependency (vdso.s includes vdso.so through incbin)
135	$(obj)/vdso.o: $(obj)/vdso.so
136
137	include/generated/vdso32-offsets.h: $(obj)/vdso.so.dbg FORCE	134	include/generated/vdso32-offsets.h: $(obj)/vdso.so.dbg FORCE
138	$(call if_changed,vdsosym)	135	$(call if_changed,vdsosym)
139		136

arch/arm64/kvm/hyp/nvhe/host.S+9−9

@@ -198,15 +198,15 @@ SYM_CODE_START(__kvm_hyp_host_vector) · 197 unmodified lines
198	invalid_host_el2_vect // FIQ EL2h	198	invalid_host_el2_vect // FIQ EL2h
199	invalid_host_el2_vect // Error EL2h	199	invalid_host_el2_vect // Error EL2h
200		200
201	host_el1_sync_vect // Synchronous 64-bit EL1	201	host_el1_sync_vect // Synchronous 64-bit EL1/EL0
202	invalid_host_el1_vect // IRQ 64-bit EL1	202	invalid_host_el1_vect // IRQ 64-bit EL1/EL0
203	invalid_host_el1_vect // FIQ 64-bit EL1	203	invalid_host_el1_vect // FIQ 64-bit EL1/EL0
204	invalid_host_el1_vect // Error 64-bit EL1	204	invalid_host_el1_vect // Error 64-bit EL1/EL0
205		205
206	invalid_host_el1_vect // Synchronous 32-bit EL1	206	host_el1_sync_vect // Synchronous 32-bit EL1/EL0
207	invalid_host_el1_vect // IRQ 32-bit EL1	207	invalid_host_el1_vect // IRQ 32-bit EL1/EL0
208	invalid_host_el1_vect // FIQ 32-bit EL1	208	invalid_host_el1_vect // FIQ 32-bit EL1/EL0
209	invalid_host_el1_vect // Error 32-bit EL1	209	invalid_host_el1_vect // Error 32-bit EL1/EL0
210	SYM_CODE_END(__kvm_hyp_host_vector)	210	SYM_CODE_END(__kvm_hyp_host_vector)
211		211
212	/*	212	/*

arch/arm64/kvm/inject_fault.c+28−0

@@ -145,6 +145,34 @@ void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr) · 144 unmodified lines
145	inject_abt64(vcpu, true, addr);	145	inject_abt64(vcpu, true, addr);
146	}	146	}
147		147
		148	void kvm_inject_size_fault(struct kvm_vcpu *vcpu)
		149	{
		150	unsigned long addr, esr;
		151
		152	addr = kvm_vcpu_get_fault_ipa(vcpu);
		153	addr \|= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
		154
		155	if (kvm_vcpu_trap_is_iabt(vcpu))
		156	kvm_inject_pabt(vcpu, addr);
		157	else
		158	kvm_inject_dabt(vcpu, addr);
		159
		160	/*
		161	* If AArch64 or LPAE, set FSC to 0 to indicate an Address
		162	* Size Fault at level 0, as if exceeding PARange.
		163	*
		164	* Non-LPAE guests will only get the external abort, as there
		165	* is no way to to describe the ASF.
		166	*/
		167	if (vcpu_el1_is_32bit(vcpu) &&
		168	!(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
		169	return;
		170
		171	esr = vcpu_read_sys_reg(vcpu, ESR_EL1);
		172	esr &= ~GENMASK_ULL(5, 0);
		173	vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
		174	}
		175
148	/**	176	/**
149	* kvm_inject_undefined - inject an undefined instruction into the guest	177	* kvm_inject_undefined - inject an undefined instruction into the guest
150	* @vcpu: The vCPU in which to inject the exception	178	* @vcpu: The vCPU in which to inject the exception

arch/arm64/kvm/mmu.c+19−0

@@ -1337,6 +1337,25 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) · 1336 unmodified lines
1337	fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);	1337	fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
1338	is_iabt = kvm_vcpu_trap_is_iabt(vcpu);	1338	is_iabt = kvm_vcpu_trap_is_iabt(vcpu);
1339		1339
		1340	if (fault_status == FSC_FAULT) {
		1341	/* Beyond sanitised PARange (which is the IPA limit) */
		1342	if (fault_ipa >= BIT_ULL(get_kvm_ipa_limit())) {
		1343	kvm_inject_size_fault(vcpu);
		1344	return 1;
		1345	}
		1346
		1347	/* Falls between the IPA range and the PARange? */
		1348	if (fault_ipa >= BIT_ULL(vcpu->arch.hw_mmu->pgt->ia_bits)) {
		1349	fault_ipa \|= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
		1350
		1351	if (is_iabt)
		1352	kvm_inject_pabt(vcpu, fault_ipa);
		1353	else
		1354	kvm_inject_dabt(vcpu, fault_ipa);
		1355	return 1;
		1356	}
		1357	}
		1358
1340	/* Synchronous External Abort? */	1359	/* Synchronous External Abort? */
1341	if (kvm_vcpu_abt_issea(vcpu)) {	1360	if (kvm_vcpu_abt_issea(vcpu)) {
1342	/*	1361	/*

arch/arm64/kvm/pmu-emul.c+22−1

 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	struct kvm_pmc *pmc = &pmu->pmc[select_idx];
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return 0;
 	counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
 	if (kvm_pmu_pmc_is_chained(pmc) &&
 {
 	u64 reg;
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return;
 	reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
 	      ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
 	__vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	struct kvm_pmc *pmc;
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return;
 	if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val)
 		return;
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	struct kvm_pmc *pmc;
-	if (!val)
+	if (!kvm_vcpu_has_pmu(vcpu) || !val)
 		return;
 	for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	int i;
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return;
 	if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
 		return;
 {
 	int i;
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return;
 	if (val & ARMV8_PMU_PMCR_E) {
 		kvm_pmu_enable_counter_mask(vcpu,
 		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
 {
 	u64 reg, mask;
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return;
 	mask  =  ARMV8_PMU_EVTYPE_MASK;
 	mask &= ~ARMV8_PMU_EVTYPE_EVENT;
 	mask |= kvm_pmu_event_mask(vcpu->kvm);
 	u64 val, mask = 0;
 	int base, i, nr_events;
+	if (!kvm_vcpu_has_pmu(vcpu))
+		return 0;
 	if (!pmceid1) {
 		val = read_sysreg(pmceid0_el0);
 		base = 0;

arch/arm64/kvm/psci.c+2−1

@@ -181,7 +181,8 @@ static void kvm_prepare_system_event(struct kvm_vcpu *vcpu, u32 type, u64 flags) · 180 unmodified lines
181		181
182	memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event));	182	memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event));
183	vcpu->run->system_event.type = type;	183	vcpu->run->system_event.type = type;
184	vcpu->run->system_event.flags = flags;	184	vcpu->run->system_event.ndata = 1;
		185	vcpu->run->system_event.data[0] = flags;
185	vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;	186	vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
186	}	187	}
187		188

arch/arm64/mm/ioremap.c+8−0

@@ -99,3 +99,11 @@ void __init early_ioremap_init(void) · 98 unmodified lines
99	{	99	{
100	early_ioremap_setup();	100	early_ioremap_setup();
101	}	101	}
		102
		103	bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
		104	unsigned long flags)
		105	{
		106	unsigned long pfn = PHYS_PFN(offset);
		107
		108	return pfn_is_map_memory(pfn);
		109	}

arch/mips/include/asm/timex.h+4−4

@@ -40,9 +40,9 @@ · 39 unmodified lines
40	typedef unsigned int cycles_t;	40	typedef unsigned int cycles_t;
41		41
42	/*	42	/*
43	* On R4000/R4400 before version 5.0 an erratum exists such that if the	43	* On R4000/R4400 an erratum exists such that if the cycle counter is
44	* cycle counter is read in the exact moment that it is matching the	44	* read in the exact moment that it is matching the compare register,
45	* compare register, no interrupt will be generated.	45	* no interrupt will be generated.
46	*	46	*
47	* There is a suggested workaround and also the erratum can't strike if	47	* There is a suggested workaround and also the erratum can't strike if
48	* the compare interrupt isn't being used as the clock source device.	48	* the compare interrupt isn't being used as the clock source device.
@@ -63,7 +63,7 @@ static inline int can_use_mips_counter(unsigned int prid) · 14 unmodified lines
63	if (!__builtin_constant_p(cpu_has_counter))	63	if (!__builtin_constant_p(cpu_has_counter))
64	asm volatile("" : "=m" (cpu_data[0].options));	64	asm volatile("" : "=m" (cpu_data[0].options));
65	if (likely(cpu_has_counter &&	65	if (likely(cpu_has_counter &&
66	prid >= (PRID_IMP_R4000 \| PRID_REV_ENCODE_44(5, 0))))	66	prid > (PRID_IMP_R4000 \| PRID_REV_ENCODE_44(15, 15))))
67	return 1;	67	return 1;
68	else	68	else
69	return 0;	69	return 0;

arch/mips/kernel/time.c+3−8

 	case CPU_R4400MC:
 		/*
 		 * The published errata for the R4400 up to 3.0 say the CPU
-		 * has the mfc0 from count bug.
+		 * has the mfc0 from count bug.  This seems the last version
+		 * produced.
 		 */
-		if ((current_cpu_data.processor_id & 0xff) <= 0x30)
+		return 1;
-			return 1;
-		/*
-		 * we assume newer revisions are ok
-		 */
-		return 0;
 	}
 	return 0;

arch/parisc/Kconfig+1−0

@@ -38,6 +38,7 @@ config PARISC · 37 unmodified lines
38	select ARCH_HAVE_NMI_SAFE_CMPXCHG	38	select ARCH_HAVE_NMI_SAFE_CMPXCHG
39	select GENERIC_SMP_IDLE_THREAD	39	select GENERIC_SMP_IDLE_THREAD
40	select GENERIC_ARCH_TOPOLOGY if SMP	40	select GENERIC_ARCH_TOPOLOGY if SMP
		41	select GENERIC_CPU_DEVICES if !SMP
41	select GENERIC_LIB_DEVMEM_IS_ALLOWED	42	select GENERIC_LIB_DEVMEM_IS_ALLOWED
42	select SYSCTL_ARCH_UNALIGN_ALLOW	43	select SYSCTL_ARCH_UNALIGN_ALLOW
43	select SYSCTL_EXCEPTION_TRACE	44	select SYSCTL_EXCEPTION_TRACE

arch/parisc/configs/generic-32bit_defconfig+3−1

 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_PERF_EVENTS=y
 CONFIG_PARPORT_PC=m
 CONFIG_PARPORT_1284=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=6144
 CONFIG_BLK_DEV_SD=y

arch/parisc/configs/generic-64bit_defconfig+2−1

 CONFIG_MEMCG=y
 CONFIG_CGROUP_PIDS=y
 CONFIG_CPUSETS=y
+CONFIG_USER_NS=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_CRC_CCITT=m
 CONFIG_LIBCRC32C=y
 CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_KERNEL=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_STACKOVERFLOW=y
 # CONFIG_SCHED_DEBUG is not set

arch/parisc/include/asm/pgtable.h+1−1

@@ -160,7 +160,7 @@ extern void __update_cache(pte_t pte); · 159 unmodified lines
160	#define SPACEID_SHIFT (MAX_ADDRBITS - 32)	160	#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
161	#else	161	#else
162	#define MAX_ADDRBITS (BITS_PER_LONG)	162	#define MAX_ADDRBITS (BITS_PER_LONG)
163	#define MAX_ADDRESS (1UL << MAX_ADDRBITS)	163	#define MAX_ADDRESS (1ULL << MAX_ADDRBITS)
164	#define SPACEID_SHIFT 0	164	#define SPACEID_SHIFT 0
165	#endif	165	#endif
166		166

arch/parisc/kernel/cache.c+3−15

@@ -403,7 +403,7 @@ void __init parisc_setup_cache_timing(void) · 402 unmodified lines
403	{	403	{
404	unsigned long rangetime, alltime;	404	unsigned long rangetime, alltime;
405	unsigned long size;	405	unsigned long size;
406	unsigned long threshold, threshold2;	406	unsigned long threshold;
407		407
408	alltime = mfctl(16);	408	alltime = mfctl(16);
409	flush_data_cache();	409	flush_data_cache();
@@ -418,20 +418,8 @@ void __init parisc_setup_cache_timing(void) · 8 unmodified lines
418	alltime, size, rangetime);	418	alltime, size, rangetime);
419		419
420	threshold = L1_CACHE_ALIGN(size * alltime / rangetime);	420	threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
421		421	if (threshold > cache_info.dc_size)
422	/*	422	threshold = cache_info.dc_size;
423	* The threshold computed above isn't very reliable since the
424	* flush times depend greatly on the percentage of dirty lines
425	* in the flush range. Further, the whole cache time doesn't
426	* include the time to refill lines that aren't in the mm/vma
427	* being flushed. By timing glibc build and checks on mako cpus,
428	* the following formula seems to work reasonably well. The
429	* value from the timing calculation is too small, and increases
430	* build and check times by almost a factor two.
431	*/
432	threshold2 = cache_info.dc_size * num_online_cpus();
433	if (threshold2 > threshold)
434	threshold = threshold2;
435	if (threshold)	423	if (threshold)
436	parisc_cache_flush_threshold = threshold;	424	parisc_cache_flush_threshold = threshold;
437	printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",	425	printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",

arch/parisc/kernel/kprobes.c+1−1

@@ -152,7 +152,7 @@ int __kprobes parisc_kprobe_ss_handler(struct pt_regs *regs) · 151 unmodified lines
152	/* for absolute branch instructions we can copy iaoq_b. for relative	152	/* for absolute branch instructions we can copy iaoq_b. for relative
153	* branch instructions we need to calculate the new address based on the	153	* branch instructions we need to calculate the new address based on the
154	* difference between iaoq_f and iaoq_b. We cannot use iaoq_b without	154	* difference between iaoq_f and iaoq_b. We cannot use iaoq_b without
155	* modificationt because it's based on our ainsn.insn address.	155	* modifications because it's based on our ainsn.insn address.
156	*/	156	*/
157		157
158	if (p->post_handler)	158	if (p->post_handler)

arch/parisc/kernel/patch.c+14−11

 	*need_unmap = 1;
 	set_fixmap(fixmap, page_to_phys(page));
-	raw_spin_lock_irqsave(&patch_lock, *flags);
+	if (flags)
+		raw_spin_lock_irqsave(&patch_lock, *flags);
+	else
+		__acquire(&patch_lock);
 	return (void *) (__fix_to_virt(fixmap) + (uintaddr & ~PAGE_MASK));
 }
 {
 	clear_fixmap(fixmap);
-	raw_spin_unlock_irqrestore(&patch_lock, *flags);
+	if (flags)
+		raw_spin_unlock_irqrestore(&patch_lock, *flags);
+	else
+		__release(&patch_lock);
 }
 void __kprobes __patch_text_multiple(void *addr, u32 *insn, unsigned int len)
 	int mapped;
 	/* Make sure we don't have any aliases in cache */
-	flush_kernel_dcache_range_asm(start, end);
+	flush_kernel_vmap_range(addr, len);
-	flush_kernel_icache_range_asm(start, end);
+	flush_icache_range(start, end);
-	flush_tlb_kernel_range(start, end);
 	p = fixmap = patch_map(addr, FIX_TEXT_POKE0, &flags, &mapped);
 			 * We're crossing a page boundary, so
 			 * need to remap
 			 */
-			flush_kernel_dcache_range_asm((unsigned long)fixmap,
+			flush_kernel_vmap_range((void *)fixmap,
-						      (unsigned long)p);
+						(p-fixmap) * sizeof(*p));
-			flush_tlb_kernel_range((unsigned long)fixmap,
-					       (unsigned long)p);
 			if (mapped)
 				patch_unmap(FIX_TEXT_POKE0, &flags);
 			p = fixmap = patch_map(addr, FIX_TEXT_POKE0, &flags,
 		}
 	}
-	flush_kernel_dcache_range_asm((unsigned long)fixmap, (unsigned long)p);
+	flush_kernel_vmap_range((void *)fixmap, (p-fixmap) * sizeof(*p));
-	flush_tlb_kernel_range((unsigned long)fixmap, (unsigned long)p);
 	if (mapped)
 		patch_unmap(FIX_TEXT_POKE0, &flags);
+	flush_icache_range(start, end);
 }
 void __kprobes __patch_text(void *addr, u32 insn)

arch/parisc/kernel/processor.c+9−2

 	p->cpu_num = cpu_info.cpu_num;
 	p->cpu_loc = cpu_info.cpu_loc;
+	set_cpu_possible(cpuid, true);
 	store_cpu_topology(cpuid);
 #ifdef CONFIG_SMP
 		}
 		seq_printf(m, " (0x%02lx)\n", boot_cpu_data.pdc.capabilities);
-		seq_printf(m, "model\t\t: %s\n"
+		seq_printf(m, "model\t\t: %s - %s\n",
-				"model name\t: %s\n",
 				 boot_cpu_data.pdc.sys_model_name,
 				 cpuinfo->dev ?
 				 cpuinfo->dev->name : "Unknown");
  */
 void __init processor_init(void)
 {
+	unsigned int cpu;
 	reset_cpu_topology();
+	/* reset possible mask. We will mark those which are possible. */
+	for_each_possible_cpu(cpu)
+		set_cpu_possible(cpu, false);
 	register_parisc_driver(&cpu_driver);
 }

arch/parisc/kernel/setup.c+2−0

@@ -161,6 +161,8 @@ void __init setup_arch(char **cmdline_p) · 160 unmodified lines
161	#ifdef CONFIG_PA11	161	#ifdef CONFIG_PA11
162	dma_ops_init();	162	dma_ops_init();
163	#endif	163	#endif
		164
		165	clear_sched_clock_stable();
164	}	166	}
165		167
166	/*	168	/*

arch/parisc/kernel/time.c+1−5

 static int __init init_cr16_clocksource(void)
 {
 	/*
-	 * The cr16 interval timers are not syncronized across CPUs, even if
+	 * The cr16 interval timers are not synchronized across CPUs.
-	 * they share the same socket.
 	 */
 	if (num_online_cpus() > 1 && !running_on_qemu) {
-		/* mark sched_clock unstable */
-		clear_sched_clock_stable();
 		clocksource_cr16.name = "cr16_unstable";
 		clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
 		clocksource_cr16.rating = 0;

arch/parisc/kernel/traps.c+1−1

@@ -469,7 +469,7 @@ void parisc_terminate(char msg, struct pt_regs regs, int code, unsigned long o · 468 unmodified lines
469	* panic notifiers, and we should call panic	469	* panic notifiers, and we should call panic
470	* directly from the location that we wish.	470	* directly from the location that we wish.
471	* e.g. We should not call panic from	471	* e.g. We should not call panic from
472	* parisc_terminate, but rather the oter way around.	472	* parisc_terminate, but rather the other way around.
473	* This hack works, prints the panic message twice,	473	* This hack works, prints the panic message twice,
474	* and it enables reboot timers!	474	* and it enables reboot timers!
475	*/	475	*/

arch/parisc/math-emu/dfadd.c+1−1

@@ -253,7 +253,7 @@ dbl_fadd( · 252 unmodified lines
253	return(NOEXCEPTION);	253	return(NOEXCEPTION);
254	}	254	}
255	right_exponent = 1; /* Set exponent to reflect different bias	255	right_exponent = 1; /* Set exponent to reflect different bias
256	* with denomalized numbers. */	256	* with denormalized numbers. */
257	}	257	}
258	else	258	else
259	{	259	{

arch/parisc/math-emu/dfsub.c+1−1

@@ -256,7 +256,7 @@ dbl_fsub( · 255 unmodified lines
256	return(NOEXCEPTION);	256	return(NOEXCEPTION);
257	}	257	}
258	right_exponent = 1; /* Set exponent to reflect different bias	258	right_exponent = 1; /* Set exponent to reflect different bias
259	* with denomalized numbers. */	259	* with denormalized numbers. */
260	}	260	}
261	else	261	else
262	{	262	{

arch/parisc/math-emu/sfadd.c+1−1

@@ -249,7 +249,7 @@ sgl_fadd( · 248 unmodified lines
249	return(NOEXCEPTION);	249	return(NOEXCEPTION);
250	}	250	}
251	right_exponent = 1; /* Set exponent to reflect different bias	251	right_exponent = 1; /* Set exponent to reflect different bias
252	* with denomalized numbers. */	252	* with denormalized numbers. */
253	}	253	}
254	else	254	else
255	{	255	{

arch/parisc/math-emu/sfsub.c+1−1

@@ -252,7 +252,7 @@ sgl_fsub( · 251 unmodified lines
252	return(NOEXCEPTION);	252	return(NOEXCEPTION);
253	}	253	}
254	right_exponent = 1; /* Set exponent to reflect different bias	254	right_exponent = 1; /* Set exponent to reflect different bias
255	* with denomalized numbers. */	255	* with denormalized numbers. */
256	}	256	}
257	else	257	else
258	{	258	{

arch/powerpc/kernel/vdso/gettimeofday.S+7−2

 .macro cvdso_call funct call_time=0
   .cfi_startproc
 	PPC_STLU	r1, -PPC_MIN_STKFRM(r1)
+  .cfi_adjust_cfa_offset PPC_MIN_STKFRM
 	mflr		r0
-  .cfi_register lr, r0
 	PPC_STLU	r1, -PPC_MIN_STKFRM(r1)
+  .cfi_adjust_cfa_offset PPC_MIN_STKFRM
 	PPC_STL		r0, PPC_MIN_STKFRM + PPC_LR_STKOFF(r1)
+  .cfi_rel_offset lr, PPC_MIN_STKFRM + PPC_LR_STKOFF
 #ifdef __powerpc64__
 	PPC_STL		r2, PPC_MIN_STKFRM + STK_GOT(r1)
+  .cfi_rel_offset r2, PPC_MIN_STKFRM + STK_GOT
 #endif
 	get_datapage	r5
 	.ifeq	\call_time
 	PPC_LL		r0, PPC_MIN_STKFRM + PPC_LR_STKOFF(r1)
 #ifdef __powerpc64__
 	PPC_LL		r2, PPC_MIN_STKFRM + STK_GOT(r1)
+  .cfi_restore r2
 #endif
 	.ifeq	\call_time
 	cmpwi		r3, 0
 	.endif
 	mtlr		r0
-  .cfi_restore lr
 	addi		r1, r1, 2 * PPC_MIN_STKFRM
+  .cfi_restore lr
+  .cfi_def_cfa_offset 0
 	crclr		so
 	.ifeq	\call_time
 	beqlr+

arch/powerpc/kvm/book3s_32_sr.S+21−5

@@ -122,11 +122,27 @@ · 121 unmodified lines
122		122
123	/* 0x0 - 0xb */	123	/* 0x0 - 0xb */
124		124
125	/* 'current->mm' needs to be in r4 */	125	/* switch_mmu_context() needs paging, let's enable it */
126	tophys(r4, r2)	126	mfmsr r9
127	lwz r4, MM(r4)	127	ori r11, r9, MSR_DR
128	tophys(r4, r4)	128	mtmsr r11
129	/* This only clobbers r0, r3, r4 and r5 */	129	sync
		130
		131	/* switch_mmu_context() clobbers r12, rescue it */
		132	SAVE_GPR(12, r1)
		133
		134	/* Calling switch_mmu_context(<inv>, current->mm, <inv>); */
		135	lwz r4, MM(r2)
130	bl switch_mmu_context	136	bl switch_mmu_context
131		137
		138	/* restore r12 */
		139	REST_GPR(12, r1)
		140
		141	/* Disable paging again */
		142	mfmsr r9
		143	li r6, MSR_DR
		144	andc r9, r9, r6
		145	mtmsr r9
		146	sync
		147
132	.endm	148	.endm

arch/powerpc/platforms/pseries/papr_scm.c+2−5

 {
 	struct papr_scm_perf_stat *stat;
 	struct papr_scm_perf_stats *stats;
-	char *statid;
 	int index, rc, count;
 	u32 available_events;
 	for (index = 0, stat = stats->scm_statistic, count = 0;
 		     index < available_events; index++, ++stat) {
-		statid = kzalloc(strlen(stat->stat_id) + 1, GFP_KERNEL);
+		p->nvdimm_events_map[count] = kmemdup_nul(stat->stat_id, 8, GFP_KERNEL);
-		if (!statid) {
+		if (!p->nvdimm_events_map[count]) {
 			rc = -ENOMEM;
 			goto out_nvdimm_events_map;
 		}
-		strcpy(statid, stat->stat_id);
-		p->nvdimm_events_map[count] = statid;
 		count++;
 	}
 	p->nvdimm_events_map[count] = NULL;

arch/powerpc/platforms/pseries/vas-sysfs.c+14−5

 /*
  * This function is used to get the notification from the drmgr when
- * QoS credits are changed. Though receiving the target total QoS
+ * QoS credits are changed.
- * credits here, get the official QoS capabilities from the hypervisor.
  */
-static ssize_t update_total_credits_trigger(struct vas_cop_feat_caps *caps,
+static ssize_t update_total_credits_store(struct vas_cop_feat_caps *caps,
 						const char *buf, size_t count)
 {
 	int err;
 	u16 creds;
 	err = kstrtou16(buf, 0, &creds);
+	/*
+	 * The user space interface from the management console
+	 * notifies OS with the new QoS credits and then the
+	 * hypervisor. So OS has to use this new credits value
+	 * and reconfigure VAS windows (close or reopen depends
+	 * on the credits available) instead of depending on VAS
+	 * QoS capabilities from the hypervisor.
+	 */
 	if (!err)
-		err = vas_reconfig_capabilties(caps->win_type);
+		err = vas_reconfig_capabilties(caps->win_type, creds);
 	if (err)
 		return -EINVAL;
+	pr_info("Set QoS total credits %u\n", creds);
 	return count;
 }
 VAS_ATTR_RO(nr_used_credits);
 static struct vas_sysfs_entry update_total_credits_attribute =
-	__ATTR(update_total_credits, 0200, NULL, update_total_credits_trigger);
+	__ATTR(update_total_credits, 0200, NULL, update_total_credits_store);
 static struct attribute *vas_def_capab_attrs[] = {
 	&nr_total_credits_attribute.attr,

arch/powerpc/platforms/pseries/vas.c+12−11

  * changes. Reconfig window configurations based on the credits
  * availability from this new capabilities.
  */
-int vas_reconfig_capabilties(u8 type)
+int vas_reconfig_capabilties(u8 type, int new_nr_creds)
 {
 	struct vas_cop_feat_caps *caps;
-	int old_nr_creds, new_nr_creds;
+	int old_nr_creds;
 	struct vas_caps *vcaps;
 	int rc = 0, nr_active_wins;
 	caps = &vcaps->caps;
 	mutex_lock(&vas_pseries_mutex);
-	rc = h_query_vas_capabilities(H_QUERY_VAS_CAPABILITIES, vcaps->feat,
-				      (u64)virt_to_phys(&hv_cop_caps));
-	if (rc)
-		goto out;
-	new_nr_creds = be16_to_cpu(hv_cop_caps.target_lpar_creds);
 	old_nr_creds = atomic_read(&caps->nr_total_credits);
 					false);
 	}
-out:
 	mutex_unlock(&vas_pseries_mutex);
 	return rc;
 }
 	struct of_reconfig_data *rd = data;
 	struct device_node *dn = rd->dn;
 	const __be32 *intserv = NULL;
-	int len, rc = 0;
+	int new_nr_creds, len, rc = 0;
 	if ((action == OF_RECONFIG_ATTACH_NODE) ||
 		(action == OF_RECONFIG_DETACH_NODE))
 	if (!intserv)
 		return NOTIFY_OK;
-	rc = vas_reconfig_capabilties(VAS_GZIP_DEF_FEAT_TYPE);
+	rc = h_query_vas_capabilities(H_QUERY_VAS_CAPABILITIES,
+					vascaps[VAS_GZIP_DEF_FEAT_TYPE].feat,
+					(u64)virt_to_phys(&hv_cop_caps));
+	if (!rc) {
+		new_nr_creds = be16_to_cpu(hv_cop_caps.target_lpar_creds);
+		rc = vas_reconfig_capabilties(VAS_GZIP_DEF_FEAT_TYPE,
+						new_nr_creds);
+	}
 	if (rc)
 		pr_err("Failed reconfig VAS capabilities with DLPAR\n");

arch/powerpc/platforms/pseries/vas.h+1−1

@@ -135,7 +135,7 @@ struct pseries_vas_window { · 134 unmodified lines
135	};	135	};
136		136
137	int sysfs_add_vas_caps(struct vas_cop_feat_caps *caps);	137	int sysfs_add_vas_caps(struct vas_cop_feat_caps *caps);
138	int vas_reconfig_capabilties(u8 type);	138	int vas_reconfig_capabilties(u8 type, int new_nr_creds);
139	int __init sysfs_pseries_vas_init(struct vas_all_caps *vas_caps);	139	int __init sysfs_pseries_vas_init(struct vas_all_caps *vas_caps);
140		140
141	#ifdef CONFIG_PPC_VAS	141	#ifdef CONFIG_PPC_VAS

arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi+14−2

 		reg = <0x0 0x41000000 0x0 0xF0>;
 		microchip,sync-update-mask = /bits/ 32 <0>;
 		#pwm-cells = <2>;
-		clocks = <&clkcfg CLK_FIC3>;
+		clocks = <&fabric_clk3>;
 		status = "disabled";
 	};
 		reg = <0x0 0x44000000 0x0 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&clkcfg CLK_FIC3>;
+		clocks = <&fabric_clk3>;
 		interrupt-parent = <&plic>;
 		interrupts = <122>;
 		clock-frequency = <100000>;
 		status = "disabled";
 	};
+	fabric_clk3: fabric-clk3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <62500000>;
+	};
+	fabric_clk1: fabric-clk1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
 };

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts+1−1

@@ -45,7 +45,7 @@ · 44 unmodified lines
45	};	45	};
46		46
47	&refclk {	47	&refclk {
48	clock-frequency = <600000000>;	48	clock-frequency = <125000000>;
49	};	49	};
50		50
51	&mmuart1 {	51	&mmuart1 {

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi+5−5

@@ -141,7 +141,7 @@ · 140 unmodified lines
141	};	141	};
142	};	142	};
143		143
144	refclk: msspllclk {	144	refclk: mssrefclk {
145	compatible = "fixed-clock";	145	compatible = "fixed-clock";
146	#clock-cells = <0>;	146	#clock-cells = <0>;
147	};	147	};
@@ -190,7 +190,7 @@ · 42 unmodified lines
190		190
191	clkcfg: clkcfg@20002000 {	191	clkcfg: clkcfg@20002000 {
192	compatible = "microchip,mpfs-clkcfg";	192	compatible = "microchip,mpfs-clkcfg";
193	reg = <0x0 0x20002000 0x0 0x1000>;	193	reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
194	clocks = <&refclk>;	194	clocks = <&refclk>;
195	#clock-cells = <1>;	195	#clock-cells = <1>;
196	};	196	};
@@ -393,8 +393,8 @@ · 196 unmodified lines
393	reg = <0x0 0x20124000 0x0 0x1000>;	393	reg = <0x0 0x20124000 0x0 0x1000>;
394	interrupt-parent = <&plic>;	394	interrupt-parent = <&plic>;
395	interrupts = <80>, <81>;	395	interrupts = <80>, <81>;
396	clocks = <&clkcfg CLK_RTC>;	396	clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
397	clock-names = "rtc";	397	clock-names = "rtc", "rtcref";
398	status = "disabled";	398	status = "disabled";
399	};	399	};
400		400
@@ -424,7 +424,7 @@ · 23 unmodified lines
424	<0 0 0 3 &pcie_intc 2>,	424	<0 0 0 3 &pcie_intc 2>,
425	<0 0 0 4 &pcie_intc 3>;	425	<0 0 0 4 &pcie_intc 3>;
426	interrupt-map-mask = <0 0 0 7>;	426	interrupt-map-mask = <0 0 0 7>;
427	clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;	427	clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
428	clock-names = "fic0", "fic1", "fic3";	428	clock-names = "fic0", "fic1", "fic3";
429	ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;	429	ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
430	msi-parent = <&pcie>;	430	msi-parent = <&pcie>;

arch/riscv/configs/defconfig+1−0

@@ -101,6 +101,7 @@ CONFIG_VIRTIO_BALLOON=y · 100 unmodified lines
101	CONFIG_VIRTIO_INPUT=y	101	CONFIG_VIRTIO_INPUT=y
102	CONFIG_VIRTIO_MMIO=y	102	CONFIG_VIRTIO_MMIO=y
103	CONFIG_RPMSG_CHAR=y	103	CONFIG_RPMSG_CHAR=y
		104	CONFIG_RPMSG_CTRL=y
104	CONFIG_RPMSG_VIRTIO=y	105	CONFIG_RPMSG_VIRTIO=y
105	CONFIG_EXT4_FS=y	106	CONFIG_EXT4_FS=y
106	CONFIG_EXT4_FS_POSIX_ACL=y	107	CONFIG_EXT4_FS_POSIX_ACL=y

arch/riscv/configs/rv32_defconfig+1−0

@@ -93,6 +93,7 @@ CONFIG_VIRTIO_BALLOON=y · 92 unmodified lines
93	CONFIG_VIRTIO_INPUT=y	93	CONFIG_VIRTIO_INPUT=y
94	CONFIG_VIRTIO_MMIO=y	94	CONFIG_VIRTIO_MMIO=y
95	CONFIG_RPMSG_CHAR=y	95	CONFIG_RPMSG_CHAR=y
		96	CONFIG_RPMSG_CTRL=y
96	CONFIG_RPMSG_VIRTIO=y	97	CONFIG_RPMSG_VIRTIO=y
97	CONFIG_EXT4_FS=y	98	CONFIG_EXT4_FS=y
98	CONFIG_EXT4_FS_POSIX_ACL=y	99	CONFIG_EXT4_FS_POSIX_ACL=y

arch/riscv/kernel/patch.c+1−1

@@ -104,7 +104,7 @@ static int patch_text_cb(void *data) · 103 unmodified lines
104	struct patch_insn *patch = data;	104	struct patch_insn *patch = data;
105	int ret = 0;	105	int ret = 0;
106		106
107	if (atomic_inc_return(&patch->cpu_count) == 1) {	107	if (atomic_inc_return(&patch->cpu_count) == num_online_cpus()) {
108	ret =	108	ret =
109	patch_text_nosync(patch->addr, &patch->insn,	109	patch_text_nosync(patch->addr, &patch->insn,
110	GET_INSN_LENGTH(patch->insn));	110	GET_INSN_LENGTH(patch->insn));

arch/riscv/kvm/vcpu_sbi.c+3−2

 void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
 				     struct kvm_run *run,
-				     u32 type, u64 flags)
+				     u32 type, u64 reason)
 {
 	unsigned long i;
 	struct kvm_vcpu *tmp;
 	memset(&run->system_event, 0, sizeof(run->system_event));
 	run->system_event.type = type;
-	run->system_event.flags = flags;
+	run->system_event.ndata = 1;
+	run->system_event.data[0] = reason;
 	run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
 }

arch/riscv/mm/init.c+19−2

@@ -208,8 +208,25 @@ static void __init setup_bootmem(void) · 207 unmodified lines
208	* early_init_fdt_reserve_self() since __pa() does	208	* early_init_fdt_reserve_self() since __pa() does
209	* not work for DTB pointers that are fixmap addresses	209	* not work for DTB pointers that are fixmap addresses
210	*/	210	*/
211	if (!IS_ENABLED(CONFIG_BUILTIN_DTB))	211	if (!IS_ENABLED(CONFIG_BUILTIN_DTB)) {
212	memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));	212	/*
		213	* In case the DTB is not located in a memory region we won't
		214	* be able to locate it later on via the linear mapping and
		215	* get a segfault when accessing it via __va(dtb_early_pa).
		216	* To avoid this situation copy DTB to a memory region.
		217	* Note that memblock_phys_alloc will also reserve DTB region.
		218	*/
		219	if (!memblock_is_memory(dtb_early_pa)) {
		220	size_t fdt_size = fdt_totalsize(dtb_early_va);
		221	phys_addr_t new_dtb_early_pa = memblock_phys_alloc(fdt_size, PAGE_SIZE);
		222	void *new_dtb_early_va = early_memremap(new_dtb_early_pa, fdt_size);
		223
		224	memcpy(new_dtb_early_va, dtb_early_va, fdt_size);
		225	early_memunmap(new_dtb_early_va, fdt_size);
		226	_dtb_early_pa = new_dtb_early_pa;
		227	} else
		228	memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));
		229	}
213		230
214	early_init_fdt_scan_reserved_mem();	231	early_init_fdt_scan_reserved_mem();
215	dma_contiguous_reserve(dma32_phys_limit);	232	dma_contiguous_reserve(dma32_phys_limit);

arch/s390/Makefile+10−0

@@ -30,6 +30,16 @@ KBUILD_CFLAGS_DECOMPRESSOR += -fno-stack-protector · 29 unmodified lines
30	KBUILD_CFLAGS_DECOMPRESSOR += $(call cc-disable-warning, address-of-packed-member)	30	KBUILD_CFLAGS_DECOMPRESSOR += $(call cc-disable-warning, address-of-packed-member)
31	KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO),-g)	31	KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO),-g)
32	KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO_DWARF4), $(call cc-option, -gdwarf-4,))	32	KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO_DWARF4), $(call cc-option, -gdwarf-4,))
		33
		34	ifdef CONFIG_CC_IS_GCC
		35	ifeq ($(call cc-ifversion, -ge, 1200, y), y)
		36	ifeq ($(call cc-ifversion, -lt, 1300, y), y)
		37	KBUILD_CFLAGS += $(call cc-disable-warning, array-bounds)
		38	KBUILD_CFLAGS_DECOMPRESSOR += $(call cc-disable-warning, array-bounds)
		39	endif
		40	endif
		41	endif
		42
33	UTS_MACHINE := s390x	43	UTS_MACHINE := s390x
34	STACK_SIZE := $(if $(CONFIG_KASAN),65536,16384)	44	STACK_SIZE := $(if $(CONFIG_KASAN),65536,16384)
35	CHECKFLAGS += -D__s390__ -D__s390x__	45	CHECKFLAGS += -D__s390__ -D__s390x__

arch/s390/kvm/kvm-s390.c+10−1

@@ -2384,7 +2384,16 @@ static int kvm_s390_vm_mem_op(struct kvm kvm, struct kvm_s390_mem_op mop) · 2383 unmodified lines
2384	return -EINVAL;	2384	return -EINVAL;
2385	if (mop->size > MEM_OP_MAX_SIZE)	2385	if (mop->size > MEM_OP_MAX_SIZE)
2386	return -E2BIG;	2386	return -E2BIG;
2387	if (kvm_s390_pv_is_protected(kvm))	2387	/*
		2388	* This is technically a heuristic only, if the kvm->lock is not
		2389	* taken, it is not guaranteed that the vm is/remains non-protected.
		2390	* This is ok from a kernel perspective, wrongdoing is detected
		2391	* on the access, -EFAULT is returned and the vm may crash the
		2392	* next time it accesses the memory in question.
		2393	* There is no sane usecase to do switching and a memop on two
		2394	* different CPUs at the same time.
		2395	*/
		2396	if (kvm_s390_pv_get_handle(kvm))
2388	return -EINVAL;	2397	return -EINVAL;
2389	if (mop->flags & KVM_S390_MEMOP_F_SKEY_PROTECTION) {	2398	if (mop->flags & KVM_S390_MEMOP_F_SKEY_PROTECTION) {
2390	if (access_key_invalid(mop->key))	2399	if (access_key_invalid(mop->key))

arch/s390/mm/gmap.c+7−0

 static inline void gmap_insert_rmap(struct gmap *sg, unsigned long vmaddr,
 				    struct gmap_rmap *rmap)
 {
+	struct gmap_rmap *temp;
 	void __rcu **slot;
 	BUG_ON(!gmap_is_shadow(sg));
 	if (slot) {
 		rmap->next = radix_tree_deref_slot_protected(slot,
 							&sg->guest_table_lock);
+		for (temp = rmap->next; temp; temp = temp->next) {
+			if (temp->raddr == rmap->raddr) {
+				kfree(rmap);
+				return;
+			}
+		}
 		radix_tree_replace_slot(&sg->host_to_rmap, slot, rmap);
 	} else {
 		rmap->next = NULL;

arch/x86/Kconfig+1−1

@@ -1866,7 +1866,7 @@ config X86_KERNEL_IBT · 1865 unmodified lines
1866	code with them to make this happen.	1866	code with them to make this happen.
1867		1867
1868	In addition to building the kernel with IBT, seal all functions that	1868	In addition to building the kernel with IBT, seal all functions that
1869	are not indirect call targets, avoiding them ever becomming one.	1869	are not indirect call targets, avoiding them ever becoming one.
1870		1870
1871	This requires LTO like objtool runs and will slow down the build. It	1871	This requires LTO like objtool runs and will slow down the build. It
1872	does significantly reduce the number of ENDBR instructions in the	1872	does significantly reduce the number of ENDBR instructions in the

arch/x86/entry/entry_64.S+3−0

@@ -337,6 +337,9 @@ SYM_CODE_END(ret_from_fork) · 336 unmodified lines
337		337
338	call \cfunc	338	call \cfunc
339		339
		340	/* For some configurations \cfunc ends up being a noreturn. */
		341	REACHABLE
		342
340	jmp error_return	343	jmp error_return
341	.endm	344	.endm
342		345

arch/x86/include/asm/intel-family.h+3−0

  *		_G	- parts with extra graphics on
  *		_X	- regular server parts
  *		_D	- micro server parts
+ *		_N,_P	- other mobile parts
  *
  *		Historical OPTDIFFs:
  *
 #define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */
+#define INTEL_FAM6_ALDERLAKE_N		0xBE
 #define INTEL_FAM6_RAPTORLAKE		0xB7
+#define INTEL_FAM6_RAPTORLAKE_P		0xBA
 /* "Small Core" Processors (Atom) */

arch/x86/include/asm/microcode.h+2−0

 extern void load_ucode_ap(void);
 void reload_early_microcode(void);
 extern bool initrd_gone;
+void microcode_bsp_resume(void);
 #else
 static inline void __init load_ucode_bsp(void)			{ }
 static inline void load_ucode_ap(void)				{ }
 static inline void reload_early_microcode(void)			{ }
+static inline void microcode_bsp_resume(void)			{ }
 #endif
 #endif /* _ASM_X86_MICROCODE_H */

arch/x86/include/asm/pgtable_types.h+0−4

 extern pte_t *lookup_address(unsigned long address, unsigned int *level);
 extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
 				    unsigned int *level);
-struct mm_struct;
-extern pte_t *lookup_address_in_mm(struct mm_struct *mm, unsigned long address,
-				   unsigned int *level);
 extern pmd_t *lookup_pmd_address(unsigned long address);
 extern phys_addr_t slow_virt_to_phys(void *__address);
 extern int __init kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn,

arch/x86/include/asm/static_call.h+1−0

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	".align 4 \n" \	26	".align 4 \n" \
27	".globl " STATIC_CALL_TRAMP_STR(name) " \n" \	27	".globl " STATIC_CALL_TRAMP_STR(name) " \n" \
28	STATIC_CALL_TRAMP_STR(name) ": \n" \	28	STATIC_CALL_TRAMP_STR(name) ": \n" \
		29	ANNOTATE_NOENDBR \
29	insns " \n" \	30	insns " \n" \
30	".byte 0x53, 0x43, 0x54 \n" \	31	".byte 0x53, 0x43, 0x54 \n" \
31	".type " STATIC_CALL_TRAMP_STR(name) ", @function \n" \	32	".type " STATIC_CALL_TRAMP_STR(name) ", @function \n" \

arch/x86/kernel/cpu/microcode/core.c+3−3

@@ -758,9 +758,9 @@ static struct subsys_interface mc_cpu_interface = { · 757 unmodified lines
758	};	758	};
759		759
760	/**	760	/**
761	* mc_bp_resume - Update boot CPU microcode during resume.	761	* microcode_bsp_resume - Update boot CPU microcode during resume.
762	*/	762	*/
763	static void mc_bp_resume(void)	763	void microcode_bsp_resume(void)
764	{	764	{
765	int cpu = smp_processor_id();	765	int cpu = smp_processor_id();
766	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;	766	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
@@ -772,7 +772,7 @@ static void mc_bp_resume(void) · 5 unmodified lines
772	}	772	}
773		773
774	static struct syscore_ops mc_syscore_ops = {	774	static struct syscore_ops mc_syscore_ops = {
775	.resume = mc_bp_resume,	775	.resume = microcode_bsp_resume,
776	};	776	};
777		777
778	static int mc_cpu_starting(unsigned int cpu)	778	static int mc_cpu_starting(unsigned int cpu)

arch/x86/kernel/fpu/core.c+26−41

@@ -41,17 +41,7 @@ struct fpu_state_config fpu_user_cfg __ro_after_init; · 40 unmodified lines
41	*/	41	*/
42	struct fpstate init_fpstate __ro_after_init;	42	struct fpstate init_fpstate __ro_after_init;
43		43
44	/*	44	/* Track in-kernel FPU usage */
45	* Track whether the kernel is using the FPU state
46	* currently.
47	*
48	* This flag is used:
49	*
50	* - by IRQ context code to potentially use the FPU
51	* if it's unused.
52	*
53	* - to debug kernel_fpu_begin()/end() correctness
54	*/
55	static DEFINE_PER_CPU(bool, in_kernel_fpu);	45	static DEFINE_PER_CPU(bool, in_kernel_fpu);
56		46
57	/*	47	/*
@@ -59,42 +49,37 @@ static DEFINE_PER_CPU(bool, in_kernel_fpu); · 1 unmodified line
59	*/	49	*/
60	DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);	50	DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
61		51
62	static bool kernel_fpu_disabled(void)
63	{
64	return this_cpu_read(in_kernel_fpu);
65	}
66
67	static bool interrupted_kernel_fpu_idle(void)
68	{
69	return !kernel_fpu_disabled();
70	}
71
72	/*
73	* Were we in user mode (or vm86 mode) when we were
74	* interrupted?
75	*
76	* Doing kernel_fpu_begin/end() is ok if we are running
77	* in an interrupt context from user mode - we'll just
78	* save the FPU state as required.
79	*/
80	static bool interrupted_user_mode(void)
81	{
82	struct pt_regs *regs = get_irq_regs();
83	return regs && user_mode(regs);
84	}
85
86	/*	52	/*
87	* Can we use the FPU in kernel mode with the	53	* Can we use the FPU in kernel mode with the
88	* whole "kernel_fpu_begin/end()" sequence?	54	* whole "kernel_fpu_begin/end()" sequence?
89	*
90	* It's always ok in process context (ie "not interrupt")
91	* but it is sometimes ok even from an irq.
92	*/	55	*/
93	bool irq_fpu_usable(void)	56	bool irq_fpu_usable(void)
94	{	57	{
95	return !in_interrupt() \|\|	58	if (WARN_ON_ONCE(in_nmi()))
96	interrupted_user_mode() \|\|	59	return false;
97	interrupted_kernel_fpu_idle();	60
		61	/* In kernel FPU usage already active? */
		62	if (this_cpu_read(in_kernel_fpu))
		63	return false;
		64
		65	/*
		66	* When not in NMI or hard interrupt context, FPU can be used in:
		67	*
		68	* - Task context except from within fpregs_lock()'ed critical
		69	* regions.
		70	*
		71	* - Soft interrupt processing context which cannot happen
		72	* while in a fpregs_lock()'ed critical region.
		73	*/
		74	if (!in_hardirq())
		75	return true;
		76
		77	/*
		78	* In hard interrupt context it's safe when soft interrupts
		79	* are enabled, which means the interrupt did not hit in
		80	* a fpregs_lock()'ed critical region.
		81	*/
		82	return !softirq_count();
98	}	83	}
99	EXPORT_SYMBOL(irq_fpu_usable);	84	EXPORT_SYMBOL(irq_fpu_usable);
100		85

arch/x86/kernel/unwind_orc.c+4−4

 	struct stack_info *info = &state->stack_info;
 	void *addr = (void *)_addr;
-	if (!on_stack(info, addr, len) &&
+	if (on_stack(info, addr, len))
-	    (get_stack_info(addr, state->task, info, &state->stack_mask)))
+		return true;
-		return false;
-	return true;
+	return !get_stack_info(addr, state->task, info, &state->stack_mask) &&
+		on_stack(info, addr, len);
 }
 static bool deref_stack_reg(struct unwind_state *state, unsigned long addr,

arch/x86/kvm/cpuid.c+19−5

 		union cpuid10_eax eax;
 		union cpuid10_edx edx;
+		if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
+			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
+			break;
+		}
 		perf_get_x86_pmu_capability(&cap);
 		/*
 	case 0x80000000:
 		entry->eax = min(entry->eax, 0x80000021);
 		/*
-		 * Serializing LFENCE is reported in a multitude of ways,
+		 * Serializing LFENCE is reported in a multitude of ways, and
-		 * and NullSegClearsBase is not reported in CPUID on Zen2;
+		 * NullSegClearsBase is not reported in CPUID on Zen2; help
-		 * help userspace by providing the CPUID leaf ourselves.
+		 * userspace by providing the CPUID leaf ourselves.
+		 *
+		 * However, only do it if the host has CPUID leaf 0x8000001d.
+		 * QEMU thinks that it can query the host blindly for that
+		 * CPUID leaf if KVM reports that it supports 0x8000001d or
+		 * above.  The processor merrily returns values from the
+		 * highest Intel leaf which QEMU tries to use as the guest's
+		 * 0x8000001d.  Even worse, this can result in an infinite
+		 * loop if said highest leaf has no subleaves indexed by ECX.
 		 */
-		if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
+		if (entry->eax >= 0x8000001d &&
-		    || !static_cpu_has_bug(X86_BUG_NULL_SEG))
+		    (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
+		     || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
 			entry->eax = max(entry->eax, 0x80000021);
 		break;
 	case 0x80000001:

arch/x86/kvm/mmu.h+24−0

@@ -65,6 +65,30 @@ static __always_inline u64 rsvd_bits(int s, int e) · 64 unmodified lines
65	return ((2ULL << (e - s)) - 1) << s;	65	return ((2ULL << (e - s)) - 1) << s;
66	}	66	}
67		67
		68	/*
		69	* The number of non-reserved physical address bits irrespective of features
		70	* that repurpose legal bits, e.g. MKTME.
		71	*/
		72	extern u8 __read_mostly shadow_phys_bits;
		73
		74	static inline gfn_t kvm_mmu_max_gfn(void)
		75	{
		76	/*
		77	* Note that this uses the host MAXPHYADDR, not the guest's.
		78	* EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
		79	* assuming KVM is running on bare metal, guest accesses beyond
		80	* host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
		81	* (either EPT Violation/Misconfig or #NPF), and so KVM will never
		82	* install a SPTE for such addresses. If KVM is running as a VM
		83	* itself, on the other hand, it might see a MAXPHYADDR that is less
		84	* than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
		85	* disallows such SPTEs entirely and simplifies the TDP MMU.
		86	*/
		87	int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52;
		88
		89	return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
		90	}
		91
68	void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);	92	void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
69	void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);	93	void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
70		94

arch/x86/kvm/mmu/mmu.c+55−36

 }
 #endif
-static bool spte_has_volatile_bits(u64 spte)
-{
-	if (!is_shadow_present_pte(spte))
-		return false;
-	/*
-	 * Always atomically update spte if it can be updated
-	 * out of mmu-lock, it can ensure dirty bit is not lost,
-	 * also, it can help us to get a stable is_writable_pte()
-	 * to ensure tlb flush is not missed.
-	 */
-	if (spte_can_locklessly_be_made_writable(spte) ||
-	    is_access_track_spte(spte))
-		return true;
-	if (spte_ad_enabled(spte)) {
-		if ((spte & shadow_accessed_mask) == 0 ||
-	    	    (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
-			return true;
-	}
-	return false;
-}
 /* Rules for using mmu_spte_set:
  * Set the sptep from nonpresent to present.
  * Note: the sptep being assigned *must* be either not present
 	 * we always atomically update it, see the comments in
 	 * spte_has_volatile_bits().
 	 */
-	if (spte_can_locklessly_be_made_writable(old_spte) &&
+	if (is_mmu_writable_spte(old_spte) &&
 	      !is_writable_pte(new_spte))
 		flush = true;
 	u64 old_spte = *sptep;
 	int level = sptep_to_sp(sptep)->role.level;
-	if (!spte_has_volatile_bits(old_spte))
+	if (!is_shadow_present_pte(old_spte) ||
+	    !spte_has_volatile_bits(old_spte))
 		__update_clear_spte_fast(sptep, 0ull);
 	else
 		old_spte = __update_clear_spte_slow(sptep, 0ull);
 	u64 spte = *sptep;
 	if (!is_writable_pte(spte) &&
-	      !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
+	    !(pt_protect && is_mmu_writable_spte(spte)))
 		return false;
 	rmap_printk("spte %p %llx\n", sptep, *sptep);
 				  const struct kvm_memory_slot *slot)
 {
 	unsigned long hva;
-	pte_t *pte;
+	unsigned long flags;
-	int level;
+	int level = PG_LEVEL_4K;
+	pgd_t pgd;
+	p4d_t p4d;
+	pud_t pud;
+	pmd_t pmd;
 	if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
 		return PG_LEVEL_4K;
 	 */
 	hva = __gfn_to_hva_memslot(slot, gfn);
-	pte = lookup_address_in_mm(kvm->mm, hva, &level);
+	/*
-	if (unlikely(!pte))
+	 * Lookup the mapping level in the current mm.  The information
-		return PG_LEVEL_4K;
+	 * may become stale soon, but it is safe to use as long as
+	 * 1) mmu_notifier_retry was checked after taking mmu_lock, and
+	 * 2) mmu_lock is taken now.
+	 *
+	 * We still need to disable IRQs to prevent concurrent tear down
+	 * of page tables.
+	 */
+	local_irq_save(flags);
+	pgd = READ_ONCE(*pgd_offset(kvm->mm, hva));
+	if (pgd_none(pgd))
+		goto out;
+	p4d = READ_ONCE(*p4d_offset(&pgd, hva));
+	if (p4d_none(p4d) || !p4d_present(p4d))
+		goto out;
+	pud = READ_ONCE(*pud_offset(&p4d, hva));
+	if (pud_none(pud) || !pud_present(pud))
+		goto out;
+	if (pud_large(pud)) {
+		level = PG_LEVEL_1G;
+		goto out;
+	}
+	pmd = READ_ONCE(*pmd_offset(&pud, hva));
+	if (pmd_none(pmd) || !pmd_present(pmd))
+		goto out;
+	if (pmd_large(pmd))
+		level = PG_LEVEL_2M;
+out:
+	local_irq_restore(flags);
 	return level;
 }
 		/*
 		 * If MMIO caching is disabled, emulate immediately without
 		 * touching the shadow page tables as attempting to install an
-		 * MMIO SPTE will just be an expensive nop.
+		 * MMIO SPTE will just be an expensive nop.  Do not cache MMIO
+		 * whose gfn is greater than host.MAXPHYADDR, any guest that
+		 * generates such gfns is running nested and is being tricked
+		 * by L0 userspace (you can observe gfn > L1.MAXPHYADDR if
+		 * and only if L1's MAXPHYADDR is inaccurate with respect to
+		 * the hardware's).
 		 */
-		if (unlikely(!shadow_mmio_value)) {
+		if (unlikely(!shadow_mmio_value) ||
+		    unlikely(fault->gfn > kvm_mmu_max_gfn())) {
 			*ret_val = RET_PF_EMULATE;
 			return true;
 		}
 		 * be removed in the fast path only if the SPTE was
 		 * write-protected for dirty-logging or access tracking.
 		 */
-		if (fault->write &&
+		if (fault->write && is_mmu_writable_spte(spte)) {
-		    spte_can_locklessly_be_made_writable(spte)) {
 			new_spte |= PT_WRITABLE_MASK;
 			/*

arch/x86/kvm/mmu/spte.c+28−0

@@ -90,6 +90,34 @@ static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) · 89 unmodified lines
90	E820_TYPE_RAM);	90	E820_TYPE_RAM);
91	}	91	}
92		92
		93	/*
		94	* Returns true if the SPTE has bits that may be set without holding mmu_lock.
		95	* The caller is responsible for checking if the SPTE is shadow-present, and
		96	* for determining whether or not the caller cares about non-leaf SPTEs.
		97	*/
		98	bool spte_has_volatile_bits(u64 spte)
		99	{
		100	/*
		101	* Always atomically update spte if it can be updated
		102	* out of mmu-lock, it can ensure dirty bit is not lost,
		103	* also, it can help us to get a stable is_writable_pte()
		104	* to ensure tlb flush is not missed.
		105	*/
		106	if (!is_writable_pte(spte) && is_mmu_writable_spte(spte))
		107	return true;
		108
		109	if (is_access_track_spte(spte))
		110	return true;
		111
		112	if (spte_ad_enabled(spte)) {
		113	if (!(spte & shadow_accessed_mask) \|\|
		114	(is_writable_pte(spte) && !(spte & shadow_dirty_mask)))
		115	return true;
		116	}
		117
		118	return false;
		119	}
		120
93	bool make_spte(struct kvm_vcpu vcpu, struct kvm_mmu_page sp,	121	bool make_spte(struct kvm_vcpu vcpu, struct kvm_mmu_page sp,
94	const struct kvm_memory_slot *slot,	122	const struct kvm_memory_slot *slot,
95	unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn,	123	unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn,

arch/x86/kvm/mmu/spte.h+3−7

  */
 extern u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
-/*
- * The number of non-reserved physical address bits irrespective of features
- * that repurpose legal bits, e.g. MKTME.
- */
-extern u8 __read_mostly shadow_phys_bits;
 static inline bool is_mmio_spte(u64 spte)
 {
 	return (spte & shadow_mmio_mask) == shadow_mmio_value &&
 			  "kvm: Writable SPTE is not MMU-writable: %llx", spte);
 }
-static inline bool spte_can_locklessly_be_made_writable(u64 spte)
+static inline bool is_mmu_writable_spte(u64 spte)
 {
 	return spte & shadow_mmu_writable_mask;
 }
 	return gen;
 }
+bool spte_has_volatile_bits(u64 spte);
 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 	       const struct kvm_memory_slot *slot,
 	       unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn,

arch/x86/kvm/mmu/tdp_iter.h+32−2

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	#include <linux/kvm_host.h>	6	#include <linux/kvm_host.h>
7		7
8	#include "mmu.h"	8	#include "mmu.h"
		9	#include "spte.h"
9		10
10	/*	11	/*
11	* TDP MMU SPTEs are RCU protected to allow paging structures (non-leaf SPTEs)	12	* TDP MMU SPTEs are RCU protected to allow paging structures (non-leaf SPTEs)
@@ -17,9 +18,38 @@ static inline u64 kvm_tdp_mmu_read_spte(tdp_ptep_t sptep) · 5 unmodified lines
17	{	18	{
18	return READ_ONCE(*rcu_dereference(sptep));	19	return READ_ONCE(*rcu_dereference(sptep));
19	}	20	}
20	static inline void kvm_tdp_mmu_write_spte(tdp_ptep_t sptep, u64 val)	21
		22	static inline u64 kvm_tdp_mmu_write_spte_atomic(tdp_ptep_t sptep, u64 new_spte)
		23	{
		24	return xchg(rcu_dereference(sptep), new_spte);
		25	}
		26
		27	static inline void __kvm_tdp_mmu_write_spte(tdp_ptep_t sptep, u64 new_spte)
		28	{
		29	WRITE_ONCE(*rcu_dereference(sptep), new_spte);
		30	}
		31
		32	static inline u64 kvm_tdp_mmu_write_spte(tdp_ptep_t sptep, u64 old_spte,
		33	u64 new_spte, int level)
21	{	34	{
22	WRITE_ONCE(*rcu_dereference(sptep), val);	35	/*
		36	* Atomically write the SPTE if it is a shadow-present, leaf SPTE with
		37	* volatile bits, i.e. has bits that can be set outside of mmu_lock.
		38	* The Writable bit can be set by KVM's fast page fault handler, and
		39	* Accessed and Dirty bits can be set by the CPU.
		40	*
		41	* Note, non-leaf SPTEs do have Accessed bits and those bits are
		42	* technically volatile, but KVM doesn't consume the Accessed bit of
		43	* non-leaf SPTEs, i.e. KVM doesn't care if it clobbers the bit. This
		44	* logic needs to be reassessed if KVM were to use non-leaf Accessed
		45	* bits, e.g. to skip stepping down into child SPTEs when aging SPTEs.
		46	*/
		47	if (is_shadow_present_pte(old_spte) && is_last_spte(old_spte, level) &&
		48	spte_has_volatile_bits(old_spte))
		49	return kvm_tdp_mmu_write_spte_atomic(sptep, new_spte);
		50
		51	__kvm_tdp_mmu_write_spte(sptep, new_spte);
		52	return old_spte;
23	}	53	}
24		54
25	/*	55	/*

arch/x86/kvm/mmu/tdp_mmu.c+61−36

 	tdp_mmu_unlink_sp(kvm, sp, shared);
 	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
-		u64 *sptep = rcu_dereference(pt) + i;
+		tdp_ptep_t sptep = pt + i;
 		gfn_t gfn = base_gfn + i * KVM_PAGES_PER_HPAGE(level);
-		u64 old_child_spte;
+		u64 old_spte;
 		if (shared) {
 			/*
 			 * value to the removed SPTE value.
 			 */
 			for (;;) {
-				old_child_spte = xchg(sptep, REMOVED_SPTE);
+				old_spte = kvm_tdp_mmu_write_spte_atomic(sptep, REMOVED_SPTE);
-				if (!is_removed_spte(old_child_spte))
+				if (!is_removed_spte(old_spte))
 					break;
 				cpu_relax();
 			}
 			 * are guarded by the memslots generation, not by being
 			 * unreachable.
 			 */
-			old_child_spte = READ_ONCE(*sptep);
+			old_spte = kvm_tdp_mmu_read_spte(sptep);
-			if (!is_shadow_present_pte(old_child_spte))
+			if (!is_shadow_present_pte(old_spte))
 				continue;
 			/*
-			 * Marking the SPTE as a removed SPTE is not
+			 * Use the common helper instead of a raw WRITE_ONCE as
-			 * strictly necessary here as the MMU lock will
+			 * the SPTE needs to be updated atomically if it can be
-			 * stop other threads from concurrently modifying
+			 * modified by a different vCPU outside of mmu_lock.
-			 * this SPTE. Using the removed SPTE value keeps
+			 * Even though the parent SPTE is !PRESENT, the TLB
-			 * the two branches consistent and simplifies
+			 * hasn't yet been flushed, and both Intel and AMD
-			 * the function.
+			 * document that A/D assists can use upper-level PxE
+			 * entries that are cached in the TLB, i.e. the CPU can
+			 * still access the page and mark it dirty.
+			 *
+			 * No retry is needed in the atomic update path as the
+			 * sole concern is dropping a Dirty bit, i.e. no other
+			 * task can zap/remove the SPTE as mmu_lock is held for
+			 * write.  Marking the SPTE as a removed SPTE is not
+			 * strictly necessary for the same reason, but using
+			 * the remove SPTE value keeps the shared/exclusive
+			 * paths consistent and allows the handle_changed_spte()
+			 * call below to hardcode the new value to REMOVED_SPTE.
+			 *
+			 * Note, even though dropping a Dirty bit is the only
+			 * scenario where a non-atomic update could result in a
+			 * functional bug, simply checking the Dirty bit isn't
+			 * sufficient as a fast page fault could read the upper
+			 * level SPTE before it is zapped, and then make this
+			 * target SPTE writable, resume the guest, and set the
+			 * Dirty bit between reading the SPTE above and writing
+			 * it here.
 			 */
-			WRITE_ONCE(*sptep, REMOVED_SPTE);
+			old_spte = kvm_tdp_mmu_write_spte(sptep, old_spte,
+							  REMOVED_SPTE, level);
 		}
 		handle_changed_spte(kvm, kvm_mmu_page_as_id(sp), gfn,
-				    old_child_spte, REMOVED_SPTE, level,
+				    old_spte, REMOVED_SPTE, level, shared);
-				    shared);
 	}
 	call_rcu(&sp->rcu_head, tdp_mmu_free_sp_rcu_callback);
 					   KVM_PAGES_PER_HPAGE(iter->level));
 	/*
-	 * No other thread can overwrite the removed SPTE as they
+	 * No other thread can overwrite the removed SPTE as they must either
-	 * must either wait on the MMU lock or use
+	 * wait on the MMU lock or use tdp_mmu_set_spte_atomic() which will not
-	 * tdp_mmu_set_spte_atomic which will not overwrite the
+	 * overwrite the special removed SPTE value. No bookkeeping is needed
-	 * special removed SPTE value. No bookkeeping is needed
+	 * here since the SPTE is going from non-present to non-present.  Use
-	 * here since the SPTE is going from non-present
+	 * the raw write helper to avoid an unnecessary check on volatile bits.
-	 * to non-present.
 	 */
-	kvm_tdp_mmu_write_spte(iter->sptep, 0);
+	__kvm_tdp_mmu_write_spte(iter->sptep, 0);
 	return 0;
 }
  *		      unless performing certain dirty logging operations.
  *		      Leaving record_dirty_log unset in that case prevents page
  *		      writes from being double counted.
+ *
+ * Returns the old SPTE value, which _may_ be different than @old_spte if the
+ * SPTE had voldatile bits.
  */
-static void __tdp_mmu_set_spte(struct kvm *kvm, int as_id, tdp_ptep_t sptep,
+static u64 __tdp_mmu_set_spte(struct kvm *kvm, int as_id, tdp_ptep_t sptep,
-			       u64 old_spte, u64 new_spte, gfn_t gfn, int level,
+			      u64 old_spte, u64 new_spte, gfn_t gfn, int level,
-			       bool record_acc_track, bool record_dirty_log)
+			      bool record_acc_track, bool record_dirty_log)
 {
 	lockdep_assert_held_write(&kvm->mmu_lock);
 	 */
 	WARN_ON(is_removed_spte(old_spte) || is_removed_spte(new_spte));
-	kvm_tdp_mmu_write_spte(sptep, new_spte);
+	old_spte = kvm_tdp_mmu_write_spte(sptep, old_spte, new_spte, level);
 	__handle_changed_spte(kvm, as_id, gfn, old_spte, new_spte, level, false);
 	if (record_dirty_log)
 		handle_changed_spte_dirty_log(kvm, as_id, gfn, old_spte,
 					      new_spte, level);
+	return old_spte;
 }
 static inline void _tdp_mmu_set_spte(struct kvm *kvm, struct tdp_iter *iter,
 {
 	WARN_ON_ONCE(iter->yielded);
-	__tdp_mmu_set_spte(kvm, iter->as_id, iter->sptep, iter->old_spte,
+	iter->old_spte = __tdp_mmu_set_spte(kvm, iter->as_id, iter->sptep,
-			   new_spte, iter->gfn, iter->level,
+					    iter->old_spte, new_spte,
-			   record_acc_track, record_dirty_log);
+					    iter->gfn, iter->level,
+					    record_acc_track, record_dirty_log);
 }
 static inline void tdp_mmu_set_spte(struct kvm *kvm, struct tdp_iter *iter,
 	return iter->yielded;
 }
-static inline gfn_t tdp_mmu_max_gfn_host(void)
+static inline gfn_t tdp_mmu_max_gfn_exclusive(void)
 {
 	/*
-	 * Bound TDP MMU walks at host.MAXPHYADDR, guest accesses beyond that
+	 * Bound TDP MMU walks at host.MAXPHYADDR.  KVM disallows memslots with
-	 * will hit a #PF(RSVD) and never hit an EPT Violation/Misconfig / #NPF,
+	 * a gpa range that would exceed the max gfn, and KVM does not create
-	 * and so KVM will never install a SPTE for such addresses.
+	 * MMIO SPTEs for "impossible" gfns, instead sending such accesses down
+	 * the slow emulation path every time.
 	 */
-	return 1ULL << (shadow_phys_bits - PAGE_SHIFT);
+	return kvm_mmu_max_gfn() + 1;
 }
 static void __tdp_mmu_zap_root(struct kvm *kvm, struct kvm_mmu_page *root,
 {
 	struct tdp_iter iter;
-	gfn_t end = tdp_mmu_max_gfn_host();
+	gfn_t end = tdp_mmu_max_gfn_exclusive();
 	gfn_t start = 0;
 	for_each_tdp_pte_min_level(iter, root, zap_level, start, end) {
 {
 	struct tdp_iter iter;
-	end = min(end, tdp_mmu_max_gfn_host());
+	end = min(end, tdp_mmu_max_gfn_exclusive());
 	lockdep_assert_held_write(&kvm->mmu_lock);

arch/x86/kvm/svm/pmu.c+25−3

 	[7] = { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
 };
+/* duplicated from amd_f17h_perfmon_event_map. */
+static struct kvm_event_hw_type_mapping amd_f17h_event_mapping[] = {
+	[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
+	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
+	[2] = { 0x60, 0xff, PERF_COUNT_HW_CACHE_REFERENCES },
+	[3] = { 0x64, 0x09, PERF_COUNT_HW_CACHE_MISSES },
+	[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
+	[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
+	[6] = { 0x87, 0x02, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
+	[7] = { 0x87, 0x01, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
+};
+/* amd_pmc_perf_hw_id depends on these being the same size */
+static_assert(ARRAY_SIZE(amd_event_mapping) ==
+	     ARRAY_SIZE(amd_f17h_event_mapping));
 static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type)
 {
 	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
 static unsigned int amd_pmc_perf_hw_id(struct kvm_pmc *pmc)
 {
+	struct kvm_event_hw_type_mapping *event_mapping;
 	u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
 	u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
 	int i;
 	if (WARN_ON(pmc_is_fixed(pmc)))
 		return PERF_COUNT_HW_MAX;
+	if (guest_cpuid_family(pmc->vcpu) >= 0x17)
+		event_mapping = amd_f17h_event_mapping;
+	else
+		event_mapping = amd_event_mapping;
 	for (i = 0; i < ARRAY_SIZE(amd_event_mapping); i++)
-		if (amd_event_mapping[i].eventsel == event_select
+		if (event_mapping[i].eventsel == event_select
-		    && amd_event_mapping[i].unit_mask == unit_mask)
+		    && event_mapping[i].unit_mask == unit_mask)
 			break;
 	if (i == ARRAY_SIZE(amd_event_mapping))
 		return PERF_COUNT_HW_MAX;
-	return amd_event_mapping[i].event_type;
+	return event_mapping[i].event_type;
 }
 /* check if a PMC is enabled by comparing it against global_ctrl bits. Because

arch/x86/kvm/svm/sev.c+38−4

 	atomic_set_release(&src_sev->migration_in_progress, 0);
 }
+/* vCPU mutex subclasses.  */
+enum sev_migration_role {
+	SEV_MIGRATION_SOURCE = 0,
+	SEV_MIGRATION_TARGET,
+	SEV_NR_MIGRATION_ROLES,
+};
-static int sev_lock_vcpus_for_migration(struct kvm *kvm)
+static int sev_lock_vcpus_for_migration(struct kvm *kvm,
+					enum sev_migration_role role)
 {
 	struct kvm_vcpu *vcpu;
 	unsigned long i, j;
+	bool first = true;
 	kvm_for_each_vcpu(i, vcpu, kvm) {
-		if (mutex_lock_killable(&vcpu->mutex))
+		if (mutex_lock_killable_nested(&vcpu->mutex, role))
 			goto out_unlock;
+		if (first) {
+			/*
+			 * Reset the role to one that avoids colliding with
+			 * the role used for the first vcpu mutex.
+			 */
+			role = SEV_NR_MIGRATION_ROLES;
+			first = false;
+		} else {
+			mutex_release(&vcpu->mutex.dep_map, _THIS_IP_);
+		}
 	}
 	return 0;
 out_unlock:
+	first = true;
 	kvm_for_each_vcpu(j, vcpu, kvm) {
 		if (i == j)
 			break;
+		if (first)
+			first = false;
+		else
+			mutex_acquire(&vcpu->mutex.dep_map, role, 0, _THIS_IP_);
 		mutex_unlock(&vcpu->mutex);
 	}
 	return -EINTR;
 {
 	struct kvm_vcpu *vcpu;
 	unsigned long i;
+	bool first = true;
 	kvm_for_each_vcpu(i, vcpu, kvm) {
+		if (first)
+			first = false;
+		else
+			mutex_acquire(&vcpu->mutex.dep_map,
+				      SEV_NR_MIGRATION_ROLES, 0, _THIS_IP_);
 		mutex_unlock(&vcpu->mutex);
 	}
 }
 		charged = true;
 	}
-	ret = sev_lock_vcpus_for_migration(kvm);
+	ret = sev_lock_vcpus_for_migration(kvm, SEV_MIGRATION_SOURCE);
 	if (ret)
 		goto out_dst_cgroup;
-	ret = sev_lock_vcpus_for_migration(source_kvm);
+	ret = sev_lock_vcpus_for_migration(source_kvm, SEV_MIGRATION_TARGET);
 	if (ret)
 		goto out_dst_vcpu;

arch/x86/kvm/vmx/vmx.c+1−1

@@ -5472,7 +5472,7 @@ static bool vmx_emulation_required_with_pending_exception(struct kvm_vcpu *vcpu) · 5471 unmodified lines
5472	struct vcpu_vmx *vmx = to_vmx(vcpu);	5472	struct vcpu_vmx *vmx = to_vmx(vcpu);
5473		5473
5474	return vmx->emulation_required && !vmx->rmode.vm86_active &&	5474	return vmx->emulation_required && !vmx->rmode.vm86_active &&
5475	vcpu->arch.exception.pending;	5475	(vcpu->arch.exception.pending \|\| vcpu->arch.exception.injected);
5476	}	5476	}
5477		5477
5478	static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)	5478	static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)

arch/x86/kvm/x86.c+7−1

 		if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
+			vcpu->run->system_event.ndata = 0;
 			r = 0;
 			goto out;
 		}
 		if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
+			vcpu->run->system_event.ndata = 0;
 			r = 0;
 			goto out;
 		}
 				   struct kvm_memory_slot *new,
 				   enum kvm_mr_change change)
 {
-	if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
+	if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
+		if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
+			return -EINVAL;
 		return kvm_alloc_memslot_metadata(kvm, new);
+	}
 	if (change == KVM_MR_FLAGS_ONLY)
 		memcpy(&new->arch, &old->arch, sizeof(old->arch));

arch/x86/lib/copy_user_64.S+52−35

 SYM_FUNC_START(copy_user_generic_unrolled)
 	ASM_STAC
 	cmpl $8,%edx
-	jb 20f		/* less then 8 bytes, go to byte copy loop */
+	jb .Lcopy_user_short_string_bytes
 	ALIGN_DESTINATION
 	movl %edx,%ecx
 	andl $63,%edx
 	shrl $6,%ecx
-	jz .L_copy_short_string
+	jz copy_user_short_string
 1:	movq (%rsi),%r8
 2:	movq 1*8(%rsi),%r9
 3:	movq 2*8(%rsi),%r10
 	leaq 64(%rdi),%rdi
 	decl %ecx
 	jnz 1b
-.L_copy_short_string:
+	jmp copy_user_short_string
-	movl %edx,%ecx
-	andl $7,%edx
-	shrl $3,%ecx
-	jz 20f
-18:	movq (%rsi),%r8
-19:	movq %r8,(%rdi)
-	leaq 8(%rsi),%rsi
-	leaq 8(%rdi),%rdi
-	decl %ecx
-	jnz 18b
-20:	andl %edx,%edx
-	jz 23f
-	movl %edx,%ecx
-21:	movb (%rsi),%al
-22:	movb %al,(%rdi)
-	incq %rsi
-	incq %rdi
-	decl %ecx
-	jnz 21b
-23:	xor %eax,%eax
-	ASM_CLAC
-	RET
 30:	shll $6,%ecx
 	addl %ecx,%edx
-	jmp 60f
+	jmp .Lcopy_user_handle_tail
-40:	leal (%rdx,%rcx,8),%edx
-	jmp 60f
-50:	movl %ecx,%edx
-60:	jmp .Lcopy_user_handle_tail /* ecx is zerorest also */
 	_ASM_EXTABLE_CPY(1b, 30b)
 	_ASM_EXTABLE_CPY(2b, 30b)
 	_ASM_EXTABLE_CPY(14b, 30b)
 	_ASM_EXTABLE_CPY(15b, 30b)
 	_ASM_EXTABLE_CPY(16b, 30b)
-	_ASM_EXTABLE_CPY(18b, 40b)
-	_ASM_EXTABLE_CPY(19b, 40b)
-	_ASM_EXTABLE_CPY(21b, 50b)
-	_ASM_EXTABLE_CPY(22b, 50b)
 SYM_FUNC_END(copy_user_generic_unrolled)
 EXPORT_SYMBOL(copy_user_generic_unrolled)
 SYM_FUNC_START(copy_user_enhanced_fast_string)
 	ASM_STAC
 	/* CPUs without FSRM should avoid rep movsb for short copies */
-	ALTERNATIVE "cmpl $64, %edx; jb .L_copy_short_string", "", X86_FEATURE_FSRM
+	ALTERNATIVE "cmpl $64, %edx; jb copy_user_short_string", "", X86_FEATURE_FSRM
 	movl %edx,%ecx
 1:	rep movsb
 	xorl %eax,%eax
 SYM_CODE_END(.Lcopy_user_handle_tail)
+/*
+ * Finish memcpy of less than 64 bytes.  #AC should already be set.
+ *
+ * Input:
+ * rdi destination
+ * rsi source
+ * rdx count (< 64)
+ *
+ * Output:
+ * eax uncopied bytes or 0 if successful.
+ */
+SYM_CODE_START_LOCAL(copy_user_short_string)
+	movl %edx,%ecx
+	andl $7,%edx
+	shrl $3,%ecx
+	jz .Lcopy_user_short_string_bytes
+18:	movq (%rsi),%r8
+19:	movq %r8,(%rdi)
+	leaq 8(%rsi),%rsi
+	leaq 8(%rdi),%rdi
+	decl %ecx
+	jnz 18b
+.Lcopy_user_short_string_bytes:
+	andl %edx,%edx
+	jz 23f
+	movl %edx,%ecx
+21:	movb (%rsi),%al
+22:	movb %al,(%rdi)
+	incq %rsi
+	incq %rdi
+	decl %ecx
+	jnz 21b
+23:	xor %eax,%eax
+	ASM_CLAC
+	RET
+40:	leal (%rdx,%rcx,8),%edx
+	jmp 60f
+50:	movl %ecx,%edx		/* ecx is zerorest also */
+60:	jmp .Lcopy_user_handle_tail
+	_ASM_EXTABLE_CPY(18b, 40b)
+	_ASM_EXTABLE_CPY(19b, 40b)
+	_ASM_EXTABLE_CPY(21b, 50b)
+	_ASM_EXTABLE_CPY(22b, 50b)
+SYM_CODE_END(copy_user_short_string)
 /*
  * copy_user_nocache - Uncached memory copy with exception handling
  * This will force destination out of cache for more performance.

arch/x86/lib/putuser.S+4−0

 	cmp %_ASM_BX,%_ASM_CX
 	jae .Lbad_put_user
 SYM_INNER_LABEL(__put_user_nocheck_1, SYM_L_GLOBAL)
+	ENDBR
 	ASM_STAC
 1:	movb %al,(%_ASM_CX)
 	xor %ecx,%ecx
 	cmp %_ASM_BX,%_ASM_CX
 	jae .Lbad_put_user
 SYM_INNER_LABEL(__put_user_nocheck_2, SYM_L_GLOBAL)
+	ENDBR
 	ASM_STAC
 2:	movw %ax,(%_ASM_CX)
 	xor %ecx,%ecx
 	cmp %_ASM_BX,%_ASM_CX
 	jae .Lbad_put_user
 SYM_INNER_LABEL(__put_user_nocheck_4, SYM_L_GLOBAL)
+	ENDBR
 	ASM_STAC
 3:	movl %eax,(%_ASM_CX)
 	xor %ecx,%ecx
 	cmp %_ASM_BX,%_ASM_CX
 	jae .Lbad_put_user
 SYM_INNER_LABEL(__put_user_nocheck_8, SYM_L_GLOBAL)
+	ENDBR
 	ASM_STAC
 4:	mov %_ASM_AX,(%_ASM_CX)
 #ifdef CONFIG_X86_32

arch/x86/lib/retpoline.S+1−1

 	.align RETPOLINE_THUNK_SIZE
 SYM_INNER_LABEL(__x86_indirect_thunk_\reg, SYM_L_GLOBAL)
 	UNWIND_HINT_EMPTY
+	ANNOTATE_NOENDBR
 	ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
 		      __stringify(RETPOLINE \reg), X86_FEATURE_RETPOLINE, \
 	.align RETPOLINE_THUNK_SIZE
 SYM_CODE_START(__x86_indirect_thunk_array)
-	ANNOTATE_NOENDBR // apply_retpolines
 #define GEN(reg) THUNK reg
 #include <asm/GEN-for-each-reg.h>

arch/x86/mm/init_64.c+3−2

 static void __meminit vmemmap_use_new_sub_pmd(unsigned long start, unsigned long end)
 {
+	const unsigned long page = ALIGN_DOWN(start, PMD_SIZE);
 	vmemmap_flush_unused_pmd();
 	/*
 	 * Mark with PAGE_UNUSED the unused parts of the new memmap range
 	 */
 	if (!IS_ALIGNED(start, PMD_SIZE))
-		memset((void *)start, PAGE_UNUSED,
+		memset((void *)page, PAGE_UNUSED, start - page);
-			start - ALIGN_DOWN(start, PMD_SIZE));
 	/*
 	 * We want to avoid memset(PAGE_UNUSED) when populating the vmemmap of

arch/x86/mm/pat/set_memory.c+0−11

@@ -638,17 +638,6 @@ pte_t lookup_address(unsigned long address, unsigned int level) · 637 unmodified lines
638	}	638	}
639	EXPORT_SYMBOL_GPL(lookup_address);	639	EXPORT_SYMBOL_GPL(lookup_address);
640		640
641	/*
642	* Lookup the page table entry for a virtual address in a given mm. Return a
643	* pointer to the entry and the level of the mapping.
644	*/
645	pte_t lookup_address_in_mm(struct mm_struct mm, unsigned long address,
646	unsigned int *level)
647	{
648	return lookup_address_in_pgd(pgd_offset(mm, address), address, level);
649	}
650	EXPORT_SYMBOL_GPL(lookup_address_in_mm);
651
652	static pte_t _lookup_address_cpa(struct cpa_data cpa, unsigned long address,	641	static pte_t _lookup_address_cpa(struct cpa_data cpa, unsigned long address,
653	unsigned int *level)	642	unsigned int *level)
654	{	643	{

arch/x86/pci/xen.c+5−1

 		else
 			xen_msi_ops.setup_msi_irqs = xen_setup_msi_irqs;
 		xen_msi_ops.teardown_msi_irqs = xen_pv_teardown_msi_irqs;
-		pci_msi_ignore_mask = 1;
 	} else if (xen_hvm_domain()) {
 		xen_msi_ops.setup_msi_irqs = xen_hvm_setup_msi_irqs;
 		xen_msi_ops.teardown_msi_irqs = xen_teardown_msi_irqs;
 	 * in allocating the native domain and never use it.
 	 */
 	x86_init.irqs.create_pci_msi_domain = xen_create_pci_msi_domain;
+	/*
+	 * With XEN PIRQ/Eventchannels in use PCI/MSI[-X] masking is solely
+	 * controlled by the hypervisor.
+	 */
+	pci_msi_ignore_mask = 1;
 }
 #else /* CONFIG_PCI_MSI */

arch/x86/platform/pvh/head.S+1−0

@@ -50,6 +50,7 @@ · 49 unmodified lines
50	#define PVH_DS_SEL (PVH_GDT_ENTRY_DS * 8)	50	#define PVH_DS_SEL (PVH_GDT_ENTRY_DS * 8)
51		51
52	SYM_CODE_START_LOCAL(pvh_start_xen)	52	SYM_CODE_START_LOCAL(pvh_start_xen)
		53	UNWIND_HINT_EMPTY
53	cld	54	cld
54		55
55	lgdt (_pa(gdt))	56	lgdt (_pa(gdt))

arch/x86/power/cpu.c+9−1

 #include <asm/cpu.h>
 #include <asm/mmu_context.h>
 #include <asm/cpu_device_id.h>
+#include <asm/microcode.h>
 #ifdef CONFIG_X86_32
 __visible unsigned long saved_context_ebx;
 	x86_platform.restore_sched_clock_state();
 	mtrr_bp_restore();
 	perf_restore_debug_store();
-	msr_restore_context(ctxt);
 	c = &cpu_data(smp_processor_id());
 	if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL))
 		init_ia32_feat_ctl(c);
+	microcode_bsp_resume();
+	/*
+	 * This needs to happen after the microcode has been updated upon resume
+	 * because some of the MSRs are "emulated" in microcode.
+	 */
+	msr_restore_context(ctxt);
 }
 /* Needed by apm.c */

arch/x86/xen/xen-head.S+1−0

@@ -45,6 +45,7 @@ SYM_CODE_END(hypercall_page) · 44 unmodified lines
45	__INIT	45	__INIT
46	SYM_CODE_START(startup_xen)	46	SYM_CODE_START(startup_xen)
47	UNWIND_HINT_EMPTY	47	UNWIND_HINT_EMPTY
		48	ANNOTATE_NOENDBR
48	cld	49	cld
49		50
50	/* Clear .bss */	51	/* Clear .bss */

block/bfq-iosched.c+9−3

 	struct bfq_entity *entity = &bfqq->entity;
 	struct bfq_entity *inline_entities[BFQ_LIMIT_INLINE_DEPTH];
 	struct bfq_entity **entities = inline_entities;
-	int depth, level;
+	int depth, level, alloc_depth = BFQ_LIMIT_INLINE_DEPTH;
 	int class_idx = bfqq->ioprio_class - 1;
 	struct bfq_sched_data *sched_data;
 	unsigned long wsum;
 	if (!entity->on_st_or_in_serv)
 		return false;
+retry:
+	spin_lock_irq(&bfqd->lock);
 	/* +1 for bfqq entity, root cgroup not included */
 	depth = bfqg_to_blkg(bfqq_group(bfqq))->blkcg->css.cgroup->level + 1;
-	if (depth > BFQ_LIMIT_INLINE_DEPTH) {
+	if (depth > alloc_depth) {
+		spin_unlock_irq(&bfqd->lock);
+		if (entities != inline_entities)
+			kfree(entities);
 		entities = kmalloc_array(depth, sizeof(*entities), GFP_NOIO);
 		if (!entities)
 			return false;
+		alloc_depth = depth;
+		goto retry;
 	}
-	spin_lock_irq(&bfqd->lock);
 	sched_data = entity->sched_data;
 	/* Gather our ancestors as we need to traverse them in reverse order */
 	level = 0;

block/blk-core.c+0−4

 #include "blk-pm.h"
 #include "blk-cgroup.h"
 #include "blk-throttle.h"
-#include "blk-rq-qos.h"
 struct dentry *blk_debugfs_root;
 	 */
 	blk_freeze_queue(q);
-	/* cleanup rq qos structures for queue without disk */
-	rq_qos_exit(q);
 	blk_queue_flag_set(QUEUE_FLAG_DEAD, q);
 	blk_sync_queue(q);

block/blk-iocost.c+11−1

@@ -2322,7 +2322,17 @@ static void ioc_timer_fn(struct timer_list *timer) · 2321 unmodified lines
2322	iocg->hweight_donating = hwa;	2322	iocg->hweight_donating = hwa;
2323	iocg->hweight_after_donation = new_hwi;	2323	iocg->hweight_after_donation = new_hwi;
2324	list_add(&iocg->surplus_list, &surpluses);	2324	list_add(&iocg->surplus_list, &surpluses);
2325	} else {	2325	} else if (!iocg->abs_vdebt) {
		2326	/*
		2327	* @iocg doesn't have enough to donate. Reset
		2328	* its inuse to active.
		2329	*
		2330	* Don't reset debtors as their inuse's are
		2331	* owned by debt handling. This shouldn't affect
		2332	* donation calculuation in any meaningful way
		2333	* as @iocg doesn't have a meaningful amount of
		2334	* share anyway.
		2335	*/
2326	TRACE_IOCG_PATH(inuse_shortage, iocg, &now,	2336	TRACE_IOCG_PATH(inuse_shortage, iocg, &now,
2327	iocg->inuse, iocg->active,	2337	iocg->inuse, iocg->active,
2328	iocg->hweight_inuse, new_hwi);	2338	iocg->hweight_inuse, new_hwi);

block/blk-mq.c+1−8

 	trace_block_rq_issue(rq);
 	if (test_bit(QUEUE_FLAG_STATS, &q->queue_flags)) {
-		u64 start_time;
+		rq->io_start_time_ns = ktime_get_ns();
-#ifdef CONFIG_BLK_CGROUP
-		if (rq->bio)
-			start_time = bio_issue_time(&rq->bio->bi_issue);
-		else
-#endif
-			start_time = ktime_get_ns();
-		rq->io_start_time_ns = start_time;
 		rq->stats_sectors = blk_rq_sectors(rq);
 		rq->rq_flags |= RQF_STATS;
 		rq_qos_issue(q, rq);

drivers/acpi/processor_idle.c+2−6

 	  DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
 	  DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")},
 	 (void *)1},
-	/* T40 can not handle C3 idle state */
-	{ set_max_cstate, "IBM ThinkPad T40", {
-	  DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
-	  DMI_MATCH(DMI_PRODUCT_NAME, "23737CU")},
-	 (void *)2},
 	{},
 };
 		if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2 ||
 		    cx->type == ACPI_STATE_C3) {
 			state->enter_dead = acpi_idle_play_dead;
-			drv->safe_state_index = count;
+			if (cx->type != ACPI_STATE_C3)
+				drv->safe_state_index = count;
 		}
 		/*
 		 * Halt-induced C1 is not good for ->enter_s2idle, because it

drivers/amba/bus.c+36−1

@@ -20,6 +20,10 @@ · 19 unmodified lines
20	#include <linux/platform_device.h>	20	#include <linux/platform_device.h>
21	#include <linux/reset.h>	21	#include <linux/reset.h>
22	#include <linux/of_irq.h>	22	#include <linux/of_irq.h>
		23	#include <linux/of_device.h>
		24	#include <linux/acpi.h>
		25	#include <linux/iommu.h>
		26	#include <linux/dma-map-ops.h>
23		27
24	#define to_amba_driver(d) container_of(d, struct amba_driver, drv)	28	#define to_amba_driver(d) container_of(d, struct amba_driver, drv)
25		29
@@ -273,6 +277,36 @@ static void amba_shutdown(struct device *dev) · 247 unmodified lines
273	drv->shutdown(to_amba_device(dev));	277	drv->shutdown(to_amba_device(dev));
274	}	278	}
275		279
		280	static int amba_dma_configure(struct device *dev)
		281	{
		282	struct amba_driver *drv = to_amba_driver(dev->driver);
		283	enum dev_dma_attr attr;
		284	int ret = 0;
		285
		286	if (dev->of_node) {
		287	ret = of_dma_configure(dev, dev->of_node, true);
		288	} else if (has_acpi_companion(dev)) {
		289	attr = acpi_get_dma_attr(to_acpi_device_node(dev->fwnode));
		290	ret = acpi_dma_configure(dev, attr);
		291	}
		292
		293	if (!ret && !drv->driver_managed_dma) {
		294	ret = iommu_device_use_default_domain(dev);
		295	if (ret)
		296	arch_teardown_dma_ops(dev);
		297	}
		298
		299	return ret;
		300	}
		301
		302	static void amba_dma_cleanup(struct device *dev)
		303	{
		304	struct amba_driver *drv = to_amba_driver(dev->driver);
		305
		306	if (!drv->driver_managed_dma)
		307	iommu_device_unuse_default_domain(dev);
		308	}
		309
276	#ifdef CONFIG_PM	310	#ifdef CONFIG_PM
277	/*	311	/*
278	* Hooks to provide runtime PM of the pclk (bus clock). It is safe to	312	* Hooks to provide runtime PM of the pclk (bus clock). It is safe to
@@ -341,7 +375,8 @@ struct bus_type amba_bustype = { · 62 unmodified lines
341	.probe = amba_probe,	375	.probe = amba_probe,
342	.remove = amba_remove,	376	.remove = amba_remove,
343	.shutdown = amba_shutdown,	377	.shutdown = amba_shutdown,
344	.dma_configure = platform_dma_configure,	378	.dma_configure = amba_dma_configure,
		379	.dma_cleanup = amba_dma_cleanup,
345	.pm = &amba_pm,	380	.pm = &amba_pm,
346	};	381	};
347	EXPORT_SYMBOL_GPL(amba_bustype);	382	EXPORT_SYMBOL_GPL(amba_bustype);

drivers/android/binder.c+9−1

 {
 	int ret = 0;
 	struct binder_sg_copy *sgc, *tmpsgc;
+	struct binder_ptr_fixup *tmppf;
 	struct binder_ptr_fixup *pf =
 		list_first_entry_or_null(pf_head, struct binder_ptr_fixup,
 					 node);
 		list_del(&sgc->node);
 		kfree(sgc);
 	}
-	BUG_ON(!list_empty(pf_head));
+	list_for_each_entry_safe(pf, tmppf, pf_head, node) {
+		BUG_ON(pf->skip_size == 0);
+		list_del(&pf->node);
+		kfree(pf);
+	}
 	BUG_ON(!list_empty(sgc_head));
 	return ret > 0 ? -EINVAL : ret;
 	struct binder_proc *proc = thread->proc;
 	int ret;
+	if (fda->num_fds == 0)
+		return 0;
 	fd_buf_size = sizeof(u32) * fda->num_fds;
 	if (fda->num_fds >= SIZE_MAX / sizeof(u32)) {
 		binder_user_error("%d:%d got transaction with invalid number of fds (%lld)\n",

drivers/base/arch_topology.c+10−1

 			core_mask = &cpu_topology[cpu].llc_sibling;
 	}
+	/*
+	 * For systems with no shared cpu-side LLC but with clusters defined,
+	 * extend core_mask to cluster_siblings. The sched domain builder will
+	 * then remove MC as redundant with CLS if SCHED_CLUSTER is enabled.
+	 */
+	if (IS_ENABLED(CONFIG_SCHED_CLUSTER) &&
+	    cpumask_subset(core_mask, &cpu_topology[cpu].cluster_sibling))
+		core_mask = &cpu_topology[cpu].cluster_sibling;
 	return core_mask;
 }
 	for_each_online_cpu(cpu) {
 		cpu_topo = &cpu_topology[cpu];
-		if (cpuid_topo->llc_id == cpu_topo->llc_id) {
+		if (cpu_topo->llc_id != -1 && cpuid_topo->llc_id == cpu_topo->llc_id) {
 			cpumask_set_cpu(cpu, &cpuid_topo->llc_sibling);
 			cpumask_set_cpu(cpuid, &cpu_topo->llc_sibling);
 		}

drivers/base/dd.c+5−0

 	if (dev->bus)
 		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
 					     BUS_NOTIFY_DRIVER_NOT_BOUND, dev);
+	if (dev->bus && dev->bus->dma_cleanup)
+		dev->bus->dma_cleanup(dev);
 pinctrl_bind_failed:
 	device_links_no_driver(dev);
 	device_unbind_cleanup(dev);
 		device_remove(dev);
+		if (dev->bus && dev->bus->dma_cleanup)
+			dev->bus->dma_cleanup(dev);
 		device_links_driver_cleanup(dev);
 		device_unbind_cleanup(dev);

drivers/base/firmware_loader/main.c+17−0

 		  size_t offset, u32 opt_flags)
 {
 	struct firmware *fw = NULL;
+	struct cred *kern_cred = NULL;
+	const struct cred *old_cred;
 	bool nondirect = false;
 	int ret;
 	if (ret <= 0) /* error or already assigned */
 		goto out;
+	/*
+	 * We are about to try to access the firmware file. Because we may have been
+	 * called by a driver when serving an unrelated request from userland, we use
+	 * the kernel credentials to read the file.
+	 */
+	kern_cred = prepare_kernel_cred(NULL);
+	if (!kern_cred) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	old_cred = override_creds(kern_cred);
 	ret = fw_get_filesystem_firmware(device, fw->priv, "", NULL);
 	/* Only full reads can support decompression, platform, and sysfs. */
 	} else
 		ret = assign_fw(fw, device);
+	revert_creds(old_cred);
+	put_cred(kern_cred);
  out:
 	if (ret < 0) {
 		fw_abort_batch_reqs(fw);

drivers/base/platform.c+19−2

@@ -30,6 +30,8 @@ · 29 unmodified lines
30	#include <linux/property.h>	30	#include <linux/property.h>
31	#include <linux/kmemleak.h>	31	#include <linux/kmemleak.h>
32	#include <linux/types.h>	32	#include <linux/types.h>
		33	#include <linux/iommu.h>
		34	#include <linux/dma-map-ops.h>
33		35
34	#include "base.h"	36	#include "base.h"
35	#include "power/power.h"	37	#include "power/power.h"
@@ -1454,9 +1456,9 @@ static void platform_shutdown(struct device *_dev) · 1418 unmodified lines
1454	drv->shutdown(dev);	1456	drv->shutdown(dev);
1455	}	1457	}
1456		1458
1457		1459	static int platform_dma_configure(struct device *dev)
1458	int platform_dma_configure(struct device *dev)
1459	{	1460	{
		1461	struct platform_driver *drv = to_platform_driver(dev->driver);
1460	enum dev_dma_attr attr;	1462	enum dev_dma_attr attr;
1461	int ret = 0;	1463	int ret = 0;
1462		1464
@@ -1467,9 +1469,23 @@ int platform_dma_configure(struct device *dev) · 4 unmodified lines
1467	ret = acpi_dma_configure(dev, attr);	1469	ret = acpi_dma_configure(dev, attr);
1468	}	1470	}
1469		1471
		1472	if (!ret && !drv->driver_managed_dma) {
		1473	ret = iommu_device_use_default_domain(dev);
		1474	if (ret)
		1475	arch_teardown_dma_ops(dev);
		1476	}
		1477
1470	return ret;	1478	return ret;
1471	}	1479	}
1472		1480
		1481	static void platform_dma_cleanup(struct device *dev)
		1482	{
		1483	struct platform_driver *drv = to_platform_driver(dev->driver);
		1484
		1485	if (!drv->driver_managed_dma)
		1486	iommu_device_unuse_default_domain(dev);
		1487	}
		1488
1473	static const struct dev_pm_ops platform_dev_pm_ops = {	1489	static const struct dev_pm_ops platform_dev_pm_ops = {
1474	SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, pm_generic_runtime_resume, NULL)	1490	SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, pm_generic_runtime_resume, NULL)
1475	USE_PLATFORM_PM_SLEEP_OPS	1491	USE_PLATFORM_PM_SLEEP_OPS
@@ -1484,6 +1500,7 @@ struct bus_type platform_bus_type = { · 8 unmodified lines
1484	.remove = platform_remove,	1500	.remove = platform_remove,
1485	.shutdown = platform_shutdown,	1501	.shutdown = platform_shutdown,
1486	.dma_configure = platform_dma_configure,	1502	.dma_configure = platform_dma_configure,
		1503	.dma_cleanup = platform_dma_cleanup,
1487	.pm = &platform_dev_pm_ops,	1504	.pm = &platform_dev_pm_ops,
1488	};	1505	};
1489	EXPORT_SYMBOL_GPL(platform_bus_type);	1506	EXPORT_SYMBOL_GPL(platform_bus_type);

drivers/base/topology.c+10−0

@@ -152,9 +152,19 @@ static struct attribute *default_attrs[] = { · 151 unmodified lines
152	NULL	152	NULL
153	};	153	};
154		154
		155	static umode_t topology_is_visible(struct kobject *kobj,
		156	struct attribute *attr, int unused)
		157	{
		158	if (attr == &dev_attr_ppin.attr && !topology_ppin(kobj_to_dev(kobj)->id))
		159	return 0;
		160
		161	return attr->mode;
		162	}
		163
155	static const struct attribute_group topology_attr_group = {	164	static const struct attribute_group topology_attr_group = {
156	.attrs = default_attrs,	165	.attrs = default_attrs,
157	.bin_attrs = bin_attrs,	166	.bin_attrs = bin_attrs,
		167	.is_visible = topology_is_visible,
158	.name = "topology"	168	.name = "topology"
159	};	169	};
160		170

drivers/block/Kconfig+16−0

@@ -33,6 +33,22 @@ config BLK_DEV_FD · 32 unmodified lines
33	To compile this driver as a module, choose M here: the	33	To compile this driver as a module, choose M here: the
34	module will be called floppy.	34	module will be called floppy.
35		35
		36	config BLK_DEV_FD_RAWCMD
		37	bool "Support for raw floppy disk commands (DEPRECATED)"
		38	depends on BLK_DEV_FD
		39	help
		40	If you want to use actual physical floppies and expect to do
		41	special low-level hardware accesses to them (access and use
		42	non-standard formats, for example), then enable this.
		43
		44	Note that the code enabled by this option is rarely used and
		45	might be unstable or insecure, and distros should not enable it.
		46
		47	Note: FDRAWCMD is deprecated and will be removed from the kernel
		48	in the near future.
		49
		50	If unsure, say N.
		51
36	config AMIGA_FLOPPY	52	config AMIGA_FLOPPY
37	tristate "Amiga floppy support"	53	tristate "Amiga floppy support"
38	depends on AMIGA	54	depends on AMIGA

drivers/block/ataflop.c+6−4

 	int ref;
 	int type;
 	struct blk_mq_tag_set tag_set;
+	int error_count;
 } unit[FD_MAX_UNITS];
 #define	UD	unit[drive]
 	if (!fd_request)
 		return;
-	fd_request->error_count++;
+	unit[SelectedDrive].error_count++;
-	if (fd_request->error_count >= MAX_ERRORS) {
+	if (unit[SelectedDrive].error_count >= MAX_ERRORS) {
 		printk(KERN_ERR "fd%d: too many errors.\n", SelectedDrive );
 		fd_end_request_cur(BLK_STS_IOERR);
 		finish_fdc();
 		return;
 	}
-	else if (fd_request->error_count == RECALIBRATE_ERRORS) {
+	else if (unit[SelectedDrive].error_count == RECALIBRATE_ERRORS) {
 		printk(KERN_WARNING "fd%d: recalibrating\n", SelectedDrive );
 		if (SelectedDrive != -1)
 			SUD.track = -1;
 	ReqData = ReqBuffer + 512 * ReqCnt;
 	if (UseTrackbuffer)
-		read_track = (ReqCmd == READ && fd_request->error_count == 0);
+		read_track = (ReqCmd == READ && unit[drive].error_count == 0);
 	else
 		read_track = 0;
 		return BLK_STS_RESOURCE;
 	}
 	fd_request = bd->rq;
+	unit[drive].error_count = 0;
 	blk_mq_start_request(fd_request);
 	atari_disable_irq( IRQ_MFP_FDC );

drivers/block/floppy.c+40−21

 static DECLARE_WAIT_QUEUE_HEAD(fdc_wait);
 static DECLARE_WAIT_QUEUE_HEAD(command_done);
-/* Errors during formatting are counted here. */
+/* errors encountered on the current (or last) request */
-static int format_errors;
+static int floppy_errors;
 /* Format request descriptor. */
 static struct format_descr format_req;
 static char *floppy_track_buffer;
 static int max_buffer_sectors;
-static int *errors;
 typedef void (*done_f)(int);
 static const struct cont_t {
 	void (*interrupt)(void);
 			if (drive_params[current_drive].flags & FTD_MSG)
 				DPRINT("Over/Underrun - retrying\n");
 			bad = 0;
-		} else if (*errors >= drive_params[current_drive].max_errors.reporting) {
+		} else if (floppy_errors >= drive_params[current_drive].max_errors.reporting) {
 			print_errors();
 		}
 		if (reply_buffer[ST2] & ST2_WC || reply_buffer[ST2] & ST2_BC)
 		if (!next_valid_format(current_drive))
 			return;
 	}
-	err_count = ++(*errors);
+	err_count = ++floppy_errors;
 	INFBOUND(write_errors[current_drive].badness, err_count);
 	if (err_count > drive_params[current_drive].max_errors.abort)
 		cont->done(0);
 		return -EINVAL;
 	}
 	format_req = *tmp_format_req;
-	format_errors = 0;
 	cont = &format_cont;
-	errors = &format_errors;
+	floppy_errors = 0;
 	ret = wait_til_done(redo_format, true);
 	if (ret == -EINTR)
 		return -EINTR;
 	current_req = list_first_entry_or_null(&floppy_reqs, struct request,
 					       queuelist);
 	if (current_req) {
-		current_req->error_count = 0;
+		floppy_errors = 0;
 		list_del_init(&current_req->queuelist);
+		return 1;
 	}
-	return current_req != NULL;
+	return 0;
 }
 /* Starts or continues processing request. Will automatically unlock the
 		_floppy = floppy_type + drive_params[current_drive].autodetect[drive_state[current_drive].probed_format];
 	} else
 		probing = 0;
-	errors = &(current_req->error_count);
 	tmp = make_raw_rw_request();
 	if (tmp < 2) {
 		request_done(tmp);
 		return "(null)";
 }
+#ifdef CONFIG_BLK_DEV_FD_RAWCMD
 /* raw commands */
 static void raw_cmd_done(int flag)
 {
 	return ret;
 }
+static int floppy_raw_cmd_ioctl(int type, int drive, int cmd,
+				void __user *param)
+{
+	int ret;
+	pr_warn_once("Note: FDRAWCMD is deprecated and will be removed from the kernel in the near future.\n");
+	if (type)
+		return -EINVAL;
+	if (lock_fdc(drive))
+		return -EINTR;
+	set_floppy(drive);
+	ret = raw_cmd_ioctl(cmd, param);
+	if (ret == -EINTR)
+		return -EINTR;
+	process_fd_request();
+	return ret;
+}
+#else /* CONFIG_BLK_DEV_FD_RAWCMD */
+static int floppy_raw_cmd_ioctl(int type, int drive, int cmd,
+				void __user *param)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 static int invalidate_drive(struct block_device *bdev)
 {
 	/* invalidate the buffer track to force a reread */
 {
 	int drive = (long)bdev->bd_disk->private_data;
 	int type = ITYPE(drive_state[drive].fd_device);
-	int i;
 	int ret;
 	int size;
 	union inparam {
 		outparam = &write_errors[drive];
 		break;
 	case FDRAWCMD:
-		if (type)
+		return floppy_raw_cmd_ioctl(type, drive, cmd, (void __user *)param);
-			return -EINVAL;
-		if (lock_fdc(drive))
-			return -EINTR;
-		set_floppy(drive);
-		i = raw_cmd_ioctl(cmd, (void __user *)param);
-		if (i == -EINTR)
-			return -EINTR;
-		process_fd_request();
-		return i;
 	case FDTWADDLE:
 		if (lock_fdc(drive))
 			return -EINTR;

drivers/bus/fsl-mc/fsl-mc-bus.c+22−2

 #include <linux/dma-mapping.h>
 #include <linux/acpi.h>
 #include <linux/iommu.h>
+#include <linux/dma-map-ops.h>
 #include "fsl-mc-private.h"
 {
 	struct device *dma_dev = dev;
 	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
+	struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver);
 	u32 input_id = mc_dev->icid;
+	int ret;
 	while (dev_is_fsl_mc(dma_dev))
 		dma_dev = dma_dev->parent;
 	if (dev_of_node(dma_dev))
-		return of_dma_configure_id(dev, dma_dev->of_node, 0, &input_id);
+		ret = of_dma_configure_id(dev, dma_dev->of_node, 0, &input_id);
+	else
+		ret = acpi_dma_configure_id(dev, DEV_DMA_COHERENT, &input_id);
+	if (!ret && !mc_drv->driver_managed_dma) {
+		ret = iommu_device_use_default_domain(dev);
+		if (ret)
+			arch_teardown_dma_ops(dev);
+	}
+	return ret;
+}
+static void fsl_mc_dma_cleanup(struct device *dev)
+{
+	struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver);
-	return acpi_dma_configure_id(dev, DEV_DMA_COHERENT, &input_id);
+	if (!mc_drv->driver_managed_dma)
+		iommu_device_unuse_default_domain(dev);
 }
 static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
 	.match = fsl_mc_bus_match,
 	.uevent = fsl_mc_bus_uevent,
 	.dma_configure  = fsl_mc_dma_configure,
+	.dma_cleanup = fsl_mc_dma_cleanup,
 	.dev_groups = fsl_mc_dev_groups,
 	.bus_groups = fsl_mc_bus_groups,
 };

drivers/bus/fsl-mc/fsl-mc-msi.c+5−1

 	if (error)
 		return error;
+	msi_lock_descs(dev);
 	if (msi_first_desc(dev, MSI_DESC_ALL))
-		return -EINVAL;
+		error = -EINVAL;
+	msi_unlock_descs(dev);
+	if (error)
+		return error;
 	/*
 	 * NOTE: Calling this function will trigger the invocation of the

drivers/bus/imx-weim.c+2−3

 		pdev = of_find_device_by_node(rd->dn);
 		if (!pdev) {
-			dev_err(&pdev->dev,
+			pr_err("Could not find platform device for '%pOF'\n",
-				"Could not find platform device for '%pOF'\n",
 				rd->dn);
 			ret = notifier_from_errno(-EINVAL);
 	return ret;
 }
-struct notifier_block weim_of_notifier = {
+static struct notifier_block weim_of_notifier = {
 	.notifier_call = of_weim_notify,
 };
 #endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */

drivers/bus/mhi/host/pci_generic.c+2−0

 	 * the intermediate restore kernel reinitializes MHI device with new
 	 * context.
 	 */
+	flush_work(&mhi_pdev->recovery_work);
 	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
 		mhi_power_down(mhi_cntrl, true);
 		mhi_unprepare_after_power_down(mhi_cntrl);
 	.resume = mhi_pci_resume,
 	.freeze = mhi_pci_freeze,
 	.thaw = mhi_pci_restore,
+	.poweroff = mhi_pci_freeze,
 	.restore = mhi_pci_restore,
 #endif
 };

drivers/bus/sunxi-rsb.c+2−0

@@ -227,6 +227,8 @@ static struct sunxi_rsb_device sunxi_rsb_device_create(struct sunxi_rsb rsb, · 226 unmodified lines
227		227
228	dev_dbg(&rdev->dev, "device %s registered\n", dev_name(&rdev->dev));	228	dev_dbg(&rdev->dev, "device %s registered\n", dev_name(&rdev->dev));
229		229
		230	return rdev;
		231
230	err_device_add:	232	err_device_add:
231	put_device(&rdev->dev);	233	put_device(&rdev->dev);
232		234

drivers/bus/ti-sysc.c+15−1

@@ -3232,13 +3232,27 @@ static int sysc_check_disabled_devices(struct sysc *ddata) · 3231 unmodified lines
3232	*/	3232	*/
3233	static int sysc_check_active_timer(struct sysc *ddata)	3233	static int sysc_check_active_timer(struct sysc *ddata)
3234	{	3234	{
		3235	int error;
		3236
3235	if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&	3237	if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3236	ddata->cap->type != TI_SYSC_OMAP4_TIMER)	3238	ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3237	return 0;	3239	return 0;
3238		3240
		3241	/*
		3242	* Quirk for omap3 beagleboard revision A to B4 to use gpt12.
		3243	* Revision C and later are fixed with commit 23885389dbbb ("ARM:
		3244	* dts: Fix timer regression for beagleboard revision c"). This all
		3245	* can be dropped if we stop supporting old beagleboard revisions
		3246	* A to B4 at some point.
		3247	*/
		3248	if (sysc_soc->soc == SOC_3430)
		3249	error = -ENXIO;
		3250	else
		3251	error = -EBUSY;
		3252
3239	if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&	3253	if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3240	(ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))	3254	(ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3241	return -ENXIO;	3255	return error;
3242		3256
3243	return 0;	3257	return 0;
3244	}	3258	}

drivers/char/ipmi/ipmi_msghandler.c+6−1

 void ipmi_unregister_smi(struct ipmi_smi *intf)
 {
 	struct ipmi_smi_watcher *w;
-	int intf_num = intf->intf_num, index;
+	int intf_num, index;
+	if (!intf)
+		return;
+	intf_num = intf->intf_num;
 	mutex_lock(&ipmi_interfaces_mutex);
 	intf->intf_num = -1;
 	intf->in_shutdown = true;
 		} else
 			/* The message was sent, start the timer. */
 			intf_start_seq_timer(intf, msg->msgid);
+		requeue = 0;
+		goto out;
 	} else if (((msg->rsp[0] >> 2) != ((msg->data[0] >> 2) | 1))
 		   || (msg->rsp[1] != msg->data[1])) {
 		/*

drivers/char/ipmi/ipmi_si_intf.c+1−4

@@ -2220,10 +2220,7 @@ static void cleanup_one_si(struct smi_info *smi_info) · 2219 unmodified lines
2220	return;	2220	return;
2221		2221
2222	list_del(&smi_info->link);	2222	list_del(&smi_info->link);
2223		2223	ipmi_unregister_smi(smi_info->intf);
2224	if (smi_info->intf)
2225	ipmi_unregister_smi(smi_info->intf);
2226
2227	kfree(smi_info);	2224	kfree(smi_info);
2228	}	2225	}
2229		2226

drivers/char/random.c+8−1

  * the resultant ChaCha state to the user, along with the second
  * half of the block containing 32 bytes of random data that may
  * be used; random_data_len may not be greater than 32.
+ *
+ * The returned ChaCha state contains within it a copy of the old
+ * key value, at index 4, so the state should always be zeroed out
+ * immediately after using in order to maintain forward secrecy.
+ * If the state cannot be erased in a timely manner, then it is
+ * safer to set the random_data parameter to &chacha_state[4] so
+ * that this function overwrites it before returning.
  */
 static void crng_fast_key_erasure(u8 key[CHACHA_KEY_SIZE],
 				  u32 chacha_state[CHACHA_STATE_WORDS],
 	chacha20_block(chacha_state, first_block);
 	memcpy(key, first_block, CHACHA_KEY_SIZE);
-	memmove(random_data, first_block + CHACHA_KEY_SIZE, random_data_len);
+	memcpy(random_data, first_block + CHACHA_KEY_SIZE, random_data_len);
 	memzero_explicit(first_block, sizeof(first_block));
 }

drivers/clk/microchip/clk-mpfs.c+164−31

@@ -11,20 +11,48 @@ · 10 unmodified lines
11	#include <dt-bindings/clock/microchip,mpfs-clock.h>	11	#include <dt-bindings/clock/microchip,mpfs-clock.h>
12		12
13	/* address offset of control registers */	13	/* address offset of control registers */
		14	#define REG_MSSPLL_REF_CR 0x08u
		15	#define REG_MSSPLL_POSTDIV_CR 0x10u
		16	#define REG_MSSPLL_SSCG_2_CR 0x2Cu
14	#define REG_CLOCK_CONFIG_CR 0x08u	17	#define REG_CLOCK_CONFIG_CR 0x08u
		18	#define REG_RTC_CLOCK_CR 0x0Cu
15	#define REG_SUBBLK_CLOCK_CR 0x84u	19	#define REG_SUBBLK_CLOCK_CR 0x84u
16	#define REG_SUBBLK_RESET_CR 0x88u	20	#define REG_SUBBLK_RESET_CR 0x88u
17		21
		22	#define MSSPLL_FBDIV_SHIFT 0x00u
		23	#define MSSPLL_FBDIV_WIDTH 0x0Cu
		24	#define MSSPLL_REFDIV_SHIFT 0x08u
		25	#define MSSPLL_REFDIV_WIDTH 0x06u
		26	#define MSSPLL_POSTDIV_SHIFT 0x08u
		27	#define MSSPLL_POSTDIV_WIDTH 0x07u
		28	#define MSSPLL_FIXED_DIV 4u
		29
18	struct mpfs_clock_data {	30	struct mpfs_clock_data {
19	void __iomem *base;	31	void __iomem *base;
		32	void __iomem *msspll_base;
20	struct clk_hw_onecell_data hw_data;	33	struct clk_hw_onecell_data hw_data;
21	};	34	};
22		35
		36	struct mpfs_msspll_hw_clock {
		37	void __iomem *base;
		38	unsigned int id;
		39	u32 reg_offset;
		40	u32 shift;
		41	u32 width;
		42	u32 flags;
		43	struct clk_hw hw;
		44	struct clk_init_data init;
		45	};
		46
		47	#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
		48
23	struct mpfs_cfg_clock {	49	struct mpfs_cfg_clock {
24	const struct clk_div_table *table;	50	const struct clk_div_table *table;
25	unsigned int id;	51	unsigned int id;
		52	u32 reg_offset;
26	u8 shift;	53	u8 shift;
27	u8 width;	54	u8 width;
		55	u8 flags;
28	};	56	};
29		57
30	struct mpfs_cfg_hw_clock {	58	struct mpfs_cfg_hw_clock {
@@ -55,7 +83,7 @@ struct mpfs_periph_hw_clock { · 24 unmodified lines
55	*/	83	*/
56	static DEFINE_SPINLOCK(mpfs_clk_lock);	84	static DEFINE_SPINLOCK(mpfs_clk_lock);
57		85
58	static const struct clk_parent_data mpfs_cfg_parent[] = {	86	static const struct clk_parent_data mpfs_ext_ref[] = {
59	{ .index = 0 },	87	{ .index = 0 },
60	};	88	};
61		89
@@ -69,6 +97,86 @@ static const struct clk_div_table mpfs_div_ahb_table[] = { · 7 unmodified lines
69	{ 0, 0 }	97	{ 0, 0 }
70	};	98	};
71		99
		100	/*
		101	* The only two supported reference clock frequencies for the PolarFire SoC are
		102	* 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
		103	* It therefore only needs to have divider table entries corresponding to
		104	* divide by 100 and 125.
		105	*/
		106	static const struct clk_div_table mpfs_div_rtcref_table[] = {
		107	{ 100, 100 }, { 125, 125 },
		108	{ 0, 0 }
		109	};
		110
		111	static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate)
		112	{
		113	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
		114	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
		115	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
		116	void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
		117	u32 mult, ref_div, postdiv;
		118
		119	mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
		120	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
		121	ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
		122	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
		123	postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
		124	postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
		125
		126	return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
		127	}
		128
		129	static const struct clk_ops mpfs_clk_msspll_ops = {
		130	.recalc_rate = mpfs_clk_msspll_recalc_rate,
		131	};
		132
		133	#define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
		134	.id = _id, \
		135	.shift = _shift, \
		136	.width = _width, \
		137	.reg_offset = _offset, \
		138	.flags = _flags, \
		139	.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \
		140	}
		141
		142	static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
		143	CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
		144	MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
		145	};
		146
		147	static int mpfs_clk_register_msspll(struct device dev, struct mpfs_msspll_hw_clock msspll_hw,
		148	void __iomem *base)
		149	{
		150	msspll_hw->base = base;
		151
		152	return devm_clk_hw_register(dev, &msspll_hw->hw);
		153	}
		154
		155	static int mpfs_clk_register_mssplls(struct device dev, struct mpfs_msspll_hw_clock msspll_hws,
		156	unsigned int num_clks, struct mpfs_clock_data *data)
		157	{
		158	void __iomem *base = data->msspll_base;
		159	unsigned int i;
		160	int ret;
		161
		162	for (i = 0; i < num_clks; i++) {
		163	struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
		164
		165	ret = mpfs_clk_register_msspll(dev, msspll_hw, base);
		166	if (ret)
		167	return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
		168	CLK_MSSPLL);
		169
		170	data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;
		171	}
		172
		173	return 0;
		174	}
		175
		176	/*
		177	* "CFG" clocks
		178	*/
		179
72	static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)	180	static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
73	{	181	{
74	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);	182	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
@@ -76,10 +184,10 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p · 1 unmodified line
76	void __iomem *base_addr = cfg_hw->sys_base;	184	void __iomem *base_addr = cfg_hw->sys_base;
77	u32 val;	185	u32 val;
78		186
79	val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;	187	val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift;
80	val &= clk_div_mask(cfg->width);	188	val &= clk_div_mask(cfg->width);
81		189
82	return prate / (1u << val);	190	return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
83	}	191	}
84		192
85	static long mpfs_cfg_clk_round_rate(struct clk_hw hw, unsigned long rate, unsigned long prate)	193	static long mpfs_cfg_clk_round_rate(struct clk_hw hw, unsigned long rate, unsigned long prate)
@@ -105,11 +213,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned · 19 unmodified lines
105	return divider_setting;	213	return divider_setting;
106		214
107	spin_lock_irqsave(&mpfs_clk_lock, flags);	215	spin_lock_irqsave(&mpfs_clk_lock, flags);
108		216	val = readl_relaxed(base_addr + cfg->reg_offset);
109	val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR);
110	val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);	217	val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
111	val \|= divider_setting << cfg->shift;	218	val \|= divider_setting << cfg->shift;
112	writel_relaxed(val, base_addr + REG_CLOCK_CONFIG_CR);	219	writel_relaxed(val, base_addr + cfg->reg_offset);
113		220
114	spin_unlock_irqrestore(&mpfs_clk_lock, flags);	221	spin_unlock_irqrestore(&mpfs_clk_lock, flags);
115		222
@@ -122,19 +229,33 @@ static const struct clk_ops mpfs_clk_cfg_ops = { · 6 unmodified lines
122	.set_rate = mpfs_cfg_clk_set_rate,	229	.set_rate = mpfs_cfg_clk_set_rate,
123	};	230	};
124		231
125	#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags) { \	232	#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
126	.cfg.id = _id, \	233	.cfg.id = _id, \
127	.cfg.shift = _shift, \	234	.cfg.shift = _shift, \
128	.cfg.width = _width, \	235	.cfg.width = _width, \
129	.cfg.table = _table, \	236	.cfg.table = _table, \
130	.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_cfg_ops, \	237	.cfg.reg_offset = _offset, \
131	_flags), \	238	.cfg.flags = _flags, \
		239	.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \
132	}	240	}
133		241
134	static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {	242	static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
135	CLK_CFG(CLK_CPU, "clk_cpu", mpfs_cfg_parent, 0, 2, mpfs_div_cpu_axi_table, 0),	243	CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0,
136	CLK_CFG(CLK_AXI, "clk_axi", mpfs_cfg_parent, 2, 2, mpfs_div_cpu_axi_table, 0),	244	REG_CLOCK_CONFIG_CR),
137	CLK_CFG(CLK_AHB, "clk_ahb", mpfs_cfg_parent, 4, 2, mpfs_div_ahb_table, 0),	245	CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0,
		246	REG_CLOCK_CONFIG_CR),
		247	CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0,
		248	REG_CLOCK_CONFIG_CR),
		249	{
		250	.cfg.id = CLK_RTCREF,
		251	.cfg.shift = 0,
		252	.cfg.width = 12,
		253	.cfg.table = mpfs_div_rtcref_table,
		254	.cfg.reg_offset = REG_RTC_CLOCK_CR,
		255	.cfg.flags = CLK_DIVIDER_ONE_BASED,
		256	.hw.init =
		257	CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
		258	}
138	};	259	};
139		260
140	static int mpfs_clk_register_cfg(struct device dev, struct mpfs_cfg_hw_clock cfg_hw,	261	static int mpfs_clk_register_cfg(struct device dev, struct mpfs_cfg_hw_clock cfg_hw,
@@ -160,13 +281,17 @@ static int mpfs_clk_register_cfgs(struct device dev, struct mpfs_cfg_hw_clock · 19 unmodified lines
160	return dev_err_probe(dev, ret, "failed to register clock id: %d\n",	281	return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
161	cfg_hw->cfg.id);	282	cfg_hw->cfg.id);
162		283
163	id = cfg_hws[i].cfg.id;	284	id = cfg_hw->cfg.id;
164	data->hw_data.hws[id] = &cfg_hw->hw;	285	data->hw_data.hws[id] = &cfg_hw->hw;
165	}	286	}
166		287
167	return 0;	288	return 0;
168	}	289	}
169		290
		291	/*
		292	* peripheral clocks - devices connected to axi or ahb buses.
		293	*/
		294
170	static int mpfs_periph_clk_enable(struct clk_hw *hw)	295	static int mpfs_periph_clk_enable(struct clk_hw *hw)
171	{	296	{
172	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);	297	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
@@ -200,10 +325,6 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw) · 27 unmodified lines
200		325
201	spin_lock_irqsave(&mpfs_clk_lock, flags);	326	spin_lock_irqsave(&mpfs_clk_lock, flags);
202		327
203	reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR);
204	val = reg \| (1u << periph->shift);
205	writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR);
206
207	reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);	328	reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
208	val = reg & ~(1u << periph->shift);	329	val = reg & ~(1u << periph->shift);
209	writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);	330	writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
@@ -249,8 +370,10 @@ static const struct clk_ops mpfs_periph_clk_ops = { · 39 unmodified lines
249	* trap handler	370	* trap handler
250	* - CLK_MMUART0: reserved by the hss	371	* - CLK_MMUART0: reserved by the hss
251	* - CLK_DDRC: provides clock to the ddr subsystem	372	* - CLK_DDRC: provides clock to the ddr subsystem
252	* - CLK_FICx: these provide clocks for sections of the fpga fabric, disabling them would	373	* - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
253	* cause the fabric to go into reset	374	* clock domain crossers which provide the interface to the FPGA fabric. Disabling them
		375	* causes the FPGA fabric to go into reset.
		376	* - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
254	*/	377	*/
255		378
256	static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {	379	static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
@@ -258,7 +381,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { · 1 unmodified line
258	CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),	381	CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
259	CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),	382	CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
260	CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),	383	CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
261	CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(AHB), 4, 0),	384	CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0),
262	CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),	385	CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
263	CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),	386	CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
264	CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),	387	CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
@@ -277,11 +400,11 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { · 12 unmodified lines
277	CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),	400	CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
278	CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),	401	CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
279	CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),	402	CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
280	CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AHB), 24, CLK_IS_CRITICAL),	403	CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
281	CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AHB), 25, CLK_IS_CRITICAL),	404	CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
282	CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AHB), 26, CLK_IS_CRITICAL),	405	CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
283	CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AHB), 27, CLK_IS_CRITICAL),	406	CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
284	CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AHB), 28, 0),	407	CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
285	CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),	408	CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
286	};	409	};
287		410
@@ -322,8 +445,9 @@ static int mpfs_clk_probe(struct platform_device *pdev) · 34 unmodified lines
322	unsigned int num_clks;	445	unsigned int num_clks;
323	int ret;	446	int ret;
324		447
325	/* CLK_RESERVED is not part of cfg_clks nor periph_clks, so add 1 */	448	/* CLK_RESERVED is not part of clock arrays, so add 1 */
326	num_clks = ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1;	449	num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks)
		450	+ ARRAY_SIZE(mpfs_periph_clks) + 1;
327		451
328	clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);	452	clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);
329	if (!clk_data)	453	if (!clk_data)
@@ -333,8 +457,17 @@ static int mpfs_clk_probe(struct platform_device *pdev) · 3 unmodified lines
333	if (IS_ERR(clk_data->base))	457	if (IS_ERR(clk_data->base))
334	return PTR_ERR(clk_data->base);	458	return PTR_ERR(clk_data->base);
335		459
		460	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
		461	if (IS_ERR(clk_data->msspll_base))
		462	return PTR_ERR(clk_data->msspll_base);
		463
336	clk_data->hw_data.num = num_clks;	464	clk_data->hw_data.num = num_clks;
337		465
		466	ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
		467	clk_data);
		468	if (ret)
		469	return ret;
		470
338	ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);	471	ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);
339	if (ret)	472	if (ret)
340	return ret;	473	return ret;

drivers/clk/qcom/clk-rcg2.c+1−1

@@ -818,7 +818,7 @@ EXPORT_SYMBOL_GPL(clk_pixel_ops); · 817 unmodified lines
818	static int clk_gfx3d_determine_rate(struct clk_hw *hw,	818	static int clk_gfx3d_determine_rate(struct clk_hw *hw,
819	struct clk_rate_request *req)	819	struct clk_rate_request *req)
820	{	820	{
821	struct clk_rate_request parent_req = { };	821	struct clk_rate_request parent_req = { .min_rate = 0, .max_rate = ULONG_MAX };
822	struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);	822	struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
823	struct clk_hw xo, p0, p1, p2;	823	struct clk_hw xo, p0, p1, p2;
824	unsigned long p0_rate;	824	unsigned long p0_rate;

drivers/clk/sunxi-ng/ccu-sun6i-rtc.c+2−0

 	.ops		= &ccu_mux_ops,
 	.parent_hws	= rtc_32k_parents,
 	.num_parents	= ARRAY_SIZE(rtc_32k_parents), /* updated during probe */
+	.flags		= CLK_IS_CRITICAL,
 };
 static struct ccu_mux rtc_32k_clk = {
 		.compatible	= "allwinner,sun50i-r329-rtc",
 		.data		= &sun50i_r329_rtc_ccu_data,
 	},
+	{},
 };
 int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)

drivers/clk/sunxi/clk-sun9i-mmc.c+2−0

@@ -109,6 +109,8 @@ static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev) · 108 unmodified lines
109	spin_lock_init(&data->lock);	109	spin_lock_init(&data->lock);
110		110
111	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);	111	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		112	if (!r)
		113	return -EINVAL;
112	/* one clock/reset pair per word */	114	/* one clock/reset pair per word */
113	count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);	115	count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
114	data->membase = devm_ioremap_resource(&pdev->dev, r);	116	data->membase = devm_ioremap_resource(&pdev->dev, r);

drivers/cpufreq/qcom-cpufreq-hw.c+57−13

 #define CLK_HW_DIV			2
 #define LUT_TURBO_IND			1
+#define GT_IRQ_STATUS			BIT(2)
 #define HZ_PER_KHZ			1000
 struct qcom_cpufreq_soc_data {
 	u32 reg_enable;
+	u32 reg_domain_state;
 	u32 reg_dcvs_ctrl;
 	u32 reg_freq_lut;
 	u32 reg_volt_lut;
+	u32 reg_intr_clr;
 	u32 reg_current_vote;
 	u32 reg_perf_state;
 	u8 lut_row_size;
 	}
 }
-static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
+static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
 {
-	unsigned int val = readl_relaxed(data->base + data->soc_data->reg_current_vote);
+	unsigned int lval;
+	if (data->soc_data->reg_current_vote)
+		lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
+	else
+		lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
-	return (val & 0x3FF) * 19200;
+	return lval * xo_rate;
 }
 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
 {
 	struct cpufreq_policy *policy = data->policy;
-	int cpu = cpumask_first(policy->cpus);
+	int cpu = cpumask_first(policy->related_cpus);
 	struct device *dev = get_cpu_device(cpu);
 	unsigned long freq_hz, throttled_freq;
 	struct dev_pm_opp *opp;
-	unsigned int freq;
 	/*
 	 * Get the h/w throttled frequency, normalize it using the
 	 * registered opp table and use it to calculate thermal pressure.
 	 */
-	freq = qcom_lmh_get_throttle_freq(data);
+	freq_hz = qcom_lmh_get_throttle_freq(data);
-	freq_hz = freq * HZ_PER_KHZ;
 	opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
 	if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
-		dev_pm_opp_find_freq_ceil(dev, &freq_hz);
+		opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
+	if (IS_ERR(opp)) {
+		dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
+	} else {
+		throttled_freq = freq_hz / HZ_PER_KHZ;
-	throttled_freq = freq_hz / HZ_PER_KHZ;
+		/* Update thermal pressure (the boost frequencies are accepted) */
+		arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
-	/* Update thermal pressure (the boost frequencies are accepted) */
+		dev_pm_opp_put(opp);
-	arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
+	}
 	/*
 	 * In the unlikely case policy is unregistered do not enable
 	disable_irq_nosync(c_data->throttle_irq);
 	schedule_delayed_work(&c_data->throttle_work, 0);
+	if (c_data->soc_data->reg_intr_clr)
+		writel_relaxed(GT_IRQ_STATUS,
+			       c_data->base + c_data->soc_data->reg_intr_clr);
 	return IRQ_HANDLED;
 }
 static const struct qcom_cpufreq_soc_data epss_soc_data = {
 	.reg_enable = 0x0,
+	.reg_domain_state = 0x20,
 	.reg_dcvs_ctrl = 0xb0,
 	.reg_freq_lut = 0x100,
 	.reg_volt_lut = 0x200,
+	.reg_intr_clr = 0x308,
 	.reg_perf_state = 0x320,
 	.lut_row_size = 4,
 };
 	return 0;
 }
-static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
+static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
+{
+	struct qcom_cpufreq_data *data = policy->driver_data;
+	struct platform_device *pdev = cpufreq_get_driver_data();
+	int ret;
+	ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
+	if (ret)
+		dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
+			data->irq_name, data->throttle_irq);
+	return ret;
+}
+static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
 {
+	struct qcom_cpufreq_data *data = policy->driver_data;
 	if (data->throttle_irq <= 0)
-		return;
+		return 0;
 	mutex_lock(&data->throttle_lock);
 	data->cancel_throttle = true;
 	mutex_unlock(&data->throttle_lock);
 	cancel_delayed_work_sync(&data->throttle_work);
+	irq_set_affinity_hint(data->throttle_irq, NULL);
+	return 0;
+}
+static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
+{
 	free_irq(data->throttle_irq, data);
 }
 	.get		= qcom_cpufreq_hw_get,
 	.init		= qcom_cpufreq_hw_cpu_init,
 	.exit		= qcom_cpufreq_hw_cpu_exit,
+	.online		= qcom_cpufreq_hw_cpu_online,
+	.offline	= qcom_cpufreq_hw_cpu_offline,
 	.register_em	= cpufreq_register_em_with_opp,
 	.fast_switch    = qcom_cpufreq_hw_fast_switch,
 	.name		= "qcom-cpufreq-hw",

drivers/cpufreq/sun50i-cpufreq-nvmem.c+3−1

@@ -98,8 +98,10 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) · 97 unmodified lines
98	return -ENOMEM;	98	return -ENOMEM;
99		99
100	ret = sun50i_cpufreq_get_efuse(&speed);	100	ret = sun50i_cpufreq_get_efuse(&speed);
101	if (ret)	101	if (ret) {
		102	kfree(opp_tables);
102	return ret;	103	return ret;
		104	}
103		105
104	snprintf(name, MAX_NAME_LEN, "speed%d", speed);	106	snprintf(name, MAX_NAME_LEN, "speed%d", speed);
105		107

drivers/dma-buf/dma-buf.c+4−4

 	file->f_mode |= FMODE_LSEEK;
 	dmabuf->file = file;
-	ret = dma_buf_stats_setup(dmabuf);
-	if (ret)
-		goto err_sysfs;
 	mutex_init(&dmabuf->lock);
 	INIT_LIST_HEAD(&dmabuf->attachments);
 	list_add(&dmabuf->list_node, &db_list.head);
 	mutex_unlock(&db_list.lock);
+	ret = dma_buf_stats_setup(dmabuf);
+	if (ret)
+		goto err_sysfs;
 	return dmabuf;
 err_sysfs:

drivers/firewire/core-card.c+3−0

 void fw_core_remove_card(struct fw_card *card)
 {
 	struct fw_card_driver dummy_driver = dummy_driver_template;
+	unsigned long flags;
 	card->driver->update_phy_reg(card, 4,
 				     PHY_LINK_ACTIVE | PHY_CONTENDER, 0);
 	dummy_driver.stop_iso		= card->driver->stop_iso;
 	card->driver = &dummy_driver;
+	spin_lock_irqsave(&card->lock, flags);
 	fw_destroy_nodes(card);
+	spin_unlock_irqrestore(&card->lock, flags);
 	/* Wait for all users, especially device workqueue jobs, to finish. */
 	fw_card_put(card);

drivers/firewire/core-cdev.c+3−1

 {
 	struct outbound_phy_packet_event *e =
 		container_of(packet, struct outbound_phy_packet_event, p);
+	struct client *e_client;
 	switch (status) {
 	/* expected: */
 	}
 	e->phy_packet.data[0] = packet->timestamp;
+	e_client = e->client;
 	queue_event(e->client, &e->event, &e->phy_packet,
 		    sizeof(e->phy_packet) + e->phy_packet.length, NULL, 0);
-	client_put(e->client);
+	client_put(e_client);
 }
 static int ioctl_send_phy_packet(struct client *client, union ioctl_arg *arg)

drivers/firewire/core-topology.c+3−6

 	card->bm_retries = 0;
 }
+/* Must be called with card->lock held */
 void fw_destroy_nodes(struct fw_card *card)
 {
-	unsigned long flags;
-	spin_lock_irqsave(&card->lock, flags);
 	card->color++;
 	if (card->local_node != NULL)
 		for_each_fw_node(card, card->local_node, report_lost_node);
 	card->local_node = NULL;
-	spin_unlock_irqrestore(&card->lock, flags);
 }
 static void move_tree(struct fw_node *node0, struct fw_node *node1, int port)
 	struct fw_node *local_node;
 	unsigned long flags;
+	spin_lock_irqsave(&card->lock, flags);
 	/*
 	 * If the selfID buffer is not the immediate successor of the
 	 * previously processed one, we cannot reliably compare the
 		card->bm_retries = 0;
 	}
-	spin_lock_irqsave(&card->lock, flags);
 	card->broadcast_channel_allocated = card->broadcast_channel_auto_allocated;
 	card->node_id = node_id;
 	/*

drivers/firewire/core-transaction.c+16−14

 static int close_transaction(struct fw_transaction *transaction,
 			     struct fw_card *card, int rcode)
 {
-	struct fw_transaction *t;
+	struct fw_transaction *t = NULL, *iter;
 	unsigned long flags;
 	spin_lock_irqsave(&card->lock, flags);
-	list_for_each_entry(t, &card->transaction_list, link) {
+	list_for_each_entry(iter, &card->transaction_list, link) {
-		if (t == transaction) {
+		if (iter == transaction) {
-			if (!try_cancel_split_timeout(t)) {
+			if (!try_cancel_split_timeout(iter)) {
 				spin_unlock_irqrestore(&card->lock, flags);
 				goto timed_out;
 			}
-			list_del_init(&t->link);
+			list_del_init(&iter->link);
-			card->tlabel_mask &= ~(1ULL << t->tlabel);
+			card->tlabel_mask &= ~(1ULL << iter->tlabel);
+			t = iter;
 			break;
 		}
 	}
 	spin_unlock_irqrestore(&card->lock, flags);
-	if (&t->link != &card->transaction_list) {
+	if (t) {
 		t->callback(card, rcode, NULL, 0, t->callback_data);
 		return 0;
 	}
 void fw_core_handle_response(struct fw_card *card, struct fw_packet *p)
 {
-	struct fw_transaction *t;
+	struct fw_transaction *t = NULL, *iter;
 	unsigned long flags;
 	u32 *data;
 	size_t data_length;
 	rcode	= HEADER_GET_RCODE(p->header[1]);
 	spin_lock_irqsave(&card->lock, flags);
-	list_for_each_entry(t, &card->transaction_list, link) {
+	list_for_each_entry(iter, &card->transaction_list, link) {
-		if (t->node_id == source && t->tlabel == tlabel) {
+		if (iter->node_id == source && iter->tlabel == tlabel) {
-			if (!try_cancel_split_timeout(t)) {
+			if (!try_cancel_split_timeout(iter)) {
 				spin_unlock_irqrestore(&card->lock, flags);
 				goto timed_out;
 			}
-			list_del_init(&t->link);
+			list_del_init(&iter->link);
-			card->tlabel_mask &= ~(1ULL << t->tlabel);
+			card->tlabel_mask &= ~(1ULL << iter->tlabel);
+			t = iter;
 			break;
 		}
 	}
 	spin_unlock_irqrestore(&card->lock, flags);
-	if (&t->link == &card->transaction_list) {
+	if (!t) {
  timed_out:
 		fw_notice(card, "unsolicited response (source %x, tlabel %x)\n",
 			  source, tlabel);

drivers/firewire/sbp2.c+7−6

 			      void *payload, size_t length, void *callback_data)
 {
 	struct sbp2_logical_unit *lu = callback_data;
-	struct sbp2_orb *orb;
+	struct sbp2_orb *orb = NULL, *iter;
 	struct sbp2_status status;
 	unsigned long flags;
 	/* Lookup the orb corresponding to this status write. */
 	spin_lock_irqsave(&lu->tgt->lock, flags);
-	list_for_each_entry(orb, &lu->orb_list, link) {
+	list_for_each_entry(iter, &lu->orb_list, link) {
 		if (STATUS_GET_ORB_HIGH(status) == 0 &&
-		    STATUS_GET_ORB_LOW(status) == orb->request_bus) {
+		    STATUS_GET_ORB_LOW(status) == iter->request_bus) {
-			orb->rcode = RCODE_COMPLETE;
+			iter->rcode = RCODE_COMPLETE;
-			list_del(&orb->link);
+			list_del(&iter->link);
+			orb = iter;
 			break;
 		}
 	}
 	spin_unlock_irqrestore(&lu->tgt->lock, flags);
-	if (&orb->link != &lu->orb_list) {
+	if (orb) {
 		orb->callback(orb, &status);
 		kref_put(&orb->kref, free_orb); /* orb callback reference */
 	} else {

drivers/gpio/gpio-mvebu.c+0−7

@@ -871,13 +871,6 @@ static int mvebu_pwm_probe(struct platform_device *pdev, · 870 unmodified lines
871	mvpwm->chip.dev = dev;	871	mvpwm->chip.dev = dev;
872	mvpwm->chip.ops = &mvebu_pwm_ops;	872	mvpwm->chip.ops = &mvebu_pwm_ops;
873	mvpwm->chip.npwm = mvchip->chip.ngpio;	873	mvpwm->chip.npwm = mvchip->chip.ngpio;
874	/*
875	* There may already be some PWM allocated, so we can't force
876	* mvpwm->chip.base to a fixed point like mvchip->chip.base.
877	* So, we let pwmchip_add() do the numbering and take the next free
878	* region.
879	*/
880	mvpwm->chip.base = -1;
881		874
882	spin_lock_init(&mvpwm->lock);	875	spin_lock_init(&mvpwm->lock);
883		876

drivers/gpio/gpio-pca953x.c+2−2

 	bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
 	bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
+	bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
 	if (bitmap_empty(trigger, gc->ngpio))
 		return false;
-	bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
 	bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
 	bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
 	bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);

drivers/gpio/gpio-visconti.c+2−5

 	struct gpio_irq_chip *girq;
 	struct irq_domain *parent;
 	struct device_node *irq_parent;
-	struct fwnode_handle *fwnode;
 	int ret;
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	}
 	parent = irq_find_host(irq_parent);
+	of_node_put(irq_parent);
 	if (!parent) {
 		dev_err(dev, "No IRQ parent domain\n");
 		return -ENODEV;
 	}
-	fwnode = of_node_to_fwnode(irq_parent);
-	of_node_put(irq_parent);
 	ret = bgpio_init(&priv->gpio_chip, dev, 4,
 			 priv->base + GPIO_IDATA,
 			 priv->base + GPIO_OSET,
 	girq = &priv->gpio_chip.irq;
 	girq->chip = irq_chip;
-	girq->fwnode = fwnode;
+	girq->fwnode = of_node_to_fwnode(dev->of_node);
 	girq->parent_domain = parent;
 	girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq;
 	girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec;

drivers/gpio/gpiolib-of.c+1−1

@@ -910,7 +910,7 @@ static void of_gpiochip_init_valid_mask(struct gpio_chip *chip) · 909 unmodified lines
910	i, &start);	910	i, &start);
911	of_property_read_u32_index(np, "gpio-reserved-ranges",	911	of_property_read_u32_index(np, "gpio-reserved-ranges",
912	i + 1, &count);	912	i + 1, &count);
913	if (start >= chip->ngpio \|\| start + count >= chip->ngpio)	913	if (start >= chip->ngpio \|\| start + count > chip->ngpio)
914	continue;	914	continue;
915		915
916	bitmap_clear(chip->valid_mask, start, count);	916	bitmap_clear(chip->valid_mask, start, count);

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+5−0

 {
 	struct amdgpu_device *adev = ctx->adev;
 	enum amd_dpm_forced_level level;
+	u32 current_stable_pstate;
 	int r;
 	mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 		goto done;
 	}
+	r = amdgpu_ctx_get_stable_pstate(ctx, &current_stable_pstate);
+	if (r || (stable_pstate == current_stable_pstate))
+		goto done;
 	switch (stable_pstate) {
 	case AMDGPU_CTX_STABLE_PSTATE_NONE:
 		level = AMD_DPM_FORCED_LEVEL_AUTO;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+70−35

@@ -2395,6 +2395,71 @@ static int amdgpu_pmops_restore(struct device *dev) · 2394 unmodified lines
2395	return amdgpu_device_resume(drm_dev, true);	2395	return amdgpu_device_resume(drm_dev, true);
2396	}	2396	}
2397		2397
		2398	static int amdgpu_runtime_idle_check_display(struct device *dev)
		2399	{
		2400	struct pci_dev *pdev = to_pci_dev(dev);
		2401	struct drm_device *drm_dev = pci_get_drvdata(pdev);
		2402	struct amdgpu_device *adev = drm_to_adev(drm_dev);
		2403
		2404	if (adev->mode_info.num_crtc) {
		2405	struct drm_connector *list_connector;
		2406	struct drm_connector_list_iter iter;
		2407	int ret = 0;
		2408
		2409	/* XXX: Return busy if any displays are connected to avoid
		2410	* possible display wakeups after runtime resume due to
		2411	* hotplug events in case any displays were connected while
		2412	* the GPU was in suspend. Remove this once that is fixed.
		2413	*/
		2414	mutex_lock(&drm_dev->mode_config.mutex);
		2415	drm_connector_list_iter_begin(drm_dev, &iter);
		2416	drm_for_each_connector_iter(list_connector, &iter) {
		2417	if (list_connector->status == connector_status_connected) {
		2418	ret = -EBUSY;
		2419	break;
		2420	}
		2421	}
		2422	drm_connector_list_iter_end(&iter);
		2423	mutex_unlock(&drm_dev->mode_config.mutex);
		2424
		2425	if (ret)
		2426	return ret;
		2427
		2428	if (amdgpu_device_has_dc_support(adev)) {
		2429	struct drm_crtc *crtc;
		2430
		2431	drm_for_each_crtc(crtc, drm_dev) {
		2432	drm_modeset_lock(&crtc->mutex, NULL);
		2433	if (crtc->state->active)
		2434	ret = -EBUSY;
		2435	drm_modeset_unlock(&crtc->mutex);
		2436	if (ret < 0)
		2437	break;
		2438	}
		2439	} else {
		2440	mutex_lock(&drm_dev->mode_config.mutex);
		2441	drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
		2442
		2443	drm_connector_list_iter_begin(drm_dev, &iter);
		2444	drm_for_each_connector_iter(list_connector, &iter) {
		2445	if (list_connector->dpms == DRM_MODE_DPMS_ON) {
		2446	ret = -EBUSY;
		2447	break;
		2448	}
		2449	}
		2450
		2451	drm_connector_list_iter_end(&iter);
		2452
		2453	drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
		2454	mutex_unlock(&drm_dev->mode_config.mutex);
		2455	}
		2456	if (ret)
		2457	return ret;
		2458	}
		2459
		2460	return 0;
		2461	}
		2462
2398	static int amdgpu_pmops_runtime_suspend(struct device *dev)	2463	static int amdgpu_pmops_runtime_suspend(struct device *dev)
2399	{	2464	{
2400	struct pci_dev *pdev = to_pci_dev(dev);	2465	struct pci_dev *pdev = to_pci_dev(dev);
@@ -2407,6 +2472,10 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) · 6 unmodified lines
2407	return -EBUSY;	2472	return -EBUSY;
2408	}	2473	}
2409		2474
		2475	ret = amdgpu_runtime_idle_check_display(dev);
		2476	if (ret)
		2477	return ret;
		2478
2410	/* wait for all rings to drain before suspending */	2479	/* wait for all rings to drain before suspending */
2411	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {	2480	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2412	struct amdgpu_ring *ring = adev->rings[i];	2481	struct amdgpu_ring *ring = adev->rings[i];
@@ -2516,41 +2585,7 @@ static int amdgpu_pmops_runtime_idle(struct device *dev) · 103 unmodified lines
2516	return -EBUSY;	2585	return -EBUSY;
2517	}	2586	}
2518		2587
2519	if (amdgpu_device_has_dc_support(adev)) {	2588	ret = amdgpu_runtime_idle_check_display(dev);
2520	struct drm_crtc *crtc;
2521
2522	drm_for_each_crtc(crtc, drm_dev) {
2523	drm_modeset_lock(&crtc->mutex, NULL);
2524	if (crtc->state->active)
2525	ret = -EBUSY;
2526	drm_modeset_unlock(&crtc->mutex);
2527	if (ret < 0)
2528	break;
2529	}
2530
2531	} else {
2532	struct drm_connector *list_connector;
2533	struct drm_connector_list_iter iter;
2534
2535	mutex_lock(&drm_dev->mode_config.mutex);
2536	drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2537
2538	drm_connector_list_iter_begin(drm_dev, &iter);
2539	drm_for_each_connector_iter(list_connector, &iter) {
2540	if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2541	ret = -EBUSY;
2542	break;
2543	}
2544	}
2545
2546	drm_connector_list_iter_end(&iter);
2547
2548	drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2549	mutex_unlock(&drm_dev->mode_config.mutex);
2550	}
2551
2552	if (ret == -EBUSY)
2553	DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
2554		2589
2555	pm_runtime_mark_last_busy(dev);	2590	pm_runtime_mark_last_busy(dev);
2556	pm_runtime_autosuspend(dev);	2591	pm_runtime_autosuspend(dev);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c+3−1

 #include <linux/module.h>
 #include <drm/drm_drv.h>
+#include <xen/xen.h>
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 	if (!reg) {
-		if (is_virtual_machine())	/* passthrough mode exclus sriov mod */
+		/* passthrough mode exclus sriov mod */
+		if (is_virtual_machine() && !xen_initial_domain())
 			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 	}

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+10−0

@@ -1151,6 +1151,16 @@ static int gmc_v10_0_set_clockgating_state(void *handle, · 1150 unmodified lines
1151	int r;	1151	int r;
1152	struct amdgpu_device adev = (struct amdgpu_device )handle;	1152	struct amdgpu_device adev = (struct amdgpu_device )handle;
1153		1153
		1154	/*
		1155	* The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
		1156	* is a new problem observed at DF 3.0.3, however with the same suspend sequence not
		1157	* seen any issue on the DF 3.0.2 series platform.
		1158	*/
		1159	if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) {
		1160	dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");
		1161	return 0;
		1162	}
		1163
1154	r = adev->mmhub.funcs->set_clockgating(adev, state);	1164	r = adev->mmhub.funcs->set_clockgating(adev, state);
1155	if (r)	1165	if (r)
1156	return r;	1166	return r;

drivers/gpu/drm/amd/amdgpu/vi.c+16−1

 #include "mxgpu_vi.h"
 #include "amdgpu_dm.h"
+#if IS_ENABLED(CONFIG_X86)
+#include <asm/intel-family.h>
+#endif
 #define ixPCIE_LC_L1_PM_SUBSTATE	0x100100C6
 #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK	0x00000001L
 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK	0x00000002L
 		WREG32_PCIE(ixPCIE_LC_CNTL, data);
 }
+static bool aspm_support_quirk_check(void)
+{
+#if IS_ENABLED(CONFIG_X86)
+	struct cpuinfo_x86 *c = &cpu_data(0);
+	return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
+#else
+	return true;
+#endif
+}
 static void vi_program_aspm(struct amdgpu_device *adev)
 {
 	u32 data, data1, orig;
 	bool bL1SS = false;
 	bool bClkReqSupport = true;
-	if (!amdgpu_device_should_use_aspm(adev))
+	if (!amdgpu_device_should_use_aspm(adev) || !aspm_support_quirk_check())
 		return;
 	if (adev->flags & AMD_IS_APU ||

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+37−46

@@ -130,19 +130,33 @@ void program_sh_mem_settings(struct device_queue_manager *dqm, · 129 unmodified lines
130	}	130	}
131		131
132	static void increment_queue_count(struct device_queue_manager *dqm,	132	static void increment_queue_count(struct device_queue_manager *dqm,
133	enum kfd_queue_type type)	133	struct qcm_process_device *qpd,
		134	struct queue *q)
134	{	135	{
135	dqm->active_queue_count++;	136	dqm->active_queue_count++;
136	if (type == KFD_QUEUE_TYPE_COMPUTE \|\| type == KFD_QUEUE_TYPE_DIQ)	137	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE \|\|
		138	q->properties.type == KFD_QUEUE_TYPE_DIQ)
137	dqm->active_cp_queue_count++;	139	dqm->active_cp_queue_count++;
		140
		141	if (q->properties.is_gws) {
		142	dqm->gws_queue_count++;
		143	qpd->mapped_gws_queue = true;
		144	}
138	}	145	}
139		146
140	static void decrement_queue_count(struct device_queue_manager *dqm,	147	static void decrement_queue_count(struct device_queue_manager *dqm,
141	enum kfd_queue_type type)	148	struct qcm_process_device *qpd,
		149	struct queue *q)
142	{	150	{
143	dqm->active_queue_count--;	151	dqm->active_queue_count--;
144	if (type == KFD_QUEUE_TYPE_COMPUTE \|\| type == KFD_QUEUE_TYPE_DIQ)	152	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE \|\|
		153	q->properties.type == KFD_QUEUE_TYPE_DIQ)
145	dqm->active_cp_queue_count--;	154	dqm->active_cp_queue_count--;
		155
		156	if (q->properties.is_gws) {
		157	dqm->gws_queue_count--;
		158	qpd->mapped_gws_queue = false;
		159	}
146	}	160	}
147		161
148	/*	162	/*
@@ -412,7 +426,7 @@ add_queue_to_list: · 263 unmodified lines
412	list_add(&q->list, &qpd->queues_list);	426	list_add(&q->list, &qpd->queues_list);
413	qpd->queue_count++;	427	qpd->queue_count++;
414	if (q->properties.is_active)	428	if (q->properties.is_active)
415	increment_queue_count(dqm, q->properties.type);	429	increment_queue_count(dqm, qpd, q);
416		430
417	/*	431	/*
418	* Unconditionally increment this counter, regardless of the queue's	432	* Unconditionally increment this counter, regardless of the queue's
@@ -601,13 +615,8 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, · 182 unmodified lines
601	deallocate_vmid(dqm, qpd, q);	615	deallocate_vmid(dqm, qpd, q);
602	}	616	}
603	qpd->queue_count--;	617	qpd->queue_count--;
604	if (q->properties.is_active) {	618	if (q->properties.is_active)
605	decrement_queue_count(dqm, q->properties.type);	619	decrement_queue_count(dqm, qpd, q);
606	if (q->properties.is_gws) {
607	dqm->gws_queue_count--;
608	qpd->mapped_gws_queue = false;
609	}
610	}
611		620
612	return retval;	621	return retval;
613	}	622	}
@@ -700,12 +709,11 @@ static int update_queue(struct device_queue_manager dqm, struct queue q, · 86 unmodified lines
700	* dqm->active_queue_count to determine whether a new runlist must be	709	* dqm->active_queue_count to determine whether a new runlist must be
701	* uploaded.	710	* uploaded.
702	*/	711	*/
703	if (q->properties.is_active && !prev_active)	712	if (q->properties.is_active && !prev_active) {
704	increment_queue_count(dqm, q->properties.type);	713	increment_queue_count(dqm, &pdd->qpd, q);
705	else if (!q->properties.is_active && prev_active)	714	} else if (!q->properties.is_active && prev_active) {
706	decrement_queue_count(dqm, q->properties.type);	715	decrement_queue_count(dqm, &pdd->qpd, q);
707		716	} else if (q->gws && !q->properties.is_gws) {
708	if (q->gws && !q->properties.is_gws) {
709	if (q->properties.is_active) {	717	if (q->properties.is_active) {
710	dqm->gws_queue_count++;	718	dqm->gws_queue_count++;
711	pdd->qpd.mapped_gws_queue = true;	719	pdd->qpd.mapped_gws_queue = true;
@@ -767,11 +775,7 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, · 55 unmodified lines
767	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(	775	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
768	q->properties.type)];	776	q->properties.type)];
769	q->properties.is_active = false;	777	q->properties.is_active = false;
770	decrement_queue_count(dqm, q->properties.type);	778	decrement_queue_count(dqm, qpd, q);
771	if (q->properties.is_gws) {
772	dqm->gws_queue_count--;
773	qpd->mapped_gws_queue = false;
774	}
775		779
776	if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))	780	if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
777	continue;	781	continue;
@@ -817,7 +821,7 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm, · 39 unmodified lines
817	continue;	821	continue;
818		822
819	q->properties.is_active = false;	823	q->properties.is_active = false;
820	decrement_queue_count(dqm, q->properties.type);	824	decrement_queue_count(dqm, qpd, q);
821	}	825	}
822	pdd->last_evict_timestamp = get_jiffies_64();	826	pdd->last_evict_timestamp = get_jiffies_64();
823	retval = execute_queues_cpsch(dqm,	827	retval = execute_queues_cpsch(dqm,
@@ -888,11 +892,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, · 64 unmodified lines
888	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(	892	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
889	q->properties.type)];	893	q->properties.type)];
890	q->properties.is_active = true;	894	q->properties.is_active = true;
891	increment_queue_count(dqm, q->properties.type);	895	increment_queue_count(dqm, qpd, q);
892	if (q->properties.is_gws) {
893	dqm->gws_queue_count++;
894	qpd->mapped_gws_queue = true;
895	}
896		896
897	if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))	897	if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
898	continue;	898	continue;
@@ -950,7 +950,7 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm, · 51 unmodified lines
950	continue;	950	continue;
951		951
952	q->properties.is_active = true;	952	q->properties.is_active = true;
953	increment_queue_count(dqm, q->properties.type);	953	increment_queue_count(dqm, &pdd->qpd, q);
954	}	954	}
955	retval = execute_queues_cpsch(dqm,	955	retval = execute_queues_cpsch(dqm,
956	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);	956	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
@@ -1378,7 +1378,7 @@ static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, · 421 unmodified lines
1378	dqm->total_queue_count);	1378	dqm->total_queue_count);
1379		1379
1380	list_add(&kq->list, &qpd->priv_queue_list);	1380	list_add(&kq->list, &qpd->priv_queue_list);
1381	increment_queue_count(dqm, kq->queue->properties.type);	1381	increment_queue_count(dqm, qpd, kq->queue);
1382	qpd->is_debug = true;	1382	qpd->is_debug = true;
1383	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);	1383	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1384	dqm_unlock(dqm);	1384	dqm_unlock(dqm);
@@ -1392,7 +1392,7 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, · 7 unmodified lines
1392	{	1392	{
1393	dqm_lock(dqm);	1393	dqm_lock(dqm);
1394	list_del(&kq->list);	1394	list_del(&kq->list);
1395	decrement_queue_count(dqm, kq->queue->properties.type);	1395	decrement_queue_count(dqm, qpd, kq->queue);
1396	qpd->is_debug = false;	1396	qpd->is_debug = false;
1397	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);	1397	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1398	/*	1398	/*
@@ -1467,7 +1467,7 @@ static int create_queue_cpsch(struct device_queue_manager dqm, struct queue q, · 68 unmodified lines
1467	qpd->queue_count++;	1467	qpd->queue_count++;
1468		1468
1469	if (q->properties.is_active) {	1469	if (q->properties.is_active) {
1470	increment_queue_count(dqm, q->properties.type);	1470	increment_queue_count(dqm, qpd, q);
1471		1471
1472	execute_queues_cpsch(dqm,	1472	execute_queues_cpsch(dqm,
1473	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);	1473	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
@@ -1683,15 +1683,11 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, · 209 unmodified lines
1683	list_del(&q->list);	1683	list_del(&q->list);
1684	qpd->queue_count--;	1684	qpd->queue_count--;
1685	if (q->properties.is_active) {	1685	if (q->properties.is_active) {
1686	decrement_queue_count(dqm, q->properties.type);	1686	decrement_queue_count(dqm, qpd, q);
1687	retval = execute_queues_cpsch(dqm,	1687	retval = execute_queues_cpsch(dqm,
1688	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);	1688	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1689	if (retval == -ETIME)	1689	if (retval == -ETIME)
1690	qpd->reset_wavefronts = true;	1690	qpd->reset_wavefronts = true;
1691	if (q->properties.is_gws) {
1692	dqm->gws_queue_count--;
1693	qpd->mapped_gws_queue = false;
1694	}
1695	}	1691	}
1696		1692
1697	/*	1693	/*
@@ -1932,7 +1928,7 @@ static int process_termination_cpsch(struct device_queue_manager *dqm, · 234 unmodified lines
1932	/* Clean all kernel queues */	1928	/* Clean all kernel queues */
1933	list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {	1929	list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
1934	list_del(&kq->list);	1930	list_del(&kq->list);
1935	decrement_queue_count(dqm, kq->queue->properties.type);	1931	decrement_queue_count(dqm, qpd, kq->queue);
1936	qpd->is_debug = false;	1932	qpd->is_debug = false;
1937	dqm->total_queue_count--;	1933	dqm->total_queue_count--;
1938	filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;	1934	filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
@@ -1945,13 +1941,8 @@ static int process_termination_cpsch(struct device_queue_manager *dqm, · 6 unmodified lines
1945	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)	1941	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1946	deallocate_sdma_queue(dqm, q);	1942	deallocate_sdma_queue(dqm, q);
1947		1943
1948	if (q->properties.is_active) {	1944	if (q->properties.is_active)
1949	decrement_queue_count(dqm, q->properties.type);	1945	decrement_queue_count(dqm, qpd, q);
1950	if (q->properties.is_gws) {
1951	dqm->gws_queue_count--;
1952	qpd->mapped_gws_queue = false;
1953	}
1954	}
1955		1946
1956	dqm->total_queue_count--;	1947	dqm->total_queue_count--;
1957	}	1948	}

drivers/gpu/drm/amd/amdkfd/kfd_priv.h+1−1

@@ -1103,7 +1103,7 @@ struct kfd_criu_queue_priv_data { · 1102 unmodified lines
1103	uint32_t priority;	1103	uint32_t priority;
1104	uint32_t q_percent;	1104	uint32_t q_percent;
1105	uint32_t doorbell_id;	1105	uint32_t doorbell_id;
1106	uint32_t is_gws;	1106	uint32_t gws;
1107	uint32_t sdma_id;	1107	uint32_t sdma_id;
1108	uint32_t eop_ring_buffer_size;	1108	uint32_t eop_ring_buffer_size;
1109	uint32_t ctx_save_restore_area_size;	1109	uint32_t ctx_save_restore_area_size;

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+7−3

 	q_data->ctx_save_restore_area_size =
 		q->properties.ctx_save_restore_area_size;
+	q_data->gws = !!q->gws;
 	ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack);
 	if (ret) {
 		pr_err("Failed checkpoint queue_mqd (%d)\n", ret);
 					  struct kfd_criu_queue_priv_data *q_data)
 {
 	qp->is_interop = false;
-	qp->is_gws = q_data->is_gws;
 	qp->queue_percent = q_data->q_percent;
 	qp->priority = q_data->priority;
 	qp->queue_address = q_data->q_address;
 				NULL);
 	if (ret) {
 		pr_err("Failed to create new queue err:%d\n", ret);
-		ret = -EINVAL;
+		goto exit;
 	}
+	if (q_data->gws)
+		ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws);
 exit:
 	if (ret)
-		pr_err("Failed to create queue (%d)\n", ret);
+		pr_err("Failed to restore queue (%d)\n", ret);
 	else
 		pr_debug("Queue id %d was restored successfully\n", queue_id);

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+1−1

@@ -4440,7 +4440,7 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video · 4439 unmodified lines
4440	&dpcd_pattern_type.value,	4440	&dpcd_pattern_type.value,
4441	sizeof(dpcd_pattern_type));	4441	sizeof(dpcd_pattern_type));
4442		4442
4443	channel_count = dpcd_test_mode.bits.channel_count + 1;	4443	channel_count = min(dpcd_test_mode.bits.channel_count + 1, AUDIO_CHANNELS_COUNT);
4444		4444
4445	// read pattern periods for requested channels when sawTooth pattern is requested	4445	// read pattern periods for requested channels when sawTooth pattern is requested
4446	if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH \|\|	4446	if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH \|\|

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c+1−0

@@ -997,6 +997,7 @@ static struct clock_source *dcn21_clock_source_create( · 996 unmodified lines
997	return &clk_src->base;	997	return &clk_src->base;
998	}	998	}
999		999
		1000	kfree(clk_src);
1000	BREAK_TO_DEBUGGER();	1001	BREAK_TO_DEBUGGER();
1001	return NULL;	1002	return NULL;
1002	}	1003	}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c+0−5

@@ -153,9 +153,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc) · 152 unmodified lines
153	dc->hwss.init_hw = dcn20_fpga_init_hw;	153	dc->hwss.init_hw = dcn20_fpga_init_hw;
154	dc->hwseq->funcs.init_pipes = NULL;	154	dc->hwseq->funcs.init_pipes = NULL;
155	}	155	}
156	if (dc->debug.disable_z10) {
157	/hw not support z10 or sw disable it/
158	dc->hwss.z10_restore = NULL;
159	dc->hwss.z10_save_init = NULL;
160	}
161	}	156	}

drivers/gpu/drm/amd/pm/amdgpu_dpm.c+39−0

@@ -427,6 +427,7 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso · 426 unmodified lines
427	void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev)	427	void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev)
428	{	428	{
429	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	429	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
		430	int i;
430		431
431	if (!adev->pm.dpm_enabled)	432	if (!adev->pm.dpm_enabled)
432	return;	433	return;
@@ -434,6 +435,15 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) · 1 unmodified line
434	if (!pp_funcs->pm_compute_clocks)	435	if (!pp_funcs->pm_compute_clocks)
435	return;	436	return;
436		437
		438	if (adev->mode_info.num_crtc)
		439	amdgpu_display_bandwidth_update(adev);
		440
		441	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
		442	struct amdgpu_ring *ring = adev->rings[i];
		443	if (ring && ring->sched.ready)
		444	amdgpu_fence_wait_empty(ring);
		445	}
		446
437	mutex_lock(&adev->pm.mutex);	447	mutex_lock(&adev->pm.mutex);
438	pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);	448	pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);
439	mutex_unlock(&adev->pm.mutex);	449	mutex_unlock(&adev->pm.mutex);
@@ -443,6 +453,20 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) · 3 unmodified lines
443	{	453	{
444	int ret = 0;	454	int ret = 0;
445		455
		456	if (adev->family == AMDGPU_FAMILY_SI) {
		457	mutex_lock(&adev->pm.mutex);
		458	if (enable) {
		459	adev->pm.dpm.uvd_active = true;
		460	adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
		461	} else {
		462	adev->pm.dpm.uvd_active = false;
		463	}
		464	mutex_unlock(&adev->pm.mutex);
		465
		466	amdgpu_dpm_compute_clocks(adev);
		467	return;
		468	}
		469
446	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);	470	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
447	if (ret)	471	if (ret)
448	DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",	472	DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
@@ -453,6 +477,21 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) · 4 unmodified lines
453	{	477	{
454	int ret = 0;	478	int ret = 0;
455		479
		480	if (adev->family == AMDGPU_FAMILY_SI) {
		481	mutex_lock(&adev->pm.mutex);
		482	if (enable) {
		483	adev->pm.dpm.vce_active = true;
		484	/* XXX select vce level based on ring/task */
		485	adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
		486	} else {
		487	adev->pm.dpm.vce_active = false;
		488	}
		489	mutex_unlock(&adev->pm.mutex);
		490
		491	amdgpu_dpm_compute_clocks(adev);
		492	return;
		493	}
		494
456	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);	495	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
457	if (ret)	496	if (ret)
458	DRM_ERROR("Dpm %s vce failed, ret = %d. \n",	497	DRM_ERROR("Dpm %s vce failed, ret = %d. \n",

drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c+0−10

@@ -1028,16 +1028,6 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) · 1027 unmodified lines
1028	void amdgpu_legacy_dpm_compute_clocks(void *handle)	1028	void amdgpu_legacy_dpm_compute_clocks(void *handle)
1029	{	1029	{
1030	struct amdgpu_device adev = (struct amdgpu_device )handle;	1030	struct amdgpu_device adev = (struct amdgpu_device )handle;
1031	int i = 0;
1032
1033	if (adev->mode_info.num_crtc)
1034	amdgpu_display_bandwidth_update(adev);
1035
1036	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1037	struct amdgpu_ring *ring = adev->rings[i];
1038	if (ring && ring->sched.ready)
1039	amdgpu_fence_wait_empty(ring);
1040	}
1041		1031
1042	amdgpu_dpm_get_active_displays(adev);	1032	amdgpu_dpm_get_active_displays(adev);
1043		1033

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c+0−35

@@ -3892,40 +3892,6 @@ static int si_set_boot_state(struct amdgpu_device *adev) · 3891 unmodified lines
3892	}	3892	}
3893	#endif	3893	#endif
3894		3894
3895	static int si_set_powergating_by_smu(void *handle,
3896	uint32_t block_type,
3897	bool gate)
3898	{
3899	struct amdgpu_device adev = (struct amdgpu_device )handle;
3900
3901	switch (block_type) {
3902	case AMD_IP_BLOCK_TYPE_UVD:
3903	if (!gate) {
3904	adev->pm.dpm.uvd_active = true;
3905	adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
3906	} else {
3907	adev->pm.dpm.uvd_active = false;
3908	}
3909
3910	amdgpu_legacy_dpm_compute_clocks(handle);
3911	break;
3912	case AMD_IP_BLOCK_TYPE_VCE:
3913	if (!gate) {
3914	adev->pm.dpm.vce_active = true;
3915	/* XXX select vce level based on ring/task */
3916	adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
3917	} else {
3918	adev->pm.dpm.vce_active = false;
3919	}
3920
3921	amdgpu_legacy_dpm_compute_clocks(handle);
3922	break;
3923	default:
3924	break;
3925	}
3926	return 0;
3927	}
3928
3929	static int si_set_sw_state(struct amdgpu_device *adev)	3895	static int si_set_sw_state(struct amdgpu_device *adev)
3930	{	3896	{
3931	return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?	3897	return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
@@ -8125,7 +8091,6 @@ static const struct amd_pm_funcs si_dpm_funcs = { · 4193 unmodified lines
8125	.print_power_state = &si_dpm_print_power_state,	8091	.print_power_state = &si_dpm_print_power_state,
8126	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,	8092	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8127	.force_performance_level = &si_dpm_force_performance_level,	8093	.force_performance_level = &si_dpm_force_performance_level,
8128	.set_powergating_by_smu = &si_set_powergating_by_smu,
8129	.vblank_too_short = &si_dpm_vblank_too_short,	8094	.vblank_too_short = &si_dpm_vblank_too_short,
8130	.set_fan_control_mode = &si_dpm_set_fan_control_mode,	8095	.set_fan_control_mode = &si_dpm_set_fan_control_mode,
8131	.get_fan_control_mode = &si_dpm_get_fan_control_mode,	8096	.get_fan_control_mode = &si_dpm_get_fan_control_mode,

drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c+0−10

@@ -1487,16 +1487,6 @@ static void pp_pm_compute_clocks(void *handle) · 1486 unmodified lines
1487	{	1487	{
1488	struct pp_hwmgr *hwmgr = handle;	1488	struct pp_hwmgr *hwmgr = handle;
1489	struct amdgpu_device *adev = hwmgr->adev;	1489	struct amdgpu_device *adev = hwmgr->adev;
1490	int i = 0;
1491
1492	if (adev->mode_info.num_crtc)
1493	amdgpu_display_bandwidth_update(adev);
1494
1495	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1496	struct amdgpu_ring *ring = adev->rings[i];
1497	if (ring && ring->sched.ready)
1498	amdgpu_fence_wait_empty(ring);
1499	}
1500		1490
1501	if (!amdgpu_device_has_dc_support(adev)) {	1491	if (!amdgpu_device_has_dc_support(adev)) {
1502	amdgpu_dpm_get_active_displays(adev);	1492	amdgpu_dpm_get_active_displays(adev);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+1−7

 {
 	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
-	/*
-	 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair
-	 * the workaround which always reset the asic in suspend.
-	 * It's likely that workaround will be dropped in the future.
-	 * Then the change here should be dropped together.
-	 */
 	bool use_baco = !smu->is_apu &&
-		(((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) &&
+		((amdgpu_in_reset(adev) &&
 		  (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
 		 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));

drivers/gpu/drm/bridge/Kconfig+1−0

@@ -78,6 +78,7 @@ config DRM_ITE_IT6505 · 77 unmodified lines
78	tristate "ITE IT6505 DisplayPort bridge"	78	tristate "ITE IT6505 DisplayPort bridge"
79	depends on OF	79	depends on OF
80	select DRM_KMS_HELPER	80	select DRM_KMS_HELPER
		81	select DRM_DP_HELPER
81	select EXTCON	82	select EXTCON
82	help	83	help
83	ITE IT6505 DisplayPort bridge chip driver.	84	ITE IT6505 DisplayPort bridge chip driver.

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c+26−8

 #define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_1                            0x359
+enum intel_dp_aux_backlight_modparam {
+	INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
+	INTEL_DP_AUX_BACKLIGHT_OFF = 0,
+	INTEL_DP_AUX_BACKLIGHT_ON = 1,
+	INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,
+	INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,
+};
 /* Intel EDP backlight callbacks */
 static bool
 intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
 		return false;
 	}
+	/*
+	 * If we don't have HDR static metadata there is no way to
+	 * runtime detect used range for nits based control. For now
+	 * do not use Intel proprietary eDP backlight control if we
+	 * don't have this data in panel EDID. In case we find panel
+	 * which supports only nits based control, but doesn't provide
+	 * HDR static metadata we need to start maintaining table of
+	 * ranges for such panels.
+	 */
+	if (i915->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
+	    !(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type &
+	      BIT(HDMI_STATIC_METADATA_TYPE1))) {
+		drm_info(&i915->drm,
+			 "Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d. needs this, please file a _new_ bug report on drm/i915, see " FDO_BUG_URL " for details.\n",
+			 INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL);
+		return false;
+	}
 	panel->backlight.edp.intel.sdr_uses_aux =
 		tcon_cap[2] & INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
 	.get = intel_dp_aux_vesa_get_backlight,
 };
-enum intel_dp_aux_backlight_modparam {
-	INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
-	INTEL_DP_AUX_BACKLIGHT_OFF = 0,
-	INTEL_DP_AUX_BACKLIGHT_ON = 1,
-	INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,
-	INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,
-};
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
 {
 	struct drm_device *dev = connector->base.dev;

drivers/gpu/drm/i915/display/intel_fbc.c+1−1

@@ -1037,7 +1037,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, · 1036 unmodified lines
1037	struct intel_plane_state *plane_state =	1037	struct intel_plane_state *plane_state =
1038	intel_atomic_get_new_plane_state(state, plane);	1038	intel_atomic_get_new_plane_state(state, plane);
1039	const struct drm_framebuffer *fb = plane_state->hw.fb;	1039	const struct drm_framebuffer *fb = plane_state->hw.fb;
1040	struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);	1040	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1041	const struct intel_crtc_state *crtc_state;	1041	const struct intel_crtc_state *crtc_state;
1042	struct intel_fbc *fbc = plane->fbc;	1042	struct intel_fbc *fbc = plane->fbc;
1043		1043

drivers/gpu/drm/i915/i915_reg.h+3−3

drivers/gpu/drm/i915/i915_vma.c+7−4

 static void __i915_vma_remove_closed(struct i915_vma *vma)
 {
-	struct intel_gt *gt = vma->vm->gt;
-	spin_lock_irq(&gt->closed_lock);
 	list_del_init(&vma->closed_link);
-	spin_unlock_irq(&gt->closed_lock);
 }
 void i915_vma_reopen(struct i915_vma *vma)
 {
+	struct intel_gt *gt = vma->vm->gt;
+	spin_lock_irq(&gt->closed_lock);
 	if (i915_vma_is_closed(vma))
 		__i915_vma_remove_closed(vma);
+	spin_unlock_irq(&gt->closed_lock);
 }
 void i915_vma_release(struct kref *ref)
 static void release_references(struct i915_vma *vma)
 {
 	struct drm_i915_gem_object *obj = vma->obj;
+	struct intel_gt *gt = vma->vm->gt;
 	GEM_BUG_ON(i915_vma_is_active(vma));
 		rb_erase(&vma->obj_node, &obj->vma.tree);
 	spin_unlock(&obj->vma.lock);
+	spin_lock_irq(&gt->closed_lock);
 	__i915_vma_remove_closed(vma);
+	spin_unlock_irq(&gt->closed_lock);
 	__i915_vma_put(vma);
 }

drivers/gpu/drm/msm/dp/dp_display.c+0−6

 			dp->dp_display.connector_type, state);
 	mutex_unlock(&dp->event_mutex);
-	/*
-	 * add fail safe mode outside event_mutex scope
-	 * to avoid potiential circular lock with drm thread
-	 */
-	dp_panel_add_fail_safe_mode(dp->dp_display.connector);
 	/* uevent will complete connection part */
 	return 0;
 };

drivers/gpu/drm/msm/dp/dp_panel.c+0−11

 	return rc;
 }
-void dp_panel_add_fail_safe_mode(struct drm_connector *connector)
-{
-	/* fail safe edid */
-	mutex_lock(&connector->dev->mode_config.mutex);
-	if (drm_add_modes_noedid(connector, 640, 480))
-		drm_set_preferred_mode(connector, 640, 480);
-	mutex_unlock(&connector->dev->mode_config.mutex);
-}
 int dp_panel_read_sink_caps(struct dp_panel *dp_panel,
 	struct drm_connector *connector)
 {
 			rc = -ETIMEDOUT;
 			goto end;
 		}
-		dp_panel_add_fail_safe_mode(connector);
 	}
 	if (panel->aux_cfg_update_done) {

drivers/gpu/drm/msm/dp/dp_panel.h+0−1

@@ -59,7 +59,6 @@ int dp_panel_init_panel_info(struct dp_panel *dp_panel); · 58 unmodified lines
59	int dp_panel_deinit(struct dp_panel *dp_panel);	59	int dp_panel_deinit(struct dp_panel *dp_panel);
60	int dp_panel_timing_cfg(struct dp_panel *dp_panel);	60	int dp_panel_timing_cfg(struct dp_panel *dp_panel);
61	void dp_panel_dump_regs(struct dp_panel *dp_panel);	61	void dp_panel_dump_regs(struct dp_panel *dp_panel);
62	void dp_panel_add_fail_safe_mode(struct drm_connector *connector);
63	int dp_panel_read_sink_caps(struct dp_panel *dp_panel,	62	int dp_panel_read_sink_caps(struct dp_panel *dp_panel,
64	struct drm_connector *connector);	63	struct drm_connector *connector);
65	u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp,	64	u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp,

drivers/gpu/drm/nouveau/nouveau_backlight.c+5−4

@@ -46,8 +46,9 @@ static bool · 45 unmodified lines
46	nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],	46	nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],
47	struct nouveau_backlight *bl)	47	struct nouveau_backlight *bl)
48	{	48	{
49	const int nb = ida_simple_get(&bl_ida, 0, 0, GFP_KERNEL);	49	const int nb = ida_alloc_max(&bl_ida, 99, GFP_KERNEL);
50	if (nb < 0 \|\| nb >= 100)	50
		51	if (nb < 0)
51	return false;	52	return false;
52	if (nb > 0)	53	if (nb > 0)
53	snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight%d", nb);	54	snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight%d", nb);
@@ -414,7 +415,7 @@ nouveau_backlight_init(struct drm_connector *connector) · 360 unmodified lines
414	nv_encoder, ops, &props);	415	nv_encoder, ops, &props);
415	if (IS_ERR(bl->dev)) {	416	if (IS_ERR(bl->dev)) {
416	if (bl->id >= 0)	417	if (bl->id >= 0)
417	ida_simple_remove(&bl_ida, bl->id);	418	ida_free(&bl_ida, bl->id);
418	ret = PTR_ERR(bl->dev);	419	ret = PTR_ERR(bl->dev);
419	goto fail_alloc;	420	goto fail_alloc;
420	}	421	}
@@ -442,7 +443,7 @@ nouveau_backlight_fini(struct drm_connector *connector) · 21 unmodified lines
442	return;	443	return;
443		444
444	if (bl->id >= 0)	445	if (bl->id >= 0)
445	ida_simple_remove(&bl_ida, bl->id);	446	ida_free(&bl_ida, bl->id);
446		447
447	backlight_device_unregister(bl->dev);	448	backlight_device_unregister(bl->dev);
448	nv_conn->backlight = NULL;	449	nv_conn->backlight = NULL;

drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c+1−1

@@ -123,7 +123,7 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) · 122 unmodified lines
123		123
124	mutex_init(&tdev->iommu.mutex);	124	mutex_init(&tdev->iommu.mutex);
125		125
126	if (iommu_present(&platform_bus_type)) {	126	if (device_iommu_mapped(dev)) {
127	tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type);	127	tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type);
128	if (!tdev->iommu.domain)	128	if (!tdev->iommu.domain)
129	goto error;	129	goto error;

drivers/gpu/drm/sun4i/sun4i_frontend.c+0−3

 	/* Set the physical address of the buffer in memory */
 	paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
-	paddr -= PHYS_OFFSET;
 	DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr);
 	regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr);
 	if (fb->format->num_planes > 1) {
 		paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 2 : 1);
-		paddr -= PHYS_OFFSET;
 		DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr);
 		regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG,
 			     paddr);
 	if (fb->format->num_planes > 2) {
 		paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 1 : 2);
-		paddr -= PHYS_OFFSET;
 		DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr);
 		regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG,
 			     paddr);

drivers/gpu/drm/vc4/vc4_hdmi.c+1−0

@@ -38,6 +38,7 @@ · 37 unmodified lines
38	#include <drm/drm_scdc_helper.h>	38	#include <drm/drm_scdc_helper.h>
39	#include <linux/clk.h>	39	#include <linux/clk.h>
40	#include <linux/component.h>	40	#include <linux/component.h>
		41	#include <linux/gpio/consumer.h>
41	#include <linux/i2c.h>	42	#include <linux/i2c.h>
42	#include <linux/of_address.h>	43	#include <linux/of_address.h>
43	#include <linux/of_gpio.h>	44	#include <linux/of_gpio.h>

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c+8−5

 		*seqno = atomic_add_return(1, &dev_priv->marker_seq);
 	} while (*seqno == 0);
-	if (!(vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_FENCE)) {
+	if (!vmw_has_fences(dev_priv)) {
 		/*
 		 * Don't request hardware to send a fence. The
  */
 bool vmw_cmd_supported(struct vmw_private *vmw)
 {
-	if ((vmw->capabilities & (SVGA_CAP_COMMAND_BUFFERS |
+	bool has_cmdbufs =
-				  SVGA_CAP_CMD_BUFFERS_2)) != 0)
+		(vmw->capabilities & (SVGA_CAP_COMMAND_BUFFERS |
-		return true;
+				      SVGA_CAP_CMD_BUFFERS_2)) != 0;
+	if (vmw_is_svga_v3(vmw))
+		return (has_cmdbufs &&
+			(vmw->capabilities & SVGA_CAP_GBOBJECTS) != 0);
 	/*
 	 * We have FIFO cmd's
 	 */
-	return vmw->fifo_mem != NULL;
+	return has_cmdbufs || vmw->fifo_mem != NULL;
 }

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h+8−0

@@ -1679,4 +1679,12 @@ static inline void vmw_irq_status_write(struct vmw_private *vmw, · 1678 unmodified lines
1679	outl(status, vmw->io_start + SVGA_IRQSTATUS_PORT);	1679	outl(status, vmw->io_start + SVGA_IRQSTATUS_PORT);
1680	}	1680	}
1681		1681
		1682	static inline bool vmw_has_fences(struct vmw_private *vmw)
		1683	{
		1684	if ((vmw->capabilities & (SVGA_CAP_COMMAND_BUFFERS \|
		1685	SVGA_CAP_CMD_BUFFERS_2)) != 0)
		1686	return true;
		1687	return (vmw_fifo_caps(vmw) & SVGA_FIFO_CAP_FENCE) != 0;
		1688	}
		1689
1682	#endif	1690	#endif

drivers/gpu/drm/vmwgfx/vmwgfx_fb.c+1−1

@@ -483,7 +483,7 @@ static int vmw_fb_kms_detach(struct vmw_fb_par *par, · 482 unmodified lines
483		483
484	static int vmw_fb_kms_framebuffer(struct fb_info *info)	484	static int vmw_fb_kms_framebuffer(struct fb_info *info)
485	{	485	{
486	struct drm_mode_fb_cmd2 mode_cmd;	486	struct drm_mode_fb_cmd2 mode_cmd = {0};
487	struct vmw_fb_par *par = info->par;	487	struct vmw_fb_par *par = info->par;
488	struct fb_var_screeninfo *var = &info->var;	488	struct fb_var_screeninfo *var = &info->var;
489	struct drm_framebuffer *cur_fb;	489	struct drm_framebuffer *cur_fb;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c+21−7

 	return container_of(fence->base.lock, struct vmw_fence_manager, lock);
 }
+static u32 vmw_fence_goal_read(struct vmw_private *vmw)
+{
+	if ((vmw->capabilities2 & SVGA_CAP2_EXTRA_REGS) != 0)
+		return vmw_read(vmw, SVGA_REG_FENCE_GOAL);
+	else
+		return vmw_fifo_mem_read(vmw, SVGA_FIFO_FENCE_GOAL);
+}
+static void vmw_fence_goal_write(struct vmw_private *vmw, u32 value)
+{
+	if ((vmw->capabilities2 & SVGA_CAP2_EXTRA_REGS) != 0)
+		vmw_write(vmw, SVGA_REG_FENCE_GOAL, value);
+	else
+		vmw_fifo_mem_write(vmw, SVGA_FIFO_FENCE_GOAL, value);
+}
 /*
  * Note on fencing subsystem usage of irqs:
  * Typically the vmw_fences_update function is called
 	if (likely(!fman->seqno_valid))
 		return false;
-	goal_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE_GOAL);
+	goal_seqno = vmw_fence_goal_read(fman->dev_priv);
 	if (likely(passed_seqno - goal_seqno >= VMW_FENCE_WRAP))
 		return false;
 	list_for_each_entry(fence, &fman->fence_list, head) {
 		if (!list_empty(&fence->seq_passed_actions)) {
 			fman->seqno_valid = true;
-			vmw_fifo_mem_write(fman->dev_priv,
+			vmw_fence_goal_write(fman->dev_priv,
-					   SVGA_FIFO_FENCE_GOAL,
+					     fence->base.seqno);
-					   fence->base.seqno);
 			break;
 		}
 	}
 	if (dma_fence_is_signaled_locked(&fence->base))
 		return false;
-	goal_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE_GOAL);
+	goal_seqno = vmw_fence_goal_read(fman->dev_priv);
 	if (likely(fman->seqno_valid &&
 		   goal_seqno - fence->base.seqno < VMW_FENCE_WRAP))
 		return false;
-	vmw_fifo_mem_write(fman->dev_priv, SVGA_FIFO_FENCE_GOAL,
+	vmw_fence_goal_write(fman->dev_priv, fence->base.seqno);
-			   fence->base.seqno);
 	fman->seqno_valid = true;
 	return true;

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c+18−8

 #define VMW_FENCE_WRAP (1 << 24)
+static u32 vmw_irqflag_fence_goal(struct vmw_private *vmw)
+{
+	if ((vmw->capabilities2 & SVGA_CAP2_EXTRA_REGS) != 0)
+		return SVGA_IRQFLAG_REG_FENCE_GOAL;
+	else
+		return SVGA_IRQFLAG_FENCE_GOAL;
+}
 /**
  * vmw_thread_fn - Deferred (process context) irq handler
  *
 		wake_up_all(&dev_priv->fifo_queue);
 	if ((masked_status & (SVGA_IRQFLAG_ANY_FENCE |
-			      SVGA_IRQFLAG_FENCE_GOAL)) &&
+			      vmw_irqflag_fence_goal(dev_priv))) &&
 	    !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending))
 		ret = IRQ_WAKE_THREAD;
 	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
 		return true;
-	if (!(vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_FENCE) &&
+	if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno))
-	    vmw_fifo_idle(dev_priv, seqno))
 		return true;
 	/**
 		      unsigned long timeout)
 {
 	struct vmw_fifo_state *fifo_state = dev_priv->fifo;
+	bool fifo_down = false;
 	uint32_t count = 0;
 	uint32_t signal_seq;
 	 */
 	if (fifo_idle) {
-		down_read(&fifo_state->rwsem);
 		if (dev_priv->cman) {
 			ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible,
 					      10*HZ);
 			if (ret)
 				goto out_err;
+		} else if (fifo_state) {
+			down_read(&fifo_state->rwsem);
+			fifo_down = true;
 		}
 	}
 		}
 	}
 	finish_wait(&dev_priv->fence_queue, &__wait);
-	if (ret == 0 && fifo_idle)
+	if (ret == 0 && fifo_idle && fifo_state)
 		vmw_fence_write(dev_priv, signal_seq);
 	wake_up_all(&dev_priv->fence_queue);
 out_err:
-	if (fifo_idle)
+	if (fifo_down)
 		up_read(&fifo_state->rwsem);
 	return ret;
 void vmw_goal_waiter_add(struct vmw_private *dev_priv)
 {
-	vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
+	vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv),
 			       &dev_priv->goal_queue_waiters);
 }
 void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
 {
-	vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
+	vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv),
 				  &dev_priv->goal_queue_waiters);
 }

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c+5−3

 		ret = vmw_kms_new_framebuffer_surface(dev_priv, surface, &vfb,
 						      mode_cmd,
 						      is_bo_proxy);
 		/*
 		 * vmw_create_bo_proxy() adds a reference that is no longer
 		 * needed
 	ret = vmw_user_lookup_handle(dev_priv, file_priv,
 				     mode_cmd->handles[0],
 				     &surface, &bo);
-	if (ret)
+	if (ret) {
+		DRM_ERROR("Invalid buffer object handle %u (0x%x).\n",
+			  mode_cmd->handles[0], mode_cmd->handles[0]);
 		goto err_out;
+	}
 	if (!bo &&
 	    !vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height)) {
-		DRM_ERROR("Surface size cannot exceed %dx%d",
+		DRM_ERROR("Surface size cannot exceed %dx%d\n",
 			dev_priv->texture_max_width,
 			dev_priv->texture_max_height);
 		goto err_out;

drivers/hwmon/Kconfig+1−1

@@ -960,7 +960,7 @@ config SENSORS_LTC4261 · 959 unmodified lines
960		960
961	config SENSORS_LTQ_CPUTEMP	961	config SENSORS_LTQ_CPUTEMP
962	bool "Lantiq cpu temperature sensor driver"	962	bool "Lantiq cpu temperature sensor driver"
963	depends on LANTIQ	963	depends on SOC_XWAY
964	help	964	help
965	If you say yes here you get support for the temperature	965	If you say yes here you get support for the temperature
966	sensor inside your CPU.	966	sensor inside your CPU.

drivers/hwmon/adt7470.c+2−2

 #include <linux/log2.h>
 #include <linux/kthread.h>
 #include <linux/regmap.h>
+#include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/util_macros.h>
 		adt7470_read_temperatures(data);
 		mutex_unlock(&data->lock);
-		set_current_state(TASK_INTERRUPTIBLE);
 		if (kthread_should_stop())
 			break;
-		schedule_timeout(msecs_to_jiffies(data->auto_update_interval));
+		schedule_timeout_interruptible(msecs_to_jiffies(data->auto_update_interval));
 	}
 	return 0;

drivers/hwmon/asus_wmi_sensors.c+1−1

@@ -71,7 +71,7 @@ static const struct dmi_system_id asus_wmi_dmi_table[] = { · 70 unmodified lines
71	DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X399-A"),	71	DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X399-A"),
72	DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X470-PRO"),	72	DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X470-PRO"),
73	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VI EXTREME"),	73	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VI EXTREME"),
74	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VI HERO"),	74	DMI_EXACT_MATCH_ASUS_BOARD_NAME("CROSSHAIR VI HERO"),
75	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VI HERO (WI-FI AC)"),	75	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VI HERO (WI-FI AC)"),
76	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VII HERO"),	76	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VII HERO"),
77	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VII HERO (WI-FI)"),	77	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VII HERO (WI-FI)"),

drivers/hwmon/f71882fg.c+3−2

 		temp *= 125;
 		if (sign)
 			temp -= 128000;
-	} else
+	} else {
-		temp = data->temp[nr] * 1000;
+		temp = ((s8)data->temp[nr]) * 1000;
+	}
 	return sprintf(buf, "%d\n", temp);
 }

drivers/hwmon/pmbus/delta-ahe50dc-fan.c+16−0

@@ -14,6 +14,21 @@ · 13 unmodified lines
14		14
15	#define AHE50DC_PMBUS_READ_TEMP4 0xd0	15	#define AHE50DC_PMBUS_READ_TEMP4 0xd0
16		16
		17	static int ahe50dc_fan_write_byte(struct i2c_client *client, int page, u8 value)
		18	{
		19	/*
		20	* The CLEAR_FAULTS operation seems to sometimes (unpredictably, perhaps
		21	* 5% of the time or so) trigger a problematic phenomenon in which the
		22	* fan speeds surge momentarily and at least some (perhaps all?) of the
		23	* system's power outputs experience a glitch.
		24	*
		25	* However, according to Delta it should be OK to simply not send any
		26	* CLEAR_FAULTS commands (the device doesn't seem to be capable of
		27	* reporting any faults anyway), so just blackhole them unconditionally.
		28	*/
		29	return value == PMBUS_CLEAR_FAULTS ? -EOPNOTSUPP : -ENODATA;
		30	}
		31
17	static int ahe50dc_fan_read_word_data(struct i2c_client *client, int page, int phase, int reg)	32	static int ahe50dc_fan_read_word_data(struct i2c_client *client, int page, int phase, int reg)
18	{	33	{
19	/* temp1 in (virtual) page 1 is remapped to mfr-specific temp4 */	34	/* temp1 in (virtual) page 1 is remapped to mfr-specific temp4 */
@@ -68,6 +83,7 @@ static struct pmbus_driver_info ahe50dc_fan_info = { · 48 unmodified lines
68	PMBUS_HAVE_VIN \| PMBUS_HAVE_FAN12 \| PMBUS_HAVE_FAN34 \|	83	PMBUS_HAVE_VIN \| PMBUS_HAVE_FAN12 \| PMBUS_HAVE_FAN34 \|
69	PMBUS_HAVE_STATUS_FAN12 \| PMBUS_HAVE_STATUS_FAN34 \| PMBUS_PAGE_VIRTUAL,	84	PMBUS_HAVE_STATUS_FAN12 \| PMBUS_HAVE_STATUS_FAN34 \| PMBUS_PAGE_VIRTUAL,
70	.func[1] = PMBUS_HAVE_TEMP \| PMBUS_PAGE_VIRTUAL,	85	.func[1] = PMBUS_HAVE_TEMP \| PMBUS_PAGE_VIRTUAL,
		86	.write_byte = ahe50dc_fan_write_byte,
71	.read_word_data = ahe50dc_fan_read_word_data,	87	.read_word_data = ahe50dc_fan_read_word_data,
72	};	88	};
73		89

drivers/hwmon/pmbus/pmbus_core.c+3−0

@@ -2326,6 +2326,9 @@ static int pmbus_init_common(struct i2c_client client, struct pmbus_data data, · 2325 unmodified lines
2326	data->has_status_word = true;	2326	data->has_status_word = true;
2327	}	2327	}
2328		2328
		2329	/* Make sure PEC is disabled, will be enabled later if needed */
		2330	client->flags &= ~I2C_CLIENT_PEC;
		2331
2329	/* Enable PEC if the controller and bus supports it */	2332	/* Enable PEC if the controller and bus supports it */
2330	if (!(data->flags & PMBUS_NO_CAPABILITY)) {	2333	if (!(data->flags & PMBUS_NO_CAPABILITY)) {
2331	ret = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY);	2334	ret = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY);

drivers/hwmon/pmbus/xdpe12284.c+1−1

@@ -124,7 +124,7 @@ static int xdpe122_identify(struct i2c_client *client, · 123 unmodified lines
124	return 0;	124	return 0;
125	}	125	}
126		126
127	static const struct regulator_desc xdpe122_reg_desc[] = {	127	static const struct regulator_desc __maybe_unused xdpe122_reg_desc[] = {
128	PMBUS_REGULATOR("vout", 0),	128	PMBUS_REGULATOR("vout", 0),
129	PMBUS_REGULATOR("vout", 1),	129	PMBUS_REGULATOR("vout", 1),
130	};	130	};

drivers/hwmon/tmp401.c+11−0

@@ -708,10 +708,21 @@ static int tmp401_probe(struct i2c_client *client) · 707 unmodified lines
708	return 0;	708	return 0;
709	}	709	}
710		710
		711	static const struct of_device_id __maybe_unused tmp4xx_of_match[] = {
		712	{ .compatible = "ti,tmp401", },
		713	{ .compatible = "ti,tmp411", },
		714	{ .compatible = "ti,tmp431", },
		715	{ .compatible = "ti,tmp432", },
		716	{ .compatible = "ti,tmp435", },
		717	{ },
		718	};
		719	MODULE_DEVICE_TABLE(of, tmp4xx_of_match);
		720
711	static struct i2c_driver tmp401_driver = {	721	static struct i2c_driver tmp401_driver = {
712	.class = I2C_CLASS_HWMON,	722	.class = I2C_CLASS_HWMON,
713	.driver = {	723	.driver = {
714	.name = "tmp401",	724	.name = "tmp401",
		725	.of_match_table = of_match_ptr(tmp4xx_of_match),
715	},	726	},
716	.probe_new = tmp401_probe,	727	.probe_new = tmp401_probe,
717	.id_table = tmp401_id,	728	.id_table = tmp401_id,

drivers/idle/intel_idle.c+15−12

@@ -69,7 +69,12 @@ static unsigned int preferred_states_mask; · 68 unmodified lines
69	static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;	69	static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
70		70
71	static unsigned long auto_demotion_disable_flags;	71	static unsigned long auto_demotion_disable_flags;
72	static bool disable_promotion_to_c1e;	72
		73	static enum {
		74	C1E_PROMOTION_PRESERVE,
		75	C1E_PROMOTION_ENABLE,
		76	C1E_PROMOTION_DISABLE
		77	} c1e_promotion = C1E_PROMOTION_PRESERVE;
73		78
74	struct idle_cpu {	79	struct idle_cpu {
75	struct cpuidle_state *state_table;	80	struct cpuidle_state *state_table;
@@ -1398,8 +1403,6 @@ static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { } · 1322 unmodified lines
1398	static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }	1403	static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1399	#endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */	1404	#endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1400		1405
1401	static void c1e_promotion_enable(void);
1402
1403	/**	1406	/**
1404	* ivt_idle_state_table_update - Tune the idle states table for Ivy Town.	1407	* ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1405	*	1408	*
@@ -1578,17 +1581,14 @@ static void __init spr_idle_state_table_update(void) · 172 unmodified lines
1578	unsigned long long msr;	1581	unsigned long long msr;
1579		1582
1580	/* Check if user prefers C1E over C1. */	1583	/* Check if user prefers C1E over C1. */
1581	if (preferred_states_mask & BIT(2)) {	1584	if ((preferred_states_mask & BIT(2)) &&
1582	if (preferred_states_mask & BIT(1))	1585	!(preferred_states_mask & BIT(1))) {
1583	/* Both can't be enabled, stick to the defaults. */	1586	/* Disable C1 and enable C1E. */
1584	return;
1585
1586	spr_cstates[0].flags \|= CPUIDLE_FLAG_UNUSABLE;	1587	spr_cstates[0].flags \|= CPUIDLE_FLAG_UNUSABLE;
1587	spr_cstates[1].flags &= ~CPUIDLE_FLAG_UNUSABLE;	1588	spr_cstates[1].flags &= ~CPUIDLE_FLAG_UNUSABLE;
1588		1589
1589	/* Enable C1E using the "C1E promotion" bit. */	1590	/* Enable C1E using the "C1E promotion" bit. */
1590	c1e_promotion_enable();	1591	c1e_promotion = C1E_PROMOTION_ENABLE;
1591	disable_promotion_to_c1e = false;
1592	}	1592	}
1593		1593
1594	/*	1594	/*
@@ -1754,7 +1754,9 @@ static int intel_idle_cpu_init(unsigned int cpu) · 159 unmodified lines
1754	if (auto_demotion_disable_flags)	1754	if (auto_demotion_disable_flags)
1755	auto_demotion_disable();	1755	auto_demotion_disable();
1756		1756
1757	if (disable_promotion_to_c1e)	1757	if (c1e_promotion == C1E_PROMOTION_ENABLE)
		1758	c1e_promotion_enable();
		1759	else if (c1e_promotion == C1E_PROMOTION_DISABLE)
1758	c1e_promotion_disable();	1760	c1e_promotion_disable();
1759		1761
1760	return 0;	1762	return 0;
@@ -1833,7 +1835,8 @@ static int __init intel_idle_init(void) · 72 unmodified lines
1833	if (icpu) {	1835	if (icpu) {
1834	cpuidle_state_table = icpu->state_table;	1836	cpuidle_state_table = icpu->state_table;
1835	auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;	1837	auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1836	disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;	1838	if (icpu->disable_promotion_to_c1e)
		1839	c1e_promotion = C1E_PROMOTION_DISABLE;
1837	if (icpu->use_acpi \|\| force_use_acpi)	1840	if (icpu->use_acpi \|\| force_use_acpi)
1838	intel_idle_acpi_cst_extract();	1841	intel_idle_acpi_cst_extract();
1839	} else if (!intel_idle_acpi_cst_extract()) {	1842	} else if (!intel_idle_acpi_cst_extract()) {

drivers/iio/adc/ad7280a.c+6−6

@@ -745,7 +745,7 @@ static int ad7280a_write_thresh(struct iio_dev *indio_dev, · 744 unmodified lines
745	case IIO_EV_DIR_RISING:	745	case IIO_EV_DIR_RISING:
746	addr = AD7280A_CELL_OVERVOLTAGE_REG;	746	addr = AD7280A_CELL_OVERVOLTAGE_REG;
747	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,	747	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
748	1, val);	748	1, value);
749	if (ret)	749	if (ret)
750	break;	750	break;
751	st->cell_threshhigh = value;	751	st->cell_threshhigh = value;
@@ -753,7 +753,7 @@ static int ad7280a_write_thresh(struct iio_dev *indio_dev, · 1 unmodified line
753	case IIO_EV_DIR_FALLING:	753	case IIO_EV_DIR_FALLING:
754	addr = AD7280A_CELL_UNDERVOLTAGE_REG;	754	addr = AD7280A_CELL_UNDERVOLTAGE_REG;
755	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,	755	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
756	1, val);	756	1, value);
757	if (ret)	757	if (ret)
758	break;	758	break;
759	st->cell_threshlow = value;	759	st->cell_threshlow = value;
@@ -770,18 +770,18 @@ static int ad7280a_write_thresh(struct iio_dev *indio_dev, · 10 unmodified lines
770	case IIO_EV_DIR_RISING:	770	case IIO_EV_DIR_RISING:
771	addr = AD7280A_AUX_ADC_OVERVOLTAGE_REG;	771	addr = AD7280A_AUX_ADC_OVERVOLTAGE_REG;
772	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,	772	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
773	1, val);	773	1, value);
774	if (ret)	774	if (ret)
775	break;	775	break;
776	st->aux_threshhigh = val;	776	st->aux_threshhigh = value;
777	break;	777	break;
778	case IIO_EV_DIR_FALLING:	778	case IIO_EV_DIR_FALLING:
779	addr = AD7280A_AUX_ADC_UNDERVOLTAGE_REG;	779	addr = AD7280A_AUX_ADC_UNDERVOLTAGE_REG;
780	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,	780	ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
781	1, val);	781	1, value);
782	if (ret)	782	if (ret)
783	break;	783	break;
784	st->aux_threshlow = val;	784	st->aux_threshlow = value;
785	break;	785	break;
786	default:	786	default:
787	ret = -EINVAL;	787	ret = -EINVAL;

drivers/iio/chemical/scd4x.c+4−1

 	ret = scd4x_write_and_fetch(state, CMD_FRC, arg, &val, sizeof(val));
 	mutex_unlock(&state->lock);
+	if (ret)
+		return ret;
 	if (val == 0xff) {
 		dev_err(dev, "forced calibration has failed");
 		return -EINVAL;
 	}
-	return ret ?: len;
+	return len;
 }
 static IIO_DEVICE_ATTR_RW(calibration_auto_enable, 0);

drivers/iio/dac/ad3552r.c+3−3

@@ -656,7 +656,7 @@ static int ad3552r_reset(struct ad3552r_desc *dac) · 655 unmodified lines
656	{	656	{
657	struct reg_addr_pool addr;	657	struct reg_addr_pool addr;
658	int ret;	658	int ret;
659	u16 val;	659	int val;
660		660
661	dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",	661	dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
662	GPIOD_OUT_LOW);	662	GPIOD_OUT_LOW);
@@ -809,10 +809,10 @@ static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac, · 146 unmodified lines
809		809
810	gain_child = fwnode_get_named_child_node(child,	810	gain_child = fwnode_get_named_child_node(child,
811	"custom-output-range-config");	811	"custom-output-range-config");
812	if (IS_ERR(gain_child)) {	812	if (!gain_child) {
813	dev_err(dev,	813	dev_err(dev,
814	"mandatory custom-output-range-config property missing\n");	814	"mandatory custom-output-range-config property missing\n");
815	return PTR_ERR(gain_child);	815	return -EINVAL;
816	}	816	}
817		817
818	dac->ch_data[ch].range_override = 1;	818	dac->ch_data[ch].range_override = 1;

drivers/iio/dac/ad5446.c+1−1

@@ -178,7 +178,7 @@ static int ad5446_read_raw(struct iio_dev *indio_dev, · 177 unmodified lines
178		178
179	switch (m) {	179	switch (m) {
180	case IIO_CHAN_INFO_RAW:	180	case IIO_CHAN_INFO_RAW:
181	*val = st->cached_val;	181	*val = st->cached_val >> chan->scan_type.shift;
182	return IIO_VAL_INT;	182	return IIO_VAL_INT;
183	case IIO_CHAN_INFO_SCALE:	183	case IIO_CHAN_INFO_SCALE:
184	*val = st->vref_mv;	184	*val = st->vref_mv;

drivers/iio/dac/ad5592r-base.c+1−1

@@ -522,7 +522,7 @@ static int ad5592r_alloc_channels(struct iio_dev *iio_dev) · 521 unmodified lines
522	if (!ret)	522	if (!ret)
523	st->channel_modes[reg] = tmp;	523	st->channel_modes[reg] = tmp;
524		524
525	fwnode_property_read_u32(child, "adi,off-state", &tmp);	525	ret = fwnode_property_read_u32(child, "adi,off-state", &tmp);
526	if (!ret)	526	if (!ret)
527	st->channel_offstate[reg] = tmp;	527	st->channel_offstate[reg] = tmp;
528	}	528	}

drivers/iio/dac/ltc2688.c+1−1

@@ -298,7 +298,7 @@ static int ltc2688_read_raw(struct iio_dev *indio_dev, · 297 unmodified lines
298	if (ret)	298	if (ret)
299	return ret;	299	return ret;
300		300
301	*val = 16;	301	*val2 = 16;
302	return IIO_VAL_FRACTIONAL_LOG2;	302	return IIO_VAL_FRACTIONAL_LOG2;
303	case IIO_CHAN_INFO_CALIBBIAS:	303	case IIO_CHAN_INFO_CALIBBIAS:
304	ret = regmap_read(st->regmap,	304	ret = regmap_read(st->regmap,

drivers/iio/dac/ti-dac5571.c+18−10

 #include <linux/i2c.h>
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
+#include <linux/property.h>
 #include <linux/regulator/consumer.h>
 enum chip_id {
 	const struct dac5571_spec *spec;
 	struct dac5571_data *data;
 	struct iio_dev *indio_dev;
+	enum chip_id chip_id;
 	int ret, i;
 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
 	indio_dev->modes = INDIO_DIRECT_MODE;
 	indio_dev->channels = dac5571_channels;
-	spec = &dac5571_spec[id->driver_data];
+	if (dev_fwnode(dev))
+		chip_id = (uintptr_t)device_get_match_data(dev);
+	else
+		chip_id = id->driver_data;
+	spec = &dac5571_spec[chip_id];
 	indio_dev->num_channels = spec->num_channels;
 	data->spec = spec;
 }
 static const struct of_device_id dac5571_of_id[] = {
-	{.compatible = "ti,dac5571"},
+	{.compatible = "ti,dac5571", .data = (void *)single_8bit},
-	{.compatible = "ti,dac6571"},
+	{.compatible = "ti,dac6571", .data = (void *)single_10bit},
-	{.compatible = "ti,dac7571"},
+	{.compatible = "ti,dac7571", .data = (void *)single_12bit},
-	{.compatible = "ti,dac5574"},
+	{.compatible = "ti,dac5574", .data = (void *)quad_8bit},
-	{.compatible = "ti,dac6574"},
+	{.compatible = "ti,dac6574", .data = (void *)quad_10bit},
-	{.compatible = "ti,dac7574"},
+	{.compatible = "ti,dac7574", .data = (void *)quad_12bit},
-	{.compatible = "ti,dac5573"},
+	{.compatible = "ti,dac5573", .data = (void *)quad_8bit},
-	{.compatible = "ti,dac6573"},
+	{.compatible = "ti,dac6573", .data = (void *)quad_10bit},
-	{.compatible = "ti,dac7573"},
+	{.compatible = "ti,dac7573", .data = (void *)quad_12bit},
 	{}
 };
 MODULE_DEVICE_TABLE(of, dac5571_of_id);

drivers/iio/filter/Kconfig+1−0

@@ -8,6 +8,7 @@ menu "Filters" · 7 unmodified lines
8	config ADMV8818	8	config ADMV8818
9	tristate "Analog Devices ADMV8818 High-Pass and Low-Pass Filter"	9	tristate "Analog Devices ADMV8818 High-Pass and Low-Pass Filter"
10	depends on SPI && COMMON_CLK && 64BIT	10	depends on SPI && COMMON_CLK && 64BIT
		11	select REGMAP_SPI
11	help	12	help
12	Say yes here to build support for Analog Devices ADMV8818	13	Say yes here to build support for Analog Devices ADMV8818
13	2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter.	14	2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter.

drivers/iio/imu/bmi160/bmi160_core.c+14−6

 	ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET);
 	if (ret)
-		return ret;
+		goto disable_regulator;
 	usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1);
 	if (use_spi) {
 		ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val);
 		if (ret)
-			return ret;
+			goto disable_regulator;
 	}
 	ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val);
 	if (ret) {
 		dev_err(dev, "Error reading chip id\n");
-		return ret;
+		goto disable_regulator;
 	}
 	if (val != BMI160_CHIP_ID_VAL) {
 		dev_err(dev, "Wrong chip id, got %x expected %x\n",
 			val, BMI160_CHIP_ID_VAL);
-		return -ENODEV;
+		ret = -ENODEV;
+		goto disable_regulator;
 	}
 	ret = bmi160_set_mode(data, BMI160_ACCEL, true);
 	if (ret)
-		return ret;
+		goto disable_regulator;
 	ret = bmi160_set_mode(data, BMI160_GYRO, true);
 	if (ret)
-		return ret;
+		goto disable_accel;
 	return 0;
+disable_accel:
+	bmi160_set_mode(data, BMI160_ACCEL, false);
+disable_regulator:
+	regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
+	return ret;
 }
 static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig,

drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c+9−6

@@ -18,12 +18,15 @@ static int inv_icm42600_i2c_bus_setup(struct inv_icm42600_state *st) · 17 unmodified lines
18	unsigned int mask, val;	18	unsigned int mask, val;
19	int ret;	19	int ret;
20		20
21	/* setup interface registers */	21	/*
22	ret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG6,	22	* setup interface registers
23	INV_ICM42600_INTF_CONFIG6_MASK,	23	* This register write to REG_INTF_CONFIG6 enables a spike filter that
24	INV_ICM42600_INTF_CONFIG6_I3C_EN);	24	* is impacting the line and can prevent the I2C ACK to be seen by the
25	if (ret)	25	* controller. So we don't test the return value.
26	return ret;	26	*/
		27	regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG6,
		28	INV_ICM42600_INTF_CONFIG6_MASK,
		29	INV_ICM42600_INTF_CONFIG6_I3C_EN);
27		30
28	ret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG4,	31	ret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG4,
29	INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY, 0);	32	INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY, 0);

drivers/iio/magnetometer/ak8975.c+1−0

@@ -416,6 +416,7 @@ static int ak8975_power_on(const struct ak8975_data *data) · 415 unmodified lines
416	if (ret) {	416	if (ret) {
417	dev_warn(&data->client->dev,	417	dev_warn(&data->client->dev,
418	"Failed to enable specified Vid supply\n");	418	"Failed to enable specified Vid supply\n");
		419	regulator_disable(data->vdd);
419	return ret;	420	return ret;
420	}	421	}
421		422

drivers/iio/proximity/sx9324.c+25−7

 #define SX9324_REG_AFE_PH2		0x2a
 #define SX9324_REG_AFE_PH3		0x2b
 #define SX9324_REG_AFE_CTRL8		0x2c
-#define SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM 0x02
+#define SX9324_REG_AFE_CTRL8_RESERVED	0x10
+#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02
 #define SX9324_REG_AFE_CTRL9		0x2d
 #define SX9324_REG_AFE_CTRL9_AGAIN_1	0x08
 #define SX9324_REG_PROX_CTRL0		0x30
 #define SX9324_REG_PROX_CTRL0_GAIN_MASK	GENMASK(5, 3)
-#define SX9324_REG_PROX_CTRL0_GAIN_1		0x80
+#define SX9324_REG_PROX_CTRL0_GAIN_SHIFT	3
+#define SX9324_REG_PROX_CTRL0_GAIN_RSVD		0x0
+#define SX9324_REG_PROX_CTRL0_GAIN_1		0x1
+#define SX9324_REG_PROX_CTRL0_GAIN_8		0x4
 #define SX9324_REG_PROX_CTRL0_RAWFILT_MASK	GENMASK(2, 0)
 #define SX9324_REG_PROX_CTRL0_RAWFILT_1P50	0x01
 #define SX9324_REG_PROX_CTRL1		0x31
 	if (ret)
 		return ret;
-	*val = 1 << FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
+	regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
+	if (regval)
+		regval--;
+	else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||
+		 regval > SX9324_REG_PROX_CTRL0_GAIN_8)
+		return -EINVAL;
+	*val = 1 << regval;
 	return IIO_VAL_INT;
 }
 	unsigned int gain, reg;
 	int ret;
-	gain = ilog2(val);
 	reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
+	gain = ilog2(val) + 1;
+	if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8)
+		return -EINVAL;
 	gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
 	mutex_lock(&data->mutex);
 	{ SX9324_REG_AFE_PH2, 0x1a },
 	{ SX9324_REG_AFE_PH3, 0x16 },
-	{ SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM },
+	{ SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED |
+		SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM },
 	{ SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 },
-	{ SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 |
+	{ SX9324_REG_PROX_CTRL0,
+		SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
 		SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
-	{ SX9324_REG_PROX_CTRL1, SX9324_REG_PROX_CTRL0_GAIN_1 |
+	{ SX9324_REG_PROX_CTRL1,
+		SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
 		SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
 	{ SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K },
 	{ SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |

drivers/iio/proximity/sx_common.c+1−0

@@ -521,6 +521,7 @@ int sx_common_probe(struct i2c_client *client, · 520 unmodified lines
521	return dev_err_probe(dev, ret, "error reading WHOAMI\n");	521	return dev_err_probe(dev, ret, "error reading WHOAMI\n");
522		522
523	ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(dev));	523	ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(dev));
		524	indio_dev->dev.of_node = client->dev.of_node;
524	indio_dev->modes = INDIO_DIRECT_MODE;	525	indio_dev->modes = INDIO_DIRECT_MODE;
525		526
526	indio_dev->channels = data->chip_info->iio_channels;	527	indio_dev->channels = data->chip_info->iio_channels;

drivers/infiniband/hw/irdma/cm.c+10−23

@@ -2308,10 +2308,8 @@ err: · 2307 unmodified lines
2308	return NULL;	2308	return NULL;
2309	}	2309	}
2310		2310
2311	static void irdma_cm_node_free_cb(struct rcu_head *rcu_head)	2311	static void irdma_destroy_connection(struct irdma_cm_node *cm_node)
2312	{	2312	{
2313	struct irdma_cm_node *cm_node =
2314	container_of(rcu_head, struct irdma_cm_node, rcu_head);
2315	struct irdma_cm_core *cm_core = cm_node->cm_core;	2313	struct irdma_cm_core *cm_core = cm_node->cm_core;
2316	struct irdma_qp *iwqp;	2314	struct irdma_qp *iwqp;
2317	struct irdma_cm_info nfo;	2315	struct irdma_cm_info nfo;
@@ -2359,7 +2357,6 @@ static void irdma_cm_node_free_cb(struct rcu_head *rcu_head) · 41 unmodified lines
2359	}	2357	}
2360		2358
2361	cm_core->cm_free_ah(cm_node);	2359	cm_core->cm_free_ah(cm_node);
2362	kfree(cm_node);
2363	}	2360	}
2364		2361
2365	/**	2362	/**
@@ -2387,8 +2384,9 @@ void irdma_rem_ref_cm_node(struct irdma_cm_node *cm_node) · 21 unmodified lines
2387		2384
2388	spin_unlock_irqrestore(&cm_core->ht_lock, flags);	2385	spin_unlock_irqrestore(&cm_core->ht_lock, flags);
2389		2386
2390	/* wait for all list walkers to exit their grace period */	2387	irdma_destroy_connection(cm_node);
2391	call_rcu(&cm_node->rcu_head, irdma_cm_node_free_cb);	2388
		2389	kfree_rcu(cm_node, rcu_head);
2392	}	2390	}
2393		2391
2394	/**	2392	/**
@@ -3246,15 +3244,10 @@ int irdma_setup_cm_core(struct irdma_device *iwdev, u8 rdma_ver) · 851 unmodified lines
3246	*/	3244	*/
3247	void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core)	3245	void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core)
3248	{	3246	{
3249	unsigned long flags;
3250
3251	if (!cm_core)	3247	if (!cm_core)
3252	return;	3248	return;
3253		3249
3254	spin_lock_irqsave(&cm_core->ht_lock, flags);	3250	del_timer_sync(&cm_core->tcp_timer);
3255	if (timer_pending(&cm_core->tcp_timer))
3256	del_timer_sync(&cm_core->tcp_timer);
3257	spin_unlock_irqrestore(&cm_core->ht_lock, flags);
3258		3251
3259	destroy_workqueue(cm_core->event_wq);	3252	destroy_workqueue(cm_core->event_wq);
3260	cm_core->dev->ws_reset(&cm_core->iwdev->vsi);	3253	cm_core->dev->ws_reset(&cm_core->iwdev->vsi);
@@ -3467,12 +3460,6 @@ static void irdma_cm_disconn_true(struct irdma_qp *iwqp) · 206 unmodified lines
3467	}	3460	}
3468		3461
3469	cm_id = iwqp->cm_id;	3462	cm_id = iwqp->cm_id;
3470	/* make sure we havent already closed this connection */
3471	if (!cm_id) {
3472	spin_unlock_irqrestore(&iwqp->lock, flags);
3473	return;
3474	}
3475
3476	original_hw_tcp_state = iwqp->hw_tcp_state;	3463	original_hw_tcp_state = iwqp->hw_tcp_state;
3477	original_ibqp_state = iwqp->ibqp_state;	3464	original_ibqp_state = iwqp->ibqp_state;
3478	last_ae = iwqp->last_aeq;	3465	last_ae = iwqp->last_aeq;
@@ -3494,11 +3481,11 @@ static void irdma_cm_disconn_true(struct irdma_qp *iwqp) · 15 unmodified lines
3494	disconn_status = -ECONNRESET;	3481	disconn_status = -ECONNRESET;
3495	}	3482	}
3496		3483
3497	if ((original_hw_tcp_state == IRDMA_TCP_STATE_CLOSED \|\|	3484	if (original_hw_tcp_state == IRDMA_TCP_STATE_CLOSED \|\|
3498	original_hw_tcp_state == IRDMA_TCP_STATE_TIME_WAIT \|\|	3485	original_hw_tcp_state == IRDMA_TCP_STATE_TIME_WAIT \|\|
3499	last_ae == IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE \|\|	3486	last_ae == IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE \|\|
3500	last_ae == IRDMA_AE_BAD_CLOSE \|\|	3487	last_ae == IRDMA_AE_BAD_CLOSE \|\|
3501	last_ae == IRDMA_AE_LLP_CONNECTION_RESET \|\| iwdev->rf->reset)) {	3488	last_ae == IRDMA_AE_LLP_CONNECTION_RESET \|\| iwdev->rf->reset \|\| !cm_id) {
3502	issue_close = 1;	3489	issue_close = 1;
3503	iwqp->cm_id = NULL;	3490	iwqp->cm_id = NULL;
3504	qp->term_flags = 0;	3491	qp->term_flags = 0;

drivers/infiniband/hw/irdma/utils.c+9−12

 	u32 local_ipaddr[4] = {};
 	bool ipv4 = true;
-	real_dev = rdma_vlan_dev_real_dev(netdev);
-	if (!real_dev)
-		real_dev = netdev;
-	ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
-	if (!ibdev)
-		return NOTIFY_DONE;
-	iwdev = to_iwdev(ibdev);
 	switch (event) {
 	case NETEVENT_NEIGH_UPDATE:
+		real_dev = rdma_vlan_dev_real_dev(netdev);
+		if (!real_dev)
+			real_dev = netdev;
+		ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
+		if (!ibdev)
+			return NOTIFY_DONE;
+		iwdev = to_iwdev(ibdev);
 		p = (__be32 *)neigh->primary_key;
 		if (neigh->tbl->family == AF_INET6) {
 			ipv4 = false;
 			irdma_manage_arp_cache(iwdev->rf, neigh->ha,
 					       local_ipaddr, ipv4,
 					       IRDMA_ARP_DELETE);
+		ib_device_put(ibdev);
 		break;
 	default:
 		break;
 	}
-	ib_device_put(ibdev);
 	return NOTIFY_DONE;
 }

drivers/infiniband/hw/irdma/verbs.c+2−2

 	if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) {
 		if (dont_wait) {
-			if (iwqp->cm_id && iwqp->hw_tcp_state) {
+			if (iwqp->hw_tcp_state) {
 				spin_lock_irqsave(&iwqp->lock, flags);
 				iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED;
 				iwqp->last_aeq = IRDMA_AE_RESET_SENT;
 				spin_unlock_irqrestore(&iwqp->lock, flags);
-				irdma_cm_disconn(iwqp);
 			}
+			irdma_cm_disconn(iwqp);
 		} else {
 			int close_timer_started;

drivers/infiniband/sw/rxe/rxe_mcast.c+35−46

 }
 /**
- * rxe_mcast_delete - delete multicast address from rxe device
+ * rxe_mcast_del - delete multicast address from rxe device
  * @rxe: rxe device object
  * @mgid: multicast address as a gid
  *
  * Returns 0 on success else an error
  */
-static int rxe_mcast_delete(struct rxe_dev *rxe, union ib_gid *mgid)
+static int rxe_mcast_del(struct rxe_dev *rxe, union ib_gid *mgid)
 {
 	unsigned char ll_addr[ETH_ALEN];
 struct rxe_mcg *rxe_lookup_mcg(struct rxe_dev *rxe, union ib_gid *mgid)
 {
 	struct rxe_mcg *mcg;
-	unsigned long flags;
-	spin_lock_irqsave(&rxe->mcg_lock, flags);
+	spin_lock_bh(&rxe->mcg_lock);
 	mcg = __rxe_lookup_mcg(rxe, mgid);
-	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
+	spin_unlock_bh(&rxe->mcg_lock);
 	return mcg;
 }
  * @mcg: new mcg object
  *
  * Context: caller should hold rxe->mcg lock
- * Returns: 0 on success else an error
  */
-static int __rxe_init_mcg(struct rxe_dev *rxe, union ib_gid *mgid,
+static void __rxe_init_mcg(struct rxe_dev *rxe, union ib_gid *mgid,
-			  struct rxe_mcg *mcg)
+			   struct rxe_mcg *mcg)
 {
-	int err;
-	err = rxe_mcast_add(rxe, mgid);
-	if (unlikely(err))
-		return err;
 	kref_init(&mcg->ref_cnt);
 	memcpy(&mcg->mgid, mgid, sizeof(mcg->mgid));
 	INIT_LIST_HEAD(&mcg->qp_list);
 	 */
 	kref_get(&mcg->ref_cnt);
 	__rxe_insert_mcg(mcg);
-	return 0;
 }
 /**
 static struct rxe_mcg *rxe_get_mcg(struct rxe_dev *rxe, union ib_gid *mgid)
 {
 	struct rxe_mcg *mcg, *tmp;
-	unsigned long flags;
 	int err;
 	if (rxe->attr.max_mcast_grp == 0)
 	if (mcg)
 		return mcg;
+	/* check to see if we have reached limit */
+	if (atomic_inc_return(&rxe->mcg_num) > rxe->attr.max_mcast_grp) {
+		err = -ENOMEM;
+		goto err_dec;
+	}
 	/* speculative alloc of new mcg */
 	mcg = kzalloc(sizeof(*mcg), GFP_KERNEL);
 	if (!mcg)
 		return ERR_PTR(-ENOMEM);
-	spin_lock_irqsave(&rxe->mcg_lock, flags);
+	spin_lock_bh(&rxe->mcg_lock);
 	/* re-check to see if someone else just added it */
 	tmp = __rxe_lookup_mcg(rxe, mgid);
 	if (tmp) {
+		spin_unlock_bh(&rxe->mcg_lock);
+		atomic_dec(&rxe->mcg_num);
 		kfree(mcg);
-		mcg = tmp;
+		return tmp;
-		goto out;
 	}
-	if (atomic_inc_return(&rxe->mcg_num) > rxe->attr.max_mcast_grp) {
+	__rxe_init_mcg(rxe, mgid, mcg);
-		err = -ENOMEM;
+	spin_unlock_bh(&rxe->mcg_lock);
-		goto err_dec;
-	}
-	err = __rxe_init_mcg(rxe, mgid, mcg);
+	/* add mcast address outside of lock */
-	if (err)
+	err = rxe_mcast_add(rxe, mgid);
-		goto err_dec;
+	if (!err)
-out:
+		return mcg;
-	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
-	return mcg;
+	kfree(mcg);
 err_dec:
 	atomic_dec(&rxe->mcg_num);
-	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
-	kfree(mcg);
 	return ERR_PTR(err);
 }
 	__rxe_remove_mcg(mcg);
 	kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
-	rxe_mcast_delete(mcg->rxe, &mcg->mgid);
 	atomic_dec(&rxe->mcg_num);
 }
  */
 static void rxe_destroy_mcg(struct rxe_mcg *mcg)
 {
-	unsigned long flags;
+	/* delete mcast address outside of lock */
+	rxe_mcast_del(mcg->rxe, &mcg->mgid);
-	spin_lock_irqsave(&mcg->rxe->mcg_lock, flags);
+	spin_lock_bh(&mcg->rxe->mcg_lock);
 	__rxe_destroy_mcg(mcg);
-	spin_unlock_irqrestore(&mcg->rxe->mcg_lock, flags);
+	spin_unlock_bh(&mcg->rxe->mcg_lock);
 }
 /**
 {
 	struct rxe_dev *rxe = mcg->rxe;
 	struct rxe_mca *mca, *tmp;
-	unsigned long flags;
 	int err;
 	/* check to see if the qp is already a member of the group */
-	spin_lock_irqsave(&rxe->mcg_lock, flags);
+	spin_lock_bh(&rxe->mcg_lock);
 	list_for_each_entry(mca, &mcg->qp_list, qp_list) {
 		if (mca->qp == qp) {
-			spin_unlock_irqrestore(&rxe->mcg_lock, flags);
+			spin_unlock_bh(&rxe->mcg_lock);
 			return 0;
 		}
 	}
-	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
+	spin_unlock_bh(&rxe->mcg_lock);
 	/* speculative alloc new mca without using GFP_ATOMIC */
 	mca = kzalloc(sizeof(*mca), GFP_KERNEL);
 	if (!mca)
 		return -ENOMEM;
-	spin_lock_irqsave(&rxe->mcg_lock, flags);
+	spin_lock_bh(&rxe->mcg_lock);
 	/* re-check to see if someone else just attached qp */
 	list_for_each_entry(tmp, &mcg->qp_list, qp_list) {
 		if (tmp->qp == qp) {
 	if (err)
 		kfree(mca);
 out:
-	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
+	spin_unlock_bh(&rxe->mcg_lock);
 	return err;
 }
 {
 	struct rxe_dev *rxe = mcg->rxe;
 	struct rxe_mca *mca, *tmp;
-	unsigned long flags;
-	spin_lock_irqsave(&rxe->mcg_lock, flags);
+	spin_lock_bh(&rxe->mcg_lock);
 	list_for_each_entry_safe(mca, tmp, &mcg->qp_list, qp_list) {
 		if (mca->qp == qp) {
 			__rxe_cleanup_mca(mca, mcg);
 			if (atomic_read(&mcg->qp_num) <= 0)
 				__rxe_destroy_mcg(mcg);
-			spin_unlock_irqrestore(&rxe->mcg_lock, flags);
+			spin_unlock_bh(&rxe->mcg_lock);
 			return 0;
 		}
 	}
 	/* we didn't find the qp on the list */
-	spin_unlock_irqrestore(&rxe->mcg_lock, flags);
+	spin_unlock_bh(&rxe->mcg_lock);
 	return -EINVAL;
 }

drivers/infiniband/sw/rxe/rxe_resp.c+25−10

@@ -680,6 +680,11 @@ static struct resp_res rxe_prepare_read_res(struct rxe_qp qp, · 679 unmodified lines
680	* It is assumed that the access permissions if originally good	680	* It is assumed that the access permissions if originally good
681	* are OK and the mappings to be unchanged.	681	* are OK and the mappings to be unchanged.
682	*	682	*
		683	* TODO: If someone reregisters an MR to change its size or
		684	* access permissions during the processing of an RDMA read
		685	* we should kill the responder resource and complete the
		686	* operation with an error.
		687	*
683	* Return: mr on success else NULL	688	* Return: mr on success else NULL
684	*/	689	*/
685	static struct rxe_mr rxe_recheck_mr(struct rxe_qp qp, u32 rkey)	690	static struct rxe_mr rxe_recheck_mr(struct rxe_qp qp, u32 rkey)
@@ -690,23 +695,27 @@ static struct rxe_mr rxe_recheck_mr(struct rxe_qp qp, u32 rkey) · 4 unmodified lines
690		695
691	if (rkey_is_mw(rkey)) {	696	if (rkey_is_mw(rkey)) {
692	mw = rxe_pool_get_index(&rxe->mw_pool, rkey >> 8);	697	mw = rxe_pool_get_index(&rxe->mw_pool, rkey >> 8);
693	if (!mw \|\| mw->rkey != rkey)	698	if (!mw)
694	return NULL;	699	return NULL;
695		700
696	if (mw->state != RXE_MW_STATE_VALID) {	701	mr = mw->mr;
		702	if (mw->rkey != rkey \|\| mw->state != RXE_MW_STATE_VALID \|\|
		703	!mr \|\| mr->state != RXE_MR_STATE_VALID) {
697	rxe_put(mw);	704	rxe_put(mw);
698	return NULL;	705	return NULL;
699	}	706	}
700		707
701	mr = mw->mr;	708	rxe_get(mr);
702	rxe_put(mw);	709	rxe_put(mw);
703	} else {	710
704	mr = rxe_pool_get_index(&rxe->mr_pool, rkey >> 8);	711	return mr;
705	if (!mr \|\| mr->rkey != rkey)
706	return NULL;
707	}	712	}
708		713
709	if (mr->state != RXE_MR_STATE_VALID) {	714	mr = rxe_pool_get_index(&rxe->mr_pool, rkey >> 8);
		715	if (!mr)
		716	return NULL;
		717
		718	if (mr->rkey != rkey \|\| mr->state != RXE_MR_STATE_VALID) {
710	rxe_put(mr);	719	rxe_put(mr);
711	return NULL;	720	return NULL;
712	}	721	}
@@ -736,8 +745,14 @@ static enum resp_states read_reply(struct rxe_qp *qp, · 23 unmodified lines
736	}	745	}
737		746
738	if (res->state == rdatm_res_state_new) {	747	if (res->state == rdatm_res_state_new) {
739	mr = qp->resp.mr;	748	if (!res->replay) {
740	qp->resp.mr = NULL;	749	mr = qp->resp.mr;
		750	qp->resp.mr = NULL;
		751	} else {
		752	mr = rxe_recheck_mr(qp, res->read.rkey);
		753	if (!mr)
		754	return RESPST_ERR_RKEY_VIOLATION;
		755	}
741		756
742	if (res->read.resid <= mtu)	757	if (res->read.resid <= mtu)
743	opcode = IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY;	758	opcode = IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY;

drivers/infiniband/sw/siw/siw_cm.c+4−3

 		siw_cep_set_inuse(new_cep);
 		rv = siw_proc_mpareq(new_cep);
-		siw_cep_set_free(new_cep);
 		if (rv != -EAGAIN) {
 			siw_cep_put(cep);
 			new_cep->listen_cep = NULL;
-			if (rv)
+			if (rv) {
+				siw_cep_set_free(new_cep);
 				goto error;
+			}
 		}
+		siw_cep_set_free(new_cep);
 	}
 	return;

drivers/interconnect/core.c+7−1

 {
 	struct device_node *child;
 	int count = 0;
+	const struct of_device_id __maybe_unused ignore_list[] = {
+		{ .compatible = "qcom,sc7180-ipa-virt" },
+		{ .compatible = "qcom,sdx55-ipa-virt" },
+		{}
+	};
 	for_each_available_child_of_node(np, child) {
-		if (of_property_read_bool(child, "#interconnect-cells"))
+		if (of_property_read_bool(child, "#interconnect-cells") &&
+		    likely(!of_match_node(ignore_list, child)))
 			count++;
 		count += of_count_icc_providers(child);
 	}

drivers/interconnect/qcom/sc7180.c+0−21

 DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
 DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
 DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
-DEFINE_QNODE(ipa_core_master, SC7180_MASTER_IPA_CORE, 1, 8, SC7180_SLAVE_IPA_CORE);
 DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
 DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
 DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
 DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
 DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
 DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
-DEFINE_QNODE(ipa_core_slave, SC7180_SLAVE_IPA_CORE, 1, 8);
 DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
 DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
 DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
 DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
-DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
 };
-static struct qcom_icc_bcm *ipa_virt_bcms[] = {
-	&bcm_ip0,
-};
-static struct qcom_icc_node *ipa_virt_nodes[] = {
-	[MASTER_IPA_CORE] = &ipa_core_master,
-	[SLAVE_IPA_CORE] = &ipa_core_slave,
-};
-static struct qcom_icc_desc sc7180_ipa_virt = {
-	.nodes = ipa_virt_nodes,
-	.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
-	.bcms = ipa_virt_bcms,
-	.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
-};
 static struct qcom_icc_bcm *mc_virt_bcms[] = {
 	&bcm_acv,
 	&bcm_mc0,
 	  .data = &sc7180_dc_noc},
 	{ .compatible = "qcom,sc7180-gem-noc",
 	  .data = &sc7180_gem_noc},
-	{ .compatible = "qcom,sc7180-ipa-virt",
-	  .data = &sc7180_ipa_virt},
 	{ .compatible = "qcom,sc7180-mc-virt",
 	  .data = &sc7180_mc_virt},
 	{ .compatible = "qcom,sc7180-mmss-noc",

drivers/interconnect/qcom/sdx55.c+0−21

 #include "icc-rpmh.h"
 #include "sdx55.h"
-DEFINE_QNODE(ipa_core_master, SDX55_MASTER_IPA_CORE, 1, 8, SDX55_SLAVE_IPA_CORE);
 DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0);
 DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
 DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC);
 DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
 DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
 DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC);
-DEFINE_QNODE(ipa_core_slave, SDX55_SLAVE_IPA_CORE, 1, 8);
 DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4);
 DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0);
 DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC);
 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
-DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
 DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg);
 DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
 DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie);
 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
 };
-static struct qcom_icc_bcm *ipa_virt_bcms[] = {
-	&bcm_ip0,
-};
-static struct qcom_icc_node *ipa_virt_nodes[] = {
-	[MASTER_IPA_CORE] = &ipa_core_master,
-	[SLAVE_IPA_CORE] = &ipa_core_slave,
-};
-static const struct qcom_icc_desc sdx55_ipa_virt = {
-	.nodes = ipa_virt_nodes,
-	.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
-	.bcms = ipa_virt_bcms,
-	.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
-};
 static const struct of_device_id qnoc_of_match[] = {
 	{ .compatible = "qcom,sdx55-mc-virt",
 	  .data = &sdx55_mc_virt},
 	  .data = &sdx55_mem_noc},
 	{ .compatible = "qcom,sdx55-system-noc",
 	  .data = &sdx55_system_noc},
-	{ .compatible = "qcom,sdx55-ipa-virt",
-	  .data = &sdx55_ipa_virt},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qnoc_of_match);

drivers/iommu/amd/amd_iommu_types.h+4−0

 /* IOMMU IVINFO */
 #define IOMMU_IVINFO_OFFSET     36
 #define IOMMU_IVINFO_EFRSUP     BIT(0)
+#define IOMMU_IVINFO_DMA_REMAP  BIT(1)
 /* IOMMU Feature Reporting Field (for IVHD type 10h */
 #define IOMMU_FEAT_GASUP_SHIFT	6
 /* Interrupt remapping feature used? */
 extern bool amd_iommu_irq_remap;
+/* IVRS indicates that pre-boot remapping was enabled */
+extern bool amdr_ivrs_remap_support;
 /* kmem_cache to get tables with 128 byte alignement */
 extern struct kmem_cache *amd_iommu_irq_cache;

drivers/iommu/amd/init.c+5−3

 #define ACPI_DEVFLAG_LINT1              0x80
 #define ACPI_DEVFLAG_ATSDIS             0x10000000
-#define LOOP_TIMEOUT	100000
+#define LOOP_TIMEOUT	2000000
 /*
  * ACPI table definitions
  *
 bool amd_iommu_v2_present __read_mostly;
 static bool amd_iommu_pc_present __read_mostly;
+bool amdr_ivrs_remap_support __read_mostly;
 bool amd_iommu_force_isolation __read_mostly;
 {
 	if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP)
 		iommu->features = h->efr_reg;
+	if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP)
+		amdr_ivrs_remap_support = true;
 }
 /* Access to l1 and l2 indexed register spaces */
 	for_each_iommu(iommu)
 		iommu_flush_all_caches(iommu);
-	if (!ret)
+	print_iommu_info();
-		print_iommu_info();
 out:
 	return ret;

drivers/iommu/amd/iommu.c+9−7

 	amd_iommu_domain_flush_complete(domain);
 }
-static void __init amd_iommu_init_dma_ops(void)
-{
-	swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
-}
 int __init amd_iommu_init_api(void)
 {
 	int err;
-	amd_iommu_init_dma_ops();
 	err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
 	if (err)
 		return err;
 		return (irq_remapping_enabled == 1);
 	case IOMMU_CAP_NOEXEC:
 		return false;
+	case IOMMU_CAP_PRE_BOOT_PROTECTION:
+		return amdr_ivrs_remap_support;
 	default:
 		break;
 	}
 	return 0;
 }
+static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain)
+{
+	/* IOMMU_PTE_FC is always set */
+	return true;
+}
 const struct iommu_ops amd_iommu_ops = {
 	.capable = amd_iommu_capable,
 	.domain_alloc = amd_iommu_domain_alloc,
 		.flush_iotlb_all = amd_iommu_flush_iotlb_all,
 		.iotlb_sync	= amd_iommu_iotlb_sync,
 		.free		= amd_iommu_domain_free,
+		.enforce_cache_coherency = amd_iommu_enforce_cache_coherency,
 	}
 };

drivers/iommu/amd/iommu_v2.c+11−1

 {
 	struct device_state *dev_state, *next;
 	unsigned long flags;
+	LIST_HEAD(freelist);
 	if (!amd_iommu_v2_supported())
 		return;
 		put_device_state(dev_state);
 		list_del(&dev_state->list);
-		free_device_state(dev_state);
+		list_add_tail(&dev_state->list, &freelist);
 	}
 	spin_unlock_irqrestore(&state_lock, flags);
+	/*
+	 * Since free_device_state waits on the count to be zero,
+	 * we need to free dev_state outside the spinlock.
+	 */
+	list_for_each_entry_safe(dev_state, next, &freelist, list) {
+		list_del(&dev_state->list);
+		free_device_state(dev_state);
+	}
 	destroy_workqueue(iommu_wq);
 }

drivers/iommu/apple-dart.c+5−5

 	.get_resv_regions = apple_dart_get_resv_regions,
 	.put_resv_regions = generic_iommu_put_resv_regions,
 	.pgsize_bitmap = -1UL, /* Restricted during dart probe */
+	.owner = THIS_MODULE,
 	.default_domain_ops = &(const struct iommu_domain_ops) {
 		.attach_dev	= apple_dart_attach_dev,
 		.detach_dev	= apple_dart_detach_dev,
 	dart->dev = dev;
 	spin_lock_init(&dart->lock);
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dart->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(dart->regs))
+		return PTR_ERR(dart->regs);
 	if (resource_size(res) < 0x4000) {
 		dev_err(dev, "MMIO region too small (%pr)\n", res);
 		return -EINVAL;
 	}
-	dart->regs = devm_ioremap_resource(dev, res);
-	if (IS_ERR(dart->regs))
-		return PTR_ERR(dart->regs);
 	dart->irq = platform_get_irq(pdev, 0);
 	if (dart->irq < 0)
 		return -ENODEV;

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c+19−3

 #include <linux/mm.h>
 #include <linux/mmu_context.h>
 #include <linux/mmu_notifier.h>
+#include <linux/sched/mm.h>
 #include <linux/slab.h>
 #include "arm-smmu-v3.h"
 	struct arm_smmu_ctx_desc *cd;
 	struct arm_smmu_ctx_desc *ret = NULL;
+	/* Don't free the mm until we release the ASID */
+	mmgrab(mm);
 	asid = arm64_mm_context_get(mm);
-	if (!asid)
+	if (!asid) {
-		return ERR_PTR(-ESRCH);
+		err = -ESRCH;
+		goto out_drop_mm;
+	}
 	cd = kzalloc(sizeof(*cd), GFP_KERNEL);
 	if (!cd) {
 	kfree(cd);
 out_put_context:
 	arm64_mm_context_put(mm);
+out_drop_mm:
+	mmdrop(mm);
 	return err < 0 ? ERR_PTR(err) : ret;
 }
 	if (arm_smmu_free_asid(cd)) {
 		/* Unpin ASID */
 		arm64_mm_context_put(cd->mm);
+		mmdrop(cd->mm);
 		kfree(cd);
 	}
 }
 {
 	struct arm_smmu_mmu_notifier *smmu_mn = mn_to_smmu(mn);
 	struct arm_smmu_domain *smmu_domain = smmu_mn->domain;
-	size_t size = end - start + 1;
+	size_t size;
+	/*
+	 * The mm_types defines vm_end as the first byte after the end address,
+	 * different from IOMMU subsystem using the last address of an address
+	 * range. So do a simple translation here by calculating size correctly.
+	 */
+	size = end - start;
 	if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM))
 		arm_smmu_tlb_inv_range_asid(start, size, smmu_mn->cd->asid,

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c+2−0

@@ -3770,6 +3770,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev) · 3769 unmodified lines
3770		3770
3771	/* Base address */	3771	/* Base address */
3772	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	3772	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		3773	if (!res)
		3774	return -EINVAL;
3773	if (resource_size(res) < arm_smmu_resource_size(smmu)) {	3775	if (resource_size(res) < arm_smmu_resource_size(smmu)) {
3774	dev_err(dev, "MMIO region too small (%pr)\n", res);	3776	dev_err(dev, "MMIO region too small (%pr)\n", res);
3775	return -EINVAL;	3777	return -EINVAL;

drivers/iommu/arm/arm-smmu/arm-smmu-impl.c+2−1

@@ -211,7 +211,8 @@ struct arm_smmu_device arm_smmu_impl_init(struct arm_smmu_device smmu) · 210 unmodified lines
211	if (of_property_read_bool(np, "calxeda,smmu-secure-config-access"))	211	if (of_property_read_bool(np, "calxeda,smmu-secure-config-access"))
212	smmu->impl = &calxeda_impl;	212	smmu->impl = &calxeda_impl;
213		213
214	if (of_device_is_compatible(np, "nvidia,tegra194-smmu") \|\|	214	if (of_device_is_compatible(np, "nvidia,tegra234-smmu") \|\|
		215	of_device_is_compatible(np, "nvidia,tegra194-smmu") \|\|
215	of_device_is_compatible(np, "nvidia,tegra186-smmu"))	216	of_device_is_compatible(np, "nvidia,tegra186-smmu"))
216	return nvidia_smmu_impl_init(smmu);	217	return nvidia_smmu_impl_init(smmu);
217		218

drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c+30−0

@@ -258,6 +258,34 @@ static void nvidia_smmu_probe_finalize(struct arm_smmu_device *smmu, struct devi · 257 unmodified lines
258	dev_name(dev), err);	258	dev_name(dev), err);
259	}	259	}
260		260
		261	static int nvidia_smmu_init_context(struct arm_smmu_domain *smmu_domain,
		262	struct io_pgtable_cfg *pgtbl_cfg,
		263	struct device *dev)
		264	{
		265	struct arm_smmu_device *smmu = smmu_domain->smmu;
		266	const struct device_node *np = smmu->dev->of_node;
		267
		268	/*
		269	* Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
		270	* entries to not be invalidated correctly. The problem is that the walk
		271	* cache index generated for IOVA is not same across translation and
		272	* invalidation requests. This is leading to page faults when PMD entry
		273	* is released during unmap and populated with new PTE table during
		274	* subsequent map request. Disabling large page mappings avoids the
		275	* release of PMD entry and avoid translations seeing stale PMD entry in
		276	* walk cache.
		277	* Fix this by limiting the page mappings to PAGE_SIZE on Tegra194 and
		278	* Tegra234.
		279	*/
		280	if (of_device_is_compatible(np, "nvidia,tegra234-smmu") \|\|
		281	of_device_is_compatible(np, "nvidia,tegra194-smmu")) {
		282	smmu->pgsize_bitmap = PAGE_SIZE;
		283	pgtbl_cfg->pgsize_bitmap = smmu->pgsize_bitmap;
		284	}
		285
		286	return 0;
		287	}
		288
261	static const struct arm_smmu_impl nvidia_smmu_impl = {	289	static const struct arm_smmu_impl nvidia_smmu_impl = {
262	.read_reg = nvidia_smmu_read_reg,	290	.read_reg = nvidia_smmu_read_reg,
263	.write_reg = nvidia_smmu_write_reg,	291	.write_reg = nvidia_smmu_write_reg,
@@ -268,10 +296,12 @@ static const struct arm_smmu_impl nvidia_smmu_impl = { · 4 unmodified lines
268	.global_fault = nvidia_smmu_global_fault,	296	.global_fault = nvidia_smmu_global_fault,
269	.context_fault = nvidia_smmu_context_fault,	297	.context_fault = nvidia_smmu_context_fault,
270	.probe_finalize = nvidia_smmu_probe_finalize,	298	.probe_finalize = nvidia_smmu_probe_finalize,
		299	.init_context = nvidia_smmu_init_context,
271	};	300	};
272		301
273	static const struct arm_smmu_impl nvidia_smmu_single_impl = {	302	static const struct arm_smmu_impl nvidia_smmu_single_impl = {
274	.probe_finalize = nvidia_smmu_probe_finalize,	303	.probe_finalize = nvidia_smmu_probe_finalize,
		304	.init_context = nvidia_smmu_init_context,
275	};	305	};
276		306
277	struct arm_smmu_device nvidia_smmu_impl_init(struct arm_smmu_device smmu)	307	struct arm_smmu_device nvidia_smmu_impl_init(struct arm_smmu_device smmu)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c+1−0

@@ -408,6 +408,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { · 407 unmodified lines
408	{ .compatible = "qcom,sc7180-smmu-500" },	408	{ .compatible = "qcom,sc7180-smmu-500" },
409	{ .compatible = "qcom,sc7280-smmu-500" },	409	{ .compatible = "qcom,sc7280-smmu-500" },
410	{ .compatible = "qcom,sc8180x-smmu-500" },	410	{ .compatible = "qcom,sc8180x-smmu-500" },
		411	{ .compatible = "qcom,sc8280xp-smmu-500" },
411	{ .compatible = "qcom,sdm630-smmu-v2" },	412	{ .compatible = "qcom,sdm630-smmu-v2" },
412	{ .compatible = "qcom,sdm845-smmu-500" },	413	{ .compatible = "qcom,sdm845-smmu-500" },
413	{ .compatible = "qcom,sm6125-smmu-500" },	414	{ .compatible = "qcom,sm6125-smmu-500" },

drivers/iommu/arm/arm-smmu/arm-smmu.c+5−3

 	struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);
 	const struct arm_smmu_impl *impl = cfg->smmu->impl;
+	if (using_legacy_binding)
+		return IOMMU_DOMAIN_IDENTITY;
 	if (impl && impl->def_domain_type)
 		return impl->def_domain_type(dev);
 	if (err)
 		return err;
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-	ioaddr = res->start;
-	smmu->base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(smmu->base))
 		return PTR_ERR(smmu->base);
+	ioaddr = res->start;
 	/*
 	 * The resource size should effectively match the value of SMMU_TOP;
 	 * stash that temporarily until we know PAGESIZE to validate it with.

drivers/iommu/dma-iommu.c+21−4

 #include <linux/iommu.h>
 #include <linux/iova.h>
 #include <linux/irq.h>
+#include <linux/list_sort.h>
 #include <linux/mm.h>
 #include <linux/mutex.h>
 #include <linux/pci.h>
 	return 0;
 }
+static int iommu_dma_ranges_sort(void *priv, const struct list_head *a,
+		const struct list_head *b)
+{
+	struct resource_entry *res_a = list_entry(a, typeof(*res_a), node);
+	struct resource_entry *res_b = list_entry(b, typeof(*res_b), node);
+	return res_a->res->start > res_b->res->start;
+}
 static int iova_reserve_pci_windows(struct pci_dev *dev,
 		struct iova_domain *iovad)
 {
 	}
 	/* Get reserved DMA windows from host bridge */
+	list_sort(NULL, &bridge->dma_ranges, iommu_dma_ranges_sort);
 	resource_list_for_each_entry(window, &bridge->dma_ranges) {
 		end = window->res->start - window->offset;
 resv_iova:
 			hi = iova_pfn(iovad, end);
 			reserve_iova(iovad, lo, hi);
 		} else if (end < start) {
-			/* dma_ranges list should be sorted */
+			/* DMA ranges should be non-overlapping */
 			dev_err(&dev->dev,
 				"Failed to reserve IOVA [%pa-%pa]\n",
 				&start, &end);
 	unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
 	struct page **pages;
 	dma_addr_t iova;
+	ssize_t ret;
 	if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
 	    iommu_deferred_attach(dev, domain))
 			arch_dma_prep_coherent(sg_page(sg), sg->length);
 	}
-	if (iommu_map_sg_atomic(domain, iova, sgt->sgl, sgt->orig_nents, ioprot)
+	ret = iommu_map_sg_atomic(domain, iova, sgt->sgl, sgt->orig_nents, ioprot);
-			< size)
+	if (ret < 0 || ret < size)
 		goto out_free_sg;
 	sgt->sgl->dma_address = iova;
 		void *padding_start;
 		size_t padding_size, aligned_size;
+		if (!is_swiotlb_active(dev)) {
+			dev_warn_once(dev, "DMA bounce buffers are inactive, unable to map unaligned transaction.\n");
+			return DMA_MAPPING_ERROR;
+		}
 		aligned_size = iova_align(iovad, size);
 		phys = swiotlb_tbl_map_single(dev, phys, size, aligned_size,
 					      iova_mask(iovad), dir, attrs);
 	 * implementation - it knows better than we do.
 	 */
 	ret = iommu_map_sg_atomic(domain, iova, sg, nents, prot);
-	if (ret < iova_len)
+	if (ret < 0 || ret < iova_len)
 		goto out_free_iova;
 	return __finalise_sg(dev, sg, nents, iova);

drivers/iommu/fsl_pamu.c+3−0

@@ -11,6 +11,9 @@ · 10 unmodified lines
11	#include <linux/fsl/guts.h>	11	#include <linux/fsl/guts.h>
12	#include <linux/interrupt.h>	12	#include <linux/interrupt.h>
13	#include <linux/genalloc.h>	13	#include <linux/genalloc.h>
		14	#include <linux/of_address.h>
		15	#include <linux/of_irq.h>
		16	#include <linux/platform_device.h>
14		17
15	#include <asm/mpc85xx.h>	18	#include <asm/mpc85xx.h>
16		19

drivers/iommu/fsl_pamu_domain.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9		9
10	#include "fsl_pamu_domain.h"	10	#include "fsl_pamu_domain.h"
11		11
		12	#include <linux/platform_device.h>
12	#include <sysdev/fsl_pci.h>	13	#include <sysdev/fsl_pci.h>
13		14
14	/*	15	/*

drivers/iommu/intel/iommu.c+140−103

@@ -533,33 +533,6 @@ static void domain_update_iommu_coherency(struct dmar_domain *domain) · 532 unmodified lines
533	rcu_read_unlock();	533	rcu_read_unlock();
534	}	534	}
535		535
536	static bool domain_update_iommu_snooping(struct intel_iommu *skip)
537	{
538	struct dmar_drhd_unit *drhd;
539	struct intel_iommu *iommu;
540	bool ret = true;
541
542	rcu_read_lock();
543	for_each_active_iommu(iommu, drhd) {
544	if (iommu != skip) {
545	/*
546	* If the hardware is operating in the scalable mode,
547	* the snooping control is always supported since we
548	* always set PASID-table-entry.PGSNP bit if the domain
549	* is managed outside (UNMANAGED).
550	*/
551	if (!sm_supported(iommu) &&
552	!ecap_sc_support(iommu->ecap)) {
553	ret = false;
554	break;
555	}
556	}
557	}
558	rcu_read_unlock();
559
560	return ret;
561	}
562
563	static int domain_update_iommu_superpage(struct dmar_domain *domain,	536	static int domain_update_iommu_superpage(struct dmar_domain *domain,
564	struct intel_iommu *skip)	537	struct intel_iommu *skip)
565	{	538	{
@@ -641,7 +614,6 @@ static unsigned long domain_super_pgsize_bitmap(struct dmar_domain *domain) · 75 unmodified lines
641	static void domain_update_iommu_cap(struct dmar_domain *domain)	614	static void domain_update_iommu_cap(struct dmar_domain *domain)
642	{	615	{
643	domain_update_iommu_coherency(domain);	616	domain_update_iommu_coherency(domain);
644	domain->iommu_snooping = domain_update_iommu_snooping(NULL);
645	domain->iommu_superpage = domain_update_iommu_superpage(domain, NULL);	617	domain->iommu_superpage = domain_update_iommu_superpage(domain, NULL);
646		618
647	/*	619	/*
@@ -1588,7 +1560,8 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, · 940 unmodified lines
1588	unsigned long pfn, unsigned int pages,	1560	unsigned long pfn, unsigned int pages,
1589	int ih, int map)	1561	int ih, int map)
1590	{	1562	{
1591	unsigned int mask = ilog2(__roundup_pow_of_two(pages));	1563	unsigned int aligned_pages = __roundup_pow_of_two(pages);
		1564	unsigned int mask = ilog2(aligned_pages);
1592	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;	1565	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1593	u16 did = domain->iommu_did[iommu->seq_id];	1566	u16 did = domain->iommu_did[iommu->seq_id];
1594		1567
@@ -1600,10 +1573,30 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, · 5 unmodified lines
1600	if (domain_use_first_level(domain)) {	1573	if (domain_use_first_level(domain)) {
1601	qi_flush_piotlb(iommu, did, PASID_RID2PASID, addr, pages, ih);	1574	qi_flush_piotlb(iommu, did, PASID_RID2PASID, addr, pages, ih);
1602	} else {	1575	} else {
		1576	unsigned long bitmask = aligned_pages - 1;
		1577
		1578	/*
		1579	* PSI masks the low order bits of the base address. If the
		1580	* address isn't aligned to the mask, then compute a mask value
		1581	* needed to ensure the target range is flushed.
		1582	*/
		1583	if (unlikely(bitmask & pfn)) {
		1584	unsigned long end_pfn = pfn + pages - 1, shared_bits;
		1585
		1586	/*
		1587	* Since end_pfn <= pfn + bitmask, the only way bits
		1588	* higher than bitmask can differ in pfn and end_pfn is
		1589	* by carrying. This means after masking out bitmask,
		1590	* high bits starting with the first set bit in
		1591	* shared_bits are all equal in both pfn and end_pfn.
		1592	*/
		1593	shared_bits = ~(pfn ^ end_pfn) & ~bitmask;
		1594	mask = shared_bits ? __ffs(shared_bits) : BITS_PER_LONG;
		1595	}
		1596
1603	/*	1597	/*
1604	* Fallback to domain selective flush if no PSI support or	1598	* Fallback to domain selective flush if no PSI support or
1605	* the size is too big. PSI requires page size to be 2 ^ x,	1599	* the size is too big.
1606	* and the base address is naturally aligned to the size.
1607	*/	1600	*/
1608	if (!cap_pgsel_inv(iommu->cap) \|\|	1601	if (!cap_pgsel_inv(iommu->cap) \|\|
1609	mask > cap_max_amask_val(iommu->cap))	1602	mask > cap_max_amask_val(iommu->cap))
@@ -2439,7 +2432,7 @@ static int domain_setup_first_level(struct intel_iommu *iommu, · 829 unmodified lines
2439	if (level == 5)	2432	if (level == 5)
2440	flags \|= PASID_FLAG_FL5LP;	2433	flags \|= PASID_FLAG_FL5LP;
2441		2434
2442	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)	2435	if (domain->force_snooping)
2443	flags \|= PASID_FLAG_PAGE_SNOOP;	2436	flags \|= PASID_FLAG_PAGE_SNOOP;
2444		2437
2445	return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,	2438	return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,
@@ -2453,64 +2446,6 @@ static bool dev_is_real_dma_subdevice(struct device *dev) · 7 unmodified lines
2453	pci_real_dma_dev(to_pci_dev(dev)) != to_pci_dev(dev);	2446	pci_real_dma_dev(to_pci_dev(dev)) != to_pci_dev(dev);
2454	}	2447	}
2455		2448
2456	static struct dmar_domain dmar_insert_one_dev_info(struct intel_iommu iommu,
2457	int bus, int devfn,
2458	struct device *dev,
2459	struct dmar_domain *domain)
2460	{
2461	struct device_domain_info *info = dev_iommu_priv_get(dev);
2462	unsigned long flags;
2463	int ret;
2464
2465	spin_lock_irqsave(&device_domain_lock, flags);
2466	info->domain = domain;
2467	spin_lock(&iommu->lock);
2468	ret = domain_attach_iommu(domain, iommu);
2469	spin_unlock(&iommu->lock);
2470	if (ret) {
2471	spin_unlock_irqrestore(&device_domain_lock, flags);
2472	return NULL;
2473	}
2474	list_add(&info->link, &domain->devices);
2475	spin_unlock_irqrestore(&device_domain_lock, flags);
2476
2477	/* PASID table is mandatory for a PCI device in scalable mode. */
2478	if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) {
2479	ret = intel_pasid_alloc_table(dev);
2480	if (ret) {
2481	dev_err(dev, "PASID table allocation failed\n");
2482	dmar_remove_one_dev_info(dev);
2483	return NULL;
2484	}
2485
2486	/* Setup the PASID entry for requests without PASID: */
2487	spin_lock_irqsave(&iommu->lock, flags);
2488	if (hw_pass_through && domain_type_is_si(domain))
2489	ret = intel_pasid_setup_pass_through(iommu, domain,
2490	dev, PASID_RID2PASID);
2491	else if (domain_use_first_level(domain))
2492	ret = domain_setup_first_level(iommu, domain, dev,
2493	PASID_RID2PASID);
2494	else
2495	ret = intel_pasid_setup_second_level(iommu, domain,
2496	dev, PASID_RID2PASID);
2497	spin_unlock_irqrestore(&iommu->lock, flags);
2498	if (ret) {
2499	dev_err(dev, "Setup RID2PASID failed\n");
2500	dmar_remove_one_dev_info(dev);
2501	return NULL;
2502	}
2503	}
2504
2505	if (dev && domain_context_mapping(domain, dev)) {
2506	dev_err(dev, "Domain context map failed\n");
2507	dmar_remove_one_dev_info(dev);
2508	return NULL;
2509	}
2510
2511	return domain;
2512	}
2513
2514	static int iommu_domain_identity_map(struct dmar_domain *domain,	2449	static int iommu_domain_identity_map(struct dmar_domain *domain,
2515	unsigned long first_vpfn,	2450	unsigned long first_vpfn,
2516	unsigned long last_vpfn)	2451	unsigned long last_vpfn)
@@ -2586,17 +2521,62 @@ static int __init si_domain_init(int hw) · 69 unmodified lines
2586		2521
2587	static int domain_add_dev_info(struct dmar_domain domain, struct device dev)	2522	static int domain_add_dev_info(struct dmar_domain domain, struct device dev)
2588	{	2523	{
2589	struct dmar_domain *ndomain;	2524	struct device_domain_info *info = dev_iommu_priv_get(dev);
2590	struct intel_iommu *iommu;	2525	struct intel_iommu *iommu;
		2526	unsigned long flags;
2591	u8 bus, devfn;	2527	u8 bus, devfn;
		2528	int ret;
2592		2529
2593	iommu = device_to_iommu(dev, &bus, &devfn);	2530	iommu = device_to_iommu(dev, &bus, &devfn);
2594	if (!iommu)	2531	if (!iommu)
2595	return -ENODEV;	2532	return -ENODEV;
2596		2533
2597	ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);	2534	spin_lock_irqsave(&device_domain_lock, flags);
2598	if (ndomain != domain)	2535	info->domain = domain;
2599	return -EBUSY;	2536	spin_lock(&iommu->lock);
		2537	ret = domain_attach_iommu(domain, iommu);
		2538	spin_unlock(&iommu->lock);
		2539	if (ret) {
		2540	spin_unlock_irqrestore(&device_domain_lock, flags);
		2541	return ret;
		2542	}
		2543	list_add(&info->link, &domain->devices);
		2544	spin_unlock_irqrestore(&device_domain_lock, flags);
		2545
		2546	/* PASID table is mandatory for a PCI device in scalable mode. */
		2547	if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) {
		2548	ret = intel_pasid_alloc_table(dev);
		2549	if (ret) {
		2550	dev_err(dev, "PASID table allocation failed\n");
		2551	dmar_remove_one_dev_info(dev);
		2552	return ret;
		2553	}
		2554
		2555	/* Setup the PASID entry for requests without PASID: */
		2556	spin_lock_irqsave(&iommu->lock, flags);
		2557	if (hw_pass_through && domain_type_is_si(domain))
		2558	ret = intel_pasid_setup_pass_through(iommu, domain,
		2559	dev, PASID_RID2PASID);
		2560	else if (domain_use_first_level(domain))
		2561	ret = domain_setup_first_level(iommu, domain, dev,
		2562	PASID_RID2PASID);
		2563	else
		2564	ret = intel_pasid_setup_second_level(iommu, domain,
		2565	dev, PASID_RID2PASID);
		2566	spin_unlock_irqrestore(&iommu->lock, flags);
		2567	if (ret) {
		2568	dev_err(dev, "Setup RID2PASID failed\n");
		2569	dmar_remove_one_dev_info(dev);
		2570	return ret;
		2571	}
		2572	}
		2573
		2574	ret = domain_context_mapping(domain, dev);
		2575	if (ret) {
		2576	dev_err(dev, "Domain context map failed\n");
		2577	dmar_remove_one_dev_info(dev);
		2578	return ret;
		2579	}
2600		2580
2601	return 0;	2581	return 0;
2602	}	2582	}
@@ -3586,12 +3566,7 @@ static int intel_iommu_add(struct dmar_drhd_unit *dmaru) · 983 unmodified lines
3586	iommu->name);	3566	iommu->name);
3587	return -ENXIO;	3567	return -ENXIO;
3588	}	3568	}
3589	if (!ecap_sc_support(iommu->ecap) &&	3569
3590	domain_update_iommu_snooping(iommu)) {
3591	pr_warn("%s: Doesn't support snooping.\n",
3592	iommu->name);
3593	return -ENXIO;
3594	}
3595	sp = domain_update_iommu_superpage(NULL, iommu) - 1;	3570	sp = domain_update_iommu_superpage(NULL, iommu) - 1;
3596	if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {	3571	if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
3597	pr_warn("%s: Doesn't support large page.\n",	3572	pr_warn("%s: Doesn't support large page.\n",
@@ -4283,7 +4258,6 @@ static int md_domain_init(struct dmar_domain *domain, int guest_width) · 685 unmodified lines
4283	domain->agaw = width_to_agaw(adjust_width);	4258	domain->agaw = width_to_agaw(adjust_width);
4284		4259
4285	domain->iommu_coherency = false;	4260	domain->iommu_coherency = false;
4286	domain->iommu_snooping = false;
4287	domain->iommu_superpage = 0;	4261	domain->iommu_superpage = 0;
4288	domain->max_addr = 0;	4262	domain->max_addr = 0;
4289		4263
@@ -4348,6 +4322,9 @@ static int prepare_domain_attach_device(struct iommu_domain *domain, · 58 unmodified lines
4348	if (!iommu)	4322	if (!iommu)
4349	return -ENODEV;	4323	return -ENODEV;
4350		4324
		4325	if (dmar_domain->force_snooping && !ecap_sc_support(iommu->ecap))
		4326	return -EOPNOTSUPP;
		4327
4351	/* check if this iommu agaw is sufficient for max mapped address */	4328	/* check if this iommu agaw is sufficient for max mapped address */
4352	addr_width = agaw_to_width(iommu->agaw);	4329	addr_width = agaw_to_width(iommu->agaw);
4353	if (addr_width > cap_mgaw(iommu->cap))	4330	if (addr_width > cap_mgaw(iommu->cap))
@@ -4422,7 +4399,7 @@ static int intel_iommu_map(struct iommu_domain *domain, · 68 unmodified lines
4422	prot \|= DMA_PTE_READ;	4399	prot \|= DMA_PTE_READ;
4423	if (iommu_prot & IOMMU_WRITE)	4400	if (iommu_prot & IOMMU_WRITE)
4424	prot \|= DMA_PTE_WRITE;	4401	prot \|= DMA_PTE_WRITE;
4425	if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)	4402	if (dmar_domain->set_pte_snp)
4426	prot \|= DMA_PTE_SNP;	4403	prot \|= DMA_PTE_SNP;
4427		4404
4428	max_addr = iova + size;	4405	max_addr = iova + size;
@@ -4545,12 +4522,71 @@ static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, · 116 unmodified lines
4545	return phys;	4522	return phys;
4546	}	4523	}
4547		4524
		4525	static bool domain_support_force_snooping(struct dmar_domain *domain)
		4526	{
		4527	struct device_domain_info *info;
		4528	bool support = true;
		4529
		4530	assert_spin_locked(&device_domain_lock);
		4531	list_for_each_entry(info, &domain->devices, link) {
		4532	if (!ecap_sc_support(info->iommu->ecap)) {
		4533	support = false;
		4534	break;
		4535	}
		4536	}
		4537
		4538	return support;
		4539	}
		4540
		4541	static void domain_set_force_snooping(struct dmar_domain *domain)
		4542	{
		4543	struct device_domain_info *info;
		4544
		4545	assert_spin_locked(&device_domain_lock);
		4546
		4547	/*
		4548	* Second level page table supports per-PTE snoop control. The
		4549	* iommu_map() interface will handle this by setting SNP bit.
		4550	*/
		4551	if (!domain_use_first_level(domain)) {
		4552	domain->set_pte_snp = true;
		4553	return;
		4554	}
		4555
		4556	list_for_each_entry(info, &domain->devices, link)
		4557	intel_pasid_setup_page_snoop_control(info->iommu, info->dev,
		4558	PASID_RID2PASID);
		4559	}
		4560
		4561	static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain)
		4562	{
		4563	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
		4564	unsigned long flags;
		4565
		4566	if (dmar_domain->force_snooping)
		4567	return true;
		4568
		4569	spin_lock_irqsave(&device_domain_lock, flags);
		4570	if (!domain_support_force_snooping(dmar_domain)) {
		4571	spin_unlock_irqrestore(&device_domain_lock, flags);
		4572	return false;
		4573	}
		4574
		4575	domain_set_force_snooping(dmar_domain);
		4576	dmar_domain->force_snooping = true;
		4577	spin_unlock_irqrestore(&device_domain_lock, flags);
		4578
		4579	return true;
		4580	}
		4581
4548	static bool intel_iommu_capable(enum iommu_cap cap)	4582	static bool intel_iommu_capable(enum iommu_cap cap)
4549	{	4583	{
4550	if (cap == IOMMU_CAP_CACHE_COHERENCY)	4584	if (cap == IOMMU_CAP_CACHE_COHERENCY)
4551	return domain_update_iommu_snooping(NULL);	4585	return true;
4552	if (cap == IOMMU_CAP_INTR_REMAP)	4586	if (cap == IOMMU_CAP_INTR_REMAP)
4553	return irq_remapping_enabled == 1;	4587	return irq_remapping_enabled == 1;
		4588	if (cap == IOMMU_CAP_PRE_BOOT_PROTECTION)
		4589	return dmar_platform_optin();
4554		4590
4555	return false;	4591	return false;
4556	}	4592	}
@@ -4898,6 +4934,7 @@ const struct iommu_ops intel_iommu_ops = { · 341 unmodified lines
4898	.iotlb_sync = intel_iommu_tlb_sync,	4934	.iotlb_sync = intel_iommu_tlb_sync,
4899	.iova_to_phys = intel_iommu_iova_to_phys,	4935	.iova_to_phys = intel_iommu_iova_to_phys,
4900	.free = intel_iommu_domain_free,	4936	.free = intel_iommu_domain_free,
		4937	.enforce_cache_coherency = intel_iommu_enforce_cache_coherency,
4901	}	4938	}
4902	};	4939	};
4903		4940

drivers/iommu/intel/pasid.c+42−3

@@ -710,9 +710,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, · 709 unmodified lines
710	pasid_set_fault_enable(pte);	710	pasid_set_fault_enable(pte);
711	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));	711	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
712		712
713	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
714	pasid_set_pgsnp(pte);
715
716	/*	713	/*
717	* Since it is a second level only translation setup, we should	714	* Since it is a second level only translation setup, we should
718	* set SRE bit as well (addresses are expected to be GPAs).	715	* set SRE bit as well (addresses are expected to be GPAs).
@@ -762,3 +759,45 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu, · 43 unmodified lines
762		759
763	return 0;	760	return 0;
764	}	761	}
		762
		763	/*
		764	* Set the page snoop control for a pasid entry which has been set up.
		765	*/
		766	void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu,
		767	struct device *dev, u32 pasid)
		768	{
		769	struct pasid_entry *pte;
		770	u16 did;
		771
		772	spin_lock(&iommu->lock);
		773	pte = intel_pasid_get_entry(dev, pasid);
		774	if (WARN_ON(!pte \|\| !pasid_pte_is_present(pte))) {
		775	spin_unlock(&iommu->lock);
		776	return;
		777	}
		778
		779	pasid_set_pgsnp(pte);
		780	did = pasid_get_domain_id(pte);
		781	spin_unlock(&iommu->lock);
		782
		783	if (!ecap_coherent(iommu->ecap))
		784	clflush_cache_range(pte, sizeof(*pte));
		785
		786	/*
		787	* VT-d spec 3.4 table23 states guides for cache invalidation:
		788	*
		789	* - PASID-selective-within-Domain PASID-cache invalidation
		790	* - PASID-selective PASID-based IOTLB invalidation
		791	* - If (pasid is RID_PASID)
		792	* - Global Device-TLB invalidation to affected functions
		793	* Else
		794	* - PASID-based Device-TLB invalidation (with S=1 and
		795	* Addr[63:12]=0x7FFFFFFF_FFFFF) to affected functions
		796	*/
		797	pasid_cache_invalidation_with_pasid(iommu, did, pasid);
		798	qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
		799
		800	/* Device IOTLB doesn't need to be flushed in caching mode. */
		801	if (!cap_caching_mode(iommu->cap))
		802	devtlb_invalidation_with_pasid(iommu, dev, pasid);
		803	}

drivers/iommu/intel/pasid.h+2−0

@@ -123,4 +123,6 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, · 122 unmodified lines
123	bool fault_ignore);	123	bool fault_ignore);
124	int vcmd_alloc_pasid(struct intel_iommu iommu, u32 pasid);	124	int vcmd_alloc_pasid(struct intel_iommu iommu, u32 pasid);
125	void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid);	125	void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid);
		126	void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu,
		127	struct device *dev, u32 pasid);
126	#endif /* __INTEL_PASID_H */	128	#endif /* __INTEL_PASID_H */

drivers/iommu/intel/svm.c+4−0

 			goto bad_req;
 		}
+		/* Drop Stop Marker message. No need for a response. */
+		if (unlikely(req->lpig && !req->rd_req && !req->wr_req))
+			goto prq_advance;
 		if (!svm || svm->pasid != req->pasid) {
 			/*
 			 * It can't go away, because the driver is not permitted

drivers/iommu/iommu.c+260−103

@@ -18,7 +18,6 @@ · 17 unmodified lines
18	#include <linux/errno.h>	18	#include <linux/errno.h>
19	#include <linux/iommu.h>	19	#include <linux/iommu.h>
20	#include <linux/idr.h>	20	#include <linux/idr.h>
21	#include <linux/notifier.h>
22	#include <linux/err.h>	21	#include <linux/err.h>
23	#include <linux/pci.h>	22	#include <linux/pci.h>
24	#include <linux/bitops.h>	23	#include <linux/bitops.h>
@@ -40,14 +39,16 @@ struct iommu_group { · 15 unmodified lines
40	struct kobject *devices_kobj;	39	struct kobject *devices_kobj;
41	struct list_head devices;	40	struct list_head devices;
42	struct mutex mutex;	41	struct mutex mutex;
43	struct blocking_notifier_head notifier;
44	void *iommu_data;	42	void *iommu_data;
45	void (iommu_data_release)(void iommu_data);	43	void (iommu_data_release)(void iommu_data);
46	char *name;	44	char *name;
47	int id;	45	int id;
48	struct iommu_domain *default_domain;	46	struct iommu_domain *default_domain;
		47	struct iommu_domain *blocking_domain;
49	struct iommu_domain *domain;	48	struct iommu_domain *domain;
50	struct list_head entry;	49	struct list_head entry;
		50	unsigned int owner_cnt;
		51	void *owner;
51	};	52	};
52		53
53	struct group_device {	54	struct group_device {
@@ -82,8 +83,8 @@ static int __iommu_attach_device(struct iommu_domain *domain, · 28 unmodified lines
82	struct device *dev);	83	struct device *dev);
83	static int __iommu_attach_group(struct iommu_domain *domain,	84	static int __iommu_attach_group(struct iommu_domain *domain,
84	struct iommu_group *group);	85	struct iommu_group *group);
85	static void __iommu_detach_group(struct iommu_domain *domain,	86	static int __iommu_group_set_domain(struct iommu_group *group,
86	struct iommu_group *group);	87	struct iommu_domain *new_domain);
87	static int iommu_create_device_direct_mappings(struct iommu_group *group,	88	static int iommu_create_device_direct_mappings(struct iommu_group *group,
88	struct device *dev);	89	struct device *dev);
89	static struct iommu_group iommu_group_get_for_dev(struct device dev);	90	static struct iommu_group iommu_group_get_for_dev(struct device dev);
@@ -294,7 +295,11 @@ int iommu_probe_device(struct device *dev) · 204 unmodified lines
294	mutex_lock(&group->mutex);	295	mutex_lock(&group->mutex);
295	iommu_alloc_default_domain(group, dev);	296	iommu_alloc_default_domain(group, dev);
296		297
297	if (group->default_domain) {	298	/*
		299	* If device joined an existing group which has been claimed, don't
		300	* attach the default domain.
		301	*/
		302	if (group->default_domain && !group->owner) {
298	ret = __iommu_attach_device(group->default_domain, dev);	303	ret = __iommu_attach_device(group->default_domain, dev);
299	if (ret) {	304	if (ret) {
300	mutex_unlock(&group->mutex);	305	mutex_unlock(&group->mutex);
@@ -506,6 +511,13 @@ int iommu_get_group_resv_regions(struct iommu_group *group, · 205 unmodified lines
506	list_for_each_entry(device, &group->devices, list) {	511	list_for_each_entry(device, &group->devices, list) {
507	struct list_head dev_resv_regions;	512	struct list_head dev_resv_regions;
508		513
		514	/*
		515	* Non-API groups still expose reserved_regions in sysfs,
		516	* so filter out calls that get here that way.
		517	*/
		518	if (!device->dev->iommu)
		519	break;
		520
509	INIT_LIST_HEAD(&dev_resv_regions);	521	INIT_LIST_HEAD(&dev_resv_regions);
510	iommu_get_resv_regions(device->dev, &dev_resv_regions);	522	iommu_get_resv_regions(device->dev, &dev_resv_regions);
511	ret = iommu_insert_device_resv_regions(&dev_resv_regions, head);	523	ret = iommu_insert_device_resv_regions(&dev_resv_regions, head);
@@ -592,6 +604,8 @@ static void iommu_group_release(struct kobject *kobj) · 80 unmodified lines
592		604
593	if (group->default_domain)	605	if (group->default_domain)
594	iommu_domain_free(group->default_domain);	606	iommu_domain_free(group->default_domain);
		607	if (group->blocking_domain)
		608	iommu_domain_free(group->blocking_domain);
595		609
596	kfree(group->name);	610	kfree(group->name);
597	kfree(group);	611	kfree(group);
@@ -626,7 +640,6 @@ struct iommu_group *iommu_group_alloc(void) · 28 unmodified lines
626	mutex_init(&group->mutex);	640	mutex_init(&group->mutex);
627	INIT_LIST_HEAD(&group->devices);	641	INIT_LIST_HEAD(&group->devices);
628	INIT_LIST_HEAD(&group->entry);	642	INIT_LIST_HEAD(&group->entry);
629	BLOCKING_INIT_NOTIFIER_HEAD(&group->notifier);
630		643
631	ret = ida_simple_get(&iommu_group_ida, 0, 0, GFP_KERNEL);	644	ret = ida_simple_get(&iommu_group_ida, 0, 0, GFP_KERNEL);
632	if (ret < 0) {	645	if (ret < 0) {
@@ -899,10 +912,6 @@ rename: · 266 unmodified lines
899	if (ret)	912	if (ret)
900	goto err_put_group;	913	goto err_put_group;
901		914
902	/* Notify any listeners about change to group. */
903	blocking_notifier_call_chain(&group->notifier,
904	IOMMU_GROUP_NOTIFY_ADD_DEVICE, dev);
905
906	trace_add_device_to_group(group->id, dev);	915	trace_add_device_to_group(group->id, dev);
907		916
908	dev_info(dev, "Adding to iommu group %d\n", group->id);	917	dev_info(dev, "Adding to iommu group %d\n", group->id);
@@ -944,10 +953,6 @@ void iommu_group_remove_device(struct device *dev) · 35 unmodified lines
944		953
945	dev_info(dev, "Removing from iommu group %d\n", group->id);	954	dev_info(dev, "Removing from iommu group %d\n", group->id);
946		955
947	/* Pre-notify listeners that a device is being removed. */
948	blocking_notifier_call_chain(&group->notifier,
949	IOMMU_GROUP_NOTIFY_DEL_DEVICE, dev);
950
951	mutex_lock(&group->mutex);	956	mutex_lock(&group->mutex);
952	list_for_each_entry(tmp_device, &group->devices, list) {	957	list_for_each_entry(tmp_device, &group->devices, list) {
953	if (tmp_device->dev == dev) {	958	if (tmp_device->dev == dev) {
@@ -1069,36 +1074,6 @@ void iommu_group_put(struct iommu_group *group) · 115 unmodified lines
1069	}	1074	}
1070	EXPORT_SYMBOL_GPL(iommu_group_put);	1075	EXPORT_SYMBOL_GPL(iommu_group_put);
1071		1076
1072	/**
1073	* iommu_group_register_notifier - Register a notifier for group changes
1074	* @group: the group to watch
1075	* @nb: notifier block to signal
1076	*
1077	* This function allows iommu group users to track changes in a group.
1078	* See include/linux/iommu.h for actions sent via this notifier. Caller
1079	* should hold a reference to the group throughout notifier registration.
1080	*/
1081	int iommu_group_register_notifier(struct iommu_group *group,
1082	struct notifier_block *nb)
1083	{
1084	return blocking_notifier_chain_register(&group->notifier, nb);
1085	}
1086	EXPORT_SYMBOL_GPL(iommu_group_register_notifier);
1087
1088	/**
1089	* iommu_group_unregister_notifier - Unregister a notifier
1090	* @group: the group to watch
1091	* @nb: notifier block to signal
1092	*
1093	* Unregister a previously registered group notifier block.
1094	*/
1095	int iommu_group_unregister_notifier(struct iommu_group *group,
1096	struct notifier_block *nb)
1097	{
1098	return blocking_notifier_chain_unregister(&group->notifier, nb);
1099	}
1100	EXPORT_SYMBOL_GPL(iommu_group_unregister_notifier);
1101
1102	/**	1077	/**
1103	* iommu_register_device_fault_handler() - Register a device fault handler	1078	* iommu_register_device_fault_handler() - Register a device fault handler
1104	* @dev: the device	1079	* @dev: the device
@@ -1644,14 +1619,8 @@ static int remove_iommu_group(struct device dev, void data) · 539 unmodified lines
1644	static int iommu_bus_notifier(struct notifier_block *nb,	1619	static int iommu_bus_notifier(struct notifier_block *nb,
1645	unsigned long action, void *data)	1620	unsigned long action, void *data)
1646	{	1621	{
1647	unsigned long group_action = 0;
1648	struct device *dev = data;	1622	struct device *dev = data;
1649	struct iommu_group *group;
1650		1623
1651	/*
1652	* ADD/DEL call into iommu driver ops if provided, which may
1653	* result in ADD/DEL notifiers to group->notifier
1654	*/
1655	if (action == BUS_NOTIFY_ADD_DEVICE) {	1624	if (action == BUS_NOTIFY_ADD_DEVICE) {
1656	int ret;	1625	int ret;
1657		1626
@@ -1662,34 +1631,6 @@ static int iommu_bus_notifier(struct notifier_block *nb, · 4 unmodified lines
1662	return NOTIFY_OK;	1631	return NOTIFY_OK;
1663	}	1632	}
1664		1633
1665	/*
1666	* Remaining BUS_NOTIFYs get filtered and republished to the
1667	* group, if anyone is listening
1668	*/
1669	group = iommu_group_get(dev);
1670	if (!group)
1671	return 0;
1672
1673	switch (action) {
1674	case BUS_NOTIFY_BIND_DRIVER:
1675	group_action = IOMMU_GROUP_NOTIFY_BIND_DRIVER;
1676	break;
1677	case BUS_NOTIFY_BOUND_DRIVER:
1678	group_action = IOMMU_GROUP_NOTIFY_BOUND_DRIVER;
1679	break;
1680	case BUS_NOTIFY_UNBIND_DRIVER:
1681	group_action = IOMMU_GROUP_NOTIFY_UNBIND_DRIVER;
1682	break;
1683	case BUS_NOTIFY_UNBOUND_DRIVER:
1684	group_action = IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER;
1685	break;
1686	}
1687
1688	if (group_action)
1689	blocking_notifier_call_chain(&group->notifier,
1690	group_action, dev);
1691
1692	iommu_group_put(group);
1693	return 0;	1634	return 0;
1694	}	1635	}
1695		1636
@@ -1906,6 +1847,29 @@ bool iommu_present(struct bus_type *bus) · 210 unmodified lines
1906	}	1847	}
1907	EXPORT_SYMBOL_GPL(iommu_present);	1848	EXPORT_SYMBOL_GPL(iommu_present);
1908		1849
		1850	/**
		1851	* device_iommu_capable() - check for a general IOMMU capability
		1852	* @dev: device to which the capability would be relevant, if available
		1853	* @cap: IOMMU capability
		1854	*
		1855	* Return: true if an IOMMU is present and supports the given capability
		1856	* for the given device, otherwise false.
		1857	*/
		1858	bool device_iommu_capable(struct device *dev, enum iommu_cap cap)
		1859	{
		1860	const struct iommu_ops *ops;
		1861
		1862	if (!dev->iommu \|\| !dev->iommu->iommu_dev)
		1863	return false;
		1864
		1865	ops = dev_iommu_ops(dev);
		1866	if (!ops->capable)
		1867	return false;
		1868
		1869	return ops->capable(cap);
		1870	}
		1871	EXPORT_SYMBOL_GPL(device_iommu_capable);
		1872
1909	bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)	1873	bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)
1910	{	1874	{
1911	if (!bus->iommu_ops \|\| !bus->iommu_ops->capable)	1875	if (!bus->iommu_ops \|\| !bus->iommu_ops->capable)
@@ -1976,6 +1940,24 @@ void iommu_domain_free(struct iommu_domain *domain) · 64 unmodified lines
1976	}	1940	}
1977	EXPORT_SYMBOL_GPL(iommu_domain_free);	1941	EXPORT_SYMBOL_GPL(iommu_domain_free);
1978		1942
		1943	/*
		1944	* Put the group's domain back to the appropriate core-owned domain - either the
		1945	* standard kernel-mode DMA configuration or an all-DMA-blocked domain.
		1946	*/
		1947	static void __iommu_group_set_core_domain(struct iommu_group *group)
		1948	{
		1949	struct iommu_domain *new_domain;
		1950	int ret;
		1951
		1952	if (group->owner)
		1953	new_domain = group->blocking_domain;
		1954	else
		1955	new_domain = group->default_domain;
		1956
		1957	ret = __iommu_group_set_domain(group, new_domain);
		1958	WARN(ret, "iommu driver failed to attach the default/blocking domain");
		1959	}
		1960
1979	static int __iommu_attach_device(struct iommu_domain *domain,	1961	static int __iommu_attach_device(struct iommu_domain *domain,
1980	struct device *dev)	1962	struct device *dev)
1981	{	1963	{
@@ -2032,9 +2014,6 @@ static void __iommu_detach_device(struct iommu_domain *domain, · 50 unmodified lines
2032	if (iommu_is_attach_deferred(dev))	2014	if (iommu_is_attach_deferred(dev))
2033	return;	2015	return;
2034		2016
2035	if (unlikely(domain->ops->detach_dev == NULL))
2036	return;
2037
2038	domain->ops->detach_dev(domain, dev);	2017	domain->ops->detach_dev(domain, dev);
2039	trace_detach_device_from_domain(dev);	2018	trace_detach_device_from_domain(dev);
2040	}	2019	}
@@ -2048,12 +2027,10 @@ void iommu_detach_device(struct iommu_domain domain, struct device dev) · 7 unmodified lines
2048	return;	2027	return;
2049		2028
2050	mutex_lock(&group->mutex);	2029	mutex_lock(&group->mutex);
2051	if (iommu_group_device_count(group) != 1) {	2030	if (WARN_ON(domain != group->domain) \|\|
2052	WARN_ON(1);	2031	WARN_ON(iommu_group_device_count(group) != 1))
2053	goto out_unlock;	2032	goto out_unlock;
2054	}	2033	__iommu_group_set_core_domain(group);
2055
2056	__iommu_detach_group(domain, group);
2057		2034
2058	out_unlock:	2035	out_unlock:
2059	mutex_unlock(&group->mutex);	2036	mutex_unlock(&group->mutex);
@@ -2109,7 +2086,8 @@ static int __iommu_attach_group(struct iommu_domain *domain, · 49 unmodified lines
2109	{	2086	{
2110	int ret;	2087	int ret;
2111		2088
2112	if (group->default_domain && group->domain != group->default_domain)	2089	if (group->domain && group->domain != group->default_domain &&
		2090	group->domain != group->blocking_domain)
2113	return -EBUSY;	2091	return -EBUSY;
2114		2092
2115	ret = __iommu_group_for_each_dev(group, domain,	2093	ret = __iommu_group_for_each_dev(group, domain,
@@ -2141,34 +2119,49 @@ static int iommu_group_do_detach_device(struct device dev, void data) · 25 unmodified lines
2141	return 0;	2119	return 0;
2142	}	2120	}
2143		2121
2144	static void __iommu_detach_group(struct iommu_domain *domain,	2122	static int __iommu_group_set_domain(struct iommu_group *group,
2145	struct iommu_group *group)	2123	struct iommu_domain *new_domain)
2146	{	2124	{
2147	int ret;	2125	int ret;
2148		2126
2149	if (!group->default_domain) {	2127	if (group->domain == new_domain)
2150	__iommu_group_for_each_dev(group, domain,	2128	return 0;
		2129
		2130	/*
		2131	* New drivers should support default domains and so the detach_dev() op
		2132	* will never be called. Otherwise the NULL domain represents some
		2133	* platform specific behavior.
		2134	*/
		2135	if (!new_domain) {
		2136	if (WARN_ON(!group->domain->ops->detach_dev))
		2137	return -EINVAL;
		2138	__iommu_group_for_each_dev(group, group->domain,
2151	iommu_group_do_detach_device);	2139	iommu_group_do_detach_device);
2152	group->domain = NULL;	2140	group->domain = NULL;
2153	return;	2141	return 0;
2154	}	2142	}
2155		2143
2156	if (group->domain == group->default_domain)	2144	/*
2157	return;	2145	* Changing the domain is done by calling attach_dev() on the new
2158		2146	* domain. This switch does not have to be atomic and DMA can be
2159	/* Detach by re-attaching to the default domain */	2147	* discarded during the transition. DMA must only be able to access
2160	ret = __iommu_group_for_each_dev(group, group->default_domain,	2148	* either new_domain or group->domain, never something else.
		2149	*
		2150	* Note that this is called in error unwind paths, attaching to a
		2151	* domain that has already been attached cannot fail.
		2152	*/
		2153	ret = __iommu_group_for_each_dev(group, new_domain,
2161	iommu_group_do_attach_device);	2154	iommu_group_do_attach_device);
2162	if (ret != 0)	2155	if (ret)
2163	WARN_ON(1);	2156	return ret;
2164	else	2157	group->domain = new_domain;
2165	group->domain = group->default_domain;	2158	return 0;
2166	}	2159	}
2167		2160
2168	void iommu_detach_group(struct iommu_domain domain, struct iommu_group group)	2161	void iommu_detach_group(struct iommu_domain domain, struct iommu_group group)
2169	{	2162	{
2170	mutex_lock(&group->mutex);	2163	mutex_lock(&group->mutex);
2171	__iommu_detach_group(domain, group);	2164	__iommu_group_set_core_domain(group);
2172	mutex_unlock(&group->mutex);	2165	mutex_unlock(&group->mutex);
2173	}	2166	}
2174	EXPORT_SYMBOL_GPL(iommu_detach_group);	2167	EXPORT_SYMBOL_GPL(iommu_detach_group);
@@ -3019,7 +3012,7 @@ static ssize_t iommu_group_store_type(struct iommu_group *group, · 844 unmodified lines
3019	if (!capable(CAP_SYS_ADMIN) \|\| !capable(CAP_SYS_RAWIO))	3012	if (!capable(CAP_SYS_ADMIN) \|\| !capable(CAP_SYS_RAWIO))
3020	return -EACCES;	3013	return -EACCES;
3021		3014
3022	if (WARN_ON(!group))	3015	if (WARN_ON(!group) \|\| !group->default_domain)
3023	return -EINVAL;	3016	return -EINVAL;
3024		3017
3025	if (sysfs_streq(buf, "identity"))	3018	if (sysfs_streq(buf, "identity"))
@@ -3095,3 +3088,167 @@ out: · 69 unmodified lines
3095		3088
3096	return ret;	3089	return ret;
3097	}	3090	}
		3091
		3092	/**
		3093	* iommu_device_use_default_domain() - Device driver wants to handle device
		3094	* DMA through the kernel DMA API.
		3095	* @dev: The device.
		3096	*
		3097	* The device driver about to bind @dev wants to do DMA through the kernel
		3098	* DMA API. Return 0 if it is allowed, otherwise an error.
		3099	*/
		3100	int iommu_device_use_default_domain(struct device *dev)
		3101	{
		3102	struct iommu_group *group = iommu_group_get(dev);
		3103	int ret = 0;
		3104
		3105	if (!group)
		3106	return 0;
		3107
		3108	mutex_lock(&group->mutex);
		3109	if (group->owner_cnt) {
		3110	if (group->domain != group->default_domain \|\|
		3111	group->owner) {
		3112	ret = -EBUSY;
		3113	goto unlock_out;
		3114	}
		3115	}
		3116
		3117	group->owner_cnt++;
		3118
		3119	unlock_out:
		3120	mutex_unlock(&group->mutex);
		3121	iommu_group_put(group);
		3122
		3123	return ret;
		3124	}
		3125
		3126	/**
		3127	* iommu_device_unuse_default_domain() - Device driver stops handling device
		3128	* DMA through the kernel DMA API.
		3129	* @dev: The device.
		3130	*
		3131	* The device driver doesn't want to do DMA through kernel DMA API anymore.
		3132	* It must be called after iommu_device_use_default_domain().
		3133	*/
		3134	void iommu_device_unuse_default_domain(struct device *dev)
		3135	{
		3136	struct iommu_group *group = iommu_group_get(dev);
		3137
		3138	if (!group)
		3139	return;
		3140
		3141	mutex_lock(&group->mutex);
		3142	if (!WARN_ON(!group->owner_cnt))
		3143	group->owner_cnt--;
		3144
		3145	mutex_unlock(&group->mutex);
		3146	iommu_group_put(group);
		3147	}
		3148
		3149	static int __iommu_group_alloc_blocking_domain(struct iommu_group *group)
		3150	{
		3151	struct group_device *dev =
		3152	list_first_entry(&group->devices, struct group_device, list);
		3153
		3154	if (group->blocking_domain)
		3155	return 0;
		3156
		3157	group->blocking_domain =
		3158	__iommu_domain_alloc(dev->dev->bus, IOMMU_DOMAIN_BLOCKED);
		3159	if (!group->blocking_domain) {
		3160	/*
		3161	* For drivers that do not yet understand IOMMU_DOMAIN_BLOCKED
		3162	* create an empty domain instead.
		3163	*/
		3164	group->blocking_domain = __iommu_domain_alloc(
		3165	dev->dev->bus, IOMMU_DOMAIN_UNMANAGED);
		3166	if (!group->blocking_domain)
		3167	return -EINVAL;
		3168	}
		3169	return 0;
		3170	}
		3171
		3172	/**
		3173	* iommu_group_claim_dma_owner() - Set DMA ownership of a group
		3174	* @group: The group.
		3175	* @owner: Caller specified pointer. Used for exclusive ownership.
		3176	*
		3177	* This is to support backward compatibility for vfio which manages
		3178	* the dma ownership in iommu_group level. New invocations on this
		3179	* interface should be prohibited.
		3180	*/
		3181	int iommu_group_claim_dma_owner(struct iommu_group group, void owner)
		3182	{
		3183	int ret = 0;
		3184
		3185	mutex_lock(&group->mutex);
		3186	if (group->owner_cnt) {
		3187	ret = -EPERM;
		3188	goto unlock_out;
		3189	} else {
		3190	if (group->domain && group->domain != group->default_domain) {
		3191	ret = -EBUSY;
		3192	goto unlock_out;
		3193	}
		3194
		3195	ret = __iommu_group_alloc_blocking_domain(group);
		3196	if (ret)
		3197	goto unlock_out;
		3198
		3199	ret = __iommu_group_set_domain(group, group->blocking_domain);
		3200	if (ret)
		3201	goto unlock_out;
		3202	group->owner = owner;
		3203	}
		3204
		3205	group->owner_cnt++;
		3206	unlock_out:
		3207	mutex_unlock(&group->mutex);
		3208
		3209	return ret;
		3210	}
		3211	EXPORT_SYMBOL_GPL(iommu_group_claim_dma_owner);
		3212
		3213	/**
		3214	* iommu_group_release_dma_owner() - Release DMA ownership of a group
		3215	* @group: The group.
		3216	*
		3217	* Release the DMA ownership claimed by iommu_group_claim_dma_owner().
		3218	*/
		3219	void iommu_group_release_dma_owner(struct iommu_group *group)
		3220	{
		3221	int ret;
		3222
		3223	mutex_lock(&group->mutex);
		3224	if (WARN_ON(!group->owner_cnt \|\| !group->owner))
		3225	goto unlock_out;
		3226
		3227	group->owner_cnt = 0;
		3228	group->owner = NULL;
		3229	ret = __iommu_group_set_domain(group, group->default_domain);
		3230	WARN(ret, "iommu driver failed to attach the default domain");
		3231
		3232	unlock_out:
		3233	mutex_unlock(&group->mutex);
		3234	}
		3235	EXPORT_SYMBOL_GPL(iommu_group_release_dma_owner);
		3236
		3237	/**
		3238	* iommu_group_dma_owner_claimed() - Query group dma ownership status
		3239	* @group: The group.
		3240	*
		3241	* This provides status query on a given group. It is racy and only for
		3242	* non-binding status reporting.
		3243	*/
		3244	bool iommu_group_dma_owner_claimed(struct iommu_group *group)
		3245	{
		3246	unsigned int user;
		3247
		3248	mutex_lock(&group->mutex);
		3249	user = group->owner_cnt;
		3250	mutex_unlock(&group->mutex);
		3251
		3252	return user;
		3253	}
		3254	EXPORT_SYMBOL_GPL(iommu_group_dma_owner_claimed);

drivers/iommu/msm_iommu.c+15−7

 	       GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
 }
-static void insert_iommu_master(struct device *dev,
+static int insert_iommu_master(struct device *dev,
 				struct msm_iommu_dev **iommu,
 				struct of_phandle_args *spec)
 {
 	if (list_empty(&(*iommu)->ctx_list)) {
 		master = kzalloc(sizeof(*master), GFP_ATOMIC);
+		if (!master) {
+			dev_err(dev, "Failed to allocate iommu_master\n");
+			return -ENOMEM;
+		}
 		master->of_node = dev->of_node;
 		list_add(&master->list, &(*iommu)->ctx_list);
 		dev_iommu_priv_set(dev, master);
 		if (master->mids[sid] == spec->args[0]) {
 			dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n",
 				 sid);
-			return;
+			return 0;
 		}
 	master->mids[master->num_mids++] = spec->args[0];
+	return 0;
 }
 static int qcom_iommu_of_xlate(struct device *dev,
 			       struct of_phandle_args *spec)
 {
-	struct msm_iommu_dev *iommu;
+	struct msm_iommu_dev *iommu = NULL, *iter;
 	unsigned long flags;
 	int ret = 0;
 	spin_lock_irqsave(&msm_iommu_lock, flags);
-	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)
+	list_for_each_entry(iter, &qcom_iommu_devices, dev_node) {
-		if (iommu->dev->of_node == spec->np)
+		if (iter->dev->of_node == spec->np) {
+			iommu = iter;
 			break;
+		}
+	}
-	if (!iommu || iommu->dev->of_node != spec->np) {
+	if (!iommu) {
 		ret = -ENODEV;
 		goto fail;
 	}
-	insert_iommu_master(dev, &iommu, spec);
+	ret = insert_iommu_master(dev, &iommu, spec);
 fail:
 	spin_unlock_irqrestore(&msm_iommu_lock, flags);

drivers/iommu/mtk_iommu.c+709−271

@@ -14,12 +14,14 @@ · 13 unmodified lines
14	#include <linux/io.h>	14	#include <linux/io.h>
15	#include <linux/iommu.h>	15	#include <linux/iommu.h>
16	#include <linux/iopoll.h>	16	#include <linux/iopoll.h>
		17	#include <linux/io-pgtable.h>
17	#include <linux/list.h>	18	#include <linux/list.h>
18	#include <linux/mfd/syscon.h>	19	#include <linux/mfd/syscon.h>
19	#include <linux/module.h>	20	#include <linux/module.h>
20	#include <linux/of_address.h>	21	#include <linux/of_address.h>
21	#include <linux/of_irq.h>	22	#include <linux/of_irq.h>
22	#include <linux/of_platform.h>	23	#include <linux/of_platform.h>
		24	#include <linux/pci.h>
23	#include <linux/platform_device.h>	25	#include <linux/platform_device.h>
24	#include <linux/pm_runtime.h>	26	#include <linux/pm_runtime.h>
25	#include <linux/regmap.h>	27	#include <linux/regmap.h>
@@ -29,7 +31,7 @@ · 3 unmodified lines
29	#include <asm/barrier.h>	31	#include <asm/barrier.h>
30	#include <soc/mediatek/smi.h>	32	#include <soc/mediatek/smi.h>
31		33
32	#include "mtk_iommu.h"	34	#include <dt-bindings/memory/mtk-memory-port.h>
33		35
34	#define REG_MMU_PT_BASE_ADDR 0x000	36	#define REG_MMU_PT_BASE_ADDR 0x000
35	#define MMU_PT_ADDR_MASK GENMASK(31, 7)	37	#define MMU_PT_ADDR_MASK GENMASK(31, 7)
@@ -51,6 +53,8 @@ · 15 unmodified lines
51	#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) \| BIT(19))	53	#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) \| BIT(19))
52		54
53	#define REG_MMU_DCM_DIS 0x050	55	#define REG_MMU_DCM_DIS 0x050
		56	#define F_MMU_DCM BIT(8)
		57
54	#define REG_MMU_WR_LEN_CTRL 0x054	58	#define REG_MMU_WR_LEN_CTRL 0x054
55	#define F_MMU_WR_THROT_DIS_MASK (BIT(5) \| BIT(21))	59	#define F_MMU_WR_THROT_DIS_MASK (BIT(5) \| BIT(21))
56		60
@@ -103,10 +107,15 @@ · 46 unmodified lines
103	#define REG_MMU1_INT_ID 0x154	107	#define REG_MMU1_INT_ID 0x154
104	#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)	108	#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
105	#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)	109	#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
		110	#define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
		111	#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
106	#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)	112	#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
107	#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)	113	#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
108		114
109	#define MTK_PROTECT_PA_ALIGN 256	115	#define MTK_PROTECT_PA_ALIGN 256
		116	#define MTK_IOMMU_BANK_SZ 0x1000
		117
		118	#define PERICFG_IOMMU_1 0x714
110		119
111	#define HAS_4GB_MODE BIT(0)	120	#define HAS_4GB_MODE BIT(0)
112	/* HW will use the EMI clock if there isn't the "bclk". */	121	/* HW will use the EMI clock if there isn't the "bclk". */
@@ -114,25 +123,147 @@ · 1 unmodified line
114	#define HAS_VLD_PA_RNG BIT(2)	123	#define HAS_VLD_PA_RNG BIT(2)
115	#define RESET_AXI BIT(3)	124	#define RESET_AXI BIT(3)
116	#define OUT_ORDER_WR_EN BIT(4)	125	#define OUT_ORDER_WR_EN BIT(4)
117	#define HAS_SUB_COMM BIT(5)	126	#define HAS_SUB_COMM_2BITS BIT(5)
118	#define WR_THROT_EN BIT(6)	127	#define HAS_SUB_COMM_3BITS BIT(6)
119	#define HAS_LEGACY_IVRP_PADDR BIT(7)	128	#define WR_THROT_EN BIT(7)
120	#define IOVA_34_EN BIT(8)	129	#define HAS_LEGACY_IVRP_PADDR BIT(8)
		130	#define IOVA_34_EN BIT(9)
		131	#define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */
		132	#define DCM_DISABLE BIT(11)
		133	#define STD_AXI_MODE BIT(12) /* For non MM iommu */
		134	/* 2 bits: iommu type */
		135	#define MTK_IOMMU_TYPE_MM (0x0 << 13)
		136	#define MTK_IOMMU_TYPE_INFRA (0x1 << 13)
		137	#define MTK_IOMMU_TYPE_MASK (0x3 << 13)
		138	/* PM and clock always on. e.g. infra iommu */
		139	#define PM_CLK_AO BIT(15)
		140	#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
		141
		142	#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
		143	((((pdata)->flags) & (mask)) == (_x))
		144
		145	#define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
		146	#define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
		147	MTK_IOMMU_TYPE_MASK)
		148
		149	#define MTK_INVALID_LARBID MTK_LARB_NR_MAX
		150
		151	#define MTK_LARB_COM_MAX 8
		152	#define MTK_LARB_SUBCOM_MAX 8
		153
		154	#define MTK_IOMMU_GROUP_MAX 8
		155	#define MTK_IOMMU_BANK_MAX 5
		156
		157	enum mtk_iommu_plat {
		158	M4U_MT2712,
		159	M4U_MT6779,
		160	M4U_MT8167,
		161	M4U_MT8173,
		162	M4U_MT8183,
		163	M4U_MT8186,
		164	M4U_MT8192,
		165	M4U_MT8195,
		166	};
		167
		168	struct mtk_iommu_iova_region {
		169	dma_addr_t iova_base;
		170	unsigned long long size;
		171	};
		172
		173	struct mtk_iommu_suspend_reg {
		174	u32 misc_ctrl;
		175	u32 dcm_dis;
		176	u32 ctrl_reg;
		177	u32 vld_pa_rng;
		178	u32 wr_len_ctrl;
		179
		180	u32 int_control[MTK_IOMMU_BANK_MAX];
		181	u32 int_main_control[MTK_IOMMU_BANK_MAX];
		182	u32 ivrp_paddr[MTK_IOMMU_BANK_MAX];
		183	};
		184
		185	struct mtk_iommu_plat_data {
		186	enum mtk_iommu_plat m4u_plat;
		187	u32 flags;
		188	u32 inv_sel_reg;
		189
		190	char *pericfg_comp_str;
		191	struct list_head *hw_list;
		192	unsigned int iova_region_nr;
		193	const struct mtk_iommu_iova_region *iova_region;
		194
		195	u8 banks_num;
		196	bool banks_enable[MTK_IOMMU_BANK_MAX];
		197	unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
		198	unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
		199	};
		200
		201	struct mtk_iommu_bank_data {
		202	void __iomem *base;
		203	int irq;
		204	u8 id;
		205	struct device *parent_dev;
		206	struct mtk_iommu_data *parent_data;
		207	spinlock_t tlb_lock; /* lock for tlb range flush */
		208	struct mtk_iommu_domain m4u_dom; / Each bank has a domain */
		209	};
		210
		211	struct mtk_iommu_data {
		212	struct device *dev;
		213	struct clk *bclk;
		214	phys_addr_t protect_base; /* protect memory base */
		215	struct mtk_iommu_suspend_reg reg;
		216	struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
		217	bool enable_4GB;
121		218
122	#define MTK_IOMMU_HAS_FLAG(pdata, _x) \	219	struct iommu_device iommu;
123	((((pdata)->flags) & (_x)) == (_x))	220	const struct mtk_iommu_plat_data *plat_data;
		221	struct device *smicomm_dev;
		222
		223	struct mtk_iommu_bank_data *bank;
		224
		225	struct dma_iommu_mapping mapping; / For mtk_iommu_v1.c */
		226	struct regmap *pericfg;
		227
		228	struct mutex mutex; /* Protect m4u_group/m4u_dom above */
		229
		230	/*
		231	* In the sharing pgtable case, list data->list to the global list like m4ulist.
		232	* In the non-sharing pgtable case, list data->list to the itself hw_list_head.
		233	*/
		234	struct list_head *hw_list;
		235	struct list_head hw_list_head;
		236	struct list_head list;
		237	struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
		238	};
124		239
125	struct mtk_iommu_domain {	240	struct mtk_iommu_domain {
126	struct io_pgtable_cfg cfg;	241	struct io_pgtable_cfg cfg;
127	struct io_pgtable_ops *iop;	242	struct io_pgtable_ops *iop;
128		243
129	struct mtk_iommu_data *data;	244	struct mtk_iommu_bank_data *bank;
130	struct iommu_domain domain;	245	struct iommu_domain domain;
		246
		247	struct mutex mutex; /* Protect "data" in this structure */
131	};	248	};
132		249
		250	static int mtk_iommu_bind(struct device *dev)
		251	{
		252	struct mtk_iommu_data *data = dev_get_drvdata(dev);
		253
		254	return component_bind_all(dev, &data->larb_imu);
		255	}
		256
		257	static void mtk_iommu_unbind(struct device *dev)
		258	{
		259	struct mtk_iommu_data *data = dev_get_drvdata(dev);
		260
		261	component_unbind_all(dev, &data->larb_imu);
		262	}
		263
133	static const struct iommu_ops mtk_iommu_ops;	264	static const struct iommu_ops mtk_iommu_ops;
134		265
135	static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);	266	static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
136		267
137	#define MTK_IOMMU_TLB_ADDR(iova) ({ \	268	#define MTK_IOMMU_TLB_ADDR(iova) ({ \
138	dma_addr_t _addr = iova; \	269	dma_addr_t _addr = iova; \
@@ -165,42 +296,28 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); · 26 unmodified lines
165		296
166	static LIST_HEAD(m4ulist); /* List all the M4U HWs */	297	static LIST_HEAD(m4ulist); /* List all the M4U HWs */
167		298
168	#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)	299	#define for_each_m4u(data, head) list_for_each_entry(data, head, list)
169
170	struct mtk_iommu_iova_region {
171	dma_addr_t iova_base;
172	unsigned long long size;
173	};
174		300
175	static const struct mtk_iommu_iova_region single_domain[] = {	301	static const struct mtk_iommu_iova_region single_domain[] = {
176	{.iova_base = 0, .size = SZ_4G},	302	{.iova_base = 0, .size = SZ_4G},
177	};	303	};
178		304
179	static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {	305	static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
180	{ .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */	306	{ .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */
181	#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)	307	#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
182	{ .iova_base = SZ_4G, .size = SZ_4G}, /* vdec: 4G ~ 8G */	308	{ .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */
183	{ .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */	309	{ .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */
		310	{ .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */
		311
184	{ .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */	312	{ .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
185	{ .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */	313	{ .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
186	#endif	314	#endif
187	};	315	};
188		316
189	/*	317	/* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
190	* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain	318	static struct mtk_iommu_data mtk_iommu_get_frst_data(struct list_head hwlist)
191	* for the performance.
192	*
193	* Here always return the mtk_iommu_data of the first probed M4U where the
194	* iommu domain information is recorded.
195	*/
196	static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
197	{	319	{
198	struct mtk_iommu_data *data;	320	return list_first_entry(hwlist, struct mtk_iommu_data, list);
199
200	for_each_m4u(data)
201	return data;
202
203	return NULL;
204	}	321	}
205		322
206	static struct mtk_iommu_domain to_mtk_domain(struct iommu_domain dom)	323	static struct mtk_iommu_domain to_mtk_domain(struct iommu_domain dom)
@@ -210,46 +327,72 @@ static struct mtk_iommu_domain to_mtk_domain(struct iommu_domain dom) · 3 unmodified lines
210		327
211	static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)	328	static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
212	{	329	{
		330	/* Tlb flush all always is in bank0. */
		331	struct mtk_iommu_bank_data *bank = &data->bank[0];
		332	void __iomem *base = bank->base;
213	unsigned long flags;	333	unsigned long flags;
214		334
215	spin_lock_irqsave(&data->tlb_lock, flags);	335	spin_lock_irqsave(&bank->tlb_lock, flags);
216	writel_relaxed(F_INVLD_EN1 \| F_INVLD_EN0,	336	writel_relaxed(F_INVLD_EN1 \| F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
217	data->base + data->plat_data->inv_sel_reg);	337	writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
218	writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
219	wmb(); /* Make sure the tlb flush all done */	338	wmb(); /* Make sure the tlb flush all done */
220	spin_unlock_irqrestore(&data->tlb_lock, flags);	339	spin_unlock_irqrestore(&bank->tlb_lock, flags);
221	}	340	}
222		341
223	static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,	342	static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
224	size_t granule,	343	struct mtk_iommu_bank_data *bank)
225	struct mtk_iommu_data *data)
226	{	344	{
		345	struct list_head *head = bank->parent_data->hw_list;
		346	struct mtk_iommu_bank_data *curbank;
		347	struct mtk_iommu_data *data;
		348	bool check_pm_status;
227	unsigned long flags;	349	unsigned long flags;
		350	void __iomem *base;
228	int ret;	351	int ret;
229	u32 tmp;	352	u32 tmp;
230		353
231	for_each_m4u(data) {	354	for_each_m4u(data, head) {
232	if (pm_runtime_get_if_in_use(data->dev) <= 0)	355	/*
233	continue;	356	* To avoid resume the iommu device frequently when the iommu device
		357	* is not active, it doesn't always call pm_runtime_get here, then tlb
		358	* flush depends on the tlb flush all in the runtime resume.
		359	*
		360	* There are 2 special cases:
		361	*
		362	* Case1: The iommu dev doesn't have power domain but has bclk. This case
		363	* should also avoid the tlb flush while the dev is not active to mute
		364	* the tlb timeout log. like mt8173.
		365	*
		366	* Case2: The power/clock of infra iommu is always on, and it doesn't
		367	* have the device link with the master devices. This case should avoid
		368	* the PM status check.
		369	*/
		370	check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
234		371
235	spin_lock_irqsave(&data->tlb_lock, flags);	372	if (check_pm_status) {
		373	if (pm_runtime_get_if_in_use(data->dev) <= 0)
		374	continue;
		375	}
		376
		377	curbank = &data->bank[bank->id];
		378	base = curbank->base;
		379
		380	spin_lock_irqsave(&curbank->tlb_lock, flags);
236	writel_relaxed(F_INVLD_EN1 \| F_INVLD_EN0,	381	writel_relaxed(F_INVLD_EN1 \| F_INVLD_EN0,
237	data->base + data->plat_data->inv_sel_reg);	382	base + data->plat_data->inv_sel_reg);
238		383
239	writel_relaxed(MTK_IOMMU_TLB_ADDR(iova),	384	writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
240	data->base + REG_MMU_INVLD_START_A);
241	writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),	385	writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
242	data->base + REG_MMU_INVLD_END_A);	386	base + REG_MMU_INVLD_END_A);
243	writel_relaxed(F_MMU_INV_RANGE,	387	writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
244	data->base + REG_MMU_INVALIDATE);
245		388
246	/* tlb sync */	389	/* tlb sync */
247	ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,	390	ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
248	tmp, tmp != 0, 10, 1000);	391	tmp, tmp != 0, 10, 1000);
249		392
250	/* Clear the CPE status */	393	/* Clear the CPE status */
251	writel_relaxed(0, data->base + REG_MMU_CPE_DONE);	394	writel_relaxed(0, base + REG_MMU_CPE_DONE);
252	spin_unlock_irqrestore(&data->tlb_lock, flags);	395	spin_unlock_irqrestore(&curbank->tlb_lock, flags);
253		396
254	if (ret) {	397	if (ret) {
255	dev_warn(data->dev,	398	dev_warn(data->dev,
@@ -257,70 +400,103 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, · 1 unmodified line
257	mtk_iommu_tlb_flush_all(data);	400	mtk_iommu_tlb_flush_all(data);
258	}	401	}
259		402
260	pm_runtime_put(data->dev);	403	if (check_pm_status)
		404	pm_runtime_put(data->dev);
261	}	405	}
262	}	406	}
263		407
264	static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)	408	static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
265	{	409	{
266	struct mtk_iommu_data *data = dev_id;	410	struct mtk_iommu_bank_data *bank = dev_id;
267	struct mtk_iommu_domain *dom = data->m4u_dom;	411	struct mtk_iommu_data *data = bank->parent_data;
268	unsigned int fault_larb, fault_port, sub_comm = 0;	412	struct mtk_iommu_domain *dom = bank->m4u_dom;
		413	unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
269	u32 int_state, regval, va34_32, pa34_32;	414	u32 int_state, regval, va34_32, pa34_32;
		415	const struct mtk_iommu_plat_data *plat_data = data->plat_data;
		416	void __iomem *base = bank->base;
270	u64 fault_iova, fault_pa;	417	u64 fault_iova, fault_pa;
271	bool layer, write;	418	bool layer, write;
272		419
273	/* Read error info from registers */	420	/* Read error info from registers */
274	int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);	421	int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
275	if (int_state & F_REG_MMU0_FAULT_MASK) {	422	if (int_state & F_REG_MMU0_FAULT_MASK) {
276	regval = readl_relaxed(data->base + REG_MMU0_INT_ID);	423	regval = readl_relaxed(base + REG_MMU0_INT_ID);
277	fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);	424	fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
278	fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);	425	fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
279	} else {	426	} else {
280	regval = readl_relaxed(data->base + REG_MMU1_INT_ID);	427	regval = readl_relaxed(base + REG_MMU1_INT_ID);
281	fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);	428	fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
282	fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);	429	fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
283	}	430	}
284	layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;	431	layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
285	write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;	432	write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
286	if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {	433	if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
287	va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);	434	va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
288	pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
289	fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;	435	fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
290	fault_iova \|= (u64)va34_32 << 32;	436	fault_iova \|= (u64)va34_32 << 32;
291	fault_pa \|= (u64)pa34_32 << 32;
292	}	437	}
293		438	pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
294	fault_port = F_MMU_INT_ID_PORT_ID(regval);	439	fault_pa \|= (u64)pa34_32 << 32;
295	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {	440
296	fault_larb = F_MMU_INT_ID_COMM_ID(regval);	441	if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
297	sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);	442	fault_port = F_MMU_INT_ID_PORT_ID(regval);
298	} else {	443	if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
299	fault_larb = F_MMU_INT_ID_LARB_ID(regval);	444	fault_larb = F_MMU_INT_ID_COMM_ID(regval);
		445	sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
		446	} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
		447	fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
		448	sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
		449	} else {
		450	fault_larb = F_MMU_INT_ID_LARB_ID(regval);
		451	}
		452	fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
300	}	453	}
301	fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
302		454
303	if (report_iommu_fault(&dom->domain, data->dev, fault_iova,	455	if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
304	write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {	456	write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
305	dev_err_ratelimited(	457	dev_err_ratelimited(
306	data->dev,	458	bank->parent_dev,
307	"fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",	459	"fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
308	int_state, fault_iova, fault_pa, fault_larb, fault_port,	460	int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
309	layer, write ? "write" : "read");	461	layer, write ? "write" : "read");
310	}	462	}
311		463
312	/* Interrupt clear */	464	/* Interrupt clear */
313	regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);	465	regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
314	regval \|= F_INT_CLR_BIT;	466	regval \|= F_INT_CLR_BIT;
315	writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);	467	writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
316		468
317	mtk_iommu_tlb_flush_all(data);	469	mtk_iommu_tlb_flush_all(data);
318		470
319	return IRQ_HANDLED;	471	return IRQ_HANDLED;
320	}	472	}
321		473
322	static int mtk_iommu_get_domain_id(struct device *dev,	474	static unsigned int mtk_iommu_get_bank_id(struct device *dev,
323	const struct mtk_iommu_plat_data *plat_data)	475	const struct mtk_iommu_plat_data *plat_data)
		476	{
		477	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
		478	unsigned int i, portmsk = 0, bankid = 0;
		479
		480	if (plat_data->banks_num == 1)
		481	return bankid;
		482
		483	for (i = 0; i < fwspec->num_ids; i++)
		484	portmsk \|= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
		485
		486	for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
		487	if (!plat_data->banks_enable[i])
		488	continue;
		489
		490	if (portmsk & plat_data->banks_portmsk[i]) {
		491	bankid = i;
		492	break;
		493	}
		494	}
		495	return bankid; /* default is 0 */
		496	}
		497
		498	static int mtk_iommu_get_iova_region_id(struct device *dev,
		499	const struct mtk_iommu_plat_data *plat_data)
324	{	500	{
325	const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;	501	const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
326	const struct bus_dma_region *dma_rgn = dev->dma_range_map;	502	const struct bus_dma_region *dma_rgn = dev->dma_range_map;
@@ -349,46 +525,65 @@ static int mtk_iommu_get_domain_id(struct device *dev, · 22 unmodified lines
349	return -EINVAL;	525	return -EINVAL;
350	}	526	}
351		527
352	static void mtk_iommu_config(struct mtk_iommu_data data, struct device dev,	528	static int mtk_iommu_config(struct mtk_iommu_data data, struct device dev,
353	bool enable, unsigned int domid)	529	bool enable, unsigned int regionid)
354	{	530	{
355	struct mtk_smi_larb_iommu *larb_mmu;	531	struct mtk_smi_larb_iommu *larb_mmu;
356	unsigned int larbid, portid;	532	unsigned int larbid, portid;
357	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);	533	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
358	const struct mtk_iommu_iova_region *region;	534	const struct mtk_iommu_iova_region *region;
359	int i;	535	u32 peri_mmuen, peri_mmuen_msk;
		536	int i, ret = 0;
360		537
361	for (i = 0; i < fwspec->num_ids; ++i) {	538	for (i = 0; i < fwspec->num_ids; ++i) {
362	larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);	539	larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
363	portid = MTK_M4U_TO_PORT(fwspec->ids[i]);	540	portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
364		541
365	larb_mmu = &data->larb_imu[larbid];	542	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
366		543	larb_mmu = &data->larb_imu[larbid];
367	region = data->plat_data->iova_region + domid;	544
368	larb_mmu->bank[portid] = upper_32_bits(region->iova_base);	545	region = data->plat_data->iova_region + regionid;
369		546	larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
370	dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",	547
371	enable ? "enable" : "disable", dev_name(larb_mmu->dev),	548	dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",
372	portid, domid, larb_mmu->bank[portid]);	549	enable ? "enable" : "disable", dev_name(larb_mmu->dev),
373		550	portid, regionid, larb_mmu->bank[portid]);
374	if (enable)	551
375	larb_mmu->mmu \|= MTK_SMI_MMU_EN(portid);	552	if (enable)
376	else	553	larb_mmu->mmu \|= MTK_SMI_MMU_EN(portid);
377	larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);	554	else
		555	larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
		556	} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
		557	peri_mmuen_msk = BIT(portid);
		558	/* PCI dev has only one output id, enable the next writing bit for PCIe */
		559	if (dev_is_pci(dev))
		560	peri_mmuen_msk \|= BIT(portid + 1);
		561
		562	peri_mmuen = enable ? peri_mmuen_msk : 0;
		563	ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
		564	peri_mmuen_msk, peri_mmuen);
		565	if (ret)
		566	dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
		567	enable ? "enable" : "disable",
		568	dev_name(data->dev), peri_mmuen_msk, ret);
		569	}
378	}	570	}
		571	return ret;
379	}	572	}
380		573
381	static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,	574	static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
382	struct mtk_iommu_data *data,	575	struct mtk_iommu_data *data,
383	unsigned int domid)	576	unsigned int region_id)
384	{	577	{
385	const struct mtk_iommu_iova_region *region;	578	const struct mtk_iommu_iova_region *region;
386		579	struct mtk_iommu_domain *m4u_dom;
387	/* Use the exist domain as there is only one pgtable here. */	580
388	if (data->m4u_dom) {	581	/* Always use bank0 in sharing pgtable case */
389	dom->iop = data->m4u_dom->iop;	582	m4u_dom = data->bank[0].m4u_dom;
390	dom->cfg = data->m4u_dom->cfg;	583	if (m4u_dom) {
391	dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;	584	dom->iop = m4u_dom->iop;
		585	dom->cfg = m4u_dom->cfg;
		586	dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;
392	goto update_iova_region;	587	goto update_iova_region;
393	}	588	}
394		589
@@ -417,7 +612,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, · 22 unmodified lines
417		612
418	update_iova_region:	613	update_iova_region:
419	/* Update the iova region for this domain */	614	/* Update the iova region for this domain */
420	region = data->plat_data->iova_region + domid;	615	region = data->plat_data->iova_region + region_id;
421	dom->domain.geometry.aperture_start = region->iova_base;	616	dom->domain.geometry.aperture_start = region->iova_base;
422	dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;	617	dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
423	dom->domain.geometry.force_aperture = true;	618	dom->domain.geometry.force_aperture = true;
@@ -428,12 +623,13 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) · 4 unmodified lines
428	{	623	{
429	struct mtk_iommu_domain *dom;	624	struct mtk_iommu_domain *dom;
430		625
431	if (type != IOMMU_DOMAIN_DMA)	626	if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
432	return NULL;	627	return NULL;
433		628
434	dom = kzalloc(sizeof(*dom), GFP_KERNEL);	629	dom = kzalloc(sizeof(*dom), GFP_KERNEL);
435	if (!dom)	630	if (!dom)
436	return NULL;	631	return NULL;
		632	mutex_init(&dom->mutex);
437		633
438	return &dom->domain;	634	return &dom->domain;
439	}	635	}
@@ -446,40 +642,60 @@ static void mtk_iommu_domain_free(struct iommu_domain *domain) · 6 unmodified lines
446	static int mtk_iommu_attach_device(struct iommu_domain *domain,	642	static int mtk_iommu_attach_device(struct iommu_domain *domain,
447	struct device *dev)	643	struct device *dev)
448	{	644	{
449	struct mtk_iommu_data *data = dev_iommu_priv_get(dev);	645	struct mtk_iommu_data data = dev_iommu_priv_get(dev), frstdata;
450	struct mtk_iommu_domain *dom = to_mtk_domain(domain);	646	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
		647	struct list_head *hw_list = data->hw_list;
451	struct device *m4udev = data->dev;	648	struct device *m4udev = data->dev;
452	int ret, domid;	649	struct mtk_iommu_bank_data *bank;
		650	unsigned int bankid;
		651	int ret, region_id;
453		652
454	domid = mtk_iommu_get_domain_id(dev, data->plat_data);	653	region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
455	if (domid < 0)	654	if (region_id < 0)
456	return domid;	655	return region_id;
457		656
458	if (!dom->data) {	657	bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
459	if (mtk_iommu_domain_finalise(dom, data, domid))	658	mutex_lock(&dom->mutex);
		659	if (!dom->bank) {
		660	/* Data is in the frstdata in sharing pgtable case. */
		661	frstdata = mtk_iommu_get_frst_data(hw_list);
		662
		663	ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
		664	if (ret) {
		665	mutex_unlock(&dom->mutex);
460	return -ENODEV;	666	return -ENODEV;
461	dom->data = data;	667	}
		668	dom->bank = &data->bank[bankid];
462	}	669	}
		670	mutex_unlock(&dom->mutex);
463		671
464	if (!data->m4u_dom) { /* Initialize the M4U HW */	672	mutex_lock(&data->mutex);
		673	bank = &data->bank[bankid];
		674	if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
465	ret = pm_runtime_resume_and_get(m4udev);	675	ret = pm_runtime_resume_and_get(m4udev);
466	if (ret < 0)	676	if (ret < 0) {
467	return ret;	677	dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
		678	goto err_unlock;
		679	}
468		680
469	ret = mtk_iommu_hw_init(data);	681	ret = mtk_iommu_hw_init(data, bankid);
470	if (ret) {	682	if (ret) {
471	pm_runtime_put(m4udev);	683	pm_runtime_put(m4udev);
472	return ret;	684	goto err_unlock;
473	}	685	}
474	data->m4u_dom = dom;	686	bank->m4u_dom = dom;
475	writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,	687	writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
476	data->base + REG_MMU_PT_BASE_ADDR);	688	bank->base + REG_MMU_PT_BASE_ADDR);
477		689
478	pm_runtime_put(m4udev);	690	pm_runtime_put(m4udev);
479	}	691	}
		692	mutex_unlock(&data->mutex);
480		693
481	mtk_iommu_config(data, dev, true, domid);	694	return mtk_iommu_config(data, dev, true, region_id);
482	return 0;	695
		696	err_unlock:
		697	mutex_unlock(&data->mutex);
		698	return ret;
483	}	699	}
484		700
485	static void mtk_iommu_detach_device(struct iommu_domain *domain,	701	static void mtk_iommu_detach_device(struct iommu_domain *domain,
@@ -496,7 +712,7 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, · 10 unmodified lines
496	struct mtk_iommu_domain *dom = to_mtk_domain(domain);	712	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
497		713
498	/* The "4GB mode" M4U physically can not use the lower remap of Dram. */	714	/* The "4GB mode" M4U physically can not use the lower remap of Dram. */
499	if (dom->data->enable_4GB)	715	if (dom->bank->parent_data->enable_4GB)
500	paddr \|= BIT_ULL(32);	716	paddr \|= BIT_ULL(32);
501		717
502	/* Synchronize with the tlb_lock */	718	/* Synchronize with the tlb_lock */
@@ -517,7 +733,7 @@ static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) · 14 unmodified lines
517	{	733	{
518	struct mtk_iommu_domain *dom = to_mtk_domain(domain);	734	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
519		735
520	mtk_iommu_tlb_flush_all(dom->data);	736	mtk_iommu_tlb_flush_all(dom->bank->parent_data);
521	}	737	}
522		738
523	static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,	739	static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
@@ -526,8 +742,7 @@ static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, · 2 unmodified lines
526	struct mtk_iommu_domain *dom = to_mtk_domain(domain);	742	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
527	size_t length = gather->end - gather->start + 1;	743	size_t length = gather->end - gather->start + 1;
528		744
529	mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,	745	mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
530	dom->data);
531	}	746	}
532		747
533	static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,	748	static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
@@ -535,7 +750,7 @@ static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, · 1 unmodified line
535	{	750	{
536	struct mtk_iommu_domain *dom = to_mtk_domain(domain);	751	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
537		752
538	mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data);	753	mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
539	}	754	}
540		755
541	static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,	756	static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
@@ -546,7 +761,7 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, · 4 unmodified lines
546		761
547	pa = dom->iop->iova_to_phys(dom->iop, iova);	762	pa = dom->iop->iova_to_phys(dom->iop, iova);
548	if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&	763	if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
549	dom->data->enable_4GB &&	764	dom->bank->parent_data->enable_4GB &&
550	pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)	765	pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
551	pa &= ~BIT_ULL(32);	766	pa &= ~BIT_ULL(32);
552		767
@@ -566,12 +781,18 @@ static struct iommu_device mtk_iommu_probe_device(struct device dev) · 13 unmodified lines
566		781
567	data = dev_iommu_priv_get(dev);	782	data = dev_iommu_priv_get(dev);
568		783
		784	if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
		785	return &data->iommu;
		786
569	/*	787	/*
570	* Link the consumer device with the smi-larb device(supplier).	788	* Link the consumer device with the smi-larb device(supplier).
571	* The device that connects with each a larb is a independent HW.	789	* The device that connects with each a larb is a independent HW.
572	* All the ports in each a device should be in the same larbs.	790	* All the ports in each a device should be in the same larbs.
573	*/	791	*/
574	larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);	792	larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
		793	if (larbid >= MTK_LARB_NR_MAX)
		794	return ERR_PTR(-EINVAL);
		795
575	for (i = 1; i < fwspec->num_ids; i++) {	796	for (i = 1; i < fwspec->num_ids; i++) {
576	larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);	797	larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
577	if (larbid != larbidx) {	798	if (larbid != larbidx) {
@@ -581,6 +802,9 @@ static struct iommu_device mtk_iommu_probe_device(struct device dev) · 3 unmodified lines
581	}	802	}
582	}	803	}
583	larbdev = data->larb_imu[larbid].dev;	804	larbdev = data->larb_imu[larbid].dev;
		805	if (!larbdev)
		806	return ERR_PTR(-EINVAL);
		807
584	link = device_link_add(dev, larbdev,	808	link = device_link_add(dev, larbdev,
585	DL_FLAG_PM_RUNTIME \| DL_FLAG_STATELESS);	809	DL_FLAG_PM_RUNTIME \| DL_FLAG_STATELESS);
586	if (!link)	810	if (!link)
@@ -599,34 +823,55 @@ static void mtk_iommu_release_device(struct device *dev) · 12 unmodified lines
599	return;	823	return;
600		824
601	data = dev_iommu_priv_get(dev);	825	data = dev_iommu_priv_get(dev);
602	larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);	826	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
603	larbdev = data->larb_imu[larbid].dev;	827	larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
604	device_link_remove(dev, larbdev);	828	larbdev = data->larb_imu[larbid].dev;
		829	device_link_remove(dev, larbdev);
		830	}
605		831
606	iommu_fwspec_free(dev);	832	iommu_fwspec_free(dev);
607	}	833	}
608		834
		835	static int mtk_iommu_get_group_id(struct device dev, const struct mtk_iommu_plat_data plat_data)
		836	{
		837	unsigned int bankid;
		838
		839	/*
		840	* If the bank function is enabled, each bank is a iommu group/domain.
		841	* Otherwise, each iova region is a iommu group/domain.
		842	*/
		843	bankid = mtk_iommu_get_bank_id(dev, plat_data);
		844	if (bankid)
		845	return bankid;
		846
		847	return mtk_iommu_get_iova_region_id(dev, plat_data);
		848	}
		849
609	static struct iommu_group mtk_iommu_device_group(struct device dev)	850	static struct iommu_group mtk_iommu_device_group(struct device dev)
610	{	851	{
611	struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();	852	struct mtk_iommu_data c_data = dev_iommu_priv_get(dev), data;
		853	struct list_head *hw_list = c_data->hw_list;
612	struct iommu_group *group;	854	struct iommu_group *group;
613	int domid;	855	int groupid;
614		856
		857	data = mtk_iommu_get_frst_data(hw_list);
615	if (!data)	858	if (!data)
616	return ERR_PTR(-ENODEV);	859	return ERR_PTR(-ENODEV);
617		860
618	domid = mtk_iommu_get_domain_id(dev, data->plat_data);	861	groupid = mtk_iommu_get_group_id(dev, data->plat_data);
619	if (domid < 0)	862	if (groupid < 0)
620	return ERR_PTR(domid);	863	return ERR_PTR(groupid);
621		864
622	group = data->m4u_group[domid];	865	mutex_lock(&data->mutex);
		866	group = data->m4u_group[groupid];
623	if (!group) {	867	if (!group) {
624	group = iommu_group_alloc();	868	group = iommu_group_alloc();
625	if (!IS_ERR(group))	869	if (!IS_ERR(group))
626	data->m4u_group[domid] = group;	870	data->m4u_group[groupid] = group;
627	} else {	871	} else {
628	iommu_group_ref_get(group);	872	iommu_group_ref_get(group);
629	}	873	}
		874	mutex_unlock(&data->mutex);
630	return group;	875	return group;
631	}	876	}
632		877
@@ -656,14 +901,14 @@ static void mtk_iommu_get_resv_regions(struct device *dev, · 23 unmodified lines
656	struct list_head *head)	901	struct list_head *head)
657	{	902	{
658	struct mtk_iommu_data *data = dev_iommu_priv_get(dev);	903	struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
659	unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i;	904	unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
660	const struct mtk_iommu_iova_region resv, curdom;	905	const struct mtk_iommu_iova_region resv, curdom;
661	struct iommu_resv_region *region;	906	struct iommu_resv_region *region;
662	int prot = IOMMU_WRITE \| IOMMU_READ;	907	int prot = IOMMU_WRITE \| IOMMU_READ;
663		908
664	if ((int)domid < 0)	909	if ((int)regionid < 0)
665	return;	910	return;
666	curdom = data->plat_data->iova_region + domid;	911	curdom = data->plat_data->iova_region + regionid;
667	for (i = 0; i < data->plat_data->iova_region_nr; i++) {	912	for (i = 0; i < data->plat_data->iova_region_nr; i++) {
668	resv = data->plat_data->iova_region + i;	913	resv = data->plat_data->iova_region + i;
669		914
@@ -704,42 +949,24 @@ static const struct iommu_ops mtk_iommu_ops = { · 34 unmodified lines
704	}	949	}
705	};	950	};
706		951
707	static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)	952	static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
708	{	953	{
		954	const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
		955	const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
709	u32 regval;	956	u32 regval;
710		957
		958	/*
		959	* Global control settings are in bank0. May re-init these global registers
		960	* since no sure if there is bank0 consumers.
		961	*/
711	if (data->plat_data->m4u_plat == M4U_MT8173) {	962	if (data->plat_data->m4u_plat == M4U_MT8173) {
712	regval = F_MMU_PREFETCH_RT_REPLACE_MOD \|	963	regval = F_MMU_PREFETCH_RT_REPLACE_MOD \|
713	F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;	964	F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
714	} else {	965	} else {
715	regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);	966	regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
716	regval \|= F_MMU_TF_PROT_TO_PROGRAM_ADDR;	967	regval \|= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
717	}	968	}
718	writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);	969	writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
719
720	regval = F_L2_MULIT_HIT_EN \|
721	F_TABLE_WALK_FAULT_INT_EN \|
722	F_PREETCH_FIFO_OVERFLOW_INT_EN \|
723	F_MISS_FIFO_OVERFLOW_INT_EN \|
724	F_PREFETCH_FIFO_ERR_INT_EN \|
725	F_MISS_FIFO_ERR_INT_EN;
726	writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
727
728	regval = F_INT_TRANSLATION_FAULT \|
729	F_INT_MAIN_MULTI_HIT_FAULT \|
730	F_INT_INVALID_PA_FAULT \|
731	F_INT_ENTRY_REPLACEMENT_FAULT \|
732	F_INT_TLB_MISS_FAULT \|
733	F_INT_MISS_TRANSACTION_FIFO_FAULT \|
734	F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
735	writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
736
737	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
738	regval = (data->protect_base >> 1) \| (data->enable_4GB << 31);
739	else
740	regval = lower_32_bits(data->protect_base) \|
741	upper_32_bits(data->protect_base);
742	writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
743		970
744	if (data->enable_4GB &&	971	if (data->enable_4GB &&
745	MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {	972	MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
@@ -748,31 +975,61 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) · 2 unmodified lines
748	* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].	975	* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
749	*/	976	*/
750	regval = F_MMU_VLD_PA_RNG(7, 4);	977	regval = F_MMU_VLD_PA_RNG(7, 4);
751	writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);	978	writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
752	}	979	}
753	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);	980	if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
		981	writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
		982	else
		983	writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
		984
754	if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {	985	if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
755	/* write command throttling mode */	986	/* write command throttling mode */
756	regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);	987	regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
757	regval &= ~F_MMU_WR_THROT_DIS_MASK;	988	regval &= ~F_MMU_WR_THROT_DIS_MASK;
758	writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);	989	writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
759	}	990	}
760		991
761	if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {	992	if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
762	/* The register is called STANDARD_AXI_MODE in this case */	993	/* The register is called STANDARD_AXI_MODE in this case */
763	regval = 0;	994	regval = 0;
764	} else {	995	} else {
765	regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);	996	regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
766	regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;	997	if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
		998	regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
767	if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))	999	if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
768	regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;	1000	regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
769	}	1001	}
770	writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);	1002	writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
771		1003
772	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,	1004	/* Independent settings for each bank */
773	dev_name(data->dev), (void *)data)) {	1005	regval = F_L2_MULIT_HIT_EN \|
774	writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);	1006	F_TABLE_WALK_FAULT_INT_EN \|
775	dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);	1007	F_PREETCH_FIFO_OVERFLOW_INT_EN \|
		1008	F_MISS_FIFO_OVERFLOW_INT_EN \|
		1009	F_PREFETCH_FIFO_ERR_INT_EN \|
		1010	F_MISS_FIFO_ERR_INT_EN;
		1011	writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
		1012
		1013	regval = F_INT_TRANSLATION_FAULT \|
		1014	F_INT_MAIN_MULTI_HIT_FAULT \|
		1015	F_INT_INVALID_PA_FAULT \|
		1016	F_INT_ENTRY_REPLACEMENT_FAULT \|
		1017	F_INT_TLB_MISS_FAULT \|
		1018	F_INT_MISS_TRANSACTION_FIFO_FAULT \|
		1019	F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
		1020	writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
		1021
		1022	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
		1023	regval = (data->protect_base >> 1) \| (data->enable_4GB << 31);
		1024	else
		1025	regval = lower_32_bits(data->protect_base) \|
		1026	upper_32_bits(data->protect_base);
		1027	writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
		1028
		1029	if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
		1030	dev_name(bankx->parent_dev), (void *)bankx)) {
		1031	writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
		1032	dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
776	return -ENODEV;	1033	return -ENODEV;
777	}	1034	}
778		1035
@@ -784,21 +1041,91 @@ static const struct component_master_ops mtk_iommu_com_ops = { · 5 unmodified lines
784	.unbind = mtk_iommu_unbind,	1041	.unbind = mtk_iommu_unbind,
785	};	1042	};
786		1043
		1044	static int mtk_iommu_mm_dts_parse(struct device dev, struct component_match *match,
		1045	struct mtk_iommu_data *data)
		1046	{
		1047	struct device_node larbnode, smicomm_node, *smi_subcomm_node;
		1048	struct platform_device *plarbdev;
		1049	struct device_link *link;
		1050	int i, larb_nr, ret;
		1051
		1052	larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
		1053	if (larb_nr < 0)
		1054	return larb_nr;
		1055
		1056	for (i = 0; i < larb_nr; i++) {
		1057	u32 id;
		1058
		1059	larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
		1060	if (!larbnode)
		1061	return -EINVAL;
		1062
		1063	if (!of_device_is_available(larbnode)) {
		1064	of_node_put(larbnode);
		1065	continue;
		1066	}
		1067
		1068	ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
		1069	if (ret)/* The id is consecutive if there is no this property */
		1070	id = i;
		1071
		1072	plarbdev = of_find_device_by_node(larbnode);
		1073	if (!plarbdev) {
		1074	of_node_put(larbnode);
		1075	return -ENODEV;
		1076	}
		1077	if (!plarbdev->dev.driver) {
		1078	of_node_put(larbnode);
		1079	return -EPROBE_DEFER;
		1080	}
		1081	data->larb_imu[id].dev = &plarbdev->dev;
		1082
		1083	component_match_add_release(dev, match, component_release_of,
		1084	component_compare_of, larbnode);
		1085	}
		1086
		1087	/* Get smi-(sub)-common dev from the last larb. */
		1088	smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
		1089	if (!smi_subcomm_node)
		1090	return -EINVAL;
		1091
		1092	/*
		1093	* It may have two level smi-common. the node is smi-sub-common if it
		1094	* has a new mediatek,smi property. otherwise it is smi-commmon.
		1095	*/
		1096	smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
		1097	if (smicomm_node)
		1098	of_node_put(smi_subcomm_node);
		1099	else
		1100	smicomm_node = smi_subcomm_node;
		1101
		1102	plarbdev = of_find_device_by_node(smicomm_node);
		1103	of_node_put(smicomm_node);
		1104	data->smicomm_dev = &plarbdev->dev;
		1105
		1106	link = device_link_add(data->smicomm_dev, dev,
		1107	DL_FLAG_STATELESS \| DL_FLAG_PM_RUNTIME);
		1108	if (!link) {
		1109	dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
		1110	return -EINVAL;
		1111	}
		1112	return 0;
		1113	}
		1114
787	static int mtk_iommu_probe(struct platform_device *pdev)	1115	static int mtk_iommu_probe(struct platform_device *pdev)
788	{	1116	{
789	struct mtk_iommu_data *data;	1117	struct mtk_iommu_data *data;
790	struct device *dev = &pdev->dev;	1118	struct device *dev = &pdev->dev;
791	struct device_node larbnode, smicomm_node;
792	struct platform_device *plarbdev;
793	struct device_link *link;
794	struct resource *res;	1119	struct resource *res;
795	resource_size_t ioaddr;	1120	resource_size_t ioaddr;
796	struct component_match *match = NULL;	1121	struct component_match *match = NULL;
797	struct regmap *infracfg;	1122	struct regmap *infracfg;
798	void *protect;	1123	void *protect;
799	int i, larb_nr, ret;	1124	int ret, banks_num, i = 0;
800	u32 val;	1125	u32 val;
801	char *p;	1126	char *p;
		1127	struct mtk_iommu_bank_data *bank;
		1128	void __iomem *base;
802		1129
803	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);	1130	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
804	if (!data)	1131	if (!data)
@@ -835,15 +1162,36 @@ static int mtk_iommu_probe(struct platform_device *pdev) · 30 unmodified lines
835	data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);	1162	data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
836	}	1163	}
837		1164
		1165	banks_num = data->plat_data->banks_num;
838	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	1166	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
839	data->base = devm_ioremap_resource(dev, res);	1167	if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
840	if (IS_ERR(data->base))	1168	dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
841	return PTR_ERR(data->base);	1169	return -EINVAL;
		1170	}
		1171	base = devm_ioremap_resource(dev, res);
		1172	if (IS_ERR(base))
		1173	return PTR_ERR(base);
842	ioaddr = res->start;	1174	ioaddr = res->start;
843		1175
844	data->irq = platform_get_irq(pdev, 0);	1176	data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
845	if (data->irq < 0)	1177	if (!data->bank)
846	return data->irq;	1178	return -ENOMEM;
		1179
		1180	do {
		1181	if (!data->plat_data->banks_enable[i])
		1182	continue;
		1183	bank = &data->bank[i];
		1184	bank->id = i;
		1185	bank->base = base + i * MTK_IOMMU_BANK_SZ;
		1186	bank->m4u_dom = NULL;
		1187
		1188	bank->irq = platform_get_irq(pdev, i);
		1189	if (bank->irq < 0)
		1190	return bank->irq;
		1191	bank->parent_dev = dev;
		1192	bank->parent_data = data;
		1193	spin_lock_init(&bank->tlb_lock);
		1194	} while (++i < banks_num);
847		1195
848	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {	1196	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
849	data->bclk = devm_clk_get(dev, "bclk");	1197	data->bclk = devm_clk_get(dev, "bclk");
@@ -851,62 +1199,27 @@ static int mtk_iommu_probe(struct platform_device *pdev) · 1 unmodified line
851	return PTR_ERR(data->bclk);	1199	return PTR_ERR(data->bclk);
852	}	1200	}
853		1201
854	larb_nr = of_count_phandle_with_args(dev->of_node,	1202	pm_runtime_enable(dev);
855	"mediatek,larbs", NULL);
856	if (larb_nr < 0)
857	return larb_nr;
858
859	for (i = 0; i < larb_nr; i++) {
860	u32 id;
861
862	larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
863	if (!larbnode)
864	return -EINVAL;
865
866	if (!of_device_is_available(larbnode)) {
867	of_node_put(larbnode);
868	continue;
869	}
870
871	ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
872	if (ret)/* The id is consecutive if there is no this property */
873	id = i;
874		1203
875	plarbdev = of_find_device_by_node(larbnode);	1204	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
876	if (!plarbdev) {	1205	ret = mtk_iommu_mm_dts_parse(dev, &match, data);
877	of_node_put(larbnode);	1206	if (ret) {
878	return -ENODEV;	1207	dev_err(dev, "mm dts parse fail(%d).", ret);
		1208	goto out_runtime_disable;
879	}	1209	}
880	if (!plarbdev->dev.driver) {	1210	} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
881	of_node_put(larbnode);	1211	data->plat_data->pericfg_comp_str) {
882	return -EPROBE_DEFER;	1212	infracfg = syscon_regmap_lookup_by_compatible(data->plat_data->pericfg_comp_str);
		1213	if (IS_ERR(infracfg)) {
		1214	ret = PTR_ERR(infracfg);
		1215	goto out_runtime_disable;
883	}	1216	}
884	data->larb_imu[id].dev = &plarbdev->dev;
885
886	component_match_add_release(dev, &match, component_release_of,
887	component_compare_of, larbnode);
888	}
889
890	/* Get smi-common dev from the last larb. */
891	smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
892	if (!smicomm_node)
893	return -EINVAL;
894
895	plarbdev = of_find_device_by_node(smicomm_node);
896	of_node_put(smicomm_node);
897	data->smicomm_dev = &plarbdev->dev;
898
899	pm_runtime_enable(dev);
900		1217
901	link = device_link_add(data->smicomm_dev, dev,	1218	data->pericfg = infracfg;
902	DL_FLAG_STATELESS \| DL_FLAG_PM_RUNTIME);
903	if (!link) {
904	dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
905	ret = -EINVAL;
906	goto out_runtime_disable;
907	}	1219	}
908		1220
909	platform_set_drvdata(pdev, data);	1221	platform_set_drvdata(pdev, data);
		1222	mutex_init(&data->mutex);
910		1223
911	ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,	1224	ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
912	"mtk-iommu.%pa", &ioaddr);	1225	"mtk-iommu.%pa", &ioaddr);
@@ -917,8 +1230,14 @@ static int mtk_iommu_probe(struct platform_device *pdev) · 4 unmodified lines
917	if (ret)	1230	if (ret)
918	goto out_sysfs_remove;	1231	goto out_sysfs_remove;
919		1232
920	spin_lock_init(&data->tlb_lock);	1233	if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
921	list_add_tail(&data->list, &m4ulist);	1234	list_add_tail(&data->list, data->plat_data->hw_list);
		1235	data->hw_list = data->plat_data->hw_list;
		1236	} else {
		1237	INIT_LIST_HEAD(&data->hw_list_head);
		1238	list_add_tail(&data->list, &data->hw_list_head);
		1239	data->hw_list = &data->hw_list_head;
		1240	}
922		1241
923	if (!iommu_present(&platform_bus_type)) {	1242	if (!iommu_present(&platform_bus_type)) {
924	ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);	1243	ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
@@ -926,9 +1245,20 @@ static int mtk_iommu_probe(struct platform_device *pdev) · 1 unmodified line
926	goto out_list_del;	1245	goto out_list_del;
927	}	1246	}
928		1247
929	ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);	1248	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
930	if (ret)	1249	ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
931	goto out_bus_set_null;	1250	if (ret)
		1251	goto out_bus_set_null;
		1252	} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
		1253	MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
		1254	#ifdef CONFIG_PCI
		1255	if (!iommu_present(&pci_bus_type)) {
		1256	ret = bus_set_iommu(&pci_bus_type, &mtk_iommu_ops);
		1257	if (ret) /* PCIe fail don't affect platform_bus. */
		1258	goto out_list_del;
		1259	}
		1260	#endif
		1261	}
932	return ret;	1262	return ret;
933		1263
934	out_bus_set_null:	1264	out_bus_set_null:
@@ -939,7 +1269,8 @@ out_list_del: · 4 unmodified lines
939	out_sysfs_remove:	1269	out_sysfs_remove:
940	iommu_device_sysfs_remove(&data->iommu);	1270	iommu_device_sysfs_remove(&data->iommu);
941	out_link_remove:	1271	out_link_remove:
942	device_link_remove(data->smicomm_dev, dev);	1272	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
		1273	device_link_remove(data->smicomm_dev, dev);
943	out_runtime_disable:	1274	out_runtime_disable:
944	pm_runtime_disable(dev);	1275	pm_runtime_disable(dev);
945	return ret;	1276	return ret;
@@ -948,18 +1279,30 @@ out_runtime_disable: · 2 unmodified lines
948	static int mtk_iommu_remove(struct platform_device *pdev)	1279	static int mtk_iommu_remove(struct platform_device *pdev)
949	{	1280	{
950	struct mtk_iommu_data *data = platform_get_drvdata(pdev);	1281	struct mtk_iommu_data *data = platform_get_drvdata(pdev);
		1282	struct mtk_iommu_bank_data *bank;
		1283	int i;
951		1284
952	iommu_device_sysfs_remove(&data->iommu);	1285	iommu_device_sysfs_remove(&data->iommu);
953	iommu_device_unregister(&data->iommu);	1286	iommu_device_unregister(&data->iommu);
954		1287
955	if (iommu_present(&platform_bus_type))	1288	list_del(&data->list);
956	bus_set_iommu(&platform_bus_type, NULL);
957		1289
958	clk_disable_unprepare(data->bclk);	1290	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
959	device_link_remove(data->smicomm_dev, &pdev->dev);	1291	device_link_remove(data->smicomm_dev, &pdev->dev);
		1292	component_master_del(&pdev->dev, &mtk_iommu_com_ops);
		1293	} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
		1294	MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
		1295	#ifdef CONFIG_PCI
		1296	bus_set_iommu(&pci_bus_type, NULL);
		1297	#endif
		1298	}
960	pm_runtime_disable(&pdev->dev);	1299	pm_runtime_disable(&pdev->dev);
961	devm_free_irq(&pdev->dev, data->irq, data);	1300	for (i = 0; i < data->plat_data->banks_num; i++) {
962	component_master_del(&pdev->dev, &mtk_iommu_com_ops);	1301	bank = &data->bank[i];
		1302	if (!bank->m4u_dom)
		1303	continue;
		1304	devm_free_irq(&pdev->dev, bank->irq, bank);
		1305	}
963	return 0;	1306	return 0;
964	}	1307	}
965		1308
@@ -967,16 +1310,23 @@ static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) · 1 unmodified line
967	{	1310	{
968	struct mtk_iommu_data *data = dev_get_drvdata(dev);	1311	struct mtk_iommu_data *data = dev_get_drvdata(dev);
969	struct mtk_iommu_suspend_reg *reg = &data->reg;	1312	struct mtk_iommu_suspend_reg *reg = &data->reg;
970	void __iomem *base = data->base;	1313	void __iomem *base;
		1314	int i = 0;
971		1315
		1316	base = data->bank[i].base;
972	reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);	1317	reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
973	reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);	1318	reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
974	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);	1319	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
975	reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);	1320	reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
976	reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
977	reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
978	reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
979	reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);	1321	reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
		1322	do {
		1323	if (!data->plat_data->banks_enable[i])
		1324	continue;
		1325	base = data->bank[i].base;
		1326	reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
		1327	reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
		1328	reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
		1329	} while (++i < data->plat_data->banks_num);
980	clk_disable_unprepare(data->bclk);	1330	clk_disable_unprepare(data->bclk);
981	return 0;	1331	return 0;
982	}	1332	}
@@ -985,9 +1335,9 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) · 2 unmodified lines
985	{	1335	{
986	struct mtk_iommu_data *data = dev_get_drvdata(dev);	1336	struct mtk_iommu_data *data = dev_get_drvdata(dev);
987	struct mtk_iommu_suspend_reg *reg = &data->reg;	1337	struct mtk_iommu_suspend_reg *reg = &data->reg;
988	struct mtk_iommu_domain *m4u_dom = data->m4u_dom;	1338	struct mtk_iommu_domain *m4u_dom;
989	void __iomem *base = data->base;	1339	void __iomem *base;
990	int ret;	1340	int ret, i = 0;
991		1341
992	ret = clk_prepare_enable(data->bclk);	1342	ret = clk_prepare_enable(data->bclk);
993	if (ret) {	1343	if (ret) {
@@ -999,18 +1349,26 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) · 5 unmodified lines
999	* Uppon first resume, only enable the clk and return, since the values of the	1349	* Uppon first resume, only enable the clk and return, since the values of the
1000	* registers are not yet set.	1350	* registers are not yet set.
1001	*/	1351	*/
1002	if (!m4u_dom)	1352	if (!reg->wr_len_ctrl)
1003	return 0;	1353	return 0;
1004		1354
		1355	base = data->bank[i].base;
1005	writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);	1356	writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1006	writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);	1357	writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1007	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);	1358	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1008	writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);	1359	writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1009	writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
1010	writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
1011	writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
1012	writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);	1360	writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1013	writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);	1361	do {
		1362	m4u_dom = data->bank[i].m4u_dom;
		1363	if (!data->plat_data->banks_enable[i] \|\| !m4u_dom)
		1364	continue;
		1365	base = data->bank[i].base;
		1366	writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
		1367	writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
		1368	writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
		1369	writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
		1370	base + REG_MMU_PT_BASE_ADDR);
		1371	} while (++i < data->plat_data->banks_num);
1014		1372
1015	/*	1373	/*
1016	* Users may allocate dma buffer before they call pm_runtime_get,	1374	* Users may allocate dma buffer before they call pm_runtime_get,
@@ -1029,17 +1387,24 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { · 12 unmodified lines
1029		1387
1030	static const struct mtk_iommu_plat_data mt2712_data = {	1388	static const struct mtk_iommu_plat_data mt2712_data = {
1031	.m4u_plat = M4U_MT2712,	1389	.m4u_plat = M4U_MT2712,
1032	.flags = HAS_4GB_MODE \| HAS_BCLK \| HAS_VLD_PA_RNG,	1390	.flags = HAS_4GB_MODE \| HAS_BCLK \| HAS_VLD_PA_RNG \| SHARE_PGTABLE \|
		1391	MTK_IOMMU_TYPE_MM,
		1392	.hw_list = &m4ulist,
1033	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,	1393	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1034	.iova_region = single_domain,	1394	.iova_region = single_domain,
		1395	.banks_num = 1,
		1396	.banks_enable = {true},
1035	.iova_region_nr = ARRAY_SIZE(single_domain),	1397	.iova_region_nr = ARRAY_SIZE(single_domain),
1036	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},	1398	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1037	};	1399	};
1038		1400
1039	static const struct mtk_iommu_plat_data mt6779_data = {	1401	static const struct mtk_iommu_plat_data mt6779_data = {
1040	.m4u_plat = M4U_MT6779,	1402	.m4u_plat = M4U_MT6779,
1041	.flags = HAS_SUB_COMM \| OUT_ORDER_WR_EN \| WR_THROT_EN,	1403	.flags = HAS_SUB_COMM_2BITS \| OUT_ORDER_WR_EN \| WR_THROT_EN \|
		1404	MTK_IOMMU_TYPE_MM,
1042	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,	1405	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
		1406	.banks_num = 1,
		1407	.banks_enable = {true},
1043	.iova_region = single_domain,	1408	.iova_region = single_domain,
1044	.iova_region_nr = ARRAY_SIZE(single_domain),	1409	.iova_region_nr = ARRAY_SIZE(single_domain),
1045	.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},	1410	.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
@@ -1047,8 +1412,10 @@ static const struct mtk_iommu_plat_data mt6779_data = { · 1 unmodified line
1047		1412
1048	static const struct mtk_iommu_plat_data mt8167_data = {	1413	static const struct mtk_iommu_plat_data mt8167_data = {
1049	.m4u_plat = M4U_MT8167,	1414	.m4u_plat = M4U_MT8167,
1050	.flags = RESET_AXI \| HAS_LEGACY_IVRP_PADDR,	1415	.flags = RESET_AXI \| HAS_LEGACY_IVRP_PADDR \| MTK_IOMMU_TYPE_MM,
1051	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,	1416	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
		1417	.banks_num = 1,
		1418	.banks_enable = {true},
1052	.iova_region = single_domain,	1419	.iova_region = single_domain,
1053	.iova_region_nr = ARRAY_SIZE(single_domain),	1420	.iova_region_nr = ARRAY_SIZE(single_domain),
1054	.larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */	1421	.larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
@@ -1057,8 +1424,10 @@ static const struct mtk_iommu_plat_data mt8167_data = { · 2 unmodified lines
1057	static const struct mtk_iommu_plat_data mt8173_data = {	1424	static const struct mtk_iommu_plat_data mt8173_data = {
1058	.m4u_plat = M4U_MT8173,	1425	.m4u_plat = M4U_MT8173,
1059	.flags = HAS_4GB_MODE \| HAS_BCLK \| RESET_AXI \|	1426	.flags = HAS_4GB_MODE \| HAS_BCLK \| RESET_AXI \|
1060	HAS_LEGACY_IVRP_PADDR,	1427	HAS_LEGACY_IVRP_PADDR \| MTK_IOMMU_TYPE_MM,
1061	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,	1428	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
		1429	.banks_num = 1,
		1430	.banks_enable = {true},
1062	.iova_region = single_domain,	1431	.iova_region = single_domain,
1063	.iova_region_nr = ARRAY_SIZE(single_domain),	1432	.iova_region_nr = ARRAY_SIZE(single_domain),
1064	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */	1433	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
@@ -1066,31 +1435,100 @@ static const struct mtk_iommu_plat_data mt8173_data = { · 1 unmodified line
1066		1435
1067	static const struct mtk_iommu_plat_data mt8183_data = {	1436	static const struct mtk_iommu_plat_data mt8183_data = {
1068	.m4u_plat = M4U_MT8183,	1437	.m4u_plat = M4U_MT8183,
1069	.flags = RESET_AXI,	1438	.flags = RESET_AXI \| MTK_IOMMU_TYPE_MM,
1070	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,	1439	.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
		1440	.banks_num = 1,
		1441	.banks_enable = {true},
1071	.iova_region = single_domain,	1442	.iova_region = single_domain,
1072	.iova_region_nr = ARRAY_SIZE(single_domain),	1443	.iova_region_nr = ARRAY_SIZE(single_domain),
1073	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},	1444	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1074	};	1445	};
1075		1446
		1447	static const struct mtk_iommu_plat_data mt8186_data_mm = {
		1448	.m4u_plat = M4U_MT8186,
		1449	.flags = HAS_BCLK \| HAS_SUB_COMM_2BITS \| OUT_ORDER_WR_EN \|
		1450	WR_THROT_EN \| IOVA_34_EN \| MTK_IOMMU_TYPE_MM,
		1451	.larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
		1452	{MTK_INVALID_LARBID, 14, 16},
		1453	{MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
		1454	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
		1455	.banks_num = 1,
		1456	.banks_enable = {true},
		1457	.iova_region = mt8192_multi_dom,
		1458	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
		1459	};
		1460
1076	static const struct mtk_iommu_plat_data mt8192_data = {	1461	static const struct mtk_iommu_plat_data mt8192_data = {
1077	.m4u_plat = M4U_MT8192,	1462	.m4u_plat = M4U_MT8192,
1078	.flags = HAS_BCLK \| HAS_SUB_COMM \| OUT_ORDER_WR_EN \|	1463	.flags = HAS_BCLK \| HAS_SUB_COMM_2BITS \| OUT_ORDER_WR_EN \|
1079	WR_THROT_EN \| IOVA_34_EN,	1464	WR_THROT_EN \| IOVA_34_EN \| MTK_IOMMU_TYPE_MM,
1080	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,	1465	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
		1466	.banks_num = 1,
		1467	.banks_enable = {true},
1081	.iova_region = mt8192_multi_dom,	1468	.iova_region = mt8192_multi_dom,
1082	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),	1469	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1083	.larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},	1470	.larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1084	{0, 14, 16}, {0, 13, 18, 17}},	1471	{0, 14, 16}, {0, 13, 18, 17}},
1085	};	1472	};
1086		1473
		1474	static const struct mtk_iommu_plat_data mt8195_data_infra = {
		1475	.m4u_plat = M4U_MT8195,
		1476	.flags = WR_THROT_EN \| DCM_DISABLE \| STD_AXI_MODE \| PM_CLK_AO \|
		1477	MTK_IOMMU_TYPE_INFRA \| IFA_IOMMU_PCIE_SUPPORT,
		1478	.pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
		1479	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
		1480	.banks_num = 5,
		1481	.banks_enable = {true, false, false, false, true},
		1482	.banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */
		1483	[4] = GENMASK(31, 20), /* USB */
		1484	},
		1485	.iova_region = single_domain,
		1486	.iova_region_nr = ARRAY_SIZE(single_domain),
		1487	};
		1488
		1489	static const struct mtk_iommu_plat_data mt8195_data_vdo = {
		1490	.m4u_plat = M4U_MT8195,
		1491	.flags = HAS_BCLK \| HAS_SUB_COMM_2BITS \| OUT_ORDER_WR_EN \|
		1492	WR_THROT_EN \| IOVA_34_EN \| SHARE_PGTABLE \| MTK_IOMMU_TYPE_MM,
		1493	.hw_list = &m4ulist,
		1494	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
		1495	.banks_num = 1,
		1496	.banks_enable = {true},
		1497	.iova_region = mt8192_multi_dom,
		1498	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
		1499	.larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
		1500	{13, 17, 15/* 17b */, 25}, {5}},
		1501	};
		1502
		1503	static const struct mtk_iommu_plat_data mt8195_data_vpp = {
		1504	.m4u_plat = M4U_MT8195,
		1505	.flags = HAS_BCLK \| HAS_SUB_COMM_3BITS \| OUT_ORDER_WR_EN \|
		1506	WR_THROT_EN \| IOVA_34_EN \| SHARE_PGTABLE \| MTK_IOMMU_TYPE_MM,
		1507	.hw_list = &m4ulist,
		1508	.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
		1509	.banks_num = 1,
		1510	.banks_enable = {true},
		1511	.iova_region = mt8192_multi_dom,
		1512	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
		1513	.larbid_remap = {{1}, {3},
		1514	{22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
		1515	{8}, {20}, {12},
		1516	/* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
		1517	{14, 16, 29, 26, 30, 31, 18},
		1518	{4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
		1519	};
		1520
1087	static const struct of_device_id mtk_iommu_of_ids[] = {	1521	static const struct of_device_id mtk_iommu_of_ids[] = {
1088	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},	1522	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1089	{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},	1523	{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1090	{ .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},	1524	{ .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1091	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},	1525	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1092	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},	1526	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
		1527	{ .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
1093	{ .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},	1528	{ .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
		1529	{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
		1530	{ .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
		1531	{ .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
1094	{}	1532	{}
1095	};	1533	};
1096		1534

drivers/iommu/mtk_iommu.h+0−101

@@ -1,101 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0-only */
2	/*
3	* Copyright (c) 2015-2016 MediaTek Inc.
4	* Author: Honghui Zhang <honghui.zhang@mediatek.com>
5	*/
6
7	#ifndef _MTK_IOMMU_H_
8	#define _MTK_IOMMU_H_
9
10	#include <linux/clk.h>
11	#include <linux/component.h>
12	#include <linux/device.h>
13	#include <linux/io.h>
14	#include <linux/io-pgtable.h>
15	#include <linux/iommu.h>
16	#include <linux/list.h>
17	#include <linux/spinlock.h>
18	#include <linux/dma-mapping.h>
19	#include <soc/mediatek/smi.h>
20	#include <dt-bindings/memory/mtk-memory-port.h>
21
22	#define MTK_LARB_COM_MAX 8
23	#define MTK_LARB_SUBCOM_MAX 4
24
25	#define MTK_IOMMU_GROUP_MAX 8
26
27	struct mtk_iommu_suspend_reg {
28	union {
29	u32 standard_axi_mode;/* v1 */
30	u32 misc_ctrl;/* v2 */
31	};
32	u32 dcm_dis;
33	u32 ctrl_reg;
34	u32 int_control0;
35	u32 int_main_control;
36	u32 ivrp_paddr;
37	u32 vld_pa_rng;
38	u32 wr_len_ctrl;
39	};
40
41	enum mtk_iommu_plat {
42	M4U_MT2701,
43	M4U_MT2712,
44	M4U_MT6779,
45	M4U_MT8167,
46	M4U_MT8173,
47	M4U_MT8183,
48	M4U_MT8192,
49	};
50
51	struct mtk_iommu_iova_region;
52
53	struct mtk_iommu_plat_data {
54	enum mtk_iommu_plat m4u_plat;
55	u32 flags;
56	u32 inv_sel_reg;
57
58	unsigned int iova_region_nr;
59	const struct mtk_iommu_iova_region *iova_region;
60	unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
61	};
62
63	struct mtk_iommu_domain;
64
65	struct mtk_iommu_data {
66	void __iomem *base;
67	int irq;
68	struct device *dev;
69	struct clk *bclk;
70	phys_addr_t protect_base; /* protect memory base */
71	struct mtk_iommu_suspend_reg reg;
72	struct mtk_iommu_domain *m4u_dom;
73	struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
74	bool enable_4GB;
75	spinlock_t tlb_lock; /* lock for tlb range flush */
76
77	struct iommu_device iommu;
78	const struct mtk_iommu_plat_data *plat_data;
79	struct device *smicomm_dev;
80
81	struct dma_iommu_mapping mapping; / For mtk_iommu_v1.c */
82
83	struct list_head list;
84	struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
85	};
86
87	static inline int mtk_iommu_bind(struct device *dev)
88	{
89	struct mtk_iommu_data *data = dev_get_drvdata(dev);
90
91	return component_bind_all(dev, &data->larb_imu);
92	}
93
94	static inline void mtk_iommu_unbind(struct device *dev)
95	{
96	struct mtk_iommu_data *data = dev_get_drvdata(dev);
97
98	component_unbind_all(dev, &data->larb_imu);
99	}
100
101	#endif

drivers/iommu/mtk_iommu_v1.c+139−103

  *
  * Based on driver/iommu/mtk_iommu.c
  */
-#include <linux/memblock.h>
 #include <linux/bug.h>
 #include <linux/clk.h>
 #include <linux/component.h>
 #include <linux/spinlock.h>
 #include <asm/barrier.h>
 #include <asm/dma-iommu.h>
-#include <linux/init.h>
+#include <dt-bindings/memory/mtk-memory-port.h>
 #include <dt-bindings/memory/mt2701-larb-port.h>
 #include <soc/mediatek/smi.h>
-#include "mtk_iommu.h"
 #define REG_MMU_PT_BASE_ADDR			0x000
 /* MTK generation one iommu HW only support 4K size mapping */
 #define MT2701_IOMMU_PAGE_SHIFT			12
 #define MT2701_IOMMU_PAGE_SIZE			(1UL << MT2701_IOMMU_PAGE_SHIFT)
+#define MT2701_LARB_NR_MAX			3
 /*
  * MTK m4u support 4GB iova address space, and only support 4K page
  */
 #define M2701_IOMMU_PGT_SIZE			SZ_4M
-struct mtk_iommu_domain {
+struct mtk_iommu_v1_suspend_reg {
+	u32			standard_axi_mode;
+	u32			dcm_dis;
+	u32			ctrl_reg;
+	u32			int_control0;
+};
+struct mtk_iommu_v1_data {
+	void __iomem			*base;
+	int				irq;
+	struct device			*dev;
+	struct clk			*bclk;
+	phys_addr_t			protect_base; /* protect memory base */
+	struct mtk_iommu_v1_domain	*m4u_dom;
+	struct iommu_device		iommu;
+	struct dma_iommu_mapping	*mapping;
+	struct mtk_smi_larb_iommu	larb_imu[MTK_LARB_NR_MAX];
+	struct mtk_iommu_v1_suspend_reg	reg;
+};
+struct mtk_iommu_v1_domain {
 	spinlock_t			pgtlock; /* lock for page table */
 	struct iommu_domain		domain;
 	u32				*pgt_va;
 	dma_addr_t			pgt_pa;
-	struct mtk_iommu_data		*data;
+	struct mtk_iommu_v1_data	*data;
 };
-static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
+static int mtk_iommu_v1_bind(struct device *dev)
+{
+	struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
+	return component_bind_all(dev, &data->larb_imu);
+}
+static void mtk_iommu_v1_unbind(struct device *dev)
+{
+	struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
+	component_unbind_all(dev, &data->larb_imu);
+}
+static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom)
 {
-	return container_of(dom, struct mtk_iommu_domain, domain);
+	return container_of(dom, struct mtk_iommu_v1_domain, domain);
 }
 static const int mt2701_m4u_in_larb[] = {
 	return id - mt2701_m4u_in_larb[larb];
 }
-static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
+static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data)
 {
 	writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 			data->base + REG_MMU_INV_SEL);
 	wmb(); /* Make sure the tlb flush all done */
 }
-static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
+static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data,
-				unsigned long iova, size_t size)
+					 unsigned long iova, size_t size)
 {
 	int ret;
 	u32 tmp;
 	if (ret) {
 		dev_warn(data->dev,
 			 "Partial TLB flush timed out, falling back to full flush\n");
-		mtk_iommu_tlb_flush_all(data);
+		mtk_iommu_v1_tlb_flush_all(data);
 	}
 	/* Clear the CPE status */
 	writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 }
-static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
+static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id)
 {
-	struct mtk_iommu_data *data = dev_id;
+	struct mtk_iommu_v1_data *data = dev_id;
-	struct mtk_iommu_domain *dom = data->m4u_dom;
+	struct mtk_iommu_v1_domain *dom = data->m4u_dom;
 	u32 int_state, regval, fault_iova, fault_pa;
 	unsigned int fault_larb, fault_port;
 	regval |= F_INT_CLR_BIT;
 	writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
-	mtk_iommu_tlb_flush_all(data);
+	mtk_iommu_v1_tlb_flush_all(data);
 	return IRQ_HANDLED;
 }
-static void mtk_iommu_config(struct mtk_iommu_data *data,
+static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data,
-			     struct device *dev, bool enable)
+				struct device *dev, bool enable)
 {
 	struct mtk_smi_larb_iommu    *larb_mmu;
 	unsigned int                 larbid, portid;
 	}
 }
-static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
+static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data)
 {
-	struct mtk_iommu_domain *dom = data->m4u_dom;
+	struct mtk_iommu_v1_domain *dom = data->m4u_dom;
 	spin_lock_init(&dom->pgtlock);
 	return 0;
 }
-static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
+static struct iommu_domain *mtk_iommu_v1_domain_alloc(unsigned type)
 {
-	struct mtk_iommu_domain *dom;
+	struct mtk_iommu_v1_domain *dom;
 	if (type != IOMMU_DOMAIN_UNMANAGED)
 		return NULL;
 	return &dom->domain;
 }
-static void mtk_iommu_domain_free(struct iommu_domain *domain)
+static void mtk_iommu_v1_domain_free(struct iommu_domain *domain)
 {
-	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+	struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
-	struct mtk_iommu_data *data = dom->data;
+	struct mtk_iommu_v1_data *data = dom->data;
 	dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
 			dom->pgt_va, dom->pgt_pa);
 	kfree(to_mtk_domain(domain));
 }
-static int mtk_iommu_attach_device(struct iommu_domain *domain,
+static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev)
-				   struct device *dev)
 {
-	struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
+	struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
-	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+	struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 	struct dma_iommu_mapping *mtk_mapping;
 	int ret;
 	if (!data->m4u_dom) {
 		data->m4u_dom = dom;
-		ret = mtk_iommu_domain_finalise(data);
+		ret = mtk_iommu_v1_domain_finalise(data);
 		if (ret) {
 			data->m4u_dom = NULL;
 			return ret;
 		}
 	}
-	mtk_iommu_config(data, dev, true);
+	mtk_iommu_v1_config(data, dev, true);
 	return 0;
 }
-static void mtk_iommu_detach_device(struct iommu_domain *domain,
+static void mtk_iommu_v1_detach_device(struct iommu_domain *domain, struct device *dev)
-				    struct device *dev)
 {
-	struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
+	struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
-	mtk_iommu_config(data, dev, false);
+	mtk_iommu_v1_config(data, dev, false);
 }
-static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
+static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova,
-			 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
+			    phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 {
-	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+	struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 	unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
 	unsigned long flags;
 	unsigned int i;
 	spin_unlock_irqrestore(&dom->pgtlock, flags);
-	mtk_iommu_tlb_flush_range(dom->data, iova, size);
+	mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
 	return map_size == size ? 0 : -EEXIST;
 }
-static size_t mtk_iommu_unmap(struct iommu_domain *domain,
+static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova,
-			      unsigned long iova, size_t size,
+				 size_t size, struct iommu_iotlb_gather *gather)
-			      struct iommu_iotlb_gather *gather)
 {
-	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+	struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 	unsigned long flags;
 	u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 	unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
 	memset(pgt_base_iova, 0, page_num * sizeof(u32));
 	spin_unlock_irqrestore(&dom->pgtlock, flags);
-	mtk_iommu_tlb_flush_range(dom->data, iova, size);
+	mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
 	return size;
 }
-static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
+static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
-					  dma_addr_t iova)
 {
-	struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+	struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
 	unsigned long flags;
 	phys_addr_t pa;
 	return pa;
 }
-static const struct iommu_ops mtk_iommu_ops;
+static const struct iommu_ops mtk_iommu_v1_ops;
 /*
  * MTK generation one iommu HW only support one iommu domain, and all the client
  * sharing the same iova address space.
  */
-static int mtk_iommu_create_mapping(struct device *dev,
+static int mtk_iommu_v1_create_mapping(struct device *dev, struct of_phandle_args *args)
-				    struct of_phandle_args *args)
 {
 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
-	struct mtk_iommu_data *data;
+	struct mtk_iommu_v1_data *data;
 	struct platform_device *m4updev;
 	struct dma_iommu_mapping *mtk_mapping;
 	int ret;
 	}
 	if (!fwspec) {
-		ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
+		ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_v1_ops);
 		if (ret)
 			return ret;
 		fwspec = dev_iommu_fwspec_get(dev);
-	} else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
+	} else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_v1_ops) {
 		return -EINVAL;
 	}
 	return 0;
 }
-static int mtk_iommu_def_domain_type(struct device *dev)
+static int mtk_iommu_v1_def_domain_type(struct device *dev)
 {
 	return IOMMU_DOMAIN_UNMANAGED;
 }
-static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
+static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)
 {
 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 	struct of_phandle_args iommu_spec;
-	struct mtk_iommu_data *data;
+	struct mtk_iommu_v1_data *data;
 	int err, idx = 0, larbid, larbidx;
 	struct device_link *link;
 	struct device *larbdev;
 					   "#iommu-cells",
 					   idx, &iommu_spec)) {
-		err = mtk_iommu_create_mapping(dev, &iommu_spec);
+		err = mtk_iommu_v1_create_mapping(dev, &iommu_spec);
 		of_node_put(iommu_spec.np);
 		if (err)
 			return ERR_PTR(err);
 		idx++;
 	}
-	if (!fwspec || fwspec->ops != &mtk_iommu_ops)
+	if (!fwspec || fwspec->ops != &mtk_iommu_v1_ops)
 		return ERR_PTR(-ENODEV); /* Not a iommu client device */
 	data = dev_iommu_priv_get(dev);
 	/* Link the consumer device with the smi-larb device(supplier) */
 	larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
+	if (larbid >= MT2701_LARB_NR_MAX)
+		return ERR_PTR(-EINVAL);
 	for (idx = 1; idx < fwspec->num_ids; idx++) {
 		larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]);
 		if (larbid != larbidx) {
 	}
 	larbdev = data->larb_imu[larbid].dev;
+	if (!larbdev)
+		return ERR_PTR(-EINVAL);
 	link = device_link_add(dev, larbdev,
 			       DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 	if (!link)
 	return &data->iommu;
 }
-static void mtk_iommu_probe_finalize(struct device *dev)
+static void mtk_iommu_v1_probe_finalize(struct device *dev)
 {
 	struct dma_iommu_mapping *mtk_mapping;
-	struct mtk_iommu_data *data;
+	struct mtk_iommu_v1_data *data;
 	int err;
 	data        = dev_iommu_priv_get(dev);
 		dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
 }
-static void mtk_iommu_release_device(struct device *dev)
+static void mtk_iommu_v1_release_device(struct device *dev)
 {
 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
-	struct mtk_iommu_data *data;
+	struct mtk_iommu_v1_data *data;
 	struct device *larbdev;
 	unsigned int larbid;
-	if (!fwspec || fwspec->ops != &mtk_iommu_ops)
+	if (!fwspec || fwspec->ops != &mtk_iommu_v1_ops)
 		return;
 	data = dev_iommu_priv_get(dev);
 	iommu_fwspec_free(dev);
 }
-static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
+static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data)
 {
 	u32 regval;
 	int ret;
 	writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
-	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
+	if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0,
 			     dev_name(data->dev), (void *)data)) {
 		writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 		clk_disable_unprepare(data->bclk);
 	return 0;
 }
-static const struct iommu_ops mtk_iommu_ops = {
+static const struct iommu_ops mtk_iommu_v1_ops = {
-	.domain_alloc	= mtk_iommu_domain_alloc,
+	.domain_alloc	= mtk_iommu_v1_domain_alloc,
-	.probe_device	= mtk_iommu_probe_device,
+	.probe_device	= mtk_iommu_v1_probe_device,
-	.probe_finalize = mtk_iommu_probe_finalize,
+	.probe_finalize = mtk_iommu_v1_probe_finalize,
-	.release_device	= mtk_iommu_release_device,
+	.release_device	= mtk_iommu_v1_release_device,
-	.def_domain_type = mtk_iommu_def_domain_type,
+	.def_domain_type = mtk_iommu_v1_def_domain_type,
 	.device_group	= generic_device_group,
 	.pgsize_bitmap	= ~0UL << MT2701_IOMMU_PAGE_SHIFT,
 	.owner          = THIS_MODULE,
 	.default_domain_ops = &(const struct iommu_domain_ops) {
-		.attach_dev	= mtk_iommu_attach_device,
+		.attach_dev	= mtk_iommu_v1_attach_device,
-		.detach_dev	= mtk_iommu_detach_device,
+		.detach_dev	= mtk_iommu_v1_detach_device,
-		.map		= mtk_iommu_map,
+		.map		= mtk_iommu_v1_map,
-		.unmap		= mtk_iommu_unmap,
+		.unmap		= mtk_iommu_v1_unmap,
-		.iova_to_phys	= mtk_iommu_iova_to_phys,
+		.iova_to_phys	= mtk_iommu_v1_iova_to_phys,
-		.free		= mtk_iommu_domain_free,
+		.free		= mtk_iommu_v1_domain_free,
 	}
 };
-static const struct of_device_id mtk_iommu_of_ids[] = {
+static const struct of_device_id mtk_iommu_v1_of_ids[] = {
 	{ .compatible = "mediatek,mt2701-m4u", },
 	{}
 };
-static const struct component_master_ops mtk_iommu_com_ops = {
+static const struct component_master_ops mtk_iommu_v1_com_ops = {
-	.bind		= mtk_iommu_bind,
+	.bind		= mtk_iommu_v1_bind,
-	.unbind		= mtk_iommu_unbind,
+	.unbind		= mtk_iommu_v1_unbind,
 };
-static int mtk_iommu_probe(struct platform_device *pdev)
+static int mtk_iommu_v1_probe(struct platform_device *pdev)
 {
-	struct mtk_iommu_data		*data;
 	struct device			*dev = &pdev->dev;
+	struct mtk_iommu_v1_data	*data;
 	struct resource			*res;
 	struct component_match		*match = NULL;
 	void				*protect;
 	platform_set_drvdata(pdev, data);
-	ret = mtk_iommu_hw_init(data);
+	ret = mtk_iommu_v1_hw_init(data);
 	if (ret)
 		return ret;
 	if (ret)
 		return ret;
-	ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
+	ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev);
 	if (ret)
 		goto out_sysfs_remove;
 	if (!iommu_present(&platform_bus_type)) {
-		ret = bus_set_iommu(&platform_bus_type,  &mtk_iommu_ops);
+		ret = bus_set_iommu(&platform_bus_type,  &mtk_iommu_v1_ops);
 		if (ret)
 			goto out_dev_unreg;
 	}
-	ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
+	ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match);
 	if (ret)
 		goto out_bus_set_null;
 	return ret;
 	return ret;
 }
-static int mtk_iommu_remove(struct platform_device *pdev)
+static int mtk_iommu_v1_remove(struct platform_device *pdev)
 {
-	struct mtk_iommu_data *data = platform_get_drvdata(pdev);
+	struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev);
 	iommu_device_sysfs_remove(&data->iommu);
 	iommu_device_unregister(&data->iommu);
 	clk_disable_unprepare(data->bclk);
 	devm_free_irq(&pdev->dev, data->irq, data);
-	component_master_del(&pdev->dev, &mtk_iommu_com_ops);
+	component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops);
 	return 0;
 }
-static int __maybe_unused mtk_iommu_suspend(struct device *dev)
+static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev)
 {
-	struct mtk_iommu_data *data = dev_get_drvdata(dev);
+	struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
-	struct mtk_iommu_suspend_reg *reg = &data->reg;
+	struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
 	void __iomem *base = data->base;
 	reg->standard_axi_mode = readl_relaxed(base +
 	return 0;
 }
-static int __maybe_unused mtk_iommu_resume(struct device *dev)
+static int __maybe_unused mtk_iommu_v1_resume(struct device *dev)
 {
-	struct mtk_iommu_data *data = dev_get_drvdata(dev);
+	struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
-	struct mtk_iommu_suspend_reg *reg = &data->reg;
+	struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
 	void __iomem *base = data->base;
 	writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
 	return 0;
 }
-static const struct dev_pm_ops mtk_iommu_pm_ops = {
+static const struct dev_pm_ops mtk_iommu_v1_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
+	SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume)
 };
-static struct platform_driver mtk_iommu_driver = {
+static struct platform_driver mtk_iommu_v1_driver = {
-	.probe	= mtk_iommu_probe,
+	.probe	= mtk_iommu_v1_probe,
-	.remove	= mtk_iommu_remove,
+	.remove	= mtk_iommu_v1_remove,
 	.driver	= {
 		.name = "mtk-iommu-v1",
-		.of_match_table = mtk_iommu_of_ids,
+		.of_match_table = mtk_iommu_v1_of_ids,
-		.pm = &mtk_iommu_pm_ops,
+		.pm = &mtk_iommu_v1_pm_ops,
 	}
 };
-module_platform_driver(mtk_iommu_driver);
+module_platform_driver(mtk_iommu_v1_driver);
 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
 MODULE_LICENSE("GPL v2");

drivers/iommu/s390-iommu.c+12−3

 	if (!domain_device)
 		return -ENOMEM;
-	if (zdev->dma_table) {
+	if (zdev->dma_table && !zdev->s390_domain) {
 		cc = zpci_dma_exit_device(zdev);
 		if (cc) {
 			rc = -EIO;
 		}
 	}
+	if (zdev->s390_domain)
+		zpci_unregister_ioat(zdev, 0);
 	zdev->dma_table = s390_domain->dma_table;
 	cc = zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma,
 				virt_to_phys(zdev->dma_table));
 	return 0;
 out_restore:
-	zpci_dma_init_device(zdev);
+	if (!zdev->s390_domain) {
+		zpci_dma_init_device(zdev);
+	} else {
+		zdev->dma_table = zdev->s390_domain->dma_table;
+		zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma,
+				   virt_to_phys(zdev->dma_table));
+	}
 out_free:
 	kfree(domain_device);
 	}
 	spin_unlock_irqrestore(&s390_domain->list_lock, flags);
-	if (found) {
+	if (found && (zdev->s390_domain == s390_domain)) {
 		zdev->s390_domain = NULL;
 		zpci_unregister_ioat(zdev, 0);
 		zpci_dma_init_device(zdev);

drivers/memory/renesas-rpc-if.c+46−14

@@ -164,25 +164,39 @@ static const struct regmap_access_table rpcif_volatile_table = { · 163 unmodified lines
164		164
165		165
166	/*	166	/*
167	* Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed	167	* Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
168	* with proper width. Requires SMENR_SPIDE to be correctly set before!	168	* proper width. Requires rpcif.xfer_size to be correctly set before!
169	*/	169	*/
170	static int rpcif_reg_read(void context, unsigned int reg, unsigned int val)	170	static int rpcif_reg_read(void context, unsigned int reg, unsigned int val)
171	{	171	{
172	struct rpcif *rpc = context;	172	struct rpcif *rpc = context;
173		173
174	if (reg == RPCIF_SMRDR0 \|\| reg == RPCIF_SMWDR0) {	174	switch (reg) {
175	u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);	175	case RPCIF_SMRDR0:
176		176	case RPCIF_SMWDR0:
177	if (spide == 0x8) {	177	switch (rpc->xfer_size) {
		178	case 1:
178	*val = readb(rpc->base + reg);	179	*val = readb(rpc->base + reg);
179	return 0;	180	return 0;
180	} else if (spide == 0xC) {	181
		182	case 2:
181	*val = readw(rpc->base + reg);	183	*val = readw(rpc->base + reg);
182	return 0;	184	return 0;
183	} else if (spide != 0xF) {	185
		186	case 4:
		187	case 8:
		188	*val = readl(rpc->base + reg);
		189	return 0;
		190
		191	default:
184	return -EILSEQ;	192	return -EILSEQ;
185	}	193	}
		194
		195	case RPCIF_SMRDR1:
		196	case RPCIF_SMWDR1:
		197	if (rpc->xfer_size != 8)
		198	return -EILSEQ;
		199	break;
186	}	200	}
187		201
188	*val = readl(rpc->base + reg);	202	*val = readl(rpc->base + reg);
@@ -193,18 +207,34 @@ static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val) · 4 unmodified lines
193	{	207	{
194	struct rpcif *rpc = context;	208	struct rpcif *rpc = context;
195		209
196	if (reg == RPCIF_SMRDR0 \|\| reg == RPCIF_SMWDR0) {	210	switch (reg) {
197	u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);	211	case RPCIF_SMWDR0:
198		212	switch (rpc->xfer_size) {
199	if (spide == 0x8) {	213	case 1:
200	writeb(val, rpc->base + reg);	214	writeb(val, rpc->base + reg);
201	return 0;	215	return 0;
202	} else if (spide == 0xC) {	216
		217	case 2:
203	writew(val, rpc->base + reg);	218	writew(val, rpc->base + reg);
204	return 0;	219	return 0;
205	} else if (spide != 0xF) {	220
		221	case 4:
		222	case 8:
		223	writel(val, rpc->base + reg);
		224	return 0;
		225
		226	default:
206	return -EILSEQ;	227	return -EILSEQ;
207	}	228	}
		229
		230	case RPCIF_SMWDR1:
		231	if (rpc->xfer_size != 8)
		232	return -EILSEQ;
		233	break;
		234
		235	case RPCIF_SMRDR0:
		236	case RPCIF_SMRDR1:
		237	return -EPERM;
208	}	238	}
209		239
210	writel(val, rpc->base + reg);	240	writel(val, rpc->base + reg);
@@ -469,6 +499,7 @@ int rpcif_manual_xfer(struct rpcif *rpc) · 258 unmodified lines
469		499
470	smenr \|= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));	500	smenr \|= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
471	regmap_write(rpc->regmap, RPCIF_SMENR, smenr);	501	regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
		502	rpc->xfer_size = nbytes;
472		503
473	memcpy(data, rpc->buffer + pos, nbytes);	504	memcpy(data, rpc->buffer + pos, nbytes);
474	if (nbytes == 8) {	505	if (nbytes == 8) {
@@ -533,6 +564,7 @@ int rpcif_manual_xfer(struct rpcif *rpc) · 58 unmodified lines
533	regmap_write(rpc->regmap, RPCIF_SMENR, smenr);	564	regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
534	regmap_write(rpc->regmap, RPCIF_SMCR,	565	regmap_write(rpc->regmap, RPCIF_SMCR,
535	rpc->smcr \| RPCIF_SMCR_SPIE);	566	rpc->smcr \| RPCIF_SMCR_SPIE);
		567	rpc->xfer_size = nbytes;
536	ret = wait_msg_xfer_end(rpc);	568	ret = wait_msg_xfer_end(rpc);
537	if (ret)	569	if (ret)
538	goto err_out;	570	goto err_out;

drivers/misc/eeprom/at25.c+11−8

  */
 #define	FM25_SN_LEN	8		/* serial number length */
+#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */
 struct at25_data {
 	struct spi_eeprom	chip;
 	struct spi_device	*spi;
 	struct nvmem_config	nvmem_config;
 	struct nvmem_device	*nvmem;
 	u8 sernum[FM25_SN_LEN];
+	u8 command[EE_MAXADDRLEN + 1];
 };
 #define	AT25_WREN	0x06		/* latch the write enable */
 #define	FM25_ID_LEN	9		/* ID length */
-#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */
 /*
  * Specs often allow 5ms for a page write, sometimes 20ms;
  * it's important to recover from write timeouts.
 {
 	struct at25_data *at25 = priv;
 	char *buf = val;
-	u8			command[EE_MAXADDRLEN + 1];
 	u8			*cp;
 	ssize_t			status;
 	struct spi_transfer	t[2];
 	if (unlikely(!count))
 		return -EINVAL;
-	cp = command;
+	cp = at25->command;
 	instr = AT25_READ;
 	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
 		if (offset >= BIT(at25->addrlen * 8))
 			instr |= AT25_INSTR_BIT3;
+	mutex_lock(&at25->lock);
 	*cp++ = instr;
 	/* 8/16/24-bit address is written MSB first */
 	spi_message_init(&m);
 	memset(t, 0, sizeof(t));
-	t[0].tx_buf = command;
+	t[0].tx_buf = at25->command;
 	t[0].len = at25->addrlen + 1;
 	spi_message_add_tail(&t[0], &m);
 	t[1].len = count;
 	spi_message_add_tail(&t[1], &m);
-	mutex_lock(&at25->lock);
 	/*
 	 * Read it all at once.
 	 *
 	spi_message_init(&m);
 	memset(t, 0, sizeof(t));
-	t[0].tx_buf = &command;
+	t[0].tx_buf = at25->command;
 	t[0].len = 1;
 	spi_message_add_tail(&t[0], &m);
 	mutex_lock(&at25->lock);
+	at25->command[0] = command;
 	status = spi_sync(at25->spi, &m);
 	dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);

drivers/mmc/core/mmc.c+19−4

 		goto out_err;
 	}
+	/*
+	 * Bump to HS timing and frequency. Some cards don't handle
+	 * SEND_STATUS reliably at the initial frequency.
+	 */
 	mmc_set_timing(host, MMC_TIMING_MMC_HS);
+	mmc_set_bus_speed(card);
 	err = mmc_switch_status(card, true);
 	if (err)
 		goto out_err;
-	mmc_set_clock(host, card->ext_csd.hs_max_dtr);
 	/* Switch card to DDR with strobe bit */
 	val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE;
 	err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 static int mmc_select_hs200(struct mmc_card *card)
 {
 	struct mmc_host *host = card->host;
-	unsigned int old_timing, old_signal_voltage;
+	unsigned int old_timing, old_signal_voltage, old_clock;
 	int err = -EINVAL;
 	u8 val;
 				   false, true, MMC_CMD_RETRIES);
 		if (err)
 			goto err;
+		/*
+		 * Bump to HS timing and frequency. Some cards don't handle
+		 * SEND_STATUS reliably at the initial frequency.
+		 * NB: We can't move to full (HS200) speeds until after we've
+		 * successfully switched over.
+		 */
 		old_timing = host->ios.timing;
+		old_clock = host->ios.clock;
 		mmc_set_timing(host, MMC_TIMING_MMC_HS200);
+		mmc_set_clock(card->host, card->ext_csd.hs_max_dtr);
 		/*
 		 * For HS200, CRC errors are not a reliable way to know the
 		 * mmc_select_timing() assumes timing has not changed if
 		 * it is a switch error.
 		 */
-		if (err == -EBADMSG)
+		if (err == -EBADMSG) {
+			mmc_set_clock(host, old_clock);
 			mmc_set_timing(host, old_timing);
+		}
 	}
 err:
 	if (err) {

drivers/mmc/host/sdhci-msm.c+42−0

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	#include <linux/regulator/consumer.h>	17	#include <linux/regulator/consumer.h>
18	#include <linux/interconnect.h>	18	#include <linux/interconnect.h>
19	#include <linux/pinctrl/consumer.h>	19	#include <linux/pinctrl/consumer.h>
		20	#include <linux/reset.h>
20		21
21	#include "sdhci-pltfm.h"	22	#include "sdhci-pltfm.h"
22	#include "cqhci.h"	23	#include "cqhci.h"
@@ -2482,6 +2483,43 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev, · 2459 unmodified lines
2482	of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);	2483	of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2483	}	2484	}
2484		2485
		2486	static int sdhci_msm_gcc_reset(struct device dev, struct sdhci_host host)
		2487	{
		2488	struct reset_control *reset;
		2489	int ret = 0;
		2490
		2491	reset = reset_control_get_optional_exclusive(dev, NULL);
		2492	if (IS_ERR(reset))
		2493	return dev_err_probe(dev, PTR_ERR(reset),
		2494	"unable to acquire core_reset\n");
		2495
		2496	if (!reset)
		2497	return ret;
		2498
		2499	ret = reset_control_assert(reset);
		2500	if (ret) {
		2501	reset_control_put(reset);
		2502	return dev_err_probe(dev, ret, "core_reset assert failed\n");
		2503	}
		2504
		2505	/*
		2506	* The hardware requirement for delay between assert/deassert
		2507	* is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
		2508	* ~125us (4/32768). To be on the safe side add 200us delay.
		2509	*/
		2510	usleep_range(200, 210);
		2511
		2512	ret = reset_control_deassert(reset);
		2513	if (ret) {
		2514	reset_control_put(reset);
		2515	return dev_err_probe(dev, ret, "core_reset deassert failed\n");
		2516	}
		2517
		2518	usleep_range(200, 210);
		2519	reset_control_put(reset);
		2520
		2521	return ret;
		2522	}
2485		2523
2486	static int sdhci_msm_probe(struct platform_device *pdev)	2524	static int sdhci_msm_probe(struct platform_device *pdev)
2487	{	2525	{
@@ -2529,6 +2567,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 41 unmodified lines
2529		2567
2530	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;	2568	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2531		2569
		2570	ret = sdhci_msm_gcc_reset(&pdev->dev, host);
		2571	if (ret)
		2572	goto pltfm_free;
		2573
2532	/* Setup SDCC bus voter clock. */	2574	/* Setup SDCC bus voter clock. */
2533	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");	2575	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2534	if (!IS_ERR(msm_host->bus_clk)) {	2576	if (!IS_ERR(msm_host->bus_clk)) {

drivers/mmc/host/sunxi-mmc.c+3−2

 		pdes[i].buf_addr_ptr1 =
 			cpu_to_le32(sg_dma_address(&data->sg[i]) >>
 				    host->cfg->idma_des_shift);
-		pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
+		pdes[i].buf_addr_ptr2 =
-						    host->cfg->idma_des_shift);
+			cpu_to_le32(next_desc >>
+				    host->cfg->idma_des_shift);
 	}
 	pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);

drivers/mtd/nand/raw/mtk_ecc.c+8−4

 struct mtk_ecc_caps {
 	u32 err_mask;
+	u32 err_shift;
 	const u8 *ecc_strength;
 	const u32 *ecc_regs;
 	u8 num_ecc_strength;
 };
 static const u8 ecc_strength_mt7622[] = {
-	4, 6, 8, 10, 12, 14, 16
+	4, 6, 8, 10, 12
 };
 enum mtk_ecc_regs {
 	for (i = 0; i < sectors; i++) {
 		offset = (i >> 2) << 2;
 		err = readl(ecc->regs + ECC_DECENUM0 + offset);
-		err = err >> ((i % 4) * 8);
+		err = err >> ((i % 4) * ecc->caps->err_shift);
 		err &= ecc->caps->err_mask;
 		if (err == ecc->caps->err_mask) {
 			/* uncorrectable errors */
 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
 	.err_mask = 0x3f,
+	.err_shift = 8,
 	.ecc_strength = ecc_strength_mt2701,
 	.ecc_regs = mt2701_ecc_regs,
 	.num_ecc_strength = 20,
 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
 	.err_mask = 0x7f,
+	.err_shift = 8,
 	.ecc_strength = ecc_strength_mt2712,
 	.ecc_regs = mt2712_ecc_regs,
 	.num_ecc_strength = 23,
 };
 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-	.err_mask = 0x3f,
+	.err_mask = 0x1f,
+	.err_shift = 5,
 	.ecc_strength = ecc_strength_mt7622,
 	.ecc_regs = mt7622_ecc_regs,
-	.num_ecc_strength = 7,
+	.num_ecc_strength = 5,
 	.ecc_mode_shift = 4,
 	.parity_bits = 13,
 	.pg_irq_sel = 0,

drivers/mtd/nand/raw/qcom_nandc.c+13−11

 	ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
 	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
+	/* Free the initially allocated BAM transaction for reading the ONFI params */
+	if (nandc->props->is_bam)
+		free_bam_transaction(nandc);
 	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
 				     cwperpage);
+	/* Now allocate the BAM transaction based on updated max_cwperpage */
+	if (nandc->props->is_bam) {
+		nandc->bam_txn = alloc_bam_transaction(nandc);
+		if (!nandc->bam_txn) {
+			dev_err(nandc->dev,
+				"failed to allocate bam transaction\n");
+			return -ENOMEM;
+		}
+	}
 	/*
 	 * DATA_UD_BYTES varies based on whether the read/write command protects
 	 * spare data with ECC too. We protect spare data by default, so we set
 	if (ret)
 		return ret;
-	if (nandc->props->is_bam) {
-		free_bam_transaction(nandc);
-		nandc->bam_txn = alloc_bam_transaction(nandc);
-		if (!nandc->bam_txn) {
-			dev_err(nandc->dev,
-				"failed to allocate bam transaction\n");
-			nand_cleanup(chip);
-			return -ENOMEM;
-		}
-	}
 	ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
 	if (ret)
 		nand_cleanup(chip);

drivers/mtd/nand/raw/sh_flctl.c+8−6

 	dma_addr_t dma_addr;
 	dma_cookie_t cookie;
 	uint32_t reg;
-	int ret;
+	int ret = 0;
+	unsigned long time_left;
 	if (dir == DMA_FROM_DEVICE) {
 		chan = flctl->chan_fifo0_rx;
 		goto out;
 	}
-	ret =
+	time_left =
 	wait_for_completion_timeout(&flctl->dma_complete,
 				msecs_to_jiffies(3000));
-	if (ret <= 0) {
+	if (time_left == 0) {
 		dmaengine_terminate_all(chan);
 		dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
+		ret = -ETIMEDOUT;
 	}
 out:
 	dma_unmap_single(chan->device->dev, dma_addr, len, dir);
-	/* ret > 0 is success */
+	/* ret == 0 is success */
 	return ret;
 }
 	/* initiate DMA transfer */
 	if (flctl->chan_fifo0_rx && rlen >= 32 &&
-		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_FROM_DEVICE) > 0)
+		!flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_FROM_DEVICE))
 			goto convert;	/* DMA success */
 	/* do polling transfer */
 	/* initiate DMA transfer */
 	if (flctl->chan_fifo0_tx && rlen >= 32 &&
-		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_TO_DEVICE) > 0)
+		!flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_TO_DEVICE))
 			return;	/* DMA success */
 	/* do polling transfer */

drivers/net/can/grcan.c+24−22

 		.rxsize		= GRCAN_DEFAULT_BUFFER_SIZE,	\
 		}
-#define GRCAN_TXBUG_SAFE_GRLIB_VERSION	0x4100
+#define GRCAN_TXBUG_SAFE_GRLIB_VERSION	4100
 #define GRLIB_VERSION_MASK		0xffff
 /* GRCAN private data structure */
 struct grcan_priv {
 	struct can_priv can;	/* must be the first member */
 	struct net_device *dev;
+	struct device *ofdev_dev;
 	struct napi_struct napi;
 	struct grcan_registers __iomem *regs;	/* ioremap'ed registers */
 	struct grcan_priv *priv = netdev_priv(dev);
 	struct grcan_dma *dma = &priv->dma;
-	dma_free_coherent(&dev->dev, dma->base_size, dma->base_buf,
+	dma_free_coherent(priv->ofdev_dev, dma->base_size, dma->base_buf,
 			  dma->base_handle);
 	memset(dma, 0, sizeof(*dma));
 }
 	/* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
 	dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
-	dma->base_buf = dma_alloc_coherent(&dev->dev,
+	dma->base_buf = dma_alloc_coherent(priv->ofdev_dev,
 					   dma->base_size,
 					   &dma->base_handle,
 					   GFP_KERNEL);
 	priv->closing = true;
 	if (priv->need_txbug_workaround) {
+		spin_unlock_irqrestore(&priv->lock, flags);
 		del_timer_sync(&priv->hang_timer);
 		del_timer_sync(&priv->rr_timer);
+		spin_lock_irqsave(&priv->lock, flags);
 	}
 	netif_stop_queue(dev);
 	grcan_stop_hardware(dev);
 	return 0;
 }
-static int grcan_transmit_catch_up(struct net_device *dev, int budget)
+static void grcan_transmit_catch_up(struct net_device *dev)
 {
 	struct grcan_priv *priv = netdev_priv(dev);
 	unsigned long flags;
 	spin_lock_irqsave(&priv->lock, flags);
-	work_done = catch_up_echo_skb(dev, budget, true);
+	work_done = catch_up_echo_skb(dev, -1, true);
 	if (work_done) {
 		if (!priv->resetting && !priv->closing &&
 		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
 	}
 	spin_unlock_irqrestore(&priv->lock, flags);
-	return work_done;
 }
 static int grcan_receive(struct net_device *dev, int budget)
 	struct net_device *dev = priv->dev;
 	struct grcan_registers __iomem *regs = priv->regs;
 	unsigned long flags;
-	int tx_work_done, rx_work_done;
+	int work_done;
-	int rx_budget = budget / 2;
-	int tx_budget = budget - rx_budget;
-	/* Half of the budget for receiving messages */
+	work_done = grcan_receive(dev, budget);
-	rx_work_done = grcan_receive(dev, rx_budget);
-	/* Half of the budget for transmitting messages as that can trigger echo
+	grcan_transmit_catch_up(dev);
-	 * frames being received
-	 */
-	tx_work_done = grcan_transmit_catch_up(dev, tx_budget);
-	if (rx_work_done < rx_budget && tx_work_done < tx_budget) {
+	if (work_done < budget) {
 		napi_complete(napi);
 		/* Guarantee no interference with a running reset that otherwise
 		spin_unlock_irqrestore(&priv->lock, flags);
 	}
-	return rx_work_done + tx_work_done;
+	return work_done;
 }
 /* Work tx bug by waiting while for the risky situation to clear. If that fails,
 	memcpy(&priv->config, &grcan_module_config,
 	       sizeof(struct grcan_device_config));
 	priv->dev = dev;
+	priv->ofdev_dev = &ofdev->dev;
 	priv->regs = base;
 	priv->can.bittiming_const = &grcan_bittiming_const;
 	priv->can.do_set_bittiming = grcan_set_bittiming;
 static int grcan_probe(struct platform_device *ofdev)
 {
 	struct device_node *np = ofdev->dev.of_node;
+	struct device_node *sysid_parent;
 	u32 sysid, ambafreq;
 	int irq, err;
 	void __iomem *base;
 	/* Compare GRLIB version number with the first that does not
 	 * have the tx bug (see start_xmit)
 	 */
-	err = of_property_read_u32(np, "systemid", &sysid);
+	sysid_parent = of_find_node_by_path("/ambapp0");
-	if (!err && ((sysid & GRLIB_VERSION_MASK)
+	if (sysid_parent) {
-		     >= GRCAN_TXBUG_SAFE_GRLIB_VERSION))
+		of_node_get(sysid_parent);
-		txbug = false;
+		err = of_property_read_u32(sysid_parent, "systemid", &sysid);
+		if (!err && ((sysid & GRLIB_VERSION_MASK) >=
+			     GRCAN_TXBUG_SAFE_GRLIB_VERSION))
+			txbug = false;
+		of_node_put(sysid_parent);
+	}
 	err = of_property_read_u32(np, "freq", &ambafreq);
 	if (err) {

drivers/net/dsa/b53/b53_common.c+7−29

 	config->legacy_pre_march2020 = false;
 }
-int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
+static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
-			       struct phylink_link_state *state)
+						      int port,
+						      phy_interface_t interface)
 {
 	struct b53_device *dev = ds->priv;
-	int ret = -EOPNOTSUPP;
-	if ((phy_interface_mode_is_8023z(state->interface) ||
+	if (!dev->ops->phylink_mac_select_pcs)
-	     state->interface == PHY_INTERFACE_MODE_SGMII) &&
+		return NULL;
-	     dev->ops->serdes_link_state)
-		ret = dev->ops->serdes_link_state(dev, port, state);
-	return ret;
+	return dev->ops->phylink_mac_select_pcs(dev, port, interface);
 }
-EXPORT_SYMBOL(b53_phylink_mac_link_state);
 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
 			    unsigned int mode,
 			    const struct phylink_link_state *state)
 {
-	struct b53_device *dev = ds->priv;
-	if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED)
-		return;
-	if ((phy_interface_mode_is_8023z(state->interface) ||
-	     state->interface == PHY_INTERFACE_MODE_SGMII) &&
-	     dev->ops->serdes_config)
-		dev->ops->serdes_config(dev, port, mode, state);
 }
 EXPORT_SYMBOL(b53_phylink_mac_config);
-void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
-{
-	struct b53_device *dev = ds->priv;
-	if (dev->ops->serdes_an_restart)
-		dev->ops->serdes_an_restart(dev, port);
-}
-EXPORT_SYMBOL(b53_phylink_mac_an_restart);
 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
 			       unsigned int mode,
 			       phy_interface_t interface)
 	.phy_write		= b53_phy_write16,
 	.adjust_link		= b53_adjust_link,
 	.phylink_get_caps	= b53_phylink_get_caps,
-	.phylink_mac_link_state	= b53_phylink_mac_link_state,
+	.phylink_mac_select_pcs	= b53_phylink_mac_select_pcs,
 	.phylink_mac_config	= b53_phylink_mac_config,
-	.phylink_mac_an_restart	= b53_phylink_mac_an_restart,
 	.phylink_mac_link_down	= b53_phylink_mac_link_down,
 	.phylink_mac_link_up	= b53_phylink_mac_link_up,
 	.port_enable		= b53_enable_port,

drivers/net/dsa/b53/b53_priv.h+13−11

 #include <linux/kernel.h>
 #include <linux/mutex.h>
-#include <linux/phy.h>
+#include <linux/phylink.h>
 #include <linux/etherdevice.h>
 #include <net/dsa.h>
 struct b53_device;
 struct net_device;
-struct phylink_link_state;
 struct b53_io_ops {
 	int (*read8)(struct b53_device *dev, u8 page, u8 reg, u8 *value);
 	void (*irq_disable)(struct b53_device *dev, int port);
 	void (*phylink_get_caps)(struct b53_device *dev, int port,
 				 struct phylink_config *config);
+	struct phylink_pcs *(*phylink_mac_select_pcs)(struct b53_device *dev,
+						      int port,
+						      phy_interface_t interface);
 	u8 (*serdes_map_lane)(struct b53_device *dev, int port);
-	int (*serdes_link_state)(struct b53_device *dev, int port,
-				 struct phylink_link_state *state);
-	void (*serdes_config)(struct b53_device *dev, int port,
-			      unsigned int mode,
-			      const struct phylink_link_state *state);
-	void (*serdes_an_restart)(struct b53_device *dev, int port);
 	void (*serdes_link_set)(struct b53_device *dev, int port,
 				unsigned int mode, phy_interface_t interface,
 				bool link_up);
 	BCM7278_DEVICE_ID = 0x7278,
 };
+struct b53_pcs {
+	struct phylink_pcs pcs;
+	struct b53_device *dev;
+	u8 lane;
+};
 #define B53_N_PORTS	9
 #define B53_N_PORTS_25	6
+#define B53_N_PCS	2
 struct b53_port {
 	u16		vlan_ctl_mask;
 	bool vlan_enabled;
 	unsigned int num_ports;
 	struct b53_port *ports;
+	struct b53_pcs pcs[B53_N_PCS];
 };
 #define b53_for_each_port(dev, i) \
 		 struct netlink_ext_ack *extack);
 int b53_setup_devlink_resources(struct dsa_switch *ds);
 void b53_port_event(struct dsa_switch *ds, int port);
-int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
-			       struct phylink_link_state *state);
 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
 			    unsigned int mode,
 			    const struct phylink_link_state *state);
-void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port);
 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
 			       unsigned int mode,
 			       phy_interface_t interface);

drivers/net/dsa/b53/b53_serdes.c+51−23

 #include "b53_serdes.h"
 #include "b53_regs.h"
+static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs)
+{
+	return container_of(pcs, struct b53_pcs, pcs);
+}
 static void b53_serdes_write_blk(struct b53_device *dev, u8 offset, u16 block,
 				 u16 value)
 {
 	return b53_serdes_read_blk(dev, offset, block);
 }
-void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
+static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int mode,
-		       const struct phylink_link_state *state)
+			     phy_interface_t interface,
+			     const unsigned long *advertising,
+			     bool permit_pause_to_mac)
 {
-	u8 lane = b53_serdes_map_lane(dev, port);
+	struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
+	u8 lane = pcs_to_b53_pcs(pcs)->lane;
 	u16 reg;
-	if (lane == B53_INVALID_LANE)
-		return;
 	reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
 			      SERDES_DIGITAL_BLK);
-	if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
+	if (interface == PHY_INTERFACE_MODE_1000BASEX)
 		reg |= FIBER_MODE_1000X;
 	else
 		reg &= ~FIBER_MODE_1000X;
 	b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
 			 SERDES_DIGITAL_BLK, reg);
+	return 0;
 }
-EXPORT_SYMBOL(b53_serdes_config);
-void b53_serdes_an_restart(struct b53_device *dev, int port)
+static void b53_serdes_an_restart(struct phylink_pcs *pcs)
 {
-	u8 lane = b53_serdes_map_lane(dev, port);
+	struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
+	u8 lane = pcs_to_b53_pcs(pcs)->lane;
 	u16 reg;
-	if (lane == B53_INVALID_LANE)
-		return;
 	reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
 			      SERDES_MII_BLK);
 	reg |= BMCR_ANRESTART;
 	b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
 			 SERDES_MII_BLK, reg);
 }
-EXPORT_SYMBOL(b53_serdes_an_restart);
-int b53_serdes_link_state(struct b53_device *dev, int port,
+static void b53_serdes_get_state(struct phylink_pcs *pcs,
-			  struct phylink_link_state *state)
+				  struct phylink_link_state *state)
 {
-	u8 lane = b53_serdes_map_lane(dev, port);
+	struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
+	u8 lane = pcs_to_b53_pcs(pcs)->lane;
 	u16 dig, bmsr;
-	if (lane == B53_INVALID_LANE)
-		return 1;
 	dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS,
 			      SERDES_DIGITAL_BLK);
 	bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR),
 		state->pause |= MLO_PAUSE_RX;
 	if (dig & PAUSE_RESOLUTION_TX_SIDE)
 		state->pause |= MLO_PAUSE_TX;
-	return 0;
 }
-EXPORT_SYMBOL(b53_serdes_link_state);
 void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
 			 phy_interface_t interface, bool link_up)
 }
 EXPORT_SYMBOL(b53_serdes_link_set);
+static const struct phylink_pcs_ops b53_pcs_ops = {
+	.pcs_get_state = b53_serdes_get_state,
+	.pcs_config = b53_serdes_config,
+	.pcs_an_restart = b53_serdes_an_restart,
+};
 void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
 				 struct phylink_config *config)
 {
 }
 EXPORT_SYMBOL(b53_serdes_phylink_get_caps);
+struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
+						      int port,
+						      phy_interface_t interface)
+{
+	u8 lane = b53_serdes_map_lane(dev, port);
+	if (lane == B53_INVALID_LANE || lane >= B53_N_PCS ||
+	    !dev->pcs[lane].dev)
+		return NULL;
+	if (!phy_interface_mode_is_8023z(interface) &&
+	    interface != PHY_INTERFACE_MODE_SGMII)
+		return NULL;
+	return &dev->pcs[lane].pcs;
+}
+EXPORT_SYMBOL(b53_serdes_phylink_mac_select_pcs);
 int b53_serdes_init(struct b53_device *dev, int port)
 {
 	u8 lane = b53_serdes_map_lane(dev, port);
+	struct b53_pcs *pcs;
 	u16 id0, msb, lsb;
 	if (lane == B53_INVALID_LANE)
 		 (id0 >> SERDES_ID0_REV_NUM_SHIFT) & SERDES_ID0_REV_NUM_MASK,
 		 (u32)msb << 16 | lsb);
+	pcs = &dev->pcs[lane];
+	pcs->dev = dev;
+	pcs->lane = lane;
+	pcs->pcs.ops = &b53_pcs_ops;
 	return 0;
 }
 EXPORT_SYMBOL(b53_serdes_init);

drivers/net/dsa/b53/b53_serdes.h+3−6

 	return dev->ops->serdes_map_lane(dev, port);
 }
-int b53_serdes_get_link(struct b53_device *dev, int port);
-int b53_serdes_link_state(struct b53_device *dev, int port,
-			  struct phylink_link_state *state);
-void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
-		       const struct phylink_link_state *state);
-void b53_serdes_an_restart(struct b53_device *dev, int port);
 void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
 			 phy_interface_t interface, bool link_up);
+struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
+						      int port,
+						      phy_interface_t interface);
 void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
 				 struct phylink_config *config);
 #if IS_ENABLED(CONFIG_B53_SERDES)

drivers/net/dsa/b53/b53_srab.c+1−3

 	.irq_disable = b53_srab_irq_disable,
 	.phylink_get_caps = b53_srab_phylink_get_caps,
 #if IS_ENABLED(CONFIG_B53_SERDES)
+	.phylink_mac_select_pcs = b53_serdes_phylink_mac_select_pcs,
 	.serdes_map_lane = b53_srab_serdes_map_lane,
-	.serdes_link_state = b53_serdes_link_state,
-	.serdes_config = b53_serdes_config,
-	.serdes_an_restart = b53_serdes_an_restart,
 	.serdes_link_set = b53_serdes_link_set,
 #endif
 };

drivers/net/dsa/bcm_sf2.c+3−0

@@ -809,6 +809,9 @@ static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, · 808 unmodified lines
809	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);	809	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
810	u32 reg, offset;	810	u32 reg, offset;
811		811
		812	if (priv->wol_ports_mask & BIT(port))
		813	return;
		814
812	if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {	815	if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
813	if (priv->type == BCM4908_DEVICE_ID \|\|	816	if (priv->type == BCM4908_DEVICE_ID \|\|
814	priv->type == BCM7445_DEVICE_ID)	817	priv->type == BCM7445_DEVICE_ID)

drivers/net/dsa/lantiq_gswip.c+0−3

 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
-		/* Configure the RMII clock as output: */
-		miicfg |= GSWIP_MII_CFG_RMII_CLK;
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
 	case PHY_INTERFACE_MODE_RGMII_ID:

drivers/net/dsa/microchip/ksz9477.c+34−4

@@ -1021,14 +1021,32 @@ static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, · 1020 unmodified lines
1021	bool ingress, struct netlink_ext_ack *extack)	1021	bool ingress, struct netlink_ext_ack *extack)
1022	{	1022	{
1023	struct ksz_device *dev = ds->priv;	1023	struct ksz_device *dev = ds->priv;
		1024	u8 data;
		1025	int p;
		1026
		1027	/* Limit to one sniffer port
		1028	* Check if any of the port is already set for sniffing
		1029	* If yes, instruct the user to remove the previous entry & exit
		1030	*/
		1031	for (p = 0; p < dev->port_cnt; p++) {
		1032	/* Skip the current sniffing port */
		1033	if (p == mirror->to_local_port)
		1034	continue;
		1035
		1036	ksz_pread8(dev, p, P_MIRROR_CTRL, &data);
		1037
		1038	if (data & PORT_MIRROR_SNIFFER) {
		1039	NL_SET_ERR_MSG_MOD(extack,
		1040	"Sniffer port is already configured, delete existing rules & retry");
		1041	return -EBUSY;
		1042	}
		1043	}
1024		1044
1025	if (ingress)	1045	if (ingress)
1026	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);	1046	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1027	else	1047	else
1028	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);	1048	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1029		1049
1030	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1031
1032	/* configure mirror port */	1050	/* configure mirror port */
1033	ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,	1051	ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1034	PORT_MIRROR_SNIFFER, true);	1052	PORT_MIRROR_SNIFFER, true);
@@ -1042,16 +1060,28 @@ static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, · 7 unmodified lines
1042	struct dsa_mall_mirror_tc_entry *mirror)	1060	struct dsa_mall_mirror_tc_entry *mirror)
1043	{	1061	{
1044	struct ksz_device *dev = ds->priv;	1062	struct ksz_device *dev = ds->priv;
		1063	bool in_use = false;
1045	u8 data;	1064	u8 data;
		1065	int p;
1046		1066
1047	if (mirror->ingress)	1067	if (mirror->ingress)
1048	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);	1068	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1049	else	1069	else
1050	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);	1070	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1051		1071
1052	ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1053		1072
1054	if (!(data & (PORT_MIRROR_RX \| PORT_MIRROR_TX)))	1073	/* Check if any of the port is still referring to sniffer port */
		1074	for (p = 0; p < dev->port_cnt; p++) {
		1075	ksz_pread8(dev, p, P_MIRROR_CTRL, &data);
		1076
		1077	if ((data & (PORT_MIRROR_RX \| PORT_MIRROR_TX))) {
		1078	in_use = true;
		1079	break;
		1080	}
		1081	}
		1082
		1083	/* delete sniffing if there are no other mirroring rules */
		1084	if (!in_use)
1055	ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,	1085	ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1056	PORT_MIRROR_SNIFFER, false);	1086	PORT_MIRROR_SNIFFER, false);
1057	}	1087	}

drivers/net/dsa/mt7530.c+1−0

@@ -2229,6 +2229,7 @@ mt7530_setup(struct dsa_switch *ds) · 2228 unmodified lines
2229	ret = of_get_phy_mode(mac_np, &interface);	2229	ret = of_get_phy_mode(mac_np, &interface);
2230	if (ret && ret != -ENODEV) {	2230	if (ret && ret != -ENODEV) {
2231	of_node_put(mac_np);	2231	of_node_put(mac_np);
		2232	of_node_put(phy_node);
2232	return ret;	2233	return ret;
2233	}	2234	}
2234	id = of_mdio_parse_addr(ds->dev, phy_node);	2235	id = of_mdio_parse_addr(ds->dev, phy_node);

drivers/net/dsa/mv88e6xxx/port_hidden.c+3−2

@@ -40,8 +40,9 @@ int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip) · 39 unmodified lines
40	{	40	{
41	int bit = __bf_shf(MV88E6XXX_PORT_RESERVED_1A_BUSY);	41	int bit = __bf_shf(MV88E6XXX_PORT_RESERVED_1A_BUSY);
42		42
43	return mv88e6xxx_wait_bit(chip, MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT,	43	return mv88e6xxx_port_wait_bit(chip,
44	MV88E6XXX_PORT_RESERVED_1A, bit, 0);	44	MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT,
		45	MV88E6XXX_PORT_RESERVED_1A, bit, 0);
45	}	46	}
46		47
47	int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,	48	int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,

drivers/net/dsa/ocelot/felix.c+6−1

 {
 	struct ocelot *ocelot = ds->priv;
 	struct felix *felix = ocelot_to_felix(ocelot);
+	struct ocelot_vcap_block *block_vcap_is2;
 	struct ocelot_vcap_filter *trap;
 	enum ocelot_mask_mode mask_mode;
 	unsigned long port_mask;
 	/* We are sure that "cpu" was found, otherwise
 	 * dsa_tree_setup_default_cpu() would have failed earlier.
 	 */
+	block_vcap_is2 = &ocelot->block[VCAP_IS2];
 	/* Make sure all traps are set up for that destination */
-	list_for_each_entry(trap, &ocelot->traps, trap_list) {
+	list_for_each_entry(trap, &block_vcap_is2->rules, list) {
+		if (!trap->is_trap)
+			continue;
 		/* Figure out the current trapping destination */
 		if (using_tag_8021q) {
 			/* Redirect to the tag_8021q CPU port. If timestamps

drivers/net/dsa/realtek/realtek-mdio.c+0−1

@@ -267,7 +267,6 @@ static const struct of_device_id realtek_mdio_of_match[] = { · 266 unmodified lines
267	#endif	267	#endif
268	#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB)	268	#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB)
269	{ .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, },	269	{ .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, },
270	{ .compatible = "realtek,rtl8367s", .data = &rtl8365mb_variant, },
271	#endif	270	#endif
272	{ /* sentinel */ },	271	{ /* sentinel */ },
273	};	272	};

drivers/net/dsa/realtek/realtek-smi.c+0−4

 		.compatible = "realtek,rtl8365mb",
 		.data = &rtl8365mb_variant,
 	},
-	{
-		.compatible = "realtek,rtl8367s",
-		.data = &rtl8365mb_variant,
-	},
 #endif
 	{ /* sentinel */ },
 };

drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c+2−2

@@ -449,7 +449,7 @@ static int aq_pm_freeze(struct device *dev) · 448 unmodified lines
449		449
450	static int aq_pm_suspend_poweroff(struct device *dev)	450	static int aq_pm_suspend_poweroff(struct device *dev)
451	{	451	{
452	return aq_suspend_common(dev, false);	452	return aq_suspend_common(dev, true);
453	}	453	}
454		454
455	static int aq_pm_thaw(struct device *dev)	455	static int aq_pm_thaw(struct device *dev)
@@ -459,7 +459,7 @@ static int aq_pm_thaw(struct device *dev) · 3 unmodified lines
459		459
460	static int aq_pm_resume_restore(struct device *dev)	460	static int aq_pm_resume_restore(struct device *dev)
461	{	461	{
462	return atl_resume_common(dev, false);	462	return atl_resume_common(dev, true);
463	}	463	}
464		464
465	static const struct dev_pm_ops aq_pm_ops = {	465	static const struct dev_pm_ops aq_pm_ops = {

drivers/net/ethernet/aquantia/atlantic/aq_ring.c+11−9

 		     int budget)
 {
 	struct net_device *ndev = aq_nic_get_ndev(self->aq_nic);
-	bool is_rsc_completed = true;
 	int err = 0;
 	for (; (self->sw_head != self->hw_head) && budget;
 			continue;
 		if (!buff->is_eop) {
+			unsigned int frag_cnt = 0U;
 			buff_ = buff;
 			do {
+				bool is_rsc_completed = true;
 				if (buff_->next >= self->size) {
 					err = -EIO;
 					goto err_exit;
 				}
+				frag_cnt++;
 				next_ = buff_->next,
 				buff_ = &self->buff_ring[next_];
 				is_rsc_completed =
 							    next_,
 							    self->hw_head);
-				if (unlikely(!is_rsc_completed))
+				if (unlikely(!is_rsc_completed) ||
-					break;
+						frag_cnt > MAX_SKB_FRAGS) {
+					err = 0;
+					goto err_exit;
+				}
 				buff->is_error |= buff_->is_error;
 				buff->is_cso_err |= buff_->is_cso_err;
 			} while (!buff_->is_eop);
-			if (!is_rsc_completed) {
-				err = 0;
-				goto err_exit;
-			}
 			if (buff->is_error ||
 			    (buff->is_lro && buff->is_cso_err)) {
 				buff_ = buff;
 		       ALIGN(hdr_len, sizeof(long)));
 		if (buff->len - hdr_len > 0) {
-			skb_add_rx_frag(skb, 0, buff->rxdata.page,
+			skb_add_rx_frag(skb, i++, buff->rxdata.page,
 					buff->rxdata.pg_off + hdr_len,
 					buff->len - hdr_len,
 					AQ_CFG_RX_FRAME_MAX);
 		if (!buff->is_eop) {
 			buff_ = buff;
-			i = 1U;
 			do {
 				next_ = buff_->next;
 				buff_ = &self->buff_ring[next_];

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c+7−0

@@ -889,6 +889,13 @@ int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, · 888 unmodified lines
889	err = -ENXIO;	889	err = -ENXIO;
890	goto err_exit;	890	goto err_exit;
891	}	891	}
		892
		893	/* Validate that the new hw_head_ is reasonable. */
		894	if (hw_head_ >= ring->size) {
		895	err = -ENXIO;
		896	goto err_exit;
		897	}
		898
892	ring->hw_head = hw_head_;	899	ring->hw_head = hw_head_;
893	err = aq_hw_err_from_flags(self);	900	err = aq_hw_err_from_flags(self);
894		901

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c+5−4

 	/* Stop Tx */
 	bnx2x_tx_disable(bp);
-	/* Delete all NAPI objects */
-	bnx2x_del_all_napi(bp);
-	if (CNIC_LOADED(bp))
-		bnx2x_del_all_napi_cnic(bp);
 	netdev_reset_tc(bp->dev);
 	del_timer_sync(&bp->timer);
 		bnx2x_drain_tx_queues(bp);
 		bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
 		bnx2x_netif_stop(bp, 1);
+		bnx2x_del_all_napi(bp);
+		if (CNIC_LOADED(bp))
+			bnx2x_del_all_napi_cnic(bp);
 		bnx2x_free_irq(bp);
 		/* Report UNLOAD_DONE to MCP */

drivers/net/ethernet/broadcom/bnxt/bnxt.c+8−5

@@ -2707,6 +2707,10 @@ static int bnxt_poll_p5(struct napi_struct *napi, int budget) · 2706 unmodified lines
2707	u32 idx = le32_to_cpu(nqcmp->cq_handle_low);	2707	u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2708	struct bnxt_cp_ring_info *cpr2;	2708	struct bnxt_cp_ring_info *cpr2;
2709		2709
		2710	/* No more budget for RX work */
		2711	if (budget && work_done >= budget && idx == BNXT_RX_HDL)
		2712	break;
		2713
2710	cpr2 = cpr->cp_ring_arr[idx];	2714	cpr2 = cpr->cp_ring_arr[idx];
2711	work_done += __bnxt_poll_work(bp, cpr2,	2715	work_done += __bnxt_poll_work(bp, cpr2,
2712	budget - work_done);	2716	budget - work_done);
@@ -10983,7 +10987,7 @@ static bool bnxt_rfs_capable(struct bnxt *bp) · 8270 unmodified lines
10983		10987
10984	if (bp->flags & BNXT_FLAG_CHIP_P5)	10988	if (bp->flags & BNXT_FLAG_CHIP_P5)
10985	return bnxt_rfs_supported(bp);	10989	return bnxt_rfs_supported(bp);
10986	if (!(bp->flags & BNXT_FLAG_MSIX_CAP) \|\| !bnxt_can_reserve_rings(bp))	10990	if (!(bp->flags & BNXT_FLAG_MSIX_CAP) \|\| !bnxt_can_reserve_rings(bp) \|\| !bp->rx_nr_rings)
10987	return false;	10991	return false;
10988		10992
10989	vnics = 1 + bp->rx_nr_rings;	10993	vnics = 1 + bp->rx_nr_rings;
@@ -13234,10 +13238,9 @@ static int bnxt_init_dflt_ring_mode(struct bnxt *bp) · 2244 unmodified lines
13234	goto init_dflt_ring_err;	13238	goto init_dflt_ring_err;
13235		13239
13236	bp->tx_nr_rings_per_tc = bp->tx_nr_rings;	13240	bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13237	if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {	13241
13238	bp->flags \|= BNXT_FLAG_RFS;	13242	bnxt_set_dflt_rfs(bp);
13239	bp->dev->features \|= NETIF_F_NTUPLE;	13243
13240	}
13241	init_dflt_ring_err:	13244	init_dflt_ring_err:
13242	bnxt_ulp_irq_restart(bp, rc);	13245	bnxt_ulp_irq_restart(bp, rc);
13243	return rc;	13246	return rc;

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c+7−8

 	if (rc)
 		return rc;
-	if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
-		bnxt_ptp_timecounter_init(bp, false);
-		rc = bnxt_ptp_init_rtc(bp, phc_cfg);
-		if (rc)
-			goto out;
-	}
 	if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
 		return 0;
 	atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
 	spin_lock_init(&ptp->ptp_lock);
-	if (!(bp->fw_cap & BNXT_FW_CAP_PTP_RTC))
+	if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
+		bnxt_ptp_timecounter_init(bp, false);
+		rc = bnxt_ptp_init_rtc(bp, phc_cfg);
+		if (rc)
+			goto out;
+	} else {
 		bnxt_ptp_timecounter_init(bp, true);
+	}
 	ptp->ptp_info = bnxt_ptp_caps;
 	if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {

drivers/net/ethernet/broadcom/genet/bcmgenet.c+11−0

 	return skb;
 }
+static void bcmgenet_hide_tsb(struct sk_buff *skb)
+{
+	__skb_pull(skb, sizeof(struct status_64));
+}
 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct bcmgenet_priv *priv = netdev_priv(dev);
 	}
 	GENET_CB(skb)->last_cb = tx_cb_ptr;
+	bcmgenet_hide_tsb(skb);
 	skb_tx_timestamp(skb);
 	/* Decrement total BD count and advance our write pointer */
 		goto err;
 	}
 	priv->wol_irq = platform_get_irq_optional(pdev, 2);
+	if (priv->wol_irq == -EPROBE_DEFER) {
+		err = priv->wol_irq;
+		goto err;
+	}
 	priv->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(priv->base)) {

drivers/net/ethernet/cavium/thunder/nic_main.c+8−8

@@ -59,7 +59,7 @@ struct nicpf { · 58 unmodified lines
59		59
60	/* MSI-X */	60	/* MSI-X */
61	u8 num_vec;	61	u8 num_vec;
62	bool irq_allocated[NIC_PF_MSIX_VECTORS];	62	unsigned int irq_allocated[NIC_PF_MSIX_VECTORS];
63	char irq_name[NIC_PF_MSIX_VECTORS][20];	63	char irq_name[NIC_PF_MSIX_VECTORS][20];
64	};	64	};
65		65
@@ -1150,7 +1150,7 @@ static irqreturn_t nic_mbx_intr_handler(int irq, void *nic_irq) · 1084 unmodified lines
1150	u64 intr;	1150	u64 intr;
1151	u8 vf;	1151	u8 vf;
1152		1152
1153	if (irq == pci_irq_vector(nic->pdev, NIC_PF_INTR_ID_MBOX0))	1153	if (irq == nic->irq_allocated[NIC_PF_INTR_ID_MBOX0])
1154	mbx = 0;	1154	mbx = 0;
1155	else	1155	else
1156	mbx = 1;	1156	mbx = 1;
@@ -1176,14 +1176,14 @@ static void nic_free_all_interrupts(struct nicpf *nic) · 19 unmodified lines
1176		1176
1177	for (irq = 0; irq < nic->num_vec; irq++) {	1177	for (irq = 0; irq < nic->num_vec; irq++) {
1178	if (nic->irq_allocated[irq])	1178	if (nic->irq_allocated[irq])
1179	free_irq(pci_irq_vector(nic->pdev, irq), nic);	1179	free_irq(nic->irq_allocated[irq], nic);
1180	nic->irq_allocated[irq] = false;	1180	nic->irq_allocated[irq] = 0;
1181	}	1181	}
1182	}	1182	}
1183		1183
1184	static int nic_register_interrupts(struct nicpf *nic)	1184	static int nic_register_interrupts(struct nicpf *nic)
1185	{	1185	{
1186	int i, ret;	1186	int i, ret, irq;
1187	nic->num_vec = pci_msix_vec_count(nic->pdev);	1187	nic->num_vec = pci_msix_vec_count(nic->pdev);
1188		1188
1189	/* Enable MSI-X */	1189	/* Enable MSI-X */
@@ -1201,13 +1201,13 @@ static int nic_register_interrupts(struct nicpf *nic) · 11 unmodified lines
1201	sprintf(nic->irq_name[i],	1201	sprintf(nic->irq_name[i],
1202	"NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0));	1202	"NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0));
1203		1203
1204	ret = request_irq(pci_irq_vector(nic->pdev, i),	1204	irq = pci_irq_vector(nic->pdev, i);
1205	nic_mbx_intr_handler, 0,	1205	ret = request_irq(irq, nic_mbx_intr_handler, 0,
1206	nic->irq_name[i], nic);	1206	nic->irq_name[i], nic);
1207	if (ret)	1207	if (ret)
1208	goto fail;	1208	goto fail;
1209		1209
1210	nic->irq_allocated[i] = true;	1210	nic->irq_allocated[i] = irq;
1211	}	1211	}
1212		1212
1213	/* Enable mailbox interrupt */	1213	/* Enable mailbox interrupt */

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c+5−5

@@ -2793,14 +2793,14 @@ int t4_get_raw_vpd_params(struct adapter adapter, struct vpd_params p) · 2792 unmodified lines
2793	goto out;	2793	goto out;
2794	na = ret;	2794	na = ret;
2795		2795
2796	memcpy(p->id, vpd + id, min_t(int, id_len, ID_LEN));	2796	memcpy(p->id, vpd + id, min_t(unsigned int, id_len, ID_LEN));
2797	strim(p->id);	2797	strim(p->id);
2798	memcpy(p->sn, vpd + sn, min_t(int, sn_len, SERNUM_LEN));	2798	memcpy(p->sn, vpd + sn, min_t(unsigned int, sn_len, SERNUM_LEN));
2799	strim(p->sn);	2799	strim(p->sn);
2800	memcpy(p->pn, vpd + pn, min_t(int, pn_len, PN_LEN));	2800	memcpy(p->pn, vpd + pn, min_t(unsigned int, pn_len, PN_LEN));
2801	strim(p->pn);	2801	strim(p->pn);
2802	memcpy(p->na, vpd + na, min_t(int, na_len, MACADDR_LEN));	2802	memcpy(p->na, vpd + na, min_t(unsigned int, na_len, MACADDR_LEN));
2803	strim((char *)p->na);	2803	strim(p->na);
2804		2804
2805	out:	2805	out:
2806	vfree(vpd);	2806	vfree(vpd);

drivers/net/ethernet/dec/tulip/tulip_core.c+4−1

 	/* alloc_etherdev ensures aligned and zeroed private structures */
 	dev = alloc_etherdev (sizeof (*tp));
-	if (!dev)
+	if (!dev) {
+		pci_disable_device(pdev);
 		return -ENOMEM;
+	}
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
 err_out_free_netdev:
 	free_netdev (dev);
+	pci_disable_device(pdev);
 	return -ENODEV;
 }

drivers/net/ethernet/freescale/enetc/enetc_qos.c+0−4

 	if (tc < 0 || tc >= priv->num_tx_rings)
 		return -EINVAL;
-	/* Do not support TXSTART and TX CSUM offload simutaniously */
-	if (ndev->features & NETIF_F_CSUM_MASK)
-		return -EBUSY;
 	/* TSD and Qbv are mutually exclusive in hardware */
 	if (enetc_rd(&priv->si->hw, ENETC_QBV_PTGCR_OFFSET) & ENETC_QBV_TGE)
 		return -EBUSY;

drivers/net/ethernet/freescale/fec_main.c+1−1

@@ -3731,7 +3731,7 @@ static int fec_enet_init_stop_mode(struct fec_enet_private *fep, · 3730 unmodified lines
3731	ARRAY_SIZE(out_val));	3731	ARRAY_SIZE(out_val));
3732	if (ret) {	3732	if (ret) {
3733	dev_dbg(&fep->pdev->dev, "no stop mode property\n");	3733	dev_dbg(&fep->pdev->dev, "no stop mode property\n");
3734	return ret;	3734	goto out;
3735	}	3735	}
3736		3736
3737	fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);	3737	fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c+5−1

 	device_for_each_child_node(dsaf_dev->dev, child) {
 		ret = fwnode_property_read_u32(child, "reg", &port_id);
 		if (ret) {
+			fwnode_handle_put(child);
 			dev_err(dsaf_dev->dev,
 				"get reg fail, ret=%d!\n", ret);
 			return ret;
 		}
 		if (port_id >= max_port_num) {
+			fwnode_handle_put(child);
 			dev_err(dsaf_dev->dev,
 				"reg(%u) out of range!\n", port_id);
 			return -EINVAL;
 		}
 		mac_cb = devm_kzalloc(dsaf_dev->dev, sizeof(*mac_cb),
 				      GFP_KERNEL);
-		if (!mac_cb)
+		if (!mac_cb) {
+			fwnode_handle_put(child);
 			return -ENOMEM;
+		}
 		mac_cb->fw_port = child;
 		mac_cb->mac_id = (u8)port_id;
 		dsaf_dev->mac_cb[port_id] = mac_cb;

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c+2−2

@@ -75,7 +75,7 @@ int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, · 74 unmodified lines
75	ret = hclge_comm_cmd_send(hw, &desc, 1);	75	ret = hclge_comm_cmd_send(hw, &desc, 1);
76	if (ret) {	76	if (ret) {
77	dev_err(&hw->cmq.csq.pdev->dev,	77	dev_err(&hw->cmq.csq.pdev->dev,
78	"failed to get tqp stat, ret = %d, tx = %u.\n",	78	"failed to get tqp stat, ret = %d, rx = %u.\n",
79	ret, i);	79	ret, i);
80	return ret;	80	return ret;
81	}	81	}
@@ -89,7 +89,7 @@ int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, · 7 unmodified lines
89	ret = hclge_comm_cmd_send(hw, &desc, 1);	89	ret = hclge_comm_cmd_send(hw, &desc, 1);
90	if (ret) {	90	if (ret) {
91	dev_err(&hw->cmq.csq.pdev->dev,	91	dev_err(&hw->cmq.csq.pdev->dev,
92	"failed to get tqp stat, ret = %d, rx = %u.\n",	92	"failed to get tqp stat, ret = %d, tx = %u.\n",
93	ret, i);	93	ret, i);
94	return ret;	94	return ret;
95	}	95	}

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c+42−42

@@ -562,12 +562,12 @@ static void hns3_dbg_tx_spare_info(struct hns3_enet_ring ring, char buf, · 561 unmodified lines
562		562
563	for (i = 0; i < ring_num; i++) {	563	for (i = 0; i < ring_num; i++) {
564	j = 0;	564	j = 0;
565	sprintf(result[j++], "%8u", i);	565	sprintf(result[j++], "%u", i);
566	sprintf(result[j++], "%9u", ring->tx_copybreak);	566	sprintf(result[j++], "%u", ring->tx_copybreak);
567	sprintf(result[j++], "%3u", tx_spare->len);	567	sprintf(result[j++], "%u", tx_spare->len);
568	sprintf(result[j++], "%3u", tx_spare->next_to_use);	568	sprintf(result[j++], "%u", tx_spare->next_to_use);
569	sprintf(result[j++], "%3u", tx_spare->next_to_clean);	569	sprintf(result[j++], "%u", tx_spare->next_to_clean);
570	sprintf(result[j++], "%3u", tx_spare->last_to_clean);	570	sprintf(result[j++], "%u", tx_spare->last_to_clean);
571	sprintf(result[j++], "%pad", &tx_spare->dma);	571	sprintf(result[j++], "%pad", &tx_spare->dma);
572	hns3_dbg_fill_content(content, sizeof(content),	572	hns3_dbg_fill_content(content, sizeof(content),
573	tx_spare_info_items,	573	tx_spare_info_items,
@@ -598,35 +598,35 @@ static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, · 24 unmodified lines
598	u32 base_add_l, base_add_h;	598	u32 base_add_l, base_add_h;
599	u32 j = 0;	599	u32 j = 0;
600		600
601	sprintf(result[j++], "%8u", index);	601	sprintf(result[j++], "%u", index);
602		602
603	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	603	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
604	HNS3_RING_RX_RING_BD_NUM_REG));	604	HNS3_RING_RX_RING_BD_NUM_REG));
605		605
606	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	606	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
607	HNS3_RING_RX_RING_BD_LEN_REG));	607	HNS3_RING_RX_RING_BD_LEN_REG));
608		608
609	sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +	609	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
610	HNS3_RING_RX_RING_TAIL_REG));	610	HNS3_RING_RX_RING_TAIL_REG));
611		611
612	sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +	612	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
613	HNS3_RING_RX_RING_HEAD_REG));	613	HNS3_RING_RX_RING_HEAD_REG));
614		614
615	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	615	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
616	HNS3_RING_RX_RING_FBDNUM_REG));	616	HNS3_RING_RX_RING_FBDNUM_REG));
617		617
618	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	618	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
619	HNS3_RING_RX_RING_PKTNUM_RECORD_REG));	619	HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
620	sprintf(result[j++], "%9u", ring->rx_copybreak);	620	sprintf(result[j++], "%u", ring->rx_copybreak);
621		621
622	sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +	622	sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
623	HNS3_RING_EN_REG) ? "on" : "off");	623	HNS3_RING_EN_REG) ? "on" : "off");
624		624
625	if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))	625	if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
626	sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base +	626	sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
627	HNS3_RING_RX_EN_REG) ? "on" : "off");	627	HNS3_RING_RX_EN_REG) ? "on" : "off");
628	else	628	else
629	sprintf(result[j++], "%10s", "NA");	629	sprintf(result[j++], "%s", "NA");
630		630
631	base_add_h = readl_relaxed(ring->tqp->io_base +	631	base_add_h = readl_relaxed(ring->tqp->io_base +
632	HNS3_RING_RX_RING_BASEADDR_H_REG);	632	HNS3_RING_RX_RING_BASEADDR_H_REG);
@@ -700,36 +700,36 @@ static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, · 67 unmodified lines
700	u32 base_add_l, base_add_h;	700	u32 base_add_l, base_add_h;
701	u32 j = 0;	701	u32 j = 0;
702		702
703	sprintf(result[j++], "%8u", index);	703	sprintf(result[j++], "%u", index);
704	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	704	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
705	HNS3_RING_TX_RING_BD_NUM_REG));	705	HNS3_RING_TX_RING_BD_NUM_REG));
706		706
707	sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base +	707	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
708	HNS3_RING_TX_RING_TC_REG));	708	HNS3_RING_TX_RING_TC_REG));
709		709
710	sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +	710	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
711	HNS3_RING_TX_RING_TAIL_REG));	711	HNS3_RING_TX_RING_TAIL_REG));
712		712
713	sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +	713	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
714	HNS3_RING_TX_RING_HEAD_REG));	714	HNS3_RING_TX_RING_HEAD_REG));
715		715
716	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	716	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
717	HNS3_RING_TX_RING_FBDNUM_REG));	717	HNS3_RING_TX_RING_FBDNUM_REG));
718		718
719	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	719	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
720	HNS3_RING_TX_RING_OFFSET_REG));	720	HNS3_RING_TX_RING_OFFSET_REG));
721		721
722	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +	722	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
723	HNS3_RING_TX_RING_PKTNUM_RECORD_REG));	723	HNS3_RING_TX_RING_PKTNUM_RECORD_REG));
724		724
725	sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +	725	sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
726	HNS3_RING_EN_REG) ? "on" : "off");	726	HNS3_RING_EN_REG) ? "on" : "off");
727		727
728	if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))	728	if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
729	sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base +	729	sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
730	HNS3_RING_TX_EN_REG) ? "on" : "off");	730	HNS3_RING_TX_EN_REG) ? "on" : "off");
731	else	731	else
732	sprintf(result[j++], "%10s", "NA");	732	sprintf(result[j++], "%s", "NA");
733		733
734	base_add_h = readl_relaxed(ring->tqp->io_base +	734	base_add_h = readl_relaxed(ring->tqp->io_base +
735	HNS3_RING_TX_RING_BASEADDR_H_REG);	735	HNS3_RING_TX_RING_BASEADDR_H_REG);
@@ -848,15 +848,15 @@ static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, · 112 unmodified lines
848	{	848	{
849	unsigned int j = 0;	849	unsigned int j = 0;
850		850
851	sprintf(result[j++], "%5d", idx);	851	sprintf(result[j++], "%d", idx);
852	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info));	852	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info));
853	sprintf(result[j++], "%7u", le16_to_cpu(desc->rx.pkt_len));	853	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len));
854	sprintf(result[j++], "%4u", le16_to_cpu(desc->rx.size));	854	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size));
855	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash));	855	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash));
856	sprintf(result[j++], "%5u", le16_to_cpu(desc->rx.fd_id));	856	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id));
857	sprintf(result[j++], "%8u", le16_to_cpu(desc->rx.vlan_tag));	857	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag));
858	sprintf(result[j++], "%15u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb));	858	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb));
859	sprintf(result[j++], "%11u", le16_to_cpu(desc->rx.ot_vlan_tag));	859	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag));
860	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info));	860	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info));
861	if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {	861	if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
862	u32 ol_info = le32_to_cpu(desc->rx.ol_info);	862	u32 ol_info = le32_to_cpu(desc->rx.ol_info);
@@ -930,19 +930,19 @@ static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv, · 67 unmodified lines
930	{	930	{
931	unsigned int j = 0;	931	unsigned int j = 0;
932		932
933	sprintf(result[j++], "%6d", idx);	933	sprintf(result[j++], "%d", idx);
934	sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr));	934	sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr));
935	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.vlan_tag));	935	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag));
936	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.send_size));	936	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size));
937	sprintf(result[j++], "%#x",	937	sprintf(result[j++], "%#x",
938	le32_to_cpu(desc->tx.type_cs_vlan_tso_len));	938	le32_to_cpu(desc->tx.type_cs_vlan_tso_len));
939	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.outer_vlan_tag));	939	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag));
940	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv));	940	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv));
941	sprintf(result[j++], "%10u",	941	sprintf(result[j++], "%u",
942	le32_to_cpu(desc->tx.ol_type_vlan_len_msec));	942	le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
943	sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs));	943	sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs));
944	sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));	944	sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
945	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum));	945	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum));
946	}	946	}
947		947
948	static int hns3_dbg_tx_bd_info(struct hns3_dbg_data d, char buf, int len)	948	static int hns3_dbg_tx_bd_info(struct hns3_dbg_data d, char buf, int len)

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c+9−0

 		set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
 }
+static void hns3_state_uninit(struct hnae3_handle *handle)
+{
+	struct hns3_nic_priv *priv  = handle->priv;
+	clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
+}
 static int hns3_client_init(struct hnae3_handle *handle)
 {
 	struct pci_dev *pdev = handle->pdev;
 	return ret;
 out_reg_netdev_fail:
+	hns3_state_uninit(handle);
 	hns3_dbg_uninit(handle);
+	hns3_client_stop(handle);
 out_client_start:
 	hns3_free_rx_cpu_rmap(netdev);
 	hns3_nic_uninit_irq(priv);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c+20−11

 	enum hclge_comm_cmd_status status;
 	struct hclge_desc desc;
+	if (msg_len > HCLGE_MBX_MAX_MSG_SIZE) {
+		dev_err(&hdev->pdev->dev,
+			"msg data length(=%u) exceeds maximum(=%u)\n",
+			msg_len, HCLGE_MBX_MAX_MSG_SIZE);
+		return -EMSGSIZE;
+	}
 	resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data;
 	hclge_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_PF_TO_VF, false);
 	ring_num = req->msg.ring_num;
 	if (ring_num > HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM)
-		return -ENOMEM;
+		return -EINVAL;
 	for (i = 0; i < ring_num; i++) {
 		if (req->msg.param[i].tqp_index >= vport->nic.kinfo.rss_size) {
 	return hclge_set_vport_mtu(vport, mtu);
 }
-static void hclge_get_queue_id_in_pf(struct hclge_vport *vport,
+static int hclge_get_queue_id_in_pf(struct hclge_vport *vport,
-				     struct hclge_mbx_vf_to_pf_cmd *mbx_req,
+				    struct hclge_mbx_vf_to_pf_cmd *mbx_req,
-				     struct hclge_respond_to_vf_msg *resp_msg)
+				    struct hclge_respond_to_vf_msg *resp_msg)
 {
 	struct hnae3_handle *handle = &vport->nic;
 	struct hclge_dev *hdev = vport->back;
 	if (queue_id >= handle->kinfo.num_tqps) {
 		dev_err(&hdev->pdev->dev, "Invalid queue id(%u) from VF %u\n",
 			queue_id, mbx_req->mbx_src_vfid);
-		return;
+		return -EINVAL;
 	}
 	qid_in_pf = hclge_covert_handle_qid_global(&vport->nic, queue_id);
 	memcpy(resp_msg->data, &qid_in_pf, sizeof(qid_in_pf));
 	resp_msg->len = sizeof(qid_in_pf);
+	return 0;
 }
-static void hclge_get_rss_key(struct hclge_vport *vport,
+static int hclge_get_rss_key(struct hclge_vport *vport,
-			      struct hclge_mbx_vf_to_pf_cmd *mbx_req,
+			     struct hclge_mbx_vf_to_pf_cmd *mbx_req,
-			      struct hclge_respond_to_vf_msg *resp_msg)
+			     struct hclge_respond_to_vf_msg *resp_msg)
 {
 #define HCLGE_RSS_MBX_RESP_LEN	8
 	struct hclge_dev *hdev = vport->back;
 		dev_warn(&hdev->pdev->dev,
 			 "failed to get the rss hash key, the index(%u) invalid !\n",
 			 index);
-		return;
+		return -EINVAL;
 	}
 	memcpy(resp_msg->data,
 	       &rss_cfg->rss_hash_key[index * HCLGE_RSS_MBX_RESP_LEN],
 	       HCLGE_RSS_MBX_RESP_LEN);
 	resp_msg->len = HCLGE_RSS_MBX_RESP_LEN;
+	return 0;
 }
 static void hclge_link_fail_parse(struct hclge_dev *hdev, u8 link_fail_code)
 					"VF fail(%d) to set mtu\n", ret);
 			break;
 		case HCLGE_MBX_GET_QID_IN_PF:
-			hclge_get_queue_id_in_pf(vport, req, &resp_msg);
+			ret = hclge_get_queue_id_in_pf(vport, req, &resp_msg);
 			break;
 		case HCLGE_MBX_GET_RSS_KEY:
-			hclge_get_rss_key(vport, req, &resp_msg);
+			ret = hclge_get_rss_key(vport, req, &resp_msg);
 			break;
 		case HCLGE_MBX_GET_LINK_MODE:
 			hclge_get_link_mode(vport, req);

drivers/net/ethernet/huawei/hinic/hinic_hw_wq.c+5−2

 	/* If we only have one page, still need to get shadown wqe when
 	 * wqe rolling-over page
 	 */
-	if (curr_pg != end_pg || MASKED_WQE_IDX(wq, end_prod_idx) < *prod_idx) {
+	if (curr_pg != end_pg || end_prod_idx < *prod_idx) {
 		void *shadow_addr = &wq->shadow_wqe[curr_pg * wq->max_wqe_size];
 		copy_wqe_to_shadow(wq, shadow_addr, num_wqebbs, *prod_idx);
 	*cons_idx = curr_cons_idx;
-	if (curr_pg != end_pg) {
+	/* If we only have one page, still need to get shadown wqe when
+	 * wqe rolling-over page
+	 */
+	if (curr_pg != end_pg || end_cons_idx < curr_cons_idx) {
 		void *shadow_addr = &wq->shadow_wqe[curr_pg * wq->max_wqe_size];
 		copy_wqe_to_shadow(wq, shadow_addr, num_wqebbs, *cons_idx);

drivers/net/ethernet/ibm/ibmvnic.c+35−94

 {
 	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
-	if (adapter->priv_flags & IBMVNIC_USE_SERVER_MAXES) {
+	ring->rx_max_pending = adapter->max_rx_add_entries_per_subcrq;
-		ring->rx_max_pending = adapter->max_rx_add_entries_per_subcrq;
+	ring->tx_max_pending = adapter->max_tx_entries_per_subcrq;
-		ring->tx_max_pending = adapter->max_tx_entries_per_subcrq;
-	} else {
-		ring->rx_max_pending = IBMVNIC_MAX_QUEUE_SZ;
-		ring->tx_max_pending = IBMVNIC_MAX_QUEUE_SZ;
-	}
 	ring->rx_mini_max_pending = 0;
 	ring->rx_jumbo_max_pending = 0;
 	ring->rx_pending = adapter->req_rx_add_entries_per_subcrq;
 				 struct netlink_ext_ack *extack)
 {
 	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
-	int ret;
-	ret = 0;
+	if (ring->rx_pending > adapter->max_rx_add_entries_per_subcrq  ||
+	    ring->tx_pending > adapter->max_tx_entries_per_subcrq) {
+		netdev_err(netdev, "Invalid request.\n");
+		netdev_err(netdev, "Max tx buffers = %llu\n",
+			   adapter->max_rx_add_entries_per_subcrq);
+		netdev_err(netdev, "Max rx buffers = %llu\n",
+			   adapter->max_tx_entries_per_subcrq);
+		return -EINVAL;
+	}
 	adapter->desired.rx_entries = ring->rx_pending;
 	adapter->desired.tx_entries = ring->tx_pending;
-	ret = wait_for_reset(adapter);
+	return wait_for_reset(adapter);
-	if (!ret &&
-	    (adapter->req_rx_add_entries_per_subcrq != ring->rx_pending ||
-	     adapter->req_tx_entries_per_subcrq != ring->tx_pending))
-		netdev_info(netdev,
-			    "Could not match full ringsize request. Requested: RX %d, TX %d; Allowed: RX %llu, TX %llu\n",
-			    ring->rx_pending, ring->tx_pending,
-			    adapter->req_rx_add_entries_per_subcrq,
-			    adapter->req_tx_entries_per_subcrq);
-	return ret;
 }
 static void ibmvnic_get_channels(struct net_device *netdev,
 {
 	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
-	if (adapter->priv_flags & IBMVNIC_USE_SERVER_MAXES) {
+	channels->max_rx = adapter->max_rx_queues;
-		channels->max_rx = adapter->max_rx_queues;
+	channels->max_tx = adapter->max_tx_queues;
-		channels->max_tx = adapter->max_tx_queues;
-	} else {
-		channels->max_rx = IBMVNIC_MAX_QUEUES;
-		channels->max_tx = IBMVNIC_MAX_QUEUES;
-	}
 	channels->max_other = 0;
 	channels->max_combined = 0;
 	channels->rx_count = adapter->req_rx_queues;
 				struct ethtool_channels *channels)
 {
 	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
-	int ret;
-	ret = 0;
 	adapter->desired.rx_queues = channels->rx_count;
 	adapter->desired.tx_queues = channels->tx_count;
-	ret = wait_for_reset(adapter);
+	return wait_for_reset(adapter);
-	if (!ret &&
-	    (adapter->req_rx_queues != channels->rx_count ||
-	     adapter->req_tx_queues != channels->tx_count))
-		netdev_info(netdev,
-			    "Could not match full channels request. Requested: RX %d, TX %d; Allowed: RX %llu, TX %llu\n",
-			    channels->rx_count, channels->tx_count,
-			    adapter->req_rx_queues, adapter->req_tx_queues);
-	return ret;
 }
 static void ibmvnic_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 	struct ibmvnic_adapter *adapter = netdev_priv(dev);
 	int i;
-	switch (stringset) {
+	if (stringset != ETH_SS_STATS)
-	case ETH_SS_STATS:
+		return;
-		for (i = 0; i < ARRAY_SIZE(ibmvnic_stats);
-				i++, data += ETH_GSTRING_LEN)
-			memcpy(data, ibmvnic_stats[i].name, ETH_GSTRING_LEN);
-		for (i = 0; i < adapter->req_tx_queues; i++) {
+	for (i = 0; i < ARRAY_SIZE(ibmvnic_stats); i++, data += ETH_GSTRING_LEN)
-			snprintf(data, ETH_GSTRING_LEN, "tx%d_packets", i);
+		memcpy(data, ibmvnic_stats[i].name, ETH_GSTRING_LEN);
-			data += ETH_GSTRING_LEN;
-			snprintf(data, ETH_GSTRING_LEN, "tx%d_bytes", i);
+	for (i = 0; i < adapter->req_tx_queues; i++) {
-			data += ETH_GSTRING_LEN;
+		snprintf(data, ETH_GSTRING_LEN, "tx%d_packets", i);
+		data += ETH_GSTRING_LEN;
-			snprintf(data, ETH_GSTRING_LEN,
+		snprintf(data, ETH_GSTRING_LEN, "tx%d_bytes", i);
-				 "tx%d_dropped_packets", i);
+		data += ETH_GSTRING_LEN;
-			data += ETH_GSTRING_LEN;
-		}
-		for (i = 0; i < adapter->req_rx_queues; i++) {
+		snprintf(data, ETH_GSTRING_LEN, "tx%d_dropped_packets", i);
-			snprintf(data, ETH_GSTRING_LEN, "rx%d_packets", i);
+		data += ETH_GSTRING_LEN;
-			data += ETH_GSTRING_LEN;
+	}
-			snprintf(data, ETH_GSTRING_LEN, "rx%d_bytes", i);
+	for (i = 0; i < adapter->req_rx_queues; i++) {
-			data += ETH_GSTRING_LEN;
+		snprintf(data, ETH_GSTRING_LEN, "rx%d_packets", i);
+		data += ETH_GSTRING_LEN;
-			snprintf(data, ETH_GSTRING_LEN, "rx%d_interrupts", i);
+		snprintf(data, ETH_GSTRING_LEN, "rx%d_bytes", i);
-			data += ETH_GSTRING_LEN;
+		data += ETH_GSTRING_LEN;
-		}
-		break;
-	case ETH_SS_PRIV_FLAGS:
+		snprintf(data, ETH_GSTRING_LEN, "rx%d_interrupts", i);
-		for (i = 0; i < ARRAY_SIZE(ibmvnic_priv_flags); i++)
+		data += ETH_GSTRING_LEN;
-			strcpy(data + i * ETH_GSTRING_LEN,
-			       ibmvnic_priv_flags[i]);
-		break;
-	default:
-		return;
 	}
 }
 		return ARRAY_SIZE(ibmvnic_stats) +
 		       adapter->req_tx_queues * NUM_TX_STATS +
 		       adapter->req_rx_queues * NUM_RX_STATS;
-	case ETH_SS_PRIV_FLAGS:
-		return ARRAY_SIZE(ibmvnic_priv_flags);
 	default:
 		return -EOPNOTSUPP;
 	}
 	}
 }
-static u32 ibmvnic_get_priv_flags(struct net_device *netdev)
-{
-	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
-	return adapter->priv_flags;
-}
-static int ibmvnic_set_priv_flags(struct net_device *netdev, u32 flags)
-{
-	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
-	bool which_maxes = !!(flags & IBMVNIC_USE_SERVER_MAXES);
-	if (which_maxes)
-		adapter->priv_flags |= IBMVNIC_USE_SERVER_MAXES;
-	else
-		adapter->priv_flags &= ~IBMVNIC_USE_SERVER_MAXES;
-	return 0;
-}
 static const struct ethtool_ops ibmvnic_ethtool_ops = {
 	.get_drvinfo		= ibmvnic_get_drvinfo,
 	.get_msglevel		= ibmvnic_get_msglevel,
 	.get_sset_count         = ibmvnic_get_sset_count,
 	.get_ethtool_stats	= ibmvnic_get_ethtool_stats,
 	.get_link_ksettings	= ibmvnic_get_link_ksettings,
-	.get_priv_flags		= ibmvnic_get_priv_flags,
-	.set_priv_flags		= ibmvnic_set_priv_flags,
 };
 /* Routines for managing CRQs/sCRQs  */

drivers/net/ethernet/ibm/ibmvnic.h+0−6

 #define IBMVNIC_RESET_DELAY 100
-static const char ibmvnic_priv_flags[][ETH_GSTRING_LEN] = {
-#define IBMVNIC_USE_SERVER_MAXES 0x1
-	"use-server-maxes"
-};
 struct ibmvnic_login_buffer {
 	__be32 len;
 	__be32 version;
 	struct ibmvnic_control_ip_offload_buffer ip_offload_ctrl;
 	dma_addr_t ip_offload_ctrl_tok;
 	u32 msg_enable;
-	u32 priv_flags;
 	/* Vital Product Data (VPD) */
 	struct ibmvnic_vpd *vpd;

drivers/net/ethernet/intel/i40e/i40e_main.c+14−13

 static int i40e_fwd_ring_up(struct i40e_vsi *vsi, struct net_device *vdev,
 			    struct i40e_fwd_adapter *fwd)
 {
+	struct i40e_channel *ch = NULL, *ch_tmp, *iter;
 	int ret = 0, num_tc = 1,  i, aq_err;
-	struct i40e_channel *ch, *ch_tmp;
 	struct i40e_pf *pf = vsi->back;
 	struct i40e_hw *hw = &pf->hw;
-	if (list_empty(&vsi->macvlan_list))
-		return -EINVAL;
 	/* Go through the list and find an available channel */
-	list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) {
+	list_for_each_entry_safe(iter, ch_tmp, &vsi->macvlan_list, list) {
-		if (!i40e_is_channel_macvlan(ch)) {
+		if (!i40e_is_channel_macvlan(iter)) {
-			ch->fwd = fwd;
+			iter->fwd = fwd;
 			/* record configuration for macvlan interface in vdev */
 			for (i = 0; i < num_tc; i++)
 				netdev_bind_sb_channel_queue(vsi->netdev, vdev,
 							     i,
-							     ch->num_queue_pairs,
+							     iter->num_queue_pairs,
-							     ch->base_queue);
+							     iter->base_queue);
-			for (i = 0; i < ch->num_queue_pairs; i++) {
+			for (i = 0; i < iter->num_queue_pairs; i++) {
 				struct i40e_ring *tx_ring, *rx_ring;
 				u16 pf_q;
-				pf_q = ch->base_queue + i;
+				pf_q = iter->base_queue + i;
 				/* Get to TX ring ptr */
 				tx_ring = vsi->tx_rings[pf_q];
-				tx_ring->ch = ch;
+				tx_ring->ch = iter;
 				/* Get the RX ring ptr */
 				rx_ring = vsi->rx_rings[pf_q];
-				rx_ring->ch = ch;
+				rx_ring->ch = iter;
 			}
+			ch = iter;
 			break;
 		}
 	}
+	if (!ch)
+		return -EINVAL;
 	/* Guarantee all rings are updated before we update the
 	 * MAC address filter.
 	 */

drivers/net/ethernet/intel/ice/ice.h+1−0

@@ -540,6 +540,7 @@ struct ice_pf { · 539 unmodified lines
540	struct mutex avail_q_mutex; /* protects access to avail_[rx\|tx]qs */	540	struct mutex avail_q_mutex; /* protects access to avail_[rx\|tx]qs */
541	struct mutex sw_mutex; /* lock for protecting VSI alloc flow */	541	struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
542	struct mutex tc_mutex; /* lock to protect TC changes */	542	struct mutex tc_mutex; /* lock to protect TC changes */
		543	struct mutex adev_mutex; /* lock to protect aux device access */
543	u32 msg_enable;	544	u32 msg_enable;
544	struct ice_ptp ptp;	545	struct ice_ptp ptp;
545	struct tty_driver *ice_gnss_tty_driver;	546	struct tty_driver *ice_gnss_tty_driver;

drivers/net/ethernet/intel/ice/ice_idc.c+17−8

 	if (WARN_ON_ONCE(!in_task()))
 		return;
+	mutex_lock(&pf->adev_mutex);
 	if (!pf->adev)
-		return;
+		goto finish;
 	device_lock(&pf->adev->dev);
 	iadrv = ice_get_auxiliary_drv(pf);
 	if (iadrv && iadrv->event_handler)
 		iadrv->event_handler(pf, event);
 	device_unlock(&pf->adev->dev);
+finish:
+	mutex_unlock(&pf->adev_mutex);
 }
 /**
 		return -ENOMEM;
 	adev = &iadev->adev;
-	pf->adev = adev;
 	iadev->pf = pf;
 	adev->id = pf->aux_idx;
 	ret = auxiliary_device_init(adev);
 	if (ret) {
-		pf->adev = NULL;
 		kfree(iadev);
 		return ret;
 	}
 	ret = auxiliary_device_add(adev);
 	if (ret) {
-		pf->adev = NULL;
 		auxiliary_device_uninit(adev);
 		return ret;
 	}
+	mutex_lock(&pf->adev_mutex);
+	pf->adev = adev;
+	mutex_unlock(&pf->adev_mutex);
 	return 0;
 }
  */
 void ice_unplug_aux_dev(struct ice_pf *pf)
 {
-	if (!pf->adev)
+	struct auxiliary_device *adev;
-		return;
-	auxiliary_device_delete(pf->adev);
+	mutex_lock(&pf->adev_mutex);
-	auxiliary_device_uninit(pf->adev);
+	adev = pf->adev;
 	pf->adev = NULL;
+	mutex_unlock(&pf->adev_mutex);
+	if (adev) {
+		auxiliary_device_delete(adev);
+		auxiliary_device_uninit(adev);
+	}
 }
 /**

drivers/net/ethernet/intel/ice/ice_main.c+5−0

 static void ice_deinit_pf(struct ice_pf *pf)
 {
 	ice_service_task_stop(pf);
+	mutex_destroy(&pf->adev_mutex);
 	mutex_destroy(&pf->sw_mutex);
 	mutex_destroy(&pf->tc_mutex);
 	mutex_destroy(&pf->avail_q_mutex);
 	mutex_init(&pf->sw_mutex);
 	mutex_init(&pf->tc_mutex);
+	mutex_init(&pf->adev_mutex);
 	INIT_HLIST_HEAD(&pf->aq_wait_list);
 	spin_lock_init(&pf->aq_wait_lock);
 	dev_dbg(dev, "rebuilding PF after reset_type=%d\n", reset_type);
+#define ICE_EMP_RESET_SLEEP_MS 5000
 	if (reset_type == ICE_RESET_EMPR) {
 		/* If an EMP reset has occurred, any previously pending flash
 		 * update will have completed. We no longer know whether or
 		 * not the NVM update EMP reset is restricted.
 		 */
 		pf->fw_emp_reset_disabled = false;
+		msleep(ICE_EMP_RESET_SLEEP_MS);
 	}
 	err = ice_init_all_ctrlq(hw);

drivers/net/ethernet/intel/ice/ice_ptp.c+8−2

 /**
  * ice_ptp_tx_tstamp_cleanup - Cleanup old timestamp requests that got dropped
+ * @hw: pointer to the hw struct
  * @tx: PTP Tx tracker to clean up
  *
  * Loop through the Tx timestamp requests and see if any of them have been
  * timestamp will never be captured. This might happen if the packet gets
  * discarded before it reaches the PHY timestamping block.
  */
-static void ice_ptp_tx_tstamp_cleanup(struct ice_ptp_tx *tx)
+static void ice_ptp_tx_tstamp_cleanup(struct ice_hw *hw, struct ice_ptp_tx *tx)
 {
 	u8 idx;
 	for_each_set_bit(idx, tx->in_use, tx->len) {
 		struct sk_buff *skb;
+		u64 raw_tstamp;
 		/* Check if this SKB has been waiting for too long */
 		if (time_is_after_jiffies(tx->tstamps[idx].start + 2 * HZ))
 			continue;
+		/* Read tstamp to be able to use this register again */
+		ice_read_phy_tstamp(hw, tx->quad, idx + tx->quad_offset,
+				    &raw_tstamp);
 		spin_lock(&tx->lock);
 		skb = tx->tstamps[idx].skb;
 		tx->tstamps[idx].skb = NULL;
 	ice_ptp_update_cached_phctime(pf);
-	ice_ptp_tx_tstamp_cleanup(&pf->ptp.port.tx);
+	ice_ptp_tx_tstamp_cleanup(&pf->hw, &pf->ptp.port.tx);
 	/* Run twice a second */
 	kthread_queue_delayed_work(ptp->kworker, &ptp->work,

drivers/net/ethernet/intel/ice/ice_sriov.c+1−1

 	if (!num_vfs) {
 		if (!pci_vfs_assigned(pdev)) {
-			ice_mbx_deinit_snapshot(&pf->hw);
 			ice_free_vfs(pf);
+			ice_mbx_deinit_snapshot(&pf->hw);
 			if (pf->lag)
 				ice_enable_lag(pf->lag);
 			return 0;

drivers/net/ethernet/intel/ice/ice_virtchnl.c+59−36

 				     NULL, 0);
 }
+/**
+ * ice_vf_vsi_dis_single_txq - disable a single Tx queue
+ * @vf: VF to disable queue for
+ * @vsi: VSI for the VF
+ * @q_id: VF relative (0-based) queue ID
+ *
+ * Attempt to disable the Tx queue passed in. If the Tx queue was successfully
+ * disabled then clear q_id bit in the enabled queues bitmap and return
+ * success. Otherwise return error.
+ */
+static int
+ice_vf_vsi_dis_single_txq(struct ice_vf *vf, struct ice_vsi *vsi, u16 q_id)
+{
+	struct ice_txq_meta txq_meta = { 0 };
+	struct ice_tx_ring *ring;
+	int err;
+	if (!test_bit(q_id, vf->txq_ena))
+		dev_dbg(ice_pf_to_dev(vsi->back), "Queue %u on VSI %u is not enabled, but stopping it anyway\n",
+			q_id, vsi->vsi_num);
+	ring = vsi->tx_rings[q_id];
+	if (!ring)
+		return -EINVAL;
+	ice_fill_txq_meta(vsi, ring, &txq_meta);
+	err = ice_vsi_stop_tx_ring(vsi, ICE_NO_RESET, vf->vf_id, ring, &txq_meta);
+	if (err) {
+		dev_err(ice_pf_to_dev(vsi->back), "Failed to stop Tx ring %d on VSI %d\n",
+			q_id, vsi->vsi_num);
+		return err;
+	}
+	/* Clear enabled queues flag */
+	clear_bit(q_id, vf->txq_ena);
+	return 0;
+}
 /**
  * ice_vc_dis_qs_msg
  * @vf: pointer to the VF info
  * @msg: pointer to the msg buffer
  *
- * called from the VF to disable all or specific
+ * called from the VF to disable all or specific queue(s)
- * queue(s)
  */
 static int ice_vc_dis_qs_msg(struct ice_vf *vf, u8 *msg)
 {
 		q_map = vqs->tx_queues;
 		for_each_set_bit(vf_q_id, &q_map, ICE_MAX_RSS_QS_PER_VF) {
-			struct ice_tx_ring *ring = vsi->tx_rings[vf_q_id];
-			struct ice_txq_meta txq_meta = { 0 };
 			if (!ice_vc_isvalid_q_id(vf, vqs->vsi_id, vf_q_id)) {
 				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
 				goto error_param;
 			}
-			if (!test_bit(vf_q_id, vf->txq_ena))
+			if (ice_vf_vsi_dis_single_txq(vf, vsi, vf_q_id)) {
-				dev_dbg(ice_pf_to_dev(vsi->back), "Queue %u on VSI %u is not enabled, but stopping it anyway\n",
-					vf_q_id, vsi->vsi_num);
-			ice_fill_txq_meta(vsi, ring, &txq_meta);
-			if (ice_vsi_stop_tx_ring(vsi, ICE_NO_RESET, vf->vf_id,
-						 ring, &txq_meta)) {
-				dev_err(ice_pf_to_dev(vsi->back), "Failed to stop Tx ring %d on VSI %d\n",
-					vf_q_id, vsi->vsi_num);
 				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
 				goto error_param;
 			}
-			/* Clear enabled queues flag */
-			clear_bit(vf_q_id, vf->txq_ena);
 		}
 	}
 		if (qpi->txq.ring_len > 0) {
 			vsi->tx_rings[i]->dma = qpi->txq.dma_ring_addr;
 			vsi->tx_rings[i]->count = qpi->txq.ring_len;
+			/* Disable any existing queue first */
+			if (ice_vf_vsi_dis_single_txq(vf, vsi, q_idx)) {
+				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
+				goto error_param;
+			}
+			/* Configure a queue with the requested settings */
 			if (ice_vsi_cfg_single_txq(vsi, vsi->tx_rings, q_idx)) {
 				v_ret = VIRTCHNL_STATUS_ERR_PARAM;
 				goto error_param;
 		return;
 	}
+	mutex_lock(&vf->cfg_lock);
 	/* Check if VF is disabled. */
 	if (test_bit(ICE_VF_STATE_DIS, vf->vf_states)) {
 		err = -EPERM;
 			err = -EINVAL;
 	}
-	if (!ice_vc_is_opcode_allowed(vf, v_opcode)) {
-		ice_vc_send_msg_to_vf(vf, v_opcode,
-				      VIRTCHNL_STATUS_ERR_NOT_SUPPORTED, NULL,
-				      0);
-		ice_put_vf(vf);
-		return;
-	}
 error_handler:
 	if (err) {
 		ice_vc_send_msg_to_vf(vf, v_opcode, VIRTCHNL_STATUS_ERR_PARAM,
 				      NULL, 0);
 		dev_err(dev, "Invalid message from VF %d, opcode %d, len %d, error %d\n",
 			vf_id, v_opcode, msglen, err);
-		ice_put_vf(vf);
+		goto finish;
-		return;
 	}
-	/* VF is being configured in another context that triggers a VFR, so no
+	if (!ice_vc_is_opcode_allowed(vf, v_opcode)) {
-	 * need to process this message
+		ice_vc_send_msg_to_vf(vf, v_opcode,
-	 */
+				      VIRTCHNL_STATUS_ERR_NOT_SUPPORTED, NULL,
-	if (!mutex_trylock(&vf->cfg_lock)) {
+				      0);
-		dev_info(dev, "VF %u is being configured in another context that will trigger a VFR, so there is no need to handle this message\n",
+		goto finish;
-			 vf->vf_id);
-		ice_put_vf(vf);
-		return;
 	}
 	switch (v_opcode) {
 			 vf_id, v_opcode, err);
 	}
+finish:
 	mutex_unlock(&vf->cfg_lock);
 	ice_put_vf(vf);
 }

drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c+2−1

 	/* Tx IPsec offload doesn't seem to work on this
 	 * device, so block these requests for now.
 	 */
-	if (!(sam->flags & XFRM_OFFLOAD_INBOUND)) {
+	sam->flags = sam->flags & ~XFRM_OFFLOAD_IPV6;
+	if (sam->flags != XFRM_OFFLOAD_INBOUND) {
 		err = -EOPNOTSUPP;
 		goto err_out;
 	}

drivers/net/ethernet/mediatek/mtk_ppe.c+1−1

@@ -395,7 +395,7 @@ static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe) · 394 unmodified lines
395	static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };	395	static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };
396	int i, k;	396	int i, k;
397		397
398	memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table));	398	memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(*ppe->foe_table));
399		399
400	if (!IS_ENABLED(CONFIG_SOC_MT7621))	400	if (!IS_ENABLED(CONFIG_SOC_MT7621))
401	return;	401	return;

drivers/net/ethernet/mediatek/mtk_sgmii.c+1−0

@@ -26,6 +26,7 @@ int mtk_sgmii_init(struct mtk_sgmii ss, struct device_node r, u32 ana_rgc3) · 25 unmodified lines
26	break;	26	break;
27		27
28	ss->regmap[i] = syscon_node_to_regmap(np);	28	ss->regmap[i] = syscon_node_to_regmap(np);
		29	of_node_put(np);
29	if (IS_ERR(ss->regmap[i]))	30	if (IS_ERR(ss->regmap[i]))
30	return PTR_ERR(ss->regmap[i]);	31	return PTR_ERR(ss->regmap[i]);
31	}	32	}

drivers/net/ethernet/mellanox/mlx5/core/diag/rsc_dump.c+25−6

 struct mlx5_rsc_dump {
 	u32 pdn;
 	u32 mkey;
+	u32 number_of_menu_items;
 	u16 fw_segment_type[MLX5_SGMT_TYPE_NUM];
 };
 	return -EINVAL;
 }
-static void mlx5_rsc_dump_read_menu_sgmt(struct mlx5_rsc_dump *rsc_dump, struct page *page)
+#define MLX5_RSC_DUMP_MENU_HEADER_SIZE (MLX5_ST_SZ_BYTES(resource_dump_info_segment) + \
+					MLX5_ST_SZ_BYTES(resource_dump_command_segment) + \
+					MLX5_ST_SZ_BYTES(resource_dump_menu_segment))
+static int mlx5_rsc_dump_read_menu_sgmt(struct mlx5_rsc_dump *rsc_dump, struct page *page,
+					int read_size, int start_idx)
 {
 	void *data = page_address(page);
 	enum mlx5_sgmt_type sgmt_idx;
 	int num_of_items;
 	char *sgmt_name;
 	void *member;
+	int size = 0;
 	void *menu;
 	int i;
-	menu = MLX5_ADDR_OF(menu_resource_dump_response, data, menu);
+	if (!start_idx) {
-	num_of_items = MLX5_GET(resource_dump_menu_segment, menu, num_of_records);
+		menu = MLX5_ADDR_OF(menu_resource_dump_response, data, menu);
+		rsc_dump->number_of_menu_items = MLX5_GET(resource_dump_menu_segment, menu,
+							  num_of_records);
+		size = MLX5_RSC_DUMP_MENU_HEADER_SIZE;
+		data += size;
+	}
+	num_of_items = rsc_dump->number_of_menu_items;
+	for (i = 0; start_idx + i < num_of_items; i++) {
+		size += MLX5_ST_SZ_BYTES(resource_dump_menu_record);
+		if (size >= read_size)
+			return start_idx + i;
-	for (i = 0; i < num_of_items; i++) {
+		member = data + MLX5_ST_SZ_BYTES(resource_dump_menu_record) * i;
-		member = MLX5_ADDR_OF(resource_dump_menu_segment, menu, record[i]);
 		sgmt_name =  MLX5_ADDR_OF(resource_dump_menu_record, member, segment_name);
 		sgmt_idx = mlx5_rsc_dump_sgmt_get_by_name(sgmt_name);
 		if (sgmt_idx == -EINVAL)
 		rsc_dump->fw_segment_type[sgmt_idx] = MLX5_GET(resource_dump_menu_record,
 							       member, segment_type);
 	}
+	return 0;
 }
 static int mlx5_rsc_dump_trigger(struct mlx5_core_dev *dev, struct mlx5_rsc_dump_cmd *cmd,
 	struct mlx5_rsc_dump_cmd *cmd = NULL;
 	struct mlx5_rsc_key key = {};
 	struct page *page;
+	int start_idx = 0;
 	int size;
 	int err;
 		if (err < 0)
 			goto destroy_cmd;
-		mlx5_rsc_dump_read_menu_sgmt(dev->rsc_dump, page);
+		start_idx = mlx5_rsc_dump_read_menu_sgmt(dev->rsc_dump, page, size, start_idx);
 	} while (err > 0);

drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.c+2−2

@@ -309,8 +309,8 @@ int mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv, · 308 unmodified lines
309	if (err)	309	if (err)
310	return err;	310	return err;
311		311
312	err = update_buffer_lossy(max_mtu, curr_pfc_en, prio2buffer, port_buff_cell_sz,	312	err = update_buffer_lossy(max_mtu, curr_pfc_en, prio2buffer, xoff,
313	xoff, &port_buffer, &update_buffer);	313	port_buff_cell_sz, &port_buffer, &update_buffer);
314	if (err)	314	if (err)
315	return err;	315	return err;
316	}	316	}

drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.c+1−2

@@ -145,8 +145,7 @@ mlx5e_tc_act_post_parse(struct mlx5e_tc_act_parse_state *parse_state, · 144 unmodified lines
145		145
146	flow_action_for_each(i, act, flow_action) {	146	flow_action_for_each(i, act, flow_action) {
147	tc_act = mlx5e_tc_act_get(act->id, ns_type);	147	tc_act = mlx5e_tc_act_get(act->id, ns_type);
148	if (!tc_act \|\| !tc_act->post_parse \|\|	148	if (!tc_act \|\| !tc_act->post_parse)
149	!tc_act->can_offload(parse_state, act, i, attr))
150	continue;	149	continue;
151		150
152	err = tc_act->post_parse(parse_state, priv, attr);	151	err = tc_act->post_parse(parse_state, priv, attr);

drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c+32−2

@@ -45,12 +45,41 @@ tc_act_parse_ct(struct mlx5e_tc_act_parse_state *parse_state, · 44 unmodified lines
45	if (mlx5e_is_eswitch_flow(parse_state->flow))	45	if (mlx5e_is_eswitch_flow(parse_state->flow))
46	attr->esw_attr->split_count = attr->esw_attr->out_count;	46	attr->esw_attr->split_count = attr->esw_attr->out_count;
47		47
48	if (!clear_action) {	48	if (clear_action) {
		49	parse_state->ct_clear = true;
		50	} else {
49	attr->flags \|= MLX5_ATTR_FLAG_CT;	51	attr->flags \|= MLX5_ATTR_FLAG_CT;
50	flow_flag_set(parse_state->flow, CT);	52	flow_flag_set(parse_state->flow, CT);
51	parse_state->ct = true;	53	parse_state->ct = true;
52	}	54	}
53	parse_state->ct_clear = clear_action;	55
		56	return 0;
		57	}
		58
		59	static int
		60	tc_act_post_parse_ct(struct mlx5e_tc_act_parse_state *parse_state,
		61	struct mlx5e_priv *priv,
		62	struct mlx5_flow_attr *attr)
		63	{
		64	struct mlx5e_tc_mod_hdr_acts *mod_acts = &attr->parse_attr->mod_hdr_acts;
		65	int err;
		66
		67	/* If ct action exist, we can ignore previous ct_clear actions */
		68	if (parse_state->ct)
		69	return 0;
		70
		71	if (parse_state->ct_clear) {
		72	err = mlx5_tc_ct_set_ct_clear_regs(parse_state->ct_priv, mod_acts);
		73	if (err) {
		74	NL_SET_ERR_MSG_MOD(parse_state->extack,
		75	"Failed to set registers for ct clear");
		76	return err;
		77	}
		78	attr->action \|= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
		79
		80	/* Prevent handling of additional, redundant clear actions */
		81	parse_state->ct_clear = false;
		82	}
54		83
55	return 0;	84	return 0;
56	}	85	}
@@ -70,5 +99,6 @@ struct mlx5e_tc_act mlx5e_tc_act_ct = { · 13 unmodified lines
70	.can_offload = tc_act_can_offload_ct,	99	.can_offload = tc_act_can_offload_ct,
71	.parse_action = tc_act_parse_ct,	100	.parse_action = tc_act_parse_ct,
72	.is_multi_table_act = tc_act_is_multi_table_act_ct,	101	.is_multi_table_act = tc_act_is_multi_table_act_ct,
		102	.post_parse = tc_act_post_parse_ct,
73	};	103	};
74		104

drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c+10−14

 	return 0;
 }
+int mlx5_tc_ct_set_ct_clear_regs(struct mlx5_tc_ct_priv *priv,
+				 struct mlx5e_tc_mod_hdr_acts *mod_acts)
+{
+		return mlx5_tc_ct_entry_set_registers(priv, mod_acts, 0, 0, 0, 0);
+}
 static int
 mlx5_tc_ct_parse_mangle_to_mod_act(struct flow_action_entry *act,
 				   char *modact)
 			const struct flow_action_entry *act,
 			struct netlink_ext_ack *extack)
 {
-	bool clear_action = act->ct.action & TCA_CT_ACT_CLEAR;
-	int err;
 	if (!priv) {
 		NL_SET_ERR_MSG_MOD(extack,
 				   "offload of ct action isn't available");
 	attr->ct_attr.ct_action = act->ct.action;
 	attr->ct_attr.nf_ft = act->ct.flow_table;
-	if (!clear_action)
-		goto out;
-	err = mlx5_tc_ct_entry_set_registers(priv, mod_acts, 0, 0, 0, 0);
-	if (err) {
-		NL_SET_ERR_MSG_MOD(extack, "Failed to set registers for ct clear");
-		return err;
-	}
-	attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
-out:
 	return 0;
 }
 static void
 mlx5_tc_ct_del_ft_cb(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_ft *ft)
 {
+	struct mlx5e_priv *priv;
 	if (!refcount_dec_and_test(&ft->refcount))
 		return;
 	rhashtable_free_and_destroy(&ft->ct_entries_ht,
 				    mlx5_tc_ct_flush_ft_entry,
 				    ct_priv);
+	priv = netdev_priv(ct_priv->netdev);
+	flush_workqueue(priv->wq);
 	mlx5_tc_ct_free_pre_ct_tables(ft);
 	mapping_remove(ct_priv->zone_mapping, ft->zone_restore_id);
 	kfree(ft);

drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h+11−0

 mlx5e_tc_ct_restore_flow(struct mlx5_tc_ct_priv *ct_priv,
 			 struct sk_buff *skb, u8 zone_restore_id);
+int
+mlx5_tc_ct_set_ct_clear_regs(struct mlx5_tc_ct_priv *priv,
+			     struct mlx5e_tc_mod_hdr_acts *mod_acts);
 #else /* CONFIG_MLX5_TC_CT */
 static inline struct mlx5_tc_ct_priv *
 	return 0;
 }
+static inline int
+mlx5_tc_ct_set_ct_clear_regs(struct mlx5_tc_ct_priv *priv,
+			     struct mlx5e_tc_mod_hdr_acts *mod_acts)
+{
+	return -EOPNOTSUPP;
+}
 static inline int
 mlx5_tc_ct_parse_action(struct mlx5_tc_ct_priv *priv,
 			struct mlx5_flow_attr *attr,

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c+2−1

 			      struct net_device *filter_dev)
 {
 	struct mlx5_esw_flow_attr *esw_attr = flow_attr->esw_attr;
+	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 	struct mlx5e_tc_int_port *int_port;
 	TC_TUN_ROUTE_ATTR_INIT(attr);
 	u16 vport_num;
 		esw_attr->rx_tun_attr->vni = MLX5_GET(fte_match_param, spec->match_value,
 						      misc_parameters.vxlan_vni);
 		esw_attr->rx_tun_attr->decap_vport = vport_num;
-	} else if (netif_is_ovs_master(attr.route_dev)) {
+	} else if (netif_is_ovs_master(attr.route_dev) && mlx5e_tc_int_port_supported(esw)) {
 		int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
 						 attr.route_dev->ifindex,
 						 MLX5E_TC_INT_PORT_INGRESS);

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c+10−0

@@ -1200,6 +1200,16 @@ static int mlx5e_trust_initialize(struct mlx5e_priv *priv) · 1199 unmodified lines
1200	return err;	1200	return err;
1201	WRITE_ONCE(priv->dcbx_dp.trust_state, trust_state);	1201	WRITE_ONCE(priv->dcbx_dp.trust_state, trust_state);
1202		1202
		1203	if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_PCP && priv->dcbx.dscp_app_cnt) {
		1204	/*
		1205	* Align the driver state with the register state.
		1206	* Temporary state change is required to enable the app list reset.
		1207	*/
		1208	priv->dcbx_dp.trust_state = MLX5_QPTS_TRUST_DSCP;
		1209	mlx5e_dcbnl_delete_app(priv);
		1210	priv->dcbx_dp.trust_state = MLX5_QPTS_TRUST_PCP;
		1211	}
		1212
1203	mlx5e_params_calc_trust_tx_min_inline_mode(priv->mdev, &priv->channels.params,	1213	mlx5e_params_calc_trust_tx_min_inline_mode(priv->mdev, &priv->channels.params,
1204	priv->dcbx_dp.trust_state);	1214	priv->dcbx_dp.trust_state);
1205		1215

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+11−0

@@ -2459,6 +2459,17 @@ static int __parse_cls_flower(struct mlx5e_priv *priv, · 2458 unmodified lines
2459	match.key->vlan_priority);	2459	match.key->vlan_priority);
2460		2460
2461	*match_level = MLX5_MATCH_L2;	2461	*match_level = MLX5_MATCH_L2;
		2462
		2463	if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
		2464	match.mask->vlan_eth_type &&
		2465	MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
		2466	ft_field_support.outer_second_vid,
		2467	fs_type)) {
		2468	MLX5_SET(fte_match_set_misc, misc_c,
		2469	outer_second_cvlan_tag, 1);
		2470	spec->match_criteria_enable \|=
		2471	MLX5_MATCH_MISC_PARAMETERS;
		2472	}
2462	}	2473	}
2463	} else if (*match_level != MLX5_MATCH_NONE) {	2474	} else if (*match_level != MLX5_MATCH_NONE) {
2464	/* cvlan_tag enabled in match criteria and	2475	/* cvlan_tag enabled in match criteria and

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+1−1

@@ -139,7 +139,7 @@ mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw, · 138 unmodified lines
139	if (mlx5_esw_indir_table_decap_vport(attr))	139	if (mlx5_esw_indir_table_decap_vport(attr))
140	vport = mlx5_esw_indir_table_decap_vport(attr);	140	vport = mlx5_esw_indir_table_decap_vport(attr);
141		141
142	if (esw_attr->int_port)	142	if (attr && !attr->chain && esw_attr->int_port)
143	metadata =	143	metadata =
144	mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);	144	mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
145	else	145	else

drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c+35−25

 	}
 }
+static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
+{
+	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
+	del_timer_sync(&fw_reset->timer);
+}
+static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
+{
+	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
+	if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
+		mlx5_core_warn(dev, "Reset request was already cleared\n");
+		return -EALREADY;
+	}
+	mlx5_stop_sync_reset_poll(dev);
+	if (poll_health)
+		mlx5_start_health_poll(dev);
+	return 0;
+}
 static void mlx5_sync_reset_reload_work(struct work_struct *work)
 {
 	struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 	struct mlx5_core_dev *dev = fw_reset->dev;
 	int err;
+	mlx5_sync_reset_clear_reset_requested(dev, false);
 	mlx5_enter_error_state(dev, true);
 	mlx5_unload_one(dev);
 	err = mlx5_health_wait_pci_up(dev);
 	mlx5_fw_reset_complete_reload(dev);
 }
-static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
-{
-	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
-	del_timer_sync(&fw_reset->timer);
-}
-static void mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
-{
-	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
-	mlx5_stop_sync_reset_poll(dev);
-	clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags);
-	if (poll_health)
-		mlx5_start_health_poll(dev);
-}
 #define MLX5_RESET_POLL_INTERVAL	(HZ / 10)
 static void poll_sync_reset(struct timer_list *t)
 {
 	if (fatal_error) {
 		mlx5_core_warn(dev, "Got Device Reset\n");
-		mlx5_sync_reset_clear_reset_requested(dev, false);
 		queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
 		return;
 	}
 	return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
 }
-static void mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
+static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
 {
 	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
+	if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
+		mlx5_core_warn(dev, "Reset request was already set\n");
+		return -EALREADY;
+	}
 	mlx5_stop_health_poll(dev, true);
-	set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags);
 	mlx5_start_sync_reset_poll(dev);
+	return 0;
 }
 static void mlx5_fw_live_patch_event(struct work_struct *work)
 			       err ? "Failed" : "Sent");
 		return;
 	}
-	mlx5_sync_reset_set_reset_requested(dev);
+	if (mlx5_sync_reset_set_reset_requested(dev))
+		return;
 	err = mlx5_fw_reset_set_reset_sync_ack(dev);
 	if (err)
 		mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
 	struct mlx5_core_dev *dev = fw_reset->dev;
 	int err;
-	mlx5_sync_reset_clear_reset_requested(dev, false);
+	if (mlx5_sync_reset_clear_reset_requested(dev, false))
+		return;
 	mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
 						      reset_abort_work);
 	struct mlx5_core_dev *dev = fw_reset->dev;
-	if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
+	if (mlx5_sync_reset_clear_reset_requested(dev, true))
 		return;
-	mlx5_sync_reset_clear_reset_requested(dev, true);
 	mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
 }

drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c+24−14

 	flush_workqueue(mp->wq);
 }
+static void mlx5_lag_fib_set(struct lag_mp *mp, struct fib_info *fi, u32 dst, int dst_len)
+{
+	mp->fib.mfi = fi;
+	mp->fib.priority = fi->fib_priority;
+	mp->fib.dst = dst;
+	mp->fib.dst_len = dst_len;
+}
 struct mlx5_fib_event_work {
 	struct work_struct work;
 	struct mlx5_lag *ldev;
 	};
 };
-static void mlx5_lag_fib_route_event(struct mlx5_lag *ldev,
+static void mlx5_lag_fib_route_event(struct mlx5_lag *ldev, unsigned long event,
-				     unsigned long event,
+				     struct fib_entry_notifier_info *fen_info)
-				     struct fib_info *fi)
 {
+	struct fib_info *fi = fen_info->fi;
 	struct lag_mp *mp = &ldev->lag_mp;
 	struct fib_nh *fib_nh0, *fib_nh1;
 	unsigned int nhs;
 	/* Handle delete event */
 	if (event == FIB_EVENT_ENTRY_DEL) {
 		/* stop track */
-		if (mp->mfi == fi)
+		if (mp->fib.mfi == fi)
-			mp->mfi = NULL;
+			mp->fib.mfi = NULL;
 		return;
 	}
 	/* Handle multipath entry with lower priority value */
-	if (mp->mfi && mp->mfi != fi && fi->fib_priority >= mp->mfi->fib_priority)
+	if (mp->fib.mfi && mp->fib.mfi != fi &&
+	    (mp->fib.dst != fen_info->dst || mp->fib.dst_len != fen_info->dst_len) &&
+	    fi->fib_priority >= mp->fib.priority)
 		return;
 	/* Handle add/replace event */
 			i++;
 			mlx5_lag_set_port_affinity(ldev, i);
+			mlx5_lag_fib_set(mp, fi, fen_info->dst, fen_info->dst_len);
 		}
-		mp->mfi = fi;
 		return;
 	}
 	}
 	/* First time we see multipath route */
-	if (!mp->mfi && !__mlx5_lag_is_active(ldev)) {
+	if (!mp->fib.mfi && !__mlx5_lag_is_active(ldev)) {
 		struct lag_tracker tracker;
 		tracker = ldev->tracker;
 	}
 	mlx5_lag_set_port_affinity(ldev, MLX5_LAG_NORMAL_AFFINITY);
-	mp->mfi = fi;
+	mlx5_lag_fib_set(mp, fi, fen_info->dst, fen_info->dst_len);
 }
 static void mlx5_lag_fib_nexthop_event(struct mlx5_lag *ldev,
 	struct lag_mp *mp = &ldev->lag_mp;
 	/* Check the nh event is related to the route */
-	if (!mp->mfi || mp->mfi != fi)
+	if (!mp->fib.mfi || mp->fib.mfi != fi)
 		return;
 	/* nh added/removed */
 	case FIB_EVENT_ENTRY_REPLACE:
 	case FIB_EVENT_ENTRY_DEL:
 		mlx5_lag_fib_route_event(ldev, fib_work->event,
-					 fib_work->fen_info.fi);
+					 &fib_work->fen_info);
 		fib_info_put(fib_work->fen_info.fi);
 		break;
 	case FIB_EVENT_NH_ADD:
 	/* Clear mfi, as it might become stale when a route delete event
 	 * has been missed, see mlx5_lag_fib_route_event().
 	 */
-	ldev->lag_mp.mfi = NULL;
+	ldev->lag_mp.fib.mfi = NULL;
 }
 int mlx5_lag_mp_init(struct mlx5_lag *ldev)
 	/* always clear mfi, as it might become stale when a route delete event
 	 * has been missed
 	 */
-	mp->mfi = NULL;
+	mp->fib.mfi = NULL;
 	if (mp->fib_nb.notifier_call)
 		return 0;
 	unregister_fib_notifier(&init_net, &mp->fib_nb);
 	destroy_workqueue(mp->wq);
 	mp->fib_nb.notifier_call = NULL;
-	mp->mfi = NULL;
+	mp->fib.mfi = NULL;
 }

drivers/net/ethernet/mellanox/mlx5/core/lag/mp.h+6−1

 struct lag_mp {
 	struct notifier_block     fib_nb;
-	struct fib_info           *mfi; /* used in tracking fib events */
+	struct {
+		const void        *mfi; /* used in tracking fib events */
+		u32               priority;
+		u32               dst;
+		int               dst_len;
+	} fib;
 	struct workqueue_struct   *wq;
 };

drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c+1−1

@@ -505,7 +505,7 @@ static int mlx5_lag_create_inner_ttc_table(struct mlx5_lag *ldev) · 504 unmodified lines
505	struct ttc_params ttc_params = {};	505	struct ttc_params ttc_params = {};
506		506
507	mlx5_lag_set_inner_ttc_params(ldev, &ttc_params);	507	mlx5_lag_set_inner_ttc_params(ldev, &ttc_params);
508	port_sel->inner.ttc = mlx5_create_ttc_table(dev, &ttc_params);	508	port_sel->inner.ttc = mlx5_create_inner_ttc_table(dev, &ttc_params);
509	if (IS_ERR(port_sel->inner.ttc))	509	if (IS_ERR(port_sel->inner.ttc))
510	return PTR_ERR(port_sel->inner.ttc);	510	return PTR_ERR(port_sel->inner.ttc);
511		511

drivers/net/ethernet/mellanox/mlx5/core/lib/fs_ttc.c+2−0

@@ -408,6 +408,8 @@ static int mlx5_generate_inner_ttc_table_rules(struct mlx5_core_dev *dev, · 407 unmodified lines
408	for (tt = 0; tt < MLX5_NUM_TT; tt++) {	408	for (tt = 0; tt < MLX5_NUM_TT; tt++) {
409	struct mlx5_ttc_rule *rule = &rules[tt];	409	struct mlx5_ttc_rule *rule = &rules[tt];
410		410
		411	if (test_bit(tt, params->ignore_dests))
		412	continue;
411	rule->rule = mlx5_generate_inner_ttc_rule(dev, ft,	413	rule->rule = mlx5_generate_inner_ttc_rule(dev, ft,
412	&params->dests[tt],	414	&params->dests[tt],
413	ttc_rules[tt].etype,	415	ttc_rules[tt].etype,

drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c+3−8

@@ -568,10 +568,8 @@ static int · 567 unmodified lines
568	mlxsw_sp2_ipip_rem_addr_set_gre6(struct mlxsw_sp *mlxsw_sp,	568	mlxsw_sp2_ipip_rem_addr_set_gre6(struct mlxsw_sp *mlxsw_sp,
569	struct mlxsw_sp_ipip_entry *ipip_entry)	569	struct mlxsw_sp_ipip_entry *ipip_entry)
570	{	570	{
571	struct __ip6_tnl_parm parms6;	571	return mlxsw_sp_ipv6_addr_kvdl_index_get(mlxsw_sp,
572		572	&ipip_entry->parms.daddr.addr6,
573	parms6 = mlxsw_sp_ipip_netdev_parms6(ipip_entry->ol_dev);
574	return mlxsw_sp_ipv6_addr_kvdl_index_get(mlxsw_sp, &parms6.raddr,
575	&ipip_entry->dip_kvdl_index);	573	&ipip_entry->dip_kvdl_index);
576	}	574	}
577		575
@@ -579,10 +577,7 @@ static void · 1 unmodified line
579	mlxsw_sp2_ipip_rem_addr_unset_gre6(struct mlxsw_sp *mlxsw_sp,	577	mlxsw_sp2_ipip_rem_addr_unset_gre6(struct mlxsw_sp *mlxsw_sp,
580	const struct mlxsw_sp_ipip_entry *ipip_entry)	578	const struct mlxsw_sp_ipip_entry *ipip_entry)
581	{	579	{
582	struct __ip6_tnl_parm parms6;	580	mlxsw_sp_ipv6_addr_put(mlxsw_sp, &ipip_entry->parms.daddr.addr6);
583
584	parms6 = mlxsw_sp_ipip_netdev_parms6(ipip_entry->ol_dev);
585	mlxsw_sp_ipv6_addr_put(mlxsw_sp, &parms6.raddr);
586	}	581	}
587		582
588	static const struct mlxsw_sp_ipip_ops mlxsw_sp2_ipip_gre6_ops = {	583	static const struct mlxsw_sp_ipip_ops mlxsw_sp2_ipip_gre6_ops = {

drivers/net/ethernet/microchip/lan966x/lan966x_mac.c+2−2

@@ -346,7 +346,7 @@ static void lan966x_mac_irq_process(struct lan966x *lan966x, u32 row, · 345 unmodified lines
346		346
347	lan966x_mac_process_raw_entry(&raw_entries[column],	347	lan966x_mac_process_raw_entry(&raw_entries[column],
348	mac, &vid, &dest_idx);	348	mac, &vid, &dest_idx);
349	if (WARN_ON(dest_idx > lan966x->num_phys_ports))	349	if (WARN_ON(dest_idx >= lan966x->num_phys_ports))
350	continue;	350	continue;
351		351
352	/* If the entry in SW is found, then there is nothing	352	/* If the entry in SW is found, then there is nothing
@@ -393,7 +393,7 @@ static void lan966x_mac_irq_process(struct lan966x *lan966x, u32 row, · 40 unmodified lines
393		393
394	lan966x_mac_process_raw_entry(&raw_entries[column],	394	lan966x_mac_process_raw_entry(&raw_entries[column],
395	mac, &vid, &dest_idx);	395	mac, &vid, &dest_idx);
396	if (WARN_ON(dest_idx > lan966x->num_phys_ports))	396	if (WARN_ON(dest_idx >= lan966x->num_phys_ports))
397	continue;	397	continue;
398		398
399	mac_entry = lan966x_mac_alloc_entry(mac, vid, dest_idx);	399	mac_entry = lan966x_mac_alloc_entry(mac, vid, dest_idx);

drivers/net/ethernet/mscc/ocelot.c+15−10

 	struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 	struct ocelot_vcap_filter *filter;
-	int err;
+	int err = 0;
 	u32 val;
 	list_for_each_entry(filter, &block->rules, list) {
 	if (vlan_aware)
 		err = ocelot_del_vlan_unaware_pvid(ocelot, port,
 						   ocelot_port->bridge);
-	else
+	else if (ocelot_port->bridge)
 		err = ocelot_add_vlan_unaware_pvid(ocelot, port,
 						   ocelot_port->bridge);
 	if (err)
 {
 	int err;
+	/* Ignore VID 0 added to our RX filter by the 8021q module, since
+	 * that collides with OCELOT_STANDALONE_PVID and changes it from
+	 * egress-untagged to egress-tagged.
+	 */
+	if (!vid)
+		return 0;
 	err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
 	if (err)
 		return err;
 	bool del_pvid = false;
 	int err;
+	if (!vid)
+		return 0;
 	if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
 		del_pvid = true;
 		trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
 		trap->action.port_mask = 0;
 		trap->take_ts = take_ts;
-		list_add_tail(&trap->trap_list, &ocelot->traps);
+		trap->is_trap = true;
 		new = true;
 	}
 		err = ocelot_vcap_filter_replace(ocelot, trap);
 	if (err) {
 		trap->ingress_port_mask &= ~BIT(port);
-		if (!trap->ingress_port_mask) {
+		if (!trap->ingress_port_mask)
-			list_del(&trap->trap_list);
 			kfree(trap);
-		}
 		return err;
 	}
 		return 0;
 	trap->ingress_port_mask &= ~BIT(port);
-	if (!trap->ingress_port_mask) {
+	if (!trap->ingress_port_mask)
-		list_del(&trap->trap_list);
 		return ocelot_vcap_filter_del(ocelot, trap);
-	}
 	return ocelot_vcap_filter_replace(ocelot, trap);
 }

drivers/net/ethernet/mscc/ocelot_flower.c+4−5

 			filter->type = OCELOT_VCAP_FILTER_OFFLOAD;
 			break;
 		case FLOW_ACTION_TRAP:
-			if (filter->block_id != VCAP_IS2) {
+			if (filter->block_id != VCAP_IS2 ||
+			    filter->lookup != 0) {
 				NL_SET_ERR_MSG_MOD(extack,
-						   "Trap action can only be offloaded to VCAP IS2");
+						   "Trap action can only be offloaded to VCAP IS2 lookup 0");
 				return -EOPNOTSUPP;
 			}
 			if (filter->goto_target != -1) {
 			filter->action.cpu_copy_ena = true;
 			filter->action.cpu_qu_num = 0;
 			filter->type = OCELOT_VCAP_FILTER_OFFLOAD;
-			list_add_tail(&filter->trap_list, &ocelot->traps);
+			filter->is_trap = true;
 			break;
 		case FLOW_ACTION_POLICE:
 			if (filter->block_id == PSFP_BLOCK_ID) {
 	ret = ocelot_flower_parse(ocelot, port, ingress, f, filter);
 	if (ret) {
-		if (!list_empty(&filter->trap_list))
-			list_del(&filter->trap_list);
 		kfree(filter);
 		return ret;
 	}

drivers/net/ethernet/mscc/ocelot_vcap.c+8−1

 			 OCELOT_VCAP_BIT_0);
 	vcap_key_set(vcap, &data, VCAP_IS2_HK_IGR_PORT_MASK, 0,
 		     ~filter->ingress_port_mask);
-	vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_FIRST, OCELOT_VCAP_BIT_ANY);
 	vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_HOST_MATCH,
 			 OCELOT_VCAP_BIT_ANY);
 	vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_MC, filter->dmac_mc);
 		struct ocelot_vcap_filter *tmp;
 		tmp = ocelot_vcap_block_find_filter_by_index(block, i);
+		/* Read back the filter's counters before moving it */
+		vcap_entry_get(ocelot, i - 1, tmp);
 		vcap_entry_set(ocelot, i, tmp);
 	}
 	struct ocelot_vcap_filter del_filter;
 	int i, index;
+	/* Need to inherit the block_id so that vcap_entry_set()
+	 * does not get confused and knows where to install it.
+	 */
 	memset(&del_filter, 0, sizeof(del_filter));
+	del_filter.block_id = filter->block_id;
 	/* Gets index of the filter */
 	index = ocelot_vcap_block_get_filter_index(block, filter);
 		struct ocelot_vcap_filter *tmp;
 		tmp = ocelot_vcap_block_find_filter_by_index(block, i);
+		/* Read back the filter's counters before moving it */
+		vcap_entry_get(ocelot, i + 1, tmp);
 		vcap_entry_set(ocelot, i, tmp);
 	}

drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c+2−1

 	err = ionic_map_bars(ionic);
 	if (err)
-		goto err_out_pci_disable_device;
+		goto err_out_pci_release_regions;
 	/* Configure the device */
 	err = ionic_setup(ionic);
 err_out_unmap_bars:
 	ionic_unmap_bars(ionic);
+err_out_pci_release_regions:
 	pci_release_regions(pdev);
 err_out_pci_disable_device:
 	pci_disable_device(pdev);

drivers/net/ethernet/sfc/ef10.c+5−0

 		n_parts++;
 	}
+	if (!n_parts) {
+		kfree(parts);
+		return 0;
+	}
 	rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
 fail:
 	if (rc)

drivers/net/ethernet/sfc/efx_channels.c+6−1

 int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
 {
-	struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
+	struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel,
+			   *ptp_channel = efx_ptp_channel(efx);
+	struct efx_ptp_data *ptp_data = efx->ptp_data;
 	unsigned int i, next_buffer_table = 0;
 	u32 old_rxq_entries, old_txq_entries;
 	int rc, rc2;
 	efx_set_xdp_channels(efx);
 out:
+	efx->ptp_data = NULL;
 	/* Destroy unused channel structures */
 	for (i = 0; i < efx->n_channels; i++) {
 		channel = other_channel[i];
 		}
 	}
+	efx->ptp_data = ptp_data;
 	rc2 = efx_soft_enable_interrupts(efx);
 	if (rc2) {
 		rc = rc ? rc : rc2;
 	efx->txq_entries = old_txq_entries;
 	for (i = 0; i < efx->n_channels; i++)
 		swap(efx->channel[i], other_channel[i]);
+	efx_ptp_update_channel(efx, ptp_channel);
 	goto out;
 }

drivers/net/ethernet/sfc/ptp.c+13−1

 #include "farch_regs.h"
 #include "tx.h"
 #include "nic.h" /* indirectly includes ptp.h */
+#include "efx_channels.h"
 /* Maximum number of events expected to make up a PTP event */
 #define	MAX_EVENT_FRAGS			3
 	return efx->ptp_data ? efx->ptp_data->channel : NULL;
 }
+void efx_ptp_update_channel(struct efx_nic *efx, struct efx_channel *channel)
+{
+	if (efx->ptp_data)
+		efx->ptp_data->channel = channel;
+}
 static u32 last_sync_timestamp_major(struct efx_nic *efx)
 {
 	struct efx_channel *channel = efx_ptp_channel(efx);
 	int rc = 0;
 	unsigned int pos;
+	if (efx->ptp_data) {
+		efx->ptp_data->channel = channel;
+		return 0;
+	}
 	ptp = kzalloc(sizeof(struct efx_ptp_data), GFP_KERNEL);
 	efx->ptp_data = ptp;
 	if (!efx->ptp_data)
 	.pre_probe		= efx_ptp_probe_channel,
 	.post_remove		= efx_ptp_remove_channel,
 	.get_name		= efx_ptp_get_channel_name,
-	/* no copy operation; there is no need to reallocate this channel */
+	.copy                   = efx_copy_channel,
 	.receive_skb		= efx_ptp_rx,
 	.want_txqs		= efx_ptp_want_txqs,
 	.keep_eventq		= false,

drivers/net/ethernet/sfc/ptp.h+1−0

@@ -16,6 +16,7 @@ struct ethtool_ts_info; · 15 unmodified lines
16	int efx_ptp_probe(struct efx_nic efx, struct efx_channel channel);	16	int efx_ptp_probe(struct efx_nic efx, struct efx_channel channel);
17	void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);	17	void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
18	struct efx_channel efx_ptp_channel(struct efx_nic efx);	18	struct efx_channel efx_ptp_channel(struct efx_nic efx);
		19	void efx_ptp_update_channel(struct efx_nic efx, struct efx_channel channel);
19	void efx_ptp_remove(struct efx_nic *efx);	20	void efx_ptp_remove(struct efx_nic *efx);
20	int efx_ptp_set_ts_config(struct efx_nic efx, struct ifreq ifr);	21	int efx_ptp_set_ts_config(struct efx_nic efx, struct ifreq ifr);
21	int efx_ptp_get_ts_config(struct efx_nic efx, struct ifreq ifr);	22	int efx_ptp_get_ts_config(struct efx_nic efx, struct ifreq ifr);

drivers/net/ethernet/smsc/smsc911x.c+1−1

@@ -2431,7 +2431,7 @@ static int smsc911x_drv_probe(struct platform_device *pdev) · 2430 unmodified lines
2431	if (irq == -EPROBE_DEFER) {	2431	if (irq == -EPROBE_DEFER) {
2432	retval = -EPROBE_DEFER;	2432	retval = -EPROBE_DEFER;
2433	goto out_0;	2433	goto out_0;
2434	} else if (irq <= 0) {	2434	} else if (irq < 0) {
2435	pr_warn("Could not allocate irq resource\n");	2435	pr_warn("Could not allocate irq resource\n");
2436	retval = -ENODEV;	2436	retval = -ENODEV;
2437	goto out_0;	2437	goto out_0;

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c+1−0

@@ -454,6 +454,7 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, · 453 unmodified lines
454	plat->has_gmac4 = 1;	454	plat->has_gmac4 = 1;
455	plat->force_sf_dma_mode = 0;	455	plat->force_sf_dma_mode = 0;
456	plat->tso_en = 1;	456	plat->tso_en = 1;
		457	plat->sph_disable = 1;
457		458
458	/* Multiplying factor to the clk_eee_i clock time	459	/* Multiplying factor to the clk_eee_i clock time
459	* period to make it closer to 100 ns. This value	460	* period to make it closer to 100 ns. This value

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c+7−5

 	struct phy_device *phy_dev = ndev->phydev;
 	u32 val;
-	writew(SGMII_ADAPTER_DISABLE,
+	if (sgmii_adapter_base)
-	       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
+		writew(SGMII_ADAPTER_DISABLE,
+		       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 	if (splitter_base) {
 		val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
 		writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
 	}
-	writew(SGMII_ADAPTER_ENABLE,
+	if (phy_dev && sgmii_adapter_base) {
-	       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
+		writew(SGMII_ADAPTER_ENABLE,
-	if (phy_dev)
+		       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 		tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
+	}
 }
 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c+1−0

@@ -907,6 +907,7 @@ static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) · 906 unmodified lines
907		907
908	ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,	908	ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
909	&gmac->mux_handle, priv, priv->mii);	909	&gmac->mux_handle, priv, priv->mii);
		910	of_node_put(mdio_mux);
910	return ret;	911	return ret;
911	}	912	}
912		913

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+1−1

@@ -7021,7 +7021,7 @@ int stmmac_dvr_probe(struct device *device, · 7020 unmodified lines
7021	dev_info(priv->device, "TSO feature enabled\n");	7021	dev_info(priv->device, "TSO feature enabled\n");
7022	}	7022	}
7023		7023
7024	if (priv->dma_cap.sphen) {	7024	if (priv->dma_cap.sphen && !priv->plat->sph_disable) {
7025	ndev->hw_features \|= NETIF_F_GRO;	7025	ndev->hw_features \|= NETIF_F_GRO;
7026	priv->sph_cap = true;	7026	priv->sph_cap = true;
7027	priv->sph = priv->sph_cap;	7027	priv->sph = priv->sph_cap;

drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c+1−3

 		return -ENOMEM;
 	/* Enable pci device */
-	ret = pci_enable_device(pdev);
+	ret = pcim_enable_device(pdev);
 	if (ret) {
 		dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
 			__func__);
 		pcim_iounmap_regions(pdev, BIT(i));
 		break;
 	}
-	pci_disable_device(pdev);
 }
 static int __maybe_unused stmmac_pci_suspend(struct device *dev)

drivers/net/ethernet/ti/cpsw_new.c+4−1

 	data->slave_data = devm_kcalloc(dev, CPSW_SLAVE_PORTS_NUM,
 					sizeof(struct cpsw_slave_data),
 					GFP_KERNEL);
-	if (!data->slave_data)
+	if (!data->slave_data) {
+		of_node_put(tmp_node);
 		return -ENOMEM;
+	}
 	/* Populate all the child nodes here...
 	 */
 err_node_put:
 	of_node_put(port_np);
+	of_node_put(tmp_node);
 	return ret;
 }

drivers/net/ethernet/xilinx/xilinx_emaclite.c+12−18

@@ -823,10 +823,10 @@ static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, · 822 unmodified lines
823	static int xemaclite_mdio_setup(struct net_local lp, struct device dev)	823	static int xemaclite_mdio_setup(struct net_local lp, struct device dev)
824	{	824	{
825	struct mii_bus *bus;	825	struct mii_bus *bus;
826	int rc;
827	struct resource res;	826	struct resource res;
828	struct device_node *np = of_get_parent(lp->phy_node);	827	struct device_node *np = of_get_parent(lp->phy_node);
829	struct device_node *npp;	828	struct device_node *npp;
		829	int rc, ret;
830		830
831	/* Don't register the MDIO bus if the phy_node or its parent node	831	/* Don't register the MDIO bus if the phy_node or its parent node
832	* can't be found.	832	* can't be found.
@@ -836,8 +836,14 @@ static int xemaclite_mdio_setup(struct net_local lp, struct device dev) · 3 unmodified lines
836	return -ENODEV;	836	return -ENODEV;
837	}	837	}
838	npp = of_get_parent(np);	838	npp = of_get_parent(np);
839		839	ret = of_address_to_resource(npp, 0, &res);
840	of_address_to_resource(npp, 0, &res);	840	of_node_put(npp);
		841	if (ret) {
		842	dev_err(dev, "%s resource error!\n",
		843	dev->of_node->full_name);
		844	of_node_put(np);
		845	return ret;
		846	}
841	if (lp->ndev->mem_start != res.start) {	847	if (lp->ndev->mem_start != res.start) {
842	struct phy_device *phydev;	848	struct phy_device *phydev;
843	phydev = of_phy_find_device(lp->phy_node);	849	phydev = of_phy_find_device(lp->phy_node);
@@ -846,6 +852,7 @@ static int xemaclite_mdio_setup(struct net_local lp, struct device dev) · 2 unmodified lines
846	"MDIO of the phy is not registered yet\n");	852	"MDIO of the phy is not registered yet\n");
847	else	853	else
848	put_device(&phydev->mdio.dev);	854	put_device(&phydev->mdio.dev);
		855	of_node_put(np);
849	return 0;	856	return 0;
850	}	857	}
851		858
@@ -858,6 +865,7 @@ static int xemaclite_mdio_setup(struct net_local lp, struct device dev) · 6 unmodified lines
858	bus = mdiobus_alloc();	865	bus = mdiobus_alloc();
859	if (!bus) {	866	if (!bus) {
860	dev_err(dev, "Failed to allocate mdiobus\n");	867	dev_err(dev, "Failed to allocate mdiobus\n");
		868	of_node_put(np);
861	return -ENOMEM;	869	return -ENOMEM;
862	}	870	}
863		871
@@ -870,6 +878,7 @@ static int xemaclite_mdio_setup(struct net_local lp, struct device dev) · 6 unmodified lines
870	bus->parent = dev;	878	bus->parent = dev;
871		879
872	rc = of_mdiobus_register(bus, np);	880	rc = of_mdiobus_register(bus, np);
		881	of_node_put(np);
873	if (rc) {	882	if (rc) {
874	dev_err(dev, "Failed to register mdio bus.\n");	883	dev_err(dev, "Failed to register mdio bus.\n");
875	goto err_register;	884	goto err_register;
@@ -926,8 +935,6 @@ static int xemaclite_open(struct net_device *dev) · 50 unmodified lines
926	xemaclite_disable_interrupts(lp);	935	xemaclite_disable_interrupts(lp);
927		936
928	if (lp->phy_node) {	937	if (lp->phy_node) {
929	u32 bmcr;
930
931	lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,	938	lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
932	xemaclite_adjust_link, 0,	939	xemaclite_adjust_link, 0,
933	PHY_INTERFACE_MODE_MII);	940	PHY_INTERFACE_MODE_MII);
@@ -938,19 +945,6 @@ static int xemaclite_open(struct net_device *dev) · 4 unmodified lines
938		945
939	/* EmacLite doesn't support giga-bit speeds */	946	/* EmacLite doesn't support giga-bit speeds */
940	phy_set_max_speed(lp->phy_dev, SPEED_100);	947	phy_set_max_speed(lp->phy_dev, SPEED_100);
941
942	/* Don't advertise 1000BASE-T Full/Half duplex speeds */
943	phy_write(lp->phy_dev, MII_CTRL1000, 0);
944
945	/* Advertise only 10 and 100mbps full/half duplex speeds */
946	phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL \|
947	ADVERTISE_CSMA);
948
949	/* Restart auto negotiation */
950	bmcr = phy_read(lp->phy_dev, MII_BMCR);
951	bmcr \|= (BMCR_ANENABLE \| BMCR_ANRESTART);
952	phy_write(lp->phy_dev, MII_BMCR, bmcr);
953
954	phy_start(lp->phy_dev);	948	phy_start(lp->phy_dev);
955	}	949	}
956		950

drivers/net/mdio/mdio-mux-bcm6368.c+1−1

@@ -115,7 +115,7 @@ static int bcm6368_mdiomux_probe(struct platform_device *pdev) · 114 unmodified lines
115	md->mii_bus = devm_mdiobus_alloc(&pdev->dev);	115	md->mii_bus = devm_mdiobus_alloc(&pdev->dev);
116	if (!md->mii_bus) {	116	if (!md->mii_bus) {
117	dev_err(&pdev->dev, "mdiomux bus alloc failed\n");	117	dev_err(&pdev->dev, "mdiomux bus alloc failed\n");
118	return ENOMEM;	118	return -ENOMEM;
119	}	119	}
120		120
121	bus = md->mii_bus;	121	bus = md->mii_bus;

drivers/net/phy/marvell10g.c+1−1

@@ -880,7 +880,7 @@ static int mv3310_read_status_copper(struct phy_device *phydev) · 879 unmodified lines
880		880
881	cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);	881	cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
882	if (cssr1 < 0)	882	if (cssr1 < 0)
883	return val;	883	return cssr1;
884		884
885	/* If the link settings are not resolved, mark the link down */	885	/* If the link settings are not resolved, mark the link down */
886	if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {	886	if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {

drivers/net/phy/micrel.c+5−5

 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
 {
-	u32 data;
+	int data;
 	phy_lock_mdio_bus(phydev);
 	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
 {
-	u16 tsu_irq_status;
+	int irq_status, tsu_irq_status;
-	int irq_status;
 	irq_status = phy_read(phydev, LAN8814_INTS);
 	if (irq_status > 0 && (irq_status & LAN8814_INT_LINK))
 	.name		= "Micrel KS8737",
 	/* PHY_BASIC_FEATURES */
 	.driver_data	= &ks8737_type,
+	.probe		= kszphy_probe,
 	.config_init	= kszphy_config_init,
 	.config_intr	= kszphy_config_intr,
 	.handle_interrupt = kszphy_handle_interrupt,
 	.config_init	= ksz8061_config_init,
 	.config_intr	= kszphy_config_intr,
 	.handle_interrupt = kszphy_handle_interrupt,
-	.suspend	= kszphy_suspend,
+	.suspend	= genphy_suspend,
-	.resume		= kszphy_resume,
+	.resume		= genphy_resume,
 }, {
 	.phy_id		= PHY_ID_KSZ9021,
 	.phy_id_mask	= 0x000ffffe,

drivers/net/phy/phy.c+6−1

 {
 	struct phy_device *phydev = phy_dat;
 	struct phy_driver *drv = phydev->drv;
+	irqreturn_t ret;
-	return drv->handle_interrupt(phydev);
+	mutex_lock(&phydev->lock);
+	ret = drv->handle_interrupt(phydev);
+	mutex_unlock(&phydev->lock);
+	return ret;
 }
 /**

drivers/net/phy/sfp.c+11−1

 	struct sfp_eeprom_id id;
 	unsigned int module_power_mW;
 	unsigned int module_t_start_up;
+	bool tx_fault_ignore;
 #if IS_ENABLED(CONFIG_HWMON)
 	struct sfp_diag diag;
 	else
 		sfp->module_t_start_up = T_START_UP;
+	if (!memcmp(id.base.vendor_name, "HUAWEI          ", 16) &&
+	    !memcmp(id.base.vendor_pn, "MA5671A         ", 16))
+		sfp->tx_fault_ignore = true;
+	else
+		sfp->tx_fault_ignore = false;
 	return 0;
 }
 	mutex_lock(&sfp->st_mutex);
 	state = sfp_get_state(sfp);
 	changed = state ^ sfp->state;
-	changed &= SFP_F_PRESENT | SFP_F_LOS | SFP_F_TX_FAULT;
+	if (sfp->tx_fault_ignore)
+		changed &= SFP_F_PRESENT | SFP_F_LOS;
+	else
+		changed &= SFP_F_PRESENT | SFP_F_LOS | SFP_F_TX_FAULT;
 	for (i = 0; i < GPIO_MAX; i++)
 		if (changed & BIT(i))

drivers/net/virtio_net.c+19−1

@@ -1005,6 +1005,24 @@ static struct sk_buff receive_mergeable(struct net_device dev, · 1004 unmodified lines
1005	* xdp.data_meta were adjusted	1005	* xdp.data_meta were adjusted
1006	*/	1006	*/
1007	len = xdp.data_end - xdp.data + vi->hdr_len + metasize;	1007	len = xdp.data_end - xdp.data + vi->hdr_len + metasize;
		1008
		1009	/* recalculate headroom if xdp.data or xdp_data_meta
		1010	* were adjusted, note that offset should always point
		1011	* to the start of the reserved bytes for virtio_net
		1012	* header which are followed by xdp.data, that means
		1013	* that offset is equal to the headroom (when buf is
		1014	* starting at the beginning of the page, otherwise
		1015	* there is a base offset inside the page) but it's used
		1016	* with a different starting point (buf start) than
		1017	* xdp.data (buf start + vnet hdr size). If xdp.data or
		1018	* data_meta were adjusted by the xdp prog then the
		1019	* headroom size has changed and so has the offset, we
		1020	* can use data_hard_start, which points at buf start +
		1021	* vnet hdr size, to calculate the new headroom and use
		1022	* it later to compute buf start in page_to_skb()
		1023	*/
		1024	headroom = xdp.data - xdp.data_hard_start - metasize;
		1025
1008	/* We can only create skb based on xdp_page. */	1026	/* We can only create skb based on xdp_page. */
1009	if (unlikely(xdp_page != page)) {	1027	if (unlikely(xdp_page != page)) {
1010	rcu_read_unlock();	1028	rcu_read_unlock();
@@ -1012,7 +1030,7 @@ static struct sk_buff receive_mergeable(struct net_device dev, · 1 unmodified line
1012	head_skb = page_to_skb(vi, rq, xdp_page, offset,	1030	head_skb = page_to_skb(vi, rq, xdp_page, offset,
1013	len, PAGE_SIZE, false,	1031	len, PAGE_SIZE, false,
1014	metasize,	1032	metasize,
1015	VIRTIO_XDP_HEADROOM);	1033	headroom);
1016	return head_skb;	1034	return head_skb;
1017	}	1035	}
1018	break;	1036	break;

drivers/net/wan/cosa.c+1−1

@@ -349,7 +349,7 @@ static int __init cosa_init(void) · 348 unmodified lines
349	}	349	}
350	} else {	350	} else {
351	cosa_major = register_chrdev(0, "cosa", &cosa_fops);	351	cosa_major = register_chrdev(0, "cosa", &cosa_fops);
352	if (!cosa_major) {	352	if (cosa_major < 0) {
353	pr_warn("unable to register chardev\n");	353	pr_warn("unable to register chardev\n");
354	err = -EIO;	354	err = -EIO;
355	goto out;	355	goto out;

drivers/net/wireguard/device.c+2−1

 #include <linux/if_arp.h>
 #include <linux/icmp.h>
 #include <linux/suspend.h>
+#include <net/dst_metadata.h>
 #include <net/icmp.h>
 #include <net/rtnetlink.h>
 #include <net/ip_tunnels.h>
 		goto err_peer;
 	}
-	mtu = skb_dst(skb) ? dst_mtu(skb_dst(skb)) : dev->mtu;
+	mtu = skb_valid_dst(skb) ? dst_mtu(skb_dst(skb)) : dev->mtu;
 	__skb_queue_head_init(&packets);
 	if (!skb_is_gso(skb)) {

drivers/net/wireless/ath/ath11k/core.c+1−0

@@ -1288,6 +1288,7 @@ static void ath11k_core_restart(struct work_struct *work) · 1287 unmodified lines
1288		1288
1289	ieee80211_stop_queues(ar->hw);	1289	ieee80211_stop_queues(ar->hw);
1290	ath11k_mac_drain_tx(ar);	1290	ath11k_mac_drain_tx(ar);
		1291	complete(&ar->completed_11d_scan);
1291	complete(&ar->scan.started);	1292	complete(&ar->scan.started);
1292	complete(&ar->scan.completed);	1293	complete(&ar->scan.completed);
1293	complete(&ar->peer_assoc_done);	1294	complete(&ar->peer_assoc_done);

drivers/net/wireless/ath/ath11k/core.h+10−3

 extern unsigned int ath11k_frame_mode;
+#define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
 #define ATH11K_MON_TIMER_INTERVAL  10
 enum ath11k_supported_bw {
 	ATH11K_SCAN_ABORTING,
 };
+enum ath11k_11d_state {
+	ATH11K_11D_IDLE,
+	ATH11K_11D_PREPARING,
+	ATH11K_11D_RUNNING,
+};
 enum ath11k_dev_flags {
 	ATH11K_CAC_RUNNING,
 	ATH11K_FLAG_CORE_REGISTERED,
 	bool dfs_block_radar_events;
 	struct ath11k_thermal thermal;
 	u32 vdev_id_11d_scan;
-	struct completion finish_11d_scan;
+	struct completion completed_11d_scan;
-	struct completion finish_11d_ch_list;
+	enum ath11k_11d_state state_11d;
-	bool pending_11d;
 	bool regdom_set_by_user;
 	int hw_rate_code;
 	u8 twt_enabled;

drivers/net/wireless/ath/ath11k/mac.c+29−42

@@ -3601,26 +3601,6 @@ static int ath11k_mac_op_hw_scan(struct ieee80211_hw *hw, · 3600 unmodified lines
3601	if (ret)	3601	if (ret)
3602	goto exit;	3602	goto exit;
3603		3603
3604	/* Currently the pending_11d=true only happened 1 time while
3605	* wlan interface up in ath11k_mac_11d_scan_start(), it is called by
3606	* ath11k_mac_op_add_interface(), after wlan interface up,
3607	* pending_11d=false always.
3608	* If remove below wait, it always happened scan fail and lead connect
3609	* fail while wlan interface up, because it has a 11d scan which is running
3610	* in firmware, and lead this scan failed.
3611	*/
3612	if (ar->pending_11d) {
3613	long time_left;
3614	unsigned long timeout = 5 * HZ;
3615
3616	if (ar->supports_6ghz)
3617	timeout += 5 * HZ;
3618
3619	time_left = wait_for_completion_timeout(&ar->finish_11d_ch_list, timeout);
3620	ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
3621	"mac wait 11d channel list time left %ld\n", time_left);
3622	}
3623
3624	memset(&arg, 0, sizeof(arg));	3604	memset(&arg, 0, sizeof(arg));
3625	ath11k_wmi_start_scan_init(ar, &arg);	3605	ath11k_wmi_start_scan_init(ar, &arg);
3626	arg.vdev_id = arvif->vdev_id;	3606	arg.vdev_id = arvif->vdev_id;
@@ -3686,6 +3666,10 @@ exit: · 59 unmodified lines
3686	kfree(arg.extraie.ptr);	3666	kfree(arg.extraie.ptr);
3687		3667
3688	mutex_unlock(&ar->conf_mutex);	3668	mutex_unlock(&ar->conf_mutex);
		3669
		3670	if (ar->state_11d == ATH11K_11D_PREPARING)
		3671	ath11k_mac_11d_scan_start(ar, arvif->vdev_id);
		3672
3689	return ret;	3673	return ret;
3690	}	3674	}
3691		3675
@@ -5814,7 +5798,7 @@ static int ath11k_mac_op_start(struct ieee80211_hw *hw) · 2122 unmodified lines
5814		5798
5815	/* TODO: Do we need to enable ANI? */	5799	/* TODO: Do we need to enable ANI? */
5816		5800
5817	ath11k_reg_update_chan_list(ar);	5801	ath11k_reg_update_chan_list(ar, false);
5818		5802
5819	ar->num_started_vdevs = 0;	5803	ar->num_started_vdevs = 0;
5820	ar->num_created_vdevs = 0;	5804	ar->num_created_vdevs = 0;
@@ -5881,6 +5865,11 @@ static void ath11k_mac_op_stop(struct ieee80211_hw *hw) · 60 unmodified lines
5881	cancel_work_sync(&ar->ab->update_11d_work);	5865	cancel_work_sync(&ar->ab->update_11d_work);
5882	cancel_work_sync(&ar->ab->rfkill_work);	5866	cancel_work_sync(&ar->ab->rfkill_work);
5883		5867
		5868	if (ar->state_11d == ATH11K_11D_PREPARING) {
		5869	ar->state_11d = ATH11K_11D_IDLE;
		5870	complete(&ar->completed_11d_scan);
		5871	}
		5872
5884	spin_lock_bh(&ar->data_lock);	5873	spin_lock_bh(&ar->data_lock);
5885	list_for_each_entry_safe(ppdu_stats, tmp, &ar->ppdu_stats_info, list) {	5874	list_for_each_entry_safe(ppdu_stats, tmp, &ar->ppdu_stats_info, list) {
5886	list_del(&ppdu_stats->list);	5875	list_del(&ppdu_stats->list);
@@ -6051,7 +6040,7 @@ static bool ath11k_mac_vif_ap_active_any(struct ath11k_base *ab) · 164 unmodified lines
6051	return false;	6040	return false;
6052	}	6041	}
6053		6042
6054	void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id, bool wait)	6043	void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id)
6055	{	6044	{
6056	struct wmi_11d_scan_start_params param;	6045	struct wmi_11d_scan_start_params param;
6057	int ret;	6046	int ret;
@@ -6079,28 +6068,22 @@ void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id, bool wait) · 21 unmodified lines
6079		6068
6080	ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac start 11d scan\n");	6069	ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac start 11d scan\n");
6081		6070
6082	if (wait)
6083	reinit_completion(&ar->finish_11d_scan);
6084
6085	ret = ath11k_wmi_send_11d_scan_start_cmd(ar, &param);	6071	ret = ath11k_wmi_send_11d_scan_start_cmd(ar, &param);
6086	if (ret) {	6072	if (ret) {
6087	ath11k_warn(ar->ab, "failed to start 11d scan vdev %d ret: %d\n",	6073	ath11k_warn(ar->ab, "failed to start 11d scan vdev %d ret: %d\n",
6088	vdev_id, ret);	6074	vdev_id, ret);
6089	} else {	6075	} else {
6090	ar->vdev_id_11d_scan = vdev_id;	6076	ar->vdev_id_11d_scan = vdev_id;
6091	if (wait) {	6077	if (ar->state_11d == ATH11K_11D_PREPARING)
6092	ar->pending_11d = true;	6078	ar->state_11d = ATH11K_11D_RUNNING;
6093	ret = wait_for_completion_timeout(&ar->finish_11d_scan,
6094	5 * HZ);
6095	ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
6096	"mac 11d scan left time %d\n", ret);
6097
6098	if (!ret)
6099	ar->pending_11d = false;
6100	}
6101	}	6079	}
6102		6080
6103	fin:	6081	fin:
		6082	if (ar->state_11d == ATH11K_11D_PREPARING) {
		6083	ar->state_11d = ATH11K_11D_IDLE;
		6084	complete(&ar->completed_11d_scan);
		6085	}
		6086
6104	mutex_unlock(&ar->ab->vdev_id_11d_lock);	6087	mutex_unlock(&ar->ab->vdev_id_11d_lock);
6105	}	6088	}
6106		6089
@@ -6123,12 +6106,15 @@ void ath11k_mac_11d_scan_stop(struct ath11k *ar) · 16 unmodified lines
6123	vdev_id = ar->vdev_id_11d_scan;	6106	vdev_id = ar->vdev_id_11d_scan;
6124		6107
6125	ret = ath11k_wmi_send_11d_scan_stop_cmd(ar, vdev_id);	6108	ret = ath11k_wmi_send_11d_scan_stop_cmd(ar, vdev_id);
6126	if (ret)	6109	if (ret) {
6127	ath11k_warn(ar->ab,	6110	ath11k_warn(ar->ab,
6128	"failed to stopt 11d scan vdev %d ret: %d\n",	6111	"failed to stopt 11d scan vdev %d ret: %d\n",
6129	vdev_id, ret);	6112	vdev_id, ret);
6130	else	6113	} else {
6131	ar->vdev_id_11d_scan = ATH11K_11D_INVALID_VDEV_ID;	6114	ar->vdev_id_11d_scan = ATH11K_11D_INVALID_VDEV_ID;
		6115	ar->state_11d = ATH11K_11D_IDLE;
		6116	complete(&ar->completed_11d_scan);
		6117	}
6132	}	6118	}
6133	mutex_unlock(&ar->ab->vdev_id_11d_lock);	6119	mutex_unlock(&ar->ab->vdev_id_11d_lock);
6134	}	6120	}
@@ -6324,8 +6310,10 @@ static int ath11k_mac_op_add_interface(struct ieee80211_hw *hw, · 189 unmodified lines
6324	goto err_peer_del;	6310	goto err_peer_del;
6325	}	6311	}
6326		6312
6327	ath11k_mac_11d_scan_start(ar, arvif->vdev_id, true);	6313	if (test_bit(WMI_TLV_SERVICE_11D_OFFLOAD, ab->wmi_ab.svc_map)) {
6328		6314	reinit_completion(&ar->completed_11d_scan);
		6315	ar->state_11d = ATH11K_11D_PREPARING;
		6316	}
6329	break;	6317	break;
6330	case WMI_VDEV_TYPE_MONITOR:	6318	case WMI_VDEV_TYPE_MONITOR:
6331	set_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);	6319	set_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
@@ -7190,7 +7178,7 @@ ath11k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw, · 858 unmodified lines
7190	}	7178	}
7191		7179
7192	if (arvif->vdev_type == WMI_VDEV_TYPE_STA)	7180	if (arvif->vdev_type == WMI_VDEV_TYPE_STA)
7193	ath11k_mac_11d_scan_start(ar, arvif->vdev_id, false);	7181	ath11k_mac_11d_scan_start(ar, arvif->vdev_id);
7194		7182
7195	mutex_unlock(&ar->conf_mutex);	7183	mutex_unlock(&ar->conf_mutex);
7196	}	7184	}
@@ -8671,8 +8659,7 @@ int ath11k_mac_allocate(struct ath11k_base *ab) · 1474 unmodified lines
8671	ar->monitor_vdev_id = -1;	8659	ar->monitor_vdev_id = -1;
8672	clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);	8660	clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
8673	ar->vdev_id_11d_scan = ATH11K_11D_INVALID_VDEV_ID;	8661	ar->vdev_id_11d_scan = ATH11K_11D_INVALID_VDEV_ID;
8674	init_completion(&ar->finish_11d_scan);	8662	init_completion(&ar->completed_11d_scan);
8675	init_completion(&ar->finish_11d_ch_list);
8676	}	8663	}
8677		8664
8678	return 0;	8665	return 0;

drivers/net/wireless/ath/ath11k/mac.h+1−1

@@ -130,7 +130,7 @@ extern const struct htt_rx_ring_tlv_filter ath11k_mac_mon_status_filter_default; · 129 unmodified lines
130	#define ATH11K_SCAN_11D_INTERVAL 600000	130	#define ATH11K_SCAN_11D_INTERVAL 600000
131	#define ATH11K_11D_INVALID_VDEV_ID 0xFFFF	131	#define ATH11K_11D_INVALID_VDEV_ID 0xFFFF
132		132
133	void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id, bool wait);	133	void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id);
134	void ath11k_mac_11d_scan_stop(struct ath11k *ar);	134	void ath11k_mac_11d_scan_stop(struct ath11k *ar);
135	void ath11k_mac_11d_scan_stop_all(struct ath11k_base *ab);	135	void ath11k_mac_11d_scan_stop_all(struct ath11k_base *ab);
136		136

drivers/net/wireless/ath/ath11k/reg.c+28−15

 	ar->regdom_set_by_user = true;
 }
-int ath11k_reg_update_chan_list(struct ath11k *ar)
+int ath11k_reg_update_chan_list(struct ath11k *ar, bool wait)
 {
 	struct ieee80211_supported_band **bands;
 	struct scan_chan_list_params *params;
 	struct channel_param *ch;
 	enum nl80211_band band;
 	int num_channels = 0;
-	int i, ret;
+	int i, ret, left;
+	if (wait && ar->state_11d != ATH11K_11D_IDLE) {
+		left = wait_for_completion_timeout(&ar->completed_11d_scan,
+						   ATH11K_SCAN_TIMEOUT_HZ);
+		if (!left) {
+			ath11k_dbg(ar->ab, ATH11K_DBG_REG,
+				   "failed to receive 11d scan complete: timed out\n");
+			ar->state_11d = ATH11K_11D_IDLE;
+		}
+		ath11k_dbg(ar->ab, ATH11K_DBG_REG,
+			   "reg 11d scan wait left time %d\n", left);
+	}
+	if (wait &&
+	    (ar->scan.state == ATH11K_SCAN_STARTING ||
+	    ar->scan.state == ATH11K_SCAN_RUNNING)) {
+		left = wait_for_completion_timeout(&ar->scan.completed,
+						   ATH11K_SCAN_TIMEOUT_HZ);
+		if (!left)
+			ath11k_dbg(ar->ab, ATH11K_DBG_REG,
+				   "failed to receive hw scan complete: timed out\n");
+		ath11k_dbg(ar->ab, ATH11K_DBG_REG,
+			   "reg hw scan wait left time %d\n", left);
+	}
 	bands = hw->wiphy->bands;
 	for (band = 0; band < NUM_NL80211_BANDS; band++) {
 	ret = ath11k_wmi_send_scan_chan_list_cmd(ar, params);
 	kfree(params);
-	if (ar->pending_11d) {
-		complete(&ar->finish_11d_ch_list);
-		ar->pending_11d = false;
-	}
 	return ret;
 }
 		goto err;
 	}
-	if (ar->pending_11d)
-		complete(&ar->finish_11d_scan);
 	rtnl_lock();
 	wiphy_lock(ar->hw->wiphy);
-	if (ar->pending_11d)
-		reinit_completion(&ar->finish_11d_ch_list);
 	ret = regulatory_set_wiphy_regd_sync(ar->hw->wiphy, regd_copy);
 	wiphy_unlock(ar->hw->wiphy);
 	rtnl_unlock();
 		goto err;
 	if (ar->state == ATH11K_STATE_ON) {
-		ret = ath11k_reg_update_chan_list(ar);
+		ret = ath11k_reg_update_chan_list(ar, true);
 		if (ret)
 			goto err;
 	}

drivers/net/wireless/ath/ath11k/reg.h+1−1

@@ -32,5 +32,5 @@ struct ieee80211_regdomain * · 31 unmodified lines
32	ath11k_reg_build_regd(struct ath11k_base *ab,	32	ath11k_reg_build_regd(struct ath11k_base *ab,
33	struct cur_regulatory_info *reg_info, bool intersect);	33	struct cur_regulatory_info *reg_info, bool intersect);
34	int ath11k_regd_update(struct ath11k *ar);	34	int ath11k_regd_update(struct ath11k *ar);
35	int ath11k_reg_update_chan_list(struct ath11k *ar);	35	int ath11k_reg_update_chan_list(struct ath11k *ar, bool wait);
36	#endif	36	#endif

drivers/net/wireless/ath/ath11k/wmi.c+14−2

 {
 	/* setup commonly used values */
 	arg->scan_req_id = 1;
-	arg->scan_priority = WMI_SCAN_PRIORITY_LOW;
+	if (ar->state_11d == ATH11K_11D_PREPARING)
+		arg->scan_priority = WMI_SCAN_PRIORITY_MEDIUM;
+	else
+		arg->scan_priority = WMI_SCAN_PRIORITY_LOW;
 	arg->dwell_time_active = 50;
 	arg->dwell_time_active_2g = 0;
 	arg->dwell_time_passive = 150;
 static int ath11k_reg_11d_new_cc_event(struct ath11k_base *ab, struct sk_buff *skb)
 {
 	const struct wmi_11d_new_cc_ev *ev;
+	struct ath11k *ar;
+	struct ath11k_pdev *pdev;
 	const void **tb;
-	int ret;
+	int ret, i;
 	tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
 	if (IS_ERR(tb)) {
 	kfree(tb);
+	for (i = 0; i < ab->num_radios; i++) {
+		pdev = &ab->pdevs[i];
+		ar = pdev->ar;
+		ar->state_11d = ATH11K_11D_IDLE;
+		complete(&ar->completed_11d_scan);
+	}
 	queue_work(ab->workqueue, &ab->update_11d_work);
 	return 0;

drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c+1−1

@@ -371,7 +371,7 @@ void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) · 370 unmodified lines
371	struct iwl_dbg_tlv_timer_node node, tmp;	371	struct iwl_dbg_tlv_timer_node node, tmp;
372		372
373	list_for_each_entry_safe(node, tmp, timer_list, list) {	373	list_for_each_entry_safe(node, tmp, timer_list, list) {
374	del_timer(&node->timer);	374	del_timer_sync(&node->timer);
375	list_del(&node->list);	375	list_del(&node->list);
376	kfree(node);	376	kfree(node);
377	}	377	}

drivers/net/wireless/mac80211_hwsim.c+8−2

@@ -2202,11 +2202,14 @@ mac80211_hwsim_sta_rc_update(struct ieee80211_hw *hw, · 2201 unmodified lines
2202	if (!data->use_chanctx) {	2202	if (!data->use_chanctx) {
2203	confbw = data->bw;	2203	confbw = data->bw;
2204	} else {	2204	} else {
2205	struct ieee80211_chanctx_conf *chanctx_conf =	2205	struct ieee80211_chanctx_conf *chanctx_conf;
2206	rcu_dereference(vif->chanctx_conf);	2206
		2207	rcu_read_lock();
		2208	chanctx_conf = rcu_dereference(vif->chanctx_conf);
2207		2209
2208	if (!WARN_ON(!chanctx_conf))	2210	if (!WARN_ON(!chanctx_conf))
2209	confbw = chanctx_conf->def.width;	2211	confbw = chanctx_conf->def.width;
		2212	rcu_read_unlock();
2210	}	2213	}
2211		2214
2212	WARN(bw > hwsim_get_chanwidth(confbw),	2215	WARN(bw > hwsim_get_chanwidth(confbw),
@@ -2475,11 +2478,13 @@ static void hw_scan_work(struct work_struct *work) · 262 unmodified lines
2475	if (req->ie_len)	2478	if (req->ie_len)
2476	skb_put_data(probe, req->ie, req->ie_len);	2479	skb_put_data(probe, req->ie, req->ie_len);
2477		2480
		2481	rcu_read_lock();
2478	if (!ieee80211_tx_prepare_skb(hwsim->hw,	2482	if (!ieee80211_tx_prepare_skb(hwsim->hw,
2479	hwsim->hw_scan_vif,	2483	hwsim->hw_scan_vif,
2480	probe,	2484	probe,
2481	hwsim->tmp_chan->band,	2485	hwsim->tmp_chan->band,
2482	NULL)) {	2486	NULL)) {
		2487	rcu_read_unlock();
2483	kfree_skb(probe);	2488	kfree_skb(probe);
2484	continue;	2489	continue;
2485	}	2490	}
@@ -2487,6 +2492,7 @@ static void hw_scan_work(struct work_struct *work) · 1 unmodified line
2487	local_bh_disable();	2492	local_bh_disable();
2488	mac80211_hwsim_tx_frame(hwsim->hw, probe,	2493	mac80211_hwsim_tx_frame(hwsim->hw, probe,
2489	hwsim->tmp_chan);	2494	hwsim->tmp_chan);
		2495	rcu_read_unlock();
2490	local_bh_enable();	2496	local_bh_enable();
2491	}	2497	}
2492	}	2498	}

drivers/nfc/nfcmrvl/main.c+1−1

 {
 	struct nci_dev *ndev = priv->ndev;
+	nci_unregister_device(ndev);
 	if (priv->ndev->nfc_dev->fw_download_in_progress)
 		nfcmrvl_fw_dnld_abort(priv);
 	if (gpio_is_valid(priv->config.reset_n_io))
 		gpio_free(priv->config.reset_n_io);
-	nci_unregister_device(ndev);
 	nci_free_device(ndev);
 	kfree(priv);
 }

drivers/pci/of.c+1−7

 	dev_dbg(dev, "Parsing dma-ranges property...\n");
 	for_each_of_pci_range(&parser, &range) {
-		struct resource_entry *entry;
 		/*
 		 * If we failed translation or got a zero-sized region
 		 * then skip this range
 			goto failed;
 		}
-		/* Keep the resource list sorted */
+		pci_add_resource_offset(ib_resources, res,
-		resource_list_for_each_entry(entry, ib_resources)
-			if (entry->res->start > res->start)
-				break;
-		pci_add_resource_offset(&entry->node, res,
 					res->start - range.pci_addr);
 	}

drivers/pci/pci-driver.c+18−0

 #include <linux/of_device.h>
 #include <linux/acpi.h>
 #include <linux/dma-map-ops.h>
+#include <linux/iommu.h>
 #include "pci.h"
 #include "pcie/portdrv.h"
  */
 static int pci_dma_configure(struct device *dev)
 {
+	struct pci_driver *driver = to_pci_driver(dev->driver);
 	struct device *bridge;
 	int ret = 0;
 	}
 	pci_put_host_bridge_device(bridge);
+	if (!ret && !driver->driver_managed_dma) {
+		ret = iommu_device_use_default_domain(dev);
+		if (ret)
+			arch_teardown_dma_ops(dev);
+	}
 	return ret;
 }
+static void pci_dma_cleanup(struct device *dev)
+{
+	struct pci_driver *driver = to_pci_driver(dev->driver);
+	if (!driver->driver_managed_dma)
+		iommu_device_unuse_default_domain(dev);
+}
 struct bus_type pci_bus_type = {
 	.name		= "pci",
 	.match		= pci_bus_match,
 	.pm		= PCI_PM_OPS_PTR,
 	.num_vf		= pci_bus_num_vf,
 	.dma_configure	= pci_dma_configure,
+	.dma_cleanup	= pci_dma_cleanup,
 };
 EXPORT_SYMBOL(pci_bus_type);

drivers/pci/pci-stub.c+1−0

@@ -36,6 +36,7 @@ static struct pci_driver stub_driver = { · 35 unmodified lines
36	.name = "pci-stub",	36	.name = "pci-stub",
37	.id_table = NULL, /* only dynamic id's */	37	.id_table = NULL, /* only dynamic id's */
38	.probe = pci_stub_probe,	38	.probe = pci_stub_probe,
		39	.driver_managed_dma = true,
39	};	40	};
40		41
41	static int __init pci_stub_init(void)	42	static int __init pci_stub_init(void)

drivers/pci/pcie/portdrv_pci.c+2−0

@@ -202,6 +202,8 @@ static struct pci_driver pcie_portdriver = { · 201 unmodified lines
202		202
203	.err_handler = &pcie_portdrv_err_handler,	203	.err_handler = &pcie_portdrv_err_handler,
204		204
		205	.driver_managed_dma = true,
		206
205	.driver.pm = PCIE_PORTDRV_PM_OPS,	207	.driver.pm = PCIE_PORTDRV_PM_OPS,
206	};	208	};
207		209

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c+12−8

 	ret = clk_prepare_enable(priv->clk_ref);
 	if (ret)
-		goto err_disable_clk_ref;
+		return ret;
 	priv->reset = devm_reset_control_array_get_exclusive(dev);
-	if (IS_ERR(priv->reset))
+	if (IS_ERR(priv->reset)) {
-		return PTR_ERR(priv->reset);
+		ret = PTR_ERR(priv->reset);
+		goto err_disable_clk_ref;
+	}
 	priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops);
 	if (IS_ERR(priv->phy)) {
 		ret = PTR_ERR(priv->phy);
-		if (ret != -EPROBE_DEFER)
+		dev_err_probe(dev, ret, "failed to create PHY\n");
-			dev_err(dev, "failed to create PHY\n");
+		goto err_disable_clk_ref;
-		return ret;
 	}
 	phy_set_drvdata(priv->phy, priv);
 	phy_provider = devm_of_phy_provider_register(dev,
 						     phy_g12a_usb3_pcie_xlate);
+	if (IS_ERR(phy_provider)) {
+		ret = PTR_ERR(phy_provider);
+		goto err_disable_clk_ref;
+	}
-	return PTR_ERR_OR_ZERO(phy_provider);
+	return 0;
 err_disable_clk_ref:
 	clk_disable_unprepare(priv->clk_ref);

drivers/phy/motorola/phy-mapphone-mdm6600.c+2−1

@@ -629,7 +629,8 @@ idle: · 628 unmodified lines
629	cleanup:	629	cleanup:
630	if (error < 0)	630	if (error < 0)
631	phy_mdm6600_device_power_off(ddata);	631	phy_mdm6600_device_power_off(ddata);
632		632	pm_runtime_disable(ddata->dev);
		633	pm_runtime_dont_use_autosuspend(ddata->dev);
633	return error;	634	return error;
634	}	635	}
635		636

drivers/phy/samsung/phy-exynos5250-sata.c+15−6

 		return -EINVAL;
 	sata_phy->client = of_find_i2c_device_by_node(node);
+	of_node_put(node);
 	if (!sata_phy->client)
 		return -EPROBE_DEFER;
 	sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl");
 	if (IS_ERR(sata_phy->phyclk)) {
 		dev_err(dev, "failed to get clk for PHY\n");
-		return PTR_ERR(sata_phy->phyclk);
+		ret = PTR_ERR(sata_phy->phyclk);
+		goto put_dev;
 	}
 	ret = clk_prepare_enable(sata_phy->phyclk);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable source clk\n");
-		return ret;
+		goto put_dev;
 	}
 	sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops);
 	if (IS_ERR(sata_phy->phy)) {
-		clk_disable_unprepare(sata_phy->phyclk);
 		dev_err(dev, "failed to create PHY\n");
-		return PTR_ERR(sata_phy->phy);
+		ret = PTR_ERR(sata_phy->phy);
+		goto clk_disable;
 	}
 	phy_set_drvdata(sata_phy->phy, sata_phy);
 	phy_provider = devm_of_phy_provider_register(dev,
 					of_phy_simple_xlate);
 	if (IS_ERR(phy_provider)) {
-		clk_disable_unprepare(sata_phy->phyclk);
+		ret = PTR_ERR(phy_provider);
-		return PTR_ERR(phy_provider);
+		goto clk_disable;
 	}
 	return 0;
+clk_disable:
+	clk_disable_unprepare(sata_phy->phyclk);
+put_dev:
+	put_device(&sata_phy->client->dev);
+	return ret;
 }
 static const struct of_device_id exynos_sata_phy_of_match[] = {

drivers/phy/ti/phy-am654-serdes.c+1−1

@@ -838,7 +838,7 @@ static int serdes_am654_probe(struct platform_device *pdev) · 837 unmodified lines
838		838
839	clk_err:	839	clk_err:
840	of_clk_del_provider(node);	840	of_clk_del_provider(node);
841		841	pm_runtime_disable(dev);
842	return ret;	842	return ret;
843	}	843	}
844		844

drivers/phy/ti/phy-omap-usb2.c+1−1

@@ -215,7 +215,7 @@ static int omap_usb2_enable_clocks(struct omap_usb *phy) · 214 unmodified lines
215	return 0;	215	return 0;
216		216
217	err1:	217	err1:
218	clk_disable(phy->wkupclk);	218	clk_disable_unprepare(phy->wkupclk);
219		219
220	err0:	220	err0:
221	return ret;	221	return ret;

drivers/phy/ti/phy-ti-pipe3.c+1−0

@@ -696,6 +696,7 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) · 695 unmodified lines
696	}	696	}
697		697
698	control_pdev = of_find_device_by_node(control_node);	698	control_pdev = of_find_device_by_node(control_node);
		699	of_node_put(control_node);
699	if (!control_pdev) {	700	if (!control_pdev) {
700	dev_err(dev, "Failed to get control device\n");	701	dev_err(dev, "Failed to get control device\n");
701	return -EINVAL;	702	return -EINVAL;

drivers/phy/ti/phy-tusb1210.c+9−3

 }
 #ifdef CONFIG_POWER_SUPPLY
-const char * const tusb1210_chg_det_states[] = {
+static const char * const tusb1210_chg_det_states[] = {
 	"CHG_DET_CONNECTING",
 	"CHG_DET_START_DET",
 	"CHG_DET_READ_DET",
 	tusb1210_probe_charger_detect(tusb);
 	tusb->phy = ulpi_phy_create(ulpi, &phy_ops);
-	if (IS_ERR(tusb->phy))
+	if (IS_ERR(tusb->phy)) {
-		return PTR_ERR(tusb->phy);
+		ret = PTR_ERR(tusb->phy);
+		goto err_remove_charger;
+	}
 	phy_set_drvdata(tusb->phy, tusb);
 	ulpi_set_drvdata(ulpi, tusb);
 	return 0;
+err_remove_charger:
+	tusb1210_remove_charger_detect(tusb);
+	return ret;
 }
 static void tusb1210_remove(struct ulpi *ulpi)

drivers/pinctrl/intel/pinctrl-alderlake.c+40−20

 #include "pinctrl-intel.h"
-#define ADL_PAD_OWN	0x0a0
+#define ADL_N_PAD_OWN		0x020
-#define ADL_PADCFGLOCK	0x110
+#define ADL_N_PADCFGLOCK	0x080
-#define ADL_HOSTSW_OWN	0x150
+#define ADL_N_HOSTSW_OWN	0x0b0
-#define ADL_GPI_IS	0x200
+#define ADL_N_GPI_IS		0x100
-#define ADL_GPI_IE	0x220
+#define ADL_N_GPI_IE		0x120
+#define ADL_S_PAD_OWN		0x0a0
+#define ADL_S_PADCFGLOCK	0x110
+#define ADL_S_HOSTSW_OWN	0x150
+#define ADL_S_GPI_IS		0x200
+#define ADL_S_GPI_IE		0x220
 #define ADL_GPP(r, s, e, g)				\
 	{						\
 		.gpio_base = (g),			\
 	}
-#define ADL_COMMUNITY(b, s, e, g)			\
+#define ADL_N_COMMUNITY(b, s, e, g)			\
+	{						\
+		.barno = (b),				\
+		.padown_offset = ADL_N_PAD_OWN,		\
+		.padcfglock_offset = ADL_N_PADCFGLOCK,	\
+		.hostown_offset = ADL_N_HOSTSW_OWN,	\
+		.is_offset = ADL_N_GPI_IS,		\
+		.ie_offset = ADL_N_GPI_IE,		\
+		.pin_base = (s),			\
+		.npins = ((e) - (s) + 1),		\
+		.gpps = (g),				\
+		.ngpps = ARRAY_SIZE(g),			\
+	}
+#define ADL_S_COMMUNITY(b, s, e, g)			\
 	{						\
 		.barno = (b),				\
-		.padown_offset = ADL_PAD_OWN,		\
+		.padown_offset = ADL_S_PAD_OWN,		\
-		.padcfglock_offset = ADL_PADCFGLOCK,	\
+		.padcfglock_offset = ADL_S_PADCFGLOCK,	\
-		.hostown_offset = ADL_HOSTSW_OWN,	\
+		.hostown_offset = ADL_S_HOSTSW_OWN,	\
-		.is_offset = ADL_GPI_IS,		\
+		.is_offset = ADL_S_GPI_IS,		\
-		.ie_offset = ADL_GPI_IE,		\
+		.ie_offset = ADL_S_GPI_IE,		\
 		.pin_base = (s),			\
 		.npins = ((e) - (s) + 1),		\
 		.gpps = (g),				\
 };
 static const struct intel_community adln_communities[] = {
-	ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),
+	ADL_N_COMMUNITY(0, 0, 66, adln_community0_gpps),
-	ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),
+	ADL_N_COMMUNITY(1, 67, 168, adln_community1_gpps),
-	ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),
+	ADL_N_COMMUNITY(2, 169, 248, adln_community4_gpps),
-	ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),
+	ADL_N_COMMUNITY(3, 249, 256, adln_community5_gpps),
 };
 static const struct intel_pinctrl_soc_data adln_soc_data = {
 };
 static const struct intel_community adls_communities[] = {
-	ADL_COMMUNITY(0, 0, 94, adls_community0_gpps),
+	ADL_S_COMMUNITY(0, 0, 94, adls_community0_gpps),
-	ADL_COMMUNITY(1, 95, 150, adls_community1_gpps),
+	ADL_S_COMMUNITY(1, 95, 150, adls_community1_gpps),
-	ADL_COMMUNITY(2, 151, 199, adls_community3_gpps),
+	ADL_S_COMMUNITY(2, 151, 199, adls_community3_gpps),
-	ADL_COMMUNITY(3, 200, 269, adls_community4_gpps),
+	ADL_S_COMMUNITY(3, 200, 269, adls_community4_gpps),
-	ADL_COMMUNITY(4, 270, 303, adls_community5_gpps),
+	ADL_S_COMMUNITY(4, 270, 303, adls_community5_gpps),
 };
 static const struct intel_pinctrl_soc_data adls_soc_data = {

drivers/pinctrl/mediatek/Kconfig+1−0

@@ -30,6 +30,7 @@ config PINCTRL_MTK_MOORE · 29 unmodified lines
30	select GENERIC_PINMUX_FUNCTIONS	30	select GENERIC_PINMUX_FUNCTIONS
31	select GPIOLIB	31	select GPIOLIB
32	select OF_GPIO	32	select OF_GPIO
		33	select EINT_MTK
33	select PINCTRL_MTK_V2	34	select PINCTRL_MTK_V2
34		35
35	config PINCTRL_MTK_PARIS	36	config PINCTRL_MTK_PARIS

drivers/pinctrl/pinctrl-pistachio.c+3−3

@@ -1374,10 +1374,10 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) · 1373 unmodified lines
1374	}	1374	}
1375		1375
1376	irq = irq_of_parse_and_map(child, 0);	1376	irq = irq_of_parse_and_map(child, 0);
1377	if (irq < 0) {	1377	if (!irq) {
1378	dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);	1378	dev_err(pctl->dev, "No IRQ for bank %u\n", i);
1379	of_node_put(child);	1379	of_node_put(child);
1380	ret = irq;	1380	ret = -EINVAL;
1381	goto err;	1381	goto err;
1382	}	1382	}
1383		1383

drivers/pinctrl/pinctrl-rockchip.c+42−27

 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 	{
+		/* gpio1b6_sel */
 		.num = 1,
 		.pin = 14,
 		.reg = 0x28,
 		.bit = 12,
 		.mask = 0xf
 	}, {
+		/* gpio1b7_sel */
 		.num = 1,
 		.pin = 15,
 		.reg = 0x2c,
 		.bit = 0,
 		.mask = 0x3
 	}, {
+		/* gpio1c2_sel */
 		.num = 1,
 		.pin = 18,
 		.reg = 0x30,
 		.bit = 4,
 		.mask = 0xf
 	}, {
+		/* gpio1c3_sel */
 		.num = 1,
 		.pin = 19,
 		.reg = 0x30,
 		.bit = 8,
 		.mask = 0xf
 	}, {
+		/* gpio1c4_sel */
 		.num = 1,
 		.pin = 20,
 		.reg = 0x30,
 		.bit = 12,
 		.mask = 0xf
 	}, {
+		/* gpio1c5_sel */
 		.num = 1,
 		.pin = 21,
 		.reg = 0x34,
 		.bit = 0,
 		.mask = 0xf
 	}, {
+		/* gpio1c6_sel */
 		.num = 1,
 		.pin = 22,
 		.reg = 0x34,
 		.bit = 4,
 		.mask = 0xf
 	}, {
+		/* gpio1c7_sel */
 		.num = 1,
 		.pin = 23,
 		.reg = 0x34,
 		.bit = 8,
 		.mask = 0xf
 	}, {
-		.num = 3,
+		/* gpio2a2_sel */
-		.pin = 12,
-		.reg = 0x68,
-		.bit = 8,
-		.mask = 0xf
-	}, {
-		.num = 3,
-		.pin = 13,
-		.reg = 0x68,
-		.bit = 12,
-		.mask = 0xf
-	}, {
 		.num = 2,
 		.pin = 2,
-		.reg = 0x608,
+		.reg = 0x40,
-		.bit = 0,
+		.bit = 4,
-		.mask = 0x7
+		.mask = 0x3
 	}, {
+		/* gpio2a3_sel */
 		.num = 2,
 		.pin = 3,
-		.reg = 0x608,
+		.reg = 0x40,
-		.bit = 4,
+		.bit = 6,
-		.mask = 0x7
+		.mask = 0x3
 	}, {
+		/* gpio2c0_sel */
 		.num = 2,
 		.pin = 16,
-		.reg = 0x610,
+		.reg = 0x50,
-		.bit = 8,
+		.bit = 0,
-		.mask = 0x7
+		.mask = 0x3
 	}, {
+		/* gpio3b2_sel */
 		.num = 3,
 		.pin = 10,
-		.reg = 0x610,
+		.reg = 0x68,
-		.bit = 0,
+		.bit = 4,
-		.mask = 0x7
+		.mask = 0x3
 	}, {
+		/* gpio3b3_sel */
 		.num = 3,
 		.pin = 11,
-		.reg = 0x610,
+		.reg = 0x68,
-		.bit = 4,
+		.bit = 6,
-		.mask = 0x7
+		.mask = 0x3
+	}, {
+		/* gpio3b4_sel */
+		.num = 3,
+		.pin = 12,
+		.reg = 0x68,
+		.bit = 8,
+		.mask = 0xf
+	}, {
+		/* gpio3b5_sel */
+		.num = 3,
+		.pin = 13,
+		.reg = 0x68,
+		.bit = 12,
+		.mask = 0xf
 	},
 };

drivers/pinctrl/qcom/pinctrl-sm6350.c+8−8

@@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = { · 263 unmodified lines
264	PINCTRL_PIN(153, "GPIO_153"),	264	PINCTRL_PIN(153, "GPIO_153"),
265	PINCTRL_PIN(154, "GPIO_154"),	265	PINCTRL_PIN(154, "GPIO_154"),
266	PINCTRL_PIN(155, "GPIO_155"),	266	PINCTRL_PIN(155, "GPIO_155"),
267	PINCTRL_PIN(156, "SDC1_RCLK"),	267	PINCTRL_PIN(156, "UFS_RESET"),
268	PINCTRL_PIN(157, "SDC1_CLK"),	268	PINCTRL_PIN(157, "SDC1_RCLK"),
269	PINCTRL_PIN(158, "SDC1_CMD"),	269	PINCTRL_PIN(158, "SDC1_CLK"),
270	PINCTRL_PIN(159, "SDC1_DATA"),	270	PINCTRL_PIN(159, "SDC1_CMD"),
271	PINCTRL_PIN(160, "SDC2_CLK"),	271	PINCTRL_PIN(160, "SDC1_DATA"),
272	PINCTRL_PIN(161, "SDC2_CMD"),	272	PINCTRL_PIN(161, "SDC2_CLK"),
273	PINCTRL_PIN(162, "SDC2_DATA"),	273	PINCTRL_PIN(162, "SDC2_CMD"),
274	PINCTRL_PIN(163, "UFS_RESET"),	274	PINCTRL_PIN(163, "SDC2_DATA"),
275	};	275	};
276		276
277	#define DECLARE_MSM_GPIO_PINS(pin) \	277	#define DECLARE_MSM_GPIO_PINS(pin) \

drivers/pinctrl/samsung/Kconfig+4−7

 #
 config PINCTRL_SAMSUNG
 	bool
-	depends on OF_GPIO
+	select GPIOLIB
 	select PINMUX
 	select PINCONF
 config PINCTRL_EXYNOS
 	bool "Pinctrl common driver part for Samsung Exynos SoCs"
-	depends on OF_GPIO
+	depends on ARCH_EXYNOS || ARCH_S5PV210 || (COMPILE_TEST && OF)
-	depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST
 	select PINCTRL_SAMSUNG
 	select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
 	select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
 config PINCTRL_S3C24XX
 	bool "Samsung S3C24XX SoC pinctrl driver"
-	depends on OF_GPIO
+	depends on ARCH_S3C24XX || (COMPILE_TEST && OF)
-	depends on ARCH_S3C24XX || COMPILE_TEST
 	select PINCTRL_SAMSUNG
 config PINCTRL_S3C64XX
 	bool "Samsung S3C64XX SoC pinctrl driver"
-	depends on OF_GPIO
+	depends on ARCH_S3C64XX || (COMPILE_TEST && OF)
-	depends on ARCH_S3C64XX || COMPILE_TEST
 	select PINCTRL_SAMSUNG

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c+1−1

@@ -770,7 +770,7 @@ static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { · 769 unmodified lines
770	EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),	770	EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
771	};	771	};
772		772
773	const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {	773	static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
774	{	774	{
775	/* pin-controller instance 0 FSYS0 data */	775	/* pin-controller instance 0 FSYS0 data */
776	.pin_banks = fsd_pin_banks0,	776	.pin_banks = fsd_pin_banks0,

drivers/pinctrl/stm32/pinctrl-stm32.c+21−2

 	pinctrl_gpio_free(chip->base + offset);
 }
+static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset)
+{
+	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
+}
 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 	clk_enable(bank->clk);
-	ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
+	ret = stm32_gpio_get_noclk(chip, offset);
 	clk_disable(bank->clk);
 	struct stm32_gpio_bank *bank = d->domain->host_data;
 	int level;
+	/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
+	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
+		return;
 	/* If level interrupt type then retrig */
-	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
+	level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
 		irq_chip_retrigger_hierarchy(d);
 {
 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+	unsigned long flags;
 	int ret;
 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
 		return ret;
 	}
+	flags = irqd_get_trigger_type(irq_data);
+	if (flags & IRQ_TYPE_LEVEL_MASK)
+		clk_enable(bank->clk);
 	return 0;
 }
 {
 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
+	if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
+		clk_disable(bank->clk);
 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
 }

drivers/pinctrl/sunplus/sppctl_sp7021.c+8−0

@@ -419,7 +419,15 @@ static const struct sppctl_grp sp7021grps_prbp[] = { · 418 unmodified lines
419	EGRP("PROBE_PORT2", 2, pins_prp2),	419	EGRP("PROBE_PORT2", 2, pins_prp2),
420	};	420	};
421		421
		422	/*
		423	* Due to compatible reason, the first valid item should start at the third
		424	* position of the array. Please keep the first two items of the table
		425	* no use (dummy).
		426	*/
422	const struct sppctl_func sppctl_list_funcs[] = {	427	const struct sppctl_func sppctl_list_funcs[] = {
		428	FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
		429	FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
		430
423	FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7),	431	FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7),
424	FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7),	432	FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7),
425	FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7),	433	FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7),

drivers/platform/surface/aggregator/core.c+1−1

@@ -817,7 +817,7 @@ err_cpkg: · 816 unmodified lines
817	err_bus:	817	err_bus:
818	return status;	818	return status;
819	}	819	}
820	module_init(ssam_core_init);	820	subsys_initcall(ssam_core_init);
821		821
822	static void __exit ssam_core_exit(void)	822	static void __exit ssam_core_exit(void)
823	{	823	{

drivers/platform/surface/surface_gpe.c+8−0

@@ -99,6 +99,14 @@ static const struct dmi_system_id dmi_lid_device_table[] = { · 98 unmodified lines
99	},	99	},
100	.driver_data = (void *)lid_device_props_l4D,	100	.driver_data = (void *)lid_device_props_l4D,
101	},	101	},
		102	{
		103	.ident = "Surface Pro 8",
		104	.matches = {
		105	DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
		106	DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Surface Pro 8"),
		107	},
		108	.driver_data = (void *)lid_device_props_l4B,
		109	},
102	{	110	{
103	.ident = "Surface Book 1",	111	.ident = "Surface Book 1",
104	.matches = {	112	.matches = {

drivers/platform/x86/asus-wmi.c+10−5

 	switch (obj->type) {
 	case ACPI_TYPE_BUFFER:
-		if (obj->buffer.length > size)
+		if (obj->buffer.length > size) {
 			err = -ENOSPC;
-		if (obj->buffer.length == 0)
+			break;
+		}
+		if (obj->buffer.length == 0) {
 			err = -ENODATA;
+			break;
+		}
 		memcpy(ret_buffer, obj->buffer.pointer, obj->buffer.length);
 		break;
 	err = fan_curve_get_factory_default(asus, fan_dev);
 	if (err) {
-		if (err == -ENODEV || err == -ENODATA)
+		pr_debug("fan_curve_get_factory_default(0x%08x) failed: %d\n",
-			return 0;
+			 fan_dev, err);
-		return err;
+		/* Don't cause probe to fail on devices without fan-curves */
+		return 0;
 	}
 	*available = true;

drivers/platform/x86/dell/dell-laptop.c+13−0

@@ -80,6 +80,10 @@ static struct quirk_entry quirk_dell_inspiron_1012 = { · 79 unmodified lines
80	.kbd_led_not_present = true,	80	.kbd_led_not_present = true,
81	};	81	};
82		82
		83	static struct quirk_entry quirk_dell_latitude_7520 = {
		84	.kbd_missing_ac_tag = true,
		85	};
		86
83	static struct platform_driver platform_driver = {	87	static struct platform_driver platform_driver = {
84	.driver = {	88	.driver = {
85	.name = "dell-laptop",	89	.name = "dell-laptop",
@@ -336,6 +340,15 @@ static const struct dmi_system_id dell_quirks[] __initconst = { · 250 unmodified lines
336	},	340	},
337	.driver_data = &quirk_dell_inspiron_1012,	341	.driver_data = &quirk_dell_inspiron_1012,
338	},	342	},
		343	{
		344	.callback = dmi_matched,
		345	.ident = "Dell Latitude 7520",
		346	.matches = {
		347	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		348	DMI_MATCH(DMI_PRODUCT_NAME, "Latitude 7520"),
		349	},
		350	.driver_data = &quirk_dell_latitude_7520,
		351	},
339	{ }	352	{ }
340	};	353	};
341		354

drivers/platform/x86/gigabyte-wmi.c+1−0

@@ -148,6 +148,7 @@ static const struct dmi_system_id gigabyte_wmi_known_working_platforms[] = { · 147 unmodified lines
148	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550I AORUS PRO AX"),	148	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550I AORUS PRO AX"),
149	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M AORUS PRO-P"),	149	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M AORUS PRO-P"),
150	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M DS3H"),	150	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M DS3H"),
		151	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B660 GAMING X DDR4"),
151	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("Z390 I AORUS PRO WIFI-CF"),	152	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("Z390 I AORUS PRO WIFI-CF"),
152	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("X570 AORUS ELITE"),	153	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("X570 AORUS ELITE"),
153	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("X570 GAMING X"),	154	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("X570 GAMING X"),

drivers/platform/x86/intel/pmc/core.h+1−1

@@ -236,7 +236,7 @@ enum ppfear_regs { · 235 unmodified lines
236	#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704	236	#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704
237	#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764	237	#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764
238		238
239	const char *pmc_lpm_modes[] = {	239	static const char *pmc_lpm_modes[] = {
240	"S0i2.0",	240	"S0i2.0",
241	"S0i2.1",	241	"S0i2.1",
242	"S0i2.2",	242	"S0i2.2",

drivers/platform/x86/intel/pmt/telemetry.c+1−1

@@ -103,7 +103,7 @@ static int pmt_telem_probe(struct auxiliary_device *auxdev, const struct auxilia · 102 unmodified lines
103	auxiliary_set_drvdata(auxdev, priv);	103	auxiliary_set_drvdata(auxdev, priv);
104		104
105	for (i = 0; i < intel_vsec_dev->num_resources; i++) {	105	for (i = 0; i < intel_vsec_dev->num_resources; i++) {
106	struct intel_pmt_entry *entry = &priv->entry[i];	106	struct intel_pmt_entry *entry = &priv->entry[priv->num_entries];
107		107
108	ret = intel_pmt_dev_create(entry, &pmt_telem_ns, intel_vsec_dev, i);	108	ret = intel_pmt_dev_create(entry, &pmt_telem_ns, intel_vsec_dev, i);
109	if (ret < 0)	109	if (ret < 0)

drivers/platform/x86/intel/sdsi.c+30−14

 #define MBOX_TIMEOUT_US			2000
 #define MBOX_TIMEOUT_ACQUIRE_US		1000
 #define MBOX_POLLING_PERIOD_US		100
+#define MBOX_ACQUIRE_NUM_RETRIES	5
+#define MBOX_ACQUIRE_RETRY_DELAY_MS	500
 #define MBOX_MAX_PACKETS		4
 #define MBOX_OWNER_NONE			0x00
 struct sdsi_mbox_info {
 	u64	*payload;
-	u64	*buffer;
+	void	*buffer;
 	int	size;
 };
 	total = 0;
 	loop = 0;
 	do {
-		int offset = SDSI_SIZE_MAILBOX * loop;
+		void *buf = info->buffer + (SDSI_SIZE_MAILBOX * loop);
-		void __iomem *addr = priv->mbox_addr + offset;
-		u64 *buf = info->buffer + offset / SDSI_SIZE_CMD;
 		u32 packet_size;
 		/* Poll on ready bit */
 			break;
 		}
-		sdsi_memcpy64_fromio(buf, addr, round_up(packet_size, SDSI_SIZE_CMD));
+		sdsi_memcpy64_fromio(buf, priv->mbox_addr, round_up(packet_size, SDSI_SIZE_CMD));
 		total += packet_size;
 		  FIELD_PREP(CTRL_PACKET_SIZE, info->size);
 	writeq(control, priv->control_addr);
-	/* Poll on run_busy bit */
+	/* Poll on ready bit */
-	ret = readq_poll_timeout(priv->control_addr, control, !(control & CTRL_RUN_BUSY),
+	ret = readq_poll_timeout(priv->control_addr, control, control & CTRL_READY,
 				 MBOX_POLLING_PERIOD_US, MBOX_TIMEOUT_US);
 	if (ret)
 {
 	u64 control;
 	u32 owner;
-	int ret;
+	int ret, retries = 0;
 	lockdep_assert_held(&priv->mb_lock);
 	if (owner != MBOX_OWNER_NONE)
 		return -EBUSY;
-	/* Write first qword of payload */
+	/*
-	writeq(info->payload[0], priv->mbox_addr);
+	 * If there has been no recent transaction and no one owns the mailbox,
+	 * we should acquire it in under 1ms. However, if we've accessed it
+	 * recently it may take up to 2.1 seconds to acquire it again.
+	 */
+	do {
+		/* Write first qword of payload */
+		writeq(info->payload[0], priv->mbox_addr);
+		/* Check for ownership */
+		ret = readq_poll_timeout(priv->control_addr, control,
+			FIELD_GET(CTRL_OWNER, control) == MBOX_OWNER_INBAND,
+			MBOX_POLLING_PERIOD_US, MBOX_TIMEOUT_ACQUIRE_US);
+		if (FIELD_GET(CTRL_OWNER, control) == MBOX_OWNER_NONE &&
+		    retries++ < MBOX_ACQUIRE_NUM_RETRIES) {
+			msleep(MBOX_ACQUIRE_RETRY_DELAY_MS);
+			continue;
+		}
-	/* Check for ownership */
+		/* Either we got it or someone else did. */
-	ret = readq_poll_timeout(priv->control_addr, control,
+		break;
-				 FIELD_GET(CTRL_OWNER, control) & MBOX_OWNER_INBAND,
+	} while (true);
-				 MBOX_POLLING_PERIOD_US, MBOX_TIMEOUT_ACQUIRE_US);
 	return ret;
 }

drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c+3−0

@@ -212,6 +212,9 @@ static int __init intel_uncore_init(void) · 211 unmodified lines
212	const struct x86_cpu_id *id;	212	const struct x86_cpu_id *id;
213	int ret;	213	int ret;
214		214
		215	if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
		216	return -ENODEV;
		217
215	id = x86_match_cpu(intel_uncore_cpu_ids);	218	id = x86_match_cpu(intel_uncore_cpu_ids);
216	if (!id)	219	if (!id)
217	return -ENODEV;	220	return -ENODEV;

drivers/platform/x86/thinkpad_acpi.c+163−12

@@ -309,6 +309,20 @@ struct ibm_init_struct { · 308 unmodified lines
309	struct ibm_struct *data;	309	struct ibm_struct *data;
310	};	310	};
311		311
		312	/* DMI Quirks */
		313	struct quirk_entry {
		314	bool btusb_bug;
		315	u32 s2idle_bug_mmio;
		316	};
		317
		318	static struct quirk_entry quirk_btusb_bug = {
		319	.btusb_bug = true,
		320	};
		321
		322	static struct quirk_entry quirk_s2idle_bug = {
		323	.s2idle_bug_mmio = 0xfed80380,
		324	};
		325
312	static struct {	326	static struct {
313	u32 bluetooth:1;	327	u32 bluetooth:1;
314	u32 hotkey:1;	328	u32 hotkey:1;
@@ -338,6 +352,7 @@ static struct { · 23 unmodified lines
338	u32 hotkey_poll_active:1;	352	u32 hotkey_poll_active:1;
339	u32 has_adaptive_kbd:1;	353	u32 has_adaptive_kbd:1;
340	u32 kbd_lang:1;	354	u32 kbd_lang:1;
		355	struct quirk_entry *quirks;
341	} tp_features;	356	} tp_features;
342		357
343	static struct {	358	static struct {
@@ -4359,9 +4374,10 @@ static void bluetooth_exit(void) · 4015 unmodified lines
4359	bluetooth_shutdown();	4374	bluetooth_shutdown();
4360	}	4375	}
4361		4376
4362	static const struct dmi_system_id bt_fwbug_list[] __initconst = {	4377	static const struct dmi_system_id fwbug_list[] __initconst = {
4363	{	4378	{
4364	.ident = "ThinkPad E485",	4379	.ident = "ThinkPad E485",
		4380	.driver_data = &quirk_btusb_bug,
4365	.matches = {	4381	.matches = {
4366	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),	4382	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
4367	DMI_MATCH(DMI_BOARD_NAME, "20KU"),	4383	DMI_MATCH(DMI_BOARD_NAME, "20KU"),
@@ -4369,6 +4385,7 @@ static const struct dmi_system_id bt_fwbug_list[] __initconst = { · 1 unmodified line
4369	},	4385	},
4370	{	4386	{
4371	.ident = "ThinkPad E585",	4387	.ident = "ThinkPad E585",
		4388	.driver_data = &quirk_btusb_bug,
4372	.matches = {	4389	.matches = {
4373	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),	4390	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
4374	DMI_MATCH(DMI_BOARD_NAME, "20KV"),	4391	DMI_MATCH(DMI_BOARD_NAME, "20KV"),
@@ -4376,6 +4393,7 @@ static const struct dmi_system_id bt_fwbug_list[] __initconst = { · 1 unmodified line
4376	},	4393	},
4377	{	4394	{
4378	.ident = "ThinkPad A285 - 20MW",	4395	.ident = "ThinkPad A285 - 20MW",
		4396	.driver_data = &quirk_btusb_bug,
4379	.matches = {	4397	.matches = {
4380	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),	4398	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
4381	DMI_MATCH(DMI_BOARD_NAME, "20MW"),	4399	DMI_MATCH(DMI_BOARD_NAME, "20MW"),
@@ -4383,6 +4401,7 @@ static const struct dmi_system_id bt_fwbug_list[] __initconst = { · 1 unmodified line
4383	},	4401	},
4384	{	4402	{
4385	.ident = "ThinkPad A285 - 20MX",	4403	.ident = "ThinkPad A285 - 20MX",
		4404	.driver_data = &quirk_btusb_bug,
4386	.matches = {	4405	.matches = {
4387	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),	4406	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
4388	DMI_MATCH(DMI_BOARD_NAME, "20MX"),	4407	DMI_MATCH(DMI_BOARD_NAME, "20MX"),
@@ -4390,6 +4409,7 @@ static const struct dmi_system_id bt_fwbug_list[] __initconst = { · 1 unmodified line
4390	},	4409	},
4391	{	4410	{
4392	.ident = "ThinkPad A485 - 20MU",	4411	.ident = "ThinkPad A485 - 20MU",
		4412	.driver_data = &quirk_btusb_bug,
4393	.matches = {	4413	.matches = {
4394	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),	4414	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
4395	DMI_MATCH(DMI_BOARD_NAME, "20MU"),	4415	DMI_MATCH(DMI_BOARD_NAME, "20MU"),
@@ -4397,14 +4417,125 @@ static const struct dmi_system_id bt_fwbug_list[] __initconst = { · 1 unmodified line
4397	},	4417	},
4398	{	4418	{
4399	.ident = "ThinkPad A485 - 20MV",	4419	.ident = "ThinkPad A485 - 20MV",
		4420	.driver_data = &quirk_btusb_bug,
4400	.matches = {	4421	.matches = {
4401	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),	4422	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
4402	DMI_MATCH(DMI_BOARD_NAME, "20MV"),	4423	DMI_MATCH(DMI_BOARD_NAME, "20MV"),
4403	},	4424	},
4404	},	4425	},
		4426	{
		4427	.ident = "L14 Gen2 AMD",
		4428	.driver_data = &quirk_s2idle_bug,
		4429	.matches = {
		4430	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4431	DMI_MATCH(DMI_PRODUCT_NAME, "20X5"),
		4432	}
		4433	},
		4434	{
		4435	.ident = "T14s Gen2 AMD",
		4436	.driver_data = &quirk_s2idle_bug,
		4437	.matches = {
		4438	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4439	DMI_MATCH(DMI_PRODUCT_NAME, "20XF"),
		4440	}
		4441	},
		4442	{
		4443	.ident = "X13 Gen2 AMD",
		4444	.driver_data = &quirk_s2idle_bug,
		4445	.matches = {
		4446	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4447	DMI_MATCH(DMI_PRODUCT_NAME, "20XH"),
		4448	}
		4449	},
		4450	{
		4451	.ident = "T14 Gen2 AMD",
		4452	.driver_data = &quirk_s2idle_bug,
		4453	.matches = {
		4454	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4455	DMI_MATCH(DMI_PRODUCT_NAME, "20XK"),
		4456	}
		4457	},
		4458	{
		4459	.ident = "T14 Gen1 AMD",
		4460	.driver_data = &quirk_s2idle_bug,
		4461	.matches = {
		4462	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4463	DMI_MATCH(DMI_PRODUCT_NAME, "20UD"),
		4464	}
		4465	},
		4466	{
		4467	.ident = "T14 Gen1 AMD",
		4468	.driver_data = &quirk_s2idle_bug,
		4469	.matches = {
		4470	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4471	DMI_MATCH(DMI_PRODUCT_NAME, "20UE"),
		4472	}
		4473	},
		4474	{
		4475	.ident = "T14s Gen1 AMD",
		4476	.driver_data = &quirk_s2idle_bug,
		4477	.matches = {
		4478	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4479	DMI_MATCH(DMI_PRODUCT_NAME, "20UH"),
		4480	}
		4481	},
		4482	{
		4483	.ident = "P14s Gen1 AMD",
		4484	.driver_data = &quirk_s2idle_bug,
		4485	.matches = {
		4486	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4487	DMI_MATCH(DMI_PRODUCT_NAME, "20Y1"),
		4488	}
		4489	},
		4490	{
		4491	.ident = "P14s Gen2 AMD",
		4492	.driver_data = &quirk_s2idle_bug,
		4493	.matches = {
		4494	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
		4495	DMI_MATCH(DMI_PRODUCT_NAME, "21A0"),
		4496	}
		4497	},
4405	{}	4498	{}
4406	};	4499	};
4407		4500
		4501	#ifdef CONFIG_SUSPEND
		4502	/*
		4503	* Lenovo laptops from a variety of generations run a SMI handler during the D3->D0
		4504	* transition that occurs specifically when exiting suspend to idle which can cause
		4505	* large delays during resume when the IOMMU translation layer is enabled (the default
		4506	* behavior) for NVME devices:
		4507	*
		4508	* To avoid this firmware problem, skip the SMI handler on these machines before the
		4509	* D0 transition occurs.
		4510	*/
		4511	static void thinkpad_acpi_amd_s2idle_restore(void)
		4512	{
		4513	struct resource *res;
		4514	void __iomem *addr;
		4515	u8 val;
		4516
		4517	res = request_mem_region_muxed(tp_features.quirks->s2idle_bug_mmio, 1,
		4518	"thinkpad_acpi_pm80");
		4519	if (!res)
		4520	return;
		4521
		4522	addr = ioremap(tp_features.quirks->s2idle_bug_mmio, 1);
		4523	if (!addr)
		4524	goto cleanup_resource;
		4525
		4526	val = ioread8(addr);
		4527	iowrite8(val & ~BIT(0), addr);
		4528
		4529	iounmap(addr);
		4530	cleanup_resource:
		4531	release_resource(res);
		4532	}
		4533
		4534	static struct acpi_s2idle_dev_ops thinkpad_acpi_s2idle_dev_ops = {
		4535	.restore = thinkpad_acpi_amd_s2idle_restore,
		4536	};
		4537	#endif
		4538
4408	static const struct pci_device_id fwbug_cards_ids[] __initconst = {	4539	static const struct pci_device_id fwbug_cards_ids[] __initconst = {
4409	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x24F3) },	4540	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x24F3) },
4410	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x24FD) },	4541	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x24FD) },
@@ -4419,7 +4550,8 @@ static int __init have_bt_fwbug(void) · 8 unmodified lines
4419	* Some AMD based ThinkPads have a firmware bug that calling	4550	* Some AMD based ThinkPads have a firmware bug that calling
4420	* "GBDC" will cause bluetooth on Intel wireless cards blocked	4551	* "GBDC" will cause bluetooth on Intel wireless cards blocked
4421	*/	4552	*/
4422	if (dmi_check_system(bt_fwbug_list) && pci_dev_present(fwbug_cards_ids)) {	4553	if (tp_features.quirks && tp_features.quirks->btusb_bug &&
		4554	pci_dev_present(fwbug_cards_ids)) {
4423	vdbg_printk(TPACPI_DBG_INIT \| TPACPI_DBG_RFKILL,	4555	vdbg_printk(TPACPI_DBG_INIT \| TPACPI_DBG_RFKILL,
4424	FW_BUG "disable bluetooth subdriver for Intel cards\n");	4556	FW_BUG "disable bluetooth subdriver for Intel cards\n");
4425	return 1;	4557	return 1;
@@ -8748,24 +8880,27 @@ static int __init fan_init(struct ibm_init_struct *iibm) · 4322 unmodified lines
8748	fan_status_access_mode = TPACPI_FAN_RD_TPEC;	8880	fan_status_access_mode = TPACPI_FAN_RD_TPEC;
8749	if (quirks & TPACPI_FAN_Q1)	8881	if (quirks & TPACPI_FAN_Q1)
8750	fan_quirk1_setup();	8882	fan_quirk1_setup();
8751	if (quirks & TPACPI_FAN_2FAN) {
8752	tp_features.second_fan = 1;
8753	pr_info("secondary fan support enabled\n");
8754	}
8755	if (quirks & TPACPI_FAN_2CTL) {
8756	tp_features.second_fan = 1;
8757	tp_features.second_fan_ctl = 1;
8758	pr_info("secondary fan control enabled\n");
8759	}
8760	/* Try and probe the 2nd fan */	8883	/* Try and probe the 2nd fan */
		8884	tp_features.second_fan = 1; /* needed for get_speed to work */
8761	res = fan2_get_speed(&speed);	8885	res = fan2_get_speed(&speed);
8762	if (res >= 0) {	8886	if (res >= 0) {
8763	/* It responded - so let's assume it's there */	8887	/* It responded - so let's assume it's there */
8764	tp_features.second_fan = 1;	8888	tp_features.second_fan = 1;
8765	tp_features.second_fan_ctl = 1;	8889	tp_features.second_fan_ctl = 1;
8766	pr_info("secondary fan control detected & enabled\n");	8890	pr_info("secondary fan control detected & enabled\n");
		8891	} else {
		8892	/* Fan not auto-detected */
		8893	tp_features.second_fan = 0;
		8894	if (quirks & TPACPI_FAN_2FAN) {
		8895	tp_features.second_fan = 1;
		8896	pr_info("secondary fan support enabled\n");
		8897	}
		8898	if (quirks & TPACPI_FAN_2CTL) {
		8899	tp_features.second_fan = 1;
		8900	tp_features.second_fan_ctl = 1;
		8901	pr_info("secondary fan control enabled\n");
		8902	}
8767	}	8903	}
8768
8769	} else {	8904	} else {
8770	pr_err("ThinkPad ACPI EC access misbehaving, fan status and control unavailable\n");	8905	pr_err("ThinkPad ACPI EC access misbehaving, fan status and control unavailable\n");
8771	return -ENODEV;	8906	return -ENODEV;
@@ -11455,6 +11590,10 @@ static void thinkpad_acpi_module_exit(void) · 2683 unmodified lines
11455		11590
11456	tpacpi_lifecycle = TPACPI_LIFE_EXITING;	11591	tpacpi_lifecycle = TPACPI_LIFE_EXITING;
11457		11592
		11593	#ifdef CONFIG_SUSPEND
		11594	if (tp_features.quirks && tp_features.quirks->s2idle_bug_mmio)
		11595	acpi_unregister_lps0_dev(&thinkpad_acpi_s2idle_dev_ops);
		11596	#endif
11458	if (tpacpi_hwmon)	11597	if (tpacpi_hwmon)
11459	hwmon_device_unregister(tpacpi_hwmon);	11598	hwmon_device_unregister(tpacpi_hwmon);
11460	if (tp_features.sensors_pdrv_registered)	11599	if (tp_features.sensors_pdrv_registered)
@@ -11496,6 +11635,7 @@ static void thinkpad_acpi_module_exit(void) · 35 unmodified lines
11496		11635
11497	static int __init thinkpad_acpi_module_init(void)	11636	static int __init thinkpad_acpi_module_init(void)
11498	{	11637	{
		11638	const struct dmi_system_id *dmi_id;
11499	int ret, i;	11639	int ret, i;
11500		11640
11501	tpacpi_lifecycle = TPACPI_LIFE_INIT;	11641	tpacpi_lifecycle = TPACPI_LIFE_INIT;
@@ -11535,6 +11675,10 @@ static int __init thinkpad_acpi_module_init(void) · 33 unmodified lines
11535	return -ENODEV;	11675	return -ENODEV;
11536	}	11676	}
11537		11677
		11678	dmi_id = dmi_first_match(fwbug_list);
		11679	if (dmi_id)
		11680	tp_features.quirks = dmi_id->driver_data;
		11681
11538	/* Device initialization */	11682	/* Device initialization */
11539	tpacpi_pdev = platform_device_register_simple(TPACPI_DRVR_NAME, -1,	11683	tpacpi_pdev = platform_device_register_simple(TPACPI_DRVR_NAME, -1,
11540	NULL, 0);	11684	NULL, 0);
@@ -11623,6 +11767,13 @@ static int __init thinkpad_acpi_module_init(void) · 82 unmodified lines
11623	tp_features.input_device_registered = 1;	11767	tp_features.input_device_registered = 1;
11624	}	11768	}
11625		11769
		11770	#ifdef CONFIG_SUSPEND
		11771	if (tp_features.quirks && tp_features.quirks->s2idle_bug_mmio) {
		11772	if (!acpi_register_lps0_dev(&thinkpad_acpi_s2idle_dev_ops))
		11773	pr_info("Using s2idle quirk to avoid %s platform firmware bug\n",
		11774	(dmi_id && dmi_id->ident) ? dmi_id->ident : "");
		11775	}
		11776	#endif
11626	return 0;	11777	return 0;
11627	}	11778	}
11628		11779

drivers/ptp/ptp_ocp.c+1−1

@@ -1557,7 +1557,7 @@ ptp_ocp_signal_set(struct ptp_ocp bp, int gen, struct ptp_ocp_signal s) · 1556 unmodified lines
1557	start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;	1557	start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1558	if (!s->start) {	1558	if (!s->start) {
1559	/* roundup() does not work on 32-bit systems */	1559	/* roundup() does not work on 32-bit systems */
1560	s->start = DIV_ROUND_UP_ULL(start_ns, s->period);	1560	s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1561	s->start = ktime_add(s->start, s->phase);	1561	s->start = ktime_add(s->start, s->phase);
1562	}	1562	}
1563		1563

drivers/s390/block/dasd.c+15−3

 		if (!cqr->lpm)
 			cqr->lpm = dasd_path_get_opm(device);
 	}
+	/*
+	 * remember the amount of formatted tracks to prevent double format on
+	 * ESE devices
+	 */
+	if (cqr->block)
+		cqr->trkcount = atomic_read(&cqr->block->trkcount);
 	if (cqr->cpmode == 1) {
 		rc = ccw_device_tm_start(device->cdev, cqr->cpaddr,
 					 (long) cqr, cqr->lpm);
 	unsigned long now;
 	int nrf_suppressed = 0;
 	int fp_suppressed = 0;
+	struct request *req;
 	u8 *sense = NULL;
 	int expires;
 	}
 	if (dasd_ese_needs_format(cqr->block, irb)) {
-		if (rq_data_dir((struct request *)cqr->callback_data) == READ) {
+		req = dasd_get_callback_data(cqr);
+		if (!req) {
+			cqr->status = DASD_CQR_ERROR;
+			return;
+		}
+		if (rq_data_dir(req) == READ) {
 			device->discipline->ese_read(cqr, irb);
 			cqr->status = DASD_CQR_SUCCESS;
 			cqr->stopclk = now;
 		 * complete a request partially.
 		 */
 		if (proc_bytes) {
-			blk_update_request(req, BLK_STS_OK,
+			blk_update_request(req, BLK_STS_OK, proc_bytes);
-					   blk_rq_bytes(req) - proc_bytes);
 			blk_mq_requeue_request(req, true);
 		} else if (likely(!blk_should_fake_timeout(req->q))) {
 			blk_mq_complete_request(req);

drivers/s390/block/dasd_eckd.c+22−11

 {
 	struct pe_handler_work_data *data;
-	data = kmalloc(sizeof(*data), GFP_ATOMIC | GFP_DMA);
+	data = kzalloc(sizeof(*data), GFP_ATOMIC | GFP_DMA);
 	if (!data) {
 		if (mutex_trylock(&dasd_pe_handler_mutex)) {
 			data = pe_handler_worker;
 		} else {
 			return -ENOMEM;
 		}
-	} else {
-		memset(data, 0, sizeof(*data));
-		data->isglobal = 0;
 	}
 	INIT_WORK(&data->worker, do_pe_handler_work);
 	dasd_get_device(device);
 }
 static bool test_and_set_format_track(struct dasd_format_entry *to_format,
-				      struct dasd_block *block)
+				      struct dasd_ccw_req *cqr)
 {
+	struct dasd_block *block = cqr->block;
 	struct dasd_format_entry *format;
 	unsigned long flags;
 	bool rc = false;
 	spin_lock_irqsave(&block->format_lock, flags);
+	if (cqr->trkcount != atomic_read(&block->trkcount)) {
+		/*
+		 * The number of formatted tracks has changed after request
+		 * start and we can not tell if the current track was involved.
+		 * To avoid data corruption treat it as if the current track is
+		 * involved
+		 */
+		rc = true;
+		goto out;
+	}
 	list_for_each_entry(format, &block->format_list, list) {
 		if (format->track == to_format->track) {
 			rc = true;
 	unsigned long flags;
 	spin_lock_irqsave(&block->format_lock, flags);
+	atomic_inc(&block->trkcount);
 	list_del_init(&format->list);
 	spin_unlock_irqrestore(&block->format_lock, flags);
 }
 	sector_t curr_trk;
 	int rc;
-	req = cqr->callback_data;
+	req = dasd_get_callback_data(cqr);
 	block = cqr->block;
 	base = block->base;
 	private = base->private;
 	}
 	format->track = curr_trk;
 	/* test if track is already in formatting by another thread */
-	if (test_and_set_format_track(format, block))
+	if (test_and_set_format_track(format, cqr)) {
+		/* this is no real error so do not count down retries */
+		cqr->retries++;
 		return ERR_PTR(-EEXIST);
+	}
 	fdata.start_unit = curr_trk;
 	fdata.stop_unit = curr_trk;
 				cqr->proc_bytes = blk_count * blksize;
 				return 0;
 			}
-			if (dst && !skip_block) {
+			if (dst && !skip_block)
-				dst += off;
 				memset(dst, 0, blksize);
-			} else {
+			else
 				skip_block--;
-			}
+			dst += blksize;
 			blk_count++;
 		}
 	}

drivers/s390/block/dasd_int.h+14−0

 	void (*callback)(struct dasd_ccw_req *, void *data);
 	void *callback_data;
 	unsigned int proc_bytes;	/* bytes for partial completion */
+	unsigned int trkcount;		/* count formatted tracks */
 };
 /*
 	struct list_head format_list;
 	spinlock_t format_lock;
+	atomic_t trkcount;
 };
 struct dasd_attention_data {
 	return 0;
 }
+/*
+ * return the callback data of the original request in case there are
+ * ERP requests build on top of it
+ */
+static inline void *dasd_get_callback_data(struct dasd_ccw_req *cqr)
+{
+	while (cqr->refers)
+		cqr = cqr->refers;
+	return cqr->callback_data;
+}
 /* externals in dasd.c */
 #define DASD_PROFILE_OFF	 0
 #define DASD_PROFILE_ON 	 1

drivers/s390/net/ctcm_mpc.c+1−5

 		ctcm_clear_busy_do(dev);
 	}
-	kfree(mpcginfo);
 	return;
 }
 						CTCM_FUNTAIL, dev->name);
 			priv->stats.rx_dropped++;
 			/* mpcginfo only used for non-data transfers */
-			kfree(mpcginfo);
 			if (do_debug_data)
 				ctcmpc_dump_skb(pskb, -8);
 		}
+		kfree(mpcginfo);
 	}
 done:
 		}
 		break;
 	}
-	kfree(mpcginfo);
 	CTCM_PR_DEBUG("ctcmpc:%s() %s xid2:%i xid7:%i xidt_p2:%i \n",
 		__func__, ch->id, grp->outstanding_xid2,
 		mpc_validate_xid(mpcginfo);
 		break;
 	}
-	kfree(mpcginfo);
 	return;
 }

drivers/s390/net/ctcm_sysfs.c+3−2

 	struct ctcm_priv *priv = dev_get_drvdata(dev);
 	int rc;
-	ndev = priv->channel[CTCM_READ]->netdev;
+	if (!(priv && priv->channel[CTCM_READ] &&
-	if (!(priv && priv->channel[CTCM_READ] && ndev)) {
+	      priv->channel[CTCM_READ]->netdev)) {
 		CTCM_DBF_TEXT(SETUP, CTC_DBF_ERROR, "bfnondev");
 		return -ENODEV;
 	}
+	ndev = priv->channel[CTCM_READ]->netdev;
 	rc = kstrtouint(buf, 0, &bs1);
 	if (rc)

drivers/s390/net/lcs.c+4−3

 			lcs_schedule_recovery(card);
 			break;
 		case LCS_CMD_STOPLAN:
-			pr_warn("Stoplan for %s initiated by LGW\n",
+			if (card->dev) {
-				card->dev->name);
+				pr_warn("Stoplan for %s initiated by LGW\n",
-			if (card->dev)
+					card->dev->name);
 				netif_carrier_off(card->dev);
+			}
 			break;
 		default:
 			LCS_DBF_TEXT(5, trace, "noLGWcmd");

drivers/scsi/device_handler/scsi_dh_alua.c+1−2

 	case SCSI_ACCESS_STATE_OPTIMAL:
 	case SCSI_ACCESS_STATE_ACTIVE:
 	case SCSI_ACCESS_STATE_LBA:
-		return BLK_STS_OK;
 	case SCSI_ACCESS_STATE_TRANSITIONING:
-		return BLK_STS_AGAIN;
+		return BLK_STS_OK;
 	default:
 		req->rq_flags |= RQF_QUIET;
 		return BLK_STS_IOERR;

drivers/scsi/lpfc/lpfc_els.c+1−1

@@ -1330,7 +1330,7 @@ lpfc_issue_els_flogi(struct lpfc_vport vport, struct lpfc_nodelist ndlp, · 1329 unmodified lines
1330	if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==	1330	if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
1331	LPFC_SLI_INTF_IF_TYPE_0) {	1331	LPFC_SLI_INTF_IF_TYPE_0) {
1332	/* FLOGI needs to be 3 for WQE FCFI */	1332	/* FLOGI needs to be 3 for WQE FCFI */
1333	ct = ((SLI4_CT_FCFI >> 1) & 1) \| (SLI4_CT_FCFI & 1);	1333	ct = SLI4_CT_FCFI;
1334	bf_set(wqe_ct, &wqe->els_req.wqe_com, ct);	1334	bf_set(wqe_ct, &wqe->els_req.wqe_com, ct);
1335		1335
1336	/* Set the fcfi to the fcfi we registered with */	1336	/* Set the fcfi to the fcfi we registered with */

drivers/scsi/lpfc/lpfc_sli.c+3−3

@@ -10720,10 +10720,10 @@ __lpfc_sli_prep_gen_req_s4(struct lpfc_iocbq cmdiocbq, struct lpfc_dmabuf bmp, · 10719 unmodified lines
10720		10720
10721	/* Words 0 - 2 */	10721	/* Words 0 - 2 */
10722	bde = (struct ulp_bde64_le *)&cmdwqe->generic.bde;	10722	bde = (struct ulp_bde64_le *)&cmdwqe->generic.bde;
10723	bde->addr_low = cpu_to_le32(putPaddrLow(bmp->phys));	10723	bde->addr_low = bpl->addr_low;
10724	bde->addr_high = cpu_to_le32(putPaddrHigh(bmp->phys));	10724	bde->addr_high = bpl->addr_high;
10725	bde->type_size = cpu_to_le32(xmit_len);	10725	bde->type_size = cpu_to_le32(xmit_len);
10726	bde->type_size \|= cpu_to_le32(ULP_BDE64_TYPE_BLP_64);	10726	bde->type_size \|= cpu_to_le32(ULP_BDE64_TYPE_BDE_64);
10727		10727
10728	/* Word 3 */	10728	/* Word 3 */
10729	cmdwqe->gen_req.request_payload_len = xmit_len;	10729	cmdwqe->gen_req.request_payload_len = xmit_len;

drivers/scsi/qla2xxx/qla_target.c+3−0

@@ -3826,6 +3826,9 @@ int qlt_abort_cmd(struct qla_tgt_cmd *cmd) · 3825 unmodified lines
3826		3826
3827	spin_lock_irqsave(&cmd->cmd_lock, flags);	3827	spin_lock_irqsave(&cmd->cmd_lock, flags);
3828	if (cmd->aborted) {	3828	if (cmd->aborted) {
		3829	if (cmd->sg_mapped)
		3830	qlt_unmap_sg(vha, cmd);
		3831
3829	spin_unlock_irqrestore(&cmd->cmd_lock, flags);	3832	spin_unlock_irqrestore(&cmd->cmd_lock, flags);
3830	/*	3833	/*
3831	* It's normal to see 2 calls in this path:	3834	* It's normal to see 2 calls in this path:

drivers/slimbus/qcom-ctrl.c+2−2

@@ -510,9 +510,9 @@ static int qcom_slim_probe(struct platform_device *pdev) · 509 unmodified lines
510	}	510	}
511		511
512	ctrl->irq = platform_get_irq(pdev, 0);	512	ctrl->irq = platform_get_irq(pdev, 0);
513	if (!ctrl->irq) {	513	if (ctrl->irq < 0) {
514	dev_err(&pdev->dev, "no slimbus IRQ\n");	514	dev_err(&pdev->dev, "no slimbus IRQ\n");
515	return -ENODEV;	515	return ctrl->irq;
516	}	516	}
517		517
518	sctrl = &ctrl->ctrl;	518	sctrl = &ctrl->ctrl;

drivers/soc/imx/imx8m-blk-ctrl.c+1−1

@@ -50,7 +50,7 @@ struct imx8m_blk_ctrl_domain_data { · 49 unmodified lines
50	u32 mipi_phy_rst_mask;	50	u32 mipi_phy_rst_mask;
51	};	51	};
52		52
53	#define DOMAIN_MAX_CLKS 3	53	#define DOMAIN_MAX_CLKS 4
54		54
55	struct imx8m_blk_ctrl_domain {	55	struct imx8m_blk_ctrl_domain {
56	struct generic_pm_domain genpd;	56	struct generic_pm_domain genpd;

drivers/target/target_core_pscsi.c+5−5

 }
 static void pscsi_complete_cmd(struct se_cmd *cmd, u8 scsi_status,
-			       unsigned char *req_sense)
+			       unsigned char *req_sense, int valid_data)
 {
 	struct pscsi_dev_virt *pdv = PSCSI_DEV(cmd->se_dev);
 	struct scsi_device *sd = pdv->pdv_sd;
 		 * back despite framework assumption that a
 		 * check condition means there is no data
 		 */
-		if (sd->type == TYPE_TAPE &&
+		if (sd->type == TYPE_TAPE && valid_data &&
 		    cmd->data_direction == DMA_FROM_DEVICE) {
 			/*
 			 * is sense data valid, fixed format,
 	struct se_cmd *cmd = req->end_io_data;
 	struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(req);
 	enum sam_status scsi_status = scmd->result & 0xff;
+	int valid_data = cmd->data_length - scmd->resid_len;
 	u8 *cdb = cmd->priv;
 	if (scsi_status != SAM_STAT_GOOD) {
 			" 0x%02x Result: 0x%08x\n", cmd, cdb[0], scmd->result);
 	}
-	pscsi_complete_cmd(cmd, scsi_status, scmd->sense_buffer);
+	pscsi_complete_cmd(cmd, scsi_status, scmd->sense_buffer, valid_data);
 	switch (host_byte(scmd->result)) {
 	case DID_OK:
-		target_complete_cmd_with_length(cmd, scsi_status,
+		target_complete_cmd_with_length(cmd, scsi_status, valid_data);
-			cmd->data_length - scmd->resid_len);
 		break;
 	default:
 		pr_debug("PSCSI Host Byte exception at cmd: %p CDB:"

drivers/tee/optee/ffa_abi.c+1−0

@@ -865,6 +865,7 @@ err_rhashtable_free: · 864 unmodified lines
865	rhashtable_free_and_destroy(&optee->ffa.global_ids, rh_free_fn, NULL);	865	rhashtable_free_and_destroy(&optee->ffa.global_ids, rh_free_fn, NULL);
866	optee_supp_uninit(&optee->supp);	866	optee_supp_uninit(&optee->supp);
867	mutex_destroy(&optee->call_queue.mutex);	867	mutex_destroy(&optee->call_queue.mutex);
		868	mutex_destroy(&optee->ffa.mutex);
868	err_unreg_supp_teedev:	869	err_unreg_supp_teedev:
869	tee_device_unregister(optee->supp_teedev);	870	tee_device_unregister(optee->supp_teedev);
870	err_unreg_teedev:	871	err_unreg_teedev:

drivers/thermal/Kconfig+4−2

 	bool "user_space"
 	select THERMAL_GOV_USER_SPACE
 	help
-	  Select this if you want to let the user space manage the
+	  The Userspace governor allows to get trip point crossed
-	  platform thermals.
+	  notification from the kernel via uevents. It is recommended
+	  to use the netlink interface instead which gives richer
+	  information about the thermal framework events.
 config THERMAL_DEFAULT_GOV_POWER_ALLOCATOR
 	bool "power_allocator"

drivers/thermal/gov_user_space.c+1−2

@@ -17,8 +17,7 @@ · 16 unmodified lines
17		17
18	static int user_space_bind(struct thermal_zone_device *tz)	18	static int user_space_bind(struct thermal_zone_device *tz)
19	{	19	{
20	pr_warn_once("Userspace governor deprecated: use thermal netlink " \	20	pr_info_once("Consider using thermal netlink events interface\n");
21	"notification instead\n");
22		21
23	return 0;	22	return 0;
24	}	23	}

drivers/thermal/intel/int340x_thermal/int3400_thermal.c+2−2

@@ -68,7 +68,7 @@ static int evaluate_odvp(struct int3400_thermal_priv *priv); · 67 unmodified lines
68	struct odvp_attr {	68	struct odvp_attr {
69	int odvp;	69	int odvp;
70	struct int3400_thermal_priv *priv;	70	struct int3400_thermal_priv *priv;
71	struct kobj_attribute attr;	71	struct device_attribute attr;
72	};	72	};
73		73
74	static ssize_t data_vault_read(struct file file, struct kobject kobj,	74	static ssize_t data_vault_read(struct file file, struct kobject kobj,
@@ -311,7 +311,7 @@ end: · 236 unmodified lines
311	return result;	311	return result;
312	}	312	}
313		313
314	static ssize_t odvp_show(struct kobject kobj, struct kobj_attribute attr,	314	static ssize_t odvp_show(struct device dev, struct device_attribute attr,
315	char *buf)	315	char *buf)
316	{	316	{
317	struct odvp_attr *odvp_attr;	317	struct odvp_attr *odvp_attr;

drivers/thermal/thermal_sysfs.c+0−3

@@ -610,9 +610,6 @@ cur_state_store(struct device dev, struct device_attribute attr, · 609 unmodified lines
610	unsigned long state;	610	unsigned long state;
611	int result;	611	int result;
612		612
613	dev_warn_once(&cdev->device,
614	"Setting cooling device state is deprecated\n");
615
616	if (sscanf(buf, "%ld\n", &state) != 1)	613	if (sscanf(buf, "%ld\n", &state) != 1)
617	return -EINVAL;	614	return -EINVAL;
618		615

drivers/thunderbolt/domain.c+3−9

@@ -7,9 +7,7 @@ · 6 unmodified lines
7	*/	7	*/
8		8
9	#include <linux/device.h>	9	#include <linux/device.h>
10	#include <linux/dmar.h>
11	#include <linux/idr.h>	10	#include <linux/idr.h>
12	#include <linux/iommu.h>
13	#include <linux/module.h>	11	#include <linux/module.h>
14	#include <linux/pm_runtime.h>	12	#include <linux/pm_runtime.h>
15	#include <linux/slab.h>	13	#include <linux/slab.h>
@@ -257,13 +255,9 @@ static ssize_t iommu_dma_protection_show(struct device *dev, · 241 unmodified lines
257	struct device_attribute *attr,	255	struct device_attribute *attr,
258	char *buf)	256	char *buf)
259	{	257	{
260	/*	258	struct tb *tb = container_of(dev, struct tb, dev);
261	* Kernel DMA protection is a feature where Thunderbolt security is	259
262	* handled natively using IOMMU. It is enabled when IOMMU is	260	return sysfs_emit(buf, "%d\n", tb->nhi->iommu_dma_protection);
263	* enabled and ACPI DMAR table has DMAR_PLATFORM_OPT_IN set.
264	*/
265	return sprintf(buf, "%d\n",
266	iommu_present(&pci_bus_type) && dmar_platform_optin());
267	}	261	}
268	static DEVICE_ATTR_RO(iommu_dma_protection);	262	static DEVICE_ATTR_RO(iommu_dma_protection);
269		263

drivers/thunderbolt/nhi.c+44−0

@@ -15,9 +15,11 @@ · 14 unmodified lines
15	#include <linux/pci.h>	15	#include <linux/pci.h>
16	#include <linux/dma-mapping.h>	16	#include <linux/dma-mapping.h>
17	#include <linux/interrupt.h>	17	#include <linux/interrupt.h>
		18	#include <linux/iommu.h>
18	#include <linux/module.h>	19	#include <linux/module.h>
19	#include <linux/delay.h>	20	#include <linux/delay.h>
20	#include <linux/property.h>	21	#include <linux/property.h>
		22	#include <linux/string_helpers.h>
21		23
22	#include "nhi.h"	24	#include "nhi.h"
23	#include "nhi_regs.h"	25	#include "nhi_regs.h"
@@ -1103,6 +1105,47 @@ static void nhi_check_quirks(struct tb_nhi *nhi) · 1079 unmodified lines
1103	nhi->quirks \|= QUIRK_AUTO_CLEAR_INT;	1105	nhi->quirks \|= QUIRK_AUTO_CLEAR_INT;
1104	}	1106	}
1105		1107
		1108	static int nhi_check_iommu_pdev(struct pci_dev pdev, void data)
		1109	{
		1110	if (!pdev->external_facing \|\|
		1111	!device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION))
		1112	return 0;
		1113	(bool )data = true;
		1114	return 1; /* Stop walking */
		1115	}
		1116
		1117	static void nhi_check_iommu(struct tb_nhi *nhi)
		1118	{
		1119	struct pci_bus *bus = nhi->pdev->bus;
		1120	bool port_ok = false;
		1121
		1122	/*
		1123	* Ideally what we'd do here is grab every PCI device that
		1124	* represents a tunnelling adapter for this NHI and check their
		1125	* status directly, but unfortunately USB4 seems to make it
		1126	* obnoxiously difficult to reliably make any correlation.
		1127	*
		1128	* So for now we'll have to bodge it... Hoping that the system
		1129	* is at least sane enough that an adapter is in the same PCI
		1130	* segment as its NHI, if we can find something on that segment
		1131	* which meets the requirements for Kernel DMA Protection, we'll
		1132	* take that to imply that firmware is aware and has (hopefully)
		1133	* done the right thing in general. We need to know that the PCI
		1134	* layer has seen the ExternalFacingPort property which will then
		1135	* inform the IOMMU layer to enforce the complete "untrusted DMA"
		1136	* flow, but also that the IOMMU driver itself can be trusted not
		1137	* to have been subverted by a pre-boot DMA attack.
		1138	*/
		1139	while (bus->parent)
		1140	bus = bus->parent;
		1141
		1142	pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok);
		1143
		1144	nhi->iommu_dma_protection = port_ok;
		1145	dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n",
		1146	str_enabled_disabled(port_ok));
		1147	}
		1148
1106	static int nhi_init_msi(struct tb_nhi *nhi)	1149	static int nhi_init_msi(struct tb_nhi *nhi)
1107	{	1150	{
1108	struct pci_dev *pdev = nhi->pdev;	1151	struct pci_dev *pdev = nhi->pdev;
@@ -1220,6 +1263,7 @@ static int nhi_probe(struct pci_dev pdev, const struct pci_device_id id) · 111 unmodified lines
1220	return -ENOMEM;	1263	return -ENOMEM;
1221		1264
1222	nhi_check_quirks(nhi);	1265	nhi_check_quirks(nhi);
		1266	nhi_check_iommu(nhi);
1223		1267
1224	res = nhi_init_msi(nhi);	1268	res = nhi_init_msi(nhi);
1225	if (res) {	1269	if (res) {

drivers/tty/n_gsm.c+287−208

@@ -73,6 +73,8 @@ module_param(debug, int, 0600); · 72 unmodified lines
73	*/	73	*/
74	#define MAX_MRU 1500	74	#define MAX_MRU 1500
75	#define MAX_MTU 1500	75	#define MAX_MTU 1500
		76	/* SOF, ADDR, CTRL, LEN1, LEN2, ..., FCS, EOF */
		77	#define PROT_OVERHEAD 7
76	#define GSM_NET_TX_TIMEOUT (HZ*10)	78	#define GSM_NET_TX_TIMEOUT (HZ*10)
77		79
78	/*	80	/*
@@ -135,6 +137,7 @@ struct gsm_dlci { · 56 unmodified lines
135	int retries;	137	int retries;
136	/* Uplink tty if active */	138	/* Uplink tty if active */
137	struct tty_port port; /* The tty bound to this DLCI if there is one */	139	struct tty_port port; /* The tty bound to this DLCI if there is one */
		140	#define TX_SIZE 4096 /* Must be power of 2. */
138	struct kfifo fifo; /* Queue fifo for the DLCI */	141	struct kfifo fifo; /* Queue fifo for the DLCI */
139	int adaption; /* Adaption layer in use */	142	int adaption; /* Adaption layer in use */
140	int prev_adaption;	143	int prev_adaption;
@@ -219,7 +222,6 @@ struct gsm_mux { · 78 unmodified lines
219	int encoding;	222	int encoding;
220	u8 control;	223	u8 control;
221	u8 fcs;	224	u8 fcs;
222	u8 received_fcs;
223	u8 txframe; / TX framing buffer */	225	u8 txframe; / TX framing buffer */
224		226
225	/* Method for the receiver side */	227	/* Method for the receiver side */
@@ -231,6 +233,7 @@ struct gsm_mux { · 5 unmodified lines
231	int initiator; /* Did we initiate connection */	233	int initiator; /* Did we initiate connection */
232	bool dead; /* Has the mux been shut down */	234	bool dead; /* Has the mux been shut down */
233	struct gsm_dlci *dlci[NUM_DLCI];	235	struct gsm_dlci *dlci[NUM_DLCI];
		236	int old_c_iflag; /* termios c_iflag value before attach */
234	bool constipated; /* Asked by remote to shut up */	237	bool constipated; /* Asked by remote to shut up */
235		238
236	spinlock_t tx_lock;	239	spinlock_t tx_lock;
@@ -271,10 +274,6 @@ static DEFINE_SPINLOCK(gsm_mux_lock); · 34 unmodified lines
271		274
272	static struct tty_driver *gsm_tty_driver;	275	static struct tty_driver *gsm_tty_driver;
273		276
274	/* Save dlci open address */
275	static int addr_open[256] = { 0 };
276	/* Save dlci open count */
277	static int addr_cnt;
278	/*	277	/*
279	* This section of the driver logic implements the GSM encodings	278	* This section of the driver logic implements the GSM encodings
280	* both the basic and the 'advanced'. Reliable transport is not	279	* both the basic and the 'advanced'. Reliable transport is not
@@ -369,6 +368,7 @@ static const u8 gsm_fcs8[256] = { · 88 unmodified lines
369	#define GOOD_FCS 0xCF	368	#define GOOD_FCS 0xCF
370		369
371	static int gsmld_output(struct gsm_mux gsm, u8 data, int len);	370	static int gsmld_output(struct gsm_mux gsm, u8 data, int len);
		371	static int gsm_modem_update(struct gsm_dlci *dlci, u8 brk);
372		372
373	/**	373	/**
374	* gsm_fcs_add - update FCS	374	* gsm_fcs_add - update FCS
@@ -832,7 +832,7 @@ static int gsm_dlci_data_output(struct gsm_mux gsm, struct gsm_dlci dlci) · 457 unmodified lines
832	break;	832	break;
833	case 2: /* Unstructed with modem bits.	833	case 2: /* Unstructed with modem bits.
834	Always one byte as we never send inline break data */	834	Always one byte as we never send inline break data */
835	*dp++ = gsm_encode_modem(dlci);	835	*dp++ = (gsm_encode_modem(dlci) << 1) \| EA;
836	break;	836	break;
837	}	837	}
838	WARN_ON(kfifo_out_locked(&dlci->fifo, dp , len, &dlci->lock) != len);	838	WARN_ON(kfifo_out_locked(&dlci->fifo, dp , len, &dlci->lock) != len);
@@ -916,6 +916,66 @@ static int gsm_dlci_data_output_framed(struct gsm_mux *gsm, · 77 unmodified lines
916	return size;	916	return size;
917	}	917	}
918		918
		919	/**
		920	* gsm_dlci_modem_output - try and push modem status out of a DLCI
		921	* @gsm: mux
		922	* @dlci: the DLCI to pull modem status from
		923	* @brk: break signal
		924	*
		925	* Push an empty frame in to the transmit queue to update the modem status
		926	* bits and to transmit an optional break.
		927	*
		928	* Caller must hold the tx_lock of the mux.
		929	*/
		930
		931	static int gsm_dlci_modem_output(struct gsm_mux gsm, struct gsm_dlci dlci,
		932	u8 brk)
		933	{
		934	u8 *dp = NULL;
		935	struct gsm_msg *msg;
		936	int size = 0;
		937
		938	/* for modem bits without break data */
		939	switch (dlci->adaption) {
		940	case 1: /* Unstructured */
		941	break;
		942	case 2: /* Unstructured with modem bits. */
		943	size++;
		944	if (brk > 0)
		945	size++;
		946	break;
		947	default:
		948	pr_err("%s: unsupported adaption %d\n", __func__,
		949	dlci->adaption);
		950	return -EINVAL;
		951	}
		952
		953	msg = gsm_data_alloc(gsm, dlci->addr, size, gsm->ftype);
		954	if (!msg) {
		955	pr_err("%s: gsm_data_alloc error", __func__);
		956	return -ENOMEM;
		957	}
		958	dp = msg->data;
		959	switch (dlci->adaption) {
		960	case 1: /* Unstructured */
		961	break;
		962	case 2: /* Unstructured with modem bits. */
		963	if (brk == 0) {
		964	*dp++ = (gsm_encode_modem(dlci) << 1) \| EA;
		965	} else {
		966	*dp++ = gsm_encode_modem(dlci) << 1;
		967	dp++ = (brk << 4) \| 2 \| EA; / Length, Break, EA */
		968	}
		969	break;
		970	default:
		971	/* Handled above */
		972	break;
		973	}
		974
		975	__gsm_data_queue(dlci, msg);
		976	return size;
		977	}
		978
919	/**	979	/**
920	* gsm_dlci_data_sweep - look for data to send	980	* gsm_dlci_data_sweep - look for data to send
921	* @gsm: the GSM mux	981	* @gsm: the GSM mux
@@ -1093,7 +1153,6 @@ static void gsm_control_modem(struct gsm_mux gsm, const u8 data, int clen) · 171 unmodified lines
1093	{	1153	{
1094	unsigned int addr = 0;	1154	unsigned int addr = 0;
1095	unsigned int modem = 0;	1155	unsigned int modem = 0;
1096	unsigned int brk = 0;
1097	struct gsm_dlci *dlci;	1156	struct gsm_dlci *dlci;
1098	int len = clen;	1157	int len = clen;
1099	int slen;	1158	int slen;
@@ -1123,17 +1182,8 @@ static void gsm_control_modem(struct gsm_mux gsm, const u8 data, int clen) · 23 unmodified lines
1123	return;	1182	return;
1124	}	1183	}
1125	len--;	1184	len--;
1126	if (len > 0) {
1127	while (gsm_read_ea(&brk, *dp++) == 0) {
1128	len--;
1129	if (len == 0)
1130	return;
1131	}
1132	modem <<= 7;
1133	modem \|= (brk & 0x7f);
1134	}
1135	tty = tty_port_tty_get(&dlci->port);	1185	tty = tty_port_tty_get(&dlci->port);
1136	gsm_process_modem(tty, dlci, modem, slen);	1186	gsm_process_modem(tty, dlci, modem, slen - len);
1137	if (tty) {	1187	if (tty) {
1138	tty_wakeup(tty);	1188	tty_wakeup(tty);
1139	tty_kref_put(tty);	1189	tty_kref_put(tty);
@@ -1193,7 +1243,6 @@ static void gsm_control_rls(struct gsm_mux gsm, const u8 data, int clen) · 53 unmodified lines
1193	}	1243	}
1194		1244
1195	static void gsm_dlci_begin_close(struct gsm_dlci *dlci);	1245	static void gsm_dlci_begin_close(struct gsm_dlci *dlci);
1196	static void gsm_dlci_close(struct gsm_dlci *dlci);
1197		1246
1198	/**	1247	/**
1199	* gsm_control_message - DLCI 0 control processing	1248	* gsm_control_message - DLCI 0 control processing
@@ -1212,28 +1261,15 @@ static void gsm_control_message(struct gsm_mux *gsm, unsigned int command, · 12 unmodified lines
1212	{	1261	{
1213	u8 buf[1];	1262	u8 buf[1];
1214	unsigned long flags;	1263	unsigned long flags;
1215	struct gsm_dlci *dlci;
1216	int i;
1217	int address;
1218		1264
1219	switch (command) {	1265	switch (command) {
1220	case CMD_CLD: {	1266	case CMD_CLD: {
1221	if (addr_cnt > 0) {	1267	struct gsm_dlci *dlci = gsm->dlci[0];
1222	for (i = 0; i < addr_cnt; i++) {
1223	address = addr_open[i];
1224	dlci = gsm->dlci[address];
1225	gsm_dlci_close(dlci);
1226	addr_open[i] = 0;
1227	}
1228	}
1229	/* Modem wishes to close down */	1268	/* Modem wishes to close down */
1230	dlci = gsm->dlci[0];
1231	if (dlci) {	1269	if (dlci) {
1232	dlci->dead = true;	1270	dlci->dead = true;
1233	gsm->dead = true;	1271	gsm->dead = true;
1234	gsm_dlci_close(dlci);	1272	gsm_dlci_begin_close(dlci);
1235	addr_cnt = 0;
1236	gsm_response(gsm, 0, UA\|PF);
1237	}	1273	}
1238	}	1274	}
1239	break;	1275	break;
@@ -1326,11 +1362,12 @@ static void gsm_control_response(struct gsm_mux *gsm, unsigned int command, · 86 unmodified lines
1326		1362
1327	static void gsm_control_transmit(struct gsm_mux gsm, struct gsm_control ctrl)	1363	static void gsm_control_transmit(struct gsm_mux gsm, struct gsm_control ctrl)
1328	{	1364	{
1329	struct gsm_msg *msg = gsm_data_alloc(gsm, 0, ctrl->len + 1, gsm->ftype);	1365	struct gsm_msg *msg = gsm_data_alloc(gsm, 0, ctrl->len + 2, gsm->ftype);
1330	if (msg == NULL)	1366	if (msg == NULL)
1331	return;	1367	return;
1332	msg->data[0] = (ctrl->cmd << 1) \| 2 \| EA; /* command */	1368	msg->data[0] = (ctrl->cmd << 1) \| CR \| EA; /* command */
1333	memcpy(msg->data + 1, ctrl->data, ctrl->len);	1369	msg->data[1] = (ctrl->len << 1) \| EA;
		1370	memcpy(msg->data + 2, ctrl->data, ctrl->len);
1334	gsm_data_queue(gsm->dlci[0], msg);	1371	gsm_data_queue(gsm->dlci[0], msg);
1335	}	1372	}
1336		1373
@@ -1353,7 +1390,6 @@ static void gsm_control_retransmit(struct timer_list *t) · 16 unmodified lines
1353	spin_lock_irqsave(&gsm->control_lock, flags);	1390	spin_lock_irqsave(&gsm->control_lock, flags);
1354	ctrl = gsm->pending_cmd;	1391	ctrl = gsm->pending_cmd;
1355	if (ctrl) {	1392	if (ctrl) {
1356	gsm->cretries--;
1357	if (gsm->cretries == 0) {	1393	if (gsm->cretries == 0) {
1358	gsm->pending_cmd = NULL;	1394	gsm->pending_cmd = NULL;
1359	ctrl->error = -ETIMEDOUT;	1395	ctrl->error = -ETIMEDOUT;
@@ -1362,6 +1398,7 @@ static void gsm_control_retransmit(struct timer_list *t) · 2 unmodified lines
1362	wake_up(&gsm->event);	1398	wake_up(&gsm->event);
1363	return;	1399	return;
1364	}	1400	}
		1401	gsm->cretries--;
1365	gsm_control_transmit(gsm, ctrl);	1402	gsm_control_transmit(gsm, ctrl);
1366	mod_timer(&gsm->t2_timer, jiffies + gsm->t2 * HZ / 100);	1403	mod_timer(&gsm->t2_timer, jiffies + gsm->t2 * HZ / 100);
1367	}	1404	}
@@ -1402,7 +1439,7 @@ retry: · 34 unmodified lines
1402		1439
1403	/* If DLCI0 is in ADM mode skip retries, it won't respond */	1440	/* If DLCI0 is in ADM mode skip retries, it won't respond */
1404	if (gsm->dlci[0]->mode == DLCI_MODE_ADM)	1441	if (gsm->dlci[0]->mode == DLCI_MODE_ADM)
1405	gsm->cretries = 1;	1442	gsm->cretries = 0;
1406	else	1443	else
1407	gsm->cretries = gsm->n2;	1444	gsm->cretries = gsm->n2;
1408		1445
@@ -1450,20 +1487,22 @@ static int gsm_control_wait(struct gsm_mux gsm, struct gsm_control control) · 41 unmodified lines
1450		1487
1451	static void gsm_dlci_close(struct gsm_dlci *dlci)	1488	static void gsm_dlci_close(struct gsm_dlci *dlci)
1452	{	1489	{
		1490	unsigned long flags;
		1491
1453	del_timer(&dlci->t1);	1492	del_timer(&dlci->t1);
1454	if (debug & 8)	1493	if (debug & 8)
1455	pr_debug("DLCI %d goes closed.\n", dlci->addr);	1494	pr_debug("DLCI %d goes closed.\n", dlci->addr);
1456	dlci->state = DLCI_CLOSED;	1495	dlci->state = DLCI_CLOSED;
1457	if (dlci->addr != 0) {	1496	if (dlci->addr != 0) {
1458	tty_port_tty_hangup(&dlci->port, false);	1497	tty_port_tty_hangup(&dlci->port, false);
		1498	spin_lock_irqsave(&dlci->lock, flags);
1459	kfifo_reset(&dlci->fifo);	1499	kfifo_reset(&dlci->fifo);
		1500	spin_unlock_irqrestore(&dlci->lock, flags);
1460	/* Ensure that gsmtty_open() can return. */	1501	/* Ensure that gsmtty_open() can return. */
1461	tty_port_set_initialized(&dlci->port, 0);	1502	tty_port_set_initialized(&dlci->port, 0);
1462	wake_up_interruptible(&dlci->port.open_wait);	1503	wake_up_interruptible(&dlci->port.open_wait);
1463	} else	1504	} else
1464	dlci->gsm->dead = true;	1505	dlci->gsm->dead = true;
1465	/* Unregister gsmtty driver,report gsmtty dev remove uevent for user */
1466	tty_unregister_device(gsm_tty_driver, dlci->addr);
1467	wake_up(&dlci->gsm->event);	1506	wake_up(&dlci->gsm->event);
1468	/* A DLCI 0 close is a MUX termination so we need to kick that	1507	/* A DLCI 0 close is a MUX termination so we need to kick that
1469	back to userspace somehow */	1508	back to userspace somehow */
@@ -1485,8 +1524,9 @@ static void gsm_dlci_open(struct gsm_dlci *dlci) · 15 unmodified lines
1485	dlci->state = DLCI_OPEN;	1524	dlci->state = DLCI_OPEN;
1486	if (debug & 8)	1525	if (debug & 8)
1487	pr_debug("DLCI %d goes open.\n", dlci->addr);	1526	pr_debug("DLCI %d goes open.\n", dlci->addr);
1488	/* Register gsmtty driver,report gsmtty dev add uevent for user */	1527	/* Send current modem state */
1489	tty_register_device(gsm_tty_driver, dlci->addr, NULL);	1528	if (dlci->addr)
		1529	gsm_modem_update(dlci, 0);
1490	wake_up(&dlci->gsm->event);	1530	wake_up(&dlci->gsm->event);
1491	}	1531	}
1492		1532
@@ -1619,10 +1659,12 @@ static void gsm_dlci_data(struct gsm_dlci dlci, const u8 data, int clen) · 126 unmodified lines
1619	if (len == 0)	1659	if (len == 0)
1620	return;	1660	return;
1621	}	1661	}
		1662	len--;
1622	slen++;	1663	slen++;
1623	tty = tty_port_tty_get(port);	1664	tty = tty_port_tty_get(port);
1624	if (tty) {	1665	if (tty) {
1625	gsm_process_modem(tty, dlci, modem, slen);	1666	gsm_process_modem(tty, dlci, modem, slen);
		1667	tty_wakeup(tty);
1626	tty_kref_put(tty);	1668	tty_kref_put(tty);
1627	}	1669	}
1628	fallthrough;	1670	fallthrough;
@@ -1690,7 +1732,7 @@ static struct gsm_dlci gsm_dlci_alloc(struct gsm_mux gsm, int addr) · 61 unmodified lines
1690	return NULL;	1732	return NULL;
1691	spin_lock_init(&dlci->lock);	1733	spin_lock_init(&dlci->lock);
1692	mutex_init(&dlci->mutex);	1734	mutex_init(&dlci->mutex);
1693	if (kfifo_alloc(&dlci->fifo, 4096, GFP_KERNEL) < 0) {	1735	if (kfifo_alloc(&dlci->fifo, TX_SIZE, GFP_KERNEL) < 0) {
1694	kfree(dlci);	1736	kfree(dlci);
1695	return NULL;	1737	return NULL;
1696	}	1738	}
@@ -1793,19 +1835,7 @@ static void gsm_queue(struct gsm_mux *gsm) · 96 unmodified lines
1793	struct gsm_dlci *dlci;	1835	struct gsm_dlci *dlci;
1794	u8 cr;	1836	u8 cr;
1795	int address;	1837	int address;
1796	int i, j, k, address_tmp;
1797	/* We have to sneak a look at the packet body to do the FCS.
1798	A somewhat layering violation in the spec */
1799		1838
1800	if ((gsm->control & ~PF) == UI)
1801	gsm->fcs = gsm_fcs_add_block(gsm->fcs, gsm->buf, gsm->len);
1802	if (gsm->encoding == 0) {
1803	/* WARNING: gsm->received_fcs is used for
1804	gsm->encoding = 0 only.
1805	In this case it contain the last piece of data
1806	required to generate final CRC */
1807	gsm->fcs = gsm_fcs_add(gsm->fcs, gsm->received_fcs);
1808	}
1809	if (gsm->fcs != GOOD_FCS) {	1839	if (gsm->fcs != GOOD_FCS) {
1810	gsm->bad_fcs++;	1840	gsm->bad_fcs++;
1811	if (debug & 4)	1841	if (debug & 4)
@@ -1836,11 +1866,6 @@ static void gsm_queue(struct gsm_mux *gsm) · 24 unmodified lines
1836	else {	1866	else {
1837	gsm_response(gsm, address, UA\|PF);	1867	gsm_response(gsm, address, UA\|PF);
1838	gsm_dlci_open(dlci);	1868	gsm_dlci_open(dlci);
1839	/* Save dlci open address */
1840	if (address) {
1841	addr_open[addr_cnt] = address;
1842	addr_cnt++;
1843	}
1844	}	1869	}
1845	break;	1870	break;
1846	case DISC\|PF:	1871	case DISC\|PF:
@@ -1851,35 +1876,9 @@ static void gsm_queue(struct gsm_mux *gsm) · 4 unmodified lines
1851	return;	1876	return;
1852	}	1877	}
1853	/* Real close complete */	1878	/* Real close complete */
1854	if (!address) {	1879	gsm_response(gsm, address, UA\|PF);
1855	if (addr_cnt > 0) {	1880	gsm_dlci_close(dlci);
1856	for (i = 0; i < addr_cnt; i++) {
1857	address = addr_open[i];
1858	dlci = gsm->dlci[address];
1859	gsm_dlci_close(dlci);
1860	addr_open[i] = 0;
1861	}
1862	}
1863	dlci = gsm->dlci[0];
1864	gsm_dlci_close(dlci);
1865	addr_cnt = 0;
1866	gsm_response(gsm, 0, UA\|PF);
1867	} else {
1868	gsm_response(gsm, address, UA\|PF);
1869	gsm_dlci_close(dlci);
1870	/* clear dlci address */
1871	for (j = 0; j < addr_cnt; j++) {
1872	address_tmp = addr_open[j];
1873	if (address_tmp == address) {
1874	for (k = j; k < addr_cnt; k++)
1875	addr_open[k] = addr_open[k+1];
1876	addr_cnt--;
1877	break;
1878	}
1879	}
1880	}
1881	break;	1881	break;
1882	case UA:
1883	case UA\|PF:	1882	case UA\|PF:
1884	if (cr == 0 \|\| dlci == NULL)	1883	if (cr == 0 \|\| dlci == NULL)
1885	break;	1884	break;
@@ -1993,19 +1992,25 @@ static void gsm0_receive(struct gsm_mux *gsm, unsigned char c) · 107 unmodified lines
1993	break;	1992	break;
1994	case GSM_DATA: /* Data */	1993	case GSM_DATA: /* Data */
1995	gsm->buf[gsm->count++] = c;	1994	gsm->buf[gsm->count++] = c;
1996	if (gsm->count == gsm->len)	1995	if (gsm->count == gsm->len) {
		1996	/* Calculate final FCS for UI frames over all data */
		1997	if ((gsm->control & ~PF) != UIH) {
		1998	gsm->fcs = gsm_fcs_add_block(gsm->fcs, gsm->buf,
		1999	gsm->count);
		2000	}
1997	gsm->state = GSM_FCS;	2001	gsm->state = GSM_FCS;
		2002	}
1998	break;	2003	break;
1999	case GSM_FCS: /* FCS follows the packet */	2004	case GSM_FCS: /* FCS follows the packet */
2000	gsm->received_fcs = c;	2005	gsm->fcs = gsm_fcs_add(gsm->fcs, c);
2001	gsm_queue(gsm);
2002	gsm->state = GSM_SSOF;	2006	gsm->state = GSM_SSOF;
2003	break;	2007	break;
2004	case GSM_SSOF:	2008	case GSM_SSOF:
2005	if (c == GSM0_SOF) {	2009	gsm->state = GSM_SEARCH;
2006	gsm->state = GSM_SEARCH;	2010	if (c == GSM0_SOF)
2007	break;	2011	gsm_queue(gsm);
2008	}	2012	else
		2013	gsm->bad_size++;
2009	break;	2014	break;
2010	default:	2015	default:
2011	pr_debug("%s: unhandled state: %d\n", __func__, gsm->state);	2016	pr_debug("%s: unhandled state: %d\n", __func__, gsm->state);
@@ -2023,12 +2028,35 @@ static void gsm0_receive(struct gsm_mux *gsm, unsigned char c) · 11 unmodified lines
2023		2028
2024	static void gsm1_receive(struct gsm_mux *gsm, unsigned char c)	2029	static void gsm1_receive(struct gsm_mux *gsm, unsigned char c)
2025	{	2030	{
		2031	/* handle XON/XOFF */
		2032	if ((c & ISO_IEC_646_MASK) == XON) {
		2033	gsm->constipated = true;
		2034	return;
		2035	} else if ((c & ISO_IEC_646_MASK) == XOFF) {
		2036	gsm->constipated = false;
		2037	/* Kick the link in case it is idling */
		2038	gsm_data_kick(gsm, NULL);
		2039	return;
		2040	}
2026	if (c == GSM1_SOF) {	2041	if (c == GSM1_SOF) {
2027	/* EOF is only valid in frame if we have got to the data state	2042	/* EOF is only valid in frame if we have got to the data state */
2028	and received at least one byte (the FCS) */	2043	if (gsm->state == GSM_DATA) {
2029	if (gsm->state == GSM_DATA && gsm->count) {	2044	if (gsm->count < 1) {
2030	/* Extract the FCS */	2045	/* Missing FSC */
		2046	gsm->malformed++;
		2047	gsm->state = GSM_START;
		2048	return;
		2049	}
		2050	/* Remove the FCS from data */
2031	gsm->count--;	2051	gsm->count--;
		2052	if ((gsm->control & ~PF) != UIH) {
		2053	/* Calculate final FCS for UI frames over all
		2054	* data but FCS
		2055	*/
		2056	gsm->fcs = gsm_fcs_add_block(gsm->fcs, gsm->buf,
		2057	gsm->count);
		2058	}
		2059	/* Add the FCS itself to test against GOOD_FCS */
2032	gsm->fcs = gsm_fcs_add(gsm->fcs, gsm->buf[gsm->count]);	2060	gsm->fcs = gsm_fcs_add(gsm->fcs, gsm->buf[gsm->count]);
2033	gsm->len = gsm->count;	2061	gsm->len = gsm->count;
2034	gsm_queue(gsm);	2062	gsm_queue(gsm);
@@ -2037,7 +2065,8 @@ static void gsm1_receive(struct gsm_mux *gsm, unsigned char c) · 2 unmodified lines
2037	}	2065	}
2038	/* Any partial frame was a runt so go back to start */	2066	/* Any partial frame was a runt so go back to start */
2039	if (gsm->state != GSM_START) {	2067	if (gsm->state != GSM_START) {
2040	gsm->malformed++;	2068	if (gsm->state != GSM_SEARCH)
		2069	gsm->malformed++;
2041	gsm->state = GSM_START;	2070	gsm->state = GSM_START;
2042	}	2071	}
2043	/* A SOF in GSM_START means we are still reading idling or	2072	/* A SOF in GSM_START means we are still reading idling or
@@ -2106,74 +2135,43 @@ static void gsm_error(struct gsm_mux *gsm) · 62 unmodified lines
2106	gsm->io_error++;	2135	gsm->io_error++;
2107	}	2136	}
2108		2137
2109	static int gsm_disconnect(struct gsm_mux *gsm)
2110	{
2111	struct gsm_dlci *dlci = gsm->dlci[0];
2112	struct gsm_control *gc;
2113
2114	if (!dlci)
2115	return 0;
2116
2117	/* In theory disconnecting DLCI 0 is sufficient but for some
2118	modems this is apparently not the case. */
2119	gc = gsm_control_send(gsm, CMD_CLD, NULL, 0);
2120	if (gc)
2121	gsm_control_wait(gsm, gc);
2122
2123	del_timer_sync(&gsm->t2_timer);
2124	/* Now we are sure T2 has stopped */
2125
2126	gsm_dlci_begin_close(dlci);
2127	wait_event_interruptible(gsm->event,
2128	dlci->state == DLCI_CLOSED);
2129
2130	if (signal_pending(current))
2131	return -EINTR;
2132
2133	return 0;
2134	}
2135
2136	/**	2138	/**
2137	* gsm_cleanup_mux - generic GSM protocol cleanup	2139	* gsm_cleanup_mux - generic GSM protocol cleanup
2138	* @gsm: our mux	2140	* @gsm: our mux
		2141	* @disc: disconnect link?
2139	*	2142	*
2140	* Clean up the bits of the mux which are the same for all framing	2143	* Clean up the bits of the mux which are the same for all framing
2141	* protocols. Remove the mux from the mux table, stop all the timers	2144	* protocols. Remove the mux from the mux table, stop all the timers
2142	* and then shut down each device hanging up the channels as we go.	2145	* and then shut down each device hanging up the channels as we go.
2143	*/	2146	*/
2144		2147
2145	static void gsm_cleanup_mux(struct gsm_mux *gsm)	2148	static void gsm_cleanup_mux(struct gsm_mux *gsm, bool disc)
2146	{	2149	{
2147	int i;	2150	int i;
2148	struct gsm_dlci *dlci = gsm->dlci[0];	2151	struct gsm_dlci *dlci = gsm->dlci[0];
2149	struct gsm_msg txq, ntxq;	2152	struct gsm_msg txq, ntxq;
2150		2153
2151	gsm->dead = true;	2154	gsm->dead = true;
		2155	mutex_lock(&gsm->mutex);
2152		2156
2153	spin_lock(&gsm_mux_lock);	2157	if (dlci) {
2154	for (i = 0; i < MAX_MUX; i++) {	2158	if (disc && dlci->state != DLCI_CLOSED) {
2155	if (gsm_mux[i] == gsm) {	2159	gsm_dlci_begin_close(dlci);
2156	gsm_mux[i] = NULL;	2160	wait_event(gsm->event, dlci->state == DLCI_CLOSED);
2157	break;
2158	}	2161	}
		2162	dlci->dead = true;
2159	}	2163	}
2160	spin_unlock(&gsm_mux_lock);
2161	/* open failed before registering => nothing to do */
2162	if (i == MAX_MUX)
2163	return;
2164		2164
		2165	/* Finish outstanding timers, making sure they are done */
2165	del_timer_sync(&gsm->t2_timer);	2166	del_timer_sync(&gsm->t2_timer);
2166	/* Now we are sure T2 has stopped */
2167	if (dlci)
2168	dlci->dead = true;
2169		2167
2170	/* Free up any link layer users */	2168	/* Free up any link layer users and finally the control channel */
2171	mutex_lock(&gsm->mutex);	2169	for (i = NUM_DLCI - 1; i >= 0; i--)
2172	for (i = 0; i < NUM_DLCI; i++)
2173	if (gsm->dlci[i])	2170	if (gsm->dlci[i])
2174	gsm_dlci_release(gsm->dlci[i]);	2171	gsm_dlci_release(gsm->dlci[i]);
2175	mutex_unlock(&gsm->mutex);	2172	mutex_unlock(&gsm->mutex);
2176	/* Now wipe the queues */	2173	/* Now wipe the queues */
		2174	tty_ldisc_flush(gsm->tty);
2177	list_for_each_entry_safe(txq, ntxq, &gsm->tx_list, list)	2175	list_for_each_entry_safe(txq, ntxq, &gsm->tx_list, list)
2178	kfree(txq);	2176	kfree(txq);
2179	INIT_LIST_HEAD(&gsm->tx_list);	2177	INIT_LIST_HEAD(&gsm->tx_list);
@@ -2191,7 +2189,6 @@ static void gsm_cleanup_mux(struct gsm_mux *gsm) · 11 unmodified lines
2191	static int gsm_activate_mux(struct gsm_mux *gsm)	2189	static int gsm_activate_mux(struct gsm_mux *gsm)
2192	{	2190	{
2193	struct gsm_dlci *dlci;	2191	struct gsm_dlci *dlci;
2194	int i = 0;
2195		2192
2196	timer_setup(&gsm->t2_timer, gsm_control_retransmit, 0);	2193	timer_setup(&gsm->t2_timer, gsm_control_retransmit, 0);
2197	init_waitqueue_head(&gsm->event);	2194	init_waitqueue_head(&gsm->event);
@@ -2203,18 +2200,6 @@ static int gsm_activate_mux(struct gsm_mux *gsm) · 5 unmodified lines
2203	else	2200	else
2204	gsm->receive = gsm1_receive;	2201	gsm->receive = gsm1_receive;
2205		2202
2206	spin_lock(&gsm_mux_lock);
2207	for (i = 0; i < MAX_MUX; i++) {
2208	if (gsm_mux[i] == NULL) {
2209	gsm->num = i;
2210	gsm_mux[i] = gsm;
2211	break;
2212	}
2213	}
2214	spin_unlock(&gsm_mux_lock);
2215	if (i == MAX_MUX)
2216	return -EBUSY;
2217
2218	dlci = gsm_dlci_alloc(gsm, 0);	2203	dlci = gsm_dlci_alloc(gsm, 0);
2219	if (dlci == NULL)	2204	if (dlci == NULL)
2220	return -ENOMEM;	2205	return -ENOMEM;
@@ -2230,6 +2215,15 @@ static int gsm_activate_mux(struct gsm_mux *gsm) · 9 unmodified lines
2230	*/	2215	*/
2231	static void gsm_free_mux(struct gsm_mux *gsm)	2216	static void gsm_free_mux(struct gsm_mux *gsm)
2232	{	2217	{
		2218	int i;
		2219
		2220	for (i = 0; i < MAX_MUX; i++) {
		2221	if (gsm == gsm_mux[i]) {
		2222	gsm_mux[i] = NULL;
		2223	break;
		2224	}
		2225	}
		2226	mutex_destroy(&gsm->mutex);
2233	kfree(gsm->txframe);	2227	kfree(gsm->txframe);
2234	kfree(gsm->buf);	2228	kfree(gsm->buf);
2235	kfree(gsm);	2229	kfree(gsm);
@@ -2249,12 +2243,20 @@ static void gsm_free_muxr(struct kref *ref) · 13 unmodified lines
2249		2243
2250	static inline void mux_get(struct gsm_mux *gsm)	2244	static inline void mux_get(struct gsm_mux *gsm)
2251	{	2245	{
		2246	unsigned long flags;
		2247
		2248	spin_lock_irqsave(&gsm_mux_lock, flags);
2252	kref_get(&gsm->ref);	2249	kref_get(&gsm->ref);
		2250	spin_unlock_irqrestore(&gsm_mux_lock, flags);
2253	}	2251	}
2254		2252
2255	static inline void mux_put(struct gsm_mux *gsm)	2253	static inline void mux_put(struct gsm_mux *gsm)
2256	{	2254	{
		2255	unsigned long flags;
		2256
		2257	spin_lock_irqsave(&gsm_mux_lock, flags);
2257	kref_put(&gsm->ref, gsm_free_muxr);	2258	kref_put(&gsm->ref, gsm_free_muxr);
		2259	spin_unlock_irqrestore(&gsm_mux_lock, flags);
2258	}	2260	}
2259		2261
2260	static inline unsigned int mux_num_to_base(struct gsm_mux *gsm)	2262	static inline unsigned int mux_num_to_base(struct gsm_mux *gsm)
@@ -2275,6 +2277,7 @@ static inline unsigned int mux_line_to_num(unsigned int line) · 14 unmodified lines
2275		2277
2276	static struct gsm_mux *gsm_alloc_mux(void)	2278	static struct gsm_mux *gsm_alloc_mux(void)
2277	{	2279	{
		2280	int i;
2278	struct gsm_mux *gsm = kzalloc(sizeof(struct gsm_mux), GFP_KERNEL);	2281	struct gsm_mux *gsm = kzalloc(sizeof(struct gsm_mux), GFP_KERNEL);
2279	if (gsm == NULL)	2282	if (gsm == NULL)
2280	return NULL;	2283	return NULL;
@@ -2283,7 +2286,7 @@ static struct gsm_mux *gsm_alloc_mux(void) · 2 unmodified lines
2283	kfree(gsm);	2286	kfree(gsm);
2284	return NULL;	2287	return NULL;
2285	}	2288	}
2286	gsm->txframe = kmalloc(2 * MAX_MRU + 2, GFP_KERNEL);	2289	gsm->txframe = kmalloc(2 * (MAX_MTU + PROT_OVERHEAD - 1), GFP_KERNEL);
2287	if (gsm->txframe == NULL) {	2290	if (gsm->txframe == NULL) {
2288	kfree(gsm->buf);	2291	kfree(gsm->buf);
2289	kfree(gsm);	2292	kfree(gsm);
@@ -2304,6 +2307,26 @@ static struct gsm_mux *gsm_alloc_mux(void) · 14 unmodified lines
2304	gsm->mtu = 64;	2307	gsm->mtu = 64;
2305	gsm->dead = true; /* Avoid early tty opens */	2308	gsm->dead = true; /* Avoid early tty opens */
2306		2309
		2310	/* Store the instance to the mux array or abort if no space is
		2311	* available.
		2312	*/
		2313	spin_lock(&gsm_mux_lock);
		2314	for (i = 0; i < MAX_MUX; i++) {
		2315	if (!gsm_mux[i]) {
		2316	gsm_mux[i] = gsm;
		2317	gsm->num = i;
		2318	break;
		2319	}
		2320	}
		2321	spin_unlock(&gsm_mux_lock);
		2322	if (i == MAX_MUX) {
		2323	mutex_destroy(&gsm->mutex);
		2324	kfree(gsm->txframe);
		2325	kfree(gsm->buf);
		2326	kfree(gsm);
		2327	return NULL;
		2328	}
		2329
2307	return gsm;	2330	return gsm;
2308	}	2331	}
2309		2332
@@ -2330,6 +2353,7 @@ static void gsm_copy_config_values(struct gsm_mux *gsm, · 20 unmodified lines
2330		2353
2331	static int gsm_config(struct gsm_mux gsm, struct gsm_config c)	2354	static int gsm_config(struct gsm_mux gsm, struct gsm_config c)
2332	{	2355	{
		2356	int ret = 0;
2333	int need_close = 0;	2357	int need_close = 0;
2334	int need_restart = 0;	2358	int need_restart = 0;
2335		2359
@@ -2339,7 +2363,7 @@ static int gsm_config(struct gsm_mux gsm, struct gsm_config c) · 3 unmodified lines
2339	/* Check the MRU/MTU range looks sane */	2363	/* Check the MRU/MTU range looks sane */
2340	if (c->mru > MAX_MRU \|\| c->mtu > MAX_MTU \|\| c->mru < 8 \|\| c->mtu < 8)	2364	if (c->mru > MAX_MRU \|\| c->mtu > MAX_MTU \|\| c->mru < 8 \|\| c->mtu < 8)
2341	return -EINVAL;	2365	return -EINVAL;
2342	if (c->n2 < 3)	2366	if (c->n2 > 255)
2343	return -EINVAL;	2367	return -EINVAL;
2344	if (c->encapsulation > 1) /* Basic, advanced, no I */	2368	if (c->encapsulation > 1) /* Basic, advanced, no I */
2345	return -EINVAL;	2369	return -EINVAL;
@@ -2370,19 +2394,11 @@ static int gsm_config(struct gsm_mux gsm, struct gsm_config c) · 24 unmodified lines
2370		2394
2371	/*	2395	/*
2372	* Close down what is needed, restart and initiate the new	2396	* Close down what is needed, restart and initiate the new
2373	* configuration	2397	* configuration. On the first time there is no DLCI[0]
		2398	* and closing or cleaning up is not necessary.
2374	*/	2399	*/
2375		2400	if (need_close \|\| need_restart)
2376	if (gsm->initiator && (need_close \|\| need_restart)) {	2401	gsm_cleanup_mux(gsm, true);
2377	int ret;
2378
2379	ret = gsm_disconnect(gsm);
2380
2381	if (ret)
2382	return ret;
2383	}
2384	if (need_restart)
2385	gsm_cleanup_mux(gsm);
2386		2402
2387	gsm->initiator = c->initiator;	2403	gsm->initiator = c->initiator;
2388	gsm->mru = c->mru;	2404	gsm->mru = c->mru;
@@ -2405,10 +2421,13 @@ static int gsm_config(struct gsm_mux gsm, struct gsm_config c) · 16 unmodified lines
2405	* FIXME: We need to separate activation/deactivation from adding	2421	* FIXME: We need to separate activation/deactivation from adding
2406	* and removing from the mux array	2422	* and removing from the mux array
2407	*/	2423	*/
2408	if (need_restart)	2424	if (gsm->dead) {
2409	gsm_activate_mux(gsm);	2425	ret = gsm_activate_mux(gsm);
2410	if (gsm->initiator && need_close)	2426	if (ret)
2411	gsm_dlci_begin_open(gsm->dlci[0]);	2427	return ret;
		2428	if (gsm->initiator)
		2429	gsm_dlci_begin_open(gsm->dlci[0]);
		2430	}
2412	return 0;	2431	return 0;
2413	}	2432	}
2414		2433
@@ -2450,25 +2469,26 @@ static int gsmld_attach_gsm(struct tty_struct tty, struct gsm_mux gsm) · 35 unmodified lines
2450	int ret, i;	2469	int ret, i;
2451		2470
2452	gsm->tty = tty_kref_get(tty);	2471	gsm->tty = tty_kref_get(tty);
		2472	/* Turn off tty XON/XOFF handling to handle it explicitly. */
		2473	gsm->old_c_iflag = tty->termios.c_iflag;
		2474	tty->termios.c_iflag &= (IXON \| IXOFF);
2453	ret = gsm_activate_mux(gsm);	2475	ret = gsm_activate_mux(gsm);
2454	if (ret != 0)	2476	if (ret != 0)
2455	tty_kref_put(gsm->tty);	2477	tty_kref_put(gsm->tty);
2456	else {	2478	else {
2457	/* Don't register device 0 - this is the control channel and not	2479	/* Don't register device 0 - this is the control channel and not
2458	a usable tty interface */	2480	a usable tty interface */
2459	if (gsm->initiator) {	2481	base = mux_num_to_base(gsm); /* Base for this MUX */
2460	base = mux_num_to_base(gsm); /* Base for this MUX */	2482	for (i = 1; i < NUM_DLCI; i++) {
2461	for (i = 1; i < NUM_DLCI; i++) {	2483	struct device *dev;
2462	struct device *dev;
2463		2484
2464	dev = tty_register_device(gsm_tty_driver,	2485	dev = tty_register_device(gsm_tty_driver,
2465	base + i, NULL);	2486	base + i, NULL);
2466	if (IS_ERR(dev)) {	2487	if (IS_ERR(dev)) {
2467	for (i--; i >= 1; i--)	2488	for (i--; i >= 1; i--)
2468	tty_unregister_device(gsm_tty_driver,	2489	tty_unregister_device(gsm_tty_driver,
2469	base + i);	2490	base + i);
2470	return PTR_ERR(dev);	2491	return PTR_ERR(dev);
2471	}
2472	}	2492	}
2473	}	2493	}
2474	}	2494	}
@@ -2490,11 +2510,10 @@ static void gsmld_detach_gsm(struct tty_struct tty, struct gsm_mux gsm) · 15 unmodified lines
2490	int i;	2510	int i;
2491		2511
2492	WARN_ON(tty != gsm->tty);	2512	WARN_ON(tty != gsm->tty);
2493	if (gsm->initiator) {	2513	for (i = 1; i < NUM_DLCI; i++)
2494	for (i = 1; i < NUM_DLCI; i++)	2514	tty_unregister_device(gsm_tty_driver, base + i);
2495	tty_unregister_device(gsm_tty_driver, base + i);	2515	/* Restore tty XON/XOFF handling. */
2496	}	2516	gsm->tty->termios.c_iflag = gsm->old_c_iflag;
2497	gsm_cleanup_mux(gsm);
2498	tty_kref_put(gsm->tty);	2517	tty_kref_put(gsm->tty);
2499	gsm->tty = NULL;	2518	gsm->tty = NULL;
2500	}	2519	}
@@ -2559,6 +2578,12 @@ static void gsmld_close(struct tty_struct *tty) · 58 unmodified lines
2559	{	2578	{
2560	struct gsm_mux *gsm = tty->disc_data;	2579	struct gsm_mux *gsm = tty->disc_data;
2561		2580
		2581	/* The ldisc locks and closes the port before calling our close. This
		2582	* means we have no way to do a proper disconnect. We will not bother
		2583	* to do one.
		2584	*/
		2585	gsm_cleanup_mux(gsm, false);
		2586
2562	gsmld_detach_gsm(tty, gsm);	2587	gsmld_detach_gsm(tty, gsm);
2563		2588
2564	gsmld_flush_buffer(tty);	2589	gsmld_flush_buffer(tty);
@@ -2597,7 +2622,7 @@ static int gsmld_open(struct tty_struct *tty) · 32 unmodified lines
2597		2622
2598	ret = gsmld_attach_gsm(tty, gsm);	2623	ret = gsmld_attach_gsm(tty, gsm);
2599	if (ret != 0) {	2624	if (ret != 0) {
2600	gsm_cleanup_mux(gsm);	2625	gsm_cleanup_mux(gsm, false);
2601	mux_put(gsm);	2626	mux_put(gsm);
2602	}	2627	}
2603	return ret;	2628	return ret;
@@ -2952,28 +2977,78 @@ static struct tty_ldisc_ops tty_ldisc_packet = { · 348 unmodified lines
2952	* Virtual tty side	2977	* Virtual tty side
2953	*/	2978	*/
2954		2979
2955	#define TX_SIZE 512	2980	/**
		2981	* gsm_modem_upd_via_data - send modem bits via convergence layer
		2982	* @dlci: channel
		2983	* @brk: break signal
		2984	*
		2985	* Send an empty frame to signal mobile state changes and to transmit the
		2986	* break signal for adaption 2.
		2987	*/
		2988
		2989	static void gsm_modem_upd_via_data(struct gsm_dlci *dlci, u8 brk)
		2990	{
		2991	struct gsm_mux *gsm = dlci->gsm;
		2992	unsigned long flags;
		2993
		2994	if (dlci->state != DLCI_OPEN \|\| dlci->adaption != 2)
		2995	return;
		2996
		2997	spin_lock_irqsave(&gsm->tx_lock, flags);
		2998	gsm_dlci_modem_output(gsm, dlci, brk);
		2999	spin_unlock_irqrestore(&gsm->tx_lock, flags);
		3000	}
		3001
		3002	/**
		3003	* gsm_modem_upd_via_msc - send modem bits via control frame
		3004	* @dlci: channel
		3005	* @brk: break signal
		3006	*/
2956		3007
2957	static int gsmtty_modem_update(struct gsm_dlci *dlci, u8 brk)	3008	static int gsm_modem_upd_via_msc(struct gsm_dlci *dlci, u8 brk)
2958	{	3009	{
2959	u8 modembits[5];	3010	u8 modembits[3];
2960	struct gsm_control *ctrl;	3011	struct gsm_control *ctrl;
2961	int len = 2;	3012	int len = 2;
2962		3013
2963	if (brk)	3014	if (dlci->gsm->encoding != 0)
2964	len++;	3015	return 0;
2965		3016
2966	modembits[0] = len << 1 \| EA; /* Data bytes */	3017	modembits[0] = (dlci->addr << 2) \| 2 \| EA; /* DLCI, Valid, EA */
2967	modembits[1] = dlci->addr << 2 \| 3; /* DLCI, EA, 1 */	3018	if (!brk) {
2968	modembits[2] = gsm_encode_modem(dlci) << 1 \| EA;	3019	modembits[1] = (gsm_encode_modem(dlci) << 1) \| EA;
2969	if (brk)	3020	} else {
2970	modembits[3] = brk << 4 \| 2 \| EA; /* Valid, EA */	3021	modembits[1] = gsm_encode_modem(dlci) << 1;
2971	ctrl = gsm_control_send(dlci->gsm, CMD_MSC, modembits, len + 1);	3022	modembits[2] = (brk << 4) \| 2 \| EA; /* Length, Break, EA */
		3023	len++;
		3024	}
		3025	ctrl = gsm_control_send(dlci->gsm, CMD_MSC, modembits, len);
2972	if (ctrl == NULL)	3026	if (ctrl == NULL)
2973	return -ENOMEM;	3027	return -ENOMEM;
2974	return gsm_control_wait(dlci->gsm, ctrl);	3028	return gsm_control_wait(dlci->gsm, ctrl);
2975	}	3029	}
2976		3030
		3031	/**
		3032	* gsm_modem_update - send modem status line state
		3033	* @dlci: channel
		3034	* @brk: break signal
		3035	*/
		3036
		3037	static int gsm_modem_update(struct gsm_dlci *dlci, u8 brk)
		3038	{
		3039	if (dlci->adaption == 2) {
		3040	/* Send convergence layer type 2 empty data frame. */
		3041	gsm_modem_upd_via_data(dlci, brk);
		3042	return 0;
		3043	} else if (dlci->gsm->encoding == 0) {
		3044	/* Send as MSC control message. */
		3045	return gsm_modem_upd_via_msc(dlci, brk);
		3046	}
		3047
		3048	/* Modem status lines are not supported. */
		3049	return -EPROTONOSUPPORT;
		3050	}
		3051
2977	static int gsm_carrier_raised(struct tty_port *port)	3052	static int gsm_carrier_raised(struct tty_port *port)
2978	{	3053	{
2979	struct gsm_dlci *dlci = container_of(port, struct gsm_dlci, port);	3054	struct gsm_dlci *dlci = container_of(port, struct gsm_dlci, port);
@@ -3006,7 +3081,7 @@ static void gsm_dtr_rts(struct tty_port *port, int onoff) · 26 unmodified lines
3006	modem_tx &= ~(TIOCM_DTR \| TIOCM_RTS);	3081	modem_tx &= ~(TIOCM_DTR \| TIOCM_RTS);
3007	if (modem_tx != dlci->modem_tx) {	3082	if (modem_tx != dlci->modem_tx) {
3008	dlci->modem_tx = modem_tx;	3083	dlci->modem_tx = modem_tx;
3009	gsmtty_modem_update(dlci, 0);	3084	gsm_modem_update(dlci, 0);
3010	}	3085	}
3011	}	3086	}
3012		3087
@@ -3141,7 +3216,7 @@ static unsigned int gsmtty_write_room(struct tty_struct *tty) · 128 unmodified lines
3141	struct gsm_dlci *dlci = tty->driver_data;	3216	struct gsm_dlci *dlci = tty->driver_data;
3142	if (dlci->state == DLCI_CLOSED)	3217	if (dlci->state == DLCI_CLOSED)
3143	return 0;	3218	return 0;
3144	return TX_SIZE - kfifo_len(&dlci->fifo);	3219	return kfifo_avail(&dlci->fifo);
3145	}	3220	}
3146		3221
3147	static unsigned int gsmtty_chars_in_buffer(struct tty_struct *tty)	3222	static unsigned int gsmtty_chars_in_buffer(struct tty_struct *tty)
@@ -3155,13 +3230,17 @@ static unsigned int gsmtty_chars_in_buffer(struct tty_struct *tty) · 7 unmodified lines
3155	static void gsmtty_flush_buffer(struct tty_struct *tty)	3230	static void gsmtty_flush_buffer(struct tty_struct *tty)
3156	{	3231	{
3157	struct gsm_dlci *dlci = tty->driver_data;	3232	struct gsm_dlci *dlci = tty->driver_data;
		3233	unsigned long flags;
		3234
3158	if (dlci->state == DLCI_CLOSED)	3235	if (dlci->state == DLCI_CLOSED)
3159	return;	3236	return;
3160	/* Caution needed: If we implement reliable transport classes	3237	/* Caution needed: If we implement reliable transport classes
3161	then the data being transmitted can't simply be junked once	3238	then the data being transmitted can't simply be junked once
3162	it has first hit the stack. Until then we can just blow it	3239	it has first hit the stack. Until then we can just blow it
3163	away */	3240	away */
		3241	spin_lock_irqsave(&dlci->lock, flags);
3164	kfifo_reset(&dlci->fifo);	3242	kfifo_reset(&dlci->fifo);
		3243	spin_unlock_irqrestore(&dlci->lock, flags);
3165	/* Need to unhook this DLCI from the transmit queue logic */	3244	/* Need to unhook this DLCI from the transmit queue logic */
3166	}	3245	}
3167		3246
@@ -3193,7 +3272,7 @@ static int gsmtty_tiocmset(struct tty_struct *tty, · 25 unmodified lines
3193		3272
3194	if (modem_tx != dlci->modem_tx) {	3273	if (modem_tx != dlci->modem_tx) {
3195	dlci->modem_tx = modem_tx;	3274	dlci->modem_tx = modem_tx;
3196	return gsmtty_modem_update(dlci, 0);	3275	return gsm_modem_update(dlci, 0);
3197	}	3276	}
3198	return 0;	3277	return 0;
3199	}	3278	}
@@ -3254,7 +3333,7 @@ static void gsmtty_throttle(struct tty_struct *tty) · 54 unmodified lines
3254	dlci->modem_tx &= ~TIOCM_RTS;	3333	dlci->modem_tx &= ~TIOCM_RTS;
3255	dlci->throttled = true;	3334	dlci->throttled = true;
3256	/* Send an MSC with RTS cleared */	3335	/* Send an MSC with RTS cleared */
3257	gsmtty_modem_update(dlci, 0);	3336	gsm_modem_update(dlci, 0);
3258	}	3337	}
3259		3338
3260	static void gsmtty_unthrottle(struct tty_struct *tty)	3339	static void gsmtty_unthrottle(struct tty_struct *tty)
@@ -3266,7 +3345,7 @@ static void gsmtty_unthrottle(struct tty_struct *tty) · 5 unmodified lines
3266	dlci->modem_tx \|= TIOCM_RTS;	3345	dlci->modem_tx \|= TIOCM_RTS;
3267	dlci->throttled = false;	3346	dlci->throttled = false;
3268	/* Send an MSC with RTS set */	3347	/* Send an MSC with RTS set */
3269	gsmtty_modem_update(dlci, 0);	3348	gsm_modem_update(dlci, 0);
3270	}	3349	}
3271		3350
3272	static int gsmtty_break_ctl(struct tty_struct *tty, int state)	3351	static int gsmtty_break_ctl(struct tty_struct *tty, int state)
@@ -3284,7 +3363,7 @@ static int gsmtty_break_ctl(struct tty_struct *tty, int state) · 11 unmodified lines
3284	if (encode > 0x0F)	3363	if (encode > 0x0F)
3285	encode = 0x0F; /* Best effort */	3364	encode = 0x0F; /* Best effort */
3286	}	3365	}
3287	return gsmtty_modem_update(dlci, encode);	3366	return gsm_modem_update(dlci, encode);
3288	}	3367	}
3289		3368
3290	static void gsmtty_cleanup(struct tty_struct *tty)	3369	static void gsmtty_cleanup(struct tty_struct *tty)

drivers/tty/serial/8250/8250_mtk.c+20−9

 #define MTK_UART_IER_RTSI	0x40	/* Enable RTS Modem status interrupt */
 #define MTK_UART_IER_CTSI	0x80	/* Enable CTS Modem status interrupt */
+#define MTK_UART_EFR		38	/* I/O: Extended Features Register */
 #define MTK_UART_EFR_EN		0x10	/* Enable enhancement feature */
 #define MTK_UART_EFR_RTS	0x40	/* Enable hardware rx flow control */
 #define MTK_UART_EFR_CTS	0x80	/* Enable hardware tx flow control */
 #define MTK_UART_TX_TRIGGER	1
 #define MTK_UART_RX_TRIGGER	MTK_UART_RX_SIZE
+#define MTK_UART_FEATURE_SEL	39	/* Feature Selection register */
+#define MTK_UART_FEAT_NEWRMAP	BIT(0)	/* Use new register map */
+#define MTK_UART_XON1		40	/* I/O: Xon character 1 */
+#define MTK_UART_XOFF1		42	/* I/O: Xoff character 1 */
 #ifdef CONFIG_SERIAL_8250_DMA
 enum dma_rx_status {
 	DMA_RX_START = 0,
 		   MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-	serial_out(up, UART_EFR, UART_EFR_ECB);
+	serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
 	serial_out(up, UART_LCR, lcr);
 	if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0)
 	int lcr = serial_in(up, UART_LCR);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-	serial_out(up, UART_EFR, UART_EFR_ECB);
+	serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
 	serial_out(up, UART_LCR, lcr);
 	lcr = serial_in(up, UART_LCR);
 		serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
 		serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-		serial_out(up, UART_EFR, serial_in(up, UART_EFR) &
+		serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) &
 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)));
 		serial_out(up, UART_LCR, lcr);
 		mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI |
 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 		/*enable hw flow control*/
-		serial_out(up, UART_EFR, MTK_UART_EFR_HW_FC |
+		serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC |
-			(serial_in(up, UART_EFR) &
+			(serial_in(up, MTK_UART_EFR) &
 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
 		serial_out(up, UART_LCR, lcr);
 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 		/*enable sw flow control */
-		serial_out(up, UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
+		serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
-			(serial_in(up, UART_EFR) &
+			(serial_in(up, MTK_UART_EFR) &
 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
-		serial_out(up, UART_XON1, START_CHAR(port->state->port.tty));
+		serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty));
-		serial_out(up, UART_XOFF1, STOP_CHAR(port->state->port.tty));
+		serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty));
 		serial_out(up, UART_LCR, lcr);
 		mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI);
 		mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI);
 		uart.dma = data->dma;
 #endif
+	/* Set AP UART new register map */
+	writel(MTK_UART_FEAT_NEWRMAP, uart.port.membase +
+	       (MTK_UART_FEATURE_SEL << uart.port.regshift));
 	/* Disable Rate Fix function */
 	writel(0x0, uart.port.membase +
 			(MTK_UART_RATE_FIX << uart.port.regshift));

drivers/tty/serial/8250/8250_pci.c+4−4

@@ -2667,7 +2667,7 @@ enum pci_board_num_t { · 2666 unmodified lines
2667	pbn_panacom2,	2667	pbn_panacom2,
2668	pbn_panacom4,	2668	pbn_panacom4,
2669	pbn_plx_romulus,	2669	pbn_plx_romulus,
2670	pbn_endrun_2_4000000,	2670	pbn_endrun_2_3906250,
2671	pbn_oxsemi,	2671	pbn_oxsemi,
2672	pbn_oxsemi_1_3906250,	2672	pbn_oxsemi_1_3906250,
2673	pbn_oxsemi_2_3906250,	2673	pbn_oxsemi_2_3906250,
@@ -3195,10 +3195,10 @@ static struct pciserial_board pci_boards[] = { · 521 unmodified lines
3195	* signal now many ports are available	3195	* signal now many ports are available
3196	* 2 port 952 Uart support	3196	* 2 port 952 Uart support
3197	*/	3197	*/
3198	[pbn_endrun_2_4000000] = {	3198	[pbn_endrun_2_3906250] = {
3199	.flags = FL_BASE0,	3199	.flags = FL_BASE0,
3200	.num_ports = 2,	3200	.num_ports = 2,
3201	.base_baud = 4000000,	3201	.base_baud = 3906250,
3202	.uart_offset = 0x200,	3202	.uart_offset = 0x200,
3203	.first_offset = 0x1000,	3203	.first_offset = 0x1000,
3204	},	3204	},
@@ -4115,7 +4115,7 @@ static const struct pci_device_id serial_pci_tbl[] = { · 910 unmodified lines
4115	*/	4115	*/
4116	{ PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,	4116	{ PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4117	PCI_ANY_ID, PCI_ANY_ID, 0, 0,	4117	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118	pbn_endrun_2_4000000 },	4118	pbn_endrun_2_3906250 },
4119	/*	4119	/*
4120	* Quatech cards. These actually have configurable clocks but for	4120	* Quatech cards. These actually have configurable clocks but for
4121	* now we just use the default.	4121	* now we just use the default.

drivers/tty/serial/8250/8250_port.c+3−3

 	struct uart_8250_port *up = up_to_u8250p(port);
 	struct uart_8250_em485 *em485 = up->em485;
-	serial8250_rpm_get_tx(up);
 	if (!port->x_char && uart_circ_empty(&port->state->xmit))
 		return;
+	serial8250_rpm_get_tx(up);
 	if (em485 &&
 	    em485->active_timer == &em485->start_tx_timer)
 		return;
 	serial8250_set_divisor(port, baud, quot, frac);
 	serial_port_out(port, UART_LCR, up->lcr);
-	serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
+	serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
 }
 /*

drivers/tty/serial/amba-pl011.c+7−2

 static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
 {
+	/*
+	 * To be on the safe side only time out after twice as many iterations
+	 * as fifo size.
+	 */
+	const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
 	struct uart_port *port = &uap->port;
 	int i = 0;
 	u32 cr;
 	/* Wait until hardware tx queue is empty */
 	while (!pl011_tx_empty(port)) {
-		if (i == port->fifosize) {
+		if (i > MAX_TX_DRAIN_ITERS) {
 			dev_warn(port->dev,
 				 "timeout while draining hardware tx queue\n");
 			break;
 	 * with the given baud rate. We use this as the poll interval when we
 	 * wait for the tx queue to empty.
 	 */
-	uap->rs485_tx_drain_interval = (bits * 1000 * 1000) / baud;
+	uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
 	pl011_setup_status_masks(port, termios);

drivers/tty/serial/digicolor-usart.c+2−3

 	if (IS_ERR(uart_clk))
 		return PTR_ERR(uart_clk);
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dp->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-	dp->port.mapbase = res->start;
-	dp->port.membase = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(dp->port.membase))
 		return PTR_ERR(dp->port.membase);
+	dp->port.mapbase = res->start;
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)

drivers/tty/serial/fsl_lpuart.c+9−9

 	struct device_node *np = pdev->dev.of_node;
 	struct lpuart_port *sport;
 	struct resource *res;
+	irq_handler_t handler;
 	int ret;
 	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
 	if (lpuart_is_32(sport)) {
 		lpuart_reg.cons = LPUART32_CONSOLE;
-		ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
+		handler = lpuart32_int;
-					DRIVER_NAME, sport);
 	} else {
 		lpuart_reg.cons = LPUART_CONSOLE;
-		ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
+		handler = lpuart_int;
-					DRIVER_NAME, sport);
 	}
-	if (ret)
-		goto failed_irq_request;
 	ret = uart_add_one_port(&lpuart_reg, &sport->port);
 	if (ret)
 		goto failed_attach_port;
 	sport->port.rs485_config(&sport->port, &sport->port.rs485);
+	ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
+				DRIVER_NAME, sport);
+	if (ret)
+		goto failed_irq_request;
 	return 0;
+failed_irq_request:
 failed_get_rs485:
 failed_reset:
 	uart_remove_one_port(&lpuart_reg, &sport->port);
 failed_attach_port:
-failed_irq_request:
 	lpuart_disable_clks(sport);
 failed_clock_enable:
 failed_out_of_range:

drivers/tty/serial/imx.c+1−1

@@ -1448,7 +1448,7 @@ static int imx_uart_startup(struct uart_port *port) · 1447 unmodified lines
1448	imx_uart_writel(sport, ucr1, UCR1);	1448	imx_uart_writel(sport, ucr1, UCR1);
1449		1449
1450	ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN \| UCR4_INVR);	1450	ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN \| UCR4_INVR);
1451	if (!sport->dma_is_enabled)	1451	if (!dma_is_inited)
1452	ucr4 \|= UCR4_OREN;	1452	ucr4 \|= UCR4_OREN;
1453	if (sport->inverted_rx)	1453	if (sport->inverted_rx)
1454	ucr4 \|= UCR4_INVR;	1454	ucr4 \|= UCR4_INVR;

drivers/tty/serial/sc16is7xx.c+2−4

 	/* Disable all interrupts */
 	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
-	/* Disable TX/RX, clear auto RS485 and RTS invert */
+	/* Disable TX/RX */
 	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
 			      SC16IS7XX_EFCR_RXDISABLE_BIT |
-			      SC16IS7XX_EFCR_TXDISABLE_BIT |
+			      SC16IS7XX_EFCR_TXDISABLE_BIT,
-			      SC16IS7XX_EFCR_AUTO_RS485_BIT |
-			      SC16IS7XX_EFCR_RTS_INVERT_BIT,
 			      SC16IS7XX_EFCR_RXDISABLE_BIT |
 			      SC16IS7XX_EFCR_TXDISABLE_BIT);

drivers/usb/cdns3/cdns3-gadget.c+5−2

 	struct usb_request *request;
 	struct cdns3_request *priv_req;
 	struct cdns3_trb *trb = NULL;
+	struct cdns3_trb trb_tmp;
 	int ret;
 	int val;
 	if (request) {
 		priv_req = to_cdns3_request(request);
 		trb = priv_req->trb;
-		if (trb)
+		if (trb) {
+			trb_tmp = *trb;
 			trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE);
+		}
 	}
 	writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
 	if (request) {
 		if (trb)
-			trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE);
+			*trb = trb_tmp;
 		cdns3_rearm_transfer(priv_ep, 1);
 	}

drivers/usb/class/cdc-wdm.c+1−0

@@ -774,6 +774,7 @@ static int wdm_release(struct inode inode, struct file file) · 773 unmodified lines
774	poison_urbs(desc);	774	poison_urbs(desc);
775	spin_lock_irq(&desc->iuspin);	775	spin_lock_irq(&desc->iuspin);
776	desc->resp_count = 0;	776	desc->resp_count = 0;
		777	clear_bit(WDM_RESPONDING, &desc->flags);
777	spin_unlock_irq(&desc->iuspin);	778	spin_unlock_irq(&desc->iuspin);
778	desc->manage_power(desc->intf, 0);	779	desc->manage_power(desc->intf, 0);
779	unpoison_urbs(desc);	780	unpoison_urbs(desc);

drivers/usb/core/devio.c+9−5

 		usb_unlock_device(dev);
 		i = usbfs_start_wait_urb(urb, tmo, &actlen);
+		/* Linger a bit, prior to the next control message. */
+		if (dev->quirks & USB_QUIRK_DELAY_CTRL_MSG)
+			msleep(200);
 		usb_lock_device(dev);
 		snoop_urb(dev, NULL, pipe, actlen, i, COMPLETE, tbuf, actlen);
 		if (!i && actlen) {
 			if (copy_to_user(ctrl->data, tbuf, actlen)) {
 				ret = -EFAULT;
-				goto recv_fault;
+				goto done;
 			}
 		}
 	} else {
 		usb_unlock_device(dev);
 		i = usbfs_start_wait_urb(urb, tmo, &actlen);
+		/* Linger a bit, prior to the next control message. */
+		if (dev->quirks & USB_QUIRK_DELAY_CTRL_MSG)
+			msleep(200);
 		usb_lock_device(dev);
 		snoop_urb(dev, NULL, pipe, actlen, i, COMPLETE, NULL, 0);
 	}
 	}
 	ret = (i < 0 ? i : actlen);
- recv_fault:
-	/* Linger a bit, prior to the next control message. */
-	if (dev->quirks & USB_QUIRK_DELAY_CTRL_MSG)
-		msleep(200);
  done:
 	kfree(dr);
 	usb_free_urb(urb);

drivers/usb/core/quirks.c+6−0

 	{ USB_DEVICE(0x0b05, 0x17e0), .driver_info =
 			USB_QUIRK_IGNORE_REMOTE_WAKEUP },
+	/* Realtek Semiconductor Corp. Mass Storage Device (Multicard Reader)*/
+	{ USB_DEVICE(0x0bda, 0x0151), .driver_info = USB_QUIRK_CONFIG_INTF_STRINGS },
 	/* Realtek hub in Dell WD19 (Type-C) */
 	{ USB_DEVICE(0x0bda, 0x0487), .driver_info = USB_QUIRK_NO_LPM },
 	/* DJI CineSSD */
 	{ USB_DEVICE(0x2ca3, 0x0031), .driver_info = USB_QUIRK_NO_LPM },
+	/* VCOM device */
+	{ USB_DEVICE(0x4296, 0x7570), .driver_info = USB_QUIRK_CONFIG_INTF_STRINGS },
 	/* INTEL VALUE SSD */
 	{ USB_DEVICE(0x8086, 0xf1a5), .driver_info = USB_QUIRK_RESET_RESUME },

drivers/usb/dwc3/core.c+29−5

 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 	reg |= DWC3_DCTL_CSFTRST;
-	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
+	reg &= ~DWC3_DCTL_RUN_STOP;
+	dwc3_gadget_dctl_write_safe(dwc, reg);
 	/*
 	 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 	u8			lpm_nyet_threshold;
 	u8			tx_de_emphasis;
 	u8			hird_threshold;
-	u8			rx_thr_num_pkt_prd;
+	u8			rx_thr_num_pkt_prd = 0;
-	u8			rx_max_burst_prd;
+	u8			rx_max_burst_prd = 0;
-	u8			tx_thr_num_pkt_prd;
+	u8			tx_thr_num_pkt_prd = 0;
-	u8			tx_max_burst_prd;
+	u8			tx_max_burst_prd = 0;
 	u8			tx_fifo_resize_max_num;
 	const char		*usb_psy_name;
 	int			ret;
 		/*
 		 * Clocks are optional, but new DT platforms should support all
 		 * clocks as required by the DT-binding.
+		 * Some devices have different clock names in legacy device trees,
+		 * check for them to retain backwards compatibility.
 		 */
 		dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
 		if (IS_ERR(dwc->bus_clk))
 			return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
 					     "could not get bus clock\n");
+		if (dwc->bus_clk == NULL) {
+			dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
+			if (IS_ERR(dwc->bus_clk))
+				return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
+						     "could not get bus clock\n");
+		}
 		dwc->ref_clk = devm_clk_get_optional(dev, "ref");
 		if (IS_ERR(dwc->ref_clk))
 			return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
 					     "could not get ref clock\n");
+		if (dwc->ref_clk == NULL) {
+			dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
+			if (IS_ERR(dwc->ref_clk))
+				return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
+						     "could not get ref clock\n");
+		}
 		dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
 		if (IS_ERR(dwc->susp_clk))
 			return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
 					     "could not get suspend clock\n");
+		if (dwc->susp_clk == NULL) {
+			dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
+			if (IS_ERR(dwc->susp_clk))
+				return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
+						     "could not get suspend clock\n");
+		}
 	}
 	ret = reset_control_deassert(dwc->reset);

drivers/usb/dwc3/drd.c+5−6

 {
 	int ret, irq;
+	if (ROLE_SWITCH &&
+	    device_property_read_bool(dwc->dev, "usb-role-switch"))
+		return dwc3_setup_role_switch(dwc);
 	dwc->edev = dwc3_get_extcon(dwc);
 	if (IS_ERR(dwc->edev))
 		return PTR_ERR(dwc->edev);
-	if (ROLE_SWITCH &&
+	if (dwc->edev) {
-	    device_property_read_bool(dwc->dev, "usb-role-switch")) {
-		ret = dwc3_setup_role_switch(dwc);
-		if (ret < 0)
-			return ret;
-	} else if (dwc->edev) {
 		dwc->edev_nb.notifier_call = dwc3_drd_notifier;
 		ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
 					       &dwc->edev_nb);

drivers/usb/dwc3/dwc3-pci.c+8−0

 #define PCI_DEVICE_ID_INTEL_ADLM		0x54ee
 #define PCI_DEVICE_ID_INTEL_ADLS		0x7ae1
 #define PCI_DEVICE_ID_INTEL_RPLS		0x7a61
+#define PCI_DEVICE_ID_INTEL_MTLP		0x7ec1
+#define PCI_DEVICE_ID_INTEL_MTL			0x7e7e
 #define PCI_DEVICE_ID_INTEL_TGL			0x9a15
 #define PCI_DEVICE_ID_AMD_MR			0x163a
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS),
 	  (kernel_ulong_t) &dwc3_pci_intel_swnode, },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP),
+	  (kernel_ulong_t) &dwc3_pci_intel_swnode, },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL),
+	  (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
 	  (kernel_ulong_t) &dwc3_pci_intel_swnode, },

drivers/usb/dwc3/gadget.c+30−1

@@ -3274,6 +3274,7 @@ static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, · 3273 unmodified lines
3274	const struct dwc3_event_depevt *event,	3274	const struct dwc3_event_depevt *event,
3275	struct dwc3_request *req, int status)	3275	struct dwc3_request *req, int status)
3276	{	3276	{
		3277	int request_status;
3277	int ret;	3278	int ret;
3278		3279
3279	if (req->request.num_mapped_sgs)	3280	if (req->request.num_mapped_sgs)
@@ -3294,7 +3295,35 @@ static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, · 14 unmodified lines
3294	req->needs_extra_trb = false;	3295	req->needs_extra_trb = false;
3295	}	3296	}
3296		3297
3297	dwc3_gadget_giveback(dep, req, status);	3298	/*
		3299	* The event status only reflects the status of the TRB with IOC set.
		3300	* For the requests that don't set interrupt on completion, the driver
		3301	* needs to check and return the status of the completed TRBs associated
		3302	* with the request. Use the status of the last TRB of the request.
		3303	*/
		3304	if (req->request.no_interrupt) {
		3305	struct dwc3_trb *trb;
		3306
		3307	trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
		3308	switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
		3309	case DWC3_TRBSTS_MISSED_ISOC:
		3310	/* Isoc endpoint only */
		3311	request_status = -EXDEV;
		3312	break;
		3313	case DWC3_TRB_STS_XFER_IN_PROG:
		3314	/* Applicable when End Transfer with ForceRM=0 */
		3315	case DWC3_TRBSTS_SETUP_PENDING:
		3316	/* Control endpoint only */
		3317	case DWC3_TRBSTS_OK:
		3318	default:
		3319	request_status = 0;
		3320	break;
		3321	}
		3322	} else {
		3323	request_status = status;
		3324	}
		3325
		3326	dwc3_gadget_giveback(dep, req, request_status);
3298		3327
3299	out:	3328	out:
3300	return ret;	3329	return ret;

drivers/usb/gadget/configfs.c+2−0

 	usb_ep_autoconfig_reset(cdev->gadget);
 	spin_lock_irqsave(&gi->spinlock, flags);
 	cdev->gadget = NULL;
+	cdev->deactivations = 0;
+	gadget->deactivated = false;
 	set_gadget_data(gadget, NULL);
 	spin_unlock_irqrestore(&gi->spinlock, flags);
 }

drivers/usb/gadget/function/f_uvc.c+25−0

@@ -890,13 +890,37 @@ static void uvc_function_unbind(struct usb_configuration *c, · 889 unmodified lines
890	{	890	{
891	struct usb_composite_dev *cdev = c->cdev;	891	struct usb_composite_dev *cdev = c->cdev;
892	struct uvc_device *uvc = to_uvc(f);	892	struct uvc_device *uvc = to_uvc(f);
		893	long wait_ret = 1;
893		894
894	uvcg_info(f, "%s()\n", __func__);	895	uvcg_info(f, "%s()\n", __func__);
895		896
		897	/* If we know we're connected via v4l2, then there should be a cleanup
		898	* of the device from userspace either via UVC_EVENT_DISCONNECT or
		899	* though the video device removal uevent. Allow some time for the
		900	* application to close out before things get deleted.
		901	*/
		902	if (uvc->func_connected) {
		903	uvcg_dbg(f, "waiting for clean disconnect\n");
		904	wait_ret = wait_event_interruptible_timeout(uvc->func_connected_queue,
		905	uvc->func_connected == false, msecs_to_jiffies(500));
		906	uvcg_dbg(f, "done waiting with ret: %ld\n", wait_ret);
		907	}
		908
896	device_remove_file(&uvc->vdev.dev, &dev_attr_function_name);	909	device_remove_file(&uvc->vdev.dev, &dev_attr_function_name);
897	video_unregister_device(&uvc->vdev);	910	video_unregister_device(&uvc->vdev);
898	v4l2_device_unregister(&uvc->v4l2_dev);	911	v4l2_device_unregister(&uvc->v4l2_dev);
899		912
		913	if (uvc->func_connected) {
		914	/* Wait for the release to occur to ensure there are no longer any
		915	* pending operations that may cause panics when resources are cleaned
		916	* up.
		917	*/
		918	uvcg_warn(f, "%s no clean disconnect, wait for release\n", __func__);
		919	wait_ret = wait_event_interruptible_timeout(uvc->func_connected_queue,
		920	uvc->func_connected == false, msecs_to_jiffies(1000));
		921	uvcg_dbg(f, "done waiting for release with ret: %ld\n", wait_ret);
		922	}
		923
900	usb_ep_free_request(cdev->gadget->ep0, uvc->control_req);	924	usb_ep_free_request(cdev->gadget->ep0, uvc->control_req);
901	kfree(uvc->control_buf);	925	kfree(uvc->control_buf);
902		926
@@ -915,6 +939,7 @@ static struct usb_function uvc_alloc(struct usb_function_instance fi) · 12 unmodified lines
915		939
916	mutex_init(&uvc->video.mutex);	940	mutex_init(&uvc->video.mutex);
917	uvc->state = UVC_STATE_DISCONNECTED;	941	uvc->state = UVC_STATE_DISCONNECTED;
		942	init_waitqueue_head(&uvc->func_connected_queue);
918	opts = fi_to_f_uvc_opts(fi);	943	opts = fi_to_f_uvc_opts(fi);
919		944
920	mutex_lock(&opts->lock);	945	mutex_lock(&opts->lock);

drivers/usb/gadget/function/uvc.h+2−0

 #include <linux/spinlock.h>
 #include <linux/usb/composite.h>
 #include <linux/videodev2.h>
+#include <linux/wait.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-dev.h>
 	struct usb_function func;
 	struct uvc_video video;
 	bool func_connected;
+	wait_queue_head_t func_connected_queue;
 	/* Descriptors */
 	struct {

drivers/usb/gadget/function/uvc_queue.c+2−0

@@ -264,6 +264,8 @@ void uvcg_queue_cancel(struct uvc_video_queue *queue, int disconnect) · 263 unmodified lines
264	buf->state = UVC_BUF_STATE_ERROR;	264	buf->state = UVC_BUF_STATE_ERROR;
265	vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR);	265	vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR);
266	}	266	}
		267	queue->buf_used = 0;
		268
267	/* This must be protected by the irqlock spinlock to avoid race	269	/* This must be protected by the irqlock spinlock to avoid race
268	* conditions between uvc_queue_buffer and the disconnection event that	270	* conditions between uvc_queue_buffer and the disconnection event that
269	* could result in an interruptible wait in uvc_dequeue_buffer. Do not	271	* could result in an interruptible wait in uvc_dequeue_buffer. Do not

drivers/usb/gadget/function/uvc_v4l2.c+2−1

 static void uvc_v4l2_disable(struct uvc_device *uvc)
 {
-	uvc->func_connected = false;
 	uvc_function_disconnect(uvc);
 	uvcg_video_enable(&uvc->video, 0);
 	uvcg_free_buffers(&uvc->video.queue);
+	uvc->func_connected = false;
+	wake_up_interruptible(&uvc->func_connected_queue);
 }
 static int

drivers/usb/gadget/legacy/raw_gadget.c+2−0

 	STATE_DEV_INVALID = 0,
 	STATE_DEV_OPENED,
 	STATE_DEV_INITIALIZED,
+	STATE_DEV_REGISTERING,
 	STATE_DEV_RUNNING,
 	STATE_DEV_CLOSED,
 	STATE_DEV_FAILED
 		ret = -EINVAL;
 		goto out_unlock;
 	}
+	dev->state = STATE_DEV_REGISTERING;
 	spin_unlock_irqrestore(&dev->lock, flags);
 	ret = usb_gadget_probe_driver(&dev->driver);

drivers/usb/host/ehci-hcd.c+23−0

@@ -1103,6 +1103,26 @@ static void ehci_remove_device(struct usb_hcd hcd, struct usb_device udev) · 1102 unmodified lines
1103		1103
1104	#ifdef CONFIG_PM	1104	#ifdef CONFIG_PM
1105		1105
		1106	/* Clear wakeup signal locked in zhaoxin platform when device plug in. */
		1107	static void ehci_zx_wakeup_clear(struct ehci_hcd *ehci)
		1108	{
		1109	u32 __iomem *reg = &ehci->regs->port_status[4];
		1110	u32 t1 = ehci_readl(ehci, reg);
		1111
		1112	t1 &= (u32)~0xf0000;
		1113	t1 \|= PORT_TEST_FORCE;
		1114	ehci_writel(ehci, t1, reg);
		1115	t1 = ehci_readl(ehci, reg);
		1116	msleep(1);
		1117	t1 &= (u32)~0xf0000;
		1118	ehci_writel(ehci, t1, reg);
		1119	ehci_readl(ehci, reg);
		1120	msleep(1);
		1121	t1 = ehci_readl(ehci, reg);
		1122	ehci_writel(ehci, t1 \| PORT_CSC, reg);
		1123	ehci_readl(ehci, reg);
		1124	}
		1125
1106	/* suspend/resume, section 4.3 */	1126	/* suspend/resume, section 4.3 */
1107		1127
1108	/* These routines handle the generic parts of controller suspend/resume */	1128	/* These routines handle the generic parts of controller suspend/resume */
@@ -1154,6 +1174,9 @@ int ehci_resume(struct usb_hcd *hcd, bool force_reset) · 45 unmodified lines
1154	if (ehci->shutdown)	1174	if (ehci->shutdown)
1155	return 0; /* Controller is dead */	1175	return 0; /* Controller is dead */
1156		1176
		1177	if (ehci->zx_wakeup_clear_needed)
		1178	ehci_zx_wakeup_clear(ehci);
		1179
1157	/*	1180	/*
1158	* If CF is still set and reset isn't forced	1181	* If CF is still set and reset isn't forced
1159	* then we maintained suspend power.	1182	* then we maintained suspend power.

drivers/usb/host/ehci-pci.c+4−0

 			ehci->is_aspeed = 1;
 		}
 		break;
+	case PCI_VENDOR_ID_ZHAOXIN:
+		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x90)
+			ehci->zx_wakeup_clear_needed = 1;
+		break;
 	}
 	/* optional debug port, normally in the first BAR */

drivers/usb/host/ehci.h+1−0

@@ -220,6 +220,7 @@ struct ehci_hcd { /* one per controller */ · 219 unmodified lines
220	unsigned imx28_write_fix:1; /* For Freescale i.MX28 */	220	unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
221	unsigned spurious_oc:1;	221	unsigned spurious_oc:1;
222	unsigned is_aspeed:1;	222	unsigned is_aspeed:1;
		223	unsigned zx_wakeup_clear_needed:1;
223		224
224	/* required for usb32 quirk */	225	/* required for usb32 quirk */
225	#define OHCI_CTRL_HCFS (3 << 6)	226	#define OHCI_CTRL_HCFS (3 << 6)

drivers/usb/host/xhci-hub.c+1−1

@@ -1434,7 +1434,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, · 1433 unmodified lines
1434	}	1434	}
1435	spin_unlock_irqrestore(&xhci->lock, flags);	1435	spin_unlock_irqrestore(&xhci->lock, flags);
1436	if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],	1436	if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1437	msecs_to_jiffies(100)))	1437	msecs_to_jiffies(500)))
1438	xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",	1438	xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1439	hcd->self.busnum, wIndex + 1);	1439	hcd->self.busnum, wIndex + 1);
1440	spin_lock_irqsave(&xhci->lock, flags);	1440	spin_lock_irqsave(&xhci->lock, flags);

drivers/usb/host/xhci-mtk-sch.c+19−71

 #define HS_BW_BOUNDARY	6144
 /* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
 #define FS_PAYLOAD_MAX 188
-/*
- * max number of microframes for split transfer,
- * for fs isoc in : 1 ss + 1 idle + 7 cs
- */
-#define TT_MICROFRAMES_MAX 9
 #define DBG_BUF_EN	64
 static struct mu3h_sch_ep_info *
 create_sch_ep(struct xhci_hcd_mtk *mtk, struct usb_device *udev,
-	      struct usb_host_endpoint *ep, struct xhci_ep_ctx *ep_ctx)
+	      struct usb_host_endpoint *ep)
 {
 	struct mu3h_sch_ep_info *sch_ep;
 	struct mu3h_sch_bw_info *bw_info;
 	struct mu3h_sch_tt *tt = NULL;
-	u32 len_bw_budget_table;
 	bw_info = get_bw_info(mtk, udev, ep);
 	if (!bw_info)
 		return ERR_PTR(-ENODEV);
-	if (is_fs_or_ls(udev->speed))
+	sch_ep = kzalloc(sizeof(*sch_ep), GFP_KERNEL);
-		len_bw_budget_table = TT_MICROFRAMES_MAX;
-	else if ((udev->speed >= USB_SPEED_SUPER)
-			&& usb_endpoint_xfer_isoc(&ep->desc))
-		len_bw_budget_table = get_esit(ep_ctx);
-	else
-		len_bw_budget_table = 1;
-	sch_ep = kzalloc(struct_size(sch_ep, bw_budget_table,
-				     len_bw_budget_table),
-			 GFP_KERNEL);
 	if (!sch_ep)
 		return ERR_PTR(-ENOMEM);
 	u32 mult;
 	u32 esit_pkts;
 	u32 max_esit_payload;
-	u32 *bwb_table = sch_ep->bw_budget_table;
-	int i;
 	ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
 	maxpkt = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
 		 */
 		sch_ep->pkts = max_burst + 1;
 		sch_ep->bw_cost_per_microframe = maxpkt * sch_ep->pkts;
-		bwb_table[0] = sch_ep->bw_cost_per_microframe;
 	} else if (sch_ep->speed >= USB_SPEED_SUPER) {
 		/* usb3_r1 spec section4.4.7 & 4.4.8 */
 		sch_ep->cs_count = 0;
 		if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 			sch_ep->pkts = esit_pkts;
 			sch_ep->num_budget_microframes = 1;
-			bwb_table[0] = maxpkt * sch_ep->pkts;
 		}
 		if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
 				DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
 			sch_ep->repeat = !!(sch_ep->num_budget_microframes > 1);
-			sch_ep->bw_cost_per_microframe = maxpkt * sch_ep->pkts;
-			for (i = 0; i < sch_ep->num_budget_microframes - 1; i++)
-				bwb_table[i] = sch_ep->bw_cost_per_microframe;
-			/* last one <= bw_cost_per_microframe */
-			bwb_table[i] = maxpkt * esit_pkts
-				       - i * sch_ep->bw_cost_per_microframe;
 		}
+		sch_ep->bw_cost_per_microframe = maxpkt * sch_ep->pkts;
 	} else if (is_fs_or_ls(sch_ep->speed)) {
 		sch_ep->pkts = 1; /* at most one packet for each microframe */
 		 */
 		sch_ep->cs_count = DIV_ROUND_UP(maxpkt, FS_PAYLOAD_MAX);
 		sch_ep->num_budget_microframes = sch_ep->cs_count;
-		sch_ep->bw_cost_per_microframe =
+		sch_ep->bw_cost_per_microframe = min_t(u32, maxpkt, FS_PAYLOAD_MAX);
-			(maxpkt < FS_PAYLOAD_MAX) ? maxpkt : FS_PAYLOAD_MAX;
-		/* init budget table */
-		if (ep_type == ISOC_OUT_EP) {
-			for (i = 0; i < sch_ep->num_budget_microframes; i++)
-				bwb_table[i] =	sch_ep->bw_cost_per_microframe;
-		} else if (ep_type == INT_OUT_EP) {
-			/* only first one consumes bandwidth, others as zero */
-			bwb_table[0] = sch_ep->bw_cost_per_microframe;
-		} else { /* INT_IN_EP or ISOC_IN_EP */
-			bwb_table[0] = 0; /* start split */
-			bwb_table[1] = 0; /* idle */
-			/*
-			 * due to cs_count will be updated according to cs
-			 * position, assign all remainder budget array
-			 * elements as @bw_cost_per_microframe, but only first
-			 * @num_budget_microframes elements will be used later
-			 */
-			for (i = 2; i < TT_MICROFRAMES_MAX; i++)
-				bwb_table[i] =	sch_ep->bw_cost_per_microframe;
-		}
 	}
 }
 		for (j = 0; j < sch_ep->num_budget_microframes; j++) {
 			k = XHCI_MTK_BW_INDEX(base + j);
-			bw = sch_bw->bus_bw[k] + sch_ep->bw_budget_table[j];
+			bw = sch_bw->bus_bw[k] + sch_ep->bw_cost_per_microframe;
 			if (bw > max_bw)
 				max_bw = bw;
 		}
 static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
 	struct mu3h_sch_ep_info *sch_ep, bool used)
 {
+	int bw_updated;
 	u32 base;
-	int i, j, k;
+	int i, j;
+	bw_updated = sch_ep->bw_cost_per_microframe * (used ? 1 : -1);
 	for (i = 0; i < sch_ep->num_esit; i++) {
 		base = sch_ep->offset + i * sch_ep->esit;
-		for (j = 0; j < sch_ep->num_budget_microframes; j++) {
+		for (j = 0; j < sch_ep->num_budget_microframes; j++)
-			k = XHCI_MTK_BW_INDEX(base + j);
+			sch_bw->bus_bw[XHCI_MTK_BW_INDEX(base + j)] += bw_updated;
-			if (used)
-				sch_bw->bus_bw[k] += sch_ep->bw_budget_table[j];
-			else
-				sch_bw->bus_bw[k] -= sch_ep->bw_budget_table[j];
-		}
 	}
 }
 		 */
 		for (j = 0; j < sch_ep->num_budget_microframes; j++) {
 			k = XHCI_MTK_BW_INDEX(base + j);
-			tmp = tt->fs_bus_bw[k] + sch_ep->bw_budget_table[j];
+			tmp = tt->fs_bus_bw[k] + sch_ep->bw_cost_per_microframe;
 			if (tmp > FS_PAYLOAD_MAX)
 				return -ESCH_BW_OVERFLOW;
 		}
 static void update_sch_tt(struct mu3h_sch_ep_info *sch_ep, bool used)
 {
 	struct mu3h_sch_tt *tt = sch_ep->sch_tt;
+	int bw_updated;
 	u32 base;
-	int i, j, k;
+	int i, j;
+	bw_updated = sch_ep->bw_cost_per_microframe * (used ? 1 : -1);
 	for (i = 0; i < sch_ep->num_esit; i++) {
 		base = sch_ep->offset + i * sch_ep->esit;
-		for (j = 0; j < sch_ep->num_budget_microframes; j++) {
+		for (j = 0; j < sch_ep->num_budget_microframes; j++)
-			k = XHCI_MTK_BW_INDEX(base + j);
+			tt->fs_bus_bw[XHCI_MTK_BW_INDEX(base + j)] += bw_updated;
-			if (used)
-				tt->fs_bus_bw[k] += sch_ep->bw_budget_table[j];
-			else
-				tt->fs_bus_bw[k] -= sch_ep->bw_budget_table[j];
-		}
 	}
 	if (used)
 	xhci_dbg(xhci, "%s %s\n", __func__, decode_ep(ep, udev->speed));
-	sch_ep = create_sch_ep(mtk, udev, ep, ep_ctx);
+	sch_ep = create_sch_ep(mtk, udev, ep);
 	if (IS_ERR_OR_NULL(sch_ep))
 		return -ENOMEM;

drivers/usb/host/xhci-mtk.h+0−2

  *		times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
  *		according to @pkts and @repeat. normal mode is used by
  *		default
- * @bw_budget_table: table to record bandwidth budget per microframe
  */
 struct mu3h_sch_ep_info {
 	u32 esit;
 	u32 pkts;
 	u32 cs_count;
 	u32 burst_mode;
-	u32 bw_budget_table[];
 };
 #define MU3C_U3_PORT_MAX 4

drivers/usb/host/xhci-pci.c+3−1

 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI		0x9a13
 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI		0x1138
 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI		0x461e
+#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI	0x51ed
 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI			0x1639
 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4			0x43b9
 	     pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 	     pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 	     pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
-	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
+	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
+	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI))
 		xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&

drivers/usb/host/xhci-ring.c+1−0

@@ -3141,6 +3141,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) · 3140 unmodified lines
3141	if (event_loop++ < TRBS_PER_SEGMENT / 2)	3141	if (event_loop++ < TRBS_PER_SEGMENT / 2)
3142	continue;	3142	continue;
3143	xhci_update_erst_dequeue(xhci, event_ring_deq);	3143	xhci_update_erst_dequeue(xhci, event_ring_deq);
		3144	event_ring_deq = xhci->event_ring->dequeue;
3144		3145
3145	/* ring is half-full, force isoc trbs to interrupt more often */	3146	/* ring is half-full, force isoc trbs to interrupt more often */
3146	if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)	3147	if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)

drivers/usb/host/xhci-tegra.c+2−2

@@ -1034,13 +1034,13 @@ static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra) · 1033 unmodified lines
1034	int rc;	1034	int rc;
1035		1035
1036	if (tegra->use_genpd) {	1036	if (tegra->use_genpd) {
1037	rc = pm_runtime_get_sync(tegra->genpd_dev_ss);	1037	rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss);
1038	if (rc < 0) {	1038	if (rc < 0) {
1039	dev_err(dev, "failed to enable XUSB SS partition\n");	1039	dev_err(dev, "failed to enable XUSB SS partition\n");
1040	return rc;	1040	return rc;
1041	}	1041	}
1042		1042
1043	rc = pm_runtime_get_sync(tegra->genpd_dev_host);	1043	rc = pm_runtime_resume_and_get(tegra->genpd_dev_host);
1044	if (rc < 0) {	1044	if (rc < 0) {
1045	dev_err(dev, "failed to enable XUSB Host partition\n");	1045	dev_err(dev, "failed to enable XUSB Host partition\n");
1046	pm_runtime_put_sync(tegra->genpd_dev_ss);	1046	pm_runtime_put_sync(tegra->genpd_dev_ss);

drivers/usb/host/xhci.c+11−0

@@ -781,6 +781,17 @@ void xhci_shutdown(struct usb_hcd *hcd) · 780 unmodified lines
781	if (xhci->quirks & XHCI_SPURIOUS_REBOOT)	781	if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
782	usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));	782	usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
783		783
		784	/* Don't poll the roothubs after shutdown. */
		785	xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
		786	__func__, hcd->self.busnum);
		787	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
		788	del_timer_sync(&hcd->rh_timer);
		789
		790	if (xhci->shared_hcd) {
		791	clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
		792	del_timer_sync(&xhci->shared_hcd->rh_timer);
		793	}
		794
784	spin_lock_irq(&xhci->lock);	795	spin_lock_irq(&xhci->lock);
785	xhci_halt(xhci);	796	xhci_halt(xhci);
786	/* Workaround for spurious wakeups at shutdown with HSW */	797	/* Workaround for spurious wakeups at shutdown with HSW */

drivers/usb/misc/qcom_eud.c+5−5

 	chip->dev = &pdev->dev;
-	ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip);
-	if (ret)
-		return dev_err_probe(chip->dev, ret,
-				"failed to add role switch release action\n");
 	chip->role_sw = usb_role_switch_get(&pdev->dev);
 	if (IS_ERR(chip->role_sw))
 		return dev_err_probe(chip->dev, PTR_ERR(chip->role_sw),
 					"failed to get role switch\n");
+	ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip);
+	if (ret)
+		return dev_err_probe(chip->dev, ret,
+				"failed to add role switch release action\n");
 	chip->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(chip->base))
 		return PTR_ERR(chip->base);

drivers/usb/misc/uss720.c+1−2

 	dev_dbg(&priv->usbdev->dev, "destroying priv datastructure\n");
 	usb_put_dev(priv->usbdev);
+	priv->usbdev = NULL;
 	kfree(priv);
 }
 	parport_announce_port(pp);
 	usb_set_intfdata(intf, pp);
-	usb_put_dev(usbdev);
 	return 0;
 probe_abort:
 	usb_set_intfdata(intf, NULL);
 	if (pp) {
 		priv = pp->private_data;
-		priv->usbdev = NULL;
 		priv->pp = NULL;
 		dev_dbg(&intf->dev, "parport_remove_port\n");
 		parport_remove_port(pp);

drivers/usb/mtu3/mtu3_dr.c+2−4

 static void toggle_opstate(struct ssusb_mtk *ssusb)
 {
-	if (!ssusb->otg_switch.is_u3_drd) {
+	mtu3_setbits(ssusb->mac_base, U3D_DEVICE_CONTROL, DC_SESSION);
-		mtu3_setbits(ssusb->mac_base, U3D_DEVICE_CONTROL, DC_SESSION);
+	mtu3_setbits(ssusb->mac_base, U3D_POWER_MANAGEMENT, SOFT_CONN);
-		mtu3_setbits(ssusb->mac_base, U3D_POWER_MANAGEMENT, SOFT_CONN);
-	}
 }
 /* only port0 supports dual-role mode */

drivers/usb/phy/phy-generic.c+7−0

@@ -268,6 +268,13 @@ int usb_phy_gen_create_phy(struct device dev, struct usb_phy_generic nop) · 267 unmodified lines
268	return -EPROBE_DEFER;	268	return -EPROBE_DEFER;
269	}	269	}
270		270
		271	nop->vbus_draw = devm_regulator_get_exclusive(dev, "vbus");
		272	if (PTR_ERR(nop->vbus_draw) == -ENODEV)
		273	nop->vbus_draw = NULL;
		274	if (IS_ERR(nop->vbus_draw))
		275	return dev_err_probe(dev, PTR_ERR(nop->vbus_draw),
		276	"could not get vbus regulator\n");
		277
271	nop->dev = dev;	278	nop->dev = dev;
272	nop->phy.dev = nop->dev;	279	nop->phy.dev = nop->dev;
273	nop->phy.label = "nop-xceiv";	280	nop->phy.label = "nop-xceiv";

drivers/usb/serial/cp210x.c+2−0

 	{ USB_DEVICE(0x16DC, 0x0015) }, /* W-IE-NE-R Plein & Baus GmbH CML Control, Monitoring and Data Logger */
 	{ USB_DEVICE(0x17A8, 0x0001) }, /* Kamstrup Optical Eye/3-wire */
 	{ USB_DEVICE(0x17A8, 0x0005) }, /* Kamstrup M-Bus Master MultiPort 250D */
+	{ USB_DEVICE(0x17A8, 0x0101) }, /* Kamstrup 868 MHz wM-Bus C-Mode Meter Reader (Int Ant) */
+	{ USB_DEVICE(0x17A8, 0x0102) }, /* Kamstrup 868 MHz wM-Bus C-Mode Meter Reader (Ext Ant) */
 	{ USB_DEVICE(0x17F4, 0xAAAA) }, /* Wavesense Jazz blood glucose meter */
 	{ USB_DEVICE(0x1843, 0x0200) }, /* Vaisala USB Instrument Cable */
 	{ USB_DEVICE(0x18EF, 0xE00F) }, /* ELV USB-I2C-Interface */

drivers/usb/serial/option.c+16−0

 #define CINTERION_PRODUCT_CLS8			0x00b0
 #define CINTERION_PRODUCT_MV31_MBIM		0x00b3
 #define CINTERION_PRODUCT_MV31_RMNET		0x00b7
+#define CINTERION_PRODUCT_MV32_WA		0x00f1
+#define CINTERION_PRODUCT_MV32_WB		0x00f2
 /* Olivetti products */
 #define OLIVETTI_VENDOR_ID			0x0b3c
 	  .driver_info = NCTRL(0) | RSVD(1) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1056, 0xff),	/* Telit FD980 */
 	  .driver_info = NCTRL(2) | RSVD(3) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1057, 0xff),	/* Telit FN980 */
+	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1058, 0xff),	/* Telit FN980 (PCIe) */
+	  .driver_info = NCTRL(0) | RSVD(1) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1060, 0xff),	/* Telit LN920 (rmnet) */
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1061, 0xff),	/* Telit LN920 (MBIM) */
 	  .driver_info = NCTRL(2) | RSVD(3) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1073, 0xff),	/* Telit FN990 (ECM) */
 	  .driver_info = NCTRL(0) | RSVD(1) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1075, 0xff),	/* Telit FN990 (PCIe) */
+	  .driver_info = RSVD(0) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(3) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910_DUAL_MODEM),
 	  .driver_info = RSVD(3)},
 	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV31_RMNET, 0xff),
 	  .driver_info = RSVD(0)},
+	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV32_WA, 0xff),
+	  .driver_info = RSVD(3)},
+	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_MV32_WB, 0xff),
+	  .driver_info = RSVD(3)},
 	{ USB_DEVICE(OLIVETTI_VENDOR_ID, OLIVETTI_PRODUCT_OLICARD100),
 	  .driver_info = RSVD(4) },
 	{ USB_DEVICE(OLIVETTI_VENDOR_ID, OLIVETTI_PRODUCT_OLICARD120),
 	  .driver_info = RSVD(3) },
 	{ USB_DEVICE(0x1508, 0x1001),						/* Fibocom NL668 (IOT version) */
 	  .driver_info = RSVD(4) | RSVD(5) | RSVD(6) },
+	{ USB_DEVICE(0x1782, 0x4d10) },						/* Fibocom L610 (AT mode) */
+	{ USB_DEVICE_INTERFACE_CLASS(0x1782, 0x4d11, 0xff) },			/* Fibocom L610 (ECM/RNDIS mode) */
 	{ USB_DEVICE(0x2cb7, 0x0104),						/* Fibocom NL678 series */
 	  .driver_info = RSVD(4) | RSVD(5) },
 	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x0105, 0xff),			/* Fibocom NL678 series */
 	  .driver_info = RSVD(6) },
+	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x0106, 0xff) },			/* Fibocom MA510 (ECM mode w/ diag intf.) */
+	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x010a, 0xff) },			/* Fibocom MA510 (ECM mode) */
 	{ USB_DEVICE_AND_INTERFACE_INFO(0x2cb7, 0x010b, 0xff, 0xff, 0x30) },	/* Fibocom FG150 Diag */
 	{ USB_DEVICE_AND_INTERFACE_INFO(0x2cb7, 0x010b, 0xff, 0, 0) },		/* Fibocom FG150 AT */
 	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a0, 0xff) },			/* Fibocom NL668-AM/NL652-EU (laptop MBIM) */

drivers/usb/serial/pl2303.c+1−0

@@ -106,6 +106,7 @@ static const struct usb_device_id id_table[] = { · 105 unmodified lines
106	{ USB_DEVICE(HP_VENDOR_ID, HP_LCM220_PRODUCT_ID) },	106	{ USB_DEVICE(HP_VENDOR_ID, HP_LCM220_PRODUCT_ID) },
107	{ USB_DEVICE(HP_VENDOR_ID, HP_LCM960_PRODUCT_ID) },	107	{ USB_DEVICE(HP_VENDOR_ID, HP_LCM960_PRODUCT_ID) },
108	{ USB_DEVICE(HP_VENDOR_ID, HP_LM920_PRODUCT_ID) },	108	{ USB_DEVICE(HP_VENDOR_ID, HP_LM920_PRODUCT_ID) },
		109	{ USB_DEVICE(HP_VENDOR_ID, HP_LM930_PRODUCT_ID) },
109	{ USB_DEVICE(HP_VENDOR_ID, HP_LM940_PRODUCT_ID) },	110	{ USB_DEVICE(HP_VENDOR_ID, HP_LM940_PRODUCT_ID) },
110	{ USB_DEVICE(HP_VENDOR_ID, HP_TD620_PRODUCT_ID) },	111	{ USB_DEVICE(HP_VENDOR_ID, HP_TD620_PRODUCT_ID) },
111	{ USB_DEVICE(CRESSI_VENDOR_ID, CRESSI_EDY_PRODUCT_ID) },	112	{ USB_DEVICE(CRESSI_VENDOR_ID, CRESSI_EDY_PRODUCT_ID) },

drivers/usb/serial/pl2303.h+1−0

@@ -135,6 +135,7 @@ · 134 unmodified lines
135	#define HP_TD620_PRODUCT_ID 0x0956	135	#define HP_TD620_PRODUCT_ID 0x0956
136	#define HP_LD960_PRODUCT_ID 0x0b39	136	#define HP_LD960_PRODUCT_ID 0x0b39
137	#define HP_LD381_PRODUCT_ID 0x0f7f	137	#define HP_LD381_PRODUCT_ID 0x0f7f
		138	#define HP_LM930_PRODUCT_ID 0x0f9b
138	#define HP_LCM220_PRODUCT_ID 0x3139	139	#define HP_LCM220_PRODUCT_ID 0x3139
139	#define HP_LCM960_PRODUCT_ID 0x3239	140	#define HP_LCM960_PRODUCT_ID 0x3239
140	#define HP_LD220_PRODUCT_ID 0x3524	141	#define HP_LD220_PRODUCT_ID 0x3524

drivers/usb/serial/qcserial.c+2−0

 	{DEVICE_SWI(0x1199, 0x9090)},	/* Sierra Wireless EM7565 QDL */
 	{DEVICE_SWI(0x1199, 0x9091)},	/* Sierra Wireless EM7565 */
 	{DEVICE_SWI(0x1199, 0x90d2)},	/* Sierra Wireless EM9191 QDL */
+	{DEVICE_SWI(0x1199, 0xc080)},	/* Sierra Wireless EM7590 QDL */
+	{DEVICE_SWI(0x1199, 0xc081)},	/* Sierra Wireless EM7590 */
 	{DEVICE_SWI(0x413c, 0x81a2)},	/* Dell Wireless 5806 Gobi(TM) 4G LTE Mobile Broadband Card */
 	{DEVICE_SWI(0x413c, 0x81a3)},	/* Dell Wireless 5570 HSPA+ (42Mbps) Mobile Broadband Card */
 	{DEVICE_SWI(0x413c, 0x81a4)},	/* Dell Wireless 5570e HSPA+ (42Mbps) Mobile Broadband Card */

drivers/usb/serial/whiteheat.c+2−3

 		switch (command) {
 		case WHITEHEAT_GET_DTR_RTS:
 			info = usb_get_serial_port_data(port);
-			memcpy(&info->mcr, command_info->result_buffer,
+			info->mcr = command_info->result_buffer[0];
-					sizeof(struct whiteheat_dr_info));
+			break;
-				break;
 		}
 	}
 exit:

drivers/usb/typec/Kconfig+1−0

@@ -56,6 +56,7 @@ config TYPEC_RT1719 · 55 unmodified lines
56	tristate "Richtek RT1719 Sink Only Type-C controller driver"	56	tristate "Richtek RT1719 Sink Only Type-C controller driver"
57	depends on USB_ROLE_SWITCH \|\| !USB_ROLE_SWITCH	57	depends on USB_ROLE_SWITCH \|\| !USB_ROLE_SWITCH
58	depends on I2C	58	depends on I2C
		59	depends on POWER_SUPPLY
59	select REGMAP_I2C	60	select REGMAP_I2C
60	help	61	help
61	Say Y or M here if your system has Richtek RT1719 sink only	62	Say Y or M here if your system has Richtek RT1719 sink only

drivers/usb/typec/tcpm/tcpci.c+1−1

@@ -877,7 +877,7 @@ static int tcpci_remove(struct i2c_client *client) · 876 unmodified lines
877	/* Disable chip interrupts before unregistering port */	877	/* Disable chip interrupts before unregistering port */
878	err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0);	878	err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0);
879	if (err < 0)	879	if (err < 0)
880	return err;	880	dev_warn(&client->dev, "Failed to disable irqs (%pe)\n", ERR_PTR(err));
881		881
882	tcpci_unregister_port(chip->tcpci);	882	tcpci_unregister_port(chip->tcpci);
883		883

drivers/usb/typec/tcpm/tcpci_mt6360.c+26−0

@@ -15,6 +15,9 @@ · 14 unmodified lines
15		15
16	#include "tcpci.h"	16	#include "tcpci.h"
17		17
		18	#define MT6360_REG_PHYCTRL1 0x80
		19	#define MT6360_REG_PHYCTRL3 0x82
		20	#define MT6360_REG_PHYCTRL7 0x86
18	#define MT6360_REG_VCONNCTRL1 0x8C	21	#define MT6360_REG_VCONNCTRL1 0x8C
19	#define MT6360_REG_MODECTRL2 0x8F	22	#define MT6360_REG_MODECTRL2 0x8F
20	#define MT6360_REG_SWRESET 0xA0	23	#define MT6360_REG_SWRESET 0xA0
@@ -22,6 +25,8 @@ · 1 unmodified line
22	#define MT6360_REG_DRPCTRL1 0xA2	25	#define MT6360_REG_DRPCTRL1 0xA2
23	#define MT6360_REG_DRPCTRL2 0xA3	26	#define MT6360_REG_DRPCTRL2 0xA3
24	#define MT6360_REG_I2CTORST 0xBF	27	#define MT6360_REG_I2CTORST 0xBF
		28	#define MT6360_REG_PHYCTRL11 0xCA
		29	#define MT6360_REG_RXCTRL1 0xCE
25	#define MT6360_REG_RXCTRL2 0xCF	30	#define MT6360_REG_RXCTRL2 0xCF
26	#define MT6360_REG_CTDCTRL2 0xEC	31	#define MT6360_REG_CTDCTRL2 0xEC
27		32
@@ -106,6 +111,27 @@ static int mt6360_tcpc_init(struct tcpci tcpci, struct tcpci_data tdata) · 78 unmodified lines
106	if (ret)	111	if (ret)
107	return ret;	112	return ret;
108		113
		114	/* BMC PHY */
		115	ret = mt6360_tcpc_write16(regmap, MT6360_REG_PHYCTRL1, 0x3A70);
		116	if (ret)
		117	return ret;
		118
		119	ret = regmap_write(regmap, MT6360_REG_PHYCTRL3, 0x82);
		120	if (ret)
		121	return ret;
		122
		123	ret = regmap_write(regmap, MT6360_REG_PHYCTRL7, 0x36);
		124	if (ret)
		125	return ret;
		126
		127	ret = mt6360_tcpc_write16(regmap, MT6360_REG_PHYCTRL11, 0x3C60);
		128	if (ret)
		129	return ret;
		130
		131	ret = regmap_write(regmap, MT6360_REG_RXCTRL1, 0xE8);
		132	if (ret)
		133	return ret;
		134
109	/* Set shipping mode off, AUTOIDLE on */	135	/* Set shipping mode off, AUTOIDLE on */
110	return regmap_write(regmap, MT6360_REG_MODECTRL2, 0x7A);	136	return regmap_write(regmap, MT6360_REG_MODECTRL2, 0x7A);
111	}	137	}

drivers/usb/typec/ucsi/ucsi.c+17−7

@@ -949,6 +949,8 @@ static int ucsi_dr_swap(struct typec_port *port, enum typec_data_role role) · 948 unmodified lines
949	role == TYPEC_HOST))	949	role == TYPEC_HOST))
950	goto out_unlock;	950	goto out_unlock;
951		951
		952	reinit_completion(&con->complete);
		953
952	command = UCSI_SET_UOR \| UCSI_CONNECTOR_NUMBER(con->num);	954	command = UCSI_SET_UOR \| UCSI_CONNECTOR_NUMBER(con->num);
953	command \|= UCSI_SET_UOR_ROLE(role);	955	command \|= UCSI_SET_UOR_ROLE(role);
954	command \|= UCSI_SET_UOR_ACCEPT_ROLE_SWAPS;	956	command \|= UCSI_SET_UOR_ACCEPT_ROLE_SWAPS;
@@ -956,14 +958,18 @@ static int ucsi_dr_swap(struct typec_port *port, enum typec_data_role role) · 1 unmodified line
956	if (ret < 0)	958	if (ret < 0)
957	goto out_unlock;	959	goto out_unlock;
958		960
		961	mutex_unlock(&con->lock);
		962
959	if (!wait_for_completion_timeout(&con->complete,	963	if (!wait_for_completion_timeout(&con->complete,
960	msecs_to_jiffies(UCSI_SWAP_TIMEOUT_MS)))	964	msecs_to_jiffies(UCSI_SWAP_TIMEOUT_MS)))
961	ret = -ETIMEDOUT;	965	return -ETIMEDOUT;
		966
		967	return 0;
962		968
963	out_unlock:	969	out_unlock:
964	mutex_unlock(&con->lock);	970	mutex_unlock(&con->lock);
965		971
966	return ret < 0 ? ret : 0;	972	return ret;
967	}	973	}
968		974
969	static int ucsi_pr_swap(struct typec_port *port, enum typec_role role)	975	static int ucsi_pr_swap(struct typec_port *port, enum typec_role role)
@@ -985,6 +991,8 @@ static int ucsi_pr_swap(struct typec_port *port, enum typec_role role) · 15 unmodified lines
985	if (cur_role == role)	991	if (cur_role == role)
986	goto out_unlock;	992	goto out_unlock;
987		993
		994	reinit_completion(&con->complete);
		995
988	command = UCSI_SET_PDR \| UCSI_CONNECTOR_NUMBER(con->num);	996	command = UCSI_SET_PDR \| UCSI_CONNECTOR_NUMBER(con->num);
989	command \|= UCSI_SET_PDR_ROLE(role);	997	command \|= UCSI_SET_PDR_ROLE(role);
990	command \|= UCSI_SET_PDR_ACCEPT_ROLE_SWAPS;	998	command \|= UCSI_SET_PDR_ACCEPT_ROLE_SWAPS;
@@ -992,11 +1000,13 @@ static int ucsi_pr_swap(struct typec_port *port, enum typec_role role) · 1 unmodified line
992	if (ret < 0)	1000	if (ret < 0)
993	goto out_unlock;	1001	goto out_unlock;
994		1002
		1003	mutex_unlock(&con->lock);
		1004
995	if (!wait_for_completion_timeout(&con->complete,	1005	if (!wait_for_completion_timeout(&con->complete,
996	msecs_to_jiffies(UCSI_SWAP_TIMEOUT_MS))) {	1006	msecs_to_jiffies(UCSI_SWAP_TIMEOUT_MS)))
997	ret = -ETIMEDOUT;	1007	return -ETIMEDOUT;
998	goto out_unlock;	1008
999	}	1009	mutex_lock(&con->lock);
1000		1010
1001	/* Something has gone wrong while swapping the role */	1011	/* Something has gone wrong while swapping the role */
1002	if (UCSI_CONSTAT_PWR_OPMODE(con->status.flags) !=	1012	if (UCSI_CONSTAT_PWR_OPMODE(con->status.flags) !=

drivers/vfio/fsl-mc/vfio_fsl_mc.c+1−0

@@ -588,6 +588,7 @@ static struct fsl_mc_driver vfio_fsl_mc_driver = { · 587 unmodified lines
588	.name = "vfio-fsl-mc",	588	.name = "vfio-fsl-mc",
589	.owner = THIS_MODULE,	589	.owner = THIS_MODULE,
590	},	590	},
		591	.driver_managed_dma = true,
591	};	592	};
592		593
593	static int __init vfio_fsl_mc_driver_init(void)	594	static int __init vfio_fsl_mc_driver_init(void)

drivers/vfio/pci/vfio_pci.c+1−0

@@ -194,6 +194,7 @@ static struct pci_driver vfio_pci_driver = { · 193 unmodified lines
194	.remove = vfio_pci_remove,	194	.remove = vfio_pci_remove,
195	.sriov_configure = vfio_pci_sriov_configure,	195	.sriov_configure = vfio_pci_sriov_configure,
196	.err_handler = &vfio_pci_core_err_handlers,	196	.err_handler = &vfio_pci_core_err_handlers,
		197	.driver_managed_dma = true,
197	};	198	};
198		199
199	static void __init vfio_pci_fill_ids(void)	200	static void __init vfio_pci_fill_ids(void)

drivers/vfio/platform/vfio_amba.c+1−0

@@ -95,6 +95,7 @@ static struct amba_driver vfio_amba_driver = { · 94 unmodified lines
95	.name = "vfio-amba",	95	.name = "vfio-amba",
96	.owner = THIS_MODULE,	96	.owner = THIS_MODULE,
97	},	97	},
		98	.driver_managed_dma = true,
98	};	99	};
99		100
100	module_amba_driver(vfio_amba_driver);	101	module_amba_driver(vfio_amba_driver);

drivers/vfio/platform/vfio_platform.c+1−0

@@ -76,6 +76,7 @@ static struct platform_driver vfio_platform_driver = { · 75 unmodified lines
76	.driver = {	76	.driver = {
77	.name = "vfio-platform",	77	.name = "vfio-platform",
78	},	78	},
		79	.driver_managed_dma = true,
79	};	80	};
80		81
81	module_platform_driver(vfio_platform_driver);	82	module_platform_driver(vfio_platform_driver);

drivers/vfio/vfio.c+22−230

 	bool				noiommu;
 };
-struct vfio_unbound_dev {
-	struct device			*dev;
-	struct list_head		unbound_next;
-};
 struct vfio_group {
 	struct device 			dev;
 	struct cdev			cdev;
 	struct vfio_container		*container;
 	struct list_head		device_list;
 	struct mutex			device_lock;
-	struct notifier_block		nb;
 	struct list_head		vfio_next;
 	struct list_head		container_next;
-	struct list_head		unbound_list;
-	struct mutex			unbound_lock;
 	atomic_t			opened;
 	wait_queue_head_t		container_q;
 	enum vfio_group_type		type;
 }
 EXPORT_SYMBOL_GPL(vfio_unregister_iommu_driver);
-static int vfio_iommu_group_notifier(struct notifier_block *nb,
-				     unsigned long action, void *data);
 static void vfio_group_get(struct vfio_group *group);
 /*
 static void vfio_group_release(struct device *dev)
 {
 	struct vfio_group *group = container_of(dev, struct vfio_group, dev);
-	struct vfio_unbound_dev *unbound, *tmp;

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@@ -4345,12 +4345,12 @@ · 4344 unmodified lines
4345	#define _DSPAADDR 0x70184	4345	#define _DSPAADDR 0x70184
4346	#define _DSPASTRIDE 0x70188	4346	#define _DSPASTRIDE 0x70188
4347	#define _DSPAPOS 0x7018C /* reserved */	4347	#define _DSPAPOS 0x7018C /* reserved */
4348	#define DISP_POS_Y_MASK REG_GENMASK(31, 0)	4348	#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
4349	#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))	4349	#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
4350	#define DISP_POS_X_MASK REG_GENMASK(15, 0)	4350	#define DISP_POS_X_MASK REG_GENMASK(15, 0)
4351	#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))	4351	#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
4352	#define _DSPASIZE 0x70190	4352	#define _DSPASIZE 0x70190
4353	#define DISP_HEIGHT_MASK REG_GENMASK(31, 0)	4353	#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
4354	#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))	4354	#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
4355	#define DISP_WIDTH_MASK REG_GENMASK(15, 0)	4355	#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
4356	#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))	4356	#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
@@ -5152,7 +5152,7 @@ · 795 unmodified lines
5152	#define _SEL_FETCH_PLANE_BASE_6_A 0x70940	5152	#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
5153	#define _SEL_FETCH_PLANE_BASE_7_A 0x70960	5153	#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
5154	#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880	5154	#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
5155	#define _SEL_FETCH_PLANE_BASE_1_B 0x70990	5155	#define _SEL_FETCH_PLANE_BASE_1_B 0x71890
5156		5156
5157	#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \	5157	#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
5158	_SEL_FETCH_PLANE_BASE_1_A, \	5158	_SEL_FETCH_PLANE_BASE_1_A, \