History

Merge tag 'drm-intel-next-2018-09-06-2' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Merge tag 'gvt-next-2018-09-04' drm-intel-next-2018-09-06-1: UAPI Changes: - GGTT coherency GETPARAM: GGTT has turned out to be non-coherent for some platforms, which we've failed to communicate to userspace so far. SNA was modified to do extra flushing on non-coherent GGTT access, while Mesa will mitigate by always requiring WC mapping (which is non-coherent anyway). - Neuter Resource Streamer uAPI: There never really were users for the feature, so neuter it while keeping the interface bits for compatibility. This is a long due item from past. Cross-subsystem Changes: - Backmerge of branch drm-next-4.19 for DP_DPCD_REV_14 changes Core Changes: - None Driver Changes: - A load of Icelake (ICL) enabling patches (Paulo, Manasi) - Enabled full PPGTT for IVB,VLV and HSW (Chris) - Bugzilla #107113: Distribute DDB based on display resolutions (Mahesh) - Bugzillas #100023,#107476,#94921: Support limited range DP displays (Jani) - Bugzilla #107503: Increase LSPCON timeout (Fredrik) - Avoid boosting GPU due to an occasional stall in interactive workloads (Chris) - Apply GGTT coherency W/A only for affected systems instead of all (Chris) - Fix for infinite link training loop for faulty USB-C MST hubs (Nathan) - Keep KMS functional on Gen4 and earlier when GPU is wedged (Chris) - Stop holding ppGTT reference from closed VMAs (Chris) - Clear error registers after error capture (Lionel) - Various Icelake fixes (Anusha, Jyoti, Ville, Tvrtko) - Add missing Coffeelake (CFL) PCI IDs (Rodrigo) - Flush execlists tasklet directly from reset-finish (Chris) - Fix LPE audio runtime PM (Chris) - Fix detection of out of range surface positions (GLK/CNL) (Ville) - Remove wait-for-idle for PSR2 (Dhinakaran) - Power down existing display hardware resources when display is disabled (Chris) - Don't allow runtime power management if RC6 doesn't exist (Chris) - Add debugging checks for runtime power management paths (Imre) - Increase symmetry in display power init/fini paths (Imre) - Isolate GVT specific macros from i915_reg.h (Lucas) - Increase symmetry in power management enable/disable paths (Chris) - Increase IP disable timeout to 100 ms to avoid DRM_ERROR (Imre) - Fix memory leak from HDMI HDCP write function (Brian, Rodrigo) - Reject Y/Yf tiling on interlaced modes (Ville) - Use a cached mapping for the physical HWS on older gens (Chris) - Force slow path of writing relocations to buffer if unable to write to userspace (Chris) - Do a full device reset after being wedged (Chris) - Keep forcewake counts over reset (in case of debugfs user) (Imre, Chris) - Avoid false-positive errors from power wells during init (Imre) - Reset engines forcibly in exchange of declaring whole device wedged (Mika) - Reduce context HW ID lifetime in preparation for Icelake (Chris) - Attempt to recover from module load failures (Chris) - Keep select interrupts over a reset to avoid missing/losing them (Chris) - GuC submission backend improvements (Jakub) - Terminate context images with BB_END (Chris, Lionel) - Make GCC evaluate GGTT view struct size assertions again (Ville) - Add selftest to exercise suspend/hibernate code-paths for GEM (Chris) - Use a full emulation of a user ppgtt context in selftests (Chris) - Exercise resetting in the middle of a wait-on-fence in selftests (Chris) - Fix coherency issues on selftests for Baytrail (Chris) - Various other GEM fixes / self-test updates (Chris, Matt) - GuC doorbell self-tests (Daniele) - PSR mode control through debugfs for IGTs (Maarten) - Degrade expected WM latency errors to DRM_DEBUG_KMS (Chris) - Cope with errors better in MST link training (Dhinakaran) - Fix WARN on KBL external displays (Azhar) - Power well code cleanups (Imre) - Fixes to PSR debugging (Dhinakaran) - Make forcewake errors louder for easier catching in CI (WARNs) (Chris) - Fortify tiling code against programmer errors (Chris) - Bunch of fixes for CI exposed corner cases (multiple authors, mostly Chris) Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 8 years ago

Commit b1c15662 parents 1f3eb34 a28957b87 files · +3857 −1806Browse files

Unified · Split

87 files
  1. drivers/gpu/drm/i915/Kconfig.debug +12 −0
  2. drivers/gpu/drm/i915/gvt/cfg_space.c +12 −0
  3. drivers/gpu/drm/i915/gvt/cmd_parser.c +10 −1
  4. drivers/gpu/drm/i915/gvt/display.c +1 −0
  5. drivers/gpu/drm/i915/gvt/edid.c +9 −0
  6. drivers/gpu/drm/i915/gvt/gtt.c +6 −3
  7. drivers/gpu/drm/i915/gvt/gvt.c +1 −2
  8. drivers/gpu/drm/i915/gvt/handlers.c +12 −22
  9. drivers/gpu/drm/i915/gvt/kvmgt.c +2 −2
  10. drivers/gpu/drm/i915/gvt/mmio.c +2 −1
  11. drivers/gpu/drm/i915/gvt/mmio_context.c +0 −13
  12. drivers/gpu/drm/i915/gvt/mmio_context.h +3 −0
  13. drivers/gpu/drm/i915/gvt/opregion.c +0 −1
  14. drivers/gpu/drm/i915/gvt/page_track.c +2 −0
  15. drivers/gpu/drm/i915/gvt/reg.h +18 −0
  16. drivers/gpu/drm/i915/gvt/scheduler.c +34 −30
  17. drivers/gpu/drm/i915/i915_debugfs.c +64 −24
  18. drivers/gpu/drm/i915/i915_drv.c +104 −90
  19. drivers/gpu/drm/i915/i915_drv.h +49 −14
  20. drivers/gpu/drm/i915/i915_gem.c +52 −13
  21. drivers/gpu/drm/i915/i915_gem.h +0 −6
  22. drivers/gpu/drm/i915/i915_gem_context.c +161 −71
  23. drivers/gpu/drm/i915/i915_gem_context.h +23 −3
  24. drivers/gpu/drm/i915/i915_gem_execbuffer.c +21 −22
  25. drivers/gpu/drm/i915/i915_gem_gtt.c +25 −27
  26. drivers/gpu/drm/i915/i915_gem_gtt.h +10 −13
  27. drivers/gpu/drm/i915/i915_gem_object.h +5 −5
  28. drivers/gpu/drm/i915/i915_irq.c +26 −10
  29. drivers/gpu/drm/i915/i915_pci.c +11 −5
  30. drivers/gpu/drm/i915/i915_perf.c +24 −31
  31. drivers/gpu/drm/i915/i915_reg.h +387 −340
  32. drivers/gpu/drm/i915/i915_request.c +4 −5
  33. drivers/gpu/drm/i915/i915_request.h +25 −14
  34. drivers/gpu/drm/i915/i915_vma.c +4 −1
  35. drivers/gpu/drm/i915/i915_vma.h +9 −1
  36. drivers/gpu/drm/i915/intel_atomic_plane.c +4 −2
  37. drivers/gpu/drm/i915/intel_breadcrumbs.c +2 −4
  38. drivers/gpu/drm/i915/intel_csr.c +24 −9
  39. drivers/gpu/drm/i915/intel_ddi.c +223 −17
  40. drivers/gpu/drm/i915/intel_device_info.h +1 −1
  41. drivers/gpu/drm/i915/intel_display.c +115 −57
  42. drivers/gpu/drm/i915/intel_display.h +26 −2
  43. drivers/gpu/drm/i915/intel_dp.c +451 −83
  44. drivers/gpu/drm/i915/intel_dp_link_training.c +20 −5
  45. drivers/gpu/drm/i915/intel_dp_mst.c +7 −7
  46. drivers/gpu/drm/i915/intel_dpll_mgr.c +46 −16
  47. drivers/gpu/drm/i915/intel_dpll_mgr.h +1 −0
  48. drivers/gpu/drm/i915/intel_drv.h +33 −10
  49. drivers/gpu/drm/i915/intel_engine_cs.c +41 −52
  50. drivers/gpu/drm/i915/intel_guc.c +46 −56
  51. drivers/gpu/drm/i915/intel_guc.h +5 −7
  52. drivers/gpu/drm/i915/intel_guc_ads.c +1 −1
  53. drivers/gpu/drm/i915/intel_guc_ct.c +2 −5
  54. drivers/gpu/drm/i915/intel_guc_fwif.h +1 −0
  55. drivers/gpu/drm/i915/intel_guc_log.c +1 −1
  56. drivers/gpu/drm/i915/intel_guc_submission.c +20 −15
  57. drivers/gpu/drm/i915/intel_guc_submission.h +4 −0
  58. drivers/gpu/drm/i915/intel_hangcheck.c +1 −1
  59. drivers/gpu/drm/i915/intel_hdcp.c +3 −3
  60. drivers/gpu/drm/i915/intel_hdmi.c +7 −3
  61. drivers/gpu/drm/i915/intel_huc.c +1 −1
  62. drivers/gpu/drm/i915/intel_i2c.c +8 −8
  63. drivers/gpu/drm/i915/intel_lrc.c +110 −49
  64. drivers/gpu/drm/i915/intel_lrc.h +0 −2
  65. drivers/gpu/drm/i915/intel_lrc_reg.h +1 −1
  66. drivers/gpu/drm/i915/intel_mocs.c +3 −8
  67. drivers/gpu/drm/i915/intel_mocs.h +1 −1
  68. drivers/gpu/drm/i915/intel_pm.c +62 −39
  69. drivers/gpu/drm/i915/intel_psr.c +192 −85
  70. drivers/gpu/drm/i915/intel_ringbuffer.c +56 −54
  71. drivers/gpu/drm/i915/intel_ringbuffer.h +29 −10
  72. drivers/gpu/drm/i915/intel_runtime_pm.c +674 −329
  73. drivers/gpu/drm/i915/intel_sprite.c +7 −6
  74. drivers/gpu/drm/i915/intel_uc_fw.c +1 −1
  75. drivers/gpu/drm/i915/intel_uncore.c +92 −38
  76. drivers/gpu/drm/i915/intel_wopcm.c +6 −0
  77. drivers/gpu/drm/i915/selftests/huge_pages.c +6 −5
  78. drivers/gpu/drm/i915/selftests/i915_gem.c +221 −0
  79. drivers/gpu/drm/i915/selftests/i915_gem_coherency.c +17 −21
  80. drivers/gpu/drm/i915/selftests/i915_gem_object.c +1 −1
  81. drivers/gpu/drm/i915/selftests/i915_live_selftests.h +1 −0
  82. drivers/gpu/drm/i915/selftests/intel_guc.c +38 −0
  83. drivers/gpu/drm/i915/selftests/intel_hangcheck.c +89 −12
  84. drivers/gpu/drm/i915/selftests/mock_context.c +3 −8
  85. drivers/gpu/drm/i915/selftests/mock_gtt.c +2 −0
  86. include/drm/i915_pciids.h +1 −0
  87. include/uapi/drm/i915_drm.h +22 −0
drivers/gpu/drm/i915/Kconfig.debug+12−0
@@ -30,6 +30,7 @@ config DRM_I915_DEBUG · 29 unmodified lines
3030 select SW_SYNC # signaling validation framework (igt/syncobj*)
3131 select DRM_I915_SW_FENCE_DEBUG_OBJECTS
3232 select DRM_I915_SELFTEST
33+ select DRM_I915_DEBUG_RUNTIME_PM
3334 default n
3435 help
3536 Choose this option to turn on extra driver debugging that may affect
@@ -167,3 +168,14 @@ config DRM_I915_DEBUG_VBLANK_EVADE · 131 unmodified lines
167168 the vblank.
168169
169170 If in doubt, say "N".
171+
172+config DRM_I915_DEBUG_RUNTIME_PM
173+ bool "Enable extra state checking for runtime PM"
174+ depends on DRM_I915
175+ default n
176+ help
177+ Choose this option to turn on extra state checking for the
178+ runtime PM functionality. This may introduce overhead during
179+ driver loading, suspend and resume operations.
180+
181+ If in doubt, say "N"
drivers/gpu/drm/i915/gvt/cfg_space.c+12−0
@@ -56,6 +56,10 @@ static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = { · 55 unmodified lines
5656
5757 /**
5858 * vgpu_pci_cfg_mem_write - write virtual cfg space memory
59+ * @vgpu: target vgpu
60+ * @off: offset
61+ * @src: src ptr to write
62+ * @bytes: number of bytes
5963 *
6064 * Use this function to write virtual cfg space memory.
6165 * For standard cfg space, only RW bits can be changed,
@@ -91,6 +95,10 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, · 29 unmodified lines
9195
9296 /**
9397 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
98+ * @vgpu: target vgpu
99+ * @offset: offset
100+ * @p_data: return data ptr
101+ * @bytes: number of bytes to read
94102 *
95103 * Returns:
96104 * Zero on success, negative error code if failed.
@@ -278,6 +286,10 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, · 181 unmodified lines
278286
279287 /**
280288 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
289+ * @vgpu: target vgpu
290+ * @offset: offset
291+ * @p_data: write data ptr
292+ * @bytes: number of bytes to write
281293 *
282294 * Returns:
283295 * Zero on success, negative error code if failed.
drivers/gpu/drm/i915/gvt/cmd_parser.c+10−1
@@ -1840,6 +1840,8 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) · 1839 unmodified lines
18401840 return ret;
18411841 }
18421842
1843+static int mi_noop_index;
1844+
18431845 static struct cmd_info cmd_info[] = {
18441846 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
18451847
@@ -2525,7 +2527,12 @@ static int cmd_parser_exec(struct parser_exec_state *s) · 679 unmodified lines
25252527
25262528 cmd = cmd_val(s, 0);
25272529
2528− info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2530+ /* fastpath for MI_NOOP */
2531+ if (cmd == MI_NOOP)
2532+ info = &cmd_info[mi_noop_index];
2533+ else
2534+ info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2535+
25292536 if (info == NULL) {
25302537 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
25312538 cmd, get_opcode(cmd, s->ring_id),
@@ -2928,6 +2935,8 @@ static int init_cmd_table(struct intel_gvt *gvt) · 396 unmodified lines
29282935 kfree(e);
29292936 return -EEXIST;
29302937 }
2938+ if (cmd_info[i].opcode == OP_MI_NOOP)
2939+ mi_noop_index = i;
29312940
29322941 INIT_HLIST_NODE(&e->hlist);
29332942 add_cmd_entry(gvt, e);
drivers/gpu/drm/i915/gvt/display.c+1−0
@@ -462,6 +462,7 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) · 461 unmodified lines
462462 /**
463463 * intel_vgpu_init_display- initialize vGPU virtual display emulation
464464 * @vgpu: a vGPU
465+ * @resolution: resolution index for intel_vgpu_edid
465466 *
466467 * This function is used to initialize vGPU virtual display emulation stuffs
467468 *
drivers/gpu/drm/i915/gvt/edid.c+9−0
@@ -340,6 +340,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, · 339 unmodified lines
340340 /**
341341 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
342342 * @vgpu: a vGPU
343+ * @offset: reg offset
344+ * @p_data: data return buffer
345+ * @bytes: access data length
343346 *
344347 * This function is used to emulate gmbus register mmio read
345348 *
@@ -365,6 +368,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, · 19 unmodified lines
365368 /**
366369 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
367370 * @vgpu: a vGPU
371+ * @offset: reg offset
372+ * @p_data: data return buffer
373+ * @bytes: access data length
368374 *
369375 * This function is used to emulate gmbus register mmio write
370376 *
@@ -437,6 +443,9 @@ static inline int get_aux_ch_reg(unsigned int offset) · 66 unmodified lines
437443 /**
438444 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
439445 * @vgpu: a vGPU
446+ * @port_idx: port index
447+ * @offset: reg offset
448+ * @p_data: write ptr
440449 *
441450 * This function is used to emulate AUX channel register write
442451 *
drivers/gpu/drm/i915/gvt/gtt.c+6−3
@@ -1113,6 +1113,10 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se, · 1112 unmodified lines
11131113 }
11141114
11151115 /**
1116+ * Check if can do 2M page
1117+ * @vgpu: target vgpu
1118+ * @entry: target pfn's gtt entry
1119+ *
11161120 * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
11171121 * negtive if found err.
11181122 */
@@ -1945,7 +1949,7 @@ void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm) · 826 unmodified lines
19451949
19461950 /**
19471951 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1948− * @vgpu: a vGPU
1952+ * @mm: target vgpu mm
19491953 *
19501954 * This function is called when user wants to use a vGPU mm object. If this
19511955 * mm object hasn't been shadowed yet, the shadow will be populated at this
@@ -2521,8 +2525,7 @@ fail: · 569 unmodified lines
25212525 /**
25222526 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
25232527 * @vgpu: a vGPU
2524− * @page_table_level: PPGTT page table level
2525− * @root_entry: PPGTT page table root pointers
2528+ * @pdps: pdp root array
25262529 *
25272530 * This function is used to find a PPGTT mm object from mm object pool
25282531 *
drivers/gpu/drm/i915/gvt/gvt.c+1−2
@@ -189,7 +189,6 @@ static const struct intel_gvt_ops intel_gvt_ops = { · 188 unmodified lines
189189
190190 /**
191191 * intel_gvt_init_host - Load MPT modules and detect if we're running in host
192− * @gvt: intel gvt device
193192 *
194193 * This function is called at the driver loading stage. If failed to find a
195194 * loadable MPT module or detect currently we're running in a VM, then GVT-g
@@ -303,7 +302,7 @@ static int init_service_thread(struct intel_gvt *gvt) · 107 unmodified lines
303302
304303 /**
305304 * intel_gvt_clean_device - clean a GVT device
306− * @gvt: intel gvt device
305+ * @dev_priv: i915 private
307306 *
308307 * This function is called at the driver unloading stage, to free the
309308 * resources owned by a GVT device.
drivers/gpu/drm/i915/gvt/handlers.c+12−22
@@ -1287,12 +1287,13 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, · 1286 unmodified lines
12871287 {
12881288 write_vreg(vgpu, offset, p_data, bytes);
12891289
1290− if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
1290+ if (vgpu_vreg(vgpu, offset) &
1291+ HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
12911292 vgpu_vreg(vgpu, offset) |=
1292− HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1293+ HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
12931294 else
12941295 vgpu_vreg(vgpu, offset) &=
1295− ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1296+ ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
12961297 return 0;
12971298 }
12981299
@@ -2118,7 +2119,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) · 819 unmodified lines
21182119
21192120 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
21202121 gmbus_mmio_write);
2121− MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2122+ MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
21222123 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
21232124
21242125 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
@@ -2443,17 +2444,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) · 318 unmodified lines
24432444 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
24442445 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
24452446 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2446− /*
2447− * Use an arbitrary power well controlled by the PWR_WELL_CTL
2448− * register.
2449− */
2450− MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2451− power_well_ctl_mmio_write);
2452− MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2453− power_well_ctl_mmio_write);
2454− MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2455− MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2456− power_well_ctl_mmio_write);
2447+ MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2448+ MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2449+ MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2450+ MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
24572451 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
24582452 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
24592453
@@ -2804,13 +2798,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) · 344 unmodified lines
28042798 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
28052799 dp_aux_ch_ctl_mmio_write);
28062800
2807− /*
2808− * Use an arbitrary power well controlled by the PWR_WELL_CTL
2809− * register.
2810− */
2811− MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2812− MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2813− skl_power_well_ctl_write);
2801+ MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2802+ MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
28142803
28152804 MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
28162805 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
@@ -3434,6 +3423,7 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, · 617 unmodified lines
34343423 * @offset: register offset
34353424 * @pdata: data buffer
34363425 * @bytes: data length
3426+ * @is_read: read or write
34373427 *
34383428 * Returns:
34393429 * Zero on success, negative error code if failed.
drivers/gpu/drm/i915/gvt/kvmgt.c+2−2
@@ -1712,7 +1712,7 @@ static unsigned long kvmgt_gfn_to_pfn(unsigned long handle, unsigned long gfn) · 1711 unmodified lines
17121712 return pfn;
17131713 }
17141714
1715−int kvmgt_dma_map_guest_page(unsigned long handle, unsigned long gfn,
1715+static int kvmgt_dma_map_guest_page(unsigned long handle, unsigned long gfn,
17161716 unsigned long size, dma_addr_t *dma_addr)
17171717 {
17181718 struct kvmgt_guest_info *info;
@@ -1761,7 +1761,7 @@ static void __gvt_dma_release(struct kref *ref) · 42 unmodified lines
17611761 __gvt_cache_remove_entry(entry->vgpu, entry);
17621762 }
17631763
1764−void kvmgt_dma_unmap_guest_page(unsigned long handle, dma_addr_t dma_addr)
1764+static void kvmgt_dma_unmap_guest_page(unsigned long handle, dma_addr_t dma_addr)
17651765 {
17661766 struct kvmgt_guest_info *info;
17671767 struct gvt_dma *entry;
drivers/gpu/drm/i915/gvt/mmio.c+2−1
@@ -39,6 +39,7 @@ · 38 unmodified lines
3939 /**
4040 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
4141 * @vgpu: a vGPU
42+ * @gpa: guest physical address
4243 *
4344 * Returns:
4445 * Zero on success, negative error code if failed
@@ -228,7 +229,7 @@ out: · 183 unmodified lines
228229 /**
229230 * intel_vgpu_reset_mmio - reset virtual MMIO space
230231 * @vgpu: a vGPU
231− *
232+ * @dmlr: whether this is device model level reset
232233 */
233234 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
234235 {
drivers/gpu/drm/i915/gvt/mmio_context.c+0−13
@@ -37,19 +37,6 @@ · 36 unmodified lines
3737 #include "gvt.h"
3838 #include "trace.h"
3939
40−/**
41− * Defined in Intel Open Source PRM.
42− * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
43− */
44−#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4)
45−#define TRNULLDETCT _MMIO(0x4de8)
46−#define TRINVTILEDETCT _MMIO(0x4dec)
47−#define TRVADR _MMIO(0x4df0)
48−#define TRTTE _MMIO(0x4df4)
49−#define RING_EXCC(base) _MMIO((base) + 0x28)
50−#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
51−#define VF_GUARDBAND _MMIO(0x83a4)
52−
5340 #define GEN9_MOCS_SIZE 64
5441
5542 /* Raw offset is appened to each line for convenience. */
drivers/gpu/drm/i915/gvt/mmio_context.h+3−0
@@ -53,5 +53,8 @@ bool is_inhibit_context(struct intel_context *ce); · 52 unmodified lines
5353
5454 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
5555 struct i915_request *req);
56+#define IS_RESTORE_INHIBIT(a) \
57+ (_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
58+ ((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
5659
5760 #endif
drivers/gpu/drm/i915/gvt/opregion.c+0−1
@@ -216,7 +216,6 @@ static void virt_vbt_generation(struct vbt *v) · 215 unmodified lines
216216 /**
217217 * intel_vgpu_init_opregion - initialize the stuff used to emulate opregion
218218 * @vgpu: a vGPU
219− * @gpa: guest physical address of opregion
220219 *
221220 * Returns:
222221 * Zero on success, negative error code if failed.
drivers/gpu/drm/i915/gvt/page_track.c+2−0
@@ -41,6 +41,8 @@ struct intel_vgpu_page_track *intel_vgpu_find_page_track( · 40 unmodified lines
4141 * intel_vgpu_register_page_track - register a guest page to be tacked
4242 * @vgpu: a vGPU
4343 * @gfn: the gfn of guest page
44+ * @handler: page track handler
45+ * @priv: tracker private
4446 *
4547 * Returns:
4648 * zero on success, negative error code if failed.
drivers/gpu/drm/i915/gvt/reg.h+18−0
@@ -77,4 +77,22 @@ · 76 unmodified lines
7777 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
7878 I915_GTT_PAGE_SIZE)
7979
80+#define PCH_GPIO_BASE _MMIO(0xc5010)
81+
82+#define PCH_GMBUS0 _MMIO(0xc5100)
83+#define PCH_GMBUS1 _MMIO(0xc5104)
84+#define PCH_GMBUS2 _MMIO(0xc5108)
85+#define PCH_GMBUS3 _MMIO(0xc510c)
86+#define PCH_GMBUS4 _MMIO(0xc5110)
87+#define PCH_GMBUS5 _MMIO(0xc5120)
88+
89+#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4)
90+#define TRNULLDETCT _MMIO(0x4de8)
91+#define TRINVTILEDETCT _MMIO(0x4dec)
92+#define TRVADR _MMIO(0x4df0)
93+#define TRTTE _MMIO(0x4df4)
94+#define RING_EXCC(base) _MMIO((base) + 0x28)
95+#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
96+#define VF_GUARDBAND _MMIO(0x83a4)
97+
8098 #endif
drivers/gpu/drm/i915/gvt/scheduler.c+34−30
@@ -132,35 +132,6 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) · 131 unmodified lines
132132 unsigned long context_gpa, context_page_num;
133133 int i;
134134
135− gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
136− workload->ctx_desc.lrca);
137−
138− context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
139−
140− context_page_num = context_page_num >> PAGE_SHIFT;
141−
142− if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
143− context_page_num = 19;
144−
145− i = 2;
146−
147− while (i < context_page_num) {
148− context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
149− (u32)((workload->ctx_desc.lrca + i) <<
150− I915_GTT_PAGE_SHIFT));
151− if (context_gpa == INTEL_GVT_INVALID_ADDR) {
152− gvt_vgpu_err("Invalid guest context descriptor\n");
153− return -EFAULT;
154− }
155−
156− page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
157− dst = kmap(page);
158− intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
159− I915_GTT_PAGE_SIZE);
160− kunmap(page);
161− i++;
162− }
163−
164135 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
165136 shadow_ring_context = kmap(page);
166137
@@ -195,6 +166,37 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) · 28 unmodified lines
195166
196167 sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
197168 kunmap(page);
169+
170+ if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
171+ return 0;
172+
173+ gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
174+ workload->ctx_desc.lrca);
175+
176+ context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
177+
178+ context_page_num = context_page_num >> PAGE_SHIFT;
179+
180+ if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
181+ context_page_num = 19;
182+
183+ i = 2;
184+ while (i < context_page_num) {
185+ context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
186+ (u32)((workload->ctx_desc.lrca + i) <<
187+ I915_GTT_PAGE_SHIFT));
188+ if (context_gpa == INTEL_GVT_INVALID_ADDR) {
189+ gvt_vgpu_err("Invalid guest context descriptor\n");
190+ return -EFAULT;
191+ }
192+
193+ page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
194+ dst = kmap(page);
195+ intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
196+ I915_GTT_PAGE_SIZE);
197+ kunmap(page);
198+ i++;
199+ }
198200 return 0;
199201 }
200202
@@ -1138,6 +1140,7 @@ out_shadow_ctx: · 937 unmodified lines
11381140 /**
11391141 * intel_vgpu_select_submission_ops - select virtual submission interface
11401142 * @vgpu: a vGPU
1143+ * @engine_mask: either ALL_ENGINES or target engine mask
11411144 * @interface: expected vGPU virtual submission interface
11421145 *
11431146 * This function is called when guest configures submission interface.
@@ -1190,7 +1193,7 @@ int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu, · 46 unmodified lines
11901193
11911194 /**
11921195 * intel_vgpu_destroy_workload - destroy a vGPU workload
1193− * @vgpu: a vGPU
1196+ * @workload: workload to destroy
11941197 *
11951198 * This function is called when destroy a vGPU workload.
11961199 *
@@ -1282,6 +1285,7 @@ static int prepare_mm(struct intel_vgpu_workload *workload) · 85 unmodified lines
12821285 /**
12831286 * intel_vgpu_create_workload - create a vGPU workload
12841287 * @vgpu: a vGPU
1288+ * @ring_id: ring index
12851289 * @desc: a guest context descriptor
12861290 *
12871291 * This function is called when creating a vGPU workload.
drivers/gpu/drm/i915/i915_debugfs.c+64−24
@@ -1953,7 +1953,10 @@ static int i915_context_status(struct seq_file *m, void *unused) · 1952 unmodified lines
19531953 return ret;
19541954
19551955 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1956− seq_printf(m, "HW context %u ", ctx->hw_id);
1956+ seq_puts(m, "HW context ");
1957+ if (!list_empty(&ctx->hw_id_link))
1958+ seq_printf(m, "%x [pin %u]", ctx->hw_id,
1959+ atomic_read(&ctx->hw_id_pin_count));
19571960 if (ctx->pid) {
19581961 struct task_struct *task;
19591962
@@ -2708,7 +2711,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) · 748 unmodified lines
27082711 intel_runtime_pm_get(dev_priv);
27092712
27102713 mutex_lock(&dev_priv->psr.lock);
2711− seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2714+ seq_printf(m, "PSR mode: %s\n",
2715+ dev_priv->psr.psr2_enabled ? "PSR2" : "PSR1");
2716+ seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
27122717 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
27132718 dev_priv->psr.busy_frontbuffer_bits);
27142719
@@ -2735,7 +2740,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) · 20 unmodified lines
27352740 psr_source_status(dev_priv, m);
27362741 mutex_unlock(&dev_priv->psr.lock);
27372742
2738− if (READ_ONCE(dev_priv->psr.debug)) {
2743+ if (READ_ONCE(dev_priv->psr.debug) & I915_PSR_DEBUG_IRQ) {
27392744 seq_printf(m, "Last attempted entry at: %lld\n",
27402745 dev_priv->psr.last_entry_attempt);
27412746 seq_printf(m, "Last exit at: %lld\n",
@@ -2750,17 +2755,32 @@ static int · 8 unmodified lines
27502755 i915_edp_psr_debug_set(void *data, u64 val)
27512756 {
27522757 struct drm_i915_private *dev_priv = data;
2758+ struct drm_modeset_acquire_ctx ctx;
2759+ int ret;
27532760
27542761 if (!CAN_PSR(dev_priv))
27552762 return -ENODEV;
27562763
2757− DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
2764+ DRM_DEBUG_KMS("Setting PSR debug to %llx\n", val);
27582765
27592766 intel_runtime_pm_get(dev_priv);
2760− intel_psr_irq_control(dev_priv, !!val);
2767+
2768+ drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2769+
2770+retry:
2771+ ret = intel_psr_set_debugfs_mode(dev_priv, &ctx, val);
2772+ if (ret == -EDEADLK) {
2773+ ret = drm_modeset_backoff(&ctx);
2774+ if (!ret)
2775+ goto retry;
2776+ }
2777+
2778+ drm_modeset_drop_locks(&ctx);
2779+ drm_modeset_acquire_fini(&ctx);
2780+
27612781 intel_runtime_pm_put(dev_priv);
27622782
2763− return 0;
2783+ return ret;
27642784 }
27652785
27662786 static int
@@ -2845,10 +2865,10 @@ static int i915_power_domain_info(struct seq_file *m, void *unused) · 78 unmodified lines
28452865 enum intel_display_power_domain power_domain;
28462866
28472867 power_well = &power_domains->power_wells[i];
2848− seq_printf(m, "%-25s %d\n", power_well->name,
2868+ seq_printf(m, "%-25s %d\n", power_well->desc->name,
28492869 power_well->count);
28502870
2851− for_each_power_domain(power_domain, power_well->domains)
2871+ for_each_power_domain(power_domain, power_well->desc->domains)
28522872 seq_printf(m, " %-23s %d\n",
28532873 intel_display_power_domain_str(power_domain),
28542874 power_domains->domain_use_count[power_domain]);
@@ -4114,13 +4134,17 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, · 1259 unmodified lines
41144134 #define DROP_FREED BIT(4)
41154135 #define DROP_SHRINK_ALL BIT(5)
41164136 #define DROP_IDLE BIT(6)
4137+#define DROP_RESET_ACTIVE BIT(7)
4138+#define DROP_RESET_SEQNO BIT(8)
41174139 #define DROP_ALL (DROP_UNBOUND | \
41184140 DROP_BOUND | \
41194141 DROP_RETIRE | \
41204142 DROP_ACTIVE | \
41214143 DROP_FREED | \
41224144 DROP_SHRINK_ALL |\
4123− DROP_IDLE)
4145+ DROP_IDLE | \
4146+ DROP_RESET_ACTIVE | \
4147+ DROP_RESET_SEQNO)
41244148 static int
41254149 i915_drop_caches_get(void *data, u64 *val)
41264150 {
@@ -4132,53 +4156,69 @@ i915_drop_caches_get(void *data, u64 *val) · 5 unmodified lines
41324156 static int
41334157 i915_drop_caches_set(void *data, u64 val)
41344158 {
4135− struct drm_i915_private *dev_priv = data;
4136− struct drm_device *dev = &dev_priv->drm;
4159+ struct drm_i915_private *i915 = data;
41374160 int ret = 0;
41384161
41394162 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
41404163 val, val & DROP_ALL);
41414164
4165+ if (val & DROP_RESET_ACTIVE && !intel_engines_are_idle(i915))
4166+ i915_gem_set_wedged(i915);
4167+
41424168 /* No need to check and wait for gpu resets, only libdrm auto-restarts
41434169 * on ioctls on -EAGAIN. */
4144− if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4145− ret = mutex_lock_interruptible(&dev->struct_mutex);
4170+ if (val & (DROP_ACTIVE | DROP_RETIRE | DROP_RESET_SEQNO)) {
4171+ ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
41464172 if (ret)
41474173 return ret;
41484174
41494175 if (val & DROP_ACTIVE)
4150− ret = i915_gem_wait_for_idle(dev_priv,
4176+ ret = i915_gem_wait_for_idle(i915,
41514177 I915_WAIT_INTERRUPTIBLE |
41524178 I915_WAIT_LOCKED,
41534179 MAX_SCHEDULE_TIMEOUT);
41544180
4181+ if (val & DROP_RESET_SEQNO) {
4182+ intel_runtime_pm_get(i915);
4183+ ret = i915_gem_set_global_seqno(&i915->drm, 1);
4184+ intel_runtime_pm_put(i915);
4185+ }
4186+
41554187 if (val & DROP_RETIRE)
4156− i915_retire_requests(dev_priv);
4188+ i915_retire_requests(i915);
41574189
4158− mutex_unlock(&dev->struct_mutex);
4190+ mutex_unlock(&i915->drm.struct_mutex);
4191+ }
4192+
4193+ if (val & DROP_RESET_ACTIVE &&
4194+ i915_terminally_wedged(&i915->gpu_error)) {
4195+ i915_handle_error(i915, ALL_ENGINES, 0, NULL);
4196+ wait_on_bit(&i915->gpu_error.flags,
4197+ I915_RESET_HANDOFF,
4198+ TASK_UNINTERRUPTIBLE);
41594199 }
41604200
41614201 fs_reclaim_acquire(GFP_KERNEL);
41624202 if (val & DROP_BOUND)
4163− i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4203+ i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
41644204
41654205 if (val & DROP_UNBOUND)
4166− i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4206+ i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
41674207
41684208 if (val & DROP_SHRINK_ALL)
4169− i915_gem_shrink_all(dev_priv);
4209+ i915_gem_shrink_all(i915);
41704210 fs_reclaim_release(GFP_KERNEL);
41714211
41724212 if (val & DROP_IDLE) {
41734213 do {
4174− if (READ_ONCE(dev_priv->gt.active_requests))
4175− flush_delayed_work(&dev_priv->gt.retire_work);
4176− drain_delayed_work(&dev_priv->gt.idle_work);
4177− } while (READ_ONCE(dev_priv->gt.awake));
4214+ if (READ_ONCE(i915->gt.active_requests))
4215+ flush_delayed_work(&i915->gt.retire_work);
4216+ drain_delayed_work(&i915->gt.idle_work);
4217+ } while (READ_ONCE(i915->gt.awake));
41784218 }
41794219
41804220 if (val & DROP_FREED)
4181− i915_gem_drain_freed_objects(dev_priv);
4221+ i915_gem_drain_freed_objects(i915);
41824222
41834223 return ret;
41844224 }
drivers/gpu/drm/i915/i915_drv.c+104−90
@@ -373,7 +373,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, · 372 unmodified lines
373373 value = 2;
374374 break;
375375 case I915_PARAM_HAS_RESOURCE_STREAMER:
376− value = HAS_RESOURCE_STREAMER(dev_priv);
376+ value = 0;
377377 break;
378378 case I915_PARAM_HAS_POOLED_EU:
379379 value = HAS_POOLED_EU(dev_priv);
@@ -441,6 +441,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, · 61 unmodified lines
441441 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
442442 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
443443 break;
444+ case I915_PARAM_MMAP_GTT_COHERENT:
445+ value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
446+ break;
444447 default:
445448 DRM_DEBUG("Unknown parameter %d\n", param->param);
446449 return -EINVAL;
@@ -709,7 +712,7 @@ cleanup_irq: · 262 unmodified lines
709712 intel_teardown_gmbus(dev_priv);
710713 cleanup_csr:
711714 intel_csr_ucode_fini(dev_priv);
712− intel_power_domains_fini(dev_priv);
715+ intel_power_domains_fini_hw(dev_priv);
713716 vga_switcheroo_unregister_client(pdev);
714717 cleanup_vga_client:
715718 vga_client_register(pdev, NULL, NULL, NULL);
@@ -867,7 +870,6 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) · 151 unmodified lines
867870 /**
868871 * i915_driver_init_early - setup state not requiring device access
869872 * @dev_priv: device private
870− * @ent: the matching pci_device_id
871873 *
872874 * Initialize everything that is a "SW-only" state, that is state not
873875 * requiring accessing the device or exposing the driver via kernel internal
@@ -875,25 +877,13 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) · 1 unmodified line
875877 * system memory allocation, setting up device specific attributes and
876878 * function hooks not requiring accessing the device.
877879 */
878−static int i915_driver_init_early(struct drm_i915_private *dev_priv,
879− const struct pci_device_id *ent)
880+static int i915_driver_init_early(struct drm_i915_private *dev_priv)
880881 {
881− const struct intel_device_info *match_info =
882− (struct intel_device_info *)ent->driver_data;
883− struct intel_device_info *device_info;
884882 int ret = 0;
885883
886884 if (i915_inject_load_failure())
887885 return -ENODEV;
888886
889− /* Setup the write-once "constant" device info */
890− device_info = mkwrite_device_info(dev_priv);
891− memcpy(device_info, match_info, sizeof(*device_info));
892− device_info->device_id = dev_priv->drm.pdev->device;
893−
894− BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
895− sizeof(device_info->platform_mask) * BITS_PER_BYTE);
896− BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
897887 spin_lock_init(&dev_priv->irq_lock);
898888 spin_lock_init(&dev_priv->gpu_error.lock);
899889 mutex_init(&dev_priv->backlight_lock);
@@ -921,7 +911,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, · 21 unmodified lines
921911 intel_uc_init_early(dev_priv);
922912 intel_pm_setup(dev_priv);
923913 intel_init_dpio(dev_priv);
924− intel_power_domains_init(dev_priv);
914+ ret = intel_power_domains_init(dev_priv);
915+ if (ret < 0)
916+ goto err_uc;
925917 intel_irq_init(dev_priv);
926918 intel_hangcheck_init(dev_priv);
927919 intel_init_display_hooks(dev_priv);
@@ -933,6 +925,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, · 5 unmodified lines
933925
934926 return 0;
935927
928+err_uc:
929+ intel_uc_cleanup_early(dev_priv);
930+ i915_gem_cleanup_early(dev_priv);
936931 err_workqueues:
937932 i915_workqueues_cleanup(dev_priv);
938933 err_engines:
@@ -947,6 +942,7 @@ err_engines: · 8 unmodified lines
947942 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
948943 {
949944 intel_irq_fini(dev_priv);
945+ intel_power_domains_cleanup(dev_priv);
950946 intel_uc_cleanup_early(dev_priv);
951947 i915_gem_cleanup_early(dev_priv);
952948 i915_workqueues_cleanup(dev_priv);
@@ -1272,6 +1268,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) · 319 unmodified lines
12721268 */
12731269 if (INTEL_INFO(dev_priv)->num_pipes)
12741270 drm_kms_helper_poll_init(dev);
1271+
1272+ intel_power_domains_enable(dev_priv);
1273+ intel_runtime_pm_enable(dev_priv);
12751274 }
12761275
12771276 /**
@@ -1280,6 +1279,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) · 2 unmodified lines
12801279 */
12811280 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
12821281 {
1282+ intel_runtime_pm_disable(dev_priv);
1283+ intel_power_domains_disable(dev_priv);
1284+
12831285 intel_fbdev_unregister(dev_priv);
12841286 intel_audio_deinit(dev_priv);
12851287
@@ -1316,6 +1318,52 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) · 30 unmodified lines
13161318 DRM_INFO("DRM_I915_DEBUG enabled\n");
13171319 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
13181320 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1321+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1322+ DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1323+}
1324+
1325+static struct drm_i915_private *
1326+i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1327+{
1328+ const struct intel_device_info *match_info =
1329+ (struct intel_device_info *)ent->driver_data;
1330+ struct intel_device_info *device_info;
1331+ struct drm_i915_private *i915;
1332+
1333+ i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1334+ if (!i915)
1335+ return NULL;
1336+
1337+ if (drm_dev_init(&i915->drm, &driver, &pdev->dev)) {
1338+ kfree(i915);
1339+ return NULL;
1340+ }
1341+
1342+ i915->drm.pdev = pdev;
1343+ i915->drm.dev_private = i915;
1344+ pci_set_drvdata(pdev, &i915->drm);
1345+
1346+ /* Setup the write-once "constant" device info */
1347+ device_info = mkwrite_device_info(i915);
1348+ memcpy(device_info, match_info, sizeof(*device_info));
1349+ device_info->device_id = pdev->device;
1350+
1351+ BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1352+ sizeof(device_info->platform_mask) * BITS_PER_BYTE);
1353+ BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1354+
1355+ return i915;
1356+}
1357+
1358+static void i915_driver_destroy(struct drm_i915_private *i915)
1359+{
1360+ struct pci_dev *pdev = i915->drm.pdev;
1361+
1362+ drm_dev_fini(&i915->drm);
1363+ kfree(i915);
1364+
1365+ /* And make sure we never chase our dangling pointer from pci_dev */
1366+ pci_set_drvdata(pdev, NULL);
13191367 }
13201368
13211369 /**
@@ -1340,38 +1388,19 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) · 18 unmodified lines
13401388 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
13411389 driver.driver_features &= ~DRIVER_ATOMIC;
13421390
1343− ret = -ENOMEM;
1344− dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1345− if (dev_priv)
1346− ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1347− if (ret) {
1348− DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1349− goto out_free;
1350− }
1351−
1352− dev_priv->drm.pdev = pdev;
1353− dev_priv->drm.dev_private = dev_priv;
1391+ dev_priv = i915_driver_create(pdev, ent);
1392+ if (!dev_priv)
1393+ return -ENOMEM;
13541394
13551395 ret = pci_enable_device(pdev);
13561396 if (ret)
13571397 goto out_fini;
13581398
1359− pci_set_drvdata(pdev, &dev_priv->drm);
1360− /*
1361− * Disable the system suspend direct complete optimization, which can
1362− * leave the device suspended skipping the driver's suspend handlers
1363− * if the device was already runtime suspended. This is needed due to
1364− * the difference in our runtime and system suspend sequence and
1365− * becaue the HDA driver may require us to enable the audio power
1366− * domain during system suspend.
1367− */
1368− dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1369−
1370− ret = i915_driver_init_early(dev_priv, ent);
1399+ ret = i915_driver_init_early(dev_priv);
13711400 if (ret < 0)
13721401 goto out_pci_disable;
13731402
1374− intel_runtime_pm_get(dev_priv);
1403+ disable_rpm_wakeref_asserts(dev_priv);
13751404
13761405 ret = i915_driver_init_mmio(dev_priv);
13771406 if (ret < 0)
@@ -1399,11 +1428,9 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) · 21 unmodified lines
13991428
14001429 i915_driver_register(dev_priv);
14011430
1402− intel_runtime_pm_enable(dev_priv);
1403−
14041431 intel_init_ipc(dev_priv);
14051432
1406− intel_runtime_pm_put(dev_priv);
1433+ enable_rpm_wakeref_asserts(dev_priv);
14071434
14081435 i915_welcome_messages(dev_priv);
14091436
@@ -1414,16 +1441,13 @@ out_cleanup_hw: · 4 unmodified lines
14141441 out_cleanup_mmio:
14151442 i915_driver_cleanup_mmio(dev_priv);
14161443 out_runtime_pm_put:
1417− intel_runtime_pm_put(dev_priv);
1444+ enable_rpm_wakeref_asserts(dev_priv);
14181445 i915_driver_cleanup_early(dev_priv);
14191446 out_pci_disable:
14201447 pci_disable_device(pdev);
14211448 out_fini:
14221449 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1423− drm_dev_fini(&dev_priv->drm);
1424−out_free:
1425− kfree(dev_priv);
1426− pci_set_drvdata(pdev, NULL);
1450+ i915_driver_destroy(dev_priv);
14271451 return ret;
14281452 }
14291453
@@ -1432,13 +1456,13 @@ void i915_driver_unload(struct drm_device *dev) · 2 unmodified lines
14321456 struct drm_i915_private *dev_priv = to_i915(dev);
14331457 struct pci_dev *pdev = dev_priv->drm.pdev;
14341458
1459+ disable_rpm_wakeref_asserts(dev_priv);
1460+
14351461 i915_driver_unregister(dev_priv);
14361462
14371463 if (i915_gem_suspend(dev_priv))
14381464 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
14391465
1440− intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1441−
14421466 drm_atomic_helper_shutdown(dev);
14431467
14441468 intel_gvt_cleanup(dev_priv);
@@ -1459,12 +1483,14 @@ void i915_driver_unload(struct drm_device *dev) · 14 unmodified lines
14591483 i915_gem_fini(dev_priv);
14601484 intel_fbc_cleanup_cfb(dev_priv);
14611485
1462− intel_power_domains_fini(dev_priv);
1486+ intel_power_domains_fini_hw(dev_priv);
14631487
14641488 i915_driver_cleanup_hw(dev_priv);
14651489 i915_driver_cleanup_mmio(dev_priv);
14661490
1467− intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1491+ enable_rpm_wakeref_asserts(dev_priv);
1492+
1493+ WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
14681494 }
14691495
14701496 static void i915_driver_release(struct drm_device *dev)
@@ -1472,9 +1498,7 @@ static void i915_driver_release(struct drm_device *dev) · 1 unmodified line
14721498 struct drm_i915_private *dev_priv = to_i915(dev);
14731499
14741500 i915_driver_cleanup_early(dev_priv);
1475− drm_dev_fini(&dev_priv->drm);
1476−
1477− kfree(dev_priv);
1501+ i915_driver_destroy(dev_priv);
14781502 }
14791503
14801504 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
@@ -1573,7 +1597,7 @@ static int i915_drm_suspend(struct drm_device *dev) · 92 unmodified lines
15731597
15741598 /* We do a lot of poking in a lot of registers, make sure they work
15751599 * properly. */
1576− intel_display_set_init_power(dev_priv, true);
1600+ intel_power_domains_disable(dev_priv);
15771601
15781602 drm_kms_helper_poll_disable(dev);
15791603
@@ -1610,6 +1634,18 @@ static int i915_drm_suspend(struct drm_device *dev) · 30 unmodified lines
16101634 return 0;
16111635 }
16121636
1637+static enum i915_drm_suspend_mode
1638+get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1639+{
1640+ if (hibernate)
1641+ return I915_DRM_SUSPEND_HIBERNATE;
1642+
1643+ if (suspend_to_idle(dev_priv))
1644+ return I915_DRM_SUSPEND_IDLE;
1645+
1646+ return I915_DRM_SUSPEND_MEM;
1647+}
1648+
16131649 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
16141650 {
16151651 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1620,21 +1656,10 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) · 4 unmodified lines
16201656
16211657 i915_gem_suspend_late(dev_priv);
16221658
1623− intel_display_set_init_power(dev_priv, false);
16241659 intel_uncore_suspend(dev_priv);
16251660
1626− /*
1627− * In case of firmware assisted context save/restore don't manually
1628− * deinit the power domains. This also means the CSR/DMC firmware will
1629− * stay active, it will power down any HW resources as required and
1630− * also enable deeper system power states that would be blocked if the
1631− * firmware was inactive.
1632− */
1633− if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1634− dev_priv->csr.dmc_payload == NULL) {
1635− intel_power_domains_suspend(dev_priv);
1636− dev_priv->power_domains_suspended = true;
1637− }
1661+ intel_power_domains_suspend(dev_priv,
1662+ get_suspend_mode(dev_priv, hibernation));
16381663
16391664 ret = 0;
16401665 if (IS_GEN9_LP(dev_priv))
@@ -1646,10 +1671,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) · 5 unmodified lines
16461671
16471672 if (ret) {
16481673 DRM_ERROR("Suspend complete failed: %d\n", ret);
1649− if (dev_priv->power_domains_suspended) {
1650− intel_power_domains_init_hw(dev_priv, true);
1651− dev_priv->power_domains_suspended = false;
1652− }
1674+ intel_power_domains_resume(dev_priv);
16531675
16541676 goto out;
16551677 }
@@ -1755,7 +1777,7 @@ static int i915_drm_resume(struct drm_device *dev) · 99 unmodified lines
17551777 /*
17561778 * ... but also need to make sure that hotplug processing
17571779 * doesn't cause havoc. Like in the driver load code we don't
1758− * bother with the tiny race here where we might loose hotplug
1780+ * bother with the tiny race here where we might lose hotplug
17591781 * notifications.
17601782 * */
17611783 intel_hpd_init(dev_priv);
@@ -1766,6 +1788,8 @@ static int i915_drm_resume(struct drm_device *dev) · 4 unmodified lines
17661788
17671789 intel_opregion_notify_adapter(dev_priv, PCI_D0);
17681790
1791+ intel_power_domains_enable(dev_priv);
1792+
17691793 enable_rpm_wakeref_asserts(dev_priv);
17701794
17711795 return 0;
@@ -1800,7 +1824,7 @@ static int i915_drm_resume_early(struct drm_device *dev) · 28 unmodified lines
18001824 ret = pci_set_power_state(pdev, PCI_D0);
18011825 if (ret) {
18021826 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1803− goto out;
1827+ return ret;
18041828 }
18051829
18061830 /*
@@ -1816,10 +1840,8 @@ static int i915_drm_resume_early(struct drm_device *dev) · 9 unmodified lines
18161840 * depend on the device enable refcount we can't anyway depend on them
18171841 * disabling/enabling the device.
18181842 */
1819− if (pci_enable_device(pdev)) {
1820− ret = -EIO;
1821− goto out;
1822− }
1843+ if (pci_enable_device(pdev))
1844+ return -EIO;
18231845
18241846 pci_set_master(pdev);
18251847
@@ -1842,18 +1864,12 @@ static int i915_drm_resume_early(struct drm_device *dev) · 16 unmodified lines
18421864
18431865 intel_uncore_sanitize(dev_priv);
18441866
1845− if (dev_priv->power_domains_suspended)
1846− intel_power_domains_init_hw(dev_priv, true);
1847− else
1848− intel_display_set_init_power(dev_priv, true);
1867+ intel_power_domains_resume(dev_priv);
18491868
18501869 intel_engines_sanitize(dev_priv);
18511870
18521871 enable_rpm_wakeref_asserts(dev_priv);
18531872
1854−out:
1855− dev_priv->power_domains_suspended = false;
1856−
18571873 return ret;
18581874 }
18591875
@@ -1915,7 +1931,6 @@ void i915_reset(struct drm_i915_private *i915, · 55 unmodified lines
19151931 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
19161932 error->reset_count++;
19171933
1918− disable_irq(i915->drm.irq);
19191934 ret = i915_gem_reset_prepare(i915);
19201935 if (ret) {
19211936 dev_err(i915->drm.dev, "GPU recovery failed\n");
@@ -1977,8 +1992,6 @@ void i915_reset(struct drm_i915_private *i915, · 55 unmodified lines
19771992
19781993 finish:
19791994 i915_gem_reset_finish(i915);
1980− enable_irq(i915->drm.irq);
1981−
19821995 wakeup:
19831996 clear_bit(I915_RESET_HANDOFF, &error->flags);
19841997 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
@@ -2073,6 +2086,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg) · 88 unmodified lines
20732086 goto out;
20742087
20752088 out:
2089+ intel_engine_cancel_stop_cs(engine);
20762090 i915_gem_reset_finish_engine(engine);
20772091 return ret;
20782092 }
drivers/gpu/drm/i915/i915_drv.h+49−14
@@ -86,8 +86,8 @@ · 85 unmodified lines
8686
8787 #define DRIVER_NAME "i915"
8888 #define DRIVER_DESC "Intel Graphics"
89−#define DRIVER_DATE "20180719"
90−#define DRIVER_TIMESTAMP 1532015279
89+#define DRIVER_DATE "20180906"
90+#define DRIVER_TIMESTAMP 1536242083
9191
9292 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
9393 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -611,8 +611,18 @@ struct i915_drrs { · 517 unmodified lines
611611
612612 struct i915_psr {
613613 struct mutex lock;
614+
615+#define I915_PSR_DEBUG_MODE_MASK 0x0f
616+#define I915_PSR_DEBUG_DEFAULT 0x00
617+#define I915_PSR_DEBUG_DISABLE 0x01
618+#define I915_PSR_DEBUG_ENABLE 0x02
619+#define I915_PSR_DEBUG_FORCE_PSR1 0x03
620+#define I915_PSR_DEBUG_IRQ 0x10
621+
622+ u32 debug;
614623 bool sink_support;
615− struct intel_dp *enabled;
624+ bool prepared, enabled;
625+ struct intel_dp *dp;
616626 bool active;
617627 struct work_struct work;
618628 unsigned busy_frontbuffer_bits;
@@ -622,7 +632,6 @@ struct i915_psr { · 3 unmodified lines
622632 bool alpm;
623633 bool psr2_enabled;
624634 u8 sink_sync_latency;
625− bool debug;
626635 ktime_t last_entry_attempt;
627636 ktime_t last_exit;
628637 };
@@ -867,14 +876,17 @@ struct i915_power_well_ops { · 238 unmodified lines
867876 struct i915_power_well *power_well);
868877 };
869878
879+struct i915_power_well_regs {
880+ i915_reg_t bios;
881+ i915_reg_t driver;
882+ i915_reg_t kvmr;
883+ i915_reg_t debug;
884+};
885+
870886 /* Power well structure for haswell */
871−struct i915_power_well {
887+struct i915_power_well_desc {
872888 const char *name;
873889 bool always_on;
874− /* power well enable/disable usage count */
875− int count;
876− /* cached hw enabled state */
877− bool hw_enabled;
878890 u64 domains;
879891 /* unique identifier for this power well */
880892 enum i915_power_well_id id;
@@ -883,10 +895,23 @@ struct i915_power_well { · 2 unmodified lines
883895 * well specific.
884896 */
885897 union {
898+ struct {
899+ /*
900+ * request/status flag index in the PUNIT power well
901+ * control/status registers.
902+ */
903+ u8 idx;
904+ } vlv;
886905 struct {
887906 enum dpio_phy phy;
888907 } bxt;
889908 struct {
909+ const struct i915_power_well_regs *regs;
910+ /*
911+ * request/status flag index in the power well
912+ * constrol/status registers.
913+ */
914+ u8 idx;
890915 /* Mask of pipes whose IRQ logic is backed by the pw */
891916 u8 irq_pipe_mask;
892917 /* The pw is backing the VGA functionality */
@@ -897,13 +922,21 @@ struct i915_power_well { · 4 unmodified lines
897922 const struct i915_power_well_ops *ops;
898923 };
899924
925+struct i915_power_well {
926+ const struct i915_power_well_desc *desc;
927+ /* power well enable/disable usage count */
928+ int count;
929+ /* cached hw enabled state */
930+ bool hw_enabled;
931+};
932+
900933 struct i915_power_domains {
901934 /*
902935 * Power wells needed for initialization at driver init and suspend
903936 * time are on. They are kept on until after the first modeset.
904937 */
905− bool init_power_on;
906938 bool initializing;
939+ bool display_core_suspended;
907940 int power_well_count;
908941
909942 struct mutex lock;
@@ -1610,7 +1643,8 @@ struct drm_i915_private { · 700 unmodified lines
16101643 struct mutex gmbus_mutex;
16111644
16121645 /**
1613− * Base address of the gmbus and gpio block.
1646+ * Base address of where the gmbus and gpio blocks are located (either
1647+ * on PCH or on SoC for platforms without PCH).
16141648 */
16151649 uint32_t gpio_mmio_base;
16161650
@@ -1632,7 +1666,6 @@ struct drm_i915_private { · 15 unmodified lines
16321666 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
16331667 [MAX_ENGINE_INSTANCE + 1];
16341668
1635− struct drm_dma_handle *status_page_dmah;
16361669 struct resource mch_res;
16371670
16381671 /* protects the irq masks */
@@ -1828,6 +1861,7 @@ struct drm_i915_private { · 189 unmodified lines
18281861 struct mutex av_mutex;
18291862
18301863 struct {
1864+ struct mutex mutex;
18311865 struct list_head list;
18321866 struct llist_head free_list;
18331867 struct work_struct free_work;
@@ -1840,6 +1874,7 @@ struct drm_i915_private { · 6 unmodified lines
18401874 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
18411875 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
18421876 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1877+ struct list_head hw_id_list;
18431878 } contexts;
18441879
18451880 u32 fdi_rx_config;
@@ -2610,8 +2645,6 @@ intel_info(const struct drm_i915_private *dev_priv) · 764 unmodified lines
26102645 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
26112646 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
26122647
2613−#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2614−
26152648 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
26162649
26172650 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -2775,6 +2808,8 @@ extern void intel_irq_fini(struct drm_i915_private *dev_priv); · 157 unmodified lines
27752808 int intel_irq_install(struct drm_i915_private *dev_priv);
27762809 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
27772810
2811+void i915_clear_error_registers(struct drm_i915_private *dev_priv);
2812+
27782813 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
27792814 {
27802815 return dev_priv->gvt;
drivers/gpu/drm/i915/i915_gem.c+52−13
@@ -802,6 +802,11 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv) · 801 unmodified lines
802802 * that was!).
803803 */
804804
805+ wmb();
806+
807+ if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
808+ return;
809+
805810 i915_gem_chipset_flush(dev_priv);
806811
807812 intel_runtime_pm_get(dev_priv);
@@ -1906,7 +1911,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, · 1098 unmodified lines
19061911 return 0;
19071912 }
19081913
1909−static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1914+static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj)
19101915 {
19111916 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
19121917 }
@@ -1965,7 +1970,7 @@ int i915_gem_mmap_gtt_version(void) · 52 unmodified lines
19651970 }
19661971
19671972 static inline struct i915_ggtt_view
1968−compute_partial_view(struct drm_i915_gem_object *obj,
1973+compute_partial_view(const struct drm_i915_gem_object *obj,
19691974 pgoff_t page_offset,
19701975 unsigned int chunk)
19711976 {
@@ -2013,7 +2018,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf) · 41 unmodified lines
20132018 struct drm_device *dev = obj->base.dev;
20142019 struct drm_i915_private *dev_priv = to_i915(dev);
20152020 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2016− bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
2021+ bool write = area->vm_flags & VM_WRITE;
20172022 struct i915_vma *vma;
20182023 pgoff_t page_offset;
20192024 int ret;
@@ -2528,13 +2533,21 @@ static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) · 508 unmodified lines
25282533 gfp_t noreclaim;
25292534 int ret;
25302535
2531− /* Assert that the object is not currently in any GPU domain. As it
2536+ /*
2537+ * Assert that the object is not currently in any GPU domain. As it
25322538 * wasn't in the GTT, there shouldn't be any way it could have been in
25332539 * a GPU cache
25342540 */
25352541 GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
25362542 GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
25372543
2544+ /*
2545+ * If there's no chance of allocating enough pages for the whole
2546+ * object, bail early.
2547+ */
2548+ if (page_count > totalram_pages)
2549+ return -ENOMEM;
2550+
25382551 st = kmalloc(sizeof(*st), GFP_KERNEL);
25392552 if (st == NULL)
25402553 return -ENOMEM;
@@ -2545,7 +2558,8 @@ rebuild_st: · 4 unmodified lines
25452558 return -ENOMEM;
25462559 }
25472560
2548− /* Get the list of pages out of our struct file. They'll be pinned
2561+ /*
2562+ * Get the list of pages out of our struct file. They'll be pinned
25492563 * at this point until we release them.
25502564 *
25512565 * Fail silently without starting the shrinker
@@ -2577,7 +2591,8 @@ rebuild_st: · 25 unmodified lines
25772591 i915_gem_shrink(dev_priv, 2 * page_count, NULL, *s++);
25782592 cond_resched();
25792593
2580− /* We've tried hard to allocate the memory by reaping
2594+ /*
2595+ * We've tried hard to allocate the memory by reaping
25812596 * our own buffer, now let the real VM do its job and
25822597 * go down in flames if truly OOM.
25832598 *
@@ -2589,7 +2604,8 @@ rebuild_st: · 5 unmodified lines
25892604 /* reclaim and warn, but no oom */
25902605 gfp = mapping_gfp_mask(mapping);
25912606
2592− /* Our bo are always dirty and so we require
2607+ /*
2608+ * Our bo are always dirty and so we require
25932609 * kswapd to reclaim our pages (direct reclaim
25942610 * does not effectively begin pageout of our
25952611 * buffers on its own). However, direct reclaim
@@ -2633,7 +2649,8 @@ rebuild_st: · 37 unmodified lines
26332649
26342650 ret = i915_gem_gtt_prepare_pages(obj, st);
26352651 if (ret) {
2636− /* DMA remapping failed? One possible cause is that
2652+ /*
2653+ * DMA remapping failed? One possible cause is that
26372654 * it could not reserve enough large entries, asking
26382655 * for PAGE_SIZE chunks instead may be helpful.
26392656 */
@@ -2667,7 +2684,8 @@ err_pages: · 27 unmodified lines
26672684 sg_free_table(st);
26682685 kfree(st);
26692686
2670− /* shmemfs first checks if there is enough memory to allocate the page
2687+ /*
2688+ * shmemfs first checks if there is enough memory to allocate the page
26712689 * and reports ENOSPC should there be insufficient, along with the usual
26722690 * ENOMEM for a genuine allocation failure.
26732691 *
@@ -3307,8 +3325,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 633 unmodified lines
33073325 intel_engine_dump(engine, &p, "%s\n", engine->name);
33083326 }
33093327
3310− set_bit(I915_WEDGED, &i915->gpu_error.flags);
3311− smp_mb__after_atomic();
3328+ if (test_and_set_bit(I915_WEDGED, &i915->gpu_error.flags))
3329+ goto out;
33123330
33133331 /*
33143332 * First, stop submission to hw, but do not yet complete requests by
@@ -3324,7 +3342,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 9 unmodified lines
33243342 i915->caps.scheduler = 0;
33253343
33263344 /* Even if the GPU reset fails, it should still stop the engines */
3327− intel_gpu_reset(i915, ALL_ENGINES);
3345+ if (INTEL_GEN(i915) >= 5)
3346+ intel_gpu_reset(i915, ALL_ENGINES);
33283347
33293348 /*
33303349 * Make sure no one is running the old callback before we proceed with
@@ -3367,6 +3386,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 36 unmodified lines
33673386 i915_gem_reset_finish_engine(engine);
33683387 }
33693388
3389+out:
33703390 GEM_TRACE("end\n");
33713391
33723392 wake_up_all(&i915->gpu_error.reset_queue);
@@ -3816,6 +3836,12 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915, · 443 unmodified lines
38163836 if (timeout < 0)
38173837 return timeout;
38183838 }
3839+ if (GEM_SHOW_DEBUG() && !timeout) {
3840+ /* Presume that timeout was non-zero to begin with! */
3841+ dev_warn(&i915->drm.pdev->dev,
3842+ "Missed idle-completion interrupt!\n");
3843+ GEM_TRACE_DUMP();
3844+ }
38193845
38203846 err = wait_for_engines(i915);
38213847 if (err)
@@ -5592,6 +5618,8 @@ err_uc_misc: · 1770 unmodified lines
55925618 i915_gem_cleanup_userptr(dev_priv);
55935619
55945620 if (ret == -EIO) {
5621+ mutex_lock(&dev_priv->drm.struct_mutex);
5622+
55955623 /*
55965624 * Allow engine initialisation to fail by marking the GPU as
55975625 * wedged. But we only want to do this where the GPU is angry,
@@ -5602,7 +5630,14 @@ err_uc_misc: · 4 unmodified lines
56025630 "Failed to initialize GPU, declaring it wedged!\n");
56035631 i915_gem_set_wedged(dev_priv);
56045632 }
5605− ret = 0;
5633+
5634+ /* Minimal basic recovery for KMS */
5635+ ret = i915_ggtt_enable_hw(dev_priv);
5636+ i915_gem_restore_gtt_mappings(dev_priv);
5637+ i915_gem_restore_fences(dev_priv);
5638+ intel_init_clock_gating(dev_priv);
5639+
5640+ mutex_unlock(&dev_priv->drm.struct_mutex);
56065641 }
56075642
56085643 i915_gem_drain_freed_objects(dev_priv);
@@ -5612,6 +5647,7 @@ err_uc_misc: · 3 unmodified lines
56125647 void i915_gem_fini(struct drm_i915_private *dev_priv)
56135648 {
56145649 i915_gem_suspend_late(dev_priv);
5650+ intel_disable_gt_powersave(dev_priv);
56155651
56165652 /* Flush any outstanding unpin_work. */
56175653 i915_gem_drain_workqueue(dev_priv);
@@ -5623,6 +5659,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv) · 5 unmodified lines
56235659 i915_gem_contexts_fini(dev_priv);
56245660 mutex_unlock(&dev_priv->drm.struct_mutex);
56255661
5662+ intel_cleanup_gt_powersave(dev_priv);
5663+
56265664 intel_uc_fini_misc(dev_priv);
56275665 i915_gem_cleanup_userptr(dev_priv);
56285666
@@ -6182,4 +6220,5 @@ err_unlock: · 553 unmodified lines
61826220 #include "selftests/huge_pages.c"
61836221 #include "selftests/i915_gem_object.c"
61846222 #include "selftests/i915_gem_coherency.c"
6223+#include "selftests/i915_gem.c"
61856224 #endif
drivers/gpu/drm/i915/i915_gem.h+0−6
@@ -82,12 +82,6 @@ static inline void __tasklet_disable_sync_once(struct tasklet_struct *t) · 81 unmodified lines
8282 tasklet_unlock_wait(t);
8383 }
8484
85−static inline void __tasklet_enable_sync_once(struct tasklet_struct *t)
86−{
87− if (atomic_dec_return(&t->count) == 0)
88− tasklet_kill(t);
89−}
90−
9185 static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
9286 {
9387 return !atomic_read(&t->count);
drivers/gpu/drm/i915/i915_gem_context.c+161−71
@@ -115,6 +115,95 @@ static void lut_close(struct i915_gem_context *ctx) · 114 unmodified lines
115115 rcu_read_unlock();
116116 }
117117
118+static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
119+{
120+ unsigned int max;
121+
122+ lockdep_assert_held(&i915->contexts.mutex);
123+
124+ if (INTEL_GEN(i915) >= 11)
125+ max = GEN11_MAX_CONTEXT_HW_ID;
126+ else if (USES_GUC_SUBMISSION(i915))
127+ /*
128+ * When using GuC in proxy submission, GuC consumes the
129+ * highest bit in the context id to indicate proxy submission.
130+ */
131+ max = MAX_GUC_CONTEXT_HW_ID;
132+ else
133+ max = MAX_CONTEXT_HW_ID;
134+
135+ return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
136+}
137+
138+static int steal_hw_id(struct drm_i915_private *i915)
139+{
140+ struct i915_gem_context *ctx, *cn;
141+ LIST_HEAD(pinned);
142+ int id = -ENOSPC;
143+
144+ lockdep_assert_held(&i915->contexts.mutex);
145+
146+ list_for_each_entry_safe(ctx, cn,
147+ &i915->contexts.hw_id_list, hw_id_link) {
148+ if (atomic_read(&ctx->hw_id_pin_count)) {
149+ list_move_tail(&ctx->hw_id_link, &pinned);
150+ continue;
151+ }
152+
153+ GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
154+ list_del_init(&ctx->hw_id_link);
155+ id = ctx->hw_id;
156+ break;
157+ }
158+
159+ /*
160+ * Remember how far we got up on the last repossesion scan, so the
161+ * list is kept in a "least recently scanned" order.
162+ */
163+ list_splice_tail(&pinned, &i915->contexts.hw_id_list);
164+ return id;
165+}
166+
167+static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
168+{
169+ int ret;
170+
171+ lockdep_assert_held(&i915->contexts.mutex);
172+
173+ /*
174+ * We prefer to steal/stall ourselves and our users over that of the
175+ * entire system. That may be a little unfair to our users, and
176+ * even hurt high priority clients. The choice is whether to oomkill
177+ * something else, or steal a context id.
178+ */
179+ ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
180+ if (unlikely(ret < 0)) {
181+ ret = steal_hw_id(i915);
182+ if (ret < 0) /* once again for the correct errno code */
183+ ret = new_hw_id(i915, GFP_KERNEL);
184+ if (ret < 0)
185+ return ret;
186+ }
187+
188+ *out = ret;
189+ return 0;
190+}
191+
192+static void release_hw_id(struct i915_gem_context *ctx)
193+{
194+ struct drm_i915_private *i915 = ctx->i915;
195+
196+ if (list_empty(&ctx->hw_id_link))
197+ return;
198+
199+ mutex_lock(&i915->contexts.mutex);
200+ if (!list_empty(&ctx->hw_id_link)) {
201+ ida_simple_remove(&i915->contexts.hw_ida, ctx->hw_id);
202+ list_del_init(&ctx->hw_id_link);
203+ }
204+ mutex_unlock(&i915->contexts.mutex);
205+}
206+
118207 static void i915_gem_context_free(struct i915_gem_context *ctx)
119208 {
120209 unsigned int n;
@@ -122,6 +211,7 @@ static void i915_gem_context_free(struct i915_gem_context *ctx) · 1 unmodified line
122211 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
123212 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
124213
214+ release_hw_id(ctx);
125215 i915_ppgtt_put(ctx->ppgtt);
126216
127217 for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
@@ -136,7 +226,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx) · 8 unmodified lines
136226
137227 list_del(&ctx->link);
138228
139− ida_simple_remove(&ctx->i915->contexts.hw_ida, ctx->hw_id);
140229 kfree_rcu(ctx, rcu);
141230 }
142231
@@ -190,6 +279,12 @@ static void context_close(struct i915_gem_context *ctx) · 47 unmodified lines
190279 {
191280 i915_gem_context_set_closed(ctx);
192281
282+ /*
283+ * This context will never again be assinged to HW, so we can
284+ * reuse its ID for the next context.
285+ */
286+ release_hw_id(ctx);
287+
193288 /*
194289 * The LUT uses the VMA as a backpointer to unref the object,
195290 * so we need to clear the LUT before we close all the VMA (inside
@@ -203,43 +298,6 @@ static void context_close(struct i915_gem_context *ctx) · 7 unmodified lines
203298 i915_gem_context_put(ctx);
204299 }
205300
206−static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
207−{
208− int ret;
209− unsigned int max;
210−
211− if (INTEL_GEN(dev_priv) >= 11) {
212− max = GEN11_MAX_CONTEXT_HW_ID;
213− } else {
214− /*
215− * When using GuC in proxy submission, GuC consumes the
216− * highest bit in the context id to indicate proxy submission.
217− */
218− if (USES_GUC_SUBMISSION(dev_priv))
219− max = MAX_GUC_CONTEXT_HW_ID;
220− else
221− max = MAX_CONTEXT_HW_ID;
222− }
223−
224−
225− ret = ida_simple_get(&dev_priv->contexts.hw_ida,
226− 0, max, GFP_KERNEL);
227− if (ret < 0) {
228− /* Contexts are only released when no longer active.
229− * Flush any pending retires to hopefully release some
230− * stale contexts and try again.
231− */
232− i915_retire_requests(dev_priv);
233− ret = ida_simple_get(&dev_priv->contexts.hw_ida,
234− 0, max, GFP_KERNEL);
235− if (ret < 0)
236− return ret;
237− }
238−
239− *out = ret;
240− return 0;
241−}
242−
243301 static u32 default_desc_template(const struct drm_i915_private *i915,
244302 const struct i915_hw_ppgtt *ppgtt)
245303 {
@@ -276,12 +334,6 @@ __create_hw_context(struct drm_i915_private *dev_priv, · 30 unmodified lines
276334 if (ctx == NULL)
277335 return ERR_PTR(-ENOMEM);
278336
279− ret = assign_hw_id(dev_priv, &ctx->hw_id);
280− if (ret) {
281− kfree(ctx);
282− return ERR_PTR(ret);
283− }
284−
285337 kref_init(&ctx->ref);
286338 list_add_tail(&ctx->link, &dev_priv->contexts.list);
287339 ctx->i915 = dev_priv;
@@ -295,6 +347,7 @@ __create_hw_context(struct drm_i915_private *dev_priv, · 7 unmodified lines
295347
296348 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
297349 INIT_LIST_HEAD(&ctx->handles_list);
350+ INIT_LIST_HEAD(&ctx->hw_id_link);
298351
299352 /* Default context will never have a file_priv */
300353 ret = DEFAULT_CONTEXT_HANDLE;
@@ -329,16 +382,6 @@ __create_hw_context(struct drm_i915_private *dev_priv, · 28 unmodified lines
329382 ctx->desc_template =
330383 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
331384
332− /*
333− * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
334− * present or not in use we still need a small bias as ring wraparound
335− * at offset 0 sometimes hangs. No idea why.
336− */
337− if (USES_GUC(dev_priv))
338− ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
339− else
340− ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
341−
342385 return ctx;
343386
344387 err_pid:
@@ -431,15 +474,35 @@ out: · 86 unmodified lines
431474 return ctx;
432475 }
433476
477+static void
478+destroy_kernel_context(struct i915_gem_context **ctxp)
479+{
480+ struct i915_gem_context *ctx;
481+
482+ /* Keep the context ref so that we can free it immediately ourselves */
483+ ctx = i915_gem_context_get(fetch_and_zero(ctxp));
484+ GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
485+
486+ context_close(ctx);
487+ i915_gem_context_free(ctx);
488+}
489+
434490 struct i915_gem_context *
435491 i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
436492 {
437493 struct i915_gem_context *ctx;
494+ int err;
438495
439496 ctx = i915_gem_create_context(i915, NULL);
440497 if (IS_ERR(ctx))
441498 return ctx;
442499
500+ err = i915_gem_context_pin_hw_id(ctx);
501+ if (err) {
502+ destroy_kernel_context(&ctx);
503+ return ERR_PTR(err);
504+ }
505+
443506 i915_gem_context_clear_bannable(ctx);
444507 ctx->sched.priority = prio;
445508 ctx->ring_size = PAGE_SIZE;
@@ -449,17 +512,19 @@ i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio) · 3 unmodified lines
449512 return ctx;
450513 }
451514
452−static void
453−destroy_kernel_context(struct i915_gem_context **ctxp)
515+static void init_contexts(struct drm_i915_private *i915)
454516 {
455− struct i915_gem_context *ctx;
517+ mutex_init(&i915->contexts.mutex);
518+ INIT_LIST_HEAD(&i915->contexts.list);
456519
457− /* Keep the context ref so that we can free it immediately ourselves */
458− ctx = i915_gem_context_get(fetch_and_zero(ctxp));
459− GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
520+ /* Using the simple ida interface, the max is limited by sizeof(int) */
521+ BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
522+ BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
523+ ida_init(&i915->contexts.hw_ida);
524+ INIT_LIST_HEAD(&i915->contexts.hw_id_list);
460525
461− context_close(ctx);
462− i915_gem_context_free(ctx);
526+ INIT_WORK(&i915->contexts.free_work, contexts_free_worker);
527+ init_llist_head(&i915->contexts.free_list);
463528 }
464529
465530 static bool needs_preempt_context(struct drm_i915_private *i915)
@@ -480,14 +545,7 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv) · 14 unmodified lines
480545 if (ret)
481546 return ret;
482547
483− INIT_LIST_HEAD(&dev_priv->contexts.list);
484− INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
485− init_llist_head(&dev_priv->contexts.free_list);
486−
487− /* Using the simple ida interface, the max is limited by sizeof(int) */
488− BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
489− BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
490− ida_init(&dev_priv->contexts.hw_ida);
548+ init_contexts(dev_priv);
491549
492550 /* lowest priority; idle task */
493551 ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN);
@@ -497,9 +555,13 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv) · 3 unmodified lines
497555 }
498556 /*
499557 * For easy recognisablity, we want the kernel context to be 0 and then
500− * all user contexts will have non-zero hw_id.
558+ * all user contexts will have non-zero hw_id. Kernel contexts are
559+ * permanently pinned, so that we never suffer a stall and can
560+ * use them from any allocation context (e.g. for evicting other
561+ * contexts and from inside the shrinker).
501562 */
502563 GEM_BUG_ON(ctx->hw_id);
564+ GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
503565 dev_priv->kernel_context = ctx;
504566
505567 /* highest priority; preempting task */
@@ -537,6 +599,7 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915) · 31 unmodified lines
537599 destroy_kernel_context(&i915->kernel_context);
538600
539601 /* Must free all deferred contexts (via flush_workqueue) first */
602+ GEM_BUG_ON(!list_empty(&i915->contexts.hw_id_list));
540603 ida_destroy(&i915->contexts.hw_ida);
541604 }
542605
@@ -942,6 +1005,33 @@ out: · 399 unmodified lines
9421005 return ret;
9431006 }
9441007
1008+int __i915_gem_context_pin_hw_id(struct i915_gem_context *ctx)
1009+{
1010+ struct drm_i915_private *i915 = ctx->i915;
1011+ int err = 0;
1012+
1013+ mutex_lock(&i915->contexts.mutex);
1014+
1015+ GEM_BUG_ON(i915_gem_context_is_closed(ctx));
1016+
1017+ if (list_empty(&ctx->hw_id_link)) {
1018+ GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count));
1019+
1020+ err = assign_hw_id(i915, &ctx->hw_id);
1021+ if (err)
1022+ goto out_unlock;
1023+
1024+ list_add_tail(&ctx->hw_id_link, &i915->contexts.hw_id_list);
1025+ }
1026+
1027+ GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count) == ~0u);
1028+ atomic_inc(&ctx->hw_id_pin_count);
1029+
1030+out_unlock:
1031+ mutex_unlock(&i915->contexts.mutex);
1032+ return err;
1033+}
1034+
9451035 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
9461036 #include "selftests/mock_context.c"
9471037 #include "selftests/i915_gem_context.c"
drivers/gpu/drm/i915/i915_gem_context.h+23−3
@@ -134,8 +134,16 @@ struct i915_gem_context { · 133 unmodified lines
134134 * functions like fault reporting, PASID, scheduling. The
135135 * &drm_i915_private.context_hw_ida is used to assign a unqiue
136136 * id for the lifetime of the context.
137+ *
138+ * @hw_id_pin_count: - number of times this context had been pinned
139+ * for use (should be, at most, once per engine).
140+ *
141+ * @hw_id_link: - all contexts with an assigned id are tracked
142+ * for possible repossession.
137143 */
138144 unsigned int hw_id;
145+ atomic_t hw_id_pin_count;
146+ struct list_head hw_id_link;
139147
140148 /**
141149 * @user_handle: userspace identifier
@@ -147,9 +155,6 @@ struct i915_gem_context { · 5 unmodified lines
147155
148156 struct i915_sched_attr sched;
149157
150− /** ggtt_offset_bias: placement restriction for context objects */
151− u32 ggtt_offset_bias;
152−
153158 /** engine: per-engine logical HW state */
154159 struct intel_context {
155160 struct i915_gem_context *gem_context;
@@ -257,6 +262,21 @@ static inline void i915_gem_context_set_force_single_submission(struct i915_gem_ · 101 unmodified lines
257262 __set_bit(CONTEXT_FORCE_SINGLE_SUBMISSION, &ctx->flags);
258263 }
259264
265+int __i915_gem_context_pin_hw_id(struct i915_gem_context *ctx);
266+static inline int i915_gem_context_pin_hw_id(struct i915_gem_context *ctx)
267+{
268+ if (atomic_inc_not_zero(&ctx->hw_id_pin_count))
269+ return 0;
270+
271+ return __i915_gem_context_pin_hw_id(ctx);
272+}
273+
274+static inline void i915_gem_context_unpin_hw_id(struct i915_gem_context *ctx)
275+{
276+ GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count) == 0u);
277+ atomic_dec(&ctx->hw_id_pin_count);
278+}
279+
260280 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
261281 {
262282 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
drivers/gpu/drm/i915/i915_gem_execbuffer.c+21−22
@@ -64,7 +64,9 @@ enum { · 63 unmodified lines
6464 #define BATCH_OFFSET_BIAS (256*1024)
6565
6666 #define __I915_EXEC_ILLEGAL_FLAGS \
67− (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
67+ (__I915_EXEC_UNKNOWN_FLAGS | \
68+ I915_EXEC_CONSTANTS_MASK | \
69+ I915_EXEC_RESOURCE_STREAMER)
6870
6971 /* Catch emission of unexpected errors for CI! */
7072 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
@@ -733,7 +735,12 @@ static int eb_select_context(struct i915_execbuffer *eb) · 662 unmodified lines
733735 return -ENOENT;
734736
735737 eb->ctx = ctx;
736− eb->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &eb->i915->ggtt.vm;
738+ if (ctx->ppgtt) {
739+ eb->vm = &ctx->ppgtt->vm;
740+ eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
741+ } else {
742+ eb->vm = &eb->i915->ggtt.vm;
743+ }
737744
738745 eb->context_flags = 0;
739746 if (ctx->flags & CONTEXT_NO_ZEROMAP)
@@ -1120,6 +1127,13 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, · 380 unmodified lines
11201127 u32 *cmd;
11211128 int err;
11221129
1130+ if (DBG_FORCE_RELOC == FORCE_GPU_RELOC) {
1131+ obj = vma->obj;
1132+ if (obj->cache_dirty & ~obj->cache_coherent)
1133+ i915_gem_clflush_object(obj, 0);
1134+ obj->write_domain = 0;
1135+ }
1136+
11231137 GEM_BUG_ON(vma->obj->write_domain & I915_GEM_DOMAIN_CPU);
11241138
11251139 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
@@ -1484,8 +1498,10 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) · 358 unmodified lines
14841498 * can read from this userspace address.
14851499 */
14861500 offset = gen8_canonical_addr(offset & ~UPDATE);
1487− __put_user(offset,
1488− &urelocs[r-stack].presumed_offset);
1501+ if (unlikely(__put_user(offset, &urelocs[r-stack].presumed_offset))) {
1502+ remain = -EFAULT;
1503+ goto out;
1504+ }
14891505 }
14901506 } while (r++, --count);
14911507 urelocs += ARRAY_SIZE(stack);
@@ -1570,7 +1586,6 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) · 78 unmodified lines
15701586
15711587 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
15721588 if (!relocs) {
1573− kvfree(relocs);
15741589 err = -ENOMEM;
15751590 goto err;
15761591 }
@@ -1584,6 +1599,7 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) · 7 unmodified lines
15841599 if (__copy_from_user((char *)relocs + copied,
15851600 (char __user *)urelocs + copied,
15861601 len)) {
1602+end_user:
15871603 kvfree(relocs);
15881604 err = -EFAULT;
15891605 goto err;
@@ -1607,7 +1623,6 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) · 17 unmodified lines
16071623 unsafe_put_user(-1,
16081624 &urelocs[copied].presumed_offset,
16091625 end_user);
1610−end_user:
16111626 user_access_end();
16121627
16131628 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
@@ -2199,8 +2214,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, · 585 unmodified lines
21992214 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
22002215
22012216 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2202− if (USES_FULL_PPGTT(eb.i915))
2203− eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
22042217 reloc_cache_init(&eb.reloc_cache, eb.i915);
22052218
22062219 eb.buffer_count = args->buffer_count;
@@ -2221,20 +2234,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, · 14 unmodified lines
22212234 if (!eb.engine)
22222235 return -EINVAL;
22232236
2224− if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
2225− if (!HAS_RESOURCE_STREAMER(eb.i915)) {
2226− DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2227− return -EINVAL;
2228− }
2229− if (eb.engine->id != RCS) {
2230− DRM_DEBUG("RS is not available on %s\n",
2231− eb.engine->name);
2232− return -EINVAL;
2233− }
2234−
2235− eb.batch_flags |= I915_DISPATCH_RS;
2236− }
2237−
22382237 if (args->flags & I915_EXEC_FENCE_IN) {
22392238 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
22402239 if (!in_fence)
drivers/gpu/drm/i915/i915_gem_gtt.c+25−27
@@ -173,19 +173,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, · 172 unmodified lines
173173 return 0;
174174 }
175175
176− /* Early VLV doesn't have this */
177− if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) {
178− DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
179− return 0;
180− }
181−
182− if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
183− if (has_full_48bit_ppgtt)
184− return 3;
176+ if (has_full_48bit_ppgtt)
177+ return 3;
185178
186− if (has_full_ppgtt)
187− return 2;
188− }
179+ if (has_full_ppgtt)
180+ return 2;
189181
190182 return 1;
191183 }
@@ -1259,9 +1251,6 @@ static void gen8_free_page_tables(struct i915_address_space *vm, · 1067 unmodified lines
12591251 {
12601252 int i;
12611253
1262− if (!px_page(pd))
1263− return;
1264−
12651254 for (i = 0; i < I915_PDES; i++) {
12661255 if (pd->page_table[i] != vm->scratch_pt)
12671256 free_pt(vm, pd->page_table[i]);
@@ -2348,7 +2337,7 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) · 1080 unmodified lines
23482337 return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
23492338 }
23502339
2351−static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv)
2340+static void gen6_check_faults(struct drm_i915_private *dev_priv)
23522341 {
23532342 struct intel_engine_cs *engine;
23542343 enum intel_engine_id id;
@@ -2366,15 +2355,11 @@ static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv) · 11 unmodified lines
23662355 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
23672356 RING_FAULT_SRCID(fault),
23682357 RING_FAULT_FAULT_TYPE(fault));
2369− I915_WRITE(RING_FAULT_REG(engine),
2370− fault & ~RING_FAULT_VALID);
23712358 }
23722359 }
2373−
2374− POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
23752360 }
23762361
2377−static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
2362+static void gen8_check_faults(struct drm_i915_private *dev_priv)
23782363 {
23792364 u32 fault = I915_READ(GEN8_RING_FAULT_REG);
23802365
@@ -2399,22 +2384,20 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv) · 18 unmodified lines
23992384 GEN8_RING_FAULT_ENGINE_ID(fault),
24002385 RING_FAULT_SRCID(fault),
24012386 RING_FAULT_FAULT_TYPE(fault));
2402− I915_WRITE(GEN8_RING_FAULT_REG,
2403− fault & ~RING_FAULT_VALID);
24042387 }
2405−
2406− POSTING_READ(GEN8_RING_FAULT_REG);
24072388 }
24082389
24092390 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
24102391 {
24112392 /* From GEN8 onwards we only have one 'All Engine Fault Register' */
24122393 if (INTEL_GEN(dev_priv) >= 8)
2413− gen8_check_and_clear_faults(dev_priv);
2394+ gen8_check_faults(dev_priv);
24142395 else if (INTEL_GEN(dev_priv) >= 6)
2415− gen6_check_and_clear_faults(dev_priv);
2396+ gen6_check_faults(dev_priv);
24162397 else
24172398 return;
2399+
2400+ i915_clear_error_registers(dev_priv);
24182401 }
24192402
24202403 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
@@ -2937,6 +2920,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) · 516 unmodified lines
29372920 struct drm_mm_node *entry;
29382921 int ret;
29392922
2923+ /*
2924+ * GuC requires all resources that we're sharing with it to be placed in
2925+ * non-WOPCM memory. If GuC is not present or not in use we still need a
2926+ * small bias as ring wraparound at offset 0 sometimes hangs. No idea
2927+ * why.
2928+ */
2929+ ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
2930+ intel_guc_reserved_gtt_size(&dev_priv->guc));
2931+
29402932 ret = intel_vgt_balloon(dev_priv);
29412933 if (ret)
29422934 return ret;
@@ -3612,6 +3604,8 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) · 669 unmodified lines
36123604 mutex_lock(&dev_priv->drm.struct_mutex);
36133605 i915_address_space_init(&ggtt->vm, dev_priv);
36143606
3607+ ggtt->vm.is_ggtt = true;
3608+
36153609 /* Only VLV supports read-only GGTT mappings */
36163610 ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
36173611
@@ -3662,6 +3656,10 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915) · 44 unmodified lines
36623656
36633657 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
36643658 {
3659+ /* XXX Temporary pardon for error unload */
3660+ if (i915->ggtt.invalidate == gen6_ggtt_invalidate)
3661+ return;
3662+
36653663 /* We should only be called after i915_ggtt_enable_guc() */
36663664 GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
36673665
drivers/gpu/drm/i915/i915_gem_gtt.h+10−13
@@ -167,29 +167,22 @@ struct intel_rotation_info { · 166 unmodified lines
167167 } plane[2];
168168 } __packed;
169169
170−static inline void assert_intel_rotation_info_is_packed(void)
171−{
172− BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
173−}
174−
175170 struct intel_partial_info {
176171 u64 offset;
177172 unsigned int size;
178173 } __packed;
179174
180−static inline void assert_intel_partial_info_is_packed(void)
181−{
182− BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
183−}
184−
185175 enum i915_ggtt_view_type {
186176 I915_GGTT_VIEW_NORMAL = 0,
187177 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
188178 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
189179 };
190180
191−static inline void assert_i915_ggtt_view_type_is_unique(void)
181+static inline void assert_i915_gem_gtt_types(void)
192182 {
183+ BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
184+ BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
185+
193186 /* As we encode the size of each branch inside the union into its type,
194187 * we have to be careful that each branch has a unique size.
195188 */
@@ -229,7 +222,6 @@ struct i915_page_dma { · 33 unmodified lines
229222 };
230223
231224 #define px_base(px) (&(px)->base)
232−#define px_page(px) (px_base(px)->page)
233225 #define px_dma(px) (px_base(px)->daddr)
234226
235227 struct i915_page_table {
@@ -332,6 +324,9 @@ struct i915_address_space { · 96 unmodified lines
332324
333325 struct pagestash free_pages;
334326
327+ /* Global GTT */
328+ bool is_ggtt:1;
329+
335330 /* Some systems require uncached updates of the page directories */
336331 bool pt_kmap_wc:1;
337332
@@ -365,7 +360,7 @@ struct i915_address_space { · 27 unmodified lines
365360 I915_SELFTEST_DECLARE(bool scrub_64K);
366361 };
367362
368−#define i915_is_ggtt(V) (!(V)->file)
363+#define i915_is_ggtt(vm) ((vm)->is_ggtt)
369364
370365 static inline bool
371366 i915_vm_is_48bit(const struct i915_address_space *vm)
@@ -401,6 +396,8 @@ struct i915_ggtt { · 29 unmodified lines
401396
402397 int mtrr;
403398
399+ u32 pin_bias;
400+
404401 struct drm_mm_node error_capture;
405402 };
406403
drivers/gpu/drm/i915/i915_gem_object.h+5−5
@@ -421,19 +421,19 @@ i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj) · 420 unmodified lines
421421 }
422422
423423 static inline unsigned int
424−i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
424+i915_gem_object_get_tiling(const struct drm_i915_gem_object *obj)
425425 {
426426 return obj->tiling_and_stride & TILING_MASK;
427427 }
428428
429429 static inline bool
430−i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
430+i915_gem_object_is_tiled(const struct drm_i915_gem_object *obj)
431431 {
432432 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
433433 }
434434
435435 static inline unsigned int
436−i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
436+i915_gem_object_get_stride(const struct drm_i915_gem_object *obj)
437437 {
438438 return obj->tiling_and_stride & STRIDE_MASK;
439439 }
@@ -446,13 +446,13 @@ i915_gem_tile_height(unsigned int tiling) · 6 unmodified lines
446446 }
447447
448448 static inline unsigned int
449−i915_gem_object_get_tile_height(struct drm_i915_gem_object *obj)
449+i915_gem_object_get_tile_height(const struct drm_i915_gem_object *obj)
450450 {
451451 return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
452452 }
453453
454454 static inline unsigned int
455−i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj)
455+i915_gem_object_get_tile_row_size(const struct drm_i915_gem_object *obj)
456456 {
457457 return (i915_gem_object_get_stride(obj) *
458458 i915_gem_object_get_tile_height(obj));
drivers/gpu/drm/i915/i915_irq.c+26−10
@@ -478,7 +478,7 @@ void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv) · 477 unmodified lines
478478 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
479479 {
480480 spin_lock_irq(&dev_priv->irq_lock);
481− gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
481+ gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
482482 dev_priv->gt_pm.rps.pm_iir = 0;
483483 spin_unlock_irq(&dev_priv->irq_lock);
484484 }
@@ -516,7 +516,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) · 31 unmodified lines
516516
517517 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
518518
519− gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
519+ gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
520520
521521 spin_unlock_irq(&dev_priv->irq_lock);
522522 synchronize_irq(dev_priv->drm.irq);
@@ -1534,11 +1534,8 @@ static void gen8_gt_irq_ack(struct drm_i915_private *i915, · 1011 unmodified lines
15341534
15351535 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
15361536 gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1537− if (likely(gt_iir[2] & (i915->pm_rps_events |
1538− i915->pm_guc_events)))
1539− raw_reg_write(regs, GEN8_GT_IIR(2),
1540− gt_iir[2] & (i915->pm_rps_events |
1541− i915->pm_guc_events));
1537+ if (likely(gt_iir[2]))
1538+ raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
15421539 }
15431540
15441541 if (master_ctl & GEN8_GT_VECS_IRQ) {
@@ -3218,7 +3215,7 @@ static void i915_reset_device(struct drm_i915_private *dev_priv, · 1673 unmodified lines
32183215 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
32193216 }
32203217
3221−static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
3218+void i915_clear_error_registers(struct drm_i915_private *dev_priv)
32223219 {
32233220 u32 eir;
32243221
@@ -3241,6 +3238,22 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv) · 16 unmodified lines
32413238 I915_WRITE(EMR, I915_READ(EMR) | eir);
32423239 I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
32433240 }
3241+
3242+ if (INTEL_GEN(dev_priv) >= 8) {
3243+ I915_WRITE(GEN8_RING_FAULT_REG,
3244+ I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
3245+ POSTING_READ(GEN8_RING_FAULT_REG);
3246+ } else if (INTEL_GEN(dev_priv) >= 6) {
3247+ struct intel_engine_cs *engine;
3248+ enum intel_engine_id id;
3249+
3250+ for_each_engine(engine, dev_priv, id) {
3251+ I915_WRITE(RING_FAULT_REG(engine),
3252+ I915_READ(RING_FAULT_REG(engine)) &
3253+ ~RING_FAULT_VALID);
3254+ }
3255+ POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
3256+ }
32443257 }
32453258
32463259 /**
@@ -3296,7 +3309,8 @@ void i915_handle_error(struct drm_i915_private *dev_priv, · 49 unmodified lines
32963309 * Try engine reset when available. We fall back to full reset if
32973310 * single reset fails.
32983311 */
3299− if (intel_has_reset_engine(dev_priv)) {
3312+ if (intel_has_reset_engine(dev_priv) &&
3313+ !i915_terminally_wedged(&dev_priv->gpu_error)) {
33003314 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
33013315 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
33023316 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
@@ -4781,7 +4795,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) · 1478 unmodified lines
47814795 /* WaGsvRC0ResidencyMethod:vlv */
47824796 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
47834797 else
4784− dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4798+ dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD |
4799+ GEN6_PM_RP_DOWN_THRESHOLD |
4800+ GEN6_PM_RP_DOWN_TIMEOUT);
47854801
47864802 rps->pm_intrmsk_mbz = 0;
47874803
drivers/gpu/drm/i915/i915_pci.c+11−5
@@ -74,6 +74,7 @@ · 73 unmodified lines
7474 .unfenced_needs_alignment = 1, \
7575 .ring_mask = RENDER_RING, \
7676 .has_snoop = true, \
77+ .has_coherent_ggtt = false, \
7778 GEN_DEFAULT_PIPEOFFSETS, \
7879 GEN_DEFAULT_PAGE_SIZES, \
7980 CURSOR_OFFSETS
@@ -110,6 +111,7 @@ static const struct intel_device_info intel_i865g_info = { · 30 unmodified lines
110111 .has_gmch_display = 1, \
111112 .ring_mask = RENDER_RING, \
112113 .has_snoop = true, \
114+ .has_coherent_ggtt = true, \
113115 GEN_DEFAULT_PIPEOFFSETS, \
114116 GEN_DEFAULT_PAGE_SIZES, \
115117 CURSOR_OFFSETS
@@ -117,6 +119,7 @@ static const struct intel_device_info intel_i865g_info = { · 1 unmodified line
117119 static const struct intel_device_info intel_i915g_info = {
118120 GEN3_FEATURES,
119121 PLATFORM(INTEL_I915G),
122+ .has_coherent_ggtt = false,
120123 .cursor_needs_physical = 1,
121124 .has_overlay = 1, .overlay_needs_physical = 1,
122125 .hws_needs_physical = 1,
@@ -178,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = { · 55 unmodified lines
178181 .has_gmch_display = 1, \
179182 .ring_mask = RENDER_RING, \
180183 .has_snoop = true, \
184+ .has_coherent_ggtt = true, \
181185 GEN_DEFAULT_PIPEOFFSETS, \
182186 GEN_DEFAULT_PAGE_SIZES, \
183187 CURSOR_OFFSETS
@@ -220,6 +224,7 @@ static const struct intel_device_info intel_gm45_info = { · 36 unmodified lines
220224 .has_hotplug = 1, \
221225 .ring_mask = RENDER_RING | BSD_RING, \
222226 .has_snoop = true, \
227+ .has_coherent_ggtt = true, \
223228 /* ilk does support rc6, but we do not implement [power] contexts */ \
224229 .has_rc6 = 0, \
225230 GEN_DEFAULT_PIPEOFFSETS, \
@@ -243,6 +248,7 @@ static const struct intel_device_info intel_ironlake_m_info = { · 17 unmodified lines
243248 .has_hotplug = 1, \
244249 .has_fbc = 1, \
245250 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
251+ .has_coherent_ggtt = true, \
246252 .has_llc = 1, \
247253 .has_rc6 = 1, \
248254 .has_rc6p = 1, \
@@ -287,6 +293,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = { · 38 unmodified lines
287293 .has_hotplug = 1, \
288294 .has_fbc = 1, \
289295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
296+ .has_coherent_ggtt = true, \
290297 .has_llc = 1, \
291298 .has_rc6 = 1, \
292299 .has_rc6p = 1, \
@@ -347,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = { · 54 unmodified lines
347354 .has_aliasing_ppgtt = 1,
348355 .has_full_ppgtt = 1,
349356 .has_snoop = true,
357+ .has_coherent_ggtt = false,
350358 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
351359 .display_mmio_offset = VLV_DISPLAY_BASE,
352360 GEN_DEFAULT_PAGE_SIZES,
@@ -360,7 +368,6 @@ static const struct intel_device_info intel_valleyview_info = { · 7 unmodified lines
360368 .has_ddi = 1, \
361369 .has_fpga_dbg = 1, \
362370 .has_psr = 1, \
363− .has_resource_streamer = 1, \
364371 .has_dp_mst = 1, \
365372 .has_rc6p = 0 /* RC6p removed-by HSW */, \
366373 .has_runtime_pm = 1
@@ -433,7 +440,6 @@ static const struct intel_device_info intel_cherryview_info = { · 66 unmodified lines
433440 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
434441 .has_64bit_reloc = 1,
435442 .has_runtime_pm = 1,
436− .has_resource_streamer = 1,
437443 .has_rc6 = 1,
438444 .has_logical_ring_contexts = 1,
439445 .has_gmch_display = 1,
@@ -441,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = { · 1 unmodified line
441447 .has_full_ppgtt = 1,
442448 .has_reset_engine = 1,
443449 .has_snoop = true,
450+ .has_coherent_ggtt = false,
444451 .display_mmio_offset = VLV_DISPLAY_BASE,
445452 GEN_DEFAULT_PAGE_SIZES,
446453 GEN_CHV_PIPEOFFSETS,
@@ -506,7 +513,6 @@ static const struct intel_device_info intel_skylake_gt4_info = { · 59 unmodified lines
506513 .has_runtime_pm = 1, \
507514 .has_pooled_eu = 0, \
508515 .has_csr = 1, \
509− .has_resource_streamer = 1, \
510516 .has_rc6 = 1, \
511517 .has_dp_mst = 1, \
512518 .has_logical_ring_contexts = 1, \
@@ -517,6 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { · 4 unmodified lines
517523 .has_full_48bit_ppgtt = 1, \
518524 .has_reset_engine = 1, \
519525 .has_snoop = true, \
526+ .has_coherent_ggtt = false, \
520527 .has_ipc = 1, \
521528 GEN9_DEFAULT_PAGE_SIZES, \
522529 GEN_DEFAULT_PIPEOFFSETS, \
@@ -580,6 +587,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = { · 57 unmodified lines
580587 GEN9_FEATURES, \
581588 GEN(10), \
582589 .ddb_size = 1024, \
590+ .has_coherent_ggtt = false, \
583591 GLK_COLORS
584592
585593 static const struct intel_device_info intel_cannonlake_info = {
@@ -592,14 +600,12 @@ static const struct intel_device_info intel_cannonlake_info = { · 6 unmodified lines
592600 GEN10_FEATURES, \
593601 GEN(11), \
594602 .ddb_size = 2048, \
595− .has_csr = 0, \
596603 .has_logical_ring_elsq = 1
597604
598605 static const struct intel_device_info intel_icelake_11_info = {
599606 GEN11_FEATURES,
600607 PLATFORM(INTEL_ICELAKE),
601608 .is_alpha_support = 1,
602− .has_resource_streamer = 0,
603609 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
604610 };
605611
drivers/gpu/drm/i915/i915_perf.c+24−31
@@ -210,6 +210,7 @@ · 209 unmodified lines
210210 #include "i915_oa_cflgt3.h"
211211 #include "i915_oa_cnl.h"
212212 #include "i915_oa_icl.h"
213+#include "intel_lrc_reg.h"
213214
214215 /* HW requires this to be a power of two, between 128k and 16M, though driver
215216 * is currently generally designed assuming the largest 16M size is used such
@@ -1338,14 +1339,12 @@ free_oa_buffer(struct drm_i915_private *i915) · 1122 unmodified lines
13381339 {
13391340 mutex_lock(&i915->drm.struct_mutex);
13401341
1341− i915_gem_object_unpin_map(i915->perf.oa.oa_buffer.vma->obj);
1342− i915_vma_unpin(i915->perf.oa.oa_buffer.vma);
1343− i915_gem_object_put(i915->perf.oa.oa_buffer.vma->obj);
1344−
1345− i915->perf.oa.oa_buffer.vma = NULL;
1346− i915->perf.oa.oa_buffer.vaddr = NULL;
1342+ i915_vma_unpin_and_release(&i915->perf.oa.oa_buffer.vma,
1343+ I915_VMA_RELEASE_MAP);
13471344
13481345 mutex_unlock(&i915->drm.struct_mutex);
1346+
1347+ i915->perf.oa.oa_buffer.vaddr = NULL;
13491348 }
13501349
13511350 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
@@ -1638,27 +1637,25 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, · 286 unmodified lines
16381637 u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
16391638 u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
16401639 /* The MMIO offsets for Flex EU registers aren't contiguous */
1641− u32 flex_mmio[] = {
1642− i915_mmio_reg_offset(EU_PERF_CNTL0),
1643− i915_mmio_reg_offset(EU_PERF_CNTL1),
1644− i915_mmio_reg_offset(EU_PERF_CNTL2),
1645− i915_mmio_reg_offset(EU_PERF_CNTL3),
1646− i915_mmio_reg_offset(EU_PERF_CNTL4),
1647− i915_mmio_reg_offset(EU_PERF_CNTL5),
1648− i915_mmio_reg_offset(EU_PERF_CNTL6),
1640+ i915_reg_t flex_regs[] = {
1641+ EU_PERF_CNTL0,
1642+ EU_PERF_CNTL1,
1643+ EU_PERF_CNTL2,
1644+ EU_PERF_CNTL3,
1645+ EU_PERF_CNTL4,
1646+ EU_PERF_CNTL5,
1647+ EU_PERF_CNTL6,
16491648 };
16501649 int i;
16511650
1652− reg_state[ctx_oactxctrl] = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
1653− reg_state[ctx_oactxctrl+1] = (dev_priv->perf.oa.period_exponent <<
1654− GEN8_OA_TIMER_PERIOD_SHIFT) |
1655− (dev_priv->perf.oa.periodic ?
1656− GEN8_OA_TIMER_ENABLE : 0) |
1657− GEN8_OA_COUNTER_RESUME;
1651+ CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
1652+ (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
1653+ (dev_priv->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
1654+ GEN8_OA_COUNTER_RESUME);
16581655
1659− for (i = 0; i < ARRAY_SIZE(flex_mmio); i++) {
1656+ for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
16601657 u32 state_offset = ctx_flexeu0 + i * 2;
1661− u32 mmio = flex_mmio[i];
1658+ u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
16621659
16631660 /*
16641661 * This arbitrary default will select the 'EU FPU0 Pipeline
@@ -1678,8 +1675,7 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, · 13 unmodified lines
16781675 }
16791676 }
16801677
1681− reg_state[state_offset] = mmio;
1682− reg_state[state_offset+1] = value;
1678+ CTX_REG(reg_state, state_offset, flex_regs[i], value);
16831679 }
16841680 }
16851681
@@ -1821,7 +1817,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, · 135 unmodified lines
18211817 /* Switch away from any user context. */
18221818 ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
18231819 if (ret)
1824− goto out;
1820+ return ret;
18251821
18261822 /*
18271823 * The OA register config is setup through the context image. This image
@@ -1840,7 +1836,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, · 12 unmodified lines
18401836 wait_flags,
18411837 MAX_SCHEDULE_TIMEOUT);
18421838 if (ret)
1843− goto out;
1839+ return ret;
18441840
18451841 /* Update all contexts now that we've stalled the submission. */
18461842 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
@@ -1852,10 +1848,8 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, · 5 unmodified lines
18521848 continue;
18531849
18541850 regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1855− if (IS_ERR(regs)) {
1856− ret = PTR_ERR(regs);
1857− goto out;
1858− }
1851+ if (IS_ERR(regs))
1852+ return PTR_ERR(regs);
18591853
18601854 ce->state->obj->mm.dirty = true;
18611855 regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
@@ -1865,7 +1859,6 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, · 3 unmodified lines
18651859 i915_gem_object_unpin_map(ce->state->obj);
18661860 }
18671861
1868− out:
18691862 return ret;
18701863 }
18711864
drivers/gpu/drm/i915/i915_reg.h+387−340
@@ -344,6 +344,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 343 unmodified lines
344344 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
345345 #define GEN8_RPCS_S_CNT_SHIFT 15
346346 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
347+#define GEN11_RPCS_S_CNT_SHIFT 12
348+#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
347349 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
348350 #define GEN8_RPCS_SS_CNT_SHIFT 8
349351 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
@@ -1029,126 +1031,43 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 679 unmodified lines
10291031 /*
10301032 * i915_power_well_id:
10311033 *
1032− * Platform specific IDs used to look up power wells and - except for custom
1033− * power wells - to define request/status register flag bit positions. As such
1034− * the set of IDs on a given platform must be unique and except for custom
1035− * power wells their value must stay fixed.
1034+ * IDs used to look up power wells. Power wells accessed directly bypassing
1035+ * the power domains framework must be assigned a unique ID. The rest of power
1036+ * wells must be assigned DISP_PW_ID_NONE.
10361037 */
10371038 enum i915_power_well_id {
1038− /*
1039− * I830
1040− * - custom power well
1041− */
1042− I830_DISP_PW_PIPES = 0,
1043−
1044− /*
1045− * VLV/CHV
1046− * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
1047− * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
1048− */
1049− PUNIT_POWER_WELL_RENDER = 0,
1050− PUNIT_POWER_WELL_MEDIA = 1,
1051− PUNIT_POWER_WELL_DISP2D = 3,
1052− PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
1053− PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
1054− PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
1055− PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
1056− PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
1057− PUNIT_POWER_WELL_DPIO_RX0 = 10,
1058− PUNIT_POWER_WELL_DPIO_RX1 = 11,
1059− PUNIT_POWER_WELL_DPIO_CMN_D = 12,
1060− /* - custom power well */
1061− CHV_DISP_PW_PIPE_A, /* 13 */
1062−
1063− /*
1064− * HSW/BDW
1065− * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
1066− */
1067− HSW_DISP_PW_GLOBAL = 15,
1068−
1069− /*
1070− * GEN9+
1071− * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
1072− */
1073− SKL_DISP_PW_MISC_IO = 0,
1074− SKL_DISP_PW_DDI_A_E,
1075− GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1076− CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1077− SKL_DISP_PW_DDI_B,
1078− SKL_DISP_PW_DDI_C,
1079− SKL_DISP_PW_DDI_D,
1080− CNL_DISP_PW_DDI_F = 6,
1081−
1082− GLK_DISP_PW_AUX_A = 8,
1083− GLK_DISP_PW_AUX_B,
1084− GLK_DISP_PW_AUX_C,
1085− CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
1086− CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
1087− CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
1088− CNL_DISP_PW_AUX_D,
1089− CNL_DISP_PW_AUX_F,
1090−
1091− SKL_DISP_PW_1 = 14,
1039+ DISP_PW_ID_NONE,
1040+
1041+ VLV_DISP_PW_DISP2D,
1042+ BXT_DISP_PW_DPIO_CMN_A,
1043+ VLV_DISP_PW_DPIO_CMN_BC,
1044+ GLK_DISP_PW_DPIO_CMN_C,
1045+ CHV_DISP_PW_DPIO_CMN_D,
1046+ HSW_DISP_PW_GLOBAL,
1047+ SKL_DISP_PW_MISC_IO,
1048+ SKL_DISP_PW_1,
10921049 SKL_DISP_PW_2,
1093−
1094− /* - custom power wells */
1095− BXT_DPIO_CMN_A,
1096− BXT_DPIO_CMN_BC,
1097− GLK_DPIO_CMN_C, /* 18 */
1098−
1099− /*
1100− * GEN11+
1101− * - _HSW_PWR_WELL_CTL1-4
1102− * (status bit: (id&15)*2, req bit:(id&15)*2+1)
1103− */
1104− ICL_DISP_PW_1 = 0,
1105− ICL_DISP_PW_2,
1106− ICL_DISP_PW_3,
1107− ICL_DISP_PW_4,
1108−
1109− /*
1110− * - _HSW_PWR_WELL_CTL_AUX1/2/4
1111− * (status bit: (id&15)*2, req bit:(id&15)*2+1)
1112− */
1113− ICL_DISP_PW_AUX_A = 16,
1114− ICL_DISP_PW_AUX_B,
1115− ICL_DISP_PW_AUX_C,
1116− ICL_DISP_PW_AUX_D,
1117− ICL_DISP_PW_AUX_E,
1118− ICL_DISP_PW_AUX_F,
1119−
1120− ICL_DISP_PW_AUX_TBT1 = 24,
1121− ICL_DISP_PW_AUX_TBT2,
1122− ICL_DISP_PW_AUX_TBT3,
1123− ICL_DISP_PW_AUX_TBT4,
1124−
1125− /*
1126− * - _HSW_PWR_WELL_CTL_DDI1/2/4
1127− * (status bit: (id&15)*2, req bit:(id&15)*2+1)
1128− */
1129− ICL_DISP_PW_DDI_A = 32,
1130− ICL_DISP_PW_DDI_B,
1131− ICL_DISP_PW_DDI_C,
1132− ICL_DISP_PW_DDI_D,
1133− ICL_DISP_PW_DDI_E,
1134− ICL_DISP_PW_DDI_F, /* 37 */
1135−
1136− /*
1137− * Multiple platforms.
1138− * Must start following the highest ID of any platform.
1139− * - custom power wells
1140− */
1141− SKL_DISP_PW_DC_OFF = 38,
1142− I915_DISP_PW_ALWAYS_ON,
11431050 };
11441051
11451052 #define PUNIT_REG_PWRGT_CTRL 0x60
11461053 #define PUNIT_REG_PWRGT_STATUS 0x61
1147−#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
1148−#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
1149−#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
1150−#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
1151−#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
1054+#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1055+#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1056+#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1057+#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1058+#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1059+
1060+#define PUNIT_PWGT_IDX_RENDER 0
1061+#define PUNIT_PWGT_IDX_MEDIA 1
1062+#define PUNIT_PWGT_IDX_DISP2D 3
1063+#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1064+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1065+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1066+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1067+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1068+#define PUNIT_PWGT_IDX_DPIO_RX0 10
1069+#define PUNIT_PWGT_IDX_DPIO_RX1 11
1070+#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
11521071
11531072 #define PUNIT_REG_GPU_LFM 0xd3
11541073 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
@@ -1932,121 +1851,200 @@ enum i915_power_well_id { · 777 unmodified lines
19321851 #define N_SCALAR(x) ((x) << 24)
19331852 #define N_SCALAR_MASK (0x7F << 24)
19341853
1935−#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1854+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
19361855 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
19371856
1938−#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1939−#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1940−#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1941−#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1942−#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1943−#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1944−#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1945−#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1946−#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
1947− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1948− _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1949− _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1950−
1951−#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1952−#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1953−#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1954−#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1955−#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1956−#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1957−#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1958−#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1959−#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
1960− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1961− _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1962− _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1963−#define CRI_USE_FS32 (1 << 5)
1964−
1965−#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1966−#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1967−#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1968−#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1969−#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1970−#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1971−#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1972−#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1973−#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
1974− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1975− _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1976− _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1977−
1978−#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1979−#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1980−#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1981−#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1982−#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1983−#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1984−#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1985−#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1986−#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
1987− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1988− _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1989− _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1990−#define CRI_CALCINIT (1 << 1)
1991−
1992−#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1993−#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
1994−#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
1995−#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
1996−#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
1997−#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
1998−#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
1999−#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2000−#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
2001− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2002− _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2003− _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
2004−
2005−#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2006−#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2007−#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2008−#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2009−#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2010−#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2011−#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2012−#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2013−#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
2014− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2015− _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2016− _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
2017−#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2018−#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
2019−
2020−#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
2021−#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
2022−#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
2023−#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
2024−#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
2025−#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
2026−#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
2027−#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
2028−#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
2029− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
2030− _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
2031− _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
2032−
2033−#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2034−#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2035−#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2036−#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2037−#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2038−#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2039−#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2040−#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2041−#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
2042− _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
2043− _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
2044− _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
2045−#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2046−#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2047−#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2048−#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2049−#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
1857+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1858+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1859+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1860+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1861+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1862+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1863+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1864+#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1865+#define MG_TX1_LINK_PARAMS(port, ln) \
1866+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1867+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1868+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1869+
1870+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1871+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1872+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1873+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1874+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1875+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1876+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1877+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1878+#define MG_TX2_LINK_PARAMS(port, ln) \
1879+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1880+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1881+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1882+#define CRI_USE_FS32 (1 << 5)
1883+
1884+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1885+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1886+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1887+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1888+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1889+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1890+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1891+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1892+#define MG_TX1_PISO_READLOAD(port, ln) \
1893+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1894+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1895+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1896+
1897+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1898+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1899+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1900+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1901+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1902+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1903+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1904+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1905+#define MG_TX2_PISO_READLOAD(port, ln) \
1906+ MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1907+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1908+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1909+#define CRI_CALCINIT (1 << 1)
1910+
1911+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1912+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
1913+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
1914+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
1915+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
1916+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
1917+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
1918+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
1919+#define MG_TX1_SWINGCTRL(port, ln) \
1920+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
1921+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
1922+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
1923+
1924+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
1925+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
1926+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
1927+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
1928+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
1929+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
1930+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
1931+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
1932+#define MG_TX2_SWINGCTRL(port, ln) \
1933+ MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
1934+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
1935+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
1936+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
1937+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
1938+
1939+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
1940+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
1941+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
1942+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
1943+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
1944+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
1945+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
1946+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
1947+#define MG_TX1_DRVCTRL(port, ln) \
1948+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
1949+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
1950+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
1951+
1952+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
1953+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
1954+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
1955+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
1956+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
1957+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
1958+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
1959+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
1960+#define MG_TX2_DRVCTRL(port, ln) \
1961+ MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
1962+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
1963+ MG_TX_DRVCTRL_TX2LN1_PORT1)
1964+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
1965+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
1966+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
1967+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
1968+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
1969+#define CRI_LOADGEN_SEL(x) ((x) << 12)
1970+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
1971+
1972+#define MG_CLKHUB_LN0_PORT1 0x16839C
1973+#define MG_CLKHUB_LN1_PORT1 0x16879C
1974+#define MG_CLKHUB_LN0_PORT2 0x16939C
1975+#define MG_CLKHUB_LN1_PORT2 0x16979C
1976+#define MG_CLKHUB_LN0_PORT3 0x16A39C
1977+#define MG_CLKHUB_LN1_PORT3 0x16A79C
1978+#define MG_CLKHUB_LN0_PORT4 0x16B39C
1979+#define MG_CLKHUB_LN1_PORT4 0x16B79C
1980+#define MG_CLKHUB(port, ln) \
1981+ MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
1982+ MG_CLKHUB_LN0_PORT2, \
1983+ MG_CLKHUB_LN1_PORT1)
1984+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
1985+
1986+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
1987+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
1988+#define MG_TX_DCC_TX1LN0_PORT2 0x169110
1989+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
1990+#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
1991+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
1992+#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
1993+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
1994+#define MG_TX1_DCC(port, ln) \
1995+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
1996+ MG_TX_DCC_TX1LN0_PORT2, \
1997+ MG_TX_DCC_TX1LN1_PORT1)
1998+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
1999+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
2000+#define MG_TX_DCC_TX2LN0_PORT2 0x169090
2001+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
2002+#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2003+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2004+#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2005+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2006+#define MG_TX2_DCC(port, ln) \
2007+ MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
2008+ MG_TX_DCC_TX2LN0_PORT2, \
2009+ MG_TX_DCC_TX2LN1_PORT1)
2010+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2011+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2012+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2013+
2014+#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2015+#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2016+#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2017+#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2018+#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2019+#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2020+#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2021+#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2022+#define MG_DP_MODE(port, ln) \
2023+ MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
2024+ MG_DP_MODE_LN0_ACU_PORT2, \
2025+ MG_DP_MODE_LN1_ACU_PORT1)
2026+#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2027+#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2028+#define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
2029+#define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
2030+#define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
2031+#define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
2032+#define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
2033+
2034+#define MG_MISC_SUS0_PORT1 0x168814
2035+#define MG_MISC_SUS0_PORT2 0x169814
2036+#define MG_MISC_SUS0_PORT3 0x16A814
2037+#define MG_MISC_SUS0_PORT4 0x16B814
2038+#define MG_MISC_SUS0(tc_port) \
2039+ _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2040+#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
2041+#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
2042+#define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
2043+#define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
2044+#define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
2045+#define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
2046+#define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
2047+#define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
20502048
20512049 /* The spec defines this only for BXT PHY0, but lets assume that this
20522050 * would exist for PHY1 too if it had a second channel.
@@ -3086,18 +3084,9 @@ enum i915_power_well_id { · 1033 unmodified lines
30863084 /*
30873085 * GPIO regs
30883086 */
3089−#define GPIOA _MMIO(0x5010)
3090−#define GPIOB _MMIO(0x5014)
3091−#define GPIOC _MMIO(0x5018)
3092−#define GPIOD _MMIO(0x501c)
3093−#define GPIOE _MMIO(0x5020)
3094−#define GPIOF _MMIO(0x5024)
3095−#define GPIOG _MMIO(0x5028)
3096−#define GPIOH _MMIO(0x502c)
3097−#define GPIOJ _MMIO(0x5034)
3098−#define GPIOK _MMIO(0x5038)
3099−#define GPIOL _MMIO(0x503C)
3100−#define GPIOM _MMIO(0x5040)
3087+#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3088+ 4 * (gpio))
3089+
31013090 # define GPIO_CLOCK_DIR_MASK (1 << 0)
31023091 # define GPIO_CLOCK_DIR_IN (0 << 1)
31033092 # define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -5476,6 +5465,7 @@ enum { · 2372 unmodified lines
54765465 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
54775466 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
54785467 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5468+#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
54795469 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
54805470 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
54815471 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
@@ -6527,7 +6517,7 @@ enum { · 1045 unmodified lines
65276517 #define PLANE_CTL_YUV422_UYVY (1 << 16)
65286518 #define PLANE_CTL_YUV422_YVYU (2 << 16)
65296519 #define PLANE_CTL_YUV422_VYUY (3 << 16)
6530−#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
6520+#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
65316521 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
65326522 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
65336523 #define PLANE_CTL_TILED_MASK (0x7 << 10)
@@ -7207,6 +7197,7 @@ enum { · 673 unmodified lines
72077197 #define GEN11_TC3_HOTPLUG (1 << 18)
72087198 #define GEN11_TC2_HOTPLUG (1 << 17)
72097199 #define GEN11_TC1_HOTPLUG (1 << 16)
7200+#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
72107201 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
72117202 GEN11_TC3_HOTPLUG | \
72127203 GEN11_TC2_HOTPLUG | \
@@ -7215,6 +7206,7 @@ enum { · 2 unmodified lines
72157206 #define GEN11_TBT3_HOTPLUG (1 << 2)
72167207 #define GEN11_TBT2_HOTPLUG (1 << 1)
72177208 #define GEN11_TBT1_HOTPLUG (1 << 0)
7209+#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
72187210 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
72197211 GEN11_TBT3_HOTPLUG | \
72207212 GEN11_TBT2_HOTPLUG | \
@@ -7490,6 +7482,8 @@ enum { · 269 unmodified lines
74907482
74917483 /* PCH */
74927484
7485+#define PCH_DISPLAY_BASE 0xc0000u
7486+
74937487 /* south display engine interrupt: IBX */
74947488 #define SDE_AUDIO_POWER_D (1 << 27)
74957489 #define SDE_AUDIO_POWER_C (1 << 26)
@@ -7587,6 +7581,8 @@ enum { · 91 unmodified lines
75877581 #define SDE_GMBUS_ICP (1 << 23)
75887582 #define SDE_DDIB_HOTPLUG_ICP (1 << 17)
75897583 #define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7584+#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
7585+#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
75907586 #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
75917587 SDE_DDIA_HOTPLUG_ICP)
75927588 #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
@@ -7782,20 +7778,6 @@ enum { · 189 unmodified lines
77827778 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
77837779 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
77847780
7785−#define PCH_GPIOA _MMIO(0xc5010)
7786−#define PCH_GPIOB _MMIO(0xc5014)
7787−#define PCH_GPIOC _MMIO(0xc5018)
7788−#define PCH_GPIOD _MMIO(0xc501c)
7789−#define PCH_GPIOE _MMIO(0xc5020)
7790−#define PCH_GPIOF _MMIO(0xc5024)
7791−
7792−#define PCH_GMBUS0 _MMIO(0xc5100)
7793−#define PCH_GMBUS1 _MMIO(0xc5104)
7794−#define PCH_GMBUS2 _MMIO(0xc5108)
7795−#define PCH_GMBUS3 _MMIO(0xc510c)
7796−#define PCH_GMBUS4 _MMIO(0xc5110)
7797−#define PCH_GMBUS5 _MMIO(0xc5120)
7798−
77997781 #define _PCH_DPLL_A 0xc6014
78007782 #define _PCH_DPLL_B 0xc6018
78017783 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
@@ -8498,8 +8480,10 @@ enum { · 696 unmodified lines
84988480 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
84998481 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
85008482 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8501−#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
8502− GEN6_PM_RP_DOWN_THRESHOLD | \
8483+#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
8484+ GEN6_PM_RP_UP_THRESHOLD | \
8485+ GEN6_PM_RP_DOWN_EI_EXPIRED | \
8486+ GEN6_PM_RP_DOWN_THRESHOLD | \
85038487 GEN6_PM_RP_DOWN_TIMEOUT)
85048488
85058489 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
@@ -8827,46 +8811,78 @@ enum { · 321 unmodified lines
88278811 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
88288812 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
88298813
8830−/* HSW Power Wells */
8831−#define _HSW_PWR_WELL_CTL1 0x45400
8832−#define _HSW_PWR_WELL_CTL2 0x45404
8833−#define _HSW_PWR_WELL_CTL3 0x45408
8834−#define _HSW_PWR_WELL_CTL4 0x4540C
8835−
8836−#define _ICL_PWR_WELL_CTL_AUX1 0x45440
8837−#define _ICL_PWR_WELL_CTL_AUX2 0x45444
8838−#define _ICL_PWR_WELL_CTL_AUX4 0x4544C
8839−
8840−#define _ICL_PWR_WELL_CTL_DDI1 0x45450
8841−#define _ICL_PWR_WELL_CTL_DDI2 0x45454
8842−#define _ICL_PWR_WELL_CTL_DDI4 0x4545C
8843−
88448814 /*
8845− * Each power well control register contains up to 16 (request, status) HW
8846− * flag tuples. The register index and HW flag shift is determined by the
8847− * power well ID (see i915_power_well_id). There are 4 possible sources of
8848− * power well requests each source having its own set of control registers:
8849− * BIOS, DRIVER, KVMR, DEBUG.
8815+ * HSW - ICL power wells
8816+ *
8817+ * Platforms have up to 3 power well control register sets, each set
8818+ * controlling up to 16 power wells via a request/status HW flag tuple:
8819+ * - main (HSW_PWR_WELL_CTL[1-4])
8820+ * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
8821+ * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
8822+ * Each control register set consists of up to 4 registers used by different
8823+ * sources that can request a power well to be enabled:
8824+ * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
8825+ * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
8826+ * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
8827+ * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
88508828 */
8851−#define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
8852−#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
8853−#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8854− _HSW_PWR_WELL_CTL1, \
8855− _ICL_PWR_WELL_CTL_AUX1, \
8856− _ICL_PWR_WELL_CTL_DDI1))
8857−#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8858− _HSW_PWR_WELL_CTL2, \
8859− _ICL_PWR_WELL_CTL_AUX2, \
8860− _ICL_PWR_WELL_CTL_DDI2))
8861−/* KVMR doesn't have a reg for AUX or DDI power well control */
8862−#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
8863−#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8864− _HSW_PWR_WELL_CTL4, \
8865− _ICL_PWR_WELL_CTL_AUX4, \
8866− _ICL_PWR_WELL_CTL_DDI4))
8867−
8868−#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
8869−#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
8829+#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
8830+#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
8831+#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
8832+#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
8833+#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
8834+#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
8835+
8836+/* HSW/BDW power well */
8837+#define HSW_PW_CTL_IDX_GLOBAL 15
8838+
8839+/* SKL/BXT/GLK/CNL power wells */
8840+#define SKL_PW_CTL_IDX_PW_2 15
8841+#define SKL_PW_CTL_IDX_PW_1 14
8842+#define CNL_PW_CTL_IDX_AUX_F 12
8843+#define CNL_PW_CTL_IDX_AUX_D 11
8844+#define GLK_PW_CTL_IDX_AUX_C 10
8845+#define GLK_PW_CTL_IDX_AUX_B 9
8846+#define GLK_PW_CTL_IDX_AUX_A 8
8847+#define CNL_PW_CTL_IDX_DDI_F 6
8848+#define SKL_PW_CTL_IDX_DDI_D 4
8849+#define SKL_PW_CTL_IDX_DDI_C 3
8850+#define SKL_PW_CTL_IDX_DDI_B 2
8851+#define SKL_PW_CTL_IDX_DDI_A_E 1
8852+#define GLK_PW_CTL_IDX_DDI_A 1
8853+#define SKL_PW_CTL_IDX_MISC_IO 0
8854+
8855+/* ICL - power wells */
8856+#define ICL_PW_CTL_IDX_PW_4 3
8857+#define ICL_PW_CTL_IDX_PW_3 2
8858+#define ICL_PW_CTL_IDX_PW_2 1
8859+#define ICL_PW_CTL_IDX_PW_1 0
8860+
8861+#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
8862+#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
8863+#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
8864+#define ICL_PW_CTL_IDX_AUX_TBT4 11
8865+#define ICL_PW_CTL_IDX_AUX_TBT3 10
8866+#define ICL_PW_CTL_IDX_AUX_TBT2 9
8867+#define ICL_PW_CTL_IDX_AUX_TBT1 8
8868+#define ICL_PW_CTL_IDX_AUX_F 5
8869+#define ICL_PW_CTL_IDX_AUX_E 4
8870+#define ICL_PW_CTL_IDX_AUX_D 3
8871+#define ICL_PW_CTL_IDX_AUX_C 2
8872+#define ICL_PW_CTL_IDX_AUX_B 1
8873+#define ICL_PW_CTL_IDX_AUX_A 0
8874+
8875+#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
8876+#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
8877+#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
8878+#define ICL_PW_CTL_IDX_DDI_F 5
8879+#define ICL_PW_CTL_IDX_DDI_E 4
8880+#define ICL_PW_CTL_IDX_DDI_D 3
8881+#define ICL_PW_CTL_IDX_DDI_C 2
8882+#define ICL_PW_CTL_IDX_DDI_B 1
8883+#define ICL_PW_CTL_IDX_DDI_A 0
8884+
8885+/* HSW - power well misc debug registers */
88708886 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
88718887 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
88728888 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
@@ -8878,22 +8894,32 @@ enum skl_power_gate { · 5 unmodified lines
88788894 SKL_PG0,
88798895 SKL_PG1,
88808896 SKL_PG2,
8897+ ICL_PG3,
8898+ ICL_PG4,
88818899 };
88828900
88838901 #define SKL_FUSE_STATUS _MMIO(0x42000)
88848902 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
8885−/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
8886−#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
8887−/* PG0 (HW control->no power well ID), PG1..PG4 (ICL_DISP_PW1..ICL_DISP_PW4) */
8888−#define ICL_PW_TO_PG(pw) ((pw) - ICL_DISP_PW_1 + SKL_PG1)
8903+/*
8904+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
8905+ * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
8906+ */
8907+#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
8908+ ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
8909+/*
8910+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
8911+ * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
8912+ */
8913+#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
8914+ ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
88898915 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
88908916
8891−#define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
8917+#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
88928918 #define _CNL_AUX_ANAOVRD1_B 0x162250
88938919 #define _CNL_AUX_ANAOVRD1_C 0x162210
88948920 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
88958921 #define _CNL_AUX_ANAOVRD1_F 0x162A90
8896−#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
8922+#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
88978923 _CNL_AUX_ANAOVRD1_B, \
88988924 _CNL_AUX_ANAOVRD1_C, \
88998925 _CNL_AUX_ANAOVRD1_D, \
@@ -9367,9 +9393,13 @@ enum skl_power_gate { · 467 unmodified lines
93679393 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
93689394 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
93699395 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9370−#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12)
93719396 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
9397+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
9398+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
9399+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
9400+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
93729401 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
9402+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
93739403 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
93749404 #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
93759405 _MG_CLKTOP2_HSCLKCTL_PORT1, \
@@ -9380,7 +9410,10 @@ enum skl_power_gate { · 4 unmodified lines
93809410 #define _MG_PLL_DIV0_PORT3 0x16AA00
93819411 #define _MG_PLL_DIV0_PORT4 0x16BA00
93829412 #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
9413+#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
9414+#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
93839415 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
9416+#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
93849417 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
93859418 #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
93869419 _MG_PLL_DIV0_PORT2)
@@ -9395,6 +9428,7 @@ enum skl_power_gate { · 8 unmodified lines
93959428 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
93969429 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
93979430 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
9431+#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
93989432 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
93999433 #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
94009434 _MG_PLL_DIV1_PORT2)
@@ -10347,8 +10381,8 @@ enum skl_power_gate { · 946 unmodified lines
1034710381 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
1034810382
1034910383 /* Icelake Display Stream Compression Registers */
10350−#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
10351−#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
10384+#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
10385+#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
1035210386 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
1035310387 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
1035410388 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
@@ -10368,8 +10402,8 @@ enum skl_power_gate { · 13 unmodified lines
1036810402 #define DSC_VER_MIN_SHIFT 4
1036910403 #define DSC_VER_MAJ (0x1 << 0)
1037010404
10371−#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
10372−#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
10405+#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
10406+#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
1037310407 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
1037410408 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
1037510409 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
@@ -10382,8 +10416,8 @@ enum skl_power_gate { · 6 unmodified lines
1038210416 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
1038310417 #define DSC_BPP(bpp) ((bpp) << 0)
1038410418
10385−#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
10386−#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
10419+#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
10420+#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
1038710421 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
1038810422 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
1038910423 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
@@ -10397,8 +10431,8 @@ enum skl_power_gate { · 7 unmodified lines
1039710431 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
1039810432 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
1039910433
10400−#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
10401−#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
10434+#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
10435+#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
1040210436 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
1040310437 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
1040410438 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
@@ -10412,8 +10446,8 @@ enum skl_power_gate { · 7 unmodified lines
1041210446 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
1041310447 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
1041410448
10415−#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
10416−#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
10449+#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
10450+#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
1041710451 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
1041810452 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
1041910453 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
@@ -10422,13 +10456,13 @@ enum skl_power_gate { · 2 unmodified lines
1042210456 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
1042310457 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
1042410458 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10425− _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
10459+ _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
1042610460 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
1042710461 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
1042810462 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
1042910463
10430−#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
10431−#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
10464+#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
10465+#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
1043210466 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
1043310467 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
1043410468 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
@@ -10437,13 +10471,13 @@ enum skl_power_gate { · 2 unmodified lines
1043710471 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
1043810472 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
1043910473 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10440− _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
10474+ _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
1044110475 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10442−#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
10476+#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
1044310477 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
1044410478
10445−#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
10446−#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
10479+#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
10480+#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
1044710481 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
1044810482 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
1044910483 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
@@ -10454,13 +10488,13 @@ enum skl_power_gate { · 4 unmodified lines
1045410488 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
1045510489 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
1045610490 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
10457−#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
10458−#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
10491+#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
10492+#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
1045910493 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
1046010494 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
1046110495
10462−#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
10463−#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
10496+#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
10497+#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
1046410498 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
1046510499 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
1046610500 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
@@ -10474,8 +10508,8 @@ enum skl_power_gate { · 7 unmodified lines
1047410508 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
1047510509 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
1047610510
10477−#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
10478−#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
10511+#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
10512+#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
1047910513 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
1048010514 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
1048110515 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
@@ -10489,8 +10523,8 @@ enum skl_power_gate { · 7 unmodified lines
1048910523 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
1049010524 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
1049110525
10492−#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
10493−#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
10526+#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
10527+#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
1049410528 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
1049510529 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
1049610530 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
@@ -10504,8 +10538,8 @@ enum skl_power_gate { · 7 unmodified lines
1050410538 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
1050510539 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
1050610540
10507−#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
10508−#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
10541+#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
10542+#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
1050910543 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
1051010544 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
1051110545 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
@@ -10521,8 +10555,8 @@ enum skl_power_gate { · 9 unmodified lines
1052110555 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
1052210556 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
1052310557
10524−#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
10525−#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
10558+#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
10559+#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
1052610560 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
1052710561 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
1052810562 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
@@ -10534,8 +10568,8 @@ enum skl_power_gate { · 5 unmodified lines
1053410568 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
1053510569 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
1053610570
10537−#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
10538−#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
10571+#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
10572+#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
1053910573 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
1054010574 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
1054110575 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
@@ -10547,8 +10581,8 @@ enum skl_power_gate { · 5 unmodified lines
1054710581 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
1054810582 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
1054910583
10550−#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
10551−#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
10584+#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
10585+#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
1055210586 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
1055310587 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
1055410588 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
@@ -10560,8 +10594,8 @@ enum skl_power_gate { · 5 unmodified lines
1056010594 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
1056110595 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
1056210596
10563−#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
10564−#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
10597+#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
10598+#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
1056510599 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
1056610600 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
1056710601 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
@@ -10573,8 +10607,8 @@ enum skl_power_gate { · 5 unmodified lines
1057310607 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
1057410608 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
1057510609
10576−#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
10577−#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
10610+#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
10611+#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
1057810612 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
1057910613 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
1058010614 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
@@ -10586,8 +10620,8 @@ enum skl_power_gate { · 5 unmodified lines
1058610620 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
1058710621 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
1058810622
10589−#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
10590−#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
10623+#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
10624+#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
1059110625 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
1059210626 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
1059310627 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
@@ -10599,7 +10633,7 @@ enum skl_power_gate { · 5 unmodified lines
1059910633 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
1060010634 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
1060110635 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
10602−#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
10636+#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
1060310637
1060410638 /* Icelake Rate Control Buffer Threshold Registers */
1060510639 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
@@ -10652,4 +10686,17 @@ enum skl_power_gate { · 46 unmodified lines
1065210686 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
1065310687 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
1065410688
10689+#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
10690+#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
10691+#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
10692+#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
10693+#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
10694+#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
10695+
10696+#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
10697+#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
10698+
10699+#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
10700+#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
10701+
1065510702 #endif /* _I915_REG_H_ */
drivers/gpu/drm/i915/i915_request.c+4−5
@@ -527,7 +527,7 @@ void __i915_request_submit(struct i915_request *request) · 526 unmodified lines
527527
528528 seqno = timeline_get_seqno(&engine->timeline);
529529 GEM_BUG_ON(!seqno);
530− GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
530+ GEM_BUG_ON(intel_engine_signaled(engine, seqno));
531531
532532 /* We may be recursing from the signal callback of another i915 fence */
533533 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
@@ -579,8 +579,7 @@ void __i915_request_unsubmit(struct i915_request *request) · 45 unmodified lines
579579 */
580580 GEM_BUG_ON(!request->global_seqno);
581581 GEM_BUG_ON(request->global_seqno != engine->timeline.seqno);
582− GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine),
583− request->global_seqno));
582+ GEM_BUG_ON(intel_engine_has_completed(engine, request->global_seqno));
584583 engine->timeline.seqno--;
585584
586585 /* We may be recursing from the signal callback of another i915 fence */
@@ -1205,7 +1204,7 @@ static bool __i915_spin_request(const struct i915_request *rq, · 618 unmodified lines
12051204 * it is a fair assumption that it will not complete within our
12061205 * relatively short timeout.
12071206 */
1208− if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1))
1207+ if (!intel_engine_has_started(engine, seqno))
12091208 return false;
12101209
12111210 /*
@@ -1222,7 +1221,7 @@ static bool __i915_spin_request(const struct i915_request *rq, · 10 unmodified lines
12221221 irq = READ_ONCE(engine->breadcrumbs.irq_count);
12231222 timeout_us += local_clock_us(&cpu);
12241223 do {
1225− if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
1224+ if (intel_engine_has_completed(engine, seqno))
12261225 return seqno == i915_request_global_seqno(rq);
12271226
12281227 /*
drivers/gpu/drm/i915/i915_request.h+25−14
@@ -272,7 +272,10 @@ long i915_request_wait(struct i915_request *rq, · 271 unmodified lines
272272 #define I915_WAIT_ALL BIT(2) /* used by i915_gem_object_wait() */
273273 #define I915_WAIT_FOR_IDLE_BOOST BIT(3)
274274
275−static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine);
275+static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
276+ u32 seqno);
277+static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
278+ u32 seqno);
276279
277280 /**
278281 * Returns true if seq1 is later than seq2.
@@ -282,11 +285,31 @@ static inline bool i915_seqno_passed(u32 seq1, u32 seq2) · 3 unmodified lines
282285 return (s32)(seq1 - seq2) >= 0;
283286 }
284287
288+/**
289+ * i915_request_started - check if the request has begun being executed
290+ * @rq: the request
291+ *
292+ * Returns true if the request has been submitted to hardware, and the hardware
293+ * has advanced passed the end of the previous request and so should be either
294+ * currently processing the request (though it may be preempted and so
295+ * not necessarily the next request to complete) or have completed the request.
296+ */
297+static inline bool i915_request_started(const struct i915_request *rq)
298+{
299+ u32 seqno;
300+
301+ seqno = i915_request_global_seqno(rq);
302+ if (!seqno) /* not yet submitted to HW */
303+ return false;
304+
305+ return intel_engine_has_started(rq->engine, seqno);
306+}
307+
285308 static inline bool
286309 __i915_request_completed(const struct i915_request *rq, u32 seqno)
287310 {
288311 GEM_BUG_ON(!seqno);
289− return i915_seqno_passed(intel_engine_get_seqno(rq->engine), seqno) &&
312+ return intel_engine_has_completed(rq->engine, seqno) &&
290313 seqno == i915_request_global_seqno(rq);
291314 }
292315
@@ -301,18 +324,6 @@ static inline bool i915_request_completed(const struct i915_request *rq) · 8 unmodified lines
301324 return __i915_request_completed(rq, seqno);
302325 }
303326
304−static inline bool i915_request_started(const struct i915_request *rq)
305−{
306− u32 seqno;
307−
308− seqno = i915_request_global_seqno(rq);
309− if (!seqno)
310− return false;
311−
312− return i915_seqno_passed(intel_engine_get_seqno(rq->engine),
313− seqno - 1);
314−}
315−
316327 static inline bool i915_sched_node_signaled(const struct i915_sched_node *node)
317328 {
318329 const struct i915_request *rq =
drivers/gpu/drm/i915/i915_vma.c+4−1
@@ -405,7 +405,7 @@ void i915_vma_unpin_iomap(struct i915_vma *vma) · 404 unmodified lines
405405 i915_vma_unpin(vma);
406406 }
407407
408−void i915_vma_unpin_and_release(struct i915_vma **p_vma)
408+void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags)
409409 {
410410 struct i915_vma *vma;
411411 struct drm_i915_gem_object *obj;
@@ -420,6 +420,9 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma) · 8 unmodified lines
420420 i915_vma_unpin(vma);
421421 i915_vma_close(vma);
422422
423+ if (flags & I915_VMA_RELEASE_MAP)
424+ i915_gem_object_unpin_map(obj);
425+
423426 __i915_gem_object_release_unless_active(obj);
424427 }
425428
drivers/gpu/drm/i915/i915_vma.h+9−1
@@ -138,7 +138,8 @@ i915_vma_instance(struct drm_i915_gem_object *obj, · 137 unmodified lines
138138 struct i915_address_space *vm,
139139 const struct i915_ggtt_view *view);
140140
141−void i915_vma_unpin_and_release(struct i915_vma **p_vma);
141+void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags);
142+#define I915_VMA_RELEASE_MAP BIT(0)
142143
143144 static inline bool i915_vma_is_active(struct i915_vma *vma)
144145 {
@@ -207,6 +208,11 @@ static inline u32 i915_ggtt_offset(const struct i915_vma *vma) · 62 unmodified lines
207208 return lower_32_bits(vma->node.start);
208209 }
209210
211+static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
212+{
213+ return i915_vm_to_ggtt(vma->vm)->pin_bias;
214+}
215+
210216 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
211217 {
212218 i915_gem_object_get(vma->obj);
@@ -245,6 +251,8 @@ i915_vma_compare(struct i915_vma *vma, · 32 unmodified lines
245251 if (cmp)
246252 return cmp;
247253
254+ assert_i915_gem_gtt_types();
255+
248256 /* ggtt_view.type also encodes its size so that we both distinguish
249257 * different views using it as a "type" and also use a compact (no
250258 * accessing of uninitialised padding bytes) memcmp without storing
drivers/gpu/drm/i915/intel_atomic_plane.c+4−2
@@ -159,7 +159,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ · 158 unmodified lines
159159 }
160160
161161 intel_state->base.visible = false;
162− ret = intel_plane->check_plane(intel_plane, crtc_state, intel_state);
162+ ret = intel_plane->check_plane(crtc_state, intel_state);
163163 if (ret)
164164 return ret;
165165
@@ -170,7 +170,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ · 4 unmodified lines
170170 if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
171171 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
172172 if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
173− state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
173+ state->fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
174+ state->fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
175+ state->fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
174176 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
175177 return -EINVAL;
176178 }
drivers/gpu/drm/i915/intel_breadcrumbs.c+2−4
@@ -256,8 +256,7 @@ void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine) · 255 unmodified lines
256256 spin_unlock(&b->irq_lock);
257257
258258 rbtree_postorder_for_each_entry_safe(wait, n, &b->waiters, node) {
259− GEM_BUG_ON(!i915_seqno_passed(intel_engine_get_seqno(engine),
260− wait->seqno));
259+ GEM_BUG_ON(!intel_engine_signaled(engine, wait->seqno));
261260 RB_CLEAR_NODE(&wait->node);
262261 wake_up_process(wait->tsk);
263262 }
@@ -508,8 +507,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine, · 244 unmodified lines
508507 return armed;
509508
510509 /* Make the caller recheck if its request has already started. */
511− return i915_seqno_passed(intel_engine_get_seqno(engine),
512− wait->seqno - 1);
510+ return intel_engine_has_started(engine, wait->seqno);
513511 }
514512
515513 static inline bool chain_wakeup(struct rb_node *rb, int priority)
drivers/gpu/drm/i915/intel_csr.c+24−9
@@ -55,7 +55,9 @@ MODULE_FIRMWARE(I915_CSR_BXT); · 54 unmodified lines
5555 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
5656
5757
58−#define CSR_MAX_FW_SIZE 0x2FFF
58+#define BXT_CSR_MAX_FW_SIZE 0x3000
59+#define GLK_CSR_MAX_FW_SIZE 0x4000
60+#define ICL_CSR_MAX_FW_SIZE 0x6000
5961 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
6062
6163 struct intel_css_header {
@@ -279,6 +281,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, · 217 unmodified lines
279281 struct intel_csr *csr = &dev_priv->csr;
280282 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
281283 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
284+ uint32_t max_fw_size = 0;
282285 uint32_t i;
283286 uint32_t *dmc_payload;
284287 uint32_t required_version;
@@ -359,6 +362,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, · 74 unmodified lines
359362 si->stepping);
360363 return NULL;
361364 }
365+ /* Convert dmc_offset into number of bytes. By default it is in dwords*/
366+ dmc_offset *= 4;
362367 readcount += dmc_offset;
363368
364369 /* Extract dmc_header information. */
@@ -391,8 +396,16 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, · 26 unmodified lines
391396
392397 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
393398 nbytes = dmc_header->fw_size * 4;
394− if (nbytes > CSR_MAX_FW_SIZE) {
395− DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
399+ if (INTEL_GEN(dev_priv) >= 11)
400+ max_fw_size = ICL_CSR_MAX_FW_SIZE;
401+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
402+ max_fw_size = GLK_CSR_MAX_FW_SIZE;
403+ else if (IS_GEN9(dev_priv))
404+ max_fw_size = BXT_CSR_MAX_FW_SIZE;
405+ else
406+ MISSING_CASE(INTEL_REVID(dev_priv));
407+ if (nbytes > max_fw_size) {
408+ DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
396409 return NULL;
397410 }
398411 csr->dmc_fw_size = dmc_header->fw_size;
@@ -468,12 +481,6 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) · 69 unmodified lines
468481 csr->fw_path = I915_CSR_SKL;
469482 else if (IS_BROXTON(dev_priv))
470483 csr->fw_path = I915_CSR_BXT;
471− else {
472− DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
473− return;
474− }
475−
476− DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
477484
478485 /*
479486 * Obtain a runtime pm reference, until CSR is loaded,
@@ -481,6 +488,14 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) · 1 unmodified line
481488 */
482489 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
483490
491+ if (csr->fw_path == NULL) {
492+ DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
493+ WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv)));
494+
495+ return;
496+ }
497+
498+ DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
484499 schedule_work(&dev_priv->csr.work);
485500 }
486501
drivers/gpu/drm/i915/intel_ddi.c+223−17
@@ -1414,7 +1414,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, · 1413 unmodified lines
14141414 break;
14151415 }
14161416
1417− ref_clock = dev_priv->cdclk.hw.ref;
1417+ ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
14181418
14191419 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
14201420
@@ -1427,6 +1427,81 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, · 6 unmodified lines
14271427 return dco_freq / (p0 * p1 * p2 * 5);
14281428 }
14291429
1430+static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1431+ enum port port)
1432+{
1433+ u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1434+
1435+ switch (val) {
1436+ case DDI_CLK_SEL_NONE:
1437+ return 0;
1438+ case DDI_CLK_SEL_TBT_162:
1439+ return 162000;
1440+ case DDI_CLK_SEL_TBT_270:
1441+ return 270000;
1442+ case DDI_CLK_SEL_TBT_540:
1443+ return 540000;
1444+ case DDI_CLK_SEL_TBT_810:
1445+ return 810000;
1446+ default:
1447+ MISSING_CASE(val);
1448+ return 0;
1449+ }
1450+}
1451+
1452+static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1453+ enum port port)
1454+{
1455+ u32 mg_pll_div0, mg_clktop_hsclkctl;
1456+ u32 m1, m2_int, m2_frac, div1, div2, refclk;
1457+ u64 tmp;
1458+
1459+ refclk = dev_priv->cdclk.hw.ref;
1460+
1461+ mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462+ mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1463+
1464+ m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465+ m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466+ m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467+ (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468+ MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1469+
1470+ switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1472+ div1 = 2;
1473+ break;
1474+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1475+ div1 = 3;
1476+ break;
1477+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1478+ div1 = 5;
1479+ break;
1480+ case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1481+ div1 = 7;
1482+ break;
1483+ default:
1484+ MISSING_CASE(mg_clktop_hsclkctl);
1485+ return 0;
1486+ }
1487+
1488+ div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490+ /* div2 value of 0 is same as 1 means no div */
1491+ if (div2 == 0)
1492+ div2 = 1;
1493+
1494+ /*
1495+ * Adjust the original formula to delay the division by 2^22 in order to
1496+ * minimize possible rounding errors.
1497+ */
1498+ tmp = (u64)m1 * m2_int * refclk +
1499+ (((u64)m1 * m2_frac * refclk) >> 22);
1500+ tmp = div_u64(tmp, 5 * div1 * div2);
1501+
1502+ return tmp;
1503+}
1504+
14301505 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
14311506 {
14321507 int dotclock;
@@ -1467,8 +1542,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, · 34 unmodified lines
14671542 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
14681543 pll_id);
14691544 } else {
1470− /* FIXME - Add for MG PLL */
1471− WARN(1, "MG PLL clock_get code not implemented yet\n");
1545+ if (pll_id == DPLL_ID_ICL_TBTPLL)
1546+ link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1547+ else
1548+ link_clock = icl_calc_mg_pll_link(dev_priv, port);
14721549 }
14731550
14741551 pipe_config->port_clock = link_clock;
@@ -2468,7 +2545,128 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, · 993 unmodified lines
24682545 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
24692546 }
24702547
2471−static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
2548+static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2549+ int link_clock,
2550+ u32 level)
2551+{
2552+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2553+ enum port port = encoder->port;
2554+ const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2555+ u32 n_entries, val;
2556+ int ln;
2557+
2558+ n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2559+ ddi_translations = icl_mg_phy_ddi_translations;
2560+ /* The table does not have values for level 3 and level 9. */
2561+ if (level >= n_entries || level == 3 || level == 9) {
2562+ DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2563+ level, n_entries - 2);
2564+ level = n_entries - 2;
2565+ }
2566+
2567+ /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2568+ for (ln = 0; ln < 2; ln++) {
2569+ val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2570+ val &= ~CRI_USE_FS32;
2571+ I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2572+
2573+ val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2574+ val &= ~CRI_USE_FS32;
2575+ I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2576+ }
2577+
2578+ /* Program MG_TX_SWINGCTRL with values from vswing table */
2579+ for (ln = 0; ln < 2; ln++) {
2580+ val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2581+ val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2582+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2583+ ddi_translations[level].cri_txdeemph_override_17_12);
2584+ I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2585+
2586+ val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2587+ val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2588+ val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2589+ ddi_translations[level].cri_txdeemph_override_17_12);
2590+ I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2591+ }
2592+
2593+ /* Program MG_TX_DRVCTRL with values from vswing table */
2594+ for (ln = 0; ln < 2; ln++) {
2595+ val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2596+ val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2597+ CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2598+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2599+ ddi_translations[level].cri_txdeemph_override_5_0) |
2600+ CRI_TXDEEMPH_OVERRIDE_11_6(
2601+ ddi_translations[level].cri_txdeemph_override_11_6) |
2602+ CRI_TXDEEMPH_OVERRIDE_EN;
2603+ I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2604+
2605+ val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2606+ val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2607+ CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2608+ val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2609+ ddi_translations[level].cri_txdeemph_override_5_0) |
2610+ CRI_TXDEEMPH_OVERRIDE_11_6(
2611+ ddi_translations[level].cri_txdeemph_override_11_6) |
2612+ CRI_TXDEEMPH_OVERRIDE_EN;
2613+ I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2614+
2615+ /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2616+ }
2617+
2618+ /*
2619+ * Program MG_CLKHUB<LN, port being used> with value from frequency table
2620+ * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2621+ * values from table for which TX1 and TX2 enabled.
2622+ */
2623+ for (ln = 0; ln < 2; ln++) {
2624+ val = I915_READ(MG_CLKHUB(port, ln));
2625+ if (link_clock < 300000)
2626+ val |= CFG_LOW_RATE_LKREN_EN;
2627+ else
2628+ val &= ~CFG_LOW_RATE_LKREN_EN;
2629+ I915_WRITE(MG_CLKHUB(port, ln), val);
2630+ }
2631+
2632+ /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2633+ for (ln = 0; ln < 2; ln++) {
2634+ val = I915_READ(MG_TX1_DCC(port, ln));
2635+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2636+ if (link_clock <= 500000) {
2637+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2638+ } else {
2639+ val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2640+ CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2641+ }
2642+ I915_WRITE(MG_TX1_DCC(port, ln), val);
2643+
2644+ val = I915_READ(MG_TX2_DCC(port, ln));
2645+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2646+ if (link_clock <= 500000) {
2647+ val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2648+ } else {
2649+ val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2650+ CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2651+ }
2652+ I915_WRITE(MG_TX2_DCC(port, ln), val);
2653+ }
2654+
2655+ /* Program MG_TX_PISO_READLOAD with values from vswing table */
2656+ for (ln = 0; ln < 2; ln++) {
2657+ val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2658+ val |= CRI_CALCINIT;
2659+ I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2660+
2661+ val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2662+ val |= CRI_CALCINIT;
2663+ I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2664+ }
2665+}
2666+
2667+static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2668+ int link_clock,
2669+ u32 level,
24722670 enum intel_output_type type)
24732671 {
24742672 enum port port = encoder->port;
@@ -2476,8 +2674,7 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level, · 1 unmodified line
24762674 if (port == PORT_A || port == PORT_B)
24772675 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
24782676 else
2479− /* Not Implemented Yet */
2480− WARN_ON(1);
2677+ icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
24812678 }
24822679
24832680 static uint32_t translate_signal_level(int signal_levels)
@@ -2512,7 +2709,8 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp) · 28 unmodified lines
25122709 int level = intel_ddi_dp_level(intel_dp);
25132710
25142711 if (IS_ICELAKE(dev_priv))
2515− icl_ddi_vswing_sequence(encoder, level, encoder->type);
2712+ icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2713+ level, encoder->type);
25162714 else if (IS_CANNONLAKE(dev_priv))
25172715 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
25182716 else
@@ -2692,8 +2890,12 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, · 173 unmodified lines
26922890
26932891 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
26942892
2893+ icl_program_mg_dp_mode(intel_dp);
2894+ icl_disable_phy_clock_gating(dig_port);
2895+
26952896 if (IS_ICELAKE(dev_priv))
2696− icl_ddi_vswing_sequence(encoder, level, encoder->type);
2897+ icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2898+ level, encoder->type);
26972899 else if (IS_CANNONLAKE(dev_priv))
26982900 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
26992901 else if (IS_GEN9_LP(dev_priv))
@@ -2708,7 +2910,10 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, · 8 unmodified lines
27082910 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
27092911 intel_dp_stop_link_train(intel_dp);
27102912
2711− intel_ddi_enable_pipe_clock(crtc_state);
2913+ icl_enable_phy_clock_gating(dig_port);
2914+
2915+ if (!is_mst)
2916+ intel_ddi_enable_pipe_clock(crtc_state);
27122917 }
27132918
27142919 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
@@ -2728,7 +2933,8 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, · 13 unmodified lines
27282933 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
27292934
27302935 if (IS_ICELAKE(dev_priv))
2731− icl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2936+ icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2937+ level, INTEL_OUTPUT_HDMI);
27322938 else if (IS_CANNONLAKE(dev_priv))
27332939 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
27342940 else if (IS_GEN9_LP(dev_priv))
@@ -2810,14 +3016,14 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, · 75 unmodified lines
28103016 bool is_mst = intel_crtc_has_type(old_crtc_state,
28113017 INTEL_OUTPUT_DP_MST);
28123018
2813− intel_ddi_disable_pipe_clock(old_crtc_state);
2814−
2815− /*
2816− * Power down sink before disabling the port, otherwise we end
2817− * up getting interrupts from the sink on detecting link loss.
2818− */
2819− if (!is_mst)
3019+ if (!is_mst) {
3020+ intel_ddi_disable_pipe_clock(old_crtc_state);
3021+ /*
3022+ * Power down sink before disabling the port, otherwise we end
3023+ * up getting interrupts from the sink on detecting link loss.
3024+ */
28203025 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3026+ }
28213027
28223028 intel_disable_ddi_buf(encoder);
28233029
drivers/gpu/drm/i915/intel_device_info.h+1−1
@@ -103,9 +103,9 @@ enum intel_platform { · 102 unmodified lines
103103 func(has_psr); \
104104 func(has_rc6); \
105105 func(has_rc6p); \
106− func(has_resource_streamer); \
107106 func(has_runtime_pm); \
108107 func(has_snoop); \
108+ func(has_coherent_ggtt); \
109109 func(unfenced_needs_alignment); \
110110 func(cursor_needs_physical); \
111111 func(hws_needs_physical); \
drivers/gpu/drm/i915/intel_display.c+115−57
@@ -2474,6 +2474,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) · 2473 unmodified lines
24742474 }
24752475 }
24762476
2477+bool is_ccs_modifier(u64 modifier)
2478+{
2479+ return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2480+ modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2481+}
2482+
24772483 static int
24782484 intel_fill_fb_info(struct drm_i915_private *dev_priv,
24792485 struct drm_framebuffer *fb)
@@ -2504,8 +2510,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, · 24 unmodified lines
25042510 return ret;
25052511 }
25062512
2507− if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2508− fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2513+ if (is_ccs_modifier(fb->modifier) && i == 1) {
25092514 int hsub = fb->format->hsub;
25102515 int vsub = fb->format->vsub;
25112516 int tile_width, tile_height;
@@ -3055,8 +3060,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state, · 543 unmodified lines
30553060 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
30563061 * they match with the main surface x/y offsets.
30573062 */
3058− if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3059− fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3063+ if (is_ccs_modifier(fb->modifier)) {
30603064 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
30613065 if (offset == 0)
30623066 break;
@@ -3190,8 +3194,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, · 127 unmodified lines
31903194 ret = skl_check_nv12_aux_surface(plane_state);
31913195 if (ret)
31923196 return ret;
3193− } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3194− fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3197+ } else if (is_ccs_modifier(fb->modifier)) {
31953198 ret = skl_check_ccs_aux_surface(plane_state);
31963199 if (ret)
31973200 return ret;
@@ -3552,11 +3555,11 @@ static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) · 354 unmodified lines
35523555 case I915_FORMAT_MOD_Y_TILED:
35533556 return PLANE_CTL_TILED_Y;
35543557 case I915_FORMAT_MOD_Y_TILED_CCS:
3555− return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3558+ return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
35563559 case I915_FORMAT_MOD_Yf_TILED:
35573560 return PLANE_CTL_TILED_YF;
35583561 case I915_FORMAT_MOD_Yf_TILED_CCS:
3559− return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3562+ return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
35603563 default:
35613564 MISSING_CASE(fb_modifier);
35623565 }
@@ -5079,10 +5082,14 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) · 1516 unmodified lines
50795082 mutex_lock(&dev_priv->pcu_lock);
50805083 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
50815084 mutex_unlock(&dev_priv->pcu_lock);
5082− /* wait for pcode to finish disabling IPS, which may take up to 42ms */
5085+ /*
5086+ * Wait for PCODE to finish disabling IPS. The BSpec specified
5087+ * 42ms timeout value leads to occasional timeouts so use 100ms
5088+ * instead.
5089+ */
50835090 if (intel_wait_for_register(dev_priv,
50845091 IPS_CTL, IPS_ENABLE, 0,
5085− 42))
5092+ 100))
50865093 DRM_ERROR("Timed out waiting for IPS disable\n");
50875094 } else {
50885095 I915_WRITE(IPS_CTL, 0);
@@ -8799,13 +8806,13 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, · 3710 unmodified lines
87998806 fb->modifier = I915_FORMAT_MOD_X_TILED;
88008807 break;
88018808 case PLANE_CTL_TILED_Y:
8802− if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8809+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
88038810 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
88048811 else
88058812 fb->modifier = I915_FORMAT_MOD_Y_TILED;
88068813 break;
88078814 case PLANE_CTL_TILED_YF:
8808− if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8815+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
88098816 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
88108817 else
88118818 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
@@ -8974,7 +8981,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) · 162 unmodified lines
89748981 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
89758982 pipe_name(crtc->pipe));
89768983
8977− I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8984+ I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
89788985 "Display power well on\n");
89798986 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
89808987 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
@@ -9691,8 +9698,7 @@ static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) · 710 unmodified lines
96919698 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
96929699 }
96939700
9694−static int i845_check_cursor(struct intel_plane *plane,
9695− struct intel_crtc_state *crtc_state,
9701+static int i845_check_cursor(struct intel_crtc_state *crtc_state,
96969702 struct intel_plane_state *plane_state)
96979703 {
96989704 const struct drm_framebuffer *fb = plane_state->base.fb;
@@ -9882,10 +9888,10 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) · 183 unmodified lines
98829888 return true;
98839889 }
98849890
9885−static int i9xx_check_cursor(struct intel_plane *plane,
9886− struct intel_crtc_state *crtc_state,
9891+static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
98879892 struct intel_plane_state *plane_state)
98889893 {
9894+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
98899895 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98909896 const struct drm_framebuffer *fb = plane_state->base.fb;
98919897 enum pipe pipe = plane->pipe;
@@ -12739,7 +12745,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 2847 unmodified lines
1273912745 * down.
1274012746 */
1274112747 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
12742− schedule_work(&state->commit_work);
12748+ queue_work(system_highpri_wq, &state->commit_work);
1274312749 }
1274412750
1274512751 static void intel_atomic_commit_work(struct work_struct *work)
@@ -12969,8 +12975,11 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state) · 223 unmodified lines
1296912975 INTEL_INFO(dev_priv)->cursor_needs_physical) {
1297012976 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1297112977 const int align = intel_cursor_alignment(dev_priv);
12978+ int err;
1297212979
12973− return i915_gem_object_attach_phys(obj, align);
12980+ err = i915_gem_object_attach_phys(obj, align);
12981+ if (err)
12982+ return err;
1297412983 }
1297512984
1297612985 vma = intel_pin_and_fence_fb_obj(fb,
@@ -13189,10 +13198,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, · 212 unmodified lines
1318913198 }
1319013199
1319113200 static int
13192−intel_check_primary_plane(struct intel_plane *plane,
13193− struct intel_crtc_state *crtc_state,
13201+intel_check_primary_plane(struct intel_crtc_state *crtc_state,
1319413202 struct intel_plane_state *state)
1319513203 {
13204+ struct intel_plane *plane = to_intel_plane(state->base.plane);
1319613205 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1319713206 struct drm_crtc *crtc = state->base.crtc;
1319813207 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
@@ -13400,8 +13409,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, · 201 unmodified lines
1340013409 case DRM_FORMAT_XBGR8888:
1340113410 case DRM_FORMAT_ARGB8888:
1340213411 case DRM_FORMAT_ABGR8888:
13403− if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13404− modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13412+ if (is_ccs_modifier(modifier))
1340513413 return true;
1340613414 /* fall through */
1340713415 case DRM_FORMAT_RGB565:
@@ -13620,24 +13628,22 @@ static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, · 212 unmodified lines
1362013628 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1362113629 enum pipe pipe, enum plane_id plane_id)
1362213630 {
13623− if (plane_id == PLANE_PRIMARY) {
13624− if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13625− return false;
13626− else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
13627− !IS_GEMINILAKE(dev_priv))
13628− return false;
13629− } else if (plane_id >= PLANE_SPRITE0) {
13630− if (plane_id == PLANE_CURSOR)
13631− return false;
13632− if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
13633− if (plane_id != PLANE_SPRITE0)
13634− return false;
13635− } else {
13636− if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
13637− IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13638− return false;
13639− }
13640− }
13631+ /*
13632+ * FIXME: ICL requires two hardware planes for scanning out NV12
13633+ * framebuffers. Do not advertize support until this is implemented.
13634+ */
13635+ if (INTEL_GEN(dev_priv) >= 11)
13636+ return false;
13637+
13638+ if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13639+ return false;
13640+
13641+ if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
13642+ return false;
13643+
13644+ if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
13645+ return false;
13646+
1364113647 return true;
1364213648 }
1364313649
@@ -14131,6 +14137,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) · 487 unmodified lines
1413114137
1413214138 intel_pps_init(dev_priv);
1413314139
14140+ if (INTEL_INFO(dev_priv)->num_pipes == 0)
14141+ return;
14142+
1413414143 /*
1413514144 * intel_edp_init_connector() depends on this completing first, to
1413614145 * prevent the registeration of both eDP and LVDS and the incorrect
@@ -14547,7 +14556,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, · 410 unmodified lines
1454714556 break;
1454814557 case DRM_FORMAT_NV12:
1454914558 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14550− IS_BROXTON(dev_priv)) {
14559+ IS_BROXTON(dev_priv) || INTEL_GEN(dev_priv) >= 11) {
1455114560 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
1455214561 drm_get_format_name(mode_cmd->pixel_format,
1455314562 &format_name));
@@ -14594,8 +14603,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, · 40 unmodified lines
1459414603 * potential runtime errors at plane configuration time.
1459514604 */
1459614605 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14597− (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14598− fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14606+ is_ccs_modifier(fb->modifier))
1459914607 stride_alignment *= 4;
1460014608
1460114609 if (fb->pitches[i] & (stride_alignment - 1)) {
@@ -15131,12 +15139,61 @@ static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) · 529 unmodified lines
1513115139 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
1513215140 }
1513315141
15142+static int intel_initial_commit(struct drm_device *dev)
15143+{
15144+ struct drm_atomic_state *state = NULL;
15145+ struct drm_modeset_acquire_ctx ctx;
15146+ struct drm_crtc *crtc;
15147+ struct drm_crtc_state *crtc_state;
15148+ int ret = 0;
15149+
15150+ state = drm_atomic_state_alloc(dev);
15151+ if (!state)
15152+ return -ENOMEM;
15153+
15154+ drm_modeset_acquire_init(&ctx, 0);
15155+
15156+retry:
15157+ state->acquire_ctx = &ctx;
15158+
15159+ drm_for_each_crtc(crtc, dev) {
15160+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
15161+ if (IS_ERR(crtc_state)) {
15162+ ret = PTR_ERR(crtc_state);
15163+ goto out;
15164+ }
15165+
15166+ if (crtc_state->active) {
15167+ ret = drm_atomic_add_affected_planes(state, crtc);
15168+ if (ret)
15169+ goto out;
15170+ }
15171+ }
15172+
15173+ ret = drm_atomic_commit(state);
15174+
15175+out:
15176+ if (ret == -EDEADLK) {
15177+ drm_atomic_state_clear(state);
15178+ drm_modeset_backoff(&ctx);
15179+ goto retry;
15180+ }
15181+
15182+ drm_atomic_state_put(state);
15183+
15184+ drm_modeset_drop_locks(&ctx);
15185+ drm_modeset_acquire_fini(&ctx);
15186+
15187+ return ret;
15188+}
15189+
1513415190 int intel_modeset_init(struct drm_device *dev)
1513515191 {
1513615192 struct drm_i915_private *dev_priv = to_i915(dev);
1513715193 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1513815194 enum pipe pipe;
1513915195 struct intel_crtc *crtc;
15196+ int ret;
1514015197
1514115198 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
1514215199
@@ -15160,9 +15217,6 @@ int intel_modeset_init(struct drm_device *dev) · 17 unmodified lines
1516015217
1516115218 intel_init_pm(dev_priv);
1516215219
15163− if (INTEL_INFO(dev_priv)->num_pipes == 0)
15164− return 0;
15165−
1516615220 /*
1516715221 * There may be no VBT; and if the BIOS enabled SSC we can
1516815222 * just keep using it to avoid unnecessary flicker. Whereas if the
@@ -15211,8 +15265,6 @@ int intel_modeset_init(struct drm_device *dev) · 42 unmodified lines
1521115265 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
1521215266
1521315267 for_each_pipe(dev_priv, pipe) {
15214− int ret;
15215−
1521615268 ret = intel_crtc_init(dev_priv, pipe);
1521715269 if (ret) {
1521815270 drm_mode_config_cleanup(dev);
@@ -15268,6 +15320,16 @@ int intel_modeset_init(struct drm_device *dev) · 49 unmodified lines
1526815320 if (!HAS_GMCH_DISPLAY(dev_priv))
1526915321 sanitize_watermarks(dev);
1527015322
15323+ /*
15324+ * Force all active planes to recompute their states. So that on
15325+ * mode_setcrtc after probe, all the intel_plane_state variables
15326+ * are already calculated and there is no assert_plane warnings
15327+ * during bootup.
15328+ */
15329+ ret = intel_initial_commit(dev);
15330+ if (ret)
15331+ DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15332+
1527115333 return 0;
1527215334 }
1527315335
@@ -15792,6 +15854,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 518 unmodified lines
1579215854 struct intel_encoder *encoder;
1579315855 int i;
1579415856
15857+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
15858+
1579515859 intel_early_display_was(dev_priv);
1579615860 intel_modeset_readout_hw_state(dev);
1579715861
@@ -15846,9 +15910,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 48 unmodified lines
1584615910 if (WARN_ON(put_domains))
1584715911 modeset_put_power_domains(dev_priv, put_domains);
1584815912 }
15849− intel_display_set_init_power(dev_priv, false);
1585015913
15851− intel_power_domains_verify_state(dev_priv);
15914+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1585215915
1585315916 intel_fbc_init_pipe_state(dev_priv);
1585415917 }
@@ -15937,8 +16000,6 @@ void intel_modeset_cleanup(struct drm_device *dev) · 82 unmodified lines
1593716000 flush_work(&dev_priv->atomic_helper.free_work);
1593816001 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
1593916002
15940− intel_disable_gt_powersave(dev_priv);
15941−
1594216003 /*
1594316004 * Interrupts and polling as the first thing to avoid creating havoc.
1594416005 * Too much stuff here (turning of connectors, ...) would
@@ -15966,8 +16027,6 @@ void intel_modeset_cleanup(struct drm_device *dev) · 21 unmodified lines
1596616027
1596716028 intel_cleanup_overlay(dev_priv);
1596816029
15969− intel_cleanup_gt_powersave(dev_priv);
15970−
1597116030 intel_teardown_gmbus(dev_priv);
1597216031
1597316032 destroy_workqueue(dev_priv->modeset_wq);
@@ -16075,8 +16134,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) · 101 unmodified lines
1607516134 return NULL;
1607616135
1607716136 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16078− error->power_well_driver =
16079− I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
16137+ error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
1608016138
1608116139 for_each_pipe(dev_priv, i) {
1608216140 error->pipe[i].power_domain_on =
drivers/gpu/drm/i915/intel_display.h+26−2
@@ -25,6 +25,22 @@ · 24 unmodified lines
2525 #ifndef _INTEL_DISPLAY_H_
2626 #define _INTEL_DISPLAY_H_
2727
28+enum i915_gpio {
29+ GPIOA,
30+ GPIOB,
31+ GPIOC,
32+ GPIOD,
33+ GPIOE,
34+ GPIOF,
35+ GPIOG,
36+ GPIOH,
37+ __GPIOI_UNUSED,
38+ GPIOJ,
39+ GPIOK,
40+ GPIOL,
41+ GPIOM,
42+};
43+
2844 enum pipe {
2945 INVALID_PIPE = -1,
3046
@@ -161,6 +177,13 @@ enum tc_port { · 130 unmodified lines
161177 I915_MAX_TC_PORTS
162178 };
163179
180+enum tc_port_type {
181+ TC_PORT_UNKNOWN = 0,
182+ TC_PORT_TYPEC,
183+ TC_PORT_TBT,
184+ TC_PORT_LEGACY,
185+};
186+
164187 enum dpio_channel {
165188 DPIO_CH0,
166189 DPIO_CH1
@@ -346,11 +369,11 @@ struct intel_link_m_n { · 179 unmodified lines
346369
347370 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
348371 for_each_power_well(__dev_priv, __power_well) \
349− for_each_if((__power_well)->domains & (__domain_mask))
372+ for_each_if((__power_well)->desc->domains & (__domain_mask))
350373
351374 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
352375 for_each_power_well_rev(__dev_priv, __power_well) \
353− for_each_if((__power_well)->domains & (__domain_mask))
376+ for_each_if((__power_well)->desc->domains & (__domain_mask))
354377
355378 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
356379 for ((__i) = 0; \
@@ -382,4 +405,5 @@ void intel_link_compute_m_n(int bpp, int nlanes, · 25 unmodified lines
382405 struct intel_link_m_n *m_n,
383406 bool reduce_m_n);
384407
408+bool is_ccs_modifier(u64 modifier);
385409 #endif
drivers/gpu/drm/i915/intel_dp.c+451−83
@@ -107,13 +107,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) · 106 unmodified lines
107107 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
108108 }
109109
110−static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
111−{
112− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113−
114− return intel_dig_port->base.base.dev;
115−}
116−
117110 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
118111 {
119112 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
@@ -176,14 +169,45 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp) · 56 unmodified lines
176169 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
177170 }
178171
172+static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
173+{
174+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
175+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
176+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
177+ u32 lane_info;
178+
179+ if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
180+ return 4;
181+
182+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
183+ DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
184+ DP_LANE_ASSIGNMENT_SHIFT(tc_port);
185+
186+ switch (lane_info) {
187+ default:
188+ MISSING_CASE(lane_info);
189+ case 1:
190+ case 2:
191+ case 4:
192+ case 8:
193+ return 1;
194+ case 3:
195+ case 12:
196+ return 2;
197+ case 15:
198+ return 4;
199+ }
200+}
201+
179202 /* Theoretical max between source and sink */
180203 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
181204 {
182205 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
183206 int source_max = intel_dig_port->max_lanes;
184207 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
208+ int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
185209
186− return min(source_max, sink_max);
210+ return min3(source_max, sink_max, fia_max);
187211 }
188212
189213 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
@@ -198,6 +222,138 @@ intel_dp_link_required(int pixel_clock, int bpp) · 8 unmodified lines
198222 return DIV_ROUND_UP(pixel_clock * bpp, 8);
199223 }
200224
225+void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
226+{
227+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
228+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
229+ enum port port = intel_dig_port->base.port;
230+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
231+ u32 ln0, ln1, lane_info;
232+
233+ if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
234+ return;
235+
236+ ln0 = I915_READ(MG_DP_MODE(port, 0));
237+ ln1 = I915_READ(MG_DP_MODE(port, 1));
238+
239+ switch (intel_dig_port->tc_type) {
240+ case TC_PORT_TYPEC:
241+ ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
242+ ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
243+
244+ lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
245+ DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
246+ DP_LANE_ASSIGNMENT_SHIFT(tc_port);
247+
248+ switch (lane_info) {
249+ case 0x1:
250+ case 0x4:
251+ break;
252+ case 0x2:
253+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
254+ break;
255+ case 0x3:
256+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
257+ MG_DP_MODE_CFG_DP_X2_MODE;
258+ break;
259+ case 0x8:
260+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
261+ break;
262+ case 0xC:
263+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
264+ MG_DP_MODE_CFG_DP_X2_MODE;
265+ break;
266+ case 0xF:
267+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
268+ MG_DP_MODE_CFG_DP_X2_MODE;
269+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
270+ MG_DP_MODE_CFG_DP_X2_MODE;
271+ break;
272+ default:
273+ MISSING_CASE(lane_info);
274+ }
275+ break;
276+
277+ case TC_PORT_LEGACY:
278+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
279+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
280+ break;
281+
282+ default:
283+ MISSING_CASE(intel_dig_port->tc_type);
284+ return;
285+ }
286+
287+ I915_WRITE(MG_DP_MODE(port, 0), ln0);
288+ I915_WRITE(MG_DP_MODE(port, 1), ln1);
289+}
290+
291+void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
292+{
293+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
294+ enum port port = dig_port->base.port;
295+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
296+ i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
297+ u32 val;
298+ int i;
299+
300+ if (tc_port == PORT_TC_NONE)
301+ return;
302+
303+ for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
304+ val = I915_READ(mg_regs[i]);
305+ val |= MG_DP_MODE_CFG_TR2PWR_GATING |
306+ MG_DP_MODE_CFG_TRPWR_GATING |
307+ MG_DP_MODE_CFG_CLNPWR_GATING |
308+ MG_DP_MODE_CFG_DIGPWR_GATING |
309+ MG_DP_MODE_CFG_GAONPWR_GATING;
310+ I915_WRITE(mg_regs[i], val);
311+ }
312+
313+ val = I915_READ(MG_MISC_SUS0(tc_port));
314+ val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
315+ MG_MISC_SUS0_CFG_TR2PWR_GATING |
316+ MG_MISC_SUS0_CFG_CL2PWR_GATING |
317+ MG_MISC_SUS0_CFG_GAONPWR_GATING |
318+ MG_MISC_SUS0_CFG_TRPWR_GATING |
319+ MG_MISC_SUS0_CFG_CL1PWR_GATING |
320+ MG_MISC_SUS0_CFG_DGPWR_GATING;
321+ I915_WRITE(MG_MISC_SUS0(tc_port), val);
322+}
323+
324+void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
325+{
326+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
327+ enum port port = dig_port->base.port;
328+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
329+ i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
330+ u32 val;
331+ int i;
332+
333+ if (tc_port == PORT_TC_NONE)
334+ return;
335+
336+ for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
337+ val = I915_READ(mg_regs[i]);
338+ val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
339+ MG_DP_MODE_CFG_TRPWR_GATING |
340+ MG_DP_MODE_CFG_CLNPWR_GATING |
341+ MG_DP_MODE_CFG_DIGPWR_GATING |
342+ MG_DP_MODE_CFG_GAONPWR_GATING);
343+ I915_WRITE(mg_regs[i], val);
344+ }
345+
346+ val = I915_READ(MG_MISC_SUS0(tc_port));
347+ val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
348+ MG_MISC_SUS0_CFG_TR2PWR_GATING |
349+ MG_MISC_SUS0_CFG_CL2PWR_GATING |
350+ MG_MISC_SUS0_CFG_GAONPWR_GATING |
351+ MG_MISC_SUS0_CFG_TRPWR_GATING |
352+ MG_MISC_SUS0_CFG_CL1PWR_GATING |
353+ MG_MISC_SUS0_CFG_DGPWR_GATING);
354+ I915_WRITE(MG_MISC_SUS0(tc_port), val);
355+}
356+
201357 int
202358 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
203359 {
@@ -498,7 +654,7 @@ intel_dp_pps_init(struct intel_dp *intel_dp); · 294 unmodified lines
498654
499655 static void pps_lock(struct intel_dp *intel_dp)
500656 {
501− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
657+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
502658
503659 /*
504660 * See intel_power_sequencer_reset() why we need
@@ -511,7 +667,7 @@ static void pps_lock(struct intel_dp *intel_dp) · 6 unmodified lines
511667
512668 static void pps_unlock(struct intel_dp *intel_dp)
513669 {
514− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
670+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
515671
516672 mutex_unlock(&dev_priv->pps_mutex);
517673
@@ -521,7 +677,7 @@ static void pps_unlock(struct intel_dp *intel_dp) · 3 unmodified lines
521677 static void
522678 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
523679 {
524− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
680+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
525681 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
526682 enum pipe pipe = intel_dp->pps_pipe;
527683 bool pll_enabled, release_cl_override = false;
@@ -626,7 +782,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) · 98 unmodified lines
626782 static enum pipe
627783 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
628784 {
629− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
785+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
630786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
631787 enum pipe pipe;
632788
@@ -673,7 +829,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) · 40 unmodified lines
673829 static int
674830 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
675831 {
676− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
832+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
677833 int backlight_controller = dev_priv->vbt.backlight.controller;
678834
679835 lockdep_assert_held(&dev_priv->pps_mutex);
@@ -742,7 +898,7 @@ vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, · 62 unmodified lines
742898 static void
743899 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
744900 {
745− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
901+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
746902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
747903 enum port port = intel_dig_port->base.port;
748904
@@ -819,7 +975,7 @@ struct pps_registers { · 70 unmodified lines
819975 static void intel_pps_get_registers(struct intel_dp *intel_dp,
820976 struct pps_registers *regs)
821977 {
822− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
978+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
823979 int pps_idx = 0;
824980
825981 memset(regs, 0, sizeof(*regs));
@@ -865,7 +1021,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code, · 39 unmodified lines
8651021 {
8661022 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
8671023 edp_notifier);
868− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1024+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8691025
8701026 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
8711027 return 0;
@@ -895,7 +1051,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code, · 23 unmodified lines
8951051
8961052 static bool edp_have_panel_power(struct intel_dp *intel_dp)
8971053 {
898− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1054+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8991055
9001056 lockdep_assert_held(&dev_priv->pps_mutex);
9011057
@@ -908,7 +1064,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp) · 6 unmodified lines
9081064
9091065 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
9101066 {
911− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1067+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9121068
9131069 lockdep_assert_held(&dev_priv->pps_mutex);
9141070
@@ -922,7 +1078,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp) · 7 unmodified lines
9221078 static void
9231079 intel_dp_check_edp(struct intel_dp *intel_dp)
9241080 {
925− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1081+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9261082
9271083 if (!intel_dp_is_edp(intel_dp))
9281084 return;
@@ -938,7 +1094,7 @@ intel_dp_check_edp(struct intel_dp *intel_dp) · 9 unmodified lines
9381094 static uint32_t
9391095 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
9401096 {
941− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1097+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9421098 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
9431099 uint32_t status;
9441100 bool done;
@@ -955,7 +1111,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) · 10 unmodified lines
9551111
9561112 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
9571113 {
958− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1114+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9591115
9601116 if (index)
9611117 return 0;
@@ -969,7 +1125,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) · 7 unmodified lines
9691125
9701126 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
9711127 {
972− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1128+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9731129
9741130 if (index)
9751131 return 0;
@@ -987,7 +1143,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) · 11 unmodified lines
9871143
9881144 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
9891145 {
990− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1146+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9911147
9921148 if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
9931149 /* Workaround for non-ULT HSW */
@@ -1045,15 +1201,23 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, · 51 unmodified lines
10451201 int send_bytes,
10461202 uint32_t unused)
10471203 {
1048− return DP_AUX_CH_CTL_SEND_BUSY |
1049− DP_AUX_CH_CTL_DONE |
1050− DP_AUX_CH_CTL_INTERRUPT |
1051− DP_AUX_CH_CTL_TIME_OUT_ERROR |
1052− DP_AUX_CH_CTL_TIME_OUT_MAX |
1053− DP_AUX_CH_CTL_RECEIVE_ERROR |
1054− (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1055− DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1056− DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1204+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205+ uint32_t ret;
1206+
1207+ ret = DP_AUX_CH_CTL_SEND_BUSY |
1208+ DP_AUX_CH_CTL_DONE |
1209+ DP_AUX_CH_CTL_INTERRUPT |
1210+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
1211+ DP_AUX_CH_CTL_TIME_OUT_MAX |
1212+ DP_AUX_CH_CTL_RECEIVE_ERROR |
1213+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1214+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1215+ DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1216+
1217+ if (intel_dig_port->tc_type == TC_PORT_TBT)
1218+ ret |= DP_AUX_CH_CTL_TBT_IO;
1219+
1220+ return ret;
10571221 }
10581222
10591223 static int
@@ -1381,7 +1545,7 @@ intel_aux_power_domain(struct intel_dp *intel_dp) · 321 unmodified lines
13811545
13821546 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
13831547 {
1384− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1548+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
13851549 enum aux_ch aux_ch = intel_dp->aux_ch;
13861550
13871551 switch (aux_ch) {
@@ -1397,7 +1561,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) · 9 unmodified lines
13971561
13981562 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
13991563 {
1400− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1564+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
14011565 enum aux_ch aux_ch = intel_dp->aux_ch;
14021566
14031567 switch (aux_ch) {
@@ -1413,7 +1577,7 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) · 9 unmodified lines
14131577
14141578 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
14151579 {
1416− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1580+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
14171581 enum aux_ch aux_ch = intel_dp->aux_ch;
14181582
14191583 switch (aux_ch) {
@@ -1431,7 +1595,7 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) · 11 unmodified lines
14311595
14321596 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
14331597 {
1434− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1598+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
14351599 enum aux_ch aux_ch = intel_dp->aux_ch;
14361600
14371601 switch (aux_ch) {
@@ -1449,7 +1613,7 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) · 11 unmodified lines
14491613
14501614 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
14511615 {
1452− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1616+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
14531617 enum aux_ch aux_ch = intel_dp->aux_ch;
14541618
14551619 switch (aux_ch) {
@@ -1468,7 +1632,7 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) · 12 unmodified lines
14681632
14691633 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
14701634 {
1471− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1635+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
14721636 enum aux_ch aux_ch = intel_dp->aux_ch;
14731637
14741638 switch (aux_ch) {
@@ -1494,7 +1658,7 @@ intel_dp_aux_fini(struct intel_dp *intel_dp) · 19 unmodified lines
14941658 static void
14951659 intel_dp_aux_init(struct intel_dp *intel_dp)
14961660 {
1497− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1661+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
14981662 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
14991663
15001664 intel_dp->aux_ch = intel_aux_ch(intel_dp);
@@ -1662,7 +1826,7 @@ struct link_config_limits { · 161 unmodified lines
16621826 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
16631827 struct intel_crtc_state *pipe_config)
16641828 {
1665− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1829+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
16661830 struct intel_connector *intel_connector = intel_dp->attached_connector;
16671831 int bpp, bpc;
16681832
@@ -2030,7 +2194,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, · 361 unmodified lines
20302194 u32 mask,
20312195 u32 value)
20322196 {
2033− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2197+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
20342198 i915_reg_t pp_stat_reg, pp_ctrl_reg;
20352199
20362200 lockdep_assert_held(&dev_priv->pps_mutex);
@@ -2106,7 +2270,7 @@ static void edp_wait_backlight_off(struct intel_dp *intel_dp) · 69 unmodified lines
21062270
21072271 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
21082272 {
2109− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2273+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
21102274 u32 control;
21112275
21122276 lockdep_assert_held(&dev_priv->pps_mutex);
@@ -2127,7 +2291,7 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) · 14 unmodified lines
21272291 */
21282292 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
21292293 {
2130− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2294+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
21312295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
21322296 u32 pp;
21332297 i915_reg_t pp_stat_reg, pp_ctrl_reg;
@@ -2198,7 +2362,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) · 64 unmodified lines
21982362
21992363 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
22002364 {
2201− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2365+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
22022366 struct intel_digital_port *intel_dig_port =
22032367 dp_to_dig_port(intel_dp);
22042368 u32 pp;
@@ -2264,7 +2428,7 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) · 59 unmodified lines
22642428 */
22652429 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
22662430 {
2267− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2431+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
22682432
22692433 lockdep_assert_held(&dev_priv->pps_mutex);
22702434
@@ -2284,7 +2448,7 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) · 13 unmodified lines
22842448
22852449 static void edp_panel_on(struct intel_dp *intel_dp)
22862450 {
2287− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2451+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
22882452 u32 pp;
22892453 i915_reg_t pp_ctrl_reg;
22902454
@@ -2342,7 +2506,7 @@ void intel_edp_panel_on(struct intel_dp *intel_dp) · 51 unmodified lines
23422506
23432507 static void edp_panel_off(struct intel_dp *intel_dp)
23442508 {
2345− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2509+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
23462510 u32 pp;
23472511 i915_reg_t pp_ctrl_reg;
23482512
@@ -2390,7 +2554,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp) · 41 unmodified lines
23902554 /* Enable backlight in the panel power control. */
23912555 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
23922556 {
2393− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2557+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
23942558 u32 pp;
23952559 i915_reg_t pp_ctrl_reg;
23962560
@@ -2433,7 +2597,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, · 36 unmodified lines
24332597 /* Disable backlight in the panel power control. */
24342598 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
24352599 {
2436− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2600+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
24372601 u32 pp;
24382602 i915_reg_t pp_ctrl_reg;
24392603
@@ -2864,7 +3028,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, · 424 unmodified lines
28643028 uint32_t *DP,
28653029 uint8_t dp_train_pat)
28663030 {
2867− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3031+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
28683032 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
28693033 enum port port = intel_dig_port->base.port;
28703034 uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
@@ -2946,7 +3110,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, · 75 unmodified lines
29463110 static void intel_dp_enable_port(struct intel_dp *intel_dp,
29473111 const struct intel_crtc_state *old_crtc_state)
29483112 {
2949− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3113+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
29503114
29513115 /* enable with pattern 1 (as per spec) */
29523116
@@ -3203,7 +3367,7 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ · 250 unmodified lines
32033367 uint8_t
32043368 intel_dp_voltage_max(struct intel_dp *intel_dp)
32053369 {
3206− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3370+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
32073371 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
32083372 enum port port = encoder->port;
32093373
@@ -3222,7 +3386,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) · 12 unmodified lines
32223386 uint8_t
32233387 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
32243388 {
3225− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3389+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
32263390 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
32273391 enum port port = encoder->port;
32283392
@@ -3534,7 +3698,7 @@ ivb_cpu_edp_signal_levels(uint8_t train_set) · 305 unmodified lines
35343698 void
35353699 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
35363700 {
3537− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3701+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
35383702 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
35393703 enum port port = intel_dig_port->base.port;
35403704 uint32_t signal_levels, mask = 0;
@@ -3591,7 +3755,7 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, · 50 unmodified lines
35913755
35923756 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
35933757 {
3594− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3758+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
35953759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
35963760 enum port port = intel_dig_port->base.port;
35973761 uint32_t val;
@@ -4090,12 +4254,14 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) · 492 unmodified lines
40904254 int ret = 0;
40914255 int retry;
40924256 bool handled;
4257+
4258+ WARN_ON_ONCE(intel_dp->active_mst_links < 0);
40934259 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
40944260 go_again:
40954261 if (bret == true) {
40964262
40974263 /* check link status - esi[10] = 0x200c */
4098− if (intel_dp->active_mst_links &&
4264+ if (intel_dp->active_mst_links > 0 &&
40994265 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
41004266 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
41014267 intel_dp_start_link_train(intel_dp);
@@ -4160,18 +4326,6 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) · 58 unmodified lines
41604326 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
41614327 }
41624328
4163−/*
4164− * If display is now connected check links status,
4165− * there has been known issues of link loss triggering
4166− * long pulse.
4167− *
4168− * Some sinks (eg. ASUS PB287Q) seem to perform some
4169− * weird HPD ping pong during modesets. So we can apparently
4170− * end up with HPD going low during a modeset, and then
4171− * going back up soon after. And once that happens we must
4172− * retrain the link to get a picture. That's in case no
4173− * userspace component reacted to intermittent HPD dip.
4174− */
41754329 int intel_dp_retrain_link(struct intel_encoder *encoder,
41764330 struct drm_modeset_acquire_ctx *ctx)
41774331 {
@@ -4294,7 +4448,7 @@ static bool intel_dp_hotplug(struct intel_encoder *encoder, · 116 unmodified lines
42944448 static bool
42954449 intel_dp_short_pulse(struct intel_dp *intel_dp)
42964450 {
4297− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4451+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
42984452 u8 sink_irq_vector = 0;
42994453 u8 old_sink_count = intel_dp->sink_count;
43004454 bool ret;
@@ -4586,10 +4740,205 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder) · 285 unmodified lines
45864740 return I915_READ(GEN8_DE_PORT_ISR) & bit;
45874741 }
45884742
4743+static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
4744+ struct intel_digital_port *intel_dig_port)
4745+{
4746+ enum port port = intel_dig_port->base.port;
4747+
4748+ return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
4749+}
4750+
4751+static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
4752+ struct intel_digital_port *intel_dig_port,
4753+ bool is_legacy, bool is_typec, bool is_tbt)
4754+{
4755+ enum port port = intel_dig_port->base.port;
4756+ enum tc_port_type old_type = intel_dig_port->tc_type;
4757+ const char *type_str;
4758+
4759+ WARN_ON(is_legacy + is_typec + is_tbt != 1);
4760+
4761+ if (is_legacy) {
4762+ intel_dig_port->tc_type = TC_PORT_LEGACY;
4763+ type_str = "legacy";
4764+ } else if (is_typec) {
4765+ intel_dig_port->tc_type = TC_PORT_TYPEC;
4766+ type_str = "typec";
4767+ } else if (is_tbt) {
4768+ intel_dig_port->tc_type = TC_PORT_TBT;
4769+ type_str = "tbt";
4770+ } else {
4771+ return;
4772+ }
4773+
4774+ /* Types are not supposed to be changed at runtime. */
4775+ WARN_ON(old_type != TC_PORT_UNKNOWN &&
4776+ old_type != intel_dig_port->tc_type);
4777+
4778+ if (old_type != intel_dig_port->tc_type)
4779+ DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
4780+ type_str);
4781+}
4782+
4783+/*
4784+ * This function implements the first part of the Connect Flow described by our
4785+ * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
4786+ * lanes, EDID, etc) is done as needed in the typical places.
4787+ *
4788+ * Unlike the other ports, type-C ports are not available to use as soon as we
4789+ * get a hotplug. The type-C PHYs can be shared between multiple controllers:
4790+ * display, USB, etc. As a result, handshaking through FIA is required around
4791+ * connect and disconnect to cleanly transfer ownership with the controller and
4792+ * set the type-C power state.
4793+ *
4794+ * We could opt to only do the connect flow when we actually try to use the AUX
4795+ * channels or do a modeset, then immediately run the disconnect flow after
4796+ * usage, but there are some implications on this for a dynamic environment:
4797+ * things may go away or change behind our backs. So for now our driver is
4798+ * always trying to acquire ownership of the controller as soon as it gets an
4799+ * interrupt (or polls state and sees a port is connected) and only gives it
4800+ * back when it sees a disconnect. Implementation of a more fine-grained model
4801+ * will require a lot of coordination with user space and thorough testing for
4802+ * the extra possible cases.
4803+ */
4804+static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
4805+ struct intel_digital_port *dig_port)
4806+{
4807+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4808+ u32 val;
4809+
4810+ if (dig_port->tc_type != TC_PORT_LEGACY &&
4811+ dig_port->tc_type != TC_PORT_TYPEC)
4812+ return true;
4813+
4814+ val = I915_READ(PORT_TX_DFLEXDPPMS);
4815+ if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
4816+ DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
4817+ return false;
4818+ }
4819+
4820+ /*
4821+ * This function may be called many times in a row without an HPD event
4822+ * in between, so try to avoid the write when we can.
4823+ */
4824+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
4825+ if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
4826+ val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4827+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4828+ }
4829+
4830+ /*
4831+ * Now we have to re-check the live state, in case the port recently
4832+ * became disconnected. Not necessary for legacy mode.
4833+ */
4834+ if (dig_port->tc_type == TC_PORT_TYPEC &&
4835+ !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
4836+ DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
4837+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
4838+ val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4839+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4840+ return false;
4841+ }
4842+
4843+ return true;
4844+}
4845+
4846+/*
4847+ * See the comment at the connect function. This implements the Disconnect
4848+ * Flow.
4849+ */
4850+static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4851+ struct intel_digital_port *dig_port)
4852+{
4853+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4854+ u32 val;
4855+
4856+ if (dig_port->tc_type != TC_PORT_LEGACY &&
4857+ dig_port->tc_type != TC_PORT_TYPEC)
4858+ return;
4859+
4860+ /*
4861+ * This function may be called many times in a row without an HPD event
4862+ * in between, so try to avoid the write when we can.
4863+ */
4864+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
4865+ if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
4866+ val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4867+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4868+ }
4869+}
4870+
4871+/*
4872+ * The type-C ports are different because even when they are connected, they may
4873+ * not be available/usable by the graphics driver: see the comment on
4874+ * icl_tc_phy_connect(). So in our driver instead of adding the additional
4875+ * concept of "usable" and make everything check for "connected and usable" we
4876+ * define a port as "connected" when it is not only connected, but also when it
4877+ * is usable by the rest of the driver. That maintains the old assumption that
4878+ * connected ports are usable, and avoids exposing to the users objects they
4879+ * can't really use.
4880+ */
4881+static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
4882+ struct intel_digital_port *intel_dig_port)
4883+{
4884+ enum port port = intel_dig_port->base.port;
4885+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4886+ bool is_legacy, is_typec, is_tbt;
4887+ u32 dpsp;
4888+
4889+ is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
4890+
4891+ /*
4892+ * The spec says we shouldn't be using the ISR bits for detecting
4893+ * between TC and TBT. We should use DFLEXDPSP.
4894+ */
4895+ dpsp = I915_READ(PORT_TX_DFLEXDPSP);
4896+ is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
4897+ is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
4898+
4899+ if (!is_legacy && !is_typec && !is_tbt) {
4900+ icl_tc_phy_disconnect(dev_priv, intel_dig_port);
4901+ return false;
4902+ }
4903+
4904+ icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
4905+ is_tbt);
4906+
4907+ if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
4908+ return false;
4909+
4910+ return true;
4911+}
4912+
4913+static bool icl_digital_port_connected(struct intel_encoder *encoder)
4914+{
4915+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4916+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4917+
4918+ switch (encoder->hpd_pin) {
4919+ case HPD_PORT_A:
4920+ case HPD_PORT_B:
4921+ return icl_combo_port_connected(dev_priv, dig_port);
4922+ case HPD_PORT_C:
4923+ case HPD_PORT_D:
4924+ case HPD_PORT_E:
4925+ case HPD_PORT_F:
4926+ return icl_tc_port_connected(dev_priv, dig_port);
4927+ default:
4928+ MISSING_CASE(encoder->hpd_pin);
4929+ return false;
4930+ }
4931+}
4932+
45894933 /*
45904934 * intel_digital_port_connected - is the specified port connected?
45914935 * @encoder: intel_encoder
45924936 *
4937+ * In cases where there's a connector physically connected but it can't be used
4938+ * by our hardware we also return false, since the rest of the driver should
4939+ * pretty much treat the port as disconnected. This is relevant for type-C
4940+ * (starting on ICL) where there's ownership involved.
4941+ *
45934942 * Return %true if port is connected, %false otherwise.
45944943 */
45954944 bool intel_digital_port_connected(struct intel_encoder *encoder)
@@ -4613,8 +4962,10 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) · 17 unmodified lines
46134962 return bdw_digital_port_connected(encoder);
46144963 else if (IS_GEN9_LP(dev_priv))
46154964 return bxt_digital_port_connected(encoder);
4616− else
4965+ else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
46174966 return spt_digital_port_connected(encoder);
4967+ else
4968+ return icl_digital_port_connected(encoder);
46184969 }
46194970
46204971 static struct edid *
@@ -4661,7 +5012,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) · 40 unmodified lines
46615012 }
46625013
46635014 static int
4664−intel_dp_long_pulse(struct intel_connector *connector)
5015+intel_dp_long_pulse(struct intel_connector *connector,
5016+ struct drm_modeset_acquire_ctx *ctx)
46655017 {
46665018 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
46675019 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
@@ -4720,6 +5072,22 @@ intel_dp_long_pulse(struct intel_connector *connector) · 52 unmodified lines
47205072 */
47215073 status = connector_status_disconnected;
47225074 goto out;
5075+ } else {
5076+ /*
5077+ * If display is now connected check links status,
5078+ * there has been known issues of link loss triggering
5079+ * long pulse.
5080+ *
5081+ * Some sinks (eg. ASUS PB287Q) seem to perform some
5082+ * weird HPD ping pong during modesets. So we can apparently
5083+ * end up with HPD going low during a modeset, and then
5084+ * going back up soon after. And once that happens we must
5085+ * retrain the link to get a picture. That's in case no
5086+ * userspace component reacted to intermittent HPD dip.
5087+ */
5088+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5089+
5090+ intel_dp_retrain_link(encoder, ctx);
47235091 }
47245092
47255093 /*
@@ -4781,7 +5149,7 @@ intel_dp_detect(struct drm_connector *connector, · 55 unmodified lines
47815149 return ret;
47825150 }
47835151
4784− status = intel_dp_long_pulse(intel_dp->attached_connector);
5152+ status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
47855153 }
47865154
47875155 intel_dp->detect_done = false;
@@ -5172,7 +5540,7 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { · 384 unmodified lines
51725540
51735541 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
51745542 {
5175− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5543+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
51765544
51775545 lockdep_assert_held(&dev_priv->pps_mutex);
51785546
@@ -5193,7 +5561,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) · 14 unmodified lines
51935561
51945562 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
51955563 {
5196− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5564+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
51975565 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
51985566 enum pipe pipe;
51995567
@@ -5260,7 +5628,7 @@ enum irqreturn · 60 unmodified lines
52605628 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
52615629 {
52625630 struct intel_dp *intel_dp = &intel_dig_port->dp;
5263− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5631+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
52645632 enum irqreturn ret = IRQ_NONE;
52655633
52665634 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
@@ -5376,7 +5744,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) · 109 unmodified lines
53765744 static void
53775745 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
53785746 {
5379− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5747+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
53805748 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
53815749 struct pps_registers regs;
53825750
@@ -5444,7 +5812,7 @@ intel_pps_verify_state(struct intel_dp *intel_dp) · 61 unmodified lines
54445812 static void
54455813 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
54465814 {
5447− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5815+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
54485816 struct edp_power_seq cur, vbt, spec,
54495817 *final = &intel_dp->pps_delays;
54505818
@@ -5537,7 +5905,7 @@ static void · 86 unmodified lines
55375905 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
55385906 bool force_disable_vdd)
55395907 {
5540− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5908+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
55415909 u32 pp_on, pp_off, pp_div, port_sel = 0;
55425910 int div = dev_priv->rawclk_freq / 1000;
55435911 struct pps_registers regs;
@@ -5633,7 +6001,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, · 89 unmodified lines
56336001
56346002 static void intel_dp_pps_init(struct intel_dp *intel_dp)
56356003 {
5636− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
6004+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
56376005
56386006 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
56396007 vlv_initial_power_sequencer_setup(intel_dp);
@@ -5750,7 +6118,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, · 110 unmodified lines
57506118 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
57516119 const struct intel_crtc_state *crtc_state)
57526120 {
5753− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
6121+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
57546122
57556123 if (!crtc_state->has_drrs) {
57566124 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
@@ -5785,7 +6153,7 @@ unlock: · 28 unmodified lines
57856153 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
57866154 const struct intel_crtc_state *old_crtc_state)
57876155 {
5788− struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
6156+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
57896157
57906158 if (!old_crtc_state->has_drrs)
57916159 return;
@@ -6017,8 +6385,8 @@ intel_dp_drrs_init(struct intel_connector *connector, · 225 unmodified lines
60176385 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
60186386 struct intel_connector *intel_connector)
60196387 {
6020− struct drm_device *dev = intel_dp_to_dev(intel_dp);
6021− struct drm_i915_private *dev_priv = to_i915(dev);
6388+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6389+ struct drm_device *dev = &dev_priv->drm;
60226390 struct drm_connector *connector = &intel_connector->base;
60236391 struct drm_display_mode *fixed_mode = NULL;
60246392 struct drm_display_mode *downclock_mode = NULL;
drivers/gpu/drm/i915/intel_dp_link_training.c+20−5
@@ -129,7 +129,8 @@ static bool · 128 unmodified lines
129129 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
130130 {
131131 uint8_t voltage;
132− int voltage_tries, max_vswing_tries;
132+ int voltage_tries, cr_tries, max_cr_tries;
133+ bool max_vswing_reached = false;
133134 uint8_t link_config[2];
134135 uint8_t link_bw, rate_select;
135136
@@ -170,9 +171,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) · 34 unmodified lines
170171 return false;
171172 }
172173
174+ /*
175+ * The DP 1.4 spec defines the max clock recovery retries value
176+ * as 10 but for pre-DP 1.4 devices we set a very tolerant
177+ * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
178+ * x 5 identical voltage retries). Since the previous specs didn't
179+ * define a limit and created the possibility of an infinite loop
180+ * we want to prevent any sync from triggering that corner case.
181+ */
182+ if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
183+ max_cr_tries = 10;
184+ else
185+ max_cr_tries = 80;
186+
173187 voltage_tries = 1;
174− max_vswing_tries = 0;
175− for (;;) {
188+ for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
176189 uint8_t link_status[DP_LINK_STATUS_SIZE];
177190
178191 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
@@ -192,7 +205,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) · 13 unmodified lines
192205 return false;
193206 }
194207
195− if (max_vswing_tries == 1) {
208+ if (max_vswing_reached) {
196209 DRM_DEBUG_KMS("Max Voltage Swing reached\n");
197210 return false;
198211 }
@@ -213,9 +226,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) · 14 unmodified lines
213226 voltage_tries = 1;
214227
215228 if (intel_dp_link_max_vswing_reached(intel_dp))
216− ++max_vswing_tries;
229+ max_vswing_reached = true;
217230
218231 }
232+ DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries);
233+ return false;
219234 }
220235
221236 /*
drivers/gpu/drm/i915/intel_dp_mst.c+7−7
@@ -166,6 +166,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, · 165 unmodified lines
166166 struct intel_connector *connector =
167167 to_intel_connector(old_conn_state->connector);
168168
169+ intel_ddi_disable_pipe_clock(old_crtc_state);
170+
169171 /* this can fail */
170172 drm_dp_check_act_status(&intel_dp->mst_mgr);
171173 /* and this can also fail */
@@ -241,17 +243,16 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, · 69 unmodified lines
241243 connector->port,
242244 pipe_config->pbn,
243245 pipe_config->dp_m_n.tu);
244− if (ret == false) {
246+ if (!ret)
245247 DRM_ERROR("failed to allocate vcpi\n");
246− return;
247− }
248−
249248
250249 intel_dp->active_mst_links++;
251250 temp = I915_READ(DP_TP_STATUS(port));
252251 I915_WRITE(DP_TP_STATUS(port), temp);
253252
254253 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
254+
255+ intel_ddi_enable_pipe_clock(pipe_config);
255256 }
256257
257258 static void intel_mst_enable_dp(struct intel_encoder *encoder,
@@ -263,7 +264,6 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder, · 5 unmodified lines
263264 struct intel_dp *intel_dp = &intel_dig_port->dp;
264265 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
265266 enum port port = intel_dig_port->base.port;
266− int ret;
267267
268268 DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
269269
@@ -274,9 +274,9 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder, · 4 unmodified lines
274274 1))
275275 DRM_ERROR("Timed out waiting for ACT sent\n");
276276
277− ret = drm_dp_check_act_status(&intel_dp->mst_mgr);
277+ drm_dp_check_act_status(&intel_dp->mst_mgr);
278278
279− ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr);
279+ drm_dp_update_payload_part2(&intel_dp->mst_mgr);
280280 if (pipe_config->has_audio)
281281 intel_audio_codec_enable(encoder, pipe_config, conn_state);
282282 }
drivers/gpu/drm/i915/intel_dpll_mgr.c+46−16
@@ -2212,6 +2212,20 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, · 2211 unmodified lines
22122212 params->dco_fraction = dco & 0x7fff;
22132213 }
22142214
2215+int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
2216+{
2217+ int ref_clock = dev_priv->cdclk.hw.ref;
2218+
2219+ /*
2220+ * For ICL+, the spec states: if reference frequency is 38.4,
2221+ * use 19.2 because the DPLL automatically divides that by 2.
2222+ */
2223+ if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
2224+ ref_clock = 19200;
2225+
2226+ return ref_clock;
2227+}
2228+
22152229 static bool
22162230 cnl_ddi_calculate_wrpll(int clock,
22172231 struct drm_i915_private *dev_priv,
@@ -2251,14 +2265,7 @@ cnl_ddi_calculate_wrpll(int clock, · 33 unmodified lines
22512265
22522266 cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
22532267
2254− ref_clock = dev_priv->cdclk.hw.ref;
2255−
2256− /*
2257− * For ICL, the spec states: if reference frequency is 38.4, use 19.2
2258− * because the DPLL automatically divides that by 2.
2259− */
2260− if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
2261− ref_clock = 19200;
2268+ ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
22622269
22632270 cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
22642271 kdiv);
@@ -2452,6 +2459,16 @@ static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = { · 187 unmodified lines
24522459 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
24532460 };
24542461
2462+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2463+ .dco_integer = 0x151, .dco_fraction = 0x4000,
2464+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2465+};
2466+
2467+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2468+ .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2469+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2470+};
2471+
24552472 static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
24562473 struct skl_wrpll_params *pll_params)
24572474 {
@@ -2494,6 +2511,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock, · 36 unmodified lines
24942511 return true;
24952512 }
24962513
2514+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
2515+ struct skl_wrpll_params *pll_params)
2516+{
2517+ *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
2518+ icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
2519+ return true;
2520+}
2521+
24972522 static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
24982523 struct intel_encoder *encoder, int clock,
24992524 struct intel_dpll_hw_state *pll_state)
@@ -2503,7 +2528,9 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, · 3 unmodified lines
25032528 struct skl_wrpll_params pll_params = { 0 };
25042529 bool ret;
25052530
2506− if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2531+ if (intel_port_is_tc(dev_priv, encoder->port))
2532+ ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
2533+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
25072534 ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
25082535 else
25092536 ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
@@ -2623,7 +2650,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, · 113 unmodified lines
26232650
26242651 for (div2 = 10; div2 > 0; div2--) {
26252652 int dco = div1 * div2 * clock_khz * 5;
2626− int a_divratio, tlinedrv, inputsel, hsdiv;
2653+ int a_divratio, tlinedrv, inputsel;
2654+ u32 hsdiv;
26272655
26282656 if (dco < dco_min_freq || dco > dco_max_freq)
26292657 continue;
@@ -2642,16 +2670,16 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, · 12 unmodified lines
26422670 MISSING_CASE(div1);
26432671 /* fall through */
26442672 case 2:
2645− hsdiv = 0;
2673+ hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
26462674 break;
26472675 case 3:
2648− hsdiv = 1;
2676+ hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
26492677 break;
26502678 case 5:
2651− hsdiv = 2;
2679+ hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
26522680 break;
26532681 case 7:
2654− hsdiv = 3;
2682+ hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
26552683 break;
26562684 }
26572685
@@ -2665,7 +2693,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, · 7 unmodified lines
26652693 state->mg_clktop2_hsclkctl =
26662694 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
26672695 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2668− MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |
2696+ hsdiv |
26692697 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
26702698
26712699 return true;
@@ -2846,6 +2874,8 @@ static struct intel_shared_dpll * · 174 unmodified lines
28462874 icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
28472875 struct intel_encoder *encoder)
28482876 {
2877+ struct intel_digital_port *intel_dig_port =
2878+ enc_to_dig_port(&encoder->base);
28492879 struct intel_shared_dpll *pll;
28502880 struct intel_dpll_hw_state pll_state = {};
28512881 enum port port = encoder->port;
@@ -2865,7 +2895,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, · 13 unmodified lines
28652895 case PORT_D:
28662896 case PORT_E:
28672897 case PORT_F:
2868− if (0 /* TODO: TBT PLLs */) {
2898+ if (intel_dig_port->tc_type == TC_PORT_TBT) {
28692899 min = DPLL_ID_ICL_TBTPLL;
28702900 max = min;
28712901 ret = icl_calc_dpll_state(crtc_state, encoder, clock,
drivers/gpu/drm/i915/intel_dpll_mgr.h+1−0
@@ -344,5 +344,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, · 343 unmodified lines
344344 struct intel_dpll_hw_state *hw_state);
345345 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
346346 uint32_t pll_id);
347+int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
347348
348349 #endif /* _INTEL_DPLL_MGR_H_ */
drivers/gpu/drm/i915/intel_drv.h+33−10
@@ -972,9 +972,8 @@ struct intel_plane { · 971 unmodified lines
972972 void (*disable_plane)(struct intel_plane *plane,
973973 struct intel_crtc *crtc);
974974 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
975− int (*check_plane)(struct intel_plane *plane,
976− struct intel_crtc_state *crtc_state,
977− struct intel_plane_state *state);
975+ int (*check_plane)(struct intel_crtc_state *crtc_state,
976+ struct intel_plane_state *plane_state);
978977 };
979978
980979 struct intel_watermark_params {
@@ -1168,6 +1167,7 @@ struct intel_digital_port { · 187 unmodified lines
11681167 bool release_cl2_override;
11691168 uint8_t max_lanes;
11701169 enum intel_display_power_domain ddi_io_power_domain;
1170+ enum tc_port_type tc_type;
11711171
11721172 void (*write_infoframe)(struct drm_encoder *encoder,
11731173 const struct intel_crtc_state *crtc_state,
@@ -1314,6 +1314,12 @@ dp_to_lspcon(struct intel_dp *intel_dp) · 140 unmodified lines
13141314 return &dp_to_dig_port(intel_dp)->lspcon;
13151315 }
13161316
1317+static inline struct drm_i915_private *
1318+dp_to_i915(struct intel_dp *intel_dp)
1319+{
1320+ return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1321+}
1322+
13171323 static inline struct intel_digital_port *
13181324 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
13191325 {
@@ -1717,6 +1723,9 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, · 397 unmodified lines
17171723 unsigned int frontbuffer_bits);
17181724 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
17191725 unsigned int frontbuffer_bits);
1726+void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
1727+void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
1728+void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
17201729
17211730 void
17221731 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
@@ -1930,6 +1939,9 @@ void intel_psr_enable(struct intel_dp *intel_dp, · 207 unmodified lines
19301939 const struct intel_crtc_state *crtc_state);
19311940 void intel_psr_disable(struct intel_dp *intel_dp,
19321941 const struct intel_crtc_state *old_crtc_state);
1942+int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
1943+ struct drm_modeset_acquire_ctx *ctx,
1944+ u64 value);
19331945 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
19341946 unsigned frontbuffer_bits,
19351947 enum fb_op_origin origin);
@@ -1939,20 +1951,33 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, · 3 unmodified lines
19391951 void intel_psr_init(struct drm_i915_private *dev_priv);
19401952 void intel_psr_compute_config(struct intel_dp *intel_dp,
19411953 struct intel_crtc_state *crtc_state);
1942−void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1954+void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
19431955 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
19441956 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1945−int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
1957+int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
1958+ u32 *out_value);
19461959
19471960 /* intel_runtime_pm.c */
19481961 int intel_power_domains_init(struct drm_i915_private *);
1949−void intel_power_domains_fini(struct drm_i915_private *);
1962+void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
19501963 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1951−void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1952−void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1964+void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
1965+void intel_power_domains_enable(struct drm_i915_private *dev_priv);
1966+void intel_power_domains_disable(struct drm_i915_private *dev_priv);
1967+
1968+enum i915_drm_suspend_mode {
1969+ I915_DRM_SUSPEND_IDLE,
1970+ I915_DRM_SUSPEND_MEM,
1971+ I915_DRM_SUSPEND_HIBERNATE,
1972+};
1973+
1974+void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
1975+ enum i915_drm_suspend_mode);
1976+void intel_power_domains_resume(struct drm_i915_private *dev_priv);
19531977 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
19541978 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
19551979 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1980+void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
19561981 const char *
19571982 intel_display_power_domain_str(enum intel_display_power_domain domain);
19581983
@@ -2030,8 +2055,6 @@ bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); · 71 unmodified lines
20302055 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
20312056 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
20322057
2033−void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2034−
20352058 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
20362059 bool override, unsigned int mask);
20372060 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
drivers/gpu/drm/i915/intel_engine_cs.c+41−52
@@ -513,7 +513,7 @@ int intel_engine_create_scratch(struct intel_engine_cs *engine, · 512 unmodified lines
513513 goto err_unref;
514514 }
515515
516− ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
516+ ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
517517 if (ret)
518518 goto err_unref;
519519
@@ -527,36 +527,19 @@ err_unref: · 7 unmodified lines
527527
528528 void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
529529 {
530− i915_vma_unpin_and_release(&engine->scratch);
531−}
532−
533−static void cleanup_phys_status_page(struct intel_engine_cs *engine)
534−{
535− struct drm_i915_private *dev_priv = engine->i915;
536−
537− if (!dev_priv->status_page_dmah)
538− return;
539−
540− drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
541− engine->status_page.page_addr = NULL;
530+ i915_vma_unpin_and_release(&engine->scratch, 0);
542531 }
543532
544533 static void cleanup_status_page(struct intel_engine_cs *engine)
545534 {
546− struct i915_vma *vma;
547− struct drm_i915_gem_object *obj;
548−
549− vma = fetch_and_zero(&engine->status_page.vma);
550− if (!vma)
551− return;
552−
553− obj = vma->obj;
535+ if (HWS_NEEDS_PHYSICAL(engine->i915)) {
536+ void *addr = fetch_and_zero(&engine->status_page.page_addr);
554537
555− i915_vma_unpin(vma);
556− i915_vma_close(vma);
538+ __free_page(virt_to_page(addr));
539+ }
557540
558− i915_gem_object_unpin_map(obj);
559− __i915_gem_object_release_unless_active(obj);
541+ i915_vma_unpin_and_release(&engine->status_page.vma,
542+ I915_VMA_RELEASE_MAP);
560543 }
561544
562545 static int init_status_page(struct intel_engine_cs *engine)
@@ -598,7 +581,7 @@ static int init_status_page(struct intel_engine_cs *engine) · 35 unmodified lines
598581 flags |= PIN_MAPPABLE;
599582 else
600583 flags |= PIN_HIGH;
601− ret = i915_vma_pin(vma, 0, 4096, flags);
584+ ret = i915_vma_pin(vma, 0, 0, flags);
602585 if (ret)
603586 goto err;
604587
@@ -622,17 +605,18 @@ err: · 17 unmodified lines
622605
623606 static int init_phys_status_page(struct intel_engine_cs *engine)
624607 {
625− struct drm_i915_private *dev_priv = engine->i915;
608+ struct page *page;
626609
627− GEM_BUG_ON(engine->id != RCS);
628−
629− dev_priv->status_page_dmah =
630− drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
631− if (!dev_priv->status_page_dmah)
610+ /*
611+ * Though the HWS register does support 36bit addresses, historically
612+ * we have had hangs and corruption reported due to wild writes if
613+ * the HWS is placed above 4G.
614+ */
615+ page = alloc_page(GFP_KERNEL | __GFP_DMA32 | __GFP_ZERO);
616+ if (!page)
632617 return -ENOMEM;
633618
634− engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
635− memset(engine->status_page.page_addr, 0, PAGE_SIZE);
619+ engine->status_page.page_addr = page_address(page);
636620
637621 return 0;
638622 }
@@ -722,10 +706,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) · 83 unmodified lines
722706
723707 intel_engine_cleanup_scratch(engine);
724708
725− if (HWS_NEEDS_PHYSICAL(engine->i915))
726− cleanup_phys_status_page(engine);
727− else
728− cleanup_status_page(engine);
709+ cleanup_status_page(engine);
729710
730711 intel_engine_fini_breadcrumbs(engine);
731712 intel_engine_cleanup_cmd_parser(engine);
@@ -800,6 +781,16 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine) · 68 unmodified lines
800781 return err;
801782 }
802783
784+void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
785+{
786+ struct drm_i915_private *dev_priv = engine->i915;
787+
788+ GEM_TRACE("%s\n", engine->name);
789+
790+ I915_WRITE_FW(RING_MI_MODE(engine->mmio_base),
791+ _MASKED_BIT_DISABLE(STOP_RING));
792+}
793+
803794 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
804795 {
805796 switch (type) {
@@ -980,8 +971,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) · 174 unmodified lines
980971 return true;
981972
982973 /* Any inflight/incomplete requests? */
983− if (!i915_seqno_passed(intel_engine_get_seqno(engine),
984− intel_engine_last_submit(engine)))
974+ if (!intel_engine_signaled(engine, intel_engine_last_submit(engine)))
985975 return false;
986976
987977 if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock))
@@ -1348,20 +1338,19 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, · 360 unmodified lines
13481338
13491339 if (HAS_EXECLISTS(dev_priv)) {
13501340 const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
1351− u32 ptr, read, write;
13521341 unsigned int idx;
1342+ u8 read, write;
13531343
13541344 drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
13551345 I915_READ(RING_EXECLIST_STATUS_LO(engine)),
13561346 I915_READ(RING_EXECLIST_STATUS_HI(engine)));
13571347
1358− ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
1359− read = GEN8_CSB_READ_PTR(ptr);
1360− write = GEN8_CSB_WRITE_PTR(ptr);
1361− drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], tasklet queued? %s (%s)\n",
1362− read, execlists->csb_head,
1363− write,
1364− intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
1348+ read = execlists->csb_head;
1349+ write = READ_ONCE(*execlists->csb_write);
1350+
1351+ drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
1352+ read, write,
1353+ GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
13651354 yesno(test_bit(TASKLET_STATE_SCHED,
13661355 &engine->execlists.tasklet.state)),
13671356 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
@@ -1373,12 +1362,12 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, · 5 unmodified lines
13731362 write += GEN8_CSB_ENTRIES;
13741363 while (read < write) {
13751364 idx = ++read % GEN8_CSB_ENTRIES;
1376− drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [0x%08x in hwsp], context: %d [%d in hwsp]\n",
1365+ drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
13771366 idx,
1378− I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
13791367 hws[idx * 2],
1380− I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)),
1381− hws[idx * 2 + 1]);
1368+ I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
1369+ hws[idx * 2 + 1],
1370+ I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
13821371 }
13831372
13841373 rcu_read_lock();
drivers/gpu/drm/i915/intel_guc.c+46−56
@@ -27,8 +27,6 @@ · 26 unmodified lines
2727 #include "intel_guc_submission.h"
2828 #include "i915_drv.h"
2929
30−static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
31−
3230 static void gen8_guc_raise_irq(struct intel_guc *guc)
3331 {
3432 struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -128,13 +126,15 @@ static int guc_init_wq(struct intel_guc *guc) · 93 unmodified lines
128126
129127 static void guc_fini_wq(struct intel_guc *guc)
130128 {
131− struct drm_i915_private *dev_priv = guc_to_i915(guc);
129+ struct workqueue_struct *wq;
132130
133− if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
134− USES_GUC_SUBMISSION(dev_priv))
135− destroy_workqueue(guc->preempt_wq);
131+ wq = fetch_and_zero(&guc->preempt_wq);
132+ if (wq)
133+ destroy_workqueue(wq);
136134
137− destroy_workqueue(guc->log.relay.flush_wq);
135+ wq = fetch_and_zero(&guc->log.relay.flush_wq);
136+ if (wq)
137+ destroy_workqueue(wq);
138138 }
139139
140140 int intel_guc_init_misc(struct intel_guc *guc)
@@ -142,8 +142,6 @@ int intel_guc_init_misc(struct intel_guc *guc) · 1 unmodified line
142142 struct drm_i915_private *i915 = guc_to_i915(guc);
143143 int ret;
144144
145− guc_init_ggtt_pin_bias(guc);
146−
147145 ret = guc_init_wq(guc);
148146 if (ret)
149147 return ret;
@@ -170,7 +168,7 @@ static int guc_shared_data_create(struct intel_guc *guc) · 20 unmodified lines
170168
171169 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
172170 if (IS_ERR(vaddr)) {
173− i915_vma_unpin_and_release(&vma);
171+ i915_vma_unpin_and_release(&vma, 0);
174172 return PTR_ERR(vaddr);
175173 }
176174
@@ -182,8 +180,7 @@ static int guc_shared_data_create(struct intel_guc *guc) · 5 unmodified lines
182180
183181 static void guc_shared_data_destroy(struct intel_guc *guc)
184182 {
185− i915_gem_object_unpin_map(guc->shared_data->obj);
186− i915_vma_unpin_and_release(&guc->shared_data);
183+ i915_vma_unpin_and_release(&guc->shared_data, I915_VMA_RELEASE_MAP);
187184 }
188185
189186 int intel_guc_init(struct intel_guc *guc)
@@ -584,52 +581,27 @@ int intel_guc_resume(struct intel_guc *guc) · 394 unmodified lines
584581 *
585582 * ::
586583 *
587− * +==============> +====================+ <== GUC_GGTT_TOP
588− * ^ | |
589− * | | |
590− * | | DRAM |
591− * | | Memory |
592− * | | |
593− * GuC | |
594− * Address +========> +====================+ <== WOPCM Top
595− * Space ^ | HW contexts RSVD |
596− * | | | WOPCM |
597− * | | +==> +--------------------+ <== GuC WOPCM Top
598− * | GuC ^ | |
599− * | GGTT | | |
600− * | Pin GuC | GuC |
601− * | Bias WOPCM | WOPCM |
602− * | | Size | |
603− * | | | | |
604− * v v v | |
605− * +=====+=====+==> +====================+ <== GuC WOPCM Base
606− * | Non-GuC WOPCM |
607− * | (HuC/Reserved) |
608− * +====================+ <== WOPCM Base
584+ * +===========> +====================+ <== FFFF_FFFF
585+ * ^ | Reserved |
586+ * | +====================+ <== GUC_GGTT_TOP
587+ * | | |
588+ * | | DRAM |
589+ * GuC | |
590+ * Address +===> +====================+ <== GuC ggtt_pin_bias
591+ * Space ^ | |
592+ * | | | |
593+ * | GuC | GuC |
594+ * | WOPCM | WOPCM |
595+ * | Size | |
596+ * | | | |
597+ * v v | |
598+ * +=======+===> +====================+ <== 0000_0000
609599 *
610− * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
600+ * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
611601 * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
612− * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
613− * actual GuC WOPCM size.
602+ * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
614603 */
615604
616−/**
617− * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
618− * @guc: intel_guc structure.
619− *
620− * This function will calculate and initialize the ggtt_pin_bias value based on
621− * overall WOPCM size and GuC WOPCM size.
622− */
623−static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
624−{
625− struct drm_i915_private *i915 = guc_to_i915(guc);
626−
627− GEM_BUG_ON(!i915->wopcm.size);
628− GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
629−
630− guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
631−}
632−
633605 /**
634606 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
635607 * @guc: the guc
@@ -648,6 +620,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) · 12 unmodified lines
648620 struct drm_i915_private *dev_priv = guc_to_i915(guc);
649621 struct drm_i915_gem_object *obj;
650622 struct i915_vma *vma;
623+ u64 flags;
651624 int ret;
652625
653626 obj = i915_gem_object_create(dev_priv, size);
@@ -658,8 +631,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) · 4 unmodified lines
658631 if (IS_ERR(vma))
659632 goto err;
660633
661− ret = i915_vma_pin(vma, 0, PAGE_SIZE,
662− PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
634+ flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
635+ ret = i915_vma_pin(vma, 0, 0, flags);
663636 if (ret) {
664637 vma = ERR_PTR(ret);
665638 goto err;
@@ -671,3 +644,20 @@ err: · 5 unmodified lines
671644 i915_gem_object_put(obj);
672645 return vma;
673646 }
647+
648+/**
649+ * intel_guc_reserved_gtt_size()
650+ * @guc: intel_guc structure
651+ *
652+ * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using
653+ * GuC we can't have any objects pinned in that region. This function returns
654+ * the size of the shadowed region.
655+ *
656+ * Returns:
657+ * 0 if GuC is not present or not in use.
658+ * Otherwise, the GuC WOPCM size.
659+ */
660+u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
661+{
662+ return guc_to_i915(guc)->wopcm.guc.size;
663+}
drivers/gpu/drm/i915/intel_guc.h+5−7
@@ -49,9 +49,6 @@ struct intel_guc { · 48 unmodified lines
4949 struct intel_guc_log log;
5050 struct intel_guc_ct ct;
5151
52− /* Offset where Non-WOPCM memory starts. */
53− u32 ggtt_pin_bias;
54−
5552 /* Log snapshot if GuC errors during load */
5653 struct drm_i915_gem_object *load_err_log;
5754
@@ -130,10 +127,10 @@ static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) · 72 unmodified lines
130127 * @vma: i915 graphics virtual memory area.
131128 *
132129 * GuC does not allow any gfx GGTT address that falls into range
133− * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
134− * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
130+ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
131+ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
135132 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
136− * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
133+ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
137134 *
138135 * Return: GGTT offset of the @vma.
139136 */
@@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, · 2 unmodified lines
142139 {
143140 u32 offset = i915_ggtt_offset(vma);
144141
145− GEM_BUG_ON(offset < guc->ggtt_pin_bias);
142+ GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
146143 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
147144
148145 return offset;
@@ -168,6 +165,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); · 19 unmodified lines
168165 int intel_guc_suspend(struct intel_guc *guc);
169166 int intel_guc_resume(struct intel_guc *guc);
170167 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
168+u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
171169
172170 static inline int intel_guc_sanitize(struct intel_guc *guc)
173171 {
drivers/gpu/drm/i915/intel_guc_ads.c+1−1
@@ -148,5 +148,5 @@ int intel_guc_ads_create(struct intel_guc *guc) · 147 unmodified lines
148148
149149 void intel_guc_ads_destroy(struct intel_guc *guc)
150150 {
151− i915_vma_unpin_and_release(&guc->ads_vma);
151+ i915_vma_unpin_and_release(&guc->ads_vma, 0);
152152 }
drivers/gpu/drm/i915/intel_guc_ct.c+2−5
@@ -204,7 +204,7 @@ static int ctch_init(struct intel_guc *guc, · 203 unmodified lines
204204 return 0;
205205
206206 err_vma:
207− i915_vma_unpin_and_release(&ctch->vma);
207+ i915_vma_unpin_and_release(&ctch->vma, 0);
208208 err_out:
209209 CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
210210 ctch->owner, err);
@@ -214,10 +214,7 @@ err_out: · 3 unmodified lines
214214 static void ctch_fini(struct intel_guc *guc,
215215 struct intel_guc_ct_channel *ctch)
216216 {
217− GEM_BUG_ON(!ctch->vma);
218−
219− i915_gem_object_unpin_map(ctch->vma->obj);
220− i915_vma_unpin_and_release(&ctch->vma);
217+ i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
221218 }
222219
223220 static int ctch_open(struct intel_guc *guc,
drivers/gpu/drm/i915/intel_guc_fwif.h+1−0
@@ -49,6 +49,7 @@ · 48 unmodified lines
4949 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
5050 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
5151 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
52+#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
5253 #define WQ_TARGET_SHIFT 10
5354 #define WQ_LEN_SHIFT 16
5455 #define WQ_NO_WCFLUSH_WAIT (1 << 27)
drivers/gpu/drm/i915/intel_guc_log.c+1−1
@@ -498,7 +498,7 @@ err: · 497 unmodified lines
498498
499499 void intel_guc_log_destroy(struct intel_guc_log *log)
500500 {
501− i915_vma_unpin_and_release(&log->vma);
501+ i915_vma_unpin_and_release(&log->vma, 0);
502502 }
503503
504504 int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
drivers/gpu/drm/i915/intel_guc_submission.c+20−15
@@ -317,7 +317,7 @@ static int guc_stage_desc_pool_create(struct intel_guc *guc) · 316 unmodified lines
317317
318318 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
319319 if (IS_ERR(vaddr)) {
320− i915_vma_unpin_and_release(&vma);
320+ i915_vma_unpin_and_release(&vma, 0);
321321 return PTR_ERR(vaddr);
322322 }
323323
@@ -331,8 +331,7 @@ static int guc_stage_desc_pool_create(struct intel_guc *guc) · 7 unmodified lines
331331 static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
332332 {
333333 ida_destroy(&guc->stage_ids);
334− i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
335− i915_vma_unpin_and_release(&guc->stage_desc_pool);
334+ i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP);
336335 }
337336
338337 /*
@@ -457,6 +456,9 @@ static void guc_wq_item_append(struct intel_guc_client *client, · 118 unmodified lines
457456 */
458457 BUILD_BUG_ON(wqi_size != 16);
459458
459+ /* We expect the WQ to be active if we're appending items to it */
460+ GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
461+
460462 /* Free space is guaranteed. */
461463 wq_off = READ_ONCE(desc->tail);
462464 GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
@@ -466,15 +468,19 @@ static void guc_wq_item_append(struct intel_guc_client *client, · 3 unmodified lines
466468 /* WQ starts from the page after doorbell / process_desc */
467469 wqi = client->vaddr + wq_off + GUC_DB_SIZE;
468470
469− /* Now fill in the 4-word work queue item */
470− wqi->header = WQ_TYPE_INORDER |
471− (wqi_len << WQ_LEN_SHIFT) |
472− (target_engine << WQ_TARGET_SHIFT) |
473− WQ_NO_WCFLUSH_WAIT;
474− wqi->context_desc = context_desc;
475− wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
476− GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
477− wqi->fence_id = fence_id;
471+ if (I915_SELFTEST_ONLY(client->use_nop_wqi)) {
472+ wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT);
473+ } else {
474+ /* Now fill in the 4-word work queue item */
475+ wqi->header = WQ_TYPE_INORDER |
476+ (wqi_len << WQ_LEN_SHIFT) |
477+ (target_engine << WQ_TARGET_SHIFT) |
478+ WQ_NO_WCFLUSH_WAIT;
479+ wqi->context_desc = context_desc;
480+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
481+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
482+ wqi->fence_id = fence_id;
483+ }
478484
479485 /* Make the update visible to GuC */
480486 WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
@@ -1008,7 +1014,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv, · 527 unmodified lines
10081014 err_vaddr:
10091015 i915_gem_object_unpin_map(client->vma->obj);
10101016 err_vma:
1011− i915_vma_unpin_and_release(&client->vma);
1017+ i915_vma_unpin_and_release(&client->vma, 0);
10121018 err_id:
10131019 ida_simple_remove(&guc->stage_ids, client->stage_id);
10141020 err_client:
@@ -1020,8 +1026,7 @@ static void guc_client_free(struct intel_guc_client *client) · 5 unmodified lines
10201026 {
10211027 unreserve_doorbell(client);
10221028 guc_stage_desc_fini(client->guc, client);
1023− i915_gem_object_unpin_map(client->vma->obj);
1024− i915_vma_unpin_and_release(&client->vma);
1029+ i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP);
10251030 ida_simple_remove(&client->guc->stage_ids, client->stage_id);
10261031 kfree(client);
10271032 }
drivers/gpu/drm/i915/intel_guc_submission.h+4−0
@@ -28,6 +28,7 @@ · 27 unmodified lines
2828 #include <linux/spinlock.h>
2929
3030 #include "i915_gem.h"
31+#include "i915_selftest.h"
3132
3233 struct drm_i915_private;
3334
@@ -71,6 +72,9 @@ struct intel_guc_client { · 37 unmodified lines
7172 spinlock_t wq_lock;
7273 /* Per-engine counts of GuC submissions */
7374 u64 submissions[I915_NUM_ENGINES];
75+
76+ /* For testing purposes, use nop WQ items instead of real ones */
77+ I915_SELFTEST_DECLARE(bool use_nop_wqi);
7478 };
7579
7680 int intel_guc_submission_init(struct intel_guc *guc);
drivers/gpu/drm/i915/intel_hangcheck.c+1−1
@@ -142,7 +142,7 @@ static int semaphore_passed(struct intel_engine_cs *engine) · 141 unmodified lines
142142 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
143143 return -1;
144144
145− if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
145+ if (intel_engine_signaled(signaller, seqno))
146146 return 1;
147147
148148 /* cursory check for an unkickable deadlock */
drivers/gpu/drm/i915/intel_hdcp.c+3−3
@@ -57,9 +57,9 @@ static bool hdcp_key_loadable(struct drm_i915_private *dev_priv) · 56 unmodified lines
5757
5858 /* PG1 (power well #1) needs to be enabled */
5959 for_each_power_well(dev_priv, power_well) {
60− if (power_well->id == id) {
61− enabled = power_well->ops->is_enabled(dev_priv,
62− power_well);
60+ if (power_well->desc->id == id) {
61+ enabled = power_well->desc->ops->is_enabled(dev_priv,
62+ power_well);
6363 break;
6464 }
6565 }
drivers/gpu/drm/i915/intel_hdmi.c+7−3
@@ -1911,22 +1911,26 @@ intel_hdmi_set_edid(struct drm_connector *connector) · 1910 unmodified lines
19111911 static enum drm_connector_status
19121912 intel_hdmi_detect(struct drm_connector *connector, bool force)
19131913 {
1914− enum drm_connector_status status;
1914+ enum drm_connector_status status = connector_status_disconnected;
19151915 struct drm_i915_private *dev_priv = to_i915(connector->dev);
19161916 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1917+ struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
19171918
19181919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
19191920 connector->base.id, connector->name);
19201921
19211922 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
19221923
1924+ if (IS_ICELAKE(dev_priv) &&
1925+ !intel_digital_port_connected(encoder))
1926+ goto out;
1927+
19231928 intel_hdmi_unset_edid(connector);
19241929
19251930 if (intel_hdmi_set_edid(connector))
19261931 status = connector_status_connected;
1927− else
1928− status = connector_status_disconnected;
19291932
1933+out:
19301934 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
19311935
19321936 if (status != connector_status_connected)
drivers/gpu/drm/i915/intel_huc.c+1−1
@@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc) · 62 unmodified lines
6363 return -ENOEXEC;
6464
6565 vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
66− PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
66+ PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
6767 if (IS_ERR(vma)) {
6868 ret = PTR_ERR(vma);
6969 DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
drivers/gpu/drm/i915/intel_i2c.c+8−8
@@ -37,7 +37,7 @@ · 36 unmodified lines
3737
3838 struct gmbus_pin {
3939 const char *name;
40− i915_reg_t reg;
40+ enum i915_gpio gpio;
4141 };
4242
4343 /* Map gmbus pin pairs to names and registers. */
@@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, · 77 unmodified lines
121121 else
122122 size = ARRAY_SIZE(gmbus_pins);
123123
124− return pin < size &&
125− i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
124+ return pin < size && get_gmbus_pin(dev_priv, pin)->name;
126125 }
127126
128127 /* Intel GPIO access functions */
@@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) · 163 unmodified lines
292291
293292 algo = &bus->bit_algo;
294293
295− bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
296− i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
294+ bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
297295 bus->adapter.algo_data = algo;
298296 algo->setsda = set_data;
299297 algo->setscl = set_clock;
@@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) · 525 unmodified lines
825823 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
826824 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
827825 else if (!HAS_GMCH_DISPLAY(dev_priv))
828− dev_priv->gpio_mmio_base =
829− i915_mmio_reg_offset(PCH_GPIOA) -
830− i915_mmio_reg_offset(GPIOA);
826+ /*
827+ * Broxton uses the same PCH offsets for South Display Engine,
828+ * even though it doesn't have a PCH.
829+ */
830+ dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
831831
832832 mutex_init(&dev_priv->gmbus_mutex);
833833 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
drivers/gpu/drm/i915/intel_lrc.c+110−49
@@ -541,11 +541,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine) · 540 unmodified lines
541541
542542 GEM_BUG_ON(execlists->preempt_complete_status !=
543543 upper_32_bits(ce->lrc_desc));
544− GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] &
545− _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
546− CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) !=
547− _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
548− CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
549544
550545 /*
551546 * Switch to our empty preempt context so
@@ -1277,6 +1272,8 @@ static void execlists_context_destroy(struct intel_context *ce) · 725 unmodified lines
12771272
12781273 static void execlists_context_unpin(struct intel_context *ce)
12791274 {
1275+ i915_gem_context_unpin_hw_id(ce->gem_context);
1276+
12801277 intel_ring_unpin(ce->ring);
12811278
12821279 ce->state->obj->pin_global--;
@@ -1303,10 +1300,9 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma) · 20 unmodified lines
13031300 }
13041301
13051302 flags = PIN_GLOBAL | PIN_HIGH;
1306− if (ctx->ggtt_offset_bias)
1307− flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
1303+ flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
13081304
1309− return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
1305+ return i915_vma_pin(vma, 0, 0, flags);
13101306 }
13111307
13121308 static struct intel_context *
@@ -1332,10 +1328,14 @@ __execlists_context_pin(struct intel_engine_cs *engine, · 19 unmodified lines
13321328 goto unpin_vma;
13331329 }
13341330
1335− ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
1331+ ret = intel_ring_pin(ce->ring);
13361332 if (ret)
13371333 goto unpin_map;
13381334
1335+ ret = i915_gem_context_pin_hw_id(ctx);
1336+ if (ret)
1337+ goto unpin_ring;
1338+
13391339 intel_lr_context_descriptor_update(ctx, engine, ce);
13401340
13411341 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
@@ -1348,6 +1348,8 @@ __execlists_context_pin(struct intel_engine_cs *engine, · 6 unmodified lines
13481348 i915_gem_context_get(ctx);
13491349 return ce;
13501350
1351+unpin_ring:
1352+ intel_ring_unpin(ce->ring);
13511353 unpin_map:
13521354 i915_gem_object_unpin_map(ce->state->obj);
13531355 unpin_vma:
@@ -1643,7 +1645,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) · 289 unmodified lines
16431645 goto err;
16441646 }
16451647
1646− err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1648+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
16471649 if (err)
16481650 goto err;
16491651
@@ -1657,7 +1659,7 @@ err: · 7 unmodified lines
16571659
16581660 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
16591661 {
1660− i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1662+ i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
16611663 }
16621664
16631665 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
@@ -1775,11 +1777,7 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine) · 111 unmodified lines
17751777
17761778 static int gen8_init_common_ring(struct intel_engine_cs *engine)
17771779 {
1778− int ret;
1779−
1780− ret = intel_mocs_init_engine(engine);
1781− if (ret)
1782− return ret;
1780+ intel_mocs_init_engine(engine);
17831781
17841782 intel_engine_reset_breadcrumbs(engine);
17851783
@@ -1838,7 +1836,8 @@ execlists_reset_prepare(struct intel_engine_cs *engine) · 52 unmodified lines
18381836 struct i915_request *request, *active;
18391837 unsigned long flags;
18401838
1841− GEM_TRACE("%s\n", engine->name);
1839+ GEM_TRACE("%s: depth<-%d\n", engine->name,
1840+ atomic_read(&execlists->tasklet.count));
18421841
18431842 /*
18441843 * Prevent request submission to the hardware until we have
@@ -1971,22 +1970,18 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) · 126 unmodified lines
19711970 {
19721971 struct intel_engine_execlists * const execlists = &engine->execlists;
19731972
1974− /* After a GPU reset, we may have requests to replay */
1975− if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
1976− tasklet_schedule(&execlists->tasklet);
1977−
19781973 /*
1979− * Flush the tasklet while we still have the forcewake to be sure
1980− * that it is not allowed to sleep before we restart and reload a
1981− * context.
1974+ * After a GPU reset, we may have requests to replay. Do so now while
1975+ * we still have the forcewake to be sure that the GPU is not allowed
1976+ * to sleep before we restart and reload a context.
19821977 *
1983− * As before (with execlists_reset_prepare) we rely on the caller
1984− * serialising multiple attempts to reset so that we know that we
1985− * are the only one manipulating tasklet state.
19861978 */
1987− __tasklet_enable_sync_once(&execlists->tasklet);
1979+ if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
1980+ execlists->tasklet.func(execlists->tasklet.data);
19881981
1989− GEM_TRACE("%s\n", engine->name);
1982+ tasklet_enable(&execlists->tasklet);
1983+ GEM_TRACE("%s: depth->%d\n", engine->name,
1984+ atomic_read(&execlists->tasklet.count));
19901985 }
19911986
19921987 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
@@ -2066,8 +2061,7 @@ static int gen8_emit_bb_start(struct i915_request *rq, · 73 unmodified lines
20662061
20672062 /* FIXME(BDW): Address space and security selectors. */
20682063 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2069− (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
2070− (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
2064+ (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
20712065 *cs++ = lower_32_bits(offset);
20722066 *cs++ = upper_32_bits(offset);
20732067
@@ -2494,6 +2488,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) · 420 unmodified lines
24942488 static u32
24952489 make_rpcs(struct drm_i915_private *dev_priv)
24962490 {
2491+ bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
2492+ u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
2493+ u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
24972494 u32 rpcs = 0;
24982495
24992496 /*
@@ -2503,6 +2500,38 @@ make_rpcs(struct drm_i915_private *dev_priv) · 3 unmodified lines
25032500 if (INTEL_GEN(dev_priv) < 9)
25042501 return 0;
25052502
2503+ /*
2504+ * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
2505+ * wide and Icelake has up to eight subslices, specfial programming is
2506+ * needed in order to correctly enable all subslices.
2507+ *
2508+ * According to documentation software must consider the configuration
2509+ * as 2x4x8 and hardware will translate this to 1x8x8.
2510+ *
2511+ * Furthemore, even though SScount is three bits, maximum documented
2512+ * value for it is four. From this some rules/restrictions follow:
2513+ *
2514+ * 1.
2515+ * If enabled subslice count is greater than four, two whole slices must
2516+ * be enabled instead.
2517+ *
2518+ * 2.
2519+ * When more than one slice is enabled, hardware ignores the subslice
2520+ * count altogether.
2521+ *
2522+ * From these restrictions it follows that it is not possible to enable
2523+ * a count of subslices between the SScount maximum of four restriction,
2524+ * and the maximum available number on a particular SKU. Either all
2525+ * subslices are enabled, or a count between one and four on the first
2526+ * slice.
2527+ */
2528+ if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) {
2529+ GEM_BUG_ON(subslices & 1);
2530+
2531+ subslice_pg = false;
2532+ slices *= 2;
2533+ }
2534+
25062535 /*
25072536 * Starting in Gen9, render power gating can leave
25082537 * slice/subslice/EU in a partially enabled state. We
@@ -2510,24 +2539,50 @@ make_rpcs(struct drm_i915_private *dev_priv) · 1 unmodified line
25102539 * enablement.
25112540 */
25122541 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2513− rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2514− rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
2515− GEN8_RPCS_S_CNT_SHIFT;
2516− rpcs |= GEN8_RPCS_ENABLE;
2542+ u32 mask, val = slices;
2543+
2544+ if (INTEL_GEN(dev_priv) >= 11) {
2545+ mask = GEN11_RPCS_S_CNT_MASK;
2546+ val <<= GEN11_RPCS_S_CNT_SHIFT;
2547+ } else {
2548+ mask = GEN8_RPCS_S_CNT_MASK;
2549+ val <<= GEN8_RPCS_S_CNT_SHIFT;
2550+ }
2551+
2552+ GEM_BUG_ON(val & ~mask);
2553+ val &= mask;
2554+
2555+ rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
25172556 }
25182557
2519− if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
2520− rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2521− rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
2522− GEN8_RPCS_SS_CNT_SHIFT;
2523− rpcs |= GEN8_RPCS_ENABLE;
2558+ if (subslice_pg) {
2559+ u32 val = subslices;
2560+
2561+ val <<= GEN8_RPCS_SS_CNT_SHIFT;
2562+
2563+ GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
2564+ val &= GEN8_RPCS_SS_CNT_MASK;
2565+
2566+ rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
25242567 }
25252568
25262569 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2527− rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2528− GEN8_RPCS_EU_MIN_SHIFT;
2529− rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2530− GEN8_RPCS_EU_MAX_SHIFT;
2570+ u32 val;
2571+
2572+ val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2573+ GEN8_RPCS_EU_MIN_SHIFT;
2574+ GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
2575+ val &= GEN8_RPCS_EU_MIN_MASK;
2576+
2577+ rpcs |= val;
2578+
2579+ val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2580+ GEN8_RPCS_EU_MAX_SHIFT;
2581+ GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
2582+ val &= GEN8_RPCS_EU_MAX_MASK;
2583+
2584+ rpcs |= val;
2585+
25312586 rpcs |= GEN8_RPCS_ENABLE;
25322587 }
25332588
@@ -2584,11 +2639,13 @@ static void execlists_init_reg_state(u32 *regs, · 50 unmodified lines
25842639 MI_LRI_FORCE_POSTED;
25852640
25862641 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2587− _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2588− CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT) |
2589− _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2590− (HAS_RESOURCE_STREAMER(dev_priv) ?
2591− CTX_CTRL_RS_CTX_ENABLE : 0)));
2642+ _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2643+ _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2644+ if (INTEL_GEN(dev_priv) < 11) {
2645+ regs[CTX_CONTEXT_CONTROL + 1] |=
2646+ _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2647+ CTX_CTRL_RS_CTX_ENABLE);
2648+ }
25922649 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
25932650 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
25942651 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
@@ -2654,6 +2711,10 @@ static void execlists_init_reg_state(u32 *regs, · 59 unmodified lines
26542711
26552712 i915_oa_init_reg_state(engine, ctx, regs);
26562713 }
2714+
2715+ regs[CTX_END] = MI_BATCH_BUFFER_END;
2716+ if (INTEL_GEN(dev_priv) >= 10)
2717+ regs[CTX_END] |= BIT(0);
26572718 }
26582719
26592720 static int
drivers/gpu/drm/i915/intel_lrc.h+0−2
@@ -27,8 +27,6 @@ · 26 unmodified lines
2727 #include "intel_ringbuffer.h"
2828 #include "i915_gem_context.h"
2929
30−#define GEN8_LR_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT
31−
3230 /* Execlists regs */
3331 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
3432 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
drivers/gpu/drm/i915/intel_lrc_reg.h+1−1
@@ -37,7 +37,7 @@ · 36 unmodified lines
3737 #define CTX_PDP0_LDW 0x32
3838 #define CTX_LRI_HEADER_2 0x41
3939 #define CTX_R_PWR_CLK_STATE 0x42
40−#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
40+#define CTX_END 0x44
4141
4242 #define CTX_REG(reg_state, pos, reg, val) do { \
4343 u32 *reg_state__ = (reg_state); \
drivers/gpu/drm/i915/intel_mocs.c+3−8
@@ -232,20 +232,17 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index) · 231 unmodified lines
232232 *
233233 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
234234 * given table starting at the given address.
235− *
236− * Return: 0 on success, otherwise the error status.
237235 */
238−int intel_mocs_init_engine(struct intel_engine_cs *engine)
236+void intel_mocs_init_engine(struct intel_engine_cs *engine)
239237 {
240238 struct drm_i915_private *dev_priv = engine->i915;
241239 struct drm_i915_mocs_table table;
242240 unsigned int index;
243241
244242 if (!get_mocs_settings(dev_priv, &table))
245− return 0;
243+ return;
246244
247− if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES))
248− return -ENODEV;
245+ GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES);
249246
250247 for (index = 0; index < table.size; index++)
251248 I915_WRITE(mocs_register(engine->id, index),
@@ -262,8 +259,6 @@ int intel_mocs_init_engine(struct intel_engine_cs *engine) · 10 unmodified lines
262259 for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
263260 I915_WRITE(mocs_register(engine->id, index),
264261 table.table[0].control_value);
265−
266− return 0;
267262 }
268263
269264 /**
drivers/gpu/drm/i915/intel_mocs.h+1−1
@@ -54,6 +54,6 @@ · 53 unmodified lines
5454
5555 int intel_rcs_context_init_mocs(struct i915_request *rq);
5656 void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
57−int intel_mocs_init_engine(struct intel_engine_cs *engine);
57+void intel_mocs_init_engine(struct intel_engine_cs *engine);
5858
5959 #endif
drivers/gpu/drm/i915/intel_pm.c+62−39
@@ -26,6 +26,7 @@ · 25 unmodified lines
2626 */
2727
2828 #include <linux/cpufreq.h>
29+#include <linux/pm_runtime.h>
2930 #include <drm/drm_plane_helper.h>
3031 #include "i915_drv.h"
3132 #include "intel_drv.h"
@@ -2942,8 +2943,8 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, · 2910 unmodified lines
29422943 unsigned int latency = wm[level];
29432944
29442945 if (latency == 0) {
2945− DRM_ERROR("%s WM%d latency not provided\n",
2946− name, level);
2946+ DRM_DEBUG_KMS("%s WM%d latency not provided\n",
2947+ name, level);
29472948 continue;
29482949 }
29492950
@@ -3771,11 +3772,11 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) · 821 unmodified lines
37713772 return true;
37723773 }
37733774
3774−static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
3775− const struct intel_crtc_state *cstate,
3776− const unsigned int total_data_rate,
3777− const int num_active,
3778− struct skl_ddb_allocation *ddb)
3775+static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
3776+ const struct intel_crtc_state *cstate,
3777+ const unsigned int total_data_rate,
3778+ const int num_active,
3779+ struct skl_ddb_allocation *ddb)
37793780 {
37803781 const struct drm_display_mode *adjusted_mode;
37813782 u64 total_data_bw;
@@ -3814,8 +3815,12 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, · 32 unmodified lines
38143815 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
38153816 struct drm_i915_private *dev_priv = to_i915(dev);
38163817 struct drm_crtc *for_crtc = cstate->base.crtc;
3817− unsigned int pipe_size, ddb_size;
3818− int nth_active_pipe;
3818+ const struct drm_crtc_state *crtc_state;
3819+ const struct drm_crtc *crtc;
3820+ u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
3821+ enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
3822+ u16 ddb_size;
3823+ u32 i;
38193824
38203825 if (WARN_ON(!state) || !cstate->base.active) {
38213826 alloc->start = 0;
@@ -3833,14 +3838,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, · 11 unmodified lines
38333838 *num_active, ddb);
38343839
38353840 /*
3836− * If the state doesn't change the active CRTC's, then there's
3837− * no need to recalculate; the existing pipe allocation limits
3838− * should remain unchanged. Note that we're safe from racing
3839− * commits since any racing commit that changes the active CRTC
3840− * list would need to grab _all_ crtc locks, including the one
3841− * we currently hold.
3841+ * If the state doesn't change the active CRTC's or there is no
3842+ * modeset request, then there's no need to recalculate;
3843+ * the existing pipe allocation limits should remain unchanged.
3844+ * Note that we're safe from racing commits since any racing commit
3845+ * that changes the active CRTC list or do modeset would need to
3846+ * grab _all_ crtc locks, including the one we currently hold.
38423847 */
3843− if (!intel_state->active_pipe_changes) {
3848+ if (!intel_state->active_pipe_changes && !intel_state->modeset) {
38443849 /*
38453850 * alloc may be cleared by clear_intel_crtc_state,
38463851 * copy from old state to be sure
@@ -3849,11 +3854,32 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, · 2 unmodified lines
38493854 return;
38503855 }
38513856
3852− nth_active_pipe = hweight32(intel_state->active_crtcs &
3853− (drm_crtc_mask(for_crtc) - 1));
3854− pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3855− alloc->start = nth_active_pipe * ddb_size / *num_active;
3856− alloc->end = alloc->start + pipe_size;
3857+ /*
3858+ * Watermark/ddb requirement highly depends upon width of the
3859+ * framebuffer, So instead of allocating DDB equally among pipes
3860+ * distribute DDB based on resolution/width of the display.
3861+ */
3862+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3863+ const struct drm_display_mode *adjusted_mode;
3864+ int hdisplay, vdisplay;
3865+ enum pipe pipe;
3866+
3867+ if (!crtc_state->enable)
3868+ continue;
3869+
3870+ pipe = to_intel_crtc(crtc)->pipe;
3871+ adjusted_mode = &crtc_state->adjusted_mode;
3872+ drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
3873+ total_width += hdisplay;
3874+
3875+ if (pipe < for_pipe)
3876+ width_before_pipe += hdisplay;
3877+ else if (pipe == for_pipe)
3878+ pipe_width = hdisplay;
3879+ }
3880+
3881+ alloc->start = ddb_size * width_before_pipe / total_width;
3882+ alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
38573883 }
38583884
38593885 static unsigned int skl_cursor_allocation(int num_active)
@@ -3909,7 +3935,12 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, · 49 unmodified lines
39093935 val & PLANE_CTL_ALPHA_MASK);
39103936
39113937 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3912− val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
3938+ /*
3939+ * FIXME: add proper NV12 support for ICL. Avoid reading unclaimed
3940+ * registers for now.
3941+ */
3942+ if (INTEL_GEN(dev_priv) < 11)
3943+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
39133944
39143945 if (fourcc == DRM_FORMAT_NV12) {
39153946 skl_ddb_entry_init_from_hw(dev_priv,
@@ -4977,6 +5008,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc, · 1061 unmodified lines
49775008
49785009 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
49795010 &ddb->plane[pipe][plane_id]);
5011+ /* FIXME: add proper NV12 support for ICL. */
49805012 if (INTEL_GEN(dev_priv) >= 11)
49815013 return skl_ddb_entry_write(dev_priv,
49825014 PLANE_BUF_CFG(pipe, plane_id),
@@ -5141,17 +5173,6 @@ skl_compute_ddb(struct drm_atomic_state *state) · 158 unmodified lines
51415173 return 0;
51425174 }
51435175
5144−static void
5145−skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
5146− struct skl_ddb_values *src,
5147− enum pipe pipe)
5148−{
5149− memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
5150− sizeof(dst->ddb.uv_plane[pipe]));
5151− memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
5152− sizeof(dst->ddb.plane[pipe]));
5153−}
5154−
51555176 static void
51565177 skl_print_wm_changes(const struct drm_atomic_state *state)
51575178 {
@@ -5259,7 +5280,7 @@ skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed) · 101 unmodified lines
52595280 * any other display updates race with this transaction, so we need
52605281 * to grab the lock on *all* CRTC's.
52615282 */
5262− if (intel_state->active_pipe_changes) {
5283+ if (intel_state->active_pipe_changes || intel_state->modeset) {
52635284 realloc_pipes = ~0;
52645285 intel_state->wm_results.dirty_pipes = ~0;
52655286 }
@@ -5381,7 +5402,10 @@ static void skl_initial_wm(struct intel_atomic_state *state, · 115 unmodified lines
53815402 if (cstate->base.active_changed)
53825403 skl_atomic_update_crtc_wm(state, cstate);
53835404
5384− skl_copy_ddb_for_pipe(hw_vals, results, pipe);
5405+ memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
5406+ sizeof(hw_vals->ddb.uv_plane[pipe]));
5407+ memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
5408+ sizeof(hw_vals->ddb.plane[pipe]));
53855409
53865410 mutex_unlock(&dev_priv->wm.wm_mutex);
53875411 }
@@ -6379,7 +6403,6 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) · 991 unmodified lines
63796403 new_power = HIGH_POWER;
63806404 rps_set_power(dev_priv, new_power);
63816405 mutex_unlock(&rps->power.mutex);
6382− rps->last_adj = 0;
63836406 }
63846407
63856408 void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive)
@@ -8159,7 +8182,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) · 1773 unmodified lines
81598182 */
81608183 if (!sanitize_rc6(dev_priv)) {
81618184 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
8162− intel_runtime_pm_get(dev_priv);
8185+ pm_runtime_get(&dev_priv->drm.pdev->dev);
81638186 }
81648187
81658188 mutex_lock(&dev_priv->pcu_lock);
@@ -8211,7 +8234,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) · 45 unmodified lines
82118234 valleyview_cleanup_gt_powersave(dev_priv);
82128235
82138236 if (!HAS_RC6(dev_priv))
8214− intel_runtime_pm_put(dev_priv);
8237+ pm_runtime_put(&dev_priv->drm.pdev->dev);
82158238 }
82168239
82178240 /**
@@ -8238,7 +8261,7 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) · 20 unmodified lines
82388261
82398262 if (INTEL_GEN(dev_priv) >= 11)
82408263 gen11_reset_rps_interrupts(dev_priv);
8241− else
8264+ else if (INTEL_GEN(dev_priv) >= 6)
82428265 gen6_reset_rps_interrupts(dev_priv);
82438266 }
82448267
drivers/gpu/drm/i915/intel_psr.c+192−85
@@ -56,7 +56,30 @@ · 55 unmodified lines
5656 #include "intel_drv.h"
5757 #include "i915_drv.h"
5858
59−void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
59+static bool psr_global_enabled(u32 debug)
60+{
61+ switch (debug & I915_PSR_DEBUG_MODE_MASK) {
62+ case I915_PSR_DEBUG_DEFAULT:
63+ return i915_modparams.enable_psr;
64+ case I915_PSR_DEBUG_DISABLE:
65+ return false;
66+ default:
67+ return true;
68+ }
69+}
70+
71+static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
72+ const struct intel_crtc_state *crtc_state)
73+{
74+ switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
75+ case I915_PSR_DEBUG_FORCE_PSR1:
76+ return false;
77+ default:
78+ return crtc_state->has_psr2;
79+ }
80+}
81+
82+void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
6083 {
6184 u32 debug_mask, mask;
6285
@@ -77,10 +100,9 @@ void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug) · 14 unmodified lines
77100 EDP_PSR_PRE_ENTRY(TRANSCODER_C);
78101 }
79102
80− if (debug)
103+ if (debug & I915_PSR_DEBUG_IRQ)
81104 mask |= debug_mask;
82105
83− WRITE_ONCE(dev_priv->psr.debug, debug);
84106 I915_WRITE(EDP_PSR_IMR, ~mask);
85107 }
86108
@@ -213,6 +235,9 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) · 126 unmodified lines
213235 dev_priv->psr.sink_sync_latency =
214236 intel_dp_get_sink_sync_latency(intel_dp);
215237
238+ WARN_ON(dev_priv->psr.dp);
239+ dev_priv->psr.dp = intel_dp;
240+
216241 if (INTEL_GEN(dev_priv) >= 9 &&
217242 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
218243 bool y_req = intel_dp->psr_dpcd[1] &
@@ -245,7 +270,7 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp, · 26 unmodified lines
245270 const struct intel_crtc_state *crtc_state)
246271 {
247272 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
248− struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
273+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
249274 struct edp_vsc_psr psr_vsc;
250275
251276 if (dev_priv->psr.psr2_enabled) {
@@ -275,8 +300,7 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp, · 23 unmodified lines
275300
276301 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
277302 {
278− struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
279− struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
303+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
280304 u32 aux_clock_divider, aux_ctl;
281305 int i;
282306 static const uint8_t aux_msg[] = {
@@ -309,9 +333,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) · 26 unmodified lines
309333
310334 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
311335 {
312− struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
313− struct drm_device *dev = dig_port->base.base.dev;
314− struct drm_i915_private *dev_priv = to_i915(dev);
336+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
315337 u8 dpcd_val = DP_PSR_ENABLE;
316338
317339 /* Enable ALPM at sink for psr2 */
@@ -332,9 +354,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) · 14 unmodified lines
332354
333355 static void hsw_activate_psr1(struct intel_dp *intel_dp)
334356 {
335− struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
336− struct drm_device *dev = dig_port->base.base.dev;
337− struct drm_i915_private *dev_priv = to_i915(dev);
357+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
338358 u32 max_sleep_time = 0x1f;
339359 u32 val = EDP_PSR_ENABLE;
340360
@@ -389,9 +409,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) · 48 unmodified lines
389409
390410 static void hsw_activate_psr2(struct intel_dp *intel_dp)
391411 {
392− struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
393− struct drm_device *dev = dig_port->base.base.dev;
394− struct drm_i915_private *dev_priv = to_i915(dev);
412+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
395413 u32 val;
396414
397415 /* Let's use 6 as the minimum to cover all known cases including the
@@ -427,8 +445,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) · 29 unmodified lines
427445 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
428446 struct intel_crtc_state *crtc_state)
429447 {
430− struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
431− struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
448+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
432449 int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
433450 int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
434451 int psr_max_h = 0, psr_max_v = 0;
@@ -463,7 +480,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, · 28 unmodified lines
463480 struct intel_crtc_state *crtc_state)
464481 {
465482 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
466− struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
483+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
467484 const struct drm_display_mode *adjusted_mode =
468485 &crtc_state->base.adjusted_mode;
469486 int psr_setup_time;
@@ -471,10 +488,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, · 1 unmodified line
471488 if (!CAN_PSR(dev_priv))
472489 return;
473490
474− if (!i915_modparams.enable_psr) {
475− DRM_DEBUG_KMS("PSR disable by flag\n");
491+ if (intel_dp != dev_priv->psr.dp)
476492 return;
477− }
478493
479494 /*
480495 * HSW spec explicitly says PSR is tied to port A.
@@ -517,14 +532,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, · 36 unmodified lines
517532
518533 crtc_state->has_psr = true;
519534 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
520− DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
521535 }
522536
523537 static void intel_psr_activate(struct intel_dp *intel_dp)
524538 {
525− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
526− struct drm_device *dev = intel_dig_port->base.base.dev;
527− struct drm_i915_private *dev_priv = to_i915(dev);
539+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
528540
529541 if (INTEL_GEN(dev_priv) >= 9)
530542 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
@@ -544,9 +556,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) · 13 unmodified lines
544556 static void intel_psr_enable_source(struct intel_dp *intel_dp,
545557 const struct intel_crtc_state *crtc_state)
546558 {
547− struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
548− struct drm_device *dev = dig_port->base.base.dev;
549− struct drm_i915_private *dev_priv = to_i915(dev);
559+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
550560 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
551561
552562 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
@@ -589,6 +599,24 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, · 36 unmodified lines
589599 }
590600 }
591601
602+static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
603+ const struct intel_crtc_state *crtc_state)
604+{
605+ struct intel_dp *intel_dp = dev_priv->psr.dp;
606+
607+ if (dev_priv->psr.enabled)
608+ return;
609+
610+ DRM_DEBUG_KMS("Enabling PSR%s\n",
611+ dev_priv->psr.psr2_enabled ? "2" : "1");
612+ intel_psr_setup_vsc(intel_dp, crtc_state);
613+ intel_psr_enable_sink(intel_dp);
614+ intel_psr_enable_source(intel_dp, crtc_state);
615+ dev_priv->psr.enabled = true;
616+
617+ intel_psr_activate(intel_dp);
618+}
619+
592620 /**
593621 * intel_psr_enable - Enable PSR
594622 * @intel_dp: Intel DP
@@ -599,9 +627,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, · 4 unmodified lines
599627 void intel_psr_enable(struct intel_dp *intel_dp,
600628 const struct intel_crtc_state *crtc_state)
601629 {
602− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
603− struct drm_device *dev = intel_dig_port->base.base.dev;
604− struct drm_i915_private *dev_priv = to_i915(dev);
630+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
605631
606632 if (!crtc_state->has_psr)
607633 return;
@@ -610,21 +636,21 @@ void intel_psr_enable(struct intel_dp *intel_dp, · 2 unmodified lines
610636 return;
611637
612638 WARN_ON(dev_priv->drrs.dp);
639+
613640 mutex_lock(&dev_priv->psr.lock);
614− if (dev_priv->psr.enabled) {
641+ if (dev_priv->psr.prepared) {
615642 DRM_DEBUG_KMS("PSR already in use\n");
616643 goto unlock;
617644 }
618645
619− dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
646+ dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
620647 dev_priv->psr.busy_frontbuffer_bits = 0;
648+ dev_priv->psr.prepared = true;
621649
622− intel_psr_setup_vsc(intel_dp, crtc_state);
623− intel_psr_enable_sink(intel_dp);
624− intel_psr_enable_source(intel_dp, crtc_state);
625− dev_priv->psr.enabled = intel_dp;
626−
627− intel_psr_activate(intel_dp);
650+ if (psr_global_enabled(dev_priv->psr.debug))
651+ intel_psr_enable_locked(dev_priv, crtc_state);
652+ else
653+ DRM_DEBUG_KMS("PSR disabled by flag\n");
628654
629655 unlock:
630656 mutex_unlock(&dev_priv->psr.lock);
@@ -633,9 +659,7 @@ unlock: · 2 unmodified lines
633659 static void
634660 intel_psr_disable_source(struct intel_dp *intel_dp)
635661 {
636− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
637− struct drm_device *dev = intel_dig_port->base.base.dev;
638− struct drm_i915_private *dev_priv = to_i915(dev);
662+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
639663
640664 if (dev_priv->psr.active) {
641665 i915_reg_t psr_status;
@@ -674,21 +698,21 @@ intel_psr_disable_source(struct intel_dp *intel_dp) · 32 unmodified lines
674698
675699 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
676700 {
677− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
678− struct drm_device *dev = intel_dig_port->base.base.dev;
679− struct drm_i915_private *dev_priv = to_i915(dev);
701+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
680702
681703 lockdep_assert_held(&dev_priv->psr.lock);
682704
683705 if (!dev_priv->psr.enabled)
684706 return;
685707
708+ DRM_DEBUG_KMS("Disabling PSR%s\n",
709+ dev_priv->psr.psr2_enabled ? "2" : "1");
686710 intel_psr_disable_source(intel_dp);
687711
688712 /* Disable PSR on Sink */
689713 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
690714
691− dev_priv->psr.enabled = NULL;
715+ dev_priv->psr.enabled = false;
692716 }
693717
694718 /**
@@ -701,9 +725,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) · 6 unmodified lines
701725 void intel_psr_disable(struct intel_dp *intel_dp,
702726 const struct intel_crtc_state *old_crtc_state)
703727 {
704− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
705− struct drm_device *dev = intel_dig_port->base.base.dev;
706− struct drm_i915_private *dev_priv = to_i915(dev);
728+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
707729
708730 if (!old_crtc_state->has_psr)
709731 return;
@@ -712,57 +734,61 @@ void intel_psr_disable(struct intel_dp *intel_dp, · 2 unmodified lines
712734 return;
713735
714736 mutex_lock(&dev_priv->psr.lock);
737+ if (!dev_priv->psr.prepared) {
738+ mutex_unlock(&dev_priv->psr.lock);
739+ return;
740+ }
741+
715742 intel_psr_disable_locked(intel_dp);
743+
744+ dev_priv->psr.prepared = false;
716745 mutex_unlock(&dev_priv->psr.lock);
717746 cancel_work_sync(&dev_priv->psr.work);
718747 }
719748
720−int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
749+/**
750+ * intel_psr_wait_for_idle - wait for PSR1 to idle
751+ * @new_crtc_state: new CRTC state
752+ * @out_value: PSR status in case of failure
753+ *
754+ * This function is expected to be called from pipe_update_start() where it is
755+ * not expected to race with PSR enable or disable.
756+ *
757+ * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
758+ */
759+int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
760+ u32 *out_value)
721761 {
722762 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
723763 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
724− i915_reg_t reg;
725− u32 mask;
726764
727− if (!new_crtc_state->has_psr)
765+ if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
728766 return 0;
729767
730− /*
731− * The sole user right now is intel_pipe_update_start(),
732− * which won't race with psr_enable/disable, which is
733− * where psr2_enabled is written to. So, we don't need
734− * to acquire the psr.lock. More importantly, we want the
735− * latency inside intel_pipe_update_start() to be as low
736− * as possible, so no need to acquire psr.lock when it is
737− * not needed and will induce latencies in the atomic
738− * update path.
739− */
740− if (dev_priv->psr.psr2_enabled) {
741− reg = EDP_PSR2_STATUS;
742− mask = EDP_PSR2_STATUS_STATE_MASK;
743− } else {
744− reg = EDP_PSR_STATUS;
745− mask = EDP_PSR_STATUS_STATE_MASK;
746− }
768+ /* FIXME: Update this for PSR2 if we need to wait for idle */
769+ if (READ_ONCE(dev_priv->psr.psr2_enabled))
770+ return 0;
747771
748772 /*
749− * Max time for PSR to idle = Inverse of the refresh rate +
750− * 6 ms of exit training time + 1.5 ms of aux channel
751− * handshake. 50 msec is defesive enough to cover everything.
773+ * From bspec: Panel Self Refresh (BDW+)
774+ * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
775+ * exit training time + 1.5 ms of aux channel handshake. 50 ms is
776+ * defensive enough to cover everything.
752777 */
753− return intel_wait_for_register(dev_priv, reg, mask,
754− EDP_PSR_STATUS_STATE_IDLE, 50);
778+
779+ return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
780+ EDP_PSR_STATUS_STATE_MASK,
781+ EDP_PSR_STATUS_STATE_IDLE, 2, 50,
782+ out_value);
755783 }
756784
757785 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
758786 {
759− struct intel_dp *intel_dp;
760787 i915_reg_t reg;
761788 u32 mask;
762789 int err;
763790
764− intel_dp = dev_priv->psr.enabled;
765− if (!intel_dp)
791+ if (!dev_priv->psr.enabled)
766792 return false;
767793
768794 if (dev_priv->psr.psr2_enabled) {
@@ -784,6 +810,89 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) · 15 unmodified lines
784810 return err == 0 && dev_priv->psr.enabled;
785811 }
786812
813+static bool switching_psr(struct drm_i915_private *dev_priv,
814+ struct intel_crtc_state *crtc_state,
815+ u32 mode)
816+{
817+ /* Can't switch psr state anyway if PSR2 is not supported. */
818+ if (!crtc_state || !crtc_state->has_psr2)
819+ return false;
820+
821+ if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1)
822+ return true;
823+
824+ if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1)
825+ return true;
826+
827+ return false;
828+}
829+
830+int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
831+ struct drm_modeset_acquire_ctx *ctx,
832+ u64 val)
833+{
834+ struct drm_device *dev = &dev_priv->drm;
835+ struct drm_connector_state *conn_state;
836+ struct intel_crtc_state *crtc_state = NULL;
837+ struct drm_crtc_commit *commit;
838+ struct drm_crtc *crtc;
839+ struct intel_dp *dp;
840+ int ret;
841+ bool enable;
842+ u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
843+
844+ if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
845+ mode > I915_PSR_DEBUG_FORCE_PSR1) {
846+ DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
847+ return -EINVAL;
848+ }
849+
850+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx);
851+ if (ret)
852+ return ret;
853+
854+ /* dev_priv->psr.dp should be set once and then never touched again. */
855+ dp = READ_ONCE(dev_priv->psr.dp);
856+ conn_state = dp->attached_connector->base.state;
857+ crtc = conn_state->crtc;
858+ if (crtc) {
859+ ret = drm_modeset_lock(&crtc->mutex, ctx);
860+ if (ret)
861+ return ret;
862+
863+ crtc_state = to_intel_crtc_state(crtc->state);
864+ commit = crtc_state->base.commit;
865+ } else {
866+ commit = conn_state->commit;
867+ }
868+ if (commit) {
869+ ret = wait_for_completion_interruptible(&commit->hw_done);
870+ if (ret)
871+ return ret;
872+ }
873+
874+ ret = mutex_lock_interruptible(&dev_priv->psr.lock);
875+ if (ret)
876+ return ret;
877+
878+ enable = psr_global_enabled(val);
879+
880+ if (!enable || switching_psr(dev_priv, crtc_state, mode))
881+ intel_psr_disable_locked(dev_priv->psr.dp);
882+
883+ dev_priv->psr.debug = val;
884+ if (crtc)
885+ dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
886+
887+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
888+
889+ if (dev_priv->psr.prepared && enable)
890+ intel_psr_enable_locked(dev_priv, crtc_state);
891+
892+ mutex_unlock(&dev_priv->psr.lock);
893+ return ret;
894+}
895+
787896 static void intel_psr_work(struct work_struct *work)
788897 {
789898 struct drm_i915_private *dev_priv =
@@ -811,7 +920,7 @@ static void intel_psr_work(struct work_struct *work) · 21 unmodified lines
811920 if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
812921 goto unlock;
813922
814− intel_psr_activate(dev_priv->psr.enabled);
923+ intel_psr_activate(dev_priv->psr.dp);
815924 unlock:
816925 mutex_unlock(&dev_priv->psr.lock);
817926 }
@@ -866,7 +975,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, · 48 unmodified lines
866975 return;
867976 }
868977
869− crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
978+ crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
870979 pipe = to_intel_crtc(crtc)->pipe;
871980
872981 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
@@ -909,7 +1018,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, · 36 unmodified lines
9091018 return;
9101019 }
9111020
912− crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1021+ crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
9131022 pipe = to_intel_crtc(crtc)->pipe;
9141023
9151024 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
@@ -977,9 +1086,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv) · 61 unmodified lines
9771086
9781087 void intel_psr_short_pulse(struct intel_dp *intel_dp)
9791088 {
980− struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
981− struct drm_device *dev = intel_dig_port->base.base.dev;
982− struct drm_i915_private *dev_priv = to_i915(dev);
1089+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9831090 struct i915_psr *psr = &dev_priv->psr;
9841091 u8 val;
9851092 const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
@@ -991,7 +1098,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) · 5 unmodified lines
9911098
9921099 mutex_lock(&psr->lock);
9931100
994− if (psr->enabled != intel_dp)
1101+ if (!psr->enabled || psr->dp != intel_dp)
9951102 goto exit;
9961103
9971104 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
drivers/gpu/drm/i915/intel_ringbuffer.c+56−54
@@ -344,11 +344,14 @@ gen7_render_ring_flush(struct i915_request *rq, u32 mode) · 343 unmodified lines
344344 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
345345 {
346346 struct drm_i915_private *dev_priv = engine->i915;
347+ struct page *page = virt_to_page(engine->status_page.page_addr);
348+ phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
347349 u32 addr;
348350
349− addr = dev_priv->status_page_dmah->busaddr;
351+ addr = lower_32_bits(phys);
350352 if (INTEL_GEN(dev_priv) >= 4)
351− addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
353+ addr |= (phys >> 28) & 0xf0;
354+
352355 I915_WRITE(HWS_PGA, addr);
353356 }
354357
@@ -537,6 +540,8 @@ static int init_ring_common(struct intel_engine_cs *engine) · 182 unmodified lines
537540 if (INTEL_GEN(dev_priv) > 2)
538541 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
539542
543+ /* Papering over lost _interrupts_ immediately following the restart */
544+ intel_engine_wakeup(engine);
540545 out:
541546 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
542547
@@ -1013,24 +1018,22 @@ i915_emit_bb_start(struct i915_request *rq, · 470 unmodified lines
10131018 return 0;
10141019 }
10151020
1016−
1017−
1018−int intel_ring_pin(struct intel_ring *ring,
1019− struct drm_i915_private *i915,
1020− unsigned int offset_bias)
1021+int intel_ring_pin(struct intel_ring *ring)
10211022 {
1022− enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
10231023 struct i915_vma *vma = ring->vma;
1024+ enum i915_map_type map =
1025+ HAS_LLC(vma->vm->i915) ? I915_MAP_WB : I915_MAP_WC;
10241026 unsigned int flags;
10251027 void *addr;
10261028 int ret;
10271029
10281030 GEM_BUG_ON(ring->vaddr);
10291031
1030−
10311032 flags = PIN_GLOBAL;
1032− if (offset_bias)
1033− flags |= PIN_OFFSET_BIAS | offset_bias;
1033+
1034+ /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1035+ flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1036+
10341037 if (vma->obj->stolen)
10351038 flags |= PIN_MAPPABLE;
10361039 else
@@ -1045,7 +1048,7 @@ int intel_ring_pin(struct intel_ring *ring, · 8 unmodified lines
10451048 return ret;
10461049 }
10471050
1048− ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1051+ ret = i915_vma_pin(vma, 0, 0, flags);
10491052 if (unlikely(ret))
10501053 return ret;
10511054
@@ -1230,8 +1233,7 @@ static int __context_pin(struct intel_context *ce) · 178 unmodified lines
12301233 return err;
12311234 }
12321235
1233− err = i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1234− PIN_GLOBAL | PIN_HIGH);
1236+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
12351237 if (err)
12361238 return err;
12371239
@@ -1419,8 +1421,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) · 181 unmodified lines
14191421 goto err;
14201422 }
14211423
1422− /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1423− err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1424+ err = intel_ring_pin(ring);
14241425 if (err)
14251426 goto err_ring;
14261427
@@ -1706,9 +1707,29 @@ static int switch_context(struct i915_request *rq) · 279 unmodified lines
17061707 }
17071708
17081709 if (ppgtt) {
1710+ ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1711+ if (ret)
1712+ goto err_mm;
1713+
17091714 ret = flush_pd_dir(rq);
17101715 if (ret)
17111716 goto err_mm;
1717+
1718+ /*
1719+ * Not only do we need a full barrier (post-sync write) after
1720+ * invalidating the TLBs, but we need to wait a little bit
1721+ * longer. Whether this is merely delaying us, or the
1722+ * subsequent flush is a key part of serialising with the
1723+ * post-sync op, this extra pass appears vital before a
1724+ * mm switch!
1725+ */
1726+ ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1727+ if (ret)
1728+ goto err_mm;
1729+
1730+ ret = engine->emit_flush(rq, EMIT_FLUSH);
1731+ if (ret)
1732+ goto err_mm;
17121733 }
17131734
17141735 if (ctx->remap_slice) {
@@ -1946,7 +1967,7 @@ static void gen6_bsd_submit_request(struct i915_request *request) · 231 unmodified lines
19461967 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
19471968 }
19481969
1949−static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
1970+static int mi_flush_dw(struct i915_request *rq, u32 flags)
19501971 {
19511972 u32 cmd, *cs;
19521973
@@ -1956,7 +1977,8 @@ static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) · 3 unmodified lines
19561977
19571978 cmd = MI_FLUSH_DW;
19581979
1959− /* We always require a command barrier so that subsequent
1980+ /*
1981+ * We always require a command barrier so that subsequent
19601982 * commands, such as breadcrumb interrupts, are strictly ordered
19611983 * wrt the contents of the write cache being flushed to memory
19621984 * (and thus being coherent from the CPU).
@@ -1964,22 +1986,33 @@ static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) · 1 unmodified line
19641986 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
19651987
19661988 /*
1967− * Bspec vol 1c.5 - video engine command streamer:
1989+ * Bspec vol 1c.3 - blitter engine command streamer:
19681990 * "If ENABLED, all TLBs will be invalidated once the flush
19691991 * operation is complete. This bit is only valid when the
19701992 * Post-Sync Operation field is a value of 1h or 3h."
19711993 */
1972− if (mode & EMIT_INVALIDATE)
1973− cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1994+ cmd |= flags;
19741995
19751996 *cs++ = cmd;
19761997 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
19771998 *cs++ = 0;
19781999 *cs++ = MI_NOOP;
2000+
19792001 intel_ring_advance(rq, cs);
2002+
19802003 return 0;
19812004 }
19822005
2006+static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
2007+{
2008+ return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
2009+}
2010+
2011+static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
2012+{
2013+ return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
2014+}
2015+
19832016 static int
19842017 hsw_emit_bb_start(struct i915_request *rq,
19852018 u64 offset, u32 len,
@@ -1992,9 +2025,7 @@ hsw_emit_bb_start(struct i915_request *rq, · 6 unmodified lines
19922025 return PTR_ERR(cs);
19932026
19942027 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1995− 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
1996− (dispatch_flags & I915_DISPATCH_RS ?
1997− MI_BATCH_RESOURCE_STREAMER : 0);
2028+ 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW);
19982029 /* bit0-7 is the length on GEN6+ */
19992030 *cs++ = offset;
20002031 intel_ring_advance(rq, cs);
@@ -2026,36 +2057,7 @@ gen6_emit_bb_start(struct i915_request *rq, · 25 unmodified lines
20262057
20272058 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
20282059 {
2029− u32 cmd, *cs;
2030−
2031− cs = intel_ring_begin(rq, 4);
2032− if (IS_ERR(cs))
2033− return PTR_ERR(cs);
2034−
2035− cmd = MI_FLUSH_DW;
2036−
2037− /* We always require a command barrier so that subsequent
2038− * commands, such as breadcrumb interrupts, are strictly ordered
2039− * wrt the contents of the write cache being flushed to memory
2040− * (and thus being coherent from the CPU).
2041− */
2042− cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2043−
2044− /*
2045− * Bspec vol 1c.3 - blitter engine command streamer:
2046− * "If ENABLED, all TLBs will be invalidated once the flush
2047− * operation is complete. This bit is only valid when the
2048− * Post-Sync Operation field is a value of 1h or 3h."
2049− */
2050− if (mode & EMIT_INVALIDATE)
2051− cmd |= MI_INVALIDATE_TLB;
2052− *cs++ = cmd;
2053− *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2054− *cs++ = 0;
2055− *cs++ = MI_NOOP;
2056− intel_ring_advance(rq, cs);
2057−
2058− return 0;
2060+ return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
20592061 }
20602062
20612063 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
drivers/gpu/drm/i915/intel_ringbuffer.h+29−10
@@ -474,7 +474,6 @@ struct intel_engine_cs { · 473 unmodified lines
474474 unsigned int dispatch_flags);
475475 #define I915_DISPATCH_SECURE BIT(0)
476476 #define I915_DISPATCH_PINNED BIT(1)
477−#define I915_DISPATCH_RS BIT(2)
478477 void (*emit_breadcrumb)(struct i915_request *rq, u32 *cs);
479478 int emit_breadcrumb_sz;
480479
@@ -797,9 +796,7 @@ struct intel_ring * · 316 unmodified lines
797796 intel_engine_create_ring(struct intel_engine_cs *engine,
798797 struct i915_timeline *timeline,
799798 int size);
800−int intel_ring_pin(struct intel_ring *ring,
801− struct drm_i915_private *i915,
802− unsigned int offset_bias);
799+int intel_ring_pin(struct intel_ring *ring);
803800 void intel_ring_reset(struct intel_ring *ring, u32 tail);
804801 unsigned int intel_ring_update_space(struct intel_ring *ring);
805802 void intel_ring_unpin(struct intel_ring *ring);
@@ -909,18 +906,15 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); · 103 unmodified lines
909906 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
910907
911908 int intel_engine_stop_cs(struct intel_engine_cs *engine);
909+void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
912910
913911 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
914912 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
915913
916−static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
917−{
918− return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
919−}
920−
921914 static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
922915 {
923− /* We are only peeking at the tail of the submit queue (and not the
916+ /*
917+ * We are only peeking at the tail of the submit queue (and not the
924918 * queue itself) in order to gain a hint as to the current active
925919 * state of the engine. Callers are not expected to be taking
926920 * engine->timeline->lock, nor are they expected to be concerned
@@ -930,6 +924,31 @@ static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine) · 3 unmodified lines
930924 return READ_ONCE(engine->timeline.seqno);
931925 }
932926
927+static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
928+{
929+ return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
930+}
931+
932+static inline bool intel_engine_signaled(struct intel_engine_cs *engine,
933+ u32 seqno)
934+{
935+ return i915_seqno_passed(intel_engine_get_seqno(engine), seqno);
936+}
937+
938+static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
939+ u32 seqno)
940+{
941+ GEM_BUG_ON(!seqno);
942+ return intel_engine_signaled(engine, seqno);
943+}
944+
945+static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
946+ u32 seqno)
947+{
948+ GEM_BUG_ON(!seqno);
949+ return intel_engine_signaled(engine, seqno - 1);
950+}
951+
933952 void intel_engine_get_instdone(struct intel_engine_cs *engine,
934953 struct intel_instdone *instdone);
935954
drivers/gpu/drm/i915/intel_runtime_pm.c+674−329
@@ -52,10 +52,6 @@ · 51 unmodified lines
5252 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
5353 enum i915_power_well_id power_well_id);
5454
55−static struct i915_power_well *
56−lookup_power_well(struct drm_i915_private *dev_priv,
57− enum i915_power_well_id power_well_id);
58−
5955 const char *
6056 intel_display_power_domain_str(enum intel_display_power_domain domain)
6157 {
@@ -159,17 +155,17 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 97 unmodified lines
159155 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
160156 struct i915_power_well *power_well)
161157 {
162− DRM_DEBUG_KMS("enabling %s\n", power_well->name);
163− power_well->ops->enable(dev_priv, power_well);
158+ DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
159+ power_well->desc->ops->enable(dev_priv, power_well);
164160 power_well->hw_enabled = true;
165161 }
166162
167163 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
168164 struct i915_power_well *power_well)
169165 {
170− DRM_DEBUG_KMS("disabling %s\n", power_well->name);
166+ DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
171167 power_well->hw_enabled = false;
172− power_well->ops->disable(dev_priv, power_well);
168+ power_well->desc->ops->disable(dev_priv, power_well);
173169 }
174170
175171 static void intel_power_well_get(struct drm_i915_private *dev_priv,
@@ -183,7 +179,7 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv, · 7 unmodified lines
183179 struct i915_power_well *power_well)
184180 {
185181 WARN(!power_well->count, "Use count on power well %s is already zero",
186− power_well->name);
182+ power_well->desc->name);
187183
188184 if (!--power_well->count)
189185 intel_power_well_disable(dev_priv, power_well);
@@ -213,7 +209,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, · 23 unmodified lines
213209 is_enabled = true;
214210
215211 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
216− if (power_well->always_on)
212+ if (power_well->desc->always_on)
217213 continue;
218214
219215 if (!power_well->hw_enabled) {
@@ -257,30 +253,6 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, · 37 unmodified lines
257253 return ret;
258254 }
259255
260−/**
261− * intel_display_set_init_power - set the initial power domain state
262− * @dev_priv: i915 device instance
263− * @enable: whether to enable or disable the initial power domain state
264− *
265− * For simplicity our driver load/unload and system suspend/resume code assumes
266− * that all power domains are always enabled. This functions controls the state
267− * of this little hack. While the initial power domain state is enabled runtime
268− * pm is effectively disabled.
269− */
270−void intel_display_set_init_power(struct drm_i915_private *dev_priv,
271− bool enable)
272−{
273− if (dev_priv->power_domains.init_power_on == enable)
274− return;
275−
276− if (enable)
277− intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
278− else
279− intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
280−
281− dev_priv->power_domains.init_power_on = enable;
282−}
283−
284256 /*
285257 * Starting with Haswell, we have a "Power Down Well" that can be turned off
286258 * when not needed anymore. We have 4 registers that can request the power well
@@ -323,26 +295,29 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, · 36 unmodified lines
323295 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
324296 struct i915_power_well *power_well)
325297 {
326− enum i915_power_well_id id = power_well->id;
298+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
299+ int pw_idx = power_well->desc->hsw.idx;
327300
328301 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
329302 WARN_ON(intel_wait_for_register(dev_priv,
330− HSW_PWR_WELL_CTL_DRIVER(id),
331− HSW_PWR_WELL_CTL_STATE(id),
332− HSW_PWR_WELL_CTL_STATE(id),
303+ regs->driver,
304+ HSW_PWR_WELL_CTL_STATE(pw_idx),
305+ HSW_PWR_WELL_CTL_STATE(pw_idx),
333306 1));
334307 }
335308
336309 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
337− enum i915_power_well_id id)
310+ const struct i915_power_well_regs *regs,
311+ int pw_idx)
338312 {
339− u32 req_mask = HSW_PWR_WELL_CTL_REQ(id);
313+ u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
340314 u32 ret;
341315
342− ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0;
343− ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0;
344− ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0;
345− ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0;
316+ ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
317+ ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
318+ if (regs->kvmr.reg)
319+ ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
320+ ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
346321
347322 return ret;
348323 }
@@ -350,7 +325,8 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, · 1 unmodified line
350325 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
351326 struct i915_power_well *power_well)
352327 {
353− enum i915_power_well_id id = power_well->id;
328+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
329+ int pw_idx = power_well->desc->hsw.idx;
354330 bool disabled;
355331 u32 reqs;
356332
@@ -363,14 +339,14 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, · 6 unmodified lines
363339 * Skip the wait in case any of the request bits are set and print a
364340 * diagnostic message.
365341 */
366− wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &
367− HSW_PWR_WELL_CTL_STATE(id))) ||
368− (reqs = hsw_power_well_requesters(dev_priv, id)), 1);
342+ wait_for((disabled = !(I915_READ(regs->driver) &
343+ HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
344+ (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
369345 if (disabled)
370346 return;
371347
372348 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
373− power_well->name,
349+ power_well->desc->name,
374350 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
375351 }
376352
@@ -386,14 +362,15 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, · 9 unmodified lines
386362 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
387363 struct i915_power_well *power_well)
388364 {
389− enum i915_power_well_id id = power_well->id;
390− bool wait_fuses = power_well->hsw.has_fuses;
365+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
366+ int pw_idx = power_well->desc->hsw.idx;
367+ bool wait_fuses = power_well->desc->hsw.has_fuses;
391368 enum skl_power_gate uninitialized_var(pg);
392369 u32 val;
393370
394371 if (wait_fuses) {
395− pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_TO_PG(id) :
396− SKL_PW_TO_PG(id);
372+ pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
373+ SKL_PW_CTL_IDX_TO_PG(pw_idx);
397374 /*
398375 * For PW1 we have to wait both for the PW0/PG0 fuse state
399376 * before enabling the power well and PW1/PG1's own fuse
@@ -405,52 +382,55 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, · 5 unmodified lines
405382 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
406383 }
407384
408− val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
409− I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
385+ val = I915_READ(regs->driver);
386+ I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
410387 hsw_wait_for_power_well_enable(dev_priv, power_well);
411388
412389 /* Display WA #1178: cnl */
413390 if (IS_CANNONLAKE(dev_priv) &&
414− (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
415− id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) {
416− val = I915_READ(CNL_AUX_ANAOVRD1(id));
391+ pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
392+ pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
393+ val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
417394 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
418− I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
395+ I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
419396 }
420397
421398 if (wait_fuses)
422399 gen9_wait_for_power_well_fuses(dev_priv, pg);
423400
424− hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
425− power_well->hsw.has_vga);
401+ hsw_power_well_post_enable(dev_priv,
402+ power_well->desc->hsw.irq_pipe_mask,
403+ power_well->desc->hsw.has_vga);
426404 }
427405
428406 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
429407 struct i915_power_well *power_well)
430408 {
431− enum i915_power_well_id id = power_well->id;
409+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
410+ int pw_idx = power_well->desc->hsw.idx;
432411 u32 val;
433412
434− hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
413+ hsw_power_well_pre_disable(dev_priv,
414+ power_well->desc->hsw.irq_pipe_mask);
435415
436− val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
437− I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
438− val & ~HSW_PWR_WELL_CTL_REQ(id));
416+ val = I915_READ(regs->driver);
417+ I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
439418 hsw_wait_for_power_well_disable(dev_priv, power_well);
440419 }
441420
442−#define ICL_AUX_PW_TO_PORT(pw) ((pw) - ICL_DISP_PW_AUX_A)
421+#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
443422
444423 static void
445424 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
446425 struct i915_power_well *power_well)
447426 {
448− enum i915_power_well_id id = power_well->id;
449− enum port port = ICL_AUX_PW_TO_PORT(id);
427+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
428+ int pw_idx = power_well->desc->hsw.idx;
429+ enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
450430 u32 val;
451431
452− val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
453− I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
432+ val = I915_READ(regs->driver);
433+ I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
454434
455435 val = I915_READ(ICL_PORT_CL_DW12(port));
456436 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
@@ -462,16 +442,16 @@ static void · 5 unmodified lines
462442 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
463443 struct i915_power_well *power_well)
464444 {
465− enum i915_power_well_id id = power_well->id;
466− enum port port = ICL_AUX_PW_TO_PORT(id);
445+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
446+ int pw_idx = power_well->desc->hsw.idx;
447+ enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
467448 u32 val;
468449
469450 val = I915_READ(ICL_PORT_CL_DW12(port));
470451 I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
471452
472− val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
473− I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
474− val & ~HSW_PWR_WELL_CTL_REQ(id));
453+ val = I915_READ(regs->driver);
454+ I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
475455
476456 hsw_wait_for_power_well_disable(dev_priv, power_well);
477457 }
@@ -484,22 +464,22 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, · 6 unmodified lines
484464 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
485465 struct i915_power_well *power_well)
486466 {
487− enum i915_power_well_id id = power_well->id;
488− u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
467+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
468+ int pw_idx = power_well->desc->hsw.idx;
469+ u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
470+ HSW_PWR_WELL_CTL_STATE(pw_idx);
489471
490− return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask;
472+ return (I915_READ(regs->driver) & mask) == mask;
491473 }
492474
493475 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
494476 {
495− enum i915_power_well_id id = SKL_DISP_PW_2;
496−
497477 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
498478 "DC9 already programmed to be enabled.\n");
499479 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
500480 "DC5 still not disabled to enable DC9.\n");
501− WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &
502− HSW_PWR_WELL_CTL_REQ(id),
481+ WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
482+ HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
503483 "Power well 2 on.\n");
504484 WARN_ONCE(intel_irqs_enabled(dev_priv),
505485 "Interrupts not disabled yet.\n");
@@ -668,6 +648,27 @@ static void assert_csr_loaded(struct drm_i915_private *dev_priv) · 162 unmodified lines
668648 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
669649 }
670650
651+static struct i915_power_well *
652+lookup_power_well(struct drm_i915_private *dev_priv,
653+ enum i915_power_well_id power_well_id)
654+{
655+ struct i915_power_well *power_well;
656+
657+ for_each_power_well(dev_priv, power_well)
658+ if (power_well->desc->id == power_well_id)
659+ return power_well;
660+
661+ /*
662+ * It's not feasible to add error checking code to the callers since
663+ * this condition really shouldn't happen and it doesn't even make sense
664+ * to abort things like display initialization sequences. Just return
665+ * the first power well and hope the WARN gets reported so we can fix
666+ * our driver.
667+ */
668+ WARN(1, "Power well %d not defined for this platform\n", power_well_id);
669+ return &dev_priv->power_domains.power_wells[0];
670+}
671+
671672 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
672673 {
673674 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
@@ -723,54 +724,57 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv) · 49 unmodified lines
723724 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
724725 struct i915_power_well *power_well)
725726 {
726− enum i915_power_well_id id = power_well->id;
727− u32 mask = HSW_PWR_WELL_CTL_REQ(id);
728− u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));
727+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
728+ int pw_idx = power_well->desc->hsw.idx;
729+ u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
730+ u32 bios_req = I915_READ(regs->bios);
729731
730732 /* Take over the request bit if set by BIOS. */
731733 if (bios_req & mask) {
732− u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
734+ u32 drv_req = I915_READ(regs->driver);
733735
734736 if (!(drv_req & mask))
735− I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask);
736− I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask);
737+ I915_WRITE(regs->driver, drv_req | mask);
738+ I915_WRITE(regs->bios, bios_req & ~mask);
737739 }
738740 }
739741
740742 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
741743 struct i915_power_well *power_well)
742744 {
743− bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
745+ bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
744746 }
745747
746748 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
747749 struct i915_power_well *power_well)
748750 {
749− bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
751+ bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
750752 }
751753
752754 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
753755 struct i915_power_well *power_well)
754756 {
755− return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy);
757+ return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
756758 }
757759
758760 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
759761 {
760762 struct i915_power_well *power_well;
761763
762− power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
764+ power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
763765 if (power_well->count > 0)
764− bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
766+ bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
765767
766− power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
768+ power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
767769 if (power_well->count > 0)
768− bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
770+ bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
769771
770772 if (IS_GEMINILAKE(dev_priv)) {
771− power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
773+ power_well = lookup_power_well(dev_priv,
774+ GLK_DISP_PW_DPIO_CMN_C);
772775 if (power_well->count > 0)
773− bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
776+ bxt_ddi_phy_verify_state(dev_priv,
777+ power_well->desc->bxt.phy);
774778 }
775779 }
776780
@@ -869,14 +873,14 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, · 92 unmodified lines
869873 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
870874 struct i915_power_well *power_well, bool enable)
871875 {
872− enum i915_power_well_id power_well_id = power_well->id;
876+ int pw_idx = power_well->desc->vlv.idx;
873877 u32 mask;
874878 u32 state;
875879 u32 ctrl;
876880
877− mask = PUNIT_PWRGT_MASK(power_well_id);
878− state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
879− PUNIT_PWRGT_PWR_GATE(power_well_id);
881+ mask = PUNIT_PWRGT_MASK(pw_idx);
882+ state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
883+ PUNIT_PWRGT_PWR_GATE(pw_idx);
880884
881885 mutex_lock(&dev_priv->pcu_lock);
882886
@@ -917,14 +921,14 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv, · 34 unmodified lines
917921 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
918922 struct i915_power_well *power_well)
919923 {
920− enum i915_power_well_id power_well_id = power_well->id;
924+ int pw_idx = power_well->desc->vlv.idx;
921925 bool enabled = false;
922926 u32 mask;
923927 u32 state;
924928 u32 ctrl;
925929
926− mask = PUNIT_PWRGT_MASK(power_well_id);
927− ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
930+ mask = PUNIT_PWRGT_MASK(pw_idx);
931+ ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
928932
929933 mutex_lock(&dev_priv->pcu_lock);
930934
@@ -933,8 +937,8 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, · 2 unmodified lines
933937 * We only ever set the power-on and power-gate states, anything
934938 * else is unexpected.
935939 */
936− WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
937− state != PUNIT_PWRGT_PWR_GATE(power_well_id));
940+ WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
941+ state != PUNIT_PWRGT_PWR_GATE(pw_idx));
938942 if (state == ctrl)
939943 enabled = true;
940944
@@ -1045,8 +1049,6 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) · 104 unmodified lines
10451049 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
10461050 struct i915_power_well *power_well)
10471051 {
1048− WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
1049−
10501052 vlv_set_power_well(dev_priv, power_well, true);
10511053
10521054 vlv_display_power_well_init(dev_priv);
@@ -1055,8 +1057,6 @@ static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, · 2 unmodified lines
10551057 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
10561058 struct i915_power_well *power_well)
10571059 {
1058− WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
1059−
10601060 vlv_display_power_well_deinit(dev_priv);
10611061
10621062 vlv_set_power_well(dev_priv, power_well, false);
@@ -1065,8 +1065,6 @@ static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, · 2 unmodified lines
10651065 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
10661066 struct i915_power_well *power_well)
10671067 {
1068− WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
1069−
10701068 /* since ref/cri clock was enabled */
10711069 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
10721070
@@ -1091,8 +1089,6 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, · 18 unmodified lines
10911089 {
10921090 enum pipe pipe;
10931091
1094− WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
1095−
10961092 for_each_pipe(dev_priv, pipe)
10971093 assert_pll_disabled(dev_priv, pipe);
10981094
@@ -1104,32 +1100,14 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, · 5 unmodified lines
11041100
11051101 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
11061102
1107−static struct i915_power_well *
1108−lookup_power_well(struct drm_i915_private *dev_priv,
1109− enum i915_power_well_id power_well_id)
1110−{
1111− struct i915_power_domains *power_domains = &dev_priv->power_domains;
1112− int i;
1113−
1114− for (i = 0; i < power_domains->power_well_count; i++) {
1115− struct i915_power_well *power_well;
1116−
1117− power_well = &power_domains->power_wells[i];
1118− if (power_well->id == power_well_id)
1119− return power_well;
1120− }
1121−
1122− return NULL;
1123−}
1124−
11251103 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
11261104
11271105 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
11281106 {
11291107 struct i915_power_well *cmn_bc =
1130− lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1108+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
11311109 struct i915_power_well *cmn_d =
1132− lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1110+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
11331111 u32 phy_control = dev_priv->chv_phy_control;
11341112 u32 phy_status = 0;
11351113 u32 phy_status_mask = 0xffffffff;
@@ -1154,7 +1132,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) · 18 unmodified lines
11541132 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
11551133 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
11561134
1157− if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1135+ if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
11581136 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
11591137
11601138 /* this assumes override is only used to enable lanes */
@@ -1195,7 +1173,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) · 34 unmodified lines
11951173 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
11961174 }
11971175
1198− if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1176+ if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
11991177 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
12001178
12011179 /* this assumes override is only used to enable lanes */
@@ -1239,10 +1217,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, · 37 unmodified lines
12391217 enum pipe pipe;
12401218 uint32_t tmp;
12411219
1242− WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1243− power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
1220+ WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1221+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
12441222
1245− if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1223+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
12461224 pipe = PIPE_A;
12471225 phy = DPIO_PHY0;
12481226 } else {
@@ -1270,7 +1248,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, · 21 unmodified lines
12701248 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
12711249 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
12721250
1273− if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1251+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
12741252 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
12751253 tmp |= DPIO_DYNPWRDOWNEN_CH1;
12761254 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1301,10 +1279,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, · 24 unmodified lines
13011279 {
13021280 enum dpio_phy phy;
13031281
1304− WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1305− power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
1282+ WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1283+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
13061284
1307− if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1285+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
13081286 phy = DPIO_PHY0;
13091287 assert_pll_disabled(dev_priv, PIPE_A);
13101288 assert_pll_disabled(dev_priv, PIPE_B);
@@ -1516,8 +1494,6 @@ out: · 205 unmodified lines
15161494 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
15171495 struct i915_power_well *power_well)
15181496 {
1519− WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
1520−
15211497 chv_set_pipe_power_well(dev_priv, power_well, true);
15221498
15231499 vlv_display_power_well_init(dev_priv);
@@ -1526,8 +1502,6 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, · 2 unmodified lines
15261502 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
15271503 struct i915_power_well *power_well)
15281504 {
1529− WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
1530−
15311505 vlv_display_power_well_deinit(dev_priv);
15321506
15331507 chv_set_pipe_power_well(dev_priv, power_well, false);
@@ -2063,13 +2037,13 @@ static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { · 529 unmodified lines
20632037 .is_enabled = vlv_power_well_enabled,
20642038 };
20652039
2066−static struct i915_power_well i9xx_always_on_power_well[] = {
2040+static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
20672041 {
20682042 .name = "always-on",
20692043 .always_on = 1,
20702044 .domains = POWER_DOMAIN_MASK,
20712045 .ops = &i9xx_always_on_power_well_ops,
2072− .id = I915_DISP_PW_ALWAYS_ON,
2046+ .id = DISP_PW_ID_NONE,
20732047 },
20742048 };
20752049
@@ -2080,19 +2054,19 @@ static const struct i915_power_well_ops i830_pipes_power_well_ops = { · 4 unmodified lines
20802054 .is_enabled = i830_pipes_power_well_enabled,
20812055 };
20822056
2083−static struct i915_power_well i830_power_wells[] = {
2057+static const struct i915_power_well_desc i830_power_wells[] = {
20842058 {
20852059 .name = "always-on",
20862060 .always_on = 1,
20872061 .domains = POWER_DOMAIN_MASK,
20882062 .ops = &i9xx_always_on_power_well_ops,
2089− .id = I915_DISP_PW_ALWAYS_ON,
2063+ .id = DISP_PW_ID_NONE,
20902064 },
20912065 {
20922066 .name = "pipes",
20932067 .domains = I830_PIPES_POWER_DOMAINS,
20942068 .ops = &i830_pipes_power_well_ops,
2095− .id = I830_DISP_PW_PIPES,
2069+ .id = DISP_PW_ID_NONE,
20962070 },
20972071 };
20982072
@@ -2117,13 +2091,20 @@ static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { · 18 unmodified lines
21172091 .is_enabled = bxt_dpio_cmn_power_well_enabled,
21182092 };
21192093
2120−static struct i915_power_well hsw_power_wells[] = {
2094+static const struct i915_power_well_regs hsw_power_well_regs = {
2095+ .bios = HSW_PWR_WELL_CTL1,
2096+ .driver = HSW_PWR_WELL_CTL2,
2097+ .kvmr = HSW_PWR_WELL_CTL3,
2098+ .debug = HSW_PWR_WELL_CTL4,
2099+};
2100+
2101+static const struct i915_power_well_desc hsw_power_wells[] = {
21212102 {
21222103 .name = "always-on",
21232104 .always_on = 1,
21242105 .domains = POWER_DOMAIN_MASK,
21252106 .ops = &i9xx_always_on_power_well_ops,
2126− .id = I915_DISP_PW_ALWAYS_ON,
2107+ .id = DISP_PW_ID_NONE,
21272108 },
21282109 {
21292110 .name = "display",
@@ -2131,18 +2112,20 @@ static struct i915_power_well hsw_power_wells[] = { · 1 unmodified line
21312112 .ops = &hsw_power_well_ops,
21322113 .id = HSW_DISP_PW_GLOBAL,
21332114 {
2115+ .hsw.regs = &hsw_power_well_regs,
2116+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
21342117 .hsw.has_vga = true,
21352118 },
21362119 },
21372120 };
21382121
2139−static struct i915_power_well bdw_power_wells[] = {
2122+static const struct i915_power_well_desc bdw_power_wells[] = {
21402123 {
21412124 .name = "always-on",
21422125 .always_on = 1,
21432126 .domains = POWER_DOMAIN_MASK,
21442127 .ops = &i9xx_always_on_power_well_ops,
2145− .id = I915_DISP_PW_ALWAYS_ON,
2128+ .id = DISP_PW_ID_NONE,
21462129 },
21472130 {
21482131 .name = "display",
@@ -2150,6 +2133,8 @@ static struct i915_power_well bdw_power_wells[] = { · 1 unmodified line
21502133 .ops = &hsw_power_well_ops,
21512134 .id = HSW_DISP_PW_GLOBAL,
21522135 {
2136+ .hsw.regs = &hsw_power_well_regs,
2137+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
21532138 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
21542139 .hsw.has_vga = true,
21552140 },
@@ -2177,19 +2162,22 @@ static const struct i915_power_well_ops vlv_dpio_power_well_ops = { · 21 unmodified lines
21772162 .is_enabled = vlv_power_well_enabled,
21782163 };
21792164
2180−static struct i915_power_well vlv_power_wells[] = {
2165+static const struct i915_power_well_desc vlv_power_wells[] = {
21812166 {
21822167 .name = "always-on",
21832168 .always_on = 1,
21842169 .domains = POWER_DOMAIN_MASK,
21852170 .ops = &i9xx_always_on_power_well_ops,
2186− .id = I915_DISP_PW_ALWAYS_ON,
2171+ .id = DISP_PW_ID_NONE,
21872172 },
21882173 {
21892174 .name = "display",
21902175 .domains = VLV_DISPLAY_POWER_DOMAINS,
2191− .id = PUNIT_POWER_WELL_DISP2D,
21922176 .ops = &vlv_display_power_well_ops,
2177+ .id = VLV_DISP_PW_DISP2D,
2178+ {
2179+ .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
2180+ },
21932181 },
21942182 {
21952183 .name = "dpio-tx-b-01",
@@ -2198,7 +2186,10 @@ static struct i915_power_well vlv_power_wells[] = { · 2 unmodified lines
21982186 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
21992187 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
22002188 .ops = &vlv_dpio_power_well_ops,
2201− .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
2189+ .id = DISP_PW_ID_NONE,
2190+ {
2191+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
2192+ },
22022193 },
22032194 {
22042195 .name = "dpio-tx-b-23",
@@ -2207,7 +2198,10 @@ static struct i915_power_well vlv_power_wells[] = { · 2 unmodified lines
22072198 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
22082199 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
22092200 .ops = &vlv_dpio_power_well_ops,
2210− .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
2201+ .id = DISP_PW_ID_NONE,
2202+ {
2203+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
2204+ },
22112205 },
22122206 {
22132207 .name = "dpio-tx-c-01",
@@ -2216,7 +2210,10 @@ static struct i915_power_well vlv_power_wells[] = { · 2 unmodified lines
22162210 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
22172211 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
22182212 .ops = &vlv_dpio_power_well_ops,
2219− .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
2213+ .id = DISP_PW_ID_NONE,
2214+ {
2215+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
2216+ },
22202217 },
22212218 {
22222219 .name = "dpio-tx-c-23",
@@ -2225,23 +2222,29 @@ static struct i915_power_well vlv_power_wells[] = { · 2 unmodified lines
22252222 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
22262223 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
22272224 .ops = &vlv_dpio_power_well_ops,
2228− .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
2225+ .id = DISP_PW_ID_NONE,
2226+ {
2227+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
2228+ },
22292229 },
22302230 {
22312231 .name = "dpio-common",
22322232 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2233− .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
22342233 .ops = &vlv_dpio_cmn_power_well_ops,
2234+ .id = VLV_DISP_PW_DPIO_CMN_BC,
2235+ {
2236+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2237+ },
22352238 },
22362239 };
22372240
2238−static struct i915_power_well chv_power_wells[] = {
2241+static const struct i915_power_well_desc chv_power_wells[] = {
22392242 {
22402243 .name = "always-on",
22412244 .always_on = 1,
22422245 .domains = POWER_DOMAIN_MASK,
22432246 .ops = &i9xx_always_on_power_well_ops,
2244− .id = I915_DISP_PW_ALWAYS_ON,
2247+ .id = DISP_PW_ID_NONE,
22452248 },
22462249 {
22472250 .name = "display",
@@ -2251,20 +2254,26 @@ static struct i915_power_well chv_power_wells[] = { · 3 unmodified lines
22512254 * required for any pipe to work.
22522255 */
22532256 .domains = CHV_DISPLAY_POWER_DOMAINS,
2254− .id = CHV_DISP_PW_PIPE_A,
22552257 .ops = &chv_pipe_power_well_ops,
2258+ .id = DISP_PW_ID_NONE,
22562259 },
22572260 {
22582261 .name = "dpio-common-bc",
22592262 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2260− .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
22612263 .ops = &chv_dpio_cmn_power_well_ops,
2264+ .id = VLV_DISP_PW_DPIO_CMN_BC,
2265+ {
2266+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2267+ },
22622268 },
22632269 {
22642270 .name = "dpio-common-d",
22652271 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2266− .id = PUNIT_POWER_WELL_DPIO_CMN_D,
22672272 .ops = &chv_dpio_cmn_power_well_ops,
2273+ .id = CHV_DISP_PW_DPIO_CMN_D,
2274+ {
2275+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
2276+ },
22682277 },
22692278 };
22702279
@@ -2275,18 +2284,18 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, · 4 unmodified lines
22752284 bool ret;
22762285
22772286 power_well = lookup_power_well(dev_priv, power_well_id);
2278− ret = power_well->ops->is_enabled(dev_priv, power_well);
2287+ ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
22792288
22802289 return ret;
22812290 }
22822291
2283−static struct i915_power_well skl_power_wells[] = {
2292+static const struct i915_power_well_desc skl_power_wells[] = {
22842293 {
22852294 .name = "always-on",
22862295 .always_on = 1,
22872296 .domains = POWER_DOMAIN_MASK,
22882297 .ops = &i9xx_always_on_power_well_ops,
2289− .id = I915_DISP_PW_ALWAYS_ON,
2298+ .id = DISP_PW_ID_NONE,
22902299 },
22912300 {
22922301 .name = "power well 1",
@@ -2295,6 +2304,8 @@ static struct i915_power_well skl_power_wells[] = { · 2 unmodified lines
22952304 .ops = &hsw_power_well_ops,
22962305 .id = SKL_DISP_PW_1,
22972306 {
2307+ .hsw.regs = &hsw_power_well_regs,
2308+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
22982309 .hsw.has_fuses = true,
22992310 },
23002311 },
@@ -2304,12 +2315,16 @@ static struct i915_power_well skl_power_wells[] = { · 3 unmodified lines
23042315 .domains = 0,
23052316 .ops = &hsw_power_well_ops,
23062317 .id = SKL_DISP_PW_MISC_IO,
2318+ {
2319+ .hsw.regs = &hsw_power_well_regs,
2320+ .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
2321+ },
23072322 },
23082323 {
23092324 .name = "DC off",
23102325 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
23112326 .ops = &gen9_dc_off_power_well_ops,
2312− .id = SKL_DISP_PW_DC_OFF,
2327+ .id = DISP_PW_ID_NONE,
23132328 },
23142329 {
23152330 .name = "power well 2",
@@ -2317,6 +2332,8 @@ static struct i915_power_well skl_power_wells[] = { · 1 unmodified line
23172332 .ops = &hsw_power_well_ops,
23182333 .id = SKL_DISP_PW_2,
23192334 {
2335+ .hsw.regs = &hsw_power_well_regs,
2336+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
23202337 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
23212338 .hsw.has_vga = true,
23222339 .hsw.has_fuses = true,
@@ -2326,35 +2343,51 @@ static struct i915_power_well skl_power_wells[] = { · 3 unmodified lines
23262343 .name = "DDI A/E IO power well",
23272344 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
23282345 .ops = &hsw_power_well_ops,
2329− .id = SKL_DISP_PW_DDI_A_E,
2346+ .id = DISP_PW_ID_NONE,
2347+ {
2348+ .hsw.regs = &hsw_power_well_regs,
2349+ .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
2350+ },
23302351 },
23312352 {
23322353 .name = "DDI B IO power well",
23332354 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
23342355 .ops = &hsw_power_well_ops,
2335− .id = SKL_DISP_PW_DDI_B,
2356+ .id = DISP_PW_ID_NONE,
2357+ {
2358+ .hsw.regs = &hsw_power_well_regs,
2359+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2360+ },
23362361 },
23372362 {
23382363 .name = "DDI C IO power well",
23392364 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
23402365 .ops = &hsw_power_well_ops,
2341− .id = SKL_DISP_PW_DDI_C,
2366+ .id = DISP_PW_ID_NONE,
2367+ {
2368+ .hsw.regs = &hsw_power_well_regs,
2369+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2370+ },
23422371 },
23432372 {
23442373 .name = "DDI D IO power well",
23452374 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
23462375 .ops = &hsw_power_well_ops,
2347− .id = SKL_DISP_PW_DDI_D,
2376+ .id = DISP_PW_ID_NONE,
2377+ {
2378+ .hsw.regs = &hsw_power_well_regs,
2379+ .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2380+ },
23482381 },
23492382 };
23502383
2351−static struct i915_power_well bxt_power_wells[] = {
2384+static const struct i915_power_well_desc bxt_power_wells[] = {
23522385 {
23532386 .name = "always-on",
23542387 .always_on = 1,
23552388 .domains = POWER_DOMAIN_MASK,
23562389 .ops = &i9xx_always_on_power_well_ops,
2357− .id = I915_DISP_PW_ALWAYS_ON,
2390+ .id = DISP_PW_ID_NONE,
23582391 },
23592392 {
23602393 .name = "power well 1",
@@ -2362,6 +2395,8 @@ static struct i915_power_well bxt_power_wells[] = { · 1 unmodified line
23622395 .ops = &hsw_power_well_ops,
23632396 .id = SKL_DISP_PW_1,
23642397 {
2398+ .hsw.regs = &hsw_power_well_regs,
2399+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
23652400 .hsw.has_fuses = true,
23662401 },
23672402 },
@@ -2369,7 +2404,7 @@ static struct i915_power_well bxt_power_wells[] = { · 1 unmodified line
23692404 .name = "DC off",
23702405 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
23712406 .ops = &gen9_dc_off_power_well_ops,
2372− .id = SKL_DISP_PW_DC_OFF,
2407+ .id = DISP_PW_ID_NONE,
23732408 },
23742409 {
23752410 .name = "power well 2",
@@ -2377,6 +2412,8 @@ static struct i915_power_well bxt_power_wells[] = { · 1 unmodified line
23772412 .ops = &hsw_power_well_ops,
23782413 .id = SKL_DISP_PW_2,
23792414 {
2415+ .hsw.regs = &hsw_power_well_regs,
2416+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
23802417 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
23812418 .hsw.has_vga = true,
23822419 .hsw.has_fuses = true,
@@ -2386,7 +2423,7 @@ static struct i915_power_well bxt_power_wells[] = { · 3 unmodified lines
23862423 .name = "dpio-common-a",
23872424 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
23882425 .ops = &bxt_dpio_cmn_power_well_ops,
2389− .id = BXT_DPIO_CMN_A,
2426+ .id = BXT_DISP_PW_DPIO_CMN_A,
23902427 {
23912428 .bxt.phy = DPIO_PHY1,
23922429 },
@@ -2395,20 +2432,20 @@ static struct i915_power_well bxt_power_wells[] = { · 2 unmodified lines
23952432 .name = "dpio-common-bc",
23962433 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
23972434 .ops = &bxt_dpio_cmn_power_well_ops,
2398− .id = BXT_DPIO_CMN_BC,
2435+ .id = VLV_DISP_PW_DPIO_CMN_BC,
23992436 {
24002437 .bxt.phy = DPIO_PHY0,
24012438 },
24022439 },
24032440 };
24042441
2405−static struct i915_power_well glk_power_wells[] = {
2442+static const struct i915_power_well_desc glk_power_wells[] = {
24062443 {
24072444 .name = "always-on",
24082445 .always_on = 1,
24092446 .domains = POWER_DOMAIN_MASK,
24102447 .ops = &i9xx_always_on_power_well_ops,
2411− .id = I915_DISP_PW_ALWAYS_ON,
2448+ .id = DISP_PW_ID_NONE,
24122449 },
24132450 {
24142451 .name = "power well 1",
@@ -2417,6 +2454,8 @@ static struct i915_power_well glk_power_wells[] = { · 2 unmodified lines
24172454 .ops = &hsw_power_well_ops,
24182455 .id = SKL_DISP_PW_1,
24192456 {
2457+ .hsw.regs = &hsw_power_well_regs,
2458+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
24202459 .hsw.has_fuses = true,
24212460 },
24222461 },
@@ -2424,7 +2463,7 @@ static struct i915_power_well glk_power_wells[] = { · 1 unmodified line
24242463 .name = "DC off",
24252464 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
24262465 .ops = &gen9_dc_off_power_well_ops,
2427− .id = SKL_DISP_PW_DC_OFF,
2466+ .id = DISP_PW_ID_NONE,
24282467 },
24292468 {
24302469 .name = "power well 2",
@@ -2432,6 +2471,8 @@ static struct i915_power_well glk_power_wells[] = { · 1 unmodified line
24322471 .ops = &hsw_power_well_ops,
24332472 .id = SKL_DISP_PW_2,
24342473 {
2474+ .hsw.regs = &hsw_power_well_regs,
2475+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
24352476 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
24362477 .hsw.has_vga = true,
24372478 .hsw.has_fuses = true,
@@ -2441,7 +2482,7 @@ static struct i915_power_well glk_power_wells[] = { · 3 unmodified lines
24412482 .name = "dpio-common-a",
24422483 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
24432484 .ops = &bxt_dpio_cmn_power_well_ops,
2444− .id = BXT_DPIO_CMN_A,
2485+ .id = BXT_DISP_PW_DPIO_CMN_A,
24452486 {
24462487 .bxt.phy = DPIO_PHY1,
24472488 },
@@ -2450,7 +2491,7 @@ static struct i915_power_well glk_power_wells[] = { · 2 unmodified lines
24502491 .name = "dpio-common-b",
24512492 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
24522493 .ops = &bxt_dpio_cmn_power_well_ops,
2453− .id = BXT_DPIO_CMN_BC,
2494+ .id = VLV_DISP_PW_DPIO_CMN_BC,
24542495 {
24552496 .bxt.phy = DPIO_PHY0,
24562497 },
@@ -2459,7 +2500,7 @@ static struct i915_power_well glk_power_wells[] = { · 2 unmodified lines
24592500 .name = "dpio-common-c",
24602501 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
24612502 .ops = &bxt_dpio_cmn_power_well_ops,
2462− .id = GLK_DPIO_CMN_C,
2503+ .id = GLK_DISP_PW_DPIO_CMN_C,
24632504 {
24642505 .bxt.phy = DPIO_PHY2,
24652506 },
@@ -2468,47 +2509,71 @@ static struct i915_power_well glk_power_wells[] = { · 2 unmodified lines
24682509 .name = "AUX A",
24692510 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
24702511 .ops = &hsw_power_well_ops,
2471− .id = GLK_DISP_PW_AUX_A,
2512+ .id = DISP_PW_ID_NONE,
2513+ {
2514+ .hsw.regs = &hsw_power_well_regs,
2515+ .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2516+ },
24722517 },
24732518 {
24742519 .name = "AUX B",
24752520 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
24762521 .ops = &hsw_power_well_ops,
2477− .id = GLK_DISP_PW_AUX_B,
2522+ .id = DISP_PW_ID_NONE,
2523+ {
2524+ .hsw.regs = &hsw_power_well_regs,
2525+ .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2526+ },
24782527 },
24792528 {
24802529 .name = "AUX C",
24812530 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
24822531 .ops = &hsw_power_well_ops,
2483− .id = GLK_DISP_PW_AUX_C,
2532+ .id = DISP_PW_ID_NONE,
2533+ {
2534+ .hsw.regs = &hsw_power_well_regs,
2535+ .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2536+ },
24842537 },
24852538 {
24862539 .name = "DDI A IO power well",
24872540 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
24882541 .ops = &hsw_power_well_ops,
2489− .id = GLK_DISP_PW_DDI_A,
2542+ .id = DISP_PW_ID_NONE,
2543+ {
2544+ .hsw.regs = &hsw_power_well_regs,
2545+ .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2546+ },
24902547 },
24912548 {
24922549 .name = "DDI B IO power well",
24932550 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
24942551 .ops = &hsw_power_well_ops,
2495− .id = SKL_DISP_PW_DDI_B,
2552+ .id = DISP_PW_ID_NONE,
2553+ {
2554+ .hsw.regs = &hsw_power_well_regs,
2555+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2556+ },
24962557 },
24972558 {
24982559 .name = "DDI C IO power well",
24992560 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
25002561 .ops = &hsw_power_well_ops,
2501− .id = SKL_DISP_PW_DDI_C,
2562+ .id = DISP_PW_ID_NONE,
2563+ {
2564+ .hsw.regs = &hsw_power_well_regs,
2565+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2566+ },
25022567 },
25032568 };
25042569
2505−static struct i915_power_well cnl_power_wells[] = {
2570+static const struct i915_power_well_desc cnl_power_wells[] = {
25062571 {
25072572 .name = "always-on",
25082573 .always_on = 1,
25092574 .domains = POWER_DOMAIN_MASK,
25102575 .ops = &i9xx_always_on_power_well_ops,
2511− .id = I915_DISP_PW_ALWAYS_ON,
2576+ .id = DISP_PW_ID_NONE,
25122577 },
25132578 {
25142579 .name = "power well 1",
@@ -2517,6 +2582,8 @@ static struct i915_power_well cnl_power_wells[] = { · 2 unmodified lines
25172582 .ops = &hsw_power_well_ops,
25182583 .id = SKL_DISP_PW_1,
25192584 {
2585+ .hsw.regs = &hsw_power_well_regs,
2586+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
25202587 .hsw.has_fuses = true,
25212588 },
25222589 },
@@ -2524,31 +2591,47 @@ static struct i915_power_well cnl_power_wells[] = { · 1 unmodified line
25242591 .name = "AUX A",
25252592 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
25262593 .ops = &hsw_power_well_ops,
2527− .id = CNL_DISP_PW_AUX_A,
2594+ .id = DISP_PW_ID_NONE,
2595+ {
2596+ .hsw.regs = &hsw_power_well_regs,
2597+ .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2598+ },
25282599 },
25292600 {
25302601 .name = "AUX B",
25312602 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
25322603 .ops = &hsw_power_well_ops,
2533− .id = CNL_DISP_PW_AUX_B,
2604+ .id = DISP_PW_ID_NONE,
2605+ {
2606+ .hsw.regs = &hsw_power_well_regs,
2607+ .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2608+ },
25342609 },
25352610 {
25362611 .name = "AUX C",
25372612 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
25382613 .ops = &hsw_power_well_ops,
2539− .id = CNL_DISP_PW_AUX_C,
2614+ .id = DISP_PW_ID_NONE,
2615+ {
2616+ .hsw.regs = &hsw_power_well_regs,
2617+ .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2618+ },
25402619 },
25412620 {
25422621 .name = "AUX D",
25432622 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
25442623 .ops = &hsw_power_well_ops,
2545− .id = CNL_DISP_PW_AUX_D,
2624+ .id = DISP_PW_ID_NONE,
2625+ {
2626+ .hsw.regs = &hsw_power_well_regs,
2627+ .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
2628+ },
25462629 },
25472630 {
25482631 .name = "DC off",
25492632 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
25502633 .ops = &gen9_dc_off_power_well_ops,
2551− .id = SKL_DISP_PW_DC_OFF,
2634+ .id = DISP_PW_ID_NONE,
25522635 },
25532636 {
25542637 .name = "power well 2",
@@ -2556,6 +2639,8 @@ static struct i915_power_well cnl_power_wells[] = { · 1 unmodified line
25562639 .ops = &hsw_power_well_ops,
25572640 .id = SKL_DISP_PW_2,
25582641 {
2642+ .hsw.regs = &hsw_power_well_regs,
2643+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
25592644 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
25602645 .hsw.has_vga = true,
25612646 .hsw.has_fuses = true,
@@ -2565,37 +2650,61 @@ static struct i915_power_well cnl_power_wells[] = { · 3 unmodified lines
25652650 .name = "DDI A IO power well",
25662651 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
25672652 .ops = &hsw_power_well_ops,
2568− .id = CNL_DISP_PW_DDI_A,
2653+ .id = DISP_PW_ID_NONE,
2654+ {
2655+ .hsw.regs = &hsw_power_well_regs,
2656+ .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2657+ },
25692658 },
25702659 {
25712660 .name = "DDI B IO power well",
25722661 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
25732662 .ops = &hsw_power_well_ops,
2574− .id = SKL_DISP_PW_DDI_B,
2663+ .id = DISP_PW_ID_NONE,
2664+ {
2665+ .hsw.regs = &hsw_power_well_regs,
2666+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2667+ },
25752668 },
25762669 {
25772670 .name = "DDI C IO power well",
25782671 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
25792672 .ops = &hsw_power_well_ops,
2580− .id = SKL_DISP_PW_DDI_C,
2673+ .id = DISP_PW_ID_NONE,
2674+ {
2675+ .hsw.regs = &hsw_power_well_regs,
2676+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2677+ },
25812678 },
25822679 {
25832680 .name = "DDI D IO power well",
25842681 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
25852682 .ops = &hsw_power_well_ops,
2586− .id = SKL_DISP_PW_DDI_D,
2683+ .id = DISP_PW_ID_NONE,
2684+ {
2685+ .hsw.regs = &hsw_power_well_regs,
2686+ .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2687+ },
25872688 },
25882689 {
25892690 .name = "DDI F IO power well",
25902691 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
25912692 .ops = &hsw_power_well_ops,
2592− .id = CNL_DISP_PW_DDI_F,
2693+ .id = DISP_PW_ID_NONE,
2694+ {
2695+ .hsw.regs = &hsw_power_well_regs,
2696+ .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
2697+ },
25932698 },
25942699 {
25952700 .name = "AUX F",
25962701 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
25972702 .ops = &hsw_power_well_ops,
2598− .id = CNL_DISP_PW_AUX_F,
2703+ .id = DISP_PW_ID_NONE,
2704+ {
2705+ .hsw.regs = &hsw_power_well_regs,
2706+ .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
2707+ },
25992708 },
26002709 };
26012710
@@ -2606,147 +2715,239 @@ static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = { · 4 unmodified lines
26062715 .is_enabled = hsw_power_well_enabled,
26072716 };
26082717
2609−static struct i915_power_well icl_power_wells[] = {
2718+static const struct i915_power_well_regs icl_aux_power_well_regs = {
2719+ .bios = ICL_PWR_WELL_CTL_AUX1,
2720+ .driver = ICL_PWR_WELL_CTL_AUX2,
2721+ .debug = ICL_PWR_WELL_CTL_AUX4,
2722+};
2723+
2724+static const struct i915_power_well_regs icl_ddi_power_well_regs = {
2725+ .bios = ICL_PWR_WELL_CTL_DDI1,
2726+ .driver = ICL_PWR_WELL_CTL_DDI2,
2727+ .debug = ICL_PWR_WELL_CTL_DDI4,
2728+};
2729+
2730+static const struct i915_power_well_desc icl_power_wells[] = {
26102731 {
26112732 .name = "always-on",
26122733 .always_on = 1,
26132734 .domains = POWER_DOMAIN_MASK,
26142735 .ops = &i9xx_always_on_power_well_ops,
2615− .id = I915_DISP_PW_ALWAYS_ON,
2736+ .id = DISP_PW_ID_NONE,
26162737 },
26172738 {
26182739 .name = "power well 1",
26192740 /* Handled by the DMC firmware */
26202741 .domains = 0,
26212742 .ops = &hsw_power_well_ops,
2622− .id = ICL_DISP_PW_1,
2623− .hsw.has_fuses = true,
2743+ .id = SKL_DISP_PW_1,
2744+ {
2745+ .hsw.regs = &hsw_power_well_regs,
2746+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
2747+ .hsw.has_fuses = true,
2748+ },
26242749 },
26252750 {
26262751 .name = "power well 2",
26272752 .domains = ICL_PW_2_POWER_DOMAINS,
26282753 .ops = &hsw_power_well_ops,
2629− .id = ICL_DISP_PW_2,
2630− .hsw.has_fuses = true,
2754+ .id = SKL_DISP_PW_2,
2755+ {
2756+ .hsw.regs = &hsw_power_well_regs,
2757+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
2758+ .hsw.has_fuses = true,
2759+ },
26312760 },
26322761 {
26332762 .name = "DC off",
26342763 .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
26352764 .ops = &gen9_dc_off_power_well_ops,
2636− .id = SKL_DISP_PW_DC_OFF,
2765+ .id = DISP_PW_ID_NONE,
26372766 },
26382767 {
26392768 .name = "power well 3",
26402769 .domains = ICL_PW_3_POWER_DOMAINS,
26412770 .ops = &hsw_power_well_ops,
2642− .id = ICL_DISP_PW_3,
2643− .hsw.irq_pipe_mask = BIT(PIPE_B),
2644− .hsw.has_vga = true,
2645− .hsw.has_fuses = true,
2771+ .id = DISP_PW_ID_NONE,
2772+ {
2773+ .hsw.regs = &hsw_power_well_regs,
2774+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
2775+ .hsw.irq_pipe_mask = BIT(PIPE_B),
2776+ .hsw.has_vga = true,
2777+ .hsw.has_fuses = true,
2778+ },
26462779 },
26472780 {
26482781 .name = "DDI A IO",
26492782 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
26502783 .ops = &hsw_power_well_ops,
2651− .id = ICL_DISP_PW_DDI_A,
2784+ .id = DISP_PW_ID_NONE,
2785+ {
2786+ .hsw.regs = &icl_ddi_power_well_regs,
2787+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
2788+ },
26522789 },
26532790 {
26542791 .name = "DDI B IO",
26552792 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
26562793 .ops = &hsw_power_well_ops,
2657− .id = ICL_DISP_PW_DDI_B,
2794+ .id = DISP_PW_ID_NONE,
2795+ {
2796+ .hsw.regs = &icl_ddi_power_well_regs,
2797+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
2798+ },
26582799 },
26592800 {
26602801 .name = "DDI C IO",
26612802 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
26622803 .ops = &hsw_power_well_ops,
2663− .id = ICL_DISP_PW_DDI_C,
2804+ .id = DISP_PW_ID_NONE,
2805+ {
2806+ .hsw.regs = &icl_ddi_power_well_regs,
2807+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
2808+ },
26642809 },
26652810 {
26662811 .name = "DDI D IO",
26672812 .domains = ICL_DDI_IO_D_POWER_DOMAINS,
26682813 .ops = &hsw_power_well_ops,
2669− .id = ICL_DISP_PW_DDI_D,
2814+ .id = DISP_PW_ID_NONE,
2815+ {
2816+ .hsw.regs = &icl_ddi_power_well_regs,
2817+ .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
2818+ },
26702819 },
26712820 {
26722821 .name = "DDI E IO",
26732822 .domains = ICL_DDI_IO_E_POWER_DOMAINS,
26742823 .ops = &hsw_power_well_ops,
2675− .id = ICL_DISP_PW_DDI_E,
2824+ .id = DISP_PW_ID_NONE,
2825+ {
2826+ .hsw.regs = &icl_ddi_power_well_regs,
2827+ .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
2828+ },
26762829 },
26772830 {
26782831 .name = "DDI F IO",
26792832 .domains = ICL_DDI_IO_F_POWER_DOMAINS,
26802833 .ops = &hsw_power_well_ops,
2681− .id = ICL_DISP_PW_DDI_F,
2834+ .id = DISP_PW_ID_NONE,
2835+ {
2836+ .hsw.regs = &icl_ddi_power_well_regs,
2837+ .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
2838+ },
26822839 },
26832840 {
26842841 .name = "AUX A",
26852842 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
26862843 .ops = &icl_combo_phy_aux_power_well_ops,
2687− .id = ICL_DISP_PW_AUX_A,
2844+ .id = DISP_PW_ID_NONE,
2845+ {
2846+ .hsw.regs = &icl_aux_power_well_regs,
2847+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
2848+ },
26882849 },
26892850 {
26902851 .name = "AUX B",
26912852 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
26922853 .ops = &icl_combo_phy_aux_power_well_ops,
2693− .id = ICL_DISP_PW_AUX_B,
2854+ .id = DISP_PW_ID_NONE,
2855+ {
2856+ .hsw.regs = &icl_aux_power_well_regs,
2857+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
2858+ },
26942859 },
26952860 {
26962861 .name = "AUX C",
26972862 .domains = ICL_AUX_C_IO_POWER_DOMAINS,
26982863 .ops = &hsw_power_well_ops,
2699− .id = ICL_DISP_PW_AUX_C,
2864+ .id = DISP_PW_ID_NONE,
2865+ {
2866+ .hsw.regs = &icl_aux_power_well_regs,
2867+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
2868+ },
27002869 },
27012870 {
27022871 .name = "AUX D",
27032872 .domains = ICL_AUX_D_IO_POWER_DOMAINS,
27042873 .ops = &hsw_power_well_ops,
2705− .id = ICL_DISP_PW_AUX_D,
2874+ .id = DISP_PW_ID_NONE,
2875+ {
2876+ .hsw.regs = &icl_aux_power_well_regs,
2877+ .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
2878+ },
27062879 },
27072880 {
27082881 .name = "AUX E",
27092882 .domains = ICL_AUX_E_IO_POWER_DOMAINS,
27102883 .ops = &hsw_power_well_ops,
2711− .id = ICL_DISP_PW_AUX_E,
2884+ .id = DISP_PW_ID_NONE,
2885+ {
2886+ .hsw.regs = &icl_aux_power_well_regs,
2887+ .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
2888+ },
27122889 },
27132890 {
27142891 .name = "AUX F",
27152892 .domains = ICL_AUX_F_IO_POWER_DOMAINS,
27162893 .ops = &hsw_power_well_ops,
2717− .id = ICL_DISP_PW_AUX_F,
2894+ .id = DISP_PW_ID_NONE,
2895+ {
2896+ .hsw.regs = &icl_aux_power_well_regs,
2897+ .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
2898+ },
27182899 },
27192900 {
27202901 .name = "AUX TBT1",
27212902 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
27222903 .ops = &hsw_power_well_ops,
2723− .id = ICL_DISP_PW_AUX_TBT1,
2904+ .id = DISP_PW_ID_NONE,
2905+ {
2906+ .hsw.regs = &icl_aux_power_well_regs,
2907+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
2908+ },
27242909 },
27252910 {
27262911 .name = "AUX TBT2",
27272912 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
27282913 .ops = &hsw_power_well_ops,
2729− .id = ICL_DISP_PW_AUX_TBT2,
2914+ .id = DISP_PW_ID_NONE,
2915+ {
2916+ .hsw.regs = &icl_aux_power_well_regs,
2917+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
2918+ },
27302919 },
27312920 {
27322921 .name = "AUX TBT3",
27332922 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
27342923 .ops = &hsw_power_well_ops,
2735− .id = ICL_DISP_PW_AUX_TBT3,
2924+ .id = DISP_PW_ID_NONE,
2925+ {
2926+ .hsw.regs = &icl_aux_power_well_regs,
2927+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
2928+ },
27362929 },
27372930 {
27382931 .name = "AUX TBT4",
27392932 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
27402933 .ops = &hsw_power_well_ops,
2741− .id = ICL_DISP_PW_AUX_TBT4,
2934+ .id = DISP_PW_ID_NONE,
2935+ {
2936+ .hsw.regs = &icl_aux_power_well_regs,
2937+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
2938+ },
27422939 },
27432940 {
27442941 .name = "power well 4",
27452942 .domains = ICL_PW_4_POWER_DOMAINS,
27462943 .ops = &hsw_power_well_ops,
2747− .id = ICL_DISP_PW_4,
2748− .hsw.has_fuses = true,
2749− .hsw.irq_pipe_mask = BIT(PIPE_C),
2944+ .id = DISP_PW_ID_NONE,
2945+ {
2946+ .hsw.regs = &hsw_power_well_regs,
2947+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
2948+ .hsw.has_fuses = true,
2949+ .hsw.irq_pipe_mask = BIT(PIPE_C),
2950+ },
27502951 },
27512952 };
27522953
@@ -2809,26 +3010,41 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, · 56 unmodified lines
28093010 return mask;
28103011 }
28113012
2812−static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv)
3013+static int
3014+__set_power_wells(struct i915_power_domains *power_domains,
3015+ const struct i915_power_well_desc *power_well_descs,
3016+ int power_well_count)
28133017 {
2814− struct i915_power_domains *power_domains = &dev_priv->power_domains;
2815− u64 power_well_ids;
3018+ u64 power_well_ids = 0;
28163019 int i;
28173020
2818− power_well_ids = 0;
2819− for (i = 0; i < power_domains->power_well_count; i++) {
2820− enum i915_power_well_id id = power_domains->power_wells[i].id;
3021+ power_domains->power_well_count = power_well_count;
3022+ power_domains->power_wells =
3023+ kcalloc(power_well_count,
3024+ sizeof(*power_domains->power_wells),
3025+ GFP_KERNEL);
3026+ if (!power_domains->power_wells)
3027+ return -ENOMEM;
3028+
3029+ for (i = 0; i < power_well_count; i++) {
3030+ enum i915_power_well_id id = power_well_descs[i].id;
3031+
3032+ power_domains->power_wells[i].desc = &power_well_descs[i];
3033+
3034+ if (id == DISP_PW_ID_NONE)
3035+ continue;
28213036
28223037 WARN_ON(id >= sizeof(power_well_ids) * 8);
28233038 WARN_ON(power_well_ids & BIT_ULL(id));
28243039 power_well_ids |= BIT_ULL(id);
28253040 }
3041+
3042+ return 0;
28263043 }
28273044
2828−#define set_power_wells(power_domains, __power_wells) ({ \
2829− (power_domains)->power_wells = (__power_wells); \
2830− (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2831−})
3045+#define set_power_wells(power_domains, __power_well_descs) \
3046+ __set_power_wells(power_domains, __power_well_descs, \
3047+ ARRAY_SIZE(__power_well_descs))
28323048
28333049 /**
28343050 * intel_power_domains_init - initializes the power domain structures
@@ -2840,6 +3056,7 @@ static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) · 5 unmodified lines
28403056 int intel_power_domains_init(struct drm_i915_private *dev_priv)
28413057 {
28423058 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3059+ int err;
28433060
28443061 i915_modparams.disable_power_well =
28453062 sanitize_disable_power_well_option(dev_priv,
@@ -2856,15 +3073,15 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) · 10 unmodified lines
28563073 * the disabling order is reversed.
28573074 */
28583075 if (IS_ICELAKE(dev_priv)) {
2859− set_power_wells(power_domains, icl_power_wells);
3076+ err = set_power_wells(power_domains, icl_power_wells);
28603077 } else if (IS_HASWELL(dev_priv)) {
2861− set_power_wells(power_domains, hsw_power_wells);
3078+ err = set_power_wells(power_domains, hsw_power_wells);
28623079 } else if (IS_BROADWELL(dev_priv)) {
2863− set_power_wells(power_domains, bdw_power_wells);
3080+ err = set_power_wells(power_domains, bdw_power_wells);
28643081 } else if (IS_GEN9_BC(dev_priv)) {
2865− set_power_wells(power_domains, skl_power_wells);
3082+ err = set_power_wells(power_domains, skl_power_wells);
28663083 } else if (IS_CANNONLAKE(dev_priv)) {
2867− set_power_wells(power_domains, cnl_power_wells);
3084+ err = set_power_wells(power_domains, cnl_power_wells);
28683085
28693086 /*
28703087 * DDI and Aux IO are getting enabled for all ports
@@ -2876,57 +3093,31 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) · 5 unmodified lines
28763093 power_domains->power_well_count -= 2;
28773094
28783095 } else if (IS_BROXTON(dev_priv)) {
2879− set_power_wells(power_domains, bxt_power_wells);
3096+ err = set_power_wells(power_domains, bxt_power_wells);
28803097 } else if (IS_GEMINILAKE(dev_priv)) {
2881− set_power_wells(power_domains, glk_power_wells);
3098+ err = set_power_wells(power_domains, glk_power_wells);
28823099 } else if (IS_CHERRYVIEW(dev_priv)) {
2883− set_power_wells(power_domains, chv_power_wells);
3100+ err = set_power_wells(power_domains, chv_power_wells);
28843101 } else if (IS_VALLEYVIEW(dev_priv)) {
2885− set_power_wells(power_domains, vlv_power_wells);
3102+ err = set_power_wells(power_domains, vlv_power_wells);
28863103 } else if (IS_I830(dev_priv)) {
2887− set_power_wells(power_domains, i830_power_wells);
3104+ err = set_power_wells(power_domains, i830_power_wells);
28883105 } else {
2889− set_power_wells(power_domains, i9xx_always_on_power_well);
3106+ err = set_power_wells(power_domains, i9xx_always_on_power_well);
28903107 }
28913108
2892− assert_power_well_ids_unique(dev_priv);
2893−
2894− return 0;
3109+ return err;
28953110 }
28963111
28973112 /**
2898− * intel_power_domains_fini - finalizes the power domain structures
3113+ * intel_power_domains_cleanup - clean up power domains resources
28993114 * @dev_priv: i915 device instance
29003115 *
2901− * Finalizes the power domain structures for @dev_priv depending upon the
2902− * supported platform. This function also disables runtime pm and ensures that
2903− * the device stays powered up so that the driver can be reloaded.
3116+ * Release any resources acquired by intel_power_domains_init()
29043117 */
2905−void intel_power_domains_fini(struct drm_i915_private *dev_priv)
3118+void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
29063119 {
2907− struct device *kdev = &dev_priv->drm.pdev->dev;
2908−
2909− /*
2910− * The i915.ko module is still not prepared to be loaded when
2911− * the power well is not enabled, so just enable it in case
2912− * we're going to unload/reload.
2913− * The following also reacquires the RPM reference the core passed
2914− * to the driver during loading, which is dropped in
2915− * intel_runtime_pm_enable(). We have to hand back the control of the
2916− * device to the core with this reference held.
2917− */
2918− intel_display_set_init_power(dev_priv, true);
2919−
2920− /* Remove the refcount we took to keep power well support disabled. */
2921− if (!i915_modparams.disable_power_well)
2922− intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2923−
2924− /*
2925− * Remove the refcount we took in intel_runtime_pm_enable() in case
2926− * the platform doesn't support runtime PM.
2927− */
2928− if (!HAS_RUNTIME_PM(dev_priv))
2929− pm_runtime_put(kdev);
3120+ kfree(dev_priv->power_domains.power_wells);
29303121 }
29313122
29323123 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
@@ -2936,9 +3127,9 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) · 3 unmodified lines
29363127
29373128 mutex_lock(&power_domains->lock);
29383129 for_each_power_well(dev_priv, power_well) {
2939− power_well->ops->sync_hw(dev_priv, power_well);
2940− power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2941− power_well);
3130+ power_well->desc->ops->sync_hw(dev_priv, power_well);
3131+ power_well->hw_enabled =
3132+ power_well->desc->ops->is_enabled(dev_priv, power_well);
29423133 }
29433134 mutex_unlock(&power_domains->lock);
29443135 }
@@ -3360,7 +3551,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, · 415 unmodified lines
33603551 * The AUX IO power wells will be enabled on demand.
33613552 */
33623553 mutex_lock(&power_domains->lock);
3363− well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
3554+ well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
33643555 intel_power_well_enable(dev_priv, well);
33653556 mutex_unlock(&power_domains->lock);
33663557
@@ -3372,10 +3563,6 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, · 5 unmodified lines
33723563
33733564 /* 7. Setup MBUS. */
33743565 icl_mbus_init(dev_priv);
3375−
3376− /* 8. CHICKEN_DCPR_1 */
3377− I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
3378− CNL_DDI_CLOCK_REG_ACCESS_ON);
33793566 }
33803567
33813568 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3401,7 +3588,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) · 19 unmodified lines
34013588 * disabled at this point.
34023589 */
34033590 mutex_lock(&power_domains->lock);
3404− well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
3591+ well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
34053592 intel_power_well_disable(dev_priv, well);
34063593 mutex_unlock(&power_domains->lock);
34073594
@@ -3416,9 +3603,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) · 8 unmodified lines
34163603 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
34173604 {
34183605 struct i915_power_well *cmn_bc =
3419− lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
3606+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
34203607 struct i915_power_well *cmn_d =
3421− lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
3608+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
34223609
34233610 /*
34243611 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
@@ -3441,7 +3628,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) · 16 unmodified lines
34413628 * override and set the lane powerdown bits accding to the
34423629 * current lane status.
34433630 */
3444− if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
3631+ if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
34453632 uint32_t status = I915_READ(DPLL(PIPE_A));
34463633 unsigned int mask;
34473634
@@ -3472,7 +3659,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) · 24 unmodified lines
34723659 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
34733660 }
34743661
3475− if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
3662+ if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
34763663 uint32_t status = I915_READ(DPIO_PHY_STATUS);
34773664 unsigned int mask;
34783665
@@ -3503,20 +3690,20 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) · 24 unmodified lines
35033690 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
35043691 {
35053692 struct i915_power_well *cmn =
3506− lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
3693+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
35073694 struct i915_power_well *disp2d =
3508− lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
3695+ lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
35093696
35103697 /* If the display might be already active skip this */
3511− if (cmn->ops->is_enabled(dev_priv, cmn) &&
3512− disp2d->ops->is_enabled(dev_priv, disp2d) &&
3698+ if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
3699+ disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
35133700 I915_READ(DPIO_CTL) & DPIO_CMNRST)
35143701 return;
35153702
35163703 DRM_DEBUG_KMS("toggling display PHY side reset\n");
35173704
35183705 /* cmnlane needs DPLL registers */
3519− disp2d->ops->enable(dev_priv, disp2d);
3706+ disp2d->desc->ops->enable(dev_priv, disp2d);
35203707
35213708 /*
35223709 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
@@ -3525,9 +3712,11 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) · 2 unmodified lines
35253712 * Simply ungating isn't enough to reset the PHY enough to get
35263713 * ports and lanes running.
35273714 */
3528− cmn->ops->disable(dev_priv, cmn);
3715+ cmn->desc->ops->disable(dev_priv, cmn);
35293716 }
35303717
3718+static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
3719+
35313720 /**
35323721 * intel_power_domains_init_hw - initialize hardware power domain state
35333722 * @dev_priv: i915 device instance
@@ -3535,9 +3724,14 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) · 1 unmodified line
35353724 *
35363725 * This function initializes the hardware power domain state and enables all
35373726 * power wells belonging to the INIT power domain. Power wells in other
3538− * domains (and not in the INIT domain) are referenced or disabled during the
3539− * modeset state HW readout. After that the reference count of each power well
3540− * must match its HW enabled state, see intel_power_domains_verify_state().
3727+ * domains (and not in the INIT domain) are referenced or disabled by
3728+ * intel_modeset_readout_hw_state(). After that the reference count of each
3729+ * power well must match its HW enabled state, see
3730+ * intel_power_domains_verify_state().
3731+ *
3732+ * It will return with power domains disabled (to be enabled later by
3733+ * intel_power_domains_enable()) and must be paired with
3734+ * intel_power_domains_fini_hw().
35413735 */
35423736 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
35433737 {
@@ -3563,30 +3757,117 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) · 19 unmodified lines
35633757 mutex_unlock(&power_domains->lock);
35643758 }
35653759
3566− /* For now, we need the power well to be always enabled. */
3567− intel_display_set_init_power(dev_priv, true);
3760+ /*
3761+ * Keep all power wells enabled for any dependent HW access during
3762+ * initialization and to make sure we keep BIOS enabled display HW
3763+ * resources powered until display HW readout is complete. We drop
3764+ * this reference in intel_power_domains_enable().
3765+ */
3766+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
35683767 /* Disable power support if the user asked so. */
35693768 if (!i915_modparams.disable_power_well)
35703769 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
35713770 intel_power_domains_sync_hw(dev_priv);
3771+
35723772 power_domains->initializing = false;
35733773 }
35743774
3775+/**
3776+ * intel_power_domains_fini_hw - deinitialize hw power domain state
3777+ * @dev_priv: i915 device instance
3778+ *
3779+ * De-initializes the display power domain HW state. It also ensures that the
3780+ * device stays powered up so that the driver can be reloaded.
3781+ *
3782+ * It must be called with power domains already disabled (after a call to
3783+ * intel_power_domains_disable()) and must be paired with
3784+ * intel_power_domains_init_hw().
3785+ */
3786+void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv)
3787+{
3788+ /* Keep the power well enabled, but cancel its rpm wakeref. */
3789+ intel_runtime_pm_put(dev_priv);
3790+
3791+ /* Remove the refcount we took to keep power well support disabled. */
3792+ if (!i915_modparams.disable_power_well)
3793+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3794+
3795+ intel_power_domains_verify_state(dev_priv);
3796+}
3797+
3798+/**
3799+ * intel_power_domains_enable - enable toggling of display power wells
3800+ * @dev_priv: i915 device instance
3801+ *
3802+ * Enable the ondemand enabling/disabling of the display power wells. Note that
3803+ * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
3804+ * only at specific points of the display modeset sequence, thus they are not
3805+ * affected by the intel_power_domains_enable()/disable() calls. The purpose
3806+ * of these function is to keep the rest of power wells enabled until the end
3807+ * of display HW readout (which will acquire the power references reflecting
3808+ * the current HW state).
3809+ */
3810+void intel_power_domains_enable(struct drm_i915_private *dev_priv)
3811+{
3812+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3813+
3814+ intel_power_domains_verify_state(dev_priv);
3815+}
3816+
3817+/**
3818+ * intel_power_domains_disable - disable toggling of display power wells
3819+ * @dev_priv: i915 device instance
3820+ *
3821+ * Disable the ondemand enabling/disabling of the display power wells. See
3822+ * intel_power_domains_enable() for which power wells this call controls.
3823+ */
3824+void intel_power_domains_disable(struct drm_i915_private *dev_priv)
3825+{
3826+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3827+
3828+ intel_power_domains_verify_state(dev_priv);
3829+}
3830+
35753831 /**
35763832 * intel_power_domains_suspend - suspend power domain state
35773833 * @dev_priv: i915 device instance
3834+ * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
35783835 *
35793836 * This function prepares the hardware power domain state before entering
3580− * system suspend. It must be paired with intel_power_domains_init_hw().
3837+ * system suspend.
3838+ *
3839+ * It must be called with power domains already disabled (after a call to
3840+ * intel_power_domains_disable()) and paired with intel_power_domains_resume().
35813841 */
3582−void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
3842+void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
3843+ enum i915_drm_suspend_mode suspend_mode)
35833844 {
3845+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
3846+
3847+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3848+
3849+ /*
3850+ * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
3851+ * support don't manually deinit the power domains. This also means the
3852+ * CSR/DMC firmware will stay active, it will power down any HW
3853+ * resources as required and also enable deeper system power states
3854+ * that would be blocked if the firmware was inactive.
3855+ */
3856+ if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
3857+ suspend_mode == I915_DRM_SUSPEND_IDLE &&
3858+ dev_priv->csr.dmc_payload != NULL) {
3859+ intel_power_domains_verify_state(dev_priv);
3860+ return;
3861+ }
3862+
35843863 /*
35853864 * Even if power well support was disabled we still want to disable
3586− * power wells while we are system suspended.
3865+ * power wells if power domains must be deinitialized for suspend.
35873866 */
3588− if (!i915_modparams.disable_power_well)
3867+ if (!i915_modparams.disable_power_well) {
35893868 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3869+ intel_power_domains_verify_state(dev_priv);
3870+ }
35903871
35913872 if (IS_ICELAKE(dev_priv))
35923873 icl_display_core_uninit(dev_priv);
@@ -3596,8 +3877,36 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv) · 3 unmodified lines
35963877 skl_display_core_uninit(dev_priv);
35973878 else if (IS_GEN9_LP(dev_priv))
35983879 bxt_display_core_uninit(dev_priv);
3880+
3881+ power_domains->display_core_suspended = true;
35993882 }
36003883
3884+/**
3885+ * intel_power_domains_resume - resume power domain state
3886+ * @dev_priv: i915 device instance
3887+ *
3888+ * This function resume the hardware power domain state during system resume.
3889+ *
3890+ * It will return with power domain support disabled (to be enabled later by
3891+ * intel_power_domains_enable()) and must be paired with
3892+ * intel_power_domains_suspend().
3893+ */
3894+void intel_power_domains_resume(struct drm_i915_private *dev_priv)
3895+{
3896+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
3897+
3898+ if (power_domains->display_core_suspended) {
3899+ intel_power_domains_init_hw(dev_priv, true);
3900+ power_domains->display_core_suspended = false;
3901+ } else {
3902+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3903+ }
3904+
3905+ intel_power_domains_verify_state(dev_priv);
3906+}
3907+
3908+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
3909+
36013910 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
36023911 {
36033912 struct i915_power_domains *power_domains = &dev_priv->power_domains;
@@ -3607,9 +3916,9 @@ static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) · 3 unmodified lines
36073916 enum intel_display_power_domain domain;
36083917
36093918 DRM_DEBUG_DRIVER("%-25s %d\n",
3610− power_well->name, power_well->count);
3919+ power_well->desc->name, power_well->count);
36113920
3612− for_each_power_domain(domain, power_well->domains)
3921+ for_each_power_domain(domain, power_well->desc->domains)
36133922 DRM_DEBUG_DRIVER(" %-23s %d\n",
36143923 intel_display_power_domain_str(domain),
36153924 power_domains->domain_use_count[domain]);
@@ -3626,7 +3935,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) · 10 unmodified lines
36263935 * acquiring reference counts for any power wells in use and disabling the
36273936 * ones left on by BIOS but not required by any active output.
36283937 */
3629−void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3938+static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
36303939 {
36313940 struct i915_power_domains *power_domains = &dev_priv->power_domains;
36323941 struct i915_power_well *power_well;
@@ -3645,22 +3954,25 @@ void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) · 12 unmodified lines
36453954 * and PW1 power wells) are under FW control, so ignore them,
36463955 * since their state can change asynchronously.
36473956 */
3648− if (!power_well->domains)
3957+ if (!power_well->desc->domains)
36493958 continue;
36503959
3651− enabled = power_well->ops->is_enabled(dev_priv, power_well);
3652− if ((power_well->count || power_well->always_on) != enabled)
3960+ enabled = power_well->desc->ops->is_enabled(dev_priv,
3961+ power_well);
3962+ if ((power_well->count || power_well->desc->always_on) !=
3963+ enabled)
36533964 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
3654− power_well->name, power_well->count, enabled);
3965+ power_well->desc->name,
3966+ power_well->count, enabled);
36553967
36563968 domains_count = 0;
3657− for_each_power_domain(domain, power_well->domains)
3969+ for_each_power_domain(domain, power_well->desc->domains)
36583970 domains_count += power_domains->domain_use_count[domain];
36593971
36603972 if (power_well->count != domains_count) {
36613973 DRM_ERROR("power well %s refcount/domain refcount mismatch "
36623974 "(refcount %d/domains refcount %d)\n",
3663− power_well->name, power_well->count,
3975+ power_well->desc->name, power_well->count,
36643976 domains_count);
36653977 dump_domain_info = true;
36663978 }
@@ -3678,6 +3990,14 @@ void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) · 11 unmodified lines
36783990 mutex_unlock(&power_domains->lock);
36793991 }
36803992
3993+#else
3994+
3995+static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3996+{
3997+}
3998+
3999+#endif
4000+
36814001 /**
36824002 * intel_runtime_pm_get - grab a runtime pm reference
36834003 * @dev_priv: i915 device instance
@@ -3791,14 +4111,24 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv) · 107 unmodified lines
37914111 * This function enables runtime pm at the end of the driver load sequence.
37924112 *
37934113 * Note that this function does currently not enable runtime pm for the
3794− * subordinate display power domains. That is only done on the first modeset
3795− * using intel_display_set_init_power().
4114+ * subordinate display power domains. That is done by
4115+ * intel_power_domains_enable().
37964116 */
37974117 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
37984118 {
37994119 struct pci_dev *pdev = dev_priv->drm.pdev;
38004120 struct device *kdev = &pdev->dev;
38014121
4122+ /*
4123+ * Disable the system suspend direct complete optimization, which can
4124+ * leave the device suspended skipping the driver's suspend handlers
4125+ * if the device was already runtime suspended. This is needed due to
4126+ * the difference in our runtime and system suspend sequence and
4127+ * becaue the HDA driver may require us to enable the audio power
4128+ * domain during system suspend.
4129+ */
4130+ dev_pm_set_driver_flags(kdev, DPM_FLAG_NEVER_SKIP);
4131+
38024132 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
38034133 pm_runtime_mark_last_busy(kdev);
38044134
@@ -3825,3 +4155,18 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) · 20 unmodified lines
38254155 */
38264156 pm_runtime_put_autosuspend(kdev);
38274157 }
4158+
4159+void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
4160+{
4161+ struct pci_dev *pdev = dev_priv->drm.pdev;
4162+ struct device *kdev = &pdev->dev;
4163+
4164+ /* Transfer rpm ownership back to core */
4165+ WARN(pm_runtime_get_sync(&dev_priv->drm.pdev->dev) < 0,
4166+ "Failed to pass rpm ownership back to core\n");
4167+
4168+ pm_runtime_dont_use_autosuspend(kdev);
4169+
4170+ if (!HAS_RUNTIME_PM(dev_priv))
4171+ pm_runtime_put(kdev);
4172+}
drivers/gpu/drm/i915/intel_sprite.c+7−6
@@ -83,6 +83,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) · 82 unmodified lines
8383 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8484 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
8585 DEFINE_WAIT(wait);
86+ u32 psr_status;
8687
8788 vblank_start = adjusted_mode->crtc_vblank_start;
8889 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -104,8 +105,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) · 15 unmodified lines
104105 * VBL interrupts will start the PSR exit and prevent a PSR
105106 * re-entry as well.
106107 */
107− if (intel_psr_wait_for_idle(new_crtc_state))
108− DRM_ERROR("PSR idle timed out, atomic update may fail\n");
108+ if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
109+ DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
110+ psr_status);
109111
110112 local_irq_disable();
111113
@@ -957,10 +959,10 @@ g4x_plane_get_hw_state(struct intel_plane *plane, · 845 unmodified lines
957959 }
958960
959961 static int
960−intel_check_sprite_plane(struct intel_plane *plane,
961− struct intel_crtc_state *crtc_state,
962+intel_check_sprite_plane(struct intel_crtc_state *crtc_state,
962963 struct intel_plane_state *state)
963964 {
965+ struct intel_plane *plane = to_intel_plane(state->base.plane);
964966 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
965967 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
966968 struct drm_framebuffer *fb = state->base.fb;
@@ -1407,8 +1409,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, · 440 unmodified lines
14071409 case DRM_FORMAT_XBGR8888:
14081410 case DRM_FORMAT_ARGB8888:
14091411 case DRM_FORMAT_ABGR8888:
1410− if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
1411− modifier == I915_FORMAT_MOD_Y_TILED_CCS)
1412+ if (is_ccs_modifier(modifier))
14121413 return true;
14131414 /* fall through */
14141415 case DRM_FORMAT_RGB565:
drivers/gpu/drm/i915/intel_uc_fw.c+1−1
@@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, · 221 unmodified lines
222222 goto fail;
223223 }
224224
225− ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
225+ ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
226226 vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
227227 PIN_OFFSET_BIAS | ggtt_pin_bias);
228228 if (IS_ERR(vma)) {
drivers/gpu/drm/i915/intel_uncore.c+92−38
@@ -283,14 +283,24 @@ fw_domains_reset(struct drm_i915_private *i915, · 282 unmodified lines
283283 fw_domain_reset(i915, d);
284284 }
285285
286+static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
287+{
288+ u32 val;
289+
290+ val = __raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG);
291+ val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
292+
293+ return val;
294+}
295+
286296 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
287297 {
288− /* w/a for a sporadic read returning 0 by waiting for the GT
298+ /*
299+ * w/a for a sporadic read returning 0 by waiting for the GT
289300 * thread to wake up.
290301 */
291− if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
292− GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
293− DRM_ERROR("GT thread status wait timed out\n");
302+ WARN_ONCE(wait_for_atomic_us(gt_thread_status(dev_priv) == 0, 5000),
303+ "GT thread status wait timed out\n");
294304 }
295305
296306 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
@@ -1729,7 +1739,7 @@ static void gen3_stop_engine(struct intel_engine_cs *engine) · 1432 unmodified lines
17291739 }
17301740
17311741 static void i915_stop_engines(struct drm_i915_private *dev_priv,
1732− unsigned engine_mask)
1742+ unsigned int engine_mask)
17331743 {
17341744 struct intel_engine_cs *engine;
17351745 enum intel_engine_id id;
@@ -1749,7 +1759,9 @@ static bool i915_in_reset(struct pci_dev *pdev) · 13 unmodified lines
17491759 return gdrst & GRDOM_RESET_STATUS;
17501760 }
17511761
1752−static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1762+static int i915_do_reset(struct drm_i915_private *dev_priv,
1763+ unsigned int engine_mask,
1764+ unsigned int retry)
17531765 {
17541766 struct pci_dev *pdev = dev_priv->drm.pdev;
17551767 int err;
@@ -1776,7 +1788,9 @@ static bool g4x_reset_complete(struct pci_dev *pdev) · 20 unmodified lines
17761788 return (gdrst & GRDOM_RESET_ENABLE) == 0;
17771789 }
17781790
1779−static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1791+static int g33_do_reset(struct drm_i915_private *dev_priv,
1792+ unsigned int engine_mask,
1793+ unsigned int retry)
17801794 {
17811795 struct pci_dev *pdev = dev_priv->drm.pdev;
17821796
@@ -1784,7 +1798,9 @@ static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) · 1 unmodified line
17841798 return wait_for(g4x_reset_complete(pdev), 500);
17851799 }
17861800
1787−static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1801+static int g4x_do_reset(struct drm_i915_private *dev_priv,
1802+ unsigned int engine_mask,
1803+ unsigned int retry)
17881804 {
17891805 struct pci_dev *pdev = dev_priv->drm.pdev;
17901806 int ret;
@@ -1821,7 +1837,8 @@ out: · 30 unmodified lines
18211837 }
18221838
18231839 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1824− unsigned engine_mask)
1840+ unsigned int engine_mask,
1841+ unsigned int retry)
18251842 {
18261843 int ret;
18271844
@@ -1877,6 +1894,7 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, · 49 unmodified lines
18771894 * gen6_reset_engines - reset individual engines
18781895 * @dev_priv: i915 device
18791896 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1897+ * @retry: the count of of previous attempts to reset.
18801898 *
18811899 * This function will reset the individual engines that are set in engine_mask.
18821900 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
@@ -1887,7 +1905,8 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, · 4 unmodified lines
18871905 * Returns 0 on success, nonzero on error.
18881906 */
18891907 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1890− unsigned engine_mask)
1908+ unsigned int engine_mask,
1909+ unsigned int retry)
18911910 {
18921911 struct intel_engine_cs *engine;
18931912 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
@@ -1926,7 +1945,7 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, · 32 unmodified lines
19261945 * Returns 0 on success, nonzero on error.
19271946 */
19281947 static int gen11_reset_engines(struct drm_i915_private *dev_priv,
1929− unsigned engine_mask)
1948+ unsigned int engine_mask)
19301949 {
19311950 struct intel_engine_cs *engine;
19321951 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
@@ -2066,7 +2085,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv, · 133 unmodified lines
20662085 return ret;
20672086 }
20682087
2069−static int gen8_reset_engine_start(struct intel_engine_cs *engine)
2088+static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
20702089 {
20712090 struct drm_i915_private *dev_priv = engine->i915;
20722091 int ret;
@@ -2086,7 +2105,7 @@ static int gen8_reset_engine_start(struct intel_engine_cs *engine) · 13 unmodified lines
20862105 return ret;
20872106 }
20882107
2089−static void gen8_reset_engine_cancel(struct intel_engine_cs *engine)
2108+static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
20902109 {
20912110 struct drm_i915_private *dev_priv = engine->i915;
20922111
@@ -2094,33 +2113,56 @@ static void gen8_reset_engine_cancel(struct intel_engine_cs *engine) · 1 unmodified line
20942113 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
20952114 }
20962115
2116+static int reset_engines(struct drm_i915_private *i915,
2117+ unsigned int engine_mask,
2118+ unsigned int retry)
2119+{
2120+ if (INTEL_GEN(i915) >= 11)
2121+ return gen11_reset_engines(i915, engine_mask);
2122+ else
2123+ return gen6_reset_engines(i915, engine_mask, retry);
2124+}
2125+
20972126 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
2098− unsigned engine_mask)
2127+ unsigned int engine_mask,
2128+ unsigned int retry)
20992129 {
21002130 struct intel_engine_cs *engine;
2131+ const bool reset_non_ready = retry >= 1;
21012132 unsigned int tmp;
21022133 int ret;
21032134
21042135 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
2105− if (gen8_reset_engine_start(engine)) {
2106− ret = -EIO;
2107− goto not_ready;
2108− }
2136+ ret = gen8_engine_reset_prepare(engine);
2137+ if (ret && !reset_non_ready)
2138+ goto skip_reset;
2139+
2140+ /*
2141+ * If this is not the first failed attempt to prepare,
2142+ * we decide to proceed anyway.
2143+ *
2144+ * By doing so we risk context corruption and with
2145+ * some gens (kbl), possible system hang if reset
2146+ * happens during active bb execution.
2147+ *
2148+ * We rather take context corruption instead of
2149+ * failed reset with a wedged driver/gpu. And
2150+ * active bb execution case should be covered by
2151+ * i915_stop_engines we have before the reset.
2152+ */
21092153 }
21102154
2111− if (INTEL_GEN(dev_priv) >= 11)
2112− ret = gen11_reset_engines(dev_priv, engine_mask);
2113− else
2114− ret = gen6_reset_engines(dev_priv, engine_mask);
2155+ ret = reset_engines(dev_priv, engine_mask, retry);
21152156
2116−not_ready:
2157+skip_reset:
21172158 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
2118− gen8_reset_engine_cancel(engine);
2159+ gen8_engine_reset_cancel(engine);
21192160
21202161 return ret;
21212162 }
21222163
2123−typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
2164+typedef int (*reset_func)(struct drm_i915_private *,
2165+ unsigned int engine_mask, unsigned int retry);
21242166
21252167 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
21262168 {
@@ -2143,12 +2185,15 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) · 16 unmodified lines
21432185 return NULL;
21442186 }
21452187
2146−int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
2188+int intel_gpu_reset(struct drm_i915_private *dev_priv,
2189+ const unsigned int engine_mask)
21472190 {
21482191 reset_func reset = intel_get_gpu_reset(dev_priv);
2149− int retry;
2192+ unsigned int retry;
21502193 int ret;
21512194
2195+ GEM_BUG_ON(!engine_mask);
2196+
21522197 /*
21532198 * We want to perform per-engine reset from atomic context (e.g.
21542199 * softirq), which imposes the constraint that we cannot sleep.
@@ -2190,8 +2235,9 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) · 35 unmodified lines
21902235
21912236 ret = -ENODEV;
21922237 if (reset) {
2193− GEM_TRACE("engine_mask=%x\n", engine_mask);
2194− ret = reset(dev_priv, engine_mask);
2238+ ret = reset(dev_priv, engine_mask, retry);
2239+ GEM_TRACE("engine_mask=%x, ret=%d, retry=%d\n",
2240+ engine_mask, ret, retry);
21952241 }
21962242 if (ret != -ETIMEDOUT || engine_mask != ALL_ENGINES)
21972243 break;
@@ -2237,20 +2283,28 @@ bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) · 39 unmodified lines
22372283 bool
22382284 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
22392285 {
2240− if (unlikely(i915_modparams.mmio_debug ||
2241− dev_priv->uncore.unclaimed_mmio_check <= 0))
2242− return false;
2286+ bool ret = false;
2287+
2288+ spin_lock_irq(&dev_priv->uncore.lock);
2289+
2290+ if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
2291+ goto out;
22432292
22442293 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
2245− DRM_DEBUG("Unclaimed register detected, "
2246− "enabling oneshot unclaimed register reporting. "
2247− "Please use i915.mmio_debug=N for more information.\n");
2248− i915_modparams.mmio_debug++;
2294+ if (!i915_modparams.mmio_debug) {
2295+ DRM_DEBUG("Unclaimed register detected, "
2296+ "enabling oneshot unclaimed register reporting. "
2297+ "Please use i915.mmio_debug=N for more information.\n");
2298+ i915_modparams.mmio_debug++;
2299+ }
22492300 dev_priv->uncore.unclaimed_mmio_check--;
2250− return true;
2301+ ret = true;
22512302 }
22522303
2253− return false;
2304+out:
2305+ spin_unlock_irq(&dev_priv->uncore.lock);
2306+
2307+ return ret;
22542308 }
22552309
22562310 static enum forcewake_domains
drivers/gpu/drm/i915/intel_wopcm.c+6−0
@@ -163,8 +163,14 @@ int intel_wopcm_init(struct intel_wopcm *wopcm) · 162 unmodified lines
163163 u32 guc_wopcm_rsvd;
164164 int err;
165165
166+ if (!USES_GUC(dev_priv))
167+ return 0;
168+
166169 GEM_BUG_ON(!wopcm->size);
167170
171+ if (i915_inject_load_failure())
172+ return -E2BIG;
173+
168174 if (guc_fw_size >= wopcm->size) {
169175 DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
170176 guc_fw_size / 1024);
drivers/gpu/drm/i915/selftests/huge_pages.c+6−5
@@ -906,7 +906,11 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) · 905 unmodified lines
906906 if (IS_ERR(obj))
907907 return ERR_CAST(obj);
908908
909− cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
909+ err = i915_gem_object_set_to_wc_domain(obj, true);
910+ if (err)
911+ goto err;
912+
913+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
910914 if (IS_ERR(cmd)) {
911915 err = PTR_ERR(cmd);
912916 goto err;
@@ -936,13 +940,10 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) · 23 unmodified lines
936940 }
937941
938942 *cmd = MI_BATCH_BUFFER_END;
943+ i915_gem_chipset_flush(i915);
939944
940945 i915_gem_object_unpin_map(obj);
941946
942− err = i915_gem_object_set_to_gtt_domain(obj, false);
943− if (err)
944− goto err;
945−
946947 batch = i915_vma_instance(obj, vma->vm, NULL);
947948 if (IS_ERR(batch)) {
948949 err = PTR_ERR(batch);
drivers/gpu/drm/i915/selftests/i915_gem.c+221−0
@@ -0,0 +1,221 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright © 2018 Intel Corporation
5+ */
6+
7+#include <linux/random.h>
8+
9+#include "../i915_selftest.h"
10+
11+#include "mock_context.h"
12+#include "igt_flush_test.h"
13+
14+static int switch_to_context(struct drm_i915_private *i915,
15+ struct i915_gem_context *ctx)
16+{
17+ struct intel_engine_cs *engine;
18+ enum intel_engine_id id;
19+ int err = 0;
20+
21+ intel_runtime_pm_get(i915);
22+
23+ for_each_engine(engine, i915, id) {
24+ struct i915_request *rq;
25+
26+ rq = i915_request_alloc(engine, ctx);
27+ if (IS_ERR(rq)) {
28+ err = PTR_ERR(rq);
29+ break;
30+ }
31+
32+ i915_request_add(rq);
33+ }
34+
35+ intel_runtime_pm_put(i915);
36+
37+ return err;
38+}
39+
40+static void trash_stolen(struct drm_i915_private *i915)
41+{
42+ struct i915_ggtt *ggtt = &i915->ggtt;
43+ const u64 slot = ggtt->error_capture.start;
44+ const resource_size_t size = resource_size(&i915->dsm);
45+ unsigned long page;
46+ u32 prng = 0x12345678;
47+
48+ for (page = 0; page < size; page += PAGE_SIZE) {
49+ const dma_addr_t dma = i915->dsm.start + page;
50+ u32 __iomem *s;
51+ int x;
52+
53+ ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
54+
55+ s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
56+ for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
57+ prng = next_pseudo_random32(prng);
58+ iowrite32(prng, &s[x]);
59+ }
60+ io_mapping_unmap_atomic(s);
61+ }
62+
63+ ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
64+}
65+
66+static void simulate_hibernate(struct drm_i915_private *i915)
67+{
68+ intel_runtime_pm_get(i915);
69+
70+ /*
71+ * As a final sting in the tail, invalidate stolen. Under a real S4,
72+ * stolen is lost and needs to be refilled on resume. However, under
73+ * CI we merely do S4-device testing (as full S4 is too unreliable
74+ * for automated testing across a cluster), so to simulate the effect
75+ * of stolen being trashed across S4, we trash it ourselves.
76+ */
77+ trash_stolen(i915);
78+
79+ intel_runtime_pm_put(i915);
80+}
81+
82+static int pm_prepare(struct drm_i915_private *i915)
83+{
84+ int err = 0;
85+
86+ if (i915_gem_suspend(i915)) {
87+ pr_err("i915_gem_suspend failed\n");
88+ err = -EINVAL;
89+ }
90+
91+ return err;
92+}
93+
94+static void pm_suspend(struct drm_i915_private *i915)
95+{
96+ intel_runtime_pm_get(i915);
97+
98+ i915_gem_suspend_gtt_mappings(i915);
99+ i915_gem_suspend_late(i915);
100+
101+ intel_runtime_pm_put(i915);
102+}
103+
104+static void pm_hibernate(struct drm_i915_private *i915)
105+{
106+ intel_runtime_pm_get(i915);
107+
108+ i915_gem_suspend_gtt_mappings(i915);
109+
110+ i915_gem_freeze(i915);
111+ i915_gem_freeze_late(i915);
112+
113+ intel_runtime_pm_put(i915);
114+}
115+
116+static void pm_resume(struct drm_i915_private *i915)
117+{
118+ /*
119+ * Both suspend and hibernate follow the same wakeup path and assume
120+ * that runtime-pm just works.
121+ */
122+ intel_runtime_pm_get(i915);
123+
124+ intel_engines_sanitize(i915);
125+ i915_gem_sanitize(i915);
126+ i915_gem_resume(i915);
127+
128+ intel_runtime_pm_put(i915);
129+}
130+
131+static int igt_gem_suspend(void *arg)
132+{
133+ struct drm_i915_private *i915 = arg;
134+ struct i915_gem_context *ctx;
135+ struct drm_file *file;
136+ int err;
137+
138+ file = mock_file(i915);
139+ if (IS_ERR(file))
140+ return PTR_ERR(file);
141+
142+ err = -ENOMEM;
143+ mutex_lock(&i915->drm.struct_mutex);
144+ ctx = live_context(i915, file);
145+ if (!IS_ERR(ctx))
146+ err = switch_to_context(i915, ctx);
147+ mutex_unlock(&i915->drm.struct_mutex);
148+ if (err)
149+ goto out;
150+
151+ err = pm_prepare(i915);
152+ if (err)
153+ goto out;
154+
155+ pm_suspend(i915);
156+
157+ /* Here be dragons! Note that with S3RST any S3 may become S4! */
158+ simulate_hibernate(i915);
159+
160+ pm_resume(i915);
161+
162+ mutex_lock(&i915->drm.struct_mutex);
163+ err = switch_to_context(i915, ctx);
164+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
165+ err = -EIO;
166+ mutex_unlock(&i915->drm.struct_mutex);
167+out:
168+ mock_file_free(i915, file);
169+ return err;
170+}
171+
172+static int igt_gem_hibernate(void *arg)
173+{
174+ struct drm_i915_private *i915 = arg;
175+ struct i915_gem_context *ctx;
176+ struct drm_file *file;
177+ int err;
178+
179+ file = mock_file(i915);
180+ if (IS_ERR(file))
181+ return PTR_ERR(file);
182+
183+ err = -ENOMEM;
184+ mutex_lock(&i915->drm.struct_mutex);
185+ ctx = live_context(i915, file);
186+ if (!IS_ERR(ctx))
187+ err = switch_to_context(i915, ctx);
188+ mutex_unlock(&i915->drm.struct_mutex);
189+ if (err)
190+ goto out;
191+
192+ err = pm_prepare(i915);
193+ if (err)
194+ goto out;
195+
196+ pm_hibernate(i915);
197+
198+ /* Here be dragons! */
199+ simulate_hibernate(i915);
200+
201+ pm_resume(i915);
202+
203+ mutex_lock(&i915->drm.struct_mutex);
204+ err = switch_to_context(i915, ctx);
205+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
206+ err = -EIO;
207+ mutex_unlock(&i915->drm.struct_mutex);
208+out:
209+ mock_file_free(i915, file);
210+ return err;
211+}
212+
213+int i915_gem_live_selftests(struct drm_i915_private *i915)
214+{
215+ static const struct i915_subtest tests[] = {
216+ SUBTEST(igt_gem_suspend),
217+ SUBTEST(igt_gem_hibernate),
218+ };
219+
220+ return i915_subtests(tests, i915);
221+}
drivers/gpu/drm/i915/selftests/i915_gem_coherency.c+17−21
@@ -33,7 +33,8 @@ static int cpu_set(struct drm_i915_gem_object *obj, · 32 unmodified lines
3333 {
3434 unsigned int needs_clflush;
3535 struct page *page;
36− u32 *map;
36+ void *map;
37+ u32 *cpu;
3738 int err;
3839
3940 err = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
@@ -42,24 +43,19 @@ static int cpu_set(struct drm_i915_gem_object *obj, · 2 unmodified lines
4243
4344 page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
4445 map = kmap_atomic(page);
46+ cpu = map + offset_in_page(offset);
4547
46− if (needs_clflush & CLFLUSH_BEFORE) {
47− mb();
48− clflush(map+offset_in_page(offset) / sizeof(*map));
49− mb();
50− }
48+ if (needs_clflush & CLFLUSH_BEFORE)
49+ drm_clflush_virt_range(cpu, sizeof(*cpu));
5150
52− map[offset_in_page(offset) / sizeof(*map)] = v;
51+ *cpu = v;
5352
54− if (needs_clflush & CLFLUSH_AFTER) {
55− mb();
56− clflush(map+offset_in_page(offset) / sizeof(*map));
57− mb();
58− }
53+ if (needs_clflush & CLFLUSH_AFTER)
54+ drm_clflush_virt_range(cpu, sizeof(*cpu));
5955
6056 kunmap_atomic(map);
61−
6257 i915_gem_obj_finish_shmem_access(obj);
58+
6359 return 0;
6460 }
6561
@@ -69,7 +65,8 @@ static int cpu_get(struct drm_i915_gem_object *obj, · 3 unmodified lines
6965 {
7066 unsigned int needs_clflush;
7167 struct page *page;
72− u32 *map;
68+ void *map;
69+ u32 *cpu;
7370 int err;
7471
7572 err = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
@@ -78,17 +75,16 @@ static int cpu_get(struct drm_i915_gem_object *obj, · 2 unmodified lines
7875
7976 page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
8077 map = kmap_atomic(page);
78+ cpu = map + offset_in_page(offset);
8179
82− if (needs_clflush & CLFLUSH_BEFORE) {
83− mb();
84− clflush(map+offset_in_page(offset) / sizeof(*map));
85− mb();
86− }
80+ if (needs_clflush & CLFLUSH_BEFORE)
81+ drm_clflush_virt_range(cpu, sizeof(*cpu));
8782
88− *v = map[offset_in_page(offset) / sizeof(*map)];
89− kunmap_atomic(map);
83+ *v = *cpu;
9084
85+ kunmap_atomic(map);
9186 i915_gem_obj_finish_shmem_access(obj);
87+
9288 return 0;
9389 }
9490
drivers/gpu/drm/i915/selftests/i915_gem_object.c+1−1
@@ -282,7 +282,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, · 281 unmodified lines
282282 view.partial.offset,
283283 view.partial.size,
284284 vma->size >> PAGE_SHIFT,
285− tile_row_pages(obj),
285+ tile->tiling ? tile_row_pages(obj) : 0,
286286 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
287287 offset >> PAGE_SHIFT,
288288 (unsigned int)offset_in_page(offset),
drivers/gpu/drm/i915/selftests/i915_live_selftests.h+1−0
@@ -17,6 +17,7 @@ selftest(objects, i915_gem_object_live_selftests) · 16 unmodified lines
1717 selftest(dmabuf, i915_gem_dmabuf_live_selftests)
1818 selftest(coherency, i915_gem_coherency_live_selftests)
1919 selftest(gtt, i915_gem_gtt_live_selftests)
20+selftest(gem, i915_gem_live_selftests)
2021 selftest(evict, i915_gem_evict_live_selftests)
2122 selftest(hugepages, i915_gem_huge_page_live_selftests)
2223 selftest(contexts, i915_gem_context_live_selftests)
drivers/gpu/drm/i915/selftests/intel_guc.c+38−0
@@ -65,6 +65,40 @@ static int check_all_doorbells(struct intel_guc *guc) · 64 unmodified lines
6565 return 0;
6666 }
6767
68+static int ring_doorbell_nop(struct intel_guc_client *client)
69+{
70+ struct guc_process_desc *desc = __get_process_desc(client);
71+ int err;
72+
73+ client->use_nop_wqi = true;
74+
75+ spin_lock_irq(&client->wq_lock);
76+
77+ guc_wq_item_append(client, 0, 0, 0, 0);
78+ guc_ring_doorbell(client);
79+
80+ spin_unlock_irq(&client->wq_lock);
81+
82+ client->use_nop_wqi = false;
83+
84+ /* if there are no issues GuC will update the WQ head and keep the
85+ * WQ in active status
86+ */
87+ err = wait_for(READ_ONCE(desc->head) == READ_ONCE(desc->tail), 10);
88+ if (err) {
89+ pr_err("doorbell %u ring failed!\n", client->doorbell_id);
90+ return -EIO;
91+ }
92+
93+ if (desc->wq_status != WQ_STATUS_ACTIVE) {
94+ pr_err("doorbell %u ring put WQ in bad state (%u)!\n",
95+ client->doorbell_id, desc->wq_status);
96+ return -EIO;
97+ }
98+
99+ return 0;
100+}
101+
68102 /*
69103 * Basic client sanity check, handy to validate create_clients.
70104 */
@@ -332,6 +366,10 @@ static int igt_guc_doorbells(void *arg) · 261 unmodified lines
332366 err = check_all_doorbells(guc);
333367 if (err)
334368 goto out;
369+
370+ err = ring_doorbell_nop(clients[i]);
371+ if (err)
372+ goto out;
335373 }
336374
337375 out:
drivers/gpu/drm/i915/selftests/intel_hangcheck.c+89−12
@@ -1018,8 +1018,41 @@ static int evict_vma(void *data) · 1017 unmodified lines
10181018 return err;
10191019 }
10201020
1021+static int evict_fence(void *data)
1022+{
1023+ struct evict_vma *arg = data;
1024+ struct drm_i915_private *i915 = arg->vma->vm->i915;
1025+ int err;
1026+
1027+ complete(&arg->completion);
1028+
1029+ mutex_lock(&i915->drm.struct_mutex);
1030+
1031+ /* Mark the fence register as dirty to force the mmio update. */
1032+ err = i915_gem_object_set_tiling(arg->vma->obj, I915_TILING_Y, 512);
1033+ if (err) {
1034+ pr_err("Invalid Y-tiling settings; err:%d\n", err);
1035+ goto out_unlock;
1036+ }
1037+
1038+ err = i915_vma_pin_fence(arg->vma);
1039+ if (err) {
1040+ pr_err("Unable to pin Y-tiled fence; err:%d\n", err);
1041+ goto out_unlock;
1042+ }
1043+
1044+ i915_vma_unpin_fence(arg->vma);
1045+
1046+out_unlock:
1047+ mutex_unlock(&i915->drm.struct_mutex);
1048+
1049+ return err;
1050+}
1051+
10211052 static int __igt_reset_evict_vma(struct drm_i915_private *i915,
1022− struct i915_address_space *vm)
1053+ struct i915_address_space *vm,
1054+ int (*fn)(void *),
1055+ unsigned int flags)
10231056 {
10241057 struct drm_i915_gem_object *obj;
10251058 struct task_struct *tsk = NULL;
@@ -1040,12 +1073,20 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 14 unmodified lines
10401073 if (err)
10411074 goto unlock;
10421075
1043− obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1076+ obj = i915_gem_object_create_internal(i915, SZ_1M);
10441077 if (IS_ERR(obj)) {
10451078 err = PTR_ERR(obj);
10461079 goto fini;
10471080 }
10481081
1082+ if (flags & EXEC_OBJECT_NEEDS_FENCE) {
1083+ err = i915_gem_object_set_tiling(obj, I915_TILING_X, 512);
1084+ if (err) {
1085+ pr_err("Invalid X-tiling settings; err:%d\n", err);
1086+ goto out_obj;
1087+ }
1088+ }
1089+
10491090 arg.vma = i915_vma_instance(obj, vm, NULL);
10501091 if (IS_ERR(arg.vma)) {
10511092 err = PTR_ERR(arg.vma);
@@ -1059,11 +1100,28 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 7 unmodified lines
10591100 }
10601101
10611102 err = i915_vma_pin(arg.vma, 0, 0,
1062− i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER);
1063− if (err)
1103+ i915_vma_is_ggtt(arg.vma) ?
1104+ PIN_GLOBAL | PIN_MAPPABLE :
1105+ PIN_USER);
1106+ if (err) {
1107+ i915_request_add(rq);
10641108 goto out_obj;
1109+ }
1110+
1111+ if (flags & EXEC_OBJECT_NEEDS_FENCE) {
1112+ err = i915_vma_pin_fence(arg.vma);
1113+ if (err) {
1114+ pr_err("Unable to pin X-tiled fence; err:%d\n", err);
1115+ i915_vma_unpin(arg.vma);
1116+ i915_request_add(rq);
1117+ goto out_obj;
1118+ }
1119+ }
1120+
1121+ err = i915_vma_move_to_active(arg.vma, rq, flags);
10651122
1066− err = i915_vma_move_to_active(arg.vma, rq, EXEC_OBJECT_WRITE);
1123+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
1124+ i915_vma_unpin_fence(arg.vma);
10671125 i915_vma_unpin(arg.vma);
10681126
10691127 i915_request_get(rq);
@@ -1086,7 +1144,7 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 16 unmodified lines
10861144
10871145 init_completion(&arg.completion);
10881146
1089− tsk = kthread_run(evict_vma, &arg, "igt/evict_vma");
1147+ tsk = kthread_run(fn, &arg, "igt/evict_vma");
10901148 if (IS_ERR(tsk)) {
10911149 err = PTR_ERR(tsk);
10921150 tsk = NULL;
@@ -1137,29 +1195,47 @@ static int igt_reset_evict_ggtt(void *arg) · 44 unmodified lines
11371195 {
11381196 struct drm_i915_private *i915 = arg;
11391197
1140− return __igt_reset_evict_vma(i915, &i915->ggtt.vm);
1198+ return __igt_reset_evict_vma(i915, &i915->ggtt.vm,
1199+ evict_vma, EXEC_OBJECT_WRITE);
11411200 }
11421201
11431202 static int igt_reset_evict_ppgtt(void *arg)
11441203 {
11451204 struct drm_i915_private *i915 = arg;
11461205 struct i915_gem_context *ctx;
1206+ struct drm_file *file;
11471207 int err;
11481208
1209+ file = mock_file(i915);
1210+ if (IS_ERR(file))
1211+ return PTR_ERR(file);
1212+
11491213 mutex_lock(&i915->drm.struct_mutex);
1150− ctx = kernel_context(i915);
1214+ ctx = live_context(i915, file);
11511215 mutex_unlock(&i915->drm.struct_mutex);
1152− if (IS_ERR(ctx))
1153− return PTR_ERR(ctx);
1216+ if (IS_ERR(ctx)) {
1217+ err = PTR_ERR(ctx);
1218+ goto out;
1219+ }
11541220
11551221 err = 0;
11561222 if (ctx->ppgtt) /* aliasing == global gtt locking, covered above */
1157− err = __igt_reset_evict_vma(i915, &ctx->ppgtt->vm);
1223+ err = __igt_reset_evict_vma(i915, &ctx->ppgtt->vm,
1224+ evict_vma, EXEC_OBJECT_WRITE);
11581225
1159− kernel_context_close(ctx);
1226+out:
1227+ mock_file_free(i915, file);
11601228 return err;
11611229 }
11621230
1231+static int igt_reset_evict_fence(void *arg)
1232+{
1233+ struct drm_i915_private *i915 = arg;
1234+
1235+ return __igt_reset_evict_vma(i915, &i915->ggtt.vm,
1236+ evict_fence, EXEC_OBJECT_NEEDS_FENCE);
1237+}
1238+
11631239 static int wait_for_others(struct drm_i915_private *i915,
11641240 struct intel_engine_cs *exclude)
11651241 {
@@ -1409,6 +1485,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) · 243 unmodified lines
14091485 SUBTEST(igt_reset_wait),
14101486 SUBTEST(igt_reset_evict_ggtt),
14111487 SUBTEST(igt_reset_evict_ppgtt),
1488+ SUBTEST(igt_reset_evict_fence),
14121489 SUBTEST(igt_handle_error),
14131490 };
14141491 bool saved_hangcheck;
drivers/gpu/drm/i915/selftests/mock_context.c+3−8
@@ -43,6 +43,7 @@ mock_context(struct drm_i915_private *i915, · 42 unmodified lines
4343
4444 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
4545 INIT_LIST_HEAD(&ctx->handles_list);
46+ INIT_LIST_HEAD(&ctx->hw_id_link);
4647
4748 for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
4849 struct intel_context *ce = &ctx->__engine[n];
@@ -50,11 +51,9 @@ mock_context(struct drm_i915_private *i915, · 1 unmodified line
5051 ce->gem_context = ctx;
5152 }
5253
53− ret = ida_simple_get(&i915->contexts.hw_ida,
54− 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
54+ ret = i915_gem_context_pin_hw_id(ctx);
5555 if (ret < 0)
5656 goto err_handles;
57− ctx->hw_id = ret;
5857
5958 if (name) {
6059 ctx->name = kstrdup(name, GFP_KERNEL);
@@ -85,11 +84,7 @@ void mock_context_close(struct i915_gem_context *ctx) · 24 unmodified lines
8584
8685 void mock_init_contexts(struct drm_i915_private *i915)
8786 {
88− INIT_LIST_HEAD(&i915->contexts.list);
89− ida_init(&i915->contexts.hw_ida);
90−
91− INIT_WORK(&i915->contexts.free_work, contexts_free_worker);
92− init_llist_head(&i915->contexts.free_list);
87+ init_contexts(i915);
9388 }
9489
9590 struct i915_gem_context *
drivers/gpu/drm/i915/selftests/mock_gtt.c+2−0
@@ -118,6 +118,8 @@ void mock_init_ggtt(struct drm_i915_private *i915) · 117 unmodified lines
118118 ggtt->vm.vma_ops.clear_pages = clear_pages;
119119
120120 i915_address_space_init(&ggtt->vm, i915);
121+
122+ ggtt->vm.is_ggtt = true;
121123 }
122124
123125 void mock_fini_ggtt(struct drm_i915_private *i915)
include/drm/i915_pciids.h+1−0
@@ -386,6 +386,7 @@ · 385 unmodified lines
386386 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
387387 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
388388 INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
389+ INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
389390 INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
390391
391392 /* CFL H */
include/uapi/drm/i915_drm.h+22−0
@@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait { · 528 unmodified lines
529529 */
530530 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
531531
532+/*
533+ * Once upon a time we supposed that writes through the GGTT would be
534+ * immediately in physical memory (once flushed out of the CPU path). However,
535+ * on a few different processors and chipsets, this is not necessarily the case
536+ * as the writes appear to be buffered internally. Thus a read of the backing
537+ * storage (physical memory) via a different path (with different physical tags
538+ * to the indirect write via the GGTT) will see stale values from before
539+ * the GGTT write. Inside the kernel, we can for the most part keep track of
540+ * the different read/write domains in use (e.g. set-domain), but the assumption
541+ * of coherency is baked into the ABI, hence reporting its true state in this
542+ * parameter.
543+ *
544+ * Reports true when writes via mmap_gtt are immediately visible following an
545+ * lfence to flush the WCB.
546+ *
547+ * Reports false when writes via mmap_gtt are indeterminately delayed in an in
548+ * internal buffer and are _not_ immediately visible to third parties accessing
549+ * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
550+ * communications channel when reporting false is strongly disadvised.
551+ */
552+#define I915_PARAM_MMAP_GTT_COHERENT 52
553+
532554 typedef struct drm_i915_getparam {
533555 __s32 param;
534556 /*

Keyboard shortcuts

General

Show keyboard shortcuts
?
Focus the current search
/

Issues and pull requests

Open filters
f

Issues, pull requests and Inbox

Select next item
j↓
Select previous item
k↑
Open selected item
Enter
Dismiss filters or clear selection
Esc

Repository code

Go to file
t