History

Merge tag 'drm-fixes-2023-12-01' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "Weekly fixes, mostly amdgpu fixes with a scattering of nouveau, i915, and a couple of reverts. Hopefully it will quieten down in coming weeks. drm: - Revert unexport of prime helpers for fd/handle conversion dma_resv: - Do not double add fences in dma_resv_add_fence. gpuvm: - Fix GPUVM license identifier. i915: - Mark internal GSC engine with reserved uabi class - Take VGA converters into account in eDP probe - Fix intel_pre_plane_updates() call to ensure workarounds get applied panel: - Revert panel fixes as they require exporting device_is_dependent. nouveau: - fix oversized allocations in new vm path - fix zero-length array - remove a stray lock nt36523: - Fix error check for nt36523. amdgpu: - DMUB fix - DCN 3.5 fixes - XGMI fix - DCN 3.2 fixes - Vangogh suspend fix - NBIO 7.9 fix - GFX11 golden register fix - Backlight fix - NBIO 7.11 fix - IB test overflow fix - DCN 3.1.4 fixes - fix a runtime pm ref count - Retimer fix - ABM fix - DCN 3.1.5 fix - Fix AGP addressing - Fix possible memory leak in SMU error path - Make sure PME is enabled in D3 - Fix possible NULL pointer dereference in debugfs - EEPROM fix - GC 9.4.3 fix amdkfd: - IP version check fix - Fix memory leak in pqm_uninit()" * tag 'drm-fixes-2023-12-01' of git://anongit.freedesktop.org/drm/drm: (53 commits) Revert "drm/prime: Unexport helpers for fd/handle conversion" drm/amdgpu: Use another offset for GC 9.4.3 remap drm/amd/display: Fix some HostVM parameters in DML drm/amdkfd: Free gang_ctx_bo and wptr_bo in pqm_uninit drm/amdgpu: Update EEPROM I2C address for smu v13_0_0 drm/amd/display: Allow DTBCLK disable for DCN35 drm/amdgpu: Fix cat debugfs amdgpu_regs_didt causes kernel null pointer drm/amd: Enable PCIe PME from D3 drm/amd/pm: fix a memleak in aldebaran_tables_init drm/amdgpu: fix AGP addressing when GART is not at 0 drm/amd/display: update dcn315 lpddr pstate latency drm/amd/display: fix ABM disablement drm/amd/display: Fix black screen on video playback with embedded panel drm/amd/display: Fix conversions between bytes and KB drm/amdkfd: Use common function for IP version check drm/amd/display: Remove config update drm/amd/display: Update DCN35 clock table policy drm/amd/display: force toggle rate wa for first link training for a retimer drm/amdgpu: correct the amdgpu runtime dereference usage count drm/amd/display: Update min Z8 residency time to 2100 for DCN314 ...

Linus Torvalds committed 2 years ago

Commit b1e51582 parents c9a925b 908f60667 files · +537 −302Browse files

Unified · Split

67 files
  1. drivers/dma-buf/dma-resv.c +1 −1
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +1 −1
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +6 −0
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +4 −0
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +3 −6
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +2 −0
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +3 −0
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +7 −3
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +6 −0
  10. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 −3
  11. drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +9 −1
  12. drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +2 −2
  13. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +2 −2
  14. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +2 −2
  15. drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c +9 −9
  16. drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +0 −5
  17. drivers/gpu/drm/amd/amdgpu/soc15.c +5 −0
  18. drivers/gpu/drm/amd/amdkfd/kfd_priv.h +1 −1
  19. drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +33 −21
  20. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +5 −3
  21. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +4 −4
  22. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +79 −80
  23. drivers/gpu/drm/amd/display/dc/dc.h +1 −1
  24. drivers/gpu/drm/amd/display/dc/dc_types.h +0 −4
  25. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +1 −1
  26. drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c +10 −0
  27. drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c +8 −1
  28. drivers/gpu/drm/amd/display/dc/dml/dc_features.h +1 −1
  29. drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +1 −14
  30. drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +14 −9
  31. drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +80 −4
  32. drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h +2 −0
  33. drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +8 −8
  34. drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +40 −20
  35. drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h +2 −0
  36. drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +2 −4
  37. drivers/gpu/drm/amd/display/dc/link/link_detection.c +1 −1
  38. drivers/gpu/drm/amd/display/dc/link/link_dpms.c +1 −2
  39. drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c +3 −3
  40. drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +3 −13
  41. drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +0 −1
  42. drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +1 −0
  43. drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h +2 −0
  44. drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h +2 −0
  45. drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h +29 −0
  46. drivers/gpu/drm/amd/include/kgd_pp_interface.h +1 −0
  47. drivers/gpu/drm/amd/pm/amdgpu_dpm.c +18 −0
  48. drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +2 −0
  49. drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +10 −0
  50. drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +5 −0
  51. drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +2 −3
  52. drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +4 −1
  53. drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +1 −0
  54. drivers/gpu/drm/bridge/panel.c +0 −17
  55. drivers/gpu/drm/drm_gpuvm.c +1 −1
  56. drivers/gpu/drm/drm_prime.c +18 −15
  57. drivers/gpu/drm/i915/display/intel_display.c +2 −1
  58. drivers/gpu/drm/i915/display/intel_dp.c +22 −6
  59. drivers/gpu/drm/i915/gt/intel_engine_user.c +22 −17
  60. drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h +1 −1
  61. drivers/gpu/drm/nouveau/nouveau_bo.c +3 −2
  62. drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c +2 −4
  63. drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +1 −0
  64. drivers/gpu/drm/panel/panel-novatek-nt36523.c +2 −2
  65. include/drm/drm_gpuvm.h +1 −1
  66. include/drm/drm_prime.h +7 −0
  67. include/linux/dma-fence.h +15 −0
drivers/dma-buf/dma-resv.c+1−1
@@ -301,7 +301,7 @@ void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, · 300 unmodified lines
301 301
302 dma_resv_list_entry(fobj, i, obj, &old, &old_usage);302 dma_resv_list_entry(fobj, i, obj, &old, &old_usage);
303 if ((old->context == fence->context && old_usage >= usage &&303 if ((old->context == fence->context && old_usage >= usage &&
304 dma_fence_is_later(fence, old)) ||304 dma_fence_is_later_or_same(fence, old)) ||
305 dma_fence_is_signaled(old)) {305 dma_fence_is_signaled(old)) {
306 dma_resv_list_set(fobj, i, fence, usage);306 dma_resv_list_set(fobj, i, fence, usage);
307 dma_fence_put(old);307 dma_fence_put(old);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+1−1
@@ -547,7 +547,7 @@ int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, · 546 unmodified lines
547 struct amdgpu_device *adev = dst, *peer_adev;547 struct amdgpu_device *adev = dst, *peer_adev;
548 int num_links;548 int num_links;
549 549
550 if (adev->asic_type != CHIP_ALDEBARAN)550 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))
551 return 0;551 return 0;
552 552
553 if (src)553 if (src)
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+6−0
@@ -638,6 +638,9 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, · 637 unmodified lines
638 if (size & 0x3 || *pos & 0x3)638 if (size & 0x3 || *pos & 0x3)
639 return -EINVAL;639 return -EINVAL;
640 640
641 if (!adev->didt_rreg)
642 return -EOPNOTSUPP;
643
641 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);644 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
642 if (r < 0) {645 if (r < 0) {
643 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);646 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -694,6 +697,9 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user · 50 unmodified lines
694 if (size & 0x3 || *pos & 0x3)697 if (size & 0x3 || *pos & 0x3)
695 return -EINVAL;698 return -EINVAL;
696 699
700 if (!adev->didt_wreg)
701 return -EOPNOTSUPP;
702
697 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);703 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
698 if (r < 0) {704 if (r < 0) {
699 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);705 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+4−0
@@ -4538,6 +4538,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) · 4537 unmodified lines
4538 if (amdgpu_sriov_vf(adev))4538 if (amdgpu_sriov_vf(adev))
4539 amdgpu_virt_release_full_gpu(adev, false);4539 amdgpu_virt_release_full_gpu(adev, false);
4540 4540
4541 r = amdgpu_dpm_notify_rlc_state(adev, false);
4542 if (r)
4543 return r;
4544
4541 return 0;4545 return 0;
4542}4546}
4543 4547
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+3−6
@@ -340,14 +340,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, · 339 unmodified lines
340 adev->have_disp_power_ref = true;340 adev->have_disp_power_ref = true;
341 return ret;341 return ret;
342 }342 }
343 /* if we have no active crtcs, then drop the power ref343 /* if we have no active crtcs, then go to
344 * we got before344 * drop the power ref we got before
345 */345 */
346 if (!active && adev->have_disp_power_ref) {346 if (!active && adev->have_disp_power_ref)
347 pm_runtime_put_autosuspend(dev->dev);
348 adev->have_disp_power_ref = false;347 adev->have_disp_power_ref = false;
349 }
350
351out:348out:
352 /* drop the power reference we got coming in here */349 /* drop the power reference we got coming in here */
353 pm_runtime_put_autosuspend(dev->dev);350 pm_runtime_put_autosuspend(dev->dev);
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+2−0
@@ -2263,6 +2263,8 @@ retry_init: · 2262 unmodified lines
2263 pm_runtime_mark_last_busy(ddev->dev);2263 pm_runtime_mark_last_busy(ddev->dev);
2264 pm_runtime_put_autosuspend(ddev->dev);2264 pm_runtime_put_autosuspend(ddev->dev);
2265 2265
2266 pci_wake_from_d3(pdev, TRUE);
2267
2266 /*2268 /*
2267 * For runpm implemented via BACO, PMFW will handle the2269 * For runpm implemented via BACO, PMFW will handle the
2268 * timing for BACO in and out:2270 * timing for BACO in and out:
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+3−0
@@ -181,6 +181,9 @@ uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) · 180 unmodified lines
181{181{
182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
183 183
184 if (!bo->ttm)
185 return AMDGPU_BO_INVALID_OFFSET;
186
184 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)187 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
185 return AMDGPU_BO_INVALID_OFFSET;188 return AMDGPU_BO_INVALID_OFFSET;
186 189
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+7−3
@@ -1527,10 +1527,14 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) · 1526 unmodified lines
1527u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)1527u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1528{1528{
1529 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);1529 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1530 uint64_t offset;1530 uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
1531 1531
1532 offset = (bo->tbo.resource->start << PAGE_SHIFT) +1532 if (bo->tbo.resource->mem_type == TTM_PL_TT)
1533 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);1533 offset = amdgpu_gmc_agp_addr(&bo->tbo);
1534
1535 if (offset == AMDGPU_BO_INVALID_OFFSET)
1536 offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1537 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1534 1538
1535 return amdgpu_gmc_sign_extend(offset);1539 return amdgpu_gmc_sign_extend(offset);
1536}1540}
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+6−0
@@ -214,6 +214,12 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, · 213 unmodified lines
214 control->i2c_address = EEPROM_I2C_MADDR_0;214 control->i2c_address = EEPROM_I2C_MADDR_0;
215 return true;215 return true;
216 case IP_VERSION(13, 0, 0):216 case IP_VERSION(13, 0, 0):
217 if (strnstr(atom_ctx->vbios_pn, "D707",
218 sizeof(atom_ctx->vbios_pn)))
219 control->i2c_address = EEPROM_I2C_MADDR_0;
220 else
221 control->i2c_address = EEPROM_I2C_MADDR_4;
222 return true;
217 case IP_VERSION(13, 0, 6):223 case IP_VERSION(13, 0, 6):
218 case IP_VERSION(13, 0, 10):224 case IP_VERSION(13, 0, 10):
219 control->i2c_address = EEPROM_I2C_MADDR_4;225 control->i2c_address = EEPROM_I2C_MADDR_4;
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+1−3
@@ -959,10 +959,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 958 unmodified lines
959 return 0;959 return 0;
960 960
961 addr = amdgpu_gmc_agp_addr(bo);961 addr = amdgpu_gmc_agp_addr(bo);
962 if (addr != AMDGPU_BO_INVALID_OFFSET) {962 if (addr != AMDGPU_BO_INVALID_OFFSET)
963 bo->resource->start = addr >> PAGE_SHIFT;
964 return 0;963 return 0;
965 }
966 964
967 /* allocate GART space */965 /* allocate GART space */
968 placement.num_placement = 1;966 placement.num_placement = 1;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+9−1
@@ -89,6 +89,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); · 88 unmodified lines
89MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");89MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
90MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");90MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
91 91
92static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
93 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
94};
95
92static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =96static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
93{97{
94 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),98 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
@@ -304,6 +308,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) · 209 unmodified lines
304 default:308 default:
305 break;309 break;
306 }310 }
311 soc15_program_register_sequence(adev,
312 golden_settings_gc_11_0,
313 (const u32)ARRAY_SIZE(golden_settings_gc_11_0));
314
307}315}
308 316
309static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,317static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
@@ -419,7 +427,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 109 unmodified lines
419 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);427 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
420 cpu_ptr = &adev->wb.wb[index];428 cpu_ptr = &adev->wb.wb[index];
421 429
422 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);430 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
423 if (r) {431 if (r) {
424 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);432 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
425 goto err1;433 goto err1;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+2−2
@@ -883,8 +883,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 882 unmodified lines
883 gpu_addr = adev->wb.gpu_addr + (index * 4);883 gpu_addr = adev->wb.gpu_addr + (index * 4);
884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
885 memset(&ib, 0, sizeof(ib));885 memset(&ib, 0, sizeof(ib));
886 r = amdgpu_ib_get(adev, NULL, 16,886
887 AMDGPU_IB_POOL_DIRECT, &ib);887 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
888 if (r)888 if (r)
889 goto err1;889 goto err1;
890 890
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+2−2
@@ -1039,8 +1039,8 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 1038 unmodified lines
1039 gpu_addr = adev->wb.gpu_addr + (index * 4);1039 gpu_addr = adev->wb.gpu_addr + (index * 4);
1040 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);1040 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
1041 memset(&ib, 0, sizeof(ib));1041 memset(&ib, 0, sizeof(ib));
1042 r = amdgpu_ib_get(adev, NULL, 16,1042
1043 AMDGPU_IB_POOL_DIRECT, &ib);1043 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
1044 if (r)1044 if (r)
1045 goto err1;1045 goto err1;
1046 1046
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c+2−2
@@ -297,8 +297,8 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 296 unmodified lines
297 gpu_addr = adev->wb.gpu_addr + (index * 4);297 gpu_addr = adev->wb.gpu_addr + (index * 4);
298 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);298 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
299 memset(&ib, 0, sizeof(ib));299 memset(&ib, 0, sizeof(ib));
300 r = amdgpu_ib_get(adev, NULL, 16,300
301 AMDGPU_IB_POOL_DIRECT, &ib);301 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
302 if (r)302 if (r)
303 goto err1;303 goto err1;
304 304
drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c+9−9
@@ -259,17 +259,17 @@ const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = { · 258 unmodified lines
259 259
260static void nbio_v7_11_init_registers(struct amdgpu_device *adev)260static void nbio_v7_11_init_registers(struct amdgpu_device *adev)
261{261{
262/* uint32_t def, data;262 uint32_t def, data;
263
264 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);
265 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
266 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
267 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
268 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
263 269
264 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);270 if (def != data)
265 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,271 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);
266 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
267 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
268 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
269 272
270 if (def != data)
271 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);
272*/
273}273}
274 274
275static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,275static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c+0−5
@@ -611,11 +611,6 @@ static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device · 610 unmodified lines
611 611
612 dev_info(adev->dev, "RAS controller interrupt triggered "612 dev_info(adev->dev, "RAS controller interrupt triggered "
613 "by NBIF error\n");613 "by NBIF error\n");
614
615 /* ras_controller_int is dedicated for nbif ras error,
616 * not the global interrupt for sync flood
617 */
618 amdgpu_ras_reset_gpu(adev);
619 }614 }
620 615
621 amdgpu_ras_error_data_fini(&err_data);616 amdgpu_ras_error_data_fini(&err_data);
drivers/gpu/drm/amd/amdgpu/soc15.c+5−0
@@ -1161,6 +1161,11 @@ static int soc15_common_early_init(void *handle) · 1160 unmodified lines
1161 AMD_PG_SUPPORT_VCN_DPG |1161 AMD_PG_SUPPORT_VCN_DPG |
1162 AMD_PG_SUPPORT_JPEG;1162 AMD_PG_SUPPORT_JPEG;
1163 adev->external_rev_id = adev->rev_id + 0x46;1163 adev->external_rev_id = adev->rev_id + 0x46;
1164 /* GC 9.4.3 uses MMIO register region hole at a different offset */
1165 if (!amdgpu_sriov_vf(adev)) {
1166 adev->rmmio_remap.reg_offset = 0x1A000;
1167 adev->rmmio_remap.bus_addr = adev->rmmio_base + 0x1A000;
1168 }
1164 break;1169 break;
1165 default:1170 default:
1166 /* FIXME: not supported yet */1171 /* FIXME: not supported yet */
drivers/gpu/drm/amd/amdkfd/kfd_priv.h+1−1
@@ -1128,7 +1128,7 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, · 1127 unmodified lines
1128 struct kfd_dev *dev = adev->kfd.dev;1128 struct kfd_dev *dev = adev->kfd.dev;
1129 uint32_t i;1129 uint32_t i;
1130 1130
1131 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3))1131 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3))
1132 return dev->nodes[0];1132 return dev->nodes[0];
1133 1133
1134 for (i = 0; i < dev->num_nodes; i++)1134 for (i = 0; i < dev->num_nodes; i++)
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+33−21
@@ -169,16 +169,43 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) · 168 unmodified lines
169 return 0;169 return 0;
170}170}
171 171
172static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
173 struct process_queue_node *pqn)
174{
175 struct kfd_node *dev;
176 struct kfd_process_device *pdd;
177
178 dev = pqn->q->device;
179
180 pdd = kfd_get_process_device_data(dev, pqm->process);
181 if (!pdd) {
182 pr_err("Process device data doesn't exist\n");
183 return;
184 }
185
186 if (pqn->q->gws) {
187 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
188 !dev->kfd->shared_resources.enable_mes)
189 amdgpu_amdkfd_remove_gws_from_process(
190 pqm->process->kgd_process_info, pqn->q->gws);
191 pdd->qpd.num_gws = 0;
192 }
193
194 if (dev->kfd->shared_resources.enable_mes) {
195 amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->gang_ctx_bo);
196 if (pqn->q->wptr_bo)
197 amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
198 }
199}
200
172void pqm_uninit(struct process_queue_manager *pqm)201void pqm_uninit(struct process_queue_manager *pqm)
173{202{
174 struct process_queue_node *pqn, *next;203 struct process_queue_node *pqn, *next;
175 204
176 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {205 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
177 if (pqn->q && pqn->q->gws &&206 if (pqn->q)
178 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&207 pqm_clean_queue_resource(pqm, pqn);
179 !pqn->q->device->kfd->shared_resources.enable_mes)208
180 amdgpu_amdkfd_remove_gws_from_process(pqm->process->kgd_process_info,
181 pqn->q->gws);
182 kfd_procfs_del_queue(pqn->q);209 kfd_procfs_del_queue(pqn->q);
183 uninit_queue(pqn->q);210 uninit_queue(pqn->q);
184 list_del(&pqn->process_queue_list);211 list_del(&pqn->process_queue_list);
@@ -461,22 +488,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) · 276 unmodified lines
461 goto err_destroy_queue;488 goto err_destroy_queue;
462 }489 }
463 490
464 if (pqn->q->gws) {491 pqm_clean_queue_resource(pqm, pqn);
465 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
466 !dev->kfd->shared_resources.enable_mes)
467 amdgpu_amdkfd_remove_gws_from_process(
468 pqm->process->kgd_process_info,
469 pqn->q->gws);
470 pdd->qpd.num_gws = 0;
471 }
472
473 if (dev->kfd->shared_resources.enable_mes) {
474 amdgpu_amdkfd_free_gtt_mem(dev->adev,
475 pqn->q->gang_ctx_bo);
476 if (pqn->q->wptr_bo)
477 amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
478
479 }
480 uninit_queue(pqn->q);492 uninit_queue(pqn->q);
481 }493 }
482 494
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+5−3
@@ -6267,7 +6267,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, · 6266 unmodified lines
6267 dm_new_state->underscan_enable = val;6267 dm_new_state->underscan_enable = val;
6268 ret = 0;6268 ret = 0;
6269 } else if (property == adev->mode_info.abm_level_property) {6269 } else if (property == adev->mode_info.abm_level_property) {
6270 dm_new_state->abm_level = val;6270 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
6271 ret = 0;6271 ret = 0;
6272 }6272 }
6273 6273
@@ -6312,7 +6312,8 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, · 38 unmodified lines
6312 *val = dm_state->underscan_enable;6312 *val = dm_state->underscan_enable;
6313 ret = 0;6313 ret = 0;
6314 } else if (property == adev->mode_info.abm_level_property) {6314 } else if (property == adev->mode_info.abm_level_property) {
6315 *val = dm_state->abm_level;6315 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6316 dm_state->abm_level : 0;
6316 ret = 0;6317 ret = 0;
6317 }6318 }
6318 6319
@@ -6385,7 +6386,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) · 66 unmodified lines
6385 state->pbn = 0;6386 state->pbn = 0;
6386 6387
6387 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)6388 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6388 state->abm_level = amdgpu_dm_abm_level;6389 state->abm_level = amdgpu_dm_abm_level ?:
6390 ABM_LEVEL_IMMEDIATE_DISABLE;
6389 6391
6390 __drm_atomic_helper_connector_reset(connector, &state->base);6392 __drm_atomic_helper_connector_reset(connector, &state->base);
6391 }6393 }
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c+4−4
@@ -334,7 +334,7 @@ static struct wm_table lpddr5_wm_table = { · 333 unmodified lines
334 {334 {
335 .wm_inst = WM_A,335 .wm_inst = WM_A,
336 .wm_type = WM_TYPE_PSTATE_CHG,336 .wm_type = WM_TYPE_PSTATE_CHG,
337 .pstate_latency_us = 11.65333,337 .pstate_latency_us = 129.0,
338 .sr_exit_time_us = 11.5,338 .sr_exit_time_us = 11.5,
339 .sr_enter_plus_exit_time_us = 14.5,339 .sr_enter_plus_exit_time_us = 14.5,
340 .valid = true,340 .valid = true,
@@ -342,7 +342,7 @@ static struct wm_table lpddr5_wm_table = { · 1 unmodified line
342 {342 {
343 .wm_inst = WM_B,343 .wm_inst = WM_B,
344 .wm_type = WM_TYPE_PSTATE_CHG,344 .wm_type = WM_TYPE_PSTATE_CHG,
345 .pstate_latency_us = 11.65333,345 .pstate_latency_us = 129.0,
346 .sr_exit_time_us = 11.5,346 .sr_exit_time_us = 11.5,
347 .sr_enter_plus_exit_time_us = 14.5,347 .sr_enter_plus_exit_time_us = 14.5,
348 .valid = true,348 .valid = true,
@@ -350,7 +350,7 @@ static struct wm_table lpddr5_wm_table = { · 1 unmodified line
350 {350 {
351 .wm_inst = WM_C,351 .wm_inst = WM_C,
352 .wm_type = WM_TYPE_PSTATE_CHG,352 .wm_type = WM_TYPE_PSTATE_CHG,
353 .pstate_latency_us = 11.65333,353 .pstate_latency_us = 129.0,
354 .sr_exit_time_us = 11.5,354 .sr_exit_time_us = 11.5,
355 .sr_enter_plus_exit_time_us = 14.5,355 .sr_enter_plus_exit_time_us = 14.5,
356 .valid = true,356 .valid = true,
@@ -358,7 +358,7 @@ static struct wm_table lpddr5_wm_table = { · 1 unmodified line
358 {358 {
359 .wm_inst = WM_D,359 .wm_inst = WM_D,
360 .wm_type = WM_TYPE_PSTATE_CHG,360 .wm_type = WM_TYPE_PSTATE_CHG,
361 .pstate_latency_us = 11.65333,361 .pstate_latency_us = 129.0,
362 .sr_exit_time_us = 11.5,362 .sr_exit_time_us = 11.5,
363 .sr_enter_plus_exit_time_us = 14.5,363 .sr_enter_plus_exit_time_us = 14.5,
364 .valid = true,364 .valid = true,
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c+79−80
@@ -232,6 +232,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, · 231 unmodified lines
232 if (dc->work_arounds.skip_clock_update)232 if (dc->work_arounds.skip_clock_update)
233 return;233 return;
234 234
235 /* DTBCLK is fixed, so set a default if unspecified. */
236 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
237 new_clocks->ref_dtbclk_khz = 600000;
238
235 /*239 /*
236 * if it is safe to lower, but we are already in the lower state, we don't have to do anything240 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
237 * also if safe to lower is false, we just go in the higher state241 * also if safe to lower is false, we just go in the higher state
@@ -265,8 +269,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, · 27 unmodified lines
265 269
266 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {270 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
267 dcn35_smu_set_dtbclk(clk_mgr, true);271 dcn35_smu_set_dtbclk(clk_mgr, true);
268 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
269 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;272 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
273
274 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
275 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
270 }276 }
271 277
272 /* check that we're not already in D0 */278 /* check that we're not already in D0 */
@@ -314,17 +320,12 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, · 41 unmodified lines
314 update_dispclk = true;320 update_dispclk = true;
315 }321 }
316 322
317 if (!new_clocks->dtbclk_en) {
318 new_clocks->ref_dtbclk_khz = 600000;
319 }
320
321 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */323 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
322 if (!dc->debug.disable_dtb_ref_clk_switch &&324 if (!dc->debug.disable_dtb_ref_clk_switch &&
323 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {325 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
324 /* DCCG requires KHz precision for DTBCLK */326 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
325 dcn35_smu_set_dtbclk(clk_mgr, true);327 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
326 328 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
327 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
328 }329 }
329 330
330 if (dpp_clock_lowered) {331 if (dpp_clock_lowered) {
@@ -443,32 +444,32 @@ static struct wm_table ddr5_wm_table = { · 112 unmodified lines
443 .wm_inst = WM_A,444 .wm_inst = WM_A,
444 .wm_type = WM_TYPE_PSTATE_CHG,445 .wm_type = WM_TYPE_PSTATE_CHG,
445 .pstate_latency_us = 11.72,446 .pstate_latency_us = 11.72,
446 .sr_exit_time_us = 9,447 .sr_exit_time_us = 14.0,
447 .sr_enter_plus_exit_time_us = 11,448 .sr_enter_plus_exit_time_us = 16.0,
448 .valid = true,449 .valid = true,
449 },450 },
450 {451 {
451 .wm_inst = WM_B,452 .wm_inst = WM_B,
452 .wm_type = WM_TYPE_PSTATE_CHG,453 .wm_type = WM_TYPE_PSTATE_CHG,
453 .pstate_latency_us = 11.72,454 .pstate_latency_us = 11.72,
454 .sr_exit_time_us = 9,455 .sr_exit_time_us = 14.0,
455 .sr_enter_plus_exit_time_us = 11,456 .sr_enter_plus_exit_time_us = 16.0,
456 .valid = true,457 .valid = true,
457 },458 },
458 {459 {
459 .wm_inst = WM_C,460 .wm_inst = WM_C,
460 .wm_type = WM_TYPE_PSTATE_CHG,461 .wm_type = WM_TYPE_PSTATE_CHG,
461 .pstate_latency_us = 11.72,462 .pstate_latency_us = 11.72,
462 .sr_exit_time_us = 9,463 .sr_exit_time_us = 14.0,
463 .sr_enter_plus_exit_time_us = 11,464 .sr_enter_plus_exit_time_us = 16.0,
464 .valid = true,465 .valid = true,
465 },466 },
466 {467 {
467 .wm_inst = WM_D,468 .wm_inst = WM_D,
468 .wm_type = WM_TYPE_PSTATE_CHG,469 .wm_type = WM_TYPE_PSTATE_CHG,
469 .pstate_latency_us = 11.72,470 .pstate_latency_us = 11.72,
470 .sr_exit_time_us = 9,471 .sr_exit_time_us = 14.0,
471 .sr_enter_plus_exit_time_us = 11,472 .sr_enter_plus_exit_time_us = 16.0,
472 .valid = true,473 .valid = true,
473 },474 },
474 }475 }
@@ -480,32 +481,32 @@ static struct wm_table lpddr5_wm_table = { · 5 unmodified lines
480 .wm_inst = WM_A,481 .wm_inst = WM_A,
481 .wm_type = WM_TYPE_PSTATE_CHG,482 .wm_type = WM_TYPE_PSTATE_CHG,
482 .pstate_latency_us = 11.65333,483 .pstate_latency_us = 11.65333,
483 .sr_exit_time_us = 11.5,484 .sr_exit_time_us = 14.0,
484 .sr_enter_plus_exit_time_us = 14.5,485 .sr_enter_plus_exit_time_us = 16.0,
485 .valid = true,486 .valid = true,
486 },487 },
487 {488 {
488 .wm_inst = WM_B,489 .wm_inst = WM_B,
489 .wm_type = WM_TYPE_PSTATE_CHG,490 .wm_type = WM_TYPE_PSTATE_CHG,
490 .pstate_latency_us = 11.65333,491 .pstate_latency_us = 11.65333,
491 .sr_exit_time_us = 11.5,492 .sr_exit_time_us = 14.0,
492 .sr_enter_plus_exit_time_us = 14.5,493 .sr_enter_plus_exit_time_us = 16.0,
493 .valid = true,494 .valid = true,
494 },495 },
495 {496 {
496 .wm_inst = WM_C,497 .wm_inst = WM_C,
497 .wm_type = WM_TYPE_PSTATE_CHG,498 .wm_type = WM_TYPE_PSTATE_CHG,
498 .pstate_latency_us = 11.65333,499 .pstate_latency_us = 11.65333,
499 .sr_exit_time_us = 11.5,500 .sr_exit_time_us = 14.0,
500 .sr_enter_plus_exit_time_us = 14.5,501 .sr_enter_plus_exit_time_us = 16.0,
501 .valid = true,502 .valid = true,
502 },503 },
503 {504 {
504 .wm_inst = WM_D,505 .wm_inst = WM_D,
505 .wm_type = WM_TYPE_PSTATE_CHG,506 .wm_type = WM_TYPE_PSTATE_CHG,
506 .pstate_latency_us = 11.65333,507 .pstate_latency_us = 11.65333,
507 .sr_exit_time_us = 11.5,508 .sr_exit_time_us = 14.0,
508 .sr_enter_plus_exit_time_us = 14.5,509 .sr_enter_plus_exit_time_us = 16.0,
509 .valid = true,510 .valid = true,
510 },511 },
511 }512 }
@@ -515,11 +516,6 @@ static DpmClocks_t_dcn35 dummy_clocks; · 3 unmodified lines
515 516
516static struct dcn35_watermarks dummy_wms = { 0 };517static struct dcn35_watermarks dummy_wms = { 0 };
517 518
518static struct dcn35_ss_info_table ss_info_table = {
519 .ss_divider = 1000,
520 .ss_percentage = {0, 0, 375, 375, 375}
521};
522
523static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)519static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
524{520{
525 int i, num_valid_sets;521 int i, num_valid_sets;
@@ -653,27 +649,47 @@ static unsigned int convert_wck_ratio(uint8_t wck_ratio) · 127 unmodified lines
653 return 1;649 return 1;
654}650}
655 651
652static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
653{
654 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
655}
656
656static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,657static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
657 struct integrated_info *bios_info,658 struct integrated_info *bios_info,
658 DpmClocks_t_dcn35 *clock_table)659 DpmClocks_t_dcn35 *clock_table)
659{660{
660 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;661 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
661 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];662 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
662 uint32_t max_pstate = 0, max_uclk = 0, max_fclk = 0;663 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
663 uint32_t min_pstate = 0, max_dispclk = 0, max_dppclk = 0;664 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
664 int i;665 int i;
665 666
667 /* Determine min/max p-state values. */
666 for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {668 for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
667 if (is_valid_clock_value(clock_table->MemPstateTable[i].UClk) &&669 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
668 clock_table->MemPstateTable[i].UClk > max_uclk) {670
669 max_uclk = clock_table->MemPstateTable[i].UClk;671 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
672 max_dram_speed_mts = dram_speed_mts;
670 max_pstate = i;673 max_pstate = i;
671 }674 }
672 }675 }
673 676
674 /* We expect the table to contain at least one valid Uclk entry. */677 min_dram_speed_mts = max_dram_speed_mts;
675 ASSERT(is_valid_clock_value(max_uclk));678 min_pstate = max_pstate;
679
680 for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
681 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
682
683 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
684 min_dram_speed_mts = dram_speed_mts;
685 min_pstate = i;
686 }
687 }
676 688
689 /* We expect the table to contain at least one valid P-state entry. */
690 ASSERT(clock_table->NumMemPstatesEnabled &&
691 is_valid_clock_value(max_dram_speed_mts) &&
692 is_valid_clock_value(min_dram_speed_mts));
677 693
678 /* dispclk and dppclk can be max at any voltage, same number of levels for both */694 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
679 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&695 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
@@ -683,47 +699,46 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk · 3 unmodified lines
683 max_dppclk = find_max_clk_value(clock_table->DppClocks,699 max_dppclk = find_max_clk_value(clock_table->DppClocks,
684 clock_table->NumDispClkLevelsEnabled);700 clock_table->NumDispClkLevelsEnabled);
685 } else {701 } else {
702 /* Invalid number of entries in the table from PMFW. */
686 ASSERT(0);703 ASSERT(0);
687 }704 }
688 if (clock_table->NumFclkLevelsEnabled <= NUM_FCLK_DPM_LEVELS)
689 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq,
690 clock_table->NumFclkLevelsEnabled);
691 705
692 for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {706 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
693 uint32_t min_uclk = clock_table->MemPstateTable[0].UClk;707 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
694 int j;
695 708
696 for (j = 1; j < clock_table->NumMemPstatesEnabled; j++) {709 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, clock_table->NumFclkLevelsEnabled);
697 if (is_valid_clock_value(clock_table->MemPstateTable[j].UClk) &&
698 clock_table->MemPstateTable[j].UClk < min_uclk &&
699 clock_table->MemPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
700 min_uclk = clock_table->MemPstateTable[j].UClk;
701 min_pstate = j;
702 }
703 }
704 710
711 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
712 int j;
713
714 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
705 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)715 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
706 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])716 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
707 break;717 break;
708 718
709 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;719 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
710 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;720 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
711 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;721 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
712 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;722
723 /* Now update clocks we do read */
713 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;724 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
714 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;725 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
715 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];726 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
716 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];727 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
717 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;728 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
718 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;729 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
719 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(730 bw_params->clk_table.entries[i].wck_ratio =
720 clock_table->MemPstateTable[min_pstate].WckRatio);731 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
721 }732
733 /* Dcfclk and Fclk are tied, but at a different ratio */
734 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
735 }
722 736
723 /* Make sure to include at least one entry at highest pstate */737 /* Make sure to include at least one entry at highest pstate */
724 if (max_pstate != min_pstate || i == 0) {738 if (max_pstate != min_pstate || i == 0) {
725 if (i > MAX_NUM_DPM_LVL - 1)739 if (i > MAX_NUM_DPM_LVL - 1)
726 i = MAX_NUM_DPM_LVL - 1;740 i = MAX_NUM_DPM_LVL - 1;
741
727 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;742 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
728 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;743 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
729 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;744 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
@@ -739,6 +754,7 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk · 9 unmodified lines
739 }754 }
740 bw_params->clk_table.num_entries = i--;755 bw_params->clk_table.num_entries = i--;
741 756
757 /* Make sure all highest clocks are included*/
742 bw_params->clk_table.entries[i].socclk_mhz =758 bw_params->clk_table.entries[i].socclk_mhz =
743 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);759 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
744 bw_params->clk_table.entries[i].dispclk_mhz =760 bw_params->clk_table.entries[i].dispclk_mhz =
@@ -757,6 +773,11 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk · 12 unmodified lines
757 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;773 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
758 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;774 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
759 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;775 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
776
777 /*
778 * Set any 0 clocks to max default setting. Not an issue for
779 * power since we aren't doing switching in such case anyway
780 */
760 for (i = 0; i < bw_params->clk_table.num_entries; i++) {781 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
761 if (!bw_params->clk_table.entries[i].fclk_mhz) {782 if (!bw_params->clk_table.entries[i].fclk_mhz) {
762 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;783 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
@@ -965,21 +986,6 @@ struct clk_mgr_funcs dcn35_fpga_funcs = { · 202 unmodified lines
965 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,986 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
966};987};
967 988
968static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
969{
970 uint32_t clock_source;
971 struct dc_context *ctx = clk_mgr->base.ctx;
972
973 REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
974
975 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
976
977 if (clk_mgr->dprefclk_ss_percentage != 0) {
978 clk_mgr->ss_on_dprefclk = true;
979 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
980 }
981}
982
983void dcn35_clk_mgr_construct(989void dcn35_clk_mgr_construct(
984 struct dc_context *ctx,990 struct dc_context *ctx,
985 struct clk_mgr_dcn35 *clk_mgr,991 struct clk_mgr_dcn35 *clk_mgr,
@@ -1043,17 +1049,11 @@ void dcn35_clk_mgr_construct( · 57 unmodified lines
1043 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);1049 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
1044 1050
1045 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);1051 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1046 clk_mgr->base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&clk_mgr->base);1052 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1047 1053
1048 if (!clk_mgr->base.base.clks.ref_dtbclk_khz)
1049 dcn35_smu_set_dtbclk(&clk_mgr->base, true);
1050
1051 clk_mgr->base.base.clks.dtbclk_en = true;
1052 dce_clock_read_ss_info(&clk_mgr->base);1054 dce_clock_read_ss_info(&clk_mgr->base);
1053 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/1055 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1054 1056
1055 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1056
1057 clk_mgr->base.base.bw_params = &dcn35_bw_params;1057 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1058 1058
1059 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {1059 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
@@ -1129,7 +1129,6 @@ void dcn35_clk_mgr_construct( · 69 unmodified lines
1129 ctx->dc->debug.disable_dpp_power_gate = false;1129 ctx->dc->debug.disable_dpp_power_gate = false;
1130 ctx->dc->debug.disable_hubp_power_gate = false;1130 ctx->dc->debug.disable_hubp_power_gate = false;
1131 ctx->dc->debug.disable_dsc_power_gate = false;1131 ctx->dc->debug.disable_dsc_power_gate = false;
1132 ctx->dc->debug.disable_hpo_power_gate = false;
1133 } else {1132 } else {
1134 /*let's reset the config control flag*/1133 /*let's reset the config control flag*/
1135 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/1134 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
drivers/gpu/drm/amd/display/dc/dc.h+1−1
@@ -874,6 +874,7 @@ struct dc_debug_options { · 873 unmodified lines
874 unsigned int seamless_boot_odm_combine;874 unsigned int seamless_boot_odm_combine;
875 unsigned int force_odm_combine_4to1; //bit vector based on otg inst875 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
876 int minimum_z8_residency_time;876 int minimum_z8_residency_time;
877 int minimum_z10_residency_time;
877 bool disable_z9_mpc;878 bool disable_z9_mpc;
878 unsigned int force_fclk_khz;879 unsigned int force_fclk_khz;
879 bool enable_tri_buf;880 bool enable_tri_buf;
@@ -1608,7 +1609,6 @@ struct dc_link { · 728 unmodified lines
1608 enum edp_revision edp_revision;1609 enum edp_revision edp_revision;
1609 union dpcd_sink_ext_caps dpcd_sink_ext_caps;1610 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1610 1611
1611 struct backlight_settings backlight_settings;
1612 struct psr_settings psr_settings;1612 struct psr_settings psr_settings;
1613 1613
1614 struct replay_settings replay_settings;1614 struct replay_settings replay_settings;
drivers/gpu/drm/amd/display/dc/dc_types.h+0−4
@@ -991,10 +991,6 @@ struct link_mst_stream_allocation_table { · 990 unmodified lines
991 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];991 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
992};992};
993 993
994struct backlight_settings {
995 uint32_t backlight_millinits;
996};
997
998/* PSR feature flags */994/* PSR feature flags */
999struct psr_settings {995struct psr_settings {
1000 bool psr_feature_enabled; // PSR is supported by sink996 bool psr_feature_enabled; // PSR is supported by sink
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c+1−1
@@ -871,7 +871,7 @@ static const struct dc_plane_cap plane_cap = { · 870 unmodified lines
871static const struct dc_debug_options debug_defaults_drv = {871static const struct dc_debug_options debug_defaults_drv = {
872 .disable_z10 = false,872 .disable_z10 = false,
873 .enable_z9_disable_interface = true,873 .enable_z9_disable_interface = true,
874 .minimum_z8_residency_time = 2000,874 .minimum_z8_residency_time = 2100,
875 .psr_skip_crtc_disable = true,875 .psr_skip_crtc_disable = true,
876 .replay_skip_crtc_disabled = true,876 .replay_skip_crtc_disabled = true,
877 .disable_dmcu = true,877 .disable_dmcu = true,
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c+10−0
@@ -261,6 +261,7 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 260 unmodified lines
261 uint32_t power_gate = power_on ? 0 : 1;261 uint32_t power_gate = power_on ? 0 : 1;
262 uint32_t pwr_status = power_on ? 0 : 2;262 uint32_t pwr_status = power_on ? 0 : 2;
263 uint32_t org_ip_request_cntl;263 uint32_t org_ip_request_cntl;
264 uint32_t power_forceon;
264 bool block_enabled;265 bool block_enabled;
265 266
266 if (pg_cntl->ctx->dc->debug.ignore_pg ||267 if (pg_cntl->ctx->dc->debug.ignore_pg ||
@@ -277,6 +278,10 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 10 unmodified lines
277 return;278 return;
278 }279 }
279 280
281 REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon);
282 if (power_forceon)
283 return;
284
280 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);285 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
281 if (org_ip_request_cntl == 0)286 if (org_ip_request_cntl == 0)
282 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);287 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
@@ -304,6 +309,7 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 21 unmodified lines
304 uint32_t power_gate = power_on ? 0 : 1;309 uint32_t power_gate = power_on ? 0 : 1;
305 uint32_t pwr_status = power_on ? 0 : 2;310 uint32_t pwr_status = power_on ? 0 : 2;
306 uint32_t org_ip_request_cntl;311 uint32_t org_ip_request_cntl;
312 uint32_t power_forceon;
307 bool block_enabled;313 bool block_enabled;
308 314
309 if (pg_cntl->ctx->dc->debug.ignore_pg ||315 if (pg_cntl->ctx->dc->debug.ignore_pg ||
@@ -319,6 +325,10 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) · 9 unmodified lines
319 return;325 return;
320 }326 }
321 327
328 REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon);
329 if (power_forceon)
330 return;
331
322 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);332 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
323 if (org_ip_request_cntl == 0)333 if (org_ip_request_cntl == 0)
324 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);334 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c+8−1
@@ -1712,6 +1712,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc, · 1711 unmodified lines
1712 1712
1713 out = dml2_validate(dc, context, fast_validate);1713 out = dml2_validate(dc, context, fast_validate);
1714 1714
1715 if (fast_validate)
1716 return out;
1717
1718 DC_FP_START();
1719 dcn35_decide_zstate_support(dc, context);
1720 DC_FP_END();
1721
1715 return out;1722 return out;
1716}1723}
1717 1724
@@ -1857,7 +1864,7 @@ static bool dcn35_resource_construct( · 139 unmodified lines
1857 1864
1858 /* Use pipe context based otg sync logic */1865 /* Use pipe context based otg sync logic */
1859 dc->config.use_pipe_ctx_sync_logic = true;1866 dc->config.use_pipe_ctx_sync_logic = true;
1860 dc->config.use_default_clock_table = false;1867
1861 /* read VBIOS LTTPR caps */1868 /* read VBIOS LTTPR caps */
1862 {1869 {
1863 if (ctx->dc_bios->funcs->get_lttpr_caps) {1870 if (ctx->dc_bios->funcs->get_lttpr_caps) {
drivers/gpu/drm/amd/display/dc/dml/dc_features.h+1−1
@@ -36,7 +36,7 @@ · 35 unmodified lines
36 * Define the maximum amount of states supported by the ASIC. Every ASIC has a36 * Define the maximum amount of states supported by the ASIC. Every ASIC has a
37 * specific number of states; this macro defines the maximum number of states.37 * specific number of states; this macro defines the maximum number of states.
38 */38 */
39#define DC__VOLTAGE_STATES 2039#define DC__VOLTAGE_STATES 40
40#define DC__NUM_DPP__4 140#define DC__NUM_DPP__4 1
41#define DC__NUM_DPP__0_PRESENT 141#define DC__NUM_DPP__0_PRESENT 1
42#define DC__NUM_DPP__1_PRESENT 142#define DC__NUM_DPP__1_PRESENT 1
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c+1−14
@@ -950,10 +950,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc · 949 unmodified lines
950{950{
951 int plane_count;951 int plane_count;
952 int i;952 int i;
953 unsigned int min_dst_y_next_start_us;
954 953
955 plane_count = 0;954 plane_count = 0;
956 min_dst_y_next_start_us = 0;
957 for (i = 0; i < dc->res_pool->pipe_count; i++) {955 for (i = 0; i < dc->res_pool->pipe_count; i++) {
958 if (context->res_ctx.pipe_ctx[i].plane_state)956 if (context->res_ctx.pipe_ctx[i].plane_state)
959 plane_count++;957 plane_count++;
@@ -975,26 +973,15 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc · 15 unmodified lines
975 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {973 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
976 struct dc_link *link = context->streams[0]->sink->link;974 struct dc_link *link = context->streams[0]->sink->link;
977 struct dc_stream_status *stream_status = &context->stream_status[0];975 struct dc_stream_status *stream_status = &context->stream_status[0];
978 struct dc_stream_state *current_stream = context->streams[0];
979 int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;976 int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
980 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;977 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
981 bool is_pwrseq0 = link->link_index == 0;978 bool is_pwrseq0 = link->link_index == 0;
982 bool isFreesyncVideo;
983
984 isFreesyncVideo = current_stream->adjust.v_total_min == current_stream->adjust.v_total_max;
985 isFreesyncVideo = isFreesyncVideo && current_stream->timing.v_total < current_stream->adjust.v_total_min;
986 for (i = 0; i < dc->res_pool->pipe_count; i++) {
987 if (context->res_ctx.pipe_ctx[i].stream == current_stream && isFreesyncVideo) {
988 min_dst_y_next_start_us = context->res_ctx.pipe_ctx[i].dlg_regs.min_dst_y_next_start_us;
989 break;
990 }
991 }
992 979
993 /* Don't support multi-plane configurations */980 /* Don't support multi-plane configurations */
994 if (stream_status->plane_count > 1)981 if (stream_status->plane_count > 1)
995 return DCN_ZSTATE_SUPPORT_DISALLOW;982 return DCN_ZSTATE_SUPPORT_DISALLOW;
996 983
997 if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || min_dst_y_next_start_us > 5000))984 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
998 return DCN_ZSTATE_SUPPORT_ALLOW;985 return DCN_ZSTATE_SUPPORT_ALLOW;
999 else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)986 else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)
1000 return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;987 return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+14−9
@@ -1192,13 +1192,16 @@ static bool update_pipe_slice_table_with_split_flags( · 1191 unmodified lines
1192 */1192 */
1193 struct pipe_ctx *pipe;1193 struct pipe_ctx *pipe;
1194 bool odm;1194 bool odm;
1195 int i;1195 int dc_pipe_idx, dml_pipe_idx = 0;
1196 bool updated = false;1196 bool updated = false;
1197 1197
1198 for (i = 0; i < dc->res_pool->pipe_count; i++) {1198 for (dc_pipe_idx = 0;
1199 pipe = &context->res_ctx.pipe_ctx[i];1199 dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {
1200 pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1201 if (resource_is_pipe_type(pipe, FREE_PIPE))
1202 continue;
1200 1203
1201 if (merge[i]) {1204 if (merge[dc_pipe_idx]) {
1202 if (resource_is_pipe_type(pipe, OPP_HEAD))1205 if (resource_is_pipe_type(pipe, OPP_HEAD))
1203 /* merging OPP head means reducing ODM slice1206 /* merging OPP head means reducing ODM slice
1204 * count by 11207 * count by 1
@@ -1213,17 +1216,18 @@ static bool update_pipe_slice_table_with_split_flags( · 8 unmodified lines
1213 updated = true;1216 updated = true;
1214 }1217 }
1215 1218
1216 if (split[i]) {1219 if (split[dc_pipe_idx]) {
1217 odm = vba->ODMCombineEnabled[vba->pipe_plane[i]] !=1220 odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] !=
1218 dm_odm_combine_mode_disabled;1221 dm_odm_combine_mode_disabled;
1219 if (odm && resource_is_pipe_type(pipe, OPP_HEAD))1222 if (odm && resource_is_pipe_type(pipe, OPP_HEAD))
1220 update_slice_table_for_stream(1223 update_slice_table_for_stream(
1221 table, pipe->stream, split[i] - 1);1224 table, pipe->stream, split[dc_pipe_idx] - 1);
1222 else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))1225 else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))
1223 update_slice_table_for_plane(table, pipe,1226 update_slice_table_for_plane(table, pipe,
1224 pipe->plane_state, split[i] - 1);1227 pipe->plane_state, split[dc_pipe_idx] - 1);
1225 updated = true;1228 updated = true;
1226 }1229 }
1230 dml_pipe_idx++;
1227 }1231 }
1228 return updated;1232 return updated;
1229}1233}
@@ -2231,6 +2235,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, · 1001 unmodified lines
2231 int i, pipe_idx, vlevel_temp = 0;2235 int i, pipe_idx, vlevel_temp = 0;
2232 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;2236 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2233 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];2237 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2238 double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;
2234 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;2239 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
2235 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=2240 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2236 dm_dram_clock_change_unsupported;2241 dm_dram_clock_change_unsupported;
@@ -2418,7 +2423,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, · 181 unmodified lines
2418 }2423 }
2419 2424
2420 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {2425 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2421 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;2426 min_dram_speed_mts = dram_speed_from_validation;
2422 min_dram_speed_mts_margin = 160;2427 min_dram_speed_mts_margin = 160;
2423 2428
2424 context->bw_ctx.dml.soc.dram_clock_change_latency_us =2429 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c+80−4
@@ -164,10 +164,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { · 163 unmodified lines
164 },164 },
165 },165 },
166 .num_states = 5,166 .num_states = 5,
167 .sr_exit_time_us = 9.0,167 .sr_exit_time_us = 14.0,
168 .sr_enter_plus_exit_time_us = 11.0,168 .sr_enter_plus_exit_time_us = 16.0,
169 .sr_exit_z8_time_us = 50.0, /*changed from 442.0*/169 .sr_exit_z8_time_us = 525.0,
170 .sr_enter_plus_exit_z8_time_us = 50.0,/*changed from 560.0*/170 .sr_enter_plus_exit_z8_time_us = 715.0,
171 .fclk_change_latency_us = 20.0,171 .fclk_change_latency_us = 20.0,
172 .usr_retraining_latency_us = 2,172 .usr_retraining_latency_us = 2,
173 .writeback_latency_us = 12.0,173 .writeback_latency_us = 12.0,
@@ -329,6 +329,48 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, · 155 unmodified lines
329 /*temp till dml2 fully work without dml1*/329 /*temp till dml2 fully work without dml1*/
330 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,330 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,
331 DML_PROJECT_DCN31);331 DML_PROJECT_DCN31);
332
333 /*copy to dml2, before dml2_create*/
334 if (clk_table->num_entries > 2) {
335
336 for (i = 0; i < clk_table->num_entries; i++) {
337 dc->dml2_options.bbox_overrides.clks_table.num_states =
338 clk_table->num_entries;
339 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
340 clock_limits[i].dcfclk_mhz;
341 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
342 clock_limits[i].fabricclk_mhz;
343 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
344 clock_limits[i].dispclk_mhz;
345 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
346 clock_limits[i].dppclk_mhz;
347 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
348 clock_limits[i].socclk_mhz;
349 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
350 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
351 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
352 clk_table->num_entries;
353 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
354 clk_table->num_entries;
355 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
356 clk_table->num_entries;
357 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
358 clk_table->num_entries;
359 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
360 clk_table->num_entries;
361 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
362 clk_table->num_entries;
363 }
364 }
365
366 /* Update latency values */
367 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;
368
369 dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;
370 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;
371
372 dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;
373 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;
332}374}
333 375
334static bool is_dual_plane(enum surface_pixel_format format)376static bool is_dual_plane(enum surface_pixel_format format)
@@ -507,3 +549,37 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, · 172 unmodified lines
507 549
508 return pipe_cnt;550 return pipe_cnt;
509}551}
552
553void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
554{
555 enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;
556 unsigned int i, plane_count = 0;
557
558 for (i = 0; i < dc->res_pool->pipe_count; i++) {
559 if (context->res_ctx.pipe_ctx[i].plane_state)
560 plane_count++;
561 }
562
563 if (plane_count == 0) {
564 support = DCN_ZSTATE_SUPPORT_ALLOW;
565 } else if (plane_count == 1 && context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
566 struct dc_link *link = context->streams[0]->sink->link;
567 bool is_pwrseq0 = link && link->link_index == 0;
568 bool is_psr1 = link && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr;
569 int minmum_z8_residency =
570 dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
571 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
572 int minmum_z10_residency =
573 dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;
574 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;
575
576 if (is_pwrseq0 && allow_z10)
577 support = DCN_ZSTATE_SUPPORT_ALLOW;
578 else if (is_pwrseq0 && is_psr1)
579 support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
580 else if (allow_z8)
581 support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
582 }
583
584 context->bw_ctx.bw.dcn.clk.zstate_support = support;
585}
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h+2−0
@@ -39,4 +39,6 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, · 38 unmodified lines
39 display_e2e_pipe_params_st *pipes,39 display_e2e_pipe_params_st *pipes,
40 bool fast_validate);40 bool fast_validate);
41 41
42void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);
43
42#endif44#endif
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c+8−8
@@ -6329,7 +6329,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib) · 6328 unmodified lines
6329 mode_lib->ms.NoOfDPPThisState,6329 mode_lib->ms.NoOfDPPThisState,
6330 mode_lib->ms.dpte_group_bytes,6330 mode_lib->ms.dpte_group_bytes,
6331 s->HostVMInefficiencyFactor,6331 s->HostVMInefficiencyFactor,
6332 mode_lib->ms.soc.hostvm_min_page_size_kbytes,6332 mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
6333 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);6333 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);
6334 6334
6335 s->NextMaxVStartup = s->MaxVStartupAllPlanes[j];6335 s->NextMaxVStartup = s->MaxVStartupAllPlanes[j];
@@ -6542,7 +6542,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib) · 206 unmodified lines
6542 mode_lib->ms.cache_display_cfg.plane.HostVMEnable,6542 mode_lib->ms.cache_display_cfg.plane.HostVMEnable,
6543 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,6543 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,
6544 mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,6544 mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,
6545 mode_lib->ms.soc.hostvm_min_page_size_kbytes,6545 mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
6546 mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k],6546 mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k],
6547 mode_lib->ms.MetaRowBytes[j][k],6547 mode_lib->ms.MetaRowBytes[j][k],
6548 mode_lib->ms.DPTEBytesPerRow[j][k],6548 mode_lib->ms.DPTEBytesPerRow[j][k],
@@ -7687,7 +7687,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib) · 1138 unmodified lines
7687 CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;7687 CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
7688 CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;7688 CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;
7689 CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;7689 CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;
7690 CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;7690 CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
7691 CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;7691 CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;
7692 CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;7692 CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;
7693 CalculateVMRowAndSwath_params->PTEBufferSizeNotExceeded = mode_lib->ms.PTEBufferSizeNotExceededPerState;7693 CalculateVMRowAndSwath_params->PTEBufferSizeNotExceeded = mode_lib->ms.PTEBufferSizeNotExceededPerState;
@@ -7957,7 +7957,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib) · 263 unmodified lines
7957 UseMinimumDCFCLK_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;7957 UseMinimumDCFCLK_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;
7958 UseMinimumDCFCLK_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;7958 UseMinimumDCFCLK_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;
7959 UseMinimumDCFCLK_params->NumberOfActiveSurfaces = mode_lib->ms.num_active_planes;7959 UseMinimumDCFCLK_params->NumberOfActiveSurfaces = mode_lib->ms.num_active_planes;
7960 UseMinimumDCFCLK_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;7960 UseMinimumDCFCLK_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
7961 UseMinimumDCFCLK_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;7961 UseMinimumDCFCLK_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
7962 UseMinimumDCFCLK_params->DynamicMetadataVMEnabled = mode_lib->ms.ip.dynamic_metadata_vm_enabled;7962 UseMinimumDCFCLK_params->DynamicMetadataVMEnabled = mode_lib->ms.ip.dynamic_metadata_vm_enabled;
7963 UseMinimumDCFCLK_params->ImmediateFlipRequirement = s->ImmediateFlipRequiredFinal;7963 UseMinimumDCFCLK_params->ImmediateFlipRequirement = s->ImmediateFlipRequiredFinal;
@@ -8699,7 +8699,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 735 unmodified lines
8699 CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;8699 CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
8700 CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;8700 CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;
8701 CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;8701 CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;
8702 CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;8702 CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
8703 CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;8703 CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;
8704 CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;8704 CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;
8705 CalculateVMRowAndSwath_params->PTEBufferSizeNotExceeded = s->dummy_boolean_array[0];8705 CalculateVMRowAndSwath_params->PTEBufferSizeNotExceeded = s->dummy_boolean_array[0];
@@ -8805,7 +8805,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 99 unmodified lines
8805 mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,8805 mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,
8806 locals->dpte_group_bytes,8806 locals->dpte_group_bytes,
8807 s->HostVMInefficiencyFactor,8807 s->HostVMInefficiencyFactor,
8808 mode_lib->ms.soc.hostvm_min_page_size_kbytes,8808 mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
8809 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);8809 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);
8810 8810
8811 locals->TCalc = 24.0 / locals->DCFCLKDeepSleep;8811 locals->TCalc = 24.0 / locals->DCFCLKDeepSleep;
@@ -8995,7 +8995,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 183 unmodified lines
8995 CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;8995 CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;
8996 CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;8996 CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;
8997 CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;8997 CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;
8998 CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes;8998 CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
8999 CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];8999 CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];
9000 CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ms.ip.dynamic_metadata_vm_enabled;9000 CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ms.ip.dynamic_metadata_vm_enabled;
9001 CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];9001 CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];
@@ -9240,7 +9240,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc · 238 unmodified lines
9240 mode_lib->ms.cache_display_cfg.plane.HostVMEnable,9240 mode_lib->ms.cache_display_cfg.plane.HostVMEnable,
9241 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,9241 mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,
9242 mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,9242 mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,
9243 mode_lib->ms.soc.hostvm_min_page_size_kbytes,9243 mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
9244 locals->PDEAndMetaPTEBytesFrame[k],9244 locals->PDEAndMetaPTEBytesFrame[k],
9245 locals->MetaRowByte[k],9245 locals->MetaRowByte[k],
9246 locals->PixelPTEBytesPerRow[k],9246 locals->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c+40−20
@@ -341,25 +341,42 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, · 340 unmodified lines
341 break;341 break;
342 }342 }
343 343
344 /* Override from passed values, mainly for debugging purposes, if available */344 /* Override from passed values, if available */
345 if (dml2->config.bbox_overrides.sr_exit_latency_us) {345 for (i = 0; i < p->in_states->num_states; i++) {
346 p->in_states->state_array[0].sr_exit_time_us = dml2->config.bbox_overrides.sr_exit_latency_us;346 if (dml2->config.bbox_overrides.sr_exit_latency_us) {
347 }347 p->in_states->state_array[i].sr_exit_time_us =
348 dml2->config.bbox_overrides.sr_exit_latency_us;
349 }
348 350
349 if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {351 if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
350 p->in_states->state_array[0].sr_enter_plus_exit_time_us = dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;352 p->in_states->state_array[i].sr_enter_plus_exit_time_us =
351 }353 dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
354 }
352 355
353 if (dml2->config.bbox_overrides.urgent_latency_us) {356 if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {
354 p->in_states->state_array[0].urgent_latency_pixel_data_only_us = dml2->config.bbox_overrides.urgent_latency_us;357 p->in_states->state_array[i].sr_exit_z8_time_us =
355 }358 dml2->config.bbox_overrides.sr_exit_z8_time_us;
359 }
356 360
357 if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {361 if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {
358 p->in_states->state_array[0].dram_clock_change_latency_us = dml2->config.bbox_overrides.dram_clock_change_latency_us;362 p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =
359 }363 dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;
364 }
365
366 if (dml2->config.bbox_overrides.urgent_latency_us) {
367 p->in_states->state_array[i].urgent_latency_pixel_data_only_us =
368 dml2->config.bbox_overrides.urgent_latency_us;
369 }
360 370
361 if (dml2->config.bbox_overrides.fclk_change_latency_us) {371 if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
362 p->in_states->state_array[0].fclk_change_latency_us = dml2->config.bbox_overrides.fclk_change_latency_us;372 p->in_states->state_array[i].dram_clock_change_latency_us =
373 dml2->config.bbox_overrides.dram_clock_change_latency_us;
374 }
375
376 if (dml2->config.bbox_overrides.fclk_change_latency_us) {
377 p->in_states->state_array[i].fclk_change_latency_us =
378 dml2->config.bbox_overrides.fclk_change_latency_us;
379 }
363 }380 }
364 381
365 /* DCFCLK stas values are project specific */382 /* DCFCLK stas values are project specific */
@@ -498,8 +515,8 @@ void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st · 132 unmodified lines
498 out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;515 out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;
499 out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;516 out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;
500 out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;517 out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;
501 out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes * 1024;518 out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024;
502 out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes * 1024;519 out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024;
503 out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;520 out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;
504 out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;521 out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;
505 out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;522 out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;
@@ -1040,9 +1057,12 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat · 534 unmodified lines
1040 }1057 }
1041 1058
1042 //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file1059 //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
1043 dml_dispcfg->plane.GPUVMEnable = true;1060 dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;
1044 dml_dispcfg->plane.GPUVMMaxPageTableLevels = 4;1061 dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;
1045 dml_dispcfg->plane.HostVMEnable = false;1062 dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;
1063 dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;
1064 if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
1065 dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;
1046 1066
1047 dml2_populate_pipe_to_plane_index_mapping(dml2, context);1067 dml2_populate_pipe_to_plane_index_mapping(dml2, context);
1048 1068
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h+2−0
@@ -139,6 +139,8 @@ struct dml2_soc_bbox_overrides { · 138 unmodified lines
139 double urgent_latency_us;139 double urgent_latency_us;
140 double sr_exit_latency_us;140 double sr_exit_latency_us;
141 double sr_enter_plus_exit_latency_us;141 double sr_enter_plus_exit_latency_us;
142 double sr_exit_z8_time_us;
143 double sr_enter_plus_exit_z8_time_us;
142 double dram_clock_change_latency_us;144 double dram_clock_change_latency_us;
143 double fclk_change_latency_us;145 double fclk_change_latency_us;
144 unsigned int dram_num_chan;146 unsigned int dram_num_chan;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c+2−4
@@ -487,8 +487,7 @@ bool dcn32_set_mcm_luts( · 486 unmodified lines
487 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)487 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
488 lut_params = &plane_state->blend_tf->pwl;488 lut_params = &plane_state->blend_tf->pwl;
489 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {489 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
490 cm_helper_translate_curve_to_hw_format(plane_state->ctx,490 cm3_helper_translate_curve_to_hw_format(plane_state->blend_tf,
491 plane_state->blend_tf,
492 &dpp_base->regamma_params, false);491 &dpp_base->regamma_params, false);
493 lut_params = &dpp_base->regamma_params;492 lut_params = &dpp_base->regamma_params;
494 }493 }
@@ -503,8 +502,7 @@ bool dcn32_set_mcm_luts( · 8 unmodified lines
503 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {502 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
504 // TODO: dpp_base replace503 // TODO: dpp_base replace
505 ASSERT(false);504 ASSERT(false);
506 cm_helper_translate_curve_to_hw_format(plane_state->ctx,505 cm3_helper_translate_curve_to_hw_format(plane_state->in_shaper_func,
507 plane_state->in_shaper_func,
508 &dpp_base->shaper_params, true);506 &dpp_base->shaper_params, true);
509 lut_params = &dpp_base->shaper_params;507 lut_params = &dpp_base->shaper_params;
510 }508 }
drivers/gpu/drm/amd/display/dc/link/link_detection.c+1−1
@@ -879,7 +879,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, · 878 unmodified lines
879 (link->dpcd_sink_ext_caps.bits.oled == 1)) {879 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
880 dpcd_set_source_specific_data(link);880 dpcd_set_source_specific_data(link);
881 msleep(post_oui_delay);881 msleep(post_oui_delay);
882 set_cached_brightness_aux(link);882 set_default_brightness_aux(link);
883 }883 }
884 884
885 return true;885 return true;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c+1−2
@@ -2142,8 +2142,7 @@ static enum dc_status enable_link_dp(struct dc_state *state, · 2141 unmodified lines
2142 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||2142 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2143 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||2143 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2144 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {2144 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2145 set_cached_brightness_aux(link);2145 set_default_brightness_aux(link);
2146
2147 if (link->dpcd_sink_ext_caps.bits.oled == 1)2146 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2148 msleep(bl_oled_enable_delay);2147 msleep(bl_oled_enable_delay);
2149 edp_backlight_enable_aux(link, true);2148 edp_backlight_enable_aux(link, true);
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c+3−3
@@ -115,7 +115,7 @@ static enum link_training_result perform_fixed_vs_pe_nontransparent_training_seq · 114 unmodified lines
115 lt_settings->cr_pattern_time = 16000;115 lt_settings->cr_pattern_time = 16000;
116 116
117 /* Fixed VS/PE specific: Toggle link rate */117 /* Fixed VS/PE specific: Toggle link rate */
118 apply_toggle_rate_wa = (link->vendor_specific_lttpr_link_rate_wa == target_rate);118 apply_toggle_rate_wa = ((link->vendor_specific_lttpr_link_rate_wa == target_rate) || (link->vendor_specific_lttpr_link_rate_wa == 0));
119 target_rate = get_dpcd_link_rate(&lt_settings->link_settings);119 target_rate = get_dpcd_link_rate(&lt_settings->link_settings);
120 toggle_rate = (target_rate == 0x6) ? 0xA : 0x6;120 toggle_rate = (target_rate == 0x6) ? 0xA : 0x6;
121 121
@@ -271,7 +271,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy( · 149 unmodified lines
271 /* Vendor specific: Toggle link rate */271 /* Vendor specific: Toggle link rate */
272 toggle_rate = (rate == 0x6) ? 0xA : 0x6;272 toggle_rate = (rate == 0x6) ? 0xA : 0x6;
273 273
274 if (link->vendor_specific_lttpr_link_rate_wa == rate) {274 if (link->vendor_specific_lttpr_link_rate_wa == rate || link->vendor_specific_lttpr_link_rate_wa == 0) {
275 core_link_write_dpcd(275 core_link_write_dpcd(
276 link,276 link,
277 DP_LINK_BW_SET,277 DP_LINK_BW_SET,
@@ -617,7 +617,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence( · 339 unmodified lines
617 /* Vendor specific: Toggle link rate */617 /* Vendor specific: Toggle link rate */
618 toggle_rate = (rate == 0x6) ? 0xA : 0x6;618 toggle_rate = (rate == 0x6) ? 0xA : 0x6;
619 619
620 if (link->vendor_specific_lttpr_link_rate_wa == rate) {620 if (link->vendor_specific_lttpr_link_rate_wa == rate || link->vendor_specific_lttpr_link_rate_wa == 0) {
621 core_link_write_dpcd(621 core_link_write_dpcd(
622 link,622 link,
623 DP_LINK_BW_SET,623 DP_LINK_BW_SET,
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c+3−13
@@ -170,7 +170,6 @@ bool edp_set_backlight_level_nits(struct dc_link *link, · 169 unmodified lines
170 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;170 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
171 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;171 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
172 172
173 link->backlight_settings.backlight_millinits = backlight_millinits;
174 173
175 if (!link->dpcd_caps.panel_luminance_control) {174 if (!link->dpcd_caps.panel_luminance_control) {
176 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,175 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
@@ -288,9 +287,9 @@ bool set_default_brightness_aux(struct dc_link *link) · 111 unmodified lines
288 if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {287 if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
289 if (!read_default_bl_aux(link, &default_backlight))288 if (!read_default_bl_aux(link, &default_backlight))
290 default_backlight = 150000;289 default_backlight = 150000;
291 // if < 1 nits or > 5000, it might be wrong readback290 // if > 5000, it might be wrong readback
292 if (default_backlight < 1000 || default_backlight > 5000000)291 if (default_backlight > 5000000)
293 default_backlight = 150000; //292 default_backlight = 150000;
294 293
295 return edp_set_backlight_level_nits(link, true,294 return edp_set_backlight_level_nits(link, true,
296 default_backlight, 0);295 default_backlight, 0);
@@ -298,15 +297,6 @@ bool set_default_brightness_aux(struct dc_link *link) · 1 unmodified line
298 return false;297 return false;
299}298}
300 299
301bool set_cached_brightness_aux(struct dc_link *link)
302{
303 if (link->backlight_settings.backlight_millinits)
304 return edp_set_backlight_level_nits(link, true,
305 link->backlight_settings.backlight_millinits, 0);
306 else
307 return set_default_brightness_aux(link);
308 return false;
309}
310bool edp_is_ilr_optimization_enabled(struct dc_link *link)300bool edp_is_ilr_optimization_enabled(struct dc_link *link)
311{301{
312 if (link->dpcd_caps.edp_supported_link_rates_count == 0 || !link->panel_config.ilr.optimize_edp_link_rate)302 if (link->dpcd_caps.edp_supported_link_rates_count == 0 || !link->panel_config.ilr.optimize_edp_link_rate)
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h+0−1
@@ -30,7 +30,6 @@ · 29 unmodified lines
30enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);30enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
31void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);31void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
32bool set_default_brightness_aux(struct dc_link *link);32bool set_default_brightness_aux(struct dc_link *link);
33bool set_cached_brightness_aux(struct dc_link *link);
34void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);33void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);
35int edp_get_backlight_level(const struct dc_link *link);34int edp_get_backlight_level(const struct dc_link *link);
36bool edp_get_backlight_level_nits(struct dc_link *link,35bool edp_get_backlight_level_nits(struct dc_link *link,
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c+1−0
@@ -1077,6 +1077,7 @@ enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t ti · 1076 unmodified lines
1077 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);1077 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
1078 if (ack)1078 if (ack)
1079 return DMUB_STATUS_OK;1079 return DMUB_STATUS_OK;
1080 udelay(1);
1080 }1081 }
1081 return DMUB_STATUS_TIMEOUT;1082 return DMUB_STATUS_TIMEOUT;
1082}1083}
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h+2−0
@@ -6369,6 +6369,8 @@ · 6368 unmodified lines
6369#define regTCP_INVALIDATE_BASE_IDX 16369#define regTCP_INVALIDATE_BASE_IDX 1
6370#define regTCP_STATUS 0x19a16370#define regTCP_STATUS 0x19a1
6371#define regTCP_STATUS_BASE_IDX 16371#define regTCP_STATUS_BASE_IDX 1
6372#define regTCP_CNTL 0x19a2
6373#define regTCP_CNTL_BASE_IDX 1
6372#define regTCP_CNTL2 0x19a36374#define regTCP_CNTL2 0x19a3
6373#define regTCP_CNTL2_BASE_IDX 16375#define regTCP_CNTL2_BASE_IDX 1
6374#define regTCP_DEBUG_INDEX 0x19a56376#define regTCP_DEBUG_INDEX 0x19a5
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h+2−0
@@ -781,6 +781,8 @@ · 780 unmodified lines
781#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX 5781#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX 5
782#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 0x420187782#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 0x420187
783#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX 5783#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
784#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3 0x4201c6
785#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3_BASE_IDX 5
784 786
785 787
786// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp788// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h+29−0
@@ -24646,6 +24646,35 @@ · 24645 unmodified lines
24646//BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_124646//BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1
24647#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L24647#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
24648#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L24648#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
24649//BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3
24650#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8
24651#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9
24652#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE__SHIFT 0xb
24653#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT 0xd
24654#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN__SHIFT 0xf
24655#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
24656#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
24657#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
24658#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
24659#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
24660#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
24661#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b
24662#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c
24663#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e
24664#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L
24665#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L
24666#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE_MASK 0x00001800L
24667#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK 0x00006000L
24668#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN_MASK 0x00008000L
24669#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
24670#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L
24671#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
24672#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L
24673#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
24674#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
24675#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L
24676#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L
24677#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L
24649 24678
24650// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp24679// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
24651//BIF_CFG_DEV0_RC0_VENDOR_ID24680//BIF_CFG_DEV0_RC0_VENDOR_ID
drivers/gpu/drm/amd/include/kgd_pp_interface.h+1−0
@@ -444,6 +444,7 @@ struct amd_pm_funcs { · 443 unmodified lines
444 struct dpm_clocks *clock_table);444 struct dpm_clocks *clock_table);
445 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);445 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
446 void (*pm_compute_clocks)(void *handle);446 void (*pm_compute_clocks)(void *handle);
447 int (*notify_rlc_state)(void *handle, bool en);
447};448};
448 449
449struct metrics_table_header {450struct metrics_table_header {
drivers/gpu/drm/amd/pm/amdgpu_dpm.c+18−0
@@ -181,6 +181,24 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, · 180 unmodified lines
181 return ret;181 return ret;
182}182}
183 183
184int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en)
185{
186 int ret = 0;
187 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
188
189 if (pp_funcs && pp_funcs->notify_rlc_state) {
190 mutex_lock(&adev->pm.mutex);
191
192 ret = pp_funcs->notify_rlc_state(
193 adev->powerplay.pp_handle,
194 en);
195
196 mutex_unlock(&adev->pm.mutex);
197 }
198
199 return ret;
200}
201
184bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)202bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)
185{203{
186 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;204 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h+2−0
@@ -415,6 +415,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); · 414 unmodified lines
415int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,415int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
416 enum pp_mp1_state mp1_state);416 enum pp_mp1_state mp1_state);
417 417
418int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en);
419
418int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);420int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
419 421
420int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);422int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+10−0
@@ -1710,6 +1710,16 @@ static int smu_disable_dpms(struct smu_context *smu) · 1709 unmodified lines
1710 }1710 }
1711 }1711 }
1712 1712
1713 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction.
1714 * otherwise SMU will hang while interacting with RLC if RLC is halted
1715 * this is a WA for Vangogh asic which fix the SMU hang issue.
1716 */
1717 ret = smu_notify_rlc_state(smu, false);
1718 if (ret) {
1719 dev_err(adev->dev, "Fail to notify rlc status!\n");
1720 return ret;
1721 }
1722
1713 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&1723 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&
1714 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&1724 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&
1715 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)1725 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h+5−0
@@ -1360,6 +1360,11 @@ struct pptable_funcs { · 1359 unmodified lines
1360 * management.1360 * management.
1361 */1361 */
1362 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);1362 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);
1363
1364 /**
1365 * @notify_rlc_state: Notify RLC power state to SMU.
1366 */
1367 int (*notify_rlc_state)(struct smu_context *smu, bool en);
1363};1368};
1364 1369
1365typedef enum {1370typedef enum {
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c+2−3
@@ -2193,8 +2193,7 @@ static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clock · 2192 unmodified lines
2193 return 0;2193 return 0;
2194}2194}
2195 2195
2196 2196static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2197static int vangogh_system_features_control(struct smu_context *smu, bool en)
2198{2197{
2199 struct amdgpu_device *adev = smu->adev;2198 struct amdgpu_device *adev = smu->adev;
2200 int ret = 0;2199 int ret = 0;
@@ -2523,7 +2522,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = { · 322 unmodified lines
2523 .print_clk_levels = vangogh_common_print_clk_levels,2522 .print_clk_levels = vangogh_common_print_clk_levels,
2524 .set_default_dpm_table = vangogh_set_default_dpm_tables,2523 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2525 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,2524 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2526 .system_features_control = vangogh_system_features_control,2525 .notify_rlc_state = vangogh_notify_rlc_state,
2527 .feature_is_enabled = smu_cmn_feature_is_enabled,2526 .feature_is_enabled = smu_cmn_feature_is_enabled,
2528 .set_power_profile_mode = vangogh_set_power_profile_mode,2527 .set_power_profile_mode = vangogh_set_power_profile_mode,
2529 .get_power_profile_mode = vangogh_get_power_profile_mode,2528 .get_power_profile_mode = vangogh_get_power_profile_mode,
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+4−1
@@ -257,8 +257,11 @@ static int aldebaran_tables_init(struct smu_context *smu) · 256 unmodified lines
257 }257 }
258 258
259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
260 if (!smu_table->ecc_table)260 if (!smu_table->ecc_table) {
261 kfree(smu_table->metrics_table);
262 kfree(smu_table->gpu_metrics_table);
261 return -ENOMEM;263 return -ENOMEM;
264 }
262 265
263 return 0;266 return 0;
264}267}
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h+1−0
@@ -97,6 +97,7 @@ · 96 unmodified lines
97#define smu_get_default_config_table_settings(smu, config_table) smu_ppt_funcs(get_default_config_table_settings, -EOPNOTSUPP, smu, config_table)97#define smu_get_default_config_table_settings(smu, config_table) smu_ppt_funcs(get_default_config_table_settings, -EOPNOTSUPP, smu, config_table)
98#define smu_set_config_table(smu, config_table) smu_ppt_funcs(set_config_table, -EOPNOTSUPP, smu, config_table)98#define smu_set_config_table(smu, config_table) smu_ppt_funcs(set_config_table, -EOPNOTSUPP, smu, config_table)
99#define smu_init_pptable_microcode(smu) smu_ppt_funcs(init_pptable_microcode, 0, smu)99#define smu_init_pptable_microcode(smu) smu_ppt_funcs(init_pptable_microcode, 0, smu)
100#define smu_notify_rlc_state(smu, en) smu_ppt_funcs(notify_rlc_state, 0, smu, en)
100 101
101#endif102#endif
102#endif103#endif
drivers/gpu/drm/bridge/panel.c+0−17
@@ -4,8 +4,6 @@ · 3 unmodified lines
4 * Copyright (C) 2017 Broadcom4 * Copyright (C) 2017 Broadcom
5 */5 */
6 6
7#include <linux/device.h>
8
9#include <drm/drm_atomic_helper.h>7#include <drm/drm_atomic_helper.h>
10#include <drm/drm_bridge.h>8#include <drm/drm_bridge.h>
11#include <drm/drm_connector.h>9#include <drm/drm_connector.h>
@@ -21,7 +19,6 @@ struct panel_bridge { · 9 unmodified lines
21 struct drm_bridge bridge;19 struct drm_bridge bridge;
22 struct drm_connector connector;20 struct drm_connector connector;
23 struct drm_panel *panel;21 struct drm_panel *panel;
24 struct device_link *link;
25 u32 connector_type;22 u32 connector_type;
26};23};
27 24
@@ -63,24 +60,13 @@ static int panel_bridge_attach(struct drm_bridge *bridge, · 35 unmodified lines
63{60{
64 struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);61 struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
65 struct drm_connector *connector = &panel_bridge->connector;62 struct drm_connector *connector = &panel_bridge->connector;
66 struct drm_panel *panel = panel_bridge->panel;
67 struct drm_device *drm_dev = bridge->dev;
68 int ret;63 int ret;
69 64
70 panel_bridge->link = device_link_add(drm_dev->dev, panel->dev,
71 DL_FLAG_STATELESS);
72 if (!panel_bridge->link) {
73 DRM_ERROR("Failed to add device link between %s and %s\n",
74 dev_name(drm_dev->dev), dev_name(panel->dev));
75 return -EINVAL;
76 }
77
78 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)65 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
79 return 0;66 return 0;
80 67
81 if (!bridge->encoder) {68 if (!bridge->encoder) {
82 DRM_ERROR("Missing encoder\n");69 DRM_ERROR("Missing encoder\n");
83 device_link_del(panel_bridge->link);
84 return -ENODEV;70 return -ENODEV;
85 }71 }
86 72
@@ -92,7 +78,6 @@ static int panel_bridge_attach(struct drm_bridge *bridge, · 5 unmodified lines
92 panel_bridge->connector_type);78 panel_bridge->connector_type);
93 if (ret) {79 if (ret) {
94 DRM_ERROR("Failed to initialize connector\n");80 DRM_ERROR("Failed to initialize connector\n");
95 device_link_del(panel_bridge->link);
96 return ret;81 return ret;
97 }82 }
98 83
@@ -115,8 +100,6 @@ static void panel_bridge_detach(struct drm_bridge *bridge) · 16 unmodified lines
115 struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);100 struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
116 struct drm_connector *connector = &panel_bridge->connector;101 struct drm_connector *connector = &panel_bridge->connector;
117 102
118 device_link_del(panel_bridge->link);
119
120 /*103 /*
121 * Cleanup the connector if we know it was initialized.104 * Cleanup the connector if we know it was initialized.
122 *105 *
drivers/gpu/drm/drm_gpuvm.c+1−1
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 OR MIT1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*2/*
3 * Copyright (c) 2022 Red Hat.3 * Copyright (c) 2022 Red Hat.
4 *4 *
drivers/gpu/drm/drm_prime.c+18−15
@@ -278,7 +278,7 @@ void drm_gem_dmabuf_release(struct dma_buf *dma_buf) · 277 unmodified lines
278}278}
279EXPORT_SYMBOL(drm_gem_dmabuf_release);279EXPORT_SYMBOL(drm_gem_dmabuf_release);
280 280
281/*281/**
282 * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers282 * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers
283 * @dev: drm_device to import into283 * @dev: drm_device to import into
284 * @file_priv: drm file-private structure284 * @file_priv: drm file-private structure
@@ -292,9 +292,9 @@ EXPORT_SYMBOL(drm_gem_dmabuf_release); · 7 unmodified lines
292 *292 *
293 * Returns 0 on success or a negative error code on failure.293 * Returns 0 on success or a negative error code on failure.
294 */294 */
295static int drm_gem_prime_fd_to_handle(struct drm_device *dev,295int drm_gem_prime_fd_to_handle(struct drm_device *dev,
296 struct drm_file *file_priv, int prime_fd,296 struct drm_file *file_priv, int prime_fd,
297 uint32_t *handle)297 uint32_t *handle)
298{298{
299 struct dma_buf *dma_buf;299 struct dma_buf *dma_buf;
300 struct drm_gem_object *obj;300 struct drm_gem_object *obj;
@@ -360,6 +360,7 @@ out_put: · 59 unmodified lines
360 dma_buf_put(dma_buf);360 dma_buf_put(dma_buf);
361 return ret;361 return ret;
362}362}
363EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);
363 364
364int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,365int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
365 struct drm_file *file_priv)366 struct drm_file *file_priv)
@@ -408,7 +409,7 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev, · 42 unmodified lines
408 return dmabuf;409 return dmabuf;
409}410}
410 411
411/*412/**
412 * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers413 * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers
413 * @dev: dev to export the buffer from414 * @dev: dev to export the buffer from
414 * @file_priv: drm file-private structure415 * @file_priv: drm file-private structure
@@ -421,10 +422,10 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev, · 6 unmodified lines
421 * The actual exporting from GEM object to a dma-buf is done through the422 * The actual exporting from GEM object to a dma-buf is done through the
422 * &drm_gem_object_funcs.export callback.423 * &drm_gem_object_funcs.export callback.
423 */424 */
424static int drm_gem_prime_handle_to_fd(struct drm_device *dev,425int drm_gem_prime_handle_to_fd(struct drm_device *dev,
425 struct drm_file *file_priv, uint32_t handle,426 struct drm_file *file_priv, uint32_t handle,
426 uint32_t flags,427 uint32_t flags,
427 int *prime_fd)428 int *prime_fd)
428{429{
429 struct drm_gem_object *obj;430 struct drm_gem_object *obj;
430 int ret = 0;431 int ret = 0;
@@ -506,6 +507,7 @@ out_unlock: · 75 unmodified lines
506 507
507 return ret;508 return ret;
508}509}
510EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
509 511
510int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,512int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file_priv)513 struct drm_file *file_priv)
@@ -864,9 +866,9 @@ EXPORT_SYMBOL(drm_prime_get_contiguous_size); · 352 unmodified lines
864 * @obj: GEM object to export866 * @obj: GEM object to export
865 * @flags: flags like DRM_CLOEXEC and DRM_RDWR867 * @flags: flags like DRM_CLOEXEC and DRM_RDWR
866 *868 *
867 * This is the implementation of the &drm_gem_object_funcs.export functions869 * This is the implementation of the &drm_gem_object_funcs.export functions for GEM drivers
868 * for GEM drivers using the PRIME helpers. It is used as the default for870 * using the PRIME helpers. It is used as the default in
869 * drivers that do not set their own.871 * drm_gem_prime_handle_to_fd().
870 */872 */
871struct dma_buf *drm_gem_prime_export(struct drm_gem_object *obj,873struct dma_buf *drm_gem_prime_export(struct drm_gem_object *obj,
872 int flags)874 int flags)
@@ -962,9 +964,10 @@ EXPORT_SYMBOL(drm_gem_prime_import_dev); · 89 unmodified lines
962 * @dev: drm_device to import into964 * @dev: drm_device to import into
963 * @dma_buf: dma-buf object to import965 * @dma_buf: dma-buf object to import
964 *966 *
965 * This is the implementation of the gem_prime_import functions for GEM967 * This is the implementation of the gem_prime_import functions for GEM drivers
966 * drivers using the PRIME helpers. It is the default for drivers that do968 * using the PRIME helpers. Drivers can use this as their
967 * not set their own &drm_driver.gem_prime_import.969 * &drm_driver.gem_prime_import implementation. It is used as the default
970 * implementation in drm_gem_prime_fd_to_handle().
968 *971 *
969 * Drivers must arrange to call drm_prime_gem_destroy() from their972 * Drivers must arrange to call drm_prime_gem_destroy() from their
970 * &drm_gem_object_funcs.free hook when using this function.973 * &drm_gem_object_funcs.free hook when using this function.
drivers/gpu/drm/i915/display/intel_display.c+2−1
@@ -6853,10 +6853,11 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) · 6852 unmodified lines
6853 if (!intel_crtc_needs_modeset(new_crtc_state))6853 if (!intel_crtc_needs_modeset(new_crtc_state))
6854 continue;6854 continue;
6855 6855
6856 intel_pre_plane_update(state, crtc);
6857
6856 if (!old_crtc_state->hw.active)6858 if (!old_crtc_state->hw.active)
6857 continue;6859 continue;
6858 6860
6859 intel_pre_plane_update(state, crtc);
6860 intel_crtc_disable_planes(state, crtc);6861 intel_crtc_disable_planes(state, crtc);
6861 }6862 }
6862 6863
drivers/gpu/drm/i915/display/intel_dp.c+22−6
@@ -6037,8 +6037,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, · 6036 unmodified lines
6037 * (eg. Acer Chromebook C710), so we'll check it only if multiple6037 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6038 * ports are attempting to use the same AUX CH, according to VBT.6038 * ports are attempting to use the same AUX CH, according to VBT.
6039 */6039 */
6040 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata) &&6040 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6041 !intel_digital_port_connected(encoder)) {
6042 /*6041 /*
6043 * If this fails, presume the DPCD answer came6042 * If this fails, presume the DPCD answer came
6044 * from some other port using the same AUX CH.6043 * from some other port using the same AUX CH.
@@ -6046,10 +6045,27 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, · 1 unmodified line
6046 * FIXME maybe cleaner to check this before the6045 * FIXME maybe cleaner to check this before the
6047 * DPCD read? Would need sort out the VDD handling...6046 * DPCD read? Would need sort out the VDD handling...
6048 */6047 */
6049 drm_info(&dev_priv->drm,6048 if (!intel_digital_port_connected(encoder)) {
6050 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",6049 drm_info(&dev_priv->drm,
6051 encoder->base.base.id, encoder->base.name);6050 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6052 goto out_vdd_off;6051 encoder->base.base.id, encoder->base.name);
6052 goto out_vdd_off;
6053 }
6054
6055 /*
6056 * Unfortunately even the HPD based detection fails on
6057 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6058 * back to checking for a VGA branch device. Only do this
6059 * on known affected platforms to minimize false positives.
6060 */
6061 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6062 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6063 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6064 drm_info(&dev_priv->drm,
6065 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6066 encoder->base.base.id, encoder->base.name);
6067 goto out_vdd_off;
6068 }
6053 }6069 }
6054 6070
6055 mutex_lock(&dev_priv->drm.mode_config.mutex);6071 mutex_lock(&dev_priv->drm.mode_config.mutex);
drivers/gpu/drm/i915/gt/intel_engine_user.c+22−17
@@ -41,12 +41,15 @@ void intel_engine_add_user(struct intel_engine_cs *engine) · 40 unmodified lines
41 llist_add(&engine->uabi_llist, &engine->i915->uabi_engines_llist);41 llist_add(&engine->uabi_llist, &engine->i915->uabi_engines_llist);
42}42}
43 43
44static const u8 uabi_classes[] = {44#define I915_NO_UABI_CLASS ((u16)(-1))
45
46static const u16 uabi_classes[] = {
45 [RENDER_CLASS] = I915_ENGINE_CLASS_RENDER,47 [RENDER_CLASS] = I915_ENGINE_CLASS_RENDER,
46 [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,48 [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
47 [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,49 [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
48 [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,50 [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
49 [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,51 [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
52 [OTHER_CLASS] = I915_NO_UABI_CLASS, /* Not exposed to users, no uabi class. */
50};53};
51 54
52static int engine_cmp(void *priv, const struct list_head *A,55static int engine_cmp(void *priv, const struct list_head *A,
@@ -200,6 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 · 147 unmodified lines
200 203
201void intel_engines_driver_register(struct drm_i915_private *i915)204void intel_engines_driver_register(struct drm_i915_private *i915)
202{205{
206 u16 name_instance, other_instance = 0;
203 struct legacy_ring ring = {};207 struct legacy_ring ring = {};
204 struct list_head *it, *next;208 struct list_head *it, *next;
205 struct rb_node **p, *prev;209 struct rb_node **p, *prev;
@@ -216,27 +220,28 @@ void intel_engines_driver_register(struct drm_i915_private *i915) · 10 unmodified lines
216 if (intel_gt_has_unrecoverable_error(engine->gt))220 if (intel_gt_has_unrecoverable_error(engine->gt))
217 continue; /* ignore incomplete engines */221 continue; /* ignore incomplete engines */
218 222
219 /*
220 * We don't want to expose the GSC engine to the users, but we
221 * still rename it so it is easier to identify in the debug logs
222 */
223 if (engine->id == GSC0) {
224 engine_rename(engine, "gsc", 0);
225 continue;
226 }
227
228 GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));223 GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
229 engine->uabi_class = uabi_classes[engine->class];224 engine->uabi_class = uabi_classes[engine->class];
225 if (engine->uabi_class == I915_NO_UABI_CLASS) {
226 name_instance = other_instance++;
227 } else {
228 GEM_BUG_ON(engine->uabi_class >=
229 ARRAY_SIZE(i915->engine_uabi_class_count));
230 name_instance =
231 i915->engine_uabi_class_count[engine->uabi_class]++;
232 }
233 engine->uabi_instance = name_instance;
230 234
231 GEM_BUG_ON(engine->uabi_class >=235 /*
232 ARRAY_SIZE(i915->engine_uabi_class_count));236 * Replace the internal name with the final user and log facing
233 engine->uabi_instance =237 * name.
234 i915->engine_uabi_class_count[engine->uabi_class]++;238 */
235
236 /* Replace the internal name with the final user facing name */
237 engine_rename(engine,239 engine_rename(engine,
238 intel_engine_class_repr(engine->class),240 intel_engine_class_repr(engine->class),
239 engine->uabi_instance);241 name_instance);
242
243 if (engine->uabi_class == I915_NO_UABI_CLASS)
244 continue;
240 245
241 rb_link_node(&engine->uabi_node, prev, p);246 rb_link_node(&engine->uabi_node, prev, p);
242 rb_insert_color(&engine->uabi_node, &i915->uabi_engines);247 rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h+1−1
@@ -38,7 +38,7 @@ typedef struct PACKED_REGISTRY_TABLE · 37 unmodified lines
38{38{
39 NvU32 size;39 NvU32 size;
40 NvU32 numEntries;40 NvU32 numEntries;
41 PACKED_REGISTRY_ENTRY entries[0];41 PACKED_REGISTRY_ENTRY entries[] __counted_by(numEntries);
42} PACKED_REGISTRY_TABLE;42} PACKED_REGISTRY_TABLE;
43 43
44#endif44#endif
drivers/gpu/drm/nouveau/nouveau_bo.c+3−2
@@ -318,8 +318,9 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, · 317 unmodified lines
318 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))318 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
319 continue;319 continue;
320 320
321 if (pi < 0)321 /* pick the last one as it will be smallest. */
322 pi = i;322 pi = i;
323
323 /* Stop once the buffer is larger than the current page size. */324 /* Stop once the buffer is larger than the current page size. */
324 if (*size >= 1ULL << vmm->page[i].shift)325 if (*size >= 1ULL << vmm->page[i].shift)
325 break;326 break;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c+2−4
@@ -365,10 +365,8 @@ r535_gsp_rpc_send(struct nvkm_gsp *gsp, void *argv, bool wait, u32 repc) · 364 unmodified lines
365 }365 }
366 366
367 ret = r535_gsp_cmdq_push(gsp, rpc);367 ret = r535_gsp_cmdq_push(gsp, rpc);
368 if (ret) {368 if (ret)
369 mutex_unlock(&gsp->cmdq.mutex);
370 return ERR_PTR(ret);369 return ERR_PTR(ret);
371 }
372 370
373 if (wait) {371 if (wait) {
374 msg = r535_gsp_msg_recv(gsp, fn, repc);372 msg = r535_gsp_msg_recv(gsp, fn, repc);
@@ -1048,7 +1046,7 @@ r535_gsp_rpc_set_registry(struct nvkm_gsp *gsp) · 673 unmodified lines
1048 char *strings;1046 char *strings;
1049 int str_offset;1047 int str_offset;
1050 int i;1048 int i;
1051 size_t rpc_size = sizeof(*rpc) + sizeof(rpc->entries[0]) * NV_GSP_REG_NUM_ENTRIES;1049 size_t rpc_size = struct_size(rpc, entries, NV_GSP_REG_NUM_ENTRIES);
1052 1050
1053 /* add strings + null terminator */1051 /* add strings + null terminator */
1054 for (i = 0; i < NV_GSP_REG_NUM_ENTRIES; i++)1052 for (i = 0; i < NV_GSP_REG_NUM_ENTRIES; i++)
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c+1−0
@@ -1764,6 +1764,7 @@ static const struct panel_desc starry_qfh032011_53g_desc = { · 1763 unmodified lines
1764 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |1764 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1765 MIPI_DSI_MODE_LPM,1765 MIPI_DSI_MODE_LPM,
1766 .init_cmds = starry_qfh032011_53g_init_cmd,1766 .init_cmds = starry_qfh032011_53g_init_cmd,
1767 .lp11_before_reset = true,
1767};1768};
1768 1769
1769static const struct drm_display_mode starry_himax83102_j02_default_mode = {1770static const struct drm_display_mode starry_himax83102_j02_default_mode = {
drivers/gpu/drm/panel/panel-novatek-nt36523.c+2−2
@@ -1254,9 +1254,9 @@ static int nt36523_probe(struct mipi_dsi_device *dsi) · 1253 unmodified lines
1254 return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");1254 return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");
1255 1255
1256 pinfo->dsi[1] = mipi_dsi_device_register_full(dsi1_host, info);1256 pinfo->dsi[1] = mipi_dsi_device_register_full(dsi1_host, info);
1257 if (!pinfo->dsi[1]) {1257 if (IS_ERR(pinfo->dsi[1])) {
1258 dev_err(dev, "cannot get secondary DSI device\n");1258 dev_err(dev, "cannot get secondary DSI device\n");
1259 return -ENODEV;1259 return PTR_ERR(pinfo->dsi[1]);
1260 }1260 }
1261 }1261 }
1262 1262
include/drm/drm_gpuvm.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 OR MIT */1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2 2
3#ifndef __DRM_GPUVM_H__3#ifndef __DRM_GPUVM_H__
4#define __DRM_GPUVM_H__4#define __DRM_GPUVM_H__
include/drm/drm_prime.h+7−0
@@ -60,12 +60,19 @@ enum dma_data_direction; · 59 unmodified lines
60 60
61struct drm_device;61struct drm_device;
62struct drm_gem_object;62struct drm_gem_object;
63struct drm_file;
63 64
64/* core prime functions */65/* core prime functions */
65struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,66struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
66 struct dma_buf_export_info *exp_info);67 struct dma_buf_export_info *exp_info);
67void drm_gem_dmabuf_release(struct dma_buf *dma_buf);68void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
68 69
70int drm_gem_prime_fd_to_handle(struct drm_device *dev,
71 struct drm_file *file_priv, int prime_fd, uint32_t *handle);
72int drm_gem_prime_handle_to_fd(struct drm_device *dev,
73 struct drm_file *file_priv, uint32_t handle, uint32_t flags,
74 int *prime_fd);
75
69/* helper functions for exporting */76/* helper functions for exporting */
70int drm_gem_map_attach(struct dma_buf *dma_buf,77int drm_gem_map_attach(struct dma_buf *dma_buf,
71 struct dma_buf_attachment *attach);78 struct dma_buf_attachment *attach);
include/linux/dma-fence.h+15−0
@@ -498,6 +498,21 @@ static inline bool dma_fence_is_later(struct dma_fence *f1, · 497 unmodified lines
498 return __dma_fence_is_later(f1->seqno, f2->seqno, f1->ops);498 return __dma_fence_is_later(f1->seqno, f2->seqno, f1->ops);
499}499}
500 500
501/**
502 * dma_fence_is_later_or_same - return true if f1 is later or same as f2
503 * @f1: the first fence from the same context
504 * @f2: the second fence from the same context
505 *
506 * Returns true if f1 is chronologically later than f2 or the same fence. Both
507 * fences must be from the same context, since a seqno is not re-used across
508 * contexts.
509 */
510static inline bool dma_fence_is_later_or_same(struct dma_fence *f1,
511 struct dma_fence *f2)
512{
513 return f1 == f2 || dma_fence_is_later(f1, f2);
514}
515
501/**516/**
502 * dma_fence_later - return the chronologically later fence517 * dma_fence_later - return the chronologically later fence
503 * @f1: the first fence from the same context518 * @f1: the first fence from the same context