History

Merge tag 'gpio-updates-for-v5.9-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

gpio updates for v5.9 - use kobj_to_dev() in sysfs interface - kerneldoc and documentation fixes - relax the interrupt flags in gpio-mpc8xxx - support new model in gpio-pca953x - remove a redundant check from gpio-max732x - support a new platform in gpio-zynq (+ some minor fixes) - don't depend on GPIOLIB when already inside the "if GPIOLIB" in Kconfig - support PM ops for suspend in gpio-omap - minor tweaks in gpiolib

Linus Walleij committed 6 years ago

Commit b239e442 parents 84651e8 ae66eca11 files · +106 −15Browse files

Unified · Split

11 files
  1. Documentation/devicetree/bindings/gpio/gpio-pca953x.txt +1 −0
  2. Documentation/devicetree/bindings/gpio/gpio-zynq.txt +3 −1
  3. drivers/gpio/Kconfig +2 −2
  4. drivers/gpio/TODO +1 −1
  5. drivers/gpio/gpio-mpc8xxx.c +1 −1
  6. drivers/gpio/gpio-omap.c +26 −0
  7. drivers/gpio/gpio-pca953x.c +2 −0
  8. drivers/gpio/gpio-zynq.c +64 −2
  9. drivers/gpio/gpiolib-sysfs.c +1 −1
  10. drivers/gpio/gpiolib.c +4 −6
  11. include/linux/gpio/driver.h +1 −1
Documentation/devicetree/bindings/gpio/gpio-pca953x.txt+1−0
@@ -19,6 +19,7 @@ Required properties: · 18 unmodified lines
19 nxp,pca969819 nxp,pca9698
20 nxp,pcal641620 nxp,pcal6416
21 nxp,pcal652421 nxp,pcal6524
22 nxp,pcal9535
22 nxp,pcal9555a23 nxp,pcal9555a
23 maxim,max731024 maxim,max7310
24 maxim,max731225 maxim,max7312
Documentation/devicetree/bindings/gpio/gpio-zynq.txt+3−1
@@ -6,7 +6,9 @@ Required properties: · 5 unmodified lines
6 - First cell is the GPIO line number6 - First cell is the GPIO line number
7 - Second cell is used to specify optional7 - Second cell is used to specify optional
8 parameters (unused)8 parameters (unused)
9- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0"9- compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
10- clocks : Clock specifier (see clock bindings for details)12- clocks : Clock specifier (see clock bindings for details)
11- gpio-controller : Marks the device node as a GPIO controller.13- gpio-controller : Marks the device node as a GPIO controller.
12- interrupts : Interrupt specifier (see interrupt bindings for14- interrupts : Interrupt specifier (see interrupt bindings for
drivers/gpio/Kconfig+2−2
@@ -410,7 +410,7 @@ config GPIO_MXS · 409 unmodified lines
410 410
411config GPIO_OCTEON411config GPIO_OCTEON
412 tristate "Cavium OCTEON GPIO"412 tristate "Cavium OCTEON GPIO"
413 depends on GPIOLIB && CAVIUM_OCTEON_SOC413 depends on CAVIUM_OCTEON_SOC
414 default y414 default y
415 help415 help
416 Say yes here to support the on-chip GPIO lines on the OCTEON416 Say yes here to support the on-chip GPIO lines on the OCTEON
@@ -1117,7 +1117,7 @@ config GPIO_DLN2 · 700 unmodified lines
1117 1117
1118config HTC_EGPIO1118config HTC_EGPIO
1119 bool "HTC EGPIO support"1119 bool "HTC EGPIO support"
1120 depends on GPIOLIB && ARM1120 depends on ARM
1121 help1121 help
1122 This driver supports the CPLD egpio chip present on1122 This driver supports the CPLD egpio chip present on
1123 several HTC phones. It provides basic support for input1123 several HTC phones. It provides basic support for input
drivers/gpio/TODO+1−1
@@ -5,7 +5,7 @@ subsystem. · 4 unmodified lines
5GPIO descriptors5GPIO descriptors
6 6
7Starting with commit 79a9becda894 the GPIO subsystem embarked on a journey7Starting with commit 79a9becda894 the GPIO subsystem embarked on a journey
8to move away from the global GPIO numberspace and toward a decriptor-based8to move away from the global GPIO numberspace and toward a descriptor-based
9approach. This means that GPIO consumers, drivers and machine descriptions9approach. This means that GPIO consumers, drivers and machine descriptions
10ideally have no use or idea of the global GPIO numberspace that has/was10ideally have no use or idea of the global GPIO numberspace that has/was
11used in the inception of the GPIO subsystem.11used in the inception of the GPIO subsystem.
drivers/gpio/gpio-mpc8xxx.c+1−1
@@ -417,7 +417,7 @@ static int mpc8xxx_probe(struct platform_device *pdev) · 416 unmodified lines
417 417
418 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,418 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
419 mpc8xxx_gpio_irq_cascade,419 mpc8xxx_gpio_irq_cascade,
420 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",420 IRQF_SHARED, "gpio-cascade",
421 mpc8xxx_gc);421 mpc8xxx_gc);
422 if (ret) {422 if (ret) {
423 dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",423 dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
drivers/gpio/gpio-omap.c+26−0
@@ -60,6 +60,7 @@ struct gpio_bank { · 59 unmodified lines
60 struct clk *dbck;60 struct clk *dbck;
61 struct notifier_block nb;61 struct notifier_block nb;
62 unsigned int is_suspended:1;62 unsigned int is_suspended:1;
63 unsigned int needs_resume:1;
63 u32 mod_usage;64 u32 mod_usage;
64 u32 irq_usage;65 u32 irq_usage;
65 u32 dbck_enable_mask;66 u32 dbck_enable_mask;
@@ -1504,9 +1505,34 @@ static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) · 1438 unmodified lines
1504 return 0;1505 return 0;
1505}1506}
1506 1507
1508static int omap_gpio_suspend(struct device *dev)
1509{
1510 struct gpio_bank *bank = dev_get_drvdata(dev);
1511
1512 if (bank->is_suspended)
1513 return 0;
1514
1515 bank->needs_resume = 1;
1516
1517 return omap_gpio_runtime_suspend(dev);
1518}
1519
1520static int omap_gpio_resume(struct device *dev)
1521{
1522 struct gpio_bank *bank = dev_get_drvdata(dev);
1523
1524 if (!bank->needs_resume)
1525 return 0;
1526
1527 bank->needs_resume = 0;
1528
1529 return omap_gpio_runtime_resume(dev);
1530}
1531
1507static const struct dev_pm_ops gpio_pm_ops = {1532static const struct dev_pm_ops gpio_pm_ops = {
1508 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,1533 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1509 NULL)1534 NULL)
1535 SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1510};1536};
1511 1537
1512static struct platform_driver omap_gpio_driver = {1538static struct platform_driver omap_gpio_driver = {
drivers/gpio/gpio-pca953x.c+2−0
@@ -89,6 +89,7 @@ static const struct i2c_device_id pca953x_id[] = { · 88 unmodified lines
89 89
90 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },90 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
91 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },91 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
92 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
92 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },93 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
93 94
94 { "max7310", 8 | PCA953X_TYPE, },95 { "max7310", 8 | PCA953X_TYPE, },
@@ -1145,6 +1146,7 @@ static const struct of_device_id pca953x_dt_ids[] = { · 1050 unmodified lines
1145 1146
1146 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },1147 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1147 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },1148 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1149 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1148 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },1150 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1149 1151
1150 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },1152 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
drivers/gpio/gpio-zynq.c+64−2
@@ -10,6 +10,7 @@ · 9 unmodified lines
10#include <linux/gpio/driver.h>10#include <linux/gpio/driver.h>
11#include <linux/init.h>11#include <linux/init.h>
12#include <linux/interrupt.h>12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
13#include <linux/io.h>14#include <linux/io.h>
14#include <linux/module.h>15#include <linux/module.h>
15#include <linux/platform_device.h>16#include <linux/platform_device.h>
@@ -21,6 +22,9 @@ · 5 unmodified lines
21/* Maximum banks */22/* Maximum banks */
22#define ZYNQ_GPIO_MAX_BANK 423#define ZYNQ_GPIO_MAX_BANK 4
23#define ZYNQMP_GPIO_MAX_BANK 624#define ZYNQMP_GPIO_MAX_BANK 6
25#define VERSAL_GPIO_MAX_BANK 4
26#define PMC_GPIO_MAX_BANK 5
27#define VERSAL_UNUSED_BANKS 2
24 28
25#define ZYNQ_GPIO_BANK0_NGPIO 3229#define ZYNQ_GPIO_BANK0_NGPIO 32
26#define ZYNQ_GPIO_BANK1_NGPIO 2230#define ZYNQ_GPIO_BANK1_NGPIO 22
@@ -95,6 +99,7 @@ · 68 unmodified lines
95/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
96#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
97#define GPIO_QUIRK_DATA_RO_BUG BIT(1)101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
102#define GPIO_QUIRK_VERSAL BIT(2)
98 103
99struct gpio_regs {104struct gpio_regs {
100 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
@@ -116,6 +121,7 @@ struct gpio_regs { · 15 unmodified lines
116 * @irq: interrupt for the GPIO device121 * @irq: interrupt for the GPIO device
117 * @p_data: pointer to platform data122 * @p_data: pointer to platform data
118 * @context: context registers123 * @context: context registers
124 * @dirlock: lock used for direction in/out synchronization
119 */125 */
120struct zynq_gpio {126struct zynq_gpio {
121 struct gpio_chip chip;127 struct gpio_chip chip;
@@ -124,6 +130,7 @@ struct zynq_gpio { · 2 unmodified lines
124 int irq;130 int irq;
125 const struct zynq_platform_data *p_data;131 const struct zynq_platform_data *p_data;
126 struct gpio_regs context;132 struct gpio_regs context;
133 spinlock_t dirlock; /* lock */
127};134};
128 135
129/**136/**
@@ -196,6 +203,8 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, · 66 unmodified lines
196 gpio->p_data->bank_min[bank];203 gpio->p_data->bank_min[bank];
197 return;204 return;
198 }205 }
206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
207 bank = bank + VERSAL_UNUSED_BANKS;
199 }208 }
200 209
201 /* default */210 /* default */
@@ -297,6 +306,7 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) · 95 unmodified lines
297{306{
298 u32 reg;307 u32 reg;
299 unsigned int bank_num, bank_pin_num;308 unsigned int bank_num, bank_pin_num;
309 unsigned long flags;
300 struct zynq_gpio *gpio = gpiochip_get_data(chip);310 struct zynq_gpio *gpio = gpiochip_get_data(chip);
301 311
302 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
@@ -310,9 +320,11 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) · 7 unmodified lines
310 return -EINVAL;320 return -EINVAL;
311 321
312 /* clear the bit in direction mode reg to set the pin as input */322 /* clear the bit in direction mode reg to set the pin as input */
323 spin_lock_irqsave(&gpio->dirlock, flags);
313 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
314 reg &= ~BIT(bank_pin_num);325 reg &= ~BIT(bank_pin_num);
315 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
327 spin_unlock_irqrestore(&gpio->dirlock, flags);
316 328
317 return 0;329 return 0;
318}330}
@@ -334,11 +346,13 @@ static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, · 15 unmodified lines
334{346{
335 u32 reg;347 u32 reg;
336 unsigned int bank_num, bank_pin_num;348 unsigned int bank_num, bank_pin_num;
349 unsigned long flags;
337 struct zynq_gpio *gpio = gpiochip_get_data(chip);350 struct zynq_gpio *gpio = gpiochip_get_data(chip);
338 351
339 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
340 353
341 /* set the GPIO pin as output */354 /* set the GPIO pin as output */
355 spin_lock_irqsave(&gpio->dirlock, flags);
342 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
343 reg |= BIT(bank_pin_num);357 reg |= BIT(bank_pin_num);
344 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
@@ -347,6 +361,7 @@ static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, · 2 unmodified lines
347 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
348 reg |= BIT(bank_pin_num);362 reg |= BIT(bank_pin_num);
349 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
364 spin_unlock_irqrestore(&gpio->dirlock, flags);
350 365
351 /* set the state of the pin */366 /* set the state of the pin */
352 zynq_gpio_set_value(chip, pin, state);367 zynq_gpio_set_value(chip, pin, state);
@@ -647,6 +662,8 @@ static void zynq_gpio_irqhandler(struct irq_desc *desc) · 294 unmodified lines
647 int_enb = readl_relaxed(gpio->base_addr +662 int_enb = readl_relaxed(gpio->base_addr +
648 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));663 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
649 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);664 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
665 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
666 bank_num = bank_num + VERSAL_UNUSED_BANKS;
650 }667 }
651 668
652 chained_irq_exit(irqchip, desc);669 chained_irq_exit(irqchip, desc);
@@ -676,6 +693,8 @@ static void zynq_gpio_save_context(struct zynq_gpio *gpio) · 23 unmodified lines
676 gpio->context.int_any[bank_num] =693 gpio->context.int_any[bank_num] =
677 readl_relaxed(gpio->base_addr +694 readl_relaxed(gpio->base_addr +
678 ZYNQ_GPIO_INTANY_OFFSET(bank_num));695 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
696 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
697 bank_num = bank_num + VERSAL_UNUSED_BANKS;
679 }698 }
680}699}
681 700
@@ -707,6 +726,8 @@ static void zynq_gpio_restore_context(struct zynq_gpio *gpio) · 25 unmodified lines
707 writel_relaxed(~(gpio->context.int_en[bank_num]),726 writel_relaxed(~(gpio->context.int_en[bank_num]),
708 gpio->base_addr +727 gpio->base_addr +
709 ZYNQ_GPIO_INTEN_OFFSET(bank_num));728 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
729 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
730 bank_num = bank_num + VERSAL_UNUSED_BANKS;
710 }731 }
711}732}
712 733
@@ -715,6 +736,9 @@ static int __maybe_unused zynq_gpio_suspend(struct device *dev) · 2 unmodified lines
715 struct zynq_gpio *gpio = dev_get_drvdata(dev);736 struct zynq_gpio *gpio = dev_get_drvdata(dev);
716 struct irq_data *data = irq_get_irq_data(gpio->irq);737 struct irq_data *data = irq_get_irq_data(gpio->irq);
717 738
739 if (!device_may_wakeup(dev))
740 disable_irq(gpio->irq);
741
718 if (!irqd_is_wakeup_set(data)) {742 if (!irqd_is_wakeup_set(data)) {
719 zynq_gpio_save_context(gpio);743 zynq_gpio_save_context(gpio);
720 return pm_runtime_force_suspend(dev);744 return pm_runtime_force_suspend(dev);
@@ -729,6 +753,9 @@ static int __maybe_unused zynq_gpio_resume(struct device *dev) · 8 unmodified lines
729 struct irq_data *data = irq_get_irq_data(gpio->irq);753 struct irq_data *data = irq_get_irq_data(gpio->irq);
730 int ret;754 int ret;
731 755
756 if (!device_may_wakeup(dev))
757 enable_irq(gpio->irq);
758
732 if (!irqd_is_wakeup_set(data)) {759 if (!irqd_is_wakeup_set(data)) {
733 ret = pm_runtime_force_resume(dev);760 ret = pm_runtime_force_resume(dev);
734 zynq_gpio_restore_context(gpio);761 zynq_gpio_restore_context(gpio);
@@ -778,6 +805,31 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { · 43 unmodified lines
778 zynq_gpio_runtime_resume, NULL)805 zynq_gpio_runtime_resume, NULL)
779};806};
780 807
808static const struct zynq_platform_data versal_gpio_def = {
809 .label = "versal_gpio",
810 .quirks = GPIO_QUIRK_VERSAL,
811 .ngpio = 58,
812 .max_bank = VERSAL_GPIO_MAX_BANK,
813 .bank_min[0] = 0,
814 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
815 .bank_min[3] = 26,
816 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
817};
818
819static const struct zynq_platform_data pmc_gpio_def = {
820 .label = "pmc_gpio",
821 .ngpio = 116,
822 .max_bank = PMC_GPIO_MAX_BANK,
823 .bank_min[0] = 0,
824 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
825 .bank_min[1] = 26,
826 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
827 .bank_min[3] = 52,
828 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
829 .bank_min[4] = 84,
830 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
831};
832
781static const struct zynq_platform_data zynqmp_gpio_def = {833static const struct zynq_platform_data zynqmp_gpio_def = {
782 .label = "zynqmp_gpio",834 .label = "zynqmp_gpio",
783 .quirks = GPIO_QUIRK_DATA_RO_BUG,835 .quirks = GPIO_QUIRK_DATA_RO_BUG,
@@ -815,6 +867,8 @@ static const struct zynq_platform_data zynq_gpio_def = { · 31 unmodified lines
815static const struct of_device_id zynq_gpio_of_match[] = {867static const struct of_device_id zynq_gpio_of_match[] = {
816 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },868 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
817 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },869 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
870 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
871 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
818 { /* end of table */ }872 { /* end of table */ }
819};873};
820MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);874MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
@@ -876,7 +930,8 @@ static int zynq_gpio_probe(struct platform_device *pdev) · 55 unmodified lines
876 /* Retrieve GPIO clock */930 /* Retrieve GPIO clock */
877 gpio->clk = devm_clk_get(&pdev->dev, NULL);931 gpio->clk = devm_clk_get(&pdev->dev, NULL);
878 if (IS_ERR(gpio->clk)) {932 if (IS_ERR(gpio->clk)) {
879 dev_err(&pdev->dev, "input clock not found.\n");933 if (PTR_ERR(gpio->clk) != -EPROBE_DEFER)
934 dev_err(&pdev->dev, "input clock not found.\n");
880 return PTR_ERR(gpio->clk);935 return PTR_ERR(gpio->clk);
881 }936 }
882 ret = clk_prepare_enable(gpio->clk);937 ret = clk_prepare_enable(gpio->clk);
@@ -885,6 +940,8 @@ static int zynq_gpio_probe(struct platform_device *pdev) · 2 unmodified lines
885 return ret;940 return ret;
886 }941 }
887 942
943 spin_lock_init(&gpio->dirlock);
944
888 pm_runtime_set_active(&pdev->dev);945 pm_runtime_set_active(&pdev->dev);
889 pm_runtime_enable(&pdev->dev);946 pm_runtime_enable(&pdev->dev);
890 ret = pm_runtime_get_sync(&pdev->dev);947 ret = pm_runtime_get_sync(&pdev->dev);
@@ -892,9 +949,12 @@ static int zynq_gpio_probe(struct platform_device *pdev) · 1 unmodified line
892 goto err_pm_dis;949 goto err_pm_dis;
893 950
894 /* disable interrupts for all banks */951 /* disable interrupts for all banks */
895 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)952 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
896 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +953 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
897 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));954 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
955 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
956 bank_num = bank_num + VERSAL_UNUSED_BANKS;
957 }
898 958
899 /* Set up the GPIO irqchip */959 /* Set up the GPIO irqchip */
900 girq = &chip->irq;960 girq = &chip->irq;
@@ -919,6 +979,8 @@ static int zynq_gpio_probe(struct platform_device *pdev) · 18 unmodified lines
919 goto err_pm_put;979 goto err_pm_put;
920 }980 }
921 981
982 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
983 device_init_wakeup(&pdev->dev, 1);
922 pm_runtime_put(&pdev->dev);984 pm_runtime_put(&pdev->dev);
923 985
924 return 0;986 return 0;
drivers/gpio/gpiolib-sysfs.c+1−1
@@ -365,7 +365,7 @@ static DEVICE_ATTR_RW(active_low); · 364 unmodified lines
365static umode_t gpio_is_visible(struct kobject *kobj, struct attribute *attr,365static umode_t gpio_is_visible(struct kobject *kobj, struct attribute *attr,
366 int n)366 int n)
367{367{
368 struct device *dev = container_of(kobj, struct device, kobj);368 struct device *dev = kobj_to_dev(kobj);
369 struct gpiod_data *data = dev_get_drvdata(dev);369 struct gpiod_data *data = dev_get_drvdata(dev);
370 struct gpio_desc *desc = data->desc;370 struct gpio_desc *desc = data->desc;
371 umode_t mode = attr->mode;371 umode_t mode = attr->mode;
drivers/gpio/gpiolib.c+4−6
@@ -2594,10 +2594,9 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep, · 2593 unmodified lines
2594 bitmap_xor(value_bitmap, value_bitmap,2594 bitmap_xor(value_bitmap, value_bitmap,
2595 array_info->invert_mask, array_size);2595 array_info->invert_mask, array_size);
2596 2596
2597 if (bitmap_full(array_info->get_mask, array_size))
2598 return 0;
2599
2600 i = find_first_zero_bit(array_info->get_mask, array_size);2597 i = find_first_zero_bit(array_info->get_mask, array_size);
2598 if (i == array_size)
2599 return 0;
2601 } else {2600 } else {
2602 array_info = NULL;2601 array_info = NULL;
2603 }2602 }
@@ -2878,10 +2877,9 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep, · 274 unmodified lines
2878 gpio_chip_set_multiple(array_info->chip, array_info->set_mask,2877 gpio_chip_set_multiple(array_info->chip, array_info->set_mask,
2879 value_bitmap);2878 value_bitmap);
2880 2879
2881 if (bitmap_full(array_info->set_mask, array_size))
2882 return 0;
2883
2884 i = find_first_zero_bit(array_info->set_mask, array_size);2880 i = find_first_zero_bit(array_info->set_mask, array_size);
2881 if (i == array_size)
2882 return 0;
2885 } else {2883 } else {
2886 array_info = NULL;2884 array_info = NULL;
2887 }2885 }
include/linux/gpio/driver.h+1−1
@@ -497,7 +497,7 @@ extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, · 496 unmodified lines
497 497
498/**498/**
499 * gpiochip_add_data() - register a gpio_chip499 * gpiochip_add_data() - register a gpio_chip
500 * @chip: the chip to register, with chip->base initialized500 * @gc: the chip to register, with chip->base initialized
501 * @data: driver-private data associated with this chip501 * @data: driver-private data associated with this chip
502 *502 *
503 * Context: potentially before irqs will work503 * Context: potentially before irqs will work