Pick up another "Soft Reservation" fix for v6.0-final on top of some straggling nvdimm fixes that missed v5.19.
Unified · Split
| @@ -516,6 +516,7 @@ ForEachMacros: · 515 unmodified lines | |||
| 516 | - 'of_property_for_each_string' | 516 | - 'of_property_for_each_string' |
| 517 | - 'of_property_for_each_u32' | 517 | - 'of_property_for_each_u32' |
| 518 | - 'pci_bus_for_each_resource' | 518 | - 'pci_bus_for_each_resource' |
| 519 | - 'pci_doe_for_each_off' | ||
| 519 | - 'pcl_for_each_chunk' | 520 | - 'pcl_for_each_chunk' |
| 520 | - 'pcl_for_each_segment' | 521 | - 'pcl_for_each_segment' |
| 521 | - 'pcm_for_each_format' | 522 | - 'pcm_for_each_format' |
| @@ -1,2 +1,4 @@ | |||
| 1 | Alan Cox <alan@lxorguk.ukuu.org.uk> | ||
| 2 | Alan Cox <root@hraefn.swansea.linux.org.uk> | ||
| 1 | Christoph Hellwig <hch@lst.de> | 3 | Christoph Hellwig <hch@lst.de> |
| 2 | Marc Gonzalez <marc.w.gonzalez@free.fr> | 4 | Marc Gonzalez <marc.w.gonzalez@free.fr> |
| @@ -60,10 +60,17 @@ Arnd Bergmann <arnd@arndb.de> · 59 unmodified lines | |||
| 60 | Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com> | 60 | Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com> |
| 61 | Axel Dyks <xl@xlsigned.net> | 61 | Axel Dyks <xl@xlsigned.net> |
| 62 | Axel Lin <axel.lin@gmail.com> | 62 | Axel Lin <axel.lin@gmail.com> |
| 63 | Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang@linaro.org> | ||
| 64 | Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang@spreadtrum.com> | ||
| 65 | Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang@unisoc.com> | ||
| 66 | Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang7@gmail.com> | ||
| 63 | Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com> | 67 | Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com> |
| 64 | Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com> | 68 | Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com> |
| 65 | Ben Gardner <bgardner@wabtec.com> | 69 | Ben Gardner <bgardner@wabtec.com> |
| 66 | Ben M Cahill <ben.m.cahill@intel.com> | 70 | Ben M Cahill <ben.m.cahill@intel.com> |
| 71 | Ben Widawsky <bwidawsk@kernel.org> <ben@bwidawsk.net> | ||
| 72 | Ben Widawsky <bwidawsk@kernel.org> <ben.widawsky@intel.com> | ||
| 73 | Ben Widawsky <bwidawsk@kernel.org> <benjamin.widawsky@intel.com> | ||
| 67 | Björn Steinbrink <B.Steinbrink@gmx.de> | 74 | Björn Steinbrink <B.Steinbrink@gmx.de> |
| 68 | Björn Töpel <bjorn@kernel.org> <bjorn.topel@gmail.com> | 75 | Björn Töpel <bjorn@kernel.org> <bjorn.topel@gmail.com> |
| 69 | Björn Töpel <bjorn@kernel.org> <bjorn.topel@intel.com> | 76 | Björn Töpel <bjorn@kernel.org> <bjorn.topel@intel.com> |
| @@ -71,6 +78,7 @@ Boris Brezillon <bbrezillon@kernel.org> <b.brezillon.dev@gmail.com> · 1 unmodified line | |||
| 71 | Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com> | 78 | Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com> |
| 72 | Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> | 79 | Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> |
| 73 | Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> | 80 | Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> |
| 81 | Brendan Higgins <brendan.higgins@linux.dev> <brendanhiggins@google.com> | ||
| 74 | Brian Avery <b.avery@hp.com> | 82 | Brian Avery <b.avery@hp.com> |
| 75 | Brian King <brking@us.ibm.com> | 83 | Brian King <brking@us.ibm.com> |
| 76 | Brian Silverman <bsilver16384@gmail.com> <brian.silverman@bluerivertech.com> | 84 | Brian Silverman <bsilver16384@gmail.com> <brian.silverman@bluerivertech.com> |
| @@ -90,8 +98,7 @@ Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com> · 13 unmodified lines | |||
| 90 | Christian Marangi <ansuelsmth@gmail.com> | 98 | Christian Marangi <ansuelsmth@gmail.com> |
| 91 | Christophe Ricard <christophe.ricard@gmail.com> | 99 | Christophe Ricard <christophe.ricard@gmail.com> |
| 92 | Christoph Hellwig <hch@lst.de> | 100 | Christoph Hellwig <hch@lst.de> |
| 93 | Colin Ian King <colin.king@intel.com> <colin.king@canonical.com> | 101 | Colin Ian King <colin.i.king@gmail.com> <colin.king@canonical.com> |
| 94 | Colin Ian King <colin.king@intel.com> <colin.i.king@gmail.com> | ||
| 95 | Corey Minyard <minyard@acm.org> | 102 | Corey Minyard <minyard@acm.org> |
| 96 | Damian Hobson-Garcia <dhobsong@igel.co.jp> | 103 | Damian Hobson-Garcia <dhobsong@igel.co.jp> |
| 97 | Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com> | 104 | Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com> |
| @@ -132,6 +139,8 @@ Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com> · 34 unmodified lines | |||
| 132 | Frank Zago <fzago@systemfabricworks.com> | 139 | Frank Zago <fzago@systemfabricworks.com> |
| 133 | Gao Xiang <xiang@kernel.org> <gaoxiang25@huawei.com> | 140 | Gao Xiang <xiang@kernel.org> <gaoxiang25@huawei.com> |
| 134 | Gao Xiang <xiang@kernel.org> <hsiangkao@aol.com> | 141 | Gao Xiang <xiang@kernel.org> <hsiangkao@aol.com> |
| 142 | Gao Xiang <xiang@kernel.org> <hsiangkao@linux.alibaba.com> | ||
| 143 | Gao Xiang <xiang@kernel.org> <hsiangkao@redhat.com> | ||
| 135 | Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@de.ibm.com> | 144 | Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@de.ibm.com> |
| 136 | Gerald Schaefer <gerald.schaefer@linux.ibm.com> <gerald.schaefer@de.ibm.com> | 145 | Gerald Schaefer <gerald.schaefer@linux.ibm.com> <gerald.schaefer@de.ibm.com> |
| 137 | Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@linux.vnet.ibm.com> | 146 | Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@linux.vnet.ibm.com> |
| @@ -140,6 +149,8 @@ Greg Kroah-Hartman <gregkh@suse.de> · 2 unmodified lines | |||
| 140 | Greg Kroah-Hartman <greg@kroah.com> | 149 | Greg Kroah-Hartman <greg@kroah.com> |
| 141 | Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> | 150 | Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> |
| 142 | Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com> | 151 | Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com> |
| 152 | Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@linux.vnet.ibm.com> | ||
| 153 | Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@canonical.com> | ||
| 143 | Guo Ren <guoren@kernel.org> <guoren@linux.alibaba.com> | 154 | Guo Ren <guoren@kernel.org> <guoren@linux.alibaba.com> |
| 144 | Guo Ren <guoren@kernel.org> <ren_guo@c-sky.com> | 155 | Guo Ren <guoren@kernel.org> <ren_guo@c-sky.com> |
| 145 | Gustavo Padovan <gustavo@las.ic.unicamp.br> | 156 | Gustavo Padovan <gustavo@las.ic.unicamp.br> |
| @@ -221,7 +232,7 @@ Kees Cook <keescook@chromium.org> <kees@ubuntu.com> · 75 unmodified lines | |||
| 221 | Keith Busch <kbusch@kernel.org> <keith.busch@intel.com> | 232 | Keith Busch <kbusch@kernel.org> <keith.busch@intel.com> |
| 222 | Keith Busch <kbusch@kernel.org> <keith.busch@linux.intel.com> | 233 | Keith Busch <kbusch@kernel.org> <keith.busch@linux.intel.com> |
| 223 | Kenneth W Chen <kenneth.w.chen@intel.com> | 234 | Kenneth W Chen <kenneth.w.chen@intel.com> |
| 224 | Kirill Tkhai <kirill.tkhai@openvz.org> <ktkhai@virtuozzo.com> | 235 | Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com> |
| 225 | Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru> | 236 | Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru> |
| 226 | Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> | 237 | Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> |
| 227 | Koushik <raghavendra.koushik@neterion.com> | 238 | Koushik <raghavendra.koushik@neterion.com> |
| @@ -243,6 +254,7 @@ Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de> · 15 unmodified lines | |||
| 243 | Li Yang <leoyang.li@nxp.com> <leoli@freescale.com> | 254 | Li Yang <leoyang.li@nxp.com> <leoli@freescale.com> |
| 244 | Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org> | 255 | Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org> |
| 245 | Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com> | 256 | Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com> |
| 257 | Luca Ceresoli <luca.ceresoli@bootlin.com> <luca@lucaceresoli.net> | ||
| 246 | Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com> | 258 | Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com> |
| 247 | Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com> | 259 | Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com> |
| 248 | Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org> | 260 | Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org> |
| @@ -303,6 +315,7 @@ Morten Welinder <welinder@troll.com> · 54 unmodified lines | |||
| 303 | Mythri P K <mythripk@ti.com> | 315 | Mythri P K <mythripk@ti.com> |
| 304 | Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com> | 316 | Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com> |
| 305 | Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com> | 317 | Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com> |
| 318 | Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com> | ||
| 306 | Nguyen Anh Quynh <aquynh@gmail.com> | 319 | Nguyen Anh Quynh <aquynh@gmail.com> |
| 307 | Nicholas Piggin <npiggin@gmail.com> <npiggen@suse.de> | 320 | Nicholas Piggin <npiggin@gmail.com> <npiggen@suse.de> |
| 308 | Nicholas Piggin <npiggin@gmail.com> <npiggin@kernel.dk> | 321 | Nicholas Piggin <npiggin@gmail.com> <npiggin@kernel.dk> |
| @@ -368,6 +381,7 @@ Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk> · 59 unmodified lines | |||
| 368 | Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk> | 381 | Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk> |
| 369 | Sebastian Reichel <sre@kernel.org> <sre@debian.org> | 382 | Sebastian Reichel <sre@kernel.org> <sre@debian.org> |
| 370 | Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de> | 383 | Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de> |
| 384 | Seth Forshee <sforshee@kernel.org> <seth.forshee@canonical.com> | ||
| 371 | Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com> | 385 | Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com> |
| 372 | Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com> | 386 | Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com> |
| 373 | Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com> | 387 | Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com> |
| @@ -627,6 +627,10 @@ S: 48287 Sawleaf · 626 unmodified lines | |||
| 627 | S: Fremont, California 94539 | 627 | S: Fremont, California 94539 |
| 628 | S: USA | 628 | S: USA |
| 629 | 629 | ||
| 630 | N: Tomas Cech | ||
| 631 | E: sleep_walker@suse.com | ||
| 632 | D: arm/palm treo support | ||
| 633 | |||
| 630 | N: Florent Chabaud | 634 | N: Florent Chabaud |
| 631 | E: florent.chabaud@polytechnique.org | 635 | E: florent.chabaud@polytechnique.org |
| 632 | D: software suspend | 636 | D: software suspend |
| @@ -3491,6 +3495,10 @@ D: wd33c93 SCSI driver (linux-m68k) · 2858 unmodified lines | |||
| 3491 | S: San Jose, California | 3495 | S: San Jose, California |
| 3492 | S: USA | 3496 | S: USA |
| 3493 | 3497 | ||
| 3498 | N: Joonyoung Shim | ||
| 3499 | E: y0922.shim@samsung.com | ||
| 3500 | D: Samsung Exynos DRM drivers | ||
| 3501 | |||
| 3494 | N: Robert Siemer | 3502 | N: Robert Siemer |
| 3495 | E: Robert.Siemer@gmx.de | 3503 | E: Robert.Siemer@gmx.de |
| 3496 | P: 2048/C99A4289 2F DC 17 2E 56 62 01 C8 3D F2 AC 09 F2 E5 DD EE | 3504 | P: 2048/C99A4289 2F DC 17 2E 56 62 01 C8 3D F2 AC 09 F2 E5 DD EE |
| @@ -260,6 +260,15 @@ Description: · 259 unmodified lines | |||
| 260 | for discards, and don't read this file. | 260 | for discards, and don't read this file. |
| 261 | 261 | ||
| 262 | 262 | ||
| 263 | What: /sys/block/<disk>/queue/dma_alignment | ||
| 264 | Date: May 2022 | ||
| 265 | Contact: linux-block@vger.kernel.org | ||
| 266 | Description: | ||
| 267 | Reports the alignment that user space addresses must have to be | ||
| 268 | used for raw block device access with O_DIRECT and other driver | ||
| 269 | specific passthrough mechanisms. | ||
| 270 | |||
| 271 | |||
| 263 | What: /sys/block/<disk>/queue/fua | 272 | What: /sys/block/<disk>/queue/fua |
| 264 | Date: May 2018 | 273 | Date: May 2018 |
| 265 | Contact: linux-block@vger.kernel.org | 274 | Contact: linux-block@vger.kernel.org |
| @@ -1,7 +1,7 @@ | |||
| 1 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health | 1 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health |
| 2 | Date: June 2018 | 2 | Date: June 2018 |
| 3 | KernelVersion: 4.19 | 3 | KernelVersion: 4.19 |
| 4 | Contact: Vadim Pasternak <vadimpmellanox.com> | 4 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 5 | Description: This file shows ASIC health status. The possible values are: | 5 | Description: This file shows ASIC health status. The possible values are: |
| 6 | 0 - health failed, 2 - health OK, 3 - ASIC in booting state. | 6 | 0 - health failed, 2 - health OK, 3 - ASIC in booting state. |
| 7 | 7 | ||
| @@ -11,7 +11,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version · 3 unmodified lines | |||
| 11 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version | 11 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version |
| 12 | Date: June 2018 | 12 | Date: June 2018 |
| 13 | KernelVersion: 4.19 | 13 | KernelVersion: 4.19 |
| 14 | Contact: Vadim Pasternak <vadimpmellanox.com> | 14 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 15 | Description: These files show with which CPLD versions have been burned | 15 | Description: These files show with which CPLD versions have been burned |
| 16 | on carrier and switch boards. | 16 | on carrier and switch boards. |
| 17 | 17 | ||
| @@ -20,7 +20,7 @@ Description: These files show with which CPLD versions have been burned · 2 unmodified lines | |||
| 20 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir | 20 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir |
| 21 | Date: December 2018 | 21 | Date: December 2018 |
| 22 | KernelVersion: 5.0 | 22 | KernelVersion: 5.0 |
| 23 | Contact: Vadim Pasternak <vadimpmellanox.com> | 23 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 24 | Description: This file shows the system fans direction: | 24 | Description: This file shows the system fans direction: |
| 25 | forward direction - relevant bit is set 0; | 25 | forward direction - relevant bit is set 0; |
| 26 | reversed direction - relevant bit is set 1. | 26 | reversed direction - relevant bit is set 1. |
| @@ -30,7 +30,7 @@ Description: This file shows the system fans direction: · 3 unmodified lines | |||
| 30 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version | 30 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version |
| 31 | Date: November 2018 | 31 | Date: November 2018 |
| 32 | KernelVersion: 5.0 | 32 | KernelVersion: 5.0 |
| 33 | Contact: Vadim Pasternak <vadimpmellanox.com> | 33 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 34 | Description: These files show with which CPLD versions have been burned | 34 | Description: These files show with which CPLD versions have been burned |
| 35 | on LED or Gearbox board. | 35 | on LED or Gearbox board. |
| 36 | 36 | ||
| @@ -39,7 +39,7 @@ Description: These files show with which CPLD versions have been burned · 2 unmodified lines | |||
| 39 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable | 39 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable |
| 40 | Date: November 2018 | 40 | Date: November 2018 |
| 41 | KernelVersion: 5.0 | 41 | KernelVersion: 5.0 |
| 42 | Contact: Vadim Pasternak <vadimpmellanox.com> | 42 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 43 | Description: These files enable and disable the access to the JTAG domain. | 43 | Description: These files enable and disable the access to the JTAG domain. |
| 44 | By default access to the JTAG domain is disabled. | 44 | By default access to the JTAG domain is disabled. |
| 45 | 45 | ||
| @@ -48,7 +48,7 @@ Description: These files enable and disable the access to the JTAG domain. · 2 unmodified lines | |||
| 48 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/select_iio | 48 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/select_iio |
| 49 | Date: June 2018 | 49 | Date: June 2018 |
| 50 | KernelVersion: 4.19 | 50 | KernelVersion: 4.19 |
| 51 | Contact: Vadim Pasternak <vadimpmellanox.com> | 51 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 52 | Description: This file allows iio devices selection. | 52 | Description: This file allows iio devices selection. |
| 53 | 53 | ||
| 54 | Attribute select_iio can be written with 0 or with 1. It | 54 | Attribute select_iio can be written with 0 or with 1. It |
| @@ -62,7 +62,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu1_on · 7 unmodified lines | |||
| 62 | /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_down | 62 | /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_down |
| 63 | Date: June 2018 | 63 | Date: June 2018 |
| 64 | KernelVersion: 4.19 | 64 | KernelVersion: 4.19 |
| 65 | Contact: Vadim Pasternak <vadimpmellanox.com> | 65 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 66 | Description: These files allow asserting system power cycling, switching | 66 | Description: These files allow asserting system power cycling, switching |
| 67 | power supply units on and off and system's main power domain | 67 | power supply units on and off and system's main power domain |
| 68 | shutdown. | 68 | shutdown. |
| @@ -89,7 +89,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_short_pb · 20 unmodified lines | |||
| 89 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_reset | 89 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_reset |
| 90 | Date: June 2018 | 90 | Date: June 2018 |
| 91 | KernelVersion: 4.19 | 91 | KernelVersion: 4.19 |
| 92 | Contact: Vadim Pasternak <vadimpmellanox.com> | 92 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 93 | Description: These files show the system reset cause, as following: power | 93 | Description: These files show the system reset cause, as following: power |
| 94 | auxiliary outage or power refresh, ASIC thermal shutdown, halt, | 94 | auxiliary outage or power refresh, ASIC thermal shutdown, halt, |
| 95 | hotswap, watchdog, firmware reset, long press power button, | 95 | hotswap, watchdog, firmware reset, long press power button, |
| @@ -106,7 +106,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_system · 10 unmodified lines | |||
| 106 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_voltmon_upgrade_fail | 106 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_voltmon_upgrade_fail |
| 107 | Date: November 2018 | 107 | Date: November 2018 |
| 108 | KernelVersion: 5.0 | 108 | KernelVersion: 5.0 |
| 109 | Contact: Vadim Pasternak <vadimpmellanox.com> | 109 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 110 | Description: These files show the system reset cause, as following: ComEx | 110 | Description: These files show the system reset cause, as following: ComEx |
| 111 | power fail, reset from ComEx, system platform reset, reset | 111 | power fail, reset from ComEx, system platform reset, reset |
| 112 | due to voltage monitor devices upgrade failure, | 112 | due to voltage monitor devices upgrade failure, |
| @@ -119,7 +119,7 @@ Description: These files show the system reset cause, as following: ComEx · 6 unmodified lines | |||
| 119 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version | 119 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version |
| 120 | Date: November 2018 | 120 | Date: November 2018 |
| 121 | KernelVersion: 5.0 | 121 | KernelVersion: 5.0 |
| 122 | Contact: Vadim Pasternak <vadimpmellanox.com> | 122 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 123 | Description: These files show with which CPLD versions have been burned | 123 | Description: These files show with which CPLD versions have been burned |
| 124 | on LED board. | 124 | on LED board. |
| 125 | 125 | ||
| @@ -133,7 +133,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sff_wd · 7 unmodified lines | |||
| 133 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_wd | 133 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_wd |
| 134 | Date: June 2019 | 134 | Date: June 2019 |
| 135 | KernelVersion: 5.3 | 135 | KernelVersion: 5.3 |
| 136 | Contact: Vadim Pasternak <vadimpmellanox.com> | 136 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 137 | Description: These files show the system reset cause, as following: | 137 | Description: These files show the system reset cause, as following: |
| 138 | COMEX thermal shutdown; wathchdog power off or reset was derived | 138 | COMEX thermal shutdown; wathchdog power off or reset was derived |
| 139 | by one of the next components: COMEX, switch board or by Small Form | 139 | by one of the next components: COMEX, switch board or by Small Form |
| @@ -148,7 +148,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config1 · 8 unmodified lines | |||
| 148 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config2 | 148 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config2 |
| 149 | Date: January 2020 | 149 | Date: January 2020 |
| 150 | KernelVersion: 5.6 | 150 | KernelVersion: 5.6 |
| 151 | Contact: Vadim Pasternak <vadimpmellanox.com> | 151 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 152 | Description: These files show system static topology identification | 152 | Description: These files show system static topology identification |
| 153 | like system's static I2C topology, number and type of FPGA | 153 | like system's static I2C topology, number and type of FPGA |
| 154 | devices within the system and so on. | 154 | devices within the system and so on. |
| @@ -161,7 +161,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_soc · 6 unmodified lines | |||
| 161 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_pwr_off | 161 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_pwr_off |
| 162 | Date: January 2020 | 162 | Date: January 2020 |
| 163 | KernelVersion: 5.6 | 163 | KernelVersion: 5.6 |
| 164 | Contact: Vadim Pasternak <vadimpmellanox.com> | 164 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 165 | Description: These files show the system reset causes, as following: reset | 165 | Description: These files show the system reset causes, as following: reset |
| 166 | due to AC power failure, reset invoked from software by | 166 | due to AC power failure, reset invoked from software by |
| 167 | assertion reset signal through CPLD. reset caused by signal | 167 | assertion reset signal through CPLD. reset caused by signal |
| @@ -173,7 +173,7 @@ Description: These files show the system reset causes, as following: reset · 5 unmodified lines | |||
| 173 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pcie_asic_reset_dis | 173 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pcie_asic_reset_dis |
| 174 | Date: January 2020 | 174 | Date: January 2020 |
| 175 | KernelVersion: 5.6 | 175 | KernelVersion: 5.6 |
| 176 | Contact: Vadim Pasternak <vadimpmellanox.com> | 176 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 177 | Description: This file allows to retain ASIC up during PCIe root complex | 177 | Description: This file allows to retain ASIC up during PCIe root complex |
| 178 | reset, when attribute is set 1. | 178 | reset, when attribute is set 1. |
| 179 | 179 | ||
| @@ -182,7 +182,7 @@ Description: This file allows to retain ASIC up during PCIe root complex · 2 unmodified lines | |||
| 182 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/vpd_wp | 182 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/vpd_wp |
| 183 | Date: January 2020 | 183 | Date: January 2020 |
| 184 | KernelVersion: 5.6 | 184 | KernelVersion: 5.6 |
| 185 | Contact: Vadim Pasternak <vadimpmellanox.com> | 185 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 186 | Description: This file allows to overwrite system VPD hardware write | 186 | Description: This file allows to overwrite system VPD hardware write |
| 187 | protection when attribute is set 1. | 187 | protection when attribute is set 1. |
| 188 | 188 | ||
| @@ -191,7 +191,7 @@ Description: This file allows to overwrite system VPD hardware write · 2 unmodified lines | |||
| 191 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/voltreg_update_status | 191 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/voltreg_update_status |
| 192 | Date: January 2020 | 192 | Date: January 2020 |
| 193 | KernelVersion: 5.6 | 193 | KernelVersion: 5.6 |
| 194 | Contact: Vadim Pasternak <vadimpmellanox.com> | 194 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 195 | Description: This file exposes the configuration update status of burnable | 195 | Description: This file exposes the configuration update status of burnable |
| 196 | voltage regulator devices. The status values are as following: | 196 | voltage regulator devices. The status values are as following: |
| 197 | 0 - OK; 1 - CRC failure; 2 = I2C failure; 3 - in progress. | 197 | 0 - OK; 1 - CRC failure; 2 = I2C failure; 3 - in progress. |
| @@ -201,7 +201,7 @@ Description: This file exposes the configuration update status of burnable · 3 unmodified lines | |||
| 201 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/ufm_version | 201 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/ufm_version |
| 202 | Date: January 2020 | 202 | Date: January 2020 |
| 203 | KernelVersion: 5.6 | 203 | KernelVersion: 5.6 |
| 204 | Contact: Vadim Pasternak <vadimpmellanox.com> | 204 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 205 | Description: This file exposes the firmware version of burnable voltage | 205 | Description: This file exposes the firmware version of burnable voltage |
| 206 | regulator devices. | 206 | regulator devices. |
| 207 | 207 | ||
| @@ -217,7 +217,7 @@ What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version_min · 9 unmodified lines | |||
| 217 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version_min | 217 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version_min |
| 218 | Date: July 2020 | 218 | Date: July 2020 |
| 219 | KernelVersion: 5.9 | 219 | KernelVersion: 5.9 |
| 220 | Contact: Vadim Pasternak <vadimpmellanox.com> | 220 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 221 | Description: These files show with which CPLD part numbers and minor | 221 | Description: These files show with which CPLD part numbers and minor |
| 222 | versions have been burned CPLD devices equipped on a | 222 | versions have been burned CPLD devices equipped on a |
| 223 | system. | 223 | system. |
| @@ -471,7 +471,7 @@ Description: These files provide the maximum powered required for line card · 247 unmodified lines | |||
| 471 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/phy_reset | 471 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/phy_reset |
| 472 | Date: May 2022 | 472 | Date: May 2022 |
| 473 | KernelVersion: 5.19 | 473 | KernelVersion: 5.19 |
| 474 | Contact: Vadim Pasternak <vadimpmellanox.com> | 474 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 475 | Description: This file allows to reset PHY 88E1548 when attribute is set 0 | 475 | Description: This file allows to reset PHY 88E1548 when attribute is set 0 |
| 476 | due to some abnormal PHY behavior. | 476 | due to some abnormal PHY behavior. |
| 477 | Expected behavior: | 477 | Expected behavior: |
| @@ -483,7 +483,7 @@ Description: This file allows to reset PHY 88E1548 when attribute is set 0 · 5 unmodified lines | |||
| 483 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/mac_reset | 483 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/mac_reset |
| 484 | Date: May 2022 | 484 | Date: May 2022 |
| 485 | KernelVersion: 5.19 | 485 | KernelVersion: 5.19 |
| 486 | Contact: Vadim Pasternak <vadimpmellanox.com> | 486 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 487 | Description: This file allows to reset ASIC MT52132 when attribute is set 0 | 487 | Description: This file allows to reset ASIC MT52132 when attribute is set 0 |
| 488 | due to some abnormal ASIC behavior. | 488 | due to some abnormal ASIC behavior. |
| 489 | Expected behavior: | 489 | Expected behavior: |
| @@ -495,7 +495,7 @@ Description: This file allows to reset ASIC MT52132 when attribute is set 0 · 5 unmodified lines | |||
| 495 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/qsfp_pwr_good | 495 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/qsfp_pwr_good |
| 496 | Date: May 2022 | 496 | Date: May 2022 |
| 497 | KernelVersion: 5.19 | 497 | KernelVersion: 5.19 |
| 498 | Contact: Vadim Pasternak <vadimpmellanox.com> | 498 | Contact: Vadim Pasternak <vadimp@nvidia.com> |
| 499 | Description: This file shows QSFP ports power status. The value is set to 0 | 499 | Description: This file shows QSFP ports power status. The value is set to 0 |
| 500 | when one of any QSFP ports is plugged. The value is set to 1 when | 500 | when one of any QSFP ports is plugged. The value is set to 1 when |
| 501 | there are no any QSFP ports are plugged. | 501 | there are no any QSFP ports are plugged. |
| @@ -503,3 +503,42 @@ Description: This file shows QSFP ports power status. The value is set to 0 · 1 unmodified line | |||
| 503 | 0 - Power good, 1 - Not power good. | 503 | 0 - Power good, 1 - Not power good. |
| 504 | 504 | ||
| 505 | The files are read only. | 505 | The files are read only. |
| 506 | |||
| 507 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic2_health | ||
| 508 | Date: July 2022 | ||
| 509 | KernelVersion: 5.20 | ||
| 510 | Contact: Vadim Pasternak <vadimp@nvidia.com> | ||
| 511 | Description: This file shows 2-nd ASIC health status. The possible values are: | ||
| 512 | 0 - health failed, 2 - health OK, 3 - ASIC in booting state. | ||
| 513 | |||
| 514 | The file is read only. | ||
| 515 | |||
| 516 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_reset | ||
| 517 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic2_reset | ||
| 518 | Date: July 2022 | ||
| 519 | KernelVersion: 5.20 | ||
| 520 | Contact: Vadim Pasternak <vadimp@nvidia.com> | ||
| 521 | Description: These files allow to each of ASICs by writing 1. | ||
| 522 | |||
| 523 | The files are write only. | ||
| 524 | |||
| 525 | |||
| 526 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/comm_chnl_ready | ||
| 527 | Date: July 2022 | ||
| 528 | KernelVersion: 5.20 | ||
| 529 | Contact: Vadim Pasternak <vadimp@nvidia.com> | ||
| 530 | Description: This file is used to indicate remote end (for example BMC) that system | ||
| 531 | host CPU is ready for sending telemetry data to remote end. | ||
| 532 | For indication the file should be written 1. | ||
| 533 | |||
| 534 | The file is write only. | ||
| 535 | |||
| 536 | What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config3 | ||
| 537 | Date: January 2020 | ||
| 538 | KernelVersion: 5.6 | ||
| 539 | Contact: Vadim Pasternak <vadimp@nvidia.com> | ||
| 540 | Description: The file indicates COME module hardware configuration. | ||
| 541 | The value is pushed by hardware through GPIO pins. | ||
| 542 | The purpose is to expose some minor BOM changes for the same system SKU. | ||
| 543 | |||
| 544 | The file is read only. | ||
| @@ -38,7 +38,7 @@ What: /sys/module/<MODULENAME>/srcversion · 37 unmodified lines | |||
| 38 | Date: Jun 2005 | 38 | Date: Jun 2005 |
| 39 | Description: | 39 | Description: |
| 40 | If the module source has MODULE_VERSION, this file will contain | 40 | If the module source has MODULE_VERSION, this file will contain |
| 41 | the checksum of the the source code. | 41 | the checksum of the source code. |
| 42 | 42 | ||
| 43 | What: /sys/module/<MODULENAME>/version | 43 | What: /sys/module/<MODULENAME>/version |
| 44 | Date: Jun 2005 | 44 | Date: Jun 2005 |
| @@ -19,7 +19,7 @@ KernelVersion: 3.13 · 18 unmodified lines | |||
| 19 | Description: | 19 | Description: |
| 20 | The attributes: | 20 | The attributes: |
| 21 | 21 | ||
| 22 | =========== ============================================== | 22 | ============ ============================================== |
| 23 | file The path to the backing file for the LUN. | 23 | file The path to the backing file for the LUN. |
| 24 | Required if LUN is not marked as removable. | 24 | Required if LUN is not marked as removable. |
| 25 | ro Flag specifying access to the LUN shall be | 25 | ro Flag specifying access to the LUN shall be |
| @@ -32,4 +32,10 @@ Description: · 6 unmodified lines | |||
| 32 | being a CD-ROM. | 32 | being a CD-ROM. |
| 33 | nofua Flag specifying that FUA flag | 33 | nofua Flag specifying that FUA flag |
| 34 | in SCSI WRITE(10,12) | 34 | in SCSI WRITE(10,12) |
| 35 | =========== ============================================== | 35 | forced_eject This write-only file is useful only when |
| 36 | the function is active. It causes the backing | ||
| 37 | file to be forcibly detached from the LUN, | ||
| 38 | regardless of whether the host has allowed it. | ||
| 39 | Any non-zero number of bytes written will | ||
| 40 | result in ejection. | ||
| 41 | ============ ============================================== | ||
| @@ -101,6 +101,15 @@ Description: Specify the size of the DMA transaction when using DMA to read · 100 unmodified lines | |||
| 101 | When the write is finished, the user can read the "data_dma" | 101 | When the write is finished, the user can read the "data_dma" |
| 102 | blob | 102 | blob |
| 103 | 103 | ||
| 104 | What: /sys/kernel/debug/habanalabs/hl<n>/dump_razwi_events | ||
| 105 | Date: Aug 2022 | ||
| 106 | KernelVersion: 5.20 | ||
| 107 | Contact: fkassabri@habana.ai | ||
| 108 | Description: Dumps all razwi events to dmesg if exist. | ||
| 109 | After reading the status register of an existing event | ||
| 110 | the routine will clear the status register. | ||
| 111 | Usage: cat dump_razwi_events | ||
| 112 | |||
| 104 | What: /sys/kernel/debug/habanalabs/hl<n>/dump_security_violations | 113 | What: /sys/kernel/debug/habanalabs/hl<n>/dump_security_violations |
| 105 | Date: Jan 2021 | 114 | Date: Jan 2021 |
| 106 | KernelVersion: 5.12 | 115 | KernelVersion: 5.12 |
| @@ -121,14 +130,16 @@ Date: Jan 2019 · 14 unmodified lines | |||
| 121 | KernelVersion: 5.1 | 130 | KernelVersion: 5.1 |
| 122 | Contact: ogabbay@kernel.org | 131 | Contact: ogabbay@kernel.org |
| 123 | Description: Sets I2C device address for I2C transaction that is generated | 132 | Description: Sets I2C device address for I2C transaction that is generated |
| 124 | by the device's CPU | 133 | by the device's CPU, Not available when device is loaded with secured |
| 134 | firmware | ||
| 125 | 135 | ||
| 126 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_bus | 136 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_bus |
| 127 | Date: Jan 2019 | 137 | Date: Jan 2019 |
| 128 | KernelVersion: 5.1 | 138 | KernelVersion: 5.1 |
| 129 | Contact: ogabbay@kernel.org | 139 | Contact: ogabbay@kernel.org |
| 130 | Description: Sets I2C bus address for I2C transaction that is generated by | 140 | Description: Sets I2C bus address for I2C transaction that is generated by |
| 131 | the device's CPU | 141 | the device's CPU, Not available when device is loaded with secured |
| 142 | firmware | ||
| 132 | 143 | ||
| 133 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_data | 144 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_data |
| 134 | Date: Jan 2019 | 145 | Date: Jan 2019 |
| @@ -136,39 +147,45 @@ KernelVersion: 5.1 · 1 unmodified line | |||
| 136 | Contact: ogabbay@kernel.org | 147 | Contact: ogabbay@kernel.org |
| 137 | Description: Triggers an I2C transaction that is generated by the device's | 148 | Description: Triggers an I2C transaction that is generated by the device's |
| 138 | CPU. Writing to this file generates a write transaction while | 149 | CPU. Writing to this file generates a write transaction while |
| 139 | reading from the file generates a read transaction | 150 | reading from the file generates a read transaction, Not available |
| 151 | when device is loaded with secured firmware | ||
| 140 | 152 | ||
| 141 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_len | 153 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_len |
| 142 | Date: Dec 2021 | 154 | Date: Dec 2021 |
| 143 | KernelVersion: 5.17 | 155 | KernelVersion: 5.17 |
| 144 | Contact: obitton@habana.ai | 156 | Contact: obitton@habana.ai |
| 145 | Description: Sets I2C length in bytes for I2C transaction that is generated by | 157 | Description: Sets I2C length in bytes for I2C transaction that is generated by |
| 146 | the device's CPU | 158 | the device's CPU, Not available when device is loaded with secured |
| 159 | firmware | ||
| 147 | 160 | ||
| 148 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_reg | 161 | What: /sys/kernel/debug/habanalabs/hl<n>/i2c_reg |
| 149 | Date: Jan 2019 | 162 | Date: Jan 2019 |
| 150 | KernelVersion: 5.1 | 163 | KernelVersion: 5.1 |
| 151 | Contact: ogabbay@kernel.org | 164 | Contact: ogabbay@kernel.org |
| 152 | Description: Sets I2C register id for I2C transaction that is generated by | 165 | Description: Sets I2C register id for I2C transaction that is generated by |
| 153 | the device's CPU | 166 | the device's CPU, Not available when device is loaded with secured |
| 167 | firmware | ||
| 154 | 168 | ||
| 155 | What: /sys/kernel/debug/habanalabs/hl<n>/led0 | 169 | What: /sys/kernel/debug/habanalabs/hl<n>/led0 |
| 156 | Date: Jan 2019 | 170 | Date: Jan 2019 |
| 157 | KernelVersion: 5.1 | 171 | KernelVersion: 5.1 |
| 158 | Contact: ogabbay@kernel.org | 172 | Contact: ogabbay@kernel.org |
| 159 | Description: Sets the state of the first S/W led on the device | 173 | Description: Sets the state of the first S/W led on the device, Not available |
| 174 | when device is loaded with secured firmware | ||
| 160 | 175 | ||
| 161 | What: /sys/kernel/debug/habanalabs/hl<n>/led1 | 176 | What: /sys/kernel/debug/habanalabs/hl<n>/led1 |
| 162 | Date: Jan 2019 | 177 | Date: Jan 2019 |
| 163 | KernelVersion: 5.1 | 178 | KernelVersion: 5.1 |
| 164 | Contact: ogabbay@kernel.org | 179 | Contact: ogabbay@kernel.org |
| 165 | Description: Sets the state of the second S/W led on the device | 180 | Description: Sets the state of the second S/W led on the device, Not available |
| 181 | when device is loaded with secured firmware | ||
| 166 | 182 | ||
| 167 | What: /sys/kernel/debug/habanalabs/hl<n>/led2 | 183 | What: /sys/kernel/debug/habanalabs/hl<n>/led2 |
| 168 | Date: Jan 2019 | 184 | Date: Jan 2019 |
| 169 | KernelVersion: 5.1 | 185 | KernelVersion: 5.1 |
| 170 | Contact: ogabbay@kernel.org | 186 | Contact: ogabbay@kernel.org |
| 171 | Description: Sets the state of the third S/W led on the device | 187 | Description: Sets the state of the third S/W led on the device, Not available |
| 188 | when device is loaded with secured firmware | ||
| 172 | 189 | ||
| 173 | What: /sys/kernel/debug/habanalabs/hl<n>/memory_scrub | 190 | What: /sys/kernel/debug/habanalabs/hl<n>/memory_scrub |
| 174 | Date: May 2022 | 191 | Date: May 2022 |
| @@ -182,7 +199,8 @@ Date: May 2022 · 7 unmodified lines | |||
| 182 | KernelVersion: 5.19 | 199 | KernelVersion: 5.19 |
| 183 | Contact: dhirschfeld@habana.ai | 200 | Contact: dhirschfeld@habana.ai |
| 184 | Description: The value to which the dram will be set to when the user | 201 | Description: The value to which the dram will be set to when the user |
| 185 | scrubs the dram using 'memory_scrub' debugfs file | 202 | scrubs the dram using 'memory_scrub' debugfs file and |
| 203 | the scrubbing value when using module param 'memory_scrub' | ||
| 186 | 204 | ||
| 187 | What: /sys/kernel/debug/habanalabs/hl<n>/mmu | 205 | What: /sys/kernel/debug/habanalabs/hl<n>/mmu |
| 188 | Date: Jan 2019 | 206 | Date: Jan 2019 |
| @@ -277,7 +295,7 @@ Description: Displays a list with information about the currently user · 88 unmodified lines | |||
| 277 | to DMA addresses | 295 | to DMA addresses |
| 278 | 296 | ||
| 279 | What: /sys/kernel/debug/habanalabs/hl<n>/userptr_lookup | 297 | What: /sys/kernel/debug/habanalabs/hl<n>/userptr_lookup |
| 280 | Date: Aug 2021 | 298 | Date: Oct 2021 |
| 281 | KernelVersion: 5.15 | 299 | KernelVersion: 5.15 |
| 282 | Contact: ogabbay@kernel.org | 300 | Contact: ogabbay@kernel.org |
| 283 | Description: Allows to search for specific user pointers (user virtual | 301 | Description: Allows to search for specific user pointers (user virtual |
| @@ -22,6 +22,7 @@ Description: · 21 unmodified lines | |||
| 22 | MMUPageSize: 4 kB | 22 | MMUPageSize: 4 kB |
| 23 | Rss: 884 kB | 23 | Rss: 884 kB |
| 24 | Pss: 385 kB | 24 | Pss: 385 kB |
| 25 | Pss_Dirty: 68 kB | ||
| 25 | Pss_Anon: 301 kB | 26 | Pss_Anon: 301 kB |
| 26 | Pss_File: 80 kB | 27 | Pss_File: 80 kB |
| 27 | Pss_Shmem: 4 kB | 28 | Pss_Shmem: 4 kB |
| @@ -7,6 +7,7 @@ Description: · 6 unmodified lines | |||
| 7 | all descendant memdevs for unbind. Writing '1' to this attribute | 7 | all descendant memdevs for unbind. Writing '1' to this attribute |
| 8 | flushes that work. | 8 | flushes that work. |
| 9 | 9 | ||
| 10 | |||
| 10 | What: /sys/bus/cxl/devices/memX/firmware_version | 11 | What: /sys/bus/cxl/devices/memX/firmware_version |
| 11 | Date: December, 2020 | 12 | Date: December, 2020 |
| 12 | KernelVersion: v5.12 | 13 | KernelVersion: v5.12 |
| @@ -16,6 +17,7 @@ Description: · 3 unmodified lines | |||
| 16 | Memory Device Output Payload in the CXL-2.0 | 17 | Memory Device Output Payload in the CXL-2.0 |
| 17 | specification. | 18 | specification. |
| 18 | 19 | ||
| 20 | |||
| 19 | What: /sys/bus/cxl/devices/memX/ram/size | 21 | What: /sys/bus/cxl/devices/memX/ram/size |
| 20 | Date: December, 2020 | 22 | Date: December, 2020 |
| 21 | KernelVersion: v5.12 | 23 | KernelVersion: v5.12 |
| @@ -25,6 +27,7 @@ Description: · 3 unmodified lines | |||
| 25 | identically named field in the Identify Memory Device Output | 27 | identically named field in the Identify Memory Device Output |
| 26 | Payload in the CXL-2.0 specification. | 28 | Payload in the CXL-2.0 specification. |
| 27 | 29 | ||
| 30 | |||
| 28 | What: /sys/bus/cxl/devices/memX/pmem/size | 31 | What: /sys/bus/cxl/devices/memX/pmem/size |
| 29 | Date: December, 2020 | 32 | Date: December, 2020 |
| 30 | KernelVersion: v5.12 | 33 | KernelVersion: v5.12 |
| @@ -34,6 +37,7 @@ Description: · 3 unmodified lines | |||
| 34 | identically named field in the Identify Memory Device Output | 37 | identically named field in the Identify Memory Device Output |
| 35 | Payload in the CXL-2.0 specification. | 38 | Payload in the CXL-2.0 specification. |
| 36 | 39 | ||
| 40 | |||
| 37 | What: /sys/bus/cxl/devices/memX/serial | 41 | What: /sys/bus/cxl/devices/memX/serial |
| 38 | Date: January, 2022 | 42 | Date: January, 2022 |
| 39 | KernelVersion: v5.18 | 43 | KernelVersion: v5.18 |
| @@ -43,6 +47,7 @@ Description: · 3 unmodified lines | |||
| 43 | capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 | 47 | capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 |
| 44 | Memory Device PCIe Capabilities and Extended Capabilities. | 48 | Memory Device PCIe Capabilities and Extended Capabilities. |
| 45 | 49 | ||
| 50 | |||
| 46 | What: /sys/bus/cxl/devices/memX/numa_node | 51 | What: /sys/bus/cxl/devices/memX/numa_node |
| 47 | Date: January, 2022 | 52 | Date: January, 2022 |
| 48 | KernelVersion: v5.18 | 53 | KernelVersion: v5.18 |
| @@ -52,114 +57,334 @@ Description: · 3 unmodified lines | |||
| 52 | host PCI device for this memory device, emit the CPU node | 57 | host PCI device for this memory device, emit the CPU node |
| 53 | affinity for this device. | 58 | affinity for this device. |
| 54 | 59 | ||
| 60 | |||
| 55 | What: /sys/bus/cxl/devices/*/devtype | 61 | What: /sys/bus/cxl/devices/*/devtype |
| 56 | Date: June, 2021 | 62 | Date: June, 2021 |
| 57 | KernelVersion: v5.14 | 63 | KernelVersion: v5.14 |
| 58 | Contact: linux-cxl@vger.kernel.org | 64 | Contact: linux-cxl@vger.kernel.org |
| 59 | Description: | 65 | Description: |
| 60 | CXL device objects export the devtype attribute which mirrors | 66 | (RO) CXL device objects export the devtype attribute which |
| 61 | the same value communicated in the DEVTYPE environment variable | 67 | mirrors the same value communicated in the DEVTYPE environment |
| 62 | for uevents for devices on the "cxl" bus. | 68 | variable for uevents for devices on the "cxl" bus. |
| 69 | |||
| 63 | 70 | ||
| 64 | What: /sys/bus/cxl/devices/*/modalias | 71 | What: /sys/bus/cxl/devices/*/modalias |
| 65 | Date: December, 2021 | 72 | Date: December, 2021 |
| 66 | KernelVersion: v5.18 | 73 | KernelVersion: v5.18 |
| 67 | Contact: linux-cxl@vger.kernel.org | 74 | Contact: linux-cxl@vger.kernel.org |
| 68 | Description: | 75 | Description: |
| 69 | CXL device objects export the modalias attribute which mirrors | 76 | (RO) CXL device objects export the modalias attribute which |
| 70 | the same value communicated in the MODALIAS environment variable | 77 | mirrors the same value communicated in the MODALIAS environment |
| 71 | for uevents for devices on the "cxl" bus. | 78 | variable for uevents for devices on the "cxl" bus. |
| 79 | |||
| 72 | 80 | ||
| 73 | What: /sys/bus/cxl/devices/portX/uport | 81 | What: /sys/bus/cxl/devices/portX/uport |
| 74 | Date: June, 2021 | 82 | Date: June, 2021 |
| 75 | KernelVersion: v5.14 | 83 | KernelVersion: v5.14 |
| 76 | Contact: linux-cxl@vger.kernel.org | 84 | Contact: linux-cxl@vger.kernel.org |
| 77 | Description: | 85 | Description: |
| 78 | CXL port objects are enumerated from either a platform firmware | 86 | (RO) CXL port objects are enumerated from either a platform |
| 79 | device (ACPI0017 and ACPI0016) or PCIe switch upstream port with | 87 | firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream |
| 80 | CXL component registers. The 'uport' symlink connects the CXL | 88 | port with CXL component registers. The 'uport' symlink connects |
| 81 | portX object to the device that published the CXL port | 89 | the CXL portX object to the device that published the CXL port |
| 82 | capability. | 90 | capability. |
| 83 | 91 | ||
| 92 | |||
| 84 | What: /sys/bus/cxl/devices/portX/dportY | 93 | What: /sys/bus/cxl/devices/portX/dportY |
| 85 | Date: June, 2021 | 94 | Date: June, 2021 |
| 86 | KernelVersion: v5.14 | 95 | KernelVersion: v5.14 |
| 87 | Contact: linux-cxl@vger.kernel.org | 96 | Contact: linux-cxl@vger.kernel.org |
| 88 | Description: | 97 | Description: |
| 89 | CXL port objects are enumerated from either a platform firmware | 98 | (RO) CXL port objects are enumerated from either a platform |
| 90 | device (ACPI0017 and ACPI0016) or PCIe switch upstream port with | 99 | firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream |
| 91 | CXL component registers. The 'dportY' symlink identifies one or | 100 | port with CXL component registers. The 'dportY' symlink |
| 92 | more downstream ports that the upstream port may target in its | 101 | identifies one or more downstream ports that the upstream port |
| 93 | decode of CXL memory resources. The 'Y' integer reflects the | 102 | may target in its decode of CXL memory resources. The 'Y' |
| 94 | hardware port unique-id used in the hardware decoder target | 103 | integer reflects the hardware port unique-id used in the |
| 95 | list. | 104 | hardware decoder target list. |
| 105 | |||
| 96 | 106 | ||
| 97 | What: /sys/bus/cxl/devices/decoderX.Y | 107 | What: /sys/bus/cxl/devices/decoderX.Y |
| 98 | Date: June, 2021 | 108 | Date: June, 2021 |
| 99 | KernelVersion: v5.14 | 109 | KernelVersion: v5.14 |
| 100 | Contact: linux-cxl@vger.kernel.org | 110 | Contact: linux-cxl@vger.kernel.org |
| 101 | Description: | 111 | Description: |
| 102 | CXL decoder objects are enumerated from either a platform | 112 | (RO) CXL decoder objects are enumerated from either a platform |
| 103 | firmware description, or a CXL HDM decoder register set in a | 113 | firmware description, or a CXL HDM decoder register set in a |
| 104 | PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder | 114 | PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder |
| 105 | Capability Structure). The 'X' in decoderX.Y represents the | 115 | Capability Structure). The 'X' in decoderX.Y represents the |
| 106 | cxl_port container of this decoder, and 'Y' represents the | 116 | cxl_port container of this decoder, and 'Y' represents the |
| 107 | instance id of a given decoder resource. | 117 | instance id of a given decoder resource. |
| 108 | 118 | ||
| 119 | |||
| 109 | What: /sys/bus/cxl/devices/decoderX.Y/{start,size} | 120 | What: /sys/bus/cxl/devices/decoderX.Y/{start,size} |
| 110 | Date: June, 2021 | 121 | Date: June, 2021 |
| 111 | KernelVersion: v5.14 | 122 | KernelVersion: v5.14 |
| 112 | Contact: linux-cxl@vger.kernel.org | 123 | Contact: linux-cxl@vger.kernel.org |
| 113 | Description: | 124 | Description: |
| 114 | The 'start' and 'size' attributes together convey the physical | 125 | (RO) The 'start' and 'size' attributes together convey the |
| 115 | address base and number of bytes mapped in the decoder's decode | 126 | physical address base and number of bytes mapped in the |
| 116 | window. For decoders of devtype "cxl_decoder_root" the address | 127 | decoder's decode window. For decoders of devtype |
| 117 | range is fixed. For decoders of devtype "cxl_decoder_switch" the | 128 | "cxl_decoder_root" the address range is fixed. For decoders of |
| 118 | address is bounded by the decode range of the cxl_port ancestor | 129 | devtype "cxl_decoder_switch" the address is bounded by the |
| 119 | of the decoder's cxl_port, and dynamically updates based on the | 130 | decode range of the cxl_port ancestor of the decoder's cxl_port, |
| 120 | active memory regions in that address space. | 131 | and dynamically updates based on the active memory regions in |
| 132 | that address space. | ||
| 133 | |||
| 121 | 134 | ||
| 122 | What: /sys/bus/cxl/devices/decoderX.Y/locked | 135 | What: /sys/bus/cxl/devices/decoderX.Y/locked |
| 123 | Date: June, 2021 | 136 | Date: June, 2021 |
| 124 | KernelVersion: v5.14 | 137 | KernelVersion: v5.14 |
| 125 | Contact: linux-cxl@vger.kernel.org | 138 | Contact: linux-cxl@vger.kernel.org |
| 126 | Description: | 139 | Description: |
| 127 | CXL HDM decoders have the capability to lock the configuration | 140 | (RO) CXL HDM decoders have the capability to lock the |
| 128 | until the next device reset. For decoders of devtype | 141 | configuration until the next device reset. For decoders of |
| 129 | "cxl_decoder_root" there is no standard facility to unlock them. | 142 | devtype "cxl_decoder_root" there is no standard facility to |
| 130 | For decoders of devtype "cxl_decoder_switch" a secondary bus | 143 | unlock them. For decoders of devtype "cxl_decoder_switch" a |
| 131 | reset, of the PCIe bridge that provides the bus for this | 144 | secondary bus reset, of the PCIe bridge that provides the bus |
| 132 | decoders uport, unlocks / resets the decoder. | 145 | for this decoders uport, unlocks / resets the decoder. |
| 146 | |||
| 133 | 147 | ||
| 134 | What: /sys/bus/cxl/devices/decoderX.Y/target_list | 148 | What: /sys/bus/cxl/devices/decoderX.Y/target_list |
| 135 | Date: June, 2021 | 149 | Date: June, 2021 |
| 136 | KernelVersion: v5.14 | 150 | KernelVersion: v5.14 |
| 137 | Contact: linux-cxl@vger.kernel.org | 151 | Contact: linux-cxl@vger.kernel.org |
| 138 | Description: | 152 | Description: |
| 139 | Display a comma separated list of the current decoder target | 153 | (RO) Display a comma separated list of the current decoder |
| 140 | configuration. The list is ordered by the current configured | 154 | target configuration. The list is ordered by the current |
| 141 | interleave order of the decoder's dport instances. Each entry in | 155 | configured interleave order of the decoder's dport instances. |
| 142 | the list is a dport id. | 156 | Each entry in the list is a dport id. |
| 157 | |||
| 143 | 158 | ||
| 144 | What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} | 159 | What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} |
| 145 | Date: June, 2021 | 160 | Date: June, 2021 |
| 146 | KernelVersion: v5.14 | 161 | KernelVersion: v5.14 |
| 147 | Contact: linux-cxl@vger.kernel.org | 162 | Contact: linux-cxl@vger.kernel.org |
| 148 | Description: | 163 | Description: |
| 149 | When a CXL decoder is of devtype "cxl_decoder_root", it | 164 | (RO) When a CXL decoder is of devtype "cxl_decoder_root", it |
| 150 | represents a fixed memory window identified by platform | 165 | represents a fixed memory window identified by platform |
| 151 | firmware. A fixed window may only support a subset of memory | 166 | firmware. A fixed window may only support a subset of memory |
| 152 | types. The 'cap_*' attributes indicate whether persistent | 167 | types. The 'cap_*' attributes indicate whether persistent |
| 153 | memory, volatile memory, accelerator memory, and / or expander | 168 | memory, volatile memory, accelerator memory, and / or expander |
| 154 | memory may be mapped behind this decoder's memory window. | 169 | memory may be mapped behind this decoder's memory window. |
| 155 | 170 | ||
| 171 | |||
| 156 | What: /sys/bus/cxl/devices/decoderX.Y/target_type | 172 | What: /sys/bus/cxl/devices/decoderX.Y/target_type |
| 157 | Date: June, 2021 | 173 | Date: June, 2021 |
| 158 | KernelVersion: v5.14 | 174 | KernelVersion: v5.14 |
| 159 | Contact: linux-cxl@vger.kernel.org | 175 | Contact: linux-cxl@vger.kernel.org |
| 160 | Description: | 176 | Description: |
| 161 | When a CXL decoder is of devtype "cxl_decoder_switch", it can | 177 | (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it |
| 162 | optionally decode either accelerator memory (type-2) or expander | 178 | can optionally decode either accelerator memory (type-2) or |
| 163 | memory (type-3). The 'target_type' attribute indicates the | 179 | expander memory (type-3). The 'target_type' attribute indicates |
| 164 | current setting which may dynamically change based on what | 180 | the current setting which may dynamically change based on what |
| 165 | memory regions are activated in this decode hierarchy. | 181 | memory regions are activated in this decode hierarchy. |
| 182 | |||
| 183 | |||
| 184 | What: /sys/bus/cxl/devices/endpointX/CDAT | ||
| 185 | Date: July, 2022 | ||
| 186 | KernelVersion: v5.20 | ||
| 187 | Contact: linux-cxl@vger.kernel.org | ||
| 188 | Description: | ||
| 189 | (RO) If this sysfs entry is not present no DOE mailbox was | ||
| 190 | found to support CDAT data. If it is present and the length of | ||
| 191 | the data is 0 reading the CDAT data failed. Otherwise the CDAT | ||
| 192 | data is reported. | ||
| 193 | |||
| 194 | |||
| 195 | What: /sys/bus/cxl/devices/decoderX.Y/mode | ||
| 196 | Date: May, 2022 | ||
| 197 | KernelVersion: v5.20 | ||
| 198 | Contact: linux-cxl@vger.kernel.org | ||
| 199 | Description: | ||
| 200 | (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it | ||
| 201 | translates from a host physical address range, to a device local | ||
| 202 | address range. Device-local address ranges are further split | ||
| 203 | into a 'ram' (volatile memory) range and 'pmem' (persistent | ||
| 204 | memory) range. The 'mode' attribute emits one of 'ram', 'pmem', | ||
| 205 | 'mixed', or 'none'. The 'mixed' indication is for error cases | ||
| 206 | when a decoder straddles the volatile/persistent partition | ||
| 207 | boundary, and 'none' indicates the decoder is not actively | ||
| 208 | decoding, or no DPA allocation policy has been set. | ||
| 209 | |||
| 210 | 'mode' can be written, when the decoder is in the 'disabled' | ||
| 211 | state, with either 'ram' or 'pmem' to set the boundaries for the | ||
| 212 | next allocation. | ||
| 213 | |||
| 214 | |||
| 215 | What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource | ||
| 216 | Date: May, 2022 | ||
| 217 | KernelVersion: v5.20 | ||
| 218 | Contact: linux-cxl@vger.kernel.org | ||
| 219 | Description: | ||
| 220 | (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", | ||
| 221 | and its 'dpa_size' attribute is non-zero, this attribute | ||
| 222 | indicates the device physical address (DPA) base address of the | ||
| 223 | allocation. | ||
| 224 | |||
| 225 | |||
| 226 | What: /sys/bus/cxl/devices/decoderX.Y/dpa_size | ||
| 227 | Date: May, 2022 | ||
| 228 | KernelVersion: v5.20 | ||
| 229 | Contact: linux-cxl@vger.kernel.org | ||
| 230 | Description: | ||
| 231 | (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it | ||
| 232 | translates from a host physical address range, to a device local | ||
| 233 | address range. The range, base address plus length in bytes, of | ||
| 234 | DPA allocated to this decoder is conveyed in these 2 attributes. | ||
| 235 | Allocations can be mutated as long as the decoder is in the | ||
| 236 | disabled state. A write to 'dpa_size' releases the previous DPA | ||
| 237 | allocation and then attempts to allocate from the free capacity | ||
| 238 | in the device partition referred to by 'decoderX.Y/mode'. | ||
| 239 | Allocate and free requests can only be performed on the highest | ||
| 240 | instance number disabled decoder with non-zero size. I.e. | ||
| 241 | allocations are enforced to occur in increasing 'decoderX.Y/id' | ||
| 242 | order and frees are enforced to occur in decreasing | ||
| 243 | 'decoderX.Y/id' order. | ||
| 244 | |||
| 245 | |||
| 246 | What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways | ||
| 247 | Date: May, 2022 | ||
| 248 | KernelVersion: v5.20 | ||
| 249 | Contact: linux-cxl@vger.kernel.org | ||
| 250 | Description: | ||
| 251 | (RO) The number of targets across which this decoder's host | ||
| 252 | physical address (HPA) memory range is interleaved. The device | ||
| 253 | maps every Nth block of HPA (of size == | ||
| 254 | 'interleave_granularity') to consecutive DPA addresses. The | ||
| 255 | decoder's position in the interleave is determined by the | ||
| 256 | device's (endpoint or switch) switch ancestry. For root | ||
| 257 | decoders their interleave is specified by platform firmware and | ||
| 258 | they only specify a downstream target order for host bridges. | ||
| 259 | |||
| 260 | |||
| 261 | What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity | ||
| 262 | Date: May, 2022 | ||
| 263 | KernelVersion: v5.20 | ||
| 264 | Contact: linux-cxl@vger.kernel.org | ||
| 265 | Description: | ||
| 266 | (RO) The number of consecutive bytes of host physical address | ||
| 267 | space this decoder claims at address N before the decode rotates | ||
| 268 | to the next target in the interleave at address N + | ||
| 269 | interleave_granularity (assuming N is aligned to | ||
| 270 | interleave_granularity). | ||
| 271 | |||
| 272 | |||
| 273 | What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region | ||
| 274 | Date: May, 2022 | ||
| 275 | KernelVersion: v5.20 | ||
| 276 | Contact: linux-cxl@vger.kernel.org | ||
| 277 | Description: | ||
| 278 | (RW) Write a string in the form 'regionZ' to start the process | ||
| 279 | of defining a new persistent memory region (interleave-set) | ||
| 280 | within the decode range bounded by root decoder 'decoderX.Y'. | ||
| 281 | The value written must match the current value returned from | ||
| 282 | reading this attribute. An atomic compare exchange operation is | ||
| 283 | done on write to assign the requested id to a region and | ||
| 284 | allocate the region-id for the next creation attempt. EBUSY is | ||
| 285 | returned if the region name written does not match the current | ||
| 286 | cached value. | ||
| 287 | |||
| 288 | |||
| 289 | What: /sys/bus/cxl/devices/decoderX.Y/delete_region | ||
| 290 | Date: May, 2022 | ||
| 291 | KernelVersion: v5.20 | ||
| 292 | Contact: linux-cxl@vger.kernel.org | ||
| 293 | Description: | ||
| 294 | (WO) Write a string in the form 'regionZ' to delete that region, | ||
| 295 | provided it is currently idle / not bound to a driver. | ||
| 296 | |||
| 297 | |||
| 298 | What: /sys/bus/cxl/devices/regionZ/uuid | ||
| 299 | Date: May, 2022 | ||
| 300 | KernelVersion: v5.20 | ||
| 301 | Contact: linux-cxl@vger.kernel.org | ||
| 302 | Description: | ||
| 303 | (RW) Write a unique identifier for the region. This field must | ||
| 304 | be set for persistent regions and it must not conflict with the | ||
| 305 | UUID of another region. | ||
| 306 | |||
| 307 | |||
| 308 | What: /sys/bus/cxl/devices/regionZ/interleave_granularity | ||
| 309 | Date: May, 2022 | ||
| 310 | KernelVersion: v5.20 | ||
| 311 | Contact: linux-cxl@vger.kernel.org | ||
| 312 | Description: | ||
| 313 | (RW) Set the number of consecutive bytes each device in the | ||
| 314 | interleave set will claim. The possible interleave granularity | ||
| 315 | values are determined by the CXL spec and the participating | ||
| 316 | devices. | ||
| 317 | |||
| 318 | |||
| 319 | What: /sys/bus/cxl/devices/regionZ/interleave_ways | ||
| 320 | Date: May, 2022 | ||
| 321 | KernelVersion: v5.20 | ||
| 322 | Contact: linux-cxl@vger.kernel.org | ||
| 323 | Description: | ||
| 324 | (RW) Configures the number of devices participating in the | ||
| 325 | region is set by writing this value. Each device will provide | ||
| 326 | 1/interleave_ways of storage for the region. | ||
| 327 | |||
| 328 | |||
| 329 | What: /sys/bus/cxl/devices/regionZ/size | ||
| 330 | Date: May, 2022 | ||
| 331 | KernelVersion: v5.20 | ||
| 332 | Contact: linux-cxl@vger.kernel.org | ||
| 333 | Description: | ||
| 334 | (RW) System physical address space to be consumed by the region. | ||
| 335 | When written trigger the driver to allocate space out of the | ||
| 336 | parent root decoder's address space. When read the size of the | ||
| 337 | address space is reported and should match the span of the | ||
| 338 | region's resource attribute. Size shall be set after the | ||
| 339 | interleave configuration parameters. Once set it cannot be | ||
| 340 | changed, only freed by writing 0. The kernel makes no guarantees | ||
| 341 | that data is maintained over an address space freeing event, and | ||
| 342 | there is no guarantee that a free followed by an allocate | ||
| 343 | results in the same address being allocated. | ||
| 344 | |||
| 345 | |||
| 346 | What: /sys/bus/cxl/devices/regionZ/resource | ||
| 347 | Date: May, 2022 | ||
| 348 | KernelVersion: v5.20 | ||
| 349 | Contact: linux-cxl@vger.kernel.org | ||
| 350 | Description: | ||
| 351 | (RO) A region is a contiguous partition of a CXL root decoder | ||
| 352 | address space. Region capacity is allocated by writing to the | ||
| 353 | size attribute, the resulting physical address space determined | ||
| 354 | by the driver is reflected here. It is therefore not useful to | ||
| 355 | read this before writing a value to the size attribute. | ||
| 356 | |||
| 357 | |||
| 358 | What: /sys/bus/cxl/devices/regionZ/target[0..N] | ||
| 359 | Date: May, 2022 | ||
| 360 | KernelVersion: v5.20 | ||
| 361 | Contact: linux-cxl@vger.kernel.org | ||
| 362 | Description: | ||
| 363 | (RW) Write an endpoint decoder object name to 'targetX' where X | ||
| 364 | is the intended position of the endpoint device in the region | ||
| 365 | interleave and N is the 'interleave_ways' setting for the | ||
| 366 | region. ENXIO is returned if the write results in an impossible | ||
| 367 | to map decode scenario, like the endpoint is unreachable at that | ||
| 368 | position relative to the root decoder interleave. EBUSY is | ||
| 369 | returned if the position in the region is already occupied, or | ||
| 370 | if the region is not in a state to accept interleave | ||
| 371 | configuration changes. EINVAL is returned if the object name is | ||
| 372 | not an endpoint decoder. Once all positions have been | ||
| 373 | successfully written a final validation for decode conflicts is | ||
| 374 | performed before activating the region. | ||
| 375 | |||
| 376 | |||
| 377 | What: /sys/bus/cxl/devices/regionZ/commit | ||
| 378 | Date: May, 2022 | ||
| 379 | KernelVersion: v5.20 | ||
| 380 | Contact: linux-cxl@vger.kernel.org | ||
| 381 | Description: | ||
| 382 | (RW) Write a boolean 'true' string value to this attribute to | ||
| 383 | trigger the region to transition from the software programmed | ||
| 384 | state to the actively decoding in hardware state. The commit | ||
| 385 | operation in addition to validating that the region is in proper | ||
| 386 | configured state, validates that the decoders are being | ||
| 387 | committed in spec mandated order (last committed decoder id + | ||
| 388 | 1), and checks that the hardware accepts the commit request. | ||
| 389 | Reading this value indicates whether the region is committed or | ||
| 390 | not. | ||
| @@ -0,0 +1,18 @@ | |||
| 1 | What: /sys/bus/event_source/devices/<dev>/caps | ||
| 2 | Date: May 2022 | ||
| 3 | KernelVersion: 5.19 | ||
| 4 | Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> | ||
| 5 | Description: | ||
| 6 | Attribute group to describe the capabilities exposed | ||
| 7 | for a particular pmu. Each attribute of this group can | ||
| 8 | expose information specific to a PMU, say pmu_name, so that | ||
| 9 | userspace can understand some of the feature which the | ||
| 10 | platform specific PMU supports. | ||
| 11 | |||
| 12 | One of the example available capability in supported platform | ||
| 13 | like Intel is pmu_name, which exposes underlying CPU name known | ||
| 14 | to the PMU driver. | ||
| 15 | |||
| 16 | Example output in powerpc: | ||
| 17 | grep . /sys/bus/event_source/devices/cpu/caps/* | ||
| 18 | /sys/bus/event_source/devices/cpu/caps/pmu_name:POWER9 | ||
| @@ -79,6 +79,11 @@ Description: · 78 unmodified lines | |||
| 79 | * "accel-base" | 79 | * "accel-base" |
| 80 | * "accel-display" | 80 | * "accel-display" |
| 81 | 81 | ||
| 82 | For devices where an accelerometer is housed in the swivel camera subassembly | ||
| 83 | (for AR application), the following standardized label is used: | ||
| 84 | |||
| 85 | * "accel-camera" | ||
| 86 | |||
| 82 | What: /sys/bus/iio/devices/iio:deviceX/current_timestamp_clock | 87 | What: /sys/bus/iio/devices/iio:deviceX/current_timestamp_clock |
| 83 | KernelVersion: 4.5 | 88 | KernelVersion: 4.5 |
| 84 | Contact: linux-iio@vger.kernel.org | 89 | Contact: linux-iio@vger.kernel.org |
| @@ -102,6 +107,9 @@ Description: · 17 unmodified lines | |||
| 102 | relevant directories. If it affects all of the above | 107 | relevant directories. If it affects all of the above |
| 103 | then it is to be found in the base device directory. | 108 | then it is to be found in the base device directory. |
| 104 | 109 | ||
| 110 | The stm32-timer-trigger has the additional characteristic that | ||
| 111 | a sampling_frequency of 0 is defined to stop sampling. | ||
| 112 | |||
| 105 | What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency_available | 113 | What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency_available |
| 106 | What: /sys/bus/iio/devices/iio:deviceX/in_intensity_sampling_frequency_available | 114 | What: /sys/bus/iio/devices/iio:deviceX/in_intensity_sampling_frequency_available |
| 107 | What: /sys/bus/iio/devices/iio:deviceX/in_proximity_sampling_frequency_available | 115 | What: /sys/bus/iio/devices/iio:deviceX/in_proximity_sampling_frequency_available |
| @@ -5,6 +5,7 @@ Contact: Gwendal Grignou <gwendal@chromium.org> · 4 unmodified lines | |||
| 5 | Description: | 5 | Description: |
| 6 | SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout | 6 | SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout |
| 7 | defines if the input is | 7 | defines if the input is |
| 8 | |||
| 8 | + not connected (HZ), | 9 | + not connected (HZ), |
| 9 | + grounded (GD), | 10 | + grounded (GD), |
| 10 | + connected to an antenna where it can act as a base | 11 | + connected to an antenna where it can act as a base |
| @@ -1,31 +0,0 @@ | |||
| 1 | What: /sys/bus/iio/devices/iio:deviceX/fault_oc | ||
| 2 | KernelVersion: 5.1 | ||
| 3 | Contact: linux-iio@vger.kernel.org | ||
| 4 | Description: | ||
| 5 | Open-circuit fault. The detection of open-circuit faults, | ||
| 6 | such as those caused by broken thermocouple wires. | ||
| 7 | Reading returns either '1' or '0'. | ||
| 8 | |||
| 9 | === ======================================================= | ||
| 10 | '1' An open circuit such as broken thermocouple wires | ||
| 11 | has been detected. | ||
| 12 | '0' No open circuit or broken thermocouple wires are detected | ||
| 13 | === ======================================================= | ||
| 14 | |||
| 15 | What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv | ||
| 16 | KernelVersion: 5.1 | ||
| 17 | Contact: linux-iio@vger.kernel.org | ||
| 18 | Description: | ||
| 19 | Overvoltage or Undervoltage Input Fault. The internal circuitry | ||
| 20 | is protected from excessive voltages applied to the thermocouple | ||
| 21 | cables by integrated MOSFETs at the T+ and T- inputs, and the | ||
| 22 | BIAS output. These MOSFETs turn off when the input voltage is | ||
| 23 | negative or greater than VDD. | ||
| 24 | |||
| 25 | Reading returns either '1' or '0'. | ||
| 26 | |||
| 27 | === ======================================================= | ||
| 28 | '1' The input voltage is negative or greater than VDD. | ||
| 29 | '0' The input voltage is positive and less than VDD (normal | ||
| 30 | state). | ||
| 31 | === ======================================================= | ||
| @@ -1,20 +0,0 @@ | |||
| 1 | What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv | ||
| 2 | KernelVersion: 5.11 | ||
| 3 | Contact: linux-iio@vger.kernel.org | ||
| 4 | Description: | ||
| 5 | Overvoltage or Undervoltage Input fault. The internal circuitry | ||
| 6 | is protected from excessive voltages applied to the thermocouple | ||
| 7 | cables at FORCE+, FORCE2, RTDIN+ & RTDIN-. This circuitry turn | ||
| 8 | off when the input voltage is negative or greater than VDD. | ||
| 9 | |||
| 10 | Reading returns '1' if input voltage is negative or greater | ||
| 11 | than VDD, otherwise '0'. | ||
| 12 | |||
| 13 | What: /sys/bus/iio/devices/iio:deviceX/in_filter_notch_center_frequency | ||
| 14 | KernelVersion: 5.11 | ||
| 15 | Contact: linux-iio@vger.kernel.org | ||
| 16 | Description: | ||
| 17 | Notch frequency in Hz for a noise rejection filter. Used i.e for | ||
| 18 | line noise rejection. | ||
| 19 | |||
| 20 | Valid notch filter values are 50 Hz and 60 Hz. | ||
| @@ -0,0 +1,18 @@ | |||
| 1 | What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv | ||
| 2 | KernelVersion: 5.1 | ||
| 3 | Contact: linux-iio@vger.kernel.org | ||
| 4 | Description: | ||
| 5 | Overvoltage or Undervoltage Input Fault. The internal circuitry | ||
| 6 | is protected from excessive voltages applied to the thermocouple | ||
| 7 | cables. The device can also detect if such a condition occurs. | ||
| 8 | |||
| 9 | Reading returns '1' if input voltage is negative or greater | ||
| 10 | than VDD, otherwise '0'. | ||
| 11 | |||
| 12 | What: /sys/bus/iio/devices/iio:deviceX/fault_oc | ||
| 13 | KernelVersion: 5.1 | ||
| 14 | Contact: linux-iio@vger.kernel.org | ||
| 15 | Description: | ||
| 16 | Open-circuit fault. The detection of open-circuit faults, | ||
| 17 | such as those caused by broken thermocouple wires. | ||
| 18 | Reading returns '1' if fault, '0' otherwise. | ||
| @@ -90,14 +90,6 @@ Description: · 89 unmodified lines | |||
| 90 | Reading returns the current master modes. | 90 | Reading returns the current master modes. |
| 91 | Writing set the master mode | 91 | Writing set the master mode |
| 92 | 92 | ||
| 93 | What: /sys/bus/iio/devices/triggerX/sampling_frequency | ||
| 94 | KernelVersion: 4.11 | ||
| 95 | Contact: benjamin.gaignard@st.com | ||
| 96 | Description: | ||
| 97 | Reading returns the current sampling frequency. | ||
| 98 | Writing an value different of 0 set and start sampling. | ||
| 99 | Writing 0 stop sampling. | ||
| 100 | |||
| 101 | What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset | 93 | What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset |
| 102 | KernelVersion: 4.12 | 94 | KernelVersion: 4.12 |
| 103 | Contact: benjamin.gaignard@st.com | 95 | Contact: benjamin.gaignard@st.com |
| @@ -0,0 +1,8 @@ | |||
| 1 | What: /sys/bus/platform/devices/<dev>/always_powered_in_suspend | ||
| 2 | Date: June 2022 | ||
| 3 | KernelVersion: 5.20 | ||
| 4 | Contact: Matthias Kaehlcke <matthias@kaehlcke.net> | ||
| 5 | linux-usb@vger.kernel.org | ||
| 6 | Description: | ||
| 7 | (RW) Controls whether the USB hub remains always powered | ||
| 8 | during system suspend or not. | ||
| @@ -0,0 +1,57 @@ | |||
| 1 | What: /sys/bus/surface_aggregator/devices/01:0e:01:00:01/state | ||
| 2 | Date: July 2022 | ||
| 3 | KernelVersion: 5.20 | ||
| 4 | Contact: Maximilian Luz <luzmaximilian@gmail.com> | ||
| 5 | Description: | ||
| 6 | This attribute returns a string with the current type-cover | ||
| 7 | or device posture, as indicated by the embedded controller. | ||
| 8 | Currently returned posture states are: | ||
| 9 | |||
| 10 | - "disconnected": The type-cover has been disconnected. | ||
| 11 | |||
| 12 | - "closed": The type-cover has been folded closed and lies on | ||
| 13 | top of the display. | ||
| 14 | |||
| 15 | - "laptop": The type-cover is open and in laptop-mode, i.e., | ||
| 16 | ready for normal use. | ||
| 17 | |||
| 18 | - "folded-canvas": The type-cover has been folded back | ||
| 19 | part-ways, but does not lie flush with the back side of the | ||
| 20 | device. In general, this means that the kick-stand is used | ||
| 21 | and extended atop of the cover. | ||
| 22 | |||
| 23 | - "folded-back": The type cover has been fully folded back and | ||
| 24 | lies flush with the back side of the device. | ||
| 25 | |||
| 26 | - "<unknown>": The current state is unknown to the driver, for | ||
| 27 | example due to newer as-of-yet unsupported hardware. | ||
| 28 | |||
| 29 | New states may be introduced with new hardware. Users therefore | ||
| 30 | must not rely on this list of states being exhaustive and | ||
| 31 | gracefully handle unknown states. | ||
| 32 | |||
| 33 | What: /sys/bus/surface_aggregator/devices/01:26:01:00:01/state | ||
| 34 | Date: July 2022 | ||
| 35 | KernelVersion: 5.20 | ||
| 36 | Contact: Maximilian Luz <luzmaximilian@gmail.com> | ||
| 37 | Description: | ||
| 38 | This attribute returns a string with the current device posture, as indicated by the embedded controller. Currently | ||
| 39 | returned posture states are: | ||
| 40 | |||
| 41 | - "closed": The lid of the device is closed. | ||
| 42 | |||
| 43 | - "laptop": The lid of the device is opened and the device | ||
| 44 | operates as a normal laptop. | ||
| 45 | |||
| 46 | - "slate": The screen covers the keyboard or has been flipped | ||
| 47 | back and the device operates mainly based on touch input. | ||
| 48 | |||
| 49 | - "tablet": The device operates as tablet and exclusively | ||
| 50 | relies on touch input (or external peripherals). | ||
| 51 | |||
| 52 | - "<unknown>": The current state is unknown to the driver, for | ||
| 53 | example due to newer as-of-yet unsupported hardware. | ||
| 54 | |||
| 55 | New states may be introduced with new hardware. Users therefore | ||
| 56 | must not rely on this list of states being exhaustive and | ||
| 57 | gracefully handle unknown states. | ||
| @@ -253,6 +253,17 @@ Description: · 252 unmodified lines | |||
| 253 | only if the system firmware is capable of describing the | 253 | only if the system firmware is capable of describing the |
| 254 | connection between a port and its connector. | 254 | connection between a port and its connector. |
| 255 | 255 | ||
| 256 | What: /sys/bus/usb/devices/.../<hub_interface>/port<X>/disable | ||
| 257 | Date: June 2022 | ||
| 258 | Contact: Michael Grzeschik <m.grzeschik@pengutronix.de> | ||
| 259 | Description: | ||
| 260 | This file controls the state of a USB port, including | ||
| 261 | Vbus power output (but only on hubs that support | ||
| 262 | power switching -- most hubs don't support it). If | ||
| 263 | a port is disabled, the port is unusable: Devices | ||
| 264 | attached to the port will not be detected, initialized, | ||
| 265 | or enumerated. | ||
| 266 | |||
| 256 | What: /sys/bus/usb/devices/.../power/usb2_lpm_l1_timeout | 267 | What: /sys/bus/usb/devices/.../power/usb2_lpm_l1_timeout |
| 257 | Date: May 2013 | 268 | Date: May 2013 |
| 258 | Contact: Mathias Nyman <mathias.nyman@linux.intel.com> | 269 | Contact: Mathias Nyman <mathias.nyman@linux.intel.com> |
| @@ -938,3 +938,12 @@ Description: · 937 unmodified lines | |||
| 938 | - 1: enable | 938 | - 1: enable |
| 939 | 939 | ||
| 940 | RW | 940 | RW |
| 941 | |||
| 942 | What: /sys/class/hwmon/hwmonX/device/pec | ||
| 943 | Description: | ||
| 944 | PEC support on I2C devices | ||
| 945 | |||
| 946 | - 0, off, n: disable | ||
| 947 | - 1, on, y: enable | ||
| 948 | |||
| 949 | RW | ||
| @@ -81,7 +81,7 @@ Description: · 80 unmodified lines | |||
| 81 | What: /sys/class/pwm/pwmchip<N>/pwmX/capture | 81 | What: /sys/class/pwm/pwmchip<N>/pwmX/capture |
| 82 | Date: June 2016 | 82 | Date: June 2016 |
| 83 | KernelVersion: 4.8 | 83 | KernelVersion: 4.8 |
| 84 | Contact: Lee Jones <lee.jones@linaro.org> | 84 | Contact: Lee Jones <lee@kernel.org> |
| 85 | Description: | 85 | Description: |
| 86 | Capture information about a PWM signal. The output format is a | 86 | Capture information about a PWM signal. The output format is a |
| 87 | pair unsigned integers (period and duty cycle), separated by a | 87 | pair unsigned integers (period and duty cycle), separated by a |
| @@ -78,7 +78,7 @@ What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_name · 77 unmodified lines | |||
| 78 | Date: Feb 2020 | 78 | Date: Feb 2020 |
| 79 | KernelVersion: 5.7 | 79 | KernelVersion: 5.7 |
| 80 | Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com> | 80 | Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com> |
| 81 | Description: RO, Contains the the name of HCA the connection established on. | 81 | Description: RO, Contains the name of HCA the connection established on. |
| 82 | 82 | ||
| 83 | What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_port | 83 | What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_port |
| 84 | Date: Feb 2020 | 84 | Date: Feb 2020 |
| @@ -24,7 +24,7 @@ What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_name · 23 unmodified lines | |||
| 24 | Date: Feb 2020 | 24 | Date: Feb 2020 |
| 25 | KernelVersion: 5.7 | 25 | KernelVersion: 5.7 |
| 26 | Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com> | 26 | Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com> |
| 27 | Description: RO, Contains the the name of HCA the connection established on. | 27 | Description: RO, Contains the name of HCA the connection established on. |
| 28 | 28 | ||
| 29 | What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_port | 29 | What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_port |
| 30 | Date: Feb 2020 | 30 | Date: Feb 2020 |
| @@ -141,6 +141,14 @@ Description: · 140 unmodified lines | |||
| 141 | - "reverse": CC2 orientation | 141 | - "reverse": CC2 orientation |
| 142 | - "unknown": Orientation cannot be determined. | 142 | - "unknown": Orientation cannot be determined. |
| 143 | 143 | ||
| 144 | What: /sys/class/typec/<port>/select_usb_power_delivery | ||
| 145 | Date: May 2022 | ||
| 146 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 147 | Description: | ||
| 148 | Lists the USB Power Delivery Capabilities that the port can | ||
| 149 | advertise to the partner. The currently used capabilities are in | ||
| 150 | brackets. Selection happens by writing to the file. | ||
| 151 | |||
| 144 | USB Type-C partner devices (eg. /sys/class/typec/port0-partner/) | 152 | USB Type-C partner devices (eg. /sys/class/typec/port0-partner/) |
| 145 | 153 | ||
| 146 | What: /sys/class/typec/<port>-partner/accessory_mode | 154 | What: /sys/class/typec/<port>-partner/accessory_mode |
| @@ -0,0 +1,240 @@ | |||
| 1 | What: /sys/class/usb_power_delivery | ||
| 2 | Date: May 2022 | ||
| 3 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 4 | Description: | ||
| 5 | Directory for USB Power Delivery devices. | ||
| 6 | |||
| 7 | What: /sys/class/usb_power_delivery/.../revision | ||
| 8 | Date: May 2022 | ||
| 9 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 10 | Description: | ||
| 11 | File showing the USB Power Delivery Specification Revision used | ||
| 12 | in communication. | ||
| 13 | |||
| 14 | What: /sys/class/usb_power_delivery/.../version | ||
| 15 | Date: May 2022 | ||
| 16 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 17 | Description: | ||
| 18 | This is an optional attribute file showing the version of the | ||
| 19 | specific revision of the USB Power Delivery Specification. In | ||
| 20 | most cases the specification version is not known and the file | ||
| 21 | is not available. | ||
| 22 | |||
| 23 | What: /sys/class/usb_power_delivery/.../source-capabilities | ||
| 24 | Date: May 2022 | ||
| 25 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 26 | Description: | ||
| 27 | The source capabilities message "Source_Capabilities" contains a | ||
| 28 | set of Power Data Objects (PDO), each representing a type of | ||
| 29 | power supply. The order of the PDO objects is defined in the USB | ||
| 30 | Power Delivery Specification. Each PDO - power supply - will | ||
| 31 | have its own device, and the PDO device name will start with the | ||
| 32 | object position number as the first character followed by the | ||
| 33 | power supply type name (":" as delimiter). | ||
| 34 | |||
| 35 | /sys/class/usb_power_delivery/.../source_capabilities/<position>:<type> | ||
| 36 | |||
| 37 | What: /sys/class/usb_power_delivery/.../sink-capabilities | ||
| 38 | Date: May 2022 | ||
| 39 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 40 | Description: | ||
| 41 | The sink capability message "Sink_Capabilities" contains a set | ||
| 42 | of Power Data Objects (PDO) just like with source capabilities, | ||
| 43 | but instead of describing the power capabilities, these objects | ||
| 44 | describe the power requirements. | ||
| 45 | |||
| 46 | The order of the objects in the sink capability message is the | ||
| 47 | same as with the source capabilities message. | ||
| 48 | |||
| 49 | Fixed Supplies | ||
| 50 | |||
| 51 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:fixed_supply | ||
| 52 | Date: May 2022 | ||
| 53 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 54 | Description: | ||
| 55 | Devices containing the attributes (the bit fields) defined for | ||
| 56 | Fixed Supplies. | ||
| 57 | |||
| 58 | The device "1:fixed_supply" is special. USB Power Delivery | ||
| 59 | Specification dictates that the first PDO (at object position | ||
| 60 | 1), and the only mandatory PDO, is always the vSafe5V Fixed | ||
| 61 | Supply Object. vSafe5V Object has additional fields defined for | ||
| 62 | it that the other Fixed Supply Objects do not have and that are | ||
| 63 | related to the USB capabilities rather than power capabilities. | ||
| 64 | |||
| 65 | What: /sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/dual_role_power | ||
| 66 | Date: May 2022 | ||
| 67 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 68 | Description: | ||
| 69 | This file contains boolean value that tells does the device | ||
| 70 | support both source and sink power roles. | ||
| 71 | |||
| 72 | What: /sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/usb_suspend_supported | ||
| 73 | Date: May 2022 | ||
| 74 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 75 | Description: | ||
| 76 | This file shows the value of the USB Suspend Supported bit in | ||
| 77 | vSafe5V Fixed Supply Object. If the bit is set then the device | ||
| 78 | will follow the USB 2.0 and USB 3.2 rules for suspend and | ||
| 79 | resume. | ||
| 80 | |||
| 81 | What: /sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/unconstrained_power | ||
| 82 | Date: May 2022 | ||
| 83 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 84 | Description: | ||
| 85 | This file shows the value of the Unconstrained Power bit in | ||
| 86 | vSafe5V Fixed Supply Object. The bit is set when an external | ||
| 87 | source of power, powerful enough to power the entire system on | ||
| 88 | its own, is available for the device. | ||
| 89 | |||
| 90 | What: /sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/usb_communication_capable | ||
| 91 | Date: May 2022 | ||
| 92 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 93 | Description: | ||
| 94 | This file shows the value of the USB Communication Capable bit in | ||
| 95 | vSafe5V Fixed Supply Object. | ||
| 96 | |||
| 97 | What: /sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/dual_role_data | ||
| 98 | Date: May 2022 | ||
| 99 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 100 | Description: | ||
| 101 | This file shows the value of the Dual-Role Data bit in vSafe5V | ||
| 102 | Fixed Supply Object. Dual role data means ability act as both | ||
| 103 | USB host and USB device. | ||
| 104 | |||
| 105 | What: /sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/unchunked_extended_messages_supported | ||
| 106 | Date: May 2022 | ||
| 107 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 108 | Description: | ||
| 109 | This file shows the value of the Unchunked Extended Messages | ||
| 110 | Supported bit in vSafe5V Fixed Supply Object. | ||
| 111 | |||
| 112 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:fixed_supply/voltage | ||
| 113 | Date: May 2022 | ||
| 114 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 115 | Description: | ||
| 116 | The voltage the supply supports in millivolts. | ||
| 117 | |||
| 118 | What: /sys/class/usb_power_delivery/.../source-capabilities/<position>:fixed_supply/maximum_current | ||
| 119 | Date: May 2022 | ||
| 120 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 121 | Description: | ||
| 122 | Maximum current of the fixed source supply in milliamperes. | ||
| 123 | |||
| 124 | What: /sys/class/usb_power_delivery/.../sink-capabilities/<position>:fixed_supply/operational_current | ||
| 125 | Date: May 2022 | ||
| 126 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 127 | Description: | ||
| 128 | Operational current of the sink in milliamperes. | ||
| 129 | |||
| 130 | What: /sys/class/usb_power_delivery/.../sink-capabilities/<position>:fixed_supply/fast_role_swap_current | ||
| 131 | Date: May 2022 | ||
| 132 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 133 | Description: | ||
| 134 | This file contains the value of the "Fast Role Swap USB Type-C | ||
| 135 | Current" field that tells the current level the sink requires | ||
| 136 | after a Fast Role Swap. | ||
| 137 | 0 - Fast Swap not supported" | ||
| 138 | 1 - Default USB Power" | ||
| 139 | 2 - 1.5A@5V" | ||
| 140 | 3 - 3.0A@5V" | ||
| 141 | |||
| 142 | Variable Supplies | ||
| 143 | |||
| 144 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:variable_supply | ||
| 145 | Date: May 2022 | ||
| 146 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 147 | Description: | ||
| 148 | Variable Power Supply PDO. | ||
| 149 | |||
| 150 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:variable_supply/maximum_voltage | ||
| 151 | Date: May 2022 | ||
| 152 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 153 | Description: | ||
| 154 | Maximum Voltage in millivolts. | ||
| 155 | |||
| 156 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:variable_supply/minimum_voltage | ||
| 157 | Date: May 2022 | ||
| 158 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 159 | Description: | ||
| 160 | Minimum Voltage in millivolts. | ||
| 161 | |||
| 162 | What: /sys/class/usb_power_delivery/.../source-capabilities/<position>:variable_supply/maximum_current | ||
| 163 | Date: May 2022 | ||
| 164 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 165 | Description: | ||
| 166 | The maximum current in milliamperes that the source can supply | ||
| 167 | at the given Voltage range. | ||
| 168 | |||
| 169 | What: /sys/class/usb_power_delivery/.../sink-capabilities/<position>:variable_supply/operational_current | ||
| 170 | Date: May 2022 | ||
| 171 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 172 | Description: | ||
| 173 | The operational current in milliamperes that the sink requires | ||
| 174 | at the given Voltage range. | ||
| 175 | |||
| 176 | Battery Supplies | ||
| 177 | |||
| 178 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:battery | ||
| 179 | Date: May 2022 | ||
| 180 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 181 | Description: | ||
| 182 | Battery PDO. | ||
| 183 | |||
| 184 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:battery/maximum_voltage | ||
| 185 | Date: May 2022 | ||
| 186 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 187 | Description: | ||
| 188 | Maximum Voltage in millivolts. | ||
| 189 | |||
| 190 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:battery/minimum_voltage | ||
| 191 | Date: May 2022 | ||
| 192 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 193 | Description: | ||
| 194 | Minimum Voltage in millivolts. | ||
| 195 | |||
| 196 | What: /sys/class/usb_power_delivery/.../source-capabilities/<position>:battery/maximum_power | ||
| 197 | Date: May 2022 | ||
| 198 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 199 | Description: | ||
| 200 | Maximum allowable Power in milliwatts. | ||
| 201 | |||
| 202 | What: /sys/class/usb_power_delivery/.../sink-capabilities/<position>:battery/operational_power | ||
| 203 | Date: May 2022 | ||
| 204 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 205 | Description: | ||
| 206 | The operational power that the sink requires at the given | ||
| 207 | voltage range. | ||
| 208 | |||
| 209 | Standard Power Range (SPR) Programmable Power Supplies | ||
| 210 | |||
| 211 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply | ||
| 212 | Date: May 2022 | ||
| 213 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 214 | Description: | ||
| 215 | Programmable Power Supply (PPS) Augmented PDO (APDO). | ||
| 216 | |||
| 217 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply/maximum_voltage | ||
| 218 | Date: May 2022 | ||
| 219 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 220 | Description: | ||
| 221 | Maximum Voltage in millivolts. | ||
| 222 | |||
| 223 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply/minimum_voltage | ||
| 224 | Date: May 2022 | ||
| 225 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 226 | Description: | ||
| 227 | Minimum Voltage in millivolts. | ||
| 228 | |||
| 229 | What: /sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply/maximum_current | ||
| 230 | Date: May 2022 | ||
| 231 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 232 | Description: | ||
| 233 | Maximum Current in milliamperes. | ||
| 234 | |||
| 235 | What: /sys/class/usb_power_delivery/.../source-capabilities/<position>:programmable_supply/pps_power_limited | ||
| 236 | Date: May 2022 | ||
| 237 | Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> | ||
| 238 | Description: | ||
| 239 | The PPS Power Limited bit indicates whether or not the source | ||
| 240 | supply will exceed the rated output power if requested. | ||
| @@ -0,0 +1,33 @@ | |||
| 1 | What: /sys/class/vduse/ | ||
| 2 | Date: Oct 2021 | ||
| 3 | KernelVersion: 5.15 | ||
| 4 | Contact: Yongji Xie <xieyongji@bytedance.com> | ||
| 5 | Description: | ||
| 6 | The vduse/ class sub-directory belongs to the VDUSE | ||
| 7 | framework and provides a sysfs interface for configuring | ||
| 8 | VDUSE devices. | ||
| 9 | |||
| 10 | What: /sys/class/vduse/control/ | ||
| 11 | Date: Oct 2021 | ||
| 12 | KernelVersion: 5.15 | ||
| 13 | Contact: Yongji Xie <xieyongji@bytedance.com> | ||
| 14 | Description: | ||
| 15 | This directory entry is created for the control device | ||
| 16 | of VDUSE framework. | ||
| 17 | |||
| 18 | What: /sys/class/vduse/<device-name>/ | ||
| 19 | Date: Oct 2021 | ||
| 20 | KernelVersion: 5.15 | ||
| 21 | Contact: Yongji Xie <xieyongji@bytedance.com> | ||
| 22 | Description: | ||
| 23 | This directory entry is created when a VDUSE device is | ||
| 24 | created via the control device. | ||
| 25 | |||
| 26 | What: /sys/class/vduse/<device-name>/msg_timeout | ||
| 27 | Date: Oct 2021 | ||
| 28 | KernelVersion: 5.15 | ||
| 29 | Contact: Yongji Xie <xieyongji@bytedance.com> | ||
| 30 | Description: | ||
| 31 | (RW) The timeout (in seconds) for waiting for the control | ||
| 32 | message's response from userspace. Default value is 30s. | ||
| 33 | Writing a '0' to the file means to disable the timeout. | ||
| @@ -74,7 +74,7 @@ Description: · 73 unmodified lines | |||
| 74 | 74 | ||
| 75 | Reads also cause the AC alarm timer status to be reset. | 75 | Reads also cause the AC alarm timer status to be reset. |
| 76 | 76 | ||
| 77 | Another way to reset the the status of the AC alarm timer is to | 77 | Another way to reset the status of the AC alarm timer is to |
| 78 | write (the number) 0 to this file. | 78 | write (the number) 0 to this file. |
| 79 | 79 | ||
| 80 | If the status return value indicates that the timer has expired, | 80 | If the status return value indicates that the timer has expired, |
| @@ -46,33 +46,69 @@ Description: · 45 unmodified lines | |||
| 46 | that is supported by the hardware. The possible values | 46 | that is supported by the hardware. The possible values |
| 47 | are "MAPv4" or "MAPv5". | 47 | are "MAPv4" or "MAPv5". |
| 48 | 48 | ||
| 49 | What: .../XXXXXXX.ipa/endpoint_id/ | ||
| 50 | Date: July 2022 | ||
| 51 | KernelVersion: v5.19 | ||
| 52 | Contact: Alex Elder <elder@kernel.org> | ||
| 53 | Description: | ||
| 54 | The .../XXXXXXX.ipa/endpoint_id/ directory contains | ||
| 55 | attributes that define IDs associated with IPA | ||
| 56 | endpoints. The "rx" or "tx" in an endpoint name is | ||
| 57 | from the perspective of the AP. An endpoint ID is a | ||
| 58 | small unsigned integer. | ||
| 59 | |||
| 60 | What: .../XXXXXXX.ipa/endpoint_id/modem_rx | ||
| 61 | Date: July 2022 | ||
| 62 | KernelVersion: v5.19 | ||
| 63 | Contact: Alex Elder <elder@kernel.org> | ||
| 64 | Description: | ||
| 65 | The .../XXXXXXX.ipa/endpoint_id/modem_rx file contains | ||
| 66 | the ID of the AP endpoint on which packets originating | ||
| 67 | from the embedded modem are received. | ||
| 68 | |||
| 69 | What: .../XXXXXXX.ipa/endpoint_id/modem_tx | ||
| 70 | Date: July 2022 | ||
| 71 | KernelVersion: v5.19 | ||
| 72 | Contact: Alex Elder <elder@kernel.org> | ||
| 73 | Description: | ||
| 74 | The .../XXXXXXX.ipa/endpoint_id/modem_tx file contains | ||
| 75 | the ID of the AP endpoint on which packets destined | ||
| 76 | for the embedded modem are sent. | ||
| 77 | |||
| 78 | What: .../XXXXXXX.ipa/endpoint_id/monitor_rx | ||
| 79 | Date: July 2022 | ||
| 80 | KernelVersion: v5.19 | ||
| 81 | Contact: Alex Elder <elder@kernel.org> | ||
| 82 | Description: | ||
| 83 | The .../XXXXXXX.ipa/endpoint_id/monitor_rx file contains | ||
| 84 | the ID of the AP endpoint on which IPA "monitor" data is | ||
| 85 | received. The monitor endpoint supplies replicas of | ||
| 86 | packets that enter the IPA hardware for processing. | ||
| 87 | Each replicated packet is preceded by a fixed-size "ODL" | ||
| 88 | header (see .../XXXXXXX.ipa/feature/monitor, above). | ||
| 89 | Large packets are truncated, to reduce the bandwidth | ||
| 90 | required to provide the monitor function. | ||
| 91 | |||
| 49 | What: .../XXXXXXX.ipa/modem/ | 92 | What: .../XXXXXXX.ipa/modem/ |
| 50 | Date: June 2021 | 93 | Date: June 2021 |
| 51 | KernelVersion: v5.14 | 94 | KernelVersion: v5.14 |
| 52 | Contact: Alex Elder <elder@kernel.org> | 95 | Contact: Alex Elder <elder@kernel.org> |
| 53 | Description: | 96 | Description: |
| 54 | The .../XXXXXXX.ipa/modem/ directory contains a set of | 97 | The .../XXXXXXX.ipa/modem/ directory contains attributes |
| 55 | attributes describing properties of the modem execution | 98 | describing properties of the modem embedded in the SoC. |
| 56 | environment reachable by the IPA hardware. | ||
| 57 | 99 | ||
| 58 | What: .../XXXXXXX.ipa/modem/rx_endpoint_id | 100 | What: .../XXXXXXX.ipa/modem/rx_endpoint_id |
| 59 | Date: June 2021 | 101 | Date: June 2021 |
| 60 | KernelVersion: v5.14 | 102 | KernelVersion: v5.14 |
| 61 | Contact: Alex Elder <elder@kernel.org> | 103 | Contact: Alex Elder <elder@kernel.org> |
| 62 | Description: | 104 | Description: |
| 63 | The .../XXXXXXX.ipa/feature/rx_endpoint_id file contains | 105 | The .../XXXXXXX.ipa/modem/rx_endpoint_id file duplicates |
| 64 | the AP endpoint ID that receives packets originating from | 106 | the value found in .../XXXXXXX.ipa/endpoint_id/modem_rx. |
| 65 | the modem execution environment. The "rx" is from the | ||
| 66 | perspective of the AP; this endpoint is considered an "IPA | ||
| 67 | producer". An endpoint ID is a small unsigned integer. | ||
| 68 | 107 | ||
| 69 | What: .../XXXXXXX.ipa/modem/tx_endpoint_id | 108 | What: .../XXXXXXX.ipa/modem/tx_endpoint_id |
| 70 | Date: June 2021 | 109 | Date: June 2021 |
| 71 | KernelVersion: v5.14 | 110 | KernelVersion: v5.14 |
| 72 | Contact: Alex Elder <elder@kernel.org> | 111 | Contact: Alex Elder <elder@kernel.org> |
| 73 | Description: | 112 | Description: |
| 74 | The .../XXXXXXX.ipa/feature/tx_endpoint_id file contains | 113 | The .../XXXXXXX.ipa/modem/tx_endpoint_id file duplicates |
| 75 | the AP endpoint ID used to transmit packets destined for | 114 | the value found in .../XXXXXXX.ipa/endpoint_id/modem_tx. |
| 76 | the modem execution environment. The "tx" is from the | ||
| 77 | perspective of the AP; this endpoint is considered an "IPA | ||
| 78 | consumer". An endpoint ID is a small unsigned integer. | ||
| @@ -303,5 +303,5 @@ Date: Apr 2010 · 302 unmodified lines | |||
| 303 | Contact: Dominik Brodowski <linux@dominikbrodowski.net> | 303 | Contact: Dominik Brodowski <linux@dominikbrodowski.net> |
| 304 | Description: | 304 | Description: |
| 305 | Reports the runtime PM children usage count of a device, or | 305 | Reports the runtime PM children usage count of a device, or |
| 306 | 0 if the the children will be ignored. | 306 | 0 if the children will be ignored. |
| 307 | 307 | ||
| @@ -1,6 +1,6 @@ | |||
| 1 | What: /sys/devices/socX | 1 | What: /sys/devices/socX |
| 2 | Date: January 2012 | 2 | Date: January 2012 |
| 3 | contact: Lee Jones <lee.jones@linaro.org> | 3 | contact: Lee Jones <lee@kernel.org> |
| 4 | Description: | 4 | Description: |
| 5 | The /sys/devices/ directory contains a sub-directory for each | 5 | The /sys/devices/ directory contains a sub-directory for each |
| 6 | System-on-Chip (SoC) device on a running platform. Information | 6 | System-on-Chip (SoC) device on a running platform. Information |
| @@ -14,14 +14,14 @@ Description: · 7 unmodified lines | |||
| 14 | 14 | ||
| 15 | What: /sys/devices/socX/machine | 15 | What: /sys/devices/socX/machine |
| 16 | Date: January 2012 | 16 | Date: January 2012 |
| 17 | contact: Lee Jones <lee.jones@linaro.org> | 17 | contact: Lee Jones <lee@kernel.org> |
| 18 | Description: | 18 | Description: |
| 19 | Read-only attribute common to all SoCs. Contains the SoC machine | 19 | Read-only attribute common to all SoCs. Contains the SoC machine |
| 20 | name (e.g. Ux500). | 20 | name (e.g. Ux500). |
| 21 | 21 | ||
| 22 | What: /sys/devices/socX/family | 22 | What: /sys/devices/socX/family |
| 23 | Date: January 2012 | 23 | Date: January 2012 |
| 24 | contact: Lee Jones <lee.jones@linaro.org> | 24 | contact: Lee Jones <lee@kernel.org> |
| 25 | Description: | 25 | Description: |
| 26 | Read-only attribute common to all SoCs. Contains SoC family name | 26 | Read-only attribute common to all SoCs. Contains SoC family name |
| 27 | (e.g. DB8500). | 27 | (e.g. DB8500). |
| @@ -59,7 +59,7 @@ Description: · 31 unmodified lines | |||
| 59 | 59 | ||
| 60 | What: /sys/devices/socX/soc_id | 60 | What: /sys/devices/socX/soc_id |
| 61 | Date: January 2012 | 61 | Date: January 2012 |
| 62 | contact: Lee Jones <lee.jones@linaro.org> | 62 | contact: Lee Jones <lee@kernel.org> |
| 63 | Description: | 63 | Description: |
| 64 | Read-only attribute supported by most SoCs. In the case of | 64 | Read-only attribute supported by most SoCs. In the case of |
| 65 | ST-Ericsson's chips this contains the SoC serial number. | 65 | ST-Ericsson's chips this contains the SoC serial number. |
| @@ -72,21 +72,21 @@ Description: · 6 unmodified lines | |||
| 72 | 72 | ||
| 73 | What: /sys/devices/socX/revision | 73 | What: /sys/devices/socX/revision |
| 74 | Date: January 2012 | 74 | Date: January 2012 |
| 75 | contact: Lee Jones <lee.jones@linaro.org> | 75 | contact: Lee Jones <lee@kernel.org> |
| 76 | Description: | 76 | Description: |
| 77 | Read-only attribute supported by most SoCs. Contains the SoC's | 77 | Read-only attribute supported by most SoCs. Contains the SoC's |
| 78 | manufacturing revision number. | 78 | manufacturing revision number. |
| 79 | 79 | ||
| 80 | What: /sys/devices/socX/process | 80 | What: /sys/devices/socX/process |
| 81 | Date: January 2012 | 81 | Date: January 2012 |
| 82 | contact: Lee Jones <lee.jones@linaro.org> | 82 | contact: Lee Jones <lee@kernel.org> |
| 83 | Description: | 83 | Description: |
| 84 | Read-only attribute supported ST-Ericsson's silicon. Contains the | 84 | Read-only attribute supported ST-Ericsson's silicon. Contains the |
| 85 | the process by which the silicon chip was manufactured. | 85 | the process by which the silicon chip was manufactured. |
| 86 | 86 | ||
| 87 | What: /sys/bus/soc | 87 | What: /sys/bus/soc |
| 88 | Date: January 2012 | 88 | Date: January 2012 |
| 89 | contact: Lee Jones <lee.jones@linaro.org> | 89 | contact: Lee Jones <lee@kernel.org> |
| 90 | Description: | 90 | Description: |
| 91 | The /sys/bus/soc/ directory contains the usual sub-folders | 91 | The /sys/bus/soc/ directory contains the usual sub-folders |
| 92 | expected under most buses. /sys/bus/soc/devices is of particular | 92 | expected under most buses. /sys/bus/soc/devices is of particular |
| @@ -67,8 +67,7 @@ Description: Discover NUMA node a CPU belongs to · 66 unmodified lines | |||
| 67 | /sys/devices/system/cpu/cpu42/node2 -> ../../node/node2 | 67 | /sys/devices/system/cpu/cpu42/node2 -> ../../node/node2 |
| 68 | 68 | ||
| 69 | 69 | ||
| 70 | What: /sys/devices/system/cpu/cpuX/topology/core_id | 70 | What: /sys/devices/system/cpu/cpuX/topology/core_siblings |
| 71 | /sys/devices/system/cpu/cpuX/topology/core_siblings | ||
| 72 | /sys/devices/system/cpu/cpuX/topology/core_siblings_list | 71 | /sys/devices/system/cpu/cpuX/topology/core_siblings_list |
| 73 | /sys/devices/system/cpu/cpuX/topology/physical_package_id | 72 | /sys/devices/system/cpu/cpuX/topology/physical_package_id |
| 74 | /sys/devices/system/cpu/cpuX/topology/thread_siblings | 73 | /sys/devices/system/cpu/cpuX/topology/thread_siblings |
| @@ -84,10 +83,6 @@ Description: CPU topology files that describe a logical CPU's relationship · 9 unmodified lines | |||
| 84 | 83 | ||
| 85 | Briefly, the files above are: | 84 | Briefly, the files above are: |
| 86 | 85 | ||
| 87 | core_id: the CPU core ID of cpuX. Typically it is the | ||
| 88 | hardware platform's identifier (rather than the kernel's). | ||
| 89 | The actual value is architecture and platform dependent. | ||
| 90 | |||
| 91 | core_siblings: internal kernel map of cpuX's hardware threads | 86 | core_siblings: internal kernel map of cpuX's hardware threads |
| 92 | within the same physical_package_id. | 87 | within the same physical_package_id. |
| 93 | 88 | ||
| @@ -493,12 +488,13 @@ What: /sys/devices/system/cpu/cpuX/regs/ · 399 unmodified lines | |||
| 493 | /sys/devices/system/cpu/cpuX/regs/identification/ | 488 | /sys/devices/system/cpu/cpuX/regs/identification/ |
| 494 | /sys/devices/system/cpu/cpuX/regs/identification/midr_el1 | 489 | /sys/devices/system/cpu/cpuX/regs/identification/midr_el1 |
| 495 | /sys/devices/system/cpu/cpuX/regs/identification/revidr_el1 | 490 | /sys/devices/system/cpu/cpuX/regs/identification/revidr_el1 |
| 491 | /sys/devices/system/cpu/cpuX/regs/identification/smidr_el1 | ||
| 496 | Date: June 2016 | 492 | Date: June 2016 |
| 497 | Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org> | 493 | Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org> |
| 498 | Description: AArch64 CPU registers | 494 | Description: AArch64 CPU registers |
| 499 | 495 | ||
| 500 | 'identification' directory exposes the CPU ID registers for | 496 | 'identification' directory exposes the CPU ID registers for |
| 501 | identifying model and revision of the CPU. | 497 | identifying model and revision of the CPU and SMCU. |
| 502 | 498 | ||
| 503 | What: /sys/devices/system/cpu/aarch32_el0 | 499 | What: /sys/devices/system/cpu/aarch32_el0 |
| 504 | Date: May 2021 | 500 | Date: May 2021 |
| @@ -527,6 +523,7 @@ What: /sys/devices/system/cpu/vulnerabilities · 22 unmodified lines | |||
| 527 | /sys/devices/system/cpu/vulnerabilities/tsx_async_abort | 523 | /sys/devices/system/cpu/vulnerabilities/tsx_async_abort |
| 528 | /sys/devices/system/cpu/vulnerabilities/itlb_multihit | 524 | /sys/devices/system/cpu/vulnerabilities/itlb_multihit |
| 529 | /sys/devices/system/cpu/vulnerabilities/mmio_stale_data | 525 | /sys/devices/system/cpu/vulnerabilities/mmio_stale_data |
| 526 | /sys/devices/system/cpu/vulnerabilities/retbleed | ||
| 530 | Date: January 2018 | 527 | Date: January 2018 |
| 531 | Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> | 528 | Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> |
| 532 | Description: Information about CPU vulnerabilities | 529 | Description: Information about CPU vulnerabilities |
| @@ -0,0 +1,61 @@ | |||
| 1 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash | ||
| 2 | Date: Sep 2022 | ||
| 3 | KernelVersion: 5.20 | ||
| 4 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 5 | Description: Read only. Returns the root entry hash for the static | ||
| 6 | region if one is programmed, else it returns the | ||
| 7 | string: "hash not programmed". This file is only | ||
| 8 | visible if the underlying device supports it. | ||
| 9 | Format: string. | ||
| 10 | |||
| 11 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash | ||
| 12 | Date: Sep 2022 | ||
| 13 | KernelVersion: 5.20 | ||
| 14 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 15 | Description: Read only. Returns the root entry hash for the partial | ||
| 16 | reconfiguration region if one is programmed, else it | ||
| 17 | returns the string: "hash not programmed". This file | ||
| 18 | is only visible if the underlying device supports it. | ||
| 19 | Format: string. | ||
| 20 | |||
| 21 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash | ||
| 22 | Date: Sep 2022 | ||
| 23 | KernelVersion: 5.20 | ||
| 24 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 25 | Description: Read only. Returns the root entry hash for the BMC image | ||
| 26 | if one is programmed, else it returns the string: | ||
| 27 | "hash not programmed". This file is only visible if the | ||
| 28 | underlying device supports it. | ||
| 29 | Format: string. | ||
| 30 | |||
| 31 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks | ||
| 32 | Date: Sep 2022 | ||
| 33 | KernelVersion: 5.20 | ||
| 34 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 35 | Description: Read only. Returns a list of indices for canceled code | ||
| 36 | signing keys for the static region. The standard bitmap | ||
| 37 | list format is used (e.g. "1,2-6,9"). | ||
| 38 | |||
| 39 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks | ||
| 40 | Date: Sep 2022 | ||
| 41 | KernelVersion: 5.20 | ||
| 42 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 43 | Description: Read only. Returns a list of indices for canceled code | ||
| 44 | signing keys for the partial reconfiguration region. The | ||
| 45 | standard bitmap list format is used (e.g. "1,2-6,9"). | ||
| 46 | |||
| 47 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks | ||
| 48 | Date: Sep 2022 | ||
| 49 | KernelVersion: 5.20 | ||
| 50 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 51 | Description: Read only. Returns a list of indices for canceled code | ||
| 52 | signing keys for the BMC. The standard bitmap list format | ||
| 53 | is used (e.g. "1,2-6,9"). | ||
| 54 | |||
| 55 | What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count | ||
| 56 | Date: Sep 2022 | ||
| 57 | KernelVersion: 5.20 | ||
| 58 | Contact: Russ Weight <russell.h.weight@intel.com> | ||
| 59 | Description: Read only. Returns number of times the secure update | ||
| 60 | staging area has been flashed. | ||
| 61 | Format: "%u". | ||
| @@ -0,0 +1,49 @@ | |||
| 1 | What: /sys/bus/pci/devices/<BDF>/qat/state | ||
| 2 | Date: June 2022 | ||
| 3 | KernelVersion: 5.20 | ||
| 4 | Contact: qat-linux@intel.com | ||
| 5 | Description: (RW) Reports the current state of the QAT device. Write to | ||
| 6 | the file to start or stop the device. | ||
| 7 | |||
| 8 | The values are: | ||
| 9 | |||
| 10 | * up: the device is up and running | ||
| 11 | * down: the device is down | ||
| 12 | |||
| 13 | |||
| 14 | It is possible to transition the device from up to down only | ||
| 15 | if the device is up and vice versa. | ||
| 16 | |||
| 17 | This attribute is only available for qat_4xxx devices. | ||
| 18 | |||
| 19 | What: /sys/bus/pci/devices/<BDF>/qat/cfg_services | ||
| 20 | Date: June 2022 | ||
| 21 | KernelVersion: 5.20 | ||
| 22 | Contact: qat-linux@intel.com | ||
| 23 | Description: (RW) Reports the current configuration of the QAT device. | ||
| 24 | Write to the file to change the configured services. | ||
| 25 | |||
| 26 | The values are: | ||
| 27 | |||
| 28 | * sym;asym: the device is configured for running crypto | ||
| 29 | services | ||
| 30 | * dc: the device is configured for running compression services | ||
| 31 | |||
| 32 | It is possible to set the configuration only if the device | ||
| 33 | is in the `down` state (see /sys/bus/pci/devices/<BDF>/qat/state) | ||
| 34 | |||
| 35 | The following example shows how to change the configuration of | ||
| 36 | a device configured for running crypto services in order to | ||
| 37 | run data compression:: | ||
| 38 | |||
| 39 | # cat /sys/bus/pci/devices/<BDF>/qat/state | ||
| 40 | up | ||
| 41 | # cat /sys/bus/pci/devices/<BDF>/qat/cfg_services | ||
| 42 | sym;asym | ||
| 43 | # echo down > /sys/bus/pci/devices/<BDF>/qat/state | ||
| 44 | # echo dc > /sys/bus/pci/devices/<BDF>/qat/cfg_services | ||
| 45 | # echo up > /sys/bus/pci/devices/<BDF>/qat/state | ||
| 46 | # cat /sys/bus/pci/devices/<BDF>/qat/cfg_services | ||
| 47 | dc | ||
| 48 | |||
| 49 | This attribute is only available for qat_4xxx devices. | ||
| @@ -42,5 +42,5 @@ KernelVersion: 5.10 · 41 unmodified lines | |||
| 42 | Contact: Maximilian Heyne <mheyne@amazon.de> | 42 | Contact: Maximilian Heyne <mheyne@amazon.de> |
| 43 | Description: | 43 | Description: |
| 44 | Whether to enable the persistent grants feature or not. Note | 44 | Whether to enable the persistent grants feature or not. Note |
| 45 | that this option only takes effect on newly created backends. | 45 | that this option only takes effect on newly connected backends. |
| 46 | The default is Y (enable). | 46 | The default is Y (enable). |
| @@ -15,5 +15,5 @@ KernelVersion: 5.10 · 14 unmodified lines | |||
| 15 | Contact: Maximilian Heyne <mheyne@amazon.de> | 15 | Contact: Maximilian Heyne <mheyne@amazon.de> |
| 16 | Description: | 16 | Description: |
| 17 | Whether to enable the persistent grants feature or not. Note | 17 | Whether to enable the persistent grants feature or not. Note |
| 18 | that this option only takes effect on newly created frontends. | 18 | that this option only takes effect on newly connected frontends. |
| 19 | The default is Y (enable). | 19 | The default is Y (enable). |
| @@ -12,8 +12,9 @@ Description: · 11 unmodified lines | |||
| 12 | configuration data to the guest userspace. | 12 | configuration data to the guest userspace. |
| 13 | 13 | ||
| 14 | The authoritative guest-side hardware interface documentation | 14 | The authoritative guest-side hardware interface documentation |
| 15 | to the fw_cfg device can be found in "docs/specs/fw_cfg.txt" | 15 | to the fw_cfg device can be found in "docs/specs/fw_cfg.rst" |
| 16 | in the QEMU source tree. | 16 | in the QEMU source tree, or online at: |
| 17 | https://qemu-project.gitlab.io/qemu/specs/fw_cfg.html | ||
| 17 | 18 | ||
| 18 | **SysFS fw_cfg Interface** | 19 | **SysFS fw_cfg Interface** |
| 19 | 20 | ||
| @@ -580,3 +580,33 @@ Date: January 2022 · 579 unmodified lines | |||
| 580 | Contact: "Jaegeuk Kim" <jaegeuk@kernel.org> | 580 | Contact: "Jaegeuk Kim" <jaegeuk@kernel.org> |
| 581 | Description: Controls max # of node block writes to be used for roll forward | 581 | Description: Controls max # of node block writes to be used for roll forward |
| 582 | recovery. This can limit the roll forward recovery time. | 582 | recovery. This can limit the roll forward recovery time. |
| 583 | |||
| 584 | What: /sys/fs/f2fs/<disk>/unusable_blocks_per_sec | ||
| 585 | Date: June 2022 | ||
| 586 | Contact: "Jaegeuk Kim" <jaegeuk@kernel.org> | ||
| 587 | Description: Shows the number of unusable blocks in a section which was defined by | ||
| 588 | the zone capacity reported by underlying zoned device. | ||
| 589 | |||
| 590 | What: /sys/fs/f2fs/<disk>/current_atomic_write | ||
| 591 | Date: July 2022 | ||
| 592 | Contact: "Daeho Jeong" <daehojeong@google.com> | ||
| 593 | Description: Show the total current atomic write block count, which is not committed yet. | ||
| 594 | This is a read-only entry. | ||
| 595 | |||
| 596 | What: /sys/fs/f2fs/<disk>/peak_atomic_write | ||
| 597 | Date: July 2022 | ||
| 598 | Contact: "Daeho Jeong" <daehojeong@google.com> | ||
| 599 | Description: Show the peak value of total current atomic write block count after boot. | ||
| 600 | If you write "0" here, you can initialize to "0". | ||
| 601 | |||
| 602 | What: /sys/fs/f2fs/<disk>/committed_atomic_block | ||
| 603 | Date: July 2022 | ||
| 604 | Contact: "Daeho Jeong" <daehojeong@google.com> | ||
| 605 | Description: Show the accumulated total committed atomic write block count after boot. | ||
| 606 | If you write "0" here, you can initialize to "0". | ||
| 607 | |||
| 608 | What: /sys/fs/f2fs/<disk>/revoked_atomic_block | ||
| 609 | Date: July 2022 | ||
| 610 | Contact: "Daeho Jeong" <daehojeong@google.com> | ||
| 611 | Description: Show the accumulated total revoked atomic write block count after boot. | ||
| 612 | If you write "0" here, you can initialize to "0". | ||
| @@ -41,7 +41,7 @@ Description: Kernel Samepage Merging daemon sysfs interface · 40 unmodified lines | |||
| 41 | sleep_millisecs: how many milliseconds ksm should sleep between | 41 | sleep_millisecs: how many milliseconds ksm should sleep between |
| 42 | scans. | 42 | scans. |
| 43 | 43 | ||
| 44 | See Documentation/vm/ksm.rst for more information. | 44 | See Documentation/mm/ksm.rst for more information. |
| 45 | 45 | ||
| 46 | What: /sys/kernel/mm/ksm/merge_across_nodes | 46 | What: /sys/kernel/mm/ksm/merge_across_nodes |
| 47 | Date: January 2013 | 47 | Date: January 2013 |
| @@ -37,7 +37,7 @@ Description: · 36 unmodified lines | |||
| 37 | The alloc_calls file is read-only and lists the kernel code | 37 | The alloc_calls file is read-only and lists the kernel code |
| 38 | locations from which allocations for this cache were performed. | 38 | locations from which allocations for this cache were performed. |
| 39 | The alloc_calls file only contains information if debugging is | 39 | The alloc_calls file only contains information if debugging is |
| 40 | enabled for that cache (see Documentation/vm/slub.rst). | 40 | enabled for that cache (see Documentation/mm/slub.rst). |
| 41 | 41 | ||
| 42 | What: /sys/kernel/slab/<cache>/alloc_fastpath | 42 | What: /sys/kernel/slab/<cache>/alloc_fastpath |
| 43 | Date: February 2008 | 43 | Date: February 2008 |
| @@ -219,7 +219,7 @@ Contact: Pekka Enberg <penberg@cs.helsinki.fi>, · 175 unmodified lines | |||
| 219 | Description: | 219 | Description: |
| 220 | The free_calls file is read-only and lists the locations of | 220 | The free_calls file is read-only and lists the locations of |
| 221 | object frees if slab debugging is enabled (see | 221 | object frees if slab debugging is enabled (see |
| 222 | Documentation/vm/slub.rst). | 222 | Documentation/mm/slub.rst). |
| 223 | 223 | ||
| 224 | What: /sys/kernel/slab/<cache>/free_fastpath | 224 | What: /sys/kernel/slab/<cache>/free_fastpath |
| 225 | Date: February 2008 | 225 | Date: February 2008 |
| @@ -1,23 +1,22 @@ | |||
| 1 | config WARN_MISSING_DOCUMENTS | 1 | config WARN_MISSING_DOCUMENTS |
| 2 | |||
| 3 | bool "Warn if there's a missing documentation file" | 2 | bool "Warn if there's a missing documentation file" |
| 4 | depends on COMPILE_TEST | 3 | depends on COMPILE_TEST |
| 5 | help | 4 | help |
| 6 | It is not uncommon that a document gets renamed. | 5 | It is not uncommon that a document gets renamed. |
| 7 | This option makes the Kernel to check for missing dependencies, | 6 | This option makes the Kernel to check for missing dependencies, |
| 8 | warning when something is missing. Works only if the Kernel | 7 | warning when something is missing. Works only if the Kernel |
| 9 | is built from a git tree. | 8 | is built from a git tree. |
| 10 | 9 | ||
| 11 | If unsure, select 'N'. | 10 | If unsure, select 'N'. |
| 12 | 11 | ||
| 13 | config WARN_ABI_ERRORS | 12 | config WARN_ABI_ERRORS |
| 14 | bool "Warn if there are errors at ABI files" | 13 | bool "Warn if there are errors at ABI files" |
| 15 | depends on COMPILE_TEST | 14 | depends on COMPILE_TEST |
| 16 | help | 15 | help |
| 17 | The files under Documentation/ABI should follow what's | 16 | The files under Documentation/ABI should follow what's |
| 18 | described at Documentation/ABI/README. Yet, as they're manually | 17 | described at Documentation/ABI/README. Yet, as they're manually |
| 19 | written, it would be possible that some of those files would | 18 | written, it would be possible that some of those files would |
| 20 | have errors that would break them for being parsed by | 19 | have errors that would break them for being parsed by |
| 21 | scripts/get_abi.pl. Add a check to verify them. | 20 | scripts/get_abi.pl. Add a check to verify them. |
| 22 | 21 | ||
| 23 | If unsure, select 'N'. | 22 | If unsure, select 'N'. |
| @@ -13,6 +13,8 @@ PCI Endpoint Framework · 12 unmodified lines | |||
| 13 | pci-test-howto | 13 | pci-test-howto |
| 14 | pci-ntb-function | 14 | pci-ntb-function |
| 15 | pci-ntb-howto | 15 | pci-ntb-howto |
| 16 | pci-vntb-function | ||
| 17 | pci-vntb-howto | ||
| 16 | 18 | ||
| 17 | function/binding/pci-test | 19 | function/binding/pci-test |
| 18 | function/binding/pci-ntb | 20 | function/binding/pci-ntb |
| @@ -0,0 +1,129 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0 | ||
| 2 | |||
| 3 | ================= | ||
| 4 | PCI vNTB Function | ||
| 5 | ================= | ||
| 6 | |||
| 7 | :Author: Frank Li <Frank.Li@nxp.com> | ||
| 8 | |||
| 9 | The difference between PCI NTB function and PCI vNTB function is | ||
| 10 | |||
| 11 | PCI NTB function need at two endpoint instances and connect HOST1 | ||
| 12 | and HOST2. | ||
| 13 | |||
| 14 | PCI vNTB function only use one host and one endpoint(EP), use NTB | ||
| 15 | connect EP and PCI host | ||
| 16 | |||
| 17 | .. code-block:: text | ||
| 18 | |||
| 19 | |||
| 20 | +------------+ +---------------------------------------+ | ||
| 21 | | | | | | ||
| 22 | +------------+ | +--------------+ | ||
| 23 | | NTB | | | NTB | | ||
| 24 | | NetDev | | | NetDev | | ||
| 25 | +------------+ | +--------------+ | ||
| 26 | | NTB | | | NTB | | ||
| 27 | | Transfer | | | Transfer | | ||
| 28 | +------------+ | +--------------+ | ||
| 29 | | | | | | | ||
| 30 | | PCI NTB | | | | | ||
| 31 | | EPF | | | | | ||
| 32 | | Driver | | | PCI Virtual | | ||
| 33 | | | +---------------+ | NTB Driver | | ||
| 34 | | | | PCI EP NTB |<------>| | | ||
| 35 | | | | FN Driver | | | | ||
| 36 | +------------+ +---------------+ +--------------+ | ||
| 37 | | | | | | | | ||
| 38 | | PCI BUS | <-----> | PCI EP BUS | | Virtual PCI | | ||
| 39 | | | PCI | | | BUS | | ||
| 40 | +------------+ +---------------+--------+--------------+ | ||
| 41 | PCI RC PCI EP | ||
| 42 | |||
| 43 | Constructs used for Implementing vNTB | ||
| 44 | ===================================== | ||
| 45 | |||
| 46 | 1) Config Region | ||
| 47 | 2) Self Scratchpad Registers | ||
| 48 | 3) Peer Scratchpad Registers | ||
| 49 | 4) Doorbell (DB) Registers | ||
| 50 | 5) Memory Window (MW) | ||
| 51 | |||
| 52 | |||
| 53 | Config Region: | ||
| 54 | -------------- | ||
| 55 | |||
| 56 | It is same as PCI NTB Function driver | ||
| 57 | |||
| 58 | Scratchpad Registers: | ||
| 59 | --------------------- | ||
| 60 | |||
| 61 | It is appended after Config region. | ||
| 62 | |||
| 63 | .. code-block:: text | ||
| 64 | |||
| 65 | |||
| 66 | +--------------------------------------------------+ Base | ||
| 67 | | | | ||
| 68 | | | | ||
| 69 | | | | ||
| 70 | | Common Config Register | | ||
| 71 | | | | ||
| 72 | | | | ||
| 73 | | | | ||
| 74 | +-----------------------+--------------------------+ Base + span_offset | ||
| 75 | | | | | ||
| 76 | | Peer Span Space | Span Space | | ||
| 77 | | | | | ||
| 78 | | | | | ||
| 79 | +-----------------------+--------------------------+ Base + span_offset | ||
| 80 | | | | + span_count * 4 | ||
| 81 | | | | | ||
| 82 | | Span Space | Peer Span Space | | ||
| 83 | | | | | ||
| 84 | +-----------------------+--------------------------+ | ||
| 85 | Virtual PCI Pcie Endpoint | ||
| 86 | NTB Driver NTB Driver | ||
| 87 | |||
| 88 | |||
| 89 | Doorbell Registers: | ||
| 90 | ------------------- | ||
| 91 | |||
| 92 | Doorbell Registers are used by the hosts to interrupt each other. | ||
| 93 | |||
| 94 | Memory Window: | ||
| 95 | -------------- | ||
| 96 | |||
| 97 | Actual transfer of data between the two hosts will happen using the | ||
| 98 | memory window. | ||
| 99 | |||
| 100 | Modeling Constructs: | ||
| 101 | ==================== | ||
| 102 | |||
| 103 | 32-bit BARs. | ||
| 104 | |||
| 105 | ====== =============== | ||
| 106 | BAR NO CONSTRUCTS USED | ||
| 107 | ====== =============== | ||
| 108 | BAR0 Config Region | ||
| 109 | BAR1 Doorbell | ||
| 110 | BAR2 Memory Window 1 | ||
| 111 | BAR3 Memory Window 2 | ||
| 112 | BAR4 Memory Window 3 | ||
| 113 | BAR5 Memory Window 4 | ||
| 114 | ====== =============== | ||
| 115 | |||
| 116 | 64-bit BARs. | ||
| 117 | |||
| 118 | ====== =============================== | ||
| 119 | BAR NO CONSTRUCTS USED | ||
| 120 | ====== =============================== | ||
| 121 | BAR0 Config Region + Scratchpad | ||
| 122 | BAR1 | ||
| 123 | BAR2 Doorbell | ||
| 124 | BAR3 | ||
| 125 | BAR4 Memory Window 1 | ||
| 126 | BAR5 | ||
| 127 | ====== =============================== | ||
| 128 | |||
| 129 | |||
| @@ -0,0 +1,167 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0 | ||
| 2 | |||
| 3 | =================================================================== | ||
| 4 | PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide | ||
| 5 | =================================================================== | ||
| 6 | |||
| 7 | :Author: Frank Li <Frank.Li@nxp.com> | ||
| 8 | |||
| 9 | This document is a guide to help users use pci-epf-vntb function driver | ||
| 10 | and ntb_hw_epf host driver for NTB functionality. The list of steps to | ||
| 11 | be followed in the host side and EP side is given below. For the hardware | ||
| 12 | configuration and internals of NTB using configurable endpoints see | ||
| 13 | Documentation/PCI/endpoint/pci-vntb-function.rst | ||
| 14 | |||
| 15 | Endpoint Device | ||
| 16 | =============== | ||
| 17 | |||
| 18 | Endpoint Controller Devices | ||
| 19 | --------------------------- | ||
| 20 | |||
| 21 | To find the list of endpoint controller devices in the system:: | ||
| 22 | |||
| 23 | # ls /sys/class/pci_epc/ | ||
| 24 | 5f010000.pcie_ep | ||
| 25 | |||
| 26 | If PCI_ENDPOINT_CONFIGFS is enabled:: | ||
| 27 | |||
| 28 | # ls /sys/kernel/config/pci_ep/controllers | ||
| 29 | 5f010000.pcie_ep | ||
| 30 | |||
| 31 | Endpoint Function Drivers | ||
| 32 | ------------------------- | ||
| 33 | |||
| 34 | To find the list of endpoint function drivers in the system:: | ||
| 35 | |||
| 36 | # ls /sys/bus/pci-epf/drivers | ||
| 37 | pci_epf_ntb pci_epf_test pci_epf_vntb | ||
| 38 | |||
| 39 | If PCI_ENDPOINT_CONFIGFS is enabled:: | ||
| 40 | |||
| 41 | # ls /sys/kernel/config/pci_ep/functions | ||
| 42 | pci_epf_ntb pci_epf_test pci_epf_vntb | ||
| 43 | |||
| 44 | |||
| 45 | Creating pci-epf-vntb Device | ||
| 46 | ---------------------------- | ||
| 47 | |||
| 48 | PCI endpoint function device can be created using the configfs. To create | ||
| 49 | pci-epf-vntb device, the following commands can be used:: | ||
| 50 | |||
| 51 | # mount -t configfs none /sys/kernel/config | ||
| 52 | # cd /sys/kernel/config/pci_ep/ | ||
| 53 | # mkdir functions/pci_epf_vntb/func1 | ||
| 54 | |||
| 55 | The "mkdir func1" above creates the pci-epf-ntb function device that will | ||
| 56 | be probed by pci_epf_vntb driver. | ||
| 57 | |||
| 58 | The PCI endpoint framework populates the directory with the following | ||
| 59 | configurable fields:: | ||
| 60 | |||
| 61 | # ls functions/pci_epf_ntb/func1 | ||
| 62 | baseclass_code deviceid msi_interrupts pci-epf-ntb.0 | ||
| 63 | progif_code secondary subsys_id vendorid | ||
| 64 | cache_line_size interrupt_pin msix_interrupts primary | ||
| 65 | revid subclass_code subsys_vendor_id | ||
| 66 | |||
| 67 | The PCI endpoint function driver populates these entries with default values | ||
| 68 | when the device is bound to the driver. The pci-epf-vntb driver populates | ||
| 69 | vendorid with 0xffff and interrupt_pin with 0x0001:: | ||
| 70 | |||
| 71 | # cat functions/pci_epf_vntb/func1/vendorid | ||
| 72 | 0xffff | ||
| 73 | # cat functions/pci_epf_vntb/func1/interrupt_pin | ||
| 74 | 0x0001 | ||
| 75 | |||
| 76 | |||
| 77 | Configuring pci-epf-vntb Device | ||
| 78 | ------------------------------- | ||
| 79 | |||
| 80 | The user can configure the pci-epf-vntb device using its configfs entry. In order | ||
| 81 | to change the vendorid and the deviceid, the following | ||
| 82 | commands can be used:: | ||
| 83 | |||
| 84 | # echo 0x1957 > functions/pci_epf_vntb/func1/vendorid | ||
| 85 | # echo 0x0809 > functions/pci_epf_vntb/func1/deviceid | ||
| 86 | |||
| 87 | In order to configure NTB specific attributes, a new sub-directory to func1 | ||
| 88 | should be created:: | ||
| 89 | |||
| 90 | # mkdir functions/pci_epf_vntb/func1/pci_epf_vntb.0/ | ||
| 91 | |||
| 92 | The NTB function driver will populate this directory with various attributes | ||
| 93 | that can be configured by the user:: | ||
| 94 | |||
| 95 | # ls functions/pci_epf_vntb/func1/pci_epf_vntb.0/ | ||
| 96 | db_count mw1 mw2 mw3 mw4 num_mws | ||
| 97 | spad_count | ||
| 98 | |||
| 99 | A sample configuration for NTB function is given below:: | ||
| 100 | |||
| 101 | # echo 4 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/db_count | ||
| 102 | # echo 128 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/spad_count | ||
| 103 | # echo 1 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws | ||
| 104 | # echo 0x100000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1 | ||
| 105 | |||
| 106 | A sample configuration for virtual NTB driver for virutal PCI bus:: | ||
| 107 | |||
| 108 | # echo 0x1957 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_vid | ||
| 109 | # echo 0x080A > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_pid | ||
| 110 | # echo 0x10 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vbus_number | ||
| 111 | |||
| 112 | Binding pci-epf-ntb Device to EP Controller | ||
| 113 | -------------------------------------------- | ||
| 114 | |||
| 115 | NTB function device should be attached to PCI endpoint controllers | ||
| 116 | connected to the host. | ||
| 117 | |||
| 118 | # ln -s controllers/5f010000.pcie_ep functions/pci-epf-ntb/func1/primary | ||
| 119 | |||
| 120 | Once the above step is completed, the PCI endpoint controllers are ready to | ||
| 121 | establish a link with the host. | ||
| 122 | |||
| 123 | |||
| 124 | Start the Link | ||
| 125 | -------------- | ||
| 126 | |||
| 127 | In order for the endpoint device to establish a link with the host, the _start_ | ||
| 128 | field should be populated with '1'. For NTB, both the PCI endpoint controllers | ||
| 129 | should establish link with the host (imx8 don't need this steps):: | ||
| 130 | |||
| 131 | # echo 1 > controllers/5f010000.pcie_ep/start | ||
| 132 | |||
| 133 | RootComplex Device | ||
| 134 | ================== | ||
| 135 | |||
| 136 | lspci Output at Host side | ||
| 137 | ------------------------- | ||
| 138 | |||
| 139 | Note that the devices listed here correspond to the values populated in | ||
| 140 | "Creating pci-epf-ntb Device" section above:: | ||
| 141 | |||
| 142 | # lspci | ||
| 143 | 00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01) | ||
| 144 | 01:00.0 RAM memory: Freescale Semiconductor Inc Device 0809 | ||
| 145 | |||
| 146 | Endpoint Device / Virtual PCI bus | ||
| 147 | ================================= | ||
| 148 | |||
| 149 | lspci Output at EP Side / Virtual PCI bus | ||
| 150 | ----------------------------------------- | ||
| 151 | |||
| 152 | Note that the devices listed here correspond to the values populated in | ||
| 153 | "Creating pci-epf-ntb Device" section above:: | ||
| 154 | |||
| 155 | # lspci | ||
| 156 | 10:00.0 Unassigned class [ffff]: Dawicontrol Computersysteme GmbH Device 1234 (rev ff) | ||
| 157 | |||
| 158 | Using ntb_hw_epf Device | ||
| 159 | ----------------------- | ||
| 160 | |||
| 161 | The host side software follows the standard NTB software architecture in Linux. | ||
| 162 | All the existing client side NTB utilities like NTB Transport Client and NTB | ||
| 163 | Netdev, NTB Ping Pong Test Client and NTB Tool Test Client can be used with NTB | ||
| 164 | function device. | ||
| 165 | |||
| 166 | For more information on NTB see | ||
| 167 | :doc:`Non-Transparent Bridge <../../driver-api/ntb>` | ||
| @@ -125,14 +125,14 @@ Following piece of code illustrates the usage of the SR-IOV API. · 124 unmodified lines | |||
| 125 | ... | 125 | ... |
| 126 | } | 126 | } |
| 127 | 127 | ||
| 128 | static int dev_suspend(struct pci_dev *dev, pm_message_t state) | 128 | static int dev_suspend(struct device *dev) |
| 129 | { | 129 | { |
| 130 | ... | 130 | ... |
| 131 | 131 | ||
| 132 | return 0; | 132 | return 0; |
| 133 | } | 133 | } |
| 134 | 134 | ||
| 135 | static int dev_resume(struct pci_dev *dev) | 135 | static int dev_resume(struct device *dev) |
| 136 | { | 136 | { |
| 137 | ... | 137 | ... |
| 138 | 138 | ||
| @@ -165,8 +165,7 @@ Following piece of code illustrates the usage of the SR-IOV API. · 26 unmodified lines | |||
| 165 | .id_table = dev_id_table, | 165 | .id_table = dev_id_table, |
| 166 | .probe = dev_probe, | 166 | .probe = dev_probe, |
| 167 | .remove = dev_remove, | 167 | .remove = dev_remove, |
| 168 | .suspend = dev_suspend, | 168 | .driver.pm = &dev_pm_ops, |
| 169 | .resume = dev_resume, | ||
| 170 | .shutdown = dev_shutdown, | 169 | .shutdown = dev_shutdown, |
| 171 | .sriov_configure = dev_sriov_configure, | 170 | .sriov_configure = dev_sriov_configure, |
| 172 | }; | 171 | }; |
| @@ -125,7 +125,7 @@ implementation of that functionality. To support the historical interface of · 124 unmodified lines | |||
| 125 | mmap() through files in /proc/bus/pci, platforms may also set HAVE_PCI_MMAP. | 125 | mmap() through files in /proc/bus/pci, platforms may also set HAVE_PCI_MMAP. |
| 126 | 126 | ||
| 127 | Alternatively, platforms which set HAVE_PCI_MMAP may provide their own | 127 | Alternatively, platforms which set HAVE_PCI_MMAP may provide their own |
| 128 | implementation of pci_mmap_page_range() instead of defining | 128 | implementation of pci_mmap_resource_range() instead of defining |
| 129 | ARCH_GENERIC_PCI_MMAP_RESOURCE. | 129 | ARCH_GENERIC_PCI_MMAP_RESOURCE. |
| 130 | 130 | ||
| 131 | Platforms which support write-combining maps of PCI resources must define | 131 | Platforms which support write-combining maps of PCI resources must define |
| @@ -1844,10 +1844,10 @@ that meets this requirement. · 1843 unmodified lines | |||
| 1844 | 1844 | ||
| 1845 | Furthermore, NMI handlers can be interrupted by what appear to RCU to be | 1845 | Furthermore, NMI handlers can be interrupted by what appear to RCU to be |
| 1846 | normal interrupts. One way that this can happen is for code that | 1846 | normal interrupts. One way that this can happen is for code that |
| 1847 | directly invokes rcu_irq_enter() and rcu_irq_exit() to be called | 1847 | directly invokes ct_irq_enter() and ct_irq_exit() to be called |
| 1848 | from an NMI handler. This astonishing fact of life prompted the current | 1848 | from an NMI handler. This astonishing fact of life prompted the current |
| 1849 | code structure, which has rcu_irq_enter() invoking | 1849 | code structure, which has ct_irq_enter() invoking |
| 1850 | rcu_nmi_enter() and rcu_irq_exit() invoking rcu_nmi_exit(). | 1850 | ct_nmi_enter() and ct_irq_exit() invoking ct_nmi_exit(). |
| 1851 | And yes, I also learned of this requirement the hard way. | 1851 | And yes, I also learned of this requirement the hard way. |
| 1852 | 1852 | ||
| 1853 | Loadable Modules | 1853 | Loadable Modules |
| @@ -2195,7 +2195,7 @@ scheduling-clock interrupt be enabled when RCU needs it to be: · 341 unmodified lines | |||
| 2195 | sections, and RCU believes this CPU to be idle, no problem. This | 2195 | sections, and RCU believes this CPU to be idle, no problem. This |
| 2196 | sort of thing is used by some architectures for light-weight | 2196 | sort of thing is used by some architectures for light-weight |
| 2197 | exception handlers, which can then avoid the overhead of | 2197 | exception handlers, which can then avoid the overhead of |
| 2198 | rcu_irq_enter() and rcu_irq_exit() at exception entry and | 2198 | ct_irq_enter() and ct_irq_exit() at exception entry and |
| 2199 | exit, respectively. Some go further and avoid the entireties of | 2199 | exit, respectively. Some go further and avoid the entireties of |
| 2200 | irq_enter() and irq_exit(). | 2200 | irq_enter() and irq_exit(). |
| 2201 | Just make very sure you are running some of your tests with | 2201 | Just make very sure you are running some of your tests with |
| @@ -2226,7 +2226,7 @@ scheduling-clock interrupt be enabled when RCU needs it to be: · 24 unmodified lines | |||
| 2226 | +-----------------------------------------------------------------------+ | 2226 | +-----------------------------------------------------------------------+ |
| 2227 | | **Answer**: | | 2227 | | **Answer**: | |
| 2228 | +-----------------------------------------------------------------------+ | 2228 | +-----------------------------------------------------------------------+ |
| 2229 | | One approach is to do ``rcu_irq_exit();rcu_irq_enter();`` every so | | 2229 | | One approach is to do ``ct_irq_exit();ct_irq_enter();`` every so | |
| 2230 | | often. But given that long-running interrupt handlers can cause other | | 2230 | | often. But given that long-running interrupt handlers can cause other | |
| 2231 | | problems, not least for response time, shouldn't you work to keep | | 2231 | | problems, not least for response time, shouldn't you work to keep | |
| 2232 | | your interrupt handler's runtime within reasonable bounds? | | 2232 | | your interrupt handler's runtime within reasonable bounds? | |
| @@ -97,12 +97,12 @@ warnings: · 96 unmodified lines | |||
| 97 | which will include additional debugging information. | 97 | which will include additional debugging information. |
| 98 | 98 | ||
| 99 | - A low-level kernel issue that either fails to invoke one of the | 99 | - A low-level kernel issue that either fails to invoke one of the |
| 100 | variants of rcu_user_enter(), rcu_user_exit(), rcu_idle_enter(), | 100 | variants of rcu_eqs_enter(true), rcu_eqs_exit(true), ct_idle_enter(), |
| 101 | rcu_idle_exit(), rcu_irq_enter(), or rcu_irq_exit() on the one | 101 | ct_idle_exit(), ct_irq_enter(), or ct_irq_exit() on the one |
| 102 | hand, or that invokes one of them too many times on the other. | 102 | hand, or that invokes one of them too many times on the other. |
| 103 | Historically, the most frequent issue has been an omission | 103 | Historically, the most frequent issue has been an omission |
| 104 | of either irq_enter() or irq_exit(), which in turn invoke | 104 | of either irq_enter() or irq_exit(), which in turn invoke |
| 105 | rcu_irq_enter() or rcu_irq_exit(), respectively. Building your | 105 | ct_irq_enter() or ct_irq_exit(), respectively. Building your |
| 106 | kernel with CONFIG_RCU_EQS_DEBUG=y can help track down these types | 106 | kernel with CONFIG_RCU_EQS_DEBUG=y can help track down these types |
| 107 | of issues, which sometimes arise in architecture-specific code. | 107 | of issues, which sometimes arise in architecture-specific code. |
| 108 | 108 | ||
| @@ -1,9 +1,9 @@ | |||
| 1 | .. _readme: | 1 | .. _readme: |
| 2 | 2 | ||
| 3 | Linux kernel release 5.x <http://kernel.org/> | 3 | Linux kernel release 6.x <http://kernel.org/> |
| 4 | ============================================= | 4 | ============================================= |
| 5 | 5 | ||
| 6 | These are the release notes for Linux version 5. Read them carefully, | 6 | These are the release notes for Linux version 6. Read them carefully, |
| 7 | as they tell you what this is all about, explain how to install the | 7 | as they tell you what this is all about, explain how to install the |
| 8 | kernel, and what to do if something goes wrong. | 8 | kernel, and what to do if something goes wrong. |
| 9 | 9 | ||
| @@ -63,7 +63,7 @@ Installing the kernel source · 53 unmodified lines | |||
| 63 | directory where you have permissions (e.g. your home directory) and | 63 | directory where you have permissions (e.g. your home directory) and |
| 64 | unpack it:: | 64 | unpack it:: |
| 65 | 65 | ||
| 66 | xz -cd linux-5.x.tar.xz | tar xvf - | 66 | xz -cd linux-6.x.tar.xz | tar xvf - |
| 67 | 67 | ||
| 68 | Replace "X" with the version number of the latest kernel. | 68 | Replace "X" with the version number of the latest kernel. |
| 69 | 69 | ||
| @@ -72,12 +72,12 @@ Installing the kernel source · 2 unmodified lines | |||
| 72 | files. They should match the library, and not get messed up by | 72 | files. They should match the library, and not get messed up by |
| 73 | whatever the kernel-du-jour happens to be. | 73 | whatever the kernel-du-jour happens to be. |
| 74 | 74 | ||
| 75 | - You can also upgrade between 5.x releases by patching. Patches are | 75 | - You can also upgrade between 6.x releases by patching. Patches are |
| 76 | distributed in the xz format. To install by patching, get all the | 76 | distributed in the xz format. To install by patching, get all the |
| 77 | newer patch files, enter the top level directory of the kernel source | 77 | newer patch files, enter the top level directory of the kernel source |
| 78 | (linux-5.x) and execute:: | 78 | (linux-6.x) and execute:: |
| 79 | 79 | ||
| 80 | xz -cd ../patch-5.x.xz | patch -p1 | 80 | xz -cd ../patch-6.x.xz | patch -p1 |
| 81 | 81 | ||
| 82 | Replace "x" for all versions bigger than the version "x" of your current | 82 | Replace "x" for all versions bigger than the version "x" of your current |
| 83 | source tree, **in_order**, and you should be ok. You may want to remove | 83 | source tree, **in_order**, and you should be ok. You may want to remove |
| @@ -85,13 +85,13 @@ Installing the kernel source · 1 unmodified line | |||
| 85 | that there are no failed patches (some-file-name# or some-file-name.rej). | 85 | that there are no failed patches (some-file-name# or some-file-name.rej). |
| 86 | If there are, either you or I have made a mistake. | 86 | If there are, either you or I have made a mistake. |
| 87 | 87 | ||
| 88 | Unlike patches for the 5.x kernels, patches for the 5.x.y kernels | 88 | Unlike patches for the 6.x kernels, patches for the 6.x.y kernels |
| 89 | (also known as the -stable kernels) are not incremental but instead apply | 89 | (also known as the -stable kernels) are not incremental but instead apply |
| 90 | directly to the base 5.x kernel. For example, if your base kernel is 5.0 | 90 | directly to the base 6.x kernel. For example, if your base kernel is 6.0 |
| 91 | and you want to apply the 5.0.3 patch, you must not first apply the 5.0.1 | 91 | and you want to apply the 6.0.3 patch, you must not first apply the 6.0.1 |
| 92 | and 5.0.2 patches. Similarly, if you are running kernel version 5.0.2 and | 92 | and 6.0.2 patches. Similarly, if you are running kernel version 6.0.2 and |
| 93 | want to jump to 5.0.3, you must first reverse the 5.0.2 patch (that is, | 93 | want to jump to 6.0.3, you must first reverse the 6.0.2 patch (that is, |
| 94 | patch -R) **before** applying the 5.0.3 patch. You can read more on this in | 94 | patch -R) **before** applying the 6.0.3 patch. You can read more on this in |
| 95 | :ref:`Documentation/process/applying-patches.rst <applying_patches>`. | 95 | :ref:`Documentation/process/applying-patches.rst <applying_patches>`. |
| 96 | 96 | ||
| 97 | Alternatively, the script patch-kernel can be used to automate this | 97 | Alternatively, the script patch-kernel can be used to automate this |
| @@ -114,7 +114,7 @@ Installing the kernel source · 16 unmodified lines | |||
| 114 | Software requirements | 114 | Software requirements |
| 115 | --------------------- | 115 | --------------------- |
| 116 | 116 | ||
| 117 | Compiling and running the 5.x kernels requires up-to-date | 117 | Compiling and running the 6.x kernels requires up-to-date |
| 118 | versions of various software packages. Consult | 118 | versions of various software packages. Consult |
| 119 | :ref:`Documentation/process/changes.rst <changes>` for the minimum version numbers | 119 | :ref:`Documentation/process/changes.rst <changes>` for the minimum version numbers |
| 120 | required and how to get updates for these packages. Beware that using | 120 | required and how to get updates for these packages. Beware that using |
| @@ -132,12 +132,12 @@ Build directory for the kernel · 11 unmodified lines | |||
| 132 | place for the output files (including .config). | 132 | place for the output files (including .config). |
| 133 | Example:: | 133 | Example:: |
| 134 | 134 | ||
| 135 | kernel source code: /usr/src/linux-5.x | 135 | kernel source code: /usr/src/linux-6.x |
| 136 | build directory: /home/name/build/kernel | 136 | build directory: /home/name/build/kernel |
| 137 | 137 | ||
| 138 | To configure and build the kernel, use:: | 138 | To configure and build the kernel, use:: |
| 139 | 139 | ||
| 140 | cd /usr/src/linux-5.x | 140 | cd /usr/src/linux-6.x |
| 141 | make O=/home/name/build/kernel menuconfig | 141 | make O=/home/name/build/kernel menuconfig |
| 142 | make O=/home/name/build/kernel | 142 | make O=/home/name/build/kernel |
| 143 | sudo make O=/home/name/build/kernel modules_install install | 143 | sudo make O=/home/name/build/kernel modules_install install |
| @@ -97,7 +97,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y. · 96 unmodified lines | |||
| 97 | ============= | 97 | ============= |
| 98 | 98 | ||
| 99 | Page Cache is charged at | 99 | Page Cache is charged at |
| 100 | - add_to_page_cache_locked(). | 100 | - filemap_add_folio(). |
| 101 | 101 | ||
| 102 | The logic is very clear. (About migration, see below) | 102 | The logic is very clear. (About migration, see below) |
| 103 | 103 | ||
| @@ -184,6 +184,14 @@ cgroup v2 currently supports the following mount options. · 183 unmodified lines | |||
| 184 | ignored on non-init namespace mounts. Please refer to the | 184 | ignored on non-init namespace mounts. Please refer to the |
| 185 | Delegation section for details. | 185 | Delegation section for details. |
| 186 | 186 | ||
| 187 | favordynmods | ||
| 188 | Reduce the latencies of dynamic cgroup modifications such as | ||
| 189 | task migrations and controller on/offs at the cost of making | ||
| 190 | hot path operations such as forks and exits more expensive. | ||
| 191 | The static usage pattern of creating a cgroup, enabling | ||
| 192 | controllers, and then seeding it with CLONE_INTO_CGROUP is | ||
| 193 | not affected by this option. | ||
| 194 | |||
| 187 | memory_localevents | 195 | memory_localevents |
| 188 | Only populate memory.events with data for the current cgroup, | 196 | Only populate memory.events with data for the current cgroup, |
| 189 | and not any subtrees. This is legacy behaviour, the default | 197 | and not any subtrees. This is legacy behaviour, the default |
| @@ -1229,6 +1237,13 @@ PAGE_SIZE multiple when read back. · 1039 unmodified lines | |||
| 1229 | the target cgroup. If less bytes are reclaimed than the | 1237 | the target cgroup. If less bytes are reclaimed than the |
| 1230 | specified amount, -EAGAIN is returned. | 1238 | specified amount, -EAGAIN is returned. |
| 1231 | 1239 | ||
| 1240 | Please note that the proactive reclaim (triggered by this | ||
| 1241 | interface) is not meant to indicate memory pressure on the | ||
| 1242 | memory cgroup. Therefore socket memory balancing triggered by | ||
| 1243 | the memory reclaim normally is not exercised in this case. | ||
| 1244 | This means that the networking layer will not adapt based on | ||
| 1245 | reclaim induced by memory.reclaim. | ||
| 1246 | |||
| 1232 | memory.peak | 1247 | memory.peak |
| 1233 | A read-only single value file which exists on non-root | 1248 | A read-only single value file which exists on non-root |
| 1234 | cgroups. | 1249 | cgroups. |
| @@ -1433,6 +1448,24 @@ PAGE_SIZE multiple when read back. · 198 unmodified lines | |||
| 1433 | workingset_nodereclaim | 1448 | workingset_nodereclaim |
| 1434 | Number of times a shadow node has been reclaimed | 1449 | Number of times a shadow node has been reclaimed |
| 1435 | 1450 | ||
| 1451 | pgscan (npn) | ||
| 1452 | Amount of scanned pages (in an inactive LRU list) | ||
| 1453 | |||
| 1454 | pgsteal (npn) | ||
| 1455 | Amount of reclaimed pages | ||
| 1456 | |||
| 1457 | pgscan_kswapd (npn) | ||
| 1458 | Amount of scanned pages by kswapd (in an inactive LRU list) | ||
| 1459 | |||
| 1460 | pgscan_direct (npn) | ||
| 1461 | Amount of scanned pages directly (in an inactive LRU list) | ||
| 1462 | |||
| 1463 | pgsteal_kswapd (npn) | ||
| 1464 | Amount of reclaimed pages by kswapd | ||
| 1465 | |||
| 1466 | pgsteal_direct (npn) | ||
| 1467 | Amount of reclaimed pages directly | ||
| 1468 | |||
| 1436 | pgfault (npn) | 1469 | pgfault (npn) |
| 1437 | Total number of page faults incurred | 1470 | Total number of page faults incurred |
| 1438 | 1471 | ||
| @@ -1442,12 +1475,6 @@ PAGE_SIZE multiple when read back. · 3 unmodified lines | |||
| 1442 | pgrefill (npn) | 1475 | pgrefill (npn) |
| 1443 | Amount of scanned pages (in an active LRU list) | 1476 | Amount of scanned pages (in an active LRU list) |
| 1444 | 1477 | ||
| 1445 | pgscan (npn) | ||
| 1446 | Amount of scanned pages (in an inactive LRU list) | ||
| 1447 | |||
| 1448 | pgsteal (npn) | ||
| 1449 | Amount of reclaimed pages | ||
| 1450 | |||
| 1451 | pgactivate (npn) | 1478 | pgactivate (npn) |
| 1452 | Amount of pages moved to the active LRU list | 1479 | Amount of pages moved to the active LRU list |
| 1453 | 1480 | ||
| @@ -20,6 +20,7 @@ Constructor parameters: · 19 unmodified lines | |||
| 20 | size) | 20 | size) |
| 21 | 5. the number of optional parameters (the parameters with an argument | 21 | 5. the number of optional parameters (the parameters with an argument |
| 22 | count as two) | 22 | count as two) |
| 23 | |||
| 23 | start_sector n (default: 0) | 24 | start_sector n (default: 0) |
| 24 | offset from the start of cache device in 512-byte sectors | 25 | offset from the start of cache device in 512-byte sectors |
| 25 | high_watermark n (default: 50) | 26 | high_watermark n (default: 50) |
| @@ -74,20 +75,21 @@ Constructor parameters: · 48 unmodified lines | |||
| 74 | the origin volume in the last n milliseconds | 75 | the origin volume in the last n milliseconds |
| 75 | 76 | ||
| 76 | Status: | 77 | Status: |
| 78 | |||
| 77 | 1. error indicator - 0 if there was no error, otherwise error number | 79 | 1. error indicator - 0 if there was no error, otherwise error number |
| 78 | 2. the number of blocks | 80 | 2. the number of blocks |
| 79 | 3. the number of free blocks | 81 | 3. the number of free blocks |
| 80 | 4. the number of blocks under writeback | 82 | 4. the number of blocks under writeback |
| 81 | 5. the number of read requests | 83 | 5. the number of read blocks |
| 82 | 6. the number of read requests that hit the cache | 84 | 6. the number of read blocks that hit the cache |
| 83 | 7. the number of write requests | 85 | 7. the number of write blocks |
| 84 | 8. the number of write requests that hit uncommitted block | 86 | 8. the number of write blocks that hit uncommitted block |
| 85 | 9. the number of write requests that hit committed block | 87 | 9. the number of write blocks that hit committed block |
| 86 | 10. the number of write requests that bypass the cache | 88 | 10. the number of write blocks that bypass the cache |
| 87 | 11. the number of write requests that are allocated in the cache | 89 | 11. the number of write blocks that are allocated in the cache |
| 88 | 12. the number of write requests that are blocked on the freelist | 90 | 12. the number of write requests that are blocked on the freelist |
| 89 | 13. the number of flush requests | 91 | 13. the number of flush requests |
| 90 | 14. the number of discard requests | 92 | 14. the number of discarded blocks |
| 91 | 93 | ||
| 92 | Messages: | 94 | Messages: |
| 93 | flush | 95 | flush |
| @@ -7,10 +7,9 @@ This list is the Linux Device List, the official registry of allocated · 6 unmodified lines | |||
| 7 | device numbers and ``/dev`` directory nodes for the Linux operating | 7 | device numbers and ``/dev`` directory nodes for the Linux operating |
| 8 | system. | 8 | system. |
| 9 | 9 | ||
| 10 | The LaTeX version of this document is no longer maintained, nor is | 10 | The version of this document at lanana.org is no longer maintained. This |
| 11 | the document that used to reside at lanana.org. This version in the | 11 | version in the mainline Linux kernel is the master document. Updates |
| 12 | mainline Linux kernel is the master document. Updates shall be sent | 12 | shall be sent as patches to the kernel maintainers (see the |
| 13 | as patches to the kernel maintainers (see the | ||
| 14 | :ref:`Documentation/process/submitting-patches.rst <submittingpatches>` document). | 13 | :ref:`Documentation/process/submitting-patches.rst <submittingpatches>` document). |
| 15 | Specifically explore the sections titled "CHAR and MISC DRIVERS", and | 14 | Specifically explore the sections titled "CHAR and MISC DRIVERS", and |
| 16 | "BLOCK LAYER" in the MAINTAINERS file to find the right maintainers | 15 | "BLOCK LAYER" in the MAINTAINERS file to find the right maintainers |
| @@ -7,10 +7,10 @@ as a PE/COFF image, thereby convincing EFI firmware loaders to load · 6 unmodified lines | |||
| 7 | it as an EFI executable. The code that modifies the bzImage header, | 7 | it as an EFI executable. The code that modifies the bzImage header, |
| 8 | along with the EFI-specific entry point that the firmware loader | 8 | along with the EFI-specific entry point that the firmware loader |
| 9 | jumps to are collectively known as the "EFI boot stub", and live in | 9 | jumps to are collectively known as the "EFI boot stub", and live in |
| 10 | arch/x86/boot/header.S and arch/x86/boot/compressed/eboot.c, | 10 | arch/x86/boot/header.S and drivers/firmware/efi/libstub/x86-stub.c, |
| 11 | respectively. For ARM the EFI stub is implemented in | 11 | respectively. For ARM the EFI stub is implemented in |
| 12 | arch/arm/boot/compressed/efi-header.S and | 12 | arch/arm/boot/compressed/efi-header.S and |
| 13 | arch/arm/boot/compressed/efi-stub.c. EFI stub code that is shared | 13 | drivers/firmware/efi/libstub/arm32-stub.c. EFI stub code that is shared |
| 14 | between architectures is in drivers/firmware/efi/libstub. | 14 | between architectures is in drivers/firmware/efi/libstub. |
| 15 | 15 | ||
| 16 | For arm64, there is no compressed kernel support, so the Image itself | 16 | For arm64, there is no compressed kernel support, so the Image itself |
| @@ -230,6 +230,20 @@ The possible values in this file are: · 229 unmodified lines | |||
| 230 | * - 'Mitigation: Clear CPU buffers' | 230 | * - 'Mitigation: Clear CPU buffers' |
| 231 | - The processor is vulnerable and the CPU buffer clearing mitigation is | 231 | - The processor is vulnerable and the CPU buffer clearing mitigation is |
| 232 | enabled. | 232 | enabled. |
| 233 | * - 'Unknown: No mitigations' | ||
| 234 | - The processor vulnerability status is unknown because it is | ||
| 235 | out of Servicing period. Mitigation is not attempted. | ||
| 236 | |||
| 237 | Definitions: | ||
| 238 | ------------ | ||
| 239 | |||
| 240 | Servicing period: The process of providing functional and security updates to | ||
| 241 | Intel processors or platforms, utilizing the Intel Platform Update (IPU) | ||
| 242 | process or other similar mechanisms. | ||
| 243 | |||
| 244 | End of Servicing Updates (ESU): ESU is the date at which Intel will no | ||
| 245 | longer provide Servicing, such as through IPU or other similar update | ||
| 246 | processes. ESU dates will typically be aligned to end of quarter. | ||
| 233 | 247 | ||
| 234 | If the processor is vulnerable then the following information is appended to | 248 | If the processor is vulnerable then the following information is appended to |
| 235 | the above information: | 249 | the above information: |
| @@ -422,6 +422,14 @@ The possible values in this file are: · 421 unmodified lines | |||
| 422 | 'RSB filling' Protection of RSB on context switch enabled | 422 | 'RSB filling' Protection of RSB on context switch enabled |
| 423 | ============= =========================================== | 423 | ============= =========================================== |
| 424 | 424 | ||
| 425 | - EIBRS Post-barrier Return Stack Buffer (PBRSB) protection status: | ||
| 426 | |||
| 427 | =========================== ======================================================= | ||
| 428 | 'PBRSB-eIBRS: SW sequence' CPU is affected and protection of RSB on VMEXIT enabled | ||
| 429 | 'PBRSB-eIBRS: Vulnerable' CPU is vulnerable | ||
| 430 | 'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB | ||
| 431 | =========================== ======================================================= | ||
| 432 | |||
| 425 | Full mitigation might require a microcode update from the CPU | 433 | Full mitigation might require a microcode update from the CPU |
| 426 | vendor. When the necessary microcode is not available, the kernel will | 434 | vendor. When the necessary microcode is not available, the kernel will |
| 427 | report vulnerability. | 435 | report vulnerability. |
| @@ -400,6 +400,12 @@ · 399 unmodified lines | |||
| 400 | arm64.nomte [ARM64] Unconditionally disable Memory Tagging Extension | 400 | arm64.nomte [ARM64] Unconditionally disable Memory Tagging Extension |
| 401 | support | 401 | support |
| 402 | 402 | ||
| 403 | arm64.nosve [ARM64] Unconditionally disable Scalable Vector | ||
| 404 | Extension support | ||
| 405 | |||
| 406 | arm64.nosme [ARM64] Unconditionally disable Scalable Matrix | ||
| 407 | Extension support | ||
| 408 | |||
| 403 | ataflop= [HW,M68k] | 409 | ataflop= [HW,M68k] |
| 404 | 410 | ||
| 405 | atarimouse= [HW,MOUSE] Atari Mouse | 411 | atarimouse= [HW,MOUSE] Atari Mouse |
| @@ -550,7 +556,7 @@ · 144 unmodified lines | |||
| 550 | nosocket -- Disable socket memory accounting. | 556 | nosocket -- Disable socket memory accounting. |
| 551 | nokmem -- Disable kernel memory accounting. | 557 | nokmem -- Disable kernel memory accounting. |
| 552 | 558 | ||
| 553 | checkreqprot [SELINUX] Set initial checkreqprot flag value. | 559 | checkreqprot= [SELINUX] Set initial checkreqprot flag value. |
| 554 | Format: { "0" | "1" } | 560 | Format: { "0" | "1" } |
| 555 | See security/selinux/Kconfig help text. | 561 | See security/selinux/Kconfig help text. |
| 556 | 0 -- check protection applied by kernel (includes | 562 | 0 -- check protection applied by kernel (includes |
| @@ -1152,8 +1158,12 @@ · 595 unmodified lines | |||
| 1152 | nopku [X86] Disable Memory Protection Keys CPU feature found | 1158 | nopku [X86] Disable Memory Protection Keys CPU feature found |
| 1153 | in some Intel CPUs. | 1159 | in some Intel CPUs. |
| 1154 | 1160 | ||
| 1155 | <module>.async_probe [KNL] | 1161 | <module>.async_probe[=<bool>] [KNL] |
| 1156 | Enable asynchronous probe on this module. | 1162 | If no <bool> value is specified or if the value |
| 1163 | specified is not a valid <bool>, enable asynchronous | ||
| 1164 | probe on this module. Otherwise, enable/disable | ||
| 1165 | asynchronous probe on this module as indicated by the | ||
| 1166 | <bool> value. See also: module.async_probe | ||
| 1157 | 1167 | ||
| 1158 | early_ioremap_debug [KNL] | 1168 | early_ioremap_debug [KNL] |
| 1159 | Enable debug messages in early_ioremap support. This | 1169 | Enable debug messages in early_ioremap support. This |
| @@ -1439,7 +1449,7 @@ · 279 unmodified lines | |||
| 1439 | (in particular on some ATI chipsets). | 1449 | (in particular on some ATI chipsets). |
| 1440 | The kernel tries to set a reasonable default. | 1450 | The kernel tries to set a reasonable default. |
| 1441 | 1451 | ||
| 1442 | enforcing [SELINUX] Set initial enforcing status. | 1452 | enforcing= [SELINUX] Set initial enforcing status. |
| 1443 | Format: {"0" | "1"} | 1453 | Format: {"0" | "1"} |
| 1444 | See security/selinux/Kconfig help text. | 1454 | See security/selinux/Kconfig help text. |
| 1445 | 0 -- permissive (log only, no denials). | 1455 | 0 -- permissive (log only, no denials). |
| @@ -1667,6 +1677,19 @@ · 221 unmodified lines | |||
| 1667 | 1677 | ||
| 1668 | hlt [BUGS=ARM,SH] | 1678 | hlt [BUGS=ARM,SH] |
| 1669 | 1679 | ||
| 1680 | hostname= [KNL] Set the hostname (aka UTS nodename). | ||
| 1681 | Format: <string> | ||
| 1682 | This allows setting the system's hostname during early | ||
| 1683 | startup. This sets the name returned by gethostname. | ||
| 1684 | Using this parameter to set the hostname makes it | ||
| 1685 | possible to ensure the hostname is correctly set before | ||
| 1686 | any userspace processes run, avoiding the possibility | ||
| 1687 | that a process may call gethostname before the hostname | ||
| 1688 | has been explicitly set, resulting in the calling | ||
| 1689 | process getting an incorrect result. The string must | ||
| 1690 | not exceed the maximum allowed hostname length (usually | ||
| 1691 | 64 characters) and will be truncated otherwise. | ||
| 1692 | |||
| 1670 | hpet= [X86-32,HPET] option to control HPET usage | 1693 | hpet= [X86-32,HPET] option to control HPET usage |
| 1671 | Format: { enable (default) | disable | force | | 1694 | Format: { enable (default) | disable | force | |
| 1672 | verbose } | 1695 | verbose } |
| @@ -1712,19 +1735,22 @@ · 39 unmodified lines | |||
| 1712 | hugetlb_free_vmemmap= | 1735 | hugetlb_free_vmemmap= |
| 1713 | [KNL] Reguires CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP | 1736 | [KNL] Reguires CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP |
| 1714 | enabled. | 1737 | enabled. |
| 1738 | Control if HugeTLB Vmemmap Optimization (HVO) is enabled. | ||
| 1715 | Allows heavy hugetlb users to free up some more | 1739 | Allows heavy hugetlb users to free up some more |
| 1716 | memory (7 * PAGE_SIZE for each 2MB hugetlb page). | 1740 | memory (7 * PAGE_SIZE for each 2MB hugetlb page). |
| 1717 | Format: { [oO][Nn]/Y/y/1 | [oO][Ff]/N/n/0 (default) } | 1741 | Format: { on | off (default) } |
| 1718 | 1742 | ||
| 1719 | [oO][Nn]/Y/y/1: enable the feature | 1743 | on: enable HVO |
| 1720 | [oO][Ff]/N/n/0: disable the feature | 1744 | off: disable HVO |
| 1721 | 1745 | ||
| 1722 | Built with CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y, | 1746 | Built with CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y, |
| 1723 | the default is on. | 1747 | the default is on. |
| 1724 | 1748 | ||
| 1725 | This is not compatible with memory_hotplug.memmap_on_memory. | 1749 | Note that the vmemmap pages may be allocated from the added |
| 1726 | If both parameters are enabled, hugetlb_free_vmemmap takes | 1750 | memory block itself when memory_hotplug.memmap_on_memory is |
| 1727 | precedence over memory_hotplug.memmap_on_memory. | 1751 | enabled, those vmemmap pages cannot be optimized even if this |
| 1752 | feature is enabled. Other vmemmap pages not allocated from | ||
| 1753 | the added memory block itself do not be affected. | ||
| 1728 | 1754 | ||
| 1729 | hung_task_panic= | 1755 | hung_task_panic= |
| 1730 | [KNL] Should the hung task detector generate panics. | 1756 | [KNL] Should the hung task detector generate panics. |
| @@ -2266,23 +2292,39 @@ · 535 unmodified lines | |||
| 2266 | 2292 | ||
| 2267 | ivrs_ioapic [HW,X86-64] | 2293 | ivrs_ioapic [HW,X86-64] |
| 2268 | Provide an override to the IOAPIC-ID<->DEVICE-ID | 2294 | Provide an override to the IOAPIC-ID<->DEVICE-ID |
| 2269 | mapping provided in the IVRS ACPI table. For | 2295 | mapping provided in the IVRS ACPI table. |
| 2270 | example, to map IOAPIC-ID decimal 10 to | 2296 | By default, PCI segment is 0, and can be omitted. |
| 2271 | PCI device 00:14.0 write the parameter as: | 2297 | For example: |
| 2298 | * To map IOAPIC-ID decimal 10 to PCI device 00:14.0 | ||
| 2299 | write the parameter as: | ||
| 2272 | ivrs_ioapic[10]=00:14.0 | 2300 | ivrs_ioapic[10]=00:14.0 |
| 2301 | * To map IOAPIC-ID decimal 10 to PCI segment 0x1 and | ||
| 2302 | PCI device 00:14.0 write the parameter as: | ||
| 2303 | ivrs_ioapic[10]=0001:00:14.0 | ||
| 2273 | 2304 | ||
| 2274 | ivrs_hpet [HW,X86-64] | 2305 | ivrs_hpet [HW,X86-64] |
| 2275 | Provide an override to the HPET-ID<->DEVICE-ID | 2306 | Provide an override to the HPET-ID<->DEVICE-ID |
| 2276 | mapping provided in the IVRS ACPI table. For | 2307 | mapping provided in the IVRS ACPI table. |
| 2277 | example, to map HPET-ID decimal 0 to | 2308 | By default, PCI segment is 0, and can be omitted. |
| 2278 | PCI device 00:14.0 write the parameter as: | 2309 | For example: |
| 2310 | * To map HPET-ID decimal 0 to PCI device 00:14.0 | ||
| 2311 | write the parameter as: | ||
| 2279 | ivrs_hpet[0]=00:14.0 | 2312 | ivrs_hpet[0]=00:14.0 |
| 2313 | * To map HPET-ID decimal 10 to PCI segment 0x1 and | ||
| 2314 | PCI device 00:14.0 write the parameter as: | ||
| 2315 | ivrs_ioapic[10]=0001:00:14.0 | ||
| 2280 | 2316 | ||
| 2281 | ivrs_acpihid [HW,X86-64] | 2317 | ivrs_acpihid [HW,X86-64] |
| 2282 | Provide an override to the ACPI-HID:UID<->DEVICE-ID | 2318 | Provide an override to the ACPI-HID:UID<->DEVICE-ID |
| 2283 | mapping provided in the IVRS ACPI table. For | 2319 | mapping provided in the IVRS ACPI table. |
| 2284 | example, to map UART-HID:UID AMD0020:0 to | 2320 | |
| 2285 | PCI device 00:14.5 write the parameter as: | 2321 | For example, to map UART-HID:UID AMD0020:0 to |
| 2322 | PCI segment 0x1 and PCI device ID 00:14.5, | ||
| 2323 | write the parameter as: | ||
| 2324 | ivrs_acpihid[0001:00:14.5]=AMD0020:0 | ||
| 2325 | |||
| 2326 | By default, PCI segment is 0, and can be omitted. | ||
| 2327 | For example, PCI device 00:14.5 write the parameter as: | ||
| 2286 | ivrs_acpihid[00:14.5]=AMD0020:0 | 2328 | ivrs_acpihid[00:14.5]=AMD0020:0 |
| 2287 | 2329 | ||
| 2288 | js= [HW,JOY] Analog joystick | 2330 | js= [HW,JOY] Analog joystick |
| @@ -2418,8 +2460,7 @@ · 129 unmodified lines | |||
| 2418 | the KVM_CLEAR_DIRTY ioctl, and only for the pages being | 2460 | the KVM_CLEAR_DIRTY ioctl, and only for the pages being |
| 2419 | cleared. | 2461 | cleared. |
| 2420 | 2462 | ||
| 2421 | Eager page splitting currently only supports splitting | 2463 | Eager page splitting is only supported when kvm.tdp_mmu=Y. |
| 2422 | huge pages mapped by the TDP MMU. | ||
| 2423 | 2464 | ||
| 2424 | Default is Y (on). | 2465 | Default is Y (on). |
| 2425 | 2466 | ||
| @@ -3068,10 +3109,12 @@ · 642 unmodified lines | |||
| 3068 | [KNL,X86,ARM] Boolean flag to enable this feature. | 3109 | [KNL,X86,ARM] Boolean flag to enable this feature. |
| 3069 | Format: {on | off (default)} | 3110 | Format: {on | off (default)} |
| 3070 | When enabled, runtime hotplugged memory will | 3111 | When enabled, runtime hotplugged memory will |
| 3071 | allocate its internal metadata (struct pages) | 3112 | allocate its internal metadata (struct pages, |
| 3072 | from the hotadded memory which will allow to | 3113 | those vmemmap pages cannot be optimized even |
| 3073 | hotadd a lot of memory without requiring | 3114 | if hugetlb_free_vmemmap is enabled) from the |
| 3074 | additional memory to do so. | 3115 | hotadded memory which will allow to hotadd a |
| 3116 | lot of memory without requiring additional | ||
| 3117 | memory to do so. | ||
| 3075 | This feature is disabled by default because it | 3118 | This feature is disabled by default because it |
| 3076 | has some implication on large (e.g. GB) | 3119 | has some implication on large (e.g. GB) |
| 3077 | allocations in some configurations (e.g. small | 3120 | allocations in some configurations (e.g. small |
| @@ -3081,10 +3124,6 @@ · 3 unmodified lines | |||
| 3081 | Note that even when enabled, there are a few cases where | 3124 | Note that even when enabled, there are a few cases where |
| 3082 | the feature is not effective. | 3125 | the feature is not effective. |
| 3083 | 3126 | ||
| 3084 | This is not compatible with hugetlb_free_vmemmap. If | ||
| 3085 | both parameters are enabled, hugetlb_free_vmemmap takes | ||
| 3086 | precedence over memory_hotplug.memmap_on_memory. | ||
| 3087 | |||
| 3088 | memtest= [KNL,X86,ARM,M68K,PPC,RISCV] Enable memtest | 3127 | memtest= [KNL,X86,ARM,M68K,PPC,RISCV] Enable memtest |
| 3089 | Format: <integer> | 3128 | Format: <integer> |
| 3090 | default : 0 <disable> | 3129 | default : 0 <disable> |
| @@ -3103,7 +3142,7 @@ · 12 unmodified lines | |||
| 3103 | mem_encrypt=on: Activate SME | 3142 | mem_encrypt=on: Activate SME |
| 3104 | mem_encrypt=off: Do not activate SME | 3143 | mem_encrypt=off: Do not activate SME |
| 3105 | 3144 | ||
| 3106 | Refer to Documentation/virt/kvm/amd-memory-encryption.rst | 3145 | Refer to Documentation/virt/kvm/x86/amd-memory-encryption.rst |
| 3107 | for details on when memory encryption can be activated. | 3146 | for details on when memory encryption can be activated. |
| 3108 | 3147 | ||
| 3109 | mem_sleep_default= [SUSPEND] Default system suspend mode: | 3148 | mem_sleep_default= [SUSPEND] Default system suspend mode: |
| @@ -3161,7 +3200,7 @@ · 51 unmodified lines | |||
| 3161 | improves system performance, but it may also | 3200 | improves system performance, but it may also |
| 3162 | expose users to several CPU vulnerabilities. | 3201 | expose users to several CPU vulnerabilities. |
| 3163 | Equivalent to: nopti [X86,PPC] | 3202 | Equivalent to: nopti [X86,PPC] |
| 3164 | kpti=0 [ARM64] | 3203 | if nokaslr then kpti=0 [ARM64] |
| 3165 | nospectre_v1 [X86,PPC] | 3204 | nospectre_v1 [X86,PPC] |
| 3166 | nobp=0 [S390] | 3205 | nobp=0 [S390] |
| 3167 | nospectre_v2 [X86,PPC,S390,ARM64] | 3206 | nospectre_v2 [X86,PPC,S390,ARM64] |
| @@ -3176,6 +3215,7 @@ · 8 unmodified lines | |||
| 3176 | no_entry_flush [PPC] | 3215 | no_entry_flush [PPC] |
| 3177 | no_uaccess_flush [PPC] | 3216 | no_uaccess_flush [PPC] |
| 3178 | mmio_stale_data=off [X86] | 3217 | mmio_stale_data=off [X86] |
| 3218 | retbleed=off [X86] | ||
| 3179 | 3219 | ||
| 3180 | Exceptions: | 3220 | Exceptions: |
| 3181 | This does not have any effect on | 3221 | This does not have any effect on |
| @@ -3198,6 +3238,7 @@ · 16 unmodified lines | |||
| 3198 | mds=full,nosmt [X86] | 3238 | mds=full,nosmt [X86] |
| 3199 | tsx_async_abort=full,nosmt [X86] | 3239 | tsx_async_abort=full,nosmt [X86] |
| 3200 | mmio_stale_data=full,nosmt [X86] | 3240 | mmio_stale_data=full,nosmt [X86] |
| 3241 | retbleed=auto,nosmt [X86] | ||
| 3201 | 3242 | ||
| 3202 | mminit_loglevel= | 3243 | mminit_loglevel= |
| 3203 | [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this | 3244 | [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this |
| @@ -3241,6 +3282,15 @@ · 37 unmodified lines | |||
| 3241 | For details see: | 3282 | For details see: |
| 3242 | Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst | 3283 | Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst |
| 3243 | 3284 | ||
| 3285 | module.async_probe=<bool> | ||
| 3286 | [KNL] When set to true, modules will use async probing | ||
| 3287 | by default. To enable/disable async probing for a | ||
| 3288 | specific module, use the module specific control that | ||
| 3289 | is documented under <module>.async_probe. When both | ||
| 3290 | module.async_probe and <module>.async_probe are | ||
| 3291 | specified, <module>.async_probe takes precedence for | ||
| 3292 | the specific module. | ||
| 3293 | |||
| 3244 | module.sig_enforce | 3294 | module.sig_enforce |
| 3245 | [KNL] When CONFIG_MODULE_SIG is set, this means that | 3295 | [KNL] When CONFIG_MODULE_SIG is set, this means that |
| 3246 | modules without (valid) signatures will fail to load. | 3296 | modules without (valid) signatures will fail to load. |
| @@ -3530,9 +3580,6 @@ · 283 unmodified lines | |||
| 3530 | 3580 | ||
| 3531 | noautogroup Disable scheduler automatic task group creation. | 3581 | noautogroup Disable scheduler automatic task group creation. |
| 3532 | 3582 | ||
| 3533 | nobats [PPC] Do not use BATs for mapping kernel lowmem | ||
| 3534 | on "Classic" PPC cores. | ||
| 3535 | |||
| 3536 | nocache [ARM] | 3583 | nocache [ARM] |
| 3537 | 3584 | ||
| 3538 | nodsp [SH] Disable hardware DSP at boot time. | 3585 | nodsp [SH] Disable hardware DSP at boot time. |
| @@ -3659,6 +3706,9 @@ · 120 unmodified lines | |||
| 3659 | just as if they had also been called out in the | 3706 | just as if they had also been called out in the |
| 3660 | rcu_nocbs= boot parameter. | 3707 | rcu_nocbs= boot parameter. |
| 3661 | 3708 | ||
| 3709 | Note that this argument takes precedence over | ||
| 3710 | the CONFIG_RCU_NOCB_CPU_DEFAULT_ALL option. | ||
| 3711 | |||
| 3662 | noiotrap [SH] Disables trapped I/O port accesses. | 3712 | noiotrap [SH] Disables trapped I/O port accesses. |
| 3663 | 3713 | ||
| 3664 | noirqdebug [X86-32] Disables the code which attempts to detect and | 3714 | noirqdebug [X86-32] Disables the code which attempts to detect and |
| @@ -3699,9 +3749,6 @@ · 34 unmodified lines | |||
| 3699 | 3749 | ||
| 3700 | nolapic_timer [X86-32,APIC] Do not use the local APIC timer. | 3750 | nolapic_timer [X86-32,APIC] Do not use the local APIC timer. |
| 3701 | 3751 | ||
| 3702 | noltlbs [PPC] Do not use large page/tlb entries for kernel | ||
| 3703 | lowmem mapping on PPC40x and PPC8xx | ||
| 3704 | |||
| 3705 | nomca [IA-64] Disable machine check abort handling | 3752 | nomca [IA-64] Disable machine check abort handling |
| 3706 | 3753 | ||
| 3707 | nomce [X86-32] Disable Machine Check Exception | 3754 | nomce [X86-32] Disable Machine Check Exception |
| @@ -3733,11 +3780,6 @@ · 25 unmodified lines | |||
| 3733 | noreplace-smp [X86-32,SMP] Don't replace SMP instructions | 3780 | noreplace-smp [X86-32,SMP] Don't replace SMP instructions |
| 3734 | with UP alternatives | 3781 | with UP alternatives |
| 3735 | 3782 | ||
| 3736 | nordrand [X86] Disable kernel use of the RDRAND and | ||
| 3737 | RDSEED instructions even if they are supported | ||
| 3738 | by the processor. RDRAND and RDSEED are still | ||
| 3739 | available to user space applications. | ||
| 3740 | |||
| 3741 | noresume [SWSUSP] Disables resume and restores original swap | 3783 | noresume [SWSUSP] Disables resume and restores original swap |
| 3742 | space. | 3784 | space. |
| 3743 | 3785 | ||
| @@ -4557,6 +4599,9 @@ · 813 unmodified lines | |||
| 4557 | no-callback mode from boot but the mode may be | 4599 | no-callback mode from boot but the mode may be |
| 4558 | toggled at runtime via cpusets. | 4600 | toggled at runtime via cpusets. |
| 4559 | 4601 | ||
| 4602 | Note that this argument takes precedence over | ||
| 4603 | the CONFIG_RCU_NOCB_CPU_DEFAULT_ALL option. | ||
| 4604 | |||
| 4560 | rcu_nocb_poll [KNL] | 4605 | rcu_nocb_poll [KNL] |
| 4561 | Rather than requiring that offloaded CPUs | 4606 | Rather than requiring that offloaded CPUs |
| 4562 | (specified by rcu_nocbs= above) explicitly | 4607 | (specified by rcu_nocbs= above) explicitly |
| @@ -4666,6 +4711,34 @@ · 103 unmodified lines | |||
| 4666 | When RCU_NOCB_CPU is set, also adjust the | 4711 | When RCU_NOCB_CPU is set, also adjust the |
| 4667 | priority of NOCB callback kthreads. | 4712 | priority of NOCB callback kthreads. |
| 4668 | 4713 | ||
| 4714 | rcutree.rcu_divisor= [KNL] | ||
| 4715 | Set the shift-right count to use to compute | ||
| 4716 | the callback-invocation batch limit bl from | ||
| 4717 | the number of callbacks queued on this CPU. | ||
| 4718 | The result will be bounded below by the value of | ||
| 4719 | the rcutree.blimit kernel parameter. Every bl | ||
| 4720 | callbacks, the softirq handler will exit in | ||
| 4721 | order to allow the CPU to do other work. | ||
| 4722 | |||
| 4723 | Please note that this callback-invocation batch | ||
| 4724 | limit applies only to non-offloaded callback | ||
| 4725 | invocation. Offloaded callbacks are instead | ||
| 4726 | invoked in the context of an rcuoc kthread, which | ||
| 4727 | scheduler will preempt as it does any other task. | ||
| 4728 | |||
| 4729 | rcutree.nocb_nobypass_lim_per_jiffy= [KNL] | ||
| 4730 | On callback-offloaded (rcu_nocbs) CPUs, | ||
| 4731 | RCU reduces the lock contention that would | ||
| 4732 | otherwise be caused by callback floods through | ||
| 4733 | use of the ->nocb_bypass list. However, in the | ||
| 4734 | common non-flooded case, RCU queues directly to | ||
| 4735 | the main ->cblist in order to avoid the extra | ||
| 4736 | overhead of the ->nocb_bypass list and its lock. | ||
| 4737 | But if there are too many callbacks queued during | ||
| 4738 | a single jiffy, RCU pre-queues the callbacks into | ||
| 4739 | the ->nocb_bypass queue. The definition of "too | ||
| 4740 | many" is supplied by this kernel boot parameter. | ||
| 4741 | |||
| 4669 | rcutree.rcu_nocb_gp_stride= [KNL] | 4742 | rcutree.rcu_nocb_gp_stride= [KNL] |
| 4670 | Set the number of NOCB callback kthreads in | 4743 | Set the number of NOCB callback kthreads in |
| 4671 | each group, which defaults to the square root | 4744 | each group, which defaults to the square root |
| @@ -5197,6 +5270,43 @@ · 525 unmodified lines | |||
| 5197 | 5270 | ||
| 5198 | retain_initrd [RAM] Keep initrd memory after extraction | 5271 | retain_initrd [RAM] Keep initrd memory after extraction |
| 5199 | 5272 | ||
| 5273 | retbleed= [X86] Control mitigation of RETBleed (Arbitrary | ||
| 5274 | Speculative Code Execution with Return Instructions) | ||
| 5275 | vulnerability. | ||
| 5276 | |||
| 5277 | AMD-based UNRET and IBPB mitigations alone do not stop | ||
| 5278 | sibling threads from influencing the predictions of other | ||
| 5279 | sibling threads. For that reason, STIBP is used on pro- | ||
| 5280 | cessors that support it, and mitigate SMT on processors | ||
| 5281 | that don't. | ||
| 5282 | |||
| 5283 | off - no mitigation | ||
| 5284 | auto - automatically select a migitation | ||
| 5285 | auto,nosmt - automatically select a mitigation, | ||
| 5286 | disabling SMT if necessary for | ||
| 5287 | the full mitigation (only on Zen1 | ||
| 5288 | and older without STIBP). | ||
| 5289 | ibpb - On AMD, mitigate short speculation | ||
| 5290 | windows on basic block boundaries too. | ||
| 5291 | Safe, highest perf impact. It also | ||
| 5292 | enables STIBP if present. Not suitable | ||
| 5293 | on Intel. | ||
| 5294 | ibpb,nosmt - Like "ibpb" above but will disable SMT | ||
| 5295 | when STIBP is not available. This is | ||
| 5296 | the alternative for systems which do not | ||
| 5297 | have STIBP. | ||
| 5298 | unret - Force enable untrained return thunks, | ||
| 5299 | only effective on AMD f15h-f17h based | ||
| 5300 | systems. | ||
| 5301 | unret,nosmt - Like unret, but will disable SMT when STIBP | ||
| 5302 | is not available. This is the alternative for | ||
| 5303 | systems which do not have STIBP. | ||
| 5304 | |||
| 5305 | Selecting 'auto' will choose a mitigation method at run | ||
| 5306 | time according to the CPU. | ||
| 5307 | |||
| 5308 | Not specifying this option is equivalent to retbleed=auto. | ||
| 5309 | |||
| 5200 | rfkill.default_state= | 5310 | rfkill.default_state= |
| 5201 | 0 "airplane mode". All wifi, bluetooth, wimax, gps, fm, | 5311 | 0 "airplane mode". All wifi, bluetooth, wimax, gps, fm, |
| 5202 | etc. communication is blocked by default. | 5312 | etc. communication is blocked by default. |
| @@ -5221,6 +5331,8 @@ · 18 unmodified lines | |||
| 5221 | rodata= [KNL] | 5331 | rodata= [KNL] |
| 5222 | on Mark read-only kernel memory as read-only (default). | 5332 | on Mark read-only kernel memory as read-only (default). |
| 5223 | off Leave read-only kernel memory writable for debugging. | 5333 | off Leave read-only kernel memory writable for debugging. |
| 5334 | full Mark read-only kernel memory and aliases as read-only | ||
| 5335 | [arm64] | ||
| 5224 | 5336 | ||
| 5225 | rockchip.usb_uart | 5337 | rockchip.usb_uart |
| 5226 | Enable the uart passthrough on the designated usb port | 5338 | Enable the uart passthrough on the designated usb port |
| @@ -5442,7 +5554,7 @@ · 215 unmodified lines | |||
| 5442 | cache (risks via metadata attacks are mostly | 5554 | cache (risks via metadata attacks are mostly |
| 5443 | unchanged). Debug options disable merging on their | 5555 | unchanged). Debug options disable merging on their |
| 5444 | own. | 5556 | own. |
| 5445 | For more information see Documentation/vm/slub.rst. | 5557 | For more information see Documentation/mm/slub.rst. |
| 5446 | 5558 | ||
| 5447 | slab_max_order= [MM, SLAB] | 5559 | slab_max_order= [MM, SLAB] |
| 5448 | Determines the maximum allowed order for slabs. | 5560 | Determines the maximum allowed order for slabs. |
| @@ -5456,13 +5568,13 @@ · 7 unmodified lines | |||
| 5456 | slub_debug can create guard zones around objects and | 5568 | slub_debug can create guard zones around objects and |
| 5457 | may poison objects when not in use. Also tracks the | 5569 | may poison objects when not in use. Also tracks the |
| 5458 | last alloc / free. For more information see | 5570 | last alloc / free. For more information see |
| 5459 | Documentation/vm/slub.rst. | 5571 | Documentation/mm/slub.rst. |
| 5460 | 5572 | ||
| 5461 | slub_max_order= [MM, SLUB] | 5573 | slub_max_order= [MM, SLUB] |
| 5462 | Determines the maximum allowed order for slabs. | 5574 | Determines the maximum allowed order for slabs. |
| 5463 | A high setting may cause OOMs due to memory | 5575 | A high setting may cause OOMs due to memory |
| 5464 | fragmentation. For more information see | 5576 | fragmentation. For more information see |
| 5465 | Documentation/vm/slub.rst. | 5577 | Documentation/mm/slub.rst. |
| 5466 | 5578 | ||
| 5467 | slub_min_objects= [MM, SLUB] | 5579 | slub_min_objects= [MM, SLUB] |
| 5468 | The minimum number of objects per slab. SLUB will | 5580 | The minimum number of objects per slab. SLUB will |
| @@ -5471,12 +5583,12 @@ · 2 unmodified lines | |||
| 5471 | the number of objects indicated. The higher the number | 5583 | the number of objects indicated. The higher the number |
| 5472 | of objects the smaller the overhead of tracking slabs | 5584 | of objects the smaller the overhead of tracking slabs |
| 5473 | and the less frequently locks need to be acquired. | 5585 | and the less frequently locks need to be acquired. |
| 5474 | For more information see Documentation/vm/slub.rst. | 5586 | For more information see Documentation/mm/slub.rst. |
| 5475 | 5587 | ||
| 5476 | slub_min_order= [MM, SLUB] | 5588 | slub_min_order= [MM, SLUB] |
| 5477 | Determines the minimum page order for slabs. Must be | 5589 | Determines the minimum page order for slabs. Must be |
| 5478 | lower than slub_max_order. | 5590 | lower than slub_max_order. |
| 5479 | For more information see Documentation/vm/slub.rst. | 5591 | For more information see Documentation/mm/slub.rst. |
| 5480 | 5592 | ||
| 5481 | slub_merge [MM, SLUB] | 5593 | slub_merge [MM, SLUB] |
| 5482 | Same with slab_merge. | 5594 | Same with slab_merge. |
| @@ -5568,6 +5680,7 @@ · 85 unmodified lines | |||
| 5568 | eibrs - enhanced IBRS | 5680 | eibrs - enhanced IBRS |
| 5569 | eibrs,retpoline - enhanced IBRS + Retpolines | 5681 | eibrs,retpoline - enhanced IBRS + Retpolines |
| 5570 | eibrs,lfence - enhanced IBRS + LFENCE | 5682 | eibrs,lfence - enhanced IBRS + LFENCE |
| 5683 | ibrs - use IBRS to protect kernel | ||
| 5571 | 5684 | ||
| 5572 | Not specifying this option is equivalent to | 5685 | Not specifying this option is equivalent to |
| 5573 | spectre_v2=auto. | 5686 | spectre_v2=auto. |
| @@ -5771,6 +5884,24 @@ · 197 unmodified lines | |||
| 5771 | expediting. Set to zero to disable automatic | 5884 | expediting. Set to zero to disable automatic |
| 5772 | expediting. | 5885 | expediting. |
| 5773 | 5886 | ||
| 5887 | srcutree.srcu_max_nodelay [KNL] | ||
| 5888 | Specifies the number of no-delay instances | ||
| 5889 | per jiffy for which the SRCU grace period | ||
| 5890 | worker thread will be rescheduled with zero | ||
| 5891 | delay. Beyond this limit, worker thread will | ||
| 5892 | be rescheduled with a sleep delay of one jiffy. | ||
| 5893 | |||
| 5894 | srcutree.srcu_max_nodelay_phase [KNL] | ||
| 5895 | Specifies the per-grace-period phase, number of | ||
| 5896 | non-sleeping polls of readers. Beyond this limit, | ||
| 5897 | grace period worker thread will be rescheduled | ||
| 5898 | with a sleep delay of one jiffy, between each | ||
| 5899 | rescan of the readers, for a grace period phase. | ||
| 5900 | |||
| 5901 | srcutree.srcu_retry_check_delay [KNL] | ||
| 5902 | Specifies number of microseconds of non-sleeping | ||
| 5903 | delay between each non-sleeping poll of readers. | ||
| 5904 | |||
| 5774 | srcutree.small_contention_lim [KNL] | 5905 | srcutree.small_contention_lim [KNL] |
| 5775 | Specifies the number of update-side contention | 5906 | Specifies the number of update-side contention |
| 5776 | events per jiffy will be tolerated before | 5907 | events per jiffy will be tolerated before |
| @@ -5904,8 +6035,11 @@ · 127 unmodified lines | |||
| 5904 | it if 0 is given (See Documentation/admin-guide/cgroup-v1/memory.rst) | 6035 | it if 0 is given (See Documentation/admin-guide/cgroup-v1/memory.rst) |
| 5905 | 6036 | ||
| 5906 | swiotlb= [ARM,IA-64,PPC,MIPS,X86] | 6037 | swiotlb= [ARM,IA-64,PPC,MIPS,X86] |
| 5907 | Format: { <int> | force | noforce } | 6038 | Format: { <int> [,<int>] | force | noforce } |
| 5908 | <int> -- Number of I/O TLB slabs | 6039 | <int> -- Number of I/O TLB slabs |
| 6040 | <int> -- Second integer after comma. Number of swiotlb | ||
| 6041 | areas with their own lock. Will be rounded up | ||
| 6042 | to a power of 2. | ||
| 5909 | force -- force using of bounce buffers even if they | 6043 | force -- force using of bounce buffers even if they |
| 5910 | wouldn't be automatically used by the kernel | 6044 | wouldn't be automatically used by the kernel |
| 5911 | noforce -- Never use bounce buffers (for debugging) | 6045 | noforce -- Never use bounce buffers (for debugging) |
| @@ -5,9 +5,13 @@ digraph board { · 4 unmodified lines | |||
| 5 | n00000001 [label="{{} | Sensor A\n/dev/v4l-subdev0 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green] | 5 | n00000001 [label="{{} | Sensor A\n/dev/v4l-subdev0 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green] |
| 6 | n00000001:port0 -> n00000005:port0 [style=bold] | 6 | n00000001:port0 -> n00000005:port0 [style=bold] |
| 7 | n00000001:port0 -> n0000000b [style=bold] | 7 | n00000001:port0 -> n0000000b [style=bold] |
| 8 | n00000001 -> n00000002 | ||
| 9 | n00000002 [label="{{} | Lens A\n/dev/v4l-subdev5 | {<port0>}}", shape=Mrecord, style=filled, fillcolor=green] | ||
| 8 | n00000003 [label="{{} | Sensor B\n/dev/v4l-subdev1 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green] | 10 | n00000003 [label="{{} | Sensor B\n/dev/v4l-subdev1 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green] |
| 9 | n00000003:port0 -> n00000008:port0 [style=bold] | 11 | n00000003:port0 -> n00000008:port0 [style=bold] |
| 10 | n00000003:port0 -> n0000000f [style=bold] | 12 | n00000003:port0 -> n0000000f [style=bold] |
| 13 | n00000003 -> n00000004 | ||
| 14 | n00000004 [label="{{} | Lens B\n/dev/v4l-subdev6 | {<port0>}}", shape=Mrecord, style=filled, fillcolor=green] | ||
| 11 | n00000005 [label="{{<port0> 0} | Debayer A\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] | 15 | n00000005 [label="{{<port0> 0} | Debayer A\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] |
| 12 | n00000005:port1 -> n00000015:port0 | 16 | n00000005:port1 -> n00000015:port0 |
| 13 | n00000008 [label="{{<port0> 0} | Debayer B\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] | 17 | n00000008 [label="{{<port0> 0} | Debayer B\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] |
| @@ -53,6 +53,25 @@ vimc-sensor: · 52 unmodified lines | |||
| 53 | 53 | ||
| 54 | * 1 Pad source | 54 | * 1 Pad source |
| 55 | 55 | ||
| 56 | vimc-lens: | ||
| 57 | Ancillary lens for a sensor. Supports auto focus control. Linked to | ||
| 58 | a vimc-sensor using an ancillary link. The lens supports FOCUS_ABSOLUTE | ||
| 59 | control. | ||
| 60 | |||
| 61 | .. code-block:: bash | ||
| 62 | |||
| 63 | media-ctl -p | ||
| 64 | ... | ||
| 65 | - entity 28: Lens A (0 pad, 0 link) | ||
| 66 | type V4L2 subdev subtype Lens flags 0 | ||
| 67 | device node name /dev/v4l-subdev6 | ||
| 68 | - entity 29: Lens B (0 pad, 0 link) | ||
| 69 | type V4L2 subdev subtype Lens flags 0 | ||
| 70 | device node name /dev/v4l-subdev7 | ||
| 71 | v4l2-ctl -d /dev/v4l-subdev7 -C focus_absolute | ||
| 72 | focus_absolute: 0 | ||
| 73 | |||
| 74 | |||
| 56 | vimc-debayer: | 75 | vimc-debayer: |
| 57 | Transforms images in bayer format into a non-bayer format. | 76 | Transforms images in bayer format into a non-bayer format. |
| 58 | Exposes: | 77 | Exposes: |
| @@ -714,6 +714,20 @@ The Test Pattern Controls are all specific to video capture. · 713 unmodified lines | |||
| 714 | 714 | ||
| 715 | does the same for the EAV (End of Active Video) code. | 715 | does the same for the EAV (End of Active Video) code. |
| 716 | 716 | ||
| 717 | - Insert Video Guard Band | ||
| 718 | |||
| 719 | adds 4 columns of pixels with the HDMI Video Guard Band code at the | ||
| 720 | left hand side of the image. This only works with 3 or 4 byte RGB pixel | ||
| 721 | formats. The RGB pixel value 0xab/0x55/0xab turns out to be equivalent | ||
| 722 | to the HDMI Video Guard Band code that precedes each active video line | ||
| 723 | (see section 5.2.2.1 in the HDMI 1.3 Specification). To test if a video | ||
| 724 | receiver has correct HDMI Video Guard Band processing, enable this | ||
| 725 | control and then move the image to the left hand side of the screen. | ||
| 726 | That will result in video lines that start with multiple pixels that | ||
| 727 | have the same value as the Video Guard Band that precedes them. | ||
| 728 | Receivers that will just keep skipping Video Guard Band values will | ||
| 729 | now fail and either loose sync or these video lines will shift. | ||
| 730 | |||
| 717 | 731 | ||
| 718 | Capture Feature Selection Controls | 732 | Capture Feature Selection Controls |
| 719 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | 733 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| @@ -125,7 +125,7 @@ processor. Each bank is referred to as a `node` and for each node Linux · 124 unmodified lines | |||
| 125 | constructs an independent memory management subsystem. A node has its | 125 | constructs an independent memory management subsystem. A node has its |
| 126 | own set of zones, lists of free and used pages and various statistics | 126 | own set of zones, lists of free and used pages and various statistics |
| 127 | counters. You can find more details about NUMA in | 127 | counters. You can find more details about NUMA in |
| 128 | :ref:`Documentation/vm/numa.rst <numa>` and in | 128 | :ref:`Documentation/mm/numa.rst <numa>` and in |
| 129 | :ref:`Documentation/admin-guide/mm/numa_memory_policy.rst <numa_memory_policy>`. | 129 | :ref:`Documentation/admin-guide/mm/numa_memory_policy.rst <numa_memory_policy>`. |
| 130 | 130 | ||
| 131 | Page cache | 131 | Page cache |
| @@ -4,7 +4,7 @@ · 3 unmodified lines | |||
| 4 | Monitoring Data Accesses | 4 | Monitoring Data Accesses |
| 5 | ======================== | 5 | ======================== |
| 6 | 6 | ||
| 7 | :doc:`DAMON </vm/damon/index>` allows light-weight data access monitoring. | 7 | :doc:`DAMON </mm/damon/index>` allows light-weight data access monitoring. |
| 8 | Using DAMON, users can analyze the memory access patterns of their systems and | 8 | Using DAMON, users can analyze the memory access patterns of their systems and |
| 9 | optimize those. | 9 | optimize those. |
| 10 | 10 | ||
| @@ -14,3 +14,4 @@ optimize those. · 3 unmodified lines | |||
| 14 | start | 14 | start |
| 15 | usage | 15 | usage |
| 16 | reclaim | 16 | reclaim |
| 17 | lru_sort | ||
| @@ -0,0 +1,294 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0 | ||
| 2 | |||
| 3 | ============================= | ||
| 4 | DAMON-based LRU-lists Sorting | ||
| 5 | ============================= | ||
| 6 | |||
| 7 | DAMON-based LRU-lists Sorting (DAMON_LRU_SORT) is a static kernel module that | ||
| 8 | aimed to be used for proactive and lightweight data access pattern based | ||
| 9 | (de)prioritization of pages on their LRU-lists for making LRU-lists a more | ||
| 10 | trusworthy data access pattern source. | ||
| 11 | |||
| 12 | Where Proactive LRU-lists Sorting is Required? | ||
| 13 | ============================================== | ||
| 14 | |||
| 15 | As page-granularity access checking overhead could be significant on huge | ||
| 16 | systems, LRU lists are normally not proactively sorted but partially and | ||
| 17 | reactively sorted for special events including specific user requests, system | ||
| 18 | calls and memory pressure. As a result, LRU lists are sometimes not so | ||
| 19 | perfectly prepared to be used as a trustworthy access pattern source for some | ||
| 20 | situations including reclamation target pages selection under sudden memory | ||
| 21 | pressure. | ||
| 22 | |||
| 23 | Because DAMON can identify access patterns of best-effort accuracy while | ||
| 24 | inducing only user-specified range of overhead, proactively running | ||
| 25 | DAMON_LRU_SORT could be helpful for making LRU lists more trustworthy access | ||
| 26 | pattern source with low and controlled overhead. | ||
| 27 | |||
| 28 | How It Works? | ||
| 29 | ============= | ||
| 30 | |||
| 31 | DAMON_LRU_SORT finds hot pages (pages of memory regions that showing access | ||
| 32 | rates that higher than a user-specified threshold) and cold pages (pages of | ||
| 33 | memory regions that showing no access for a time that longer than a | ||
| 34 | user-specified threshold) using DAMON, and prioritizes hot pages while | ||
| 35 | deprioritizing cold pages on their LRU-lists. To avoid it consuming too much | ||
| 36 | CPU for the prioritizations, a CPU time usage limit can be configured. Under | ||
| 37 | the limit, it prioritizes and deprioritizes more hot and cold pages first, | ||
| 38 | respectively. System administrators can also configure under what situation | ||
| 39 | this scheme should automatically activated and deactivated with three memory | ||
| 40 | pressure watermarks. | ||
| 41 | |||
| 42 | Its default parameters for hotness/coldness thresholds and CPU quota limit are | ||
| 43 | conservatively chosen. That is, the module under its default parameters could | ||
| 44 | be widely used without harm for common situations while providing a level of | ||
| 45 | benefits for systems having clear hot/cold access patterns under memory | ||
| 46 | pressure while consuming only a limited small portion of CPU time. | ||
| 47 | |||
| 48 | Interface: Module Parameters | ||
| 49 | ============================ | ||
| 50 | |||
| 51 | To use this feature, you should first ensure your system is running on a kernel | ||
| 52 | that is built with ``CONFIG_DAMON_LRU_SORT=y``. | ||
| 53 | |||
| 54 | To let sysadmins enable or disable it and tune for the given system, | ||
| 55 | DAMON_LRU_SORT utilizes module parameters. That is, you can put | ||
| 56 | ``damon_lru_sort.<parameter>=<value>`` on the kernel boot command line or write | ||
| 57 | proper values to ``/sys/modules/damon_lru_sort/parameters/<parameter>`` files. | ||
| 58 | |||
| 59 | Below are the description of each parameter. | ||
| 60 | |||
| 61 | enabled | ||
| 62 | ------- | ||
| 63 | |||
| 64 | Enable or disable DAMON_LRU_SORT. | ||
| 65 | |||
| 66 | You can enable DAMON_LRU_SORT by setting the value of this parameter as ``Y``. | ||
| 67 | Setting it as ``N`` disables DAMON_LRU_SORT. Note that DAMON_LRU_SORT could do | ||
| 68 | no real monitoring and LRU-lists sorting due to the watermarks-based activation | ||
| 69 | condition. Refer to below descriptions for the watermarks parameter for this. | ||
| 70 | |||
| 71 | commit_inputs | ||
| 72 | ------------- | ||
| 73 | |||
| 74 | Make DAMON_LRU_SORT reads the input parameters again, except ``enabled``. | ||
| 75 | |||
| 76 | Input parameters that updated while DAMON_LRU_SORT is running are not applied | ||
| 77 | by default. Once this parameter is set as ``Y``, DAMON_LRU_SORT reads values | ||
| 78 | of parametrs except ``enabled`` again. Once the re-reading is done, this | ||
| 79 | parameter is set as ``N``. If invalid parameters are found while the | ||
| 80 | re-reading, DAMON_LRU_SORT will be disabled. | ||
| 81 | |||
| 82 | hot_thres_access_freq | ||
| 83 | --------------------- | ||
| 84 | |||
| 85 | Access frequency threshold for hot memory regions identification in permil. | ||
| 86 | |||
| 87 | If a memory region is accessed in frequency of this or higher, DAMON_LRU_SORT | ||
| 88 | identifies the region as hot, and mark it as accessed on the LRU list, so that | ||
| 89 | it could not be reclaimed under memory pressure. 50% by default. | ||
| 90 | |||
| 91 | cold_min_age | ||
| 92 | ------------ | ||
| 93 | |||
| 94 | Time threshold for cold memory regions identification in microseconds. | ||
| 95 | |||
| 96 | If a memory region is not accessed for this or longer time, DAMON_LRU_SORT | ||
| 97 | identifies the region as cold, and mark it as unaccessed on the LRU list, so | ||
| 98 | that it could be reclaimed first under memory pressure. 120 seconds by | ||
| 99 | default. | ||
| 100 | |||
| 101 | quota_ms | ||
| 102 | -------- | ||
| 103 | |||
| 104 | Limit of time for trying the LRU lists sorting in milliseconds. | ||
| 105 | |||
| 106 | DAMON_LRU_SORT tries to use only up to this time within a time window | ||
| 107 | (quota_reset_interval_ms) for trying LRU lists sorting. This can be used | ||
| 108 | for limiting CPU consumption of DAMON_LRU_SORT. If the value is zero, the | ||
| 109 | limit is disabled. | ||
| 110 | |||
| 111 | 10 ms by default. | ||
| 112 | |||
| 113 | quota_reset_interval_ms | ||
| 114 | ----------------------- | ||
| 115 | |||
| 116 | The time quota charge reset interval in milliseconds. | ||
| 117 | |||
| 118 | The charge reset interval for the quota of time (quota_ms). That is, | ||
| 119 | DAMON_LRU_SORT does not try LRU-lists sorting for more than quota_ms | ||
| 120 | milliseconds or quota_sz bytes within quota_reset_interval_ms milliseconds. | ||
| 121 | |||
| 122 | 1 second by default. | ||
| 123 | |||
| 124 | wmarks_interval | ||
| 125 | --------------- | ||
| 126 | |||
| 127 | The watermarks check time interval in microseconds. | ||
| 128 | |||
| 129 | Minimal time to wait before checking the watermarks, when DAMON_LRU_SORT is | ||
| 130 | enabled but inactive due to its watermarks rule. 5 seconds by default. | ||
| 131 | |||
| 132 | wmarks_high | ||
| 133 | ----------- | ||
| 134 | |||
| 135 | Free memory rate (per thousand) for the high watermark. | ||
| 136 | |||
| 137 | If free memory of the system in bytes per thousand bytes is higher than this, | ||
| 138 | DAMON_LRU_SORT becomes inactive, so it does nothing but periodically checks the | ||
| 139 | watermarks. 200 (20%) by default. | ||
| 140 | |||
| 141 | wmarks_mid | ||
| 142 | ---------- | ||
| 143 | |||
| 144 | Free memory rate (per thousand) for the middle watermark. | ||
| 145 | |||
| 146 | If free memory of the system in bytes per thousand bytes is between this and | ||
| 147 | the low watermark, DAMON_LRU_SORT becomes active, so starts the monitoring and | ||
| 148 | the LRU-lists sorting. 150 (15%) by default. | ||
| 149 | |||
| 150 | wmarks_low | ||
| 151 | ---------- | ||
| 152 | |||
| 153 | Free memory rate (per thousand) for the low watermark. | ||
| 154 | |||
| 155 | If free memory of the system in bytes per thousand bytes is lower than this, | ||
| 156 | DAMON_LRU_SORT becomes inactive, so it does nothing but periodically checks the | ||
| 157 | watermarks. 50 (5%) by default. | ||
| 158 | |||
| 159 | sample_interval | ||
| 160 | --------------- | ||
| 161 | |||
| 162 | Sampling interval for the monitoring in microseconds. | ||
| 163 | |||
| 164 | The sampling interval of DAMON for the cold memory monitoring. Please refer to | ||
| 165 | the DAMON documentation (:doc:`usage`) for more detail. 5ms by default. | ||
| 166 | |||
| 167 | aggr_interval | ||
| 168 | ------------- | ||
| 169 | |||
| 170 | Aggregation interval for the monitoring in microseconds. | ||
| 171 | |||
| 172 | The aggregation interval of DAMON for the cold memory monitoring. Please | ||
| 173 | refer to the DAMON documentation (:doc:`usage`) for more detail. 100ms by | ||
| 174 | default. | ||
| 175 | |||
| 176 | min_nr_regions | ||
| 177 | -------------- | ||
| 178 | |||
| 179 | Minimum number of monitoring regions. | ||
| 180 | |||
| 181 | The minimal number of monitoring regions of DAMON for the cold memory | ||
| 182 | monitoring. This can be used to set lower-bound of the monitoring quality. | ||
| 183 | But, setting this too high could result in increased monitoring overhead. | ||
| 184 | Please refer to the DAMON documentation (:doc:`usage`) for more detail. 10 by | ||
| 185 | default. | ||
| 186 | |||
| 187 | max_nr_regions | ||
| 188 | -------------- | ||
| 189 | |||
| 190 | Maximum number of monitoring regions. | ||
| 191 | |||
| 192 | The maximum number of monitoring regions of DAMON for the cold memory | ||
| 193 | monitoring. This can be used to set upper-bound of the monitoring overhead. | ||
| 194 | However, setting this too low could result in bad monitoring quality. Please | ||
| 195 | refer to the DAMON documentation (:doc:`usage`) for more detail. 1000 by | ||
| 196 | defaults. | ||
| 197 | |||
| 198 | monitor_region_start | ||
| 199 | -------------------- | ||
| 200 | |||
| 201 | Start of target memory region in physical address. | ||
| 202 | |||
| 203 | The start physical address of memory region that DAMON_LRU_SORT will do work | ||
| 204 | against. By default, biggest System RAM is used as the region. | ||
| 205 | |||
| 206 | monitor_region_end | ||
| 207 | ------------------ | ||
| 208 | |||
| 209 | End of target memory region in physical address. | ||
| 210 | |||
| 211 | The end physical address of memory region that DAMON_LRU_SORT will do work | ||
| 212 | against. By default, biggest System RAM is used as the region. | ||
| 213 | |||
| 214 | kdamond_pid | ||
| 215 | ----------- | ||
| 216 | |||
| 217 | PID of the DAMON thread. | ||
| 218 | |||
| 219 | If DAMON_LRU_SORT is enabled, this becomes the PID of the worker thread. Else, | ||
| 220 | -1. | ||
| 221 | |||
| 222 | nr_lru_sort_tried_hot_regions | ||
| 223 | ----------------------------- | ||
| 224 | |||
| 225 | Number of hot memory regions that tried to be LRU-sorted. | ||
| 226 | |||
| 227 | bytes_lru_sort_tried_hot_regions | ||
| 228 | -------------------------------- | ||
| 229 | |||
| 230 | Total bytes of hot memory regions that tried to be LRU-sorted. | ||
| 231 | |||
| 232 | nr_lru_sorted_hot_regions | ||
| 233 | ------------------------- | ||
| 234 | |||
| 235 | Number of hot memory regions that successfully be LRU-sorted. | ||
| 236 | |||
| 237 | bytes_lru_sorted_hot_regions | ||
| 238 | ---------------------------- | ||
| 239 | |||
| 240 | Total bytes of hot memory regions that successfully be LRU-sorted. | ||
| 241 | |||
| 242 | nr_hot_quota_exceeds | ||
| 243 | -------------------- | ||
| 244 | |||
| 245 | Number of times that the time quota limit for hot regions have exceeded. | ||
| 246 | |||
| 247 | nr_lru_sort_tried_cold_regions | ||
| 248 | ------------------------------ | ||
| 249 | |||
| 250 | Number of cold memory regions that tried to be LRU-sorted. | ||
| 251 | |||
| 252 | bytes_lru_sort_tried_cold_regions | ||
| 253 | --------------------------------- | ||
| 254 | |||
| 255 | Total bytes of cold memory regions that tried to be LRU-sorted. | ||
| 256 | |||
| 257 | nr_lru_sorted_cold_regions | ||
| 258 | -------------------------- | ||
| 259 | |||
| 260 | Number of cold memory regions that successfully be LRU-sorted. | ||
| 261 | |||
| 262 | bytes_lru_sorted_cold_regions | ||
| 263 | ----------------------------- | ||
| 264 | |||
| 265 | Total bytes of cold memory regions that successfully be LRU-sorted. | ||
| 266 | |||
| 267 | nr_cold_quota_exceeds | ||
| 268 | --------------------- | ||
| 269 | |||
| 270 | Number of times that the time quota limit for cold regions have exceeded. | ||
| 271 | |||
| 272 | Example | ||
| 273 | ======= | ||
| 274 | |||
| 275 | Below runtime example commands make DAMON_LRU_SORT to find memory regions | ||
| 276 | having >=50% access frequency and LRU-prioritize while LRU-deprioritizing | ||
| 277 | memory regions that not accessed for 120 seconds. The prioritization and | ||
| 278 | deprioritization is limited to be done using only up to 1% CPU time to avoid | ||
| 279 | DAMON_LRU_SORT consuming too much CPU time for the (de)prioritization. It also | ||
| 280 | asks DAMON_LRU_SORT to do nothing if the system's free memory rate is more than | ||
| 281 | 50%, but start the real works if it becomes lower than 40%. If DAMON_RECLAIM | ||
| 282 | doesn't make progress and therefore the free memory rate becomes lower than | ||
| 283 | 20%, it asks DAMON_LRU_SORT to do nothing again, so that we can fall back to | ||
| 284 | the LRU-list based page granularity reclamation. :: | ||
| 285 | |||
| 286 | # cd /sys/modules/damon_lru_sort/parameters | ||
| 287 | # echo 500 > hot_thres_access_freq | ||
| 288 | # echo 120000000 > cold_min_age | ||
| 289 | # echo 10 > quota_ms | ||
| 290 | # echo 1000 > quota_reset_interval_ms | ||
| 291 | # echo 500 > wmarks_high | ||
| 292 | # echo 400 > wmarks_mid | ||
| 293 | # echo 200 > wmarks_low | ||
| 294 | # echo Y > enabled | ||
| @@ -48,12 +48,6 @@ DAMON_RECLAIM utilizes module parameters. That is, you can put · 47 unmodified lines | |||
| 48 | ``damon_reclaim.<parameter>=<value>`` on the kernel boot command line or write | 48 | ``damon_reclaim.<parameter>=<value>`` on the kernel boot command line or write |
| 49 | proper values to ``/sys/modules/damon_reclaim/parameters/<parameter>`` files. | 49 | proper values to ``/sys/modules/damon_reclaim/parameters/<parameter>`` files. |
| 50 | 50 | ||
| 51 | Note that the parameter values except ``enabled`` are applied only when | ||
| 52 | DAMON_RECLAIM starts. Therefore, if you want to apply new parameter values in | ||
| 53 | runtime and DAMON_RECLAIM is already enabled, you should disable and re-enable | ||
| 54 | it via ``enabled`` parameter file. Writing of the new values to proper | ||
| 55 | parameter values should be done before the re-enablement. | ||
| 56 | |||
| 57 | Below are the description of each parameter. | 51 | Below are the description of each parameter. |
| 58 | 52 | ||
| 59 | enabled | 53 | enabled |
| @@ -268,4 +262,4 @@ granularity reclamation. :: · 208 unmodified lines | |||
| 268 | 262 | ||
| 269 | .. [1] https://research.google/pubs/pub48551/ | 263 | .. [1] https://research.google/pubs/pub48551/ |
| 270 | .. [2] https://lwn.net/Articles/787611/ | 264 | .. [2] https://lwn.net/Articles/787611/ |
| 271 | .. [3] https://www.kernel.org/doc/html/latest/vm/free_page_reporting.html | 265 | .. [3] https://www.kernel.org/doc/html/latest/mm/free_page_reporting.html |
| @@ -30,11 +30,11 @@ DAMON provides below interfaces for different users. · 29 unmodified lines | |||
| 30 | <sysfs_interface>`. This will be removed after next LTS kernel is released, | 30 | <sysfs_interface>`. This will be removed after next LTS kernel is released, |
| 31 | so users should move to the :ref:`sysfs interface <sysfs_interface>`. | 31 | so users should move to the :ref:`sysfs interface <sysfs_interface>`. |
| 32 | - *Kernel Space Programming Interface.* | 32 | - *Kernel Space Programming Interface.* |
| 33 | :doc:`This </vm/damon/api>` is for kernel space programmers. Using this, | 33 | :doc:`This </mm/damon/api>` is for kernel space programmers. Using this, |
| 34 | users can utilize every feature of DAMON most flexibly and efficiently by | 34 | users can utilize every feature of DAMON most flexibly and efficiently by |
| 35 | writing kernel space DAMON application programs for you. You can even extend | 35 | writing kernel space DAMON application programs for you. You can even extend |
| 36 | DAMON for various address spaces. For detail, please refer to the interface | 36 | DAMON for various address spaces. For detail, please refer to the interface |
| 37 | :doc:`document </vm/damon/api>`. | 37 | :doc:`document </mm/damon/api>`. |
| 38 | 38 | ||
| 39 | .. _sysfs_interface: | 39 | .. _sysfs_interface: |
| 40 | 40 | ||
| @@ -50,10 +50,10 @@ For a short example, users can monitor the virtual address space of a given · 9 unmodified lines | |||
| 50 | workload as below. :: | 50 | workload as below. :: |
| 51 | 51 | ||
| 52 | # cd /sys/kernel/mm/damon/admin/ | 52 | # cd /sys/kernel/mm/damon/admin/ |
| 53 | # echo 1 > kdamonds/nr && echo 1 > kdamonds/0/contexts/nr | 53 | # echo 1 > kdamonds/nr_kdamonds && echo 1 > kdamonds/0/contexts/nr_contexts |
| 54 | # echo vaddr > kdamonds/0/contexts/0/operations | 54 | # echo vaddr > kdamonds/0/contexts/0/operations |
| 55 | # echo 1 > kdamonds/0/contexts/0/targets/nr | 55 | # echo 1 > kdamonds/0/contexts/0/targets/nr_targets |
| 56 | # echo $(pidof <workload>) > kdamonds/0/contexts/0/targets/0/pid | 56 | # echo $(pidof <workload>) > kdamonds/0/contexts/0/targets/0/pid_target |
| 57 | # echo on > kdamonds/0/state | 57 | # echo on > kdamonds/0/state |
| 58 | 58 | ||
| 59 | Files Hierarchy | 59 | Files Hierarchy |
| @@ -185,7 +185,7 @@ controls the monitoring overhead, exist. You can set and get the values by · 125 unmodified lines | |||
| 185 | writing to and rading from the files. | 185 | writing to and rading from the files. |
| 186 | 186 | ||
| 187 | For more details about the intervals and monitoring regions range, please refer | 187 | For more details about the intervals and monitoring regions range, please refer |
| 188 | to the Design document (:doc:`/vm/damon/design`). | 188 | to the Design document (:doc:`/mm/damon/design`). |
| 189 | 189 | ||
| 190 | contexts/<N>/targets/ | 190 | contexts/<N>/targets/ |
| 191 | --------------------- | 191 | --------------------- |
| @@ -264,6 +264,8 @@ that can be written to and read from the file and their meaning are as below. · 72 unmodified lines | |||
| 264 | - ``pageout``: Call ``madvise()`` for the region with ``MADV_PAGEOUT`` | 264 | - ``pageout``: Call ``madvise()`` for the region with ``MADV_PAGEOUT`` |
| 265 | - ``hugepage``: Call ``madvise()`` for the region with ``MADV_HUGEPAGE`` | 265 | - ``hugepage``: Call ``madvise()`` for the region with ``MADV_HUGEPAGE`` |
| 266 | - ``nohugepage``: Call ``madvise()`` for the region with ``MADV_NOHUGEPAGE`` | 266 | - ``nohugepage``: Call ``madvise()`` for the region with ``MADV_NOHUGEPAGE`` |
| 267 | - ``lru_prio``: Prioritize the region on its LRU lists. | ||
| 268 | - ``lru_deprio``: Deprioritize the region on its LRU lists. | ||
| 267 | - ``stat``: Do nothing but count the statistics | 269 | - ``stat``: Do nothing but count the statistics |
| 268 | 270 | ||
| 269 | schemes/<N>/access_pattern/ | 271 | schemes/<N>/access_pattern/ |
| @@ -364,12 +366,12 @@ memory rate becomes larger than 60%, or lower than 30%". :: · 94 unmodified lines | |||
| 364 | # echo 1 > kdamonds/0/contexts/0/schemes/nr_schemes | 366 | # echo 1 > kdamonds/0/contexts/0/schemes/nr_schemes |
| 365 | # cd kdamonds/0/contexts/0/schemes/0 | 367 | # cd kdamonds/0/contexts/0/schemes/0 |
| 366 | # # set the basic access pattern and the action | 368 | # # set the basic access pattern and the action |
| 367 | # echo 4096 > access_patterns/sz/min | 369 | # echo 4096 > access_pattern/sz/min |
| 368 | # echo 8192 > access_patterns/sz/max | 370 | # echo 8192 > access_pattern/sz/max |
| 369 | # echo 0 > access_patterns/nr_accesses/min | 371 | # echo 0 > access_pattern/nr_accesses/min |
| 370 | # echo 5 > access_patterns/nr_accesses/max | 372 | # echo 5 > access_pattern/nr_accesses/max |
| 371 | # echo 10 > access_patterns/age/min | 373 | # echo 10 > access_pattern/age/min |
| 372 | # echo 20 > access_patterns/age/max | 374 | # echo 20 > access_pattern/age/max |
| 373 | # echo pageout > action | 375 | # echo pageout > action |
| 374 | # # set quotas | 376 | # # set quotas |
| 375 | # echo 10 > quotas/ms | 377 | # echo 10 > quotas/ms |
| @@ -402,7 +404,7 @@ Attributes · 26 unmodified lines | |||
| 402 | Users can get and set the ``sampling interval``, ``aggregation interval``, | 404 | Users can get and set the ``sampling interval``, ``aggregation interval``, |
| 403 | ``update interval``, and min/max number of monitoring target regions by | 405 | ``update interval``, and min/max number of monitoring target regions by |
| 404 | reading from and writing to the ``attrs`` file. To know about the monitoring | 406 | reading from and writing to the ``attrs`` file. To know about the monitoring |
| 405 | attributes in detail, please refer to the :doc:`/vm/damon/design`. For | 407 | attributes in detail, please refer to the :doc:`/mm/damon/design`. For |
| 406 | example, below commands set those values to 5 ms, 100 ms, 1,000 ms, 10 and | 408 | example, below commands set those values to 5 ms, 100 ms, 1,000 ms, 10 and |
| 407 | 1000, and then check it again:: | 409 | 1000, and then check it again:: |
| 408 | 410 | ||
| @@ -164,8 +164,8 @@ default_hugepagesz · 163 unmodified lines | |||
| 164 | will all result in 256 2M huge pages being allocated. Valid default | 164 | will all result in 256 2M huge pages being allocated. Valid default |
| 165 | huge page size is architecture dependent. | 165 | huge page size is architecture dependent. |
| 166 | hugetlb_free_vmemmap | 166 | hugetlb_free_vmemmap |
| 167 | When CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP is set, this enables optimizing | 167 | When CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP is set, this enables HugeTLB |
| 168 | unused vmemmap pages associated with each HugeTLB page. | 168 | Vmemmap Optimization (HVO). |
| 169 | 169 | ||
| 170 | When multiple huge page sizes are supported, ``/proc/sys/vm/nr_hugepages`` | 170 | When multiple huge page sizes are supported, ``/proc/sys/vm/nr_hugepages`` |
| 171 | indicates the current number of pre-allocated huge pages of the default size. | 171 | indicates the current number of pre-allocated huge pages of the default size. |
| @@ -36,6 +36,7 @@ the Linux memory management. · 35 unmodified lines | |||
| 36 | numa_memory_policy | 36 | numa_memory_policy |
| 37 | numaperf | 37 | numaperf |
| 38 | pagemap | 38 | pagemap |
| 39 | shrinker_debugfs | ||
| 39 | soft-dirty | 40 | soft-dirty |
| 40 | swap_numa | 41 | swap_numa |
| 41 | transhuge | 42 | transhuge |
| @@ -653,8 +653,8 @@ block might fail: · 652 unmodified lines | |||
| 653 | - Concurrent activity that operates on the same physical memory area, such as | 653 | - Concurrent activity that operates on the same physical memory area, such as |
| 654 | allocating gigantic pages, can result in temporary offlining failures. | 654 | allocating gigantic pages, can result in temporary offlining failures. |
| 655 | 655 | ||
| 656 | - Out of memory when dissolving huge pages, especially when freeing unused | 656 | - Out of memory when dissolving huge pages, especially when HugeTLB Vmemmap |
| 657 | vmemmap pages associated with each hugetlb page is enabled. | 657 | Optimization (HVO) is enabled. |
| 658 | 658 | ||
| 659 | Offlining code may be able to migrate huge page contents, but may not be able | 659 | Offlining code may be able to migrate huge page contents, but may not be able |
| 660 | to dissolve the source huge page because it fails allocating (unmovable) pages | 660 | to dissolve the source huge page because it fails allocating (unmovable) pages |
| @@ -0,0 +1,135 @@ | |||
| 1 | .. _shrinker_debugfs: | ||
| 2 | |||
| 3 | ========================== | ||
| 4 | Shrinker Debugfs Interface | ||
| 5 | ========================== | ||
| 6 | |||
| 7 | Shrinker debugfs interface provides a visibility into the kernel memory | ||
| 8 | shrinkers subsystem and allows to get information about individual shrinkers | ||
| 9 | and interact with them. | ||
| 10 | |||
| 11 | For each shrinker registered in the system a directory in **<debugfs>/shrinker/** | ||
| 12 | is created. The directory's name is composed from the shrinker's name and an | ||
| 13 | unique id: e.g. *kfree_rcu-0* or *sb-xfs:vda1-36*. | ||
| 14 | |||
| 15 | Each shrinker directory contains **count** and **scan** files, which allow to | ||
| 16 | trigger *count_objects()* and *scan_objects()* callbacks for each memcg and | ||
| 17 | numa node (if applicable). | ||
| 18 | |||
| 19 | Usage: | ||
| 20 | ------ | ||
| 21 | |||
| 22 | 1. *List registered shrinkers* | ||
| 23 | |||
| 24 | :: | ||
| 25 | |||
| 26 | $ cd /sys/kernel/debug/shrinker/ | ||
| 27 | $ ls | ||
| 28 | dquota-cache-16 sb-devpts-28 sb-proc-47 sb-tmpfs-42 | ||
| 29 | mm-shadow-18 sb-devtmpfs-5 sb-proc-48 sb-tmpfs-43 | ||
| 30 | mm-zspool:zram0-34 sb-hugetlbfs-17 sb-pstore-31 sb-tmpfs-44 | ||
| 31 | rcu-kfree-0 sb-hugetlbfs-33 sb-rootfs-2 sb-tmpfs-49 | ||
| 32 | sb-aio-20 sb-iomem-12 sb-securityfs-6 sb-tracefs-13 | ||
| 33 | sb-anon_inodefs-15 sb-mqueue-21 sb-selinuxfs-22 sb-xfs:vda1-36 | ||
| 34 | sb-bdev-3 sb-nsfs-4 sb-sockfs-8 sb-zsmalloc-19 | ||
| 35 | sb-bpf-32 sb-pipefs-14 sb-sysfs-26 thp-deferred_split-10 | ||
| 36 | sb-btrfs:vda2-24 sb-proc-25 sb-tmpfs-1 thp-zero-9 | ||
| 37 | sb-cgroup2-30 sb-proc-39 sb-tmpfs-27 xfs-buf:vda1-37 | ||
| 38 | sb-configfs-23 sb-proc-41 sb-tmpfs-29 xfs-inodegc:vda1-38 | ||
| 39 | sb-dax-11 sb-proc-45 sb-tmpfs-35 | ||
| 40 | sb-debugfs-7 sb-proc-46 sb-tmpfs-40 | ||
| 41 | |||
| 42 | 2. *Get information about a specific shrinker* | ||
| 43 | |||
| 44 | :: | ||
| 45 | |||
| 46 | $ cd sb-btrfs\:vda2-24/ | ||
| 47 | $ ls | ||
| 48 | count scan | ||
| 49 | |||
| 50 | 3. *Count objects* | ||
| 51 | |||
| 52 | Each line in the output has the following format:: | ||
| 53 | |||
| 54 | <cgroup inode id> <nr of objects on node 0> <nr of objects on node 1> ... | ||
| 55 | <cgroup inode id> <nr of objects on node 0> <nr of objects on node 1> ... | ||
| 56 | ... | ||
| 57 | |||
| 58 | If there are no objects on all numa nodes, a line is omitted. If there | ||
| 59 | are no objects at all, the output might be empty. | ||
| 60 | |||
| 61 | If the shrinker is not memcg-aware or CONFIG_MEMCG is off, 0 is printed | ||
| 62 | as cgroup inode id. If the shrinker is not numa-aware, 0's are printed | ||
| 63 | for all nodes except the first one. | ||
| 64 | :: | ||
| 65 | |||
| 66 | $ cat count | ||
| 67 | 1 224 2 | ||
| 68 | 21 98 0 | ||
| 69 | 55 818 10 | ||
| 70 | 2367 2 0 | ||
| 71 | 2401 30 0 | ||
| 72 | 225 13 0 | ||
| 73 | 599 35 0 | ||
| 74 | 939 124 0 | ||
| 75 | 1041 3 0 | ||
| 76 | 1075 1 0 | ||
| 77 | 1109 1 0 | ||
| 78 | 1279 60 0 | ||
| 79 | 1313 7 0 | ||
| 80 | 1347 39 0 | ||
| 81 | 1381 3 0 | ||
| 82 | 1449 14 0 | ||
| 83 | 1483 63 0 | ||
| 84 | 1517 53 0 | ||
| 85 | 1551 6 0 | ||
| 86 | 1585 1 0 | ||
| 87 | 1619 6 0 | ||
| 88 | 1653 40 0 | ||
| 89 | 1687 11 0 | ||
| 90 | 1721 8 0 | ||
| 91 | 1755 4 0 | ||
| 92 | 1789 52 0 | ||
| 93 | 1823 888 0 | ||
| 94 | 1857 1 0 | ||
| 95 | 1925 2 0 | ||
| 96 | 1959 32 0 | ||
| 97 | 2027 22 0 | ||
| 98 | 2061 9 0 | ||
| 99 | 2469 799 0 | ||
| 100 | 2537 861 0 | ||
| 101 | 2639 1 0 | ||
| 102 | 2707 70 0 | ||
| 103 | 2775 4 0 | ||
| 104 | 2877 84 0 | ||
| 105 | 293 1 0 | ||
| 106 | 735 8 0 | ||
| 107 | |||
| 108 | 4. *Scan objects* | ||
| 109 | |||
| 110 | The expected input format:: | ||
| 111 | |||
| 112 | <cgroup inode id> <numa id> <number of objects to scan> | ||
| 113 | |||
| 114 | For a non-memcg-aware shrinker or on a system with no memory | ||
| 115 | cgrups **0** should be passed as cgroup id. | ||
| 116 | :: | ||
| 117 | |||
| 118 | $ cd /sys/kernel/debug/shrinker/ | ||
| 119 | $ cd sb-btrfs\:vda2-24/ | ||
| 120 | |||
| 121 | $ cat count | head -n 5 | ||
| 122 | 1 212 0 | ||
| 123 | 21 97 0 | ||
| 124 | 55 802 5 | ||
| 125 | 2367 2 0 | ||
| 126 | 225 13 0 | ||
| 127 | |||
| 128 | $ echo "55 0 200" > scan | ||
| 129 | |||
| 130 | $ cat count | head -n 5 | ||
| 131 | 1 212 0 | ||
| 132 | 21 96 0 | ||
| 133 | 55 752 5 | ||
| 134 | 2367 2 0 | ||
| 135 | 225 13 0 | ||
| @@ -0,0 +1,136 @@ | |||
| 1 | ====================================== | ||
| 2 | HNS3 Performance Monitoring Unit (PMU) | ||
| 3 | ====================================== | ||
| 4 | |||
| 5 | HNS3(HiSilicon network system 3) Performance Monitoring Unit (PMU) is an | ||
| 6 | End Point device to collect performance statistics of HiSilicon SoC NIC. | ||
| 7 | On Hip09, each SICL(Super I/O cluster) has one PMU device. | ||
| 8 | |||
| 9 | HNS3 PMU supports collection of performance statistics such as bandwidth, | ||
| 10 | latency, packet rate and interrupt rate. | ||
| 11 | |||
| 12 | Each HNS3 PMU supports 8 hardware events. | ||
| 13 | |||
| 14 | HNS3 PMU driver | ||
| 15 | =============== | ||
| 16 | |||
| 17 | The HNS3 PMU driver registers a perf PMU with the name of its sicl id.:: | ||
| 18 | |||
| 19 | /sys/devices/hns3_pmu_sicl_<sicl_id> | ||
| 20 | |||
| 21 | PMU driver provides description of available events, filter modes, format, | ||
| 22 | identifier and cpumask in sysfs. | ||
| 23 | |||
| 24 | The "events" directory describes the event code of all supported events | ||
| 25 | shown in perf list. | ||
| 26 | |||
| 27 | The "filtermode" directory describes the supported filter modes of each | ||
| 28 | event. | ||
| 29 | |||
| 30 | The "format" directory describes all formats of the config (events) and | ||
| 31 | config1 (filter options) fields of the perf_event_attr structure. | ||
| 32 | |||
| 33 | The "identifier" file shows version of PMU hardware device. | ||
| 34 | |||
| 35 | The "bdf_min" and "bdf_max" files show the supported bdf range of each | ||
| 36 | pmu device. | ||
| 37 | |||
| 38 | The "hw_clk_freq" file shows the hardware clock frequency of each pmu | ||
| 39 | device. | ||
| 40 | |||
| 41 | Example usage of checking event code and subevent code:: | ||
| 42 | |||
| 43 | $# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time | ||
| 44 | config=0x00204 | ||
| 45 | $# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num | ||
| 46 | config=0x10204 | ||
| 47 | |||
| 48 | Each performance statistic has a pair of events to get two values to | ||
| 49 | calculate real performance data in userspace. | ||
| 50 | |||
| 51 | The bits 0~15 of config (here 0x0204) are the true hardware event code. If | ||
| 52 | two events have same value of bits 0~15 of config, that means they are | ||
| 53 | event pair. And the bit 16 of config indicates getting counter 0 or | ||
| 54 | counter 1 of hardware event. | ||
| 55 | |||
| 56 | After getting two values of event pair in usersapce, the formula of | ||
| 57 | computation to calculate real performance data is::: | ||
| 58 | |||
| 59 | counter 0 / counter 1 | ||
| 60 | |||
| 61 | Example usage of checking supported filter mode:: | ||
| 62 | |||
| 63 | $# cat /sys/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num | ||
| 64 | filter mode supported: global/port/port-tc/func/func-queue/ | ||
| 65 | |||
| 66 | Example usage of perf:: | ||
| 67 | |||
| 68 | $# perf list | ||
| 69 | hns3_pmu_sicl_0/bw_ssu_rpu_byte_num/ [kernel PMU event] | ||
| 70 | hns3_pmu_sicl_0/bw_ssu_rpu_time/ [kernel PMU event] | ||
| 71 | ------------------------------------------ | ||
| 72 | |||
| 73 | $# perf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_time,global=1/ -I 1000 | ||
| 74 | or | ||
| 75 | $# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,global=1/ -I 1000 | ||
| 76 | |||
| 77 | |||
| 78 | Filter modes | ||
| 79 | -------------- | ||
| 80 | |||
| 81 | 1. global mode | ||
| 82 | PMU collect performance statistics for all HNS3 PCIe functions of IO DIE. | ||
| 83 | Set the "global" filter option to 1 will enable this mode. | ||
| 84 | Example usage of perf:: | ||
| 85 | |||
| 86 | $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000 | ||
| 87 | |||
| 88 | 2. port mode | ||
| 89 | PMU collect performance statistic of one whole physical port. The port id | ||
| 90 | is same as mac id. The "tc" filter option must be set to 0xF in this mode, | ||
| 91 | here tc stands for traffic class. | ||
| 92 | |||
| 93 | Example usage of perf:: | ||
| 94 | |||
| 95 | $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000 | ||
| 96 | |||
| 97 | 3. port-tc mode | ||
| 98 | PMU collect performance statistic of one tc of physical port. The port id | ||
| 99 | is same as mac id. The "tc" filter option must be set to 0 ~ 7 in this | ||
| 100 | mode. | ||
| 101 | Example usage of perf:: | ||
| 102 | |||
| 103 | $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0/ -I 1000 | ||
| 104 | |||
| 105 | 4. func mode | ||
| 106 | PMU collect performance statistic of one PF/VF. The function id is BDF of | ||
| 107 | PF/VF, its conversion formula:: | ||
| 108 | |||
| 109 | func = (bus << 8) + (device << 3) + (function) | ||
| 110 | |||
| 111 | for example: | ||
| 112 | BDF func | ||
| 113 | 35:00.0 0x3500 | ||
| 114 | 35:00.1 0x3501 | ||
| 115 | 35:01.0 0x3508 | ||
| 116 | |||
| 117 | In this mode, the "queue" filter option must be set to 0xFFFF. | ||
| 118 | Example usage of perf:: | ||
| 119 | |||
| 120 | $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,bdf=0x3500,queue=0xFFFF/ -I 1000 | ||
| 121 | |||
| 122 | 5. func-queue mode | ||
| 123 | PMU collect performance statistic of one queue of PF/VF. The function id | ||
| 124 | is BDF of PF/VF, the "queue" filter option must be set to the exact queue | ||
| 125 | id of function. | ||
| 126 | Example usage of perf:: | ||
| 127 | |||
| 128 | $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,bdf=0x3500,queue=0/ -I 1000 | ||
| 129 | |||
| 130 | 6. func-intr mode | ||
| 131 | PMU collect performance statistic of one interrupt of PF/VF. The function | ||
| 132 | id is BDF of PF/VF, the "intr" filter option must be set to the exact | ||
| 133 | interrupt id of function. | ||
| 134 | Example usage of perf:: | ||
| 135 | |||
| 136 | $# perf stat -a -e hns3_pmu_sicl_0/config=0x00301,bdf=0x3500,intr=0/ -I 1000 | ||
| @@ -9,6 +9,7 @@ Performance monitor support · 8 unmodified lines | |||
| 9 | 9 | ||
| 10 | hisi-pmu | 10 | hisi-pmu |
| 11 | hisi-pcie-pmu | 11 | hisi-pcie-pmu |
| 12 | hns3-pmu | ||
| 12 | imx-ddr | 13 | imx-ddr |
| 13 | qcom_l2_pmu | 14 | qcom_l2_pmu |
| 14 | qcom_l3_pmu | 15 | qcom_l3_pmu |
| @@ -612,8 +612,8 @@ the ``menu`` governor to be used on the systems that use the ``ladder`` governor · 611 unmodified lines | |||
| 612 | by default this way, for example. | 612 | by default this way, for example. |
| 613 | 613 | ||
| 614 | The other kernel command line parameters controlling CPU idle time management | 614 | The other kernel command line parameters controlling CPU idle time management |
| 615 | described below are only relevant for the *x86* architecture and some of | 615 | described below are only relevant for the *x86* architecture and references |
| 616 | them affect Intel processors only. | 616 | to ``intel_idle`` affect Intel processors only. |
| 617 | 617 | ||
| 618 | The *x86* architecture support code recognizes three kernel command line | 618 | The *x86* architecture support code recognizes three kernel command line |
| 619 | options related to CPU idle time management: ``idle=poll``, ``idle=halt``, | 619 | options related to CPU idle time management: ``idle=poll``, ``idle=halt``, |
| @@ -635,10 +635,13 @@ idle, so it very well may hurt single-thread computations performance as well as · 15 unmodified lines | |||
| 635 | energy-efficiency. Thus using it for performance reasons may not be a good idea | 635 | energy-efficiency. Thus using it for performance reasons may not be a good idea |
| 636 | at all.] | 636 | at all.] |
| 637 | 637 | ||
| 638 | The ``idle=nomwait`` option disables the ``intel_idle`` driver and causes | 638 | The ``idle=nomwait`` option prevents the use of ``MWAIT`` instruction of |
| 639 | ``acpi_idle`` to be used (as long as all of the information needed by it is | 639 | the CPU to enter idle states. When this option is used, the ``acpi_idle`` |
| 640 | there in the system's ACPI tables), but it is not allowed to use the | 640 | driver will use the ``HLT`` instruction instead of ``MWAIT``. On systems |
| 641 | ``MWAIT`` instruction of the CPUs to ask the hardware to enter idle states. | 641 | running Intel processors, this option disables the ``intel_idle`` driver |
| 642 | and forces the use of the ``acpi_idle`` driver instead. Note that in either | ||
| 643 | case, ``acpi_idle`` driver will function only if all the information needed | ||
| 644 | by it is in the system's ACPI tables. | ||
| 642 | 645 | ||
| 643 | In addition to the architecture-level kernel command line options affecting CPU | 646 | In addition to the architecture-level kernel command line options affecting CPU |
| 644 | idle time management, there are parameters affecting individual ``CPUIdle`` | 647 | idle time management, there are parameters affecting individual ``CPUIdle`` |
| @@ -38,8 +38,8 @@ acct · 37 unmodified lines | |||
| 38 | 38 | ||
| 39 | If BSD-style process accounting is enabled these values control | 39 | If BSD-style process accounting is enabled these values control |
| 40 | its behaviour. If free space on filesystem where the log lives | 40 | its behaviour. If free space on filesystem where the log lives |
| 41 | goes below ``lowwater``% accounting suspends. If free space gets | 41 | goes below ``lowwater``\ % accounting suspends. If free space gets |
| 42 | above ``highwater``% accounting resumes. ``frequency`` determines | 42 | above ``highwater``\ % accounting resumes. ``frequency`` determines |
| 43 | how often do we check the amount of free space (value is in | 43 | how often do we check the amount of free space (value is in |
| 44 | seconds). Default: | 44 | seconds). Default: |
| 45 | 45 | ||
| @@ -592,6 +592,18 @@ to the guest kernel command line (see · 546 unmodified lines | |||
| 592 | Documentation/admin-guide/kernel-parameters.rst). | 592 | Documentation/admin-guide/kernel-parameters.rst). |
| 593 | 593 | ||
| 594 | 594 | ||
| 595 | nmi_wd_lpm_factor (PPC only) | ||
| 596 | ============================ | ||
| 597 | |||
| 598 | Factor to apply to the NMI watchdog timeout (only when ``nmi_watchdog`` is | ||
| 599 | set to 1). This factor represents the percentage added to | ||
| 600 | ``watchdog_thresh`` when calculating the NMI watchdog timeout during an | ||
| 601 | LPM. The soft lockup timeout is not impacted. | ||
| 602 | |||
| 603 | A value of 0 means no change. The default value is 200 meaning the NMI | ||
| 604 | watchdog is set to 30s (based on ``watchdog_thresh`` equal to 10). | ||
| 605 | |||
| 606 | |||
| 595 | numa_balancing | 607 | numa_balancing |
| 596 | ============== | 608 | ============== |
| 597 | 609 | ||
| @@ -271,7 +271,7 @@ poll cycle or the number of packets processed reaches netdev_budget. · 270 unmodified lines | |||
| 271 | netdev_max_backlog | 271 | netdev_max_backlog |
| 272 | ------------------ | 272 | ------------------ |
| 273 | 273 | ||
| 274 | Maximum number of packets, queued on the INPUT side, when the interface | 274 | Maximum number of packets, queued on the INPUT side, when the interface |
| 275 | receives packets faster than kernel can process them. | 275 | receives packets faster than kernel can process them. |
| 276 | 276 | ||
| 277 | netdev_rss_key | 277 | netdev_rss_key |
| @@ -391,6 +391,18 @@ GRO has decided not to coalesce, it is placed on a per-NAPI list. This · 113 unmodified lines | |||
| 391 | list is then passed to the stack when the number of segments reaches the | 391 | list is then passed to the stack when the number of segments reaches the |
| 392 | gro_normal_batch limit. | 392 | gro_normal_batch limit. |
| 393 | 393 | ||
| 394 | high_order_alloc_disable | ||
| 395 | ------------------------ | ||
| 396 | |||
| 397 | By default the allocator for page frags tries to use high order pages (order-3 | ||
| 398 | on x86). While the default behavior gives good results in most cases, some users | ||
| 399 | might have hit a contention in page allocations/freeing. This was especially | ||
| 400 | true on older kernels (< 5.14) when high-order pages were not stored on per-cpu | ||
| 401 | lists. This allows to opt-in for order-0 allocation instead but is now mostly of | ||
| 402 | historical importance. | ||
| 403 | |||
| 404 | Default: 0 | ||
| 405 | |||
| 394 | 2. /proc/sys/net/unix - Parameters for Unix domain sockets | 406 | 2. /proc/sys/net/unix - Parameters for Unix domain sockets |
| 395 | ---------------------------------------------------------- | 407 | ---------------------------------------------------------- |
| 396 | 408 | ||
| @@ -565,13 +565,11 @@ See Documentation/admin-guide/mm/hugetlbpage.rst · 564 unmodified lines | |||
| 565 | hugetlb_optimize_vmemmap | 565 | hugetlb_optimize_vmemmap |
| 566 | ======================== | 566 | ======================== |
| 567 | 567 | ||
| 568 | This knob is not available when memory_hotplug.memmap_on_memory (kernel parameter) | 568 | This knob is not available when the size of 'struct page' (a structure defined |
| 569 | is configured or the size of 'struct page' (a structure defined in | 569 | in include/linux/mm_types.h) is not power of two (an unusual system config could |
| 570 | include/linux/mm_types.h) is not power of two (an unusual system config could | ||
| 571 | result in this). | 570 | result in this). |
| 572 | 571 | ||
| 573 | Enable (set to 1) or disable (set to 0) the feature of optimizing vmemmap pages | 572 | Enable (set to 1) or disable (set to 0) HugeTLB Vmemmap Optimization (HVO). |
| 574 | associated with each HugeTLB page. | ||
| 575 | 573 | ||
| 576 | Once enabled, the vmemmap pages of subsequent allocation of HugeTLB pages from | 574 | Once enabled, the vmemmap pages of subsequent allocation of HugeTLB pages from |
| 577 | buddy allocator will be optimized (7 pages per 2MB HugeTLB page and 4095 pages | 575 | buddy allocator will be optimized (7 pages per 2MB HugeTLB page and 4095 pages |
| @@ -760,7 +758,7 @@ and don't use much of it. · 182 unmodified lines | |||
| 760 | 758 | ||
| 761 | The default value is 0. | 759 | The default value is 0. |
| 762 | 760 | ||
| 763 | See Documentation/vm/overcommit-accounting.rst and | 761 | See Documentation/mm/overcommit-accounting.rst and |
| 764 | mm/util.c::__vm_enough_memory() for more information. | 762 | mm/util.c::__vm_enough_memory() for more information. |
| 765 | 763 | ||
| 766 | 764 | ||
| @@ -100,6 +100,7 @@ Bit Log Number Reason that got the kernel tainted · 99 unmodified lines | |||
| 100 | 15 _/K 32768 kernel has been live patched | 100 | 15 _/K 32768 kernel has been live patched |
| 101 | 16 _/X 65536 auxiliary taint, defined for and used by distros | 101 | 16 _/X 65536 auxiliary taint, defined for and used by distros |
| 102 | 17 _/T 131072 kernel was built with the struct randomization plugin | 102 | 17 _/T 131072 kernel was built with the struct randomization plugin |
| 103 | 18 _/N 262144 an in-kernel test has been run | ||
| 103 | === === ====== ======================================================== | 104 | === === ====== ======================================================== |
| 104 | 105 | ||
| 105 | Note: The character ``_`` is representing a blank in this table to make reading | 106 | Note: The character ``_`` is representing a blank in this table to make reading |
| @@ -0,0 +1,69 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0 | ||
| 2 | |||
| 3 | ====================================== | ||
| 4 | Chromebook Boot Flow | ||
| 5 | ====================================== | ||
| 6 | |||
| 7 | Most recent Chromebooks that use device tree are using the opensource | ||
| 8 | depthcharge_ bootloader. Depthcharge_ expects the OS to be packaged as a `FIT | ||
| 9 | Image`_ which contains an OS image as well as a collection of device trees. It | ||
| 10 | is up to depthcharge_ to pick the right device tree from the `FIT Image`_ and | ||
| 11 | provide it to the OS. | ||
| 12 | |||
| 13 | The scheme that depthcharge_ uses to pick the device tree takes into account | ||
| 14 | three variables: | ||
| 15 | |||
| 16 | - Board name, specified at depthcharge_ compile time. This is $(BOARD) below. | ||
| 17 | - Board revision number, determined at runtime (perhaps by reading GPIO | ||
| 18 | strappings, perhaps via some other method). This is $(REV) below. | ||
| 19 | - SKU number, read from GPIO strappings at boot time. This is $(SKU) below. | ||
| 20 | |||
| 21 | For recent Chromebooks, depthcharge_ creates a match list that looks like this: | ||
| 22 | |||
| 23 | - google,$(BOARD)-rev$(REV)-sku$(SKU) | ||
| 24 | - google,$(BOARD)-rev$(REV) | ||
| 25 | - google,$(BOARD)-sku$(SKU) | ||
| 26 | - google,$(BOARD) | ||
| 27 | |||
| 28 | Note that some older Chromebooks use a slightly different list that may | ||
| 29 | not include SKU matching or may prioritize SKU/rev differently. | ||
| 30 | |||
| 31 | Note that for some boards there may be extra board-specific logic to inject | ||
| 32 | extra compatibles into the list, but this is uncommon. | ||
| 33 | |||
| 34 | Depthcharge_ will look through all device trees in the `FIT Image`_ trying to | ||
| 35 | find one that matches the most specific compatible. It will then look | ||
| 36 | through all device trees in the `FIT Image`_ trying to find the one that | ||
| 37 | matches the *second most* specific compatible, etc. | ||
| 38 | |||
| 39 | When searching for a device tree, depthcharge_ doesn't care where the | ||
| 40 | compatible string falls within a device tree's root compatible string array. | ||
| 41 | As an example, if we're on board "lazor", rev 4, SKU 0 and we have two device | ||
| 42 | trees: | ||
| 43 | |||
| 44 | - "google,lazor-rev5-sku0", "google,lazor-rev4-sku0", "qcom,sc7180" | ||
| 45 | - "google,lazor", "qcom,sc7180" | ||
| 46 | |||
| 47 | Then depthcharge_ will pick the first device tree even though | ||
| 48 | "google,lazor-rev4-sku0" was the second compatible listed in that device tree. | ||
| 49 | This is because it is a more specific compatible than "google,lazor". | ||
| 50 | |||
| 51 | It should be noted that depthcharge_ does not have any smarts to try to | ||
| 52 | match board or SKU revisions that are "close by". That is to say that | ||
| 53 | if depthcharge_ knows it's on "rev4" of a board but there is no "rev4" | ||
| 54 | device tree then depthcharge_ *won't* look for a "rev3" device tree. | ||
| 55 | |||
| 56 | In general when any significant changes are made to a board the board | ||
| 57 | revision number is increased even if none of those changes need to | ||
| 58 | be reflected in the device tree. Thus it's fairly common to see device | ||
| 59 | trees with multiple revisions. | ||
| 60 | |||
| 61 | It should be noted that, taking into account the above system that | ||
| 62 | depthcharge_ has, the most flexibility is achieved if the device tree | ||
| 63 | supporting the newest revision(s) of a board omits the "-rev{REV}" | ||
| 64 | compatible strings. When this is done then if you get a new board | ||
| 65 | revision and try to run old software on it then we'll at pick the | ||
| 66 | newest device tree we know about. | ||
| 67 | |||
| 68 | .. _depthcharge: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/depthcharge/ | ||
| 69 | .. _`FIT Image`: https://doc.coreboot.org/lib/payloads/fit.html | ||
| @@ -31,6 +31,8 @@ SoC-specific documents · 30 unmodified lines | |||
| 31 | .. toctree:: | 31 | .. toctree:: |
| 32 | :maxdepth: 1 | 32 | :maxdepth: 1 |
| 33 | 33 | ||
| 34 | google/chromebook-boot-flow | ||
| 35 | |||
| 34 | ixp4xx | 36 | ixp4xx |
| 35 | 37 | ||
| 36 | marvell | 38 | marvell |
| @@ -1,3 +1,5 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | |||
| 1 | ======================= | 3 | ======================= |
| 2 | S3C24XX CPUfreq support | 4 | S3C24XX CPUfreq support |
| 3 | ======================= | 5 | ======================= |
| @@ -73,4 +75,3 @@ Document Author · 69 unmodified lines | |||
| 73 | --------------- | 75 | --------------- |
| 74 | 76 | ||
| 75 | Ben Dooks, Copyright 2009 Simtec Electronics | 77 | Ben Dooks, Copyright 2009 Simtec Electronics |
| 76 | Licensed under GPLv2 | ||
| @@ -171,136 +171,107 @@ HWCAP_PACG · 170 unmodified lines | |||
| 171 | Documentation/arm64/pointer-authentication.rst. | 171 | Documentation/arm64/pointer-authentication.rst. |
| 172 | 172 | ||
| 173 | HWCAP2_DCPODP | 173 | HWCAP2_DCPODP |
| 174 | |||
| 175 | Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. | 174 | Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. |
| 176 | 175 | ||
| 177 | HWCAP2_SVE2 | 176 | HWCAP2_SVE2 |
| 178 | |||
| 179 | Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. | 177 | Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. |
| 180 | 178 | ||
| 181 | HWCAP2_SVEAES | 179 | HWCAP2_SVEAES |
| 182 | |||
| 183 | Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. | 180 | Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. |
| 184 | 181 | ||
| 185 | HWCAP2_SVEPMULL | 182 | HWCAP2_SVEPMULL |
| 186 | |||
| 187 | Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. | 183 | Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. |
| 188 | 184 | ||
| 189 | HWCAP2_SVEBITPERM | 185 | HWCAP2_SVEBITPERM |
| 190 | |||
| 191 | Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. | 186 | Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. |
| 192 | 187 | ||
| 193 | HWCAP2_SVESHA3 | 188 | HWCAP2_SVESHA3 |
| 194 | |||
| 195 | Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. | 189 | Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. |
| 196 | 190 | ||
| 197 | HWCAP2_SVESM4 | 191 | HWCAP2_SVESM4 |
| 198 | |||
| 199 | Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. | 192 | Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. |
| 200 | 193 | ||
| 201 | HWCAP2_FLAGM2 | 194 | HWCAP2_FLAGM2 |
| 202 | |||
| 203 | Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010. | 195 | Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010. |
| 204 | 196 | ||
| 205 | HWCAP2_FRINT | 197 | HWCAP2_FRINT |
| 206 | |||
| 207 | Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001. | 198 | Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001. |
| 208 | 199 | ||
| 209 | HWCAP2_SVEI8MM | 200 | HWCAP2_SVEI8MM |
| 210 | |||
| 211 | Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001. | 201 | Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001. |
| 212 | 202 | ||
| 213 | HWCAP2_SVEF32MM | 203 | HWCAP2_SVEF32MM |
| 214 | |||
| 215 | Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001. | 204 | Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001. |
| 216 | 205 | ||
| 217 | HWCAP2_SVEF64MM | 206 | HWCAP2_SVEF64MM |
| 218 | |||
| 219 | Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001. | 207 | Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001. |
| 220 | 208 | ||
| 221 | HWCAP2_SVEBF16 | 209 | HWCAP2_SVEBF16 |
| 222 | |||
| 223 | Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001. | 210 | Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001. |
| 224 | 211 | ||
| 225 | HWCAP2_I8MM | 212 | HWCAP2_I8MM |
| 226 | |||
| 227 | Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001. | 213 | Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001. |
| 228 | 214 | ||
| 229 | HWCAP2_BF16 | 215 | HWCAP2_BF16 |
| 230 | |||
| 231 | Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001. | 216 | Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001. |
| 232 | 217 | ||
| 233 | HWCAP2_DGH | 218 | HWCAP2_DGH |
| 234 | |||
| 235 | Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001. | 219 | Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001. |
| 236 | 220 | ||
| 237 | HWCAP2_RNG | 221 | HWCAP2_RNG |
| 238 | |||
| 239 | Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001. | 222 | Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001. |
| 240 | 223 | ||
| 241 | HWCAP2_BTI | 224 | HWCAP2_BTI |
| 242 | |||
| 243 | Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001. | 225 | Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001. |
| 244 | 226 | ||
| 245 | HWCAP2_MTE | 227 | HWCAP2_MTE |
| 246 | |||
| 247 | Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described | 228 | Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described |
| 248 | by Documentation/arm64/memory-tagging-extension.rst. | 229 | by Documentation/arm64/memory-tagging-extension.rst. |
| 249 | 230 | ||
| 250 | HWCAP2_ECV | 231 | HWCAP2_ECV |
| 251 | |||
| 252 | Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. | 232 | Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. |
| 253 | 233 | ||
| 254 | HWCAP2_AFP | 234 | HWCAP2_AFP |
| 255 | |||
| 256 | Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. | 235 | Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. |
| 257 | 236 | ||
| 258 | HWCAP2_RPRES | 237 | HWCAP2_RPRES |
| 259 | |||
| 260 | Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001. | 238 | Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001. |
| 261 | 239 | ||
| 262 | HWCAP2_MTE3 | 240 | HWCAP2_MTE3 |
| 263 | |||
| 264 | Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described | 241 | Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described |
| 265 | by Documentation/arm64/memory-tagging-extension.rst. | 242 | by Documentation/arm64/memory-tagging-extension.rst. |
| 266 | 243 | ||
| 267 | HWCAP2_SME | 244 | HWCAP2_SME |
| 268 | |||
| 269 | Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described | 245 | Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described |
| 270 | by Documentation/arm64/sme.rst. | 246 | by Documentation/arm64/sme.rst. |
| 271 | 247 | ||
| 272 | HWCAP2_SME_I16I64 | 248 | HWCAP2_SME_I16I64 |
| 273 | |||
| 274 | Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111. | 249 | Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111. |
| 275 | 250 | ||
| 276 | HWCAP2_SME_F64F64 | 251 | HWCAP2_SME_F64F64 |
| 277 | |||
| 278 | Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1. | 252 | Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1. |
| 279 | 253 | ||
| 280 | HWCAP2_SME_I8I32 | 254 | HWCAP2_SME_I8I32 |
| 281 | |||
| 282 | Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111. | 255 | Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111. |
| 283 | 256 | ||
| 284 | HWCAP2_SME_F16F32 | 257 | HWCAP2_SME_F16F32 |
| 285 | |||
| 286 | Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1. | 258 | Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1. |
| 287 | 259 | ||
| 288 | HWCAP2_SME_B16F32 | 260 | HWCAP2_SME_B16F32 |
| 289 | |||
| 290 | Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1. | 261 | Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1. |
| 291 | 262 | ||
| 292 | HWCAP2_SME_F32F32 | 263 | HWCAP2_SME_F32F32 |
| 293 | |||
| 294 | Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1. | 264 | Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1. |
| 295 | 265 | ||
| 296 | HWCAP2_SME_FA64 | 266 | HWCAP2_SME_FA64 |
| 297 | |||
| 298 | Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1. | 267 | Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1. |
| 299 | 268 | ||
| 300 | HWCAP2_WFXT | 269 | HWCAP2_WFXT |
| 301 | |||
| 302 | Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010. | 270 | Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010. |
| 303 | 271 | ||
| 272 | HWCAP2_EBF16 | ||
| 273 | Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010. | ||
| 274 | |||
| 304 | 4. Unused AT_HWCAP bits | 275 | 4. Unused AT_HWCAP bits |
| 305 | ----------------------- | 276 | ----------------------- |
| 306 | 277 | ||
| @@ -33,9 +33,8 @@ AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit):: · 32 unmodified lines | |||
| 33 | 0000000000000000 0000ffffffffffff 256TB user | 33 | 0000000000000000 0000ffffffffffff 256TB user |
| 34 | ffff000000000000 ffff7fffffffffff 128TB kernel logical memory map | 34 | ffff000000000000 ffff7fffffffffff 128TB kernel logical memory map |
| 35 | [ffff600000000000 ffff7fffffffffff] 32TB [kasan shadow region] | 35 | [ffff600000000000 ffff7fffffffffff] 32TB [kasan shadow region] |
| 36 | ffff800000000000 ffff800007ffffff 128MB bpf jit region | 36 | ffff800000000000 ffff800007ffffff 128MB modules |
| 37 | ffff800008000000 ffff80000fffffff 128MB modules | 37 | ffff800008000000 fffffbffefffffff 124TB vmalloc |
| 38 | ffff800010000000 fffffbffefffffff 124TB vmalloc | ||
| 39 | fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down) | 38 | fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down) |
| 40 | fffffbfffe000000 fffffbfffe7fffff 8MB [guard region] | 39 | fffffbfffe000000 fffffbfffe7fffff 8MB [guard region] |
| 41 | fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space | 40 | fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space |
| @@ -51,9 +50,8 @@ AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support): · 9 unmodified lines | |||
| 51 | 0000000000000000 000fffffffffffff 4PB user | 50 | 0000000000000000 000fffffffffffff 4PB user |
| 52 | fff0000000000000 ffff7fffffffffff ~4PB kernel logical memory map | 51 | fff0000000000000 ffff7fffffffffff ~4PB kernel logical memory map |
| 53 | [fffd800000000000 ffff7fffffffffff] 512TB [kasan shadow region] | 52 | [fffd800000000000 ffff7fffffffffff] 512TB [kasan shadow region] |
| 54 | ffff800000000000 ffff800007ffffff 128MB bpf jit region | 53 | ffff800000000000 ffff800007ffffff 128MB modules |
| 55 | ffff800008000000 ffff80000fffffff 128MB modules | 54 | ffff800008000000 fffffbffefffffff 124TB vmalloc |
| 56 | ffff800010000000 fffffbffefffffff 124TB vmalloc | ||
| 57 | fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down) | 55 | fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down) |
| 58 | fffffbfffe000000 fffffbfffe7fffff 8MB [guard region] | 56 | fffffbfffe000000 fffffbfffe7fffff 8MB [guard region] |
| 59 | fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space | 57 | fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space |
| @@ -52,6 +52,8 @@ stable kernels. · 51 unmodified lines | |||
| 52 | | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | | 52 | | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | |
| 53 | +----------------+-----------------+-----------------+-----------------------------+ | 53 | +----------------+-----------------+-----------------+-----------------------------+ |
| 54 | +----------------+-----------------+-----------------+-----------------------------+ | 54 | +----------------+-----------------+-----------------+-----------------------------+ |
| 55 | | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | | ||
| 56 | +----------------+-----------------+-----------------+-----------------------------+ | ||
| 55 | | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | | 57 | | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | |
| 56 | +----------------+-----------------+-----------------+-----------------------------+ | 58 | +----------------+-----------------+-----------------+-----------------------------+ |
| 57 | | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | | 59 | | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | |
| @@ -82,10 +84,14 @@ stable kernels. · 24 unmodified lines | |||
| 82 | +----------------+-----------------+-----------------+-----------------------------+ | 84 | +----------------+-----------------+-----------------+-----------------------------+ |
| 83 | | ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 | | 85 | | ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 | |
| 84 | +----------------+-----------------+-----------------+-----------------------------+ | 86 | +----------------+-----------------+-----------------+-----------------------------+ |
| 87 | | ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 | | ||
| 88 | +----------------+-----------------+-----------------+-----------------------------+ | ||
| 85 | | ARM | Cortex-A72 | #853709 | N/A | | 89 | | ARM | Cortex-A72 | #853709 | N/A | |
| 86 | +----------------+-----------------+-----------------+-----------------------------+ | 90 | +----------------+-----------------+-----------------+-----------------------------+ |
| 87 | | ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 | | 91 | | ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 | |
| 88 | +----------------+-----------------+-----------------+-----------------------------+ | 92 | +----------------+-----------------+-----------------+-----------------------------+ |
| 93 | | ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 | | ||
| 94 | +----------------+-----------------+-----------------+-----------------------------+ | ||
| 89 | | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | | 95 | | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | |
| 90 | +----------------+-----------------+-----------------+-----------------------------+ | 96 | +----------------+-----------------+-----------------+-----------------------------+ |
| 91 | | ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 | | 97 | | ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 | |
| @@ -102,6 +108,8 @@ stable kernels. · 10 unmodified lines | |||
| 102 | +----------------+-----------------+-----------------+-----------------------------+ | 108 | +----------------+-----------------+-----------------+-----------------------------+ |
| 103 | | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 | | 109 | | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 | |
| 104 | +----------------+-----------------+-----------------+-----------------------------+ | 110 | +----------------+-----------------+-----------------+-----------------------------+ |
| 111 | | ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 | | ||
| 112 | +----------------+-----------------+-----------------+-----------------------------+ | ||
| 105 | | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | | 113 | | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | |
| 106 | +----------------+-----------------+-----------------+-----------------------------+ | 114 | +----------------+-----------------+-----------------+-----------------------------+ |
| 107 | | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | | 115 | | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | |
| @@ -58,13 +58,11 @@ Like with atomic_t, the rule of thumb is: · 57 unmodified lines | |||
| 58 | 58 | ||
| 59 | - RMW operations that have a return value are fully ordered. | 59 | - RMW operations that have a return value are fully ordered. |
| 60 | 60 | ||
| 61 | - RMW operations that are conditional are unordered on FAILURE, | 61 | - RMW operations that are conditional are fully ordered. |
| 62 | otherwise the above rules apply. In the case of test_and_{}_bit() operations, | ||
| 63 | if the bit in memory is unchanged by the operation then it is deemed to have | ||
| 64 | failed. | ||
| 65 | 62 | ||
| 66 | Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and | 63 | Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics, |
| 67 | clear_bit_unlock() which has RELEASE semantics. | 64 | clear_bit_unlock() which has RELEASE semantics and test_bit_acquire which has |
| 65 | ACQUIRE semantics. | ||
| 68 | 66 | ||
| 69 | Since a platform only has a single means of achieving atomic operations | 67 | Since a platform only has a single means of achieving atomic operations |
| 70 | the same barriers as for atomic_t are used, see atomic_t.txt. | 68 | the same barriers as for atomic_t are used, see atomic_t.txt. |
| @@ -23,3 +23,4 @@ Block · 22 unmodified lines | |||
| 23 | stat | 23 | stat |
| 24 | switching-sched | 24 | switching-sched |
| 25 | writeback_cache_control | 25 | writeback_cache_control |
| 26 | ublk | ||
| @@ -72,6 +72,28 @@ submit_queues=[1..nr_cpus]: Default: 1 · 71 unmodified lines | |||
| 72 | hw_queue_depth=[0..qdepth]: Default: 64 | 72 | hw_queue_depth=[0..qdepth]: Default: 64 |
| 73 | The hardware queue depth of the device. | 73 | The hardware queue depth of the device. |
| 74 | 74 | ||
| 75 | memory_backed=[0/1]: Default: 0 | ||
| 76 | Whether or not to use a memory buffer to respond to IO requests | ||
| 77 | |||
| 78 | = ============================================= | ||
| 79 | 0 Transfer no data in response to IO requests | ||
| 80 | 1 Use a memory buffer to respond to IO requests | ||
| 81 | = ============================================= | ||
| 82 | |||
| 83 | discard=[0/1]: Default: 0 | ||
| 84 | Support discard operations (requires memory-backed null_blk device). | ||
| 85 | |||
| 86 | = ===================================== | ||
| 87 | 0 Do not support discard operations | ||
| 88 | 1 Enable support for discard operations | ||
| 89 | = ===================================== | ||
| 90 | |||
| 91 | cache_size=[Size in MB]: Default: 0 | ||
| 92 | Cache size in MB for memory-backed device. | ||
| 93 | |||
| 94 | mbps=[Maximum bandwidth in MB/s]: Default: 0 (no limit) | ||
| 95 | Bandwidth limit for device performance. | ||
| 96 | |||
| 75 | Multi-queue specific parameters | 97 | Multi-queue specific parameters |
| 76 | ------------------------------- | 98 | ------------------------------- |
| 77 | 99 | ||
| @@ -0,0 +1,253 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0 | ||
| 2 | |||
| 3 | =========================================== | ||
| 4 | Userspace block device driver (ublk driver) | ||
| 5 | =========================================== | ||
| 6 | |||
| 7 | Overview | ||
| 8 | ======== | ||
| 9 | |||
| 10 | ublk is a generic framework for implementing block device logic from userspace. | ||
| 11 | The motivation behind it is that moving virtual block drivers into userspace, | ||
| 12 | such as loop, nbd and similar can be very helpful. It can help to implement | ||
| 13 | new virtual block device such as ublk-qcow2 (there are several attempts of | ||
| 14 | implementing qcow2 driver in kernel). | ||
| 15 | |||
| 16 | Userspace block devices are attractive because: | ||
| 17 | |||
| 18 | - They can be written many programming languages. | ||
| 19 | - They can use libraries that are not available in the kernel. | ||
| 20 | - They can be debugged with tools familiar to application developers. | ||
| 21 | - Crashes do not kernel panic the machine. | ||
| 22 | - Bugs are likely to have a lower security impact than bugs in kernel | ||
| 23 | code. | ||
| 24 | - They can be installed and updated independently of the kernel. | ||
| 25 | - They can be used to simulate block device easily with user specified | ||
| 26 | parameters/setting for test/debug purpose | ||
| 27 | |||
| 28 | ublk block device (``/dev/ublkb*``) is added by ublk driver. Any IO request | ||
| 29 | on the device will be forwarded to ublk userspace program. For convenience, | ||
| 30 | in this document, ``ublk server`` refers to generic ublk userspace | ||
| 31 | program. ``ublksrv`` [#userspace]_ is one of such implementation. It | ||
| 32 | provides ``libublksrv`` [#userspace_lib]_ library for developing specific | ||
| 33 | user block device conveniently, while also generic type block device is | ||
| 34 | included, such as loop and null. Richard W.M. Jones wrote userspace nbd device | ||
| 35 | ``nbdublk`` [#userspace_nbdublk]_ based on ``libublksrv`` [#userspace_lib]_. | ||
| 36 | |||
| 37 | After the IO is handled by userspace, the result is committed back to the | ||
| 38 | driver, thus completing the request cycle. This way, any specific IO handling | ||
| 39 | logic is totally done by userspace, such as loop's IO handling, NBD's IO | ||
| 40 | communication, or qcow2's IO mapping. | ||
| 41 | |||
| 42 | ``/dev/ublkb*`` is driven by blk-mq request-based driver. Each request is | ||
| 43 | assigned by one queue wide unique tag. ublk server assigns unique tag to each | ||
| 44 | IO too, which is 1:1 mapped with IO of ``/dev/ublkb*``. | ||
| 45 | |||
| 46 | Both the IO request forward and IO handling result committing are done via | ||
| 47 | ``io_uring`` passthrough command; that is why ublk is also one io_uring based | ||
| 48 | block driver. It has been observed that using io_uring passthrough command can | ||
| 49 | give better IOPS than block IO; which is why ublk is one of high performance | ||
| 50 | implementation of userspace block device: not only IO request communication is | ||
| 51 | done by io_uring, but also the preferred IO handling in ublk server is io_uring | ||
| 52 | based approach too. | ||
| 53 | |||
| 54 | ublk provides control interface to set/get ublk block device parameters. | ||
| 55 | The interface is extendable and kabi compatible: basically any ublk request | ||
| 56 | queue's parameter or ublk generic feature parameters can be set/get via the | ||
| 57 | interface. Thus, ublk is generic userspace block device framework. | ||
| 58 | For example, it is easy to setup a ublk device with specified block | ||
| 59 | parameters from userspace. | ||
| 60 | |||
| 61 | Using ublk | ||
| 62 | ========== | ||
| 63 | |||
| 64 | ublk requires userspace ublk server to handle real block device logic. | ||
| 65 | |||
| 66 | Below is example of using ``ublksrv`` to provide ublk-based loop device. | ||
| 67 | |||
| 68 | - add a device:: | ||
| 69 | |||
| 70 | ublk add -t loop -f ublk-loop.img | ||
| 71 | |||
| 72 | - format with xfs, then use it:: | ||
| 73 | |||
| 74 | mkfs.xfs /dev/ublkb0 | ||
| 75 | mount /dev/ublkb0 /mnt | ||
| 76 | # do anything. all IOs are handled by io_uring | ||
| 77 | ... | ||
| 78 | umount /mnt | ||
| 79 | |||
| 80 | - list the devices with their info:: | ||
| 81 | |||
| 82 | ublk list | ||
| 83 | |||
| 84 | - delete the device:: | ||
| 85 | |||
| 86 | ublk del -a | ||
| 87 | ublk del -n $ublk_dev_id | ||
| 88 | |||
| 89 | See usage details in README of ``ublksrv`` [#userspace_readme]_. | ||
| 90 | |||
| 91 | Design | ||
| 92 | ====== | ||
| 93 | |||
| 94 | Control plane | ||
| 95 | ------------- | ||
| 96 | |||
| 97 | ublk driver provides global misc device node (``/dev/ublk-control``) for | ||
| 98 | managing and controlling ublk devices with help of several control commands: | ||
| 99 | |||
| 100 | - ``UBLK_CMD_ADD_DEV`` | ||
| 101 | |||
| 102 | Add a ublk char device (``/dev/ublkc*``) which is talked with ublk server | ||
| 103 | WRT IO command communication. Basic device info is sent together with this | ||
| 104 | command. It sets UAPI structure of ``ublksrv_ctrl_dev_info``, | ||
| 105 | such as ``nr_hw_queues``, ``queue_depth``, and max IO request buffer size, | ||
| 106 | for which the info is negotiated with the driver and sent back to the server. | ||
| 107 | When this command is completed, the basic device info is immutable. | ||
| 108 | |||
| 109 | - ``UBLK_CMD_SET_PARAMS`` / ``UBLK_CMD_GET_PARAMS`` | ||
| 110 | |||
| 111 | Set or get parameters of the device, which can be either generic feature | ||
| 112 | related, or request queue limit related, but can't be IO logic specific, | ||
| 113 | because the driver does not handle any IO logic. This command has to be | ||
| 114 | sent before sending ``UBLK_CMD_START_DEV``. | ||
| 115 | |||
| 116 | - ``UBLK_CMD_START_DEV`` | ||
| 117 | |||
| 118 | After the server prepares userspace resources (such as creating per-queue | ||
| 119 | pthread & io_uring for handling ublk IO), this command is sent to the | ||
| 120 | driver for allocating & exposing ``/dev/ublkb*``. Parameters set via | ||
| 121 | ``UBLK_CMD_SET_PARAMS`` are applied for creating the device. | ||
| 122 | |||
| 123 | - ``UBLK_CMD_STOP_DEV`` | ||
| 124 | |||
| 125 | Halt IO on ``/dev/ublkb*`` and remove the device. When this command returns, | ||
| 126 | ublk server will release resources (such as destroying per-queue pthread & | ||
| 127 | io_uring). | ||
| 128 | |||
| 129 | - ``UBLK_CMD_DEL_DEV`` | ||
| 130 | |||
| 131 | Remove ``/dev/ublkc*``. When this command returns, the allocated ublk device | ||
| 132 | number can be reused. | ||
| 133 | |||
| 134 | - ``UBLK_CMD_GET_QUEUE_AFFINITY`` | ||
| 135 | |||
| 136 | When ``/dev/ublkc`` is added, the driver creates block layer tagset, so | ||
| 137 | that each queue's affinity info is available. The server sends | ||
| 138 | ``UBLK_CMD_GET_QUEUE_AFFINITY`` to retrieve queue affinity info. It can | ||
| 139 | set up the per-queue context efficiently, such as bind affine CPUs with IO | ||
| 140 | pthread and try to allocate buffers in IO thread context. | ||
| 141 | |||
| 142 | - ``UBLK_CMD_GET_DEV_INFO`` | ||
| 143 | |||
| 144 | For retrieving device info via ``ublksrv_ctrl_dev_info``. It is the server's | ||
| 145 | responsibility to save IO target specific info in userspace. | ||
| 146 | |||
| 147 | Data plane | ||
| 148 | ---------- | ||
| 149 | |||
| 150 | ublk server needs to create per-queue IO pthread & io_uring for handling IO | ||
| 151 | commands via io_uring passthrough. The per-queue IO pthread | ||
| 152 | focuses on IO handling and shouldn't handle any control & management | ||
| 153 | tasks. | ||
| 154 | |||
| 155 | The's IO is assigned by a unique tag, which is 1:1 mapping with IO | ||
| 156 | request of ``/dev/ublkb*``. | ||
| 157 | |||
| 158 | UAPI structure of ``ublksrv_io_desc`` is defined for describing each IO from | ||
| 159 | the driver. A fixed mmaped area (array) on ``/dev/ublkc*`` is provided for | ||
| 160 | exporting IO info to the server; such as IO offset, length, OP/flags and | ||
| 161 | buffer address. Each ``ublksrv_io_desc`` instance can be indexed via queue id | ||
| 162 | and IO tag directly. | ||
| 163 | |||
| 164 | The following IO commands are communicated via io_uring passthrough command, | ||
| 165 | and each command is only for forwarding the IO and committing the result | ||
| 166 | with specified IO tag in the command data: | ||
| 167 | |||
| 168 | - ``UBLK_IO_FETCH_REQ`` | ||
| 169 | |||
| 170 | Sent from the server IO pthread for fetching future incoming IO requests | ||
| 171 | destined to ``/dev/ublkb*``. This command is sent only once from the server | ||
| 172 | IO pthread for ublk driver to setup IO forward environment. | ||
| 173 | |||
| 174 | - ``UBLK_IO_COMMIT_AND_FETCH_REQ`` | ||
| 175 | |||
| 176 | When an IO request is destined to ``/dev/ublkb*``, the driver stores | ||
| 177 | the IO's ``ublksrv_io_desc`` to the specified mapped area; then the | ||
| 178 | previous received IO command of this IO tag (either ``UBLK_IO_FETCH_REQ`` | ||
| 179 | or ``UBLK_IO_COMMIT_AND_FETCH_REQ)`` is completed, so the server gets | ||
| 180 | the IO notification via io_uring. | ||
| 181 | |||
| 182 | After the server handles the IO, its result is committed back to the | ||
| 183 | driver by sending ``UBLK_IO_COMMIT_AND_FETCH_REQ`` back. Once ublkdrv | ||
| 184 | received this command, it parses the result and complete the request to | ||
| 185 | ``/dev/ublkb*``. In the meantime setup environment for fetching future | ||
| 186 | requests with the same IO tag. That is, ``UBLK_IO_COMMIT_AND_FETCH_REQ`` | ||
| 187 | is reused for both fetching request and committing back IO result. | ||
| 188 | |||
| 189 | - ``UBLK_IO_NEED_GET_DATA`` | ||
| 190 | |||
| 191 | With ``UBLK_F_NEED_GET_DATA`` enabled, the WRITE request will be firstly | ||
| 192 | issued to ublk server without data copy. Then, IO backend of ublk server | ||
| 193 | receives the request and it can allocate data buffer and embed its addr | ||
| 194 | inside this new io command. After the kernel driver gets the command, | ||
| 195 | data copy is done from request pages to this backend's buffer. Finally, | ||
| 196 | backend receives the request again with data to be written and it can | ||
| 197 | truly handle the request. | ||
| 198 | |||
| 199 | ``UBLK_IO_NEED_GET_DATA`` adds one additional round-trip and one | ||
| 200 | io_uring_enter() syscall. Any user thinks that it may lower performance | ||
| 201 | should not enable UBLK_F_NEED_GET_DATA. ublk server pre-allocates IO | ||
| 202 | buffer for each IO by default. Any new project should try to use this | ||
| 203 | buffer to communicate with ublk driver. However, existing project may | ||
| 204 | break or not able to consume the new buffer interface; that's why this | ||
| 205 | command is added for backwards compatibility so that existing projects | ||
| 206 | can still consume existing buffers. | ||
| 207 | |||
| 208 | - data copy between ublk server IO buffer and ublk block IO request | ||
| 209 | |||
| 210 | The driver needs to copy the block IO request pages into the server buffer | ||
| 211 | (pages) first for WRITE before notifying the server of the coming IO, so | ||
| 212 | that the server can handle WRITE request. | ||
| 213 | |||
| 214 | When the server handles READ request and sends | ||
| 215 | ``UBLK_IO_COMMIT_AND_FETCH_REQ`` to the server, ublkdrv needs to copy | ||
| 216 | the server buffer (pages) read to the IO request pages. | ||
| 217 | |||
| 218 | Future development | ||
| 219 | ================== | ||
| 220 | |||
| 221 | Container-aware ublk deivice | ||
| 222 | ---------------------------- | ||
| 223 | |||
| 224 | ublk driver doesn't handle any IO logic. Its function is well defined | ||
| 225 | for now and very limited userspace interfaces are needed, which is also | ||
| 226 | well defined too. It is possible to make ublk devices container-aware block | ||
| 227 | devices in future as Stefan Hajnoczi suggested [#stefan]_, by removing | ||
| 228 | ADMIN privilege. | ||
| 229 | |||
| 230 | Zero copy | ||
| 231 | --------- | ||
| 232 | |||
| 233 | Zero copy is a generic requirement for nbd, fuse or similar drivers. A | ||
| 234 | problem [#xiaoguang]_ Xiaoguang mentioned is that pages mapped to userspace | ||
| 235 | can't be remapped any more in kernel with existing mm interfaces. This can | ||
| 236 | occurs when destining direct IO to ``/dev/ublkb*``. Also, he reported that | ||
| 237 | big requests (IO size >= 256 KB) may benefit a lot from zero copy. | ||
| 238 | |||
| 239 | |||
| 240 | References | ||
| 241 | ========== | ||
| 242 | |||
| 243 | .. [#userspace] https://github.com/ming1/ubdsrv | ||
| 244 | |||
| 245 | .. [#userspace_lib] https://github.com/ming1/ubdsrv/tree/master/lib | ||
| 246 | |||
| 247 | .. [#userspace_nbdublk] https://gitlab.com/rwmjones/libnbd/-/tree/nbdublk | ||
| 248 | |||
| 249 | .. [#userspace_readme] https://github.com/ming1/ubdsrv/blob/master/README | ||
| 250 | |||
| 251 | .. [#stefan] https://lore.kernel.org/linux-block/YoOr6jBfgVm8GvWg@stefanha-x1.localdomain/ | ||
| 252 | |||
| 253 | .. [#xiaoguang] https://lore.kernel.org/linux-block/YoOr6jBfgVm8GvWg@stefanha-x1.localdomain/ | ||
| @@ -214,6 +214,12 @@ A: NO. Tracepoints are tied to internal implementation details hence they are · 213 unmodified lines | |||
| 214 | subject to change and can break with newer kernels. BPF programs need to change | 214 | subject to change and can break with newer kernels. BPF programs need to change |
| 215 | accordingly when this happens. | 215 | accordingly when this happens. |
| 216 | 216 | ||
| 217 | Q: Are places where kprobes can attach part of the stable ABI? | ||
| 218 | -------------------------------------------------------------- | ||
| 219 | A: NO. The places to which kprobes can attach are internal implementation | ||
| 220 | details, which means that they are subject to change and can break with | ||
| 221 | newer kernels. BPF programs need to change accordingly when this happens. | ||
| 222 | |||
| 217 | Q: How much stack space a BPF program uses? | 223 | Q: How much stack space a BPF program uses? |
| 218 | ------------------------------------------- | 224 | ------------------------------------------- |
| 219 | A: Currently all program types are limited to 512 bytes of stack | 225 | A: Currently all program types are limited to 512 bytes of stack |
| @@ -273,3 +279,22 @@ cc (congestion-control) implementations. If any of these kernel · 53 unmodified lines | |||
| 273 | functions has changed, both the in-tree and out-of-tree kernel tcp cc | 279 | functions has changed, both the in-tree and out-of-tree kernel tcp cc |
| 274 | implementations have to be changed. The same goes for the bpf | 280 | implementations have to be changed. The same goes for the bpf |
| 275 | programs and they have to be adjusted accordingly. | 281 | programs and they have to be adjusted accordingly. |
| 282 | |||
| 283 | Q: Attaching to arbitrary kernel functions is an ABI? | ||
| 284 | ----------------------------------------------------- | ||
| 285 | Q: BPF programs can be attached to many kernel functions. Do these | ||
| 286 | kernel functions become part of the ABI? | ||
| 287 | |||
| 288 | A: NO. | ||
| 289 | |||
| 290 | The kernel function prototypes will change, and BPF programs attaching to | ||
| 291 | them will need to change. The BPF compile-once-run-everywhere (CO-RE) | ||
| 292 | should be used in order to make it easier to adapt your BPF programs to | ||
| 293 | different versions of the kernel. | ||
| 294 | |||
| 295 | Q: Marking a function with BTF_ID makes that function an ABI? | ||
| 296 | ------------------------------------------------------------- | ||
| 297 | A: NO. | ||
| 298 | |||
| 299 | The BTF_ID macro does not cause a function to become part of the ABI | ||
| 300 | any more than does the EXPORT_SYMBOL_GPL macro. | ||
| @@ -74,7 +74,7 @@ sequentially and type id is assigned to each recognized type starting from id · 73 unmodified lines | |||
| 74 | #define BTF_KIND_ARRAY 3 /* Array */ | 74 | #define BTF_KIND_ARRAY 3 /* Array */ |
| 75 | #define BTF_KIND_STRUCT 4 /* Struct */ | 75 | #define BTF_KIND_STRUCT 4 /* Struct */ |
| 76 | #define BTF_KIND_UNION 5 /* Union */ | 76 | #define BTF_KIND_UNION 5 /* Union */ |
| 77 | #define BTF_KIND_ENUM 6 /* Enumeration */ | 77 | #define BTF_KIND_ENUM 6 /* Enumeration up to 32-bit values */ |
| 78 | #define BTF_KIND_FWD 7 /* Forward */ | 78 | #define BTF_KIND_FWD 7 /* Forward */ |
| 79 | #define BTF_KIND_TYPEDEF 8 /* Typedef */ | 79 | #define BTF_KIND_TYPEDEF 8 /* Typedef */ |
| 80 | #define BTF_KIND_VOLATILE 9 /* Volatile */ | 80 | #define BTF_KIND_VOLATILE 9 /* Volatile */ |
| @@ -87,6 +87,7 @@ sequentially and type id is assigned to each recognized type starting from id · 6 unmodified lines | |||
| 87 | #define BTF_KIND_FLOAT 16 /* Floating point */ | 87 | #define BTF_KIND_FLOAT 16 /* Floating point */ |
| 88 | #define BTF_KIND_DECL_TAG 17 /* Decl Tag */ | 88 | #define BTF_KIND_DECL_TAG 17 /* Decl Tag */ |
| 89 | #define BTF_KIND_TYPE_TAG 18 /* Type Tag */ | 89 | #define BTF_KIND_TYPE_TAG 18 /* Type Tag */ |
| 90 | #define BTF_KIND_ENUM64 19 /* Enumeration up to 64-bit values */ | ||
| 90 | 91 | ||
| 91 | Note that the type section encodes debug info, not just pure types. | 92 | Note that the type section encodes debug info, not just pure types. |
| 92 | ``BTF_KIND_FUNC`` is not a type, and it represents a defined subprogram. | 93 | ``BTF_KIND_FUNC`` is not a type, and it represents a defined subprogram. |
| @@ -101,10 +102,10 @@ Each type contains the following common data:: · 8 unmodified lines | |||
| 101 | * bits 24-28: kind (e.g. int, ptr, array...etc) | 102 | * bits 24-28: kind (e.g. int, ptr, array...etc) |
| 102 | * bits 29-30: unused | 103 | * bits 29-30: unused |
| 103 | * bit 31: kind_flag, currently used by | 104 | * bit 31: kind_flag, currently used by |
| 104 | * struct, union and fwd | 105 | * struct, union, fwd, enum and enum64. |
| 105 | */ | 106 | */ |
| 106 | __u32 info; | 107 | __u32 info; |
| 107 | /* "size" is used by INT, ENUM, STRUCT and UNION. | 108 | /* "size" is used by INT, ENUM, STRUCT, UNION and ENUM64. |
| 108 | * "size" tells the size of the type it is describing. | 109 | * "size" tells the size of the type it is describing. |
| 109 | * | 110 | * |
| 110 | * "type" is used by PTR, TYPEDEF, VOLATILE, CONST, RESTRICT, | 111 | * "type" is used by PTR, TYPEDEF, VOLATILE, CONST, RESTRICT, |
| @@ -281,10 +282,10 @@ modes exist: · 170 unmodified lines | |||
| 281 | 282 | ||
| 282 | ``struct btf_type`` encoding requirement: | 283 | ``struct btf_type`` encoding requirement: |
| 283 | * ``name_off``: 0 or offset to a valid C identifier | 284 | * ``name_off``: 0 or offset to a valid C identifier |
| 284 | * ``info.kind_flag``: 0 | 285 | * ``info.kind_flag``: 0 for unsigned, 1 for signed |
| 285 | * ``info.kind``: BTF_KIND_ENUM | 286 | * ``info.kind``: BTF_KIND_ENUM |
| 286 | * ``info.vlen``: number of enum values | 287 | * ``info.vlen``: number of enum values |
| 287 | * ``size``: 4 | 288 | * ``size``: 1/2/4/8 |
| 288 | 289 | ||
| 289 | ``btf_type`` is followed by ``info.vlen`` number of ``struct btf_enum``.:: | 290 | ``btf_type`` is followed by ``info.vlen`` number of ``struct btf_enum``.:: |
| 290 | 291 | ||
| @@ -297,6 +298,10 @@ The ``btf_enum`` encoding: · 6 unmodified lines | |||
| 297 | * ``name_off``: offset to a valid C identifier | 298 | * ``name_off``: offset to a valid C identifier |
| 298 | * ``val``: any value | 299 | * ``val``: any value |
| 299 | 300 | ||
| 301 | If the original enum value is signed and the size is less than 4, | ||
| 302 | that value will be sign extended into 4 bytes. If the size is 8, | ||
| 303 | the value will be truncated into 4 bytes. | ||
| 304 | |||
| 300 | 2.2.7 BTF_KIND_FWD | 305 | 2.2.7 BTF_KIND_FWD |
| 301 | ~~~~~~~~~~~~~~~~~~ | 306 | ~~~~~~~~~~~~~~~~~~ |
| 302 | 307 | ||
| @@ -364,7 +369,8 @@ No additional type data follow ``btf_type``. · 61 unmodified lines | |||
| 364 | * ``name_off``: offset to a valid C identifier | 369 | * ``name_off``: offset to a valid C identifier |
| 365 | * ``info.kind_flag``: 0 | 370 | * ``info.kind_flag``: 0 |
| 366 | * ``info.kind``: BTF_KIND_FUNC | 371 | * ``info.kind``: BTF_KIND_FUNC |
| 367 | * ``info.vlen``: 0 | 372 | * ``info.vlen``: linkage information (BTF_FUNC_STATIC, BTF_FUNC_GLOBAL |
| 373 | or BTF_FUNC_EXTERN) | ||
| 368 | * ``type``: a BTF_KIND_FUNC_PROTO type | 374 | * ``type``: a BTF_KIND_FUNC_PROTO type |
| 369 | 375 | ||
| 370 | No additional type data follow ``btf_type``. | 376 | No additional type data follow ``btf_type``. |
| @@ -375,6 +381,9 @@ type. The BTF_KIND_FUNC may in turn be referenced by a func_info in the · 4 unmodified lines | |||
| 375 | :ref:`BTF_Ext_Section` (ELF) or in the arguments to :ref:`BPF_Prog_Load` | 381 | :ref:`BTF_Ext_Section` (ELF) or in the arguments to :ref:`BPF_Prog_Load` |
| 376 | (ABI). | 382 | (ABI). |
| 377 | 383 | ||
| 384 | Currently, only linkage values of BTF_FUNC_STATIC and BTF_FUNC_GLOBAL are | ||
| 385 | supported in the kernel. | ||
| 386 | |||
| 378 | 2.2.13 BTF_KIND_FUNC_PROTO | 387 | 2.2.13 BTF_KIND_FUNC_PROTO |
| 379 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ | 388 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 380 | 389 | ||
| @@ -493,7 +502,7 @@ the attribute is applied to a ``struct``/``union`` member or · 112 unmodified lines | |||
| 493 | a ``func`` argument, and ``btf_decl_tag.component_idx`` should be a | 502 | a ``func`` argument, and ``btf_decl_tag.component_idx`` should be a |
| 494 | valid index (starting from 0) pointing to a member or an argument. | 503 | valid index (starting from 0) pointing to a member or an argument. |
| 495 | 504 | ||
| 496 | 2.2.17 BTF_KIND_TYPE_TAG | 505 | 2.2.18 BTF_KIND_TYPE_TAG |
| 497 | ~~~~~~~~~~~~~~~~~~~~~~~~ | 506 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
| 498 | 507 | ||
| 499 | ``struct btf_type`` encoding requirement: | 508 | ``struct btf_type`` encoding requirement: |
| @@ -516,6 +525,32 @@ type_tag, then zero or more const/volatile/restrict/typedef · 16 unmodified lines | |||
| 516 | and finally the base type. The base type is one of | 525 | and finally the base type. The base type is one of |
| 517 | int, ptr, array, struct, union, enum, func_proto and float types. | 526 | int, ptr, array, struct, union, enum, func_proto and float types. |
| 518 | 527 | ||
| 528 | 2.2.19 BTF_KIND_ENUM64 | ||
| 529 | ~~~~~~~~~~~~~~~~~~~~~~ | ||
| 530 | |||
| 531 | ``struct btf_type`` encoding requirement: | ||
| 532 | * ``name_off``: 0 or offset to a valid C identifier | ||
| 533 | * ``info.kind_flag``: 0 for unsigned, 1 for signed | ||
| 534 | * ``info.kind``: BTF_KIND_ENUM64 | ||
| 535 | * ``info.vlen``: number of enum values | ||
| 536 | * ``size``: 1/2/4/8 | ||
| 537 | |||
| 538 | ``btf_type`` is followed by ``info.vlen`` number of ``struct btf_enum64``.:: | ||
| 539 | |||
| 540 | struct btf_enum64 { | ||
| 541 | __u32 name_off; | ||
| 542 | __u32 val_lo32; | ||
| 543 | __u32 val_hi32; | ||
| 544 | }; | ||
| 545 | |||
| 546 | The ``btf_enum64`` encoding: | ||
| 547 | * ``name_off``: offset to a valid C identifier | ||
| 548 | * ``val_lo32``: lower 32-bit value for a 64-bit value | ||
| 549 | * ``val_hi32``: high 32-bit value for a 64-bit value | ||
| 550 | |||
| 551 | If the original enum value is signed and the size is less than 8, | ||
| 552 | that value will be sign extended into 8 bytes. | ||
| 553 | |||
| 519 | 3. BTF Kernel API | 554 | 3. BTF Kernel API |
| 520 | ================= | 555 | ================= |
| 521 | 556 | ||
| @@ -19,6 +19,7 @@ that goes into great technical depth about the BPF Architecture. · 18 unmodified lines | |||
| 19 | faq | 19 | faq |
| 20 | syscall_api | 20 | syscall_api |
| 21 | helpers | 21 | helpers |
| 22 | kfuncs | ||
| 22 | programs | 23 | programs |
| 23 | maps | 24 | maps |
| 24 | bpf_prog_run | 25 | bpf_prog_run |
| @@ -127,7 +127,7 @@ BPF_XOR | BPF_K | BPF_ALU64 means:: · 126 unmodified lines | |||
| 127 | Byte swap instructions | 127 | Byte swap instructions |
| 128 | ---------------------- | 128 | ---------------------- |
| 129 | 129 | ||
| 130 | The byte swap instructions use an instruction class of ``BFP_ALU`` and a 4-bit | 130 | The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit |
| 131 | code field of ``BPF_END``. | 131 | code field of ``BPF_END``. |
| 132 | 132 | ||
| 133 | The byte swap instructions operate on the destination register | 133 | The byte swap instructions operate on the destination register |
| @@ -351,7 +351,7 @@ These instructions have seven implicit operands: · 217 unmodified lines | |||
| 351 | * Register R0 is an implicit output which contains the data fetched from | 351 | * Register R0 is an implicit output which contains the data fetched from |
| 352 | the packet. | 352 | the packet. |
| 353 | * Registers R1-R5 are scratch registers that are clobbered after a call to | 353 | * Registers R1-R5 are scratch registers that are clobbered after a call to |
| 354 | ``BPF_ABS | BPF_LD`` or ``BPF_IND`` | BPF_LD instructions. | 354 | ``BPF_ABS | BPF_LD`` or ``BPF_IND | BPF_LD`` instructions. |
| 355 | 355 | ||
| 356 | These instructions have an implicit program exit condition as well. When an | 356 | These instructions have an implicit program exit condition as well. When an |
| 357 | eBPF program is trying to access the data beyond the packet boundary, the | 357 | eBPF program is trying to access the data beyond the packet boundary, the |
| @@ -0,0 +1,170 @@ | |||
| 1 | ============================= | ||
| 2 | BPF Kernel Functions (kfuncs) | ||
| 3 | ============================= | ||
| 4 | |||
| 5 | 1. Introduction | ||
| 6 | =============== | ||
| 7 | |||
| 8 | BPF Kernel Functions or more commonly known as kfuncs are functions in the Linux | ||
| 9 | kernel which are exposed for use by BPF programs. Unlike normal BPF helpers, | ||
| 10 | kfuncs do not have a stable interface and can change from one kernel release to | ||
| 11 | another. Hence, BPF programs need to be updated in response to changes in the | ||
| 12 | kernel. | ||
| 13 | |||
| 14 | 2. Defining a kfunc | ||
| 15 | =================== | ||
| 16 | |||
| 17 | There are two ways to expose a kernel function to BPF programs, either make an | ||
| 18 | existing function in the kernel visible, or add a new wrapper for BPF. In both | ||
| 19 | cases, care must be taken that BPF program can only call such function in a | ||
| 20 | valid context. To enforce this, visibility of a kfunc can be per program type. | ||
| 21 | |||
| 22 | If you are not creating a BPF wrapper for existing kernel function, skip ahead | ||
| 23 | to :ref:`BPF_kfunc_nodef`. | ||
| 24 | |||
| 25 | 2.1 Creating a wrapper kfunc | ||
| 26 | ---------------------------- | ||
| 27 | |||
| 28 | When defining a wrapper kfunc, the wrapper function should have extern linkage. | ||
| 29 | This prevents the compiler from optimizing away dead code, as this wrapper kfunc | ||
| 30 | is not invoked anywhere in the kernel itself. It is not necessary to provide a | ||
| 31 | prototype in a header for the wrapper kfunc. | ||
| 32 | |||
| 33 | An example is given below:: | ||
| 34 | |||
| 35 | /* Disables missing prototype warnings */ | ||
| 36 | __diag_push(); | ||
| 37 | __diag_ignore_all("-Wmissing-prototypes", | ||
| 38 | "Global kfuncs as their definitions will be in BTF"); | ||
| 39 | |||
| 40 | struct task_struct *bpf_find_get_task_by_vpid(pid_t nr) | ||
| 41 | { | ||
| 42 | return find_get_task_by_vpid(nr); | ||
| 43 | } | ||
| 44 | |||
| 45 | __diag_pop(); | ||
| 46 | |||
| 47 | A wrapper kfunc is often needed when we need to annotate parameters of the | ||
| 48 | kfunc. Otherwise one may directly make the kfunc visible to the BPF program by | ||
| 49 | registering it with the BPF subsystem. See :ref:`BPF_kfunc_nodef`. | ||
| 50 | |||
| 51 | 2.2 Annotating kfunc parameters | ||
| 52 | ------------------------------- | ||
| 53 | |||
| 54 | Similar to BPF helpers, there is sometime need for additional context required | ||
| 55 | by the verifier to make the usage of kernel functions safer and more useful. | ||
| 56 | Hence, we can annotate a parameter by suffixing the name of the argument of the | ||
| 57 | kfunc with a __tag, where tag may be one of the supported annotations. | ||
| 58 | |||
| 59 | 2.2.1 __sz Annotation | ||
| 60 | --------------------- | ||
| 61 | |||
| 62 | This annotation is used to indicate a memory and size pair in the argument list. | ||
| 63 | An example is given below:: | ||
| 64 | |||
| 65 | void bpf_memzero(void *mem, int mem__sz) | ||
| 66 | { | ||
| 67 | ... | ||
| 68 | } | ||
| 69 | |||
| 70 | Here, the verifier will treat first argument as a PTR_TO_MEM, and second | ||
| 71 | argument as its size. By default, without __sz annotation, the size of the type | ||
| 72 | of the pointer is used. Without __sz annotation, a kfunc cannot accept a void | ||
| 73 | pointer. | ||
| 74 | |||
| 75 | .. _BPF_kfunc_nodef: | ||
| 76 | |||
| 77 | 2.3 Using an existing kernel function | ||
| 78 | ------------------------------------- | ||
| 79 | |||
| 80 | When an existing function in the kernel is fit for consumption by BPF programs, | ||
| 81 | it can be directly registered with the BPF subsystem. However, care must still | ||
| 82 | be taken to review the context in which it will be invoked by the BPF program | ||
| 83 | and whether it is safe to do so. | ||
| 84 | |||
| 85 | 2.4 Annotating kfuncs | ||
| 86 | --------------------- | ||
| 87 | |||
| 88 | In addition to kfuncs' arguments, verifier may need more information about the | ||
| 89 | type of kfunc(s) being registered with the BPF subsystem. To do so, we define | ||
| 90 | flags on a set of kfuncs as follows:: | ||
| 91 | |||
| 92 | BTF_SET8_START(bpf_task_set) | ||
| 93 | BTF_ID_FLAGS(func, bpf_get_task_pid, KF_ACQUIRE | KF_RET_NULL) | ||
| 94 | BTF_ID_FLAGS(func, bpf_put_pid, KF_RELEASE) | ||
| 95 | BTF_SET8_END(bpf_task_set) | ||
| 96 | |||
| 97 | This set encodes the BTF ID of each kfunc listed above, and encodes the flags | ||
| 98 | along with it. Ofcourse, it is also allowed to specify no flags. | ||
| 99 | |||
| 100 | 2.4.1 KF_ACQUIRE flag | ||
| 101 | --------------------- | ||
| 102 | |||
| 103 | The KF_ACQUIRE flag is used to indicate that the kfunc returns a pointer to a | ||
| 104 | refcounted object. The verifier will then ensure that the pointer to the object | ||
| 105 | is eventually released using a release kfunc, or transferred to a map using a | ||
| 106 | referenced kptr (by invoking bpf_kptr_xchg). If not, the verifier fails the | ||
| 107 | loading of the BPF program until no lingering references remain in all possible | ||
| 108 | explored states of the program. | ||
| 109 | |||
| 110 | 2.4.2 KF_RET_NULL flag | ||
| 111 | ---------------------- | ||
| 112 | |||
| 113 | The KF_RET_NULL flag is used to indicate that the pointer returned by the kfunc | ||
| 114 | may be NULL. Hence, it forces the user to do a NULL check on the pointer | ||
| 115 | returned from the kfunc before making use of it (dereferencing or passing to | ||
| 116 | another helper). This flag is often used in pairing with KF_ACQUIRE flag, but | ||
| 117 | both are orthogonal to each other. | ||
| 118 | |||
| 119 | 2.4.3 KF_RELEASE flag | ||
| 120 | --------------------- | ||
| 121 | |||
| 122 | The KF_RELEASE flag is used to indicate that the kfunc releases the pointer | ||
| 123 | passed in to it. There can be only one referenced pointer that can be passed in. | ||
| 124 | All copies of the pointer being released are invalidated as a result of invoking | ||
| 125 | kfunc with this flag. | ||
| 126 | |||
| 127 | 2.4.4 KF_KPTR_GET flag | ||
| 128 | ---------------------- | ||
| 129 | |||
| 130 | The KF_KPTR_GET flag is used to indicate that the kfunc takes the first argument | ||
| 131 | as a pointer to kptr, safely increments the refcount of the object it points to, | ||
| 132 | and returns a reference to the user. The rest of the arguments may be normal | ||
| 133 | arguments of a kfunc. The KF_KPTR_GET flag should be used in conjunction with | ||
| 134 | KF_ACQUIRE and KF_RET_NULL flags. | ||
| 135 | |||
| 136 | 2.4.5 KF_TRUSTED_ARGS flag | ||
| 137 | -------------------------- | ||
| 138 | |||
| 139 | The KF_TRUSTED_ARGS flag is used for kfuncs taking pointer arguments. It | ||
| 140 | indicates that the all pointer arguments will always be refcounted, and have | ||
| 141 | their offset set to 0. It can be used to enforce that a pointer to a refcounted | ||
| 142 | object acquired from a kfunc or BPF helper is passed as an argument to this | ||
| 143 | kfunc without any modifications (e.g. pointer arithmetic) such that it is | ||
| 144 | trusted and points to the original object. This flag is often used for kfuncs | ||
| 145 | that operate (change some property, perform some operation) on an object that | ||
| 146 | was obtained using an acquire kfunc. Such kfuncs need an unchanged pointer to | ||
| 147 | ensure the integrity of the operation being performed on the expected object. | ||
| 148 | |||
| 149 | 2.5 Registering the kfuncs | ||
| 150 | -------------------------- | ||
| 151 | |||
| 152 | Once the kfunc is prepared for use, the final step to making it visible is | ||
| 153 | registering it with the BPF subsystem. Registration is done per BPF program | ||
| 154 | type. An example is shown below:: | ||
| 155 | |||
| 156 | BTF_SET8_START(bpf_task_set) | ||
| 157 | BTF_ID_FLAGS(func, bpf_get_task_pid, KF_ACQUIRE | KF_RET_NULL) | ||
| 158 | BTF_ID_FLAGS(func, bpf_put_pid, KF_RELEASE) | ||
| 159 | BTF_SET8_END(bpf_task_set) | ||
| 160 | |||
| 161 | static const struct btf_kfunc_id_set bpf_task_kfunc_set = { | ||
| 162 | .owner = THIS_MODULE, | ||
| 163 | .set = &bpf_task_set, | ||
| 164 | }; | ||
| 165 | |||
| 166 | static int init_subsystem(void) | ||
| 167 | { | ||
| 168 | return register_btf_kfunc_id_set(BPF_PROG_TYPE_TRACING, &bpf_task_kfunc_set); | ||
| 169 | } | ||
| 170 | late_initcall(init_subsystem); | ||
| @@ -9,8 +9,8 @@ described here. It's recommended to follow these conventions whenever a · 8 unmodified lines | |||
| 9 | new function or type is added to keep libbpf API clean and consistent. | 9 | new function or type is added to keep libbpf API clean and consistent. |
| 10 | 10 | ||
| 11 | All types and functions provided by libbpf API should have one of the | 11 | All types and functions provided by libbpf API should have one of the |
| 12 | following prefixes: ``bpf_``, ``btf_``, ``libbpf_``, ``xsk_``, | 12 | following prefixes: ``bpf_``, ``btf_``, ``libbpf_``, ``btf_dump_``, |
| 13 | ``btf_dump_``, ``ring_buffer_``, ``perf_buffer_``. | 13 | ``ring_buffer_``, ``perf_buffer_``. |
| 14 | 14 | ||
| 15 | System call wrappers | 15 | System call wrappers |
| 16 | -------------------- | 16 | -------------------- |
| @@ -59,15 +59,6 @@ Auxiliary functions and types that don't fit well in any of categories · 42 unmodified lines | |||
| 59 | described above should have ``libbpf_`` prefix, e.g. | 59 | described above should have ``libbpf_`` prefix, e.g. |
| 60 | ``libbpf_get_error`` or ``libbpf_prog_type_by_name``. | 60 | ``libbpf_get_error`` or ``libbpf_prog_type_by_name``. |
| 61 | 61 | ||
| 62 | AF_XDP functions | ||
| 63 | ------------------- | ||
| 64 | |||
| 65 | AF_XDP functions should have an ``xsk_`` prefix, e.g. | ||
| 66 | ``xsk_umem__get_data`` or ``xsk_umem__create``. The interface consists | ||
| 67 | of both low-level ring access functions and high-level configuration | ||
| 68 | functions. These can be mixed and matched. Note that these functions | ||
| 69 | are not reentrant for performance reasons. | ||
| 70 | |||
| 71 | ABI | 62 | ABI |
| 72 | --- | 63 | --- |
| 73 | 64 | ||
| @@ -0,0 +1,185 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | .. Copyright (C) 2022 Red Hat, Inc. | ||
| 3 | |||
| 4 | =============================================== | ||
| 5 | BPF_MAP_TYPE_HASH, with PERCPU and LRU Variants | ||
| 6 | =============================================== | ||
| 7 | |||
| 8 | .. note:: | ||
| 9 | - ``BPF_MAP_TYPE_HASH`` was introduced in kernel version 3.19 | ||
| 10 | - ``BPF_MAP_TYPE_PERCPU_HASH`` was introduced in version 4.6 | ||
| 11 | - Both ``BPF_MAP_TYPE_LRU_HASH`` and ``BPF_MAP_TYPE_LRU_PERCPU_HASH`` | ||
| 12 | were introduced in version 4.10 | ||
| 13 | |||
| 14 | ``BPF_MAP_TYPE_HASH`` and ``BPF_MAP_TYPE_PERCPU_HASH`` provide general | ||
| 15 | purpose hash map storage. Both the key and the value can be structs, | ||
| 16 | allowing for composite keys and values. | ||
| 17 | |||
| 18 | The kernel is responsible for allocating and freeing key/value pairs, up | ||
| 19 | to the max_entries limit that you specify. Hash maps use pre-allocation | ||
| 20 | of hash table elements by default. The ``BPF_F_NO_PREALLOC`` flag can be | ||
| 21 | used to disable pre-allocation when it is too memory expensive. | ||
| 22 | |||
| 23 | ``BPF_MAP_TYPE_PERCPU_HASH`` provides a separate value slot per | ||
| 24 | CPU. The per-cpu values are stored internally in an array. | ||
| 25 | |||
| 26 | The ``BPF_MAP_TYPE_LRU_HASH`` and ``BPF_MAP_TYPE_LRU_PERCPU_HASH`` | ||
| 27 | variants add LRU semantics to their respective hash tables. An LRU hash | ||
| 28 | will automatically evict the least recently used entries when the hash | ||
| 29 | table reaches capacity. An LRU hash maintains an internal LRU list that | ||
| 30 | is used to select elements for eviction. This internal LRU list is | ||
| 31 | shared across CPUs but it is possible to request a per CPU LRU list with | ||
| 32 | the ``BPF_F_NO_COMMON_LRU`` flag when calling ``bpf_map_create``. | ||
| 33 | |||
| 34 | Usage | ||
| 35 | ===== | ||
| 36 | |||
| 37 | .. c:function:: | ||
| 38 | long bpf_map_update_elem(struct bpf_map *map, const void *key, const void *value, u64 flags) | ||
| 39 | |||
| 40 | Hash entries can be added or updated using the ``bpf_map_update_elem()`` | ||
| 41 | helper. This helper replaces existing elements atomically. The ``flags`` | ||
| 42 | parameter can be used to control the update behaviour: | ||
| 43 | |||
| 44 | - ``BPF_ANY`` will create a new element or update an existing element | ||
| 45 | - ``BPF_NOEXIST`` will create a new element only if one did not already | ||
| 46 | exist | ||
| 47 | - ``BPF_EXIST`` will update an existing element | ||
| 48 | |||
| 49 | ``bpf_map_update_elem()`` returns 0 on success, or negative error in | ||
| 50 | case of failure. | ||
| 51 | |||
| 52 | .. c:function:: | ||
| 53 | void *bpf_map_lookup_elem(struct bpf_map *map, const void *key) | ||
| 54 | |||
| 55 | Hash entries can be retrieved using the ``bpf_map_lookup_elem()`` | ||
| 56 | helper. This helper returns a pointer to the value associated with | ||
| 57 | ``key``, or ``NULL`` if no entry was found. | ||
| 58 | |||
| 59 | .. c:function:: | ||
| 60 | long bpf_map_delete_elem(struct bpf_map *map, const void *key) | ||
| 61 | |||
| 62 | Hash entries can be deleted using the ``bpf_map_delete_elem()`` | ||
| 63 | helper. This helper will return 0 on success, or negative error in case | ||
| 64 | of failure. | ||
| 65 | |||
| 66 | Per CPU Hashes | ||
| 67 | -------------- | ||
| 68 | |||
| 69 | For ``BPF_MAP_TYPE_PERCPU_HASH`` and ``BPF_MAP_TYPE_LRU_PERCPU_HASH`` | ||
| 70 | the ``bpf_map_update_elem()`` and ``bpf_map_lookup_elem()`` helpers | ||
| 71 | automatically access the hash slot for the current CPU. | ||
| 72 | |||
| 73 | .. c:function:: | ||
| 74 | void *bpf_map_lookup_percpu_elem(struct bpf_map *map, const void *key, u32 cpu) | ||
| 75 | |||
| 76 | The ``bpf_map_lookup_percpu_elem()`` helper can be used to lookup the | ||
| 77 | value in the hash slot for a specific CPU. Returns value associated with | ||
| 78 | ``key`` on ``cpu`` , or ``NULL`` if no entry was found or ``cpu`` is | ||
| 79 | invalid. | ||
| 80 | |||
| 81 | Concurrency | ||
| 82 | ----------- | ||
| 83 | |||
| 84 | Values stored in ``BPF_MAP_TYPE_HASH`` can be accessed concurrently by | ||
| 85 | programs running on different CPUs. Since Kernel version 5.1, the BPF | ||
| 86 | infrastructure provides ``struct bpf_spin_lock`` to synchronise access. | ||
| 87 | See ``tools/testing/selftests/bpf/progs/test_spin_lock.c``. | ||
| 88 | |||
| 89 | Userspace | ||
| 90 | --------- | ||
| 91 | |||
| 92 | .. c:function:: | ||
| 93 | int bpf_map_get_next_key(int fd, const void *cur_key, void *next_key) | ||
| 94 | |||
| 95 | In userspace, it is possible to iterate through the keys of a hash using | ||
| 96 | libbpf's ``bpf_map_get_next_key()`` function. The first key can be fetched by | ||
| 97 | calling ``bpf_map_get_next_key()`` with ``cur_key`` set to | ||
| 98 | ``NULL``. Subsequent calls will fetch the next key that follows the | ||
| 99 | current key. ``bpf_map_get_next_key()`` returns 0 on success, -ENOENT if | ||
| 100 | cur_key is the last key in the hash, or negative error in case of | ||
| 101 | failure. | ||
| 102 | |||
| 103 | Note that if ``cur_key`` gets deleted then ``bpf_map_get_next_key()`` | ||
| 104 | will instead return the *first* key in the hash table which is | ||
| 105 | undesirable. It is recommended to use batched lookup if there is going | ||
| 106 | to be key deletion intermixed with ``bpf_map_get_next_key()``. | ||
| 107 | |||
| 108 | Examples | ||
| 109 | ======== | ||
| 110 | |||
| 111 | Please see the ``tools/testing/selftests/bpf`` directory for functional | ||
| 112 | examples. The code snippets below demonstrates API usage. | ||
| 113 | |||
| 114 | This example shows how to declare an LRU Hash with a struct key and a | ||
| 115 | struct value. | ||
| 116 | |||
| 117 | .. code-block:: c | ||
| 118 | |||
| 119 | #include <linux/bpf.h> | ||
| 120 | #include <bpf/bpf_helpers.h> | ||
| 121 | |||
| 122 | struct key { | ||
| 123 | __u32 srcip; | ||
| 124 | }; | ||
| 125 | |||
| 126 | struct value { | ||
| 127 | __u64 packets; | ||
| 128 | __u64 bytes; | ||
| 129 | }; | ||
| 130 | |||
| 131 | struct { | ||
| 132 | __uint(type, BPF_MAP_TYPE_LRU_HASH); | ||
| 133 | __uint(max_entries, 32); | ||
| 134 | __type(key, struct key); | ||
| 135 | __type(value, struct value); | ||
| 136 | } packet_stats SEC(".maps"); | ||
| 137 | |||
| 138 | This example shows how to create or update hash values using atomic | ||
| 139 | instructions: | ||
| 140 | |||
| 141 | .. code-block:: c | ||
| 142 | |||
| 143 | static void update_stats(__u32 srcip, int bytes) | ||
| 144 | { | ||
| 145 | struct key key = { | ||
| 146 | .srcip = srcip, | ||
| 147 | }; | ||
| 148 | struct value *value = bpf_map_lookup_elem(&packet_stats, &key); | ||
| 149 | |||
| 150 | if (value) { | ||
| 151 | __sync_fetch_and_add(&value->packets, 1); | ||
| 152 | __sync_fetch_and_add(&value->bytes, bytes); | ||
| 153 | } else { | ||
| 154 | struct value newval = { 1, bytes }; | ||
| 155 | |||
| 156 | bpf_map_update_elem(&packet_stats, &key, &newval, BPF_NOEXIST); | ||
| 157 | } | ||
| 158 | } | ||
| 159 | |||
| 160 | Userspace walking the map elements from the map declared above: | ||
| 161 | |||
| 162 | .. code-block:: c | ||
| 163 | |||
| 164 | #include <bpf/libbpf.h> | ||
| 165 | #include <bpf/bpf.h> | ||
| 166 | |||
| 167 | static void walk_hash_elements(int map_fd) | ||
| 168 | { | ||
| 169 | struct key *cur_key = NULL; | ||
| 170 | struct key next_key; | ||
| 171 | struct value value; | ||
| 172 | int err; | ||
| 173 | |||
| 174 | for (;;) { | ||
| 175 | err = bpf_map_get_next_key(map_fd, cur_key, &next_key); | ||
| 176 | if (err) | ||
| 177 | break; | ||
| 178 | |||
| 179 | bpf_map_lookup_elem(map_fd, &next_key, &value); | ||
| 180 | |||
| 181 | // Use key and value here | ||
| 182 | |||
| 183 | cur_key = &next_key; | ||
| 184 | } | ||
| 185 | } | ||
| @@ -86,6 +86,7 @@ if major >= 3: · 85 unmodified lines | |||
| 86 | "__used", | 86 | "__used", |
| 87 | "__weak", | 87 | "__weak", |
| 88 | "noinline", | 88 | "noinline", |
| 89 | "__fix_address", | ||
| 89 | 90 | ||
| 90 | # include/linux/memblock.h: | 91 | # include/linux/memblock.h: |
| 91 | "__init_memblock", | 92 | "__init_memblock", |
| @@ -1,220 +0,0 @@ | |||
| 1 | ========================================================== | ||
| 2 | How to access I/O mapped memory from within device drivers | ||
| 3 | ========================================================== | ||
| 4 | |||
| 5 | :Author: Linus | ||
| 6 | |||
| 7 | .. warning:: | ||
| 8 | |||
| 9 | The virt_to_bus() and bus_to_virt() functions have been | ||
| 10 | superseded by the functionality provided by the PCI DMA interface | ||
| 11 | (see Documentation/core-api/dma-api-howto.rst). They continue | ||
| 12 | to be documented below for historical purposes, but new code | ||
| 13 | must not use them. --davidm 00/12/12 | ||
| 14 | |||
| 15 | :: | ||
| 16 | |||
| 17 | [ This is a mail message in response to a query on IO mapping, thus the | ||
| 18 | strange format for a "document" ] | ||
| 19 | |||
| 20 | The AHA-1542 is a bus-master device, and your patch makes the driver give the | ||
| 21 | controller the physical address of the buffers, which is correct on x86 | ||
| 22 | (because all bus master devices see the physical memory mappings directly). | ||
| 23 | |||
| 24 | However, on many setups, there are actually **three** different ways of looking | ||
| 25 | at memory addresses, and in this case we actually want the third, the | ||
| 26 | so-called "bus address". | ||
| 27 | |||
| 28 | Essentially, the three ways of addressing memory are (this is "real memory", | ||
| 29 | that is, normal RAM--see later about other details): | ||
| 30 | |||
| 31 | - CPU untranslated. This is the "physical" address. Physical address | ||
| 32 | 0 is what the CPU sees when it drives zeroes on the memory bus. | ||
| 33 | |||
| 34 | - CPU translated address. This is the "virtual" address, and is | ||
| 35 | completely internal to the CPU itself with the CPU doing the appropriate | ||
| 36 | translations into "CPU untranslated". | ||
| 37 | |||
| 38 | - bus address. This is the address of memory as seen by OTHER devices, | ||
| 39 | not the CPU. Now, in theory there could be many different bus | ||
| 40 | addresses, with each device seeing memory in some device-specific way, but | ||
| 41 | happily most hardware designers aren't actually actively trying to make | ||
| 42 | things any more complex than necessary, so you can assume that all | ||
| 43 | external hardware sees the memory the same way. | ||
| 44 | |||
| 45 | Now, on normal PCs the bus address is exactly the same as the physical | ||
| 46 | address, and things are very simple indeed. However, they are that simple | ||
| 47 | because the memory and the devices share the same address space, and that is | ||
| 48 | not generally necessarily true on other PCI/ISA setups. | ||
| 49 | |||
| 50 | Now, just as an example, on the PReP (PowerPC Reference Platform), the | ||
| 51 | CPU sees a memory map something like this (this is from memory):: | ||
| 52 | |||
| 53 | 0-2 GB "real memory" | ||
| 54 | 2 GB-3 GB "system IO" (inb/out and similar accesses on x86) | ||
| 55 | 3 GB-4 GB "IO memory" (shared memory over the IO bus) | ||
| 56 | |||
| 57 | Now, that looks simple enough. However, when you look at the same thing from | ||
| 58 | the viewpoint of the devices, you have the reverse, and the physical memory | ||
| 59 | address 0 actually shows up as address 2 GB for any IO master. | ||
| 60 | |||
| 61 | So when the CPU wants any bus master to write to physical memory 0, it | ||
| 62 | has to give the master address 0x80000000 as the memory address. | ||
| 63 | |||
| 64 | So, for example, depending on how the kernel is actually mapped on the | ||
| 65 | PPC, you can end up with a setup like this:: | ||
| 66 | |||
| 67 | physical address: 0 | ||
| 68 | virtual address: 0xC0000000 | ||
| 69 | bus address: 0x80000000 | ||
| 70 | |||
| 71 | where all the addresses actually point to the same thing. It's just seen | ||
| 72 | through different translations.. | ||
| 73 | |||
| 74 | Similarly, on the Alpha, the normal translation is:: | ||
| 75 | |||
| 76 | physical address: 0 | ||
| 77 | virtual address: 0xfffffc0000000000 | ||
| 78 | bus address: 0x40000000 | ||
| 79 | |||
| 80 | (but there are also Alphas where the physical address and the bus address | ||
| 81 | are the same). | ||
| 82 | |||
| 83 | Anyway, the way to look up all these translations, you do:: | ||
| 84 | |||
| 85 | #include <asm/io.h> | ||
| 86 | |||
| 87 | phys_addr = virt_to_phys(virt_addr); | ||
| 88 | virt_addr = phys_to_virt(phys_addr); | ||
| 89 | bus_addr = virt_to_bus(virt_addr); | ||
| 90 | virt_addr = bus_to_virt(bus_addr); | ||
| 91 | |||
| 92 | Now, when do you need these? | ||
| 93 | |||
| 94 | You want the **virtual** address when you are actually going to access that | ||
| 95 | pointer from the kernel. So you can have something like this:: | ||
| 96 | |||
| 97 | /* | ||
| 98 | * this is the hardware "mailbox" we use to communicate with | ||
| 99 | * the controller. The controller sees this directly. | ||
| 100 | */ | ||
| 101 | struct mailbox { | ||
| 102 | __u32 status; | ||
| 103 | __u32 bufstart; | ||
| 104 | __u32 buflen; | ||
| 105 | .. | ||
| 106 | } mbox; | ||
| 107 | |||
| 108 | unsigned char * retbuffer; | ||
| 109 | |||
| 110 | /* get the address from the controller */ | ||
| 111 | retbuffer = bus_to_virt(mbox.bufstart); | ||
| 112 | switch (retbuffer[0]) { | ||
| 113 | case STATUS_OK: | ||
| 114 | ... | ||
| 115 | |||
| 116 | on the other hand, you want the bus address when you have a buffer that | ||
| 117 | you want to give to the controller:: | ||
| 118 | |||
| 119 | /* ask the controller to read the sense status into "sense_buffer" */ | ||
| 120 | mbox.bufstart = virt_to_bus(&sense_buffer); | ||
| 121 | mbox.buflen = sizeof(sense_buffer); | ||
| 122 | mbox.status = 0; | ||
| 123 | notify_controller(&mbox); | ||
| 124 | |||
| 125 | And you generally **never** want to use the physical address, because you can't | ||
| 126 | use that from the CPU (the CPU only uses translated virtual addresses), and | ||
| 127 | you can't use it from the bus master. | ||
| 128 | |||
| 129 | So why do we care about the physical address at all? We do need the physical | ||
| 130 | address in some cases, it's just not very often in normal code. The physical | ||
| 131 | address is needed if you use memory mappings, for example, because the | ||
| 132 | "remap_pfn_range()" mm function wants the physical address of the memory to | ||
| 133 | be remapped as measured in units of pages, a.k.a. the pfn (the memory | ||
| 134 | management layer doesn't know about devices outside the CPU, so it | ||
| 135 | shouldn't need to know about "bus addresses" etc). | ||
| 136 | |||
| 137 | .. note:: | ||
| 138 | |||
| 139 | The above is only one part of the whole equation. The above | ||
| 140 | only talks about "real memory", that is, CPU memory (RAM). | ||
| 141 | |||
| 142 | There is a completely different type of memory too, and that's the "shared | ||
| 143 | memory" on the PCI or ISA bus. That's generally not RAM (although in the case | ||
| 144 | of a video graphics card it can be normal DRAM that is just used for a frame | ||
| 145 | buffer), but can be things like a packet buffer in a network card etc. | ||
| 146 | |||
| 147 | This memory is called "PCI memory" or "shared memory" or "IO memory" or | ||
| 148 | whatever, and there is only one way to access it: the readb/writeb and | ||
| 149 | related functions. You should never take the address of such memory, because | ||
| 150 | there is really nothing you can do with such an address: it's not | ||
| 151 | conceptually in the same memory space as "real memory" at all, so you cannot | ||
| 152 | just dereference a pointer. (Sadly, on x86 it **is** in the same memory space, | ||
| 153 | so on x86 it actually works to just deference a pointer, but it's not | ||
| 154 | portable). | ||
| 155 | |||
| 156 | For such memory, you can do things like: | ||
| 157 | |||
| 158 | - reading:: | ||
| 159 | |||
| 160 | /* | ||
| 161 | * read first 32 bits from ISA memory at 0xC0000, aka | ||
| 162 | * C000:0000 in DOS terms | ||
| 163 | */ | ||
| 164 | unsigned int signature = isa_readl(0xC0000); | ||
| 165 | |||
| 166 | - remapping and writing:: | ||
| 167 | |||
| 168 | /* | ||
| 169 | * remap framebuffer PCI memory area at 0xFC000000, | ||
| 170 | * size 1MB, so that we can access it: We can directly | ||
| 171 | * access only the 640k-1MB area, so anything else | ||
| 172 | * has to be remapped. | ||
| 173 | */ | ||
| 174 | void __iomem *baseptr = ioremap(0xFC000000, 1024*1024); | ||
| 175 | |||
| 176 | /* write a 'A' to the offset 10 of the area */ | ||
| 177 | writeb('A',baseptr+10); | ||
| 178 | |||
| 179 | /* unmap when we unload the driver */ | ||
| 180 | iounmap(baseptr); | ||
| 181 | |||
| 182 | - copying and clearing:: | ||
| 183 | |||
| 184 | /* get the 6-byte Ethernet address at ISA address E000:0040 */ | ||
| 185 | memcpy_fromio(kernel_buffer, 0xE0040, 6); | ||
| 186 | /* write a packet to the driver */ | ||
| 187 | memcpy_toio(0xE1000, skb->data, skb->len); | ||
| 188 | /* clear the frame buffer */ | ||
| 189 | memset_io(0xA0000, 0, 0x10000); | ||
| 190 | |||
| 191 | OK, that just about covers the basics of accessing IO portably. Questions? | ||
| 192 | Comments? You may think that all the above is overly complex, but one day you | ||
| 193 | might find yourself with a 500 MHz Alpha in front of you, and then you'll be | ||
| 194 | happy that your driver works ;) | ||
| 195 | |||
| 196 | Note that kernel versions 2.0.x (and earlier) mistakenly called the | ||
| 197 | ioremap() function "vremap()". ioremap() is the proper name, but I | ||
| 198 | didn't think straight when I wrote it originally. People who have to | ||
| 199 | support both can do something like:: | ||
| 200 | |||
| 201 | /* support old naming silliness */ | ||
| 202 | #if LINUX_VERSION_CODE < 0x020100 | ||
| 203 | #define ioremap vremap | ||
| 204 | #define iounmap vfree | ||
| 205 | #endif | ||
| 206 | |||
| 207 | at the top of their source files, and then they can use the right names | ||
| 208 | even on 2.0.x systems. | ||
| 209 | |||
| 210 | And the above sounds worse than it really is. Most real drivers really | ||
| 211 | don't do all that complex things (or rather: the complexity is not so | ||
| 212 | much in the actual IO accesses as in error handling and timeouts etc). | ||
| 213 | It's generally not hard to fix drivers, and in many cases the code | ||
| 214 | actually looks better afterwards:: | ||
| 215 | |||
| 216 | unsigned long signature = *(unsigned int *) 0xC0000; | ||
| 217 | vs | ||
| 218 | unsigned long signature = readl(0xC0000); | ||
| 219 | |||
| 220 | I think the second version actually is more readable, no? | ||
| @@ -707,20 +707,6 @@ to use the dma_sync_*() interfaces:: · 706 unmodified lines | |||
| 707 | } | 707 | } |
| 708 | } | 708 | } |
| 709 | 709 | ||
| 710 | Drivers converted fully to this interface should not use virt_to_bus() any | ||
| 711 | longer, nor should they use bus_to_virt(). Some drivers have to be changed a | ||
| 712 | little bit, because there is no longer an equivalent to bus_to_virt() in the | ||
| 713 | dynamic DMA mapping scheme - you have to always store the DMA addresses | ||
| 714 | returned by the dma_alloc_coherent(), dma_pool_alloc(), and dma_map_single() | ||
| 715 | calls (dma_map_sg() stores them in the scatterlist itself if the platform | ||
| 716 | supports dynamic DMA mapping in hardware) in your driver structures and/or | ||
| 717 | in the card registers. | ||
| 718 | |||
| 719 | All drivers should be using these interfaces with no exceptions. It | ||
| 720 | is planned to completely remove virt_to_bus() and bus_to_virt() as | ||
| 721 | they are entirely deprecated. Some ports already do not provide these | ||
| 722 | as it is impossible to correctly support them. | ||
| 723 | |||
| 724 | Handling Errors | 710 | Handling Errors |
| 725 | =============== | 711 | =============== |
| 726 | 712 | ||
| @@ -204,6 +204,20 @@ Returns the maximum size of a mapping for the device. The size parameter · 203 unmodified lines | |||
| 204 | of the mapping functions like dma_map_single(), dma_map_page() and | 204 | of the mapping functions like dma_map_single(), dma_map_page() and |
| 205 | others should not be larger than the returned value. | 205 | others should not be larger than the returned value. |
| 206 | 206 | ||
| 207 | :: | ||
| 208 | |||
| 209 | size_t | ||
| 210 | dma_opt_mapping_size(struct device *dev); | ||
| 211 | |||
| 212 | Returns the maximum optimal size of a mapping for the device. | ||
| 213 | |||
| 214 | Mapping larger buffers may take much longer in certain scenarios. In | ||
| 215 | addition, for high-rate short-lived streaming mappings, the upfront time | ||
| 216 | spent on the mapping may account for an appreciable part of the total | ||
| 217 | request lifetime. As such, if splitting larger requests incurs no | ||
| 218 | significant performance penalty, then device drivers are advised to | ||
| 219 | limit total DMA streaming mappings length to the returned value. | ||
| 220 | |||
| 207 | :: | 221 | :: |
| 208 | 222 | ||
| 209 | bool | 223 | bool |
| @@ -17,6 +17,9 @@ solution to the problem to avoid everybody inventing their own. The IDR · 16 unmodified lines | |||
| 17 | provides the ability to map an ID to a pointer, while the IDA provides | 17 | provides the ability to map an ID to a pointer, while the IDA provides |
| 18 | only ID allocation, and as a result is much more memory-efficient. | 18 | only ID allocation, and as a result is much more memory-efficient. |
| 19 | 19 | ||
| 20 | The IDR interface is deprecated; please use the :doc:`XArray <xarray>` | ||
| 21 | instead. | ||
| 22 | |||
| 20 | IDR usage | 23 | IDR usage |
| 21 | ========= | 24 | ========= |
| 22 | 25 | ||
| @@ -41,7 +41,6 @@ Library functionality that is used throughout the kernel. · 40 unmodified lines | |||
| 41 | rbtree | 41 | rbtree |
| 42 | generic-radix-tree | 42 | generic-radix-tree |
| 43 | packing | 43 | packing |
| 44 | bus-virt-phys-mapping | ||
| 45 | this_cpu_ops | 44 | this_cpu_ops |
| 46 | timekeeping | 45 | timekeeping |
| 47 | errseq | 46 | errseq |
| @@ -87,7 +86,7 @@ Memory management · 39 unmodified lines | |||
| 87 | ================= | 86 | ================= |
| 88 | 87 | ||
| 89 | How to allocate and use memory in the kernel. Note that there is a lot | 88 | How to allocate and use memory in the kernel. Note that there is a lot |
| 90 | more memory-management documentation in Documentation/vm/index.rst. | 89 | more memory-management documentation in Documentation/mm/index.rst. |
| 91 | 90 | ||
| 92 | .. toctree:: | 91 | .. toctree:: |
| 93 | :maxdepth: 1 | 92 | :maxdepth: 1 |
| @@ -223,7 +223,7 @@ Module Loading · 222 unmodified lines | |||
| 223 | Inter Module support | 223 | Inter Module support |
| 224 | -------------------- | 224 | -------------------- |
| 225 | 225 | ||
| 226 | Refer to the file kernel/module.c for more information. | 226 | Refer to the files in kernel/module/ for more information. |
| 227 | 227 | ||
| 228 | Hardware Interfaces | 228 | Hardware Interfaces |
| 229 | =================== | 229 | =================== |
| @@ -22,16 +22,16 @@ Memory Allocation Controls · 21 unmodified lines | |||
| 22 | .. kernel-doc:: include/linux/gfp.h | 22 | .. kernel-doc:: include/linux/gfp.h |
| 23 | :internal: | 23 | :internal: |
| 24 | 24 | ||
| 25 | .. kernel-doc:: include/linux/gfp.h | 25 | .. kernel-doc:: include/linux/gfp_types.h |
| 26 | :doc: Page mobility and placement hints | 26 | :doc: Page mobility and placement hints |
| 27 | 27 | ||
| 28 | .. kernel-doc:: include/linux/gfp.h | 28 | .. kernel-doc:: include/linux/gfp_types.h |
| 29 | :doc: Watermark modifiers | 29 | :doc: Watermark modifiers |
| 30 | 30 | ||
| 31 | .. kernel-doc:: include/linux/gfp.h | 31 | .. kernel-doc:: include/linux/gfp_types.h |
| 32 | :doc: Reclaim modifiers | 32 | :doc: Reclaim modifiers |
| 33 | 33 | ||
| 34 | .. kernel-doc:: include/linux/gfp.h | 34 | .. kernel-doc:: include/linux/gfp_types.h |
| 35 | :doc: Useful GFP flag combinations | 35 | :doc: Useful GFP flag combinations |
| 36 | 36 | ||
| 37 | The Slab Cache | 37 | The Slab Cache |
| @@ -4,31 +4,29 @@ · 3 unmodified lines | |||
| 4 | Memory Protection Keys | 4 | Memory Protection Keys |
| 5 | ====================== | 5 | ====================== |
| 6 | 6 | ||
| 7 | Memory Protection Keys for Userspace (PKU aka PKEYs) is a feature | 7 | Memory Protection Keys provide a mechanism for enforcing page-based |
| 8 | which is found on Intel's Skylake (and later) "Scalable Processor" | 8 | protections, but without requiring modification of the page tables when an |
| 9 | Server CPUs. It will be available in future non-server Intel parts | 9 | application changes protection domains. |
| 10 | and future AMD processors. | 10 | |
| 11 | 11 | Pkeys Userspace (PKU) is a feature which can be found on: | |
| 12 | For anyone wishing to test or use this feature, it is available in | 12 | * Intel server CPUs, Skylake and later |
| 13 | Amazon's EC2 C5 instances and is known to work there using an Ubuntu | 13 | * Intel client CPUs, Tiger Lake (11th Gen Core) and later |
| 14 | 17.04 image. | 14 | * Future AMD CPUs |
| 15 | 15 | ||
| 16 | Memory Protection Keys provides a mechanism for enforcing page-based | 16 | Pkeys work by dedicating 4 previously Reserved bits in each page table entry to |
| 17 | protections, but without requiring modification of the page tables | 17 | a "protection key", giving 16 possible keys. |
| 18 | when an application changes protection domains. It works by | 18 | |
| 19 | dedicating 4 previously ignored bits in each page table entry to a | 19 | Protections for each key are defined with a per-CPU user-accessible register |
| 20 | "protection key", giving 16 possible keys. | 20 | (PKRU). Each of these is a 32-bit register storing two bits (Access Disable |
| 21 | 21 | and Write Disable) for each of 16 keys. | |
| 22 | There is also a new user-accessible register (PKRU) with two separate | 22 | |
| 23 | bits (Access Disable and Write Disable) for each key. Being a CPU | 23 | Being a CPU register, PKRU is inherently thread-local, potentially giving each |
| 24 | register, PKRU is inherently thread-local, potentially giving each | ||
| 25 | thread a different set of protections from every other thread. | 24 | thread a different set of protections from every other thread. |
| 26 | 25 | ||
| 27 | There are two new instructions (RDPKRU/WRPKRU) for reading and writing | 26 | There are two instructions (RDPKRU/WRPKRU) for reading and writing to the |
| 28 | to the new register. The feature is only available in 64-bit mode, | 27 | register. The feature is only available in 64-bit mode, even though there is |
| 29 | even though there is theoretically space in the PAE PTEs. These | 28 | theoretically space in the PAE PTEs. These permissions are enforced on data |
| 30 | permissions are enforced on data access only and have no effect on | 29 | access only and have no effect on instruction fetches. |
| 31 | instruction fetches. | ||
| 32 | 30 | ||
| 33 | Syscalls | 31 | Syscalls |
| 34 | ======== | 32 | ======== |
| @@ -51,8 +51,8 @@ namespace ``USB_STORAGE``, use:: · 50 unmodified lines | |||
| 51 | The corresponding ksymtab entry struct ``kernel_symbol`` will have the member | 51 | The corresponding ksymtab entry struct ``kernel_symbol`` will have the member |
| 52 | ``namespace`` set accordingly. A symbol that is exported without a namespace will | 52 | ``namespace`` set accordingly. A symbol that is exported without a namespace will |
| 53 | refer to ``NULL``. There is no default namespace if none is defined. ``modpost`` | 53 | refer to ``NULL``. There is no default namespace if none is defined. ``modpost`` |
| 54 | and kernel/module.c make use the namespace at build time or module load time, | 54 | and kernel/module/main.c make use the namespace at build time or module load |
| 55 | respectively. | 55 | time, respectively. |
| 56 | 56 | ||
| 57 | 2.2 Using the DEFAULT_SYMBOL_NAMESPACE define | 57 | 2.2 Using the DEFAULT_SYMBOL_NAMESPACE define |
| 58 | ============================================= | 58 | ============================================= |
| @@ -66,7 +66,7 @@ The wiki documentation always refers to the linux-next version of the script. · 65 unmodified lines | |||
| 66 | 66 | ||
| 67 | For Semantic Patch Language(SmPL) grammar documentation refer to: | 67 | For Semantic Patch Language(SmPL) grammar documentation refer to: |
| 68 | 68 | ||
| 69 | http://coccinelle.lip6.fr/documentation.php | 69 | https://coccinelle.gitlabpages.inria.fr/website/docs/main_grammar.html |
| 70 | 70 | ||
| 71 | Using Coccinelle on the Linux kernel | 71 | Using Coccinelle on the Linux kernel |
| 72 | ------------------------------------ | 72 | ------------------------------------ |
| @@ -174,7 +174,6 @@ mapping: · 173 unmodified lines | |||
| 174 | 174 | ||
| 175 | - ``kmemleak_alloc_phys`` | 175 | - ``kmemleak_alloc_phys`` |
| 176 | - ``kmemleak_free_part_phys`` | 176 | - ``kmemleak_free_part_phys`` |
| 177 | - ``kmemleak_not_leak_phys`` | ||
| 178 | - ``kmemleak_ignore_phys`` | 177 | - ``kmemleak_ignore_phys`` |
| 179 | 178 | ||
| 180 | Dealing with false positives/negatives | 179 | Dealing with false positives/negatives |
| @@ -208,6 +208,14 @@ In general, the rules for selftests are · 207 unmodified lines | |||
| 208 | Contributing new tests (details) | 208 | Contributing new tests (details) |
| 209 | ================================ | 209 | ================================ |
| 210 | 210 | ||
| 211 | * In your Makefile, use facilities from lib.mk by including it instead of | ||
| 212 | reinventing the wheel. Specify flags and binaries generation flags on | ||
| 213 | need basis before including lib.mk. :: | ||
| 214 | |||
| 215 | CFLAGS = $(KHDR_INCLUDES) | ||
| 216 | TEST_GEN_PROGS := close_range_test | ||
| 217 | include ../lib.mk | ||
| 218 | |||
| 211 | * Use TEST_GEN_XXX if such binaries or files are generated during | 219 | * Use TEST_GEN_XXX if such binaries or files are generated during |
| 212 | compiling. | 220 | compiling. |
| 213 | 221 | ||
| @@ -230,13 +238,30 @@ Contributing new tests (details) · 16 unmodified lines | |||
| 230 | * First use the headers inside the kernel source and/or git repo, and then the | 238 | * First use the headers inside the kernel source and/or git repo, and then the |
| 231 | system headers. Headers for the kernel release as opposed to headers | 239 | system headers. Headers for the kernel release as opposed to headers |
| 232 | installed by the distro on the system should be the primary focus to be able | 240 | installed by the distro on the system should be the primary focus to be able |
| 233 | to find regressions. | 241 | to find regressions. Use KHDR_INCLUDES in Makefile to include headers from |
| 242 | the kernel source. | ||
| 234 | 243 | ||
| 235 | * If a test needs specific kernel config options enabled, add a config file in | 244 | * If a test needs specific kernel config options enabled, add a config file in |
| 236 | the test directory to enable them. | 245 | the test directory to enable them. |
| 237 | 246 | ||
| 238 | e.g: tools/testing/selftests/android/config | 247 | e.g: tools/testing/selftests/android/config |
| 239 | 248 | ||
| 249 | * Create a .gitignore file inside test directory and add all generated objects | ||
| 250 | in it. | ||
| 251 | |||
| 252 | * Add new test name in TARGETS in selftests/Makefile:: | ||
| 253 | |||
| 254 | TARGETS += android | ||
| 255 | |||
| 256 | * All changes should pass:: | ||
| 257 | |||
| 258 | kselftest-{all,install,clean,gen_tar} | ||
| 259 | kselftest-{all,install,clean,gen_tar} O=abo_path | ||
| 260 | kselftest-{all,install,clean,gen_tar} O=rel_path | ||
| 261 | make -C tools/testing/selftests {all,install,clean,gen_tar} | ||
| 262 | make -C tools/testing/selftests {all,install,clean,gen_tar} O=abs_path | ||
| 263 | make -C tools/testing/selftests {all,install,clean,gen_tar} O=rel_path | ||
| 264 | |||
| 240 | Test Module | 265 | Test Module |
| 241 | =========== | 266 | =========== |
| 242 | 267 | ||
| @@ -250,6 +275,14 @@ assist writing kernel modules that are for use with kselftest: · 7 unmodified lines | |||
| 250 | - ``tools/testing/selftests/kselftest_module.h`` | 275 | - ``tools/testing/selftests/kselftest_module.h`` |
| 251 | - ``tools/testing/selftests/kselftest/module.sh`` | 276 | - ``tools/testing/selftests/kselftest/module.sh`` |
| 252 | 277 | ||
| 278 | Note that test modules should taint the kernel with TAINT_TEST. This will | ||
| 279 | happen automatically for modules which are in the ``tools/testing/`` | ||
| 280 | directory, or for modules which use the ``kselftest_module.h`` header above. | ||
| 281 | Otherwise, you'll need to add ``MODULE_INFO(test, "Y")`` to your module | ||
| 282 | source. selftests which do not load modules typically should not taint the | ||
| 283 | kernel, but in cases where a non-test module is loaded, TEST_TAINT can be | ||
| 284 | applied from userspace by writing to ``/proc/sys/kernel/tainted``. | ||
| 285 | |||
| 253 | How to use | 286 | How to use |
| 254 | ---------- | 287 | ---------- |
| 255 | 288 | ||
| @@ -308,6 +341,7 @@ A bare bones test module might look like this: · 52 unmodified lines | |||
| 308 | KSTM_MODULE_LOADERS(test_foo); | 341 | KSTM_MODULE_LOADERS(test_foo); |
| 309 | MODULE_AUTHOR("John Developer <jd@fooman.org>"); | 342 | MODULE_AUTHOR("John Developer <jd@fooman.org>"); |
| 310 | MODULE_LICENSE("GPL"); | 343 | MODULE_LICENSE("GPL"); |
| 344 | MODULE_INFO(test, "Y"); | ||
| 311 | 345 | ||
| 312 | Example test script | 346 | Example test script |
| 313 | ------------------- | 347 | ------------------- |
| @@ -192,6 +192,21 @@ via UML. To run tests on qemu, by default it requires two flags: · 191 unmodified lines | |||
| 192 | if we have downloaded the microblaze toolchain from the 0-day | 192 | if we have downloaded the microblaze toolchain from the 0-day |
| 193 | website to a directory in our home directory called toolchains. | 193 | website to a directory in our home directory called toolchains. |
| 194 | 194 | ||
| 195 | This means that for most architectures, running under qemu is as simple as: | ||
| 196 | |||
| 197 | .. code-block:: bash | ||
| 198 | |||
| 199 | ./tools/testing/kunit/kunit.py run --arch=x86_64 | ||
| 200 | |||
| 201 | When cross-compiling, we'll likely need to specify a different toolchain, for | ||
| 202 | example: | ||
| 203 | |||
| 204 | .. code-block:: bash | ||
| 205 | |||
| 206 | ./tools/testing/kunit/kunit.py run \ | ||
| 207 | --arch=s390 \ | ||
| 208 | --cross_compile=s390x-linux-gnu- | ||
| 209 | |||
| 195 | If we want to run KUnit tests on an architecture not supported by | 210 | If we want to run KUnit tests on an architecture not supported by |
| 196 | the ``--arch`` flag, or want to run KUnit tests on qemu using a | 211 | the ``--arch`` flag, or want to run KUnit tests on qemu using a |
| 197 | non-default configuration; then we can write our own``QemuConfig``. | 212 | non-default configuration; then we can write our own``QemuConfig``. |
| @@ -214,14 +229,11 @@ as · 16 unmodified lines | |||
| 214 | --jobs=12 \ | 229 | --jobs=12 \ |
| 215 | --qemu_config=./tools/testing/kunit/qemu_configs/x86_64.py | 230 | --qemu_config=./tools/testing/kunit/qemu_configs/x86_64.py |
| 216 | 231 | ||
| 217 | To run existing KUnit tests on non-UML architectures, see: | ||
| 218 | Documentation/dev-tools/kunit/non_uml.rst. | ||
| 219 | |||
| 220 | Command-Line Arguments | 232 | Command-Line Arguments |
| 221 | ====================== | 233 | ====================== |
| 222 | 234 | ||
| 223 | kunit_tool has a number of other command-line arguments which can | 235 | kunit_tool has a number of other command-line arguments which can |
| 224 | be useful for our test environment. Below the most commonly used | 236 | be useful for our test environment. Below are the most commonly used |
| 225 | command line arguments: | 237 | command line arguments: |
| 226 | 238 | ||
| 227 | - ``--help``: Lists all available options. To list common options, | 239 | - ``--help``: Lists all available options. To list common options, |
| @@ -245,3 +257,64 @@ command line arguments: · 17 unmodified lines | |||
| 245 | added or modified. Instead, enable all tests | 257 | added or modified. Instead, enable all tests |
| 246 | which have satisfied dependencies by adding | 258 | which have satisfied dependencies by adding |
| 247 | ``CONFIG_KUNIT_ALL_TESTS=y`` to your ``.kunitconfig``. | 259 | ``CONFIG_KUNIT_ALL_TESTS=y`` to your ``.kunitconfig``. |
| 260 | |||
| 261 | - ``--kunitconfig``: Specifies the path or the directory of the ``.kunitconfig`` | ||
| 262 | file. For example: | ||
| 263 | |||
| 264 | - ``lib/kunit/.kunitconfig`` can be the path of the file. | ||
| 265 | |||
| 266 | - ``lib/kunit`` can be the directory in which the file is located. | ||
| 267 | |||
| 268 | This file is used to build and run with a predefined set of tests | ||
| 269 | and their dependencies. For example, to run tests for a given subsystem. | ||
| 270 | |||
| 271 | - ``--kconfig_add``: Specifies additional configuration options to be | ||
| 272 | appended to the ``.kunitconfig`` file. For example: | ||
| 273 | |||
| 274 | .. code-block:: | ||
| 275 | |||
| 276 | ./tools/testing/kunit/kunit.py run --kconfig_add CONFIG_KASAN=y | ||
| 277 | |||
| 278 | - ``--arch``: Runs tests on the specified architecture. The architecture | ||
| 279 | argument is same as the Kbuild ARCH environment variable. | ||
| 280 | For example, i386, x86_64, arm, um, etc. Non-UML architectures run on qemu. | ||
| 281 | Default is `um`. | ||
| 282 | |||
| 283 | - ``--cross_compile``: Specifies the Kbuild toolchain. It passes the | ||
| 284 | same argument as passed to the ``CROSS_COMPILE`` variable used by | ||
| 285 | Kbuild. This will be the prefix for the toolchain | ||
| 286 | binaries such as GCC. For example: | ||
| 287 | |||
| 288 | - ``sparc64-linux-gnu-`` if we have the sparc toolchain installed on | ||
| 289 | our system. | ||
| 290 | |||
| 291 | - ``$HOME/toolchains/microblaze/gcc-9.2.0-nolibc/microblaze-linux/bin/microblaze-linux`` | ||
| 292 | if we have downloaded the microblaze toolchain from the 0-day | ||
| 293 | website to a specified path in our home directory called toolchains. | ||
| 294 | |||
| 295 | - ``--qemu_config``: Specifies the path to a file containing a | ||
| 296 | custom qemu architecture definition. This should be a python file | ||
| 297 | containing a `QemuArchParams` object. | ||
| 298 | |||
| 299 | - ``--qemu_args``: Specifies additional qemu arguments, for example, ``-smp 8``. | ||
| 300 | |||
| 301 | - ``--jobs``: Specifies the number of jobs (commands) to run simultaneously. | ||
| 302 | By default, this is set to the number of cores on your system. | ||
| 303 | |||
| 304 | - ``--timeout``: Specifies the maximum number of seconds allowed for all tests to run. | ||
| 305 | This does not include the time taken to build the tests. | ||
| 306 | |||
| 307 | - ``--kernel_args``: Specifies additional kernel command-line arguments. May be repeated. | ||
| 308 | |||
| 309 | - ``--run_isolated``: If set, boots the kernel for each individual suite/test. | ||
| 310 | This is useful for debugging a non-hermetic test, one that | ||
| 311 | might pass/fail based on what ran before it. | ||
| 312 | |||
| 313 | - ``--raw_output``: If set, generates unformatted output from kernel. Possible options are: | ||
| 314 | |||
| 315 | - ``all``: To view the full kernel output, use ``--raw_output=all``. | ||
| 316 | |||
| 317 | - ``kunit``: This is the default option and filters to KUnit output. Use ``--raw_output`` or ``--raw_output=kunit``. | ||
| 318 | |||
| 319 | - ``--json``: If set, stores the test results in a JSON format and prints to `stdout` or | ||
| 320 | saves to a file if a filename is specified. | ||
| @@ -15,7 +15,7 @@ It can be handy to create a bash function like: · 14 unmodified lines | |||
| 15 | .. code-block:: bash | 15 | .. code-block:: bash |
| 16 | 16 | ||
| 17 | function run_kunit() { | 17 | function run_kunit() { |
| 18 | ( cd "$(git rev-parse --show-toplevel)" && ./tools/testing/kunit/kunit.py run $@ ) | 18 | ( cd "$(git rev-parse --show-toplevel)" && ./tools/testing/kunit/kunit.py run "$@" ) |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | .. note:: | 21 | .. note:: |
| @@ -123,8 +123,7 @@ Putting it together into a copy-pastable sequence of commands: · 101 unmodified lines | |||
| 123 | .. code-block:: bash | 123 | .. code-block:: bash |
| 124 | 124 | ||
| 125 | # Append coverage options to the current config | 125 | # Append coverage options to the current config |
| 126 | $ echo -e "CONFIG_DEBUG_KERNEL=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y\nCONFIG_GCOV=y" >> .kunit/.kunitconfig | 126 | $ ./tools/testing/kunit/kunit.py run --kunitconfig=.kunit/ --kunitconfig=tools/testing/kunit/configs/coverage_uml.config |
| 127 | $ ./tools/testing/kunit/kunit.py run | ||
| 128 | # Extract the coverage information from the build dir (.kunit/) | 127 | # Extract the coverage information from the build dir (.kunit/) |
| 129 | $ lcov -t "my_kunit_tests" -o coverage.info -c -d .kunit/ | 128 | $ lcov -t "my_kunit_tests" -o coverage.info -c -d .kunit/ |
| 130 | 129 | ||
| @@ -505,7 +505,7 @@ By reusing the same ``cases`` array from above, we can write the test as a · 504 unmodified lines | |||
| 505 | const char *str; | 505 | const char *str; |
| 506 | const char *sha1; | 506 | const char *sha1; |
| 507 | }; | 507 | }; |
| 508 | struct sha1_test_case cases[] = { | 508 | const struct sha1_test_case cases[] = { |
| 509 | { | 509 | { |
| 510 | .str = "hello world", | 510 | .str = "hello world", |
| 511 | .sha1 = "2aae6c35c94fcfb415dbe95f408b9ce91ee846ed", | 511 | .sha1 = "2aae6c35c94fcfb415dbe95f408b9ce91ee846ed", |
| @@ -42,9 +42,7 @@ quiet_cmd_chk_bindings = CHKDT $@ · 41 unmodified lines | |||
| 42 | 42 | ||
| 43 | quiet_cmd_mk_schema = SCHEMA $@ | 43 | quiet_cmd_mk_schema = SCHEMA $@ |
| 44 | cmd_mk_schema = f=$$(mktemp) ; \ | 44 | cmd_mk_schema = f=$$(mktemp) ; \ |
| 45 | $(if $(DT_MK_SCHEMA_FLAGS), \ | 45 | $(find_all_cmd) > $$f ; \ |
| 46 | printf '%s\n' $(real-prereqs), \ | ||
| 47 | $(find_all_cmd)) > $$f ; \ | ||
| 48 | $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \ | 46 | $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \ |
| 49 | rm -f $$f | 47 | rm -f $$f |
| 50 | 48 | ||
| @@ -25,7 +25,14 @@ properties: · 24 unmodified lines | |||
| 25 | items: | 25 | items: |
| 26 | - enum: | 26 | - enum: |
| 27 | - altr,socfpga-arria10-socdk | 27 | - altr,socfpga-arria10-socdk |
| 28 | - enclustra,mercury-aa1 | 28 | - const: altr,socfpga-arria10 |
| 29 | - const: altr,socfpga | ||
| 30 | |||
| 31 | - description: Mercury+ AA1 boards | ||
| 32 | items: | ||
| 33 | - enum: | ||
| 34 | - google,chameleon-v3 | ||
| 35 | - const: enclustra,mercury-aa1 | ||
| 29 | - const: altr,socfpga-arria10 | 36 | - const: altr,socfpga-arria10 |
| 30 | - const: altr,socfpga | 37 | - const: altr,socfpga |
| 31 | 38 | ||
| @@ -47,6 +54,7 @@ properties: · 15 unmodified lines | |||
| 47 | items: | 54 | items: |
| 48 | - enum: | 55 | - enum: |
| 49 | - altr,socfpga-stratix10-socdk | 56 | - altr,socfpga-stratix10-socdk |
| 57 | - altr,socfpga-stratix10-swvp | ||
| 50 | - const: altr,socfpga-stratix10 | 58 | - const: altr,socfpga-stratix10 |
| 51 | 59 | ||
| 52 | - description: SoCFPGA VT | 60 | - description: SoCFPGA VT |
| @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" · 7 unmodified lines | |||
| 8 | title: Amlogic Meson Firmware registers Interface | 8 | title: Amlogic Meson Firmware registers Interface |
| 9 | 9 | ||
| 10 | maintainers: | 10 | maintainers: |
| 11 | - Neil Armstrong <narmstrong@baylibre.com> | 11 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 12 | 12 | ||
| 13 | description: | | 13 | description: | |
| 14 | The Meson SoCs have a register bank with status and data shared with the | 14 | The Meson SoCs have a register bank with status and data shared with the |
| @@ -0,0 +1,101 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm Coresight Address Translation Unit (CATU) | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The CoreSight Address Translation Unit (CATU) translates addresses between an | ||
| 24 | AXI master and system memory. The CATU is normally used along with the TMC to | ||
| 25 | implement scattering of virtual trace buffers in physical memory. The CATU | ||
| 26 | translates contiguous Virtual Addresses (VAs) from an AXI master into | ||
| 27 | non-contiguous Physical Addresses (PAs) that are intended for system memory. | ||
| 28 | |||
| 29 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 30 | select: | ||
| 31 | properties: | ||
| 32 | compatible: | ||
| 33 | contains: | ||
| 34 | const: arm,coresight-catu | ||
| 35 | required: | ||
| 36 | - compatible | ||
| 37 | |||
| 38 | allOf: | ||
| 39 | - $ref: /schemas/arm/primecell.yaml# | ||
| 40 | |||
| 41 | properties: | ||
| 42 | compatible: | ||
| 43 | items: | ||
| 44 | - const: arm,coresight-catu | ||
| 45 | - const: arm,primecell | ||
| 46 | |||
| 47 | reg: | ||
| 48 | maxItems: 1 | ||
| 49 | |||
| 50 | clocks: | ||
| 51 | minItems: 1 | ||
| 52 | maxItems: 2 | ||
| 53 | |||
| 54 | clock-names: | ||
| 55 | minItems: 1 | ||
| 56 | items: | ||
| 57 | - const: apb_pclk | ||
| 58 | - const: atclk | ||
| 59 | |||
| 60 | interrupts: | ||
| 61 | maxItems: 1 | ||
| 62 | description: Address translation error interrupt | ||
| 63 | |||
| 64 | in-ports: | ||
| 65 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 66 | additionalProperties: false | ||
| 67 | |||
| 68 | properties: | ||
| 69 | port: | ||
| 70 | description: AXI Slave connected to another Coresight component | ||
| 71 | $ref: /schemas/graph.yaml#/properties/port | ||
| 72 | |||
| 73 | required: | ||
| 74 | - compatible | ||
| 75 | - reg | ||
| 76 | - clocks | ||
| 77 | - clock-names | ||
| 78 | - in-ports | ||
| 79 | |||
| 80 | unevaluatedProperties: false | ||
| 81 | |||
| 82 | examples: | ||
| 83 | - | | ||
| 84 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 85 | catu@207e0000 { | ||
| 86 | compatible = "arm,coresight-catu", "arm,primecell"; | ||
| 87 | reg = <0x207e0000 0x1000>; | ||
| 88 | |||
| 89 | clocks = <&oscclk6a>; | ||
| 90 | clock-names = "apb_pclk"; | ||
| 91 | |||
| 92 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | ||
| 93 | in-ports { | ||
| 94 | port { | ||
| 95 | catu_in_port: endpoint { | ||
| 96 | remote-endpoint = <&etr_out_port>; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | ... | ||
| @@ -0,0 +1,81 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: CoreSight CPU Debug Component | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight CPU debug component are compliant with the ARMv8 architecture | ||
| 17 | reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The | ||
| 18 | external debug module is mainly used for two modes: self-hosted debug and | ||
| 19 | external debug, and it can be accessed from mmio region from Coresight and | ||
| 20 | eventually the debug module connects with CPU for debugging. And the debug | ||
| 21 | module provides sample-based profiling extension, which can be used to sample | ||
| 22 | CPU program counter, secure state and exception level, etc; usually every CPU | ||
| 23 | has one dedicated debug module to be connected. | ||
| 24 | |||
| 25 | select: | ||
| 26 | properties: | ||
| 27 | compatible: | ||
| 28 | contains: | ||
| 29 | const: arm,coresight-cpu-debug | ||
| 30 | required: | ||
| 31 | - compatible | ||
| 32 | |||
| 33 | allOf: | ||
| 34 | - $ref: /schemas/arm/primecell.yaml# | ||
| 35 | |||
| 36 | properties: | ||
| 37 | compatible: | ||
| 38 | items: | ||
| 39 | - const: arm,coresight-cpu-debug | ||
| 40 | - const: arm,primecell | ||
| 41 | |||
| 42 | reg: | ||
| 43 | maxItems: 1 | ||
| 44 | |||
| 45 | clocks: | ||
| 46 | maxItems: 1 | ||
| 47 | |||
| 48 | clock-names: | ||
| 49 | maxItems: 1 | ||
| 50 | |||
| 51 | cpu: | ||
| 52 | description: | ||
| 53 | A phandle to the cpu this debug component is bound to. | ||
| 54 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 55 | |||
| 56 | power-domains: | ||
| 57 | maxItems: 1 | ||
| 58 | description: | ||
| 59 | A phandle to the debug power domain if the debug logic has its own | ||
| 60 | dedicated power domain. CPU idle states may also need to be separately | ||
| 61 | constrained to keep CPU cores powered. | ||
| 62 | |||
| 63 | required: | ||
| 64 | - compatible | ||
| 65 | - reg | ||
| 66 | - clocks | ||
| 67 | - clock-names | ||
| 68 | - cpu | ||
| 69 | |||
| 70 | unevaluatedProperties: false | ||
| 71 | |||
| 72 | examples: | ||
| 73 | - | | ||
| 74 | debug@f6590000 { | ||
| 75 | compatible = "arm,coresight-cpu-debug", "arm,primecell"; | ||
| 76 | reg = <0xf6590000 0x1000>; | ||
| 77 | clocks = <&sys_ctrl 1>; | ||
| 78 | clock-names = "apb_pclk"; | ||
| 79 | cpu = <&cpu0>; | ||
| 80 | }; | ||
| 81 | ... | ||
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2019 Linaro Ltd. | 2 | # Copyright 2019 Linaro Ltd. |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: http://devicetree.org/schemas/arm/coresight-cti.yaml# | 5 | $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml# |
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | 7 | ||
| 8 | title: ARM Coresight Cross Trigger Interface (CTI) device. | 8 | title: ARM Coresight Cross Trigger Interface (CTI) device. |
| @@ -12,8 +12,7 @@ description: | · 3 unmodified lines | |||
| 12 | to one or more CoreSight components and/or a CPU, with CTIs interconnected in | 12 | to one or more CoreSight components and/or a CPU, with CTIs interconnected in |
| 13 | a star topology via the Cross Trigger Matrix (CTM), which is not programmable. | 13 | a star topology via the Cross Trigger Matrix (CTM), which is not programmable. |
| 14 | The ECT components are not part of the trace generation data path and are thus | 14 | The ECT components are not part of the trace generation data path and are thus |
| 15 | not part of the CoreSight graph described in the general CoreSight bindings | 15 | not part of the CoreSight graph. |
| 16 | file coresight.txt. | ||
| 17 | 16 | ||
| 18 | The CTI component properties define the connections between the individual | 17 | The CTI component properties define the connections between the individual |
| 19 | CTI and the components it is directly connected to, consisting of input and | 18 | CTI and the components it is directly connected to, consisting of input and |
| @@ -0,0 +1,126 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Programmable Trace Bus Funnel | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The Coresight funnel merges 2-8 trace sources into a single trace | ||
| 24 | stream with programmable enable and priority of input ports. | ||
| 25 | |||
| 26 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 27 | select: | ||
| 28 | properties: | ||
| 29 | compatible: | ||
| 30 | contains: | ||
| 31 | const: arm,coresight-dynamic-funnel | ||
| 32 | required: | ||
| 33 | - compatible | ||
| 34 | |||
| 35 | allOf: | ||
| 36 | - $ref: /schemas/arm/primecell.yaml# | ||
| 37 | |||
| 38 | properties: | ||
| 39 | compatible: | ||
| 40 | items: | ||
| 41 | - const: arm,coresight-dynamic-funnel | ||
| 42 | - const: arm,primecell | ||
| 43 | |||
| 44 | reg: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | clocks: | ||
| 48 | minItems: 1 | ||
| 49 | maxItems: 2 | ||
| 50 | |||
| 51 | clock-names: | ||
| 52 | minItems: 1 | ||
| 53 | items: | ||
| 54 | - const: apb_pclk | ||
| 55 | - const: atclk | ||
| 56 | |||
| 57 | in-ports: | ||
| 58 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 59 | |||
| 60 | patternProperties: | ||
| 61 | '^port(@[0-7])?$': | ||
| 62 | description: Input connections from CoreSight Trace bus | ||
| 63 | $ref: /schemas/graph.yaml#/properties/port | ||
| 64 | |||
| 65 | out-ports: | ||
| 66 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 67 | additionalProperties: false | ||
| 68 | |||
| 69 | properties: | ||
| 70 | port: | ||
| 71 | description: Output connection to CoreSight Trace bus | ||
| 72 | $ref: /schemas/graph.yaml#/properties/port | ||
| 73 | |||
| 74 | required: | ||
| 75 | - compatible | ||
| 76 | - reg | ||
| 77 | - clocks | ||
| 78 | - clock-names | ||
| 79 | - in-ports | ||
| 80 | - out-ports | ||
| 81 | |||
| 82 | unevaluatedProperties: false | ||
| 83 | |||
| 84 | examples: | ||
| 85 | - | | ||
| 86 | funnel@20040000 { | ||
| 87 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | ||
| 88 | reg = <0x20040000 0x1000>; | ||
| 89 | |||
| 90 | clocks = <&oscclk6a>; | ||
| 91 | clock-names = "apb_pclk"; | ||
| 92 | out-ports { | ||
| 93 | port { | ||
| 94 | funnel_out_port0: endpoint { | ||
| 95 | remote-endpoint = <&replicator_in_port0>; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | |||
| 100 | in-ports { | ||
| 101 | #address-cells = <1>; | ||
| 102 | #size-cells = <0>; | ||
| 103 | |||
| 104 | port@0 { | ||
| 105 | reg = <0>; | ||
| 106 | funnel_in_port0: endpoint { | ||
| 107 | remote-endpoint = <&ptm0_out_port>; | ||
| 108 | }; | ||
| 109 | }; | ||
| 110 | |||
| 111 | port@1 { | ||
| 112 | reg = <1>; | ||
| 113 | funnel_in_port1: endpoint { | ||
| 114 | remote-endpoint = <&ptm1_out_port>; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | |||
| 118 | port@2 { | ||
| 119 | reg = <2>; | ||
| 120 | funnel_in_port2: endpoint { | ||
| 121 | remote-endpoint = <&etm0_out_port>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | ... | ||
| @@ -0,0 +1,126 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm Coresight Programmable Trace Bus Replicator | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The Coresight replicator splits a single trace stream into two trace streams | ||
| 24 | for systems that have more than one trace sink component. | ||
| 25 | |||
| 26 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 27 | select: | ||
| 28 | properties: | ||
| 29 | compatible: | ||
| 30 | contains: | ||
| 31 | const: arm,coresight-dynamic-replicator | ||
| 32 | required: | ||
| 33 | - compatible | ||
| 34 | |||
| 35 | allOf: | ||
| 36 | - $ref: /schemas/arm/primecell.yaml# | ||
| 37 | |||
| 38 | properties: | ||
| 39 | compatible: | ||
| 40 | items: | ||
| 41 | - const: arm,coresight-dynamic-replicator | ||
| 42 | - const: arm,primecell | ||
| 43 | |||
| 44 | reg: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | clocks: | ||
| 48 | minItems: 1 | ||
| 49 | maxItems: 2 | ||
| 50 | |||
| 51 | clock-names: | ||
| 52 | minItems: 1 | ||
| 53 | items: | ||
| 54 | - const: apb_pclk | ||
| 55 | - const: atclk | ||
| 56 | |||
| 57 | qcom,replicator-loses-context: | ||
| 58 | type: boolean | ||
| 59 | description: | ||
| 60 | Indicates that the replicator will lose register context when AMBA clock | ||
| 61 | is removed which is observed in some replicator designs. | ||
| 62 | |||
| 63 | in-ports: | ||
| 64 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 65 | additionalProperties: false | ||
| 66 | |||
| 67 | properties: | ||
| 68 | port: | ||
| 69 | description: Input connection from CoreSight Trace bus | ||
| 70 | $ref: /schemas/graph.yaml#/properties/port | ||
| 71 | |||
| 72 | out-ports: | ||
| 73 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 74 | |||
| 75 | patternProperties: | ||
| 76 | '^port(@[01])?$': | ||
| 77 | description: Output connections to CoreSight Trace bus | ||
| 78 | $ref: /schemas/graph.yaml#/properties/port | ||
| 79 | |||
| 80 | required: | ||
| 81 | - compatible | ||
| 82 | - reg | ||
| 83 | - clocks | ||
| 84 | - clock-names | ||
| 85 | - in-ports | ||
| 86 | - out-ports | ||
| 87 | |||
| 88 | unevaluatedProperties: false | ||
| 89 | |||
| 90 | examples: | ||
| 91 | - | | ||
| 92 | replicator@20120000 { | ||
| 93 | compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; | ||
| 94 | reg = <0x20120000 0x1000>; | ||
| 95 | |||
| 96 | clocks = <&soc_smc50mhz>; | ||
| 97 | clock-names = "apb_pclk"; | ||
| 98 | |||
| 99 | out-ports { | ||
| 100 | #address-cells = <1>; | ||
| 101 | #size-cells = <0>; | ||
| 102 | |||
| 103 | /* replicator output ports */ | ||
| 104 | port@0 { | ||
| 105 | reg = <0>; | ||
| 106 | replicator_out_port0: endpoint { | ||
| 107 | remote-endpoint = <&tpiu_in_port>; | ||
| 108 | }; | ||
| 109 | }; | ||
| 110 | |||
| 111 | port@1 { | ||
| 112 | reg = <1>; | ||
| 113 | replicator_out_port1: endpoint { | ||
| 114 | remote-endpoint = <&etr_in_port>; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | in-ports { | ||
| 119 | port { | ||
| 120 | replicator_in_port0: endpoint { | ||
| 121 | remote-endpoint = <&csys2_funnel_out_port>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | ... | ||
| @@ -0,0 +1,92 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Embedded Trace Buffer | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is | ||
| 24 | used as a circular buffer. | ||
| 25 | |||
| 26 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 27 | select: | ||
| 28 | properties: | ||
| 29 | compatible: | ||
| 30 | contains: | ||
| 31 | const: arm,coresight-etb10 | ||
| 32 | required: | ||
| 33 | - compatible | ||
| 34 | |||
| 35 | allOf: | ||
| 36 | - $ref: /schemas/arm/primecell.yaml# | ||
| 37 | |||
| 38 | properties: | ||
| 39 | compatible: | ||
| 40 | items: | ||
| 41 | - const: arm,coresight-etb10 | ||
| 42 | - const: arm,primecell | ||
| 43 | |||
| 44 | reg: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | clocks: | ||
| 48 | minItems: 1 | ||
| 49 | maxItems: 2 | ||
| 50 | |||
| 51 | clock-names: | ||
| 52 | minItems: 1 | ||
| 53 | items: | ||
| 54 | - const: apb_pclk | ||
| 55 | - const: atclk | ||
| 56 | |||
| 57 | in-ports: | ||
| 58 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 59 | additionalProperties: false | ||
| 60 | |||
| 61 | properties: | ||
| 62 | port: | ||
| 63 | description: Input connection from CoreSight Trace bus. | ||
| 64 | $ref: /schemas/graph.yaml#/properties/port | ||
| 65 | |||
| 66 | required: | ||
| 67 | - compatible | ||
| 68 | - reg | ||
| 69 | - clocks | ||
| 70 | - clock-names | ||
| 71 | - in-ports | ||
| 72 | |||
| 73 | unevaluatedProperties: false | ||
| 74 | |||
| 75 | examples: | ||
| 76 | - | | ||
| 77 | etb@20010000 { | ||
| 78 | compatible = "arm,coresight-etb10", "arm,primecell"; | ||
| 79 | reg = <0x20010000 0x1000>; | ||
| 80 | |||
| 81 | clocks = <&oscclk6a>; | ||
| 82 | clock-names = "apb_pclk"; | ||
| 83 | in-ports { | ||
| 84 | port { | ||
| 85 | etb_in_port: endpoint { | ||
| 86 | remote-endpoint = <&replicator_out_port0>; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | |||
| 92 | ... | ||
| @@ -0,0 +1,156 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Embedded Trace MacroCell | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The Embedded Trace Macrocell (ETM) is a real-time trace module providing | ||
| 24 | instruction and data tracing of a processor. | ||
| 25 | |||
| 26 | select: | ||
| 27 | properties: | ||
| 28 | compatible: | ||
| 29 | contains: | ||
| 30 | enum: | ||
| 31 | - arm,coresight-etm3x | ||
| 32 | - arm,coresight-etm4x | ||
| 33 | - arm,coresight-etm4x-sysreg | ||
| 34 | required: | ||
| 35 | - compatible | ||
| 36 | |||
| 37 | allOf: | ||
| 38 | - if: | ||
| 39 | not: | ||
| 40 | properties: | ||
| 41 | compatible: | ||
| 42 | contains: | ||
| 43 | const: arm,coresight-etm4x-sysreg | ||
| 44 | then: | ||
| 45 | $ref: /schemas/arm/primecell.yaml# | ||
| 46 | required: | ||
| 47 | - reg | ||
| 48 | |||
| 49 | properties: | ||
| 50 | compatible: | ||
| 51 | oneOf: | ||
| 52 | - description: | ||
| 53 | Embedded Trace Macrocell with memory mapped access. | ||
| 54 | items: | ||
| 55 | - enum: | ||
| 56 | - arm,coresight-etm3x | ||
| 57 | - arm,coresight-etm4x | ||
| 58 | - const: arm,primecell | ||
| 59 | - description: | ||
| 60 | Embedded Trace Macrocell (version 4.x), with system register access only | ||
| 61 | const: arm,coresight-etm4x-sysreg | ||
| 62 | |||
| 63 | reg: | ||
| 64 | maxItems: 1 | ||
| 65 | |||
| 66 | clocks: | ||
| 67 | minItems: 1 | ||
| 68 | maxItems: 2 | ||
| 69 | |||
| 70 | clock-names: | ||
| 71 | minItems: 1 | ||
| 72 | items: | ||
| 73 | - const: apb_pclk | ||
| 74 | - const: atclk | ||
| 75 | |||
| 76 | arm,coresight-loses-context-with-cpu: | ||
| 77 | type: boolean | ||
| 78 | description: | ||
| 79 | Indicates that the hardware will lose register context on CPU power down | ||
| 80 | (e.g. CPUIdle). An example of where this may be needed are systems which | ||
| 81 | contain a coresight component and CPU in the same power domain. When the | ||
| 82 | CPU powers down the coresight component also powers down and loses its | ||
| 83 | context. | ||
| 84 | |||
| 85 | arm,cp14: | ||
| 86 | type: boolean | ||
| 87 | description: | ||
| 88 | Must be present if the system accesses ETM/PTM management registers via | ||
| 89 | co-processor 14. | ||
| 90 | |||
| 91 | qcom,skip-power-up: | ||
| 92 | type: boolean | ||
| 93 | description: | ||
| 94 | Indicates that an implementation can skip powering up the trace unit. | ||
| 95 | TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems | ||
| 96 | since ETMs are in the same power domain as their CPU cores. This property | ||
| 97 | is required to identify such systems with hardware errata where the CPU | ||
| 98 | watchdog counter is stopped when TRCPDCR.PU is set. | ||
| 99 | |||
| 100 | cpu: | ||
| 101 | description: | ||
| 102 | phandle to the cpu this ETM is bound to. | ||
| 103 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 104 | |||
| 105 | out-ports: | ||
| 106 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 107 | additionalProperties: false | ||
| 108 | |||
| 109 | properties: | ||
| 110 | port: | ||
| 111 | description: Output connection from the ETM to CoreSight Trace bus. | ||
| 112 | $ref: /schemas/graph.yaml#/properties/port | ||
| 113 | |||
| 114 | required: | ||
| 115 | - compatible | ||
| 116 | - clocks | ||
| 117 | - clock-names | ||
| 118 | - cpu | ||
| 119 | - out-ports | ||
| 120 | |||
| 121 | unevaluatedProperties: false | ||
| 122 | |||
| 123 | examples: | ||
| 124 | - | | ||
| 125 | ptm@2201c000 { | ||
| 126 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
| 127 | reg = <0x2201c000 0x1000>; | ||
| 128 | |||
| 129 | cpu = <&cpu0>; | ||
| 130 | clocks = <&oscclk6a>; | ||
| 131 | clock-names = "apb_pclk"; | ||
| 132 | out-ports { | ||
| 133 | port { | ||
| 134 | ptm0_out_port: endpoint { | ||
| 135 | remote-endpoint = <&funnel_in_port0>; | ||
| 136 | }; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | }; | ||
| 140 | |||
| 141 | ptm@2201d000 { | ||
| 142 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
| 143 | reg = <0x2201d000 0x1000>; | ||
| 144 | |||
| 145 | cpu = <&cpu1>; | ||
| 146 | clocks = <&oscclk6a>; | ||
| 147 | clock-names = "apb_pclk"; | ||
| 148 | out-ports { | ||
| 149 | port { | ||
| 150 | ptm1_out_port: endpoint { | ||
| 151 | remote-endpoint = <&funnel_in_port1>; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | }; | ||
| 155 | }; | ||
| 156 | ... | ||
| @@ -0,0 +1,90 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Static Trace Bus Funnel | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The Coresight static funnel merges 2-8 trace sources into a single trace | ||
| 24 | stream. | ||
| 25 | |||
| 26 | properties: | ||
| 27 | compatible: | ||
| 28 | const: arm,coresight-static-funnel | ||
| 29 | |||
| 30 | in-ports: | ||
| 31 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 32 | |||
| 33 | patternProperties: | ||
| 34 | '^port@[0-7]$': | ||
| 35 | description: Input connections from CoreSight Trace bus | ||
| 36 | $ref: /schemas/graph.yaml#/properties/port | ||
| 37 | |||
| 38 | out-ports: | ||
| 39 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 40 | additionalProperties: false | ||
| 41 | |||
| 42 | properties: | ||
| 43 | port: | ||
| 44 | description: Output connection to CoreSight Trace bus | ||
| 45 | $ref: /schemas/graph.yaml#/properties/port | ||
| 46 | |||
| 47 | required: | ||
| 48 | - compatible | ||
| 49 | - in-ports | ||
| 50 | - out-ports | ||
| 51 | |||
| 52 | additionalProperties: false | ||
| 53 | |||
| 54 | examples: | ||
| 55 | - | | ||
| 56 | funnel { | ||
| 57 | /* | ||
| 58 | * non-configurable replicators don't show up on the | ||
| 59 | * AMBA bus. As such no need to add "arm,primecell". | ||
| 60 | */ | ||
| 61 | compatible = "arm,coresight-static-funnel"; | ||
| 62 | |||
| 63 | out-ports { | ||
| 64 | port { | ||
| 65 | combo_funnel_out: endpoint { | ||
| 66 | remote-endpoint = <&top_funnel_in>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | in-ports { | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <0>; | ||
| 74 | |||
| 75 | port@0 { | ||
| 76 | reg = <0>; | ||
| 77 | combo_funnel_in0: endpoint { | ||
| 78 | remote-endpoint = <&cluster0_etf_out>; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | port@1 { | ||
| 83 | reg = <1>; | ||
| 84 | combo_funnel_in1: endpoint { | ||
| 85 | remote-endpoint = <&cluster1_etf_out>; | ||
| 86 | }; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | ... | ||
| @@ -0,0 +1,91 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Static Trace Bus Replicator | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The Coresight replicator splits a single trace stream into two trace streams | ||
| 24 | for systems that have more than one trace sink component. | ||
| 25 | |||
| 26 | properties: | ||
| 27 | compatible: | ||
| 28 | const: arm,coresight-static-replicator | ||
| 29 | |||
| 30 | in-ports: | ||
| 31 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 32 | additionalProperties: false | ||
| 33 | |||
| 34 | properties: | ||
| 35 | port: | ||
| 36 | description: Input connection from CoreSight Trace bus | ||
| 37 | $ref: /schemas/graph.yaml#/properties/port | ||
| 38 | |||
| 39 | out-ports: | ||
| 40 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 41 | |||
| 42 | patternProperties: | ||
| 43 | '^port@[01]$': | ||
| 44 | description: Output connections to CoreSight Trace bus | ||
| 45 | $ref: /schemas/graph.yaml#/properties/port | ||
| 46 | |||
| 47 | required: | ||
| 48 | - compatible | ||
| 49 | - in-ports | ||
| 50 | - out-ports | ||
| 51 | |||
| 52 | additionalProperties: false | ||
| 53 | |||
| 54 | examples: | ||
| 55 | - | | ||
| 56 | replicator { | ||
| 57 | /* | ||
| 58 | * non-configurable replicators don't show up on the | ||
| 59 | * AMBA bus. As such no need to add "arm,primecell". | ||
| 60 | */ | ||
| 61 | compatible = "arm,coresight-static-replicator"; | ||
| 62 | |||
| 63 | out-ports { | ||
| 64 | #address-cells = <1>; | ||
| 65 | #size-cells = <0>; | ||
| 66 | |||
| 67 | /* replicator output ports */ | ||
| 68 | port@0 { | ||
| 69 | reg = <0>; | ||
| 70 | replicator_out_port0: endpoint { | ||
| 71 | remote-endpoint = <&etb_in_port>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | port@1 { | ||
| 76 | reg = <1>; | ||
| 77 | replicator_out_port1: endpoint { | ||
| 78 | remote-endpoint = <&tpiu_in_port>; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | in-ports { | ||
| 84 | port { | ||
| 85 | replicator_in_port0: endpoint { | ||
| 86 | remote-endpoint = <&funnel_out_port0>; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | ... | ||
| @@ -0,0 +1,101 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight System Trace MacroCell | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The STM is a trace source that is integrated into a CoreSight system, designed | ||
| 24 | primarily for high-bandwidth trace of instrumentation embedded into software. | ||
| 25 | This instrumentation is made up of memory-mapped writes to the STM Advanced | ||
| 26 | eXtensible Interface (AXI) slave, which carry information about the behavior | ||
| 27 | of the software. | ||
| 28 | |||
| 29 | select: | ||
| 30 | properties: | ||
| 31 | compatible: | ||
| 32 | contains: | ||
| 33 | const: arm,coresight-stm | ||
| 34 | required: | ||
| 35 | - compatible | ||
| 36 | |||
| 37 | allOf: | ||
| 38 | - $ref: /schemas/arm/primecell.yaml# | ||
| 39 | |||
| 40 | properties: | ||
| 41 | compatible: | ||
| 42 | items: | ||
| 43 | - const: arm,coresight-stm | ||
| 44 | - const: arm,primecell | ||
| 45 | |||
| 46 | reg: | ||
| 47 | maxItems: 2 | ||
| 48 | |||
| 49 | reg-names: | ||
| 50 | items: | ||
| 51 | - const: stm-base | ||
| 52 | - const: stm-stimulus-base | ||
| 53 | |||
| 54 | clocks: | ||
| 55 | minItems: 1 | ||
| 56 | maxItems: 2 | ||
| 57 | |||
| 58 | clock-names: | ||
| 59 | minItems: 1 | ||
| 60 | items: | ||
| 61 | - const: apb_pclk | ||
| 62 | - const: atclk | ||
| 63 | |||
| 64 | out-ports: | ||
| 65 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 66 | additionalProperties: false | ||
| 67 | |||
| 68 | properties: | ||
| 69 | port: | ||
| 70 | description: Output connection to the CoreSight Trace bus. | ||
| 71 | $ref: /schemas/graph.yaml#/properties/port | ||
| 72 | |||
| 73 | required: | ||
| 74 | - compatible | ||
| 75 | - reg | ||
| 76 | - reg-names | ||
| 77 | - clocks | ||
| 78 | - clock-names | ||
| 79 | - out-ports | ||
| 80 | |||
| 81 | unevaluatedProperties: false | ||
| 82 | |||
| 83 | examples: | ||
| 84 | - | | ||
| 85 | stm@20100000 { | ||
| 86 | compatible = "arm,coresight-stm", "arm,primecell"; | ||
| 87 | reg = <0x20100000 0x1000>, | ||
| 88 | <0x28000000 0x180000>; | ||
| 89 | reg-names = "stm-base", "stm-stimulus-base"; | ||
| 90 | |||
| 91 | clocks = <&soc_smc50mhz>; | ||
| 92 | clock-names = "apb_pclk"; | ||
| 93 | out-ports { | ||
| 94 | port { | ||
| 95 | stm_out_port: endpoint { | ||
| 96 | remote-endpoint = <&main_funnel_in_port2>; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | ... | ||
| @@ -0,0 +1,131 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Trace Memory Controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace | ||
| 24 | FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration | ||
| 25 | mode (ETB, ETF, ETR) is discovered at boot time when the device is probed. | ||
| 26 | |||
| 27 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 28 | select: | ||
| 29 | properties: | ||
| 30 | compatible: | ||
| 31 | contains: | ||
| 32 | const: arm,coresight-tmc | ||
| 33 | required: | ||
| 34 | - compatible | ||
| 35 | |||
| 36 | allOf: | ||
| 37 | - $ref: /schemas/arm/primecell.yaml# | ||
| 38 | |||
| 39 | properties: | ||
| 40 | compatible: | ||
| 41 | items: | ||
| 42 | - const: arm,coresight-tmc | ||
| 43 | - const: arm,primecell | ||
| 44 | |||
| 45 | reg: | ||
| 46 | maxItems: 1 | ||
| 47 | |||
| 48 | clocks: | ||
| 49 | minItems: 1 | ||
| 50 | maxItems: 2 | ||
| 51 | |||
| 52 | clock-names: | ||
| 53 | minItems: 1 | ||
| 54 | items: | ||
| 55 | - const: apb_pclk | ||
| 56 | - const: atclk | ||
| 57 | |||
| 58 | arm,buffer-size: | ||
| 59 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 60 | deprecated: true | ||
| 61 | description: | ||
| 62 | Size of contiguous buffer space for TMC ETR (embedded trace router). The | ||
| 63 | buffer size can be configured dynamically via buffer_size property in | ||
| 64 | sysfs instead. | ||
| 65 | |||
| 66 | arm,scatter-gather: | ||
| 67 | type: boolean | ||
| 68 | description: | ||
| 69 | Indicates that the TMC-ETR can safely use the SG mode on this system. | ||
| 70 | |||
| 71 | arm,max-burst-size: | ||
| 72 | description: | ||
| 73 | The maximum burst size initiated by TMC on the AXI master interface. The | ||
| 74 | burst size can be in the range [0..15], the setting supports one data | ||
| 75 | transfer per burst up to a maximum of 16 data transfers per burst. | ||
| 76 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 77 | maximum: 15 | ||
| 78 | |||
| 79 | in-ports: | ||
| 80 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 81 | additionalProperties: false | ||
| 82 | |||
| 83 | properties: | ||
| 84 | port: | ||
| 85 | description: Input connection from the CoreSight Trace bus. | ||
| 86 | $ref: /schemas/graph.yaml#/properties/port | ||
| 87 | |||
| 88 | out-ports: | ||
| 89 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 90 | additionalProperties: false | ||
| 91 | |||
| 92 | properties: | ||
| 93 | port: | ||
| 94 | description: AXI or ATB Master output connection. Used for ETR | ||
| 95 | and ETF configurations. | ||
| 96 | $ref: /schemas/graph.yaml#/properties/port | ||
| 97 | |||
| 98 | required: | ||
| 99 | - compatible | ||
| 100 | - reg | ||
| 101 | - clocks | ||
| 102 | - clock-names | ||
| 103 | - in-ports | ||
| 104 | |||
| 105 | unevaluatedProperties: false | ||
| 106 | |||
| 107 | examples: | ||
| 108 | - | | ||
| 109 | etr@20070000 { | ||
| 110 | compatible = "arm,coresight-tmc", "arm,primecell"; | ||
| 111 | reg = <0x20070000 0x1000>; | ||
| 112 | |||
| 113 | clocks = <&oscclk6a>; | ||
| 114 | clock-names = "apb_pclk"; | ||
| 115 | in-ports { | ||
| 116 | port { | ||
| 117 | etr_in_port: endpoint { | ||
| 118 | remote-endpoint = <&replicator2_out_port0>; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | out-ports { | ||
| 124 | port { | ||
| 125 | etr_out_port: endpoint { | ||
| 126 | remote-endpoint = <&catu_in_port>; | ||
| 127 | }; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | ... | ||
| @@ -0,0 +1,91 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm CoreSight Trace Port Interface Unit | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Mathieu Poirier <mathieu.poirier@linaro.org> | ||
| 11 | - Mike Leach <mike.leach@linaro.org> | ||
| 12 | - Leo Yan <leo.yan@linaro.org> | ||
| 13 | - Suzuki K Poulose <suzuki.poulose@arm.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 17 | specification and can be connected in various topologies to suit a particular | ||
| 18 | SoCs tracing needs. These trace components can generally be classified as | ||
| 19 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 20 | through the intermediate links connecting the source to the currently selected | ||
| 21 | sink. | ||
| 22 | |||
| 23 | The CoreSight Trace Port Interface Unit captures trace data from the trace bus | ||
| 24 | and outputs it to an external trace port. | ||
| 25 | |||
| 26 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 27 | select: | ||
| 28 | properties: | ||
| 29 | compatible: | ||
| 30 | contains: | ||
| 31 | const: arm,coresight-tpiu | ||
| 32 | required: | ||
| 33 | - compatible | ||
| 34 | |||
| 35 | allOf: | ||
| 36 | - $ref: /schemas/arm/primecell.yaml# | ||
| 37 | |||
| 38 | properties: | ||
| 39 | compatible: | ||
| 40 | items: | ||
| 41 | - const: arm,coresight-tpiu | ||
| 42 | - const: arm,primecell | ||
| 43 | |||
| 44 | reg: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | clocks: | ||
| 48 | minItems: 1 | ||
| 49 | maxItems: 2 | ||
| 50 | |||
| 51 | clock-names: | ||
| 52 | minItems: 1 | ||
| 53 | items: | ||
| 54 | - const: apb_pclk | ||
| 55 | - const: atclk | ||
| 56 | |||
| 57 | in-ports: | ||
| 58 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 59 | additionalProperties: false | ||
| 60 | |||
| 61 | properties: | ||
| 62 | port: | ||
| 63 | description: Input connection from the CoreSight Trace bus. | ||
| 64 | $ref: /schemas/graph.yaml#/properties/port | ||
| 65 | |||
| 66 | required: | ||
| 67 | - compatible | ||
| 68 | - reg | ||
| 69 | - clocks | ||
| 70 | - clock-names | ||
| 71 | - in-ports | ||
| 72 | |||
| 73 | unevaluatedProperties: false | ||
| 74 | |||
| 75 | examples: | ||
| 76 | - | | ||
| 77 | tpiu@e3c05000 { | ||
| 78 | compatible = "arm,coresight-tpiu", "arm,primecell"; | ||
| 79 | reg = <0xe3c05000 0x1000>; | ||
| 80 | |||
| 81 | clocks = <&clk_375m>; | ||
| 82 | clock-names = "apb_pclk"; | ||
| 83 | in-ports { | ||
| 84 | port { | ||
| 85 | tpiu_in_port: endpoint { | ||
| 86 | remote-endpoint = <&funnel4_out_port0>; | ||
| 87 | }; | ||
| 88 | }; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | ... | ||
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2021, Arm Ltd | 2 | # Copyright 2021, Arm Ltd |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/arm/ete.yaml#" | 5 | $id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | 7 | ||
| 8 | title: ARM Embedded Trace Extensions | 8 | title: ARM Embedded Trace Extensions |
| @@ -20,7 +20,6 @@ description: | · 11 unmodified lines | |||
| 20 | Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to | 20 | Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to |
| 21 | legacy CoreSight components, a node must be listed per instance, along | 21 | legacy CoreSight components, a node must be listed per instance, along |
| 22 | with any optional connection graph as per the coresight bindings. | 22 | with any optional connection graph as per the coresight bindings. |
| 23 | See bindings/arm/coresight.txt. | ||
| 24 | 23 | ||
| 25 | properties: | 24 | properties: |
| 26 | $nodename: | 25 | $nodename: |
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2021, Arm Ltd | 2 | # Copyright 2021, Arm Ltd |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/arm/trbe.yaml#" | 5 | $id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | 7 | ||
| 8 | title: ARM Trace Buffer Extensions | 8 | title: ARM Trace Buffer Extensions |
| @@ -0,0 +1,87 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Aspeed SoC based boards | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Joel Stanley <joel@jms.id.au> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | $nodename: | ||
| 14 | const: '/' | ||
| 15 | compatible: | ||
| 16 | oneOf: | ||
| 17 | - description: AST2400 based boards | ||
| 18 | items: | ||
| 19 | - enum: | ||
| 20 | - facebook,galaxy100-bmc | ||
| 21 | - facebook,wedge100-bmc | ||
| 22 | - facebook,wedge40-bmc | ||
| 23 | - microsoft,olympus-bmc | ||
| 24 | - quanta,q71l-bmc | ||
| 25 | - tyan,palmetto-bmc | ||
| 26 | - yadro,vesnin-bmc | ||
| 27 | - const: aspeed,ast2400 | ||
| 28 | |||
| 29 | - description: AST2500 based boards | ||
| 30 | items: | ||
| 31 | - enum: | ||
| 32 | - amd,ethanolx-bmc | ||
| 33 | - ampere,mtjade-bmc | ||
| 34 | - aspeed,ast2500-evb | ||
| 35 | - asrock,e3c246d4i-bmc | ||
| 36 | - asrock,romed8hm3-bmc | ||
| 37 | - bytedance,g220a-bmc | ||
| 38 | - facebook,cmm-bmc | ||
| 39 | - facebook,minipack-bmc | ||
| 40 | - facebook,tiogapass-bmc | ||
| 41 | - facebook,yamp-bmc | ||
| 42 | - facebook,yosemitev2-bmc | ||
| 43 | - facebook,wedge400-bmc | ||
| 44 | - hxt,stardragon4800-rep2-bmc | ||
| 45 | - ibm,mihawk-bmc | ||
| 46 | - ibm,mowgli-bmc | ||
| 47 | - ibm,romulus-bmc | ||
| 48 | - ibm,swift-bmc | ||
| 49 | - ibm,witherspoon-bmc | ||
| 50 | - ingrasys,zaius-bmc | ||
| 51 | - inspur,fp5280g2-bmc | ||
| 52 | - inspur,nf5280m6-bmc | ||
| 53 | - inspur,on5263m5-bmc | ||
| 54 | - intel,s2600wf-bmc | ||
| 55 | - inventec,lanyang-bmc | ||
| 56 | - lenovo,hr630-bmc | ||
| 57 | - lenovo,hr855xg2-bmc | ||
| 58 | - portwell,neptune-bmc | ||
| 59 | - qcom,centriq2400-rep-bmc | ||
| 60 | - supermicro,x11spi-bmc | ||
| 61 | - tyan,s7106-bmc | ||
| 62 | - tyan,s8036-bmc | ||
| 63 | - yadro,nicole-bmc | ||
| 64 | - yadro,vegman-n110-bmc | ||
| 65 | - yadro,vegman-rx20-bmc | ||
| 66 | - yadro,vegman-sx20-bmc | ||
| 67 | - const: aspeed,ast2500 | ||
| 68 | |||
| 69 | - description: AST2600 based boards | ||
| 70 | items: | ||
| 71 | - enum: | ||
| 72 | - aspeed,ast2600-evb | ||
| 73 | - aspeed,ast2600-evb-a1 | ||
| 74 | - facebook,bletchley-bmc | ||
| 75 | - facebook,cloudripper-bmc | ||
| 76 | - facebook,elbert-bmc | ||
| 77 | - facebook,fuji-bmc | ||
| 78 | - ibm,everest-bmc | ||
| 79 | - ibm,rainier-bmc | ||
| 80 | - ibm,tacoma-bmc | ||
| 81 | - inventec,transformer-bmc | ||
| 82 | - jabil,rbp-bmc | ||
| 83 | - nuvia,dc-scm-bmc | ||
| 84 | - quanta,s6q-bmc | ||
| 85 | - const: aspeed,ast2600 | ||
| 86 | |||
| 87 | additionalProperties: true | ||
| @@ -163,9 +163,11 @@ properties: · 162 unmodified lines | |||
| 163 | - const: microchip,sama7g5 | 163 | - const: microchip,sama7g5 |
| 164 | - const: microchip,sama7 | 164 | - const: microchip,sama7 |
| 165 | 165 | ||
| 166 | - description: Microchip LAN9662 PCB8291 Evaluation Board. | 166 | - description: Microchip LAN9662 Evaluation Boards. |
| 167 | items: | 167 | items: |
| 168 | - const: microchip,lan9662-pcb8291 | 168 | - enum: |
| 169 | - microchip,lan9662-pcb8291 | ||
| 170 | - microchip,lan9662-pcb8309 | ||
| 169 | - const: microchip,lan9662 | 171 | - const: microchip,lan9662 |
| 170 | - const: microchip,lan966 | 172 | - const: microchip,lan966 |
| 171 | 173 | ||
| @@ -25,21 +25,6 @@ System Timer (ST) required properties: · 24 unmodified lines | |||
| 25 | Its subnodes can be: | 25 | Its subnodes can be: |
| 26 | - watchdog: compatible should be "atmel,at91rm9200-wdt" | 26 | - watchdog: compatible should be "atmel,at91rm9200-wdt" |
| 27 | 27 | ||
| 28 | RSTC Reset Controller required properties: | ||
| 29 | - compatible: Should be "atmel,<chip>-rstc". | ||
| 30 | <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" | ||
| 31 | it also can be "microchip,sam9x60-rstc" | ||
| 32 | - reg: Should contain registers location and length | ||
| 33 | - clocks: phandle to input clock. | ||
| 34 | |||
| 35 | Example: | ||
| 36 | |||
| 37 | rstc@fffffd00 { | ||
| 38 | compatible = "atmel,at91sam9260-rstc"; | ||
| 39 | reg = <0xfffffd00 0x10>; | ||
| 40 | clocks = <&clk32k>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | RAMC SDRAM/DDR Controller required properties: | 28 | RAMC SDRAM/DDR Controller required properties: |
| 44 | - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" | 29 | - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" |
| 45 | "atmel,at91sam9260-sdramc", | 30 | "atmel,at91sam9260-sdramc", |
| @@ -87,6 +87,13 @@ properties: · 86 unmodified lines | |||
| 87 | - const: brcm,bcm53012 | 87 | - const: brcm,bcm53012 |
| 88 | - const: brcm,bcm4708 | 88 | - const: brcm,bcm4708 |
| 89 | 89 | ||
| 90 | - description: BCM53015 based boards | ||
| 91 | items: | ||
| 92 | - enum: | ||
| 93 | - meraki,mr26 | ||
| 94 | - const: brcm,bcm53015 | ||
| 95 | - const: brcm,bcm4708 | ||
| 96 | |||
| 90 | - description: BCM53016 based boards | 97 | - description: BCM53016 based boards |
| 91 | items: | 98 | items: |
| 92 | - enum: | 99 | - enum: |
| @@ -28,6 +28,99 @@ properties: · 27 unmodified lines | |||
| 28 | - const: brcm,bcm47622 | 28 | - const: brcm,bcm47622 |
| 29 | - const: brcm,bcmbca | 29 | - const: brcm,bcmbca |
| 30 | 30 | ||
| 31 | - description: BCM4912 based boards | ||
| 32 | items: | ||
| 33 | - enum: | ||
| 34 | - asus,gt-ax6000 | ||
| 35 | - brcm,bcm94912 | ||
| 36 | - const: brcm,bcm4912 | ||
| 37 | - const: brcm,bcmbca | ||
| 38 | |||
| 39 | - description: BCM63138 based boards | ||
| 40 | items: | ||
| 41 | - enum: | ||
| 42 | - brcm,bcm963138 | ||
| 43 | - brcm,BCM963138DVT | ||
| 44 | - const: brcm,bcm63138 | ||
| 45 | - const: brcm,bcmbca | ||
| 46 | |||
| 47 | - description: BCM63146 based boards | ||
| 48 | items: | ||
| 49 | - enum: | ||
| 50 | - brcm,bcm963146 | ||
| 51 | - const: brcm,bcm63146 | ||
| 52 | - const: brcm,bcmbca | ||
| 53 | |||
| 54 | - description: BCM63148 based boards | ||
| 55 | items: | ||
| 56 | - enum: | ||
| 57 | - brcm,bcm963148 | ||
| 58 | - const: brcm,bcm63148 | ||
| 59 | - const: brcm,bcmbca | ||
| 60 | |||
| 61 | - description: BCM63158 based boards | ||
| 62 | items: | ||
| 63 | - enum: | ||
| 64 | - brcm,bcm963158 | ||
| 65 | - const: brcm,bcm63158 | ||
| 66 | - const: brcm,bcmbca | ||
| 67 | |||
| 68 | - description: BCM63178 based boards | ||
| 69 | items: | ||
| 70 | - enum: | ||
| 71 | - brcm,bcm963178 | ||
| 72 | - const: brcm,bcm63178 | ||
| 73 | - const: brcm,bcmbca | ||
| 74 | |||
| 75 | - description: BCM6756 based boards | ||
| 76 | items: | ||
| 77 | - enum: | ||
| 78 | - brcm,bcm96756 | ||
| 79 | - const: brcm,bcm6756 | ||
| 80 | - const: brcm,bcmbca | ||
| 81 | |||
| 82 | - description: BCM6813 based boards | ||
| 83 | items: | ||
| 84 | - enum: | ||
| 85 | - brcm,bcm96813 | ||
| 86 | - const: brcm,bcm6813 | ||
| 87 | - const: brcm,bcmbca | ||
| 88 | |||
| 89 | - description: BCM6846 based boards | ||
| 90 | items: | ||
| 91 | - enum: | ||
| 92 | - brcm,bcm96846 | ||
| 93 | - const: brcm,bcm6846 | ||
| 94 | - const: brcm,bcmbca | ||
| 95 | |||
| 96 | - description: BCM6855 based boards | ||
| 97 | items: | ||
| 98 | - enum: | ||
| 99 | - brcm,bcm96855 | ||
| 100 | - const: brcm,bcm6855 | ||
| 101 | - const: brcm,bcmbca | ||
| 102 | |||
| 103 | - description: BCM6856 based boards | ||
| 104 | items: | ||
| 105 | - enum: | ||
| 106 | - brcm,bcm96856 | ||
| 107 | - const: brcm,bcm6856 | ||
| 108 | - const: brcm,bcmbca | ||
| 109 | |||
| 110 | - description: BCM6858 based boards | ||
| 111 | items: | ||
| 112 | - enum: | ||
| 113 | - brcm,bcm96858 | ||
| 114 | - const: brcm,bcm6858 | ||
| 115 | - const: brcm,bcmbca | ||
| 116 | |||
| 117 | - description: BCM6878 based boards | ||
| 118 | items: | ||
| 119 | - enum: | ||
| 120 | - brcm,bcm96878 | ||
| 121 | - const: brcm,bcm6878 | ||
| 122 | - const: brcm,bcmbca | ||
| 123 | |||
| 31 | additionalProperties: true | 124 | additionalProperties: true |
| 32 | 125 | ||
| 33 | ... | 126 | ... |
| @@ -1,49 +0,0 @@ | |||
| 1 | * CoreSight CPU Debug Component: | ||
| 2 | |||
| 3 | CoreSight CPU debug component are compliant with the ARMv8 architecture | ||
| 4 | reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The | ||
| 5 | external debug module is mainly used for two modes: self-hosted debug and | ||
| 6 | external debug, and it can be accessed from mmio region from Coresight | ||
| 7 | and eventually the debug module connects with CPU for debugging. And the | ||
| 8 | debug module provides sample-based profiling extension, which can be used | ||
| 9 | to sample CPU program counter, secure state and exception level, etc; | ||
| 10 | usually every CPU has one dedicated debug module to be connected. | ||
| 11 | |||
| 12 | Required properties: | ||
| 13 | |||
| 14 | - compatible : should be "arm,coresight-cpu-debug"; supplemented with | ||
| 15 | "arm,primecell" since this driver is using the AMBA bus | ||
| 16 | interface. | ||
| 17 | |||
| 18 | - reg : physical base address and length of the register set. | ||
| 19 | |||
| 20 | - clocks : the clock associated to this component. | ||
| 21 | |||
| 22 | - clock-names : the name of the clock referenced by the code. Since we are | ||
| 23 | using the AMBA framework, the name of the clock providing | ||
| 24 | the interconnect should be "apb_pclk" and the clock is | ||
| 25 | mandatory. The interface between the debug logic and the | ||
| 26 | processor core is clocked by the internal CPU clock, so it | ||
| 27 | is enabled with CPU clock by default. | ||
| 28 | |||
| 29 | - cpu : the CPU phandle the debug module is affined to. Do not assume it | ||
| 30 | to default to CPU0 if omitted. | ||
| 31 | |||
| 32 | Optional properties: | ||
| 33 | |||
| 34 | - power-domains: a phandle to the debug power domain. We use "power-domains" | ||
| 35 | binding to turn on the debug logic if it has own dedicated | ||
| 36 | power domain and if necessary to use "cpuidle.off=1" or | ||
| 37 | "nohlt" in the kernel command line or sysfs node to | ||
| 38 | constrain idle states to ensure registers in the CPU power | ||
| 39 | domain are accessible. | ||
| 40 | |||
| 41 | Example: | ||
| 42 | |||
| 43 | debug@f6590000 { | ||
| 44 | compatible = "arm,coresight-cpu-debug","arm,primecell"; | ||
| 45 | reg = <0 0xf6590000 0 0x1000>; | ||
| 46 | clocks = <&sys_ctrl HI6220_DAPB_CLK>; | ||
| 47 | clock-names = "apb_pclk"; | ||
| 48 | cpu = <&cpu0>; | ||
| 49 | }; | ||
| @@ -1,402 +0,0 @@ | |||
| 1 | * CoreSight Components: | ||
| 2 | |||
| 3 | CoreSight components are compliant with the ARM CoreSight architecture | ||
| 4 | specification and can be connected in various topologies to suit a particular | ||
| 5 | SoCs tracing needs. These trace components can generally be classified as | ||
| 6 | sinks, links and sources. Trace data produced by one or more sources flows | ||
| 7 | through the intermediate links connecting the source to the currently selected | ||
| 8 | sink. Each CoreSight component device should use these properties to describe | ||
| 9 | its hardware characteristcs. | ||
| 10 | |||
| 11 | * Required properties for all components *except* non-configurable replicators | ||
| 12 | and non-configurable funnels: | ||
| 13 | |||
| 14 | * compatible: These have to be supplemented with "arm,primecell" as | ||
| 15 | drivers are using the AMBA bus interface. Possible values include: | ||
| 16 | - Embedded Trace Buffer (version 1.0): | ||
| 17 | "arm,coresight-etb10", "arm,primecell"; | ||
| 18 | |||
| 19 | - Trace Port Interface Unit: | ||
| 20 | "arm,coresight-tpiu", "arm,primecell"; | ||
| 21 | |||
| 22 | - Trace Memory Controller, used for Embedded Trace Buffer(ETB), | ||
| 23 | Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) | ||
| 24 | configuration. The configuration mode (ETB, ETF, ETR) is | ||
| 25 | discovered at boot time when the device is probed. | ||
| 26 | "arm,coresight-tmc", "arm,primecell"; | ||
| 27 | |||
| 28 | - Trace Programmable Funnel: | ||
| 29 | "arm,coresight-dynamic-funnel", "arm,primecell"; | ||
| 30 | "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For | ||
| 31 | backward compatibility and will be removed) | ||
| 32 | |||
| 33 | - Embedded Trace Macrocell (version 3.x) and | ||
| 34 | Program Flow Trace Macrocell: | ||
| 35 | "arm,coresight-etm3x", "arm,primecell"; | ||
| 36 | |||
| 37 | - Embedded Trace Macrocell (version 4.x), with memory mapped access. | ||
| 38 | "arm,coresight-etm4x", "arm,primecell"; | ||
| 39 | |||
| 40 | - Embedded Trace Macrocell (version 4.x), with system register access only. | ||
| 41 | "arm,coresight-etm4x-sysreg"; | ||
| 42 | |||
| 43 | - Coresight programmable Replicator : | ||
| 44 | "arm,coresight-dynamic-replicator", "arm,primecell"; | ||
| 45 | |||
| 46 | - System Trace Macrocell: | ||
| 47 | "arm,coresight-stm", "arm,primecell"; [1] | ||
| 48 | - Coresight Address Translation Unit (CATU) | ||
| 49 | "arm,coresight-catu", "arm,primecell"; | ||
| 50 | |||
| 51 | - Coresight Cross Trigger Interface (CTI): | ||
| 52 | "arm,coresight-cti", "arm,primecell"; | ||
| 53 | See coresight-cti.yaml for full CTI definitions. | ||
| 54 | |||
| 55 | * reg: physical base address and length of the register | ||
| 56 | set(s) of the component. | ||
| 57 | |||
| 58 | * clocks: the clocks associated to this component. | ||
| 59 | |||
| 60 | * clock-names: the name of the clocks referenced by the code. | ||
| 61 | Since we are using the AMBA framework, the name of the clock | ||
| 62 | providing the interconnect should be "apb_pclk", and some | ||
| 63 | coresight blocks also have an additional clock "atclk", which | ||
| 64 | clocks the core of that coresight component. The latter clock | ||
| 65 | is optional. | ||
| 66 | |||
| 67 | * port or ports: see "Graph bindings for Coresight" below. | ||
| 68 | |||
| 69 | * Additional required property for Embedded Trace Macrocell (version 3.x and | ||
| 70 | version 4.x): | ||
| 71 | * cpu: the cpu phandle this ETM/PTM is affined to. Do not | ||
| 72 | assume it to default to CPU0 if omitted. | ||
| 73 | |||
| 74 | * Additional required properties for System Trace Macrocells (STM): | ||
| 75 | * reg: along with the physical base address and length of the register | ||
| 76 | set as described above, another entry is required to describe the | ||
| 77 | mapping of the extended stimulus port area. | ||
| 78 | |||
| 79 | * reg-names: the only acceptable values are "stm-base" and | ||
| 80 | "stm-stimulus-base", each corresponding to the areas defined in "reg". | ||
| 81 | |||
| 82 | * Required properties for Coresight Cross Trigger Interface (CTI) | ||
| 83 | See coresight-cti.yaml for full CTI definitions. | ||
| 84 | |||
| 85 | * Required properties for devices that don't show up on the AMBA bus, such as | ||
| 86 | non-configurable replicators and non-configurable funnels: | ||
| 87 | |||
| 88 | * compatible: Currently supported value is (note the absence of the | ||
| 89 | AMBA markee): | ||
| 90 | - Coresight Non-configurable Replicator: | ||
| 91 | "arm,coresight-static-replicator"; | ||
| 92 | "arm,coresight-replicator"; (OBSOLETE. For backward | ||
| 93 | compatibility and will be removed) | ||
| 94 | |||
| 95 | - Coresight Non-configurable Funnel: | ||
| 96 | "arm,coresight-static-funnel"; | ||
| 97 | |||
| 98 | * port or ports: see "Graph bindings for Coresight" below. | ||
| 99 | |||
| 100 | * Optional properties for all components: | ||
| 101 | |||
| 102 | * arm,coresight-loses-context-with-cpu : boolean. Indicates that the | ||
| 103 | hardware will lose register context on CPU power down (e.g. CPUIdle). | ||
| 104 | An example of where this may be needed are systems which contain a | ||
| 105 | coresight component and CPU in the same power domain. When the CPU | ||
| 106 | powers down the coresight component also powers down and loses its | ||
| 107 | context. This property is currently only used for the ETM 4.x driver. | ||
| 108 | |||
| 109 | * Optional properties for ETM/PTMs: | ||
| 110 | |||
| 111 | * arm,cp14: must be present if the system accesses ETM/PTM management | ||
| 112 | registers via co-processor 14. | ||
| 113 | |||
| 114 | * qcom,skip-power-up: boolean. Indicates that an implementation can | ||
| 115 | skip powering up the trace unit. TRCPDCR.PU does not have to be set | ||
| 116 | on Qualcomm Technologies Inc. systems since ETMs are in the same power | ||
| 117 | domain as their CPU cores. This property is required to identify such | ||
| 118 | systems with hardware errata where the CPU watchdog counter is stopped | ||
| 119 | when TRCPDCR.PU is set. | ||
| 120 | |||
| 121 | * Optional property for TMC: | ||
| 122 | |||
| 123 | * arm,buffer-size: size of contiguous buffer space for TMC ETR | ||
| 124 | (embedded trace router). This property is obsolete. The buffer size | ||
| 125 | can be configured dynamically via buffer_size property in sysfs. | ||
| 126 | |||
| 127 | * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely | ||
| 128 | use the SG mode on this system. | ||
| 129 | |||
| 130 | * arm,max-burst-size: The maximum burst size initiated by TMC on the | ||
| 131 | AXI master interface. The burst size can be in the range [0..15], | ||
| 132 | the setting supports one data transfer per burst up to a maximum of | ||
| 133 | 16 data transfers per burst. | ||
| 134 | |||
| 135 | * Optional property for CATU : | ||
| 136 | * interrupts : Exactly one SPI may be listed for reporting the address | ||
| 137 | error | ||
| 138 | |||
| 139 | * Optional property for configurable replicators: | ||
| 140 | |||
| 141 | * qcom,replicator-loses-context: boolean. Indicates that the replicator | ||
| 142 | will lose register context when AMBA clock is removed which is observed | ||
| 143 | in some replicator designs. | ||
| 144 | |||
| 145 | Graph bindings for Coresight | ||
| 146 | ------------------------------- | ||
| 147 | |||
| 148 | Coresight components are interconnected to create a data path for the flow of | ||
| 149 | trace data generated from the "sources" to their collection points "sink". | ||
| 150 | Each coresight component must describe the "input" and "output" connections. | ||
| 151 | The connections must be described via generic DT graph bindings as described | ||
| 152 | by the "bindings/graph.txt", where each "port" along with an "endpoint" | ||
| 153 | component represents a hardware port and the connection. | ||
| 154 | |||
| 155 | * All output ports must be listed inside a child node named "out-ports" | ||
| 156 | * All input ports must be listed inside a child node named "in-ports". | ||
| 157 | * Port address must match the hardware port number. | ||
| 158 | |||
| 159 | Example: | ||
| 160 | |||
| 161 | 1. Sinks | ||
| 162 | etb@20010000 { | ||
| 163 | compatible = "arm,coresight-etb10", "arm,primecell"; | ||
| 164 | reg = <0 0x20010000 0 0x1000>; | ||
| 165 | |||
| 166 | clocks = <&oscclk6a>; | ||
| 167 | clock-names = "apb_pclk"; | ||
| 168 | in-ports { | ||
| 169 | port { | ||
| 170 | etb_in_port: endpoint@0 { | ||
| 171 | remote-endpoint = <&replicator_out_port0>; | ||
| 172 | }; | ||
| 173 | }; | ||
| 174 | }; | ||
| 175 | }; | ||
| 176 | |||
| 177 | tpiu@20030000 { | ||
| 178 | compatible = "arm,coresight-tpiu", "arm,primecell"; | ||
| 179 | reg = <0 0x20030000 0 0x1000>; | ||
| 180 | |||
| 181 | clocks = <&oscclk6a>; | ||
| 182 | clock-names = "apb_pclk"; | ||
| 183 | in-ports { | ||
| 184 | port { | ||
| 185 | tpiu_in_port: endpoint@0 { | ||
| 186 | remote-endpoint = <&replicator_out_port1>; | ||
| 187 | }; | ||
| 188 | }; | ||
| 189 | }; | ||
| 190 | }; | ||
| 191 | |||
| 192 | etr@20070000 { | ||
| 193 | compatible = "arm,coresight-tmc", "arm,primecell"; | ||
| 194 | reg = <0 0x20070000 0 0x1000>; | ||
| 195 | |||
| 196 | clocks = <&oscclk6a>; | ||
| 197 | clock-names = "apb_pclk"; | ||
| 198 | in-ports { | ||
| 199 | port { | ||
| 200 | etr_in_port: endpoint { | ||
| 201 | remote-endpoint = <&replicator2_out_port0>; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | }; | ||
| 205 | |||
| 206 | out-ports { | ||
| 207 | port { | ||
| 208 | etr_out_port: endpoint { | ||
| 209 | remote-endpoint = <&catu_in_port>; | ||
| 210 | }; | ||
| 211 | }; | ||
| 212 | }; | ||
| 213 | }; | ||
| 214 | |||
| 215 | 2. Links | ||
| 216 | replicator { | ||
| 217 | /* non-configurable replicators don't show up on the | ||
| 218 | * AMBA bus. As such no need to add "arm,primecell". | ||
| 219 | */ | ||
| 220 | compatible = "arm,coresight-static-replicator"; | ||
| 221 | |||
| 222 | out-ports { | ||
| 223 | #address-cells = <1>; | ||
| 224 | #size-cells = <0>; | ||
| 225 | |||
| 226 | /* replicator output ports */ | ||
| 227 | port@0 { | ||
| 228 | reg = <0>; | ||
| 229 | replicator_out_port0: endpoint { | ||
| 230 | remote-endpoint = <&etb_in_port>; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | port@1 { | ||
| 235 | reg = <1>; | ||
| 236 | replicator_out_port1: endpoint { | ||
| 237 | remote-endpoint = <&tpiu_in_port>; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | }; | ||
| 241 | |||
| 242 | in-ports { | ||
| 243 | port { | ||
| 244 | replicator_in_port0: endpoint { | ||
| 245 | remote-endpoint = <&funnel_out_port0>; | ||
| 246 | }; | ||
| 247 | }; | ||
| 248 | }; | ||
| 249 | }; | ||
| 250 | |||
| 251 | funnel { | ||
| 252 | /* | ||
| 253 | * non-configurable funnel don't show up on the AMBA | ||
| 254 | * bus. As such no need to add "arm,primecell". | ||
| 255 | */ | ||
| 256 | compatible = "arm,coresight-static-funnel"; | ||
| 257 | clocks = <&crg_ctrl HI3660_PCLK>; | ||
| 258 | clock-names = "apb_pclk"; | ||
| 259 | |||
| 260 | out-ports { | ||
| 261 | port { | ||
| 262 | combo_funnel_out: endpoint { | ||
| 263 | remote-endpoint = <&top_funnel_in>; | ||
| 264 | }; | ||
| 265 | }; | ||
| 266 | }; | ||
| 267 | |||
| 268 | in-ports { | ||
| 269 | #address-cells = <1>; | ||
| 270 | #size-cells = <0>; | ||
| 271 | |||
| 272 | port@0 { | ||
| 273 | reg = <0>; | ||
| 274 | combo_funnel_in0: endpoint { | ||
| 275 | remote-endpoint = <&cluster0_etf_out>; | ||
| 276 | }; | ||
| 277 | }; | ||
| 278 | |||
| 279 | port@1 { | ||
| 280 | reg = <1>; | ||
| 281 | combo_funnel_in1: endpoint { | ||
| 282 | remote-endpoint = <&cluster1_etf_out>; | ||
| 283 | }; | ||
| 284 | }; | ||
| 285 | }; | ||
| 286 | }; | ||
| 287 | |||
| 288 | funnel@20040000 { | ||
| 289 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | ||
| 290 | reg = <0 0x20040000 0 0x1000>; | ||
| 291 | |||
| 292 | clocks = <&oscclk6a>; | ||
| 293 | clock-names = "apb_pclk"; | ||
| 294 | out-ports { | ||
| 295 | port { | ||
| 296 | funnel_out_port0: endpoint { | ||
| 297 | remote-endpoint = | ||
| 298 | <&replicator_in_port0>; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | }; | ||
| 302 | |||
| 303 | in-ports { | ||
| 304 | #address-cells = <1>; | ||
| 305 | #size-cells = <0>; | ||
| 306 | |||
| 307 | port@0 { | ||
| 308 | reg = <0>; | ||
| 309 | funnel_in_port0: endpoint { | ||
| 310 | remote-endpoint = <&ptm0_out_port>; | ||
| 311 | }; | ||
| 312 | }; | ||
| 313 | |||
| 314 | port@1 { | ||
| 315 | reg = <1>; | ||
| 316 | funnel_in_port1: endpoint { | ||
| 317 | remote-endpoint = <&ptm1_out_port>; | ||
| 318 | }; | ||
| 319 | }; | ||
| 320 | |||
| 321 | port@2 { | ||
| 322 | reg = <2>; | ||
| 323 | funnel_in_port2: endpoint { | ||
| 324 | remote-endpoint = <&etm0_out_port>; | ||
| 325 | }; | ||
| 326 | }; | ||
| 327 | |||
| 328 | }; | ||
| 329 | }; | ||
| 330 | |||
| 331 | 3. Sources | ||
| 332 | ptm@2201c000 { | ||
| 333 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
| 334 | reg = <0 0x2201c000 0 0x1000>; | ||
| 335 | |||
| 336 | cpu = <&cpu0>; | ||
| 337 | clocks = <&oscclk6a>; | ||
| 338 | clock-names = "apb_pclk"; | ||
| 339 | out-ports { | ||
| 340 | port { | ||
| 341 | ptm0_out_port: endpoint { | ||
| 342 | remote-endpoint = <&funnel_in_port0>; | ||
| 343 | }; | ||
| 344 | }; | ||
| 345 | }; | ||
| 346 | }; | ||
| 347 | |||
| 348 | ptm@2201d000 { | ||
| 349 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
| 350 | reg = <0 0x2201d000 0 0x1000>; | ||
| 351 | |||
| 352 | cpu = <&cpu1>; | ||
| 353 | clocks = <&oscclk6a>; | ||
| 354 | clock-names = "apb_pclk"; | ||
| 355 | out-ports { | ||
| 356 | port { | ||
| 357 | ptm1_out_port: endpoint { | ||
| 358 | remote-endpoint = <&funnel_in_port1>; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | }; | ||
| 362 | }; | ||
| 363 | |||
| 364 | 4. STM | ||
| 365 | stm@20100000 { | ||
| 366 | compatible = "arm,coresight-stm", "arm,primecell"; | ||
| 367 | reg = <0 0x20100000 0 0x1000>, | ||
| 368 | <0 0x28000000 0 0x180000>; | ||
| 369 | reg-names = "stm-base", "stm-stimulus-base"; | ||
| 370 | |||
| 371 | clocks = <&soc_smc50mhz>; | ||
| 372 | clock-names = "apb_pclk"; | ||
| 373 | out-ports { | ||
| 374 | port { | ||
| 375 | stm_out_port: endpoint { | ||
| 376 | remote-endpoint = <&main_funnel_in_port2>; | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | }; | ||
| 380 | }; | ||
| 381 | |||
| 382 | 5. CATU | ||
| 383 | |||
| 384 | catu@207e0000 { | ||
| 385 | compatible = "arm,coresight-catu", "arm,primecell"; | ||
| 386 | reg = <0 0x207e0000 0 0x1000>; | ||
| 387 | |||
| 388 | clocks = <&oscclk6a>; | ||
| 389 | clock-names = "apb_pclk"; | ||
| 390 | |||
| 391 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | ||
| 392 | in-ports { | ||
| 393 | port { | ||
| 394 | catu_in_port: endpoint { | ||
| 395 | remote-endpoint = <&etr_out_port>; | ||
| 396 | }; | ||
| 397 | }; | ||
| 398 | }; | ||
| 399 | }; | ||
| 400 | |||
| 401 | [1]. There is currently two version of STM: STM32 and STM500. Both | ||
| 402 | have the same HW interface and as such don't need an explicit binding name. | ||
| @@ -138,6 +138,7 @@ properties: · 137 unmodified lines | |||
| 138 | - arm,cortex-a76 | 138 | - arm,cortex-a76 |
| 139 | - arm,cortex-a77 | 139 | - arm,cortex-a77 |
| 140 | - arm,cortex-a78 | 140 | - arm,cortex-a78 |
| 141 | - arm,cortex-a78ae | ||
| 141 | - arm,cortex-a510 | 142 | - arm,cortex-a510 |
| 142 | - arm,cortex-a710 | 143 | - arm,cortex-a710 |
| 143 | - arm,cortex-m0 | 144 | - arm,cortex-m0 |
| @@ -221,6 +222,7 @@ properties: · 77 unmodified lines | |||
| 221 | - qcom,kpss-acc-v1 | 222 | - qcom,kpss-acc-v1 |
| 222 | - qcom,kpss-acc-v2 | 223 | - qcom,kpss-acc-v2 |
| 223 | - qcom,msm8226-smp | 224 | - qcom,msm8226-smp |
| 225 | - qcom,msm8909-smp | ||
| 224 | # Only valid on ARM 32-bit, see above for ARM v8 64-bit | 226 | # Only valid on ARM 32-bit, see above for ARM v8 64-bit |
| 225 | - qcom,msm8916-smp | 227 | - qcom,msm8916-smp |
| 226 | - renesas,apmu | 228 | - renesas,apmu |
| @@ -1,271 +0,0 @@ | |||
| 1 | NXP i.MX System Controller Firmware (SCFW) | ||
| 2 | -------------------------------------------------------------------- | ||
| 3 | |||
| 4 | The System Controller Firmware (SCFW) is a low-level system function | ||
| 5 | which runs on a dedicated Cortex-M core to provide power, clock, and | ||
| 6 | resource management. It exists on some i.MX8 processors. e.g. i.MX8QM | ||
| 7 | (QM, QP), and i.MX8QX (QXP, DX). | ||
| 8 | |||
| 9 | The AP communicates with the SC using a multi-ported MU module found | ||
| 10 | in the LSIO subsystem. The current definition of this MU module provides | ||
| 11 | 5 remote AP connections to the SC to support up to 5 execution environments | ||
| 12 | (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces | ||
| 13 | with the LSIO DSC IP bus. The SC firmware will communicate with this MU | ||
| 14 | using the MSI bus. | ||
| 15 | |||
| 16 | System Controller Device Node: | ||
| 17 | ============================================================ | ||
| 18 | |||
| 19 | The scu node with the following properties shall be under the /firmware/ node. | ||
| 20 | |||
| 21 | Required properties: | ||
| 22 | ------------------- | ||
| 23 | - compatible: should be "fsl,imx-scu". | ||
| 24 | - mbox-names: should include "tx0", "tx1", "tx2", "tx3", | ||
| 25 | "rx0", "rx1", "rx2", "rx3"; | ||
| 26 | include "gip3" if want to support general MU interrupt. | ||
| 27 | - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for | ||
| 28 | rx, and 1 optional MU channel for general interrupt. | ||
| 29 | All MU channels must be in the same MU instance. | ||
| 30 | Cross instances are not allowed. The MU instance can only | ||
| 31 | be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need | ||
| 32 | to make sure use the one which is not conflict with other | ||
| 33 | execution environments. e.g. ATF. | ||
| 34 | Note: | ||
| 35 | Channel 0 must be "tx0" or "rx0". | ||
| 36 | Channel 1 must be "tx1" or "rx1". | ||
| 37 | Channel 2 must be "tx2" or "rx2". | ||
| 38 | Channel 3 must be "tx3" or "rx3". | ||
| 39 | General interrupt rx channel must be "gip3". | ||
| 40 | e.g. | ||
| 41 | mboxes = <&lsio_mu1 0 0 | ||
| 42 | &lsio_mu1 0 1 | ||
| 43 | &lsio_mu1 0 2 | ||
| 44 | &lsio_mu1 0 3 | ||
| 45 | &lsio_mu1 1 0 | ||
| 46 | &lsio_mu1 1 1 | ||
| 47 | &lsio_mu1 1 2 | ||
| 48 | &lsio_mu1 1 3 | ||
| 49 | &lsio_mu1 3 3>; | ||
| 50 | See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | ||
| 51 | for detailed mailbox binding. | ||
| 52 | |||
| 53 | Note: Each mu which supports general interrupt should have an alias correctly | ||
| 54 | numbered in "aliases" node. | ||
| 55 | e.g. | ||
| 56 | aliases { | ||
| 57 | mu1 = &lsio_mu1; | ||
| 58 | }; | ||
| 59 | |||
| 60 | i.MX SCU Client Device Node: | ||
| 61 | ============================================================ | ||
| 62 | |||
| 63 | Client nodes are maintained as children of the relevant IMX-SCU device node. | ||
| 64 | |||
| 65 | Power domain bindings based on SCU Message Protocol | ||
| 66 | ------------------------------------------------------------ | ||
| 67 | |||
| 68 | This binding for the SCU power domain providers uses the generic power | ||
| 69 | domain binding[2]. | ||
| 70 | |||
| 71 | Required properties: | ||
| 72 | - compatible: Should be one of: | ||
| 73 | "fsl,imx8qm-scu-pd", | ||
| 74 | "fsl,imx8qxp-scu-pd" | ||
| 75 | followed by "fsl,scu-pd" | ||
| 76 | |||
| 77 | - #power-domain-cells: Must be 1. Contains the Resource ID used by | ||
| 78 | SCU commands. | ||
| 79 | See detailed Resource ID list from: | ||
| 80 | include/dt-bindings/firmware/imx/rsrc.h | ||
| 81 | |||
| 82 | Clock bindings based on SCU Message Protocol | ||
| 83 | ------------------------------------------------------------ | ||
| 84 | |||
| 85 | This binding uses the common clock binding[1]. | ||
| 86 | |||
| 87 | Required properties: | ||
| 88 | - compatible: Should be one of: | ||
| 89 | "fsl,imx8dxl-clk" | ||
| 90 | "fsl,imx8qm-clk" | ||
| 91 | "fsl,imx8qxp-clk" | ||
| 92 | followed by "fsl,scu-clk" | ||
| 93 | - #clock-cells: Should be 2. | ||
| 94 | Contains the Resource and Clock ID value. | ||
| 95 | - clocks: List of clock specifiers, must contain an entry for | ||
| 96 | each required entry in clock-names | ||
| 97 | - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" | ||
| 98 | |||
| 99 | The clock consumer should specify the desired clock by having the clock | ||
| 100 | ID in its "clocks" phandle cell. | ||
| 101 | |||
| 102 | See the full list of clock IDs from: | ||
| 103 | include/dt-bindings/clock/imx8qxp-clock.h | ||
| 104 | |||
| 105 | Pinctrl bindings based on SCU Message Protocol | ||
| 106 | ------------------------------------------------------------ | ||
| 107 | |||
| 108 | This binding uses the i.MX common pinctrl binding[3]. | ||
| 109 | |||
| 110 | Required properties: | ||
| 111 | - compatible: Should be one of: | ||
| 112 | "fsl,imx8qm-iomuxc", | ||
| 113 | "fsl,imx8qxp-iomuxc", | ||
| 114 | "fsl,imx8dxl-iomuxc". | ||
| 115 | |||
| 116 | Required properties for Pinctrl sub nodes: | ||
| 117 | - fsl,pins: Each entry consists of 3 integers which represents | ||
| 118 | the mux and config setting for one pin. The first 2 | ||
| 119 | integers <pin_id mux_mode> are specified using a | ||
| 120 | PIN_FUNC_ID macro, which can be found in | ||
| 121 | <dt-bindings/pinctrl/pads-imx8qm.h>, | ||
| 122 | <dt-bindings/pinctrl/pads-imx8qxp.h>, | ||
| 123 | <dt-bindings/pinctrl/pads-imx8dxl.h>. | ||
| 124 | The last integer CONFIG is the pad setting value like | ||
| 125 | pull-up on this pin. | ||
| 126 | |||
| 127 | Please refer to i.MX8QXP Reference Manual for detailed | ||
| 128 | CONFIG settings. | ||
| 129 | |||
| 130 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
| 131 | [2] Documentation/devicetree/bindings/power/power-domain.yaml | ||
| 132 | [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | ||
| 133 | |||
| 134 | RTC bindings based on SCU Message Protocol | ||
| 135 | ------------------------------------------------------------ | ||
| 136 | |||
| 137 | Required properties: | ||
| 138 | - compatible: should be "fsl,imx8qxp-sc-rtc"; | ||
| 139 | |||
| 140 | OCOTP bindings based on SCU Message Protocol | ||
| 141 | ------------------------------------------------------------ | ||
| 142 | Required properties: | ||
| 143 | - compatible: Should be one of: | ||
| 144 | "fsl,imx8qm-scu-ocotp", | ||
| 145 | "fsl,imx8qxp-scu-ocotp". | ||
| 146 | - #address-cells: Must be 1. Contains byte index | ||
| 147 | - #size-cells: Must be 1. Contains byte length | ||
| 148 | |||
| 149 | Optional Child nodes: | ||
| 150 | |||
| 151 | - Data cells of ocotp: | ||
| 152 | Detailed bindings are described in bindings/nvmem/nvmem.txt | ||
| 153 | |||
| 154 | Watchdog bindings based on SCU Message Protocol | ||
| 155 | ------------------------------------------------------------ | ||
| 156 | |||
| 157 | Required properties: | ||
| 158 | - compatible: should be: | ||
| 159 | "fsl,imx8qxp-sc-wdt" | ||
| 160 | followed by "fsl,imx-sc-wdt"; | ||
| 161 | Optional properties: | ||
| 162 | - timeout-sec: contains the watchdog timeout in seconds. | ||
| 163 | |||
| 164 | SCU key bindings based on SCU Message Protocol | ||
| 165 | ------------------------------------------------------------ | ||
| 166 | |||
| 167 | Required properties: | ||
| 168 | - compatible: should be: | ||
| 169 | "fsl,imx8qxp-sc-key" | ||
| 170 | followed by "fsl,imx-sc-key"; | ||
| 171 | - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml | ||
| 172 | |||
| 173 | Thermal bindings based on SCU Message Protocol | ||
| 174 | ------------------------------------------------------------ | ||
| 175 | |||
| 176 | Required properties: | ||
| 177 | - compatible: Should be : | ||
| 178 | "fsl,imx8qxp-sc-thermal" | ||
| 179 | followed by "fsl,imx-sc-thermal"; | ||
| 180 | |||
| 181 | - #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml | ||
| 182 | for a description. | ||
| 183 | |||
| 184 | Example (imx8qxp): | ||
| 185 | ------------- | ||
| 186 | aliases { | ||
| 187 | mu1 = &lsio_mu1; | ||
| 188 | }; | ||
| 189 | |||
| 190 | lsio_mu1: mailbox@5d1c0000 { | ||
| 191 | ... | ||
| 192 | #mbox-cells = <2>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | firmware { | ||
| 196 | scu { | ||
| 197 | compatible = "fsl,imx-scu"; | ||
| 198 | mbox-names = "tx0", "tx1", "tx2", "tx3", | ||
| 199 | "rx0", "rx1", "rx2", "rx3", | ||
| 200 | "gip3"; | ||
| 201 | mboxes = <&lsio_mu1 0 0 | ||
| 202 | &lsio_mu1 0 1 | ||
| 203 | &lsio_mu1 0 2 | ||
| 204 | &lsio_mu1 0 3 | ||
| 205 | &lsio_mu1 1 0 | ||
| 206 | &lsio_mu1 1 1 | ||
| 207 | &lsio_mu1 1 2 | ||
| 208 | &lsio_mu1 1 3 | ||
| 209 | &lsio_mu1 3 3>; | ||
| 210 | |||
| 211 | clk: clk { | ||
| 212 | compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; | ||
| 213 | #clock-cells = <2>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | iomuxc { | ||
| 217 | compatible = "fsl,imx8qxp-iomuxc"; | ||
| 218 | |||
| 219 | pinctrl_lpuart0: lpuart0grp { | ||
| 220 | fsl,pins = < | ||
| 221 | SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 | ||
| 222 | SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 | ||
| 223 | >; | ||
| 224 | }; | ||
| 225 | ... | ||
| 226 | }; | ||
| 227 | |||
| 228 | ocotp: imx8qx-ocotp { | ||
| 229 | compatible = "fsl,imx8qxp-scu-ocotp"; | ||
| 230 | #address-cells = <1>; | ||
| 231 | #size-cells = <1>; | ||
| 232 | |||
| 233 | fec_mac0: mac@2c4 { | ||
| 234 | reg = <0x2c4 8>; | ||
| 235 | }; | ||
| 236 | }; | ||
| 237 | |||
| 238 | pd: imx8qx-pd { | ||
| 239 | compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; | ||
| 240 | #power-domain-cells = <1>; | ||
| 241 | }; | ||
| 242 | |||
| 243 | rtc: rtc { | ||
| 244 | compatible = "fsl,imx8qxp-sc-rtc"; | ||
| 245 | }; | ||
| 246 | |||
| 247 | scu_key: scu-key { | ||
| 248 | compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; | ||
| 249 | linux,keycodes = <KEY_POWER>; | ||
| 250 | }; | ||
| 251 | |||
| 252 | watchdog { | ||
| 253 | compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; | ||
| 254 | timeout-sec = <60>; | ||
| 255 | }; | ||
| 256 | |||
| 257 | tsens: thermal-sensor { | ||
| 258 | compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; | ||
| 259 | #thermal-sensor-cells = <1>; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | }; | ||
| 263 | |||
| 264 | serial@5a060000 { | ||
| 265 | ... | ||
| 266 | pinctrl-names = "default"; | ||
| 267 | pinctrl-0 = <&pinctrl_lpuart0>; | ||
| 268 | clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; | ||
| 269 | clock-names = "ipg"; | ||
| 270 | power-domains = <&pd IMX_SC_R_UART_0>; | ||
| 271 | }; | ||
| @@ -321,6 +321,7 @@ properties: · 320 unmodified lines | |||
| 321 | - enum: | 321 | - enum: |
| 322 | - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board | 322 | - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board |
| 323 | - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board | 323 | - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board |
| 324 | - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board | ||
| 324 | - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board | 325 | - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board |
| 325 | - const: toradex,apalis_imx6q | 326 | - const: toradex,apalis_imx6q |
| 326 | - const: fsl,imx6q | 327 | - const: fsl,imx6q |
| @@ -670,30 +671,30 @@ properties: · 343 unmodified lines | |||
| 670 | - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules | 671 | - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules |
| 671 | items: | 672 | items: |
| 672 | - enum: | 673 | - enum: |
| 673 | - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board | 674 | - toradex,colibri-imx6ull-aster # Aster Carrier Board |
| 674 | - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3 | 675 | - toradex,colibri-imx6ull-eval # Colibri Evaluation Board V3 |
| 675 | - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board | 676 | - toradex,colibri-imx6ull-iris # Iris Carrier Board |
| 676 | - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board | 677 | - toradex,colibri-imx6ull-iris-v2 # Iris V2 Carrier Board |
| 677 | - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module | 678 | - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module |
| 678 | - const: fsl,imx6ull | 679 | - const: fsl,imx6ull |
| 679 | 680 | ||
| 680 | - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module | 681 | - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module |
| 681 | items: | 682 | items: |
| 682 | - enum: | 683 | - enum: |
| 683 | - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board | 684 | - toradex,colibri-imx6ull-emmc-aster # Aster Carrier Board |
| 684 | - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3 | 685 | - toradex,colibri-imx6ull-emmc-eval # Colibri Evaluation B. V3 |
| 685 | - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board | 686 | - toradex,colibri-imx6ull-emmc-iris # Iris Carrier Board |
| 686 | - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board | 687 | - toradex,colibri-imx6ull-emmc-iris-v2 # Iris V2 Carrier Board |
| 687 | - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module | 688 | - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module |
| 688 | - const: fsl,imx6ull | 689 | - const: fsl,imx6ull |
| 689 | 690 | ||
| 690 | - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules | 691 | - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules |
| 691 | items: | 692 | items: |
| 692 | - enum: | 693 | - enum: |
| 693 | - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3 | 694 | - toradex,colibri-imx6ull-wifi-eval # Colibri Eval. B. V3 |
| 694 | - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board | 695 | - toradex,colibri-imx6ull-wifi-aster # Aster Carrier Board |
| 695 | - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board | 696 | - toradex,colibri-imx6ull-wifi-iris # Iris Carrier Board |
| 696 | - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board | 697 | - toradex,colibri-imx6ull-wifi-iris-v2 # Iris V2 Carrier Board |
| 697 | - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module | 698 | - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module |
| 698 | - const: fsl,imx6ull | 699 | - const: fsl,imx6ull |
| 699 | 700 | ||
| @@ -738,6 +739,8 @@ properties: · 38 unmodified lines | |||
| 738 | - enum: | 739 | - enum: |
| 739 | - toradex,colibri-imx7s-aster # Module on Aster Carrier Board | 740 | - toradex,colibri-imx7s-aster # Module on Aster Carrier Board |
| 740 | - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3 | 741 | - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3 |
| 742 | - toradex,colibri-imx7s-iris # Module on Iris Carrier Board | ||
| 743 | - toradex,colibri-imx7s-iris-v2 # Module on Iris Carrier Board V2 | ||
| 741 | - const: toradex,colibri-imx7s | 744 | - const: toradex,colibri-imx7s |
| 742 | - const: fsl,imx7s | 745 | - const: fsl,imx7s |
| 743 | 746 | ||
| @@ -789,8 +792,10 @@ properties: · 45 unmodified lines | |||
| 789 | - description: i.MX7D Boards with Toradex Colibri i.MX7D Module | 792 | - description: i.MX7D Boards with Toradex Colibri i.MX7D Module |
| 790 | items: | 793 | items: |
| 791 | - enum: | 794 | - enum: |
| 792 | - toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board | 795 | - toradex,colibri-imx7d-aster # Aster Carrier Board |
| 793 | - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3 | 796 | - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3 |
| 797 | - toradex,colibri-imx7d-iris # Iris Carrier Board | ||
| 798 | - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2 | ||
| 794 | - const: toradex,colibri-imx7d | 799 | - const: toradex,colibri-imx7d |
| 795 | - const: fsl,imx7d | 800 | - const: fsl,imx7d |
| 796 | 801 | ||
| @@ -799,6 +804,8 @@ properties: · 2 unmodified lines | |||
| 799 | - enum: | 804 | - enum: |
| 800 | - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board | 805 | - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board |
| 801 | - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3 | 806 | - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3 |
| 807 | - toradex,colibri-imx7d-emmc-iris # Module on Iris Carrier Board | ||
| 808 | - toradex,colibri-imx7d-emmc-iris-v2 # Module on Iris Carrier Board V2 | ||
| 802 | - const: toradex,colibri-imx7d-emmc | 809 | - const: toradex,colibri-imx7d-emmc |
| 803 | - const: fsl,imx7d | 810 | - const: fsl,imx7d |
| 804 | 811 | ||
| @@ -865,6 +872,12 @@ properties: · 60 unmodified lines | |||
| 865 | - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module | 872 | - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module |
| 866 | - const: fsl,imx8mm | 873 | - const: fsl,imx8mm |
| 867 | 874 | ||
| 875 | - description: PHYTEC phyCORE-i.MX8MM SoM based boards | ||
| 876 | items: | ||
| 877 | - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK | ||
| 878 | - const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM | ||
| 879 | - const: fsl,imx8mm | ||
| 880 | |||
| 868 | - description: Variscite VAR-SOM-MX8MM based boards | 881 | - description: Variscite VAR-SOM-MX8MM based boards |
| 869 | items: | 882 | items: |
| 870 | - const: variscite,var-som-mx8mm-symphony | 883 | - const: variscite,var-som-mx8mm-symphony |
| @@ -914,6 +927,8 @@ properties: · 43 unmodified lines | |||
| 914 | - description: i.MX8MP based Boards | 927 | - description: i.MX8MP based Boards |
| 915 | items: | 928 | items: |
| 916 | - enum: | 929 | - enum: |
| 930 | - dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM | ||
| 931 | - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board | ||
| 917 | - fsl,imx8mp-evk # i.MX8MP EVK Board | 932 | - fsl,imx8mp-evk # i.MX8MP EVK Board |
| 918 | - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board | 933 | - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board |
| 919 | - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules | 934 | - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules |
| @@ -952,6 +967,18 @@ properties: · 32 unmodified lines | |||
| 952 | - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module | 967 | - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module |
| 953 | - const: fsl,imx8mp | 968 | - const: fsl,imx8mp |
| 954 | 969 | ||
| 970 | - description: | ||
| 971 | TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip | ||
| 972 | variants. It is designed to be soldered on different carrier boards. | ||
| 973 | All CPU variants use the same device tree hence only one compatible | ||
| 974 | is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed | ||
| 975 | version as an industrial computing device. | ||
| 976 | items: | ||
| 977 | - enum: | ||
| 978 | - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL | ||
| 979 | - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM | ||
| 980 | - const: fsl,imx8mp | ||
| 981 | |||
| 955 | - description: i.MX8MQ based Boards | 982 | - description: i.MX8MQ based Boards |
| 956 | items: | 983 | items: |
| 957 | - enum: | 984 | - enum: |
| @@ -1020,6 +1047,12 @@ properties: · 62 unmodified lines | |||
| 1020 | - fsl,imx8ulp-evk # i.MX8ULP EVK Board | 1047 | - fsl,imx8ulp-evk # i.MX8ULP EVK Board |
| 1021 | - const: fsl,imx8ulp | 1048 | - const: fsl,imx8ulp |
| 1022 | 1049 | ||
| 1050 | - description: i.MX93 based Boards | ||
| 1051 | items: | ||
| 1052 | - enum: | ||
| 1053 | - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board | ||
| 1054 | - const: fsl,imx93 | ||
| 1055 | |||
| 1023 | - description: | 1056 | - description: |
| 1024 | Freescale Vybrid Platform Device Tree Bindings | 1057 | Freescale Vybrid Platform Device Tree Bindings |
| 1025 | 1058 | ||
| @@ -72,7 +72,7 @@ mpp19 19 gpio, uart0(rxd), sdio(pw_off) · 71 unmodified lines | |||
| 72 | GPIO: | 72 | GPIO: |
| 73 | ----- | 73 | ----- |
| 74 | For common binding part and usage, refer to | 74 | For common binding part and usage, refer to |
| 75 | Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. | 75 | Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml. |
| 76 | 76 | ||
| 77 | Required properties: | 77 | Required properties: |
| 78 | 78 | ||
| @@ -156,7 +156,7 @@ GPIO: · 155 unmodified lines | |||
| 156 | ----- | 156 | ----- |
| 157 | 157 | ||
| 158 | For common binding part and usage, refer to | 158 | For common binding part and usage, refer to |
| 159 | Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. | 159 | Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml. |
| 160 | 160 | ||
| 161 | Required properties: | 161 | Required properties: |
| 162 | 162 | ||
| @@ -0,0 +1,32 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Marvell Alleycat5/5X Platforms | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Chris Packham <chris.packham@alliedtelesis.co.nz> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | $nodename: | ||
| 14 | const: '/' | ||
| 15 | compatible: | ||
| 16 | oneOf: | ||
| 17 | - description: Alleycat5 (98DX25xx) Reference Design | ||
| 18 | items: | ||
| 19 | - enum: | ||
| 20 | - marvell,rd-ac5 | ||
| 21 | - const: marvell,ac5 | ||
| 22 | |||
| 23 | - description: Alleycat5X (98DX35xx) Reference Design | ||
| 24 | items: | ||
| 25 | - enum: | ||
| 26 | - marvell,rd-ac5x | ||
| 27 | - const: marvell,ac5x | ||
| 28 | - const: marvell,ac5 | ||
| 29 | |||
| 30 | additionalProperties: true | ||
| 31 | |||
| 32 | ... | ||
| @@ -131,6 +131,36 @@ properties: · 130 unmodified lines | |||
| 131 | - enum: | 131 | - enum: |
| 132 | - mediatek,mt8183-evb | 132 | - mediatek,mt8183-evb |
| 133 | - const: mediatek,mt8183 | 133 | - const: mediatek,mt8183 |
| 134 | - description: Google Hayato | ||
| 135 | items: | ||
| 136 | - const: google,hayato-rev1 | ||
| 137 | - const: google,hayato | ||
| 138 | - const: mediatek,mt8192 | ||
| 139 | - description: Google Spherion (Acer Chromebook 514) | ||
| 140 | items: | ||
| 141 | - const: google,spherion-rev3 | ||
| 142 | - const: google,spherion-rev2 | ||
| 143 | - const: google,spherion-rev1 | ||
| 144 | - const: google,spherion-rev0 | ||
| 145 | - const: google,spherion | ||
| 146 | - const: mediatek,mt8192 | ||
| 147 | - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) | ||
| 148 | items: | ||
| 149 | - enum: | ||
| 150 | - google,tomato-rev2 | ||
| 151 | - google,tomato-rev1 | ||
| 152 | - const: google,tomato | ||
| 153 | - const: mediatek,mt8195 | ||
| 154 | - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) | ||
| 155 | items: | ||
| 156 | - const: google,tomato-rev4 | ||
| 157 | - const: google,tomato-rev3 | ||
| 158 | - const: google,tomato | ||
| 159 | - const: mediatek,mt8195 | ||
| 160 | - items: | ||
| 161 | - enum: | ||
| 162 | - mediatek,mt8186-evb | ||
| 163 | - const: mediatek,mt8186 | ||
| 134 | - items: | 164 | - items: |
| 135 | - enum: | 165 | - enum: |
| 136 | - mediatek,mt8192-evb | 166 | - mediatek,mt8192-evb |
| @@ -39,6 +39,9 @@ properties: · 38 unmodified lines | |||
| 39 | '#clock-cells': | 39 | '#clock-cells': |
| 40 | const: 1 | 40 | const: 1 |
| 41 | 41 | ||
| 42 | '#reset-cells': | ||
| 43 | const: 1 | ||
| 44 | |||
| 42 | required: | 45 | required: |
| 43 | - compatible | 46 | - compatible |
| 44 | - reg | 47 | - reg |
| @@ -24,7 +24,6 @@ properties: · 23 unmodified lines | |||
| 24 | - mediatek,mt8192-imp_iic_wrap_w | 24 | - mediatek,mt8192-imp_iic_wrap_w |
| 25 | - mediatek,mt8192-imp_iic_wrap_n | 25 | - mediatek,mt8192-imp_iic_wrap_n |
| 26 | - mediatek,mt8192-msdc_top | 26 | - mediatek,mt8192-msdc_top |
| 27 | - mediatek,mt8192-msdc | ||
| 28 | - mediatek,mt8192-mfgcfg | 27 | - mediatek,mt8192-mfgcfg |
| 29 | - mediatek,mt8192-imgsys | 28 | - mediatek,mt8192-imgsys |
| 30 | - mediatek,mt8192-imgsys2 | 29 | - mediatek,mt8192-imgsys2 |
| @@ -107,13 +106,6 @@ examples: · 76 unmodified lines | |||
| 107 | #clock-cells = <1>; | 106 | #clock-cells = <1>; |
| 108 | }; | 107 | }; |
| 109 | 108 | ||
| 110 | - | | ||
| 111 | msdc: clock-controller@11f60000 { | ||
| 112 | compatible = "mediatek,mt8192-msdc"; | ||
| 113 | reg = <0x11f60000 0x1000>; | ||
| 114 | #clock-cells = <1>; | ||
| 115 | }; | ||
| 116 | |||
| 117 | - | | 109 | - | |
| 118 | mfgcfg: clock-controller@13fbf000 { | 110 | mfgcfg: clock-controller@13fbf000 { |
| 119 | compatible = "mediatek,mt8192-mfgcfg"; | 111 | compatible = "mediatek,mt8192-mfgcfg"; |
| @@ -29,6 +29,9 @@ properties: · 28 unmodified lines | |||
| 29 | '#clock-cells': | 29 | '#clock-cells': |
| 30 | const: 1 | 30 | const: 1 |
| 31 | 31 | ||
| 32 | '#reset-cells': | ||
| 33 | const: 1 | ||
| 34 | |||
| 32 | required: | 35 | required: |
| 33 | - compatible | 36 | - compatible |
| 34 | - reg | 37 | - reg |
| @@ -37,6 +37,9 @@ properties: · 36 unmodified lines | |||
| 37 | '#clock-cells': | 37 | '#clock-cells': |
| 38 | const: 1 | 38 | const: 1 |
| 39 | 39 | ||
| 40 | '#reset-cells': | ||
| 41 | const: 1 | ||
| 42 | |||
| 40 | required: | 43 | required: |
| 41 | - compatible | 44 | - compatible |
| 42 | - reg | 45 | - reg |
| @@ -26,6 +26,7 @@ properties: · 25 unmodified lines | |||
| 26 | - mediatek,mt8135-pericfg | 26 | - mediatek,mt8135-pericfg |
| 27 | - mediatek,mt8173-pericfg | 27 | - mediatek,mt8173-pericfg |
| 28 | - mediatek,mt8183-pericfg | 28 | - mediatek,mt8183-pericfg |
| 29 | - mediatek,mt8186-pericfg | ||
| 29 | - mediatek,mt8195-pericfg | 30 | - mediatek,mt8195-pericfg |
| 30 | - mediatek,mt8516-pericfg | 31 | - mediatek,mt8516-pericfg |
| 31 | - const: syscon | 32 | - const: syscon |
| @@ -10,7 +10,7 @@ system, notifying them when a low power state is entered or exited. · 9 unmodified lines | |||
| 10 | Multiple revisions of the SAW hardware are supported using these Device Nodes. | 10 | Multiple revisions of the SAW hardware are supported using these Device Nodes. |
| 11 | SAW2 revisions differ in the register offset and configuration data. Also, the | 11 | SAW2 revisions differ in the register offset and configuration data. Also, the |
| 12 | same revision of the SAW in different SoCs may have different configuration | 12 | same revision of the SAW in different SoCs may have different configuration |
| 13 | data due the the differences in hardware capabilities. Hence the SoC name, the | 13 | data due the differences in hardware capabilities. Hence the SoC name, the |
| 14 | version of the SAW hardware in that SoC and the distinction between cpu (big | 14 | version of the SAW hardware in that SoC and the distinction between cpu (big |
| 15 | or Little) or cache, may be needed to uniquely identify the SAW register | 15 | or Little) or cache, may be needed to uniquely identify the SAW register |
| 16 | configuration and initialization data. The compatible string is used to | 16 | configuration and initialization data. The compatible string is used to |
| @@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 10 | - Jonathan Neuschäfer <j.neuschaefer@gmx.net> |
| 11 | - Tomer Maimon <tmaimon77@gmail.com> | ||
| 11 | 12 | ||
| 12 | properties: | 13 | properties: |
| 13 | $nodename: | 14 | $nodename: |
| @@ -26,4 +27,10 @@ properties: · 12 unmodified lines | |||
| 26 | - nuvoton,npcm750-evb # NPCM750 evaluation board | 27 | - nuvoton,npcm750-evb # NPCM750 evaluation board |
| 27 | - const: nuvoton,npcm750 | 28 | - const: nuvoton,npcm750 |
| 28 | 29 | ||
| 30 | - description: NPCM845 based boards | ||
| 31 | items: | ||
| 32 | - enum: | ||
| 33 | - nuvoton,npcm845-evb # NPCM845 evaluation board | ||
| 34 | - const: nuvoton,npcm845 | ||
| 35 | |||
| 29 | additionalProperties: true | 36 | additionalProperties: true |
| @@ -8,6 +8,7 @@ title: Global Control Registers block in Nuvoton SoCs · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 10 | - Jonathan Neuschäfer <j.neuschaefer@gmx.net> |
| 11 | - Tomer Maimon <tmaimon77@gmail.com> | ||
| 11 | 12 | ||
| 12 | description: | 13 | description: |
| 13 | The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs | 14 | The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs |
| @@ -20,6 +21,7 @@ properties: · 6 unmodified lines | |||
| 20 | - enum: | 21 | - enum: |
| 21 | - nuvoton,wpcm450-gcr | 22 | - nuvoton,wpcm450-gcr |
| 22 | - nuvoton,npcm750-gcr | 23 | - nuvoton,npcm750-gcr |
| 24 | - nuvoton,npcm845-gcr | ||
| 23 | - const: syscon | 25 | - const: syscon |
| 24 | - const: simple-mfd | 26 | - const: simple-mfd |
| 25 | 27 | ||
| @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: QCOM device tree bindings | 7 | title: QCOM device tree bindings |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Stephen Boyd <sboyd@codeaurora.org> | 10 | - Bjorn Andersson <bjorn.andersson@linaro.org> |
| 11 | 11 | ||
| 12 | description: | | 12 | description: | |
| 13 | Some qcom based bootloaders identify the dtb blob based on a set of | 13 | Some qcom based bootloaders identify the dtb blob based on a set of |
| @@ -38,18 +38,24 @@ description: | · 24 unmodified lines | |||
| 38 | msm8992 | 38 | msm8992 |
| 39 | msm8994 | 39 | msm8994 |
| 40 | msm8996 | 40 | msm8996 |
| 41 | msm8998 | ||
| 42 | qcs404 | ||
| 41 | sa8155p | 43 | sa8155p |
| 42 | sa8540p | 44 | sa8540p |
| 43 | sc7180 | 45 | sc7180 |
| 44 | sc7280 | 46 | sc7280 |
| 45 | sc8180x | 47 | sc8180x |
| 46 | sc8280xp | 48 | sc8280xp |
| 49 | sda660 | ||
| 47 | sdm630 | 50 | sdm630 |
| 48 | sdm632 | 51 | sdm632 |
| 52 | sdm636 | ||
| 49 | sdm660 | 53 | sdm660 |
| 50 | sdm845 | 54 | sdm845 |
| 51 | sdx55 | 55 | sdx55 |
| 52 | sdx65 | 56 | sdx65 |
| 57 | sm6125 | ||
| 58 | sm6350 | ||
| 53 | sm7225 | 59 | sm7225 |
| 54 | sm8150 | 60 | sm8150 |
| 55 | sm8250 | 61 | sm8250 |
| @@ -90,6 +96,11 @@ description: | · 34 unmodified lines | |||
| 90 | A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in | 96 | A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in |
| 91 | foundry 2. | 97 | foundry 2. |
| 92 | 98 | ||
| 99 | There are many devices in the list below that run the standard ChromeOS | ||
| 100 | bootloader setup and use the open source depthcharge bootloader to boot the | ||
| 101 | OS. These devices do not use the scheme described above. For details, see: | ||
| 102 | https://docs.kernel.org/arm/google/chromebook-boot-flow.html | ||
| 103 | |||
| 93 | properties: | 104 | properties: |
| 94 | $nodename: | 105 | $nodename: |
| 95 | const: "/" | 106 | const: "/" |
| @@ -153,28 +164,50 @@ properties: · 57 unmodified lines | |||
| 153 | - const: qcom,msm8974 | 164 | - const: qcom,msm8974 |
| 154 | 165 | ||
| 155 | - items: | 166 | - items: |
| 156 | - enum: | ||
| 157 | - alcatel,idol347 | ||
| 158 | - const: qcom,msm8916-mtp/1 | ||
| 159 | - const: qcom,msm8916-mtp | 167 | - const: qcom,msm8916-mtp |
| 168 | - const: qcom,msm8916-mtp/1 | ||
| 160 | - const: qcom,msm8916 | 169 | - const: qcom,msm8916 |
| 161 | 170 | ||
| 162 | - items: | 171 | - items: |
| 163 | - enum: | 172 | - enum: |
| 164 | - longcheer,l8150 | 173 | - alcatel,idol347 |
| 174 | - asus,z00l | ||
| 175 | - huawei,g7 | ||
| 176 | - longcheer,l8910 | ||
| 165 | - samsung,a3u-eur | 177 | - samsung,a3u-eur |
| 166 | - samsung,a5u-eur | 178 | - samsung,a5u-eur |
| 179 | - samsung,j5 | ||
| 180 | - samsung,serranove | ||
| 181 | - wingtech,wt88047 | ||
| 182 | - const: qcom,msm8916 | ||
| 183 | |||
| 184 | - items: | ||
| 185 | - const: longcheer,l8150 | ||
| 186 | - const: qcom,msm8916-v1-qrd/9-v1 | ||
| 167 | - const: qcom,msm8916 | 187 | - const: qcom,msm8916 |
| 168 | 188 | ||
| 189 | - items: | ||
| 190 | - enum: | ||
| 191 | - lg,bullhead | ||
| 192 | - microsoft,talkman | ||
| 193 | - xiaomi,libra | ||
| 194 | - const: qcom,msm8992 | ||
| 195 | |||
| 169 | - items: | 196 | - items: |
| 170 | - enum: | 197 | - enum: |
| 171 | - sony,karin_windy | 198 | - sony,karin_windy |
| 199 | - const: qcom,apq8094 | ||
| 200 | |||
| 201 | - items: | ||
| 202 | - enum: | ||
| 203 | - huawei,angler | ||
| 204 | - microsoft,cityman | ||
| 205 | - sony,ivy-row | ||
| 172 | - sony,karin-row | 206 | - sony,karin-row |
| 173 | - sony,satsuki-row | 207 | - sony,satsuki-row |
| 174 | - sony,sumire-row | 208 | - sony,sumire-row |
| 175 | - sony,suzuran-row | 209 | - sony,suzuran-row |
| 176 | - qcom,msm8994 | 210 | - const: qcom,msm8994 |
| 177 | - const: qcom,apq8094 | ||
| 178 | 211 | ||
| 179 | - items: | 212 | - items: |
| 180 | - enum: | 213 | - enum: |
| @@ -190,9 +223,24 @@ properties: · 9 unmodified lines | |||
| 190 | - sony,kagura-row | 223 | - sony,kagura-row |
| 191 | - sony,keyaki-row | 224 | - sony,keyaki-row |
| 192 | - xiaomi,gemini | 225 | - xiaomi,gemini |
| 226 | - xiaomi,natrium | ||
| 193 | - xiaomi,scorpio | 227 | - xiaomi,scorpio |
| 194 | - const: qcom,msm8996 | 228 | - const: qcom,msm8996 |
| 195 | 229 | ||
| 230 | - items: | ||
| 231 | - enum: | ||
| 232 | - asus,novago-tp370ql | ||
| 233 | - fxtec,pro1 | ||
| 234 | - hp,envy-x2 | ||
| 235 | - lenovo,miix-630 | ||
| 236 | - oneplus,cheeseburger | ||
| 237 | - oneplus,dumpling | ||
| 238 | - qcom,msm8998-mtp | ||
| 239 | - sony,xperia-lilac | ||
| 240 | - sony,xperia-maple | ||
| 241 | - sony,xperia-poplar | ||
| 242 | - const: qcom,msm8998 | ||
| 243 | |||
| 196 | - items: | 244 | - items: |
| 197 | - enum: | 245 | - enum: |
| 198 | - qcom,ipq4019-ap-dk01.1-c1 | 246 | - qcom,ipq4019-ap-dk01.1-c1 |
| @@ -214,19 +262,317 @@ properties: · 15 unmodified lines | |||
| 214 | - qcom,ipq8074-hk10-c2 | 262 | - qcom,ipq8074-hk10-c2 |
| 215 | - const: qcom,ipq8074 | 263 | - const: qcom,ipq8074 |
| 216 | 264 | ||
| 217 | - items: | 265 | - description: Qualcomm Technologies, Inc. SC7180 IDP |
| 266 | items: | ||
| 218 | - enum: | 267 | - enum: |
| 219 | - qcom,sc7180-idp | 268 | - qcom,sc7180-idp |
| 220 | - const: qcom,sc7180 | 269 | - const: qcom,sc7180 |
| 221 | 270 | ||
| 222 | - items: | 271 | - description: HP Chromebook x2 11c (rev1 - 2) |
| 223 | - enum: | 272 | items: |
| 224 | - qcom,sc7280-crd | 273 | - const: google,coachz-rev1 |
| 225 | - qcom,sc7280-idp | 274 | - const: google,coachz-rev2 |
| 226 | - qcom,sc7280-idp2 | 275 | - const: qcom,sc7180 |
| 227 | - google,hoglin | 276 | |
| 228 | - google,piglin | 277 | - description: HP Chromebook x2 11c (newest rev) |
| 229 | - google,senor | 278 | items: |
| 279 | - const: google,coachz | ||
| 280 | - const: qcom,sc7180 | ||
| 281 | |||
| 282 | - description: HP Chromebook x2 11c with LTE (rev1 - 2) | ||
| 283 | items: | ||
| 284 | - const: google,coachz-rev1-sku0 | ||
| 285 | - const: google,coachz-rev2-sku0 | ||
| 286 | - const: qcom,sc7180 | ||
| 287 | |||
| 288 | - description: HP Chromebook x2 11c with LTE (newest rev) | ||
| 289 | items: | ||
| 290 | - const: google,coachz-sku0 | ||
| 291 | - const: qcom,sc7180 | ||
| 292 | |||
| 293 | - description: Lenovo Chromebook Duet 5 13 (rev2) | ||
| 294 | items: | ||
| 295 | - const: google,homestar-rev2 | ||
| 296 | - const: google,homestar-rev23 | ||
| 297 | - const: qcom,sc7180 | ||
| 298 | |||
| 299 | - description: Lenovo Chromebook Duet 5 13 (rev3) | ||
| 300 | items: | ||
| 301 | - const: google,homestar-rev3 | ||
| 302 | - const: qcom,sc7180 | ||
| 303 | |||
| 304 | - description: Lenovo Chromebook Duet 5 13 (newest rev) | ||
| 305 | items: | ||
| 306 | - const: google,homestar | ||
| 307 | - const: qcom,sc7180 | ||
| 308 | |||
| 309 | - description: Google Kingoftown (rev0) | ||
| 310 | items: | ||
| 311 | - const: google,kingoftown-rev0 | ||
| 312 | - const: qcom,sc7180 | ||
| 313 | |||
| 314 | - description: Google Kingoftown (newest rev) | ||
| 315 | items: | ||
| 316 | - const: google,kingoftown | ||
| 317 | - const: qcom,sc7180 | ||
| 318 | |||
| 319 | - description: Acer Chromebook Spin 513 (rev0) | ||
| 320 | items: | ||
| 321 | - const: google,lazor-rev0 | ||
| 322 | - const: qcom,sc7180 | ||
| 323 | |||
| 324 | - description: Acer Chromebook Spin 513 (rev1 - 2) | ||
| 325 | items: | ||
| 326 | - const: google,lazor-rev1 | ||
| 327 | - const: google,lazor-rev2 | ||
| 328 | - const: qcom,sc7180 | ||
| 329 | |||
| 330 | - description: Acer Chromebook Spin 513 (rev3 - 8) | ||
| 331 | items: | ||
| 332 | - const: google,lazor-rev3 | ||
| 333 | - const: google,lazor-rev4 | ||
| 334 | - const: google,lazor-rev5 | ||
| 335 | - const: google,lazor-rev6 | ||
| 336 | - const: google,lazor-rev7 | ||
| 337 | - const: google,lazor-rev8 | ||
| 338 | - const: qcom,sc7180 | ||
| 339 | |||
| 340 | - description: Acer Chromebook Spin 513 (newest rev) | ||
| 341 | items: | ||
| 342 | - const: google,lazor | ||
| 343 | - const: qcom,sc7180 | ||
| 344 | |||
| 345 | - description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2) | ||
| 346 | items: | ||
| 347 | - const: google,lazor-rev1-sku2 | ||
| 348 | - const: google,lazor-rev2-sku2 | ||
| 349 | - const: qcom,sc7180 | ||
| 350 | |||
| 351 | - description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8) | ||
| 352 | items: | ||
| 353 | - const: google,lazor-rev3-sku2 | ||
| 354 | - const: google,lazor-rev4-sku2 | ||
| 355 | - const: google,lazor-rev5-sku2 | ||
| 356 | - const: google,lazor-rev6-sku2 | ||
| 357 | - const: google,lazor-rev7-sku2 | ||
| 358 | - const: google,lazor-rev8-sku2 | ||
| 359 | - const: qcom,sc7180 | ||
| 360 | |||
| 361 | - description: Acer Chromebook Spin 513 with KB Backlight (newest rev) | ||
| 362 | items: | ||
| 363 | - const: google,lazor-sku2 | ||
| 364 | - const: qcom,sc7180 | ||
| 365 | |||
| 366 | - description: Acer Chromebook Spin 513 with LTE (rev1 - 2) | ||
| 367 | items: | ||
| 368 | - const: google,lazor-rev1-sku0 | ||
| 369 | - const: google,lazor-rev2-sku0 | ||
| 370 | - const: qcom,sc7180 | ||
| 371 | |||
| 372 | - description: Acer Chromebook Spin 513 with LTE (rev3 - 8) | ||
| 373 | items: | ||
| 374 | - const: google,lazor-rev3-sku0 | ||
| 375 | - const: google,lazor-rev4-sku0 | ||
| 376 | - const: google,lazor-rev5-sku0 | ||
| 377 | - const: google,lazor-rev6-sku0 | ||
| 378 | - const: google,lazor-rev7-sku0 | ||
| 379 | - const: google,lazor-rev8-sku0 | ||
| 380 | - const: qcom,sc7180 | ||
| 381 | |||
| 382 | - description: Acer Chromebook Spin 513 with LTE (newest rev) | ||
| 383 | items: | ||
| 384 | - const: google,lazor-sku0 | ||
| 385 | - const: qcom,sc7180 | ||
| 386 | |||
| 387 | - description: Acer Chromebook 511 (rev4 - rev8) | ||
| 388 | items: | ||
| 389 | - const: google,lazor-rev4-sku4 | ||
| 390 | - const: google,lazor-rev5-sku4 | ||
| 391 | - const: google,lazor-rev6-sku4 | ||
| 392 | - const: google,lazor-rev7-sku4 | ||
| 393 | - const: google,lazor-rev8-sku4 | ||
| 394 | - const: qcom,sc7180 | ||
| 395 | |||
| 396 | - description: Acer Chromebook 511 (newest rev) | ||
| 397 | items: | ||
| 398 | - const: google,lazor-sku4 | ||
| 399 | - const: qcom,sc7180 | ||
| 400 | |||
| 401 | - description: Acer Chromebook 511 without Touchscreen (rev4) | ||
| 402 | items: | ||
| 403 | - const: google,lazor-rev4-sku5 | ||
| 404 | - const: qcom,sc7180 | ||
| 405 | |||
| 406 | - description: Acer Chromebook 511 without Touchscreen (rev5 - rev8) | ||
| 407 | items: | ||
| 408 | - const: google,lazor-rev5-sku5 | ||
| 409 | - const: google,lazor-rev5-sku6 | ||
| 410 | - const: google,lazor-rev6-sku6 | ||
| 411 | - const: google,lazor-rev7-sku6 | ||
| 412 | - const: google,lazor-rev8-sku6 | ||
| 413 | - const: qcom,sc7180 | ||
| 414 | |||
| 415 | - description: Acer Chromebook 511 without Touchscreen (newest rev) | ||
| 416 | items: | ||
| 417 | - const: google,lazor-sku6 | ||
| 418 | - const: qcom,sc7180 | ||
| 419 | |||
| 420 | - description: Google Mrbland with AUO panel (rev0) | ||
| 421 | items: | ||
| 422 | - const: google,mrbland-rev0-sku0 | ||
| 423 | - const: qcom,sc7180 | ||
| 424 | |||
| 425 | - description: Google Mrbland with AUO panel (newest rev) | ||
| 426 | items: | ||
| 427 | - const: google,mrbland-sku1536 | ||
| 428 | - const: qcom,sc7180 | ||
| 429 | |||
| 430 | - description: Google Mrbland with BOE panel (rev0) | ||
| 431 | items: | ||
| 432 | - const: google,mrbland-rev0-sku16 | ||
| 433 | - const: qcom,sc7180 | ||
| 434 | |||
| 435 | - description: Google Mrbland with BOE panel (newest rev) | ||
| 436 | items: | ||
| 437 | - const: google,mrbland-sku1024 | ||
| 438 | - const: google,mrbland-sku768 | ||
| 439 | - const: qcom,sc7180 | ||
| 440 | |||
| 441 | - description: Google Pazquel with Parade (newest rev) | ||
| 442 | items: | ||
| 443 | - const: google,pazquel-sku5 | ||
| 444 | - const: qcom,sc7180 | ||
| 445 | |||
| 446 | - description: Google Pazquel with TI (newest rev) | ||
| 447 | items: | ||
| 448 | - const: google,pazquel-sku1 | ||
| 449 | - const: qcom,sc7180 | ||
| 450 | |||
| 451 | - description: Google Pazquel with LTE and Parade (newest rev) | ||
| 452 | items: | ||
| 453 | - const: google,pazquel-sku4 | ||
| 454 | - const: qcom,sc7180 | ||
| 455 | |||
| 456 | - description: Google Pazquel with LTE and TI (newest rev) | ||
| 457 | items: | ||
| 458 | - const: google,pazquel-sku0 | ||
| 459 | - const: google,pazquel-sku2 | ||
| 460 | - const: qcom,sc7180 | ||
| 461 | |||
| 462 | - description: Sharp Dynabook Chromebook C1 (rev1) | ||
| 463 | items: | ||
| 464 | - const: google,pompom-rev1 | ||
| 465 | - const: qcom,sc7180 | ||
| 466 | |||
| 467 | - description: Sharp Dynabook Chromebook C1 (rev2) | ||
| 468 | items: | ||
| 469 | - const: google,pompom-rev2 | ||
| 470 | - const: qcom,sc7180 | ||
| 471 | |||
| 472 | - description: Sharp Dynabook Chromebook C1 (newest rev) | ||
| 473 | items: | ||
| 474 | - const: google,pompom | ||
| 475 | - const: qcom,sc7180 | ||
| 476 | |||
| 477 | - description: Sharp Dynabook Chromebook C1 with LTE (rev1) | ||
| 478 | items: | ||
| 479 | - const: google,pompom-rev1-sku0 | ||
| 480 | - const: qcom,sc7180 | ||
| 481 | |||
| 482 | - description: Sharp Dynabook Chromebook C1 with LTE (rev2) | ||
| 483 | items: | ||
| 484 | - const: google,pompom-rev2-sku0 | ||
| 485 | - const: qcom,sc7180 | ||
| 486 | |||
| 487 | - description: Sharp Dynabook Chromebook C1 with LTE (newest rev) | ||
| 488 | items: | ||
| 489 | - const: google,pompom-sku0 | ||
| 490 | - const: qcom,sc7180 | ||
| 491 | |||
| 492 | - description: Google Quackingstick (newest rev) | ||
| 493 | items: | ||
| 494 | - const: google,quackingstick-sku1537 | ||
| 495 | - const: qcom,sc7180 | ||
| 496 | |||
| 497 | - description: Google Quackingstick with LTE (newest rev) | ||
| 498 | items: | ||
| 499 | - const: google,quackingstick-sku1536 | ||
| 500 | - const: qcom,sc7180 | ||
| 501 | |||
| 502 | - description: Google Trogdor (newest rev) | ||
| 503 | items: | ||
| 504 | - const: google,trogdor | ||
| 505 | - const: qcom,sc7180 | ||
| 506 | |||
| 507 | - description: Google Trogdor with LTE (newest rev) | ||
| 508 | items: | ||
| 509 | - const: google,trogdor-sku0 | ||
| 510 | - const: qcom,sc7180 | ||
| 511 | |||
| 512 | - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0) | ||
| 513 | items: | ||
| 514 | - const: google,wormdingler-rev0-sku16 | ||
| 515 | - const: qcom,sc7180 | ||
| 516 | |||
| 517 | - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev) | ||
| 518 | items: | ||
| 519 | - const: google,wormdingler-sku1024 | ||
| 520 | - const: qcom,sc7180 | ||
| 521 | |||
| 522 | - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev) | ||
| 523 | items: | ||
| 524 | - const: google,wormdingler-sku1025 | ||
| 525 | - const: qcom,sc7180 | ||
| 526 | |||
| 527 | - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0) | ||
| 528 | items: | ||
| 529 | - const: google,wormdingler-rev0-sku0 | ||
| 530 | - const: qcom,sc7180 | ||
| 531 | |||
| 532 | - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev) | ||
| 533 | items: | ||
| 534 | - const: google,wormdingler-sku0 | ||
| 535 | - const: qcom,sc7180 | ||
| 536 | |||
| 537 | - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev) | ||
| 538 | items: | ||
| 539 | - const: google,wormdingler-sku1 | ||
| 540 | - const: qcom,sc7180 | ||
| 541 | |||
| 542 | - description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4) | ||
| 543 | items: | ||
| 544 | - const: qcom,sc7280-crd | ||
| 545 | - const: google,hoglin-rev3 | ||
| 546 | - const: google,hoglin-rev4 | ||
| 547 | - const: google,piglin-rev3 | ||
| 548 | - const: google,piglin-rev4 | ||
| 549 | - const: qcom,sc7280 | ||
| 550 | |||
| 551 | - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) | ||
| 552 | items: | ||
| 553 | - const: google,hoglin | ||
| 554 | - const: qcom,sc7280 | ||
| 555 | |||
| 556 | - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform | ||
| 557 | items: | ||
| 558 | - const: qcom,sc7280-idp | ||
| 559 | - const: google,senor | ||
| 560 | - const: qcom,sc7280 | ||
| 561 | |||
| 562 | - description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform | ||
| 563 | items: | ||
| 564 | - const: qcom,sc7280-idp2 | ||
| 565 | - const: google,piglin | ||
| 566 | - const: qcom,sc7280 | ||
| 567 | |||
| 568 | - description: Google Herobrine (newest rev) | ||
| 569 | items: | ||
| 570 | - const: google,herobrine | ||
| 571 | - const: qcom,sc7280 | ||
| 572 | |||
| 573 | - description: Google Villager (newest rev) | ||
| 574 | items: | ||
| 575 | - const: google,villager | ||
| 230 | - const: qcom,sc7280 | 576 | - const: qcom,sc7280 |
| 231 | 577 | ||
| 232 | - items: | 578 | - items: |
| @@ -238,14 +584,34 @@ properties: · 5 unmodified lines | |||
| 238 | 584 | ||
| 239 | - items: | 585 | - items: |
| 240 | - enum: | 586 | - enum: |
| 587 | - lenovo,thinkpad-x13s | ||
| 588 | - qcom,sc8280xp-crd | ||
| 241 | - qcom,sc8280xp-qrd | 589 | - qcom,sc8280xp-qrd |
| 242 | - const: qcom,sc8280xp | 590 | - const: qcom,sc8280xp |
| 243 | 591 | ||
| 592 | - items: | ||
| 593 | - enum: | ||
| 594 | - sony,discovery-row | ||
| 595 | - sony,kirin-row | ||
| 596 | - sony,pioneer-row | ||
| 597 | - sony,voyager-row | ||
| 598 | - const: qcom,sdm630 | ||
| 599 | |||
| 600 | - items: | ||
| 601 | - enum: | ||
| 602 | - inforce,ifc6560 | ||
| 603 | - const: qcom,sda660 | ||
| 604 | |||
| 244 | - items: | 605 | - items: |
| 245 | - enum: | 606 | - enum: |
| 246 | - fairphone,fp3 | 607 | - fairphone,fp3 |
| 247 | - const: qcom,sdm632 | 608 | - const: qcom,sdm632 |
| 248 | 609 | ||
| 610 | - items: | ||
| 611 | - enum: | ||
| 612 | - sony,mermaid-row | ||
| 613 | - const: qcom,sdm636 | ||
| 614 | |||
| 249 | - items: | 615 | - items: |
| 250 | - enum: | 616 | - enum: |
| 251 | - xiaomi,lavender | 617 | - xiaomi,lavender |
| @@ -269,6 +635,13 @@ properties: · 17 unmodified lines | |||
| 269 | - qcom,ipq6018-cp01-c1 | 635 | - qcom,ipq6018-cp01-c1 |
| 270 | - const: qcom,ipq6018 | 636 | - const: qcom,ipq6018 |
| 271 | 637 | ||
| 638 | - items: | ||
| 639 | - enum: | ||
| 640 | - qcom,qcs404-evb-1000 | ||
| 641 | - qcom,qcs404-evb-4000 | ||
| 642 | - const: qcom,qcs404-evb | ||
| 643 | - const: qcom,qcs404 | ||
| 644 | |||
| 272 | - items: | 645 | - items: |
| 273 | - enum: | 646 | - enum: |
| 274 | - qcom,sa8155p-adp | 647 | - qcom,sa8155p-adp |
| @@ -279,6 +652,34 @@ properties: · 4 unmodified lines | |||
| 279 | - qcom,sa8295p-adp | 652 | - qcom,sa8295p-adp |
| 280 | - const: qcom,sa8540p | 653 | - const: qcom,sa8540p |
| 281 | 654 | ||
| 655 | - items: | ||
| 656 | - enum: | ||
| 657 | - lenovo,yoga-c630 | ||
| 658 | - lg,judyln | ||
| 659 | - lg,judyp | ||
| 660 | - oneplus,enchilada | ||
| 661 | - oneplus,fajita | ||
| 662 | - qcom,sdm845-mtp | ||
| 663 | - shift,axolotl | ||
| 664 | - samsung,w737 | ||
| 665 | - sony,akari-row | ||
| 666 | - sony,akatsuki-row | ||
| 667 | - sony,apollo-row | ||
| 668 | - thundercomm,db845c | ||
| 669 | - xiaomi,beryllium | ||
| 670 | - xiaomi,polaris | ||
| 671 | - const: qcom,sdm845 | ||
| 672 | |||
| 673 | - items: | ||
| 674 | - enum: | ||
| 675 | - sony,pdx201 | ||
| 676 | - const: qcom,sm6125 | ||
| 677 | |||
| 678 | - items: | ||
| 679 | - enum: | ||
| 680 | - sony,pdx213 | ||
| 681 | - const: qcom,sm6350 | ||
| 682 | |||
| 282 | - items: | 683 | - items: |
| 283 | - enum: | 684 | - enum: |
| 284 | - fairphone,fp4 | 685 | - fairphone,fp4 |
| @@ -286,19 +687,29 @@ properties: · 1 unmodified line | |||
| 286 | 687 | ||
| 287 | - items: | 688 | - items: |
| 288 | - enum: | 689 | - enum: |
| 690 | - microsoft,surface-duo | ||
| 691 | - qcom,sm8150-hdk | ||
| 289 | - qcom,sm8150-mtp | 692 | - qcom,sm8150-mtp |
| 693 | - sony,bahamut-generic | ||
| 694 | - sony,griffin-generic | ||
| 290 | - const: qcom,sm8150 | 695 | - const: qcom,sm8150 |
| 291 | 696 | ||
| 292 | - items: | 697 | - items: |
| 293 | - enum: | 698 | - enum: |
| 294 | - qcom,qrb5165-rb5 | 699 | - qcom,qrb5165-rb5 |
| 700 | - qcom,sm8250-hdk | ||
| 295 | - qcom,sm8250-mtp | 701 | - qcom,sm8250-mtp |
| 702 | - sony,pdx203-generic | ||
| 703 | - sony,pdx206-generic | ||
| 296 | - const: qcom,sm8250 | 704 | - const: qcom,sm8250 |
| 297 | 705 | ||
| 298 | - items: | 706 | - items: |
| 299 | - enum: | 707 | - enum: |
| 708 | - microsoft,surface-duo2 | ||
| 300 | - qcom,sm8350-hdk | 709 | - qcom,sm8350-hdk |
| 301 | - qcom,sm8350-mtp | 710 | - qcom,sm8350-mtp |
| 711 | - sony,pdx214-generic | ||
| 712 | - sony,pdx215-generic | ||
| 302 | - const: qcom,sm8350 | 713 | - const: qcom,sm8350 |
| 303 | 714 | ||
| 304 | - items: | 715 | - items: |
| @@ -554,6 +554,11 @@ properties: · 553 unmodified lines | |||
| 554 | - const: vamrs,rk3399pro-vmarc-som | 554 | - const: vamrs,rk3399pro-vmarc-som |
| 555 | - const: rockchip,rk3399pro | 555 | - const: rockchip,rk3399pro |
| 556 | 556 | ||
| 557 | - description: Radxa ROCK Pi S | ||
| 558 | items: | ||
| 559 | - const: radxa,rockpis | ||
| 560 | - const: rockchip,rk3308 | ||
| 561 | |||
| 557 | - description: Radxa Rock2 Square | 562 | - description: Radxa Rock2 Square |
| 558 | items: | 563 | items: |
| 559 | - const: radxa,rock2-square | 564 | - const: radxa,rock2-square |
| @@ -0,0 +1,40 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Samsung S3C, S5P and Exynos SoC compatibles naming convention | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Krzysztof Kozlowski <krzk@kernel.org> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | Guidelines for new compatibles for SoC blocks/components. | ||
| 14 | When adding new compatibles in new bindings, use the format:: | ||
| 15 | samsung,SoC-IP | ||
| 16 | |||
| 17 | For example:: | ||
| 18 | samsung,exynos5433-cmu-isp | ||
| 19 | |||
| 20 | select: | ||
| 21 | properties: | ||
| 22 | compatible: | ||
| 23 | pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$" | ||
| 24 | required: | ||
| 25 | - compatible | ||
| 26 | |||
| 27 | properties: | ||
| 28 | compatible: | ||
| 29 | oneOf: | ||
| 30 | - description: Preferred naming style for compatibles of SoC components | ||
| 31 | pattern: "^samsung,(s3c|s5pv|exynos|exynosautov)[0-9]+-.*$" | ||
| 32 | |||
| 33 | # Legacy compatibles with wild-cards - list cannot grow with new bindings: | ||
| 34 | - enum: | ||
| 35 | - samsung,exynos4x12-pinctrl | ||
| 36 | - samsung,exynos4x12-usb2-phy | ||
| 37 | - samsung,s3c64xx-pinctrl | ||
| 38 | - samsung,s3c64xx-wakeup-eint | ||
| 39 | |||
| 40 | additionalProperties: true | ||
| @@ -59,12 +59,18 @@ properties: · 58 unmodified lines | |||
| 59 | - prt,prtt1s # Protonic PRTT1S | 59 | - prt,prtt1s # Protonic PRTT1S |
| 60 | - const: st,stm32mp151 | 60 | - const: st,stm32mp151 |
| 61 | 61 | ||
| 62 | - description: DH STM32MP153 SoM based Boards | 62 | - description: DH STM32MP153 DHCOM SoM based Boards |
| 63 | items: | 63 | items: |
| 64 | - const: dh,stm32mp153c-dhcom-drc02 | 64 | - const: dh,stm32mp153c-dhcom-drc02 |
| 65 | - const: dh,stm32mp153c-dhcom-som | 65 | - const: dh,stm32mp153c-dhcom-som |
| 66 | - const: st,stm32mp153 | 66 | - const: st,stm32mp153 |
| 67 | 67 | ||
| 68 | - description: DH STM32MP153 DHCOR SoM based Boards | ||
| 69 | items: | ||
| 70 | - const: dh,stm32mp153c-dhcor-drc-compact | ||
| 71 | - const: dh,stm32mp153c-dhcor-som | ||
| 72 | - const: st,stm32mp153 | ||
| 73 | |||
| 68 | - items: | 74 | - items: |
| 69 | - enum: | 75 | - enum: |
| 70 | - shiratech,stm32mp157a-iot-box # IoT Box | 76 | - shiratech,stm32mp157a-iot-box # IoT Box |
| @@ -0,0 +1,29 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | # Copyright (C) Sunplus Co., Ltd. 2021 | ||
| 3 | %YAML 1.2 | ||
| 4 | --- | ||
| 5 | $id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# | ||
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 7 | |||
| 8 | title: Sunplus SP7021 Boards | ||
| 9 | |||
| 10 | maintainers: | ||
| 11 | - qinjian <qinjian@cqplus1.com> | ||
| 12 | |||
| 13 | description: | | ||
| 14 | ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. | ||
| 15 | Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview | ||
| 16 | |||
| 17 | properties: | ||
| 18 | $nodename: | ||
| 19 | const: '/' | ||
| 20 | compatible: | ||
| 21 | items: | ||
| 22 | - enum: | ||
| 23 | - sunplus,sp7021-achip | ||
| 24 | - sunplus,sp7021-demo-v3 | ||
| 25 | - const: sunplus,sp7021 | ||
| 26 | |||
| 27 | additionalProperties: true | ||
| 28 | |||
| 29 | ... | ||
| @@ -863,6 +863,11 @@ properties: · 862 unmodified lines | |||
| 863 | - const: yones-toptech,bs1078-v2 | 863 | - const: yones-toptech,bs1078-v2 |
| 864 | - const: allwinner,sun6i-a31s | 864 | - const: allwinner,sun6i-a31s |
| 865 | 865 | ||
| 866 | - description: X96 Mate TV box | ||
| 867 | items: | ||
| 868 | - const: hechuang,x96-mate | ||
| 869 | - const: allwinner,sun50i-h616 | ||
| 870 | |||
| 866 | - description: Xunlong OrangePi | 871 | - description: Xunlong OrangePi |
| 867 | items: | 872 | items: |
| 868 | - const: xunlong,orangepi | 873 | - const: xunlong,orangepi |
| @@ -963,4 +968,9 @@ properties: · 94 unmodified lines | |||
| 963 | - const: xunlong,orangepi-zero-plus2-h3 | 968 | - const: xunlong,orangepi-zero-plus2-h3 |
| 964 | - const: allwinner,sun8i-h3 | 969 | - const: allwinner,sun8i-h3 |
| 965 | 970 | ||
| 971 | - description: Xunlong OrangePi Zero 2 | ||
| 972 | items: | ||
| 973 | - const: xunlong,orangepi-zero2 | ||
| 974 | - const: allwinner,sun50i-h616 | ||
| 975 | |||
| 966 | additionalProperties: true | 976 | additionalProperties: true |
| @@ -29,10 +29,20 @@ properties: · 28 unmodified lines | |||
| 29 | compatible: | 29 | compatible: |
| 30 | enum: | 30 | enum: |
| 31 | - allwinner,sun5i-a13-mbus | 31 | - allwinner,sun5i-a13-mbus |
| 32 | - allwinner,sun8i-a33-mbus | ||
| 33 | - allwinner,sun8i-a50-mbus | ||
| 34 | - allwinner,sun8i-a83t-mbus | ||
| 32 | - allwinner,sun8i-h3-mbus | 35 | - allwinner,sun8i-h3-mbus |
| 33 | - allwinner,sun8i-r40-mbus | 36 | - allwinner,sun8i-r40-mbus |
| 37 | - allwinner,sun8i-v3s-mbus | ||
| 38 | - allwinner,sun8i-v536-mbus | ||
| 39 | - allwinner,sun20i-d1-mbus | ||
| 34 | - allwinner,sun50i-a64-mbus | 40 | - allwinner,sun50i-a64-mbus |
| 41 | - allwinner,sun50i-a100-mbus | ||
| 35 | - allwinner,sun50i-h5-mbus | 42 | - allwinner,sun50i-h5-mbus |
| 43 | - allwinner,sun50i-h6-mbus | ||
| 44 | - allwinner,sun50i-h616-mbus | ||
| 45 | - allwinner,sun50i-r329-mbus | ||
| 36 | 46 | ||
| 37 | reg: | 47 | reg: |
| 38 | minItems: 1 | 48 | minItems: 1 |
| @@ -81,13 +91,13 @@ required: · 42 unmodified lines | |||
| 81 | - dma-ranges | 91 | - dma-ranges |
| 82 | 92 | ||
| 83 | if: | 93 | if: |
| 84 | properties: | 94 | not: |
| 85 | compatible: | 95 | properties: |
| 86 | contains: | 96 | compatible: |
| 87 | enum: | 97 | contains: |
| 88 | - allwinner,sun8i-h3-mbus | 98 | enum: |
| 89 | - allwinner,sun50i-a64-mbus | 99 | - allwinner,sun5i-a13-mbus |
| 90 | - allwinner,sun50i-h5-mbus | 100 | - allwinner,sun8i-r40-mbus |
| 91 | 101 | ||
| 92 | then: | 102 | then: |
| 93 | properties: | 103 | properties: |
| @@ -40,7 +40,6 @@ required: · 39 unmodified lines | |||
| 40 | - compatible | 40 | - compatible |
| 41 | - reg | 41 | - reg |
| 42 | - nvidia,bpmp | 42 | - nvidia,bpmp |
| 43 | - status | ||
| 44 | 43 | ||
| 45 | examples: | 44 | examples: |
| 46 | - | | 45 | - | |
| @@ -0,0 +1,40 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#" | ||
| 5 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | ||
| 6 | |||
| 7 | title: NVIDIA Tegra194 AXI2APB bridge | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Sumit Gupta <sumitg@nvidia.com> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | $nodename: | ||
| 14 | pattern: "^axi2apb@([0-9a-f]+)$" | ||
| 15 | |||
| 16 | compatible: | ||
| 17 | enum: | ||
| 18 | - nvidia,tegra194-axi2apb | ||
| 19 | |||
| 20 | reg: | ||
| 21 | maxItems: 6 | ||
| 22 | description: Physical base address and length of registers for all bridges | ||
| 23 | |||
| 24 | additionalProperties: false | ||
| 25 | |||
| 26 | required: | ||
| 27 | - compatible | ||
| 28 | - reg | ||
| 29 | |||
| 30 | examples: | ||
| 31 | - | | ||
| 32 | axi2apb: axi2apb@2390000 { | ||
| 33 | compatible = "nvidia,tegra194-axi2apb"; | ||
| 34 | reg = <0x02390000 0x1000>, | ||
| 35 | <0x023a0000 0x1000>, | ||
| 36 | <0x023b0000 0x1000>, | ||
| 37 | <0x023c0000 0x1000>, | ||
| 38 | <0x023d0000 0x1000>, | ||
| 39 | <0x023e0000 0x1000>; | ||
| 40 | }; | ||
| @@ -0,0 +1,97 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" | ||
| 5 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | ||
| 6 | |||
| 7 | title: NVIDIA Tegra194 CBB 1.0 bindings | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Sumit Gupta <sumitg@nvidia.com> | ||
| 11 | |||
| 12 | description: |+ | ||
| 13 | The Control Backbone (CBB) is comprised of the physical path from an | ||
| 14 | initiator to a target's register configuration space. CBB 1.0 has | ||
| 15 | multiple hierarchical sub-NOCs (Network-on-Chip) and connects various | ||
| 16 | initiators and targets using different bridges like AXIP2P, AXI2APB. | ||
| 17 | |||
| 18 | This driver handles errors due to illegal register accesses reported | ||
| 19 | by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs | ||
| 20 | "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" | ||
| 21 | which is the main NOC. | ||
| 22 | |||
| 23 | By default, the access issuing initiator is informed about the error | ||
| 24 | using SError or Data Abort exception unless the ERD (Error Response | ||
| 25 | Disable) is enabled/set for that initiator. If the ERD is enabled, then | ||
| 26 | SError or Data Abort is masked and the error is reported with interrupt. | ||
| 27 | |||
| 28 | - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the | ||
| 29 | errors due to illegal accesses from CCPLEX are reported by interrupts. | ||
| 30 | If ERD is not set, then error is reported by SError. | ||
| 31 | - For other initiators, the ERD is disabled. So, the access issuing | ||
| 32 | initiator is informed about the illegal access by Data Abort exception. | ||
| 33 | In addition, an interrupt is also generated to CCPLEX. These initiators | ||
| 34 | include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and | ||
| 35 | engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder | ||
| 36 | engine) etc which can initiate transactions. | ||
| 37 | |||
| 38 | The driver prints relevant debug information like Error Code, Error | ||
| 39 | Description, Master, Address, AXI ID, Cache, Protection, Security Group | ||
| 40 | etc on receiving error notification. | ||
| 41 | |||
| 42 | properties: | ||
| 43 | $nodename: | ||
| 44 | pattern: "^[a-z]+-noc@[0-9a-f]+$" | ||
| 45 | |||
| 46 | compatible: | ||
| 47 | enum: | ||
| 48 | - nvidia,tegra194-cbb-noc | ||
| 49 | - nvidia,tegra194-aon-noc | ||
| 50 | - nvidia,tegra194-bpmp-noc | ||
| 51 | - nvidia,tegra194-rce-noc | ||
| 52 | - nvidia,tegra194-sce-noc | ||
| 53 | |||
| 54 | reg: | ||
| 55 | maxItems: 1 | ||
| 56 | |||
| 57 | interrupts: | ||
| 58 | description: | ||
| 59 | CCPLEX receives secure or nonsecure interrupt depending on error type. | ||
| 60 | A secure interrupt is received for SEC(firewall) & SLV errors and a | ||
| 61 | non-secure interrupt is received for TMO & DEC errors. | ||
| 62 | items: | ||
| 63 | - description: non-secure interrupt | ||
| 64 | - description: secure interrupt | ||
| 65 | |||
| 66 | nvidia,axi2apb: | ||
| 67 | $ref: '/schemas/types.yaml#/definitions/phandle' | ||
| 68 | description: | ||
| 69 | Specifies the node having all axi2apb bridges which need to be checked | ||
| 70 | for any error logged in their status register. | ||
| 71 | |||
| 72 | nvidia,apbmisc: | ||
| 73 | $ref: '/schemas/types.yaml#/definitions/phandle' | ||
| 74 | description: | ||
| 75 | Specifies the apbmisc node which need to be used for reading the ERD | ||
| 76 | register. | ||
| 77 | |||
| 78 | additionalProperties: false | ||
| 79 | |||
| 80 | required: | ||
| 81 | - compatible | ||
| 82 | - reg | ||
| 83 | - interrupts | ||
| 84 | - nvidia,apbmisc | ||
| 85 | |||
| 86 | examples: | ||
| 87 | - | | ||
| 88 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 89 | |||
| 90 | cbb-noc@2300000 { | ||
| 91 | compatible = "nvidia,tegra194-cbb-noc"; | ||
| 92 | reg = <0x02300000 0x1000>; | ||
| 93 | interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, | ||
| 94 | <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; | ||
| 95 | nvidia,axi2apb = <&axi2apb>; | ||
| 96 | nvidia,apbmisc = <&apbmisc>; | ||
| 97 | }; | ||
| @@ -208,7 +208,7 @@ properties: · 207 unmodified lines | |||
| 208 | "^[a-z0-9]+$": | 208 | "^[a-z0-9]+$": |
| 209 | type: object | 209 | type: object |
| 210 | 210 | ||
| 211 | patternProperties: | 211 | properties: |
| 212 | clocks: | 212 | clocks: |
| 213 | minItems: 1 | 213 | minItems: 1 |
| 214 | maxItems: 8 | 214 | maxItems: 8 |
| @@ -0,0 +1,74 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#" | ||
| 5 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | ||
| 6 | |||
| 7 | title: NVIDIA Tegra CBB 2.0 bindings | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Sumit Gupta <sumitg@nvidia.com> | ||
| 11 | |||
| 12 | description: |+ | ||
| 13 | The Control Backbone (CBB) is comprised of the physical path from an | ||
| 14 | initiator to a target's register configuration space. CBB 2.0 consists | ||
| 15 | of multiple sub-blocks connected to each other to create a topology. | ||
| 16 | The Tegra234 SoC has different fabrics based on CBB 2.0 architecture | ||
| 17 | which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and | ||
| 18 | "CBB central fabric". | ||
| 19 | |||
| 20 | In CBB 2.0, each initiator which can issue transactions connects to a | ||
| 21 | Root Master Node (MN) before it connects to any other element of the | ||
| 22 | fabric. Each Root MN contains a Error Monitor (EM) which detects and | ||
| 23 | logs error. Interrupts from various EM blocks are collated by Error | ||
| 24 | Notifier (EN) which is per fabric and presents a single interrupt from | ||
| 25 | fabric to the SoC interrupt controller. | ||
| 26 | |||
| 27 | The driver handles errors from CBB due to illegal register accesses | ||
| 28 | and prints debug information about failed transaction on receiving | ||
| 29 | the interrupt from EN. Debug information includes Error Code, Error | ||
| 30 | Description, MasterID, Fabric, SlaveID, Address, Cache, Protection, | ||
| 31 | Security Group etc on receiving error notification. | ||
| 32 | |||
| 33 | If the Error Response Disable (ERD) is set/enabled for an initiator, | ||
| 34 | then SError or Data abort exception error response is masked and an | ||
| 35 | interrupt is used for reporting errors due to illegal accesses from | ||
| 36 | that initiator. The value returned on read failures is '0xFFFFFFFF' | ||
| 37 | for compatibility with PCIE. | ||
| 38 | |||
| 39 | properties: | ||
| 40 | $nodename: | ||
| 41 | pattern: "^[a-z]+-fabric@[0-9a-f]+$" | ||
| 42 | |||
| 43 | compatible: | ||
| 44 | enum: | ||
| 45 | - nvidia,tegra234-aon-fabric | ||
| 46 | - nvidia,tegra234-bpmp-fabric | ||
| 47 | - nvidia,tegra234-cbb-fabric | ||
| 48 | - nvidia,tegra234-dce-fabric | ||
| 49 | - nvidia,tegra234-rce-fabric | ||
| 50 | - nvidia,tegra234-sce-fabric | ||
| 51 | |||
| 52 | reg: | ||
| 53 | maxItems: 1 | ||
| 54 | |||
| 55 | interrupts: | ||
| 56 | items: | ||
| 57 | - description: secure interrupt from error notifier | ||
| 58 | |||
| 59 | additionalProperties: false | ||
| 60 | |||
| 61 | required: | ||
| 62 | - compatible | ||
| 63 | - reg | ||
| 64 | - interrupts | ||
| 65 | |||
| 66 | examples: | ||
| 67 | - | | ||
| 68 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 69 | |||
| 70 | cbb-fabric@1300000 { | ||
| 71 | compatible = "nvidia,tegra234-cbb-fabric"; | ||
| 72 | reg = <0x13a00000 0x400000>; | ||
| 73 | interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; | ||
| 74 | }; | ||
| @@ -29,6 +29,13 @@ properties: · 28 unmodified lines | |||
| 29 | 29 | ||
| 30 | ranges: true | 30 | ranges: true |
| 31 | 31 | ||
| 32 | gpio-controller: | ||
| 33 | deprecated: true | ||
| 34 | |||
| 35 | "#gpio-cells": | ||
| 36 | deprecated: true | ||
| 37 | const: 2 | ||
| 38 | |||
| 32 | additionalProperties: false | 39 | additionalProperties: false |
| 33 | 40 | ||
| 34 | patternProperties: | 41 | patternProperties: |
| @@ -67,8 +74,7 @@ patternProperties: · 32 unmodified lines | |||
| 67 | 74 | ||
| 68 | required: | 75 | required: |
| 69 | - compatible | 76 | - compatible |
| 70 | - "#address-cells" | 77 | - reg |
| 71 | - "#size-cells" | ||
| 72 | 78 | ||
| 73 | examples: | 79 | examples: |
| 74 | - | | 80 | - | |
| @@ -1,63 +0,0 @@ | |||
| 1 | Binding for CEVA AHCI SATA Controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - reg: Physical base address and size of the controller's register area. | ||
| 5 | - compatible: Compatibility string. Must be 'ceva,ahci-1v84'. | ||
| 6 | - clocks: Input clock specifier. Refer to common clock bindings. | ||
| 7 | - interrupts: Interrupt specifier. Refer to interrupt binding. | ||
| 8 | - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0. | ||
| 9 | - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1. | ||
| 10 | The fields for the above parameter must be as shown below: | ||
| 11 | ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>; | ||
| 12 | CINMP : COMINIT Negate Minimum Period. | ||
| 13 | CIBGN : COMINIT Burst Gap Nominal. | ||
| 14 | CIBGMX: COMINIT Burst Gap Maximum. | ||
| 15 | CIBGMN: COMINIT Burst Gap Minimum. | ||
| 16 | - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0. | ||
| 17 | - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1. | ||
| 18 | The fields for the above parameter must be as shown below: | ||
| 19 | ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>; | ||
| 20 | CWBGMN: COMWAKE Burst Gap Minimum. | ||
| 21 | CWBGMX: COMWAKE Burst Gap Maximum. | ||
| 22 | CWBGN: COMWAKE Burst Gap Nominal. | ||
| 23 | CWNMP: COMWAKE Negate Minimum Period. | ||
| 24 | - ceva,p0-burst-params: Burst timing value for COM parameter for port 0. | ||
| 25 | - ceva,p1-burst-params: Burst timing value for COM parameter for port 1. | ||
| 26 | The fields for the above parameter must be as shown below: | ||
| 27 | ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>; | ||
| 28 | BMX: COM Burst Maximum. | ||
| 29 | BNM: COM Burst Nominal. | ||
| 30 | SFD: Signal Failure Detection value. | ||
| 31 | PTST: Partial to Slumber timer value. | ||
| 32 | - ceva,p0-retry-params: Retry interval timing value for port 0. | ||
| 33 | - ceva,p1-retry-params: Retry interval timing value for port 1. | ||
| 34 | The fields for the above parameter must be as shown below: | ||
| 35 | ceva,pN-retry-params = /bits/ 16 <RIT RCT>; | ||
| 36 | RIT: Retry Interval Timer. | ||
| 37 | RCT: Rate Change Timer. | ||
| 38 | |||
| 39 | Optional properties: | ||
| 40 | - ceva,broken-gen2: limit to gen1 speed instead of gen2. | ||
| 41 | - phys: phandle for the PHY device | ||
| 42 | - resets: phandle to the reset controller for the SATA IP | ||
| 43 | |||
| 44 | Examples: | ||
| 45 | ahci@fd0c0000 { | ||
| 46 | compatible = "ceva,ahci-1v84"; | ||
| 47 | reg = <0xfd0c0000 0x200>; | ||
| 48 | interrupt-parent = <&gic>; | ||
| 49 | interrupts = <0 133 4>; | ||
| 50 | clocks = <&clkc SATA_CLK_ID>; | ||
| 51 | ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; | ||
| 52 | ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; | ||
| 53 | ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; | ||
| 54 | ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; | ||
| 55 | |||
| 56 | ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; | ||
| 57 | ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; | ||
| 58 | ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; | ||
| 59 | ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; | ||
| 60 | ceva,broken-gen2; | ||
| 61 | phys = <&psgtr 1 PHY_TYPE_SATA 1 1>; | ||
| 62 | resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; | ||
| 63 | }; | ||
| @@ -0,0 +1,189 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Ceva AHCI SATA Controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Piyush Mehta <piyush.mehta@xilinx.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | The Ceva SATA controller mostly conforms to the AHCI interface with some | ||
| 14 | special extensions to add functionality, is a high-performance dual-port | ||
| 15 | SATA host controller with an AHCI compliant command layer which supports | ||
| 16 | advanced features such as native command queuing and frame information | ||
| 17 | structure (FIS) based switching for systems employing port multipliers. | ||
| 18 | |||
| 19 | properties: | ||
| 20 | compatible: | ||
| 21 | const: ceva,ahci-1v84 | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | clocks: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | dma-coherent: true | ||
| 30 | |||
| 31 | interrupts: | ||
| 32 | maxItems: 1 | ||
| 33 | |||
| 34 | iommus: | ||
| 35 | maxItems: 1 | ||
| 36 | |||
| 37 | power-domains: | ||
| 38 | maxItems: 1 | ||
| 39 | |||
| 40 | ceva,p0-cominit-params: | ||
| 41 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 42 | description: | | ||
| 43 | OOB timing value for COMINIT parameter for port 0. | ||
| 44 | The fields for the above parameter must be as shown below:- | ||
| 45 | ceva,p0-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>; | ||
| 46 | items: | ||
| 47 | - description: CINMP - COMINIT Negate Minimum Period. | ||
| 48 | - description: CIBGN - COMINIT Burst Gap Nominal. | ||
| 49 | - description: CIBGMX - COMINIT Burst Gap Maximum. | ||
| 50 | - description: CIBGMN - COMINIT Burst Gap Minimum. | ||
| 51 | |||
| 52 | ceva,p0-comwake-params: | ||
| 53 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 54 | description: | | ||
| 55 | OOB timing value for COMWAKE parameter for port 0. | ||
| 56 | The fields for the above parameter must be as shown below:- | ||
| 57 | ceva,p0-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>; | ||
| 58 | items: | ||
| 59 | - description: CWBGMN - COMWAKE Burst Gap Minimum. | ||
| 60 | - description: CWBGMX - COMWAKE Burst Gap Maximum. | ||
| 61 | - description: CWBGN - COMWAKE Burst Gap Nominal. | ||
| 62 | - description: CWNMP - COMWAKE Negate Minimum Period. | ||
| 63 | |||
| 64 | ceva,p0-burst-params: | ||
| 65 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 66 | description: | | ||
| 67 | Burst timing value for COM parameter for port 0. | ||
| 68 | The fields for the above parameter must be as shown below:- | ||
| 69 | ceva,p0-burst-params = /bits/ 8 <BMX BNM SFD PTST>; | ||
| 70 | items: | ||
| 71 | - description: BMX - COM Burst Maximum. | ||
| 72 | - description: BNM - COM Burst Nominal. | ||
| 73 | - description: SFD - Signal Failure Detection value. | ||
| 74 | - description: PTST - Partial to Slumber timer value. | ||
| 75 | |||
| 76 | ceva,p0-retry-params: | ||
| 77 | $ref: /schemas/types.yaml#/definitions/uint16-array | ||
| 78 | description: | | ||
| 79 | Retry interval timing value for port 0. | ||
| 80 | The fields for the above parameter must be as shown below:- | ||
| 81 | ceva,p0-retry-params = /bits/ 16 <RIT RCT>; | ||
| 82 | items: | ||
| 83 | - description: RIT - Retry Interval Timer. | ||
| 84 | - description: RCT - Rate Change Timer. | ||
| 85 | |||
| 86 | ceva,p1-cominit-params: | ||
| 87 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 88 | description: | | ||
| 89 | OOB timing value for COMINIT parameter for port 1. | ||
| 90 | The fields for the above parameter must be as shown below:- | ||
| 91 | ceva,p1-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>; | ||
| 92 | items: | ||
| 93 | - description: CINMP - COMINIT Negate Minimum Period. | ||
| 94 | - description: CIBGN - COMINIT Burst Gap Nominal. | ||
| 95 | - description: CIBGMX - COMINIT Burst Gap Maximum. | ||
| 96 | - description: CIBGMN - COMINIT Burst Gap Minimum. | ||
| 97 | |||
| 98 | ceva,p1-comwake-params: | ||
| 99 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 100 | description: | | ||
| 101 | OOB timing value for COMWAKE parameter for port 1. | ||
| 102 | The fields for the above parameter must be as shown below:- | ||
| 103 | ceva,p1-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>; | ||
| 104 | items: | ||
| 105 | - description: CWBGMN - COMWAKE Burst Gap Minimum. | ||
| 106 | - description: CWBGMX - COMWAKE Burst Gap Maximum. | ||
| 107 | - description: CWBGN - COMWAKE Burst Gap Nominal. | ||
| 108 | - description: CWNMP - COMWAKE Negate Minimum Period. | ||
| 109 | |||
| 110 | ceva,p1-burst-params: | ||
| 111 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 112 | description: | | ||
| 113 | Burst timing value for COM parameter for port 1. | ||
| 114 | The fields for the above parameter must be as shown below:- | ||
| 115 | ceva,p1-burst-params = /bits/ 8 <BMX BNM SFD PTST>; | ||
| 116 | items: | ||
| 117 | - description: BMX - COM Burst Maximum. | ||
| 118 | - description: BNM - COM Burst Nominal. | ||
| 119 | - description: SFD - Signal Failure Detection value. | ||
| 120 | - description: PTST - Partial to Slumber timer value. | ||
| 121 | |||
| 122 | ceva,p1-retry-params: | ||
| 123 | $ref: /schemas/types.yaml#/definitions/uint16-array | ||
| 124 | description: | | ||
| 125 | Retry interval timing value for port 1. | ||
| 126 | The fields for the above parameter must be as shown below:- | ||
| 127 | ceva,pN-retry-params = /bits/ 16 <RIT RCT>; | ||
| 128 | items: | ||
| 129 | - description: RIT - Retry Interval Timer. | ||
| 130 | - description: RCT - Rate Change Timer. | ||
| 131 | |||
| 132 | ceva,broken-gen2: | ||
| 133 | $ref: /schemas/types.yaml#/definitions/flag | ||
| 134 | description: | | ||
| 135 | limit to gen1 speed instead of gen2. | ||
| 136 | |||
| 137 | phys: | ||
| 138 | maxItems: 1 | ||
| 139 | |||
| 140 | phy-names: | ||
| 141 | items: | ||
| 142 | - const: sata-phy | ||
| 143 | |||
| 144 | resets: | ||
| 145 | maxItems: 1 | ||
| 146 | |||
| 147 | required: | ||
| 148 | - compatible | ||
| 149 | - reg | ||
| 150 | - clocks | ||
| 151 | - interrupts | ||
| 152 | - ceva,p0-cominit-params | ||
| 153 | - ceva,p0-comwake-params | ||
| 154 | - ceva,p0-burst-params | ||
| 155 | - ceva,p0-retry-params | ||
| 156 | - ceva,p1-cominit-params | ||
| 157 | - ceva,p1-comwake-params | ||
| 158 | - ceva,p1-burst-params | ||
| 159 | - ceva,p1-retry-params | ||
| 160 | |||
| 161 | additionalProperties: false | ||
| 162 | |||
| 163 | examples: | ||
| 164 | - | | ||
| 165 | #include <dt-bindings/clock/xlnx-zynqmp-clk.h> | ||
| 166 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 167 | #include <dt-bindings/power/xlnx-zynqmp-power.h> | ||
| 168 | #include <dt-bindings/reset/xlnx-zynqmp-resets.h> | ||
| 169 | #include <dt-bindings/clock/xlnx-zynqmp-clk.h> | ||
| 170 | #include <dt-bindings/phy/phy.h> | ||
| 171 | |||
| 172 | sata: ahci@fd0c0000 { | ||
| 173 | compatible = "ceva,ahci-1v84"; | ||
| 174 | reg = <0xfd0c0000 0x200>; | ||
| 175 | interrupt-parent = <&gic>; | ||
| 176 | interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; | ||
| 177 | clocks = <&zynqmp_clk SATA_REF>; | ||
| 178 | ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; | ||
| 179 | ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; | ||
| 180 | ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; | ||
| 181 | ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; | ||
| 182 | ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; | ||
| 183 | ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; | ||
| 184 | ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; | ||
| 185 | ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; | ||
| 186 | ceva,broken-gen2; | ||
| 187 | phys = <&psgtr 1 PHY_TYPE_SATA 1 1>; | ||
| 188 | resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; | ||
| 189 | }; | ||
| @@ -28,11 +28,9 @@ properties: · 27 unmodified lines | |||
| 28 | - const: qcom,ssc-block-bus | 28 | - const: qcom,ssc-block-bus |
| 29 | 29 | ||
| 30 | reg: | 30 | reg: |
| 31 | description: | | 31 | items: |
| 32 | Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 | 32 | - description: SSCAON_CONFIG0 registers |
| 33 | registers | 33 | - description: SSCAON_CONFIG1 registers |
| 34 | minItems: 2 | ||
| 35 | maxItems: 2 | ||
| 36 | 34 | ||
| 37 | reg-names: | 35 | reg-names: |
| 38 | items: | 36 | items: |
| @@ -48,7 +46,6 @@ properties: · 9 unmodified lines | |||
| 48 | ranges: true | 46 | ranges: true |
| 49 | 47 | ||
| 50 | clocks: | 48 | clocks: |
| 51 | minItems: 6 | ||
| 52 | maxItems: 6 | 49 | maxItems: 6 |
| 53 | 50 | ||
| 54 | clock-names: | 51 | clock-names: |
| @@ -61,9 +58,9 @@ properties: · 6 unmodified lines | |||
| 61 | - const: ssc_ahbs | 58 | - const: ssc_ahbs |
| 62 | 59 | ||
| 63 | power-domains: | 60 | power-domains: |
| 64 | description: Power domain phandles for the ssc_cx and ssc_mx power domains | 61 | items: |
| 65 | minItems: 2 | 62 | - description: CX power domain |
| 66 | maxItems: 2 | 63 | - description: MX power domain |
| 67 | 64 | ||
| 68 | power-domain-names: | 65 | power-domain-names: |
| 69 | items: | 66 | items: |
| @@ -71,11 +68,11 @@ properties: · 1 unmodified line | |||
| 71 | - const: ssc_mx | 68 | - const: ssc_mx |
| 72 | 69 | ||
| 73 | resets: | 70 | resets: |
| 74 | description: | | 71 | items: |
| 75 | Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the | 72 | - description: Main reset |
| 76 | branch control register associated with the ssc_xo and ssc_ahbs clocks) | 73 | - description: |
| 77 | minItems: 2 | 74 | SSC Branch Control Register reset (associated with the ssc_xo and |
| 78 | maxItems: 2 | 75 | ssc_ahbs clocks) |
| 79 | 76 | ||
| 80 | reset-names: | 77 | reset-names: |
| 81 | items: | 78 | items: |
| @@ -1,137 +0,0 @@ | |||
| 1 | The chosen node | ||
| 2 | --------------- | ||
| 3 | |||
| 4 | The chosen node does not represent a real device, but serves as a place | ||
| 5 | for passing data between firmware and the operating system, like boot | ||
| 6 | arguments. Data in the chosen node does not represent the hardware. | ||
| 7 | |||
| 8 | The following properties are recognized: | ||
| 9 | |||
| 10 | |||
| 11 | kaslr-seed | ||
| 12 | ----------- | ||
| 13 | |||
| 14 | This property is used when booting with CONFIG_RANDOMIZE_BASE as the | ||
| 15 | entropy used to randomize the kernel image base address location. Since | ||
| 16 | it is used directly, this value is intended only for KASLR, and should | ||
| 17 | not be used for other purposes (as it may leak information about KASLR | ||
| 18 | offsets). It is parsed as a u64 value, e.g. | ||
| 19 | |||
| 20 | / { | ||
| 21 | chosen { | ||
| 22 | kaslr-seed = <0xfeedbeef 0xc0def00d>; | ||
| 23 | }; | ||
| 24 | }; | ||
| 25 | |||
| 26 | Note that if this property is set from UEFI (or a bootloader in EFI | ||
| 27 | mode) when EFI_RNG_PROTOCOL is supported, it will be overwritten by | ||
| 28 | the Linux EFI stub (which will populate the property itself, using | ||
| 29 | EFI_RNG_PROTOCOL). | ||
| 30 | |||
| 31 | stdout-path | ||
| 32 | ----------- | ||
| 33 | |||
| 34 | Device trees may specify the device to be used for boot console output | ||
| 35 | with a stdout-path property under /chosen, as described in the Devicetree | ||
| 36 | Specification, e.g. | ||
| 37 | |||
| 38 | / { | ||
| 39 | chosen { | ||
| 40 | stdout-path = "/serial@f00:115200"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | serial@f00 { | ||
| 44 | compatible = "vendor,some-uart"; | ||
| 45 | reg = <0xf00 0x10>; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | If the character ":" is present in the value, this terminates the path. | ||
| 50 | The meaning of any characters following the ":" is device-specific, and | ||
| 51 | must be specified in the relevant binding documentation. | ||
| 52 | |||
| 53 | For UART devices, the preferred binding is a string in the form: | ||
| 54 | |||
| 55 | <baud>{<parity>{<bits>{<flow>}}} | ||
| 56 | |||
| 57 | where | ||
| 58 | |||
| 59 | baud - baud rate in decimal | ||
| 60 | parity - 'n' (none), 'o', (odd) or 'e' (even) | ||
| 61 | bits - number of data bits | ||
| 62 | flow - 'r' (rts) | ||
| 63 | |||
| 64 | For example: 115200n8r | ||
| 65 | |||
| 66 | Implementation note: Linux will look for the property "linux,stdout-path" or | ||
| 67 | on PowerPC "stdout" if "stdout-path" is not found. However, the | ||
| 68 | "linux,stdout-path" and "stdout" properties are deprecated. New platforms | ||
| 69 | should only use the "stdout-path" property. | ||
| 70 | |||
| 71 | linux,booted-from-kexec | ||
| 72 | ----------------------- | ||
| 73 | |||
| 74 | This property is set (currently only on PowerPC, and only needed on | ||
| 75 | book3e) by some versions of kexec-tools to tell the new kernel that it | ||
| 76 | is being booted by kexec, as the booting environment may differ (e.g. | ||
| 77 | a different secondary CPU release mechanism) | ||
| 78 | |||
| 79 | linux,usable-memory-range | ||
| 80 | ------------------------- | ||
| 81 | |||
| 82 | This property holds a base address and size, describing a limited region in | ||
| 83 | which memory may be considered available for use by the kernel. Memory outside | ||
| 84 | of this range is not available for use. | ||
| 85 | |||
| 86 | This property describes a limitation: memory within this range is only | ||
| 87 | valid when also described through another mechanism that the kernel | ||
| 88 | would otherwise use to determine available memory (e.g. memory nodes | ||
| 89 | or the EFI memory map). Valid memory may be sparse within the range. | ||
| 90 | e.g. | ||
| 91 | |||
| 92 | / { | ||
| 93 | chosen { | ||
| 94 | linux,usable-memory-range = <0x9 0xf0000000 0x0 0x10000000>; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | The main usage is for crash dump kernel to identify its own usable | ||
| 99 | memory and exclude, at its boot time, any other memory areas that are | ||
| 100 | part of the panicked kernel's memory. | ||
| 101 | |||
| 102 | While this property does not represent a real hardware, the address | ||
| 103 | and the size are expressed in #address-cells and #size-cells, | ||
| 104 | respectively, of the root node. | ||
| 105 | |||
| 106 | linux,elfcorehdr | ||
| 107 | ---------------- | ||
| 108 | |||
| 109 | This property holds the memory range, the address and the size, of the elf | ||
| 110 | core header which mainly describes the panicked kernel's memory layout as | ||
| 111 | PT_LOAD segments of elf format. | ||
| 112 | e.g. | ||
| 113 | |||
| 114 | / { | ||
| 115 | chosen { | ||
| 116 | linux,elfcorehdr = <0x9 0xfffff000 0x0 0x800>; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | While this property does not represent a real hardware, the address | ||
| 121 | and the size are expressed in #address-cells and #size-cells, | ||
| 122 | respectively, of the root node. | ||
| 123 | |||
| 124 | linux,initrd-start and linux,initrd-end | ||
| 125 | --------------------------------------- | ||
| 126 | |||
| 127 | These properties hold the physical start and end address of an initrd that's | ||
| 128 | loaded by the bootloader. Note that linux,initrd-start is inclusive, but | ||
| 129 | linux,initrd-end is exclusive. | ||
| 130 | e.g. | ||
| 131 | |||
| 132 | / { | ||
| 133 | chosen { | ||
| 134 | linux,initrd-start = <0x82000000>; | ||
| 135 | linux,initrd-end = <0x82800000>; | ||
| 136 | }; | ||
| 137 | }; | ||
| @@ -20,13 +20,24 @@ properties: · 19 unmodified lines | |||
| 20 | compatible: | 20 | compatible: |
| 21 | const: google,cros-ec-typec | 21 | const: google,cros-ec-typec |
| 22 | 22 | ||
| 23 | connector: | 23 | '#address-cells': |
| 24 | const: 1 | ||
| 25 | |||
| 26 | '#size-cells': | ||
| 27 | const: 0 | ||
| 28 | |||
| 29 | patternProperties: | ||
| 30 | '^connector@[0-9a-f]+$': | ||
| 24 | $ref: /schemas/connector/usb-connector.yaml# | 31 | $ref: /schemas/connector/usb-connector.yaml# |
| 32 | unevaluatedProperties: false | ||
| 33 | properties: | ||
| 34 | reg: | ||
| 35 | maxItems: 1 | ||
| 25 | 36 | ||
| 26 | required: | 37 | required: |
| 27 | - compatible | 38 | - compatible |
| 28 | 39 | ||
| 29 | additionalProperties: true #fixme | 40 | additionalProperties: false |
| 30 | 41 | ||
| 31 | examples: | 42 | examples: |
| 32 | - |+ | 43 | - |+ |
| @@ -0,0 +1,35 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: ChromeOS keyboard backlight LED driver. | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Tzung-Bi Shih <tzungbi@kernel.org> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | compatible: | ||
| 14 | const: google,cros-kbd-led-backlight | ||
| 15 | |||
| 16 | required: | ||
| 17 | - compatible | ||
| 18 | |||
| 19 | additionalProperties: false | ||
| 20 | |||
| 21 | examples: | ||
| 22 | - | | ||
| 23 | spi0 { | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | cros_ec: ec@0 { | ||
| 28 | compatible = "google,cros-ec-spi"; | ||
| 29 | reg = <0>; | ||
| 30 | |||
| 31 | kbd-led-backlight { | ||
| 32 | compatible = "google,cros-kbd-led-backlight"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
| @@ -28,6 +28,9 @@ properties: · 27 unmodified lines | |||
| 28 | - items: | 28 | - items: |
| 29 | - const: allwinner,sun8i-r40-de2-clk | 29 | - const: allwinner,sun8i-r40-de2-clk |
| 30 | - const: allwinner,sun8i-h3-de2-clk | 30 | - const: allwinner,sun8i-h3-de2-clk |
| 31 | - items: | ||
| 32 | - const: allwinner,sun20i-d1-de2-clk | ||
| 33 | - const: allwinner,sun50i-h5-de2-clk | ||
| 31 | 34 | ||
| 32 | reg: | 35 | reg: |
| 33 | maxItems: 1 | 36 | maxItems: 1 |
| @@ -1,11 +0,0 @@ | |||
| 1 | * Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Should be "efm32gg,cmu" | ||
| 5 | - reg: Base address and length of the register set | ||
| 6 | - interrupts: Interrupt used by the CMU | ||
| 7 | - #clock-cells: Should be <1> | ||
| 8 | |||
| 9 | The clock consumer should specify the desired clock by having the clock ID in | ||
| 10 | its "clocks" phandle cell. The header efm32-clk.h contains a list of available | ||
| 11 | IDs. | ||
| @@ -13,7 +13,6 @@ maintainers: · 12 unmodified lines | |||
| 13 | properties: | 13 | properties: |
| 14 | compatible: | 14 | compatible: |
| 15 | enum: | 15 | enum: |
| 16 | - allwinner,sun4i-a10-pll3-2x-clk | ||
| 17 | - fixed-factor-clock | 16 | - fixed-factor-clock |
| 18 | 17 | ||
| 19 | "#clock-cells": | 18 | "#clock-cells": |
| @@ -0,0 +1,43 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Abel Vesa <abel.vesa@nxp.com> | ||
| 11 | |||
| 12 | description: i.MX SCU Client Device Node | ||
| 13 | Client nodes are maintained as children of the relevant IMX-SCU device node. | ||
| 14 | This binding uses the common clock binding. | ||
| 15 | (Documentation/devicetree/bindings/clock/clock-bindings.txt) | ||
| 16 | The clock consumer should specify the desired clock by having the clock | ||
| 17 | ID in its "clocks" phandle cell. See the full list of clock IDs from | ||
| 18 | include/dt-bindings/clock/imx8qxp-clock.h | ||
| 19 | |||
| 20 | properties: | ||
| 21 | compatible: | ||
| 22 | items: | ||
| 23 | - enum: | ||
| 24 | - fsl,imx8dxl-clk | ||
| 25 | - fsl,imx8qm-clk | ||
| 26 | - fsl,imx8qxp-clk | ||
| 27 | - const: fsl,scu-clk | ||
| 28 | |||
| 29 | '#clock-cells': | ||
| 30 | const: 2 | ||
| 31 | |||
| 32 | required: | ||
| 33 | - compatible | ||
| 34 | - '#clock-cells' | ||
| 35 | |||
| 36 | additionalProperties: false | ||
| 37 | |||
| 38 | examples: | ||
| 39 | - | | ||
| 40 | clock-controller { | ||
| 41 | compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; | ||
| 42 | #clock-cells = <2>; | ||
| 43 | }; | ||
| @@ -0,0 +1,49 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Nuvoton NPCM8XX Clock Controller Binding | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Tomer Maimon <tmaimon77@gmail.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which | ||
| 14 | generates and supplies clocks to all modules within the BMC. | ||
| 15 | |||
| 16 | properties: | ||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nuvoton,npcm845-clk | ||
| 20 | |||
| 21 | reg: | ||
| 22 | maxItems: 1 | ||
| 23 | |||
| 24 | '#clock-cells': | ||
| 25 | const: 1 | ||
| 26 | description: | ||
| 27 | See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full | ||
| 28 | list of NPCM8XX clock IDs. | ||
| 29 | |||
| 30 | required: | ||
| 31 | - compatible | ||
| 32 | - reg | ||
| 33 | - '#clock-cells' | ||
| 34 | |||
| 35 | additionalProperties: false | ||
| 36 | |||
| 37 | examples: | ||
| 38 | - | | ||
| 39 | ahb { | ||
| 40 | #address-cells = <2>; | ||
| 41 | #size-cells = <2>; | ||
| 42 | |||
| 43 | clock-controller@f0801000 { | ||
| 44 | compatible = "nuvoton,npcm845-clk"; | ||
| 45 | reg = <0x0 0xf0801000 0x0 0x1000>; | ||
| 46 | #clock-cells = <1>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | ... | ||
| @@ -4,18 +4,19 @@ · 3 unmodified lines | |||
| 4 | $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# | 4 | $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 | 7 | title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Jonathan Marek <jonathan@marek.ca> | 10 | - Jonathan Marek <jonathan@marek.ca> |
| 11 | 11 | ||
| 12 | description: | | 12 | description: | |
| 13 | Qualcomm display clock control module which supports the clocks, resets and | 13 | Qualcomm display clock control module which supports the clocks, resets and |
| 14 | power domains on SM8150 and SM8250. | 14 | power domains on SM8150/SM8250/SM8350. |
| 15 | 15 | ||
| 16 | See also: | 16 | See also: |
| 17 | dt-bindings/clock/qcom,dispcc-sm8150.h | 17 | dt-bindings/clock/qcom,dispcc-sm8150.h |
| 18 | dt-bindings/clock/qcom,dispcc-sm8250.h | 18 | dt-bindings/clock/qcom,dispcc-sm8250.h |
| 19 | dt-bindings/clock/qcom,dispcc-sm8350.h | ||
| 19 | 20 | ||
| 20 | properties: | 21 | properties: |
| 21 | compatible: | 22 | compatible: |
| @@ -23,6 +24,7 @@ properties: · 1 unmodified line | |||
| 23 | - qcom,sc8180x-dispcc | 24 | - qcom,sc8180x-dispcc |
| 24 | - qcom,sm8150-dispcc | 25 | - qcom,sm8150-dispcc |
| 25 | - qcom,sm8250-dispcc | 26 | - qcom,sm8250-dispcc |
| 27 | - qcom,sm8350-dispcc | ||
| 26 | 28 | ||
| 27 | clocks: | 29 | clocks: |
| 28 | items: | 30 | items: |
| @@ -4,7 +4,7 @@ · 3 unmodified lines | |||
| 4 | $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml# | 4 | $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 | 7 | title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960 |
| 8 | 8 | ||
| 9 | allOf: | 9 | allOf: |
| 10 | - $ref: qcom,gcc.yaml# | 10 | - $ref: qcom,gcc.yaml# |
| @@ -23,11 +23,25 @@ description: | · 12 unmodified lines | |||
| 23 | 23 | ||
| 24 | properties: | 24 | properties: |
| 25 | compatible: | 25 | compatible: |
| 26 | const: qcom,gcc-apq8064 | 26 | oneOf: |
| 27 | - items: | ||
| 28 | - enum: | ||
| 29 | - qcom,gcc-apq8064 | ||
| 30 | - qcom,gcc-msm8960 | ||
| 31 | - const: syscon | ||
| 32 | - enum: | ||
| 33 | - qcom,gcc-apq8064 | ||
| 34 | - qcom,gcc-msm8960 | ||
| 35 | deprecated: true | ||
| 36 | |||
| 37 | thermal-sensor: | ||
| 38 | description: child tsens device | ||
| 39 | $ref: /schemas/thermal/qcom-tsens.yaml# | ||
| 27 | 40 | ||
| 28 | nvmem-cells: | 41 | nvmem-cells: |
| 29 | minItems: 1 | 42 | minItems: 1 |
| 30 | maxItems: 2 | 43 | maxItems: 2 |
| 44 | deprecated: true | ||
| 31 | description: | 45 | description: |
| 32 | Qualcomm TSENS (thermal sensor device) on some devices can | 46 | Qualcomm TSENS (thermal sensor device) on some devices can |
| 33 | be part of GCC and hence the TSENS properties can also be part | 47 | be part of GCC and hence the TSENS properties can also be part |
| @@ -37,31 +51,39 @@ properties: · 3 unmodified lines | |||
| 37 | 51 | ||
| 38 | nvmem-cell-names: | 52 | nvmem-cell-names: |
| 39 | minItems: 1 | 53 | minItems: 1 |
| 54 | deprecated: true | ||
| 40 | items: | 55 | items: |
| 41 | - const: calib | 56 | - const: calib |
| 42 | - const: calib_backup | 57 | - const: calib_backup |
| 43 | 58 | ||
| 44 | '#thermal-sensor-cells': | 59 | '#thermal-sensor-cells': |
| 45 | const: 1 | 60 | const: 1 |
| 61 | deprecated: true | ||
| 46 | 62 | ||
| 47 | required: | 63 | required: |
| 48 | - compatible | 64 | - compatible |
| 49 | - nvmem-cells | ||
| 50 | - nvmem-cell-names | ||
| 51 | - '#thermal-sensor-cells' | ||
| 52 | 65 | ||
| 53 | unevaluatedProperties: false | 66 | unevaluatedProperties: false |
| 54 | 67 | ||
| 55 | examples: | 68 | examples: |
| 56 | - | | 69 | - | |
| 57 | clock-controller@900000 { | 70 | clock-controller@900000 { |
| 58 | compatible = "qcom,gcc-apq8064"; | 71 | compatible = "qcom,gcc-apq8064", "syscon"; |
| 59 | reg = <0x00900000 0x4000>; | 72 | reg = <0x00900000 0x4000>; |
| 60 | nvmem-cells = <&tsens_calib>, <&tsens_backup>; | ||
| 61 | nvmem-cell-names = "calib", "calib_backup"; | ||
| 62 | #clock-cells = <1>; | 73 | #clock-cells = <1>; |
| 63 | #reset-cells = <1>; | 74 | #reset-cells = <1>; |
| 64 | #power-domain-cells = <1>; | 75 | #power-domain-cells = <1>; |
| 65 | #thermal-sensor-cells = <1>; | 76 | |
| 77 | thermal-sensor { | ||
| 78 | compatible = "qcom,msm8960-tsens"; | ||
| 79 | |||
| 80 | nvmem-cells = <&tsens_calib>, <&tsens_backup>; | ||
| 81 | nvmem-cell-names = "calib", "calib_backup"; | ||
| 82 | interrupts = <0 178 4>; | ||
| 83 | interrupt-names = "uplow"; | ||
| 84 | |||
| 85 | #qcom,sensors = <11>; | ||
| 86 | #thermal-sensor-cells = <1>; | ||
| 87 | }; | ||
| 66 | }; | 88 | }; |
| 67 | ... | 89 | ... |
| @@ -24,6 +24,9 @@ properties: · 23 unmodified lines | |||
| 24 | '#clock-cells': | 24 | '#clock-cells': |
| 25 | const: 1 | 25 | const: 1 |
| 26 | 26 | ||
| 27 | '#power-domain-cells': | ||
| 28 | const: 1 | ||
| 29 | |||
| 27 | '#reset-cells': | 30 | '#reset-cells': |
| 28 | const: 1 | 31 | const: 1 |
| 29 | 32 | ||
| @@ -38,6 +41,7 @@ required: · 8 unmodified lines | |||
| 38 | - compatible | 41 | - compatible |
| 39 | - reg | 42 | - reg |
| 40 | - '#clock-cells' | 43 | - '#clock-cells' |
| 44 | - '#power-domain-cells' | ||
| 41 | - '#reset-cells' | 45 | - '#reset-cells' |
| 42 | 46 | ||
| 43 | additionalProperties: false | 47 | additionalProperties: false |
| @@ -48,6 +52,7 @@ examples: · 4 unmodified lines | |||
| 48 | compatible = "qcom,gcc-ipq8074"; | 52 | compatible = "qcom,gcc-ipq8074"; |
| 49 | reg = <0x01800000 0x80000>; | 53 | reg = <0x01800000 0x80000>; |
| 50 | #clock-cells = <1>; | 54 | #clock-cells = <1>; |
| 55 | #power-domain-cells = <1>; | ||
| 51 | #reset-cells = <1>; | 56 | #reset-cells = <1>; |
| 52 | }; | 57 | }; |
| 53 | ... | 58 | ... |
| @@ -22,16 +22,32 @@ properties: · 21 unmodified lines | |||
| 22 | const: qcom,gcc-msm8996 | 22 | const: qcom,gcc-msm8996 |
| 23 | 23 | ||
| 24 | clocks: | 24 | clocks: |
| 25 | minItems: 3 | ||
| 25 | items: | 26 | items: |
| 26 | - description: XO source | 27 | - description: XO source |
| 27 | - description: Second XO source | 28 | - description: Second XO source |
| 28 | - description: Sleep clock source | 29 | - description: Sleep clock source |
| 30 | - description: PCIe 0 PIPE clock (optional) | ||
| 31 | - description: PCIe 1 PIPE clock (optional) | ||
| 32 | - description: PCIe 2 PIPE clock (optional) | ||
| 33 | - description: USB3 PIPE clock (optional) | ||
| 34 | - description: UFS RX symbol 0 clock (optional) | ||
| 35 | - description: UFS RX symbol 1 clock (optional) | ||
| 36 | - description: UFS TX symbol 0 clock (optional) | ||
| 29 | 37 | ||
| 30 | clock-names: | 38 | clock-names: |
| 39 | minItems: 3 | ||
| 31 | items: | 40 | items: |
| 32 | - const: cxo | 41 | - const: cxo |
| 33 | - const: cxo2 | 42 | - const: cxo2 |
| 34 | - const: sleep_clk | 43 | - const: sleep_clk |
| 44 | - const: pcie_0_pipe_clk_src | ||
| 45 | - const: pcie_1_pipe_clk_src | ||
| 46 | - const: pcie_2_pipe_clk_src | ||
| 47 | - const: usb3_phy_pipe_clk_src | ||
| 48 | - const: ufs_rx_symbol_0_clk_src | ||
| 49 | - const: ufs_rx_symbol_1_clk_src | ||
| 50 | - const: ufs_tx_symbol_0_clk_src | ||
| 35 | 51 | ||
| 36 | '#clock-cells': | 52 | '#clock-cells': |
| 37 | const: 1 | 53 | const: 1 |
| @@ -44,7 +44,6 @@ properties: · 43 unmodified lines | |||
| 44 | - qcom,gcc-msm8916 | 44 | - qcom,gcc-msm8916 |
| 45 | - qcom,gcc-msm8939 | 45 | - qcom,gcc-msm8939 |
| 46 | - qcom,gcc-msm8953 | 46 | - qcom,gcc-msm8953 |
| 47 | - qcom,gcc-msm8960 | ||
| 48 | - qcom,gcc-msm8974 | 47 | - qcom,gcc-msm8974 |
| 49 | - qcom,gcc-msm8974pro | 48 | - qcom,gcc-msm8974pro |
| 50 | - qcom,gcc-msm8974pro-ac | 49 | - qcom,gcc-msm8974pro-ac |
| @@ -58,10 +57,10 @@ required: · 7 unmodified lines | |||
| 58 | unevaluatedProperties: false | 57 | unevaluatedProperties: false |
| 59 | 58 | ||
| 60 | examples: | 59 | examples: |
| 61 | # Example for GCC for MSM8960: | 60 | # Example for GCC for MSM8974: |
| 62 | - | | 61 | - | |
| 63 | clock-controller@900000 { | 62 | clock-controller@900000 { |
| 64 | compatible = "qcom,gcc-msm8960"; | 63 | compatible = "qcom,gcc-msm8974"; |
| 65 | reg = <0x900000 0x4000>; | 64 | reg = <0x900000 0x4000>; |
| 66 | #clock-cells = <1>; | 65 | #clock-cells = <1>; |
| 67 | #reset-cells = <1>; | 66 | #reset-cells = <1>; |
| @@ -43,6 +43,9 @@ properties: · 42 unmodified lines | |||
| 43 | '#reset-cells': | 43 | '#reset-cells': |
| 44 | const: 1 | 44 | const: 1 |
| 45 | 45 | ||
| 46 | power-domains: | ||
| 47 | maxItems: 1 | ||
| 48 | |||
| 46 | '#power-domain-cells': | 49 | '#power-domain-cells': |
| 47 | const: 1 | 50 | const: 1 |
| 48 | 51 | ||
| @@ -0,0 +1,72 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Qualcomm Graphics Clock & Reset Controller Binding | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Robert Foss <robert.foss@linaro.org> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | Qualcomm graphics clock control module which supports the clocks, resets and | ||
| 14 | power domains on Qualcomm SoCs. | ||
| 15 | |||
| 16 | See also: | ||
| 17 | dt-bindings/clock/qcom,gpucc-sm8350.h | ||
| 18 | |||
| 19 | properties: | ||
| 20 | compatible: | ||
| 21 | enum: | ||
| 22 | - qcom,sm8350-gpucc | ||
| 23 | |||
| 24 | clocks: | ||
| 25 | items: | ||
| 26 | - description: Board XO source | ||
| 27 | - description: GPLL0 main branch source | ||
| 28 | - description: GPLL0 div branch source | ||
| 29 | |||
| 30 | '#clock-cells': | ||
| 31 | const: 1 | ||
| 32 | |||
| 33 | '#reset-cells': | ||
| 34 | const: 1 | ||
| 35 | |||
| 36 | '#power-domain-cells': | ||
| 37 | const: 1 | ||
| 38 | |||
| 39 | reg: | ||
| 40 | maxItems: 1 | ||
| 41 | |||
| 42 | required: | ||
| 43 | - compatible | ||
| 44 | - reg | ||
| 45 | - clocks | ||
| 46 | - '#clock-cells' | ||
| 47 | - '#reset-cells' | ||
| 48 | - '#power-domain-cells' | ||
| 49 | |||
| 50 | additionalProperties: false | ||
| 51 | |||
| 52 | examples: | ||
| 53 | - | | ||
| 54 | #include <dt-bindings/clock/qcom,gcc-sm8350.h> | ||
| 55 | #include <dt-bindings/clock/qcom,rpmh.h> | ||
| 56 | |||
| 57 | soc { | ||
| 58 | #address-cells = <2>; | ||
| 59 | #size-cells = <2>; | ||
| 60 | |||
| 61 | clock-controller@3d90000 { | ||
| 62 | compatible = "qcom,sm8350-gpucc"; | ||
| 63 | reg = <0 0x03d90000 0 0x9000>; | ||
| 64 | clocks = <&rpmhcc RPMH_CXO_CLK>, | ||
| 65 | <&gcc GCC_GPU_GPLL0_CLK_SRC>, | ||
| 66 | <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; | ||
| 67 | #clock-cells = <1>; | ||
| 68 | #reset-cells = <1>; | ||
| 69 | #power-domain-cells = <1>; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | ... | ||
| @@ -49,15 +49,86 @@ properties: · 48 unmodified lines | |||
| 49 | const: 1 | 49 | const: 1 |
| 50 | 50 | ||
| 51 | clocks: | 51 | clocks: |
| 52 | maxItems: 1 | 52 | minItems: 1 |
| 53 | maxItems: 2 | ||
| 53 | 54 | ||
| 54 | clock-names: | 55 | clock-names: |
| 55 | const: xo | 56 | minItems: 1 |
| 57 | maxItems: 2 | ||
| 56 | 58 | ||
| 57 | required: | 59 | required: |
| 58 | - compatible | 60 | - compatible |
| 59 | - '#clock-cells' | 61 | - '#clock-cells' |
| 60 | 62 | ||
| 63 | allOf: | ||
| 64 | - if: | ||
| 65 | properties: | ||
| 66 | compatible: | ||
| 67 | contains: | ||
| 68 | enum: | ||
| 69 | - qcom,rpmcc-apq8060 | ||
| 70 | - qcom,rpmcc-ipq806x | ||
| 71 | - qcom,rpmcc-msm8660 | ||
| 72 | |||
| 73 | then: | ||
| 74 | properties: | ||
| 75 | clocks: | ||
| 76 | items: | ||
| 77 | - description: pxo clock | ||
| 78 | |||
| 79 | clock-names: | ||
| 80 | items: | ||
| 81 | - const: pxo | ||
| 82 | |||
| 83 | - if: | ||
| 84 | properties: | ||
| 85 | compatible: | ||
| 86 | contains: | ||
| 87 | const: qcom,rpmcc-apq8064 | ||
| 88 | then: | ||
| 89 | properties: | ||
| 90 | clocks: | ||
| 91 | items: | ||
| 92 | - description: pxo clock | ||
| 93 | - description: cxo clock | ||
| 94 | |||
| 95 | clock-names: | ||
| 96 | items: | ||
| 97 | - const: pxo | ||
| 98 | - const: cxo | ||
| 99 | |||
| 100 | - if: | ||
| 101 | properties: | ||
| 102 | compatible: | ||
| 103 | contains: | ||
| 104 | enum: | ||
| 105 | - qcom,rpmcc-mdm9607 | ||
| 106 | - qcom,rpmcc-msm8226 | ||
| 107 | - qcom,rpmcc-msm8916 | ||
| 108 | - qcom,rpmcc-msm8936 | ||
| 109 | - qcom,rpmcc-msm8953 | ||
| 110 | - qcom,rpmcc-msm8974 | ||
| 111 | - qcom,rpmcc-msm8976 | ||
| 112 | - qcom,rpmcc-msm8992 | ||
| 113 | - qcom,rpmcc-msm8994 | ||
| 114 | - qcom,rpmcc-msm8996 | ||
| 115 | - qcom,rpmcc-msm8998 | ||
| 116 | - qcom,rpmcc-qcm2290 | ||
| 117 | - qcom,rpmcc-qcs404 | ||
| 118 | - qcom,rpmcc-sdm660 | ||
| 119 | - qcom,rpmcc-sm6115 | ||
| 120 | - qcom,rpmcc-sm6125 | ||
| 121 | |||
| 122 | then: | ||
| 123 | properties: | ||
| 124 | clocks: | ||
| 125 | items: | ||
| 126 | - description: xo clock | ||
| 127 | |||
| 128 | clock-names: | ||
| 129 | items: | ||
| 130 | - const: xo | ||
| 131 | |||
| 61 | additionalProperties: false | 132 | additionalProperties: false |
| 62 | 133 | ||
| 63 | examples: | 134 | examples: |
| @@ -73,3 +144,13 @@ examples: · 9 unmodified lines | |||
| 73 | }; | 144 | }; |
| 74 | }; | 145 | }; |
| 75 | }; | 146 | }; |
| 147 | |||
| 148 | - | | ||
| 149 | rpm { | ||
| 150 | clock-controller { | ||
| 151 | compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; | ||
| 152 | #clock-cells = <1>; | ||
| 153 | clocks = <&pxo_board>; | ||
| 154 | clock-names = "pxo"; | ||
| 155 | }; | ||
| 156 | }; | ||
| @@ -0,0 +1,80 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Qualcomm Camera Clock & Reset Controller Binding for SM8450 | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | Qualcomm camera clock control module which supports the clocks, resets and | ||
| 14 | power domains on SM8450. | ||
| 15 | |||
| 16 | See also include/dt-bindings/clock/qcom,sm8450-camcc.h | ||
| 17 | |||
| 18 | properties: | ||
| 19 | compatible: | ||
| 20 | const: qcom,sm8450-camcc | ||
| 21 | |||
| 22 | clocks: | ||
| 23 | items: | ||
| 24 | - description: Camera AHB clock from GCC | ||
| 25 | - description: Board XO source | ||
| 26 | - description: Board active XO source | ||
| 27 | - description: Sleep clock source | ||
| 28 | |||
| 29 | power-domains: | ||
| 30 | maxItems: 1 | ||
| 31 | description: | ||
| 32 | A phandle and PM domain specifier for the MMCX power domain. | ||
| 33 | |||
| 34 | required-opps: | ||
| 35 | description: | ||
| 36 | A phandle to an OPP node describing required MMCX performance point. | ||
| 37 | |||
| 38 | '#clock-cells': | ||
| 39 | const: 1 | ||
| 40 | |||
| 41 | '#reset-cells': | ||
| 42 | const: 1 | ||
| 43 | |||
| 44 | '#power-domain-cells': | ||
| 45 | const: 1 | ||
| 46 | |||
| 47 | reg: | ||
| 48 | maxItems: 1 | ||
| 49 | |||
| 50 | required: | ||
| 51 | - compatible | ||
| 52 | - reg | ||
| 53 | - clocks | ||
| 54 | - power-domains | ||
| 55 | - required-opps | ||
| 56 | - '#clock-cells' | ||
| 57 | - '#reset-cells' | ||
| 58 | - '#power-domain-cells' | ||
| 59 | |||
| 60 | additionalProperties: false | ||
| 61 | |||
| 62 | examples: | ||
| 63 | - | | ||
| 64 | #include <dt-bindings/clock/qcom,gcc-sm8450.h> | ||
| 65 | #include <dt-bindings/clock/qcom,rpmh.h> | ||
| 66 | #include <dt-bindings/power/qcom-rpmpd.h> | ||
| 67 | clock-controller@ade0000 { | ||
| 68 | compatible = "qcom,sm8450-camcc"; | ||
| 69 | reg = <0xade0000 0x20000>; | ||
| 70 | clocks = <&gcc GCC_CAMERA_AHB_CLK>, | ||
| 71 | <&rpmhcc RPMH_CXO_CLK>, | ||
| 72 | <&rpmhcc RPMH_CXO_CLK_A>, | ||
| 73 | <&sleep_clk>; | ||
| 74 | power-domains = <&rpmhpd SM8450_MMCX>; | ||
| 75 | required-opps = <&rpmhpd_opp_low_svs>; | ||
| 76 | #clock-cells = <1>; | ||
| 77 | #reset-cells = <1>; | ||
| 78 | #power-domain-cells = <1>; | ||
| 79 | }; | ||
| 80 | ... | ||
| @@ -45,10 +45,9 @@ properties: · 44 unmodified lines | |||
| 45 | description: | | 45 | description: | |
| 46 | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" | 46 | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" |
| 47 | and a core clock reference, as defined in | 47 | and a core clock reference, as defined in |
| 48 | <dt-bindings/clock/r9a0*-cpg.h> | 48 | <dt-bindings/clock/r9a0*-cpg.h>, |
| 49 | - For module clocks, the two clock specifier cells must be "CPG_MOD" and | 49 | - For module clocks, the two clock specifier cells must be "CPG_MOD" and |
| 50 | a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or | 50 | a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>. |
| 51 | <dt-bindings/clock/r9a09g011-cpg.h>. | ||
| 52 | const: 2 | 51 | const: 2 |
| 53 | 52 | ||
| 54 | '#power-domain-cells': | 53 | '#power-domain-cells': |
| @@ -62,7 +61,7 @@ properties: · 7 unmodified lines | |||
| 62 | '#reset-cells': | 61 | '#reset-cells': |
| 63 | description: | 62 | description: |
| 64 | The single reset specifier cell must be the module number, as defined in | 63 | The single reset specifier cell must be the module number, as defined in |
| 65 | the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>. | 64 | <dt-bindings/clock/r9a0*-cpg.h>. |
| 66 | const: 1 | 65 | const: 1 |
| 67 | 66 | ||
| 68 | required: | 67 | required: |
| @@ -33,6 +33,7 @@ properties: · 32 unmodified lines | |||
| 33 | enum: | 33 | enum: |
| 34 | - samsung,exynos7885-cmu-top | 34 | - samsung,exynos7885-cmu-top |
| 35 | - samsung,exynos7885-cmu-core | 35 | - samsung,exynos7885-cmu-core |
| 36 | - samsung,exynos7885-cmu-fsys | ||
| 36 | - samsung,exynos7885-cmu-peri | 37 | - samsung,exynos7885-cmu-peri |
| 37 | 38 | ||
| 38 | clocks: | 39 | clocks: |
| @@ -88,6 +89,32 @@ allOf: · 49 unmodified lines | |||
| 88 | - const: dout_core_cci | 89 | - const: dout_core_cci |
| 89 | - const: dout_core_g3d | 90 | - const: dout_core_g3d |
| 90 | 91 | ||
| 92 | - if: | ||
| 93 | properties: | ||
| 94 | compatible: | ||
| 95 | contains: | ||
| 96 | const: samsung,exynos7885-cmu-fsys | ||
| 97 | |||
| 98 | then: | ||
| 99 | properties: | ||
| 100 | clocks: | ||
| 101 | items: | ||
| 102 | - description: External reference clock (26 MHz) | ||
| 103 | - description: CMU_FSYS bus clock (from CMU_TOP) | ||
| 104 | - description: MMC_CARD clock (from CMU_TOP) | ||
| 105 | - description: MMC_EMBD clock (from CMU_TOP) | ||
| 106 | - description: MMC_SDIO clock (from CMU_TOP) | ||
| 107 | - description: USB30DRD clock (from CMU_TOP) | ||
| 108 | |||
| 109 | clock-names: | ||
| 110 | items: | ||
| 111 | - const: oscclk | ||
| 112 | - const: dout_fsys_bus | ||
| 113 | - const: dout_fsys_mmc_card | ||
| 114 | - const: dout_fsys_mmc_embd | ||
| 115 | - const: dout_fsys_mmc_sdio | ||
| 116 | - const: dout_fsys_usb30drd | ||
| 117 | |||
| 91 | - if: | 118 | - if: |
| 92 | properties: | 119 | properties: |
| 93 | compatible: | 120 | compatible: |
| @@ -0,0 +1,71 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | # Copyright 2022 Unisoc Inc. | ||
| 3 | %YAML 1.2 | ||
| 4 | --- | ||
| 5 | $id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#" | ||
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | ||
| 7 | |||
| 8 | title: UMS512 Soc clock controller | ||
| 9 | |||
| 10 | maintainers: | ||
| 11 | - Orson Zhai <orsonzhai@gmail.com> | ||
| 12 | - Baolin Wang <baolin.wang7@gmail.com> | ||
| 13 | - Chunyan Zhang <zhang.lyra@gmail.com> | ||
| 14 | |||
| 15 | properties: | ||
| 16 | compatible: | ||
| 17 | enum: | ||
| 18 | - sprd,ums512-apahb-gate | ||
| 19 | - sprd,ums512-ap-clk | ||
| 20 | - sprd,ums512-aonapb-clk | ||
| 21 | - sprd,ums512-pmu-gate | ||
| 22 | - sprd,ums512-g0-pll | ||
| 23 | - sprd,ums512-g2-pll | ||
| 24 | - sprd,ums512-g3-pll | ||
| 25 | - sprd,ums512-gc-pll | ||
| 26 | - sprd,ums512-aon-gate | ||
| 27 | - sprd,ums512-audcpapb-gate | ||
| 28 | - sprd,ums512-audcpahb-gate | ||
| 29 | - sprd,ums512-gpu-clk | ||
| 30 | - sprd,ums512-mm-clk | ||
| 31 | - sprd,ums512-mm-gate-clk | ||
| 32 | - sprd,ums512-apapb-gate | ||
| 33 | |||
| 34 | "#clock-cells": | ||
| 35 | const: 1 | ||
| 36 | |||
| 37 | clocks: | ||
| 38 | minItems: 1 | ||
| 39 | maxItems: 4 | ||
| 40 | description: | | ||
| 41 | The input parent clock(s) phandle for the clock, only list | ||
| 42 | fixed clocks which are declared in devicetree. | ||
| 43 | |||
| 44 | clock-names: | ||
| 45 | minItems: 1 | ||
| 46 | items: | ||
| 47 | - const: ext-26m | ||
| 48 | - const: ext-32k | ||
| 49 | - const: ext-4m | ||
| 50 | - const: rco-100m | ||
| 51 | |||
| 52 | reg: | ||
| 53 | maxItems: 1 | ||
| 54 | |||
| 55 | required: | ||
| 56 | - compatible | ||
| 57 | - '#clock-cells' | ||
| 58 | - reg | ||
| 59 | |||
| 60 | additionalProperties: false | ||
| 61 | |||
| 62 | examples: | ||
| 63 | - | | ||
| 64 | ap_clk: clock-controller@20200000 { | ||
| 65 | compatible = "sprd,ums512-ap-clk"; | ||
| 66 | reg = <0x20200000 0x1000>; | ||
| 67 | clocks = <&ext_26m>; | ||
| 68 | clock-names = "ext-26m"; | ||
| 69 | #clock-cells = <1>; | ||
| 70 | }; | ||
| 71 | ... | ||
| @@ -78,6 +78,7 @@ if: · 77 unmodified lines | |||
| 78 | contains: | 78 | contains: |
| 79 | enum: | 79 | enum: |
| 80 | - st,stm32mp1-rcc-secure | 80 | - st,stm32mp1-rcc-secure |
| 81 | - st,stm32mp13-rcc | ||
| 81 | then: | 82 | then: |
| 82 | properties: | 83 | properties: |
| 83 | clocks: | 84 | clocks: |
| @@ -78,7 +78,7 @@ Required properties: · 77 unmodified lines | |||
| 78 | - #clock-cells : from common clock binding; shall be set to 1 (multiple clock | 78 | - #clock-cells : from common clock binding; shall be set to 1 (multiple clock |
| 79 | outputs). | 79 | outputs). |
| 80 | 80 | ||
| 81 | - clocks : must be set to the parent's phandle. it's could be output clocks of | 81 | - clocks : must be set to the parent's phandle. it could be output clocks of |
| 82 | a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks) | 82 | a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks) |
| 83 | 83 | ||
| 84 | - clock-output-names : List of strings used to name the clock outputs. | 84 | - clock-output-names : List of strings used to name the clock outputs. |
| @@ -0,0 +1,52 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | # Copyright (C) Sunplus Co., Ltd. 2021 | ||
| 3 | %YAML 1.2 | ||
| 4 | --- | ||
| 5 | $id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# | ||
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 7 | |||
| 8 | title: Sunplus SP7021 SoC Clock Controller | ||
| 9 | |||
| 10 | maintainers: | ||
| 11 | - Qin Jian <qinjian@cqplus1.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | compatible: | ||
| 15 | const: sunplus,sp7021-clkc | ||
| 16 | |||
| 17 | reg: | ||
| 18 | maxItems: 3 | ||
| 19 | |||
| 20 | clocks: | ||
| 21 | maxItems: 1 | ||
| 22 | |||
| 23 | "#clock-cells": | ||
| 24 | const: 1 | ||
| 25 | |||
| 26 | required: | ||
| 27 | - compatible | ||
| 28 | - reg | ||
| 29 | - clocks | ||
| 30 | - "#clock-cells" | ||
| 31 | |||
| 32 | additionalProperties: false | ||
| 33 | |||
| 34 | examples: | ||
| 35 | - | | ||
| 36 | extclk: osc0 { | ||
| 37 | compatible = "fixed-clock"; | ||
| 38 | #clock-cells = <0>; | ||
| 39 | clock-frequency = <27000000>; | ||
| 40 | clock-output-names = "extclk"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | clkc: clock-controller@9c000004 { | ||
| 44 | compatible = "sunplus,sp7021-clkc"; | ||
| 45 | reg = <0x9c000004 0x28>, | ||
| 46 | <0x9c000200 0x44>, | ||
| 47 | <0x9c000268 0x08>; | ||
| 48 | clocks = <&extclk>; | ||
| 49 | #clock-cells = <1>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | ... | ||
| @@ -15,7 +15,7 @@ Required properties: · 14 unmodified lines | |||
| 15 | - for "ti,da850-pll1", shall be "clksrc" | 15 | - for "ti,da850-pll1", shall be "clksrc" |
| 16 | 16 | ||
| 17 | Optional properties: | 17 | Optional properties: |
| 18 | - ti,clkmode-square-wave: Indicates that the the board is supplying a square | 18 | - ti,clkmode-square-wave: Indicates that the board is supplying a square |
| 19 | wave input on the OSCIN pin instead of using a crystal oscillator. | 19 | wave input on the OSCIN pin instead of using a crystal oscillator. |
| 20 | This property is only valid when compatible = "ti,da850-pll0". | 20 | This property is only valid when compatible = "ti,da850-pll0". |
| 21 | 21 | ||
| @@ -6,7 +6,7 @@ functional clock but can be configured to provide different clocks. · 5 unmodified lines | |||
| 6 | ATL can maintain a clock averages to some desired frequency based on the bws/aws | 6 | ATL can maintain a clock averages to some desired frequency based on the bws/aws |
| 7 | signals - can compensate the drift between the two ws signal. | 7 | signals - can compensate the drift between the two ws signal. |
| 8 | 8 | ||
| 9 | In order to provide the support for ATL and it's output clocks (which can be used | 9 | In order to provide the support for ATL and its output clocks (which can be used |
| 10 | internally within the SoC or external components) two sets of bindings is needed: | 10 | internally within the SoC or external components) two sets of bindings is needed: |
| 11 | 11 | ||
| 12 | Clock tree binding: | 12 | Clock tree binding: |
| @@ -263,11 +263,11 @@ examples: · 262 unmodified lines | |||
| 263 | # Micro-USB connector with HS lines routed via controller (MUIC). | 263 | # Micro-USB connector with HS lines routed via controller (MUIC). |
| 264 | - | | 264 | - | |
| 265 | muic-max77843 { | 265 | muic-max77843 { |
| 266 | usb_con1: connector { | 266 | usb_con1: connector { |
| 267 | compatible = "usb-b-connector"; | 267 | compatible = "usb-b-connector"; |
| 268 | label = "micro-USB"; | 268 | label = "micro-USB"; |
| 269 | type = "micro"; | 269 | type = "micro"; |
| 270 | }; | 270 | }; |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | # USB-C connector attached to CC controller (s2mm005), HS lines routed | 273 | # USB-C connector attached to CC controller (s2mm005), HS lines routed |
| @@ -275,34 +275,34 @@ examples: · 1 unmodified line | |||
| 275 | # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. | 275 | # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. |
| 276 | - | | 276 | - | |
| 277 | ccic: s2mm005 { | 277 | ccic: s2mm005 { |
| 278 | usb_con2: connector { | 278 | usb_con2: connector { |
| 279 | compatible = "usb-c-connector"; | 279 | compatible = "usb-c-connector"; |
| 280 | label = "USB-C"; | 280 | label = "USB-C"; |
| 281 | 281 | ||
| 282 | ports { | 282 | ports { |
| 283 | #address-cells = <1>; | 283 | #address-cells = <1>; |
| 284 | #size-cells = <0>; | 284 | #size-cells = <0>; |
| 285 | 285 | ||
| 286 | port@0 { | 286 | port@0 { |
| 287 | reg = <0>; | 287 | reg = <0>; |
| 288 | usb_con_hs: endpoint { | 288 | usb_con_hs: endpoint { |
| 289 | remote-endpoint = <&max77865_usbc_hs>; | 289 | remote-endpoint = <&max77865_usbc_hs>; |
| 290 | }; | 290 | }; |
| 291 | }; | 291 | }; |
| 292 | port@1 { | 292 | port@1 { |
| 293 | reg = <1>; | 293 | reg = <1>; |
| 294 | usb_con_ss: endpoint { | 294 | usb_con_ss: endpoint { |
| 295 | remote-endpoint = <&usbdrd_phy_ss>; | 295 | remote-endpoint = <&usbdrd_phy_ss>; |
| 296 | }; | 296 | }; |
| 297 | }; | 297 | }; |
| 298 | port@2 { | 298 | port@2 { |
| 299 | reg = <2>; | 299 | reg = <2>; |
| 300 | usb_con_sbu: endpoint { | 300 | usb_con_sbu: endpoint { |
| 301 | remote-endpoint = <&dp_aux>; | 301 | remote-endpoint = <&dp_aux>; |
| 302 | }; | ||
| 303 | }; | ||
| 302 | }; | 304 | }; |
| 303 | }; | ||
| 304 | }; | 305 | }; |
| 305 | }; | ||
| 306 | }; | 306 | }; |
| 307 | 307 | ||
| 308 | # USB-C connector attached to a typec port controller(ptn5110), which has | 308 | # USB-C connector attached to a typec port controller(ptn5110), which has |
| @@ -310,16 +310,16 @@ examples: · 1 unmodified line | |||
| 310 | - | | 310 | - | |
| 311 | #include <dt-bindings/usb/pd.h> | 311 | #include <dt-bindings/usb/pd.h> |
| 312 | typec: ptn5110 { | 312 | typec: ptn5110 { |
| 313 | usb_con3: connector { | 313 | usb_con3: connector { |
| 314 | compatible = "usb-c-connector"; | 314 | compatible = "usb-c-connector"; |
| 315 | label = "USB-C"; | 315 | label = "USB-C"; |
| 316 | power-role = "dual"; | 316 | power-role = "dual"; |
| 317 | try-power-role = "sink"; | 317 | try-power-role = "sink"; |
| 318 | source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; | 318 | source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; |
| 319 | sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM) | 319 | sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM) |
| 320 | PDO_VAR(5000, 12000, 2000)>; | 320 | PDO_VAR(5000, 12000, 2000)>; |
| 321 | op-sink-microwatt = <10000000>; | 321 | op-sink-microwatt = <10000000>; |
| 322 | }; | 322 | }; |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | # USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220) | 325 | # USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220) |
| @@ -332,20 +332,20 @@ examples: · 6 unmodified lines | |||
| 332 | data-role = "dual"; | 332 | data-role = "dual"; |
| 333 | 333 | ||
| 334 | ports { | 334 | ports { |
| 335 | #address-cells = <1>; | 335 | #address-cells = <1>; |
| 336 | #size-cells = <0>; | 336 | #size-cells = <0>; |
| 337 | port@0 { | 337 | port@0 { |
| 338 | reg = <0>; | 338 | reg = <0>; |
| 339 | hs_ep: endpoint { | 339 | hs_ep: endpoint { |
| 340 | remote-endpoint = <&usb3_hs_ep>; | 340 | remote-endpoint = <&usb3_hs_ep>; |
| 341 | }; | ||
| 342 | }; | 341 | }; |
| 343 | port@1 { | 342 | }; |
| 344 | reg = <1>; | 343 | port@1 { |
| 345 | ss_ep: endpoint { | 344 | reg = <1>; |
| 346 | remote-endpoint = <&hd3ss3220_in_ep>; | 345 | ss_ep: endpoint { |
| 347 | }; | 346 | remote-endpoint = <&hd3ss3220_in_ep>; |
| 348 | }; | 347 | }; |
| 348 | }; | ||
| 349 | }; | 349 | }; |
| 350 | }; | 350 | }; |
| 351 | 351 | ||
| @@ -354,12 +354,12 @@ examples: · 2 unmodified lines | |||
| 354 | #include <dt-bindings/gpio/gpio.h> | 354 | #include <dt-bindings/gpio/gpio.h> |
| 355 | 355 | ||
| 356 | usb { | 356 | usb { |
| 357 | connector { | 357 | connector { |
| 358 | compatible = "gpio-usb-b-connector", "usb-b-connector"; | 358 | compatible = "gpio-usb-b-connector", "usb-b-connector"; |
| 359 | type = "micro"; | 359 | type = "micro"; |
| 360 | id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>; | 360 | id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>; |
| 361 | vbus-supply = <&usb_p0_vbus>; | 361 | vbus-supply = <&usb_p0_vbus>; |
| 362 | }; | 362 | }; |
| 363 | }; | 363 | }; |
| 364 | 364 | ||
| 365 | # Micro-USB connector with HS lines routed via controller (MUIC) and MHL | 365 | # Micro-USB connector with HS lines routed via controller (MUIC) and MHL |
| @@ -367,27 +367,27 @@ examples: · 1 unmodified line | |||
| 367 | # mobile phone | 367 | # mobile phone |
| 368 | - | | 368 | - | |
| 369 | muic-max77843 { | 369 | muic-max77843 { |
| 370 | usb_con4: connector { | 370 | usb_con4: connector { |
| 371 | compatible = "samsung,usb-connector-11pin", "usb-b-connector"; | 371 | compatible = "samsung,usb-connector-11pin", "usb-b-connector"; |
| 372 | label = "micro-USB"; | 372 | label = "micro-USB"; |
| 373 | type = "micro"; | 373 | type = "micro"; |
| 374 | 374 | ||
| 375 | ports { | 375 | ports { |
| 376 | #address-cells = <1>; | 376 | #address-cells = <1>; |
| 377 | #size-cells = <0>; | 377 | #size-cells = <0>; |
| 378 | 378 | ||
| 379 | port@0 { | 379 | port@0 { |
| 380 | reg = <0>; | 380 | reg = <0>; |
| 381 | muic_to_usb: endpoint { | 381 | muic_to_usb: endpoint { |
| 382 | remote-endpoint = <&usb_to_muic>; | 382 | remote-endpoint = <&usb_to_muic>; |
| 383 | }; | 383 | }; |
| 384 | }; | 384 | }; |
| 385 | port@3 { | 385 | port@3 { |
| 386 | reg = <3>; | 386 | reg = <3>; |
| 387 | usb_con_mhl: endpoint { | 387 | usb_con_mhl: endpoint { |
| 388 | remote-endpoint = <&sii8620_mhl>; | 388 | remote-endpoint = <&sii8620_mhl>; |
| 389 | }; | ||
| 390 | }; | ||
| 389 | }; | 391 | }; |
| 390 | }; | ||
| 391 | }; | 392 | }; |
| 392 | }; | ||
| 393 | }; | 393 | }; |
| @@ -25,6 +25,7 @@ properties: · 24 unmodified lines | |||
| 25 | - description: v2 of CPUFREQ HW (EPSS) | 25 | - description: v2 of CPUFREQ HW (EPSS) |
| 26 | items: | 26 | items: |
| 27 | - enum: | 27 | - enum: |
| 28 | - qcom,sm6375-cpufreq-epss | ||
| 28 | - qcom,sm8250-cpufreq-epss | 29 | - qcom,sm8250-cpufreq-epss |
| 29 | - const: qcom,cpufreq-epss | 30 | - const: qcom,cpufreq-epss |
| 30 | 31 | ||
| @@ -22,6 +22,13 @@ select: · 21 unmodified lines | |||
| 22 | compatible: | 22 | compatible: |
| 23 | contains: | 23 | contains: |
| 24 | enum: | 24 | enum: |
| 25 | - qcom,apq8064 | ||
| 26 | - qcom,apq8096 | ||
| 27 | - qcom,ipq8064 | ||
| 28 | - qcom,msm8939 | ||
| 29 | - qcom,msm8960 | ||
| 30 | - qcom,msm8974 | ||
| 31 | - qcom,msm8996 | ||
| 25 | - qcom,qcs404 | 32 | - qcom,qcs404 |
| 26 | required: | 33 | required: |
| 27 | - compatible | 34 | - compatible |
| @@ -63,8 +70,8 @@ additionalProperties: true · 35 unmodified lines | |||
| 63 | examples: | 70 | examples: |
| 64 | - | | 71 | - | |
| 65 | / { | 72 | / { |
| 66 | model = "Qualcomm Technologies, Inc. QCS404"; | 73 | model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; |
| 67 | compatible = "qcom,qcs404"; | 74 | compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404"; |
| 68 | #address-cells = <2>; | 75 | #address-cells = <2>; |
| 69 | #size-cells = <2>; | 76 | #size-cells = <2>; |
| 70 | 77 | ||
| @@ -1,488 +0,0 @@ | |||
| 1 | * Generic Exynos Bus frequency device | ||
| 2 | |||
| 3 | The Samsung Exynos SoC has many buses for data transfer between DRAM | ||
| 4 | and sub-blocks in SoC. Most Exynos SoCs share the common architecture | ||
| 5 | for buses. Generally, each bus of Exynos SoC includes a source clock | ||
| 6 | and a power line, which are able to change the clock frequency | ||
| 7 | of the bus in runtime. To monitor the usage of each bus in runtime, | ||
| 8 | the driver uses the PPMU (Platform Performance Monitoring Unit), which | ||
| 9 | is able to measure the current load of sub-blocks. | ||
| 10 | |||
| 11 | The Exynos SoC includes the various sub-blocks which have the each AXI bus. | ||
| 12 | The each AXI bus has the owned source clock but, has not the only owned | ||
| 13 | power line. The power line might be shared among one more sub-blocks. | ||
| 14 | So, we can divide into two type of device as the role of each sub-block. | ||
| 15 | There are two type of bus devices as following: | ||
| 16 | - parent bus device | ||
| 17 | - passive bus device | ||
| 18 | |||
| 19 | Basically, parent and passive bus device share the same power line. | ||
| 20 | The parent bus device can only change the voltage of shared power line | ||
| 21 | and the rest bus devices (passive bus device) depend on the decision of | ||
| 22 | the parent bus device. If there are three blocks which share the VDD_xxx | ||
| 23 | power line, Only one block should be parent device and then the rest blocks | ||
| 24 | should depend on the parent device as passive device. | ||
| 25 | |||
| 26 | VDD_xxx |--- A block (parent) | ||
| 27 | |--- B block (passive) | ||
| 28 | |--- C block (passive) | ||
| 29 | |||
| 30 | There are a little different composition among Exynos SoC because each Exynos | ||
| 31 | SoC has different sub-blocks. Therefore, such difference should be specified | ||
| 32 | in devicetree file instead of each device driver. In result, this driver | ||
| 33 | is able to support the bus frequency for all Exynos SoCs. | ||
| 34 | |||
| 35 | Required properties for all bus devices: | ||
| 36 | - compatible: Should be "samsung,exynos-bus". | ||
| 37 | - clock-names : the name of clock used by the bus, "bus". | ||
| 38 | - clocks : phandles for clock specified in "clock-names" property. | ||
| 39 | - operating-points-v2: the OPP table including frequency/voltage information | ||
| 40 | to support DVFS (Dynamic Voltage/Frequency Scaling) feature. | ||
| 41 | |||
| 42 | Required properties only for parent bus device: | ||
| 43 | - vdd-supply: the regulator to provide the buses with the voltage. | ||
| 44 | - devfreq-events: the devfreq-event device to monitor the current utilization | ||
| 45 | of buses. | ||
| 46 | |||
| 47 | Required properties only for passive bus device: | ||
| 48 | - devfreq: the parent bus device. | ||
| 49 | |||
| 50 | Optional properties only for parent bus device: | ||
| 51 | - exynos,saturation-ratio: the percentage value which is used to calibrate | ||
| 52 | the performance count against total cycle count. | ||
| 53 | |||
| 54 | Optional properties for the interconnect functionality (QoS frequency | ||
| 55 | constraints): | ||
| 56 | - #interconnect-cells: should be 0. | ||
| 57 | - interconnects: as documented in ../interconnect.txt, describes a path at the | ||
| 58 | higher level interconnects used by this interconnect provider. | ||
| 59 | If this interconnect provider is directly linked to a top level interconnect | ||
| 60 | provider the property contains only one phandle. The provider extends | ||
| 61 | the interconnect graph by linking its node to a node registered by provider | ||
| 62 | pointed to by first phandle in the 'interconnects' property. | ||
| 63 | |||
| 64 | - samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data | ||
| 65 | clock frequency in Hz, default value is 8 when this property is missing. | ||
| 66 | |||
| 67 | Detailed correlation between sub-blocks and power line according to Exynos SoC: | ||
| 68 | - In case of Exynos3250, there are two power line as following: | ||
| 69 | VDD_MIF |--- DMC | ||
| 70 | |||
| 71 | VDD_INT |--- LEFTBUS (parent device) | ||
| 72 | |--- PERIL | ||
| 73 | |--- MFC | ||
| 74 | |--- G3D | ||
| 75 | |--- RIGHTBUS | ||
| 76 | |--- PERIR | ||
| 77 | |--- FSYS | ||
| 78 | |--- LCD0 | ||
| 79 | |--- PERIR | ||
| 80 | |--- ISP | ||
| 81 | |--- CAM | ||
| 82 | |||
| 83 | - In case of Exynos4210, there is one power line as following: | ||
| 84 | VDD_INT |--- DMC (parent device) | ||
| 85 | |--- LEFTBUS | ||
| 86 | |--- PERIL | ||
| 87 | |--- MFC(L) | ||
| 88 | |--- G3D | ||
| 89 | |--- TV | ||
| 90 | |--- LCD0 | ||
| 91 | |--- RIGHTBUS | ||
| 92 | |--- PERIR | ||
| 93 | |--- MFC(R) | ||
| 94 | |--- CAM | ||
| 95 | |--- FSYS | ||
| 96 | |--- GPS | ||
| 97 | |--- LCD0 | ||
| 98 | |--- LCD1 | ||
| 99 | |||
| 100 | - In case of Exynos4x12, there are two power line as following: | ||
| 101 | VDD_MIF |--- DMC | ||
| 102 | |||
| 103 | VDD_INT |--- LEFTBUS (parent device) | ||
| 104 | |--- PERIL | ||
| 105 | |--- MFC(L) | ||
| 106 | |--- G3D | ||
| 107 | |--- TV | ||
| 108 | |--- IMAGE | ||
| 109 | |--- RIGHTBUS | ||
| 110 | |--- PERIR | ||
| 111 | |--- MFC(R) | ||
| 112 | |--- CAM | ||
| 113 | |--- FSYS | ||
| 114 | |--- GPS | ||
| 115 | |--- LCD0 | ||
| 116 | |--- ISP | ||
| 117 | |||
| 118 | - In case of Exynos5422, there are two power line as following: | ||
| 119 | VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller) | ||
| 120 | |--- DREX 1 | ||
| 121 | |||
| 122 | VDD_INT |--- NoC_Core (parent device) | ||
| 123 | |--- G2D | ||
| 124 | |--- G3D | ||
| 125 | |--- DISP1 | ||
| 126 | |--- NoC_WCORE | ||
| 127 | |--- GSCL | ||
| 128 | |--- MSCL | ||
| 129 | |--- ISP | ||
| 130 | |--- MFC | ||
| 131 | |--- GEN | ||
| 132 | |--- PERIS | ||
| 133 | |--- PERIC | ||
| 134 | |--- FSYS | ||
| 135 | |--- FSYS2 | ||
| 136 | |||
| 137 | - In case of Exynos5433, there is VDD_INT power line as following: | ||
| 138 | VDD_INT |--- G2D (parent device) | ||
| 139 | |--- MSCL | ||
| 140 | |--- GSCL | ||
| 141 | |--- JPEG | ||
| 142 | |--- MFC | ||
| 143 | |--- HEVC | ||
| 144 | |--- BUS0 | ||
| 145 | |--- BUS1 | ||
| 146 | |--- BUS2 | ||
| 147 | |--- PERIS (Fixed clock rate) | ||
| 148 | |--- PERIC (Fixed clock rate) | ||
| 149 | |--- FSYS (Fixed clock rate) | ||
| 150 | |||
| 151 | Example 1: | ||
| 152 | Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to | ||
| 153 | power line (regulator). The MIF (Memory Interface) AXI bus is used to | ||
| 154 | transfer data between DRAM and CPU and uses the VDD_MIF regulator. | ||
| 155 | |||
| 156 | - MIF (Memory Interface) block | ||
| 157 | : VDD_MIF |--- DMC (Dynamic Memory Controller) | ||
| 158 | |||
| 159 | - INT (Internal) block | ||
| 160 | : VDD_INT |--- LEFTBUS (parent device) | ||
| 161 | |--- PERIL | ||
| 162 | |--- MFC | ||
| 163 | |--- G3D | ||
| 164 | |--- RIGHTBUS | ||
| 165 | |--- FSYS | ||
| 166 | |--- LCD0 | ||
| 167 | |--- PERIR | ||
| 168 | |--- ISP | ||
| 169 | |--- CAM | ||
| 170 | |||
| 171 | - MIF bus's frequency/voltage table | ||
| 172 | ----------------------- | ||
| 173 | |Lv| Freq | Voltage | | ||
| 174 | ----------------------- | ||
| 175 | |L1| 50000 |800000 | | ||
| 176 | |L2| 100000 |800000 | | ||
| 177 | |L3| 134000 |800000 | | ||
| 178 | |L4| 200000 |825000 | | ||
| 179 | |L5| 400000 |875000 | | ||
| 180 | ----------------------- | ||
| 181 | |||
| 182 | - INT bus's frequency/voltage table | ||
| 183 | ---------------------------------------------------------- | ||
| 184 | |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT | | ||
| 185 | | name| |LCD0 | | | || | | ||
| 186 | | | |FSYS | | | || | | ||
| 187 | | | |MFC | | | || | | ||
| 188 | ---------------------------------------------------------- | ||
| 189 | |Mode |*parent|passive |passive|passive|passive|| | | ||
| 190 | ---------------------------------------------------------- | ||
| 191 | |Lv |Frequency ||Voltage | | ||
| 192 | ---------------------------------------------------------- | ||
| 193 | |L1 |50000 |50000 |50000 |50000 |50000 ||900000 | | ||
| 194 | |L2 |80000 |80000 |80000 |80000 |80000 ||900000 | | ||
| 195 | |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 | | ||
| 196 | |L4 |134000 |134000 |200000 |200000 | ||1000000 | | ||
| 197 | |L5 |200000 |200000 |400000 |300000 | ||1000000 | | ||
| 198 | ---------------------------------------------------------- | ||
| 199 | |||
| 200 | Example 2: | ||
| 201 | The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi | ||
| 202 | is listed below: | ||
| 203 | |||
| 204 | bus_dmc: bus_dmc { | ||
| 205 | compatible = "samsung,exynos-bus"; | ||
| 206 | clocks = <&cmu_dmc CLK_DIV_DMC>; | ||
| 207 | clock-names = "bus"; | ||
| 208 | operating-points-v2 = <&bus_dmc_opp_table>; | ||
| 209 | status = "disabled"; | ||
| 210 | }; | ||
| 211 | |||
| 212 | bus_dmc_opp_table: opp_table1 { | ||
| 213 | compatible = "operating-points-v2"; | ||
| 214 | opp-shared; | ||
| 215 | |||
| 216 | opp-50000000 { | ||
| 217 | opp-hz = /bits/ 64 <50000000>; | ||
| 218 | opp-microvolt = <800000>; | ||
| 219 | }; | ||
| 220 | opp-100000000 { | ||
| 221 | opp-hz = /bits/ 64 <100000000>; | ||
| 222 | opp-microvolt = <800000>; | ||
| 223 | }; | ||
| 224 | opp-134000000 { | ||
| 225 | opp-hz = /bits/ 64 <134000000>; | ||
| 226 | opp-microvolt = <800000>; | ||
| 227 | }; | ||
| 228 | opp-200000000 { | ||
| 229 | opp-hz = /bits/ 64 <200000000>; | ||
| 230 | opp-microvolt = <825000>; | ||
| 231 | }; | ||
| 232 | opp-400000000 { | ||
| 233 | opp-hz = /bits/ 64 <400000000>; | ||
| 234 | opp-microvolt = <875000>; | ||
| 235 | }; | ||
| 236 | }; | ||
| 237 | |||
| 238 | bus_leftbus: bus_leftbus { | ||
| 239 | compatible = "samsung,exynos-bus"; | ||
| 240 | clocks = <&cmu CLK_DIV_GDL>; | ||
| 241 | clock-names = "bus"; | ||
| 242 | operating-points-v2 = <&bus_leftbus_opp_table>; | ||
| 243 | status = "disabled"; | ||
| 244 | }; | ||
| 245 | |||
| 246 | bus_rightbus: bus_rightbus { | ||
| 247 | compatible = "samsung,exynos-bus"; | ||
| 248 | clocks = <&cmu CLK_DIV_GDR>; | ||
| 249 | clock-names = "bus"; | ||
| 250 | operating-points-v2 = <&bus_leftbus_opp_table>; | ||
| 251 | status = "disabled"; | ||
| 252 | }; | ||
| 253 | |||
| 254 | bus_lcd0: bus_lcd0 { | ||
| 255 | compatible = "samsung,exynos-bus"; | ||
| 256 | clocks = <&cmu CLK_DIV_ACLK_160>; | ||
| 257 | clock-names = "bus"; | ||
| 258 | operating-points-v2 = <&bus_leftbus_opp_table>; | ||
| 259 | status = "disabled"; | ||
| 260 | }; | ||
| 261 | |||
| 262 | bus_fsys: bus_fsys { | ||
| 263 | compatible = "samsung,exynos-bus"; | ||
| 264 | clocks = <&cmu CLK_DIV_ACLK_200>; | ||
| 265 | clock-names = "bus"; | ||
| 266 | operating-points-v2 = <&bus_leftbus_opp_table>; | ||
| 267 | status = "disabled"; | ||
| 268 | }; | ||
| 269 | |||
| 270 | bus_mcuisp: bus_mcuisp { | ||
| 271 | compatible = "samsung,exynos-bus"; | ||
| 272 | clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; | ||
| 273 | clock-names = "bus"; | ||
| 274 | operating-points-v2 = <&bus_mcuisp_opp_table>; | ||
| 275 | status = "disabled"; | ||
| 276 | }; | ||
| 277 | |||
| 278 | bus_isp: bus_isp { | ||
| 279 | compatible = "samsung,exynos-bus"; | ||
| 280 | clocks = <&cmu CLK_DIV_ACLK_266>; | ||
| 281 | clock-names = "bus"; | ||
| 282 | operating-points-v2 = <&bus_isp_opp_table>; | ||
| 283 | status = "disabled"; | ||
| 284 | }; | ||
| 285 | |||
| 286 | bus_peril: bus_peril { | ||
| 287 | compatible = "samsung,exynos-bus"; | ||
| 288 | clocks = <&cmu CLK_DIV_ACLK_100>; | ||
| 289 | clock-names = "bus"; | ||
| 290 | operating-points-v2 = <&bus_peril_opp_table>; | ||
| 291 | status = "disabled"; | ||
| 292 | }; | ||
| 293 | |||
| 294 | bus_mfc: bus_mfc { | ||
| 295 | compatible = "samsung,exynos-bus"; | ||
| 296 | clocks = <&cmu CLK_SCLK_MFC>; | ||
| 297 | clock-names = "bus"; | ||
| 298 | operating-points-v2 = <&bus_leftbus_opp_table>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | bus_leftbus_opp_table: opp_table1 { | ||
| 303 | compatible = "operating-points-v2"; | ||
| 304 | opp-shared; | ||
| 305 | |||
| 306 | opp-50000000 { | ||
| 307 | opp-hz = /bits/ 64 <50000000>; | ||
| 308 | opp-microvolt = <900000>; | ||
| 309 | }; | ||
| 310 | opp-80000000 { | ||
| 311 | opp-hz = /bits/ 64 <80000000>; | ||
| 312 | opp-microvolt = <900000>; | ||
| 313 | }; | ||
| 314 | opp-100000000 { | ||
| 315 | opp-hz = /bits/ 64 <100000000>; | ||
| 316 | opp-microvolt = <1000000>; | ||
| 317 | }; | ||
| 318 | opp-134000000 { | ||
| 319 | opp-hz = /bits/ 64 <134000000>; | ||
| 320 | opp-microvolt = <1000000>; | ||
| 321 | }; | ||
| 322 | opp-200000000 { | ||
| 323 | opp-hz = /bits/ 64 <200000000>; | ||
| 324 | opp-microvolt = <1000000>; | ||
| 325 | }; | ||
| 326 | }; | ||
| 327 | |||
| 328 | bus_mcuisp_opp_table: opp_table2 { | ||
| 329 | compatible = "operating-points-v2"; | ||
| 330 | opp-shared; | ||
| 331 | |||
| 332 | opp-50000000 { | ||
| 333 | opp-hz = /bits/ 64 <50000000>; | ||
| 334 | }; | ||
| 335 | opp-80000000 { | ||
| 336 | opp-hz = /bits/ 64 <80000000>; | ||
| 337 | }; | ||
| 338 | opp-100000000 { | ||
| 339 | opp-hz = /bits/ 64 <100000000>; | ||
| 340 | }; | ||
| 341 | opp-200000000 { | ||
| 342 | opp-hz = /bits/ 64 <200000000>; | ||
| 343 | }; | ||
| 344 | opp-400000000 { | ||
| 345 | opp-hz = /bits/ 64 <400000000>; | ||
| 346 | }; | ||
| 347 | }; | ||
| 348 | |||
| 349 | bus_isp_opp_table: opp_table3 { | ||
| 350 | compatible = "operating-points-v2"; | ||
| 351 | opp-shared; | ||
| 352 | |||
| 353 | opp-50000000 { | ||
| 354 | opp-hz = /bits/ 64 <50000000>; | ||
| 355 | }; | ||
| 356 | opp-80000000 { | ||
| 357 | opp-hz = /bits/ 64 <80000000>; | ||
| 358 | }; | ||
| 359 | opp-100000000 { | ||
| 360 | opp-hz = /bits/ 64 <100000000>; | ||
| 361 | }; | ||
| 362 | opp-200000000 { | ||
| 363 | opp-hz = /bits/ 64 <200000000>; | ||
| 364 | }; | ||
| 365 | opp-300000000 { | ||
| 366 | opp-hz = /bits/ 64 <300000000>; | ||
| 367 | }; | ||
| 368 | }; | ||
| 369 | |||
| 370 | bus_peril_opp_table: opp_table4 { | ||
| 371 | compatible = "operating-points-v2"; | ||
| 372 | opp-shared; | ||
| 373 | |||
| 374 | opp-50000000 { | ||
| 375 | opp-hz = /bits/ 64 <50000000>; | ||
| 376 | }; | ||
| 377 | opp-80000000 { | ||
| 378 | opp-hz = /bits/ 64 <80000000>; | ||
| 379 | }; | ||
| 380 | opp-100000000 { | ||
| 381 | opp-hz = /bits/ 64 <100000000>; | ||
| 382 | }; | ||
| 383 | }; | ||
| 384 | |||
| 385 | |||
| 386 | Usage case to handle the frequency and voltage of bus on runtime | ||
| 387 | in exynos3250-rinato.dts is listed below: | ||
| 388 | |||
| 389 | &bus_dmc { | ||
| 390 | devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; | ||
| 391 | vdd-supply = <&buck1_reg>; /* VDD_MIF */ | ||
| 392 | status = "okay"; | ||
| 393 | }; | ||
| 394 | |||
| 395 | &bus_leftbus { | ||
| 396 | devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; | ||
| 397 | vdd-supply = <&buck3_reg>; | ||
| 398 | status = "okay"; | ||
| 399 | }; | ||
| 400 | |||
| 401 | &bus_rightbus { | ||
| 402 | devfreq = <&bus_leftbus>; | ||
| 403 | status = "okay"; | ||
| 404 | }; | ||
| 405 | |||
| 406 | &bus_lcd0 { | ||
| 407 | devfreq = <&bus_leftbus>; | ||
| 408 | status = "okay"; | ||
| 409 | }; | ||
| 410 | |||
| 411 | &bus_fsys { | ||
| 412 | devfreq = <&bus_leftbus>; | ||
| 413 | status = "okay"; | ||
| 414 | }; | ||
| 415 | |||
| 416 | &bus_mcuisp { | ||
| 417 | devfreq = <&bus_leftbus>; | ||
| 418 | status = "okay"; | ||
| 419 | }; | ||
| 420 | |||
| 421 | &bus_isp { | ||
| 422 | devfreq = <&bus_leftbus>; | ||
| 423 | status = "okay"; | ||
| 424 | }; | ||
| 425 | |||
| 426 | &bus_peril { | ||
| 427 | devfreq = <&bus_leftbus>; | ||
| 428 | status = "okay"; | ||
| 429 | }; | ||
| 430 | |||
| 431 | &bus_mfc { | ||
| 432 | devfreq = <&bus_leftbus>; | ||
| 433 | status = "okay"; | ||
| 434 | }; | ||
| 435 | |||
| 436 | Example 3: | ||
| 437 | An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on | ||
| 438 | Exynos4412 SoC with video mixer as an interconnect consumer device. | ||
| 439 | |||
| 440 | soc { | ||
| 441 | bus_dmc: bus_dmc { | ||
| 442 | compatible = "samsung,exynos-bus"; | ||
| 443 | clocks = <&clock CLK_DIV_DMC>; | ||
| 444 | clock-names = "bus"; | ||
| 445 | operating-points-v2 = <&bus_dmc_opp_table>; | ||
| 446 | samsung,data-clock-ratio = <4>; | ||
| 447 | #interconnect-cells = <0>; | ||
| 448 | }; | ||
| 449 | |||
| 450 | bus_leftbus: bus_leftbus { | ||
| 451 | compatible = "samsung,exynos-bus"; | ||
| 452 | clocks = <&clock CLK_DIV_GDL>; | ||
| 453 | clock-names = "bus"; | ||
| 454 | operating-points-v2 = <&bus_leftbus_opp_table>; | ||
| 455 | #interconnect-cells = <0>; | ||
| 456 | interconnects = <&bus_dmc>; | ||
| 457 | }; | ||
| 458 | |||
| 459 | bus_display: bus_display { | ||
| 460 | compatible = "samsung,exynos-bus"; | ||
| 461 | clocks = <&clock CLK_ACLK160>; | ||
| 462 | clock-names = "bus"; | ||
| 463 | operating-points-v2 = <&bus_display_opp_table>; | ||
| 464 | #interconnect-cells = <0>; | ||
| 465 | interconnects = <&bus_leftbus &bus_dmc>; | ||
| 466 | }; | ||
| 467 | |||
| 468 | bus_dmc_opp_table: opp_table1 { | ||
| 469 | compatible = "operating-points-v2"; | ||
| 470 | /* ... */ | ||
| 471 | } | ||
| 472 | |||
| 473 | bus_leftbus_opp_table: opp_table3 { | ||
| 474 | compatible = "operating-points-v2"; | ||
| 475 | /* ... */ | ||
| 476 | }; | ||
| 477 | |||
| 478 | bus_display_opp_table: opp_table4 { | ||
| 479 | compatible = "operating-points-v2"; | ||
| 480 | /* .. */ | ||
| 481 | }; | ||
| 482 | |||
| 483 | &mixer { | ||
| 484 | compatible = "samsung,exynos4212-mixer"; | ||
| 485 | interconnects = <&bus_display &bus_dmc>; | ||
| 486 | /* ... */ | ||
| 487 | }; | ||
| 488 | }; | ||
| @@ -94,6 +94,7 @@ if: · 93 unmodified lines | |||
| 94 | - allwinner,sun8i-a83t-display-engine | 94 | - allwinner,sun8i-a83t-display-engine |
| 95 | - allwinner,sun8i-r40-display-engine | 95 | - allwinner,sun8i-r40-display-engine |
| 96 | - allwinner,sun9i-a80-display-engine | 96 | - allwinner,sun9i-a80-display-engine |
| 97 | - allwinner,sun20i-d1-display-engine | ||
| 97 | - allwinner,sun50i-a64-display-engine | 98 | - allwinner,sun50i-a64-display-engine |
| 98 | 99 | ||
| 99 | then: | 100 | then: |
| @@ -233,6 +233,7 @@ allOf: · 232 unmodified lines | |||
| 233 | - allwinner,sun8i-a83t-tcon-lcd | 233 | - allwinner,sun8i-a83t-tcon-lcd |
| 234 | - allwinner,sun8i-v3s-tcon | 234 | - allwinner,sun8i-v3s-tcon |
| 235 | - allwinner,sun9i-a80-tcon-lcd | 235 | - allwinner,sun9i-a80-tcon-lcd |
| 236 | - allwinner,sun20i-d1-tcon-lcd | ||
| 236 | 237 | ||
| 237 | then: | 238 | then: |
| 238 | properties: | 239 | properties: |
| @@ -252,6 +253,7 @@ allOf: · 13 unmodified lines | |||
| 252 | - allwinner,sun8i-a83t-tcon-tv | 253 | - allwinner,sun8i-a83t-tcon-tv |
| 253 | - allwinner,sun8i-r40-tcon-tv | 254 | - allwinner,sun8i-r40-tcon-tv |
| 254 | - allwinner,sun9i-a80-tcon-tv | 255 | - allwinner,sun9i-a80-tcon-tv |
| 256 | - allwinner,sun20i-d1-tcon-tv | ||
| 255 | 257 | ||
| 256 | then: | 258 | then: |
| 257 | properties: | 259 | properties: |
| @@ -278,6 +280,7 @@ allOf: · 20 unmodified lines | |||
| 278 | - allwinner,sun9i-a80-tcon-lcd | 280 | - allwinner,sun9i-a80-tcon-lcd |
| 279 | - allwinner,sun4i-a10-tcon | 281 | - allwinner,sun4i-a10-tcon |
| 280 | - allwinner,sun8i-a83t-tcon-lcd | 282 | - allwinner,sun8i-a83t-tcon-lcd |
| 283 | - allwinner,sun20i-d1-tcon-lcd | ||
| 281 | 284 | ||
| 282 | then: | 285 | then: |
| 283 | required: | 286 | required: |
| @@ -294,6 +297,7 @@ allOf: · 10 unmodified lines | |||
| 294 | - allwinner,sun8i-a23-tcon | 297 | - allwinner,sun8i-a23-tcon |
| 295 | - allwinner,sun8i-a33-tcon | 298 | - allwinner,sun8i-a33-tcon |
| 296 | - allwinner,sun8i-a83t-tcon-lcd | 299 | - allwinner,sun8i-a83t-tcon-lcd |
| 300 | - allwinner,sun20i-d1-tcon-lcd | ||
| 297 | 301 | ||
| 298 | then: | 302 | then: |
| 299 | properties: | 303 | properties: |
| @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" · 7 unmodified lines | |||
| 8 | title: Amlogic specific extensions to the Synopsys Designware HDMI Controller | 8 | title: Amlogic specific extensions to the Synopsys Designware HDMI Controller |
| 9 | 9 | ||
| 10 | maintainers: | 10 | maintainers: |
| 11 | - Neil Armstrong <narmstrong@baylibre.com> | 11 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 12 | 12 | ||
| 13 | allOf: | 13 | allOf: |
| 14 | - $ref: /schemas/sound/name-prefix.yaml# | 14 | - $ref: /schemas/sound/name-prefix.yaml# |
| @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" · 7 unmodified lines | |||
| 8 | title: Amlogic Meson Display Controller | 8 | title: Amlogic Meson Display Controller |
| 9 | 9 | ||
| 10 | maintainers: | 10 | maintainers: |
| 11 | - Neil Armstrong <narmstrong@baylibre.com> | 11 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 12 | 12 | ||
| 13 | description: | | 13 | description: | |
| 14 | The Amlogic Meson Display controller is composed of several components | 14 | The Amlogic Meson Display controller is composed of several components |
| @@ -159,25 +159,12 @@ examples: · 158 unmodified lines | |||
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | panel { | 161 | panel { |
| 162 | compatible = "arm,rtsm-display", "panel-dpi"; | 162 | compatible = "arm,rtsm-display"; |
| 163 | power-supply = <&vcc_supply>; | ||
| 164 | 163 | ||
| 165 | port { | 164 | port { |
| 166 | clcd_panel: endpoint { | 165 | clcd_panel: endpoint { |
| 167 | remote-endpoint = <&clcd_pads>; | 166 | remote-endpoint = <&clcd_pads>; |
| 168 | }; | 167 | }; |
| 169 | }; | 168 | }; |
| 170 | |||
| 171 | panel-timing { | ||
| 172 | clock-frequency = <25175000>; | ||
| 173 | hactive = <640>; | ||
| 174 | hback-porch = <40>; | ||
| 175 | hfront-porch = <24>; | ||
| 176 | hsync-len = <96>; | ||
| 177 | vactive = <480>; | ||
| 178 | vback-porch = <32>; | ||
| 179 | vfront-porch = <11>; | ||
| 180 | vsync-len = <2>; | ||
| 181 | }; | ||
| 182 | }; | 169 | }; |
| 183 | ... | 170 | ... |
| @@ -9,7 +9,6 @@ Required properties: · 8 unmodified lines | |||
| 9 | "atmel,at91sam9g45-lcdc" , | 9 | "atmel,at91sam9g45-lcdc" , |
| 10 | "atmel,at91sam9g45es-lcdc" , | 10 | "atmel,at91sam9g45es-lcdc" , |
| 11 | "atmel,at91sam9rl-lcdc" , | 11 | "atmel,at91sam9rl-lcdc" , |
| 12 | "atmel,at32ap-lcdc" | ||
| 13 | - reg : Should contain 1 register ranges(address and length). | 12 | - reg : Should contain 1 register ranges(address and length). |
| 14 | Can contain an additional register range(address and length) | 13 | Can contain an additional register range(address and length) |
| 15 | for fixed framebuffer memory. Useful for dedicated memories. | 14 | for fixed framebuffer memory. Useful for dedicated memories. |
| @@ -94,7 +94,22 @@ properties: · 93 unmodified lines | |||
| 94 | $ref: /schemas/graph.yaml#/$defs/port-base | 94 | $ref: /schemas/graph.yaml#/$defs/port-base |
| 95 | unevaluatedProperties: false | 95 | unevaluatedProperties: false |
| 96 | description: | 96 | description: |
| 97 | Video port for MIPI DSI input. | 97 | MIPI DSI/DPI input. |
| 98 | |||
| 99 | properties: | ||
| 100 | endpoint: | ||
| 101 | $ref: /schemas/media/video-interfaces.yaml# | ||
| 102 | type: object | ||
| 103 | additionalProperties: false | ||
| 104 | |||
| 105 | properties: | ||
| 106 | remote-endpoint: true | ||
| 107 | |||
| 108 | bus-type: | ||
| 109 | enum: [7] | ||
| 110 | default: 1 | ||
| 111 | |||
| 112 | data-lanes: true | ||
| 98 | 113 | ||
| 99 | port@1: | 114 | port@1: |
| 100 | $ref: /schemas/graph.yaml#/properties/port | 115 | $ref: /schemas/graph.yaml#/properties/port |
| @@ -143,6 +158,8 @@ examples: · 42 unmodified lines | |||
| 143 | reg = <0>; | 158 | reg = <0>; |
| 144 | anx7625_in: endpoint { | 159 | anx7625_in: endpoint { |
| 145 | remote-endpoint = <&mipi_dsi>; | 160 | remote-endpoint = <&mipi_dsi>; |
| 161 | bus-type = <7>; | ||
| 162 | data-lanes = <0 1 2 3>; | ||
| 146 | }; | 163 | }; |
| 147 | }; | 164 | }; |
| 148 | 165 | ||
| @@ -8,7 +8,7 @@ title: Analogix ANX7814 SlimPort (Full-HD Transmitter) · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Andrzej Hajda <andrzej.hajda@intel.com> | 10 | - Andrzej Hajda <andrzej.hajda@intel.com> |
| 11 | - Neil Armstrong <narmstrong@baylibre.com> | 11 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 12 | - Robert Foss <robert.foss@linaro.org> | 12 | - Robert Foss <robert.foss@linaro.org> |
| 13 | 13 | ||
| 14 | properties: | 14 | properties: |
| @@ -0,0 +1,173 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Freescale i.MX8qm/qxp LVDS Display Bridge | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Liu Ying <victor.liu@nxp.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels. | ||
| 14 | |||
| 15 | The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module. | ||
| 16 | The CSR module, as a system controller, contains the LDB's configuration | ||
| 17 | registers. | ||
| 18 | |||
| 19 | For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color | ||
| 20 | format and can map the input to VESA or JEIDA standards. The two channels | ||
| 21 | cannot be used simultaneously, that is to say, the user should pick one of | ||
| 22 | them to use. Two LDB channels from two LDB instances can work together in | ||
| 23 | LDB split mode to support a dual link LVDS display. The channel indexes | ||
| 24 | have to be different. Channel0 outputs odd pixels and channel1 outputs | ||
| 25 | even pixels. | ||
| 26 | |||
| 27 | For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel | ||
| 28 | input color format. The two channels can be used simultaneously, either | ||
| 29 | in dual mode or split mode. In dual mode, the two channels output identical | ||
| 30 | data. In split mode, channel0 outputs odd pixels and channel1 outputs even | ||
| 31 | pixels. | ||
| 32 | |||
| 33 | A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in | ||
| 34 | the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in | ||
| 35 | i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming | ||
| 36 | consistency, this binding calls it LDB. | ||
| 37 | |||
| 38 | properties: | ||
| 39 | compatible: | ||
| 40 | enum: | ||
| 41 | - fsl,imx8qm-ldb | ||
| 42 | - fsl,imx8qxp-ldb | ||
| 43 | |||
| 44 | "#address-cells": | ||
| 45 | const: 1 | ||
| 46 | |||
| 47 | "#size-cells": | ||
| 48 | const: 0 | ||
| 49 | |||
| 50 | clocks: | ||
| 51 | items: | ||
| 52 | - description: pixel clock | ||
| 53 | - description: bypass clock | ||
| 54 | |||
| 55 | clock-names: | ||
| 56 | items: | ||
| 57 | - const: pixel | ||
| 58 | - const: bypass | ||
| 59 | |||
| 60 | power-domains: | ||
| 61 | maxItems: 1 | ||
| 62 | |||
| 63 | fsl,companion-ldb: | ||
| 64 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 65 | description: | | ||
| 66 | A phandle which points to companion LDB which is used in LDB split mode. | ||
| 67 | |||
| 68 | patternProperties: | ||
| 69 | "^channel@[0-1]$": | ||
| 70 | type: object | ||
| 71 | description: Represents a channel of LDB. | ||
| 72 | |||
| 73 | properties: | ||
| 74 | "#address-cells": | ||
| 75 | const: 1 | ||
| 76 | |||
| 77 | "#size-cells": | ||
| 78 | const: 0 | ||
| 79 | |||
| 80 | reg: | ||
| 81 | description: The channel index. | ||
| 82 | enum: [ 0, 1 ] | ||
| 83 | |||
| 84 | phys: | ||
| 85 | description: A phandle to the phy module representing the LVDS PHY. | ||
| 86 | maxItems: 1 | ||
| 87 | |||
| 88 | phy-names: | ||
| 89 | const: lvds_phy | ||
| 90 | |||
| 91 | port@0: | ||
| 92 | $ref: /schemas/graph.yaml#/properties/port | ||
| 93 | description: Input port of the channel. | ||
| 94 | |||
| 95 | port@1: | ||
| 96 | $ref: /schemas/graph.yaml#/properties/port | ||
| 97 | description: Output port of the channel. | ||
| 98 | |||
| 99 | required: | ||
| 100 | - "#address-cells" | ||
| 101 | - "#size-cells" | ||
| 102 | - reg | ||
| 103 | - phys | ||
| 104 | - phy-names | ||
| 105 | |||
| 106 | additionalProperties: false | ||
| 107 | |||
| 108 | required: | ||
| 109 | - compatible | ||
| 110 | - "#address-cells" | ||
| 111 | - "#size-cells" | ||
| 112 | - clocks | ||
| 113 | - clock-names | ||
| 114 | - power-domains | ||
| 115 | - channel@0 | ||
| 116 | - channel@1 | ||
| 117 | |||
| 118 | allOf: | ||
| 119 | - if: | ||
| 120 | properties: | ||
| 121 | compatible: | ||
| 122 | contains: | ||
| 123 | const: fsl,imx8qm-ldb | ||
| 124 | then: | ||
| 125 | properties: | ||
| 126 | fsl,companion-ldb: false | ||
| 127 | |||
| 128 | additionalProperties: false | ||
| 129 | |||
| 130 | examples: | ||
| 131 | - | | ||
| 132 | #include <dt-bindings/firmware/imx/rsrc.h> | ||
| 133 | ldb { | ||
| 134 | #address-cells = <1>; | ||
| 135 | #size-cells = <0>; | ||
| 136 | compatible = "fsl,imx8qxp-ldb"; | ||
| 137 | clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, | ||
| 138 | <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; | ||
| 139 | clock-names = "pixel", "bypass"; | ||
| 140 | power-domains = <&pd IMX_SC_R_LVDS_0>; | ||
| 141 | |||
| 142 | channel@0 { | ||
| 143 | #address-cells = <1>; | ||
| 144 | #size-cells = <0>; | ||
| 145 | reg = <0>; | ||
| 146 | phys = <&mipi_lvds_0_phy>; | ||
| 147 | phy-names = "lvds_phy"; | ||
| 148 | |||
| 149 | port@0 { | ||
| 150 | reg = <0>; | ||
| 151 | |||
| 152 | mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { | ||
| 153 | remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; | ||
| 154 | }; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | |||
| 158 | channel@1 { | ||
| 159 | #address-cells = <1>; | ||
| 160 | #size-cells = <0>; | ||
| 161 | reg = <1>; | ||
| 162 | phys = <&mipi_lvds_0_phy>; | ||
| 163 | phy-names = "lvds_phy"; | ||
| 164 | |||
| 165 | port@0 { | ||
| 166 | reg = <0>; | ||
| 167 | |||
| 168 | mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { | ||
| 169 | remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; | ||
| 170 | }; | ||
| 171 | }; | ||
| 172 | }; | ||
| 173 | }; | ||
| @@ -0,0 +1,144 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Freescale i.MX8qm/qxp Pixel Combiner | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Liu Ying <victor.liu@nxp.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a | ||
| 14 | single display controller and manipulates the two streams to support a number | ||
| 15 | of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as | ||
| 16 | either one screen, two screens, or virtual screens. The pixel combiner is | ||
| 17 | also responsible for generating some of the control signals for the pixel link | ||
| 18 | output channel. | ||
| 19 | |||
| 20 | properties: | ||
| 21 | compatible: | ||
| 22 | enum: | ||
| 23 | - fsl,imx8qm-pixel-combiner | ||
| 24 | - fsl,imx8qxp-pixel-combiner | ||
| 25 | |||
| 26 | "#address-cells": | ||
| 27 | const: 1 | ||
| 28 | |||
| 29 | "#size-cells": | ||
| 30 | const: 0 | ||
| 31 | |||
| 32 | reg: | ||
| 33 | maxItems: 1 | ||
| 34 | |||
| 35 | clocks: | ||
| 36 | maxItems: 1 | ||
| 37 | |||
| 38 | clock-names: | ||
| 39 | const: apb | ||
| 40 | |||
| 41 | power-domains: | ||
| 42 | maxItems: 1 | ||
| 43 | |||
| 44 | patternProperties: | ||
| 45 | "^channel@[0-1]$": | ||
| 46 | type: object | ||
| 47 | description: Represents a display stream of pixel combiner. | ||
| 48 | |||
| 49 | properties: | ||
| 50 | "#address-cells": | ||
| 51 | const: 1 | ||
| 52 | |||
| 53 | "#size-cells": | ||
| 54 | const: 0 | ||
| 55 | |||
| 56 | reg: | ||
| 57 | description: The display stream index. | ||
| 58 | enum: [ 0, 1 ] | ||
| 59 | |||
| 60 | port@0: | ||
| 61 | $ref: /schemas/graph.yaml#/properties/port | ||
| 62 | description: Input endpoint of the display stream. | ||
| 63 | |||
| 64 | port@1: | ||
| 65 | $ref: /schemas/graph.yaml#/properties/port | ||
| 66 | description: Output endpoint of the display stream. | ||
| 67 | |||
| 68 | required: | ||
| 69 | - "#address-cells" | ||
| 70 | - "#size-cells" | ||
| 71 | - reg | ||
| 72 | - port@0 | ||
| 73 | - port@1 | ||
| 74 | |||
| 75 | additionalProperties: false | ||
| 76 | |||
| 77 | required: | ||
| 78 | - compatible | ||
| 79 | - "#address-cells" | ||
| 80 | - "#size-cells" | ||
| 81 | - reg | ||
| 82 | - clocks | ||
| 83 | - clock-names | ||
| 84 | - power-domains | ||
| 85 | |||
| 86 | additionalProperties: false | ||
| 87 | |||
| 88 | examples: | ||
| 89 | - | | ||
| 90 | #include <dt-bindings/clock/imx8-lpcg.h> | ||
| 91 | #include <dt-bindings/firmware/imx/rsrc.h> | ||
| 92 | pixel-combiner@56020000 { | ||
| 93 | compatible = "fsl,imx8qxp-pixel-combiner"; | ||
| 94 | #address-cells = <1>; | ||
| 95 | #size-cells = <0>; | ||
| 96 | reg = <0x56020000 0x10000>; | ||
| 97 | clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>; | ||
| 98 | clock-names = "apb"; | ||
| 99 | power-domains = <&pd IMX_SC_R_DC_0>; | ||
| 100 | |||
| 101 | channel@0 { | ||
| 102 | #address-cells = <1>; | ||
| 103 | #size-cells = <0>; | ||
| 104 | reg = <0>; | ||
| 105 | |||
| 106 | port@0 { | ||
| 107 | reg = <0>; | ||
| 108 | |||
| 109 | dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint { | ||
| 110 | remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>; | ||
| 111 | }; | ||
| 112 | }; | ||
| 113 | |||
| 114 | port@1 { | ||
| 115 | reg = <1>; | ||
| 116 | |||
| 117 | dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint { | ||
| 118 | remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | channel@1 { | ||
| 124 | #address-cells = <1>; | ||
| 125 | #size-cells = <0>; | ||
| 126 | reg = <1>; | ||
| 127 | |||
| 128 | port@0 { | ||
| 129 | reg = <0>; | ||
| 130 | |||
| 131 | dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint { | ||
| 132 | remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | port@1 { | ||
| 137 | reg = <1>; | ||
| 138 | |||
| 139 | dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint { | ||
| 140 | remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | }; | ||
| @@ -0,0 +1,144 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Freescale i.MX8qm/qxp Display Pixel Link | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Liu Ying <victor.liu@nxp.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard | ||
| 14 | asynchronous linkage between pixel sources(display controller or | ||
| 15 | camera module) and pixel consumers(imaging or displays). | ||
| 16 | It consists of two distinct functions, a pixel transfer function and a | ||
| 17 | control interface. Multiple pixel channels can exist per one control channel. | ||
| 18 | This binding documentation is only for pixel links whose pixel sources are | ||
| 19 | display controllers. | ||
| 20 | |||
| 21 | The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU) | ||
| 22 | firmware. | ||
| 23 | |||
| 24 | properties: | ||
| 25 | compatible: | ||
| 26 | enum: | ||
| 27 | - fsl,imx8qm-dc-pixel-link | ||
| 28 | - fsl,imx8qxp-dc-pixel-link | ||
| 29 | |||
| 30 | fsl,dc-id: | ||
| 31 | $ref: /schemas/types.yaml#/definitions/uint8 | ||
| 32 | description: | | ||
| 33 | u8 value representing the display controller index that the pixel link | ||
| 34 | connects to. | ||
| 35 | |||
| 36 | fsl,dc-stream-id: | ||
| 37 | $ref: /schemas/types.yaml#/definitions/uint8 | ||
| 38 | description: | | ||
| 39 | u8 value representing the display controller stream index that the pixel | ||
| 40 | link connects to. | ||
| 41 | enum: [0, 1] | ||
| 42 | |||
| 43 | ports: | ||
| 44 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 45 | |||
| 46 | properties: | ||
| 47 | port@0: | ||
| 48 | $ref: /schemas/graph.yaml#/properties/port | ||
| 49 | description: The pixel link input port node from upstream video source. | ||
| 50 | |||
| 51 | patternProperties: | ||
| 52 | "^port@[1-4]$": | ||
| 53 | $ref: /schemas/graph.yaml#/properties/port | ||
| 54 | description: The pixel link output port node to downstream bridge. | ||
| 55 | |||
| 56 | required: | ||
| 57 | - port@0 | ||
| 58 | - port@1 | ||
| 59 | - port@2 | ||
| 60 | - port@3 | ||
| 61 | - port@4 | ||
| 62 | |||
| 63 | allOf: | ||
| 64 | - if: | ||
| 65 | properties: | ||
| 66 | compatible: | ||
| 67 | contains: | ||
| 68 | const: fsl,imx8qxp-dc-pixel-link | ||
| 69 | then: | ||
| 70 | properties: | ||
| 71 | fsl,dc-id: | ||
| 72 | const: 0 | ||
| 73 | |||
| 74 | - if: | ||
| 75 | properties: | ||
| 76 | compatible: | ||
| 77 | contains: | ||
| 78 | const: fsl,imx8qm-dc-pixel-link | ||
| 79 | then: | ||
| 80 | properties: | ||
| 81 | fsl,dc-id: | ||
| 82 | enum: [0, 1] | ||
| 83 | |||
| 84 | required: | ||
| 85 | - compatible | ||
| 86 | - fsl,dc-id | ||
| 87 | - fsl,dc-stream-id | ||
| 88 | - ports | ||
| 89 | |||
| 90 | additionalProperties: false | ||
| 91 | |||
| 92 | examples: | ||
| 93 | - | | ||
| 94 | dc0-pixel-link0 { | ||
| 95 | compatible = "fsl,imx8qxp-dc-pixel-link"; | ||
| 96 | fsl,dc-id = /bits/ 8 <0>; | ||
| 97 | fsl,dc-stream-id = /bits/ 8 <0>; | ||
| 98 | |||
| 99 | ports { | ||
| 100 | #address-cells = <1>; | ||
| 101 | #size-cells = <0>; | ||
| 102 | |||
| 103 | /* from dc0 pixel combiner channel0 */ | ||
| 104 | port@0 { | ||
| 105 | reg = <0>; | ||
| 106 | |||
| 107 | dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint { | ||
| 108 | remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>; | ||
| 109 | }; | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* to PXL2DPIs in MIPI/LVDS combo subsystems */ | ||
| 113 | port@1 { | ||
| 114 | #address-cells = <1>; | ||
| 115 | #size-cells = <0>; | ||
| 116 | reg = <1>; | ||
| 117 | |||
| 118 | dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { | ||
| 119 | reg = <0>; | ||
| 120 | remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; | ||
| 121 | }; | ||
| 122 | |||
| 123 | dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { | ||
| 124 | reg = <1>; | ||
| 125 | remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | /* unused */ | ||
| 130 | port@2 { | ||
| 131 | reg = <2>; | ||
| 132 | }; | ||
| 133 | |||
| 134 | /* unused */ | ||
| 135 | port@3 { | ||
| 136 | reg = <3>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | /* to imaging subsystem */ | ||
| 140 | port@4 { | ||
| 141 | reg = <4>; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | }; | ||
| @@ -0,0 +1,108 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Liu Ying <victor.liu@nxp.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI) | ||
| 14 | interfaces the pixel link 36-bit data output and the DSI controller’s | ||
| 15 | MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module | ||
| 16 | used in LVDS mode, to remap the pixel color codings between those modules. | ||
| 17 | This module is purely combinatorial. | ||
| 18 | |||
| 19 | The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module. | ||
| 20 | The CSR module, as a system controller, contains the PXL2DPI's configuration | ||
| 21 | register. | ||
| 22 | |||
| 23 | properties: | ||
| 24 | compatible: | ||
| 25 | const: fsl,imx8qxp-pxl2dpi | ||
| 26 | |||
| 27 | fsl,sc-resource: | ||
| 28 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 29 | description: The SCU resource ID associated with this PXL2DPI instance. | ||
| 30 | |||
| 31 | power-domains: | ||
| 32 | maxItems: 1 | ||
| 33 | |||
| 34 | fsl,companion-pxl2dpi: | ||
| 35 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 36 | description: | | ||
| 37 | A phandle which points to companion PXL2DPI which is used by downstream | ||
| 38 | LVDS Display Bridge(LDB) in split mode. | ||
| 39 | |||
| 40 | ports: | ||
| 41 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 42 | |||
| 43 | properties: | ||
| 44 | port@0: | ||
| 45 | $ref: /schemas/graph.yaml#/properties/port | ||
| 46 | description: The PXL2DPI input port node from pixel link. | ||
| 47 | |||
| 48 | port@1: | ||
| 49 | $ref: /schemas/graph.yaml#/properties/port | ||
| 50 | description: The PXL2DPI output port node to downstream bridge. | ||
| 51 | |||
| 52 | required: | ||
| 53 | - port@0 | ||
| 54 | - port@1 | ||
| 55 | |||
| 56 | required: | ||
| 57 | - compatible | ||
| 58 | - fsl,sc-resource | ||
| 59 | - power-domains | ||
| 60 | - ports | ||
| 61 | |||
| 62 | additionalProperties: false | ||
| 63 | |||
| 64 | examples: | ||
| 65 | - | | ||
| 66 | #include <dt-bindings/firmware/imx/rsrc.h> | ||
| 67 | pxl2dpi { | ||
| 68 | compatible = "fsl,imx8qxp-pxl2dpi"; | ||
| 69 | fsl,sc-resource = <IMX_SC_R_MIPI_0>; | ||
| 70 | power-domains = <&pd IMX_SC_R_MIPI_0>; | ||
| 71 | |||
| 72 | ports { | ||
| 73 | #address-cells = <1>; | ||
| 74 | #size-cells = <0>; | ||
| 75 | |||
| 76 | port@0 { | ||
| 77 | #address-cells = <1>; | ||
| 78 | #size-cells = <0>; | ||
| 79 | reg = <0>; | ||
| 80 | |||
| 81 | mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 { | ||
| 82 | reg = <0>; | ||
| 83 | remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 { | ||
| 87 | reg = <1>; | ||
| 88 | remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | |||
| 92 | port@1 { | ||
| 93 | #address-cells = <1>; | ||
| 94 | #size-cells = <0>; | ||
| 95 | reg = <1>; | ||
| 96 | |||
| 97 | mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { | ||
| 98 | reg = <0>; | ||
| 99 | remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { | ||
| 103 | reg = <1>; | ||
| 104 | remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | }; | ||
| @@ -24,6 +24,15 @@ properties: · 23 unmodified lines | |||
| 24 | clock-names: | 24 | clock-names: |
| 25 | const: ldb | 25 | const: ldb |
| 26 | 26 | ||
| 27 | reg: | ||
| 28 | minItems: 2 | ||
| 29 | maxItems: 2 | ||
| 30 | |||
| 31 | reg-names: | ||
| 32 | items: | ||
| 33 | - const: ldb | ||
| 34 | - const: lvds | ||
| 35 | |||
| 27 | ports: | 36 | ports: |
| 28 | $ref: /schemas/graph.yaml#/properties/ports | 37 | $ref: /schemas/graph.yaml#/properties/ports |
| 29 | 38 | ||
| @@ -56,10 +65,15 @@ examples: · 26 unmodified lines | |||
| 56 | #include <dt-bindings/clock/imx8mp-clock.h> | 65 | #include <dt-bindings/clock/imx8mp-clock.h> |
| 57 | 66 | ||
| 58 | blk-ctrl { | 67 | blk-ctrl { |
| 59 | bridge { | 68 | #address-cells = <1>; |
| 69 | #size-cells = <1>; | ||
| 70 | |||
| 71 | bridge@5c { | ||
| 60 | compatible = "fsl,imx8mp-ldb"; | 72 | compatible = "fsl,imx8mp-ldb"; |
| 61 | clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; | 73 | clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; |
| 62 | clock-names = "ldb"; | 74 | clock-names = "ldb"; |
| 75 | reg = <0x5c 0x4>, <0x128 0x4>; | ||
| 76 | reg-names = "ldb", "lvds"; | ||
| 63 | 77 | ||
| 64 | ports { | 78 | ports { |
| 65 | #address-cells = <1>; | 79 | #address-cells = <1>; |
| @@ -55,7 +55,6 @@ examples: · 54 unmodified lines | |||
| 55 | compatible = "ingenic,jz4780-dw-hdmi"; | 55 | compatible = "ingenic,jz4780-dw-hdmi"; |
| 56 | reg = <0x10180000 0x8000>; | 56 | reg = <0x10180000 0x8000>; |
| 57 | reg-io-width = <4>; | 57 | reg-io-width = <4>; |
| 58 | ddc-i2c-bus = <&i2c4>; | ||
| 59 | interrupt-parent = <&intc>; | 58 | interrupt-parent = <&intc>; |
| 60 | interrupts = <3>; | 59 | interrupts = <3>; |
| 61 | clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>; | 60 | clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>; |
| @@ -8,7 +8,7 @@ title: ITE it66121 HDMI bridge Device Tree Bindings · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Phong LE <ple@baylibre.com> | 10 | - Phong LE <ple@baylibre.com> |
| 11 | - Neil Armstrong <narmstrong@baylibre.com> | 11 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 12 | 12 | ||
| 13 | description: | | 13 | description: | |
| 14 | The IT66121 is a high-performance and low-power single channel HDMI | 14 | The IT66121 is a high-performance and low-power single channel HDMI |
| @@ -1,78 +0,0 @@ | |||
| 1 | sii902x HDMI bridge bindings | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: "sil,sii9022" | ||
| 5 | - reg: i2c address of the bridge | ||
| 6 | |||
| 7 | Optional properties: | ||
| 8 | - interrupts: describe the interrupt line used to inform the host | ||
| 9 | about hotplug events. | ||
| 10 | - reset-gpios: OF device-tree gpio specification for RST_N pin. | ||
| 11 | - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V) | ||
| 12 | - cvcc12-supply: Digital Core Supply Voltage (1.2V) | ||
| 13 | |||
| 14 | HDMI audio properties: | ||
| 15 | - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin | ||
| 16 | is wired, <1> if the both are wired. HDMI audio is | ||
| 17 | configured only if this property is found. | ||
| 18 | - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3 | ||
| 19 | Each integer indicates which i2s pin is connected to which | ||
| 20 | audio fifo. The first integer selects i2s audio pin for the | ||
| 21 | first audio fifo#0 (HDMI channels 1&2), second for fifo#1 | ||
| 22 | (HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s | ||
| 23 | pins (SD0 - SD3). Any i2s pin can be connected to any fifo, | ||
| 24 | but there can be no gaps. E.g. an i2s pin must be mapped to | ||
| 25 | fifo#0 and fifo#1 before mapping a channel to fifo#2. Default | ||
| 26 | value is <0>, describing SD0 pin beiging routed to hdmi audio | ||
| 27 | fifo #0. | ||
| 28 | - clocks: phandle and clock specifier for each clock listed in | ||
| 29 | the clock-names property | ||
| 30 | - clock-names: "mclk" | ||
| 31 | Describes SII902x MCLK input. MCLK can be used to produce | ||
| 32 | HDMI audio CTS values. This property follows | ||
| 33 | Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
| 34 | consumer binding. | ||
| 35 | |||
| 36 | If HDMI audio is configured the sii902x device becomes an I2S | ||
| 37 | and/or spdif audio codec component (e.g a digital audio sink), | ||
| 38 | that can be used in configuring a full audio devices with | ||
| 39 | simple-card or audio-graph-card binding. See their binding | ||
| 40 | documents on how to describe the way the sii902x device is | ||
| 41 | connected to the rest of the audio system: | ||
| 42 | Documentation/devicetree/bindings/sound/simple-card.yaml | ||
| 43 | Documentation/devicetree/bindings/sound/audio-graph-card.yaml | ||
| 44 | Note: In case of the audio-graph-card binding the used port | ||
| 45 | index should be 3. | ||
| 46 | |||
| 47 | Optional subnodes: | ||
| 48 | - video input: this subnode can contain a video input port node | ||
| 49 | to connect the bridge to a display controller output (See this | ||
| 50 | documentation [1]). | ||
| 51 | |||
| 52 | [1]: Documentation/devicetree/bindings/media/video-interfaces.txt | ||
| 53 | |||
| 54 | Example: | ||
| 55 | hdmi-bridge@39 { | ||
| 56 | compatible = "sil,sii9022"; | ||
| 57 | reg = <0x39>; | ||
| 58 | reset-gpios = <&pioA 1 0>; | ||
| 59 | iovcc-supply = <&v3v3_hdmi>; | ||
| 60 | cvcc12-supply = <&v1v2_hdmi>; | ||
| 61 | |||
| 62 | #sound-dai-cells = <0>; | ||
| 63 | sil,i2s-data-lanes = < 0 1 2 >; | ||
| 64 | clocks = <&mclk>; | ||
| 65 | clock-names = "mclk"; | ||
| 66 | |||
| 67 | ports { | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <0>; | ||
| 70 | |||
| 71 | port@0 { | ||
| 72 | reg = <0>; | ||
| 73 | bridge_in: endpoint { | ||
| 74 | remote-endpoint = <&dc_out>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | }; | ||
| @@ -0,0 +1,131 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Silicon Image sii902x HDMI bridge | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Boris Brezillon <bbrezillon@kernel.org> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | compatible: | ||
| 14 | oneOf: | ||
| 15 | - items: | ||
| 16 | - enum: | ||
| 17 | - sil,sii9022-cpi # CEC Programming Interface | ||
| 18 | - sil,sii9022-tpi # Transmitter Programming Interface | ||
| 19 | - const: sil,sii9022 | ||
| 20 | - const: sil,sii9022 | ||
| 21 | |||
| 22 | reg: | ||
| 23 | maxItems: 1 | ||
| 24 | |||
| 25 | interrupts: | ||
| 26 | maxItems: 1 | ||
| 27 | description: Interrupt line used to inform the host about hotplug events. | ||
| 28 | |||
| 29 | reset-gpios: | ||
| 30 | maxItems: 1 | ||
| 31 | |||
| 32 | iovcc-supply: | ||
| 33 | description: I/O Supply Voltage (1.8V or 3.3V) | ||
| 34 | |||
| 35 | cvcc12-supply: | ||
| 36 | description: Digital Core Supply Voltage (1.2V) | ||
| 37 | |||
| 38 | '#sound-dai-cells': | ||
| 39 | enum: [ 0, 1 ] | ||
| 40 | description: | | ||
| 41 | <0> if only I2S or S/PDIF pin is wired, | ||
| 42 | <1> if both are wired. | ||
| 43 | HDMI audio is configured only if this property is found. | ||
| 44 | If HDMI audio is configured, the sii902x device becomes an I2S and/or | ||
| 45 | S/PDIF audio codec component (e.g. a digital audio sink), that can be | ||
| 46 | used in configuring full audio devices with simple-card or | ||
| 47 | audio-graph-card bindings. See their binding documents on how to describe | ||
| 48 | the way the | ||
| 49 | sii902x device is connected to the rest of the audio system: | ||
| 50 | Documentation/devicetree/bindings/sound/simple-card.yaml | ||
| 51 | Documentation/devicetree/bindings/sound/audio-graph-card.yaml | ||
| 52 | Note: In case of the audio-graph-card binding the used port index should | ||
| 53 | be 3. | ||
| 54 | |||
| 55 | sil,i2s-data-lanes: | ||
| 56 | $ref: /schemas/types.yaml#/definitions/uint32-array | ||
| 57 | minItems: 1 | ||
| 58 | maxItems: 4 | ||
| 59 | uniqueItems: true | ||
| 60 | items: | ||
| 61 | enum: [ 0, 1, 2, 3 ] | ||
| 62 | description: | ||
| 63 | Each integer indicates which I2S pin is connected to which audio FIFO. | ||
| 64 | The first integer selects the I2S audio pin for the first audio FIFO#0 | ||
| 65 | (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so | ||
| 66 | on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be | ||
| 67 | connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be | ||
| 68 | mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The | ||
| 69 | default value is <0>, describing SD0 pin being routed to HDMI audio | ||
| 70 | FIFO#0. | ||
| 71 | |||
| 72 | clocks: | ||
| 73 | maxItems: 1 | ||
| 74 | description: MCLK input. MCLK can be used to produce HDMI audio CTS values. | ||
| 75 | |||
| 76 | clock-names: | ||
| 77 | const: mclk | ||
| 78 | |||
| 79 | ports: | ||
| 80 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 81 | |||
| 82 | properties: | ||
| 83 | port@0: | ||
| 84 | $ref: /schemas/graph.yaml#/properties/port | ||
| 85 | description: Parallel RGB input port | ||
| 86 | |||
| 87 | port@1: | ||
| 88 | $ref: /schemas/graph.yaml#/properties/port | ||
| 89 | description: HDMI output port | ||
| 90 | |||
| 91 | port@3: | ||
| 92 | $ref: /schemas/graph.yaml#/properties/port | ||
| 93 | description: Sound input port | ||
| 94 | |||
| 95 | required: | ||
| 96 | - compatible | ||
| 97 | - reg | ||
| 98 | |||
| 99 | additionalProperties: false | ||
| 100 | |||
| 101 | examples: | ||
| 102 | - | | ||
| 103 | i2c { | ||
| 104 | #address-cells = <1>; | ||
| 105 | #size-cells = <0>; | ||
| 106 | |||
| 107 | hdmi-bridge@39 { | ||
| 108 | compatible = "sil,sii9022"; | ||
| 109 | reg = <0x39>; | ||
| 110 | reset-gpios = <&pioA 1 0>; | ||
| 111 | iovcc-supply = <&v3v3_hdmi>; | ||
| 112 | cvcc12-supply = <&v1v2_hdmi>; | ||
| 113 | |||
| 114 | #sound-dai-cells = <0>; | ||
| 115 | sil,i2s-data-lanes = < 0 1 2 >; | ||
| 116 | clocks = <&mclk>; | ||
| 117 | clock-names = "mclk"; | ||
| 118 | |||
| 119 | ports { | ||
| 120 | #address-cells = <1>; | ||
| 121 | #size-cells = <0>; | ||
| 122 | |||
| 123 | port@0 { | ||
| 124 | reg = <0>; | ||
| 125 | bridge_in: endpoint { | ||
| 126 | remote-endpoint = <&dc_out>; | ||
| 127 | }; | ||
| 128 | }; | ||
| 129 | }; | ||
| 130 | }; | ||
| 131 | }; | ||
| @@ -0,0 +1,117 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: TI DLPC3433 MIPI DSI to DMD bridge | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Jagan Teki <jagan@amarulasolutions.com> | ||
| 11 | - Christopher Vollo <chris@renewoutreach.org> | ||
| 12 | |||
| 13 | description: | | ||
| 14 | TI DLPC3433 is a MIPI DSI based display controller bridge | ||
| 15 | for processing high resolution DMD based projectors. | ||
| 16 | |||
| 17 | It has a flexible configuration of MIPI DSI and DPI signal | ||
| 18 | input that produces a DMD output in RGB565, RGB666, RGB888 | ||
| 19 | formats. | ||
| 20 | |||
| 21 | It supports upto 720p resolution with 60 and 120 Hz refresh | ||
| 22 | rates. | ||
| 23 | |||
| 24 | properties: | ||
| 25 | compatible: | ||
| 26 | const: ti,dlpc3433 | ||
| 27 | |||
| 28 | reg: | ||
| 29 | enum: | ||
| 30 | - 0x1b | ||
| 31 | - 0x1d | ||
| 32 | |||
| 33 | enable-gpios: | ||
| 34 | description: PROJ_ON pin, chip powers up PROJ_ON is high. | ||
| 35 | |||
| 36 | vcc_intf-supply: | ||
| 37 | description: A 1.8V/3.3V supply that power the Host I/O. | ||
| 38 | |||
| 39 | vcc_flsh-supply: | ||
| 40 | description: A 1.8V/3.3V supply that power the Flash I/O. | ||
| 41 | |||
| 42 | ports: | ||
| 43 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 44 | |||
| 45 | properties: | ||
| 46 | port@0: | ||
| 47 | $ref: /schemas/graph.yaml#/$defs/port-base | ||
| 48 | unevaluatedProperties: false | ||
| 49 | description: Video port for MIPI DSI input. | ||
| 50 | |||
| 51 | properties: | ||
| 52 | endpoint: | ||
| 53 | $ref: /schemas/media/video-interfaces.yaml# | ||
| 54 | unevaluatedProperties: false | ||
| 55 | |||
| 56 | properties: | ||
| 57 | data-lanes: | ||
| 58 | description: array of physical DSI data lane indexes. | ||
| 59 | minItems: 1 | ||
| 60 | items: | ||
| 61 | - const: 1 | ||
| 62 | - const: 2 | ||
| 63 | - const: 3 | ||
| 64 | - const: 4 | ||
| 65 | |||
| 66 | port@1: | ||
| 67 | $ref: /schemas/graph.yaml#/properties/port | ||
| 68 | description: Video port for DMD output. | ||
| 69 | |||
| 70 | required: | ||
| 71 | - port@0 | ||
| 72 | - port@1 | ||
| 73 | |||
| 74 | required: | ||
| 75 | - compatible | ||
| 76 | - reg | ||
| 77 | - enable-gpios | ||
| 78 | - ports | ||
| 79 | |||
| 80 | additionalProperties: false | ||
| 81 | |||
| 82 | examples: | ||
| 83 | - | | ||
| 84 | #include <dt-bindings/gpio/gpio.h> | ||
| 85 | |||
| 86 | i2c1 { | ||
| 87 | #address-cells = <1>; | ||
| 88 | #size-cells = <0>; | ||
| 89 | |||
| 90 | bridge@1b { | ||
| 91 | compatible = "ti,dlpc3433"; | ||
| 92 | reg = <0x1b>; | ||
| 93 | enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; | ||
| 94 | |||
| 95 | ports { | ||
| 96 | #address-cells = <1>; | ||
| 97 | #size-cells = <0>; | ||
| 98 | |||
| 99 | port@0 { | ||
| 100 | reg = <0>; | ||
| 101 | |||
| 102 | bridge_in_dsi: endpoint { | ||
| 103 | remote-endpoint = <&dsi_out_bridge>; | ||
| 104 | data-lanes = <1 2 3 4>; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | |||
| 108 | port@1 { | ||
| 109 | reg = <1>; | ||
| 110 | |||
| 111 | bridge_out_panel: endpoint { | ||
| 112 | remote-endpoint = <&panel_out_bridge>; | ||
| 113 | }; | ||
| 114 | }; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | }; | ||
| @@ -20,6 +20,7 @@ properties: · 19 unmodified lines | |||
| 20 | - fsl,imx23-lcdif | 20 | - fsl,imx23-lcdif |
| 21 | - fsl,imx28-lcdif | 21 | - fsl,imx28-lcdif |
| 22 | - fsl,imx6sx-lcdif | 22 | - fsl,imx6sx-lcdif |
| 23 | - fsl,imx8mp-lcdif | ||
| 23 | - items: | 24 | - items: |
| 24 | - enum: | 25 | - enum: |
| 25 | - fsl,imx6sl-lcdif | 26 | - fsl,imx6sl-lcdif |
| @@ -1,27 +0,0 @@ | |||
| 1 | Ilitek ILI9341 display panels | ||
| 2 | |||
| 3 | This binding is for display panels using an Ilitek ILI9341 controller in SPI | ||
| 4 | mode. | ||
| 5 | |||
| 6 | Required properties: | ||
| 7 | - compatible: "adafruit,yx240qv29", "ilitek,ili9341" | ||
| 8 | - dc-gpios: D/C pin | ||
| 9 | - reset-gpios: Reset pin | ||
| 10 | |||
| 11 | The node for this driver must be a child node of a SPI controller, hence | ||
| 12 | all mandatory properties described in ../spi/spi-bus.txt must be specified. | ||
| 13 | |||
| 14 | Optional properties: | ||
| 15 | - rotation: panel rotation in degrees counter clockwise (0,90,180,270) | ||
| 16 | - backlight: phandle of the backlight device attached to the panel | ||
| 17 | |||
| 18 | Example: | ||
| 19 | display@0{ | ||
| 20 | compatible = "adafruit,yx240qv29", "ilitek,ili9341"; | ||
| 21 | reg = <0>; | ||
| 22 | spi-max-frequency = <32000000>; | ||
| 23 | dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; | ||
| 24 | reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; | ||
| 25 | rotation = <270>; | ||
| 26 | backlight = <&backlight>; | ||
| 27 | }; | ||
| @@ -4,16 +4,16 @@ · 3 unmodified lines | |||
| 4 | $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# | 4 | $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: mediatek DPI Controller Device Tree Bindings | 7 | title: MediaTek DPI and DP_INTF Controller |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - CK Hu <ck.hu@mediatek.com> | 10 | - CK Hu <ck.hu@mediatek.com> |
| 11 | - Jitao shi <jitao.shi@mediatek.com> | 11 | - Jitao shi <jitao.shi@mediatek.com> |
| 12 | 12 | ||
| 13 | description: | | 13 | description: | |
| 14 | The Mediatek DPI function block is a sink of the display subsystem and | 14 | The MediaTek DPI and DP_INTF function blocks are a sink of the display |
| 15 | provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel | 15 | subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a |
| 16 | output bus. | 16 | parallel output bus. |
| 17 | 17 | ||
| 18 | properties: | 18 | properties: |
| 19 | compatible: | 19 | compatible: |
| @@ -24,6 +24,7 @@ properties: · 4 unmodified lines | |||
| 24 | - mediatek,mt8183-dpi | 24 | - mediatek,mt8183-dpi |
| 25 | - mediatek,mt8186-dpi | 25 | - mediatek,mt8186-dpi |
| 26 | - mediatek,mt8192-dpi | 26 | - mediatek,mt8192-dpi |
| 27 | - mediatek,mt8195-dp-intf | ||
| 27 | 28 | ||
| 28 | reg: | 29 | reg: |
| 29 | maxItems: 1 | 30 | maxItems: 1 |
| @@ -55,7 +56,7 @@ properties: · 25 unmodified lines | |||
| 55 | $ref: /schemas/graph.yaml#/properties/port | 56 | $ref: /schemas/graph.yaml#/properties/port |
| 56 | description: | 57 | description: |
| 57 | Output port node. This port should be connected to the input port of an | 58 | Output port node. This port should be connected to the input port of an |
| 58 | attached HDMI or LVDS encoder chip. | 59 | attached HDMI, LVDS or DisplayPort encoder chip. |
| 59 | 60 | ||
| 60 | required: | 61 | required: |
| 61 | - compatible | 62 | - compatible |
| @@ -1,62 +0,0 @@ | |||
| 1 | Mediatek DSI Device | ||
| 2 | =================== | ||
| 3 | |||
| 4 | The Mediatek DSI function block is a sink of the display subsystem and can | ||
| 5 | drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- | ||
| 6 | channel output. | ||
| 7 | |||
| 8 | Required properties: | ||
| 9 | - compatible: "mediatek,<chip>-dsi" | ||
| 10 | - the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. | ||
| 11 | - reg: Physical base address and length of the controller's registers | ||
| 12 | - interrupts: The interrupt signal from the function block. | ||
| 13 | - clocks: device clocks | ||
| 14 | See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. | ||
| 15 | - clock-names: must contain "engine", "digital", and "hs" | ||
| 16 | - phys: phandle link to the MIPI D-PHY controller. | ||
| 17 | - phy-names: must contain "dphy" | ||
| 18 | - port: Output port node with endpoint definitions as described in | ||
| 19 | Documentation/devicetree/bindings/graph.txt. This port should be connected | ||
| 20 | to the input port of an attached DSI panel or DSI-to-eDP encoder chip. | ||
| 21 | |||
| 22 | Optional properties: | ||
| 23 | - resets: list of phandle + reset specifier pair, as described in [1]. | ||
| 24 | |||
| 25 | [1] Documentation/devicetree/bindings/reset/reset.txt | ||
| 26 | |||
| 27 | MIPI TX Configuration Module | ||
| 28 | ============================ | ||
| 29 | |||
| 30 | See phy/mediatek,dsi-phy.yaml | ||
| 31 | |||
| 32 | Example: | ||
| 33 | |||
| 34 | mipi_tx0: mipi-dphy@10215000 { | ||
| 35 | compatible = "mediatek,mt8173-mipi-tx"; | ||
| 36 | reg = <0 0x10215000 0 0x1000>; | ||
| 37 | clocks = <&clk26m>; | ||
| 38 | clock-output-names = "mipi_tx0_pll"; | ||
| 39 | #clock-cells = <0>; | ||
| 40 | #phy-cells = <0>; | ||
| 41 | drive-strength-microamp = <4600>; | ||
| 42 | nvmem-cells= <&mipi_tx_calibration>; | ||
| 43 | nvmem-cell-names = "calibration-data"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | dsi0: dsi@1401b000 { | ||
| 47 | compatible = "mediatek,mt8173-dsi"; | ||
| 48 | reg = <0 0x1401b000 0 0x1000>; | ||
| 49 | interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; | ||
| 50 | clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, | ||
| 51 | <&mipi_tx0>; | ||
| 52 | clock-names = "engine", "digital", "hs"; | ||
| 53 | resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; | ||
| 54 | phys = <&mipi_tx0>; | ||
| 55 | phy-names = "dphy"; | ||
| 56 | |||
| 57 | port { | ||
| 58 | dsi0_out: endpoint { | ||
| 59 | remote-endpoint = <&panel_in>; | ||
| 60 | }; | ||
| 61 | }; | ||
| 62 | }; | ||
| @@ -0,0 +1,116 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: MediaTek DSI Controller Device Tree Bindings | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Chun-Kuang Hu <chunkuang.hu@kernel.org> | ||
| 11 | - Philipp Zabel <p.zabel@pengutronix.de> | ||
| 12 | - Jitao Shi <jitao.shi@mediatek.com> | ||
| 13 | - Xinlei Lee <xinlei.lee@mediatek.com> | ||
| 14 | |||
| 15 | description: | | ||
| 16 | The MediaTek DSI function block is a sink of the display subsystem and can | ||
| 17 | drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- | ||
| 18 | channel output. | ||
| 19 | |||
| 20 | allOf: | ||
| 21 | - $ref: /schemas/display/dsi-controller.yaml# | ||
| 22 | |||
| 23 | properties: | ||
| 24 | compatible: | ||
| 25 | enum: | ||
| 26 | - mediatek,mt2701-dsi | ||
| 27 | - mediatek,mt7623-dsi | ||
| 28 | - mediatek,mt8167-dsi | ||
| 29 | - mediatek,mt8173-dsi | ||
| 30 | - mediatek,mt8183-dsi | ||
| 31 | - mediatek,mt8186-dsi | ||
| 32 | |||
| 33 | reg: | ||
| 34 | maxItems: 1 | ||
| 35 | |||
| 36 | interrupts: | ||
| 37 | maxItems: 1 | ||
| 38 | |||
| 39 | power-domains: | ||
| 40 | maxItems: 1 | ||
| 41 | |||
| 42 | clocks: | ||
| 43 | items: | ||
| 44 | - description: Engine Clock | ||
| 45 | - description: Digital Clock | ||
| 46 | - description: HS Clock | ||
| 47 | |||
| 48 | clock-names: | ||
| 49 | items: | ||
| 50 | - const: engine | ||
| 51 | - const: digital | ||
| 52 | - const: hs | ||
| 53 | |||
| 54 | resets: | ||
| 55 | maxItems: 1 | ||
| 56 | |||
| 57 | phys: | ||
| 58 | maxItems: 1 | ||
| 59 | |||
| 60 | phy-names: | ||
| 61 | items: | ||
| 62 | - const: dphy | ||
| 63 | |||
| 64 | port: | ||
| 65 | $ref: /schemas/graph.yaml#/properties/port | ||
| 66 | description: | ||
| 67 | Output port node. This port should be connected to the input | ||
| 68 | port of an attached DSI panel or DSI-to-eDP encoder chip. | ||
| 69 | |||
| 70 | required: | ||
| 71 | - compatible | ||
| 72 | - reg | ||
| 73 | - interrupts | ||
| 74 | - power-domains | ||
| 75 | - clocks | ||
| 76 | - clock-names | ||
| 77 | - phys | ||
| 78 | - phy-names | ||
| 79 | - port | ||
| 80 | |||
| 81 | unevaluatedProperties: false | ||
| 82 | |||
| 83 | examples: | ||
| 84 | - | | ||
| 85 | #include <dt-bindings/clock/mt8183-clk.h> | ||
| 86 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 87 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 88 | #include <dt-bindings/power/mt8183-power.h> | ||
| 89 | #include <dt-bindings/phy/phy.h> | ||
| 90 | #include <dt-bindings/reset/mt8183-resets.h> | ||
| 91 | |||
| 92 | soc { | ||
| 93 | #address-cells = <2>; | ||
| 94 | #size-cells = <2>; | ||
| 95 | |||
| 96 | dsi0: dsi@14014000 { | ||
| 97 | compatible = "mediatek,mt8183-dsi"; | ||
| 98 | reg = <0 0x14014000 0 0x1000>; | ||
| 99 | interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; | ||
| 100 | power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; | ||
| 101 | clocks = <&mmsys CLK_MM_DSI0_MM>, | ||
| 102 | <&mmsys CLK_MM_DSI0_IF>, | ||
| 103 | <&mipi_tx0>; | ||
| 104 | clock-names = "engine", "digital", "hs"; | ||
| 105 | resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; | ||
| 106 | phys = <&mipi_tx0>; | ||
| 107 | phy-names = "dphy"; | ||
| 108 | port { | ||
| 109 | dsi0_out: endpoint { | ||
| 110 | remote-endpoint = <&panel_in>; | ||
| 111 | }; | ||
| 112 | }; | ||
| 113 | }; | ||
| 114 | }; | ||
| 115 | |||
| 116 | ... | ||
| @@ -0,0 +1,88 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: MediaTek MDP RDMA | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Chun-Kuang Hu <chunkuang.hu@kernel.org> | ||
| 11 | - Philipp Zabel <p.zabel@pengutronix.de> | ||
| 12 | |||
| 13 | description: | ||
| 14 | The MediaTek MDP RDMA stands for Read Direct Memory Access. | ||
| 15 | It provides real time data to the back-end panel driver, such as DSI, | ||
| 16 | DPI and DP_INTF. | ||
| 17 | It contains one line buffer to store the sufficient pixel data. | ||
| 18 | RDMA device node must be siblings to the central MMSYS_CONFIG node. | ||
| 19 | For a description of the MMSYS_CONFIG binding, see | ||
| 20 | Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. | ||
| 21 | |||
| 22 | properties: | ||
| 23 | compatible: | ||
| 24 | const: mediatek,mt8195-vdo1-rdma | ||
| 25 | |||
| 26 | reg: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | interrupts: | ||
| 30 | maxItems: 1 | ||
| 31 | |||
| 32 | power-domains: | ||
| 33 | maxItems: 1 | ||
| 34 | |||
| 35 | clocks: | ||
| 36 | items: | ||
| 37 | - description: RDMA Clock | ||
| 38 | |||
| 39 | iommus: | ||
| 40 | maxItems: 1 | ||
| 41 | |||
| 42 | mediatek,gce-client-reg: | ||
| 43 | description: | ||
| 44 | The register of display function block to be set by gce. There are 4 arguments, | ||
| 45 | such as gce node, subsys id, offset and register size. The subsys id that is | ||
| 46 | mapping to the register of display function blocks is defined in the gce header | ||
| 47 | include/dt-bindings/gce/<chip>-gce.h of each chips. | ||
| 48 | $ref: /schemas/types.yaml#/definitions/phandle-array | ||
| 49 | items: | ||
| 50 | items: | ||
| 51 | - description: phandle of GCE | ||
| 52 | - description: GCE subsys id | ||
| 53 | - description: register offset | ||
| 54 | - description: register size | ||
| 55 | maxItems: 1 | ||
| 56 | |||
| 57 | required: | ||
| 58 | - compatible | ||
| 59 | - reg | ||
| 60 | - power-domains | ||
| 61 | - clocks | ||
| 62 | - iommus | ||
| 63 | - mediatek,gce-client-reg | ||
| 64 | |||
| 65 | additionalProperties: false | ||
| 66 | |||
| 67 | examples: | ||
| 68 | - | | ||
| 69 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 70 | #include <dt-bindings/clock/mt8195-clk.h> | ||
| 71 | #include <dt-bindings/power/mt8195-power.h> | ||
| 72 | #include <dt-bindings/gce/mt8195-gce.h> | ||
| 73 | #include <dt-bindings/memory/mt8195-memory-port.h> | ||
| 74 | |||
| 75 | soc { | ||
| 76 | #address-cells = <2>; | ||
| 77 | #size-cells = <2>; | ||
| 78 | |||
| 79 | rdma@1c104000 { | ||
| 80 | compatible = "mediatek,mt8195-vdo1-rdma"; | ||
| 81 | reg = <0 0x1c104000 0 0x1000>; | ||
| 82 | interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 83 | clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; | ||
| 84 | power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; | ||
| 85 | iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; | ||
| 86 | mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; | ||
| 87 | }; | ||
| 88 | }; | ||
| @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: MSM Display Port Controller | 7 | title: MSM Display Port Controller |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Kuogee Hsieh <khsieh@codeaurora.org> | 10 | - Kuogee Hsieh <quic_khsieh@quicinc.com> |
| 11 | 11 | ||
| 12 | description: | | 12 | description: | |
| 13 | Device tree bindings for DisplayPort host controller for MSM targets | 13 | Device tree bindings for DisplayPort host controller for MSM targets |
| @@ -76,6 +76,9 @@ properties: · 62 unmodified lines | |||
| 76 | "#sound-dai-cells": | 76 | "#sound-dai-cells": |
| 77 | const: 0 | 77 | const: 0 |
| 78 | 78 | ||
| 79 | vdda-0p9-supply: true | ||
| 80 | vdda-1p2-supply: true | ||
| 81 | |||
| 79 | ports: | 82 | ports: |
| 80 | $ref: /schemas/graph.yaml#/properties/ports | 83 | $ref: /schemas/graph.yaml#/properties/ports |
| 81 | properties: | 84 | properties: |
| @@ -137,6 +140,9 @@ examples: · 55 unmodified lines | |||
| 137 | 140 | ||
| 138 | power-domains = <&rpmhpd SC7180_CX>; | 141 | power-domains = <&rpmhpd SC7180_CX>; |
| 139 | 142 | ||
| 143 | vdda-0p9-supply = <&vdda_usb_ss_dp_core>; | ||
| 144 | vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; | ||
| 145 | |||
| 140 | ports { | 146 | ports { |
| 141 | #address-cells = <1>; | 147 | #address-cells = <1>; |
| 142 | #size-cells = <0>; | 148 | #size-cells = <0>; |
| @@ -1,99 +0,0 @@ | |||
| 1 | Qualcomm adreno/snapdragon hdmi output | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: one of the following | ||
| 5 | * "qcom,hdmi-tx-8996" | ||
| 6 | * "qcom,hdmi-tx-8994" | ||
| 7 | * "qcom,hdmi-tx-8084" | ||
| 8 | * "qcom,hdmi-tx-8974" | ||
| 9 | * "qcom,hdmi-tx-8660" | ||
| 10 | * "qcom,hdmi-tx-8960" | ||
| 11 | - reg: Physical base address and length of the controller's registers | ||
| 12 | - reg-names: "core_physical" | ||
| 13 | - interrupts: The interrupt signal from the hdmi block. | ||
| 14 | - power-domains: Should be <&mmcc MDSS_GDSC>. | ||
| 15 | - clocks: device clocks | ||
| 16 | See ../clocks/clock-bindings.txt for details. | ||
| 17 | - core-vdda-supply: phandle to supply regulator | ||
| 18 | - hdmi-mux-supply: phandle to mux regulator | ||
| 19 | - phys: the phandle for the HDMI PHY device | ||
| 20 | - phy-names: the name of the corresponding PHY device | ||
| 21 | |||
| 22 | Optional properties: | ||
| 23 | - hpd-gpios: hpd pin | ||
| 24 | - qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin | ||
| 25 | - qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin | ||
| 26 | - qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin | ||
| 27 | - power-domains: reference to the power domain(s), if available. | ||
| 28 | - pinctrl-names: the pin control state names; should contain "default" | ||
| 29 | - pinctrl-0: the default pinctrl state (active) | ||
| 30 | - pinctrl-1: the "sleep" pinctrl state | ||
| 31 | |||
| 32 | HDMI PHY: | ||
| 33 | Required properties: | ||
| 34 | - compatible: Could be the following | ||
| 35 | * "qcom,hdmi-phy-8660" | ||
| 36 | * "qcom,hdmi-phy-8960" | ||
| 37 | * "qcom,hdmi-phy-8974" | ||
| 38 | * "qcom,hdmi-phy-8084" | ||
| 39 | * "qcom,hdmi-phy-8996" | ||
| 40 | - #phy-cells: Number of cells in a PHY specifier; Should be 0. | ||
| 41 | - reg: Physical base address and length of the registers of the PHY sub blocks. | ||
| 42 | - reg-names: The names of register regions. The following regions are required: | ||
| 43 | * "hdmi_phy" | ||
| 44 | * "hdmi_pll" | ||
| 45 | For HDMI PHY on msm8996, these additional register regions are required: | ||
| 46 | * "hdmi_tx_l0" | ||
| 47 | * "hdmi_tx_l1" | ||
| 48 | * "hdmi_tx_l3" | ||
| 49 | * "hdmi_tx_l4" | ||
| 50 | - power-domains: Should be <&mmcc MDSS_GDSC>. | ||
| 51 | - clocks: device clocks | ||
| 52 | See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. | ||
| 53 | - core-vdda-supply: phandle to vdda regulator device node | ||
| 54 | |||
| 55 | Example: | ||
| 56 | |||
| 57 | / { | ||
| 58 | ... | ||
| 59 | |||
| 60 | hdmi: hdmi@4a00000 { | ||
| 61 | compatible = "qcom,hdmi-tx-8960"; | ||
| 62 | reg-names = "core_physical"; | ||
| 63 | reg = <0x04a00000 0x2f0>; | ||
| 64 | interrupts = <GIC_SPI 79 0>; | ||
| 65 | power-domains = <&mmcc MDSS_GDSC>; | ||
| 66 | clock-names = | ||
| 67 | "core", | ||
| 68 | "master_iface", | ||
| 69 | "slave_iface"; | ||
| 70 | clocks = | ||
| 71 | <&mmcc HDMI_APP_CLK>, | ||
| 72 | <&mmcc HDMI_M_AHB_CLK>, | ||
| 73 | <&mmcc HDMI_S_AHB_CLK>; | ||
| 74 | qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; | ||
| 75 | qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; | ||
| 76 | qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; | ||
| 77 | core-vdda-supply = <&pm8921_hdmi_mvs>; | ||
| 78 | hdmi-mux-supply = <&ext_3p3v>; | ||
| 79 | pinctrl-names = "default", "sleep"; | ||
| 80 | pinctrl-0 = <&hpd_active &ddc_active &cec_active>; | ||
| 81 | pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; | ||
| 82 | |||
| 83 | phys = <&hdmi_phy>; | ||
| 84 | phy-names = "hdmi_phy"; | ||
| 85 | }; | ||
| 86 | |||
| 87 | hdmi_phy: phy@4a00400 { | ||
| 88 | compatible = "qcom,hdmi-phy-8960"; | ||
| 89 | reg-names = "hdmi_phy", | ||
| 90 | "hdmi_pll"; | ||
| 91 | reg = <0x4a00400 0x60>, | ||
| 92 | <0x4a00500 0x100>; | ||
| 93 | #phy-cells = <0>; | ||
| 94 | power-domains = <&mmcc MDSS_GDSC>; | ||
| 95 | clock-names = "slave_iface"; | ||
| 96 | clocks = <&mmcc HDMI_S_AHB_CLK>; | ||
| 97 | core-vdda-supply = <&pm8921_hdmi_mvs>; | ||
| 98 | }; | ||
| 99 | }; | ||
| @@ -0,0 +1,232 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | |||
| 5 | $id: http://devicetree.org/schemas/display/msm/hdmi.yaml# | ||
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 7 | |||
| 8 | title: Qualcomm Adreno/Snapdragon HDMI output | ||
| 9 | |||
| 10 | maintainers: | ||
| 11 | - Rob Clark <robdclark@gmail.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | compatible: | ||
| 15 | enum: | ||
| 16 | - qcom,hdmi-tx-8084 | ||
| 17 | - qcom,hdmi-tx-8660 | ||
| 18 | - qcom,hdmi-tx-8960 | ||
| 19 | - qcom,hdmi-tx-8974 | ||
| 20 | - qcom,hdmi-tx-8994 | ||
| 21 | - qcom,hdmi-tx-8996 | ||
| 22 | |||
| 23 | clocks: | ||
| 24 | minItems: 1 | ||
| 25 | maxItems: 5 | ||
| 26 | |||
| 27 | clock-names: | ||
| 28 | minItems: 1 | ||
| 29 | maxItems: 5 | ||
| 30 | |||
| 31 | reg: | ||
| 32 | minItems: 1 | ||
| 33 | maxItems: 3 | ||
| 34 | |||
| 35 | reg-names: | ||
| 36 | minItems: 1 | ||
| 37 | items: | ||
| 38 | - const: core_physical | ||
| 39 | - const: qfprom_physical | ||
| 40 | - const: hdcp_physical | ||
| 41 | |||
| 42 | interrupts: | ||
| 43 | maxItems: 1 | ||
| 44 | |||
| 45 | phys: | ||
| 46 | maxItems: 1 | ||
| 47 | |||
| 48 | phy-names: | ||
| 49 | enum: | ||
| 50 | - hdmi_phy | ||
| 51 | - hdmi-phy | ||
| 52 | deprecated: true | ||
| 53 | |||
| 54 | core-vdda-supply: | ||
| 55 | description: phandle to VDDA supply regulator | ||
| 56 | |||
| 57 | hdmi-mux-supply: | ||
| 58 | description: phandle to mux regulator | ||
| 59 | deprecated: true | ||
| 60 | |||
| 61 | core-vcc-supply: | ||
| 62 | description: phandle to VCC supply regulator | ||
| 63 | |||
| 64 | hpd-gpios: | ||
| 65 | maxItems: 1 | ||
| 66 | description: hpd pin | ||
| 67 | |||
| 68 | qcom,hdmi-tx-mux-en-gpios: | ||
| 69 | maxItems: 1 | ||
| 70 | deprecated: true | ||
| 71 | description: HDMI mux enable pin | ||
| 72 | |||
| 73 | qcom,hdmi-tx-mux-sel-gpios: | ||
| 74 | maxItems: 1 | ||
| 75 | deprecated: true | ||
| 76 | description: HDMI mux select pin | ||
| 77 | |||
| 78 | qcom,hdmi-tx-mux-lpm-gpios: | ||
| 79 | maxItems: 1 | ||
| 80 | deprecated: true | ||
| 81 | description: HDMI mux lpm pin | ||
| 82 | |||
| 83 | '#sound-dai-cells': | ||
| 84 | const: 1 | ||
| 85 | |||
| 86 | ports: | ||
| 87 | type: object | ||
| 88 | $ref: /schemas/graph.yaml#/properties/ports | ||
| 89 | properties: | ||
| 90 | port@0: | ||
| 91 | $ref: /schemas/graph.yaml#/$defs/port-base | ||
| 92 | description: | | ||
| 93 | Input endpoints of the controller. | ||
| 94 | |||
| 95 | port@1: | ||
| 96 | $ref: /schemas/graph.yaml#/$defs/port-base | ||
| 97 | description: | | ||
| 98 | Output endpoints of the controller. | ||
| 99 | |||
| 100 | required: | ||
| 101 | - port@0 | ||
| 102 | |||
| 103 | required: | ||
| 104 | - compatible | ||
| 105 | - clocks | ||
| 106 | - clock-names | ||
| 107 | - reg | ||
| 108 | - reg-names | ||
| 109 | - interrupts | ||
| 110 | - phys | ||
| 111 | |||
| 112 | allOf: | ||
| 113 | - if: | ||
| 114 | properties: | ||
| 115 | compatible: | ||
| 116 | contains: | ||
| 117 | enum: | ||
| 118 | - qcom,hdmi-tx-8960 | ||
| 119 | - qcom,hdmi-tx-8660 | ||
| 120 | then: | ||
| 121 | properties: | ||
| 122 | clocks: | ||
| 123 | minItems: 3 | ||
| 124 | maxItems: 3 | ||
| 125 | clock-names: | ||
| 126 | items: | ||
| 127 | - const: core | ||
| 128 | - const: master_iface | ||
| 129 | - const: slave_iface | ||
| 130 | core-vcc-supplies: false | ||
| 131 | |||
| 132 | - if: | ||
| 133 | properties: | ||
| 134 | compatible: | ||
| 135 | contains: | ||
| 136 | enum: | ||
| 137 | - qcom,hdmi-tx-8974 | ||
| 138 | - qcom,hdmi-tx-8084 | ||
| 139 | - qcom,hdmi-tx-8994 | ||
| 140 | - qcom,hdmi-tx-8996 | ||
| 141 | then: | ||
| 142 | properties: | ||
| 143 | clocks: | ||
| 144 | minItems: 5 | ||
| 145 | clock-names: | ||
| 146 | items: | ||
| 147 | - const: mdp_core | ||
| 148 | - const: iface | ||
| 149 | - const: core | ||
| 150 | - const: alt_iface | ||
| 151 | - const: extp | ||
| 152 | hdmi-mux-supplies: false | ||
| 153 | |||
| 154 | additionalProperties: false | ||
| 155 | |||
| 156 | examples: | ||
| 157 | - | | ||
| 158 | #include <dt-bindings/gpio/gpio.h> | ||
| 159 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 160 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 161 | hdmi: hdmi@4a00000 { | ||
| 162 | compatible = "qcom,hdmi-tx-8960"; | ||
| 163 | reg-names = "core_physical"; | ||
| 164 | reg = <0x04a00000 0x2f0>; | ||
| 165 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | ||
| 166 | clock-names = "core", | ||
| 167 | "master_iface", | ||
| 168 | "slave_iface"; | ||
| 169 | clocks = <&clk 61>, | ||
| 170 | <&clk 72>, | ||
| 171 | <&clk 98>; | ||
| 172 | hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>; | ||
| 173 | core-vdda-supply = <&pm8921_hdmi_mvs>; | ||
| 174 | hdmi-mux-supply = <&ext_3p3v>; | ||
| 175 | pinctrl-names = "default", "sleep"; | ||
| 176 | pinctrl-0 = <&hpd_active &ddc_active &cec_active>; | ||
| 177 | pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; | ||
| 178 | |||
| 179 | phys = <&hdmi_phy>; | ||
| 180 | }; | ||
| 181 | - | | ||
| 182 | #include <dt-bindings/clock/qcom,gcc-msm8996.h> | ||
| 183 | #include <dt-bindings/clock/qcom,mmcc-msm8996.h> | ||
| 184 | #include <dt-bindings/gpio/gpio.h> | ||
| 185 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 186 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 187 | hdmi@9a0000 { | ||
| 188 | compatible = "qcom,hdmi-tx-8996"; | ||
| 189 | reg = <0x009a0000 0x50c>, | ||
| 190 | <0x00070000 0x6158>, | ||
| 191 | <0x009e0000 0xfff>; | ||
| 192 | reg-names = "core_physical", | ||
| 193 | "qfprom_physical", | ||
| 194 | "hdcp_physical"; | ||
| 195 | |||
| 196 | interrupt-parent = <&mdss>; | ||
| 197 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; | ||
| 198 | |||
| 199 | clocks = <&mmcc MDSS_MDP_CLK>, | ||
| 200 | <&mmcc MDSS_AHB_CLK>, | ||
| 201 | <&mmcc MDSS_HDMI_CLK>, | ||
| 202 | <&mmcc MDSS_HDMI_AHB_CLK>, | ||
| 203 | <&mmcc MDSS_EXTPCLK_CLK>; | ||
| 204 | clock-names = "mdp_core", | ||
| 205 | "iface", | ||
| 206 | "core", | ||
| 207 | "alt_iface", | ||
| 208 | "extp"; | ||
| 209 | |||
| 210 | phys = <&hdmi_phy>; | ||
| 211 | #sound-dai-cells = <1>; | ||
| 212 | |||
| 213 | pinctrl-names = "default", "sleep"; | ||
| 214 | pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; | ||
| 215 | pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; | ||
| 216 | |||
| 217 | core-vdda-supply = <&vreg_l12a_1p8>; | ||
| 218 | core-vcc-supply = <&vreg_s4a_1p8>; | ||
| 219 | |||
| 220 | ports { | ||
| 221 | #address-cells = <1>; | ||
| 222 | #size-cells = <0>; | ||
| 223 | |||
| 224 | port@0 { | ||
| 225 | reg = <0>; | ||
| 226 | endpoint { | ||
| 227 | remote-endpoint = <&mdp5_intf3_out>; | ||
| 228 | }; | ||
| 229 | }; | ||
| 230 | }; | ||
| 231 | }; | ||
| 232 | ... | ||
| @@ -0,0 +1,27 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/panel/arm,rtsm-display.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Arm RTSM Virtual Platforms Display | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Linus Walleij <linus.walleij@linaro.org> | ||
| 11 | |||
| 12 | allOf: | ||
| 13 | - $ref: panel-common.yaml# | ||
| 14 | |||
| 15 | properties: | ||
| 16 | compatible: | ||
| 17 | const: arm,rtsm-display | ||
| 18 | |||
| 19 | port: true | ||
| 20 | |||
| 21 | required: | ||
| 22 | - compatible | ||
| 23 | - port | ||
| 24 | |||
| 25 | additionalProperties: false | ||
| 26 | |||
| 27 | ... | ||
| @@ -0,0 +1,74 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/panel/ebbg,ft8719.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: EBBG FT8719 MIPI-DSI LCD panel | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Joel Selvaraj <jo@jsfamily.in> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | The FT8719 panel from EBBG is a FHD+ LCD display panel with a resolution | ||
| 14 | of 1080x2246. It is a video mode DSI panel. The backlight is managed | ||
| 15 | through the QCOM WLED driver. | ||
| 16 | |||
| 17 | allOf: | ||
| 18 | - $ref: panel-common.yaml# | ||
| 19 | |||
| 20 | properties: | ||
| 21 | compatible: | ||
| 22 | const: ebbg,ft8719 | ||
| 23 | |||
| 24 | reg: | ||
| 25 | maxItems: 1 | ||
| 26 | description: DSI virtual channel of the peripheral | ||
| 27 | |||
| 28 | vddio-supply: | ||
| 29 | description: power IC supply regulator | ||
| 30 | |||
| 31 | vddpos-supply: | ||
| 32 | description: positive boost supply regulator | ||
| 33 | |||
| 34 | vddneg-supply: | ||
| 35 | description: negative boost supply regulator | ||
| 36 | |||
| 37 | required: | ||
| 38 | - compatible | ||
| 39 | - reg | ||
| 40 | - vddio-supply | ||
| 41 | - vddpos-supply | ||
| 42 | - vddneg-supply | ||
| 43 | - reset-gpios | ||
| 44 | - port | ||
| 45 | |||
| 46 | unevaluatedProperties: false | ||
| 47 | |||
| 48 | examples: | ||
| 49 | - | | ||
| 50 | #include <dt-bindings/gpio/gpio.h> | ||
| 51 | |||
| 52 | dsi { | ||
| 53 | #address-cells = <1>; | ||
| 54 | #size-cells = <0>; | ||
| 55 | |||
| 56 | panel@0 { | ||
| 57 | compatible = "ebbg,ft8719"; | ||
| 58 | reg = <0>; | ||
| 59 | |||
| 60 | vddio-supply = <&vreg_l14a_1p88>; | ||
| 61 | vddpos-supply = <&lab>; | ||
| 62 | vddneg-supply = <&ibb>; | ||
| 63 | |||
| 64 | reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; | ||
| 65 | |||
| 66 | backlight = <&pmi8998_wled>; | ||
| 67 | |||
| 68 | port { | ||
| 69 | ebbg_ft8719_in_0: endpoint { | ||
| 70 | remote-endpoint = <&dsi0_out>; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | }; | ||
| @@ -35,7 +35,6 @@ required: · 34 unmodified lines | |||
| 35 | - reg | 35 | - reg |
| 36 | - avdd-supply | 36 | - avdd-supply |
| 37 | - dvdd-supply | 37 | - dvdd-supply |
| 38 | - reset-gpios | ||
| 39 | 38 | ||
| 40 | additionalProperties: false | 39 | additionalProperties: false |
| 41 | 40 | ||
| @@ -21,8 +21,10 @@ properties: · 20 unmodified lines | |||
| 21 | compatible: | 21 | compatible: |
| 22 | items: | 22 | items: |
| 23 | - enum: | 23 | - enum: |
| 24 | - adafruit,yx240qv29 | ||
| 24 | # ili9341 240*320 Color on stm32f429-disco board | 25 | # ili9341 240*320 Color on stm32f429-disco board |
| 25 | - st,sf-tc240t-9370-t | 26 | - st,sf-tc240t-9370-t |
| 27 | - canaan,kd233-tft | ||
| 26 | - const: ilitek,ili9341 | 28 | - const: ilitek,ili9341 |
| 27 | 29 | ||
| 28 | reg: true | 30 | reg: true |
| @@ -47,31 +49,50 @@ properties: · 18 unmodified lines | |||
| 47 | vddi-led-supply: | 49 | vddi-led-supply: |
| 48 | description: Voltage supply for the LED driver (1.65 .. 3.3 V) | 50 | description: Voltage supply for the LED driver (1.65 .. 3.3 V) |
| 49 | 51 | ||
| 50 | additionalProperties: false | 52 | unevaluatedProperties: false |
| 51 | 53 | ||
| 52 | required: | 54 | required: |
| 53 | - compatible | 55 | - compatible |
| 54 | - reg | 56 | - reg |
| 55 | - dc-gpios | 57 | - dc-gpios |
| 56 | - port | 58 | |
| 59 | if: | ||
| 60 | properties: | ||
| 61 | compatible: | ||
| 62 | contains: | ||
| 63 | enum: | ||
| 64 | - st,sf-tc240t-9370-t | ||
| 65 | then: | ||
| 66 | required: | ||
| 67 | - port | ||
| 57 | 68 | ||
| 58 | examples: | 69 | examples: |
| 59 | - |+ | 70 | - |+ |
| 71 | #include <dt-bindings/gpio/gpio.h> | ||
| 60 | spi { | 72 | spi { |
| 61 | #address-cells = <1>; | 73 | #address-cells = <1>; |
| 62 | #size-cells = <0>; | 74 | #size-cells = <0>; |
| 63 | panel: display@0 { | 75 | panel: display@0 { |
| 64 | compatible = "st,sf-tc240t-9370-t", | 76 | compatible = "st,sf-tc240t-9370-t", |
| 65 | "ilitek,ili9341"; | 77 | "ilitek,ili9341"; |
| 66 | reg = <0>; | 78 | reg = <0>; |
| 67 | spi-3wire; | 79 | spi-3wire; |
| 68 | spi-max-frequency = <10000000>; | 80 | spi-max-frequency = <10000000>; |
| 69 | dc-gpios = <&gpiod 13 0>; | 81 | dc-gpios = <&gpiod 13 0>; |
| 70 | port { | 82 | port { |
| 71 | panel_in: endpoint { | 83 | panel_in: endpoint { |
| 72 | remote-endpoint = <&display_out>; | 84 | remote-endpoint = <&display_out>; |
| 73 | }; | 85 | }; |
| 74 | }; | 86 | }; |
| 75 | }; | 87 | }; |
| 88 | display@1{ | ||
| 89 | compatible = "adafruit,yx240qv29", "ilitek,ili9341"; | ||
| 90 | reg = <1>; | ||
| 91 | spi-max-frequency = <10000000>; | ||
| 92 | dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; | ||
| 93 | reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; | ||
| 94 | rotation = <270>; | ||
| 95 | backlight = <&backlight>; | ||
| 76 | }; | 96 | }; |
| 97 | }; | ||
| 77 | ... | 98 | ... |
| @@ -15,13 +15,13 @@ maintainers: · 14 unmodified lines | |||
| 15 | 15 | ||
| 16 | allOf: | 16 | allOf: |
| 17 | - $ref: panel-common.yaml# | 17 | - $ref: panel-common.yaml# |
| 18 | - $ref: /schemas/spi/spi-peripheral-props.yaml# | ||
| 18 | 19 | ||
| 19 | properties: | 20 | properties: |
| 20 | compatible: | 21 | compatible: |
| 21 | const: lg,lg4573 | 22 | const: lg,lg4573 |
| 22 | 23 | ||
| 23 | reg: true | 24 | reg: true |
| 24 | spi-max-frequency: true | ||
| 25 | 25 | ||
| 26 | required: | 26 | required: |
| 27 | - compatible | 27 | - compatible |
| @@ -21,6 +21,9 @@ properties: · 20 unmodified lines | |||
| 21 | enable-gpios: true | 21 | enable-gpios: true |
| 22 | port: true | 22 | port: true |
| 23 | 23 | ||
| 24 | spi-cpha: true | ||
| 25 | spi-cpol: true | ||
| 26 | |||
| 24 | required: | 27 | required: |
| 25 | - compatible | 28 | - compatible |
| 26 | - enable-gpios | 29 | - enable-gpios |
| @@ -46,6 +46,7 @@ properties: · 45 unmodified lines | |||
| 46 | 46 | ||
| 47 | reg: true | 47 | reg: true |
| 48 | port: true | 48 | port: true |
| 49 | backlight: true | ||
| 49 | 50 | ||
| 50 | required: | 51 | required: |
| 51 | - compatible | 52 | - compatible |
| @@ -73,6 +74,7 @@ examples: · 21 unmodified lines | |||
| 73 | vddpos-supply = <&lab>; | 74 | vddpos-supply = <&lab>; |
| 74 | vddneg-supply = <&ibb>; | 75 | vddneg-supply = <&ibb>; |
| 75 | 76 | ||
| 77 | backlight = <&pmi8998_wled>; | ||
| 76 | reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; | 78 | reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; |
| 77 | 79 | ||
| 78 | port { | 80 | port { |
| @@ -35,6 +35,8 @@ properties: · 34 unmodified lines | |||
| 35 | - ampire,am-480272h3tmqw-t01h | 35 | - ampire,am-480272h3tmqw-t01h |
| 36 | # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel | 36 | # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel |
| 37 | - ampire,am800480r3tmqwa1h | 37 | - ampire,am800480r3tmqwa1h |
| 38 | # Ampire AM-800600P5TMQW-TB8H 8.0" SVGA TFT LCD panel | ||
| 39 | - ampire,am800600p5tmqw-tb8h | ||
| 38 | # AU Optronics Corporation 10.1" WSVGA TFT LCD panel | 40 | # AU Optronics Corporation 10.1" WSVGA TFT LCD panel |
| 39 | - auo,b101aw03 | 41 | - auo,b101aw03 |
| 40 | # AU Optronics Corporation 10.1" WSVGA TFT LCD panel | 42 | # AU Optronics Corporation 10.1" WSVGA TFT LCD panel |
| @@ -107,6 +109,8 @@ properties: · 66 unmodified lines | |||
| 107 | - chunghwa,claa101wb03 | 109 | - chunghwa,claa101wb03 |
| 108 | # DataImage, Inc. 4.3" WQVGA (480x272) TFT LCD panel with 24-bit parallel interface. | 110 | # DataImage, Inc. 4.3" WQVGA (480x272) TFT LCD panel with 24-bit parallel interface. |
| 109 | - dataimage,fg040346dsswbg04 | 111 | - dataimage,fg040346dsswbg04 |
| 112 | # DataImage, Inc. 10.1" WXGA (1280×800) TFT LCD panel | ||
| 113 | - dataimage,fg1001l0dsswmg01 | ||
| 110 | # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. | 114 | # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. |
| 111 | - dataimage,scf0700c48ggu18 | 115 | - dataimage,scf0700c48ggu18 |
| 112 | # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel | 116 | # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel |
| @@ -137,6 +141,8 @@ properties: · 24 unmodified lines | |||
| 137 | # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch | 141 | # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch |
| 138 | - edt,etm0700g0dh6 | 142 | - edt,etm0700g0dh6 |
| 139 | - edt,etm0700g0edh6 | 143 | - edt,etm0700g0edh6 |
| 144 | # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch | ||
| 145 | - edt,etml0700y5dha | ||
| 140 | # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with | 146 | # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with |
| 141 | # capacitive touch | 147 | # capacitive touch |
| 142 | - edt,etmv570g2dhu | 148 | - edt,etmv570g2dhu |
| @@ -158,6 +164,8 @@ properties: · 15 unmodified lines | |||
| 158 | - hannstar,hsd070pww1 | 164 | - hannstar,hsd070pww1 |
| 159 | # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel | 165 | # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel |
| 160 | - hannstar,hsd100pxn1 | 166 | - hannstar,hsd100pxn1 |
| 167 | # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel | ||
| 168 | - hannstar,hsd101pww2 | ||
| 161 | # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel | 169 | # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel |
| 162 | - hit,tx23d38vm0caa | 170 | - hit,tx23d38vm0caa |
| 163 | # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel | 171 | # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel |
| @@ -38,6 +38,7 @@ properties: · 37 unmodified lines | |||
| 38 | 0 - burst-mode | 38 | 0 - burst-mode |
| 39 | 1 - non-burst with sync event | 39 | 1 - non-burst with sync event |
| 40 | 2 - non-burst with sync pulse | 40 | 2 - non-burst with sync pulse |
| 41 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 41 | enum: [0, 1, 2] | 42 | enum: [0, 1, 2] |
| 42 | 43 | ||
| 43 | required: | 44 | required: |
| @@ -42,6 +42,9 @@ properties: · 41 unmodified lines | |||
| 42 | panel-height-mm: | 42 | panel-height-mm: |
| 43 | description: physical panel height [mm] | 43 | description: physical panel height [mm] |
| 44 | 44 | ||
| 45 | spi-cpha: true | ||
| 46 | spi-cpol: true | ||
| 47 | |||
| 45 | required: | 48 | required: |
| 46 | - compatible | 49 | - compatible |
| 47 | - reg | 50 | - reg |
| @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel | 7 | title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Neil Armstrong <narmstrong@baylibre.com> | 10 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 11 | - Thierry Reding <thierry.reding@gmail.com> | 11 | - Thierry Reding <thierry.reding@gmail.com> |
| 12 | 12 | ||
| 13 | allOf: | 13 | allOf: |
| @@ -30,7 +30,12 @@ allOf: · 29 unmodified lines | |||
| 30 | 30 | ||
| 31 | properties: | 31 | properties: |
| 32 | compatible: | 32 | compatible: |
| 33 | const: sharp,lq101r1sx01 | 33 | oneOf: |
| 34 | - items: | ||
| 35 | - const: sharp,lq101r1sx03 | ||
| 36 | - const: sharp,lq101r1sx01 | ||
| 37 | - items: | ||
| 38 | - const: sharp,lq101r1sx01 | ||
| 34 | 39 | ||
| 35 | reg: true | 40 | reg: true |
| 36 | power-supply: true | 41 | power-supply: true |
| @@ -23,6 +23,9 @@ properties: · 22 unmodified lines | |||
| 23 | backlight: true | 23 | backlight: true |
| 24 | port: true | 24 | port: true |
| 25 | 25 | ||
| 26 | spi-cpha: true | ||
| 27 | spi-cpol: true | ||
| 28 | |||
| 26 | required: | 29 | required: |
| 27 | - compatible | 30 | - compatible |
| 28 | - reg | 31 | - reg |
| @@ -28,6 +28,9 @@ properties: · 27 unmodified lines | |||
| 28 | backlight: true | 28 | backlight: true |
| 29 | port: true | 29 | port: true |
| 30 | 30 | ||
| 31 | spi-cpha: true | ||
| 32 | spi-cpol: true | ||
| 33 | |||
| 31 | required: | 34 | required: |
| 32 | - compatible | 35 | - compatible |
| 33 | - port | 36 | - port |
| @@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI DDC · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -8,7 +8,6 @@ title: Samsung Exynos SoC Mixer · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON) · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC) · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -8,7 +8,6 @@ title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON) · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -8,7 +8,6 @@ title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD) · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Inki Dae <inki.dae@samsung.com> | 10 | - Inki Dae <inki.dae@samsung.com> |
| 11 | - Joonyoung Shim <jy0922.shim@samsung.com> | ||
| 12 | - Seung-Woo Kim <sw0312.kim@samsung.com> | 11 | - Seung-Woo Kim <sw0312.kim@samsung.com> |
| 13 | - Kyungmin Park <kyungmin.park@samsung.com> | 12 | - Kyungmin Park <kyungmin.park@samsung.com> |
| 14 | - Krzysztof Kozlowski <krzk@kernel.org> | 13 | - Krzysztof Kozlowski <krzk@kernel.org> |
| @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: Simple Framebuffer Device Tree Bindings | 7 | title: Simple Framebuffer Device Tree Bindings |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | ||
| 11 | - Hans de Goede <hdegoede@redhat.com> | 10 | - Hans de Goede <hdegoede@redhat.com> |
| 12 | 11 | ||
| 13 | description: |+ | 12 | description: |+ |
| @@ -15,6 +15,7 @@ description: · 14 unmodified lines | |||
| 15 | 15 | ||
| 16 | allOf: | 16 | allOf: |
| 17 | - $ref: panel/panel-common.yaml# | 17 | - $ref: panel/panel-common.yaml# |
| 18 | - $ref: /schemas/spi/spi-peripheral-props.yaml# | ||
| 18 | 19 | ||
| 19 | properties: | 20 | properties: |
| 20 | compatible: | 21 | compatible: |
| @@ -49,9 +49,6 @@ properties: · 48 unmodified lines | |||
| 49 | vbat-supply: | 49 | vbat-supply: |
| 50 | description: The supply for VBAT | 50 | description: The supply for VBAT |
| 51 | 51 | ||
| 52 | # Only required for SPI | ||
| 53 | spi-max-frequency: true | ||
| 54 | |||
| 55 | solomon,height: | 52 | solomon,height: |
| 56 | $ref: /schemas/types.yaml#/definitions/uint32 | 53 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 57 | default: 16 | 54 | default: 16 |
| @@ -153,6 +150,8 @@ required: · 95 unmodified lines | |||
| 153 | - reg | 150 | - reg |
| 154 | 151 | ||
| 155 | allOf: | 152 | allOf: |
| 153 | - $ref: /schemas/spi/spi-peripheral-props.yaml# | ||
| 154 | |||
| 156 | - if: | 155 | - if: |
| 157 | properties: | 156 | properties: |
| 158 | compatible: | 157 | compatible: |
| @@ -223,7 +222,7 @@ allOf: · 64 unmodified lines | |||
| 223 | solomon,dclk-frq: | 222 | solomon,dclk-frq: |
| 224 | default: 10 | 223 | default: 10 |
| 225 | 224 | ||
| 226 | additionalProperties: false | 225 | unevaluatedProperties: false |
| 227 | 226 | ||
| 228 | examples: | 227 | examples: |
| 229 | - | | 228 | - | |
| @@ -1,41 +0,0 @@ | |||
| 1 | NVIDIA Tegra MIPI pad calibration controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: "nvidia,tegra<chip>-mipi" | ||
| 5 | - reg: Physical base address and length of the controller's registers. | ||
| 6 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 7 | See ../clocks/clock-bindings.txt for details. | ||
| 8 | - clock-names: Must include the following entries: | ||
| 9 | - mipi-cal | ||
| 10 | - #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads | ||
| 11 | that need to be calibrated for a given device. | ||
| 12 | |||
| 13 | User nodes need to contain an nvidia,mipi-calibrate property that has a | ||
| 14 | phandle to refer to the calibration controller node and a bitmask of the pads | ||
| 15 | that need to be calibrated. | ||
| 16 | |||
| 17 | Example: | ||
| 18 | |||
| 19 | mipi: mipi@700e3000 { | ||
| 20 | compatible = "nvidia,tegra114-mipi"; | ||
| 21 | reg = <0x700e3000 0x100>; | ||
| 22 | clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; | ||
| 23 | clock-names = "mipi-cal"; | ||
| 24 | #nvidia,mipi-calibrate-cells = <1>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | ... | ||
| 28 | |||
| 29 | host1x@50000000 { | ||
| 30 | ... | ||
| 31 | |||
| 32 | dsi@54300000 { | ||
| 33 | ... | ||
| 34 | |||
| 35 | nvidia,mipi-calibrate = <&mipi 0x060>; | ||
| 36 | |||
| 37 | ... | ||
| 38 | }; | ||
| 39 | |||
| 40 | ... | ||
| 41 | }; | ||
| @@ -0,0 +1,74 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra MIPI pad calibration controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^mipi@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra114-mipi | ||
| 20 | - nvidia,tegra210-mipi | ||
| 21 | - nvidia,tegra186-mipi | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | clocks: | ||
| 27 | items: | ||
| 28 | - description: module clock | ||
| 29 | |||
| 30 | clock-names: | ||
| 31 | items: | ||
| 32 | - const: mipi-cal | ||
| 33 | |||
| 34 | power-domains: | ||
| 35 | maxItems: 1 | ||
| 36 | |||
| 37 | "#nvidia,mipi-calibrate-cells": | ||
| 38 | description: The number of cells in a MIPI calibration specifier. | ||
| 39 | Should be 1. The single cell specifies a bitmask of the pads that | ||
| 40 | need to be calibrated for a given device. | ||
| 41 | $ref: "/schemas/types.yaml#/definitions/uint32" | ||
| 42 | const: 1 | ||
| 43 | |||
| 44 | additionalProperties: false | ||
| 45 | |||
| 46 | required: | ||
| 47 | - compatible | ||
| 48 | - reg | ||
| 49 | - clocks | ||
| 50 | - "#nvidia,mipi-calibrate-cells" | ||
| 51 | |||
| 52 | examples: | ||
| 53 | - | | ||
| 54 | #include <dt-bindings/clock/tegra114-car.h> | ||
| 55 | |||
| 56 | mipi@700e3000 { | ||
| 57 | compatible = "nvidia,tegra114-mipi"; | ||
| 58 | reg = <0x700e3000 0x100>; | ||
| 59 | clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; | ||
| 60 | clock-names = "mipi-cal"; | ||
| 61 | #nvidia,mipi-calibrate-cells = <1>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | dsia: dsi@54300000 { | ||
| 65 | compatible = "nvidia,tegra114-dsi"; | ||
| 66 | reg = <0x54300000 0x00040000>; | ||
| 67 | clocks = <&tegra_car TEGRA114_CLK_DSIA>, | ||
| 68 | <&tegra_car TEGRA114_CLK_DSIALP>, | ||
| 69 | <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; | ||
| 70 | clock-names = "dsi", "lp", "parent"; | ||
| 71 | resets = <&tegra_car 48>; | ||
| 72 | reset-names = "dsi"; | ||
| 73 | nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ | ||
| 74 | }; | ||
| @@ -0,0 +1,152 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra DisplayPort AUX Interface | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | description: | | ||
| 14 | The Tegra Display Port Auxiliary (DPAUX) pad controller manages two | ||
| 15 | pins which can be assigned to either the DPAUX channel or to an I2C | ||
| 16 | controller. | ||
| 17 | |||
| 18 | When configured for DisplayPort AUX operation, the DPAUX controller | ||
| 19 | can also be used to communicate with a DisplayPort device using the | ||
| 20 | AUX channel. | ||
| 21 | |||
| 22 | properties: | ||
| 23 | $nodename: | ||
| 24 | pattern: "^dpaux@[0-9a-f]+$" | ||
| 25 | |||
| 26 | compatible: | ||
| 27 | oneOf: | ||
| 28 | - enum: | ||
| 29 | - nvidia,tegra124-dpaux | ||
| 30 | - nvidia,tegra210-dpaux | ||
| 31 | - nvidia,tegra186-dpaux | ||
| 32 | - nvidia,tegra194-dpaux | ||
| 33 | |||
| 34 | - items: | ||
| 35 | - const: nvidia,tegra132-dpaux | ||
| 36 | - const: nvidia,tegra124-dpaux | ||
| 37 | |||
| 38 | reg: | ||
| 39 | maxItems: 1 | ||
| 40 | |||
| 41 | interrupts: | ||
| 42 | maxItems: 1 | ||
| 43 | |||
| 44 | clocks: | ||
| 45 | items: | ||
| 46 | - description: clock input for the DPAUX hardware | ||
| 47 | - description: reference clock | ||
| 48 | |||
| 49 | clock-names: | ||
| 50 | items: | ||
| 51 | - const: dpaux | ||
| 52 | - const: parent | ||
| 53 | |||
| 54 | resets: | ||
| 55 | items: | ||
| 56 | - description: module reset | ||
| 57 | |||
| 58 | reset-names: | ||
| 59 | items: | ||
| 60 | - const: dpaux | ||
| 61 | |||
| 62 | power-domains: | ||
| 63 | maxItems: 1 | ||
| 64 | |||
| 65 | i2c-bus: | ||
| 66 | description: Subnode where I2C slave devices are listed. This | ||
| 67 | subnode must be always present. If there are no I2C slave | ||
| 68 | devices, an empty node should be added. See ../../i2c/i2c.yaml | ||
| 69 | for more information. | ||
| 70 | type: object | ||
| 71 | |||
| 72 | aux-bus: | ||
| 73 | $ref: /schemas/display/dp-aux-bus.yaml# | ||
| 74 | |||
| 75 | vdd-supply: | ||
| 76 | description: phandle of a supply that powers the DisplayPort | ||
| 77 | link | ||
| 78 | |||
| 79 | patternProperties: | ||
| 80 | "^pinmux-[a-z0-9]+$": | ||
| 81 | description: | ||
| 82 | Since only three configurations are possible, only three child | ||
| 83 | nodes are needed to describe the pin mux'ing options for the | ||
| 84 | DPAUX pads. Furthermore, given that the pad functions are only | ||
| 85 | applicable to a single set of pads, the child nodes only need | ||
| 86 | to describe the pad group the functions are being applied to | ||
| 87 | rather than the individual pads. | ||
| 88 | type: object | ||
| 89 | properties: | ||
| 90 | groups: | ||
| 91 | const: dpaux-io | ||
| 92 | |||
| 93 | function: | ||
| 94 | enum: | ||
| 95 | - aux | ||
| 96 | - i2c | ||
| 97 | - off | ||
| 98 | |||
| 99 | additionalProperties: false | ||
| 100 | |||
| 101 | required: | ||
| 102 | - groups | ||
| 103 | - function | ||
| 104 | |||
| 105 | additionalProperties: false | ||
| 106 | |||
| 107 | required: | ||
| 108 | - compatible | ||
| 109 | - reg | ||
| 110 | - interrupts | ||
| 111 | - clocks | ||
| 112 | - clock-names | ||
| 113 | - resets | ||
| 114 | - reset-names | ||
| 115 | |||
| 116 | examples: | ||
| 117 | - | | ||
| 118 | #include <dt-bindings/clock/tegra210-car.h> | ||
| 119 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 120 | |||
| 121 | dpaux: dpaux@545c0000 { | ||
| 122 | compatible = "nvidia,tegra210-dpaux"; | ||
| 123 | reg = <0x545c0000 0x00040000>; | ||
| 124 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | ||
| 125 | clocks = <&tegra_car TEGRA210_CLK_DPAUX>, | ||
| 126 | <&tegra_car TEGRA210_CLK_PLL_DP>; | ||
| 127 | clock-names = "dpaux", "parent"; | ||
| 128 | resets = <&tegra_car 181>; | ||
| 129 | reset-names = "dpaux"; | ||
| 130 | power-domains = <&pd_sor>; | ||
| 131 | status = "disabled"; | ||
| 132 | |||
| 133 | state_dpaux_aux: pinmux-aux { | ||
| 134 | groups = "dpaux-io"; | ||
| 135 | function = "aux"; | ||
| 136 | }; | ||
| 137 | |||
| 138 | state_dpaux_i2c: pinmux-i2c { | ||
| 139 | groups = "dpaux-io"; | ||
| 140 | function = "i2c"; | ||
| 141 | }; | ||
| 142 | |||
| 143 | state_dpaux_off: pinmux-off { | ||
| 144 | groups = "dpaux-io"; | ||
| 145 | function = "off"; | ||
| 146 | }; | ||
| 147 | |||
| 148 | i2c-bus { | ||
| 149 | #address-cells = <1>; | ||
| 150 | #size-cells = <0>; | ||
| 151 | }; | ||
| 152 | }; | ||
| @@ -0,0 +1,197 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra SOR Output Encoder | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | description: | | ||
| 14 | The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP | ||
| 15 | and DP outputs. | ||
| 16 | |||
| 17 | properties: | ||
| 18 | $nodename: | ||
| 19 | pattern: "^sor@[0-9a-f]+$" | ||
| 20 | |||
| 21 | compatible: | ||
| 22 | oneOf: | ||
| 23 | - enum: | ||
| 24 | - nvidia,tegra124-sor | ||
| 25 | - nvidia,tegra210-sor | ||
| 26 | - nvidia,tegra210-sor1 | ||
| 27 | - nvidia,tegra186-sor | ||
| 28 | - nvidia,tegra186-sor1 | ||
| 29 | - nvidia,tegra194-sor | ||
| 30 | |||
| 31 | - items: | ||
| 32 | - const: nvidia,tegra132-sor | ||
| 33 | - const: nvidia,tegra124-sor | ||
| 34 | |||
| 35 | reg: | ||
| 36 | maxItems: 1 | ||
| 37 | |||
| 38 | interrupts: | ||
| 39 | maxItems: 1 | ||
| 40 | |||
| 41 | clocks: | ||
| 42 | minItems: 5 | ||
| 43 | maxItems: 6 | ||
| 44 | |||
| 45 | clock-names: | ||
| 46 | minItems: 5 | ||
| 47 | maxItems: 6 | ||
| 48 | |||
| 49 | resets: | ||
| 50 | items: | ||
| 51 | - description: module reset | ||
| 52 | |||
| 53 | reset-names: | ||
| 54 | items: | ||
| 55 | - const: sor | ||
| 56 | |||
| 57 | power-domains: | ||
| 58 | maxItems: 1 | ||
| 59 | |||
| 60 | avdd-io-hdmi-dp-supply: | ||
| 61 | description: I/O supply for HDMI/DP | ||
| 62 | |||
| 63 | vdd-hdmi-dp-pll-supply: | ||
| 64 | description: PLL supply for HDMI/DP | ||
| 65 | |||
| 66 | hdmi-supply: | ||
| 67 | description: +5.0V HDMI connector supply, required for HDMI | ||
| 68 | |||
| 69 | # Tegra186 and later | ||
| 70 | nvidia,interface: | ||
| 71 | description: index of the SOR interface | ||
| 72 | $ref: "/schemas/types.yaml#/definitions/uint32" | ||
| 73 | |||
| 74 | nvidia,ddc-i2c-bus: | ||
| 75 | description: phandle of an I2C controller used for DDC EDID | ||
| 76 | probing | ||
| 77 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 78 | |||
| 79 | nvidia,hpd-gpio: | ||
| 80 | description: specifies a GPIO used for hotplug detection | ||
| 81 | maxItems: 1 | ||
| 82 | |||
| 83 | nvidia,edid: | ||
| 84 | description: supplies a binary EDID blob | ||
| 85 | $ref: "/schemas/types.yaml#/definitions/uint8-array" | ||
| 86 | |||
| 87 | nvidia,panel: | ||
| 88 | description: phandle of a display panel, required for eDP | ||
| 89 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 90 | |||
| 91 | nvidia,xbar-cfg: | ||
| 92 | description: 5 cells containing the crossbar configuration. | ||
| 93 | Each lane of the SOR, identified by the cell's index, is | ||
| 94 | mapped via the crossbar to the pad specified by the cell's | ||
| 95 | value. | ||
| 96 | $ref: "/schemas/types.yaml#/definitions/uint32-array" | ||
| 97 | |||
| 98 | # optional when driving an eDP output | ||
| 99 | nvidia,dpaux: | ||
| 100 | description: phandle to a DispayPort AUX interface | ||
| 101 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 102 | |||
| 103 | allOf: | ||
| 104 | - if: | ||
| 105 | properties: | ||
| 106 | compatible: | ||
| 107 | contains: | ||
| 108 | enum: | ||
| 109 | - nvidia,tegra186-sor | ||
| 110 | - nvidia,tegra194-sor | ||
| 111 | then: | ||
| 112 | properties: | ||
| 113 | clocks: | ||
| 114 | items: | ||
| 115 | - description: clock input for the SOR hardware | ||
| 116 | - description: SOR output clock | ||
| 117 | - description: input for the pixel clock | ||
| 118 | - description: reference clock for the SOR clock | ||
| 119 | - description: safe reference clock for the SOR clock | ||
| 120 | during power up | ||
| 121 | - description: SOR pad output clock | ||
| 122 | |||
| 123 | clock-names: | ||
| 124 | items: | ||
| 125 | - const: sor | ||
| 126 | - enum: | ||
| 127 | - source # deprecated | ||
| 128 | - out | ||
| 129 | - const: parent | ||
| 130 | - const: dp | ||
| 131 | - const: safe | ||
| 132 | - const: pad | ||
| 133 | else: | ||
| 134 | properties: | ||
| 135 | clocks: | ||
| 136 | items: | ||
| 137 | - description: clock input for the SOR hardware | ||
| 138 | - description: SOR output clock | ||
| 139 | - description: input for the pixel clock | ||
| 140 | - description: reference clock for the SOR clock | ||
| 141 | - description: safe reference clock for the SOR clock | ||
| 142 | during power up | ||
| 143 | |||
| 144 | clock-names: | ||
| 145 | items: | ||
| 146 | - const: sor | ||
| 147 | - enum: | ||
| 148 | - source # deprecated | ||
| 149 | - out | ||
| 150 | - const: parent | ||
| 151 | - const: dp | ||
| 152 | - const: safe | ||
| 153 | |||
| 154 | additionalProperties: false | ||
| 155 | |||
| 156 | required: | ||
| 157 | - compatible | ||
| 158 | - reg | ||
| 159 | - interrupts | ||
| 160 | - clocks | ||
| 161 | - clock-names | ||
| 162 | - resets | ||
| 163 | - reset-names | ||
| 164 | - avdd-io-hdmi-dp-supply | ||
| 165 | - vdd-hdmi-dp-pll-supply | ||
| 166 | |||
| 167 | examples: | ||
| 168 | - | | ||
| 169 | #include <dt-bindings/clock/tegra210-car.h> | ||
| 170 | #include <dt-bindings/gpio/tegra-gpio.h> | ||
| 171 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 172 | |||
| 173 | sor0: sor@54540000 { | ||
| 174 | compatible = "nvidia,tegra210-sor"; | ||
| 175 | reg = <0x54540000 0x00040000>; | ||
| 176 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | ||
| 177 | clocks = <&tegra_car TEGRA210_CLK_SOR0>, | ||
| 178 | <&tegra_car TEGRA210_CLK_SOR0_OUT>, | ||
| 179 | <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, | ||
| 180 | <&tegra_car TEGRA210_CLK_PLL_DP>, | ||
| 181 | <&tegra_car TEGRA210_CLK_SOR_SAFE>; | ||
| 182 | clock-names = "sor", "out", "parent", "dp", "safe"; | ||
| 183 | resets = <&tegra_car 182>; | ||
| 184 | reset-names = "sor"; | ||
| 185 | pinctrl-0 = <&state_dpaux_aux>; | ||
| 186 | pinctrl-1 = <&state_dpaux_i2c>; | ||
| 187 | pinctrl-2 = <&state_dpaux_off>; | ||
| 188 | pinctrl-names = "aux", "i2c", "off"; | ||
| 189 | power-domains = <&pd_sor>; | ||
| 190 | |||
| 191 | avdd-io-hdmi-dp-supply = <&avdd_1v05>; | ||
| 192 | vdd-hdmi-dp-pll-supply = <&vdd_1v8>; | ||
| 193 | hdmi-supply = <&vdd_hdmi>; | ||
| 194 | |||
| 195 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
| 196 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>; | ||
| 197 | }; | ||
| @@ -0,0 +1,72 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra Video Image Composer | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^vic@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | oneOf: | ||
| 19 | - enum: | ||
| 20 | - nvidia,tegra124-vic | ||
| 21 | - nvidia,tegra210-vic | ||
| 22 | - nvidia,tegra186-vic | ||
| 23 | - nvidia,tegra194-vic | ||
| 24 | - nvidia,tegra234-vic | ||
| 25 | |||
| 26 | - items: | ||
| 27 | - const: nvidia,tegra132-vic | ||
| 28 | - const: nvidia,tegra124-vic | ||
| 29 | |||
| 30 | reg: | ||
| 31 | maxItems: 1 | ||
| 32 | |||
| 33 | interrupts: | ||
| 34 | maxItems: 1 | ||
| 35 | |||
| 36 | clocks: | ||
| 37 | items: | ||
| 38 | - description: clock input for the VIC hardware | ||
| 39 | |||
| 40 | clock-names: | ||
| 41 | items: | ||
| 42 | - const: vic | ||
| 43 | |||
| 44 | resets: | ||
| 45 | items: | ||
| 46 | - description: module reset | ||
| 47 | |||
| 48 | reset-names: | ||
| 49 | items: | ||
| 50 | - const: vic | ||
| 51 | |||
| 52 | power-domains: | ||
| 53 | maxItems: 1 | ||
| 54 | |||
| 55 | iommus: | ||
| 56 | maxItems: 1 | ||
| 57 | |||
| 58 | interconnects: | ||
| 59 | description: Description of the interconnect paths for the VIC; | ||
| 60 | see ../interconnect/interconnect.txt for details. | ||
| 61 | items: | ||
| 62 | - description: memory read client for VIC | ||
| 63 | - description: memory write client for VIC | ||
| 64 | |||
| 65 | interconnect-names: | ||
| 66 | items: | ||
| 67 | - const: dma-mem # read | ||
| 68 | - const: write | ||
| 69 | |||
| 70 | dma-coherent: true | ||
| 71 | |||
| 72 | additionalProperties: false | ||
| @@ -0,0 +1,85 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra186 (and later) Display Controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^display@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra186-dc | ||
| 20 | - nvidia,tegra194-dc | ||
| 21 | |||
| 22 | reg: | ||
| 23 | maxItems: 1 | ||
| 24 | |||
| 25 | interrupts: | ||
| 26 | maxItems: 1 | ||
| 27 | |||
| 28 | clocks: | ||
| 29 | items: | ||
| 30 | - description: display controller pixel clock | ||
| 31 | |||
| 32 | clock-names: | ||
| 33 | items: | ||
| 34 | - const: dc | ||
| 35 | |||
| 36 | resets: | ||
| 37 | items: | ||
| 38 | - description: display controller reset | ||
| 39 | |||
| 40 | reset-names: | ||
| 41 | items: | ||
| 42 | - const: dc | ||
| 43 | |||
| 44 | power-domains: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | iommus: | ||
| 48 | maxItems: 1 | ||
| 49 | |||
| 50 | interconnects: | ||
| 51 | description: Description of the interconnect paths for the | ||
| 52 | display controller; see ../interconnect/interconnect.txt | ||
| 53 | for details. | ||
| 54 | |||
| 55 | interconnect-names: | ||
| 56 | items: | ||
| 57 | - const: dma-mem # read-0 | ||
| 58 | - const: read-1 | ||
| 59 | |||
| 60 | nvidia,outputs: | ||
| 61 | description: A list of phandles of outputs that this display | ||
| 62 | controller can drive. | ||
| 63 | $ref: "/schemas/types.yaml#/definitions/phandle-array" | ||
| 64 | |||
| 65 | nvidia,head: | ||
| 66 | description: The number of the display controller head. This | ||
| 67 | is used to setup the various types of output to receive | ||
| 68 | video data from the given head. | ||
| 69 | $ref: "/schemas/types.yaml#/definitions/uint32" | ||
| 70 | |||
| 71 | additionalProperties: false | ||
| 72 | |||
| 73 | required: | ||
| 74 | - compatible | ||
| 75 | - reg | ||
| 76 | - interrupts | ||
| 77 | - clocks | ||
| 78 | - clock-names | ||
| 79 | - resets | ||
| 80 | - reset-names | ||
| 81 | - power-domains | ||
| 82 | - nvidia,outputs | ||
| 83 | - nvidia,head | ||
| 84 | |||
| 85 | # see nvidia,tegra186-display.yaml for examples | ||
| @@ -0,0 +1,310 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra186 (and later) Display Hub | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^display-hub@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra186-display | ||
| 20 | - nvidia,tegra194-display | ||
| 21 | |||
| 22 | '#address-cells': | ||
| 23 | const: 1 | ||
| 24 | |||
| 25 | '#size-cells': | ||
| 26 | const: 1 | ||
| 27 | |||
| 28 | reg: | ||
| 29 | maxItems: 1 | ||
| 30 | |||
| 31 | interrupts: | ||
| 32 | maxItems: 1 | ||
| 33 | |||
| 34 | clocks: | ||
| 35 | minItems: 2 | ||
| 36 | maxItems: 3 | ||
| 37 | |||
| 38 | clock-names: | ||
| 39 | minItems: 2 | ||
| 40 | maxItems: 3 | ||
| 41 | |||
| 42 | resets: | ||
| 43 | items: | ||
| 44 | - description: display hub reset | ||
| 45 | - description: window group 0 reset | ||
| 46 | - description: window group 1 reset | ||
| 47 | - description: window group 2 reset | ||
| 48 | - description: window group 3 reset | ||
| 49 | - description: window group 4 reset | ||
| 50 | - description: window group 5 reset | ||
| 51 | |||
| 52 | reset-names: | ||
| 53 | items: | ||
| 54 | - const: misc | ||
| 55 | - const: wgrp0 | ||
| 56 | - const: wgrp1 | ||
| 57 | - const: wgrp2 | ||
| 58 | - const: wgrp3 | ||
| 59 | - const: wgrp4 | ||
| 60 | - const: wgrp5 | ||
| 61 | |||
| 62 | power-domains: | ||
| 63 | maxItems: 1 | ||
| 64 | |||
| 65 | ranges: | ||
| 66 | maxItems: 1 | ||
| 67 | |||
| 68 | patternProperties: | ||
| 69 | "^display@[0-9a-f]+$": | ||
| 70 | type: object | ||
| 71 | |||
| 72 | allOf: | ||
| 73 | - if: | ||
| 74 | properties: | ||
| 75 | compatible: | ||
| 76 | contains: | ||
| 77 | const: nvidia,tegra186-display | ||
| 78 | then: | ||
| 79 | properties: | ||
| 80 | clocks: | ||
| 81 | items: | ||
| 82 | - description: display core clock | ||
| 83 | - description: display stream compression clock | ||
| 84 | - description: display hub clock | ||
| 85 | |||
| 86 | clock-names: | ||
| 87 | items: | ||
| 88 | - const: disp | ||
| 89 | - const: dsc | ||
| 90 | - const: hub | ||
| 91 | else: | ||
| 92 | properties: | ||
| 93 | clocks: | ||
| 94 | items: | ||
| 95 | - description: display core clock | ||
| 96 | - description: display hub clock | ||
| 97 | |||
| 98 | clock-names: | ||
| 99 | items: | ||
| 100 | - const: disp | ||
| 101 | - const: hub | ||
| 102 | |||
| 103 | additionalProperties: false | ||
| 104 | |||
| 105 | required: | ||
| 106 | - compatible | ||
| 107 | - reg | ||
| 108 | - clocks | ||
| 109 | - clock-names | ||
| 110 | - resets | ||
| 111 | - reset-names | ||
| 112 | - power-domains | ||
| 113 | - "#address-cells" | ||
| 114 | - "#size-cells" | ||
| 115 | - ranges | ||
| 116 | |||
| 117 | examples: | ||
| 118 | - | | ||
| 119 | #include <dt-bindings/clock/tegra186-clock.h> | ||
| 120 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 121 | #include <dt-bindings/memory/tegra186-mc.h> | ||
| 122 | #include <dt-bindings/power/tegra186-powergate.h> | ||
| 123 | #include <dt-bindings/reset/tegra186-reset.h> | ||
| 124 | |||
| 125 | display-hub@15200000 { | ||
| 126 | compatible = "nvidia,tegra186-display"; | ||
| 127 | reg = <0x15200000 0x00040000>; | ||
| 128 | resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, | ||
| 129 | <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, | ||
| 130 | <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, | ||
| 131 | <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, | ||
| 132 | <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, | ||
| 133 | <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, | ||
| 134 | <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; | ||
| 135 | reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", | ||
| 136 | "wgrp3", "wgrp4", "wgrp5"; | ||
| 137 | clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, | ||
| 138 | <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, | ||
| 139 | <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; | ||
| 140 | clock-names = "disp", "dsc", "hub"; | ||
| 141 | status = "disabled"; | ||
| 142 | |||
| 143 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; | ||
| 144 | |||
| 145 | #address-cells = <1>; | ||
| 146 | #size-cells = <1>; | ||
| 147 | |||
| 148 | ranges = <0x15200000 0x15200000 0x40000>; | ||
| 149 | |||
| 150 | display@15200000 { | ||
| 151 | compatible = "nvidia,tegra186-dc"; | ||
| 152 | reg = <0x15200000 0x10000>; | ||
| 153 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | ||
| 154 | clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; | ||
| 155 | clock-names = "dc"; | ||
| 156 | resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; | ||
| 157 | reset-names = "dc"; | ||
| 158 | |||
| 159 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; | ||
| 160 | interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 161 | <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 162 | interconnect-names = "dma-mem", "read-1"; | ||
| 163 | iommus = <&smmu TEGRA186_SID_NVDISPLAY>; | ||
| 164 | |||
| 165 | nvidia,outputs = <&dsia &dsib &sor0 &sor1>; | ||
| 166 | nvidia,head = <0>; | ||
| 167 | }; | ||
| 168 | |||
| 169 | display@15210000 { | ||
| 170 | compatible = "nvidia,tegra186-dc"; | ||
| 171 | reg = <0x15210000 0x10000>; | ||
| 172 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | ||
| 173 | clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; | ||
| 174 | clock-names = "dc"; | ||
| 175 | resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; | ||
| 176 | reset-names = "dc"; | ||
| 177 | |||
| 178 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; | ||
| 179 | interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 180 | <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 181 | interconnect-names = "dma-mem", "read-1"; | ||
| 182 | iommus = <&smmu TEGRA186_SID_NVDISPLAY>; | ||
| 183 | |||
| 184 | nvidia,outputs = <&dsia &dsib &sor0 &sor1>; | ||
| 185 | nvidia,head = <1>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | display@15220000 { | ||
| 189 | compatible = "nvidia,tegra186-dc"; | ||
| 190 | reg = <0x15220000 0x10000>; | ||
| 191 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | ||
| 192 | clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; | ||
| 193 | clock-names = "dc"; | ||
| 194 | resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; | ||
| 195 | reset-names = "dc"; | ||
| 196 | |||
| 197 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; | ||
| 198 | interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 199 | <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 200 | interconnect-names = "dma-mem", "read-1"; | ||
| 201 | iommus = <&smmu TEGRA186_SID_NVDISPLAY>; | ||
| 202 | |||
| 203 | nvidia,outputs = <&sor0 &sor1>; | ||
| 204 | nvidia,head = <2>; | ||
| 205 | }; | ||
| 206 | }; | ||
| 207 | |||
| 208 | - | | ||
| 209 | #include <dt-bindings/clock/tegra194-clock.h> | ||
| 210 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 211 | #include <dt-bindings/memory/tegra194-mc.h> | ||
| 212 | #include <dt-bindings/power/tegra194-powergate.h> | ||
| 213 | #include <dt-bindings/reset/tegra194-reset.h> | ||
| 214 | |||
| 215 | display-hub@15200000 { | ||
| 216 | compatible = "nvidia,tegra194-display"; | ||
| 217 | reg = <0x15200000 0x00040000>; | ||
| 218 | resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, | ||
| 219 | <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, | ||
| 220 | <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, | ||
| 221 | <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, | ||
| 222 | <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, | ||
| 223 | <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, | ||
| 224 | <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; | ||
| 225 | reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", | ||
| 226 | "wgrp3", "wgrp4", "wgrp5"; | ||
| 227 | clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, | ||
| 228 | <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; | ||
| 229 | clock-names = "disp", "hub"; | ||
| 230 | status = "disabled"; | ||
| 231 | |||
| 232 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; | ||
| 233 | |||
| 234 | #address-cells = <1>; | ||
| 235 | #size-cells = <1>; | ||
| 236 | |||
| 237 | ranges = <0x15200000 0x15200000 0x40000>; | ||
| 238 | |||
| 239 | display@15200000 { | ||
| 240 | compatible = "nvidia,tegra194-dc"; | ||
| 241 | reg = <0x15200000 0x10000>; | ||
| 242 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | ||
| 243 | clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; | ||
| 244 | clock-names = "dc"; | ||
| 245 | resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; | ||
| 246 | reset-names = "dc"; | ||
| 247 | |||
| 248 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; | ||
| 249 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 250 | <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 251 | interconnect-names = "dma-mem", "read-1"; | ||
| 252 | |||
| 253 | nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; | ||
| 254 | nvidia,head = <0>; | ||
| 255 | }; | ||
| 256 | |||
| 257 | display@15210000 { | ||
| 258 | compatible = "nvidia,tegra194-dc"; | ||
| 259 | reg = <0x15210000 0x10000>; | ||
| 260 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | ||
| 261 | clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; | ||
| 262 | clock-names = "dc"; | ||
| 263 | resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; | ||
| 264 | reset-names = "dc"; | ||
| 265 | |||
| 266 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; | ||
| 267 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 268 | <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 269 | interconnect-names = "dma-mem", "read-1"; | ||
| 270 | |||
| 271 | nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; | ||
| 272 | nvidia,head = <1>; | ||
| 273 | }; | ||
| 274 | |||
| 275 | display@15220000 { | ||
| 276 | compatible = "nvidia,tegra194-dc"; | ||
| 277 | reg = <0x15220000 0x10000>; | ||
| 278 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | ||
| 279 | clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; | ||
| 280 | clock-names = "dc"; | ||
| 281 | resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; | ||
| 282 | reset-names = "dc"; | ||
| 283 | |||
| 284 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; | ||
| 285 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 286 | <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 287 | interconnect-names = "dma-mem", "read-1"; | ||
| 288 | |||
| 289 | nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; | ||
| 290 | nvidia,head = <2>; | ||
| 291 | }; | ||
| 292 | |||
| 293 | display@15230000 { | ||
| 294 | compatible = "nvidia,tegra194-dc"; | ||
| 295 | reg = <0x15230000 0x10000>; | ||
| 296 | interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; | ||
| 297 | clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; | ||
| 298 | clock-names = "dc"; | ||
| 299 | resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; | ||
| 300 | reset-names = "dc"; | ||
| 301 | |||
| 302 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; | ||
| 303 | interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, | ||
| 304 | <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; | ||
| 305 | interconnect-names = "dma-mem", "read-1"; | ||
| 306 | |||
| 307 | nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; | ||
| 308 | nvidia,head = <3>; | ||
| 309 | }; | ||
| 310 | }; | ||
| @@ -0,0 +1,45 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra MIPI DSI pad controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^padctl@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | const: nvidia,tegra186-dsi-padctl | ||
| 19 | |||
| 20 | reg: | ||
| 21 | maxItems: 1 | ||
| 22 | |||
| 23 | resets: | ||
| 24 | items: | ||
| 25 | - description: module reset | ||
| 26 | |||
| 27 | reset-names: | ||
| 28 | items: | ||
| 29 | - const: dsi | ||
| 30 | |||
| 31 | allOf: | ||
| 32 | - $ref: "/schemas/reset/reset.yaml" | ||
| 33 | |||
| 34 | additionalProperties: false | ||
| 35 | |||
| 36 | examples: | ||
| 37 | - | | ||
| 38 | #include <dt-bindings/reset/tegra186-reset.h> | ||
| 39 | |||
| 40 | padctl@15880000 { | ||
| 41 | compatible = "nvidia,tegra186-dsi-padctl"; | ||
| 42 | reg = <0x15880000 0x10000>; | ||
| 43 | resets = <&bpmp TEGRA186_RESET_DSI>; | ||
| 44 | reset-names = "dsi"; | ||
| 45 | }; | ||
| @@ -0,0 +1,183 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra Display Controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^dc@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | oneOf: | ||
| 19 | - enum: | ||
| 20 | - nvidia,tegra20-dc | ||
| 21 | - nvidia,tegra30-dc | ||
| 22 | - nvidia,tegra114-dc | ||
| 23 | - nvidia,tegra124-dc | ||
| 24 | - nvidia,tegra210-dc | ||
| 25 | |||
| 26 | - items: | ||
| 27 | - const: nvidia,tegra124-dc | ||
| 28 | - const: nvidia,tegra132-dc | ||
| 29 | |||
| 30 | reg: | ||
| 31 | maxItems: 1 | ||
| 32 | |||
| 33 | interrupts: | ||
| 34 | maxItems: 1 | ||
| 35 | |||
| 36 | clocks: | ||
| 37 | minItems: 1 | ||
| 38 | items: | ||
| 39 | - description: display controller pixel clock | ||
| 40 | - description: parent clock # optional | ||
| 41 | |||
| 42 | clock-names: | ||
| 43 | minItems: 1 | ||
| 44 | items: | ||
| 45 | - const: dc | ||
| 46 | - const: parent # optional | ||
| 47 | |||
| 48 | resets: | ||
| 49 | items: | ||
| 50 | - description: module reset | ||
| 51 | |||
| 52 | reset-names: | ||
| 53 | items: | ||
| 54 | - const: dc | ||
| 55 | |||
| 56 | interconnect-names: true | ||
| 57 | interconnects: true | ||
| 58 | |||
| 59 | iommus: | ||
| 60 | maxItems: 1 | ||
| 61 | |||
| 62 | operating-points-v2: | ||
| 63 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 64 | |||
| 65 | power-domains: | ||
| 66 | items: | ||
| 67 | - description: phandle to the core power domain | ||
| 68 | |||
| 69 | memory-region: true | ||
| 70 | |||
| 71 | nvidia,head: | ||
| 72 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 73 | description: The number of the display controller head. This is used to setup the various | ||
| 74 | types of output to receive video data from the given head. | ||
| 75 | |||
| 76 | nvidia,outputs: | ||
| 77 | $ref: /schemas/types.yaml#/definitions/phandle-array | ||
| 78 | description: A list of phandles of outputs that this display controller can drive. | ||
| 79 | |||
| 80 | rgb: | ||
| 81 | type: object | ||
| 82 | |||
| 83 | allOf: | ||
| 84 | - if: | ||
| 85 | properties: | ||
| 86 | compatible: | ||
| 87 | contains: | ||
| 88 | enum: | ||
| 89 | - nvidia,tegra20-dc | ||
| 90 | - nvidia,tegra30-dc | ||
| 91 | - nvidia,tegra114-dc | ||
| 92 | then: | ||
| 93 | properties: | ||
| 94 | interconnects: | ||
| 95 | items: | ||
| 96 | - description: window A memory client | ||
| 97 | - description: window B memory client | ||
| 98 | - description: window B memory client (vertical filter) | ||
| 99 | - description: window C memory client | ||
| 100 | - description: cursor memory client | ||
| 101 | |||
| 102 | interconnect-names: | ||
| 103 | items: | ||
| 104 | - const: wina | ||
| 105 | - const: winb | ||
| 106 | - const: winb-vfilter | ||
| 107 | - const: winc | ||
| 108 | - const: cursor | ||
| 109 | |||
| 110 | rgb: | ||
| 111 | description: Each display controller node has a child node, named "rgb", that represents | ||
| 112 | the RGB output associated with the controller. | ||
| 113 | type: object | ||
| 114 | properties: | ||
| 115 | nvidia,ddc-i2c-bus: | ||
| 116 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 117 | description: phandle of an I2C controller used for DDC EDID probing | ||
| 118 | |||
| 119 | nvidia,hpd-gpio: | ||
| 120 | description: specifies a GPIO used for hotplug detection | ||
| 121 | maxItems: 1 | ||
| 122 | |||
| 123 | nvidia,edid: | ||
| 124 | $ref: /schemas/types.yaml#/definitions/uint8-array | ||
| 125 | description: supplies a binary EDID blob | ||
| 126 | |||
| 127 | nvidia,panel: | ||
| 128 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 129 | description: phandle of a display panel | ||
| 130 | |||
| 131 | - if: | ||
| 132 | properties: | ||
| 133 | compatible: | ||
| 134 | contains: | ||
| 135 | enum: | ||
| 136 | - nvidia,tegra124-dc | ||
| 137 | then: | ||
| 138 | properties: | ||
| 139 | interconnects: | ||
| 140 | minItems: 4 | ||
| 141 | items: | ||
| 142 | - description: window A memory client | ||
| 143 | - description: window B memory client | ||
| 144 | - description: window C memory client | ||
| 145 | - description: cursor memory client | ||
| 146 | - description: window D memory client | ||
| 147 | - description: window T memory client | ||
| 148 | |||
| 149 | interconnect-names: | ||
| 150 | minItems: 4 | ||
| 151 | items: | ||
| 152 | - const: wina | ||
| 153 | - const: winb | ||
| 154 | - const: winc | ||
| 155 | - const: cursor | ||
| 156 | - const: wind | ||
| 157 | - const: wint | ||
| 158 | |||
| 159 | additionalProperties: false | ||
| 160 | |||
| 161 | required: | ||
| 162 | - compatible | ||
| 163 | - reg | ||
| 164 | - interrupts | ||
| 165 | - clocks | ||
| 166 | - clock-names | ||
| 167 | - resets | ||
| 168 | - reset-names | ||
| 169 | |||
| 170 | examples: | ||
| 171 | - | | ||
| 172 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 173 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 174 | |||
| 175 | dc@54200000 { | ||
| 176 | compatible = "nvidia,tegra20-dc"; | ||
| 177 | reg = <0x54200000 0x00040000>; | ||
| 178 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | ||
| 179 | clocks = <&tegra_car TEGRA20_CLK_DISP1>; | ||
| 180 | clock-names = "dc"; | ||
| 181 | resets = <&tegra_car 27>; | ||
| 182 | reset-names = "dc"; | ||
| 183 | }; | ||
| @@ -0,0 +1,159 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra Display Serial Interface | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | compatible: | ||
| 15 | oneOf: | ||
| 16 | - enum: | ||
| 17 | - nvidia,tegra20-dsi | ||
| 18 | - nvidia,tegra30-dsi | ||
| 19 | - nvidia,tegra114-dsi | ||
| 20 | - nvidia,tegra124-dsi | ||
| 21 | - nvidia,tegra210-dsi | ||
| 22 | - nvidia,tegra186-dsi | ||
| 23 | |||
| 24 | - items: | ||
| 25 | - const: nvidia,tegra132-dsi | ||
| 26 | - const: nvidia,tegra124-dsi | ||
| 27 | |||
| 28 | reg: | ||
| 29 | maxItems: 1 | ||
| 30 | |||
| 31 | interrupts: | ||
| 32 | maxItems: 1 | ||
| 33 | |||
| 34 | clocks: | ||
| 35 | minItems: 2 | ||
| 36 | maxItems: 3 | ||
| 37 | |||
| 38 | clock-names: | ||
| 39 | minItems: 2 | ||
| 40 | maxItems: 3 | ||
| 41 | |||
| 42 | resets: | ||
| 43 | items: | ||
| 44 | - description: module reset | ||
| 45 | |||
| 46 | reset-names: | ||
| 47 | items: | ||
| 48 | - const: dsi | ||
| 49 | |||
| 50 | operating-points-v2: | ||
| 51 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 52 | |||
| 53 | power-domains: | ||
| 54 | maxItems: 1 | ||
| 55 | |||
| 56 | avdd-dsi-csi-supply: | ||
| 57 | description: phandle of a supply that powers the DSI controller | ||
| 58 | |||
| 59 | nvidia,mipi-calibrate: | ||
| 60 | description: Should contain a phandle and a specifier specifying | ||
| 61 | which pads are used by this DSI output and need to be | ||
| 62 | calibrated. See nvidia,tegra114-mipi.yaml for details. | ||
| 63 | $ref: "/schemas/types.yaml#/definitions/phandle-array" | ||
| 64 | |||
| 65 | nvidia,ddc-i2c-bus: | ||
| 66 | description: phandle of an I2C controller used for DDC EDID | ||
| 67 | probing | ||
| 68 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 69 | |||
| 70 | nvidia,hpd-gpio: | ||
| 71 | description: specifies a GPIO used for hotplug detection | ||
| 72 | maxItems: 1 | ||
| 73 | |||
| 74 | nvidia,edid: | ||
| 75 | description: supplies a binary EDID blob | ||
| 76 | $ref: "/schemas/types.yaml#/definitions/uint8-array" | ||
| 77 | |||
| 78 | nvidia,panel: | ||
| 79 | description: phandle of a display panel | ||
| 80 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 81 | |||
| 82 | nvidia,ganged-mode: | ||
| 83 | description: contains a phandle to a second DSI controller to | ||
| 84 | gang up with in order to support up to 8 data lanes | ||
| 85 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 86 | |||
| 87 | allOf: | ||
| 88 | - $ref: "../dsi-controller.yaml#" | ||
| 89 | - if: | ||
| 90 | properties: | ||
| 91 | compatible: | ||
| 92 | contains: | ||
| 93 | enum: | ||
| 94 | - nvidia,tegra20-dsi | ||
| 95 | - nvidia,tegra30-dsi | ||
| 96 | then: | ||
| 97 | properties: | ||
| 98 | clocks: | ||
| 99 | items: | ||
| 100 | - description: DSI module clock | ||
| 101 | - description: input for the pixel clock | ||
| 102 | |||
| 103 | clock-names: | ||
| 104 | items: | ||
| 105 | - const: dsi | ||
| 106 | - const: parent | ||
| 107 | else: | ||
| 108 | properties: | ||
| 109 | clocks: | ||
| 110 | items: | ||
| 111 | - description: DSI module clock | ||
| 112 | - description: low-power module clock | ||
| 113 | - description: input for the pixel clock | ||
| 114 | |||
| 115 | clock-names: | ||
| 116 | items: | ||
| 117 | - const: dsi | ||
| 118 | - const: lp | ||
| 119 | - const: parent | ||
| 120 | |||
| 121 | - if: | ||
| 122 | properties: | ||
| 123 | compatible: | ||
| 124 | contains: | ||
| 125 | const: nvidia,tegra186-dsi | ||
| 126 | then: | ||
| 127 | required: | ||
| 128 | - interrupts | ||
| 129 | |||
| 130 | unevaluatedProperties: false | ||
| 131 | |||
| 132 | required: | ||
| 133 | - compatible | ||
| 134 | - reg | ||
| 135 | - clocks | ||
| 136 | - clock-names | ||
| 137 | - resets | ||
| 138 | - reset-names | ||
| 139 | |||
| 140 | examples: | ||
| 141 | - | | ||
| 142 | #include <dt-bindings/clock/tegra186-clock.h> | ||
| 143 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 144 | #include <dt-bindings/power/tegra186-powergate.h> | ||
| 145 | #include <dt-bindings/reset/tegra186-reset.h> | ||
| 146 | |||
| 147 | dsi@15300000 { | ||
| 148 | compatible = "nvidia,tegra186-dsi"; | ||
| 149 | reg = <0x15300000 0x10000>; | ||
| 150 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
| 151 | clocks = <&bpmp TEGRA186_CLK_DSI>, | ||
| 152 | <&bpmp TEGRA186_CLK_DSIA_LP>, | ||
| 153 | <&bpmp TEGRA186_CLK_PLLD>; | ||
| 154 | clock-names = "dsi", "lp", "parent"; | ||
| 155 | resets = <&bpmp TEGRA186_RESET_DSI>; | ||
| 156 | reset-names = "dsi"; | ||
| 157 | |||
| 158 | power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; | ||
| 159 | }; | ||
| @@ -0,0 +1,70 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra Encoder Pre-Processor | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^epp@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra20-epp | ||
| 20 | - nvidia,tegra30-epp | ||
| 21 | - nvidia,tegra114-epp | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | interrupts: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | clocks: | ||
| 30 | maxItems: 1 | ||
| 31 | |||
| 32 | resets: | ||
| 33 | items: | ||
| 34 | - description: module reset | ||
| 35 | |||
| 36 | reset-names: | ||
| 37 | items: | ||
| 38 | - const: epp | ||
| 39 | |||
| 40 | iommus: | ||
| 41 | maxItems: 1 | ||
| 42 | |||
| 43 | interconnects: | ||
| 44 | maxItems: 4 | ||
| 45 | |||
| 46 | interconnect-names: | ||
| 47 | maxItems: 4 | ||
| 48 | |||
| 49 | operating-points-v2: | ||
| 50 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 51 | |||
| 52 | power-domains: | ||
| 53 | items: | ||
| 54 | - description: phandle to the core power domain | ||
| 55 | |||
| 56 | additionalProperties: false | ||
| 57 | |||
| 58 | examples: | ||
| 59 | - | | ||
| 60 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 61 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 62 | |||
| 63 | epp@540c0000 { | ||
| 64 | compatible = "nvidia,tegra20-epp"; | ||
| 65 | reg = <0x540c0000 0x00040000>; | ||
| 66 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | ||
| 67 | clocks = <&tegra_car TEGRA20_CLK_EPP>; | ||
| 68 | resets = <&tegra_car 19>; | ||
| 69 | reset-names = "epp"; | ||
| 70 | }; | ||
| @@ -0,0 +1,74 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA 2D graphics engine | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^gr2d@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra20-gr2d | ||
| 20 | - nvidia,tegra30-gr2d | ||
| 21 | - nvidia,tegra114-gr2d | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | interrupts: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | clocks: | ||
| 30 | items: | ||
| 31 | - description: module clock | ||
| 32 | |||
| 33 | resets: | ||
| 34 | items: | ||
| 35 | - description: module reset | ||
| 36 | - description: memory client hotflush reset | ||
| 37 | |||
| 38 | reset-names: | ||
| 39 | items: | ||
| 40 | - const: 2d | ||
| 41 | - const: mc | ||
| 42 | |||
| 43 | iommus: | ||
| 44 | maxItems: 1 | ||
| 45 | |||
| 46 | interconnects: | ||
| 47 | maxItems: 4 | ||
| 48 | |||
| 49 | interconnect-names: | ||
| 50 | maxItems: 4 | ||
| 51 | |||
| 52 | operating-points-v2: | ||
| 53 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 54 | |||
| 55 | power-domains: | ||
| 56 | items: | ||
| 57 | - description: phandle to the HEG or core power domain | ||
| 58 | |||
| 59 | additionalProperties: false | ||
| 60 | |||
| 61 | examples: | ||
| 62 | - | | ||
| 63 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 64 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 65 | #include <dt-bindings/memory/tegra20-mc.h> | ||
| 66 | |||
| 67 | gr2d@54140000 { | ||
| 68 | compatible = "nvidia,tegra20-gr2d"; | ||
| 69 | reg = <0x54140000 0x00040000>; | ||
| 70 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | ||
| 71 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; | ||
| 72 | resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; | ||
| 73 | reset-names = "2d", "mc"; | ||
| 74 | }; | ||
| @@ -0,0 +1,215 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA 3D graphics engine | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^gr3d@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra20-gr3d | ||
| 20 | - nvidia,tegra30-gr3d | ||
| 21 | - nvidia,tegra114-gr3d | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | clocks: | ||
| 27 | minItems: 1 | ||
| 28 | maxItems: 2 | ||
| 29 | |||
| 30 | clock-names: | ||
| 31 | minItems: 1 | ||
| 32 | maxItems: 2 | ||
| 33 | |||
| 34 | resets: | ||
| 35 | minItems: 2 | ||
| 36 | maxItems: 4 | ||
| 37 | |||
| 38 | reset-names: | ||
| 39 | minItems: 2 | ||
| 40 | maxItems: 4 | ||
| 41 | |||
| 42 | iommus: | ||
| 43 | minItems: 1 | ||
| 44 | maxItems: 2 | ||
| 45 | |||
| 46 | interconnects: | ||
| 47 | minItems: 4 | ||
| 48 | maxItems: 10 | ||
| 49 | |||
| 50 | interconnect-names: | ||
| 51 | minItems: 4 | ||
| 52 | maxItems: 10 | ||
| 53 | |||
| 54 | operating-points-v2: | ||
| 55 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 56 | |||
| 57 | power-domains: | ||
| 58 | minItems: 1 | ||
| 59 | maxItems: 2 | ||
| 60 | |||
| 61 | power-domain-names: | ||
| 62 | minItems: 2 | ||
| 63 | maxItems: 2 | ||
| 64 | |||
| 65 | allOf: | ||
| 66 | - if: | ||
| 67 | properties: | ||
| 68 | compatible: | ||
| 69 | contains: | ||
| 70 | const: nvidia,tegra20-gr2d | ||
| 71 | then: | ||
| 72 | properties: | ||
| 73 | clocks: | ||
| 74 | items: | ||
| 75 | - description: module clock | ||
| 76 | |||
| 77 | clock-names: | ||
| 78 | items: | ||
| 79 | - const: 3d | ||
| 80 | |||
| 81 | resets: | ||
| 82 | items: | ||
| 83 | - description: module reset | ||
| 84 | - description: memory client hotflush reset | ||
| 85 | |||
| 86 | reset-names: | ||
| 87 | items: | ||
| 88 | - const: 3d | ||
| 89 | - const: mc | ||
| 90 | |||
| 91 | iommus: | ||
| 92 | maxItems: 1 | ||
| 93 | |||
| 94 | interconnects: | ||
| 95 | minItems: 4 | ||
| 96 | maxItems: 4 | ||
| 97 | |||
| 98 | interconnect-names: | ||
| 99 | minItems: 4 | ||
| 100 | maxItems: 4 | ||
| 101 | |||
| 102 | power-domains: | ||
| 103 | items: | ||
| 104 | - description: phandle to the TD power domain | ||
| 105 | |||
| 106 | - if: | ||
| 107 | properties: | ||
| 108 | compatible: | ||
| 109 | contains: | ||
| 110 | const: nvidia,tegra30-gr3d | ||
| 111 | then: | ||
| 112 | properties: | ||
| 113 | clocks: | ||
| 114 | items: | ||
| 115 | - description: primary module clock | ||
| 116 | - description: secondary module clock | ||
| 117 | |||
| 118 | clock-names: | ||
| 119 | items: | ||
| 120 | - const: 3d | ||
| 121 | - const: 3d2 | ||
| 122 | |||
| 123 | resets: | ||
| 124 | items: | ||
| 125 | - description: primary module reset | ||
| 126 | - description: secondary module reset | ||
| 127 | - description: primary memory client hotflush reset | ||
| 128 | - description: secondary memory client hotflush reset | ||
| 129 | |||
| 130 | reset-names: | ||
| 131 | items: | ||
| 132 | - const: 3d | ||
| 133 | - const: 3d2 | ||
| 134 | - const: mc | ||
| 135 | - const: mc2 | ||
| 136 | |||
| 137 | iommus: | ||
| 138 | minItems: 2 | ||
| 139 | maxItems: 2 | ||
| 140 | |||
| 141 | interconnects: | ||
| 142 | minItems: 8 | ||
| 143 | maxItems: 8 | ||
| 144 | |||
| 145 | interconnect-names: | ||
| 146 | minItems: 8 | ||
| 147 | maxItems: 8 | ||
| 148 | |||
| 149 | power-domains: | ||
| 150 | items: | ||
| 151 | - description: phandle to the TD power domain | ||
| 152 | - description: phandle to the TD2 power domain | ||
| 153 | |||
| 154 | power-domain-names: | ||
| 155 | items: | ||
| 156 | - const: 3d0 | ||
| 157 | - const: 3d1 | ||
| 158 | |||
| 159 | dependencies: | ||
| 160 | power-domains: [ power-domain-names ] | ||
| 161 | |||
| 162 | - if: | ||
| 163 | properties: | ||
| 164 | compatible: | ||
| 165 | contains: | ||
| 166 | const: nvidia,tegra114-gr2d | ||
| 167 | then: | ||
| 168 | properties: | ||
| 169 | clocks: | ||
| 170 | items: | ||
| 171 | - description: module clock | ||
| 172 | |||
| 173 | clock-names: | ||
| 174 | items: | ||
| 175 | - const: 3d | ||
| 176 | |||
| 177 | resets: | ||
| 178 | items: | ||
| 179 | - description: module reset | ||
| 180 | - description: memory client hotflush reset | ||
| 181 | |||
| 182 | reset-names: | ||
| 183 | items: | ||
| 184 | - const: 3d | ||
| 185 | - const: mc | ||
| 186 | |||
| 187 | iommus: | ||
| 188 | maxItems: 1 | ||
| 189 | |||
| 190 | interconnects: | ||
| 191 | minItems: 10 | ||
| 192 | maxItems: 10 | ||
| 193 | |||
| 194 | interconnect-names: | ||
| 195 | minItems: 10 | ||
| 196 | maxItems: 10 | ||
| 197 | |||
| 198 | power-domains: | ||
| 199 | items: | ||
| 200 | - description: phandle to the TD power domain | ||
| 201 | |||
| 202 | additionalProperties: false | ||
| 203 | |||
| 204 | examples: | ||
| 205 | - | | ||
| 206 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 207 | #include <dt-bindings/memory/tegra20-mc.h> | ||
| 208 | |||
| 209 | gr3d@54180000 { | ||
| 210 | compatible = "nvidia,tegra20-gr3d"; | ||
| 211 | reg = <0x54180000 0x00040000>; | ||
| 212 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; | ||
| 213 | resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; | ||
| 214 | reset-names = "3d", "mc"; | ||
| 215 | }; | ||
| @@ -0,0 +1,126 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra HDMI Output Encoder | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^hdmi@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | oneOf: | ||
| 19 | - enum: | ||
| 20 | - nvidia,tegra20-hdmi | ||
| 21 | - nvidia,tegra30-hdmi | ||
| 22 | - nvidia,tegra114-hdmi | ||
| 23 | - nvidia,tegra124-hdmi | ||
| 24 | |||
| 25 | - items: | ||
| 26 | - const: nvidia,tegra132-hdmi | ||
| 27 | - const: nvidia,tegra124-hdmi | ||
| 28 | |||
| 29 | reg: | ||
| 30 | maxItems: 1 | ||
| 31 | |||
| 32 | interrupts: | ||
| 33 | maxItems: 1 | ||
| 34 | |||
| 35 | clocks: | ||
| 36 | items: | ||
| 37 | - description: module clock | ||
| 38 | - description: parent clock | ||
| 39 | |||
| 40 | clock-names: | ||
| 41 | items: | ||
| 42 | - const: hdmi | ||
| 43 | - const: parent | ||
| 44 | |||
| 45 | resets: | ||
| 46 | items: | ||
| 47 | - description: module reset | ||
| 48 | |||
| 49 | reset-names: | ||
| 50 | items: | ||
| 51 | - const: hdmi | ||
| 52 | |||
| 53 | operating-points-v2: | ||
| 54 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 55 | |||
| 56 | power-domains: | ||
| 57 | items: | ||
| 58 | - description: phandle to the core power domain | ||
| 59 | |||
| 60 | hdmi-supply: | ||
| 61 | description: supply for the +5V HDMI connector pin | ||
| 62 | |||
| 63 | vdd-supply: | ||
| 64 | description: regulator for supply voltage | ||
| 65 | |||
| 66 | pll-supply: | ||
| 67 | description: regulator for PLL | ||
| 68 | |||
| 69 | nvidia,ddc-i2c-bus: | ||
| 70 | description: phandle of an I2C controller used for DDC EDID | ||
| 71 | probing | ||
| 72 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 73 | |||
| 74 | nvidia,hpd-gpio: | ||
| 75 | description: specifies a GPIO used for hotplug detection | ||
| 76 | maxItems: 1 | ||
| 77 | |||
| 78 | nvidia,edid: | ||
| 79 | description: supplies a binary EDID blob | ||
| 80 | $ref: "/schemas/types.yaml#/definitions/uint8-array" | ||
| 81 | |||
| 82 | nvidia,panel: | ||
| 83 | description: phandle of a display panel | ||
| 84 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 85 | |||
| 86 | "#sound-dai-cells": | ||
| 87 | const: 0 | ||
| 88 | |||
| 89 | additionalProperties: false | ||
| 90 | |||
| 91 | required: | ||
| 92 | - compatible | ||
| 93 | - reg | ||
| 94 | - interrupts | ||
| 95 | - clocks | ||
| 96 | - clock-names | ||
| 97 | - resets | ||
| 98 | - reset-names | ||
| 99 | - pll-supply | ||
| 100 | - vdd-supply | ||
| 101 | - nvidia,ddc-i2c-bus | ||
| 102 | - nvidia,hpd-gpio | ||
| 103 | |||
| 104 | examples: | ||
| 105 | - | | ||
| 106 | #include <dt-bindings/clock/tegra124-car.h> | ||
| 107 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 108 | #include <dt-bindings/gpio/tegra-gpio.h> | ||
| 109 | |||
| 110 | hdmi@54280000 { | ||
| 111 | compatible = "nvidia,tegra124-hdmi"; | ||
| 112 | reg = <0x54280000 0x00040000>; | ||
| 113 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | ||
| 114 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, | ||
| 115 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; | ||
| 116 | clock-names = "hdmi", "parent"; | ||
| 117 | resets = <&tegra_car 51>; | ||
| 118 | reset-names = "hdmi"; | ||
| 119 | |||
| 120 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 121 | pll-supply = <&vdd_hdmi_pll>; | ||
| 122 | vdd-supply = <&vdd_3v3_hdmi>; | ||
| 123 | |||
| 124 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
| 125 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | ||
| 126 | }; | ||
| @@ -1,675 +0,0 @@ | |||
| 1 | NVIDIA Tegra host1x | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: "nvidia,tegra<chip>-host1x" | ||
| 5 | - reg: Physical base address and length of the controller's registers. | ||
| 6 | For pre-Tegra186, one entry describing the whole register area. | ||
| 7 | For Tegra186, one entry for each entry in reg-names: | ||
| 8 | "vm" - VM region assigned to Linux | ||
| 9 | "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) | ||
| 10 | - interrupts: The interrupt outputs from the controller. | ||
| 11 | - #address-cells: The number of cells used to represent physical base addresses | ||
| 12 | in the host1x address space. Should be 1. | ||
| 13 | - #size-cells: The number of cells used to represent the size of an address | ||
| 14 | range in the host1x address space. Should be 1. | ||
| 15 | - ranges: The mapping of the host1x address space to the CPU address space. | ||
| 16 | - clocks: Must contain one entry, for the module clock. | ||
| 17 | See ../clocks/clock-bindings.txt for details. | ||
| 18 | - resets: Must contain an entry for each entry in reset-names. | ||
| 19 | See ../reset/reset.txt for details. | ||
| 20 | - reset-names: Must include the following entries: | ||
| 21 | - host1x | ||
| 22 | - mc | ||
| 23 | |||
| 24 | Optional properties: | ||
| 25 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 26 | - power-domains: Phandle to HEG or core power domain. | ||
| 27 | |||
| 28 | For each opp entry in 'operating-points-v2' table of host1x and its modules: | ||
| 29 | - opp-supported-hw: One bitfield indicating: | ||
| 30 | On Tegra20: SoC process ID mask | ||
| 31 | On Tegra30+: SoC speedo ID mask | ||
| 32 | |||
| 33 | A bitwise AND is performed against the value and if any bit | ||
| 34 | matches, the OPP gets enabled. | ||
| 35 | |||
| 36 | Each host1x client module having to perform DMA through the Memory Controller | ||
| 37 | should have the interconnect endpoints set to the Memory Client and External | ||
| 38 | Memory respectively. | ||
| 39 | |||
| 40 | The host1x top-level node defines a number of children, each representing one | ||
| 41 | of the following host1x client modules: | ||
| 42 | |||
| 43 | - mpe: video encoder | ||
| 44 | |||
| 45 | Required properties: | ||
| 46 | - compatible: "nvidia,tegra<chip>-mpe" | ||
| 47 | - reg: Physical base address and length of the controller's registers. | ||
| 48 | - interrupts: The interrupt outputs from the controller. | ||
| 49 | - clocks: Must contain one entry, for the module clock. | ||
| 50 | See ../clocks/clock-bindings.txt for details. | ||
| 51 | - resets: Must contain an entry for each entry in reset-names. | ||
| 52 | See ../reset/reset.txt for details. | ||
| 53 | - reset-names: Must include the following entries: | ||
| 54 | - mpe | ||
| 55 | |||
| 56 | Optional properties: | ||
| 57 | - interconnects: Must contain entry for the MPE memory clients. | ||
| 58 | - interconnect-names: Must include name of the interconnect path for each | ||
| 59 | interconnect entry. Consult TRM documentation for information about | ||
| 60 | available memory clients, see MEMORY CONTROLLER section. | ||
| 61 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 62 | - power-domains: Phandle to MPE power domain. | ||
| 63 | |||
| 64 | - vi: video input | ||
| 65 | |||
| 66 | Required properties: | ||
| 67 | - compatible: "nvidia,tegra<chip>-vi" | ||
| 68 | - reg: Physical base address and length of the controller registers. | ||
| 69 | - interrupts: The interrupt outputs from the controller. | ||
| 70 | - clocks: clocks: Must contain one entry, for the module clock. | ||
| 71 | See ../clocks/clock-bindings.txt for details. | ||
| 72 | - Tegra20/Tegra30/Tegra114/Tegra124: | ||
| 73 | - resets: Must contain an entry for each entry in reset-names. | ||
| 74 | See ../reset/reset.txt for details. | ||
| 75 | - reset-names: Must include the following entries: | ||
| 76 | - vi | ||
| 77 | - Tegra210: | ||
| 78 | - power-domains: Must include venc powergate node as vi is in VE partition. | ||
| 79 | |||
| 80 | ports (optional node) | ||
| 81 | vi can have optional ports node and max 6 ports are supported. Each port | ||
| 82 | should have single 'endpoint' child node. All port nodes are grouped under | ||
| 83 | ports node. Please refer to the bindings defined in | ||
| 84 | Documentation/devicetree/bindings/media/video-interfaces.txt | ||
| 85 | |||
| 86 | csi (required node) | ||
| 87 | Tegra210 has CSI part of VI sharing same host interface and register space. | ||
| 88 | So, VI device node should have CSI child node. | ||
| 89 | |||
| 90 | - csi: mipi csi interface to vi | ||
| 91 | |||
| 92 | Required properties: | ||
| 93 | - compatible: "nvidia,tegra210-csi" | ||
| 94 | - reg: Physical base address offset to parent and length of the controller | ||
| 95 | registers. | ||
| 96 | - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. | ||
| 97 | See ../clocks/clock-bindings.txt for details. | ||
| 98 | - power-domains: Must include sor powergate node as csicil is in | ||
| 99 | SOR partition. | ||
| 100 | |||
| 101 | channel (optional nodes) | ||
| 102 | Maximum 6 channels are supported with each csi brick as either x4 or x2 | ||
| 103 | based on hw connectivity to sensor. | ||
| 104 | |||
| 105 | Required properties: | ||
| 106 | - reg: csi port number. Valid port numbers are 0 through 5. | ||
| 107 | - nvidia,mipi-calibrate: Should contain a phandle and a specifier | ||
| 108 | specifying which pads are used by this CSI port and need to be | ||
| 109 | calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. | ||
| 110 | |||
| 111 | Each channel node must contain 2 port nodes which can be grouped | ||
| 112 | under 'ports' node and each port should have a single child 'endpoint' | ||
| 113 | node. | ||
| 114 | |||
| 115 | ports node | ||
| 116 | Please refer to the bindings defined in | ||
| 117 | Documentation/devicetree/bindings/media/video-interfaces.txt | ||
| 118 | |||
| 119 | ports node must contain below 2 port nodes. | ||
| 120 | port@0 with single child 'endpoint' node always a sink. | ||
| 121 | port@1 with single child 'endpoint' node always a source. | ||
| 122 | |||
| 123 | port@0 (required node) | ||
| 124 | Required properties: | ||
| 125 | - reg: 0 | ||
| 126 | |||
| 127 | endpoint (required node) | ||
| 128 | Required properties: | ||
| 129 | - data-lanes: an array of data lane from 1 to 8. Valid array | ||
| 130 | lengths are 1/2/4/8. | ||
| 131 | - remote-endpoint: phandle to sensor 'endpoint' node. | ||
| 132 | |||
| 133 | port@1 (required node) | ||
| 134 | Required properties: | ||
| 135 | - reg: 1 | ||
| 136 | |||
| 137 | endpoint (required node) | ||
| 138 | Required properties: | ||
| 139 | - remote-endpoint: phandle to vi port 'endpoint' node. | ||
| 140 | |||
| 141 | Optional properties: | ||
| 142 | - interconnects: Must contain entry for the VI memory clients. | ||
| 143 | - interconnect-names: Must include name of the interconnect path for each | ||
| 144 | interconnect entry. Consult TRM documentation for information about | ||
| 145 | available memory clients, see MEMORY CONTROLLER section. | ||
| 146 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 147 | - power-domains: Phandle to VENC power domain. | ||
| 148 | |||
| 149 | - epp: encoder pre-processor | ||
| 150 | |||
| 151 | Required properties: | ||
| 152 | - compatible: "nvidia,tegra<chip>-epp" | ||
| 153 | - reg: Physical base address and length of the controller's registers. | ||
| 154 | - interrupts: The interrupt outputs from the controller. | ||
| 155 | - clocks: Must contain one entry, for the module clock. | ||
| 156 | See ../clocks/clock-bindings.txt for details. | ||
| 157 | - resets: Must contain an entry for each entry in reset-names. | ||
| 158 | See ../reset/reset.txt for details. | ||
| 159 | - reset-names: Must include the following entries: | ||
| 160 | - epp | ||
| 161 | |||
| 162 | Optional properties: | ||
| 163 | - interconnects: Must contain entry for the EPP memory clients. | ||
| 164 | - interconnect-names: Must include name of the interconnect path for each | ||
| 165 | interconnect entry. Consult TRM documentation for information about | ||
| 166 | available memory clients, see MEMORY CONTROLLER section. | ||
| 167 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 168 | - power-domains: Phandle to HEG or core power domain. | ||
| 169 | |||
| 170 | - isp: image signal processor | ||
| 171 | |||
| 172 | Required properties: | ||
| 173 | - compatible: "nvidia,tegra<chip>-isp" | ||
| 174 | - reg: Physical base address and length of the controller's registers. | ||
| 175 | - interrupts: The interrupt outputs from the controller. | ||
| 176 | - clocks: Must contain one entry, for the module clock. | ||
| 177 | See ../clocks/clock-bindings.txt for details. | ||
| 178 | - resets: Must contain an entry for each entry in reset-names. | ||
| 179 | See ../reset/reset.txt for details. | ||
| 180 | - reset-names: Must include the following entries: | ||
| 181 | - isp | ||
| 182 | |||
| 183 | Optional properties: | ||
| 184 | - interconnects: Must contain entry for the ISP memory clients. | ||
| 185 | - interconnect-names: Must include name of the interconnect path for each | ||
| 186 | interconnect entry. Consult TRM documentation for information about | ||
| 187 | available memory clients, see MEMORY CONTROLLER section. | ||
| 188 | - power-domains: Phandle to VENC or core power domain. | ||
| 189 | |||
| 190 | - gr2d: 2D graphics engine | ||
| 191 | |||
| 192 | Required properties: | ||
| 193 | - compatible: "nvidia,tegra<chip>-gr2d" | ||
| 194 | - reg: Physical base address and length of the controller's registers. | ||
| 195 | - interrupts: The interrupt outputs from the controller. | ||
| 196 | - clocks: Must contain one entry, for the module clock. | ||
| 197 | See ../clocks/clock-bindings.txt for details. | ||
| 198 | - resets: Must contain an entry for each entry in reset-names. | ||
| 199 | See ../reset/reset.txt for details. | ||
| 200 | - reset-names: Must include the following entries: | ||
| 201 | - 2d | ||
| 202 | - mc | ||
| 203 | |||
| 204 | Optional properties: | ||
| 205 | - interconnects: Must contain entry for the GR2D memory clients. | ||
| 206 | - interconnect-names: Must include name of the interconnect path for each | ||
| 207 | interconnect entry. Consult TRM documentation for information about | ||
| 208 | available memory clients, see MEMORY CONTROLLER section. | ||
| 209 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 210 | - power-domains: Phandle to HEG or core power domain. | ||
| 211 | |||
| 212 | - gr3d: 3D graphics engine | ||
| 213 | |||
| 214 | Required properties: | ||
| 215 | - compatible: "nvidia,tegra<chip>-gr3d" | ||
| 216 | - reg: Physical base address and length of the controller's registers. | ||
| 217 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 218 | See ../clocks/clock-bindings.txt for details. | ||
| 219 | - clock-names: Must include the following entries: | ||
| 220 | (This property may be omitted if the only clock in the list is "3d") | ||
| 221 | - 3d | ||
| 222 | This MUST be the first entry. | ||
| 223 | - 3d2 (Only required on SoCs with two 3D clocks) | ||
| 224 | - resets: Must contain an entry for each entry in reset-names. | ||
| 225 | See ../reset/reset.txt for details. | ||
| 226 | - reset-names: Must include the following entries: | ||
| 227 | - 3d | ||
| 228 | - 3d2 (Only required on SoCs with two 3D clocks) | ||
| 229 | - mc | ||
| 230 | - mc2 (Only required on SoCs with two 3D clocks) | ||
| 231 | |||
| 232 | Optional properties: | ||
| 233 | - interconnects: Must contain entry for the GR3D memory clients. | ||
| 234 | - interconnect-names: Must include name of the interconnect path for each | ||
| 235 | interconnect entry. Consult TRM documentation for information about | ||
| 236 | available memory clients, see MEMORY CONTROLLER section. | ||
| 237 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 238 | - power-domains: Phandles to 3D or core power domain. | ||
| 239 | |||
| 240 | - dc: display controller | ||
| 241 | |||
| 242 | Required properties: | ||
| 243 | - compatible: "nvidia,tegra<chip>-dc" | ||
| 244 | - reg: Physical base address and length of the controller's registers. | ||
| 245 | - interrupts: The interrupt outputs from the controller. | ||
| 246 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 247 | See ../clocks/clock-bindings.txt for details. | ||
| 248 | - clock-names: Must include the following entries: | ||
| 249 | - dc | ||
| 250 | This MUST be the first entry. | ||
| 251 | - parent | ||
| 252 | - resets: Must contain an entry for each entry in reset-names. | ||
| 253 | See ../reset/reset.txt for details. | ||
| 254 | - reset-names: Must include the following entries: | ||
| 255 | - dc | ||
| 256 | - nvidia,head: The number of the display controller head. This is used to | ||
| 257 | setup the various types of output to receive video data from the given | ||
| 258 | head. | ||
| 259 | |||
| 260 | Each display controller node has a child node, named "rgb", that represents | ||
| 261 | the RGB output associated with the controller. It can take the following | ||
| 262 | optional properties: | ||
| 263 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
| 264 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
| 265 | - nvidia,edid: supplies a binary EDID blob | ||
| 266 | - nvidia,panel: phandle of a display panel | ||
| 267 | - interconnects: Must contain entry for the DC memory clients. | ||
| 268 | - interconnect-names: Must include name of the interconnect path for each | ||
| 269 | interconnect entry. Consult TRM documentation for information about | ||
| 270 | available memory clients, see MEMORY CONTROLLER section. | ||
| 271 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 272 | - power-domains: Phandle to core power domain. | ||
| 273 | |||
| 274 | - hdmi: High Definition Multimedia Interface | ||
| 275 | |||
| 276 | Required properties: | ||
| 277 | - compatible: "nvidia,tegra<chip>-hdmi" | ||
| 278 | - reg: Physical base address and length of the controller's registers. | ||
| 279 | - interrupts: The interrupt outputs from the controller. | ||
| 280 | - hdmi-supply: supply for the +5V HDMI connector pin | ||
| 281 | - vdd-supply: regulator for supply voltage | ||
| 282 | - pll-supply: regulator for PLL | ||
| 283 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 284 | See ../clocks/clock-bindings.txt for details. | ||
| 285 | - clock-names: Must include the following entries: | ||
| 286 | - hdmi | ||
| 287 | This MUST be the first entry. | ||
| 288 | - parent | ||
| 289 | - resets: Must contain an entry for each entry in reset-names. | ||
| 290 | See ../reset/reset.txt for details. | ||
| 291 | - reset-names: Must include the following entries: | ||
| 292 | - hdmi | ||
| 293 | |||
| 294 | Optional properties: | ||
| 295 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
| 296 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
| 297 | - nvidia,edid: supplies a binary EDID blob | ||
| 298 | - nvidia,panel: phandle of a display panel | ||
| 299 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 300 | |||
| 301 | - tvo: TV encoder output | ||
| 302 | |||
| 303 | Required properties: | ||
| 304 | - compatible: "nvidia,tegra<chip>-tvo" | ||
| 305 | - reg: Physical base address and length of the controller's registers. | ||
| 306 | - interrupts: The interrupt outputs from the controller. | ||
| 307 | - clocks: Must contain one entry, for the module clock. | ||
| 308 | See ../clocks/clock-bindings.txt for details. | ||
| 309 | |||
| 310 | Optional properties: | ||
| 311 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 312 | - power-domains: Phandle to core power domain. | ||
| 313 | |||
| 314 | - dsi: display serial interface | ||
| 315 | |||
| 316 | Required properties: | ||
| 317 | - compatible: "nvidia,tegra<chip>-dsi" | ||
| 318 | - reg: Physical base address and length of the controller's registers. | ||
| 319 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 320 | See ../clocks/clock-bindings.txt for details. | ||
| 321 | - clock-names: Must include the following entries: | ||
| 322 | - dsi | ||
| 323 | This MUST be the first entry. | ||
| 324 | - lp | ||
| 325 | - parent | ||
| 326 | - resets: Must contain an entry for each entry in reset-names. | ||
| 327 | See ../reset/reset.txt for details. | ||
| 328 | - reset-names: Must include the following entries: | ||
| 329 | - dsi | ||
| 330 | - avdd-dsi-supply: phandle of a supply that powers the DSI controller | ||
| 331 | - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying | ||
| 332 | which pads are used by this DSI output and need to be calibrated. See also | ||
| 333 | ../display/tegra/nvidia,tegra114-mipi.txt. | ||
| 334 | |||
| 335 | Optional properties: | ||
| 336 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
| 337 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
| 338 | - nvidia,edid: supplies a binary EDID blob | ||
| 339 | - nvidia,panel: phandle of a display panel | ||
| 340 | - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang | ||
| 341 | up with in order to support up to 8 data lanes | ||
| 342 | - operating-points-v2: See ../bindings/opp/opp.txt for details. | ||
| 343 | |||
| 344 | - sor: serial output resource | ||
| 345 | |||
| 346 | Required properties: | ||
| 347 | - compatible: Should be: | ||
| 348 | - "nvidia,tegra124-sor": for Tegra124 and Tegra132 | ||
| 349 | - "nvidia,tegra132-sor": for Tegra132 | ||
| 350 | - "nvidia,tegra210-sor": for Tegra210 | ||
| 351 | - "nvidia,tegra210-sor1": for Tegra210 | ||
| 352 | - "nvidia,tegra186-sor": for Tegra186 | ||
| 353 | - "nvidia,tegra186-sor1": for Tegra186 | ||
| 354 | - reg: Physical base address and length of the controller's registers. | ||
| 355 | - interrupts: The interrupt outputs from the controller. | ||
| 356 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 357 | See ../clocks/clock-bindings.txt for details. | ||
| 358 | - clock-names: Must include the following entries: | ||
| 359 | - sor: clock input for the SOR hardware | ||
| 360 | - out: SOR output clock | ||
| 361 | - parent: input for the pixel clock | ||
| 362 | - dp: reference clock for the SOR clock | ||
| 363 | - safe: safe reference for the SOR clock during power up | ||
| 364 | |||
| 365 | For Tegra186 and later: | ||
| 366 | - pad: SOR pad output clock (on Tegra186 and later) | ||
| 367 | |||
| 368 | Obsolete: | ||
| 369 | - source: source clock for the SOR clock (obsolete, use "out" instead) | ||
| 370 | |||
| 371 | - resets: Must contain an entry for each entry in reset-names. | ||
| 372 | See ../reset/reset.txt for details. | ||
| 373 | - reset-names: Must include the following entries: | ||
| 374 | - sor | ||
| 375 | |||
| 376 | Required properties on Tegra186 and later: | ||
| 377 | - nvidia,interface: index of the SOR interface | ||
| 378 | |||
| 379 | Optional properties: | ||
| 380 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
| 381 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
| 382 | - nvidia,edid: supplies a binary EDID blob | ||
| 383 | - nvidia,panel: phandle of a display panel | ||
| 384 | - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane | ||
| 385 | of the SOR, identified by the cell's index, is mapped via the crossbar to | ||
| 386 | the pad specified by the cell's value. | ||
| 387 | |||
| 388 | Optional properties when driving an eDP output: | ||
| 389 | - nvidia,dpaux: phandle to a DispayPort AUX interface | ||
| 390 | |||
| 391 | - dpaux: DisplayPort AUX interface | ||
| 392 | - compatible : Should contain one of the following: | ||
| 393 | - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 | ||
| 394 | - "nvidia,tegra210-dpaux": for Tegra210 | ||
| 395 | - reg: Physical base address and length of the controller's registers. | ||
| 396 | - interrupts: The interrupt outputs from the controller. | ||
| 397 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 398 | See ../clocks/clock-bindings.txt for details. | ||
| 399 | - clock-names: Must include the following entries: | ||
| 400 | - dpaux: clock input for the DPAUX hardware | ||
| 401 | - parent: reference clock | ||
| 402 | - resets: Must contain an entry for each entry in reset-names. | ||
| 403 | See ../reset/reset.txt for details. | ||
| 404 | - reset-names: Must include the following entries: | ||
| 405 | - dpaux | ||
| 406 | - vdd-supply: phandle of a supply that powers the DisplayPort link | ||
| 407 | - i2c-bus: Subnode where I2C slave devices are listed. This subnode | ||
| 408 | must be always present. If there are no I2C slave devices, an empty | ||
| 409 | node should be added. See ../../i2c/i2c.txt for more information. | ||
| 410 | |||
| 411 | See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information | ||
| 412 | regarding the DPAUX pad controller bindings. | ||
| 413 | |||
| 414 | - vic: Video Image Compositor | ||
| 415 | - compatible : "nvidia,tegra<chip>-vic" | ||
| 416 | - reg: Physical base address and length of the controller's registers. | ||
| 417 | - interrupts: The interrupt outputs from the controller. | ||
| 418 | - clocks: Must contain an entry for each entry in clock-names. | ||
| 419 | See ../clocks/clock-bindings.txt for details. | ||
| 420 | - clock-names: Must include the following entries: | ||
| 421 | - vic: clock input for the VIC hardware | ||
| 422 | - resets: Must contain an entry for each entry in reset-names. | ||
| 423 | See ../reset/reset.txt for details. | ||
| 424 | - reset-names: Must include the following entries: | ||
| 425 | - vic | ||
| 426 | |||
| 427 | Optional properties: | ||
| 428 | - interconnects: Must contain entry for the VIC memory clients. | ||
| 429 | - interconnect-names: Must include name of the interconnect path for each | ||
| 430 | interconnect entry. Consult TRM documentation for information about | ||
| 431 | available memory clients, see MEMORY CONTROLLER section. | ||
| 432 | |||
| 433 | Example: | ||
| 434 | |||
| 435 | / { | ||
| 436 | ... | ||
| 437 | |||
| 438 | host1x { | ||
| 439 | compatible = "nvidia,tegra20-host1x", "simple-bus"; | ||
| 440 | reg = <0x50000000 0x00024000>; | ||
| 441 | interrupts = <0 65 0x04 /* mpcore syncpt */ | ||
| 442 | 0 67 0x04>; /* mpcore general */ | ||
| 443 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; | ||
| 444 | resets = <&tegra_car 28>; | ||
| 445 | reset-names = "host1x"; | ||
| 446 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 447 | power-domains = <&domain>; | ||
| 448 | |||
| 449 | #address-cells = <1>; | ||
| 450 | #size-cells = <1>; | ||
| 451 | |||
| 452 | ranges = <0x54000000 0x54000000 0x04000000>; | ||
| 453 | |||
| 454 | mpe { | ||
| 455 | compatible = "nvidia,tegra20-mpe"; | ||
| 456 | reg = <0x54040000 0x00040000>; | ||
| 457 | interrupts = <0 68 0x04>; | ||
| 458 | clocks = <&tegra_car TEGRA20_CLK_MPE>; | ||
| 459 | resets = <&tegra_car 60>; | ||
| 460 | reset-names = "mpe"; | ||
| 461 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 462 | power-domains = <&domain>; | ||
| 463 | }; | ||
| 464 | |||
| 465 | vi@54080000 { | ||
| 466 | compatible = "nvidia,tegra210-vi"; | ||
| 467 | reg = <0x0 0x54080000 0x0 0x700>; | ||
| 468 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | ||
| 469 | assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; | ||
| 470 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; | ||
| 471 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 472 | |||
| 473 | clocks = <&tegra_car TEGRA210_CLK_VI>; | ||
| 474 | power-domains = <&pd_venc>; | ||
| 475 | |||
| 476 | #address-cells = <1>; | ||
| 477 | #size-cells = <1>; | ||
| 478 | |||
| 479 | ranges = <0x0 0x0 0x54080000 0x2000>; | ||
| 480 | |||
| 481 | ports { | ||
| 482 | #address-cells = <1>; | ||
| 483 | #size-cells = <0>; | ||
| 484 | |||
| 485 | port@0 { | ||
| 486 | reg = <0>; | ||
| 487 | imx219_vi_in0: endpoint { | ||
| 488 | remote-endpoint = <&imx219_csi_out0>; | ||
| 489 | }; | ||
| 490 | }; | ||
| 491 | }; | ||
| 492 | |||
| 493 | csi@838 { | ||
| 494 | compatible = "nvidia,tegra210-csi"; | ||
| 495 | reg = <0x838 0x1300>; | ||
| 496 | assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, | ||
| 497 | <&tegra_car TEGRA210_CLK_CILCD>, | ||
| 498 | <&tegra_car TEGRA210_CLK_CILE>, | ||
| 499 | <&tegra_car TEGRA210_CLK_CSI_TPG>; | ||
| 500 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, | ||
| 501 | <&tegra_car TEGRA210_CLK_PLL_P>, | ||
| 502 | <&tegra_car TEGRA210_CLK_PLL_P>; | ||
| 503 | assigned-clock-rates = <102000000>, | ||
| 504 | <102000000>, | ||
| 505 | <102000000>, | ||
| 506 | <972000000>; | ||
| 507 | |||
| 508 | clocks = <&tegra_car TEGRA210_CLK_CSI>, | ||
| 509 | <&tegra_car TEGRA210_CLK_CILAB>, | ||
| 510 | <&tegra_car TEGRA210_CLK_CILCD>, | ||
| 511 | <&tegra_car TEGRA210_CLK_CILE>, | ||
| 512 | <&tegra_car TEGRA210_CLK_CSI_TPG>; | ||
| 513 | clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; | ||
| 514 | power-domains = <&pd_sor>; | ||
| 515 | |||
| 516 | #address-cells = <1>; | ||
| 517 | #size-cells = <0>; | ||
| 518 | |||
| 519 | channel@0 { | ||
| 520 | reg = <0>; | ||
| 521 | nvidia,mipi-calibrate = <&mipi 0x001>; | ||
| 522 | |||
| 523 | ports { | ||
| 524 | #address-cells = <1>; | ||
| 525 | #size-cells = <0>; | ||
| 526 | |||
| 527 | port@0 { | ||
| 528 | reg = <0>; | ||
| 529 | imx219_csi_in0: endpoint { | ||
| 530 | data-lanes = <1 2>; | ||
| 531 | remote-endpoint = <&imx219_out0>; | ||
| 532 | }; | ||
| 533 | }; | ||
| 534 | |||
| 535 | port@1 { | ||
| 536 | reg = <1>; | ||
| 537 | imx219_csi_out0: endpoint { | ||
| 538 | remote-endpoint = <&imx219_vi_in0>; | ||
| 539 | }; | ||
| 540 | }; | ||
| 541 | }; | ||
| 542 | }; | ||
| 543 | }; | ||
| 544 | }; | ||
| 545 | |||
| 546 | epp { | ||
| 547 | compatible = "nvidia,tegra20-epp"; | ||
| 548 | reg = <0x540c0000 0x00040000>; | ||
| 549 | interrupts = <0 70 0x04>; | ||
| 550 | clocks = <&tegra_car TEGRA20_CLK_EPP>; | ||
| 551 | resets = <&tegra_car 19>; | ||
| 552 | reset-names = "epp"; | ||
| 553 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 554 | power-domains = <&domain>; | ||
| 555 | }; | ||
| 556 | |||
| 557 | isp { | ||
| 558 | compatible = "nvidia,tegra20-isp"; | ||
| 559 | reg = <0x54100000 0x00040000>; | ||
| 560 | interrupts = <0 71 0x04>; | ||
| 561 | clocks = <&tegra_car TEGRA20_CLK_ISP>; | ||
| 562 | resets = <&tegra_car 23>; | ||
| 563 | reset-names = "isp"; | ||
| 564 | }; | ||
| 565 | |||
| 566 | gr2d { | ||
| 567 | compatible = "nvidia,tegra20-gr2d"; | ||
| 568 | reg = <0x54140000 0x00040000>; | ||
| 569 | interrupts = <0 72 0x04>; | ||
| 570 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; | ||
| 571 | resets = <&tegra_car 21>; | ||
| 572 | reset-names = "2d"; | ||
| 573 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 574 | power-domains = <&domain>; | ||
| 575 | }; | ||
| 576 | |||
| 577 | gr3d { | ||
| 578 | compatible = "nvidia,tegra20-gr3d"; | ||
| 579 | reg = <0x54180000 0x00040000>; | ||
| 580 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; | ||
| 581 | resets = <&tegra_car 24>; | ||
| 582 | reset-names = "3d"; | ||
| 583 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 584 | power-domains = <&domain>; | ||
| 585 | }; | ||
| 586 | |||
| 587 | dc@54200000 { | ||
| 588 | compatible = "nvidia,tegra20-dc"; | ||
| 589 | reg = <0x54200000 0x00040000>; | ||
| 590 | interrupts = <0 73 0x04>; | ||
| 591 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, | ||
| 592 | <&tegra_car TEGRA20_CLK_PLL_P>; | ||
| 593 | clock-names = "dc", "parent"; | ||
| 594 | resets = <&tegra_car 27>; | ||
| 595 | reset-names = "dc"; | ||
| 596 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 597 | power-domains = <&domain>; | ||
| 598 | |||
| 599 | interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, | ||
| 600 | <&mc TEGRA20_MC_DISPLAY0B &emc>, | ||
| 601 | <&mc TEGRA20_MC_DISPLAY0C &emc>, | ||
| 602 | <&mc TEGRA20_MC_DISPLAYHC &emc>; | ||
| 603 | interconnect-names = "wina", | ||
| 604 | "winb", | ||
| 605 | "winc", | ||
| 606 | "cursor"; | ||
| 607 | |||
| 608 | rgb { | ||
| 609 | status = "disabled"; | ||
| 610 | }; | ||
| 611 | }; | ||
| 612 | |||
| 613 | dc@54240000 { | ||
| 614 | compatible = "nvidia,tegra20-dc"; | ||
| 615 | reg = <0x54240000 0x00040000>; | ||
| 616 | interrupts = <0 74 0x04>; | ||
| 617 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, | ||
| 618 | <&tegra_car TEGRA20_CLK_PLL_P>; | ||
| 619 | clock-names = "dc", "parent"; | ||
| 620 | resets = <&tegra_car 26>; | ||
| 621 | reset-names = "dc"; | ||
| 622 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 623 | power-domains = <&domain>; | ||
| 624 | |||
| 625 | interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, | ||
| 626 | <&mc TEGRA20_MC_DISPLAY0BB &emc>, | ||
| 627 | <&mc TEGRA20_MC_DISPLAY0CB &emc>, | ||
| 628 | <&mc TEGRA20_MC_DISPLAYHCB &emc>; | ||
| 629 | interconnect-names = "wina", | ||
| 630 | "winb", | ||
| 631 | "winc", | ||
| 632 | "cursor"; | ||
| 633 | |||
| 634 | rgb { | ||
| 635 | status = "disabled"; | ||
| 636 | }; | ||
| 637 | }; | ||
| 638 | |||
| 639 | hdmi { | ||
| 640 | compatible = "nvidia,tegra20-hdmi"; | ||
| 641 | reg = <0x54280000 0x00040000>; | ||
| 642 | interrupts = <0 75 0x04>; | ||
| 643 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, | ||
| 644 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | ||
| 645 | clock-names = "hdmi", "parent"; | ||
| 646 | resets = <&tegra_car 51>; | ||
| 647 | reset-names = "hdmi"; | ||
| 648 | status = "disabled"; | ||
| 649 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 650 | }; | ||
| 651 | |||
| 652 | tvo { | ||
| 653 | compatible = "nvidia,tegra20-tvo"; | ||
| 654 | reg = <0x542c0000 0x00040000>; | ||
| 655 | interrupts = <0 76 0x04>; | ||
| 656 | clocks = <&tegra_car TEGRA20_CLK_TVO>; | ||
| 657 | status = "disabled"; | ||
| 658 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 659 | }; | ||
| 660 | |||
| 661 | dsi { | ||
| 662 | compatible = "nvidia,tegra20-dsi"; | ||
| 663 | reg = <0x54300000 0x00040000>; | ||
| 664 | clocks = <&tegra_car TEGRA20_CLK_DSI>, | ||
| 665 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | ||
| 666 | clock-names = "dsi", "parent"; | ||
| 667 | resets = <&tegra_car 48>; | ||
| 668 | reset-names = "dsi"; | ||
| 669 | status = "disabled"; | ||
| 670 | operating-points-v2 = <&dvfs_opp_table>; | ||
| 671 | }; | ||
| 672 | }; | ||
| 673 | |||
| 674 | ... | ||
| 675 | }; | ||
| @@ -0,0 +1,431 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra host1x controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | description: The host1x top-level node defines a number of children, each | ||
| 14 | representing one of the host1x client modules defined in this binding. | ||
| 15 | |||
| 16 | properties: | ||
| 17 | compatible: | ||
| 18 | oneOf: | ||
| 19 | - enum: | ||
| 20 | - nvidia,tegra20-host1x | ||
| 21 | - nvidia,tegra30-host1x | ||
| 22 | - nvidia,tegra114-host1x | ||
| 23 | - nvidia,tegra124-host1x | ||
| 24 | - nvidia,tegra210-host1x | ||
| 25 | - nvidia,tegra186-host1x | ||
| 26 | - nvidia,tegra194-host1x | ||
| 27 | - nvidia,tegra234-host1x | ||
| 28 | |||
| 29 | - items: | ||
| 30 | - const: nvidia,tegra132-host1x | ||
| 31 | - const: nvidia,tegra124-host1x | ||
| 32 | |||
| 33 | reg: | ||
| 34 | minItems: 1 | ||
| 35 | maxItems: 3 | ||
| 36 | |||
| 37 | reg-names: | ||
| 38 | minItems: 1 | ||
| 39 | maxItems: 3 | ||
| 40 | |||
| 41 | interrupts: | ||
| 42 | minItems: 1 | ||
| 43 | maxItems: 9 | ||
| 44 | |||
| 45 | interrupt-names: | ||
| 46 | minItems: 1 | ||
| 47 | maxItems: 9 | ||
| 48 | |||
| 49 | '#address-cells': | ||
| 50 | description: The number of cells used to represent physical base addresses | ||
| 51 | in the host1x address space. | ||
| 52 | enum: [1, 2] | ||
| 53 | |||
| 54 | '#size-cells': | ||
| 55 | description: The number of cells used to represent the size of an address | ||
| 56 | range in the host1x address space. | ||
| 57 | enum: [1, 2] | ||
| 58 | |||
| 59 | ranges: | ||
| 60 | maxItems: 1 | ||
| 61 | |||
| 62 | clocks: | ||
| 63 | description: Must contain one entry, for the module clock. See | ||
| 64 | ../clocks/clock-bindings.txt for details. | ||
| 65 | |||
| 66 | clock-names: | ||
| 67 | items: | ||
| 68 | - const: host1x | ||
| 69 | |||
| 70 | resets: | ||
| 71 | minItems: 1 # MC reset is optional on Tegra186 and later | ||
| 72 | items: | ||
| 73 | - description: module reset | ||
| 74 | - description: memory client hotflush reset | ||
| 75 | |||
| 76 | reset-names: | ||
| 77 | minItems: 1 # MC reset is optional on Tegra186 and later | ||
| 78 | items: | ||
| 79 | - const: host1x | ||
| 80 | - const: mc | ||
| 81 | |||
| 82 | iommus: | ||
| 83 | maxItems: 1 | ||
| 84 | |||
| 85 | interconnects: | ||
| 86 | items: | ||
| 87 | - description: memory read client for host1x | ||
| 88 | |||
| 89 | interconnect-names: | ||
| 90 | items: | ||
| 91 | - const: dma-mem # read | ||
| 92 | |||
| 93 | operating-points-v2: | ||
| 94 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 95 | |||
| 96 | power-domains: | ||
| 97 | items: | ||
| 98 | - description: phandle to the HEG or core power domain | ||
| 99 | |||
| 100 | required: | ||
| 101 | - compatible | ||
| 102 | - interrupts | ||
| 103 | - interrupt-names | ||
| 104 | - '#address-cells' | ||
| 105 | - '#size-cells' | ||
| 106 | - ranges | ||
| 107 | - reg | ||
| 108 | - clocks | ||
| 109 | - clock-names | ||
| 110 | |||
| 111 | unevaluatedProperties: | ||
| 112 | type: object | ||
| 113 | |||
| 114 | allOf: | ||
| 115 | - if: | ||
| 116 | properties: | ||
| 117 | compatible: | ||
| 118 | contains: | ||
| 119 | enum: | ||
| 120 | - nvidia,tegra20-host1x | ||
| 121 | - nvidia,tegra30-host1x | ||
| 122 | - nvidia,tegra114-host1x | ||
| 123 | - nvidia,tegra124-host1x | ||
| 124 | - nvidia,tegra210-host1x | ||
| 125 | then: | ||
| 126 | properties: | ||
| 127 | interrupts: | ||
| 128 | items: | ||
| 129 | - description: host1x syncpoint interrupt | ||
| 130 | - description: host1x general interrupt | ||
| 131 | |||
| 132 | interrupt-names: | ||
| 133 | items: | ||
| 134 | - const: syncpt | ||
| 135 | - const: host1x | ||
| 136 | required: | ||
| 137 | - resets | ||
| 138 | - reset-names | ||
| 139 | - if: | ||
| 140 | properties: | ||
| 141 | compatible: | ||
| 142 | contains: | ||
| 143 | enum: | ||
| 144 | - nvidia,tegra186-host1x | ||
| 145 | - nvidia,tegra194-host1x | ||
| 146 | then: | ||
| 147 | properties: | ||
| 148 | reg-names: | ||
| 149 | items: | ||
| 150 | - const: hypervisor | ||
| 151 | - const: vm | ||
| 152 | |||
| 153 | reg: | ||
| 154 | items: | ||
| 155 | - description: region used by the hypervisor | ||
| 156 | - description: region assigned to the virtual machine | ||
| 157 | |||
| 158 | resets: | ||
| 159 | maxItems: 1 | ||
| 160 | |||
| 161 | reset-names: | ||
| 162 | maxItems: 1 | ||
| 163 | |||
| 164 | interrupts: | ||
| 165 | items: | ||
| 166 | - description: host1x syncpoint interrupt | ||
| 167 | - description: host1x general interrupt | ||
| 168 | |||
| 169 | interrupt-names: | ||
| 170 | items: | ||
| 171 | - const: syncpt | ||
| 172 | - const: host1x | ||
| 173 | |||
| 174 | iommu-map: | ||
| 175 | description: Specification of stream IDs available for memory context device | ||
| 176 | use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to | ||
| 177 | usable stream IDs. | ||
| 178 | |||
| 179 | required: | ||
| 180 | - reg-names | ||
| 181 | - if: | ||
| 182 | properties: | ||
| 183 | compatible: | ||
| 184 | contains: | ||
| 185 | enum: | ||
| 186 | - nvidia,tegra234-host1x | ||
| 187 | then: | ||
| 188 | properties: | ||
| 189 | reg-names: | ||
| 190 | items: | ||
| 191 | - const: common | ||
| 192 | - const: hypervisor | ||
| 193 | - const: vm | ||
| 194 | |||
| 195 | reg: | ||
| 196 | items: | ||
| 197 | - description: region used by host1x server | ||
| 198 | - description: region used by the hypervisor | ||
| 199 | - description: region assigned to the virtual machine | ||
| 200 | |||
| 201 | interrupts: | ||
| 202 | items: | ||
| 203 | - description: host1x syncpoint interrupt 0 | ||
| 204 | - description: host1x syncpoint interrupt 1 | ||
| 205 | - description: host1x syncpoint interrupt 2 | ||
| 206 | - description: host1x syncpoint interrupt 3 | ||
| 207 | - description: host1x syncpoint interrupt 4 | ||
| 208 | - description: host1x syncpoint interrupt 5 | ||
| 209 | - description: host1x syncpoint interrupt 6 | ||
| 210 | - description: host1x syncpoint interrupt 7 | ||
| 211 | - description: host1x general interrupt | ||
| 212 | |||
| 213 | interrupt-names: | ||
| 214 | items: | ||
| 215 | - const: syncpt0 | ||
| 216 | - const: syncpt1 | ||
| 217 | - const: syncpt2 | ||
| 218 | - const: syncpt3 | ||
| 219 | - const: syncpt4 | ||
| 220 | - const: syncpt5 | ||
| 221 | - const: syncpt6 | ||
| 222 | - const: syncpt7 | ||
| 223 | - const: host1x | ||
| 224 | |||
| 225 | iommu-map: | ||
| 226 | description: Specification of stream IDs available for memory context device | ||
| 227 | use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to | ||
| 228 | usable stream IDs. | ||
| 229 | |||
| 230 | required: | ||
| 231 | - reg-names | ||
| 232 | |||
| 233 | examples: | ||
| 234 | - | | ||
| 235 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 236 | #include <dt-bindings/gpio/tegra-gpio.h> | ||
| 237 | #include <dt-bindings/memory/tegra20-mc.h> | ||
| 238 | |||
| 239 | host1x@50000000 { | ||
| 240 | compatible = "nvidia,tegra20-host1x"; | ||
| 241 | reg = <0x50000000 0x00024000>; | ||
| 242 | interrupts = <0 65 0x04>, /* mpcore syncpt */ | ||
| 243 | <0 67 0x04>; /* mpcore general */ | ||
| 244 | interrupt-names = "syncpt", "host1x"; | ||
| 245 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; | ||
| 246 | clock-names = "host1x"; | ||
| 247 | resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; | ||
| 248 | reset-names = "host1x", "mc"; | ||
| 249 | |||
| 250 | #address-cells = <1>; | ||
| 251 | #size-cells = <1>; | ||
| 252 | |||
| 253 | ranges = <0x54000000 0x54000000 0x04000000>; | ||
| 254 | |||
| 255 | mpe@54040000 { | ||
| 256 | compatible = "nvidia,tegra20-mpe"; | ||
| 257 | reg = <0x54040000 0x00040000>; | ||
| 258 | interrupts = <0 68 0x04>; | ||
| 259 | clocks = <&tegra_car TEGRA20_CLK_MPE>; | ||
| 260 | resets = <&tegra_car 60>; | ||
| 261 | reset-names = "mpe"; | ||
| 262 | }; | ||
| 263 | |||
| 264 | vi@54080000 { | ||
| 265 | compatible = "nvidia,tegra20-vi"; | ||
| 266 | reg = <0x54080000 0x00040000>; | ||
| 267 | interrupts = <0 69 0x04>; | ||
| 268 | clocks = <&tegra_car TEGRA20_CLK_VI>; | ||
| 269 | resets = <&tegra_car 100>; | ||
| 270 | reset-names = "vi"; | ||
| 271 | }; | ||
| 272 | |||
| 273 | epp@540c0000 { | ||
| 274 | compatible = "nvidia,tegra20-epp"; | ||
| 275 | reg = <0x540c0000 0x00040000>; | ||
| 276 | interrupts = <0 70 0x04>; | ||
| 277 | clocks = <&tegra_car TEGRA20_CLK_EPP>; | ||
| 278 | resets = <&tegra_car 19>; | ||
| 279 | reset-names = "epp"; | ||
| 280 | }; | ||
| 281 | |||
| 282 | isp@54100000 { | ||
| 283 | compatible = "nvidia,tegra20-isp"; | ||
| 284 | reg = <0x54100000 0x00040000>; | ||
| 285 | interrupts = <0 71 0x04>; | ||
| 286 | clocks = <&tegra_car TEGRA20_CLK_ISP>; | ||
| 287 | resets = <&tegra_car 23>; | ||
| 288 | reset-names = "isp"; | ||
| 289 | }; | ||
| 290 | |||
| 291 | gr2d@54140000 { | ||
| 292 | compatible = "nvidia,tegra20-gr2d"; | ||
| 293 | reg = <0x54140000 0x00040000>; | ||
| 294 | interrupts = <0 72 0x04>; | ||
| 295 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; | ||
| 296 | resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; | ||
| 297 | reset-names = "2d", "mc"; | ||
| 298 | }; | ||
| 299 | |||
| 300 | gr3d@54180000 { | ||
| 301 | compatible = "nvidia,tegra20-gr3d"; | ||
| 302 | reg = <0x54180000 0x00040000>; | ||
| 303 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; | ||
| 304 | resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; | ||
| 305 | reset-names = "3d", "mc"; | ||
| 306 | }; | ||
| 307 | |||
| 308 | dc@54200000 { | ||
| 309 | compatible = "nvidia,tegra20-dc"; | ||
| 310 | reg = <0x54200000 0x00040000>; | ||
| 311 | interrupts = <0 73 0x04>; | ||
| 312 | clocks = <&tegra_car TEGRA20_CLK_DISP1>; | ||
| 313 | clock-names = "dc"; | ||
| 314 | resets = <&tegra_car 27>; | ||
| 315 | reset-names = "dc"; | ||
| 316 | |||
| 317 | rgb { | ||
| 318 | }; | ||
| 319 | }; | ||
| 320 | |||
| 321 | dc@54240000 { | ||
| 322 | compatible = "nvidia,tegra20-dc"; | ||
| 323 | reg = <0x54240000 0x00040000>; | ||
| 324 | interrupts = <0 74 0x04>; | ||
| 325 | clocks = <&tegra_car TEGRA20_CLK_DISP2>; | ||
| 326 | clock-names = "dc"; | ||
| 327 | resets = <&tegra_car 26>; | ||
| 328 | reset-names = "dc"; | ||
| 329 | |||
| 330 | rgb { | ||
| 331 | }; | ||
| 332 | }; | ||
| 333 | |||
| 334 | hdmi@54280000 { | ||
| 335 | compatible = "nvidia,tegra20-hdmi"; | ||
| 336 | reg = <0x54280000 0x00040000>; | ||
| 337 | interrupts = <0 75 0x04>; | ||
| 338 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, | ||
| 339 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | ||
| 340 | clock-names = "hdmi", "parent"; | ||
| 341 | resets = <&tegra_car 51>; | ||
| 342 | reset-names = "hdmi"; | ||
| 343 | |||
| 344 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
| 345 | pll-supply = <&vdd_hdmi_pll>; | ||
| 346 | vdd-supply = <&vdd_3v3_hdmi>; | ||
| 347 | |||
| 348 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
| 349 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | ||
| 350 | }; | ||
| 351 | |||
| 352 | tvo@542c0000 { | ||
| 353 | compatible = "nvidia,tegra20-tvo"; | ||
| 354 | reg = <0x542c0000 0x00040000>; | ||
| 355 | interrupts = <0 76 0x04>; | ||
| 356 | clocks = <&tegra_car TEGRA20_CLK_TVO>; | ||
| 357 | }; | ||
| 358 | |||
| 359 | dsi@54300000 { | ||
| 360 | compatible = "nvidia,tegra20-dsi"; | ||
| 361 | reg = <0x54300000 0x00040000>; | ||
| 362 | clocks = <&tegra_car TEGRA20_CLK_DSI>, | ||
| 363 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | ||
| 364 | clock-names = "dsi", "parent"; | ||
| 365 | resets = <&tegra_car 48>; | ||
| 366 | reset-names = "dsi"; | ||
| 367 | }; | ||
| 368 | }; | ||
| 369 | |||
| 370 | - | | ||
| 371 | #include <dt-bindings/clock/tegra210-car.h> | ||
| 372 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 373 | #include <dt-bindings/memory/tegra210-mc.h> | ||
| 374 | |||
| 375 | host1x@50000000 { | ||
| 376 | compatible = "nvidia,tegra210-host1x"; | ||
| 377 | reg = <0x50000000 0x00024000>; | ||
| 378 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */ | ||
| 379 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */ | ||
| 380 | interrupt-names = "syncpt", "host1x"; | ||
| 381 | clocks = <&tegra_car TEGRA210_CLK_HOST1X>; | ||
| 382 | clock-names = "host1x"; | ||
| 383 | resets = <&tegra_car 28>; | ||
| 384 | reset-names = "host1x"; | ||
| 385 | |||
| 386 | #address-cells = <1>; | ||
| 387 | #size-cells = <1>; | ||
| 388 | |||
| 389 | ranges = <0x54000000 0x54000000 0x01000000>; | ||
| 390 | iommus = <&mc TEGRA_SWGROUP_HC>; | ||
| 391 | |||
| 392 | vi@54080000 { | ||
| 393 | compatible = "nvidia,tegra210-vi"; | ||
| 394 | reg = <0x54080000 0x00000700>; | ||
| 395 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | ||
| 396 | assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; | ||
| 397 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; | ||
| 398 | |||
| 399 | clocks = <&tegra_car TEGRA210_CLK_VI>; | ||
| 400 | power-domains = <&pd_venc>; | ||
| 401 | |||
| 402 | #address-cells = <1>; | ||
| 403 | #size-cells = <1>; | ||
| 404 | |||
| 405 | ranges = <0x0 0x54080000 0x2000>; | ||
| 406 | |||
| 407 | csi@838 { | ||
| 408 | compatible = "nvidia,tegra210-csi"; | ||
| 409 | reg = <0x838 0x1300>; | ||
| 410 | assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, | ||
| 411 | <&tegra_car TEGRA210_CLK_CILCD>, | ||
| 412 | <&tegra_car TEGRA210_CLK_CILE>, | ||
| 413 | <&tegra_car TEGRA210_CLK_CSI_TPG>; | ||
| 414 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, | ||
| 415 | <&tegra_car TEGRA210_CLK_PLL_P>, | ||
| 416 | <&tegra_car TEGRA210_CLK_PLL_P>; | ||
| 417 | assigned-clock-rates = <102000000>, | ||
| 418 | <102000000>, | ||
| 419 | <102000000>, | ||
| 420 | <972000000>; | ||
| 421 | |||
| 422 | clocks = <&tegra_car TEGRA210_CLK_CSI>, | ||
| 423 | <&tegra_car TEGRA210_CLK_CILAB>, | ||
| 424 | <&tegra_car TEGRA210_CLK_CILCD>, | ||
| 425 | <&tegra_car TEGRA210_CLK_CILE>, | ||
| 426 | <&tegra_car TEGRA210_CLK_CSI_TPG>; | ||
| 427 | clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; | ||
| 428 | power-domains = <&pd_sor>; | ||
| 429 | }; | ||
| 430 | }; | ||
| 431 | }; | ||
| @@ -0,0 +1,67 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra ISP processor | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | compatible: | ||
| 15 | enum: | ||
| 16 | - nvidia,tegra20-isp | ||
| 17 | - nvidia,tegra30-isp | ||
| 18 | - nvidia,tegra210-isp | ||
| 19 | |||
| 20 | reg: | ||
| 21 | maxItems: 1 | ||
| 22 | |||
| 23 | interrupts: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | clocks: | ||
| 27 | items: | ||
| 28 | - description: module clock | ||
| 29 | |||
| 30 | resets: | ||
| 31 | items: | ||
| 32 | - description: module reset | ||
| 33 | |||
| 34 | reset-names: | ||
| 35 | items: | ||
| 36 | - const: isp | ||
| 37 | |||
| 38 | iommus: | ||
| 39 | maxItems: 1 | ||
| 40 | |||
| 41 | interconnects: | ||
| 42 | items: | ||
| 43 | - description: memory write client | ||
| 44 | |||
| 45 | interconnect-names: | ||
| 46 | items: | ||
| 47 | - const: dma-mem # write | ||
| 48 | |||
| 49 | power-domains: | ||
| 50 | items: | ||
| 51 | - description: phandle to the VENC or core power domain | ||
| 52 | |||
| 53 | additionalProperties: false | ||
| 54 | |||
| 55 | examples: | ||
| 56 | - | | ||
| 57 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 58 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 59 | |||
| 60 | isp@54100000 { | ||
| 61 | compatible = "nvidia,tegra20-isp"; | ||
| 62 | reg = <0x54100000 0x00040000>; | ||
| 63 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | ||
| 64 | clocks = <&tegra_car TEGRA20_CLK_ISP>; | ||
| 65 | resets = <&tegra_car 23>; | ||
| 66 | reset-names = "isp"; | ||
| 67 | }; | ||
| @@ -0,0 +1,73 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra Video Encoder | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^mpe@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra20-mpe | ||
| 20 | - nvidia,tegra30-mpe | ||
| 21 | - nvidia,tegra114-mpe | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | interrupts: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | clocks: | ||
| 30 | items: | ||
| 31 | - description: module clock | ||
| 32 | |||
| 33 | resets: | ||
| 34 | items: | ||
| 35 | - description: module reset | ||
| 36 | |||
| 37 | reset-names: | ||
| 38 | items: | ||
| 39 | - const: mpe | ||
| 40 | |||
| 41 | iommus: | ||
| 42 | maxItems: 1 | ||
| 43 | |||
| 44 | interconnects: | ||
| 45 | minItems: 6 | ||
| 46 | maxItems: 6 | ||
| 47 | |||
| 48 | interconnect-names: | ||
| 49 | minItems: 6 | ||
| 50 | maxItems: 6 | ||
| 51 | |||
| 52 | operating-points-v2: | ||
| 53 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 54 | |||
| 55 | power-domains: | ||
| 56 | items: | ||
| 57 | - description: phandle to the MPE power domain | ||
| 58 | |||
| 59 | additionalProperties: false | ||
| 60 | |||
| 61 | examples: | ||
| 62 | - | | ||
| 63 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 64 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 65 | |||
| 66 | mpe@54040000 { | ||
| 67 | compatible = "nvidia,tegra20-mpe"; | ||
| 68 | reg = <0x54040000 0x00040000>; | ||
| 69 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | ||
| 70 | clocks = <&tegra_car TEGRA20_CLK_MPE>; | ||
| 71 | resets = <&tegra_car 60>; | ||
| 72 | reset-names = "mpe"; | ||
| 73 | }; | ||
| @@ -0,0 +1,58 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra TV Encoder Output | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^tvo@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra20-tvo | ||
| 20 | - nvidia,tegra30-tvo | ||
| 21 | - nvidia,tegra114-tvo | ||
| 22 | |||
| 23 | reg: | ||
| 24 | maxItems: 1 | ||
| 25 | |||
| 26 | interrupts: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | clocks: | ||
| 30 | items: | ||
| 31 | - description: module clock | ||
| 32 | |||
| 33 | operating-points-v2: | ||
| 34 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 35 | |||
| 36 | power-domains: | ||
| 37 | items: | ||
| 38 | - description: phandle to the core power domain | ||
| 39 | |||
| 40 | additionalProperties: false | ||
| 41 | |||
| 42 | required: | ||
| 43 | - compatible | ||
| 44 | - reg | ||
| 45 | - interrupts | ||
| 46 | - clocks | ||
| 47 | |||
| 48 | examples: | ||
| 49 | - | | ||
| 50 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 51 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 52 | |||
| 53 | tvo@542c0000 { | ||
| 54 | compatible = "nvidia,tegra20-tvo"; | ||
| 55 | reg = <0x542c0000 0x00040000>; | ||
| 56 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | ||
| 57 | clocks = <&tegra_car TEGRA20_CLK_TVO>; | ||
| 58 | }; | ||
| @@ -0,0 +1,163 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra Video Input controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^vi@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | oneOf: | ||
| 19 | - const: nvidia,tegra20-vi | ||
| 20 | - const: nvidia,tegra30-vi | ||
| 21 | - const: nvidia,tegra114-vi | ||
| 22 | - const: nvidia,tegra124-vi | ||
| 23 | - items: | ||
| 24 | - const: nvidia,tegra132-vi | ||
| 25 | - const: nvidia,tegra124-vi | ||
| 26 | - const: nvidia,tegra210-vi | ||
| 27 | - const: nvidia,tegra186-vi | ||
| 28 | - const: nvidia,tegra194-vi | ||
| 29 | |||
| 30 | reg: | ||
| 31 | maxItems: 1 | ||
| 32 | |||
| 33 | interrupts: | ||
| 34 | maxItems: 1 | ||
| 35 | |||
| 36 | clocks: | ||
| 37 | maxItems: 1 | ||
| 38 | |||
| 39 | resets: | ||
| 40 | items: | ||
| 41 | - description: module reset | ||
| 42 | |||
| 43 | reset-names: | ||
| 44 | items: | ||
| 45 | - const: vi | ||
| 46 | |||
| 47 | iommus: | ||
| 48 | maxItems: 1 | ||
| 49 | |||
| 50 | interconnects: | ||
| 51 | minItems: 4 | ||
| 52 | maxItems: 5 | ||
| 53 | |||
| 54 | interconnect-names: | ||
| 55 | minItems: 4 | ||
| 56 | maxItems: 5 | ||
| 57 | |||
| 58 | operating-points-v2: | ||
| 59 | $ref: "/schemas/types.yaml#/definitions/phandle" | ||
| 60 | |||
| 61 | power-domains: | ||
| 62 | items: | ||
| 63 | - description: phandle to the VENC power domain | ||
| 64 | |||
| 65 | "#address-cells": | ||
| 66 | const: 1 | ||
| 67 | |||
| 68 | "#size-cells": | ||
| 69 | const: 1 | ||
| 70 | |||
| 71 | ranges: | ||
| 72 | maxItems: 1 | ||
| 73 | |||
| 74 | avdd-dsi-csi-supply: | ||
| 75 | description: DSI/CSI power supply. Must supply 1.2 V. | ||
| 76 | |||
| 77 | patternProperties: | ||
| 78 | "^csi@[0-9a-f]+$": | ||
| 79 | type: object | ||
| 80 | |||
| 81 | additionalProperties: false | ||
| 82 | |||
| 83 | required: | ||
| 84 | - compatible | ||
| 85 | - reg | ||
| 86 | - interrupts | ||
| 87 | - clocks | ||
| 88 | |||
| 89 | allOf: | ||
| 90 | - if: | ||
| 91 | properties: | ||
| 92 | compatible: | ||
| 93 | contains: | ||
| 94 | enum: | ||
| 95 | - nvidia,tegra20-vi | ||
| 96 | - nvidia,tegra30-vi | ||
| 97 | - nvidia,tegra114-vi | ||
| 98 | - nvidia,tegra124-vi | ||
| 99 | then: | ||
| 100 | required: | ||
| 101 | - resets | ||
| 102 | - reset-names | ||
| 103 | else: | ||
| 104 | required: | ||
| 105 | - power-domains | ||
| 106 | |||
| 107 | examples: | ||
| 108 | - | | ||
| 109 | #include <dt-bindings/clock/tegra20-car.h> | ||
| 110 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 111 | |||
| 112 | vi@54080000 { | ||
| 113 | compatible = "nvidia,tegra20-vi"; | ||
| 114 | reg = <0x54080000 0x00040000>; | ||
| 115 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | ||
| 116 | clocks = <&tegra_car TEGRA20_CLK_VI>; | ||
| 117 | resets = <&tegra_car 100>; | ||
| 118 | reset-names = "vi"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | - | | ||
| 122 | #include <dt-bindings/clock/tegra210-car.h> | ||
| 123 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 124 | |||
| 125 | vi@54080000 { | ||
| 126 | compatible = "nvidia,tegra210-vi"; | ||
| 127 | reg = <0x54080000 0x00000700>; | ||
| 128 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | ||
| 129 | assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; | ||
| 130 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; | ||
| 131 | |||
| 132 | clocks = <&tegra_car TEGRA210_CLK_VI>; | ||
| 133 | power-domains = <&pd_venc>; | ||
| 134 | |||
| 135 | #address-cells = <1>; | ||
| 136 | #size-cells = <1>; | ||
| 137 | |||
| 138 | ranges = <0x0 0x54080000 0x2000>; | ||
| 139 | |||
| 140 | csi@838 { | ||
| 141 | compatible = "nvidia,tegra210-csi"; | ||
| 142 | reg = <0x838 0x1300>; | ||
| 143 | assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, | ||
| 144 | <&tegra_car TEGRA210_CLK_CILCD>, | ||
| 145 | <&tegra_car TEGRA210_CLK_CILE>, | ||
| 146 | <&tegra_car TEGRA210_CLK_CSI_TPG>; | ||
| 147 | assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, | ||
| 148 | <&tegra_car TEGRA210_CLK_PLL_P>, | ||
| 149 | <&tegra_car TEGRA210_CLK_PLL_P>; | ||
| 150 | assigned-clock-rates = <102000000>, | ||
| 151 | <102000000>, | ||
| 152 | <102000000>, | ||
| 153 | <972000000>; | ||
| 154 | |||
| 155 | clocks = <&tegra_car TEGRA210_CLK_CSI>, | ||
| 156 | <&tegra_car TEGRA210_CLK_CILAB>, | ||
| 157 | <&tegra_car TEGRA210_CLK_CILCD>, | ||
| 158 | <&tegra_car TEGRA210_CLK_CILE>, | ||
| 159 | <&tegra_car TEGRA210_CLK_CSI_TPG>; | ||
| 160 | clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; | ||
| 161 | power-domains = <&pd_sor>; | ||
| 162 | }; | ||
| 163 | }; | ||
| @@ -0,0 +1,52 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVIDIA Tegra CSI controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thierry Reding <thierry.reding@gmail.com> | ||
| 11 | - Jon Hunter <jonathanh@nvidia.com> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | $nodename: | ||
| 15 | pattern: "^csi@[0-9a-f]+$" | ||
| 16 | |||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - nvidia,tegra210-csi | ||
| 20 | |||
| 21 | reg: | ||
| 22 | maxItems: 1 | ||
| 23 | |||
| 24 | clocks: | ||
| 25 | items: | ||
| 26 | - description: module clock | ||
| 27 | - description: A/B lanes clock | ||
| 28 | - description: C/D lanes clock | ||
| 29 | - description: E lane clock | ||
| 30 | - description: test pattern generator clock | ||
| 31 | |||
| 32 | clock-names: | ||
| 33 | items: | ||
| 34 | - const: csi | ||
| 35 | - const: cilab | ||
| 36 | - const: cilcd | ||
| 37 | - const: cile | ||
| 38 | - const: csi_tpg | ||
| 39 | |||
| 40 | power-domains: | ||
| 41 | maxItems: 1 | ||
| 42 | |||
| 43 | additionalProperties: false | ||
| 44 | |||
| 45 | required: | ||
| 46 | - compatible | ||
| 47 | - reg | ||
| 48 | - clocks | ||
| 49 | - clock-names | ||
| 50 | - power-domains | ||
| 51 | |||
| 52 | # see nvidia,tegra20-vi.yaml for an example | ||
| @@ -67,7 +67,7 @@ if: · 66 unmodified lines | |||
| 67 | then: | 67 | then: |
| 68 | properties: | 68 | properties: |
| 69 | clocks: | 69 | clocks: |
| 70 | maxItems: 2 | 70 | minItems: 2 |
| 71 | 71 | ||
| 72 | required: | 72 | required: |
| 73 | - clock-names | 73 | - clock-names |
| @@ -0,0 +1,80 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/dma/apple,admac.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Apple Audio DMA Controller (ADMAC) | ||
| 8 | |||
| 9 | description: | | ||
| 10 | Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples | ||
| 11 | on SoCs from the "Apple Silicon" family. | ||
| 12 | |||
| 13 | The controller has been seen with up to 24 channels. Even-numbered channels | ||
| 14 | are TX-only, odd-numbered are RX-only. Individual channels are coupled to | ||
| 15 | fixed device endpoints. | ||
| 16 | |||
| 17 | maintainers: | ||
| 18 | - Martin Povišer <povik+lin@cutebit.org> | ||
| 19 | |||
| 20 | allOf: | ||
| 21 | - $ref: "dma-controller.yaml#" | ||
| 22 | |||
| 23 | properties: | ||
| 24 | compatible: | ||
| 25 | items: | ||
| 26 | - enum: | ||
| 27 | - apple,t6000-admac | ||
| 28 | - apple,t8103-admac | ||
| 29 | - const: apple,admac | ||
| 30 | |||
| 31 | reg: | ||
| 32 | maxItems: 1 | ||
| 33 | |||
| 34 | '#dma-cells': | ||
| 35 | const: 1 | ||
| 36 | description: | ||
| 37 | Clients specify a single cell with channel number. | ||
| 38 | |||
| 39 | dma-channels: | ||
| 40 | maximum: 24 | ||
| 41 | |||
| 42 | interrupts: | ||
| 43 | minItems: 4 | ||
| 44 | maxItems: 4 | ||
| 45 | description: | ||
| 46 | Interrupts that correspond to the 4 IRQ outputs of the controller. Usually | ||
| 47 | only one of the controller outputs will be connected as an usable interrupt | ||
| 48 | source. The remaining interrupts will be left without a valid value, e.g. | ||
| 49 | in an interrupts-extended list the disconnected positions will contain | ||
| 50 | an empty phandle reference <0>. | ||
| 51 | |||
| 52 | required: | ||
| 53 | - compatible | ||
| 54 | - reg | ||
| 55 | - '#dma-cells' | ||
| 56 | - dma-channels | ||
| 57 | - interrupts | ||
| 58 | |||
| 59 | additionalProperties: false | ||
| 60 | |||
| 61 | examples: | ||
| 62 | - | | ||
| 63 | #include <dt-bindings/interrupt-controller/apple-aic.h> | ||
| 64 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 65 | |||
| 66 | aic: interrupt-controller { | ||
| 67 | interrupt-controller; | ||
| 68 | #interrupt-cells = <3>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | admac: dma-controller@238200000 { | ||
| 72 | compatible = "apple,t8103-admac", "apple,admac"; | ||
| 73 | reg = <0x38200000 0x34000>; | ||
| 74 | dma-channels = <24>; | ||
| 75 | interrupts-extended = <0>, | ||
| 76 | <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, | ||
| 77 | <0>, | ||
| 78 | <0>; | ||
| 79 | #dma-cells = <1>; | ||
| 80 | }; | ||
| @@ -0,0 +1,155 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/dma/fsl,edma.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Freescale enhanced Direct Memory Access(eDMA) Controller | ||
| 8 | |||
| 9 | description: | | ||
| 10 | The eDMA channels have multiplex capability by programmable | ||
| 11 | memory-mapped registers. channels are split into two groups, called | ||
| 12 | DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed | ||
| 13 | by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. | ||
| 14 | |||
| 15 | maintainers: | ||
| 16 | - Peng Fan <peng.fan@nxp.com> | ||
| 17 | |||
| 18 | properties: | ||
| 19 | compatible: | ||
| 20 | oneOf: | ||
| 21 | - enum: | ||
| 22 | - fsl,vf610-edma | ||
| 23 | - fsl,imx7ulp-edma | ||
| 24 | - items: | ||
| 25 | - const: fsl,ls1028a-edma | ||
| 26 | - const: fsl,vf610-edma | ||
| 27 | |||
| 28 | reg: | ||
| 29 | minItems: 2 | ||
| 30 | maxItems: 3 | ||
| 31 | |||
| 32 | interrupts: | ||
| 33 | minItems: 2 | ||
| 34 | maxItems: 17 | ||
| 35 | |||
| 36 | interrupt-names: | ||
| 37 | minItems: 2 | ||
| 38 | maxItems: 17 | ||
| 39 | |||
| 40 | "#dma-cells": | ||
| 41 | const: 2 | ||
| 42 | |||
| 43 | dma-channels: | ||
| 44 | const: 32 | ||
| 45 | |||
| 46 | clocks: | ||
| 47 | maxItems: 2 | ||
| 48 | |||
| 49 | clock-names: | ||
| 50 | maxItems: 2 | ||
| 51 | |||
| 52 | big-endian: | ||
| 53 | description: | | ||
| 54 | If present registers and hardware scatter/gather descriptors of the | ||
| 55 | eDMA are implemented in big endian mode, otherwise in little mode. | ||
| 56 | type: boolean | ||
| 57 | |||
| 58 | required: | ||
| 59 | - "#dma-cells" | ||
| 60 | - compatible | ||
| 61 | - reg | ||
| 62 | - interrupts | ||
| 63 | - clocks | ||
| 64 | - dma-channels | ||
| 65 | |||
| 66 | allOf: | ||
| 67 | - $ref: "dma-controller.yaml#" | ||
| 68 | - if: | ||
| 69 | properties: | ||
| 70 | compatible: | ||
| 71 | contains: | ||
| 72 | const: fsl,vf610-edma | ||
| 73 | then: | ||
| 74 | properties: | ||
| 75 | clock-names: | ||
| 76 | items: | ||
| 77 | - const: dmamux0 | ||
| 78 | - const: dmamux1 | ||
| 79 | interrupts: | ||
| 80 | maxItems: 2 | ||
| 81 | interrupt-names: | ||
| 82 | items: | ||
| 83 | - const: edma-tx | ||
| 84 | - const: edma-err | ||
| 85 | reg: | ||
| 86 | maxItems: 3 | ||
| 87 | |||
| 88 | - if: | ||
| 89 | properties: | ||
| 90 | compatible: | ||
| 91 | contains: | ||
| 92 | const: fsl,imx7ulp-edma | ||
| 93 | then: | ||
| 94 | properties: | ||
| 95 | clock-names: | ||
| 96 | items: | ||
| 97 | - const: dma | ||
| 98 | - const: dmamux0 | ||
| 99 | interrupts: | ||
| 100 | maxItems: 17 | ||
| 101 | reg: | ||
| 102 | maxItems: 2 | ||
| 103 | |||
| 104 | unevaluatedProperties: false | ||
| 105 | |||
| 106 | examples: | ||
| 107 | - | | ||
| 108 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 109 | #include <dt-bindings/clock/vf610-clock.h> | ||
| 110 | |||
| 111 | edma0: dma-controller@40018000 { | ||
| 112 | #dma-cells = <2>; | ||
| 113 | compatible = "fsl,vf610-edma"; | ||
| 114 | reg = <0x40018000 0x2000>, | ||
| 115 | <0x40024000 0x1000>, | ||
| 116 | <0x40025000 0x1000>; | ||
| 117 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 118 | <0 9 IRQ_TYPE_LEVEL_HIGH>; | ||
| 119 | interrupt-names = "edma-tx", "edma-err"; | ||
| 120 | dma-channels = <32>; | ||
| 121 | clock-names = "dmamux0", "dmamux1"; | ||
| 122 | clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; | ||
| 123 | }; | ||
| 124 | |||
| 125 | - | | ||
| 126 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 127 | #include <dt-bindings/clock/imx7ulp-clock.h> | ||
| 128 | |||
| 129 | edma1: dma-controller@40080000 { | ||
| 130 | #dma-cells = <2>; | ||
| 131 | compatible = "fsl,imx7ulp-edma"; | ||
| 132 | reg = <0x40080000 0x2000>, | ||
| 133 | <0x40210000 0x1000>; | ||
| 134 | dma-channels = <32>; | ||
| 135 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | ||
| 136 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | ||
| 137 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | ||
| 138 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | ||
| 139 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | ||
| 140 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | ||
| 141 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 142 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | ||
| 143 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 144 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
| 145 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
| 146 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
| 147 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | ||
| 148 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | ||
| 149 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | ||
| 150 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | ||
| 151 | /* last is eDMA2-ERR interrupt */ | ||
| 152 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | ||
| 153 | clock-names = "dma", "dmamux0"; | ||
| 154 | clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; | ||
| 155 | }; | ||
| @@ -1,111 +0,0 @@ | |||
| 1 | * Freescale enhanced Direct Memory Access(eDMA) Controller | ||
| 2 | |||
| 3 | The eDMA channels have multiplex capability by programmble memory-mapped | ||
| 4 | registers. channels are split into two groups, called DMAMUX0 and DMAMUX1, | ||
| 5 | specific DMA request source can only be multiplexed by any channel of certain | ||
| 6 | group, DMAMUX0 or DMAMUX1, but not both. | ||
| 7 | |||
| 8 | * eDMA Controller | ||
| 9 | Required properties: | ||
| 10 | - compatible : | ||
| 11 | - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC | ||
| 12 | - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp | ||
| 13 | - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the | ||
| 14 | LS1028A SoC. | ||
| 15 | - reg : Specifies base physical address(s) and size of the eDMA registers. | ||
| 16 | The 1st region is eDMA control register's address and size. | ||
| 17 | The 2nd and the 3rd regions are programmable channel multiplexing | ||
| 18 | control register's address and size. | ||
| 19 | - interrupts : A list of interrupt-specifiers, one for each entry in | ||
| 20 | interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel | ||
| 21 | per transmission interrupt, total 16 channel interrupt and 1 | ||
| 22 | error interrupt(located in the last), no interrupt-names list on | ||
| 23 | i.mx7ulp for clean on dts. | ||
| 24 | - #dma-cells : Must be <2>. | ||
| 25 | The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1). | ||
| 26 | Specific request source can only be multiplexed by specific channels | ||
| 27 | group called DMAMUX. | ||
| 28 | The 2nd cell specifies the request source(slot) ID. | ||
| 29 | See the SoC's reference manual for all the supported request sources. | ||
| 30 | - dma-channels : Number of channels supported by the controller | ||
| 31 | - clock-names : A list of channel group clock names. Should contain: | ||
| 32 | "dmamux0" - clock name of mux0 group | ||
| 33 | "dmamux1" - clock name of mux1 group | ||
| 34 | Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp. | ||
| 35 | - clocks : A list of phandle and clock-specifier pairs, one for each entry in | ||
| 36 | clock-names. | ||
| 37 | |||
| 38 | Optional properties: | ||
| 39 | - big-endian: If present registers and hardware scatter/gather descriptors | ||
| 40 | of the eDMA are implemented in big endian mode, otherwise in little | ||
| 41 | mode. | ||
| 42 | - interrupt-names : Should contain the below on vf610 similar SoC but not used | ||
| 43 | on i.mx7ulp similar SoC: | ||
| 44 | "edma-tx" - the transmission interrupt | ||
| 45 | "edma-err" - the error interrupt | ||
| 46 | |||
| 47 | |||
| 48 | Examples: | ||
| 49 | |||
| 50 | edma0: dma-controller@40018000 { | ||
| 51 | #dma-cells = <2>; | ||
| 52 | compatible = "fsl,vf610-edma"; | ||
| 53 | reg = <0x40018000 0x2000>, | ||
| 54 | <0x40024000 0x1000>, | ||
| 55 | <0x40025000 0x1000>; | ||
| 56 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 57 | <0 9 IRQ_TYPE_LEVEL_HIGH>; | ||
| 58 | interrupt-names = "edma-tx", "edma-err"; | ||
| 59 | dma-channels = <32>; | ||
| 60 | clock-names = "dmamux0", "dmamux1"; | ||
| 61 | clocks = <&clks VF610_CLK_DMAMUX0>, | ||
| 62 | <&clks VF610_CLK_DMAMUX1>; | ||
| 63 | }; /* vf610 */ | ||
| 64 | |||
| 65 | edma1: dma-controller@40080000 { | ||
| 66 | #dma-cells = <2>; | ||
| 67 | compatible = "fsl,imx7ulp-edma"; | ||
| 68 | reg = <0x40080000 0x2000>, | ||
| 69 | <0x40210000 0x1000>; | ||
| 70 | dma-channels = <32>; | ||
| 71 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | ||
| 72 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | ||
| 73 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | ||
| 74 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | ||
| 75 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | ||
| 76 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | ||
| 77 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | ||
| 78 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | ||
| 79 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | ||
| 80 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
| 81 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
| 82 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
| 83 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | ||
| 84 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | ||
| 85 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | ||
| 86 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | ||
| 87 | /* last is eDMA2-ERR interrupt */ | ||
| 88 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | ||
| 89 | clock-names = "dma", "dmamux0"; | ||
| 90 | clocks = <&pcc2 IMX7ULP_CLK_DMA1>, | ||
| 91 | <&pcc2 IMX7ULP_CLK_DMA_MUX1>; | ||
| 92 | }; /* i.mx7ulp */ | ||
| 93 | |||
| 94 | * DMA clients | ||
| 95 | DMA client drivers that uses the DMA function must use the format described | ||
| 96 | in the dma.txt file, using a two-cell specifier for each channel: the 1st | ||
| 97 | specifies the channel group(DMAMUX) in which this request can be multiplexed, | ||
| 98 | and the 2nd specifies the request source. | ||
| 99 | |||
| 100 | Examples: | ||
| 101 | |||
| 102 | sai2: sai@40031000 { | ||
| 103 | compatible = "fsl,vf610-sai"; | ||
| 104 | reg = <0x40031000 0x1000>; | ||
| 105 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | ||
| 106 | clock-names = "sai"; | ||
| 107 | clocks = <&clks VF610_CLK_SAI2>; | ||
| 108 | dma-names = "tx", "rx"; | ||
| 109 | dmas = <&edma0 0 21>, | ||
| 110 | <&edma0 0 20>; | ||
| 111 | }; | ||
| @@ -22,6 +22,7 @@ properties: · 21 unmodified lines | |||
| 22 | - items: | 22 | - items: |
| 23 | - enum: | 23 | - enum: |
| 24 | - mediatek,mt2712-uart-dma | 24 | - mediatek,mt2712-uart-dma |
| 25 | - mediatek,mt8365-uart-dma | ||
| 25 | - mediatek,mt8516-uart-dma | 26 | - mediatek,mt8516-uart-dma |
| 26 | - const: mediatek,mt6577-uart-dma | 27 | - const: mediatek,mt6577-uart-dma |
| 27 | - enum: | 28 | - enum: |
| @@ -23,7 +23,9 @@ properties: · 22 unmodified lines | |||
| 23 | oneOf: | 23 | oneOf: |
| 24 | - const: nvidia,tegra186-gpcdma | 24 | - const: nvidia,tegra186-gpcdma |
| 25 | - items: | 25 | - items: |
| 26 | - const: nvidia,tegra194-gpcdma | 26 | - enum: |
| 27 | - nvidia,tegra234-gpcdma | ||
| 28 | - nvidia,tegra194-gpcdma | ||
| 27 | - const: nvidia,tegra186-gpcdma | 29 | - const: nvidia,tegra186-gpcdma |
| 28 | 30 | ||
| 29 | "#dma-cells": | 31 | "#dma-cells": |
| @@ -0,0 +1,100 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/dma/qcom,bam-dma.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Qualcomm Technologies Inc BAM DMA controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Andy Gross <agross@kernel.org> | ||
| 11 | - Bjorn Andersson <bjorn.andersson@linaro.org> | ||
| 12 | |||
| 13 | allOf: | ||
| 14 | - $ref: "dma-controller.yaml#" | ||
| 15 | |||
| 16 | properties: | ||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | # APQ8064, IPQ8064 and MSM8960 | ||
| 20 | - qcom,bam-v1.3.0 | ||
| 21 | # MSM8974, APQ8074 and APQ8084 | ||
| 22 | - qcom,bam-v1.4.0 | ||
| 23 | # MSM8916 | ||
| 24 | - qcom,bam-v1.7.0 | ||
| 25 | |||
| 26 | clocks: | ||
| 27 | maxItems: 1 | ||
| 28 | |||
| 29 | clock-names: | ||
| 30 | items: | ||
| 31 | - const: bam_clk | ||
| 32 | |||
| 33 | "#dma-cells": | ||
| 34 | const: 1 | ||
| 35 | |||
| 36 | interrupts: | ||
| 37 | maxItems: 1 | ||
| 38 | |||
| 39 | iommus: | ||
| 40 | minItems: 1 | ||
| 41 | maxItems: 4 | ||
| 42 | |||
| 43 | num-channels: | ||
| 44 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 45 | description: | ||
| 46 | Indicates supported number of DMA channels in a remotely controlled bam. | ||
| 47 | |||
| 48 | qcom,controlled-remotely: | ||
| 49 | type: boolean | ||
| 50 | description: | ||
| 51 | Indicates that the bam is controlled by remote proccessor i.e. execution | ||
| 52 | environment. | ||
| 53 | |||
| 54 | qcom,ee: | ||
| 55 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 56 | minimum: 0 | ||
| 57 | maximum: 7 | ||
| 58 | description: | ||
| 59 | Indicates the active Execution Environment identifier (0-7) used in the | ||
| 60 | secure world. | ||
| 61 | |||
| 62 | qcom,num-ees: | ||
| 63 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 64 | description: | ||
| 65 | Indicates supported number of Execution Environments in a remotely | ||
| 66 | controlled bam. | ||
| 67 | |||
| 68 | qcom,powered-remotely: | ||
| 69 | type: boolean | ||
| 70 | description: | ||
| 71 | Indicates that the bam is powered up by a remote processor but must be | ||
| 72 | initialized by the local processor. | ||
| 73 | |||
| 74 | reg: | ||
| 75 | maxItems: 1 | ||
| 76 | |||
| 77 | required: | ||
| 78 | - compatible | ||
| 79 | - "#dma-cells" | ||
| 80 | - interrupts | ||
| 81 | - qcom,ee | ||
| 82 | - reg | ||
| 83 | |||
| 84 | additionalProperties: false | ||
| 85 | |||
| 86 | examples: | ||
| 87 | - | | ||
| 88 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 89 | #include <dt-bindings/clock/qcom,gcc-msm8974.h> | ||
| 90 | |||
| 91 | dma-controller@f9944000 { | ||
| 92 | compatible = "qcom,bam-v1.4.0"; | ||
| 93 | reg = <0xf9944000 0x15000>; | ||
| 94 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | ||
| 95 | clocks = <&gcc GCC_BLSP2_AHB_CLK>; | ||
| 96 | clock-names = "bam_clk"; | ||
| 97 | #dma-cells = <1>; | ||
| 98 | qcom,ee = <0>; | ||
| 99 | }; | ||
| 100 | ... | ||
| @@ -1,52 +0,0 @@ | |||
| 1 | QCOM BAM DMA controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: must be one of the following: | ||
| 5 | * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084 | ||
| 6 | * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960 | ||
| 7 | * "qcom,bam-v1.7.0" for MSM8916 | ||
| 8 | - reg: Address range for DMA registers | ||
| 9 | - interrupts: Should contain the one interrupt shared by all channels | ||
| 10 | - #dma-cells: must be <1>, the cell in the dmas property of the client device | ||
| 11 | represents the channel number | ||
| 12 | - clocks: required clock | ||
| 13 | - clock-names: must contain "bam_clk" entry | ||
| 14 | - qcom,ee : indicates the active Execution Environment identifier (0-7) used in | ||
| 15 | the secure world. | ||
| 16 | - qcom,controlled-remotely : optional, indicates that the bam is controlled by | ||
| 17 | remote proccessor i.e. execution environment. | ||
| 18 | - qcom,powered-remotely : optional, indicates that the bam is powered up by | ||
| 19 | a remote processor but must be initialized by the local processor. | ||
| 20 | - num-channels : optional, indicates supported number of DMA channels in a | ||
| 21 | remotely controlled bam. | ||
| 22 | - qcom,num-ees : optional, indicates supported number of Execution Environments | ||
| 23 | in a remotely controlled bam. | ||
| 24 | |||
| 25 | Example: | ||
| 26 | |||
| 27 | uart-bam: dma@f9984000 = { | ||
| 28 | compatible = "qcom,bam-v1.4.0"; | ||
| 29 | reg = <0xf9984000 0x15000>; | ||
| 30 | interrupts = <0 94 0>; | ||
| 31 | clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; | ||
| 32 | clock-names = "bam_clk"; | ||
| 33 | #dma-cells = <1>; | ||
| 34 | qcom,ee = <0>; | ||
| 35 | }; | ||
| 36 | |||
| 37 | DMA clients must use the format described in the dma.txt file, using a two cell | ||
| 38 | specifier for each channel. | ||
| 39 | |||
| 40 | Example: | ||
| 41 | serial@f991e000 { | ||
| 42 | compatible = "qcom,msm-uart"; | ||
| 43 | reg = <0xf991e000 0x1000> | ||
| 44 | <0xf9944000 0x19000>; | ||
| 45 | interrupts = <0 108 0>; | ||
| 46 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | ||
| 47 | <&gcc GCC_BLSP1_AHB_CLK>; | ||
| 48 | clock-names = "core", "iface"; | ||
| 49 | |||
| 50 | dmas = <&uart-bam 0>, <&uart-bam 1>; | ||
| 51 | dma-names = "rx", "tx"; | ||
| 52 | }; | ||
| @@ -34,7 +34,12 @@ properties: · 33 unmodified lines | |||
| 34 | - const: axidma_apb_regs | 34 | - const: axidma_apb_regs |
| 35 | 35 | ||
| 36 | interrupts: | 36 | interrupts: |
| 37 | maxItems: 1 | 37 | description: |
| 38 | If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this | ||
| 39 | will be per-channel interrupts. Otherwise, this is a single combined IRQ | ||
| 40 | for all channels. | ||
| 41 | minItems: 1 | ||
| 42 | maxItems: 8 | ||
| 38 | 43 | ||
| 39 | clocks: | 44 | clocks: |
| 40 | items: | 45 | items: |
| @@ -1,138 +0,0 @@ | |||
| 1 | * DMA40 DMA Controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: "stericsson,dma40" | ||
| 5 | - reg: Address range of the DMAC registers | ||
| 6 | - reg-names: Names of the above areas to use during resource look-up | ||
| 7 | - interrupt: Should contain the DMAC interrupt number | ||
| 8 | - #dma-cells: must be <3> | ||
| 9 | - memcpy-channels: Channels to be used for memcpy | ||
| 10 | |||
| 11 | Optional properties: | ||
| 12 | - dma-channels: Number of channels supported by hardware - if not present | ||
| 13 | the driver will attempt to obtain the information from H/W | ||
| 14 | - disabled-channels: Channels which can not be used | ||
| 15 | |||
| 16 | Example: | ||
| 17 | |||
| 18 | dma: dma-controller@801c0000 { | ||
| 19 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | ||
| 20 | reg = <0x801C0000 0x1000 0x40010000 0x800>; | ||
| 21 | reg-names = "base", "lcpa"; | ||
| 22 | interrupt-parent = <&intc>; | ||
| 23 | interrupts = <0 25 0x4>; | ||
| 24 | |||
| 25 | #dma-cells = <2>; | ||
| 26 | memcpy-channels = <56 57 58 59 60>; | ||
| 27 | disabled-channels = <12>; | ||
| 28 | dma-channels = <8>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | Clients | ||
| 32 | Required properties: | ||
| 33 | - dmas: Comma separated list of dma channel requests | ||
| 34 | - dma-names: Names of the aforementioned requested channels | ||
| 35 | |||
| 36 | Each dmas request consists of 4 cells: | ||
| 37 | 1. A phandle pointing to the DMA controller | ||
| 38 | 2. Device signal number, the signal line for single and burst requests | ||
| 39 | connected from the device to the DMA40 engine | ||
| 40 | 3. The DMA request line number (only when 'use fixed channel' is set) | ||
| 41 | 4. A 32bit mask specifying; mode, direction and endianness | ||
| 42 | [NB: This list will grow] | ||
| 43 | 0x00000001: Mode: | ||
| 44 | Logical channel when unset | ||
| 45 | Physical channel when set | ||
| 46 | 0x00000002: Direction: | ||
| 47 | Memory to Device when unset | ||
| 48 | Device to Memory when set | ||
| 49 | 0x00000004: Endianness: | ||
| 50 | Little endian when unset | ||
| 51 | Big endian when set | ||
| 52 | 0x00000008: Use fixed channel: | ||
| 53 | Use automatic channel selection when unset | ||
| 54 | Use DMA request line number when set | ||
| 55 | 0x00000010: Set channel as high priority: | ||
| 56 | Normal priority when unset | ||
| 57 | High priority when set | ||
| 58 | |||
| 59 | Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are | ||
| 60 | bidirectional, i.e. the same for RX and TX operations: | ||
| 61 | |||
| 62 | 0: SPI controller 0 | ||
| 63 | 1: SD/MMC controller 0 (unused) | ||
| 64 | 2: SD/MMC controller 1 (unused) | ||
| 65 | 3: SD/MMC controller 2 (unused) | ||
| 66 | 4: I2C port 1 | ||
| 67 | 5: I2C port 3 | ||
| 68 | 6: I2C port 2 | ||
| 69 | 7: I2C port 4 | ||
| 70 | 8: Synchronous Serial Port SSP0 | ||
| 71 | 9: Synchronous Serial Port SSP1 | ||
| 72 | 10: Multi-Channel Display Engine MCDE RX | ||
| 73 | 11: UART port 2 | ||
| 74 | 12: UART port 1 | ||
| 75 | 13: UART port 0 | ||
| 76 | 14: Multirate Serial Port MSP2 | ||
| 77 | 15: I2C port 0 | ||
| 78 | 16: USB OTG in/out endpoints 7 & 15 | ||
| 79 | 17: USB OTG in/out endpoints 6 & 14 | ||
| 80 | 18: USB OTG in/out endpoints 5 & 13 | ||
| 81 | 19: USB OTG in/out endpoints 4 & 12 | ||
| 82 | 20: SLIMbus or HSI channel 0 | ||
| 83 | 21: SLIMbus or HSI channel 1 | ||
| 84 | 22: SLIMbus or HSI channel 2 | ||
| 85 | 23: SLIMbus or HSI channel 3 | ||
| 86 | 24: Multimedia DSP SXA0 | ||
| 87 | 25: Multimedia DSP SXA1 | ||
| 88 | 26: Multimedia DSP SXA2 | ||
| 89 | 27: Multimedia DSP SXA3 | ||
| 90 | 28: SD/MM controller 2 | ||
| 91 | 29: SD/MM controller 0 | ||
| 92 | 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 | ||
| 93 | 31: MSP port 0 or SLIMbus channel 0 | ||
| 94 | 32: SD/MM controller 1 | ||
| 95 | 33: SPI controller 2 | ||
| 96 | 34: i2c3 RX2 TX2 | ||
| 97 | 35: SPI controller 1 | ||
| 98 | 36: USB OTG in/out endpoints 3 & 11 | ||
| 99 | 37: USB OTG in/out endpoints 2 & 10 | ||
| 100 | 38: USB OTG in/out endpoints 1 & 9 | ||
| 101 | 39: USB OTG in/out endpoints 8 | ||
| 102 | 40: SPI controller 3 | ||
| 103 | 41: SD/MM controller 3 | ||
| 104 | 42: SD/MM controller 4 | ||
| 105 | 43: SD/MM controller 5 | ||
| 106 | 44: Multimedia DSP SXA4 | ||
| 107 | 45: Multimedia DSP SXA5 | ||
| 108 | 46: SLIMbus channel 8 or Multimedia DSP SXA6 | ||
| 109 | 47: SLIMbus channel 9 or Multimedia DSP SXA7 | ||
| 110 | 48: Crypto Accelerator 1 | ||
| 111 | 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX | ||
| 112 | 50: Hash Accelerator 1 TX | ||
| 113 | 51: memcpy TX (to be used by the DMA driver for memcpy operations) | ||
| 114 | 52: SLIMbus or HSI channel 4 | ||
| 115 | 53: SLIMbus or HSI channel 5 | ||
| 116 | 54: SLIMbus or HSI channel 6 | ||
| 117 | 55: SLIMbus or HSI channel 7 | ||
| 118 | 56: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 119 | 57: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 120 | 58: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 121 | 59: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 122 | 60: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 123 | 61: Crypto Accelerator 0 | ||
| 124 | 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX | ||
| 125 | 63: Hash Accelerator 0 TX | ||
| 126 | |||
| 127 | Example: | ||
| 128 | |||
| 129 | uart@80120000 { | ||
| 130 | compatible = "arm,pl011", "arm,primecell"; | ||
| 131 | reg = <0x80120000 0x1000>; | ||
| 132 | interrupts = <0 11 0x4>; | ||
| 133 | |||
| 134 | dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ | ||
| 135 | <&dma 13 0 0x0>; /* Logical - MemToDev */ | ||
| 136 | dma-names = "rx", "rx"; | ||
| 137 | |||
| 138 | }; | ||
| @@ -0,0 +1,159 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: ST-Ericsson DMA40 DMA Engine | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Linus Walleij <linus.walleij@linaro.org> | ||
| 11 | |||
| 12 | allOf: | ||
| 13 | - $ref: "dma-controller.yaml#" | ||
| 14 | |||
| 15 | properties: | ||
| 16 | "#dma-cells": | ||
| 17 | const: 3 | ||
| 18 | description: | | ||
| 19 | The first cell is the unique device channel number as indicated by this | ||
| 20 | table for DB8500 which is the only ASIC known to use DMA40: | ||
| 21 | |||
| 22 | 0: SPI controller 0 | ||
| 23 | 1: SD/MMC controller 0 (unused) | ||
| 24 | 2: SD/MMC controller 1 (unused) | ||
| 25 | 3: SD/MMC controller 2 (unused) | ||
| 26 | 4: I2C port 1 | ||
| 27 | 5: I2C port 3 | ||
| 28 | 6: I2C port 2 | ||
| 29 | 7: I2C port 4 | ||
| 30 | 8: Synchronous Serial Port SSP0 | ||
| 31 | 9: Synchronous Serial Port SSP1 | ||
| 32 | 10: Multi-Channel Display Engine MCDE RX | ||
| 33 | 11: UART port 2 | ||
| 34 | 12: UART port 1 | ||
| 35 | 13: UART port 0 | ||
| 36 | 14: Multirate Serial Port MSP2 | ||
| 37 | 15: I2C port 0 | ||
| 38 | 16: USB OTG in/out endpoints 7 & 15 | ||
| 39 | 17: USB OTG in/out endpoints 6 & 14 | ||
| 40 | 18: USB OTG in/out endpoints 5 & 13 | ||
| 41 | 19: USB OTG in/out endpoints 4 & 12 | ||
| 42 | 20: SLIMbus or HSI channel 0 | ||
| 43 | 21: SLIMbus or HSI channel 1 | ||
| 44 | 22: SLIMbus or HSI channel 2 | ||
| 45 | 23: SLIMbus or HSI channel 3 | ||
| 46 | 24: Multimedia DSP SXA0 | ||
| 47 | 25: Multimedia DSP SXA1 | ||
| 48 | 26: Multimedia DSP SXA2 | ||
| 49 | 27: Multimedia DSP SXA3 | ||
| 50 | 28: SD/MMC controller 2 | ||
| 51 | 29: SD/MMC controller 0 | ||
| 52 | 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 | ||
| 53 | 31: MSP port 0 or SLIMbus channel 0 | ||
| 54 | 32: SD/MMC controller 1 | ||
| 55 | 33: SPI controller 2 | ||
| 56 | 34: i2c3 RX2 TX2 | ||
| 57 | 35: SPI controller 1 | ||
| 58 | 36: USB OTG in/out endpoints 3 & 11 | ||
| 59 | 37: USB OTG in/out endpoints 2 & 10 | ||
| 60 | 38: USB OTG in/out endpoints 1 & 9 | ||
| 61 | 39: USB OTG in/out endpoints 8 | ||
| 62 | 40: SPI controller 3 | ||
| 63 | 41: SD/MMC controller 3 | ||
| 64 | 42: SD/MMC controller 4 | ||
| 65 | 43: SD/MMC controller 5 | ||
| 66 | 44: Multimedia DSP SXA4 | ||
| 67 | 45: Multimedia DSP SXA5 | ||
| 68 | 46: SLIMbus channel 8 or Multimedia DSP SXA6 | ||
| 69 | 47: SLIMbus channel 9 or Multimedia DSP SXA7 | ||
| 70 | 48: Crypto Accelerator 1 | ||
| 71 | 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX | ||
| 72 | 50: Hash Accelerator 1 TX | ||
| 73 | 51: memcpy TX (to be used by the DMA driver for memcpy operations) | ||
| 74 | 52: SLIMbus or HSI channel 4 | ||
| 75 | 53: SLIMbus or HSI channel 5 | ||
| 76 | 54: SLIMbus or HSI channel 6 | ||
| 77 | 55: SLIMbus or HSI channel 7 | ||
| 78 | 56: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 79 | 57: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 80 | 58: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 81 | 59: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 82 | 60: memcpy (to be used by the DMA driver for memcpy operations) | ||
| 83 | 61: Crypto Accelerator 0 | ||
| 84 | 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX | ||
| 85 | 63: Hash Accelerator 0 TX | ||
| 86 | |||
| 87 | The second cell is the DMA request line number. This is only used when | ||
| 88 | a fixed channel is allocated, and indicated by setting bit 3 in the | ||
| 89 | flags field (see below). | ||
| 90 | |||
| 91 | The third cell is a 32bit flags bitfield with the following possible | ||
| 92 | bits set: | ||
| 93 | 0x00000001 (bit 0) - mode: | ||
| 94 | Logical channel when unset | ||
| 95 | Physical channel when set | ||
| 96 | 0x00000002 (bit 1) - direction: | ||
| 97 | Memory to Device when unset | ||
| 98 | Device to Memory when set | ||
| 99 | 0x00000004 (bit 2) - endianness: | ||
| 100 | Little endian when unset | ||
| 101 | Big endian when set | ||
| 102 | 0x00000008 (bit 3) - use fixed channel: | ||
| 103 | Use automatic channel selection when unset | ||
| 104 | Use DMA request line number when set | ||
| 105 | 0x00000010 (bit 4) - set channel as high priority: | ||
| 106 | Normal priority when unset | ||
| 107 | High priority when set | ||
| 108 | |||
| 109 | compatible: | ||
| 110 | items: | ||
| 111 | - const: stericsson,db8500-dma40 | ||
| 112 | - const: stericsson,dma40 | ||
| 113 | |||
| 114 | reg: | ||
| 115 | items: | ||
| 116 | - description: DMA40 memory base | ||
| 117 | - description: LCPA memory base | ||
| 118 | |||
| 119 | reg-names: | ||
| 120 | items: | ||
| 121 | - const: base | ||
| 122 | - const: lcpa | ||
| 123 | |||
| 124 | interrupts: | ||
| 125 | maxItems: 1 | ||
| 126 | |||
| 127 | clocks: | ||
| 128 | maxItems: 1 | ||
| 129 | |||
| 130 | memcpy-channels: | ||
| 131 | $ref: /schemas/types.yaml#/definitions/uint32-array | ||
| 132 | description: Array of u32 elements indicating which channels on the DMA | ||
| 133 | engine are elegible for memcpy transfers | ||
| 134 | |||
| 135 | required: | ||
| 136 | - "#dma-cells" | ||
| 137 | - compatible | ||
| 138 | - reg | ||
| 139 | - interrupts | ||
| 140 | - clocks | ||
| 141 | - memcpy-channels | ||
| 142 | |||
| 143 | additionalProperties: false | ||
| 144 | |||
| 145 | examples: | ||
| 146 | - | | ||
| 147 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 148 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 149 | #include <dt-bindings/mfd/dbx500-prcmu.h> | ||
| 150 | dma-controller@801C0000 { | ||
| 151 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | ||
| 152 | reg = <0x801C0000 0x1000>, <0x40010000 0x800>; | ||
| 153 | reg-names = "base", "lcpa"; | ||
| 154 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | ||
| 155 | #dma-cells = <3>; | ||
| 156 | memcpy-channels = <56 57 58 59 60>; | ||
| 157 | clocks = <&prcmu_clk PRCMU_DMACLK>; | ||
| 158 | }; | ||
| 159 | ... | ||
| @@ -0,0 +1,91 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: MediaTek mt8186 DSP core | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Tinghan Shen <tinghan.shen@mediatek.com> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | MediaTek mt8186 SoC contains a DSP core used for | ||
| 14 | advanced pre- and post- audio processing. | ||
| 15 | |||
| 16 | properties: | ||
| 17 | compatible: | ||
| 18 | const: mediatek,mt8186-dsp | ||
| 19 | |||
| 20 | reg: | ||
| 21 | items: | ||
| 22 | - description: Address and size of the DSP config registers | ||
| 23 | - description: Address and size of the DSP SRAM | ||
| 24 | - description: Address and size of the DSP secure registers | ||
| 25 | - description: Address and size of the DSP bus registers | ||
| 26 | |||
| 27 | reg-names: | ||
| 28 | items: | ||
| 29 | - const: cfg | ||
| 30 | - const: sram | ||
| 31 | - const: sec | ||
| 32 | - const: bus | ||
| 33 | |||
| 34 | clocks: | ||
| 35 | items: | ||
| 36 | - description: mux for audio dsp clock | ||
| 37 | - description: mux for audio dsp local bus | ||
| 38 | |||
| 39 | clock-names: | ||
| 40 | items: | ||
| 41 | - const: audiodsp | ||
| 42 | - const: adsp_bus | ||
| 43 | |||
| 44 | power-domains: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | mboxes: | ||
| 48 | items: | ||
| 49 | - description: mailbox for receiving audio DSP requests. | ||
| 50 | - description: mailbox for transmitting requests to audio DSP. | ||
| 51 | |||
| 52 | mbox-names: | ||
| 53 | items: | ||
| 54 | - const: rx | ||
| 55 | - const: tx | ||
| 56 | |||
| 57 | memory-region: | ||
| 58 | items: | ||
| 59 | - description: dma buffer between host and DSP. | ||
| 60 | - description: DSP system memory. | ||
| 61 | |||
| 62 | required: | ||
| 63 | - compatible | ||
| 64 | - reg | ||
| 65 | - reg-names | ||
| 66 | - clocks | ||
| 67 | - clock-names | ||
| 68 | - power-domains | ||
| 69 | - mbox-names | ||
| 70 | - mboxes | ||
| 71 | |||
| 72 | additionalProperties: false | ||
| 73 | |||
| 74 | examples: | ||
| 75 | - | | ||
| 76 | #include <dt-bindings/clock/mt8186-clk.h> | ||
| 77 | dsp@10680000 { | ||
| 78 | compatible = "mediatek,mt8186-dsp"; | ||
| 79 | reg = <0x10680000 0x2000>, | ||
| 80 | <0x10800000 0x100000>, | ||
| 81 | <0x1068b000 0x100>, | ||
| 82 | <0x1068f000 0x1000>; | ||
| 83 | reg-names = "cfg", "sram", "sec", "bus"; | ||
| 84 | clocks = <&topckgen CLK_TOP_AUDIODSP>, | ||
| 85 | <&topckgen CLK_TOP_ADSP_BUS>; | ||
| 86 | clock-names = "audiodsp", | ||
| 87 | "adsp_bus"; | ||
| 88 | power-domains = <&spm 6>; | ||
| 89 | mbox-names = "rx", "tx"; | ||
| 90 | mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; | ||
| 91 | }; | ||
| @@ -50,13 +50,13 @@ properties: · 49 unmodified lines | |||
| 50 | 50 | ||
| 51 | mboxes: | 51 | mboxes: |
| 52 | items: | 52 | items: |
| 53 | - description: ipc reply between host and audio DSP. | 53 | - description: mailbox for receiving audio DSP requests. |
| 54 | - description: ipc request between host and audio DSP. | 54 | - description: mailbox for transmitting requests to audio DSP. |
| 55 | 55 | ||
| 56 | mbox-names: | 56 | mbox-names: |
| 57 | items: | 57 | items: |
| 58 | - const: mbox0 | 58 | - const: rx |
| 59 | - const: mbox1 | 59 | - const: tx |
| 60 | 60 | ||
| 61 | memory-region: | 61 | memory-region: |
| 62 | items: | 62 | items: |
| @@ -100,6 +100,6 @@ examples: · 37 unmodified lines | |||
| 100 | memory-region = <&adsp_dma_mem_reserved>, | 100 | memory-region = <&adsp_dma_mem_reserved>, |
| 101 | <&adsp_mem_reserved>; | 101 | <&adsp_mem_reserved>; |
| 102 | power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP | 102 | power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP |
| 103 | mbox-names = "mbox0", "mbox1"; | 103 | mbox-names = "rx", "tx"; |
| 104 | mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; | 104 | mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; |
| 105 | }; | 105 | }; |
| @@ -44,8 +44,6 @@ properties: · 43 unmodified lines | |||
| 44 | reg: | 44 | reg: |
| 45 | maxItems: 1 | 45 | maxItems: 1 |
| 46 | 46 | ||
| 47 | spi-max-frequency: true | ||
| 48 | |||
| 49 | pagesize: | 47 | pagesize: |
| 50 | $ref: /schemas/types.yaml#/definitions/uint32 | 48 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 51 | enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072] | 49 | enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072] |
| @@ -105,6 +103,7 @@ required: · 53 unmodified lines | |||
| 105 | - spi-max-frequency | 103 | - spi-max-frequency |
| 106 | 104 | ||
| 107 | allOf: | 105 | allOf: |
| 106 | - $ref: /schemas/spi/spi-peripheral-props.yaml# | ||
| 108 | - if: | 107 | - if: |
| 109 | properties: | 108 | properties: |
| 110 | compatible: | 109 | compatible: |
| @@ -117,7 +116,7 @@ allOf: · 6 unmodified lines | |||
| 117 | - size | 116 | - size |
| 118 | - address-width | 117 | - address-width |
| 119 | 118 | ||
| 120 | additionalProperties: false | 119 | unevaluatedProperties: false |
| 121 | 120 | ||
| 122 | examples: | 121 | examples: |
| 123 | - | | 122 | - | |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/misc/eeprom-93xx46.yaml# | 4 | $id: http://devicetree.org/schemas/eeprom/microchip,93lc46b.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Microchip 93xx46 SPI compatible EEPROM family dt bindings | 7 | title: Microchip 93xx46 SPI compatible EEPROM family dt bindings |
| @@ -28,9 +28,6 @@ properties: · 20 unmodified lines | |||
| 28 | description: chip select of EEPROM | 28 | description: chip select of EEPROM |
| 29 | maxItems: 1 | 29 | maxItems: 1 |
| 30 | 30 | ||
| 31 | spi-max-frequency: true | ||
| 32 | spi-cs-high: true | ||
| 33 | |||
| 34 | read-only: | 31 | read-only: |
| 35 | description: | 32 | description: |
| 36 | parameter-less property which disables writes to the EEPROM | 33 | parameter-less property which disables writes to the EEPROM |
| @@ -42,14 +39,16 @@ properties: · 5 unmodified lines | |||
| 42 | of EEPROM (e.g. for SPI bus multiplexing) | 39 | of EEPROM (e.g. for SPI bus multiplexing) |
| 43 | maxItems: 1 | 40 | maxItems: 1 |
| 44 | 41 | ||
| 45 | |||
| 46 | required: | 42 | required: |
| 47 | - compatible | 43 | - compatible |
| 48 | - reg | 44 | - reg |
| 49 | - data-size | 45 | - data-size |
| 50 | - spi-max-frequency | 46 | - spi-max-frequency |
| 51 | 47 | ||
| 52 | additionalProperties: false | 48 | allOf: |
| 49 | - $ref: /schemas/spi/spi-peripheral-props.yaml# | ||
| 50 | |||
| 51 | unevaluatedProperties: false | ||
| 53 | 52 | ||
| 54 | examples: | 53 | examples: |
| 55 | - | | 54 | - | |
| @@ -183,6 +183,12 @@ properties: · 182 unmodified lines | |||
| 183 | required: | 183 | required: |
| 184 | - reg | 184 | - reg |
| 185 | 185 | ||
| 186 | protocol@18: | ||
| 187 | type: object | ||
| 188 | properties: | ||
| 189 | reg: | ||
| 190 | const: 0x18 | ||
| 191 | |||
| 186 | additionalProperties: false | 192 | additionalProperties: false |
| 187 | 193 | ||
| 188 | patternProperties: | 194 | patternProperties: |
| @@ -323,6 +329,10 @@ examples: · 134 unmodified lines | |||
| 323 | }; | 329 | }; |
| 324 | }; | 330 | }; |
| 325 | }; | 331 | }; |
| 332 | |||
| 333 | scmi_powercap: protocol@18 { | ||
| 334 | reg = <0x18>; | ||
| 335 | }; | ||
| 326 | }; | 336 | }; |
| 327 | }; | 337 | }; |
| 328 | 338 | ||
| @@ -0,0 +1,210 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NXP i.MX System Controller Firmware (SCFW) | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Dong Aisheng <aisheng.dong@nxp.com> | ||
| 11 | |||
| 12 | description: | ||
| 13 | The System Controller Firmware (SCFW) is a low-level system function | ||
| 14 | which runs on a dedicated Cortex-M core to provide power, clock, and | ||
| 15 | resource management. It exists on some i.MX8 processors. e.g. i.MX8QM | ||
| 16 | (QM, QP), and i.MX8QX (QXP, DX). | ||
| 17 | The AP communicates with the SC using a multi-ported MU module found | ||
| 18 | in the LSIO subsystem. The current definition of this MU module provides | ||
| 19 | 5 remote AP connections to the SC to support up to 5 execution environments | ||
| 20 | (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces | ||
| 21 | with the LSIO DSC IP bus. The SC firmware will communicate with this MU | ||
| 22 | using the MSI bus. | ||
| 23 | |||
| 24 | properties: | ||
| 25 | compatible: | ||
| 26 | const: fsl,imx-scu | ||
| 27 | |||
| 28 | clock-controller: | ||
| 29 | description: | ||
| 30 | Clock controller node that provides the clocks controlled by the SCU | ||
| 31 | $ref: /schemas/clock/fsl,scu-clk.yaml | ||
| 32 | |||
| 33 | ocotp: | ||
| 34 | description: | ||
| 35 | OCOTP controller node provided by the SCU | ||
| 36 | $ref: /schemas/nvmem/fsl,scu-ocotp.yaml | ||
| 37 | |||
| 38 | keys: | ||
| 39 | description: | ||
| 40 | Keys provided by the SCU | ||
| 41 | $ref: /schemas/input/fsl,scu-key.yaml | ||
| 42 | |||
| 43 | mboxes: | ||
| 44 | description: | ||
| 45 | A list of phandles of TX MU channels followed by a list of phandles of | ||
| 46 | RX MU channels. The list may include at the end one more optional MU | ||
| 47 | channel for general interrupt. The number of expected tx and rx | ||
| 48 | channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu" | ||
| 49 | compatible, 4 TX and 4 RX channels otherwise. All MU channels must be | ||
| 50 | within the same MU instance. Cross instances are not allowed. The MU | ||
| 51 | instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users | ||
| 52 | need to ensure that one is used that does not conflict with other | ||
| 53 | execution environments such as ATF. | ||
| 54 | oneOf: | ||
| 55 | - items: | ||
| 56 | - description: TX0 MU channel | ||
| 57 | - description: RX0 MU channel | ||
| 58 | - items: | ||
| 59 | - description: TX0 MU channel | ||
| 60 | - description: RX0 MU channel | ||
| 61 | - description: optional MU channel for general interrupt | ||
| 62 | - items: | ||
| 63 | - description: TX0 MU channel | ||
| 64 | - description: TX1 MU channel | ||
| 65 | - description: TX2 MU channel | ||
| 66 | - description: TX3 MU channel | ||
| 67 | - description: RX0 MU channel | ||
| 68 | - description: RX1 MU channel | ||
| 69 | - description: RX2 MU channel | ||
| 70 | - description: RX3 MU channel | ||
| 71 | - items: | ||
| 72 | - description: TX0 MU channel | ||
| 73 | - description: TX1 MU channel | ||
| 74 | - description: TX2 MU channel | ||
| 75 | - description: TX3 MU channel | ||
| 76 | - description: RX0 MU channel | ||
| 77 | - description: RX1 MU channel | ||
| 78 | - description: RX2 MU channel | ||
| 79 | - description: RX3 MU channel | ||
| 80 | - description: optional MU channel for general interrupt | ||
| 81 | |||
| 82 | mbox-names: | ||
| 83 | oneOf: | ||
| 84 | - items: | ||
| 85 | - const: tx0 | ||
| 86 | - const: rx0 | ||
| 87 | - items: | ||
| 88 | - const: tx0 | ||
| 89 | - const: rx0 | ||
| 90 | - const: gip3 | ||
| 91 | - items: | ||
| 92 | - const: tx0 | ||
| 93 | - const: tx1 | ||
| 94 | - const: tx2 | ||
| 95 | - const: tx3 | ||
| 96 | - const: rx0 | ||
| 97 | - const: rx1 | ||
| 98 | - const: rx2 | ||
| 99 | - const: rx3 | ||
| 100 | - items: | ||
| 101 | - const: tx0 | ||
| 102 | - const: tx1 | ||
| 103 | - const: tx2 | ||
| 104 | - const: tx3 | ||
| 105 | - const: rx0 | ||
| 106 | - const: rx1 | ||
| 107 | - const: rx2 | ||
| 108 | - const: rx3 | ||
| 109 | - const: gip3 | ||
| 110 | |||
| 111 | pinctrl: | ||
| 112 | description: | ||
| 113 | Pin controller provided by the SCU | ||
| 114 | $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml | ||
| 115 | |||
| 116 | power-controller: | ||
| 117 | description: | ||
| 118 | Power domains controller node that provides the power domains | ||
| 119 | controlled by the SCU | ||
| 120 | $ref: /schemas/power/fsl,scu-pd.yaml | ||
| 121 | |||
| 122 | rtc: | ||
| 123 | description: | ||
| 124 | RTC controller provided by the SCU | ||
| 125 | $ref: /schemas/rtc/fsl,scu-rtc.yaml | ||
| 126 | |||
| 127 | thermal-sensor: | ||
| 128 | description: | ||
| 129 | Thermal sensor provided by the SCU | ||
| 130 | $ref: /schemas/thermal/fsl,scu-thermal.yaml | ||
| 131 | |||
| 132 | watchdog: | ||
| 133 | description: | ||
| 134 | Watchdog controller provided by the SCU | ||
| 135 | $ref: /schemas/watchdog/fsl,scu-wdt.yaml | ||
| 136 | |||
| 137 | required: | ||
| 138 | - compatible | ||
| 139 | - mbox-names | ||
| 140 | - mboxes | ||
| 141 | |||
| 142 | additionalProperties: false | ||
| 143 | |||
| 144 | examples: | ||
| 145 | - | | ||
| 146 | #include <dt-bindings/firmware/imx/rsrc.h> | ||
| 147 | #include <dt-bindings/input/input.h> | ||
| 148 | #include <dt-bindings/pinctrl/pads-imx8qxp.h> | ||
| 149 | |||
| 150 | firmware { | ||
| 151 | system-controller { | ||
| 152 | compatible = "fsl,imx-scu"; | ||
| 153 | mbox-names = "tx0", "tx1", "tx2", "tx3", | ||
| 154 | "rx0", "rx1", "rx2", "rx3", | ||
| 155 | "gip3"; | ||
| 156 | mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3 | ||
| 157 | &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3 | ||
| 158 | &lsio_mu1 3 3>; | ||
| 159 | |||
| 160 | clock-controller { | ||
| 161 | compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; | ||
| 162 | #clock-cells = <2>; | ||
| 163 | }; | ||
| 164 | |||
| 165 | pinctrl { | ||
| 166 | compatible = "fsl,imx8qxp-iomuxc"; | ||
| 167 | |||
| 168 | pinctrl_lpuart0: lpuart0grp { | ||
| 169 | fsl,pins = < | ||
| 170 | IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 | ||
| 171 | IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 | ||
| 172 | >; | ||
| 173 | }; | ||
| 174 | }; | ||
| 175 | |||
| 176 | ocotp { | ||
| 177 | compatible = "fsl,imx8qxp-scu-ocotp"; | ||
| 178 | #address-cells = <1>; | ||
| 179 | #size-cells = <1>; | ||
| 180 | |||
| 181 | fec_mac0: mac@2c4 { | ||
| 182 | reg = <0x2c4 6>; | ||
| 183 | }; | ||
| 184 | }; | ||
| 185 | |||
| 186 | power-controller { | ||
| 187 | compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; | ||
| 188 | #power-domain-cells = <1>; | ||
| 189 | }; | ||
| 190 | |||
| 191 | rtc { | ||
| 192 | compatible = "fsl,imx8qxp-sc-rtc"; | ||
| 193 | }; | ||
| 194 | |||
| 195 | keys { | ||
| 196 | compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; | ||
| 197 | linux,keycodes = <KEY_POWER>; | ||
| 198 | }; | ||
| 199 | |||
| 200 | watchdog { | ||
| 201 | compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; | ||
| 202 | timeout-sec = <60>; | ||
| 203 | }; | ||
| 204 | |||
| 205 | thermal-sensor { | ||
| 206 | compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; | ||
| 207 | #thermal-sensor-cells = <1>; | ||
| 208 | }; | ||
| 209 | }; | ||
| 210 | }; | ||
| @@ -23,10 +23,13 @@ Required properties: · 22 unmodified lines | |||
| 23 | * "qcom,scm-msm8994" | 23 | * "qcom,scm-msm8994" |
| 24 | * "qcom,scm-msm8996" | 24 | * "qcom,scm-msm8996" |
| 25 | * "qcom,scm-msm8998" | 25 | * "qcom,scm-msm8998" |
| 26 | * "qcom,scm-qcs404" | ||
| 26 | * "qcom,scm-sc7180" | 27 | * "qcom,scm-sc7180" |
| 27 | * "qcom,scm-sc7280" | 28 | * "qcom,scm-sc7280" |
| 29 | * "qcom,scm-sm6125" | ||
| 28 | * "qcom,scm-sdm845" | 30 | * "qcom,scm-sdm845" |
| 29 | * "qcom,scm-sdx55" | 31 | * "qcom,scm-sdx55" |
| 32 | * "qcom,scm-sdx65" | ||
| 30 | * "qcom,scm-sm6350" | 33 | * "qcom,scm-sm6350" |
| 31 | * "qcom,scm-sm8150" | 34 | * "qcom,scm-sm8150" |
| 32 | * "qcom,scm-sm8250" | 35 | * "qcom,scm-sm8250" |
| @@ -43,6 +46,7 @@ Required properties: · 10 unmodified lines | |||
| 43 | clock and "bus" for the bus clock per the requirements of the compatible. | 46 | clock and "bus" for the bus clock per the requirements of the compatible. |
| 44 | - qcom,dload-mode: phandle to the TCSR hardware block and offset of the | 47 | - qcom,dload-mode: phandle to the TCSR hardware block and offset of the |
| 45 | download mode control register (optional) | 48 | download mode control register (optional) |
| 49 | - interconnects: Specifies the bandwidth requirements of the SCM interface (optional) | ||
| 46 | 50 | ||
| 47 | Example for MSM8916: | 51 | Example for MSM8916: |
| 48 | 52 | ||
| @@ -330,7 +330,7 @@ succeeded. · 329 unmodified lines | |||
| 330 | 330 | ||
| 331 | The Device Tree Overlay will contain: | 331 | The Device Tree Overlay will contain: |
| 332 | * "target-path" or "target" | 332 | * "target-path" or "target" |
| 333 | The insertion point where the the contents of the overlay will go into the | 333 | The insertion point where the contents of the overlay will go into the |
| 334 | live tree. target-path is a full path, while target is a phandle. | 334 | live tree. target-path is a full path, while target is a phandle. |
| 335 | * "ranges" | 335 | * "ranges" |
| 336 | The address space mapping from processor to FPGA bus(ses). | 336 | The address space mapping from processor to FPGA bus(ses). |
| @@ -0,0 +1,44 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Microchip Polarfire FPGA manager. | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Ivan Bornyakov <i.bornyakov@metrotek.ru> | ||
| 11 | |||
| 12 | description: | ||
| 13 | Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to | ||
| 14 | load the bitstream in .dat format. | ||
| 15 | |||
| 16 | properties: | ||
| 17 | compatible: | ||
| 18 | enum: | ||
| 19 | - microchip,mpf-spi-fpga-mgr | ||
| 20 | |||
| 21 | reg: | ||
| 22 | description: SPI chip select | ||
| 23 | maxItems: 1 | ||
| 24 | |||
| 25 | spi-max-frequency: true | ||
| 26 | |||
| 27 | required: | ||
| 28 | - compatible | ||
| 29 | - reg | ||
| 30 | |||
| 31 | additionalProperties: false | ||
| 32 | |||
| 33 | examples: | ||
| 34 | - | | ||
| 35 | spi { | ||
| 36 | #address-cells = <1>; | ||
| 37 | #size-cells = <0>; | ||
| 38 | |||
| 39 | fpga_mgr@0 { | ||
| 40 | compatible = "microchip,mpf-spi-fpga-mgr"; | ||
| 41 | spi-max-frequency = <20000000>; | ||
| 42 | reg = <0>; | ||
| 43 | }; | ||
| 44 | }; | ||
| @@ -37,6 +37,8 @@ properties: · 36 unmodified lines | |||
| 37 | - fsl,imx8mp-gpio | 37 | - fsl,imx8mp-gpio |
| 38 | - fsl,imx8mq-gpio | 38 | - fsl,imx8mq-gpio |
| 39 | - fsl,imx8qxp-gpio | 39 | - fsl,imx8qxp-gpio |
| 40 | - fsl,imxrt1050-gpio | ||
| 41 | - fsl,imxrt1170-gpio | ||
| 40 | - const: fsl,imx35-gpio | 42 | - const: fsl,imx35-gpio |
| 41 | 43 | ||
| 42 | reg: | 44 | reg: |
| @@ -1,93 +0,0 @@ | |||
| 1 | * Marvell EBU GPIO controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | |||
| 5 | - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio", | ||
| 6 | "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio". | ||
| 7 | |||
| 8 | "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove, | ||
| 9 | Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio" | ||
| 10 | should be used for the Discovery MV78200. | ||
| 11 | |||
| 12 | "marvel,armadaxp-gpio" should be used for all Armada XP SoCs | ||
| 13 | (MV78230, MV78260, MV78460). | ||
| 14 | |||
| 15 | "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K | ||
| 16 | SoCs (either from AP or CP), see | ||
| 17 | Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt | ||
| 18 | for specific details about the offset property. | ||
| 19 | |||
| 20 | - reg: Address and length of the register set for the device. Only one | ||
| 21 | entry is expected, except for the "marvell,armadaxp-gpio" variant | ||
| 22 | for which two entries are expected: one for the general registers, | ||
| 23 | one for the per-cpu registers. Not used for marvell,armada-8k-gpio. | ||
| 24 | |||
| 25 | - interrupts: The list of interrupts that are used for all the pins | ||
| 26 | managed by this GPIO bank. There can be more than one interrupt | ||
| 27 | (example: 1 interrupt per 8 pins on Armada XP, which means 4 | ||
| 28 | interrupts per bank of 32 GPIOs). | ||
| 29 | |||
| 30 | - interrupt-controller: identifies the node as an interrupt controller | ||
| 31 | |||
| 32 | - #interrupt-cells: specifies the number of cells needed to encode an | ||
| 33 | interrupt source. Should be two. | ||
| 34 | The first cell is the GPIO number. | ||
| 35 | The second cell is used to specify flags: | ||
| 36 | bits[3:0] trigger type and level flags: | ||
| 37 | 1 = low-to-high edge triggered. | ||
| 38 | 2 = high-to-low edge triggered. | ||
| 39 | 4 = active high level-sensitive. | ||
| 40 | 8 = active low level-sensitive. | ||
| 41 | |||
| 42 | - gpio-controller: marks the device node as a gpio controller | ||
| 43 | |||
| 44 | - ngpios: number of GPIOs this controller has | ||
| 45 | |||
| 46 | - #gpio-cells: Should be two. The first cell is the pin number. The | ||
| 47 | second cell is reserved for flags, unused at the moment. | ||
| 48 | |||
| 49 | Optional properties: | ||
| 50 | |||
| 51 | In order to use the GPIO lines in PWM mode, some additional optional | ||
| 52 | properties are required. | ||
| 53 | |||
| 54 | - compatible: Must contain "marvell,armada-370-gpio" | ||
| 55 | |||
| 56 | - reg: an additional register set is needed, for the GPIO Blink | ||
| 57 | Counter on/off registers. | ||
| 58 | |||
| 59 | - reg-names: Must contain an entry "pwm" corresponding to the | ||
| 60 | additional register range needed for PWM operation. | ||
| 61 | |||
| 62 | - #pwm-cells: Should be two. The first cell is the GPIO line number. The | ||
| 63 | second cell is the period in nanoseconds. | ||
| 64 | |||
| 65 | - clocks: Must be a phandle to the clock for the GPIO controller. | ||
| 66 | |||
| 67 | Example: | ||
| 68 | |||
| 69 | gpio0: gpio@d0018100 { | ||
| 70 | compatible = "marvell,armadaxp-gpio"; | ||
| 71 | reg = <0xd0018100 0x40>, | ||
| 72 | <0xd0018800 0x30>; | ||
| 73 | ngpios = <32>; | ||
| 74 | gpio-controller; | ||
| 75 | #gpio-cells = <2>; | ||
| 76 | interrupt-controller; | ||
| 77 | #interrupt-cells = <2>; | ||
| 78 | interrupts = <16>, <17>, <18>, <19>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | gpio1: gpio@18140 { | ||
| 82 | compatible = "marvell,armada-370-gpio"; | ||
| 83 | reg = <0x18140 0x40>, <0x181c8 0x08>; | ||
| 84 | reg-names = "gpio", "pwm"; | ||
| 85 | ngpios = <17>; | ||
| 86 | gpio-controller; | ||
| 87 | #gpio-cells = <2>; | ||
| 88 | #pwm-cells = <2>; | ||
| 89 | interrupt-controller; | ||
| 90 | #interrupt-cells = <2>; | ||
| 91 | interrupts = <87>, <88>, <89>; | ||
| 92 | clocks = <&coreclk 0>; | ||
| 93 | }; | ||
| @@ -0,0 +1,146 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Marvell EBU GPIO controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 11 | - Andrew Lunn <andrew@lunn.ch> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | compatible: | ||
| 15 | oneOf: | ||
| 16 | - enum: | ||
| 17 | - marvell,armada-8k-gpio | ||
| 18 | - marvell,orion-gpio | ||
| 19 | |||
| 20 | - items: | ||
| 21 | - enum: | ||
| 22 | - marvell,mv78200-gpio | ||
| 23 | - marvell,armada-370-gpio | ||
| 24 | - const: marvell,orion-gpio | ||
| 25 | |||
| 26 | - description: Deprecated binding | ||
| 27 | items: | ||
| 28 | - const: marvell,armadaxp-gpio | ||
| 29 | - const: marvell,orion-gpio | ||
| 30 | deprecated: true | ||
| 31 | |||
| 32 | reg: | ||
| 33 | description: | | ||
| 34 | Address and length of the register set for the device. Not used for | ||
| 35 | marvell,armada-8k-gpio. | ||
| 36 | |||
| 37 | A second entry can be provided, for the PWM function using the GPIO Blink | ||
| 38 | Counter on/off registers. | ||
| 39 | minItems: 1 | ||
| 40 | maxItems: 2 | ||
| 41 | |||
| 42 | reg-names: | ||
| 43 | items: | ||
| 44 | - const: gpio | ||
| 45 | - const: pwm | ||
| 46 | minItems: 1 | ||
| 47 | |||
| 48 | offset: | ||
| 49 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 50 | description: Offset in the register map for the gpio registers (in bytes) | ||
| 51 | |||
| 52 | interrupts: | ||
| 53 | description: | | ||
| 54 | The list of interrupts that are used for all the pins managed by this | ||
| 55 | GPIO bank. There can be more than one interrupt (example: 1 interrupt | ||
| 56 | per 8 pins on Armada XP, which means 4 interrupts per bank of 32 | ||
| 57 | GPIOs). | ||
| 58 | minItems: 1 | ||
| 59 | maxItems: 4 | ||
| 60 | |||
| 61 | interrupt-controller: true | ||
| 62 | |||
| 63 | "#interrupt-cells": | ||
| 64 | const: 2 | ||
| 65 | |||
| 66 | gpio-controller: true | ||
| 67 | |||
| 68 | ngpios: | ||
| 69 | minimum: 1 | ||
| 70 | maximum: 32 | ||
| 71 | |||
| 72 | "#gpio-cells": | ||
| 73 | const: 2 | ||
| 74 | |||
| 75 | marvell,pwm-offset: | ||
| 76 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 77 | description: Offset in the register map for the pwm registers (in bytes) | ||
| 78 | |||
| 79 | "#pwm-cells": | ||
| 80 | description: | ||
| 81 | The first cell is the GPIO line number. The second cell is the period | ||
| 82 | in nanoseconds. | ||
| 83 | const: 2 | ||
| 84 | |||
| 85 | clocks: | ||
| 86 | description: | ||
| 87 | Clock(s) used for PWM function. | ||
| 88 | items: | ||
| 89 | - description: Core clock | ||
| 90 | - description: AXI bus clock | ||
| 91 | minItems: 1 | ||
| 92 | |||
| 93 | clock-names: | ||
| 94 | items: | ||
| 95 | - const: core | ||
| 96 | - const: axi | ||
| 97 | minItems: 1 | ||
| 98 | |||
| 99 | required: | ||
| 100 | - compatible | ||
| 101 | - gpio-controller | ||
| 102 | - ngpios | ||
| 103 | - "#gpio-cells" | ||
| 104 | |||
| 105 | allOf: | ||
| 106 | - if: | ||
| 107 | properties: | ||
| 108 | compatible: | ||
| 109 | contains: | ||
| 110 | const: marvell,armada-8k-gpio | ||
| 111 | then: | ||
| 112 | required: | ||
| 113 | - offset | ||
| 114 | else: | ||
| 115 | required: | ||
| 116 | - reg | ||
| 117 | |||
| 118 | unevaluatedProperties: true | ||
| 119 | |||
| 120 | examples: | ||
| 121 | - | | ||
| 122 | gpio@d0018100 { | ||
| 123 | compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; | ||
| 124 | reg = <0xd0018100 0x40>, <0xd0018800 0x30>; | ||
| 125 | ngpios = <32>; | ||
| 126 | gpio-controller; | ||
| 127 | #gpio-cells = <2>; | ||
| 128 | interrupt-controller; | ||
| 129 | #interrupt-cells = <2>; | ||
| 130 | interrupts = <16>, <17>, <18>, <19>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | - | | ||
| 134 | gpio@18140 { | ||
| 135 | compatible = "marvell,armada-370-gpio", "marvell,orion-gpio"; | ||
| 136 | reg = <0x18140 0x40>, <0x181c8 0x08>; | ||
| 137 | reg-names = "gpio", "pwm"; | ||
| 138 | ngpios = <17>; | ||
| 139 | gpio-controller; | ||
| 140 | #gpio-cells = <2>; | ||
| 141 | #pwm-cells = <2>; | ||
| 142 | interrupt-controller; | ||
| 143 | #interrupt-cells = <2>; | ||
| 144 | interrupts = <87>, <88>, <89>; | ||
| 145 | clocks = <&coreclk 0>; | ||
| 146 | }; | ||
| @@ -13,6 +13,7 @@ properties: · 12 unmodified lines | |||
| 13 | compatible: | 13 | compatible: |
| 14 | enum: | 14 | enum: |
| 15 | - nxp,pca9570 | 15 | - nxp,pca9570 |
| 16 | - nxp,pca9571 | ||
| 16 | 17 | ||
| 17 | reg: | 18 | reg: |
| 18 | maxItems: 1 | 19 | maxItems: 1 |
| @@ -14,7 +14,7 @@ Optional properties: · 13 unmodified lines | |||
| 14 | - ngpios : Number of used GPIO lines (0..n-1), default is 8. | 14 | - ngpios : Number of used GPIO lines (0..n-1), default is 8. |
| 15 | - load-gpios : GPIO pin specifier attached to load enable, this | 15 | - load-gpios : GPIO pin specifier attached to load enable, this |
| 16 | pin is pulsed before reading from the device to | 16 | pin is pulsed before reading from the device to |
| 17 | load input pin values into the the device. | 17 | load input pin values into the device. |
| 18 | 18 | ||
| 19 | For other required and optional properties of SPI slave | 19 | For other required and optional properties of SPI slave |
| 20 | nodes please refer to ../spi/spi-bus.txt. | 20 | nodes please refer to ../spi/spi-bus.txt. |
| @@ -1,16 +0,0 @@ | |||
| 1 | TPIC2810 GPIO controller bindings | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : Should be "ti,tpic2810". | ||
| 5 | - reg : The I2C address of the device | ||
| 6 | - gpio-controller : Marks the device node as a GPIO controller. | ||
| 7 | - #gpio-cells : Should be two. For consumer use see gpio.txt. | ||
| 8 | |||
| 9 | Example: | ||
| 10 | |||
| 11 | gpio@60 { | ||
| 12 | compatible = "ti,tpic2810"; | ||
| 13 | reg = <0x60>; | ||
| 14 | gpio-controller; | ||
| 15 | #gpio-cells = <2>; | ||
| 16 | }; | ||
| @@ -0,0 +1,51 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/gpio/gpio-tpic2810.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: TPIC2810 GPIO controller bindings | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Aswath Govindraju <a-govindraju@ti.com> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | compatible: | ||
| 14 | enum: | ||
| 15 | - ti,tpic2810 | ||
| 16 | |||
| 17 | reg: | ||
| 18 | maxItems: 1 | ||
| 19 | |||
| 20 | gpio-controller: true | ||
| 21 | |||
| 22 | "#gpio-cells": | ||
| 23 | const: 2 | ||
| 24 | |||
| 25 | gpio-line-names: | ||
| 26 | minItems: 1 | ||
| 27 | maxItems: 32 | ||
| 28 | |||
| 29 | required: | ||
| 30 | - compatible | ||
| 31 | - reg | ||
| 32 | - gpio-controller | ||
| 33 | - "#gpio-cells" | ||
| 34 | |||
| 35 | additionalProperties: false | ||
| 36 | |||
| 37 | examples: | ||
| 38 | - | | ||
| 39 | #include <dt-bindings/gpio/gpio.h> | ||
| 40 | |||
| 41 | i2c { | ||
| 42 | #address-cells = <1>; | ||
| 43 | #size-cells = <0>; | ||
| 44 | gpio@60 { | ||
| 45 | compatible = "ti,tpic2810"; | ||
| 46 | reg = <0x60>; | ||
| 47 | gpio-controller; | ||
| 48 | #gpio-cells = <2>; | ||
| 49 | gpio-line-names = "LED A", "LED B", "LED C"; | ||
| 50 | }; | ||
| 51 | }; | ||
| @@ -11,7 +11,11 @@ maintainers: · 10 unmodified lines | |||
| 11 | 11 | ||
| 12 | properties: | 12 | properties: |
| 13 | compatible: | 13 | compatible: |
| 14 | const: xlnx,zynq-gpio-1.0 | 14 | enum: |
| 15 | - xlnx,zynq-gpio-1.0 | ||
| 16 | - xlnx,zynqmp-gpio-1.0 | ||
| 17 | - xlnx,versal-gpio-1.0 | ||
| 18 | - xlnx,pmc-gpio-1.0 | ||
| 15 | 19 | ||
| 16 | reg: | 20 | reg: |
| 17 | maxItems: 1 | 21 | maxItems: 1 |
| @@ -24,6 +28,11 @@ properties: · 6 unmodified lines | |||
| 24 | 28 | ||
| 25 | gpio-controller: true | 29 | gpio-controller: true |
| 26 | 30 | ||
| 31 | gpio-line-names: | ||
| 32 | description: strings describing the names of each gpio line | ||
| 33 | minItems: 58 | ||
| 34 | maxItems: 174 | ||
| 35 | |||
| 27 | interrupt-controller: true | 36 | interrupt-controller: true |
| 28 | 37 | ||
| 29 | "#interrupt-cells": | 38 | "#interrupt-cells": |
| @@ -32,6 +41,54 @@ properties: · 2 unmodified lines | |||
| 32 | clocks: | 41 | clocks: |
| 33 | maxItems: 1 | 42 | maxItems: 1 |
| 34 | 43 | ||
| 44 | power-domains: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | allOf: | ||
| 48 | - if: | ||
| 49 | properties: | ||
| 50 | compatible: | ||
| 51 | enum: | ||
| 52 | - xlnx,zynqmp-gpio-1.0 | ||
| 53 | then: | ||
| 54 | properties: | ||
| 55 | gpio-line-names: | ||
| 56 | minItems: 174 | ||
| 57 | maxItems: 174 | ||
| 58 | |||
| 59 | - if: | ||
| 60 | properties: | ||
| 61 | compatible: | ||
| 62 | enum: | ||
| 63 | - xlnx,zynq-gpio-1.0 | ||
| 64 | then: | ||
| 65 | properties: | ||
| 66 | gpio-line-names: | ||
| 67 | minItems: 118 | ||
| 68 | maxItems: 118 | ||
| 69 | |||
| 70 | - if: | ||
| 71 | properties: | ||
| 72 | compatible: | ||
| 73 | enum: | ||
| 74 | - xlnx,versal-gpio-1.0 | ||
| 75 | then: | ||
| 76 | properties: | ||
| 77 | gpio-line-names: | ||
| 78 | minItems: 58 | ||
| 79 | maxItems: 58 | ||
| 80 | |||
| 81 | - if: | ||
| 82 | properties: | ||
| 83 | compatible: | ||
| 84 | enum: | ||
| 85 | - xlnx,pmc-gpio-1.0 | ||
| 86 | then: | ||
| 87 | properties: | ||
| 88 | gpio-line-names: | ||
| 89 | minItems: 116 | ||
| 90 | maxItems: 116 | ||
| 91 | |||
| 35 | required: | 92 | required: |
| 36 | - compatible | 93 | - compatible |
| 37 | - reg | 94 | - reg |
| @@ -48,11 +48,9 @@ properties: · 47 unmodified lines | |||
| 48 | - renesas,gpio-r8a77995 # R-Car D3 | 48 | - renesas,gpio-r8a77995 # R-Car D3 |
| 49 | - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2 | 49 | - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2 |
| 50 | 50 | ||
| 51 | - items: | ||
| 52 | - const: renesas,gpio-r8a779a0 # R-Car V3U | ||
| 53 | |||
| 54 | - items: | 51 | - items: |
| 55 | - enum: | 52 | - enum: |
| 53 | - renesas,gpio-r8a779a0 # R-Car V3U | ||
| 56 | - renesas,gpio-r8a779f0 # R-Car S4-8 | 54 | - renesas,gpio-r8a779f0 # R-Car S4-8 |
| 57 | - const: renesas,rcar-gen4-gpio # R-Car Gen4 | 55 | - const: renesas,rcar-gen4-gpio # R-Car Gen4 |
| 58 | 56 | ||
| @@ -27,6 +27,8 @@ properties: · 26 unmodified lines | |||
| 27 | - description: APB interface clock source | 27 | - description: APB interface clock source |
| 28 | - description: GPIO debounce reference clock source | 28 | - description: GPIO debounce reference clock source |
| 29 | 29 | ||
| 30 | gpio-ranges: true | ||
| 31 | |||
| 30 | gpio-controller: true | 32 | gpio-controller: true |
| 31 | 33 | ||
| 32 | gpio-line-names: true | 34 | gpio-line-names: true |
| @@ -46,6 +46,10 @@ properties: · 45 unmodified lines | |||
| 46 | maximum: 32 | 46 | maximum: 32 |
| 47 | default: 16 | 47 | default: 16 |
| 48 | 48 | ||
| 49 | gpio-line-names: | ||
| 50 | minItems: 1 | ||
| 51 | maxItems: 32 | ||
| 52 | |||
| 49 | gpio-controller: true | 53 | gpio-controller: true |
| 50 | 54 | ||
| 51 | required: | 55 | required: |
| @@ -19,7 +19,13 @@ properties: · 18 unmodified lines | |||
| 19 | oneOf: | 19 | oneOf: |
| 20 | - enum: | 20 | - enum: |
| 21 | - x-powers,axp209-gpio | 21 | - x-powers,axp209-gpio |
| 22 | - x-powers,axp221-gpio | ||
| 22 | - x-powers,axp813-gpio | 23 | - x-powers,axp813-gpio |
| 24 | - items: | ||
| 25 | - enum: | ||
| 26 | - x-powers,axp223-gpio | ||
| 27 | - x-powers,axp809-gpio | ||
| 28 | - const: x-powers,axp221-gpio | ||
| 23 | - items: | 29 | - items: |
| 24 | - const: x-powers,axp803-gpio | 30 | - const: x-powers,axp803-gpio |
| 25 | - const: x-powers,axp813-gpio | 31 | - const: x-powers,axp813-gpio |
| @@ -14,16 +14,21 @@ properties: · 13 unmodified lines | |||
| 14 | pattern: '^gpu@[a-f0-9]+$' | 14 | pattern: '^gpu@[a-f0-9]+$' |
| 15 | 15 | ||
| 16 | compatible: | 16 | compatible: |
| 17 | items: | 17 | oneOf: |
| 18 | - enum: | 18 | - items: |
| 19 | - amlogic,meson-g12a-mali | 19 | - enum: |
| 20 | - mediatek,mt8183-mali | 20 | - amlogic,meson-g12a-mali |
| 21 | - realtek,rtd1619-mali | 21 | - mediatek,mt8183-mali |
| 22 | - renesas,r9a07g044-mali | 22 | - realtek,rtd1619-mali |
| 23 | - renesas,r9a07g054-mali | 23 | - renesas,r9a07g044-mali |
| 24 | - rockchip,px30-mali | 24 | - renesas,r9a07g054-mali |
| 25 | - rockchip,rk3568-mali | 25 | - rockchip,px30-mali |
| 26 | - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable | 26 | - rockchip,rk3568-mali |
| 27 | - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable | ||
| 28 | - items: | ||
| 29 | - enum: | ||
| 30 | - mediatek,mt8192-mali | ||
| 31 | - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable | ||
| 27 | 32 | ||
| 28 | reg: | 33 | reg: |
| 29 | maxItems: 1 | 34 | maxItems: 1 |
| @@ -16,6 +16,7 @@ properties: · 15 unmodified lines | |||
| 16 | 16 | ||
| 17 | compatible: | 17 | compatible: |
| 18 | enum: | 18 | enum: |
| 19 | - brcm,2711-v3d | ||
| 19 | - brcm,7268-v3d | 20 | - brcm,7268-v3d |
| 20 | - brcm,7278-v3d | 21 | - brcm,7278-v3d |
| 21 | 22 | ||
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/renesas,prr.yaml# | 4 | $id: http://devicetree.org/schemas/hwinfo/renesas,prr.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Renesas Product Register | 7 | title: Renesas Product Register |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/soc/samsung/exynos-chipid.yaml# | 4 | $id: http://devicetree.org/schemas/hwinfo/samsung,exynos-chipid.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Samsung Exynos SoC series Chipid driver | 7 | title: Samsung Exynos SoC series Chipid driver |
| @@ -0,0 +1,30 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/hwinfo/samsung,s5pv210-chipid.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Samsung S5PV210 SoC ChipID | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Krzysztof Kozlowski <krzk@kernel.org> | ||
| 11 | |||
| 12 | properties: | ||
| 13 | compatible: | ||
| 14 | const: samsung,s5pv210-chipid | ||
| 15 | |||
| 16 | reg: | ||
| 17 | maxItems: 1 | ||
| 18 | |||
| 19 | required: | ||
| 20 | - compatible | ||
| 21 | - reg | ||
| 22 | |||
| 23 | additionalProperties: false | ||
| 24 | |||
| 25 | examples: | ||
| 26 | - | | ||
| 27 | chipid@e0000000 { | ||
| 28 | compatible = "samsung,s5pv210-chipid"; | ||
| 29 | reg = <0xe0000000 0x1000>; | ||
| 30 | }; | ||
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/soc/ti/k3-socinfo.yaml# | 4 | $id: http://devicetree.org/schemas/hwinfo/ti,k3-socinfo.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Texas Instruments K3 Multicore SoC platforms chipid module | 7 | title: Texas Instruments K3 Multicore SoC platforms chipid module |
| @@ -8,7 +8,6 @@ title: Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Michael Hennerich <michael.hennerich@analog.com> | 10 | - Michael Hennerich <michael.hennerich@analog.com> |
| 11 | - Beniamin Bia <beniamin.bia@analog.com> | ||
| 12 | 11 | ||
| 13 | description: | | 12 | description: | |
| 14 | Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor | 13 | Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor |
| @@ -57,7 +57,7 @@ patternProperties: · 56 unmodified lines | |||
| 57 | Configures bypassing the individual voltage input attenuator. If | 57 | Configures bypassing the individual voltage input attenuator. If |
| 58 | set to 1 the attenuator is bypassed if set to 0 the attenuator is | 58 | set to 1 the attenuator is bypassed if set to 0 the attenuator is |
| 59 | not bypassed. If the property is absent then the attenuator | 59 | not bypassed. If the property is absent then the attenuator |
| 60 | retains it's configuration from the bios/bootloader. | 60 | retains its configuration from the bios/bootloader. |
| 61 | $ref: /schemas/types.yaml#/definitions/uint32 | 61 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 62 | enum: [0, 1] | 62 | enum: [0, 1] |
| 63 | 63 | ||
File renamed without changes.
| @@ -48,7 +48,6 @@ required: · 47 unmodified lines | |||
| 48 | - compatible | 48 | - compatible |
| 49 | - reg | 49 | - reg |
| 50 | - reg-names | 50 | - reg-names |
| 51 | - intel,vm-map | ||
| 52 | - clocks | 51 | - clocks |
| 53 | - resets | 52 | - resets |
| 54 | - "#thermal-sensor-cells" | 53 | - "#thermal-sensor-cells" |
| @@ -16,6 +16,7 @@ properties: · 15 unmodified lines | |||
| 16 | - adi,adm1032 | 16 | - adi,adm1032 |
| 17 | - adi,adt7461 | 17 | - adi,adt7461 |
| 18 | - adi,adt7461a | 18 | - adi,adt7461a |
| 19 | - adi,adt7481 | ||
| 19 | - dallas,max6646 | 20 | - dallas,max6646 |
| 20 | - dallas,max6647 | 21 | - dallas,max6647 |
| 21 | - dallas,max6649 | 22 | - dallas,max6649 |
| @@ -50,6 +51,12 @@ properties: · 28 unmodified lines | |||
| 50 | "#thermal-sensor-cells": | 51 | "#thermal-sensor-cells": |
| 51 | const: 1 | 52 | const: 1 |
| 52 | 53 | ||
| 54 | '#address-cells': | ||
| 55 | const: 1 | ||
| 56 | |||
| 57 | '#size-cells': | ||
| 58 | const: 0 | ||
| 59 | |||
| 53 | vcc-supply: | 60 | vcc-supply: |
| 54 | description: phandle to the regulator that provides the +VCC supply | 61 | description: phandle to the regulator that provides the +VCC supply |
| 55 | 62 | ||
| @@ -61,6 +68,29 @@ required: · 5 unmodified lines | |||
| 61 | - compatible | 68 | - compatible |
| 62 | - reg | 69 | - reg |
| 63 | 70 | ||
| 71 | patternProperties: | ||
| 72 | "^channel@([0-2])$": | ||
| 73 | type: object | ||
| 74 | description: Represents channels of the device and their specific configuration. | ||
| 75 | |||
| 76 | properties: | ||
| 77 | reg: | ||
| 78 | description: The channel number. 0 is local channel, 1-2 are remote channels. | ||
| 79 | items: | ||
| 80 | minimum: 0 | ||
| 81 | maximum: 2 | ||
| 82 | |||
| 83 | label: | ||
| 84 | description: A descriptive name for this channel, like "ambient" or "psu". | ||
| 85 | |||
| 86 | temperature-offset-millicelsius: | ||
| 87 | description: Temperature offset to be added to or subtracted from remote temperature measurements. | ||
| 88 | |||
| 89 | required: | ||
| 90 | - reg | ||
| 91 | |||
| 92 | additionalProperties: false | ||
| 93 | |||
| 64 | allOf: | 94 | allOf: |
| 65 | - if: | 95 | - if: |
| 66 | not: | 96 | not: |
| @@ -70,12 +100,84 @@ allOf: · 3 unmodified lines | |||
| 70 | enum: | 100 | enum: |
| 71 | - adi,adt7461 | 101 | - adi,adt7461 |
| 72 | - adi,adt7461a | 102 | - adi,adt7461a |
| 103 | - adi,adt7481 | ||
| 73 | - ti,tmp451 | 104 | - ti,tmp451 |
| 74 | - ti,tmp461 | 105 | - ti,tmp461 |
| 75 | then: | 106 | then: |
| 76 | properties: | 107 | properties: |
| 77 | ti,extended-range-enable: false | 108 | ti,extended-range-enable: false |
| 78 | 109 | ||
| 110 | - if: | ||
| 111 | properties: | ||
| 112 | compatible: | ||
| 113 | contains: | ||
| 114 | enum: | ||
| 115 | - dallas,max6646 | ||
| 116 | - dallas,max6647 | ||
| 117 | - dallas,max6649 | ||
| 118 | - dallas,max6657 | ||
| 119 | - dallas,max6658 | ||
| 120 | - dallas,max6659 | ||
| 121 | - dallas,max6695 | ||
| 122 | - dallas,max6696 | ||
| 123 | then: | ||
| 124 | patternProperties: | ||
| 125 | "^channel@([0-2])$": | ||
| 126 | properties: | ||
| 127 | temperature-offset-millicelsius: false | ||
| 128 | |||
| 129 | - if: | ||
| 130 | properties: | ||
| 131 | compatible: | ||
| 132 | contains: | ||
| 133 | enum: | ||
| 134 | - adi,adt7461 | ||
| 135 | - adi,adt7461a | ||
| 136 | - adi,adt7481 | ||
| 137 | - onnn,nct1008 | ||
| 138 | then: | ||
| 139 | patternProperties: | ||
| 140 | "^channel@([0-2])$": | ||
| 141 | properties: | ||
| 142 | temperature-offset-millicelsius: | ||
| 143 | maximum: 127750 | ||
| 144 | |||
| 145 | - if: | ||
| 146 | properties: | ||
| 147 | compatible: | ||
| 148 | contains: | ||
| 149 | enum: | ||
| 150 | - adi,adm1032 | ||
| 151 | - dallas,max6680 | ||
| 152 | - dallas,max6681 | ||
| 153 | - gmt,g781 | ||
| 154 | - national,lm86 | ||
| 155 | - national,lm89 | ||
| 156 | - national,lm90 | ||
| 157 | - national,lm99 | ||
| 158 | - nxp,sa56004 | ||
| 159 | - winbond,w83l771 | ||
| 160 | then: | ||
| 161 | patternProperties: | ||
| 162 | "^channel@([0-2])$": | ||
| 163 | properties: | ||
| 164 | temperature-offset-millicelsius: | ||
| 165 | maximum: 127875 | ||
| 166 | |||
| 167 | - if: | ||
| 168 | properties: | ||
| 169 | compatible: | ||
| 170 | contains: | ||
| 171 | enum: | ||
| 172 | - ti,tmp451 | ||
| 173 | - ti,tmp461 | ||
| 174 | then: | ||
| 175 | patternProperties: | ||
| 176 | "^channel@([0-2])$": | ||
| 177 | properties: | ||
| 178 | temperature-offset-millicelsius: | ||
| 179 | maximum: 127937 | ||
| 180 | |||
| 79 | additionalProperties: false | 181 | additionalProperties: false |
| 80 | 182 | ||
| 81 | examples: | 183 | examples: |
| @@ -94,3 +196,32 @@ examples: · 12 unmodified lines | |||
| 94 | #thermal-sensor-cells = <1>; | 196 | #thermal-sensor-cells = <1>; |
| 95 | }; | 197 | }; |
| 96 | }; | 198 | }; |
| 199 | - | | ||
| 200 | i2c { | ||
| 201 | #address-cells = <1>; | ||
| 202 | #size-cells = <0>; | ||
| 203 | |||
| 204 | sensor@4c { | ||
| 205 | compatible = "adi,adt7481"; | ||
| 206 | reg = <0x4c>; | ||
| 207 | #address-cells = <1>; | ||
| 208 | #size-cells = <0>; | ||
| 209 | |||
| 210 | channel@0 { | ||
| 211 | reg = <0x0>; | ||
| 212 | label = "local"; | ||
| 213 | }; | ||
| 214 | |||
| 215 | channel@1 { | ||
| 216 | reg = <0x1>; | ||
| 217 | label = "front"; | ||
| 218 | temperature-offset-millicelsius = <4000>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | channel@2 { | ||
| 222 | reg = <0x2>; | ||
| 223 | label = "back"; | ||
| 224 | temperature-offset-millicelsius = <750>; | ||
| 225 | }; | ||
| 226 | }; | ||
| 227 | }; | ||
| @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" · 7 unmodified lines | |||
| 8 | title: Amlogic Meson I2C Controller | 8 | title: Amlogic Meson I2C Controller |
| 9 | 9 | ||
| 10 | maintainers: | 10 | maintainers: |
| 11 | - Neil Armstrong <narmstrong@baylibre.com> | 11 | - Neil Armstrong <neil.armstrong@linaro.org> |
| 12 | - Beniamino Galvani <b.galvani@gmail.com> | 12 | - Beniamino Galvani <b.galvani@gmail.com> |
| 13 | 13 | ||
| 14 | allOf: | 14 | allOf: |
| @@ -0,0 +1,29 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/i2c/arm,i2c-versatile.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: I2C Controller on ARM Ltd development platforms | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Linus Walleij <linus.walleij@linaro.org> | ||
| 11 | |||
| 12 | allOf: | ||
| 13 | - $ref: /schemas/i2c/i2c-controller.yaml# | ||
| 14 | |||
| 15 | properties: | ||
| 16 | compatible: | ||
| 17 | const: arm,versatile-i2c | ||
| 18 | |||
| 19 | reg: | ||
| 20 | maxItems: 1 | ||
| 21 | |||
| 22 | required: | ||
| 23 | - compatible | ||
| 24 | - reg | ||
| 25 | |||
| 26 | unevaluatedProperties: false | ||
| 27 | |||
| 28 | ... | ||
| 29 | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | * Energymicro efm32 i2c controller | ||
| 2 | |||
| 3 | Required properties : | ||
| 4 | |||
| 5 | - reg : Offset and length of the register set for the device | ||
| 6 | - compatible : should be "energymicro,efm32-i2c" | ||
| 7 | - interrupts : the interrupt number | ||
| 8 | - clocks : reference to the module clock | ||
| 9 | |||
| 10 | Recommended properties : | ||
| 11 | |||
| 12 | - clock-frequency : maximal I2C bus clock frequency in Hz. | ||
| 13 | - energymicro,location : Decides the location of the USART I/O pins. | ||
| 14 | Allowed range : [0 .. 6] | ||
| 15 | |||
| 16 | Example: | ||
| 17 | i2c0: i2c@4000a000 { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | compatible = "energymicro,efm32-i2c"; | ||
| 21 | reg = <0x4000a000 0x400>; | ||
| 22 | interrupts = <9>; | ||
| 23 | clocks = <&cmu clk_HFPERCLKI2C0>; | ||
| 24 | clock-frequency = <100000>; | ||
| 25 | energymicro,location = <3>; | ||
| 26 | |||
| 27 | eeprom@50 { | ||
| 28 | compatible = "microchip,24c02"; | ||
| 29 | reg = <0x50>; | ||
| 30 | pagesize = <16>; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| @@ -27,6 +27,7 @@ properties: · 26 unmodified lines | |||
| 27 | - const: mediatek,mt8173-i2c | 27 | - const: mediatek,mt8173-i2c |
| 28 | - const: mediatek,mt8183-i2c | 28 | - const: mediatek,mt8183-i2c |
| 29 | - const: mediatek,mt8186-i2c | 29 | - const: mediatek,mt8186-i2c |
| 30 | - const: mediatek,mt8188-i2c | ||
| 30 | - const: mediatek,mt8192-i2c | 31 | - const: mediatek,mt8192-i2c |
| 31 | - items: | 32 | - items: |
| 32 | - enum: | 33 | - enum: |
| @@ -1,23 +0,0 @@ | |||
| 1 | I2C for Nomadik based systems | ||
| 2 | |||
| 3 | Required (non-standard) properties: | ||
| 4 | - Nil | ||
| 5 | |||
| 6 | Recommended (non-standard) properties: | ||
| 7 | - clock-frequency : Maximum bus clock frequency for the device | ||
| 8 | |||
| 9 | Optional (non-standard) properties: | ||
| 10 | - Nil | ||
| 11 | |||
| 12 | Example : | ||
| 13 | |||
| 14 | i2c@80004000 { | ||
| 15 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | ||
| 16 | reg = <0x80004000 0x1000>; | ||
| 17 | interrupts = <0 21 0x4>; | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | v-i2c-supply = <&db8500_vape_reg>; | ||
| 21 | |||
| 22 | clock-frequency = <400000>; | ||
| 23 | }; | ||
| @@ -1,78 +0,0 @@ | |||
| 1 | Device tree configuration for i2c-ocores | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : "opencores,i2c-ocores" | ||
| 5 | "aeroflexgaisler,i2cmst" | ||
| 6 | "sifive,fu540-c000-i2c", "sifive,i2c0" | ||
| 7 | For Opencore based I2C IP block reimplemented in | ||
| 8 | FU540-C000 SoC. | ||
| 9 | "sifive,fu740-c000-i2c", "sifive,i2c0" | ||
| 10 | For Opencore based I2C IP block reimplemented in | ||
| 11 | FU740-C000 SoC. | ||
| 12 | Please refer to sifive-blocks-ip-versioning.txt for | ||
| 13 | additional details. | ||
| 14 | - reg : bus address start and address range size of device | ||
| 15 | - clocks : handle to the controller clock; see the note below. | ||
| 16 | Mutually exclusive with opencores,ip-clock-frequency | ||
| 17 | - opencores,ip-clock-frequency: frequency of the controller clock in Hz; | ||
| 18 | see the note below. Mutually exclusive with clocks | ||
| 19 | - #address-cells : should be <1> | ||
| 20 | - #size-cells : should be <0> | ||
| 21 | |||
| 22 | Optional properties: | ||
| 23 | - interrupts : interrupt number. | ||
| 24 | - clock-frequency : frequency of bus clock in Hz; see the note below. | ||
| 25 | Defaults to 100 KHz when the property is not specified | ||
| 26 | - reg-shift : device register offsets are shifted by this value | ||
| 27 | - reg-io-width : io register width in bytes (1, 2 or 4) | ||
| 28 | - regstep : deprecated, use reg-shift above | ||
| 29 | |||
| 30 | Note | ||
| 31 | clock-frequency property is meant to control the bus frequency for i2c bus | ||
| 32 | drivers, but it was incorrectly used to specify i2c controller input clock | ||
| 33 | frequency. So the following rules are set to fix this situation: | ||
| 34 | - if clock-frequency is present and neither opencores,ip-clock-frequency nor | ||
| 35 | clocks are, then clock-frequency specifies i2c controller clock frequency. | ||
| 36 | This is to keep backwards compatibility with setups using old DTB. i2c bus | ||
| 37 | frequency is fixed at 100 KHz. | ||
| 38 | - if clocks is present it specifies i2c controller clock. clock-frequency | ||
| 39 | property specifies i2c bus frequency. | ||
| 40 | - if opencores,ip-clock-frequency is present it specifies i2c controller | ||
| 41 | clock frequency. clock-frequency property specifies i2c bus frequency. | ||
| 42 | |||
| 43 | Examples: | ||
| 44 | |||
| 45 | i2c0: ocores@a0000000 { | ||
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | compatible = "opencores,i2c-ocores"; | ||
| 49 | reg = <0xa0000000 0x8>; | ||
| 50 | interrupts = <10>; | ||
| 51 | opencores,ip-clock-frequency = <20000000>; | ||
| 52 | |||
| 53 | reg-shift = <0>; /* 8 bit registers */ | ||
| 54 | reg-io-width = <1>; /* 8 bit read/write */ | ||
| 55 | |||
| 56 | dummy@60 { | ||
| 57 | compatible = "dummy"; | ||
| 58 | reg = <0x60>; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | or | ||
| 62 | i2c0: ocores@a0000000 { | ||
| 63 | #address-cells = <1>; | ||
| 64 | #size-cells = <0>; | ||
| 65 | compatible = "opencores,i2c-ocores"; | ||
| 66 | reg = <0xa0000000 0x8>; | ||
| 67 | interrupts = <10>; | ||
| 68 | clocks = <&osc>; | ||
| 69 | clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ | ||
| 70 | |||
| 71 | reg-shift = <0>; /* 8 bit registers */ | ||
| 72 | reg-io-width = <1>; /* 8 bit read/write */ | ||
| 73 | |||
| 74 | dummy@60 { | ||
| 75 | compatible = "dummy"; | ||
| 76 | reg = <0x60>; | ||
| 77 | }; | ||
| 78 | }; | ||
| @@ -1,95 +0,0 @@ | |||
| 1 | Qualcomm Camera Control Interface (CCI) I2C controller | ||
| 2 | |||
| 3 | PROPERTIES: | ||
| 4 | |||
| 5 | - compatible: | ||
| 6 | Usage: required | ||
| 7 | Value type: <string> | ||
| 8 | Definition: must be one of: | ||
| 9 | "qcom,msm8916-cci" | ||
| 10 | "qcom,msm8996-cci" | ||
| 11 | "qcom,sdm845-cci" | ||
| 12 | "qcom,sm8250-cci" | ||
| 13 | "qcom,sm8450-cci" | ||
| 14 | |||
| 15 | - reg | ||
| 16 | Usage: required | ||
| 17 | Value type: <prop-encoded-array> | ||
| 18 | Definition: base address CCI I2C controller and length of memory | ||
| 19 | mapped region. | ||
| 20 | |||
| 21 | - interrupts: | ||
| 22 | Usage: required | ||
| 23 | Value type: <prop-encoded-array> | ||
| 24 | Definition: specifies the CCI I2C interrupt. The format of the | ||
| 25 | specifier is defined by the binding document describing | ||
| 26 | the node's interrupt parent. | ||
| 27 | |||
| 28 | - clocks: | ||
| 29 | Usage: required | ||
| 30 | Value type: <prop-encoded-array> | ||
| 31 | Definition: a list of phandle, should contain an entry for each | ||
| 32 | entries in clock-names. | ||
| 33 | |||
| 34 | - clock-names | ||
| 35 | Usage: required | ||
| 36 | Value type: <string> | ||
| 37 | Definition: a list of clock names, must include "cci" clock. | ||
| 38 | |||
| 39 | - power-domains | ||
| 40 | Usage: required for "qcom,msm8996-cci" | ||
| 41 | Value type: <prop-encoded-array> | ||
| 42 | Definition: | ||
| 43 | |||
| 44 | SUBNODES: | ||
| 45 | |||
| 46 | The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996, | ||
| 47 | sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and | ||
| 48 | "i2c-bus@1". | ||
| 49 | |||
| 50 | PROPERTIES: | ||
| 51 | |||
| 52 | - reg: | ||
| 53 | Usage: required | ||
| 54 | Value type: <u32> | ||
| 55 | Definition: Index of the CCI bus/master | ||
| 56 | |||
| 57 | - clock-frequency: | ||
| 58 | Usage: optional | ||
| 59 | Value type: <u32> | ||
| 60 | Definition: Desired I2C bus clock frequency in Hz, defaults to 100 | ||
| 61 | kHz if omitted. | ||
| 62 | |||
| 63 | Example: | ||
| 64 | |||
| 65 | cci@a0c000 { | ||
| 66 | compatible = "qcom,msm8996-cci"; | ||
| 67 | #address-cells = <1>; | ||
| 68 | #size-cells = <0>; | ||
| 69 | reg = <0xa0c000 0x1000>; | ||
| 70 | interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; | ||
| 71 | clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, | ||
| 72 | <&mmcc CAMSS_TOP_AHB_CLK>, | ||
| 73 | <&mmcc CAMSS_CCI_AHB_CLK>, | ||
| 74 | <&mmcc CAMSS_CCI_CLK>, | ||
| 75 | <&mmcc CAMSS_AHB_CLK>; | ||
| 76 | clock-names = "mmss_mmagic_ahb", | ||
| 77 | "camss_top_ahb", | ||
| 78 | "cci_ahb", | ||
| 79 | "cci", | ||
| 80 | "camss_ahb"; | ||
| 81 | |||
| 82 | i2c-bus@0 { | ||
| 83 | reg = <0>; | ||
| 84 | clock-frequency = <400000>; | ||
| 85 | #address-cells = <1>; | ||
| 86 | #size-cells = <0>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | i2c-bus@1 { | ||
| 90 | reg = <1>; | ||
| 91 | clock-frequency = <400000>; | ||
| 92 | #address-cells = <1>; | ||
| 93 | #size-cells = <0>; | ||
| 94 | }; | ||
| 95 | }; | ||
| @@ -37,6 +37,8 @@ properties: · 36 unmodified lines | |||
| 37 | - rockchip,rk3308-i2c | 37 | - rockchip,rk3308-i2c |
| 38 | - rockchip,rk3328-i2c | 38 | - rockchip,rk3328-i2c |
| 39 | - rockchip,rk3568-i2c | 39 | - rockchip,rk3568-i2c |
| 40 | - rockchip,rk3588-i2c | ||
| 41 | - rockchip,rv1126-i2c | ||
| 40 | - const: rockchip,rk3399-i2c | 42 | - const: rockchip,rk3399-i2c |
| 41 | 43 | ||
| 42 | reg: | 44 | reg: |
| @@ -1,10 +0,0 @@ | |||
| 1 | i2c Controller on ARM Versatile platform: | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : Must be "arm,versatile-i2c"; | ||
| 5 | - reg | ||
| 6 | - #address-cells = <1>; | ||
| 7 | - #size-cells = <0>; | ||
| 8 | |||
| 9 | Optional properties: | ||
| 10 | - Child nodes conforming to i2c bus binding | ||
| @@ -21,10 +21,18 @@ properties: · 20 unmodified lines | |||
| 21 | - enum: | 21 | - enum: |
| 22 | - allwinner,sun8i-a23-i2c | 22 | - allwinner,sun8i-a23-i2c |
| 23 | - allwinner,sun8i-a83t-i2c | 23 | - allwinner,sun8i-a83t-i2c |
| 24 | - allwinner,sun8i-v536-i2c | ||
| 24 | - allwinner,sun50i-a64-i2c | 25 | - allwinner,sun50i-a64-i2c |
| 25 | - allwinner,sun50i-a100-i2c | ||
| 26 | - allwinner,sun50i-h6-i2c | 26 | - allwinner,sun50i-h6-i2c |
| 27 | - const: allwinner,sun6i-a31-i2c | ||
| 28 | - description: Allwinner SoCs with offload support | ||
| 29 | items: | ||
| 30 | - enum: | ||
| 31 | - allwinner,sun20i-d1-i2c | ||
| 32 | - allwinner,sun50i-a100-i2c | ||
| 27 | - allwinner,sun50i-h616-i2c | 33 | - allwinner,sun50i-h616-i2c |
| 34 | - allwinner,sun50i-r329-i2c | ||
| 35 | - const: allwinner,sun8i-v536-i2c | ||
| 28 | - const: allwinner,sun6i-a31-i2c | 36 | - const: allwinner,sun6i-a31-i2c |
| 29 | - const: marvell,mv64xxx-i2c | 37 | - const: marvell,mv64xxx-i2c |
| 30 | - const: marvell,mv78230-i2c | 38 | - const: marvell,mv78230-i2c |
| @@ -7,17 +7,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: nuvoton NPCM7XX I2C Controller Device Tree Bindings | 7 | title: nuvoton NPCM7XX I2C Controller Device Tree Bindings |
| 8 | 8 | ||
| 9 | description: | | 9 | description: | |
| 10 | The NPCM750x includes sixteen I2C bus controllers. All Controllers support | 10 | I2C bus controllers of the NPCM series support both master and |
| 11 | both master and slave mode. Each controller can switch between master and slave | 11 | slave mode. Each controller can switch between master and slave at run time |
| 12 | at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and | 12 | (i.e. IPMB mode). HW FIFO for TX and RX are supported. |
| 13 | RX. | ||
| 14 | 13 | ||
| 15 | maintainers: | 14 | maintainers: |
| 16 | - Tali Perry <tali.perry1@gmail.com> | 15 | - Tali Perry <tali.perry1@gmail.com> |
| 17 | 16 | ||
| 18 | properties: | 17 | properties: |
| 19 | compatible: | 18 | compatible: |
| 20 | const: nuvoton,npcm750-i2c | 19 | enum: |
| 20 | - nuvoton,npcm750-i2c | ||
| 21 | - nuvoton,npcm845-i2c | ||
| 21 | 22 | ||
| 22 | reg: | 23 | reg: |
| 23 | maxItems: 1 | 24 | maxItems: 1 |
| @@ -36,6 +37,10 @@ properties: · 12 unmodified lines | |||
| 36 | default: 100000 | 37 | default: 100000 |
| 37 | enum: [100000, 400000, 1000000] | 38 | enum: [100000, 400000, 1000000] |
| 38 | 39 | ||
| 40 | nuvoton,sys-mgr: | ||
| 41 | $ref: /schemas/types.yaml#/definitions/phandle | ||
| 42 | description: The phandle of system manager register node. | ||
| 43 | |||
| 39 | required: | 44 | required: |
| 40 | - compatible | 45 | - compatible |
| 41 | - reg | 46 | - reg |
| @@ -44,6 +49,15 @@ required: · 2 unmodified lines | |||
| 44 | 49 | ||
| 45 | allOf: | 50 | allOf: |
| 46 | - $ref: /schemas/i2c/i2c-controller.yaml# | 51 | - $ref: /schemas/i2c/i2c-controller.yaml# |
| 52 | - if: | ||
| 53 | properties: | ||
| 54 | compatible: | ||
| 55 | contains: | ||
| 56 | const: nuvoton,npcm845-i2c | ||
| 57 | |||
| 58 | then: | ||
| 59 | required: | ||
| 60 | - nuvoton,sys-mgr | ||
| 47 | 61 | ||
| 48 | unevaluatedProperties: false | 62 | unevaluatedProperties: false |
| 49 | 63 | ||
| @@ -57,6 +71,7 @@ examples: · 7 unmodified lines | |||
| 57 | clock-frequency = <100000>; | 71 | clock-frequency = <100000>; |
| 58 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | 72 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | compatible = "nuvoton,npcm750-i2c"; | 73 | compatible = "nuvoton,npcm750-i2c"; |
| 74 | nuvoton,sys-mgr = <&gcr>; | ||
| 60 | }; | 75 | }; |
| 61 | 76 | ||
| 62 | ... | 77 | ... |
| @@ -0,0 +1,113 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: OpenCores I2C controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Peter Korsgaard <peter@korsgaard.com> | ||
| 11 | - Andrew Lunn <andrew@lunn.ch> | ||
| 12 | |||
| 13 | allOf: | ||
| 14 | - $ref: /schemas/i2c/i2c-controller.yaml# | ||
| 15 | |||
| 16 | properties: | ||
| 17 | compatible: | ||
| 18 | oneOf: | ||
| 19 | - items: | ||
| 20 | - enum: | ||
| 21 | - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC | ||
| 22 | - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC | ||
| 23 | - const: sifive,i2c0 | ||
| 24 | - enum: | ||
| 25 | - opencores,i2c-ocores | ||
| 26 | - aeroflexgaisler,i2cmst | ||
| 27 | |||
| 28 | reg: | ||
| 29 | maxItems: 1 | ||
| 30 | |||
| 31 | interrupts: | ||
| 32 | maxItems: 1 | ||
| 33 | |||
| 34 | clocks: | ||
| 35 | maxItems: 1 | ||
| 36 | |||
| 37 | clock-frequency: | ||
| 38 | description: | | ||
| 39 | clock-frequency property is meant to control the bus frequency for i2c bus | ||
| 40 | drivers, but it was incorrectly used to specify i2c controller input clock | ||
| 41 | frequency. So the following rules are set to fix this situation: | ||
| 42 | - if clock-frequency is present and neither opencores,ip-clock-frequency nor | ||
| 43 | clocks are, then clock-frequency specifies i2c controller clock frequency. | ||
| 44 | This is to keep backwards compatibility with setups using old DTB. i2c bus | ||
| 45 | frequency is fixed at 100 KHz. | ||
| 46 | - if clocks is present it specifies i2c controller clock. clock-frequency | ||
| 47 | property specifies i2c bus frequency. | ||
| 48 | - if opencores,ip-clock-frequency is present it specifies i2c controller | ||
| 49 | clock frequency. clock-frequency property specifies i2c bus frequency. | ||
| 50 | default: 100000 | ||
| 51 | |||
| 52 | reg-io-width: | ||
| 53 | description: | | ||
| 54 | io register width in bytes | ||
| 55 | enum: [1, 2, 4] | ||
| 56 | |||
| 57 | reg-shift: | ||
| 58 | description: | | ||
| 59 | device register offsets are shifted by this value | ||
| 60 | default: 0 | ||
| 61 | |||
| 62 | regstep: | ||
| 63 | description: | | ||
| 64 | deprecated, use reg-shift above | ||
| 65 | deprecated: true | ||
| 66 | |||
| 67 | opencores,ip-clock-frequency: | ||
| 68 | $ref: /schemas/types.yaml#/definitions/uint32 | ||
| 69 | description: | | ||
| 70 | Frequency of the controller clock in Hz. Mutually exclusive with clocks. | ||
| 71 | See the note above. | ||
| 72 | |||
| 73 | required: | ||
| 74 | - compatible | ||
| 75 | - reg | ||
| 76 | - "#address-cells" | ||
| 77 | - "#size-cells" | ||
| 78 | |||
| 79 | oneOf: | ||
| 80 | - required: | ||
| 81 | - opencores,ip-clock-frequency | ||
| 82 | - required: | ||
| 83 | - clocks | ||
| 84 | |||
| 85 | unevaluatedProperties: false | ||
| 86 | |||
| 87 | examples: | ||
| 88 | - | | ||
| 89 | i2c@a0000000 { | ||
| 90 | compatible = "opencores,i2c-ocores"; | ||
| 91 | reg = <0xa0000000 0x8>; | ||
| 92 | #address-cells = <1>; | ||
| 93 | #size-cells = <0>; | ||
| 94 | interrupts = <10>; | ||
| 95 | opencores,ip-clock-frequency = <20000000>; | ||
| 96 | |||
| 97 | reg-shift = <0>; /* 8 bit registers */ | ||
| 98 | reg-io-width = <1>; /* 8 bit read/write */ | ||
| 99 | }; | ||
| 100 | |||
| 101 | i2c@b0000000 { | ||
| 102 | compatible = "opencores,i2c-ocores"; | ||
| 103 | reg = <0xa0000000 0x8>; | ||
| 104 | #address-cells = <1>; | ||
| 105 | #size-cells = <0>; | ||
| 106 | interrupts = <10>; | ||
| 107 | clocks = <&osc>; | ||
| 108 | clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ | ||
| 109 | |||
| 110 | reg-shift = <0>; /* 8 bit registers */ | ||
| 111 | reg-io-width = <1>; /* 8 bit read/write */ | ||
| 112 | }; | ||
| 113 | ... | ||
| @@ -0,0 +1,242 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Qualcomm Camera Control Interface (CCI) I2C controller | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Loic Poulain <loic.poulain@linaro.org> | ||
| 11 | - Robert Foss <robert.foss@linaro.org> | ||
| 12 | |||
| 13 | properties: | ||
| 14 | compatible: | ||
| 15 | enum: | ||
| 16 | - qcom,msm8916-cci | ||
| 17 | - qcom,msm8974-cci | ||
| 18 | - qcom,msm8996-cci | ||
| 19 | - qcom,sdm845-cci | ||
| 20 | - qcom,sm8250-cci | ||
| 21 | - qcom,sm8450-cci | ||
| 22 | |||
| 23 | "#address-cells": | ||
| 24 | const: 1 | ||
| 25 | |||
| 26 | "#size-cells": | ||
| 27 | const: 0 | ||
| 28 | |||
| 29 | clocks: | ||
| 30 | minItems: 4 | ||
| 31 | maxItems: 6 | ||
| 32 | |||
| 33 | clock-names: | ||
| 34 | minItems: 4 | ||
| 35 | maxItems: 6 | ||
| 36 | |||
| 37 | interrupts: | ||
| 38 | maxItems: 1 | ||
| 39 | |||
| 40 | power-domains: | ||
| 41 | maxItems: 1 | ||
| 42 | |||
| 43 | reg: | ||
| 44 | maxItems: 1 | ||
| 45 | |||
| 46 | patternProperties: | ||
| 47 | "^i2c-bus@[01]$": | ||
| 48 | $ref: /schemas/i2c/i2c-controller.yaml# | ||
| 49 | unevaluatedProperties: false | ||
| 50 | |||
| 51 | properties: | ||
| 52 | reg: | ||
| 53 | maxItems: 1 | ||
| 54 | |||
| 55 | clock-frequency: | ||
| 56 | default: 100000 | ||
| 57 | |||
| 58 | required: | ||
| 59 | - compatible | ||
| 60 | - clock-names | ||
| 61 | - clocks | ||
| 62 | - interrupts | ||
| 63 | - reg | ||
| 64 | |||
| 65 | allOf: | ||
| 66 | - if: | ||
| 67 | properties: | ||
| 68 | compatible: | ||
| 69 | contains: | ||
| 70 | enum: | ||
| 71 | - qcom,msm8996-cci | ||
| 72 | then: | ||
| 73 | required: | ||
| 74 | - power-domains | ||
| 75 | |||
| 76 | - if: | ||
| 77 | properties: | ||
| 78 | compatible: | ||
| 79 | contains: | ||
| 80 | enum: | ||
| 81 | - qcom,msm8916-cci | ||
| 82 | then: | ||
| 83 | properties: | ||
| 84 | i2c-bus@1: false | ||
| 85 | |||
| 86 | - if: | ||
| 87 | properties: | ||
| 88 | compatible: | ||
| 89 | contains: | ||
| 90 | enum: | ||
| 91 | - qcom,msm8916-cci | ||
| 92 | - qcom,msm8996-cci | ||
| 93 | then: | ||
| 94 | properties: | ||
| 95 | clocks: | ||
| 96 | maxItems: 4 | ||
| 97 | clock-names: | ||
| 98 | items: | ||
| 99 | - const: camss_top_ahb | ||
| 100 | - const: cci_ahb | ||
| 101 | - const: cci | ||
| 102 | - const: camss_ahb | ||
| 103 | |||
| 104 | - if: | ||
| 105 | properties: | ||
| 106 | compatible: | ||
| 107 | contains: | ||
| 108 | enum: | ||
| 109 | - qcom,sdm845-cci | ||
| 110 | then: | ||
| 111 | properties: | ||
| 112 | clocks: | ||
| 113 | minItems: 6 | ||
| 114 | clock-names: | ||
| 115 | items: | ||
| 116 | - const: camnoc_axi | ||
| 117 | - const: soc_ahb | ||
| 118 | - const: slow_ahb_src | ||
| 119 | - const: cpas_ahb | ||
| 120 | - const: cci | ||
| 121 | - const: cci_src | ||
| 122 | |||
| 123 | - if: | ||
| 124 | properties: | ||
| 125 | compatible: | ||
| 126 | contains: | ||
| 127 | enum: | ||
| 128 | - qcom,sm8250-cci | ||
| 129 | then: | ||
| 130 | properties: | ||
| 131 | clocks: | ||
| 132 | minItems: 5 | ||
| 133 | maxItems: 5 | ||
| 134 | clock-names: | ||
| 135 | items: | ||
| 136 | - const: camnoc_axi | ||
| 137 | - const: slow_ahb_src | ||
| 138 | - const: cpas_ahb | ||
| 139 | - const: cci | ||
| 140 | - const: cci_src | ||
| 141 | |||
| 142 | additionalProperties: false | ||
| 143 | |||
| 144 | examples: | ||
| 145 | - | | ||
| 146 | #include <dt-bindings/clock/qcom,camcc-sdm845.h> | ||
| 147 | #include <dt-bindings/gpio/gpio.h> | ||
| 148 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 149 | |||
| 150 | cci@ac4a000 { | ||
| 151 | reg = <0x0ac4a000 0x4000>; | ||
| 152 | compatible = "qcom,sdm845-cci"; | ||
| 153 | #address-cells = <1>; | ||
| 154 | #size-cells = <0>; | ||
| 155 | |||
| 156 | interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; | ||
| 157 | power-domains = <&clock_camcc TITAN_TOP_GDSC>; | ||
| 158 | |||
| 159 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, | ||
| 160 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, | ||
| 161 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, | ||
| 162 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, | ||
| 163 | <&clock_camcc CAM_CC_CCI_CLK>, | ||
| 164 | <&clock_camcc CAM_CC_CCI_CLK_SRC>; | ||
| 165 | clock-names = "camnoc_axi", | ||
| 166 | "soc_ahb", | ||
| 167 | "slow_ahb_src", | ||
| 168 | "cpas_ahb", | ||
| 169 | "cci", | ||
| 170 | "cci_src"; | ||
| 171 | |||
| 172 | assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, | ||
| 173 | <&clock_camcc CAM_CC_CCI_CLK>; | ||
| 174 | assigned-clock-rates = <80000000>, | ||
| 175 | <37500000>; | ||
| 176 | |||
| 177 | pinctrl-names = "default", "sleep"; | ||
| 178 | pinctrl-0 = <&cci0_default &cci1_default>; | ||
| 179 | pinctrl-1 = <&cci0_sleep &cci1_sleep>; | ||
| 180 | |||
| 181 | i2c-bus@0 { | ||
| 182 | reg = <0>; | ||
| 183 | clock-frequency = <1000000>; | ||
| 184 | #address-cells = <1>; | ||
| 185 | #size-cells = <0>; | ||
| 186 | |||
| 187 | camera@10 { | ||
| 188 | compatible = "ovti,ov8856"; | ||
| 189 | reg = <0x10>; | ||
| 190 | |||
| 191 | reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; | ||
| 192 | pinctrl-names = "default"; | ||
| 193 | pinctrl-0 = <&cam0_default>; | ||
| 194 | |||
| 195 | clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; | ||
| 196 | clock-names = "xvclk"; | ||
| 197 | clock-frequency = <19200000>; | ||
| 198 | |||
| 199 | dovdd-supply = <&vreg_lvs1a_1p8>; | ||
| 200 | avdd-supply = <&cam0_avdd_2v8>; | ||
| 201 | dvdd-supply = <&cam0_dvdd_1v2>; | ||
| 202 | |||
| 203 | port { | ||
| 204 | ov8856_ep: endpoint { | ||
| 205 | link-frequencies = /bits/ 64 <360000000 180000000>; | ||
| 206 | data-lanes = <1 2 3 4>; | ||
| 207 | remote-endpoint = <&csiphy0_ep>; | ||
| 208 | }; | ||
| 209 | }; | ||
| 210 | }; | ||
| 211 | }; | ||
| 212 | |||
| 213 | cci_i2c1: i2c-bus@1 { | ||
| 214 | reg = <1>; | ||
| 215 | clock-frequency = <1000000>; | ||
| 216 | #address-cells = <1>; | ||
| 217 | #size-cells = <0>; | ||
| 218 | |||
| 219 | camera@60 { | ||
| 220 | compatible = "ovti,ov7251"; | ||
| 221 | reg = <0x60>; | ||
| 222 | |||
| 223 | enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; | ||
| 224 | pinctrl-names = "default"; | ||
| 225 | pinctrl-0 = <&cam3_default>; | ||
| 226 | |||
| 227 | clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; | ||
| 228 | clock-names = "xclk"; | ||
| 229 | clock-frequency = <24000000>; | ||
| 230 | |||
| 231 | vdddo-supply = <&vreg_lvs1a_1p8>; | ||
| 232 | vdda-supply = <&cam3_avdd_2v8>; | ||
| 233 | |||
| 234 | port { | ||
| 235 | ov7251_ep: endpoint { | ||
| 236 | data-lanes = <0 1>; | ||
| 237 | remote-endpoint = <&csiphy3_ep>; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | }; | ||
| 241 | }; | ||
| 242 | }; | ||
| @@ -60,6 +60,9 @@ properties: · 59 unmodified lines | |||
| 60 | power-domains: | 60 | power-domains: |
| 61 | maxItems: 1 | 61 | maxItems: 1 |
| 62 | 62 | ||
| 63 | resets: | ||
| 64 | maxItems: 1 | ||
| 65 | |||
| 63 | required: | 66 | required: |
| 64 | - compatible | 67 | - compatible |
| 65 | - reg | 68 | - reg |
| @@ -0,0 +1,80 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/i2c/renesas,rzv2m.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: Renesas RZ/V2M I2C Bus Interface | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Phil Edworthy <phil.edworthy@renesas.com> | ||
| 11 | |||
| 12 | allOf: | ||
| 13 | - $ref: /schemas/i2c/i2c-controller.yaml# | ||
| 14 | |||
| 15 | properties: | ||
| 16 | compatible: | ||
| 17 | items: | ||
| 18 | - enum: | ||
| 19 | - renesas,i2c-r9a09g011 # RZ/V2M | ||
| 20 | - const: renesas,rzv2m-i2c | ||
| 21 | |||
| 22 | reg: | ||
| 23 | maxItems: 1 | ||
| 24 | |||
| 25 | interrupts: | ||
| 26 | items: | ||
| 27 | - description: Data transmission/reception interrupt | ||
| 28 | - description: Status interrupt | ||
| 29 | |||
| 30 | interrupt-names: | ||
| 31 | items: | ||
| 32 | - const: tia | ||
| 33 | - const: tis | ||
| 34 | |||
| 35 | clock-frequency: | ||
| 36 | default: 100000 | ||
| 37 | enum: [ 100000, 400000 ] | ||
| 38 | description: | ||
| 39 | Desired I2C bus clock frequency in Hz. | ||
| 40 | |||
| 41 | clocks: | ||
| 42 | maxItems: 1 | ||
| 43 | |||
| 44 | power-domains: | ||
| 45 | maxItems: 1 | ||
| 46 | |||
| 47 | resets: | ||
| 48 | maxItems: 1 | ||
| 49 | |||
| 50 | required: | ||
| 51 | - compatible | ||
| 52 | - reg | ||
| 53 | - interrupts | ||
| 54 | - interrupt-names | ||
| 55 | - clocks | ||
| 56 | - power-domains | ||
| 57 | - resets | ||
| 58 | - '#address-cells' | ||
| 59 | - '#size-cells' | ||
| 60 | |||
| 61 | unevaluatedProperties: false | ||
| 62 | |||
| 63 | examples: | ||
| 64 | - | | ||
| 65 | #include <dt-bindings/clock/r9a09g011-cpg.h> | ||
| 66 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 67 | |||
| 68 | i2c0: i2c@a4030000 { | ||
| 69 | compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; | ||
| 70 | reg = <0xa4030000 0x80>; | ||
| 71 | interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, | ||
| 72 | <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; | ||
| 73 | interrupt-names = "tia", "tis"; | ||
| 74 | clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; | ||
| 75 | resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; | ||
| 76 | power-domains = <&cpg>; | ||
| 77 | clock-frequency = <100000>; | ||
| 78 | #address-cells = <1>; | ||
| 79 | #size-cells = <0>; | ||
| 80 | }; | ||
| @@ -0,0 +1,115 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: ST Microelectronics Nomadik I2C Bindings | ||
| 8 | |||
| 9 | description: The Nomadik I2C host controller began its life in the ST | ||
| 10 | Microelectronics STn8800 SoC, and was then inherited into STn8810 and | ||
| 11 | STn8815. It was part of the prototype STn8500 which then became ST-Ericsson | ||
| 12 | DB8500 after the merge of these two companies wireless divisions. | ||
| 13 | |||
| 14 | maintainers: | ||
| 15 | - Linus Walleij <linus.walleij@linaro.org> | ||
| 16 | |||
| 17 | allOf: | ||
| 18 | - $ref: /schemas/i2c/i2c-controller.yaml# | ||
| 19 | |||
| 20 | # Need a custom select here or 'arm,primecell' will match on lots of nodes | ||
| 21 | select: | ||
| 22 | properties: | ||
| 23 | compatible: | ||
| 24 | contains: | ||
| 25 | enum: | ||
| 26 | - st,nomadik-i2c | ||
| 27 | required: | ||
| 28 | - compatible | ||
| 29 | |||
| 30 | properties: | ||
| 31 | compatible: | ||
| 32 | oneOf: | ||
| 33 | # The variant found in STn8815 | ||
| 34 | - items: | ||
| 35 | - const: st,nomadik-i2c | ||
| 36 | - const: arm,primecell | ||
| 37 | # The variant found in DB8500 | ||
| 38 | - items: | ||
| 39 | - const: stericsson,db8500-i2c | ||
| 40 | - const: st,nomadik-i2c | ||
| 41 | - const: arm,primecell | ||
| 42 | |||
| 43 | reg: | ||
| 44 | maxItems: 1 | ||
| 45 | |||
| 46 | interrupts: | ||
| 47 | maxItems: 1 | ||
| 48 | |||
| 49 | clocks: | ||
| 50 | maxItems: 2 | ||
| 51 | |||
| 52 | clock-names: | ||
| 53 | oneOf: | ||
| 54 | # Clock name in STn8815 | ||
| 55 | - items: | ||
| 56 | - const: mclk | ||
| 57 | - const: apb_pclk | ||
| 58 | # Clock name in DB8500 | ||
| 59 | - items: | ||
| 60 | - const: i2cclk | ||
| 61 | - const: apb_pclk | ||
| 62 | |||
| 63 | power-domains: | ||
| 64 | maxItems: 1 | ||
| 65 | |||
| 66 | resets: | ||
| 67 | maxItems: 1 | ||
| 68 | |||
| 69 | clock-frequency: | ||
| 70 | minimum: 1 | ||
| 71 | maximum: 400000 | ||
| 72 | |||
| 73 | required: | ||
| 74 | - compatible | ||
| 75 | - reg | ||
| 76 | - interrupts | ||
| 77 | - clocks | ||
| 78 | - clock-names | ||
| 79 | |||
| 80 | unevaluatedProperties: false | ||
| 81 | |||
| 82 | examples: | ||
| 83 | - | | ||
| 84 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 85 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 86 | #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> | ||
| 87 | #include <dt-bindings/arm/ux500_pm_domains.h> | ||
| 88 | i2c@80004000 { | ||
| 89 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; | ||
| 90 | reg = <0x80004000 0x1000>; | ||
| 91 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | ||
| 92 | |||
| 93 | #address-cells = <1>; | ||
| 94 | #size-cells = <0>; | ||
| 95 | |||
| 96 | clock-frequency = <400000>; | ||
| 97 | clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; | ||
| 98 | clock-names = "i2cclk", "apb_pclk"; | ||
| 99 | power-domains = <&pm_domains DOMAIN_VAPE>; | ||
| 100 | resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; | ||
| 101 | }; | ||
| 102 | |||
| 103 | i2c@101f8000 { | ||
| 104 | compatible = "st,nomadik-i2c", "arm,primecell"; | ||
| 105 | reg = <0x101f8000 0x1000>; | ||
| 106 | interrupt-parent = <&vica>; | ||
| 107 | interrupts = <20>; | ||
| 108 | clock-frequency = <100000>; | ||
| 109 | #address-cells = <1>; | ||
| 110 | #size-cells = <0>; | ||
| 111 | clocks = <&i2c0clk>, <&pclki2c0>; | ||
| 112 | clock-names = "mclk", "apb_pclk"; | ||
| 113 | }; | ||
| 114 | |||
| 115 | ... | ||
| @@ -17,6 +17,7 @@ allOf: · 16 unmodified lines | |||
| 17 | contains: | 17 | contains: |
| 18 | enum: | 18 | enum: |
| 19 | - st,stm32f7-i2c | 19 | - st,stm32f7-i2c |
| 20 | - st,stm32mp13-i2c | ||
| 20 | - st,stm32mp15-i2c | 21 | - st,stm32mp15-i2c |
| 21 | then: | 22 | then: |
| 22 | properties: | 23 | properties: |
| @@ -45,6 +46,7 @@ properties: · 22 unmodified lines | |||
| 45 | enum: | 46 | enum: |
| 46 | - st,stm32f4-i2c | 47 | - st,stm32f4-i2c |
| 47 | - st,stm32f7-i2c | 48 | - st,stm32f7-i2c |
| 49 | - st,stm32mp13-i2c | ||
| 48 | - st,stm32mp15-i2c | 50 | - st,stm32mp15-i2c |
| 49 | 51 | ||
| 50 | reg: | 52 | reg: |
| @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: ADIS16240 Programmable Impact Sensor and Recorder driver | 7 | title: ADIS16240 Programmable Impact Sensor and Recorder driver |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Alexandru Ardelean <alexandru.ardelean@analog.com> | 10 | - Alexandru Tachici <alexandru.tachici@analog.com> |
| 11 | 11 | ||
| 12 | description: | | 12 | description: | |
| 13 | ADIS16240 Programmable Impact Sensor and Recorder driver that supports | 13 | ADIS16240 Programmable Impact Sensor and Recorder driver that supports |
| @@ -55,7 +55,7 @@ examples: · 54 unmodified lines | |||
| 55 | /* Example for a I2C device node */ | 55 | /* Example for a I2C device node */ |
| 56 | accelerometer@2a { | 56 | accelerometer@2a { |
| 57 | compatible = "adi,adxl345"; | 57 | compatible = "adi,adxl345"; |
| 58 | reg = <0x53>; | 58 | reg = <0x2a>; |
| 59 | interrupt-parent = <&gpio0>; | 59 | interrupt-parent = <&gpio0>; |
| 60 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; | 60 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; |
| 61 | }; | 61 | }; |
| @@ -17,7 +17,9 @@ description: | · 16 unmodified lines | |||
| 17 | properties: | 17 | properties: |
| 18 | compatible: | 18 | compatible: |
| 19 | enum: | 19 | enum: |
| 20 | - bosch,bmi085-accel | ||
| 20 | - bosch,bmi088-accel | 21 | - bosch,bmi088-accel |
| 22 | - bosch,bmi090l-accel | ||
| 21 | 23 | ||
| 22 | reg: | 24 | reg: |
| 23 | maxItems: 1 | 25 | maxItems: 1 |
| @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: Freescale MMA7455 and MMA7456 three axis accelerometers | 7 | title: Freescale MMA7455 and MMA7456 three axis accelerometers |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Joachim Eastwood <manabian@gmail.com> | ||
| 11 | - Jonathan Cameron <jic23@kernel.org> | 10 | - Jonathan Cameron <jic23@kernel.org> |
| 12 | 11 | ||
| 13 | description: | 12 | description: |
| @@ -17,6 +17,7 @@ properties: · 16 unmodified lines | |||
| 17 | compatible: | 17 | compatible: |
| 18 | enum: | 18 | enum: |
| 19 | - murata,sca3300 | 19 | - murata,sca3300 |
| 20 | - murata,scl3300 | ||
| 20 | 21 | ||
| 21 | reg: | 22 | reg: |
| 22 | maxItems: 1 | 23 | maxItems: 1 |
| @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: Analog Devices AD7091R5 4-Channel 12-Bit ADC | 7 | title: Analog Devices AD7091R5 4-Channel 12-Bit ADC |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Beniamin Bia <beniamin.bia@analog.com> | 10 | - Michael Hennerich <michael.hennerich@analog.com> |
| 11 | 11 | ||
| 12 | description: | | 12 | description: | |
| 13 | Analog Devices AD7091R5 4-Channel 12-Bit ADC | 13 | Analog Devices AD7091R5 4-Channel 12-Bit ADC |
| @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines | |||
| 7 | title: Analog Devices AD7606 Simultaneous Sampling ADC | 7 | title: Analog Devices AD7606 Simultaneous Sampling ADC |
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Beniamin Bia <beniamin.bia@analog.com> | 10 | - Michael Hennerich <michael.hennerich@analog.com> |
| 11 | - Stefan Popa <stefan.popa@analog.com> | ||
| 12 | 11 | ||
| 13 | description: | | 12 | description: | |
| 14 | Analog Devices AD7606 Simultaneous Sampling ADC | 13 | Analog Devices AD7606 Simultaneous Sampling ADC |
| @@ -8,7 +8,6 @@ title: Analog Devices AD9467 and similar High-Speed ADCs · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | maintainers: | 9 | maintainers: |
| 10 | - Michael Hennerich <michael.hennerich@analog.com> | 10 | - Michael Hennerich <michael.hennerich@analog.com> |
| 11 | - Alexandru Ardelean <alexandru.ardelean@analog.com> | ||
| 12 | 11 | ||
| 13 | description: | | 12 | description: | |
| 14 | The AD9467 and the parts similar with it, are high-speed analog-to-digital | 13 | The AD9467 and the parts similar with it, are high-speed analog-to-digital |
| @@ -8,7 +8,6 @@ title: Analog Devices AXI ADC IP core · 7 unmodified lines | |||
| 8 | 8 | ||
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File renamed without changes.
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This diff is larger than a page shows: the files after these aren’t listed. Clone the repository to see all of it.