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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | +/* |
| 3 | + * Copyright (c) 2025 AIROHA Inc |
| 4 | + * Author: Lorenzo Bianconi <lorenzo@kernel.org> |
| 5 | + */ |
| 6 | +#ifndef AIROHA_OFFLOAD_H |
| 7 | +#define AIROHA_OFFLOAD_H |
| 8 | + |
| 9 | +#include <linux/spinlock.h> |
| 10 | +#include <linux/workqueue.h> |
| 11 | + |
| 12 | +#define NPU_NUM_CORES 8 |
| 13 | +#define NPU_NUM_IRQ 6 |
| 14 | +#define NPU_RX0_DESC_NUM 512 |
| 15 | +#define NPU_RX1_DESC_NUM 512 |
| 16 | + |
| 17 | +/* CTRL */ |
| 18 | +#define NPU_RX_DMA_DESC_LAST_MASK BIT(29) |
| 19 | +#define NPU_RX_DMA_DESC_LEN_MASK GENMASK(28, 15) |
| 20 | +#define NPU_RX_DMA_DESC_CUR_LEN_MASK GENMASK(14, 1) |
| 21 | +#define NPU_RX_DMA_DESC_DONE_MASK BIT(0) |
| 22 | +/* INFO */ |
| 23 | +#define NPU_RX_DMA_PKT_COUNT_MASK GENMASK(31, 28) |
| 24 | +#define NPU_RX_DMA_PKT_ID_MASK GENMASK(28, 26) |
| 25 | +#define NPU_RX_DMA_SRC_PORT_MASK GENMASK(25, 21) |
| 26 | +#define NPU_RX_DMA_CRSN_MASK GENMASK(20, 16) |
| 27 | +#define NPU_RX_DMA_FOE_ID_MASK GENMASK(15, 0) |
| 28 | +/* DATA */ |
| 29 | +#define NPU_RX_DMA_SID_MASK GENMASK(31, 16) |
| 30 | +#define NPU_RX_DMA_FRAG_TYPE_MASK GENMASK(15, 14) |
| 31 | +#define NPU_RX_DMA_PRIORITY_MASK GENMASK(13, 10) |
| 32 | +#define NPU_RX_DMA_RADIO_ID_MASK GENMASK(9, 6) |
| 33 | +#define NPU_RX_DMA_VAP_ID_MASK GENMASK(5, 2) |
| 34 | +#define NPU_RX_DMA_FRAME_TYPE_MASK GENMASK(1, 0) |
| 35 | + |
| 36 | +struct airoha_npu_rx_dma_desc { |
| 37 | + u32 ctrl; |
| 38 | + u32 info; |
| 39 | + u32 data; |
| 40 | + u32 addr; |
| 41 | + u64 rsv; |
| 42 | +} __packed; |
| 43 | + |
| 44 | +/* CTRL */ |
| 45 | +#define NPU_TX_DMA_DESC_SCHED_MASK BIT(31) |
| 46 | +#define NPU_TX_DMA_DESC_LEN_MASK GENMASK(30, 18) |
| 47 | +#define NPU_TX_DMA_DESC_VEND_LEN_MASK GENMASK(17, 1) |
| 48 | +#define NPU_TX_DMA_DESC_DONE_MASK BIT(0) |
| 49 | + |
| 50 | +#define NPU_TXWI_LEN 192 |
| 51 | + |
| 52 | +struct airoha_npu_tx_dma_desc { |
| 53 | + u32 ctrl; |
| 54 | + u32 addr; |
| 55 | + u64 rsv; |
| 56 | + u8 txwi[NPU_TXWI_LEN]; |
| 57 | +} __packed; |
| 58 | + |
| 59 | +enum airoha_npu_wlan_set_cmd { |
| 60 | + WLAN_FUNC_SET_WAIT_PCIE_ADDR, |
| 61 | + WLAN_FUNC_SET_WAIT_DESC, |
| 62 | + WLAN_FUNC_SET_WAIT_NPU_INIT_DONE, |
| 63 | + WLAN_FUNC_SET_WAIT_TRAN_TO_CPU, |
| 64 | + WLAN_FUNC_SET_WAIT_BA_WIN_SIZE, |
| 65 | + WLAN_FUNC_SET_WAIT_DRIVER_MODEL, |
| 66 | + WLAN_FUNC_SET_WAIT_DEL_STA, |
| 67 | + WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR, |
| 68 | + WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR, |
| 69 | + WLAN_FUNC_SET_WAIT_IS_TEST_NOBA, |
| 70 | + WLAN_FUNC_SET_WAIT_FLUSHONE_TIMEOUT, |
| 71 | + WLAN_FUNC_SET_WAIT_FLUSHALL_TIMEOUT, |
| 72 | + WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU, |
| 73 | + WLAN_FUNC_SET_WAIT_PCIE_STATE, |
| 74 | + WLAN_FUNC_SET_WAIT_PCIE_PORT_TYPE, |
| 75 | + WLAN_FUNC_SET_WAIT_ERROR_RETRY_TIMES, |
| 76 | + WLAN_FUNC_SET_WAIT_BAR_INFO, |
| 77 | + WLAN_FUNC_SET_WAIT_FAST_FLAG, |
| 78 | + WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU, |
| 79 | + WLAN_FUNC_SET_WAIT_TX_RING_PCIE_ADDR, |
| 80 | + WLAN_FUNC_SET_WAIT_TX_DESC_HW_BASE, |
| 81 | + WLAN_FUNC_SET_WAIT_TX_BUF_SPACE_HW_BASE, |
| 82 | + WLAN_FUNC_SET_WAIT_RX_RING_FOR_TXDONE_HW_BASE, |
| 83 | + WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR, |
| 84 | + WLAN_FUNC_SET_WAIT_INODE_TXRX_REG_ADDR, |
| 85 | + WLAN_FUNC_SET_WAIT_INODE_DEBUG_FLAG, |
| 86 | + WLAN_FUNC_SET_WAIT_INODE_HW_CFG_INFO, |
| 87 | + WLAN_FUNC_SET_WAIT_INODE_STOP_ACTION, |
| 88 | + WLAN_FUNC_SET_WAIT_INODE_PCIE_SWAP, |
| 89 | + WLAN_FUNC_SET_WAIT_RATELIMIT_CTRL, |
| 90 | + WLAN_FUNC_SET_WAIT_HWNAT_INIT, |
| 91 | + WLAN_FUNC_SET_WAIT_ARHT_CHIP_INFO, |
| 92 | + WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR, |
| 93 | + WLAN_FUNC_SET_WAIT_TOKEN_ID_SIZE, |
| 94 | +}; |
| 95 | + |
| 96 | +enum airoha_npu_wlan_get_cmd { |
| 97 | + WLAN_FUNC_GET_WAIT_NPU_INFO, |
| 98 | + WLAN_FUNC_GET_WAIT_LAST_RATE, |
| 99 | + WLAN_FUNC_GET_WAIT_COUNTER, |
| 100 | + WLAN_FUNC_GET_WAIT_DBG_COUNTER, |
| 101 | + WLAN_FUNC_GET_WAIT_RXDESC_BASE, |
| 102 | + WLAN_FUNC_GET_WAIT_WCID_DBG_COUNTER, |
| 103 | + WLAN_FUNC_GET_WAIT_DMA_ADDR, |
| 104 | + WLAN_FUNC_GET_WAIT_RING_SIZE, |
| 105 | + WLAN_FUNC_GET_WAIT_NPU_SUPPORT_MAP, |
| 106 | + WLAN_FUNC_GET_WAIT_MDC_LOCK_ADDRESS, |
| 107 | + WLAN_FUNC_GET_WAIT_NPU_VERSION, |
| 108 | +}; |
| 109 | + |
| 110 | +struct airoha_npu { |
| 111 | +#if (IS_BUILTIN(CONFIG_NET_AIROHA_NPU) || IS_MODULE(CONFIG_NET_AIROHA_NPU)) |
| 112 | + struct device *dev; |
| 113 | + struct regmap *regmap; |
| 114 | + |
| 115 | + struct airoha_npu_core { |
| 116 | + struct airoha_npu *npu; |
| 117 | + /* protect concurrent npu memory accesses */ |
| 118 | + spinlock_t lock; |
| 119 | + struct work_struct wdt_work; |
| 120 | + } cores[NPU_NUM_CORES]; |
| 121 | + |
| 122 | + int irqs[NPU_NUM_IRQ]; |
| 123 | + |
| 124 | + struct airoha_foe_stats __iomem *stats; |
| 125 | + |
| 126 | + struct { |
| 127 | + int (*ppe_init)(struct airoha_npu *npu); |
| 128 | + int (*ppe_deinit)(struct airoha_npu *npu); |
| 129 | + int (*ppe_flush_sram_entries)(struct airoha_npu *npu, |
| 130 | + dma_addr_t foe_addr, |
| 131 | + int sram_num_entries); |
| 132 | + int (*ppe_foe_commit_entry)(struct airoha_npu *npu, |
| 133 | + dma_addr_t foe_addr, |
| 134 | + u32 entry_size, u32 hash, |
| 135 | + bool ppe2); |
| 136 | + int (*wlan_init_reserved_memory)(struct airoha_npu *npu); |
| 137 | + int (*wlan_send_msg)(struct airoha_npu *npu, int ifindex, |
| 138 | + enum airoha_npu_wlan_set_cmd func_id, |
| 139 | + void *data, int data_len, gfp_t gfp); |
| 140 | + int (*wlan_get_msg)(struct airoha_npu *npu, int ifindex, |
| 141 | + enum airoha_npu_wlan_get_cmd func_id, |
| 142 | + void *data, int data_len, gfp_t gfp); |
| 143 | + u32 (*wlan_get_queue_addr)(struct airoha_npu *npu, int qid, |
| 144 | + bool xmit); |
| 145 | + void (*wlan_set_irq_status)(struct airoha_npu *npu, u32 val); |
| 146 | + u32 (*wlan_get_irq_status)(struct airoha_npu *npu, int q); |
| 147 | + void (*wlan_enable_irq)(struct airoha_npu *npu, int q); |
| 148 | + void (*wlan_disable_irq)(struct airoha_npu *npu, int q); |
| 149 | + } ops; |
| 150 | +#endif |
| 151 | +}; |
| 152 | + |
| 153 | +#if (IS_BUILTIN(CONFIG_NET_AIROHA_NPU) || IS_MODULE(CONFIG_NET_AIROHA_NPU)) |
| 154 | +struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr); |
| 155 | +void airoha_npu_put(struct airoha_npu *npu); |
| 156 | + |
| 157 | +static inline int airoha_npu_wlan_init_reserved_memory(struct airoha_npu *npu) |
| 158 | +{ |
| 159 | + return npu->ops.wlan_init_reserved_memory(npu); |
| 160 | +} |
| 161 | + |
| 162 | +static inline int airoha_npu_wlan_send_msg(struct airoha_npu *npu, |
| 163 | + int ifindex, |
| 164 | + enum airoha_npu_wlan_set_cmd cmd, |
| 165 | + void *data, int data_len, gfp_t gfp) |
| 166 | +{ |
| 167 | + return npu->ops.wlan_send_msg(npu, ifindex, cmd, data, data_len, gfp); |
| 168 | +} |
| 169 | + |
| 170 | +static inline int airoha_npu_wlan_get_msg(struct airoha_npu *npu, int ifindex, |
| 171 | + enum airoha_npu_wlan_get_cmd cmd, |
| 172 | + void *data, int data_len, gfp_t gfp) |
| 173 | +{ |
| 174 | + return npu->ops.wlan_get_msg(npu, ifindex, cmd, data, data_len, gfp); |
| 175 | +} |
| 176 | + |
| 177 | +static inline u32 airoha_npu_wlan_get_queue_addr(struct airoha_npu *npu, |
| 178 | + int qid, bool xmit) |
| 179 | +{ |
| 180 | + return npu->ops.wlan_get_queue_addr(npu, qid, xmit); |
| 181 | +} |
| 182 | + |
| 183 | +static inline void airoha_npu_wlan_set_irq_status(struct airoha_npu *npu, |
| 184 | + u32 val) |
| 185 | +{ |
| 186 | + npu->ops.wlan_set_irq_status(npu, val); |
| 187 | +} |
| 188 | + |
| 189 | +static inline u32 airoha_npu_wlan_get_irq_status(struct airoha_npu *npu, int q) |
| 190 | +{ |
| 191 | + return npu->ops.wlan_get_irq_status(npu, q); |
| 192 | +} |
| 193 | + |
| 194 | +static inline void airoha_npu_wlan_enable_irq(struct airoha_npu *npu, int q) |
| 195 | +{ |
| 196 | + npu->ops.wlan_enable_irq(npu, q); |
| 197 | +} |
| 198 | + |
| 199 | +static inline void airoha_npu_wlan_disable_irq(struct airoha_npu *npu, int q) |
| 200 | +{ |
| 201 | + npu->ops.wlan_disable_irq(npu, q); |
| 202 | +} |
| 203 | +#else |
| 204 | +static inline struct airoha_npu *airoha_npu_get(struct device *dev, |
| 205 | + dma_addr_t *foe_stats_addr) |
| 206 | +{ |
| 207 | + return NULL; |
| 208 | +} |
| 209 | + |
| 210 | +static inline void airoha_npu_put(struct airoha_npu *npu) |
| 211 | +{ |
| 212 | +} |
| 213 | + |
| 214 | +static inline int airoha_npu_wlan_init_reserved_memory(struct airoha_npu *npu) |
| 215 | +{ |
| 216 | + return -EOPNOTSUPP; |
| 217 | +} |
| 218 | + |
| 219 | +static inline int airoha_npu_wlan_send_msg(struct airoha_npu *npu, |
| 220 | + int ifindex, |
| 221 | + enum airoha_npu_wlan_set_cmd cmd, |
| 222 | + void *data, int data_len, gfp_t gfp) |
| 223 | +{ |
| 224 | + return -EOPNOTSUPP; |
| 225 | +} |
| 226 | + |
| 227 | +static inline int airoha_npu_wlan_get_msg(struct airoha_npu *npu, int ifindex, |
| 228 | + enum airoha_npu_wlan_get_cmd cmd, |
| 229 | + void *data, int data_len, gfp_t gfp) |
| 230 | +{ |
| 231 | + return -EOPNOTSUPP; |
| 232 | +} |
| 233 | + |
| 234 | +static inline u32 airoha_npu_wlan_get_queue_addr(struct airoha_npu *npu, |
| 235 | + int qid, bool xmit) |
| 236 | +{ |
| 237 | + return 0; |
| 238 | +} |
| 239 | + |
| 240 | +static inline void airoha_npu_wlan_set_irq_status(struct airoha_npu *npu, |
| 241 | + u32 val) |
| 242 | +{ |
| 243 | +} |
| 244 | + |
| 245 | +static inline u32 airoha_npu_wlan_get_irq_status(struct airoha_npu *npu, |
| 246 | + int q) |
| 247 | +{ |
| 248 | + return 0; |
| 249 | +} |
| 250 | + |
| 251 | +static inline void airoha_npu_wlan_enable_irq(struct airoha_npu *npu, int q) |
| 252 | +{ |
| 253 | +} |
| 254 | + |
| 255 | +static inline void airoha_npu_wlan_disable_irq(struct airoha_npu *npu, int q) |
| 256 | +{ |
| 257 | +} |
| 258 | +#endif |
| 259 | + |
| 260 | +#endif /* AIROHA_OFFLOAD_H */ |